PIC18CXX2
High Performance Microcontrollers with 10-bit A/D
Pin Diagrams
DIP, Windowed CERDIP
• C compiler optimized architecture/instruction set
- Source code compatible with the PIC16CXX
instruction set
• Linear program memory addressing to 2 Mbytes
• Linear data memory addressing to 4 Kbytes
On-Chip Program Memory
On-Chip
RAM
(bytes)
Device
EPROM
(bytes)
PIC18C242
16K
8192
512
PIC18C252
32K
16384
1536
PIC18C442
16K
8192
512
PIC18C452
32K
16384
1536
# Single Word
Instructions
• Up to 10 MIPs operation:
- DC - 40 MHz osc./clock input
- 4 MHz - 10 MHz osc./clock input with PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 8 x 8 Single Cycle Hardware Multiplier
Peripheral Features:
• High current sink/source 25 mA/25 mA
• Three external interrupt pins
• Timer0 module: 8-bit/16-bit timer/counter with
8-bit programmable prescaler
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter with 8-bit
period register (time-base for PWM)
• Timer3 module: 16-bit timer/counter
• Secondary oscillator clock option - Timer1/Timer3
• Two Capture/Compare/PWM (CCP) modules.
CCP pins that can be configured as:
- Capture input: capture is 16-bit,
max. resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution 100 ns (TCY)
- PWM output: PWM resolution is 1- to 10-bit.
Max. PWM freq. @: 8-bit resolution = 156 kHz
10-bit resolution = 39 kHz
• Master Synchronous Serial Port (MSSP) module.
Two modes of operation:
- 3-wire SPI (supports all 4 SPI modes)
- I2C™ master and slave mode
• Addressable USART module:
- Supports interrupt on Address bit
• Parallel Slave Port (PSP) module
1999-2013 Microchip Technology Inc.
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC18C4X2
High Performance RISC CPU:
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
* RB3 is the alternate pin for the CCP2 pin multiplexing.
Note: Pin compatible with 40-pin PIC16C7X devices.
Analog Features:
• Compatible 10-bit Analog-to-Digital Converter
module (A/D) with:
- Fast sampling rate
- Conversion available during SLEEP
- DNL = ±1 LSb, INL = ±1 LSb
• Programmable Low Voltage Detection (LVD)
module
- Supports interrupt-on-low voltage detection
• Programmable Brown-out Reset (BOR)
Special Microcontroller Features:
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
• In-Circuit Serial Programming (ICSP™) via two pins
CMOS Technology:
•
•
•
•
•
Low power, high speed EPROM technology
Fully static design
Wide operating voltage range (2.5V to 5.5V)
Industrial and Extended temperature ranges
Low power consumption
DS39026D-page 1
PIC18CXX2
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
Pin Diagrams
6
5
4
3
2
1
44
43
42
41
40
PLCC
7
8
9
10
11
12
13
14
15
16
171
PIC18C4X2
28
27
26
25
24
23
22
21
20
19
8
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
NC
39
38
37
36
35
34
33
32
31
30
29
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2*
NC
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2*
44
43
42
41
40
39
38
37
36
35
34
TQFP
1
2
3
4
5
6
7
8
9
10
11
NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN
RA4/T0CKI
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1
RA0/AN0
MCLR/VPP
RB7
RB6
RB5
RB4
NC
NC
* RB3 is the alternate pin for the CCP2 pin multiplexing.
PIC18C4X2
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2*
Note: Pin compatible with 44-pin PIC16C7X devices.
DS39026D-page 2
1999-2013 Microchip Technology Inc.
PIC18CXX2
Pin Diagrams (Cont.’d)
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC18C4X2
DIP, JW
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Note: Pin compatible with 40-pin PIC16C7X devices.
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC18C2X2
DIP, SOIC, JW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
* RB3 is the alternate pin for the CCP2 pin multiplexing.
Note: Pin compatible with 28-pin PIC16C7X devices.
1999-2013 Microchip Technology Inc.
DS39026D-page 3
PIC18CXX2
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 7
2.0 Oscillator Configurations........................................................................................................................................................... 17
3.0 Reset......................................................................................................................................................................................... 25
4.0 Memory Organization................................................................................................................................................................ 35
5.0 Table Reads/Table Writes ........................................................................................................................................................ 55
6.0 8 X 8 Hardware Multiplier.......................................................................................................................................................... 61
7.0 Interrupts................................................................................................................................................................................... 63
8.0 I/O Ports.................................................................................................................................................................................... 77
9.0 Timer0 Module .......................................................................................................................................................................... 93
10.0 Timer1 Module .......................................................................................................................................................................... 97
11.0 Timer2 Module ........................................................................................................................................................................ 101
12.0 Timer3 Module ........................................................................................................................................................................ 103
13.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................ 107
14.0 Master Synchronous Serial Port (MSSP) Module................................................................................................................... 115
15.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ............................................................ 149
16.0 Compatible 10-bit Analog-to-Digital Converter (A/D) Module ................................................................................................. 165
17.0 Low Voltage Detect................................................................................................................................................................. 173
18.0 Special Features of the CPU .................................................................................................................................................. 179
19.0 Instruction Set Summary......................................................................................................................................................... 187
20.0 Development Support ............................................................................................................................................................. 229
21.0 Electrical Characteristics......................................................................................................................................................... 235
22.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 263
23.0 Packaging Information ............................................................................................................................................................ 277
Appendix A: Revision History ......................................................................................................................................................... 287
Appendix B: Device Differences..................................................................................................................................................... 287
Appendix C: Conversion Considerations........................................................................................................................................ 288
Appendix D: Migration from Baseline to Enhanced Devices .......................................................................................................... 288
Appendix E: Migration from Mid-Range to Enhanced Devices ...................................................................................................... 289
Appendix F: Migration from High-End to Enhanced Devices ......................................................................................................... 289
Index ................................................................................................................................................................................................. 291
On-Line Support................................................................................................................................................................................ 299
Reader Response ............................................................................................................................................................................. 300
PIC18CXX2 Product Identification System ....................................................................................................................................... 301
DS39026D-page 4
1999-2013 Microchip Technology Inc.
PIC18CXX2
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Customer Notification System
Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
1999-2013 Microchip Technology Inc.
DS39026D-page 5
PIC18CXX2
NOTES:
DS39026D-page 6
1999-2013 Microchip Technology Inc.
PIC18CXX2
1.0
DEVICE OVERVIEW
This document contains device specific information for
the following four devices:
1.
2.
3.
4.
The following two figures are device block diagrams
sorted by pin count: 28-pin for Figure 1-1 and 40-pin for
Figure 1-2. The 28-pin and 40-pin pinouts are listed in
Table 1-2 and Table 1-3, respectively.
PIC18C242
PIC18C252
PIC18C442
PIC18C452
These devices come in 28-pin and 40-pin packages.
The 28-pin devices do not have a Parallel Slave Port
(PSP) implemented and the number of Analog-toDigital (A/D) converter input channels is reduced to 5.
An overview of features is shown in Table 1-1.
TABLE 1-1:
DEVICE FEATURES
Features
Operating Frequency
PIC18C242
PIC18C252
PIC18C442
PIC18C452
DC - 40 MHz
DC - 40 MHz
DC - 40 MHz
DC - 40 MHz
Program Memory (Bytes)
16K
32K
16K
32K
Program Memory (Instructions)
8192
16384
8192
16384
Data Memory (Bytes)
512
1536
512
1536
17
17
Interrupt Sources
16
16
Ports A, B, C
Ports A, B, C
Timers
4
4
4
4
Capture/Compare/PWM Modules
2
2
2
2
MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
I/O Ports
Serial Communications
Parallel Communications
10-bit Analog-to-Digital Module
RESETS (and Delays)
Ports A, B, C, D, E Ports A, B, C, D, E
—
—
PSP
PSP
5 input channels
5 input channels
8 input channels
8 input channels
POR, BOR,
POR, BOR,
RESET Instruction, RESET Instruction,
Stack Full,
Stack Full,
Stack Underflow
Stack Underflow
(PWRT, OST)
(PWRT, OST)
POR, BOR,
POR, BOR,
RESET Instruction, RESET Instruction,
Stack Full,
Stack Full,
Stack Underflow
Stack Underflow
(PWRT, OST)
(PWRT, OST)
Programmable Low Voltage
Detect
Yes
Yes
Yes
Yes
Programmable Brown-out Reset
Yes
Yes
Yes
Yes
75 Instructions
75 Instructions
75 Instructions
75 Instructions
28-pin DIP
28-pin SOIC
28-pin JW
28-pin DIP
28-pin SOIC
28-pin JW
40-pin DIP
44-pin PLCC
44-pin TQFP
40-pin JW
40-pin DIP
44-pin PLCC
44-pin TQFP
40-pin JW
Instruction Set
Packages
1999-2013 Microchip Technology Inc.
DS39026D-page 7
PIC18CXX2
FIGURE 1-1:
PIC18C2X2 BLOCK DIAGRAM
Data Bus
21
Table Pointer
8
21
PORTA
Data Latch
8
8
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RA6
Data RAM
inc/dec logic
21
Address Latch
20
Address Latch
Program Memory
(up to 2M Bytes)
PCLATU PCLATH
PCU PCH PCL
Program Counter
Data Latch
12
Address
12
4
BSR
31 Level Stack
16
(2)
Decode
Table Latch
4
Bank0, F
FSR0
FSR1
FSR2
12
inc/dec
logic
8
PORTB
ROM Latch
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2(1)
RB7:RB4
Instruction
Register
8
Instruction
Decode &
Control
OSC2/CLKO
OSC1/CLKI
PRODH PRODL
3
Timing
Generation
T1OSI
T1OSO
8
Oscillator
Start-up Timer
BIT OP
Precision
Voltage
Reference
Timer0
Timer1
CCP1
CCP2
8
8
8
Watchdog
Timer
ALU
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
Brown-out
Reset
MCLR
WREG
8
Power-on
Reset
4X PLL
Note
8 x 8 Multiply
Power-up
Timer
VDD, VSS
Timer2
Master
Synchronous
Serial Port
Timer3
A/D Converter
Addressable
USART
1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
DS39026D-page 8
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 1-2:
PIC18C4X2 BLOCK DIAGRAM
Data Bus
PORTA
21
8
21
Data RAM
(up to 4K
address reach)
8
8
inc/dec logic
21
Address Latch
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RA6
Data Latch
Table Pointer
Address Latch
20
Program Memory
(up to 2M Bytes)
(2)
PCLATU PCLATH
12
Address
PCU PCH PCL
Program Counter
Data Latch
12
4
BSR
FSR0
FSR1
FSR2
Bank0, F
31 Level Stack
16
PORTB
4
Decode
Table Latch
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2(1)
RB7:RB4
12
inc/dec
logic
8
PORTC
ROM Latch
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Instruction
Register
8
Instruction
Decode &
Control
OSC2/CLKO
OSC1/CLKI
PRODH PRODL
3
Timing
Generation
T1OSI
T1OSO
Power-up
Timer
Oscillator
Start-up Timer
8
BIT OP
8
Power-on
Reset
4X PLL
Watchdog
Timer
Precision
Voltage
Reference
Brown-out
Reset
8 x 8 Multiply
WREG
8
PORTD
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
8
8
ALU
8
PORTE
RE0/AN5/RD
MCLR
RE1/AN6/WR
VDD, VSS
RE2/AN7/CS
Note
Timer0
Timer1
Timer2
CCP1
CCP2
Master
Synchronous
Serial Port
Timer3
Addressable
USART
A/D Converter
Parallel Slave Port
1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
1999-2013 Microchip Technology Inc.
DS39026D-page 9
PIC18CXX2
TABLE 1-2:
PIC18C2X2 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
DIP
MCLR/VPP
MCLR
1
Pin
SOIC Type
Buffer
Type
1
I
ST
P
—
—
I
ST
I
CMOS
O
—
CLKO
O
—
RA6
I/O
TTL
VPP
NC
OSC1/CLKI
OSC1
—
9
—
9
CLKI
OSC2/CLKO/RA6
OSC2
10
10
Description
Master clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active low
RESET to the device.
Programming voltage input.
These pins should be left unconnected.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode. CMOS otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKIN,
OSC2/CLKOUT pins.)
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKOUT which has 1/4
the frequency of OSC1, and denotes the instruction
cycle rate.
General Purpose I/O pin.
PORTA is a bi-directional I/O port.
RA0/AN0
2
2
RA0
I/O
TTL
Digital I/O.
AN0
I
Analog
Analog input 0.
RA1/AN1
3
3
RA1
I/O
TTL
Digital I/O.
AN1
I
Analog
Analog input 1.
4
4
RA2/AN2/VREFI/O
TTL
Digital I/O.
RA2
I
Analog
Analog input 2.
AN2
I
Analog
A/D Reference Voltage (Low) input.
VREF5
5
RA3/AN3/VREF+
I/O
TTL
Digital I/O.
RA3
I
Analog
Analog input 3.
AN3
I
Analog
A/D Reference Voltage (High) input.
VREF+
RA4/T0CKI
6
6
RA4
I/O
ST/OD
Digital I/O. Open drain when configured as output.
T0CKI
I
ST
Timer0 external clock input.
RA5/AN4/SS/LVDIN
7
7
RA5
I/O
TTL
Digital I/O.
AN4
I
Analog
Analog input 4.
SS
I
ST
SPI Slave Select input.
LVDIN
I
Analog
Low Voltage Detect Input.
RA6
See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output
P = Power
OD = Open Drain (no P diode to VDD)
DS39026D-page 10
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 1-2:
PIC18C2X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
DIP
Pin
Type
SOIC
Buffer
Type
Description
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0
RB0
INT0
RB1/INT1
RB1
INT1
RB2/INT2
RB2
INT2
RB3/CCP2
RB3
CCP2
RB4
21
22
23
24
21
I/O
I
TTL
ST
Digital I/O.
External Interrupt 0.
I/O
I
TTL
ST
External Interrupt 1.
I/O
I
TTL
ST
Digital I/O.
External Interrupt 2.
I/O
I/O
I/O
TTL
ST
TTL
22
23
24
Digital I/O.
Capture2 input, Compare2 output, PWM2 output.
25
25
Digital I/O.
Interrupt-on-change pin.
RB5
26
26
I/O
TTL
Digital I/O.
Interrupt-on-change pin.
RB6
27
27
I/O
TTL
Digital I/O.
Interrupt-on-change pin.
I
ST
ICSP programming clock.
RB7
28
28
I/O
TTL
Digital I/O.
Interrupt-on-change pin.
I/O
ST
ICSP programming data.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output
P = Power
OD = Open Drain (no P diode to VDD)
1999-2013 Microchip Technology Inc.
DS39026D-page 11
PIC18CXX2
TABLE 1-2:
PIC18C2X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
DIP
Pin
Type
SOIC
Buffer
Type
Description
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
11
11
RC0
I/O
ST
Digital I/O.
T1OSO
O
—
Timer1 oscillator output.
T1CKI
I
ST
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2
12
12
RC1
I/O
ST
Digital I/O.
T1OSI
I
CMOS
Timer1 oscillator input.
CCP2
I/O
ST
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
13
13
RC2
I/O
ST
Digital I/O.
CCP1
I/O
ST
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
14
14
RC3
I/O
ST
Digital I/O.
SCK
I/O
ST
Synchronous serial clock input/output for SPI mode.
SCL
I/O
ST
Synchronous serial clock input/output for I2C mode.
RC4/SDI/SDA
15
15
RC4
I/O
ST
Digital I/O.
ST
SPI Data In.
SDI
I
I/O
ST
I2C Data I/O.
SDA
RC5/SDO
16
16
RC5
I/O
ST
Digital I/O.
SDO
O
—
SPI Data Out.
RC6/TX/CK
17
17
RC6
I/O
ST
Digital I/O.
TX
O
—
USART Asynchronous Transmit.
I/O
ST
USART Synchronous Clock (see related RX/DT).
CK
RC7/RX/DT
18
18
RC7
I/O
ST
Digital I/O.
RX
I
ST
USART Asynchronous Receive.
DT
I/O
ST
USART Synchronous Data (see related TX/CK).
8, 19 8, 19
P
—
Ground reference for logic and I/O pins.
VSS
VDD
20
20
P
—
Positive supply for logic and I/O pins.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output
P = Power
OD = Open Drain (no P diode to VDD)
DS39026D-page 12
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 1-3:
PIC18C4X2 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
DIP
MCLR/VPP
MCLR
VPP
NC
OSC1/CLKI
OSC1
1
Pin
PLCC TQFP Type
2
18
I
—
13
P
—
14
30
I
CLKI
OSC2/CLKO/RA6
OSC2
I
14
15
31
O
CLKO
O
RA6
I/O
Buffer
Type
Description
Master clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active
low RESET to the device.
Programming voltage input.
—
These pins should be left unconnected.
Oscillator crystal or external clock input.
ST
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
CMOS
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKIN,
OSC2/CLKOUT pins.)
Oscillator crystal output.
—
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
—
In RC mode, OSC2 pin outputs CLKOUT, which has
1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
TTL
General Purpose I/O pin.
PORTA is a bi-directional I/O port.
ST
RA0/AN0
2
3
19
RA0
I/O
TTL
Digital I/O.
AN0
I
Analog
Analog input 0.
RA1/AN1
3
4
20
RA1
I/O
TTL
Digital I/O.
AN1
I
Analog
Analog input 1.
4
5
21
RA2/AN2/VREFI/O
TTL
Digital I/O.
RA2
I
Analog
Analog input 2.
AN2
I
Analog
A/D Reference Voltage (Low) input.
VREF5
6
22
RA3/AN3/VREF+
I/O
TTL
Digital I/O.
RA3
I
Analog
Analog input 3.
AN3
I
Analog
A/D Reference Voltage (High) input.
VREF+
RA4/T0CKI
6
7
23
RA4
I/O
ST/OD
Digital I/O. Open drain when configured as output.
T0CKI
I
ST
Timer0 external clock input.
RA5/AN4/SS/LVDIN
7
8
24
RA5
I/O
TTL
Digital I/O.
AN4
I
Analog
Analog input 4.
SS
I
ST
SPI Slave Select input.
LVDIN
I
Analog
Low Voltage Detect Input.
RA6
See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output
P = Power
OD = Open Drain (no P diode to VDD)
1999-2013 Microchip Technology Inc.
DS39026D-page 13
PIC18CXX2
TABLE 1-3:
PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
DIP
Pin
Type
PLCC TQFP
Buffer
Type
Description
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
RB0/INT0
RB0
INT0
RB1/INT1
RB1
INT1
RB2/INT2
RB2
INT2
RB3/CCP2
RB3
CCP2
RB4
RB5
RB6
33
34
35
36
36
37
38
39
8
I/O
I
TTL
ST
Digital I/O.
External Interrupt 0.
I/O
I
TTL
ST
External Interrupt 1.
I/O
I
TTL
ST
Digital I/O.
External Interrupt 2.
9
10
11
TTL
Digital I/O.
ST
Capture2 input, Compare2 output, PWM2 output.
37
41
14
TTL
Digital I/O. Interrupt-on-change pin.
38
42
15
TTL
Digital I/O. Interrupt-on-change pin.
39
43
16
TTL
Digital I/O. Interrupt-on-change pin.
ST
ICSP programming clock.
RB7
40
44
17
TTL
Digital I/O. Interrupt-on-change pin.
ST
ICSP programming data.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output
P = Power
OD = Open Drain (no P diode to VDD)
DS39026D-page 14
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 1-3:
PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
DIP
Pin
Type
PLCC TQFP
Buffer
Type
Description
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
RC2/CCP1
RC2
CCP1
RC3/SCK/SCL
RC3
SCK
15
16
17
18
16
18
19
20
SCL
32
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
I/O
I/O
ST
ST
Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
I/O
I/O
ST
ST
I/O
ST
Digital I/O.
Synchronous serial clock input/output for
SPI mode.
Synchronous serial clock input/output for
I2C mode.
35
36
37
RC4/SDI/SDA
23
25
42
RC4
I/O
ST
Digital I/O.
SDI
I
ST
SPI Data In.
SDA
I/O
ST
I2C Data I/O.
RC5/SDO
24
26
43
RC5
I/O
ST
Digital I/O.
SDO
O
—
SPI Data Out.
RC6/TX/CK
25
27
44
RC6
I/O
ST
Digital I/O.
TX
O
—
USART Asynchronous Transmit.
CK
I/O
ST
USART Synchronous Clock (see related RX/DT).
RC7/RX/DT
26
29
1
RC7
I/O
ST
Digital I/O.
RX
I
ST
USART Asynchronous Receive.
DT
I/O
ST
USART Synchronous Data (see related TX/CK).
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output
P = Power
OD = Open Drain (no P diode to VDD)
1999-2013 Microchip Technology Inc.
DS39026D-page 15
PIC18CXX2
TABLE 1-3:
PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
DIP
Pin
Type
PLCC TQFP
RD0/PSP0
19
21
38
I/O
RD1/PSP1
20
22
39
I/O
RD2/PSP2
21
23
40
I/O
RD3/PSP3
22
24
41
I/O
RD4/PSP4
27
30
2
I/O
RD5/PSP5
28
31
3
I/O
RD6/PSP6
29
32
4
I/O
RD7/PSP7
30
33
5
I/O
RE0/RD/AN5
RE0
RD
8
9
25
I/O
Buffer
Type
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
ST
TTL
AN5
RE1/WR/AN6
RE1
WR
9
Analog
AN6
RE2/CS/AN7
RE2
CS
10
10
26
Analog
27
PORTD is a bi-directional I/O port, or a Parallel Slave Port
(PSP) for interfacing to a microprocessor port. These pins
have TTL input buffers when PSP module is enabled.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
PORTE is a bi-directional I/O port.
Digital I/O.
Read control for parallel slave port (see also WR
and CS pins).
Analog input 5.
I/O
ST
TTL
11
Description
Digital I/O.
Write control for parallel slave port (see CS
and RD pins).
Analog input 6.
I/O
Digital I/O.
Chip Select control for parallel slave port (see related
RD and WR).
AN7
Analog
Analog input 7.
12, 31 13, 34 6, 29
P
—
Ground reference for logic and I/O pins.
VSS
VDD
11, 32 12, 35 7, 28
P
—
Positive supply for logic and I/O pins.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output
P = Power
OD = Open Drain (no P diode to VDD)
DS39026D-page 16
ST
TTL
1999-2013 Microchip Technology Inc.
PIC18CXX2
2.0
OSCILLATOR
CONFIGURATIONS
2.1
Oscillator Types
TABLE 2-1:
Ranges Tested:
The PIC18CXX2 can be operated in eight different
oscillator modes. The user can program three configuration bits (FOSC2, FOSC1, and FOSC0) to select one
of these eight modes:
1.
2.
3.
4.
LP
XT
HS
HS + PLL
5.
6.
RC
RCIO
7.
8.
EC
ECIO
2.2
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
High Speed Crystal/Resonator
with x 4 PLL enabled
External Resistor/Capacitor
External Resistor/Capacitor with
RA6 I/O pin enabled
External Clock
External Clock with RA6 I/O pin
enabled
Crystal Oscillator/Ceramic
Resonators
In XT, LP, HS or HS-PLL oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
The PIC18CXX2 oscillator design requires the use of a
parallel cut crystal.
Note:
Use of a series cut crystal may give a frequency out of the crystal manufacturers
specifications.
FIGURE 2-1:
C1(1)
Mode
Freq
C1
C2
XT
455 kHz
68 - 100 pF 68 - 100 pF
2.0 MHz
15 - 68 pF
15 - 68 pF
4.0 MHz
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
10 - 68 pF
10 - 68 pF
16.0 MHz
10 - 22 pF
10 - 22 pF
These values are for design guidance only.
See notes following this table.
Resonators Used:
455 kHz Panasonic EFO-A455K04B
0.3%
2.0 MHz
Murata Erie CSA2.00MG
0.5%
4.0 MHz
Murata Erie CSA4.00MG
0.5%
8.0 MHz
Murata Erie CSA8.00MT
0.5%
16.0 MHz Murata Erie CSA16.00MX
0.5%
All resonators used did not have built-in capacitors.
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
2: When operating below 3V VDD, it may be
necessary to use high gain HS mode on
lower frequency ceramic resonators.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external components or verify oscillator performance.
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
OSC1
XTAL
RF(3)
RS(2)
C2(1)
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
OSC2
To
Internal
Logic
SLEEP
PIC18CXXX
Note 1: See Table 2-1 and Table 2-2 for recommended values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the osc mode chosen.
1999-2013 Microchip Technology Inc.
DS39026D-page 17
PIC18CXX2
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATORS
FIGURE 2-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP CONFIGURATION)
Ranges Tested:
Mode
Freq
C1
C2
LP
32.0 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
XT
HS
OSC1
Clock from
Ext. System
PIC18CXXX
OSC2
Open
200 kHz
47-68 pF
47-68 pF
1.0 MHz
15 pF
15 pF
4.0 MHz
15 pF
15 pF
2.3
4.0 MHz
15 pF
15 pF
8.0 MHz
15-33 pF
15-33 pF
20.0
MHz
15-33 pF
15-33 pF
25.0
MHz
15-33 pF
15-33 pF
For timing insensitive applications, the “RC” and
"RCIO" device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit due to
normal process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take
into account variation due to tolerance of external R
and C components used. Figure 2-3 shows how the
R/C combination is connected.
These values are for design guidance only.
See notes following this table.
Crystals Used
32.0 kHz
Epson C-001R32.768K-A
± 20 PPM
200 kHz
STD XTL 200.000kHz
± 20 PPM
1.0 MHz
ECS ECS-10-13-1
± 50 PPM
4.0 MHz
ECS ECS-40-20-1
± 50 PPM
8.0 MHz
Epson CA-301 8.000M-C
± 30 PPM
20.0 MHz
Epson CA-301 20.000M-C ± 30 PPM
RC Oscillator
In the RC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
FIGURE 2-3:
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
2: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external components or verify oscillator performance.
An external clock source may also be connected to the
OSC1 pin in these modes, as shown in Figure 2-2.
DS39026D-page 18
RC OSCILLATOR MODE
VDD
REXT
Internal
Clock
OSC1
CEXT
PIC18CXXX
VSS
FOSC/4
OSC2/CLKO
Recommended values:3 k REXT 100 k
CEXT > 20pF
The RCIO oscillator mode functions like the RC mode,
except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
1999-2013 Microchip Technology Inc.
PIC18CXX2
2.4
FIGURE 2-5:
External Clock Input
The EC and ECIO oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is no oscillator start-up time required after a Power-on Reset or
after a recovery from SLEEP mode.
2.5
HS/PLL
The PLL can only be enabled when the oscillator configuration bits are programmed for HS mode. If they are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
PIC18CXXX
OSC2
The ECIO oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO oscillator mode.
FIGURE 2-6:
I/O (OSC2)
A Phase Locked Loop circuit is provided as a programmable option for users that want to multiply the frequency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high frequency crystals.
OSC1
FOSC/4
PIC18CXXX
RA6
EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
Clock from
Ext. System
OSC1
Clock from
Ext. System
In the EC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
oscillator mode.
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
The PLL is one of the modes of the FOSC configuration bits. The oscillator mode is specified during
device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called TPLL.
PLL BLOCK DIAGRAM
(from Configuration
bit Register)
HS Osc
PLL Enable
Phase
Comparator
OSC2
FIN
Loop
Filter
Crystal
Osc
VCO
SYSCLK
OSC1
1999-2013 Microchip Technology Inc.
Divide by 4
MUX
FOUT
DS39026D-page 19
PIC18CXX2
2.6
Oscillator Switching Feature
The PIC18CXX2 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low frequency clock source.
For the PIC18CXX2 devices, this alternate clock
source is the Timer1 oscillator. If a low frequency crystal (32 kHz, for example) has been attached to the
Timer1 oscillator pins and the Timer1 oscillator has
FIGURE 2-7:
been enabled, the device can switch to a low power
execution mode. Figure 2-7 shows a block diagram of
the system clock sources. The clock switching feature
is enabled by programming the Oscillator Switching
Enable (OSCSEN) bit in Configuration Register1H to a
’0’. Clock switching is disabled in an erased device.
See Section 9.0 for further details of the Timer1 oscillator. See Section 18.0 for Configuration Register details.
DEVICE CLOCK SOURCES
PIC18CXXX
Main Oscillator
OSC2
SLEEP
4 x PLL
TOSC/4
Timer1 Oscillator
MUX
TOSC
OSC1
TT1P
T1OSO
T1OSCEN
Enable
Oscillator
T1OSI
TSCLK
Clock
Source
Clock Source option
for other modules
2.6.1
SYSTEM CLOCK SWITCH BIT
Note:
The system clock source switching is performed under
software control. The system clock switch bit, SCS
(OSCCON) controls the clock switching. When the
SCS bit is’0’, the system clock source comes from the
main oscillator that is selected by the FOSC configuration bits in Configuration Register1H. When the SCS bit
is set, the system clock source will come from the
Timer1 oscillator. The SCS bit is cleared on all forms of
RESET.
REGISTER 2-1:
The Timer1 oscillator must be enabled and
operating to switch the system clock
source. The Timer1 oscillator is enabled by
setting the T1OSCEN bit in the Timer1
control register (T1CON). If the Timer1
oscillator is not enabled, then any write to
the SCS bit will be ignored (SCS bit forced
cleared) and the main oscillator will continue to be the system clock source.
OSCCON REGISTER
U-0
—
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7-1
Unimplemented: Read as '0'
bit 0
SCS: System Clock Switch bit
When OSCSEN configuration bit = ’0’ and T1OSCEN bit is set:
1 = Switch to Timer1 oscillator/clock pin
0 = Use primary oscillator/clock input pin
When OSCSEN and T1OSCEN are in other states:
bit is forced clear
U-0
—
R/W-1
SCS
bit 0
Legend:
DS39026D-page 20
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
1999-2013 Microchip Technology Inc.
PIC18CXX2
2.6.2
OSCILLATOR TRANSITIONS
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in
Figure 2-8. The Timer1 oscillator is assumed to be running all the time. After the SCS bit is set, the processor
is frozen at the next occurring Q1 cycle. After eight synchronization cycles are counted from the Timer1 oscillator, operation resumes. No additional delays are
required after the synchronization cycles.
The PIC18CXX2 devices contain circuitry to prevent
"glitches" when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to. This
ensures that the new clock source is stable and that it’s
pulse width will not be less than the shortest pulse
width of the two clock sources.
FIGURE 2-8:
TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1 Q2
Q3 Q4
Q1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
TT1P
1
T1OSI
2
3
4
5
6
7
8
Tscs
OSC1
TOSC
Internal
System
Clock
SCS
(OSCCON)
Program
Counter
TDLY
PC
PC + 4
PC + 2
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
FIGURE 2-9:
If the main oscillator is configured for an external crystal (HS, XT, LP), then the transition will take place after
an oscillator start-up time (TOST) has occurred. A timing
diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS, XT and LP modes is
shown in Figure 2-9.
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q3
Q4
Q1
Q1
TT1P
Q2 Q3
Q4
Q1
Q2
Q3
T1OSI
1
OSC1
TOST
2
3
4
5
6
7
8
TSCS
OSC2
TOSC
Internal System
Clock
SCS
(OSCCON)
Program Counter
PC
PC + 2
PC + 6
Note 1: TOST = 1024TOSC (drawing not to scale).
1999-2013 Microchip Technology Inc.
DS39026D-page 21
PIC18CXX2
frequency. A timing diagram, indicating the transition
from the Timer1 oscillator to the main oscillator for
HS-PLL mode, is shown in Figure 2-10.
If the main oscillator is configured for HS-PLL mode, an
oscillator start-up time (TOST) plus an additional PLL
time-out (TPLL) will occur. The PLL time-out is typically
2 ms and allows the PLL to lock to the main oscillator
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
Q4
TT1P
Q1
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
T1OSI
OSC1
TOST
TPLL
OSC2
TSCS
TOSC
PLL Clock
Input
1
2
3
4
5
6
7
8
Internal System
Clock
SCS
(OSCCON)
Program Counter
PC
PC + 2
PC + 4
Note 1: TOST = 1024TOSC (drawing not to scale).
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram, indi-
FIGURE 2-11:
cating the transition from the Timer1 oscillator to the
main oscillator for RC, RCIO, EC and ECIO modes, is
shown in Figure 2-11.
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3
Q4
T1OSI
Q1
Q1 Q2 Q3
TT1P
Q4 Q1 Q2
Q3 Q4
TOSC
OSC1
1
2
3
4
5
6
7
8
OSC2
Internal System
Clock
SCS
(OSCCON)
TSCS
Program Counter
PC
PC + 2
PC + 4
Note 1: RC oscillator mode assumed.
DS39026D-page 22
1999-2013 Microchip Technology Inc.
PIC18CXX2
2.7
Effects of SLEEP Mode on the
On-chip Oscillator
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
TABLE 2-3:
switching currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during SLEEP will increase the current
consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset, or through an interrupt.
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode
OSC1 Pin
OSC2 Pin
RC
Note:
2.8
Floating, external resistor should
At logic low
pull high
RCIO
Floating, external resistor should
Configured as PORTA, bit 6
pull high
ECIO
Floating
Configured as PORTA, bit 6
EC
Floating
At logic low
LP, XT, and HS
Feedback inverter disabled, at
Feedback inverter disabled, at
quiescent voltage level
quiescent voltage level
See Table 3-1, in Section 3.0 RESET, for time-outs due to SLEEP and MCLR Reset.
Power-up Delays
Power up delays are controlled by two timers, so that
no external RESET circuitry is required for most applications. The delays ensure that the device is kept in
RESET until the device power supply and clock are stable. For additional information on RESET operation,
see the “RESET” section.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer, OST, intended to keep the
chip in RESET until the crystal oscillator is stable.
1999-2013 Microchip Technology Inc.
With the PLL enabled (HS/PLL oscillator mode), the
time-out sequence following a Power-on Reset is different from other oscillator modes. The time-out sequence
is as follows: First, the PWRT time-out is invoked after
a POR time delay has expired. Then, the Oscillator
Start-up Timer (OST) is invoked. However, this is still
not a sufficient amount of time to allow the PLL to lock
at high frequencies. The PWRT timer is used to provide
an additional fixed 2ms (nominal) time-out to allow the
PLL ample time to lock to the incoming clock frequency.
DS39026D-page 23
PIC18CXX2
NOTES:
DS39026D-page 24
1999-2013 Microchip Technology Inc.
PIC18CXX2
3.0
RESET
The PIC18CXX2 differentiates between various kinds
of RESET:
a)
b)
c)
d)
e)
f)
g)
h)
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during SLEEP
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
Most registers are unaffected by a RESET. Their status
is unknown on POR and unchanged by all other
RESETS. The other registers are forced to a “RESET
state” on Power-on Reset, MCLR, WDT Reset, Brownout Reset, MCLR Reset during SLEEP, and by the
RESET instruction.
FIGURE 3-1:
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
RESET situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
RESET. See Table 3-3 for a full description of the
RESET states of all registers.
MCLR pin is not driven low by any internal RESETS,
including WDT.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
External Reset
MCLR
SLEEP
WDT
Time-out
Reset
WDT
Module
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
S
BOREN
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
R
Q
OSC1
PWRT
On-chip
RC OSC(1)
10-bit Ripple Counter
Enable PWRT
Enable OST(2)
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: See Table 3-1 for time-out situations.
1999-2013 Microchip Technology Inc.
DS39026D-page 25
PIC18CXX2
3.1
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR circuitry, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components
usually needed to create a Power-on Reset delay. A
minimum rise rate for VDD is specified (parameter
D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (i.e., exits the
RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in reset until the operating conditions are met.
FIGURE 3-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
R
R1
MCLR
C
PIC18CXXX
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in
the event of MCLR/VPP pin breakdown, due
to Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
3.2
Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/
disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC
parameter #33 for details.
DS39026D-page 26
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
3.4
PLL Lock Time-out
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to provide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(TPLL) is typically 2 ms and follows the oscillator startup time-out (OST).
3.5
VDD
D
3.3
Brown-out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A RESET may not occur if VDD falls below
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. The Power-up Timer will then be invoked and
will keep the chip in RESET an additional time delay
(parameter #33). If VDD drops below BVDD while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above BVDD, the Power-up Timer
will execute the additional time delay.
3.6
Time-out Sequence
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18CXXX device operating in parallel.
Table 3-2 shows the RESET conditions for some
Special Function Registers, while Table 3-3 shows the
RESET conditions for all the registers.
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 3-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2)
Oscillator
Configuration
PWRTE = 0
PWRTE = 1
72 ms + 1024TOSC
1024TOSC
+ 2ms
+ 2 ms
HS, XT, LP
72 ms + 1024TOSC
1024TOSC
EC
72 ms
—
External RC
72 ms
—
Note 1: 2 ms is the nominal time required for the 4x PLL to lock.
2: 72 ms is the nominal Power-up Timer delay.
72 ms + 1024TOSC
+ 2ms
72 ms + 1024TOSC
72 ms
72 ms
HS with PLL enabled(1)
REGISTER 3-1:
Wake-up from
SLEEP or
Oscillator Switch
Brown-out(2)
1024TOSC + 2 ms
1024TOSC
—
—
RCON REGISTER BITS AND POSITIONS
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
IPEN
LWRT
—
RI
TO
PD
POR
BOR
bit 7
Note:
TABLE 3-2:
bit 0
See Register 4-3 on page 53 for bit definitions.
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program
Counter
RCON
Register
RI
TO
PD
POR
BOR
STKFUL
STKUNF
Power-on Reset
0000h
00-1 1100
1
1
1
0
0
u
u
MCLR Reset during normal
operation
0000h
00-u uuuu
u
u
u
u
u
u
u
Software Reset during normal
operation
0000h
0u-0 uuuu
0
u
u
u
u
u
u
Stack Full Reset during normal
operation
0000h
0u-u uu11
u
u
u
u
u
u
1
Stack Underflow Reset during
normal operation
0000h
0u-u uu11
u
u
u
u
u
1
u
MCLR Reset during SLEEP
0000h
00-u 10uu
u
1
0
u
u
u
u
WDT Reset
0000h
0u-u 01uu
1
0
1
u
u
u
u
WDT Wake-up
PC + 2
uu-u 00uu
u
0
0
u
u
u
u
Brown-out Reset
Interrupt wake-up from SLEEP
0000h
0u-1 11u0
1
1
1
1
0
u
u
PC + 2(1)
uu-u 00uu
u
1
0
u
u
u
u
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
1999-2013 Microchip Technology Inc.
DS39026D-page 27
PIC18CXX2
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU
242 442 252 452
---0 0000
---0 0000
---0 uuuu(3)
TOSH
242 442 252 452
0000 0000
0000 0000
uuuu uuuu(3)
TOSL
242 442 252 452
0000 0000
0000 0000
uuuu uuuu(3)
STKPTR
242 442 252 452
00-0 0000
00-0 0000
uu-u uuuu(3)
PCLATU
242 442 252 452
---0 0000
---0 0000
---u uuuu
PCLATH
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
PCL
242 442 252 452
0000 0000
0000 0000
PC + 2(2)
TBLPTRU 242 442 252 452
--00 0000
--00 0000
--uu uuuu
TBLPTRH 242 442 252 452
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
TABLAT
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
PRODH
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
242 442 252 452
0000 000x
0000 000u
uuuu uuuu(1)
INTCON2
242 442 252 452
1111 -1-1
1111 -1-1
uuuu -u-u(1)
INTCON3
242 442 252 452
11-0 0-00
11-0 0-00
uu-u u-uu(1)
INDF0
242 442 252 452
N/A
N/A
N/A
POSTINC0 242 442 252 452
N/A
N/A
N/A
POSTDEC0 242 442 252 452
N/A
N/A
N/A
PREINC0
242 442 252 452
N/A
N/A
N/A
PLUSW0
242 442 252 452
N/A
N/A
N/A
FSR0H
242 442 252 452
---- 0000
---- 0000
---- uuuu
FSR0L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
242 442 252 452
N/A
N/A
N/A
POSTINC1 242 442 252 452
N/A
N/A
N/A
POSTDEC1 242 442 252 452
N/A
N/A
N/A
PREINC1
242 442 252 452
N/A
N/A
N/A
PLUSW1
242 442 252 452
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.
DS39026D-page 28
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
FSR1H
242 442 252 452
---- 0000
---- 0000
---- uuuu
FSR1L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
242 442 252 452
---- 0000
---- 0000
---- uuuu
INDF2
242 442 252 452
N/A
N/A
N/A
POSTINC2 242 442 252 452
N/A
N/A
N/A
POSTDEC2 242 442 252 452
N/A
N/A
N/A
PREINC2
242 442 252 452
N/A
N/A
N/A
PLUSW2
242 442 252 452
N/A
N/A
N/A
FSR2H
242 442 252 452
---- 0000
---- 0000
---- uuuu
FSR2L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
242 442 252 452
---x xxxx
---u uuuu
---u uuuu
TMR0H
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR0L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
242 442 252 452
1111 1111
1111 1111
uuuu uuuu
OSCCON
242 442 252 452
---- ---0
---- ---0
---- ---u
LVDCON
242 442 252 452
--00 0101
--00 0101
--uu uuuu
WDTCON
242 442 252 452
---- ---0
---- ---0
---- ---u
(4,
6)
RCON
242 442 252 452
00-1 11q0
00-1 qquu
uu-u qquu
TMR1H
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
242 442 252 452
0-00 0000
u-uu uuuu
u-uu uuuu
TMR2
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
PR2
242 442 252 452
1111 1111
1111 1111
1111 1111
T2CON
242 442 252 452
-000 0000
-000 0000
-uuu uuuu
SSPBUF
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
SSPCON1 242 442 252 452
0000 0000
0000 0000
uuuu uuuu
SSPCON2 242 442 252 452
0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.
1999-2013 Microchip Technology Inc.
DS39026D-page 29
PIC18CXX2
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
ADRESH
ADRESL
ADCON0
ADCON1
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
TMR3H
TMR3L
T3CON
SPBRG
RCREG
TXREG
TXSTA
RCSTA
IPR2
PIR2
PIE2
IPR1
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
242 442 252 452
--0- 0000
--0- 0000
--u- uuuu
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
242 442 252 452
--00 0000
--00 0000
--uu uuuu
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
242 442 252 452
--00 0000
--00 0000
--uu uuuu
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
242 442 252 452
0000 0000
uuuu uuuu
uuuu uuuu
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
242 442 252 452
0000 -01x
0000 -01u
uuuu -uuu
242 442 252 452
0000 000x
0000 000u
uuuu uuuu
242 442 252 452
---- 1111
---- 1111
---- uuuu
242 442 252 452
---- 0000
---- 0000
---- uuuu(1)
242 442 252 452
---- 0000
---- 0000
---- uuuu
242 442 252 452
1111 1111
1111 1111
uuuu uuuu
242 442 252 452
-111 1111
-111 1111
-uuu uuuu
PIR1
242 442 252 452
0000 0000
0000 0000
uuuu uuuu(1)
242 442 252 452
-000 0000
-000 0000
-uuu uuuu(1)
PIE1
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
242 442 252 452
-000 0000
-000 0000
-uuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.
DS39026D-page 30
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TRISE
242 442 252 452
0000 -111
0000 -111
uuuu -uuu
242 442 252 452
1111 1111
1111 1111
uuuu uuuu
TRISD
TRISC
242 442 252 452
1111 1111
1111 1111
uuuu uuuu
TRISB
242 442 252 452
1111 1111
1111 1111
uuuu uuuu
TRISA(5, 7) 242 442 252 452
-111 1111(5)
-111 1111(5)
-uuu uuuu(5)
LATE
242 442 252 452
---- -xxx
---- -uuu
---- -uuu
LATD
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATA(5, 7)
242 442 252 452
-xxx xxxx(5)
-uuu uuuu(5)
-uuu uuuu(5)
PORTE
242 442 252 452
---- -000
---- -000
---- -uuu
PORTD
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA(5, 7) 242 442 252 452
-x0x 0000(5)
-u0u 0000(5)
-uuu uuuu(5)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.
1999-2013 Microchip Technology Inc.
DS39026D-page 31
PIC18CXX2
FIGURE 3-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 3-4:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 3-5:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS39026D-page 32
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 3-6:
SLOW RISE TIME (MCLR TIED TO VDD)
5V
VDD
1V
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-7:
TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
IINTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
TPLL
OST TIME-OUT
PLL TIME-OUT
INTERNAL RESET
Note:
TOST = 1024 clock cycles.
TPLL 2 ms max. First three stages of the PWRT timer.
1999-2013 Microchip Technology Inc.
DS39026D-page 33
PIC18CXX2
NOTES:
DS39026D-page 34
1999-2013 Microchip Technology Inc.
PIC18CXX2
4.0
MEMORY ORGANIZATION
There are two memory blocks in Enhanced MCU
devices. These memory blocks are:
• Program Memory
• Data Memory
Program and data memory use separate buses so that
concurrent access can occur.
4.1
Program Memory Organization
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all ’0’s (a NOP
instruction).
PIC18C252 and PIC18C452 have 32 Kbytes of
EPROM, while PIC18C242 and PIC18C442 have
16 Kbytes of EPROM. This means that PIC18CX52
devices can store up to 16K of single word instructions,
and PIC18CX42 devices can store up to 8K of single
word instructions.
The RESET vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h.
Figure 4-1 shows the Program Memory Map for
PIC18C242/442 devices and Figure 4-2 shows the
Program Memory Map for PIC18C252/452 devices.
1999-2013 Microchip Technology Inc.
DS39026D-page 35
PIC18CXX2
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC18C442/242
PC
21
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
FIGURE 4-2:
PROGRAM MEMORY MAP
AND STACK FOR
PIC18C452/252
PC
21
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
Stack Level 31
Stack Level 31
RESET Vector
RESET Vector
0000h
0000h
High Priority Interrupt Vector 0008h
High Priority Interrupt Vector 0008h
Low Priority Interrupt Vector 0018h
Low Priority Interrupt Vector 0018h
On-chip
Program Memory
On-chip
Program Memory
7FFFh
8000h
User Memory Space
Read '0'
User Memory Space
3FFFh
4000h
Read '0'
1FFFFFh
200000h
DS39026D-page 36
1FFFFFh
200000h
1999-2013 Microchip Technology Inc.
PIC18CXX2
4.2
Return Address Stack
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALL or RCALL instruction is executed, or an interrupt
is acknowledged. The PC value is pulled off the stack
on a RETURN, RETLW or a RETFIE instruction.
PCLATU and PCLATH are not affected by any of the call
or return instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the stack pointer initialized to
00000b after all RESETS. There is no RAM associated
with stack pointer 00000b. This is only a RESET value.
During a CALL type instruction causing a push onto the
stack, the stack pointer is first incremented and the
RAM location pointed to by the stack pointer is written
with the contents of the PC. During a RETURN type
instruction causing a pop from the stack, the contents
of the RAM location pointed to by the STKPTR is transferred to the PC and then the stack pointer is
decremented.
The stack space is not part of either program or data
space. The stack pointer is readable and writable, and
the address on the top of the stack is readable and writable through SFR registers. Data can also be pushed
to, or popped from, the stack, using the top-of-stack
SFRs. Status bits indicate if the stack pointer is at, or
beyond the 31 levels provided.
4.2.1
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL hold the
contents of the stack location pointed to by the
STKPTR register. This allows users to implement a
software stack, if necessary. After a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
4.2.2
RETURN STACK POINTER
(STKPTR)
The STKPTR register contains the stack pointer value,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-1 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when values are pushed onto the stack and decrements when
values are popped off the stack. At RESET, the stack
pointer value will be 0. The user may read and write the
stack pointer value. This feature can be used by a Real
Time Operating System for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR.
The action that takes place when the stack becomes
full, depends on the state of the STVREN (Stack Overflow Reset Enable) configuration bit. Refer to
Section 18.0 for a description of the device configuration bits. If STVREN is set (default), the 31st push will
push the (PC + 2) value onto the stack, set the STKFUL
bit, and reset the device. The STKFUL bit will remain
set and the stack pointer will be set to 0.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at 0. The STKUNF bit will remain set
until cleared in software or a POR occurs.
Note:
Returning a value of zero to the PC on an
underflow, has the effect of vectoring the
program to the RESET vector, where the
stack conditions can be verified and appropriate actions can be taken.
The user must disable the global interrupt enable bits
during this time to prevent inadvertent stack operations..
1999-2013 Microchip Technology Inc.
DS39026D-page 37
PIC18CXX2
REGISTER 4-1:
STKPTR REGISTER
R/C-0
STKFUL
R/C-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STKUNF
—
SP4
SP3
SP2
SP1
SP0
bit 7
bit 0
bit 7(1)
STKFUL: Stack Full Flag bit
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6(1)
STKUNF: Stack Underflow Flag bit
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5
Unimplemented: Read as '0'
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.
Legend:
FIGURE 4-3:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
11111
11110
11101
TOSU
0x00
TOSH
0x1A
STKPTR
00010
TOSL
0x34
00011
Top-of-Stack 0x001A34 00010
0x000D58 00001
00000
4.2.3
PUSH AND POP INSTRUCTIONS
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program execution, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the stack pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place a return address on the
stack.
4.2.4
STACK FULL/UNDERFLOW RESETS
These resets are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disabled, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device
RESET. When the STVREN bit is enabled, a full or
underflow will set the appropriate STKFUL or STKUNF
bit and then cause a device RESET. The STKFUL or
STKUNF bits are only cleared by the user software or
a POR Reset.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP instruction. The POP instruction discards the current TOS by decrementing the
stack pointer. The previous value pushed onto the
stack then becomes the TOS value.
DS39026D-page 38
1999-2013 Microchip Technology Inc.
PIC18CXX2
4.3
Fast Register Stack
4.4
A "fast interrupt return" option is available for interrupts.
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers and are only one in depth.
The stack is not readable or writable and is loaded with
the current value of the corresponding register when
the processor vectors for an interrupt. The values in the
registers are then loaded back into the working registers, if the FAST RETURN instruction is used to return
from the interrupt.
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called
the PCH register. This register contains the PC
bits and is not directly readable or writable. Updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC bits and is not directly
readable or writable. Updates to the PCU register may
be performed through the PCLATU register.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority interrupt will be overwritten.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of PCL is fixed to a value of ’0’.
The PC increments by 2 to address sequential instructions in the program memory.
If high priority interrupts are not disabled during low priority interrupts, users must save the key registers in
software during a low priority interrupt.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
If no interrupts are used, the fast register stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the fast register
stack for a subroutine call, a FAST CALL instruction
must be executed.
The contents of PCLATH and PCLATU will be transferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1).
Example 4-1 shows a source code example that uses
the fast register stack.
EXAMPLE 4-1:
CALL SUB1, FAST
4.5
FAST REGISTER STACK
CODE EXAMPLE
SUB1
FIGURE 4-4:
Clocking Scheme/Instruction
Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 4-4.
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
RETURN FAST
PCL, PCLATH and PCLATU
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC
Execute INST (PC-2)
Fetch INST (PC)
1999-2013 Microchip Technology Inc.
PC+2
Execute INST (PC)
Fetch INST (PC+2)
PC+4
Execute INST (PC+2)
Fetch INST (PC+4)
DS39026D-page 39
PIC18CXX2
4.6
Instruction Flow/Pipelining
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO),
then two cycles are required to complete the instruction
(Example 4-2).
EXAMPLE 4-2:
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
TCY0
TCY1
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. BRA
4. BSF
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
TCY2
TCY4
TCY5
Execute 2
Fetch 3
SUB_1
TCY3
Execute 3
Fetch 4
PORTA, BIT3 (Forced NOP)
Flush (NOP)
Fetch SUB_1 Execute SUB_1
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
4.7
Instructions in Program Memory
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB =’0’). Figure 4-5 shows an
example of how instruction words are stored in the program memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ’0’ (see Section 4.4).
FIGURE 4-5:
The CALL and GOTO instructions have an absolute program memory address embedded into the instruction.
Since instructions are always stored on word boundaries, the data contained in the instruction is a word
address. The word address is written to PC,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 4-5 shows how the
instruction “GOTO 000006h” is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner.
The offset value stored in a branch instruction represents the number of single word instructions that the
PC will be offset by. Section 19.0 provides further
details of the instruction set.
INSTRUCTIONS IN PROGRAM MEMORY
LSB = 1
LSB = 0
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Program Memory
Byte Locations
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
000006h
Instruction 3:
MOVFF
123h, 456h
DS39026D-page 40
Word Address
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
1999-2013 Microchip Technology Inc.
PIC18CXX2
4.7.1
TWO-WORD INSTRUCTIONS
The PIC18CXX2 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second
word of these instructions has the 4 MSBs set to 1’s
and is a special kind of NOP instruction. The lower 12bits of the second word contain data to be used by the
instruction. If the first word of the instruction is executed, the data in the second word is accessed. If the
EXAMPLE 4-3:
second word of the instruction is executed by itself (first
word was skipped), it will execute as a NOP. This action
is necessary when the two-word instruction is preceded
by a conditional instruction that changes the PC. A program example that demonstrates this concept is shown
in Example 4-3. Refer to Section 19.0 for further details
of the instruction set.
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
1100 0001 0010 0011
MOVFF
REG1, REG2 ; No, execute 2-word instruction
; 2nd operand holds address of REG2
1111 0100 0101 0110
0010 0100 0000 0000
; is RAM location 0?
ADDWF
REG3
; continue code
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
1100 0001 0010 0011
MOVFF
REG1, REG2 ; Yes
; 2nd operand becomes NOP
1111 0100 0101 0110
0010 0100 0000 0000
4.8
ADDWF
REG3
Lookup Tables
Lookup tables are implemented two ways. These are:
• Computed GOTO
• Table Reads
4.8.1
; is RAM location 0?
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL).
A lookup table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table, before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions that returns the value 0xnn to the calling
function.
; continue code
4.8.2
TABLE READS/TABLE WRITES
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Lookup table data may be stored 2 bytes per program
word by using table reads and writes. The table pointer
(TBLPTR) specifies the byte address and the table
latch (TABLAT) contains the data that is read from, or
written to program memory. Data is transferred to/from
program memory one byte at a time.
A description of the Table Read/Table Write operation
is shown in Section 5.0.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
1999-2013 Microchip Technology Inc.
DS39026D-page 41
PIC18CXX2
4.9
Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 4-6
and Figure 4-7 show the data memory organization for
the PIC18CXX2 devices.
The data memory map is divided into as many as 16
banks that contain 256 bytes each. The lower 4 bits of
the Bank Select Register (BSR) select which
bank will be accessed. The upper 4 bits for the BSR are
not implemented.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratch pad operations in the user’s application. The SFRs start at the last location of Bank 15
(0xFFF) and extend downwards. Any remaining space
beyond the SFRs in the Bank may be implemented as
GPRs. GPRs start at the first location of Bank 0 and
grow upwards. Any read of an unimplemented location
will read as ’0’s.
The entire data memory may be accessed directly, or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and corresponding Indirect
File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the Data Memory map without banking.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing or by the use of the MOVFF instruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
4.9.1
GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly, or indirectly. Indirect addressing operates using the File
Select Registers (FSRn) and corresponding Indirect
File Operand (INDFn). The operation of indirect
addressing is shown in Section 4.12.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other RESETS.
Data RAM is available for use as GPR registers by all
instructions. The top half of bank 15 (0xF80 to 0xFFF)
contains SFRs. All other banks of data memory contain
GPR registers, starting with bank 0.
4.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these
registers is given in Table 4-1 and Table 4-2.
The SFRs can be classified into two sets; those associated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The SFRs are typically distributed among the peripherals whose functions they control.
The unused SFR locations will be unimplemented and
read as '0's. See Table 4-1 for addresses for the SFRs.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 4.10 provides a detailed description of the Access RAM.
DS39026D-page 42
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 4-6:
DATA MEMORY MAP FOR PIC18C242/442
BSR
= 0000b
= 0001b
Data Memory Map
00h
Access RAM
FFh
00h
GPR
Bank 0
000h
07Fh
080h
0FFh
100h
GPR
Bank 1
1FFh
FFh
200h
Access Bank
00h
7Fh
80h
Access RAM high FFh
(SFR’s)
Access RAM low
= 0010b
= 1110b
= 1111b
Bank 2
to
Bank 14
Unused
Read ’00h’
00h
Unused
FFh
SFR
Bank 15
EFFh
F00h
F7Fh
F80h
FFFh
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
the BSR is used to specify the
RAM location that the instruction uses.
1999-2013 Microchip Technology Inc.
DS39026D-page 43
PIC18CXX2
FIGURE 4-7:
DATA MEMORY MAP FOR PIC18C252/452
BSR
= 0000b
= 0001b
Data Memory Map
00h
Access RAM
FFh
00h
GPR
Bank 0
GPR
Bank 1
FFh
00h
= 0010b
Bank 2
= 0011b
1FFh
200h
GPR
2FFh
300h
FFh
00h
Bank 3
GPR
3FFh
400h
FFh
= 0100b
= 0101b
Bank 4
= 1110b
= 1111b
Access Bank
GPR
4FFh
500h
00h
GPR
Bank 5
FFh
= 0110b
000h
07Fh
080h
0FFh
100h
Bank 6
to
Bank 14
5FFh
600h
Unused
Read ’00h’
00h
Unused
FFh
SFR
Bank 15
EFFh
F00h
F7Fh
F80h
FFFh
00h
7Fh
80h
Access RAM high FFh
(SFR’s)
Access RAM low
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
the BSR is used to specify the
RAM location that the instruction uses.
DS39026D-page 44
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 4-1:
FFFh
FFEh
FFDh
SPECIAL FUNCTION REGISTER MAP
TOSU
FDFh
TOSH
TOSL
INDF2(3)
FBFh
CCPR1H
F9Fh
IPR1
FDEh
POSTINC2
(3)
FBEh
CCPR1L
F9Eh
PIR1
FDDh
POSTDEC2(3)
FBDh
CCP1CON
F9Dh
PIE1
(3)
FFCh
STKPTR
FDCh
PREINC2
FBCh
CCPR2H
F9Ch
—
FFBh
PCLATU
FDBh
PLUSW2(3)
FBBh
CCPR2L
F9Bh
—
FFAh
PCLATH
FDAh
FSR2H
FBAh
CCP2CON
F9Ah
—
FF9h
PCL
FD9h
FSR2L
FB9h
—
F99h
—
F98h
—
FF8h
TBLPTRU
FD8h
STATUS
FB8h
—
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
—
F97h
—
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
—
F96h
TRISE(2)
FF5h
TABLAT
FD5h
T0CON
FB5h
—
F95h
TRISD(2)
FF4h
PRODH
FD4h
—
FB4h
—
F94h
TRISC
FF3h
PRODL
FD3h
OSCCON
FB3h
TMR3H
F93h
TRISB
FF2h
INTCON
FD2h
LVDCON
FB2h
TMR3L
F92h
TRISA
FF1h
INTCON2
FD1h
WDTCON
FB1h
T3CON
F91h
—
FF0h
INTCON3
FD0h
RCON
FB0h
—
F90h
—
FEFh
INDF0(3)
FCFh
TMR1H
FAFh
SPBRG
F8Fh
—
FEEh
POSTINC0(3)
FCEh
TMR1L
FAEh
RCREG
F8Eh
—
FEDh
POSTDEC0(3)
FCDh
T1CON
FADh
TXREG
F8Dh
LATE(2)
FECh
PREINC0(3)
FCCh
TMR2
FACh
TXSTA
F8Ch
LATD(2)
FEBh
PLUSW0(3)
FCBh
PR2
FABh
RCSTA
F8Bh
LATC
FEAh
FSR0H
FCAh
T2CON
FAAh
—
F8Ah
LATB
FE9h
FSR0L
FC9h
SSPBUF
FA9h
—
F89h
LATA
FE8h
WREG
FC8h
SSPADD
FA8h
—
F88h
—
FE7h
INDF1(3)
FC7h
SSPSTAT
FA7h
—
F87h
—
FE6h
(3)
POSTINC1
FC6h
SSPCON1
FA6h
—
F86h
—
FE5h
POSTDEC1(3)
FC5h
SSPCON2
FA5h
—
F85h
—
FE4h
PREINC1(3)
FC4h
ADRESH
FA4h
—
F84h
PORTE(2)
FE3h
PLUSW1
(3)
FC3h
ADRESL
FA3h
—
F83h
PORTD(2)
FE2h
FSR1H
FC2h
ADCON0
FA2h
IPR2
F82h
PORTC
FE1h
FSR1L
FC1h
ADCON1
FA1h
PIR2
F81h
PORTB
FC0h
—
FA0h
PIE2
F80h
PORTA
FE0h
BSR
Note 1: Unimplemented registers are read as ’0’.
2: This register is not available on PIC18C2X2 devices.
3: This is not a physical register.
1999-2013 Microchip Technology Inc.
DS39026D-page 45
PIC18CXX2
TABLE 4-2:
File Name
REGISTER FILE SUMMARY
Bit 7
Bit 6
Bit 5
—
—
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Details
on page:
---0 0000
37
TOSH
Top-of-Stack High Byte (TOS)
0000 0000
37
TOSL
Top-of-Stack Low Byte (TOS)
0000 0000
37
TOSU
STKPTR
PCLATU
Top-of-Stack Upper Byte (TOS)
Value on
POR,
BOR
STKFUL
STKUNF
—
Return Stack Pointer
00-0 0000
38
—
—
—
Holding Register for PC
---0 0000
39
PCLATH
Holding Register for PC
0000 0000
39
PCL
PC Low Byte (PC)
0000 0000
39
---0 0000
57
TBLPTRU
—
—
bit21(2)
Program Memory Table Pointer Upper Byte (TBLPTR)
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR)
0000 0000
57
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR)
0000 0000
57
TABLAT
Program Memory Table Latch
0000 0000
57
PRODH
Product Register High Byte
xxxx xxxx
61
PRODL
Product Register Low Byte
xxxx xxxx
61
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
65
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
—
TMR0IP
—
RBIP
1111 -1-1
66
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
11-0 0-00
67
INTCON3
INDF0
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
N/A
50
POSTINC0
Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)
N/A
50
POSTDEC0
Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register)
N/A
50
PREINC0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)
N/A
50
PLUSW0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) value of FSR0 offset by value in WREG
N/A
50
FSR0H
---- 0000
50
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
—
xxxx xxxx
50
WREG
Working Register
xxxx xxxx
INDF1
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
N/A
50
POSTINC1
Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register)
N/A
50
POSTDEC1
Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register)
N/A
50
PREINC1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)
N/A
50
PLUSW1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) value of FSR1 offset by value in WREG
N/A
50
---- 0000
50
FSR1H
—
FSR1L
—
—
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
Indirect Data Memory Address Pointer 1 High Byte
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
—
—
—
Bank Select Register
xxxx xxxx
50
---- 0000
49
INDF2
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
N/A
50
POSTINC2
Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)
N/A
50
POSTDEC2
Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register)
N/A
50
PREINC2
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)
N/A
50
PLUSW2
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) value of FSR2 offset by value in WREG
N/A
50
---- 0000
50
FSR2H
FSR2L
STATUS
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
OV
Z
DC
C
xxxx xxxx
50
---x xxxx
52
TMR0H
Timer0 Register High Byte
0000 0000
95
TMR0L
Timer0 Register Low Byte
xxxx xxxx
95
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
93
—
—
—
—
—
—
—
SCS
---- ---0
20
—
—
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
--00 0101
175
OSCCON
LVDCON
Legend:
Note 1:
2:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
DS39026D-page 46
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 4-2:
File Name
WDTCON
RCON
REGISTER FILE SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
—
—
—
—
IPEN
LWRT
—
RI
TO
Bit 2
Value on
POR,
BOR
Details
on page:
Bit 1
Bit 0
—
—
SWDTE
---- ---0
183
PD
POR
BOR
0q-1 11qq
53, 56,
74
97
TMR1H
Timer1 Register High Byte
xxxx xxxx
TMR1L
Timer1 Register Low Byte
xxxx xxxx
97
0-00 0000
97
T1CON
RD16
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
TMR2
Timer2 Register
0000 0000
101
PR2
Timer2 Period Register
1111 1111
102
T2CON
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
SSPBUF
SSP Receive Buffer/Transmit Register
SSPADD
SSP Address Register in I2C Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode.
T2CKPS0
-000 0000
101
xxxx xxxx
121
0000 0000
128
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
116
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
118
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
SSPCON2
ADRESH
A/D Result Register High Byte
ADRESL
A/D Result Register Low Byte
0000 0000
120
xxxx xxxx
171,172
xxxx xxxx
171,172
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0
165
ADCON1
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
00-- 0000
166
CCPR1H
Capture/Compare/PWM Register1 High Byte
xxxx xxxx
111, 113
CCPR1L
Capture/Compare/PWM Register1 Low Byte
xxxx xxxx
111, 113
CCP1CON
—
—
DC1B1
DC1B0
CCPR2H
Capture/Compare/PWM Register2 High Byte
CCPR2L
Capture/Compare/PWM Register2 Low Byte
CCP2CON
—
—
TMR3H
Timer3 Register High Byte
TMR3L
Timer3 Register Low Byte
T3CON
SPBRG
RD16
T3CCP2
DC2B1
T3CKPS1
DC2B0
T3CKPS0
CCP1M3
CCP2M3
T3CCP1
CCP1M2
CCP2M2
T3SYNC
CCP1M1
CCP2M1
TMR3CS
CCP1M0
CCP2M0
TMR3ON
USART1 Baud Rate Generator
--00 0000
107
xxxx xxxx
111, 113
xxxx xxxx
111, 113
--00 0000
107
xxxx xxxx
103
xxxx xxxx
103
0000 0000
103
0000 0000
151
RCREG
USART1 Receive Register
0000 0000
158, 161,
163
TXREG
USART1 Transmit Register
0000 0000
156, 159,
162
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
149
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
150
Legend:
Note 1:
2:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
1999-2013 Microchip Technology Inc.
DS39026D-page 47
PIC18CXX2
TABLE 4-2:
REGISTER FILE SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Details
on page:
IPR2
—
—
—
—
BCLIP
LVDIP
TMR3IP
CCP2IP
---- 1111
73
PIR2
—
—
—
—
BCLIF
LVDIF
TMR3IF
CCP2IF
---- 0000
69
PIE2
—
—
—
—
BCLIE
LVDIE
TMR3IE
CCP2IE
---- 0000
71
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111
72
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
68
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
70
IBF
OBF
IBOV
PSPMODE
—
0000 -111
88
File Name
TRISE
Data Direction bits for PORTE
TRISD
Data Direction Control Register for PORTD
1111 1111
85
TRISC
Data Direction Control Register for PORTC
1111 1111
83
TRISB
Data Direction Control Register for PORTB
1111 1111
80
-111 1111
77
---- -xxx
87
TRISA
—
TRISA6(1)
LATE
—
—
Data Direction Control Register for PORTA
—
—
—
Read PORTE Data Latch,
Write PORTE Data Latch
LATD
Read PORTD Data Latch, Write PORTD Data Latch
xxxx xxxx
85
LATC
Read PORTC Data Latch, Write PORTC Data Latch
xxxx xxxx
83
LATB
Read PORTB Data Latch, Write PORTB Data Latch
xxxx xxxx
80
-xxx xxxx
77
LATA
—
LATA6(1)
Read PORTA Data Latch, Write PORTA Data Latch(1)
PORTE
Read PORTE pins, Write PORTE Data Latch
---- -000
87
PORTD
Read PORTD pins, Write PORTD Data Latch
xxxx xxxx
85
PORTC
Read PORTC pins, Write PORTC Data Latch
xxxx xxxx
83
PORTB
Read PORTB pins, Write PORTB Data Latch
xxxx xxxx
80
-x0x 0000
77
PORTA
Legend:
Note 1:
2:
—
RA6(1)
Read PORTA pins, Write PORTA Data Latch(1)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
DS39026D-page 48
1999-2013 Microchip Technology Inc.
PIC18CXX2
4.10
Access Bank
can be accessed without any software overhead. This
is useful for testing status flags and modifying control
bits.
The Access Bank is an architectural enhancement,
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
4.11
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
This data memory region can be used for:
•
•
•
•
•
Intermediate computational values
Local variables of subroutines
Faster context saving/switching of variables
Common variables
Faster evaluation/control of SFRs (no banking)
BSR holds the upper 4 bits of the 12-bit RAM
address. The BSR bits will always read ’0’s, and
writes will have no effect.
The Access Bank is comprised of the upper 128 bytes
in Bank 15 (SFRs) and the lower 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-6
and Figure 4-7 indicate the Access RAM areas.
A MOVLB instruction has been provided in the instruction set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted by the ’a’ bit (for
access bit).
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
When forced in the Access Bank (a = ’0’), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function registers, so that these registers
FIGURE 4-8:
Bank Select Register (BSR)
A MOVFF instruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 provides a description of indirect addressing, which allows linear addressing of the entire RAM
space.
DIRECT ADDRESSING
Direct Addressing
BSR
Bank Select(2)
7
From Opcode(3)
0
Location Select(3)
00h
01h
0Eh
0Fh
000h
100h
E00h
F00h
0FFh
1FFh
EFFh
FFFh
Bank 14
Bank 15
Data
Memory(1)
Bank 0
Bank 1
Note 1: For register file map detail, see Table 4-1.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR) to the registers of the Access Bank.
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
1999-2013 Microchip Technology Inc.
DS39026D-page 49
PIC18CXX2
4.12
Indirect Addressing, INDF and
FSR Registers
Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-9
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address,
specified by the value of the FSR register.
Indirect addressing is possible by using one of the
INDF registers. Any instruction using the INDF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = '0'), will read 00h. Writing to the INDF
register indirectly, results in a no operation. The FSR
register contains a 12-bit address, which is shown in
Figure 4-10.
The INDFn register is not a physical register. Addressing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addressing.
Example 4-4 shows a simple use of indirect addressing
to clear the RAM in Bank1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 4-4:
NEXT
LFSR
CLRF
HOW TO CLEAR RAM
(BANK1) USING INDIRECT
ADDRESSING
FSR0, 0x100
POSTINC0
BTFSS FSR0H, 1
GOTO NEXT
CONTINUE
;
;
;
;
;
;
Clear INDF register
& inc pointer
All done w/ Bank1?
NO, clear next
YES, continue
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bit wide. To store the 12-bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
1.
2.
3.
FSR0: composed of FSR0H:FSR0L
FSR1: composed of FSR1H:FSR1L
FSR2: composed of FSR2H:FSR2L
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect addressing, with the value in the corresponding FSR register
being the address of the data.
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all '0's are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOP instruction and the
STATUS bits are not affected.
4.12.1
INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Performing an operation on one of these five registers determines how the FSR will be modified during indirect
addressing.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
• Do nothing to FSRn after an indirect access (no
change) - INDFn
• Auto-decrement FSRn after an indirect access
(post-decrement) - POSTDECn
• Auto-increment FSRn after an indirect access
(post-increment) - POSTINCn
• Auto-increment FSRn before an indirect access
(pre-increment) - PREINCn
• Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) - PLUSWn
When using the auto-increment or auto-decrement features, the effect on the FSR is not reflected in the
STATUS register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
Incrementing or decrementing an FSR affects all 12
bits. That is, when FSRnL overflows from an increment,
FSRnH will be incremented automatically.
Adding these features allows the FSRn to be used as a
stack pointer, in addition to its uses for table operations
in data memory.
Each FSR has an address associated with it that performs an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configured to add the signed value in the WREG register and the value in FSR to form the address before an
indirect access. The FSR value is not changed.
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(STATUS bits are not affected).
If an instruction writes a value to INDF0, the value will
be written to the address pointed to by FSR0H:FSR0L.
A read from INDF1 reads the data from the address
pointed to by FSR1H:FSR1L. INDFn can be used in
code anywhere an operand can be used.
DS39026D-page 50
1999-2013 Microchip Technology Inc.
PIC18CXX2
If an indirect addressing operation is done where the
target address is an FSRnH or FSRnL register, the
write operation will dominate over the pre- or postincrement/decrement functions.
FIGURE 4-9:
INDIRECT ADDRESSING OPERATION
RAM
0h
Instruction
Executed
Opcode
Address
FFFh
12
File Address = access of an indirect addressing register
BSR
Instruction
Fetched
4
Opcode
FIGURE 4-10:
12
12
8
FSR
File
INDIRECT ADDRESSING
Indirect Addressing
11
FSR Register
0
Location Select
0000h
Data
Memory(1)
0FFFh
Note 1: For register file map detail, see Table 4-1.
1999-2013 Microchip Technology Inc.
DS39026D-page 51
PIC18CXX2
4.13
STATUS Register
The STATUS register, shown in Register 4-2, contains
the arithmetic status of the ALU. The STATUS register
can be the destination for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
then the write to these five bits is disabled. These bits
are set or cleared according to the device logic. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.
REGISTER 4-2:
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to
alter the STATUS register, because these instructions
do not affect the Z, C, DC, OV or N bits from the
STATUS register. For other instructions not affecting
any status bits, see Table 19-2.
Note:
The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
STATUS REGISTER
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
N
OV
Z
DC
C
bit 7
bit 0
bit 7-5
Unimplemented: Read as '0'
bit 4
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative, (ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude, which causes the sign bit (bit7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWF instructions
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
Note:
bit 0
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the bit 4 or bit 3 of the source register.
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWF instructions
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
DS39026D-page 52
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
1999-2013 Microchip Technology Inc.
PIC18CXX2
4.13.1
RCON REGISTER
.
Note 1: If the BOREN configuration bit is set
(Brown-out Reset enabled), the BOR bit is
’1’ on a Power-on Reset. After a Brownout Reset has occurred, the BOR bit will
be clear and must be set by firmware to
indicate the occurrence of the next Brownout Reset.
If the BOREN configuration bit is clear
(Brown-out Reset disabled), BOR is
unknown after Power-on Reset and
Brown-out Reset conditions.
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device RESET. These flags include the TO, PD, POR,
BOR and RI bits. This register is readable and writable.
2: It is recommended that the POR bit be set
after a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
REGISTER 4-3:
RCON REGISTER
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
IPEN
LWRT
—
RI
TO
PD
POR
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6
LWRT: Long Write Enable bit
1 = Enable TBLWT to internal program memory
Once this bit is set, it can only be cleared by a POR or MCLR Reset.
0 = Disable TBLWT to internal program memory; TBLWT only to external program memory
bit 5
Unimplemented: Read as '0'
bit 4
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed
0 = The RESET instruction was executed causing a device RESET
(must be set in software after a Brown-out Reset occurs)
bit 3
TO: Watchdog Time-out Flag bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 2
PD: Power-down Detection Flag bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 1
POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred
0 = A Power-on Reset occurred
(must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred
0 = A Brown-out Reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
1999-2013 Microchip Technology Inc.
x = Bit is unknown
DS39026D-page 53
PIC18CXX2
NOTES:
DS39026D-page 54
1999-2013 Microchip Technology Inc.
PIC18CXX2
5.0
TABLE READS/TABLE WRITES
Table Read operations retrieve data from program
memory and place it into the data memory space.
Figure 5-1 shows the operation of a Table Read with
program and data memory.
Enhanced devices have two memory spaces: the program memory space and the data memory space. The
program memory space is 16-bits wide, while the data
memory space is 8 bits wide. Table Reads and Table
Writes have been provided to move data between
these two memory spaces through an 8-bit register
(TABLAT).
Table Write operations store data from the data memory space into program memory. Figure 5-2 shows the
operation of a Table Write with program and data
memory.
Table operations work with byte entities. A table block
containing data is not required to be word aligned, so a
table block can start and end at any byte address. If a
Table Write is being used to write an executable program to program memory, program instructions will
need to be word aligned.
The operations that allow the processor to move data
between the data and program memory spaces are:
• Table Read (TBLRD)
• Table Write (TBLWT)
FIGURE 5-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer points to a byte in program memory.
FIGURE 5-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
(1)
Table Pointer
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer points to a byte in program memory.
1999-2013 Microchip Technology Inc.
DS39026D-page 55
PIC18CXX2
5.1
5.1.1
Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• TBLPTR registers
• TABLAT register
• RCON register
REGISTER 5-1:
RCON REGISTER
The LWRT bit specifies the operation of Table Writes to
internal memory when the VPP voltage is applied to the
MCLR pin. When the LWRT bit is set, the controller
continues to execute user code, but long Table Writes
are allowed (for programming internal program memory) from user mode. The LWRT bit can be cleared only
by performing either a POR or MCLR Reset.
RCON REGISTER (ADDRESS: FD0h)
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
IPEN
LWRT
—
RI
TO
PD
POR
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6
LWRT: Long Write Enable bit
1 = Enable TBLWT to internal program memory
0 = Disable TBLWT to internal program memory.
Note:
Only cleared on a POR or MCLR Reset.
This bit has no effect on TBLWTs to external program memory.
bit 5
Unimplemented: Read as '0'
bit 4
RI: RESET Instruction Flag bit
1 = No RESET instruction occurred
0 = A RESET instruction occurred
bit 3
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 2
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset or POR Reset occurred
0 = A Brown-out Reset or POR Reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend:
DS39026D-page 56
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
1999-2013 Microchip Technology Inc.
PIC18CXX2
5.1.2
TABLAT - TABLE LATCH REGISTER
5.1.3
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data memory.
TBLPTR - TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers (Table Pointer Upper Byte, High
Byte and Low Byte). These three registers
(TBLPTRU:TBLPTRH:TBLPTRL) join to form a 22-bit
wide pointer. The lower 21-bits allow the device to
address up to 2 Mbytes of program memory space. The
22nd bit allows access to the Device ID, the User ID
and the Configuration bits.
The Table Pointer, TBLPTR, is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways, based on the table operation.
These operations are shown in Table 5-1. These operations on the TBLPTR only affect the lower 21-bits.
TABLE 5-1:
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example
TBLRD*
TBLWT*
TBLRD*+
TBLWT*+
TBLRD*TBLWT*TBLRD+*
TBLWT+*
5.2
5.2.1
Operation on Table Pointer
TBLPTR is not modified
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
Internal Program Memory Read/
Writes
TABLE READ OVERVIEW (TBLRD)
The TBLRD instructions are used to read data from
program memory to data memory.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next Table Read operation.
Table Reads from program memory are performed one
byte at a time. The instruction will load TABLAT with the
one byte from program memory pointed to by TBLPTR.
5.2.2
INTERNAL PROGRAM MEMORY
WRITE BLOCK SIZE
The internal program memory of PIC18CXXX devices
is written in blocks. For PIC18CXX2 devices, the write
block size is 2 bytes. Consequently, Table Write operations to internal program memory are performed in
pairs, one byte at a time.
1999-2013 Microchip Technology Inc.
When a Table Write occurs to an even program memory address (TBLPTR = 0), the contents of TABLAT
are transferred to an internal holding register. This is
performed as a short write and the program memory
block is not actually programmed at this time. The holding register is not accessible by the user.
When a Table Write occurs to an odd program memory
address (TBLPTR=1), a long write is started. During the long write, the contents of TABLAT are written
to the high byte of the program memory block and the
contents of the holding register are transferred to the
low byte of the program memory block.
Figure 5-3 shows the holding register and the program
memory write blocks.
If a single byte is to be programmed, the low (even)
byte of the destination program word should be read
using TBLRD*, modified or changed, if required, and
written back to the same address using TBLWT*+. The
high (odd) byte should be read using TBLRD*, modified
or changed if required, and written back to the same
address using TBLWT. A write to the odd address will
cause a long write to begin. This process ensures that
existing data in either byte will not be changed unless
desired.
DS39026D-page 57
PIC18CXX2
FIGURE 5-3:
HOLDING REGISTER AND THE WRITE BLOCK
Program Memory (x 2-bits)
Block n
Write Block
MSB
Holding Register
Block n + 1
Block n + 2
The write to the MSB of the Write Block
causes the entire block to be written to program memory. The program memory block
that is written depends on the address that is
written to in the MSB of the Write Block.
5.2.2.1
Operation
The long write is what actually programs words of data
into the internal memory. When a TBLWT to the MSB of
the write block occurs, instruction execution is halted.
During this time, programming voltage and the data
stored in internal latches is applied to program memory.
For a long write to occur:
1.
2.
3.
MCLR/VPP pin must be at the programming
voltage
LWRT bit must be set
TBLWT to the address of the MSB of the write
block
If the LWRT bit is clear, a short write will occur and program memory will not be changed. If the TBLWT is not
to the MSB of the write block, then the programming
phase is not initiated.
Setting the LWRT bit enables long writes when the
MCLR pin is taken to VPP voltage. Once the LWRT bit
is set, it can be cleared only by performing a POR or
MCLR Reset.
To ensure that the memory location has been well programmed, a minimum programming time is required.
The long write can be terminated after the programming time has expired by a RESET or an interrupt.
Having only one interrupt source enabled to terminate
the long write ensures that no unintended interrupts will
prematurely terminate the long write.
DS39026D-page 58
5.2.2.2
Sequence of Events
The sequence of events for programming an internal
program memory location should be:
1.
Enable the interrupt that terminates the long
write. Disable all other interrupts.
2. Clear the source interrupt flag.
3. If Interrupt Service Routine execution is desired
when the device wakes, enable global
interrupts.
4. Set LWRT bit in the RCON register.
5. Raise MCLR/VPP pin to the programming
voltage, VPP.
6. Clear the WDT (if enabled).
7. Set the interrupt source to interrupt at the
required time.
8. Execute the Table Write for the lower (even)
byte. This will be a short write.
9. Execute the Table Write for the upper (odd) byte.
This will be a long write. The microcontroller will
then halt internal operations. (This is not the
same as SLEEP mode, as the clocks and
peripherals will continue to run.) The interrupt
will cause the microcontroller to resume
operation.
10. If GIE was set, service the interrupt request.
11. Lower MCLR/VPP pin to VDD.
12. Verify the memory location (Table Read).
1999-2013 Microchip Technology Inc.
PIC18CXX2
5.2.3
INTERRUPTS
Depending on the states of interrupt priority bits, the
GIE/GIEH bit or the PIE/GIEL bit, program execution
can either be vectored to the high or low priority Interrupt Service Routine (ISR), or continue execution from
where programming commenced.
The long write must be terminated by a RESET or any
interrupt.
The interrupt source must have its interrupt enable bit
set. When the source sets its interrupt flag, programming will terminate. This will occur, regardless of the
settings of interrupt priority bits, the GIE/GIEH bit, or
the PIE/GIEL bit.
TABLE 5-2:
In either case, the interrupt flag will not be cleared
when programming is terminated and will need to be
cleared by the software.
LONG WRITE EXECUTION, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS
GIE/
GIEH
PIE/
GIEL
Priority
Interrupt
Enable
Interrupt
Flag
X
X
X
0
(default)
X
Long write continues
even if interrupt flag becomes set.
X
X
X
1
0
Long write continues, will resume operations
when the interrupt flag is set.
0
(default)
0
(default)
X
1
1
Terminates long write, executes next instruction.
Interrupt flag not cleared.
0
(default)
1
1
high priority
(default)
1
1
Terminates long write, executes next instruction.
Interrupt flag not cleared.
1
0
(default)
0
low
1
1
Terminates long write, executes next instruction.
Interrupt flag not cleared.
0
(default)
1
0
low
1
1
Terminates long write,
branches to low priority interrupt vector.
Interrupt flag can be cleared by ISR.
1
0
(default)
1
high priority
(default)
1
1
Terminates long write,
branches to high priority interrupt vector.
Interrupt flag can be cleared by ISR.
5.2.4
Action
UNEXPECTED TERMINATION OF
WRITE OPERATIONS
If a write is terminated by an unplanned event such as
loss of power, an unexpected RESET, or an interrupt
that was not disabled, the memory location just programmed should be verified and reprogrammed if
needed.
1999-2013 Microchip Technology Inc.
DS39026D-page 59
PIC18CXX2
NOTES:
DS39026D-page 60
1999-2013 Microchip Technology Inc.
PIC18CXX2
6.0
8 X 8 HARDWARE MULTIPLIER
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
6.1
Introduction
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18CXX2 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product register pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
TABLE 6-1:
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
Program
Memory
(Words)
Cycles
(Max)
Without hardware multiply
13
Hardware multiply
1
Without hardware multiply
33
Hardware multiply
6
Without hardware multiply
Multiply Method
@ 10 MHz
@ 4 MHz
69
6.9 s
27.6 s
69 s
1
100 ns
400 ns
1 s
91
9.1 s
36.4 s
91 s
6
600 ns
2.4 s
6 s
21
242
24.2 s
96.8 s
242 s
Hardware multiply
24
24
2.4 s
9.6 s
24 s
Without hardware multiply
52
254
25.4 s
102.6 s
254 s
Hardware multiply
36
36
3.6 s
14.4 s
36 s
Operation
EXAMPLE 6-2:
Example 6-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 6-1:
ARG1, W
ARG2
Time
@ 40 MHz
Example 6-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
MOVF
MULWF
Table 6-1 shows a performance comparison between
enhanced devices using the single cycle hardware multiply, and performing the same function without the
hardware multiply.
PERFORMANCE COMPARISON
Routine
6.2
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
ARG1,
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH, F
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
8 x 8 UNSIGNED
MULTIPLY ROUTINE
;
; ARG1 * ARG2 ->
;
PRODH:PRODL
;
;
;
;
;
ARG1 * ARG2 ->
PRODH:PRODL
Test Sign Bit
PRODH = PRODH
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
Example 6-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 6-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 6-1:
RES3:RES0
1999-2013 Microchip Technology Inc.
W
=
=
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 216)+
(ARG1H ARG2L 28)+
(ARG1L ARG2H 28)+
(ARG1L ARG2L)
DS39026D-page 61
PIC18CXX2
EXAMPLE 6-3:
MOVF
MULWF
16 x 16 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 6-4:
ARG1L, W
ARG2L
MOVFF
MOVFF
; ARG1L * ARG2L ->
; PRODH:PRODL
PRODH, RES1 ;
PRODL, RES0 ;
MOVF
MULWF
ARG1H, W
ARG2H
;
MOVF
MULWF
16 x 16 SIGNED
MULTIPLY ROUTINE
ARG1L, W
ARG2L
MOVFF
MOVFF
; ARG1L * ARG2L ->
; PRODH:PRODL
PRODH, RES1 ;
PRODL, RES0 ;
MOVF
MULWF
ARG1H, W
ARG2H
;
MOVFF
MOVFF
; ARG1H * ARG2H ->
; PRODH:PRODL
PRODH, RES3 ;
PRODL, RES2 ;
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL,
RES1,
PRODH,
RES2,
WREG,
RES3,
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL,
RES1,
PRODH,
RES2,
WREG,
RES3,
;
MOVFF
MOVFF
; ARG1H * ARG2H ->
; PRODH:PRODL
PRODH, RES3 ;
PRODL, RES2 ;
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL,
RES1,
PRODH,
RES2,
WREG,
RES3,
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG, F
RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
;
W
F
W
F
F
F
;
;
;
;
;
;
;
;
ARG1L * ARG2H ->
PRODH:PRODL
Add cross
products
;
W
F
W
F
F
F
;
;
;
;
;
;
;
;
ARG1L * ARG2H ->
PRODH:PRODL
Add cross
products
;
W
F
W
F
F
F
;
;
;
;
;
;
;
;
;
ARG1H * ARG2L ->
PRODH:PRODL
Add cross
products
;
;
;
;
;
;
;
;
;
ARG1H * ARG2L ->
PRODH:PRODL
Add cross
products
;
Example 6-4 shows the sequence to do a 16 x 16
signed multiply. Equation 6-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the arguments, each argument pairs’ Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
EQUATION 6-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
=
ARG1H:ARG1L ARG2H:ARG2L
=
(ARG1H ARG2H 216)+
(ARG1H ARG2L 28)+
(ARG1L ARG2H 28)+
(ARG1L ARG2L)+
(-1 ARG2H ARG1H:ARG1L 216)+
(-1 ARG1H ARG2H:ARG2L 216)
DS39026D-page 62
;
SIGN_ARG1
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
;
CONT_CODE
:
1999-2013 Microchip Technology Inc.
PIC18CXX2
7.0
INTERRUPTS
The PIC18CXX2 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high priority
level, or a low priority level. The high priority interrupt
vector is at 000008h and the low priority interrupt vector
is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress.
There are ten registers which are used to control interrupt operation. These registers are:
•
•
•
•
•
•
•
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2
PIE1, PIE2
IPR1, IPR2
It is recommended that the Microchip header files supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
Each interrupt source has three bits to control its operation. The functions of these bits are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC® mid-range devices. In Compatibility
mode, the interrupt priority bits for each source have no
effect. INTCON is the PEIE bit, which enables/disables all peripheral interrupt sources. INTCON is
the GIE bit, which enables/disables all interrupt
sources. All interrupts branch to address 000008h in
Compatibility mode.
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH, or GIEL bit.
High priority interrupt sources can interrupt a low priority interrupt.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
The interrupt priority feature is enabled by setting the
IPEN bit (RCON). When interrupt priority is
enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON) enables all
interrupts that have the priority bit set. Setting the GIEL
bit (INTCON) enables all interrupts that have the
priority bit cleared. When the interrupt flag, enable bit
and appropriate global interrupt enable bit are set, the
interrupt will vector immediately to address 000008h or
000018h, depending on the priority level. Individual
interrupts can be disabled through their corresponding
enable bits.
1999-2013 Microchip Technology Inc.
DS39026D-page 63
PIC18CXX2
FIGURE 7-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Wake-up if in SLEEP mode
Interrupt to CPU
Vector to location
0008h
GIEH/GIE
TMR1IF
TMR1IE
TMR1IP
IPE
IPEN
XXXXIF
XXXXIE
XXXXIP
GIEL/PEIE
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
TMR1IF
TMR1IE
TMR1IP
RBIF
RBIE
RBIP
XXXXIF
XXXXIE
XXXXIP
GIEL\PEIE
INT0IF
INT0IE
Additional Peripheral Interrupts
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
DS39026D-page 64
1999-2013 Microchip Technology Inc.
PIC18CXX2
7.1
INTCON Registers
The INTCON Registers are readable and writable registers, which contains various enable, priority, and flag
bits.
REGISTER 7-1:
INTCON REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
bit 7
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high priority interrupts
0 = Disables all high priority interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
1999-2013 Microchip Technology Inc.
DS39026D-page 65
PIC18CXX2
REGISTER 7-2:
INTCON2 REGISTER
R/W-1
RBPU
R/W-1
INTEDG0
R/W-1
INTEDG1
R/W-1
U-0
R/W-1
U-0
R/W-1
INTEDG2
—
TMR0IP
—
RBIP
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG0:External Interrupt0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5
INTEDG1: External Interrupt1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4
INTEDG2: External Interrupt2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3
Unimplemented: Read as '0'
bit 2
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
Unimplemented: Read as '0'
bit 0
RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
Note:
DS39026D-page 66
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
1999-2013 Microchip Technology Inc.
PIC18CXX2
REGISTER 7-3:
INTCON3 REGISTER
R/W-1
R/W-1
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
bit 7
bit 0
bit 7
INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
Unimplemented: Read as '0'
bit 4
INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2
Unimplemented: Read as '0'
bit 1
INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred
(must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred
(must be cleared in software)
0 = The INT1 external interrupt did not occur
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
1999-2013 Microchip Technology Inc.
DS39026D-page 67
PIC18CXX2
7.2
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Flag Registers (PIR1, PIR2).
Note 1: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON).
2: User software should ensure the appropriate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
REGISTER 7-4:
PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (PIR1)
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The USART receive buffer is empty
bit 4
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The USART transmit buffer is full
bit 3
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = MR1 register did not overflow
Legend:
DS39026D-page 68
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
1999-2013 Microchip Technology Inc.
PIC18CXX2
REGISTER 7-5:
PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (PIR2)
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
BCLIF
LVDIF
TMR3IF
CCP2IF
bit 7
bit 0
bit 7-4
Unimplemented: Read as '0'
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 2
LVDIF: Low Voltage Detect Interrupt Flag bit
1 = A low voltage condition occurred (must be cleared in software)
0 = The device voltage is above the Low Voltage Detect trip point
bit 1
TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 0
CCP2IF: CCPx Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
1999-2013 Microchip Technology Inc.
x = Bit is unknown
DS39026D-page 69
PIC18CXX2
7.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable Registers (PIE1, PIE2). When IPEN = 0,
the PEIE bit must be set to enable any of these peripheral interrupts.
REGISTER 7-6:
PERIPHERAL INTERRUPT ENABLE REGISTER 1 (PIE1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
DS39026D-page 70
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
1999-2013 Microchip Technology Inc.
PIC18CXX2
REGISTER 7-7:
PERIPHERAL INTERRUPT ENABLE REGISTER 2 (PIE2)
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
BCLIE
LVDIE
TMR3IE
CCP2IE
bit 7
bit 0
bit 7-4
Unimplemented: Read as '0'
bit 3
BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
LVDIE: Low Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enables the TMR3 overflow interrupt
0 = Disables the TMR3 overflow interrupt
bit 0
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
1999-2013 Microchip Technology Inc.
x = Bit is unknown
DS39026D-page 71
PIC18CXX2
7.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority Registers (IPR1, IPR2). The operation of
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 7-8:
PERIPHERAL INTERRUPT PRIORITY REGISTER 1 (IPR1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RCIP: USART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TXIP: USART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
DS39026D-page 72
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
1999-2013 Microchip Technology Inc.
PIC18CXX2
REGISTER 7-9:
PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (IPR2)
U-0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
—
BCLIP
LVDIP
TMR3IP
CCP2IP
bit 7
bit 0
bit 7-4
Unimplemented: Read as '0'
bit 3
BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
LVDIP: Low Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
1999-2013 Microchip Technology Inc.
x = Bit is unknown
DS39026D-page 73
PIC18CXX2
7.5
RCON Register
The RCON register contains the bit which is used to
enable prioritized interrupts (IPEN).
REGISTER 7-10:
RCON REGISTER
R/W-0
R/W-0
U-0
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
LWRT
—
RI
TO
PD
POR
BOR
bit 7
bit 7
bit 0
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6
LWRT: Long Write Enable bit
For details of bit operation, see Register 4-3
bit 5
Unimplemented: Read as '0'
bit 4
RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-3
bit 3
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-3
bit 2
PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-3
bit 1
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-3
bit 0
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-3
Legend:
DS39026D-page 74
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
1999-2013 Microchip Technology Inc.
PIC18CXX2
7.6
INT0 Interrupt
7.7
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge triggered: either rising, if the
corresponding INTEDGx bit is set in the INTCON2 register, or falling, if the INTEDGx bit is clear. When a valid
edge appears on the RBx/INTx pin, the corresponding
flag bit INTxF is set. This interrupt can be disabled by
clearing the corresponding enable bit INTxE. Flag bit
INTxF must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wake-up the
processor from SLEEP, if bit INTxE was set prior to
going into SLEEP. If the global interrupt enable bit GIE
set, the processor will branch to the interrupt vector
following wake-up.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits, INT1IP
(INTCON3) and INT2IP (INTCON3). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
TMR0 Interrupt
In 8-bit mode (which is the default), an overflow (FFh
00h) in the TMR0 register will set flag bit TMR0IF. In
16-bit mode, an overflow (FFFFh 0000h) in the
TMR0H:TMR0L registers will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit T0IE (INTCON). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2). See Section 8.0 for further details on the Timer0 module.
7.8
PORTB Interrupt-on-Change
An input change on PORTB sets flag bit RBIF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON).
Interrupt priority for PORTB Interrupt-on-change is
determined by the value contained in the interrupt priority bit, RBIP (INTCON2).
7.9
Context Saving During Interrupts
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return
from interrupt is not used (see Section 4.3), the user
may need to save the WREG, STATUS and BSR registers in software. Depending on the user’s application,
other registers may also need to be saved. Example 7-1
saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine.
EXAMPLE 7-1:
MOVWF
MOVFF
MOVFF
;
; USER
;
MOVFF
MOVF
MOVFF
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR located anywhere
ISR CODE
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
1999-2013 Microchip Technology Inc.
; Restore BSR
; Restore WREG
; Restore STATUS
DS39026D-page 75
PIC18CXX2
NOTES:
DS39026D-page 76
1999-2013 Microchip Technology Inc.
PIC18CXX2
8.0
I/O PORTS
Depending on the device selected, there are either five
ports, or three ports available. Some pins of the I/O
ports are multiplexed with an alternate function from
the peripheral features on the device. In general, when
a peripheral is enabled, that pin may not be used as a
general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The data latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are
driving.
8.1
INITIALIZING PORTA
CLRF PORTA
;
;
;
;
;
;
;
;
;
;
;
;
;
CLRF LATA
MOVLW 0x07
MOVWF ADCON1
MOVLW 0xCF
MOVWF TRISA
FIGURE 8-1:
RD LATA
Data
Bus
D
Q
VDD
WR LATA
or
PORTA
On a Power-on Reset, these pins are configured as digital inputs.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
Initialize PORTA by
clearing output
data latches
Alternate method
to clear output
data latches
Configure A/D
for digital inputs
Value used to
initialize data
direction
Set RA as inputs
RA as outputs
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
PORTA, TRISA and LATA
Registers
PORTA is a 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Note:
EXAMPLE 8-1:
CK
Q
D
The other PORTA pins are multiplexed with analog
inputs and the analog VREF+ and VREF- inputs. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register1).
Note:
N
Q
WR TRISA
CK
I/O pin(1)
VSS
Analog
Input
Mode
Q
TRIS Latch
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register reads and writes the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA4/
T0CKI pin is a Schmitt Trigger input and an open drain
output. All other RA port pins have TTL input levels and
full CMOS output drivers.
P
Data Latch
TTL
Input
Buffer
RD TRISA
Q
D
EN
RD PORTA
SS Input (RA5 only)
To A/D Converter and LVD Modules
Note 1: I/O pins have protection diodes to VDD and VSS.
On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
1999-2013 Microchip Technology Inc.
DS39026D-page 77
PIC18CXX2
FIGURE 8-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
FIGURE 8-3:
BLOCK DIAGRAM OF RA6
ECRA6 or
RCRA6 Enable
Data
Bus
RD LATA
Data
Bus
WR LATA
or
PORTA
WR TRISA
RD LATA
D
Q
CK
Q
D
N
Data Latch
D
Q
CK
Q
I/O pin
VDD
WR LATA
or
PORTA
TRIS Latch
CK
Q
D
WR
TRISA
CK
N
Q
VSS
Data Bus
Q
I/O pin(1)
Q
TRIS Latch
RD TRISA
P
Data Latch
VSS
Schmitt
Trigger
Input
Buffer
Q
(1)
ECRA6 or
RCRA6
Enable
TTL
Input
Buffer
D
RD TRISA
ENEN
RD PORTA
Data Bus
Q
TMR0 Clock Input
Note 1: I/O pins have protection diodes to VDD and VSS.
D
EN
RD PORTA
Note 1: I/O pins have protection diodes to VDD and VSS.
DS39026D-page 78
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 8-1:
PORTA FUNCTIONS
Name
Bit#
Buffer
Function
RA0/AN0
bit0
TTL
Input/output or analog input.
RA1/AN1
bit1
TTL
Input/output or analog input.
RA2/AN2/VREF-
bit2
TTL
Input/output or analog input or VREF-.
RA3/AN3/VREF+
bit3
TTL
Input/output or analog input or VREF+.
RA4/T0CKI
bit4
ST
Input/output or external clock input for Timer0.
Output is open drain type.
RA5/SS/AN4/LVDIN
bit5
TTL
Input/output or slave select input for synchronous serial port or analog
input, or low voltage detect input.
OSC2/CLKO/RA6
bit6
TTL
OSC2 or clock output or I/O pin.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 8-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA6
RA5
RA4
RA3
RA2
RA1
RA0
Value on
POR,
BOR
Value on all
other
RESETS
PORTA
—
LATA
—
Latch A Data Output Register
--xx xxxx --uu uuuu
TRISA
—
PORTA Data Direction Register
--11 1111 --11 1111
ADCON1
ADFM ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
--0x 0000 --0u 0000
--0- 0000 --0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by PORTA.
1999-2013 Microchip Technology Inc.
DS39026D-page 79
PIC18CXX2
8.2
PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
Note:
On a Power-on Reset, these pins are configured as digital inputs.
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register reads and writes the latched output value for
PORTB.
EXAMPLE 8-2:
CLRF
CLRF
PORTB
LATB
MOVLW 0xCF
MOVWF TRISB
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB3 can be configured by the configuration bit
CCP2MX as the alternate peripheral pin for the CCP2
module (CCP2MX = ‘0’).
FIGURE 8-4:
BLOCK DIAGRAM OF
RB7:RB4 PINS
VDD
RBPU(2)
Weak
P Pull-up
INITIALIZING PORTB
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RB as inputs
RB as outputs
RB as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
Four of the PORTB pins, RB7:RB4, have an interrupton-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON).
Data Latch
Data Bus
D
WR LATB
or
PORTB
Q
I/O
pin(1)
CK
TRIS Latch
D
WR TRISB
Q
TTL
Input
Buffer
CK
ST
Buffer
RD TRISB
RD LATB
Latch
Q
Set RBIF
D
EN
RD PORTB
Q
Q1
D
RD PORTB
From other
RB7:RB4 pins
EN
Q3
RBx/INTx
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
Clear flag bit RBIF.
DS39026D-page 80
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 8-5:
BLOCK DIAGRAM OF RB2:RB0 PINS
VDD
RBPU(2)
Weak
P Pull-up
Data Latch
Data Bus
D
WR Port
Q
I/O pin(1)
CK
TRIS Latch
D
WR TRIS
Q
TTL
Input
Buffer
CK
RD TRIS
Q
D
EN
RD Port
RB0/INT
Schmitt Trigger Buffer
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG).
FIGURE 8-6:
BLOCK DIAGRAM OF RB3
VDD
RBPU
Weak
P Pull-up
(2)
CCP2MX
CCP Output(3)
1
VDD
P
0
Enable
CCP Output(3)
Data Bus
WR LATB or
WR PORTB
Data Latch
D
I/O pin(1)
Q
N
CK
VSS
TRIS Latch
D
WR TRISB
CK
TTL
Input
Buffer
Q
RD TRISB
RD LATB
Q
RD PORTB
D
EN
RD PORTB
CCP2 Input(3)
Schmitt Trigger
Buffer
CCP2MX = 0
Note 1: I/O pin has diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2).
3: The CCP2 input/output is multiplexed with RB3, if the CCP2MX bit is enabled (=’0’) in the configuration register.
1999-2013 Microchip Technology Inc.
DS39026D-page 81
PIC18CXX2
TABLE 8-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
RB0/INT0
bit0
TTL/ST(1)
Input/output pin or external interrupt input1. Internal software
programmable weak pull-up.
RB1/INT1
bit1
TTL/ST(1)
Input/output pin or external interrupt input2. Internal software
programmable weak pull-up.
RB2/INT2
bit2
TTL/ST(1)
Input/output pin or external interrupt input3. Internal software
programmable weak pull-up.
RB3/CCP2(3)
bit3
TTL/ST(4)
Input/output pin. Capture2 input/Compare2 output/PWM output when
CCP2MX configuration bit is enabled. Internal software
programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up.
RB6
bit6
TTL/ST(2)
Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up. Serial programming clock.
RB7
bit7
TTL/ST(2)
Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up. Serial programming data.
Legend:
Note 1:
2:
3:
4:
TTL = TTL input, ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on.
This buffer is a Schmitt Trigger input when configured as the CCP2 input.
TABLE 8-4:
Name
PORTB
Function
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
LATB
LATB Data Output Register
TRISB
PORTB Data Direction Register
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
—
TMR0IP
—
RBIP
1111 -1-1
1111 -1-1
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
11-0 0-00
11-0 0-00
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS39026D-page 82
1999-2013 Microchip Technology Inc.
PIC18CXX2
8.3
PORTC, TRISC and LATC
Registers
The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
PORTC is an 8-bit wide, bi-directional port. The corresponding Data Direction Register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
Note:
On a Power-on Reset, these pins are configured as digital inputs.
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register reads and writes the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 8-5). PORTC pins have Schmitt Trigger input
buffers.
RC1 is normally configured by the configuration bit
CCP2MX as the default peripheral pin for the CCP2
module (default/erased state, CCP2MX = ‘1’).
EXAMPLE 8-3:
CLRF
PORTC
CLRF
LATC
MOVLW 0xCF
MOVWF TRISC
INITIALIZING PORTC
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTC by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RC as inputs
RC as outputs
RC as inputs
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make
a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.
FIGURE 8-7:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Port/Peripheral Select(2)
VDD
Peripheral Data Out
RD LATC
Data Bus
WR LATC or
WR PORTC
Data Latch
D
Q
CK
Q
0
P
1
I/O pin(1)
DDR Latch
D
Q
WR TRISC
CK
Q
N
RD TRISC
VSS
Schmitt
Trigger
Peripheral Output
Enable(3)
Q
D
EN
RD PORTC
Peripheral Data In
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port data (input) and peripheral output.
3: Peripheral Output Enable is only active if peripheral select is active.
1999-2013 Microchip Technology Inc.
DS39026D-page 83
PIC18CXX2
TABLE 8-5:
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0/T1OSO/T1CKI
bit0
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2
bit1
ST
Input/output port pin, Timer1 oscillator input, or Capture2 input/
Compare2 output/PWM output when CCP2MX configuration bit is
disabled.
RC2/CCP1
bit2
ST
Input/output port pin or Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
bit3
ST
RC3 can also be the synchronous serial clock for both SPI and
I2C modes.
RC4/SDI/SDA
bit4
ST
RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode).
RC5/SDO
bit5
ST
Input/output port pin or Synchronous Serial Port Data output.
RC6/TX/CK
bit6
ST
Input/output port pin, Addressable USART Asynchronous Transmit, or
Addressable USART Synchronous Clock.
RC7/RX/DT
bit7
ST
Input/output port pin, Addressable USART Asynchronous Receive, or
Addressable USART Synchronous Data.
Legend: ST = Schmitt Trigger input
TABLE 8-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
LATC
LATC Data Output Register
xxxx xxxx
uuuu uuuu
TRISC
PORTC Data Direction Register
1111 1111
1111 1111
Legend: x = unknown, u = unchanged
DS39026D-page 84
1999-2013 Microchip Technology Inc.
PIC18CXX2
8.4
PORTD, TRISD and LATD
Registers
FIGURE 8-8:
PORTD BLOCK DIAGRAM
IN I/O PORT MODE
This section is only applicable to the PIC18C4X2
devices.
PORTD is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISD bit (= 0) will
make the corresponding PORTD pin an output (i.e., put
the contents of the output latch on the selected pin).
Note:
On a Power-on Reset, these pins are configured as digital inputs.
Data
Bus
WR LATD
or
PORTD
WR TRISD
CLRF
PORTD
CLRF
LATD
MOVLW 0xCF
MOVWF TRISD
Q
I/O pin(1)
CK
Data Latch
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
RD TRISD
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or
output.
EXAMPLE 8-4:
D
D
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register reads and writes the latched output value for
PORTD.
PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit
PSPMODE (TRISE). In this mode, the input buffers
are TTL. See Section 8.6 for additional information on
the Parallel Slave Port (PSP).
RD LATD
Q
D
ENEN
RD PORTD
Note 1: I/O pins have diode protection to VDD and VSS.
INITIALIZING PORTD
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTD by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RD as inputs
RD as outputs
RD as inputs
1999-2013 Microchip Technology Inc.
DS39026D-page 85
PIC18CXX2
TABLE 8-7:
PORTD FUNCTIONS
Name
Bit#
Buffer Type
RD0/PSP0
bit0
ST/TTL(1)
Input/output port pin or parallel slave port bit0.
RD1/PSP1
bit1
ST/TTL(1)
Input/output port pin or parallel slave port bit1.
bit2
ST/TTL
(1)
Input/output port pin or parallel slave port bit2.
bit3
ST/TTL(1)
Input/output port pin or parallel slave port bit3.
RD4/PSP4
bit4
ST/TTL
(1)
Input/output port pin or parallel slave port bit4.
RD5/PSP5
bit5
ST/TTL(1)
Input/output port pin or parallel slave port bit5.
RD6/PSP6
bit6
ST/TTL(1)
Input/output port pin or parallel slave port bit6.
RD7/PSP7
bit7
ST/TTL(1)
Input/output port pin or parallel slave port bit7.
RD2/PSP2
RD3/PSP3
Function
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 8-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
0000 -111
0000 -111
LATD
LATD Data Output Register
TRISD
PORTD Data Direction Register
TRISE
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction bits
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.
DS39026D-page 86
1999-2013 Microchip Technology Inc.
PIC18CXX2
8.5
PORTE, TRISE and LATE
Registers
FIGURE 8-9:
PORTE BLOCK DIAGRAM
IN I/O PORT MODE
This section is only applicable to the PIC18C4X2
devices.
PORTE is a 3-bit wide, bi-directional port. The corresponding Data Direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e., put
the contents of the output latch on the selected pin).
Note:
On a Power-on Reset, these pins are configured as digital inputs.
RD LATE
Data
Bus
D
Q
I/O pin(1)
WR LATE
or
PORTE
CK
Data Latch
D
WR TRISE
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register reads and writes the latched output value for
PORTE.
Q
TRIS Latch
RD TRISE
PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7), which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
Register 8-1 shows the TRISE register, which also controls the parallel slave port operation.
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as '0's.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note:
Schmitt
Trigger
Input
Buffer
CK
Q
D
ENEN
RD PORTE
To Analog Converter
Note 1: I/O pins have diode protection to VDD and VSS.
On a Power-on Reset, these pins are configured as analog inputs.
EXAMPLE 8-5:
CLRF
PORTE
CLRF
LATE
MOVLW
MOVWF
MOVLW
0x07
ADCON1
0x03
MOVWF
TRISC
INITIALIZING PORTE
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTE by
clearing output
data latches
Alternate method
to clear output
data latches
Configure A/D
for digital inputs
Value used to
initialize data
direction
Set RE as inputs
RE as outputs
RE as inputs
1999-2013 Microchip Technology Inc.
DS39026D-page 87
PIC18CXX2
REGISTER 8-1:
TRISE REGISTER
R-0
IBF
R-0
OBF
R/W-0
IBOV
R/W-0
U-0
R/W-1
R/W-1
R/W-1
PSPMODE
—
TRISE2
TRISE1
TRISE0
bit 7
bit 0
bit 7
IBF: Input Buffer Full Status bit
1 = A word has been received and waiting to be read by the CPU
0 = No word has been received
bit 6
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read
(must be cleared in software)
0 = No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel Slave Port mode
0 = General purpose I/O mode
bit 3
Unimplemented: Read as '0'
bit 2
TRISE2: RE2 Direction Control bit
1 = Input
0 = Output
bit 1
TRISE1: RE1 Direction Control bit
1 = Input
0 = Output
bit 0
TRISE0: RE0 Direction Control bit
1 = Input
0 = Output
Legend:
DS39026D-page 88
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 8-9:
PORTE FUNCTIONS
Name
Bit#
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
bit0
bit1
bit2
Buffer Type
Function
ST/TTL(1)
Input/output port pin or read control input in Parallel Slave Port mode
or analog input:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected).
ST/TTL(1)
Input/output port pin or write control input in Parallel Slave Port mode
or analog input:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected).
ST/TTL(1)
Input/output port pin or chip select control input in Parallel Slave Port
mode or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 8-10:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
RE2
RE1
RE0
PORTE
—
—
—
—
—
---- -000
---- -000
LATE
—
—
—
—
—
LATE Data Output Register
---- -xxx
---- -uuu
TRISE
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction bits
0000 -111
0000 -111
ADFM
ADCS2
—
—
PCFG3
--0- -000
--0- -000
ADCON1
PCFG2
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE.
1999-2013 Microchip Technology Inc.
DS39026D-page 89
PIC18CXX2
8.6
FIGURE 8-10:
Parallel Slave Port
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)
The Parallel Slave Port is implemented on the 40-pin
devices only (PIC18C4X2).
PORTD operates as an 8-bit wide, parallel slave port,
or microprocessor port, when control bit PSPMODE
(TRISE) is set. It is asynchronously readable and
writable by the external world through RD control input
pin RE0/RD and WR control input pin RE1/WR.
Data Bus
D
WR LATD
or
PORTD
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE)
must be configured as inputs (set). The A/D port configuration bits PCFG2:PCFG0 (ADCON1) must be
set, which will configure pins RE2:RE0 as digital I/O.
Q
RDx
pin
CK
TTL
Data Latch
Q
RD PORTD
D
ENEN
RD LATD
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
One bit of PORTD
Set Interrupt Flag
The PORTE I/O pins become control inputs for the
microprocessor port when bit PSPMODE (TRISE)
is set. In this mode, the user must make sure that the
TRISE bits are set (pins are configured as digital
inputs), and the ADCON1 is configured for digital I/O.
In this mode, the input buffers are TTL.
PSPIF (PIR1)
Read
TTL
RD
Chip Select
TTL
CS
Write
WR
TTL
Note: I/O pin has protection diodes to VDD and VSS.
FIGURE 8-11:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
DS39026D-page 90
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 8-12:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
TABLE 8-11:
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on
POR, BOR
Value on all
other
RESETS
Port Data Latch when written; Port pins when read
xxxx xxxx
uuuu uuuu
LATD
LATD Data Output bits
xxxx xxxx
uuuu uuuu
TRISD
PORTD Data Direction bits
1111 1111
1111 1111
---- -000
---- -000
---- -xxx
---- -uuu
Name
PORTD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
—
—
—
—
—
LATE
—
—
—
—
—
LATE Data Output bits
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction bits
GIE/
GIEH
PEIE/
GIEL
INTCON
TMR0IF
INT0IE
RBIE
TMR0IF
RE1
Bit 0
PORTE
TRISE
RE2
Bit 1
INT0IF
RE0
RBIF
0000 -111
0000 -111
0000 000x
0000 000u
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0000 0000
0000 0000
ADCON1
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
--0- -000
--0- -000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.
1999-2013 Microchip Technology Inc.
DS39026D-page 91
PIC18CXX2
NOTES:
DS39026D-page 92
1999-2013 Microchip Technology Inc.
PIC18CXX2
9.0
TIMER0 MODULE
Figure 9-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 9-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
The Timer0 module has the following features:
• Software selectable as an 8-bit or 16-bit timer/
counter
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt-on-overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
• Edge select for external clock
REGISTER 9-1:
The T0CON register (Register 9-1) is a readable and
writable register that controls all the aspects of Timer0,
including the prescale selection.
T0CON: TIMER0 CONTROL REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
bit 7
bit 0
bit 7
TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6
T08BIT: Timer0 8-bit/16-bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2:0
T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 prescale value
110 = 1:128 prescale value
101 = 1:64 prescale value
100 = 1:32 prescale value
011 = 1:16 prescale value
010 = 1:8 prescale value
001 = 1:4 prescale value
000 = 1:2 prescale value
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
1999-2013 Microchip Technology Inc.
x = Bit is unknown
DS39026D-page 93
PIC18CXX2
FIGURE 9-1:
TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus
FOSC/4
0
8
0
1
Programmable
Prescaler
RA4/T0CKI
pin
1
Sync with
Internal
Clocks
TMR0
(2 TCY delay)
T0SE
3
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
T0PS2, T0PS1, T0PS0
T0CS
Note:
Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 9-2:
FOSC/4
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
0
0
1
Programmable
Prescaler
T0CKI pin
1
T0SE
Sync with
Internal
Clocks
TMR0L
TMR0
High Byte
8
(2 TCY delay)
3
Set Interrupt
Flag bit TMR0IF
on Overflow
Read TMR0L
T0PS2, T0PS1, T0PS0
T0CS
PSA
Write TMR0L
8
8
TMR0H
8
Data Bus
Note:
Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39026D-page 94
1999-2013 Microchip Technology Inc.
PIC18CXX2
9.1
Timer0 Operation
9.2.1
Timer0 can operate as a timer or as a counter.
The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program
execution).
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
9.3
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
9.4
An 8-bit counter is available as a prescaler for the
Timer0 module. The prescaler is not readable or
writable.
The PSA and T0PS2:T0PS0 bits determine the prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4,..., 1:256 are
selectable.
A write to the high byte of Timer0 must also take place
through the TMR0H buffer register. Timer0 high byte is
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16-bits of Timer0 to be
updated at once.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF TMR0, MOVWF
TMR0, BSF TMR0, x....etc.) will clear the prescaler
count.
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
TABLE 9-1:
Name
16-Bit Mode Timer Reads and
Writes
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 9-2). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16-bits of Timer0 without
having to verify that the read of the high and low byte
were valid due to a rollover between successive reads
of the high and low byte.
Prescaler
Note:
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or FFFFh
to 0000h in 16-bit mode. This overflow sets the TMR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IE bit must be cleared in software by the Timer0 module Interrupt Service Routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from SLEEP, since the
timer is shut-off during SLEEP.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment either on every
rising, or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge
Select bit (T0SE). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are
discussed below.
9.2
SWITCHING PRESCALER ASSIGNMENT
REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
RESETS
TMR0L
Timer0 Module’s Low Byte Register
xxxx xxxx
uuuu uuuu
TMR0H
Timer0 Module’s High Byte Register
0000 0000
0000 0000
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
1111 1111
TRISA
—
—
--11 1111
--11 1111
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
1999-2013 Microchip Technology Inc.
DS39026D-page 95
PIC18CXX2
NOTES:
DS39026D-page 96
1999-2013 Microchip Technology Inc.
PIC18CXX2
10.0
TIMER1 MODULE
Figure 10-1 is a simplified block diagram of the Timer1
module.
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter
(two 8-bit registers: TMR1H and TMR1L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module special event trigger
REGISTER 10-1:
Register 10-1 details the Timer1 control register. This
register controls the operating mode of the Timer1
module, and contains the Timer1 oscillator enable bit
(T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit TMR1ON (T1CON).
T1CON: TIMER1 CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RD16
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register Read/Write of TImer1 in one 16-bit operation
0 = Enables register Read/Write of Timer1 in two 8-bit operations
bit 6
Unimplemented: Read as '0'
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 Oscillator is enabled
0 = Timer1 Oscillator is shut-off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
1999-2013 Microchip Technology Inc.
x = Bit is unknown
DS39026D-page 97
PIC18CXX2
10.1
Timer1 Operation
When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC value is
ignored.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON).
Timer1 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 13.0).
FIGURE 10-1:
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag bit
TMR1
TMR1H
Synchronized
Clock Input
0
CLR
TMR1L
1
TMR1ON
On/Off
T1SYNC
T1OSC
T1CKI/T1OSO
T1OSCEN
Enable
Oscillator(1)
T1OSI
1
FOSC/4
Internal
Clock
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
T1CKPS1:T1CKPS0
SLEEP Input
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 10-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus
8
TMR1H
8
8
Write TMR1L
CCP Special Event Trigger
Read TMR1L
TMR1IF
Overflow
Interrupt
Flag bit
TMR1
8
Timer 1
High Byte
TMR1L
1
TMR1ON
On/Off
T1OSC
T13CKI/T1OSO
T1OSI
Synchronized
Clock Input
0
CLR
T1SYNC
1
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
SLEEP Input
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39026D-page 98
1999-2013 Microchip Technology Inc.
PIC18CXX2
10.2
Timer1 Oscillator
10.4
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON). The oscillator is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 10-1 shows the capacitor
selection for the Timer1 oscillator.
If the CCP module is configured in compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Note:
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
TABLE 10-1:
CAPACITOR SELECTION FOR
THE ALTERNATE
OSCILLATOR
Osc Type
Freq.
C1
C2
LP
32 kHz
TBD(1)
TBD(1)
Crystal to be Tested:
32.768 kHz
Epson C-001R32.768K-A
20
PPM
Note 1: Microchip suggests 33 pF as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design guidance
only.
10.3
Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit TMR1IF (PIR1).
This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1).
1999-2013 Microchip Technology Inc.
Resetting Timer1 using a CCP
Trigger Output
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1).
Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence.
In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for
Timer1.
10.5
Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 10-2). When the RD16 control bit
(T1CON) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16-bits of
Timer1, without having to determine whether a read of
the high byte, followed by a read of the low byte, is
valid, due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
TMR1H is updated from the high byte when TMR1L is
read.
The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place
through the Timer1 high byte buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L.
DS39026D-page 99
PIC18CXX2
TABLE 10-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
INTCON
GIE/GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0000 0000
0000 0000
uuuu uuuu
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
--00 0000
--uu uuuu
T1CON
RD16
—
T1CKPS1
T1CKPS0 T1OSCEN
T1SYNC
TMR1CS
TMR1ON
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
DS39026D-page 100
1999-2013 Microchip Technology Inc.
PIC18CXX2
11.0
TIMER2 MODULE
11.1
The Timer2 module timer has the following features:
•
•
•
•
•
•
•
8-bit timer (TMR2 register)
8-bit period register (PR2)
Readable and writable (both registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Interrupt on TMR2 match of PR2
SSP module optional use of TMR2 output to generate clock shift
Timer2 has a control register shown in Register 11-1.
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON) to minimize power consumption.
Figure 11-1 is a simplified block diagram of the Timer2
module. Register 11-1 shows the Timer2 control register. The prescaler and postscaler selection of Timer2
are controlled by this register.
REGISTER 11-1:
Timer2 Operation
Timer2 can be used as the PWM time-base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
RESET. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4, or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON). The match output of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit TMR2IF, (PIR1)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset)
TMR2 is not cleared when T2CON is written.
T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
TOUTPS3 TOUTPS2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
1999-2013 Microchip Technology Inc.
x = Bit is unknown
DS39026D-page 101
PIC18CXX2
11.2
Timer2 Interrupt
11.3
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
FIGURE 11-1:
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module, which optionally uses
it to generate the shift clock.
TIMER2 BLOCK DIAGRAM
Sets Flag
bit TMR2IF
TMR2
Output(1)
Prescaler
FOSC/4
TMR2
1:1, 1:4, 1:16
2
RESET
Postscaler
Comparator
EQ
1:1 to 1:16
T2CKPS1:T2CKPS0
4
PR2
TOUTPS3:TOUTPS0
Note 1:
TABLE 11-1:
Name
TMR2 register output can be software selected by the SSP Module as a baud clock.
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Value on
all other
RESETS
Bit 0
Value on
POR, BOR
0000 000x 0000 000u
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0000 0000 0000 0000
INTCON GIE/GIEH PEIE/GIEL
TMR2
T2CON
PR2
Timer2 Module Register
—
0000 0000 0000 0000
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register
1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
DS39026D-page 102
1999-2013 Microchip Technology Inc.
PIC18CXX2
12.0
TIMER3 MODULE
Figure 12-1 is a simplified block diagram of the Timer3
module.
The Timer3 module timer/counter has the following
features:
• 16-bit timer/counter
(two 8-bit registers: TMR3H and TMR3L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module trigger
REGISTER 12-1:
Register 12-1 shows the Timer3 control register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
Register 10-1 shows the Timer1 control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 oscillator
enable bit (T1OSCEN), which can be a clock source for
Timer3.
T3CON: TIMER3 CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
bit 7
bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable
1 = Enables register Read/Write of Timer3 in one 16-bit operation
0 = Enables register Read/Write of Timer3 in two 8-bit operations
bit 6-3
T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the clock source for compare/capture CCP modules
01 = Timer3 is the clock source for compare/capture of CCP2,
Timer1 is the clock source for compare/capture of CCP1
00 = Timer1 is the clock source for compare/capture CCP modules
bit 5-4
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 2
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T1CKI
(on the rising edge after the first falling edge)
0 = Internal clock (FOSC/4)
bit 0
TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
1999-2013 Microchip Technology Inc.
x = Bit is unknown
DS39026D-page 103
PIC18CXX2
12.1
Timer3 Operation
When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC value is
ignored.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON).
Timer3 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 12.0).
FIGURE 12-1:
TIMER3 BLOCK DIAGRAM
CCP Special Trigger
T3CCPx
TMR3IF
Overflow
Interrupt
Flag bit
TMR3H
Synchronized
Clock Input
0
CLR
TMR3L
1
TMR3ON
On/Off
T1OSC
T1OSO/
T13CKI
T3SYNC
(3)
1
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
T1OSI
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
TMR3CS
T3CKPS1:T3CKPS0
SLEEP Input
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus
8
TMR3H
8
8
Write TMR3L
Read TMR3L
Set TMR3IF Flag bit
on Overflow
8
CCP Special Trigger
T3CCPx
0
TMR3
Timer3
High Byte
TMR3L
CLR
Synchronized
Clock Input
1
To Timer1 Clock Input
T1OSO/
T13CKI
T1OSI
TMR3ON
On/Off
T1OSC
T3SYNC
1
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
T3CKPS1:T3CKPS0
TMR3CS
SLEEP Input
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39026D-page 104
1999-2013 Microchip Technology Inc.
PIC18CXX2
12.2
Timer1 Oscillator
12.4
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON) bit. The oscillator is a low
power oscillator rated up to 200 KHz. See Section 10.0
for further details.
12.3
If the CCP module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer3.
Note:
Timer3 Interrupt
The TMR3 Register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR3IF (PIR2).
This interrupt can be enabled/disabled by setting/clearing TMR3 interrupt enable bit, TMR3IE (PIE2).
TABLE 12-1:
Resetting Timer3 Using a CCP
Trigger Output
The special event triggers from the CCP
module will not set interrupt flag bit
TMR3IF (PIR1).
Timer3 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this RESET operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from CCP1, the write will take precedence. In this mode
of operation, the CCPR1H:CCPR1L registers pair
effectively becomes the period register for Timer3.
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR2
—
—
—
—
BCLIF
LVDIF
TMR3IF
CCP2IF
0000 0000 0000 0000
PIE2
—
—
—
—
BCLIE
LVDIE
TMR3IE
CCP2IE
0000 0000 0000 0000
IPR2
—
—
—
—
BCLIP
LVDIP
TMR3IP
CCP2IP
0000 0000 0000 0000
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
T1CON
RD16
—
T3CON
RD16
T3CCP2
Legend:
T1CKPS1 T1CKPS0 T1OSCEN
T1SYNC
TMR1CS TMR1ON --00 0000 --uu uuuu
T3CKPS1 T3CKPS0
T3SYNC
TMR3CS TMR3ON -000 0000 -uuu uuuu
T3CCP1
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
1999-2013 Microchip Technology Inc.
DS39026D-page 105
PIC18CXX2
NOTES:
DS39026D-page 106
1999-2013 Microchip Technology Inc.
PIC18CXX2
13.0
CAPTURE/COMPARE/PWM
(CCP) MODULES
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register, or as a PWM
master/slave Duty Cycle register. Table 13-1 shows the
timer resources of the CCP module modes.
REGISTER 13-1:
The operation of CCP1 is identical to that of CCP2, with
the exception of the special event trigger. Therefore,
operation of a CCP module in the following sections is
described with respect to CCP1.
Table 13-2 shows the interaction of the CCP modules.
CCP1CON REGISTER/CCP2CON REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5-4
DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode,
Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set)
1001 = Compare mode,
Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set)
1010 = Compare mode,
Generate software interrupt on compare match (CCPIF bit is set, CCP pin is
unaffected)
1011 = Compare mode,
Trigger special event (CCPIF bit is set)
11xx = PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
1999-2013 Microchip Technology Inc.
x = Bit is unknown
DS39026D-page 107
PIC18CXX2
13.1
CCP1 Module
13.2
Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
TABLE 13-1:
Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
TABLE 13-2:
CCP2 Module
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
TMR1 or TMR3 time-base. Time-base can be different for each CCP.
Capture
Compare
The compare could be configured for the special event trigger,
which clears either TMR1, or TMR3, depending upon which time-base is used.
Compare
Compare
The compare(s) could be configured for the special event trigger,
which clears TMR1, or TMR3, depending upon which time-base is used.
PWM
PWM
PWM
Capture
None.
PWM
Compare
None.
DS39026D-page 108
The PWMs will have the same frequency and update rate (TMR2 interrupt).
1999-2013 Microchip Technology Inc.
PIC18CXX2
13.3
13.3.3
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 or TMR3 registers when an
event occurs on pin RC2/CCP1. An event is defined as:
•
•
•
•
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
13.3.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC bit.
Note:
13.3.2
If the RC2/CCP1 is configured as an output, a write to the port can cause a capture
condition.
TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(either Timer1 and/or Timer3) must be running in Timer
mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not
work. The timer to be used with each CCP module is
selected in the T3CON register.
FIGURE 13-1:
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.
13.3.4
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON). When a capture is made, the interrupt request flag bit CCP1IF (PIR1) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
SOFTWARE INTERRUPT
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 13-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 13-1:
CLRF
MOVLW
MOVWF
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON, F ; Turn CCP module off
NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
CCP1CON
; Load CCP1CON with
; this value
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3L
Set Flag bit CCP1IF
T3CCP2
Prescaler
1, 4, 16
CCP1 pin
TMR3
Enable
CCPR1H
and
Edge Detect
T3CCP2
CCPR1L
TMR1
Enable
TMR1H
TMR1L
TMR3H
TMR3L
CCP1CON
Q’s
Set Flag bit CCP2IF
T3CCP1
T3CCP2
TMR3
Enable
Prescaler
1, 4, 16
CCP2 pin
CCPR2H
and
Edge Detect
CCPR2L
TMR1
Enable
T3CCP2
T3CCP1
TMR1H
TMR1L
CCP2CON
Q’s
1999-2013 Microchip Technology Inc.
DS39026D-page 109
PIC18CXX2
13.4
13.4.2
Compare Mode
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against either the TMR1
register pair value or the TMR3 register pair value.
When a match occurs, the RC2/CCP1 (RC1/CCP2) pin
is:
•
•
•
•
TIMER1/TIMER3 MODE SELECTION
13.4.3
driven High
driven Low
toggle output (High to Low or Low to High)
remains unchanged
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit, CCP1IF (CCP2IF) is set.
13.4.4
13.4.1
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
Note:
SPECIAL EVENT TRIGGER
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
The special trigger output of CCPx resets either the
TMR1 or TMR3 register pair. Additionally, the CCP2
Special Event Trigger will start an A/D conversion if the
A/D module is enabled.
Note:
FIGURE 13-2:
The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will:
Reset Timer1or Timer3, but not set Timer1 or Timer3 Interrupt Flag bit,
and set bit GO/DONE (ADCON0)
which starts an A/D Conversion (CCP2 only)
Special Event Trigger
Set Flag bit CCP1IF
CCPR1H CCPR1L
Q
RC2/CCP1
pin
TRISC
Output Enable
S
R
Output
Logic
Comparator
Match
CCP1CON
Mode Select
0
T3CCP2
TMR1H
1
TMR1L
TMR3H
TMR3L
Special Event Trigger
Set Flag bit CCP2IF
Q
RC1/CCP2
pin
TRISC
Output Enable
DS39026D-page 110
S
R
Output
Logic
Match
T3CCP1
T3CCP2
0
1
Comparator
CCPR2H CCPR2L
CCP2CON
Mode Select
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 13-3:
Name
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Value on
POR,
BOR
Value on
all other
RESETS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0000 0000 0000 0000
0000 000x 0000 000u
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
T1CON
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCPR1L
Capture/Compare/PWM Register1 (LSB)
CCPR1H
Capture/Compare/PWM Register1 (MSB)
CCP1CON
—
—
DC1B1
DC1B0
CCPR2L
Capture/Compare/PWM Register2 (LSB)
CCPR2H
Capture/Compare/PWM Register2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2CON
—
—
DC2B1
DC2B0
PIR2
—
—
—
—
BCLIF
LVDIF
TMR3IF
CCP2IF
0000 0000 0000 0000
PIE2
—
—
—
—
BCLIE
LVDIE
TMR3IE
CCP2IE
0000 0000 0000 0000
—
—
—
—
BCLIP
LVDIP
TMR3IP
CCP2IP
0000 0000 0000 0000
IPR2
CCP2M3
CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
T3CON
RD16
T3CCP2
T3CKPS1 T3CKPS0
T3CCP1
T3SYNC TMR3CS TMR3ON -000 0000 -uuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
1999-2013 Microchip Technology Inc.
DS39026D-page 111
PIC18CXX2
13.5
13.5.1
PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Figure 13-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 13.5.3.
FIGURE 13-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty Cycle Registers
PWM PERIOD
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula:
PWM period = (PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
CCP1CON
The Timer2 postscaler (see Section 11.0)
is not used in the determination of the
PWM frequency. The postscaler could be
used to have a servo update rate at a different frequency than the PWM output.
CCPR1L
13.5.2
CCPR1H (Slave)
R
Comparator
Q
RC2/CCP1
(Note 1)
TMR2
S
PWM duty cycle
Clear Timer,
CCP1 pin and
latch D.C.
PR2
Note:
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON. The following equation is
used to calculate the PWM duty cycle in time:
TRISC
Comparator
8-bit timer is concatenated with 2-bit internal Q clock or
2 bits of the prescaler to create 10-bit time-base.
A PWM output (Figure 13-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 13-4:
PWM DUTY CYCLE
PWM OUTPUT
= (CCPR1L:CCP1CON) •
TOSC • (TMR2 prescale value)
CCPR1L and CCP1CON can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
Period
F OSC
log ---------------
F PWM
PWM Resolution (max) = -----------------------------bits
log 2
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
DS39026D-page 112
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
1999-2013 Microchip Technology Inc.
PIC18CXX2
13.5.3
SETUP FOR PWM OPERATION
3.
The following steps should be taken when configuring
the CCP module for PWM operation:
4.
1.
5.
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON bits.
2.
TABLE 13-4:
Make the CCP1 pin an output by clearing the
TRISC bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz
156.25 kHz
312.50 kHz
416.67 kHz
Timer Prescaler (1, 4, 16)
16
4
1
1
1
1
PR2 Value
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
Maximum Resolution (bits)
14
12
10
8
7
6.58
TABLE 13-5:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0000 0000 0000 0000
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
TMR2
Timer2 Module Register
0000 0000 0000 0000
PR2
Timer2 Module Period Register
1111 1111 1111 1111
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L
Capture/Compare/PWM Register1 (LSB)
CCPR1H
Capture/Compare/PWM Register1 (MSB)
CCP1CON
—
—
DC1B1
DC1B0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3
CCP1M2
CCP1M1
CCP1M0 --00 0000 --00 0000
CCPR2L
Capture/Compare/PWM Register2 (LSB)
xxxx xxxx uuuu uuuu
CCPR2H
Capture/Compare/PWM Register2 (MSB)
xxxx xxxx uuuu uuuu
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
1999-2013 Microchip Technology Inc.
DS39026D-page 113
PIC18CXX2
NOTES:
DS39026D-page 114
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
14.1
Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPITM)
• Inter-Integrated Circuit (I2CTM)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode
1999-2013 Microchip Technology Inc.
DS39026D-page 115
PIC18CXX2
14.2
Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2).
REGISTER 14-1:
SSPSTAT: MSSP STATUS REGISTER
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select bit
CKP = 0:
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1:
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: STOP bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a STOP bit has been detected last (this bit is '0' on RESET)
0 = STOP bit was not detected last
Legend:
DS39026D-page 116
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
1999-2013 Microchip Technology Inc.
PIC18CXX2
REGISTER 14-1:
SSPSTAT: MSSP STATUS REGISTER (CONTINUED)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
bit 3
S: START bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a START bit has been detected last (this bit is '0' on RESET)
0 = START bit was not detected last
bit 2
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from
the address match to the next START bit, STOP bit, or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in
IDLE mode.
bit 1
UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
1999-2013 Microchip Technology Inc.
x = Bit is unknown
DS39026D-page 117
PIC18CXX2
REGISTER 14-2:
SSPCON1: MSSP CONTROL REGISTER1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
Master mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started
0 = No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.
In Slave mode, the user must read the SSPBUF, even if only transmitting data to avoid
setting overflow.
In Master mode, the overflow bit is not set, since each new reception (and transmission) is
initiated by writing to the SSPBUF register (must be cleared in software).
0 = No overflow
In I2 C mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a
“don’t care” in Transmit mode (must be cleared in software).
0 = No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes when enabled, these pins must be properly configured as input or output.
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial
port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the
serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Legend:
DS39026D-page 118
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
1999-2013 Microchip Technology Inc.
PIC18CXX2
REGISTER 14-2:
SSPCON1: MSSP CONTROL REGISTER1 (CONTINUED)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2 C Slave mode:
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2 C Master mode:
Unused in this mode
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))
1001 = Reserved
1010 = Reserved
1011 = I2C firmware controlled Master mode (Slave idle)
1100 = Reserved
1101 = Reserved
1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled
1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
1999-2013 Microchip Technology Inc.
x = Bit is unknown
DS39026D-page 119
PIC18CXX2
REGISTER 14-3:
SSPCON2: MSSP CONTROL REGISTER2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
bit 7
GCEN: General Call Enable bit (In I2C Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (In I2C Master mode only)
In Master Transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (In I2C Master mode only)
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
1 = Not Acknowledge
0 = Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3
RCEN: Receive Enable bit (In I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2
PEN: STOP Condition Enable bit (In I2C Master mode only)
SCK Release Control:
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition idle
bit 1
RSEN: Repeated START Condition Enabled bit (In I2C Master mode only)
1 = Initiate Repeated START condition on SDA and SCL pins.
Automatically cleared by hardware.
0 = Repeated START condition idle
bit 0
SEN: START Condition Enabled bit (In I2C Master mode only)
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition idle
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
Legend:
DS39026D-page 120
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.3
SPI Mode
FIGURE 14-1:
The SPI mode allows 8-bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish communication, typically three pins are used:
MSSP BLOCK DIAGRAM
(SPI MODE)
Internal
Data Bus
Read
• Serial Data Out (SDO) - RC5/SDO
• Serial Data In (SDI) - RC4/SDI/SDA
• Serial Clock (SCK) - RC3/SCK/SCL/LVOIN
Write
SSPBUF reg
Additionally, a fourth pin may be used when in a Slave
mode of operation:
SSPSR reg
• Slave Select (SS) - RA5/SS/AN4
SDI
14.3.1
SDO
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1) and SSPSTAT.
These control bits allow the following to be specified:
•
•
•
•
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data input sample phase (middle or end of data
output time)
• Clock edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Figure 14-1 shows the block diagram of the MSSP
module, when in SPI mode.
Shift
Clock
bit0
SS Control
Enable
SS
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE 4
2
Edge
Select
SCK
(TMR22output )
Prescaler TOSC
4, 16, 64
Data to TX/RX in SSPSR
TRIS bit
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register. Then the buffer full detect bit, BF
(SSPSTAT), and the interrupt flag bit, SSPIF, are
set. This double buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit, WCOL
(SSPCON1), will be set. User software must clear
the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed
successfully.
1999-2013 Microchip Technology Inc.
DS39026D-page 121
PIC18CXX2
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
EXAMPLE 14-1:
transmitter. Generally the MSSP Interrupt is used to
determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 14-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF
GOTO LOOP
MOVF SSPBUF, W
;Has data been received(transmit complete)?
;No
;WREG reg = contents of SSPBUF
MOVWF RXDATA
;Save in user RAM, if data is meaningful
MOVF TXDATA, W
MOVWF SSPBUF
;W reg = contents of TXDATA
;New data to xmit
The SSPSR is not directly readable or writable, and
can only be accessed by addressing the SSPBUF register. Additionally, the MSSP status register (SSPSTAT)
indicates the various status conditions.
14.3.2
ENABLING SPI I/O
To enable the serial port, SSP enable bit, SSPEN
(SSPCON1), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers, and then set the SSPEN bit. This
configures the SDI, SDO, SCK, and SS pins as serial
DS39026D-page 122
port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the
TRIS register) appropriately programmed. That is:
•
•
•
•
•
SDI is automatically controlled by the SPI module
SDO must have TRISC bit cleared
SCK (Master mode) must have TRISC bit cleared
SCK (Slave mode) must have TRISC bit set
SS must have TRISC bit set
Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value.
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.3.3
TYPICAL CONNECTION
Figure 14-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite
edge of the clock. Both processors should be programmed to same Clock Polarity (CKP), then both con-
FIGURE 14-2:
trollers would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data—Slave sends dummy data
• Master sends data—Slave sends data
• Master sends dummy data—Slave sends data
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
SDI
Shift Register
(SSPSR)
MSb
Serial Input Buffer
(SSPBUF)
LSb
1999-2013 Microchip Technology Inc.
Shift Register
(SSPSR)
MSb
SCK
PROCESSOR 1
SDO
Serial Clock
LSb
SCK
PROCESSOR 2
DS39026D-page 123
PIC18CXX2
14.3.4
MASTER MODE
Figure 14-3, Figure 14-5, and Figure 14-6, where the
MSB is transmitted first. In Master mode, the SPI clock
rate (bit rate) is user programmable to be one of the
following:
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 14-2) is to broadcast data by the software protocol.
•
•
•
•
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
This allows a maximum data rate (at 40 MHz) of 10.00
Mbps.
Figure 14-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
The clock polarity is selected by appropriately programming the CKP bit (SSPCON1). This then, would
give waveforms for SPI communication as shown in
FIGURE 14-3:
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
Timer2 output/2
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDO
(CKE = 1)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit7
bit0
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
DS39026D-page 124
Next Q4 cycle
after Q2
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.3.5
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating
output. External pull-up/pull-down resistors may be
desirable, depending on the application.
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
14.3.6
When the SPI module resets, the bit counter is forced
to 0. This can be done by either forcing the SS pin to a
high level, or clearing the SSPEN bit.
SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control
enabled (SSPCON1 = 04h). The pin must not
be driven low for the SS pin to function as an input.
The Data Latch must be high. When the SS pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
FIGURE 14-4:
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function),
since it cannot create a bus conflict.
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit7
bit6
bit7
bit0
bit0
bit7
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
1999-2013 Microchip Technology Inc.
Next Q4 cycle
after Q2
DS39026D-page 125
PIC18CXX2
FIGURE 14-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
FIGURE 14-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
not optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit7
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
DS39026D-page 126
Next Q4 cycle
after Q2
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.3.7
SLEEP OPERATION
14.3.9
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to transmit/
receive data.
Table 14-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE
control bits.
TABLE 14-1:
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode, and data to be
shifted into the SPI transmit/receive shift register.
When all 8-bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the
device from SLEEP.
14.3.8
0,
0,
1,
1,
Control Bits State
0
1
0
1
CKP
CKE
0
0
1
1
1
0
1
0
There is also a SMP bit which controls when the data is
sampled.
A RESET disables the MSSP module and terminates
the current transfer.
Name
SPI BUS MODES
Standard SPI Mode
Terminology
EFFECTS OF A RESET
TABLE 14-2:
BUS MODE COMPATIBILITY
REGISTERS ASSOCIATED WITH SPI OPERATION
Value on
POR,
BOR
Value on
all other
RESETS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF (1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE (1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP (1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0000 0000 0000 0000
TRISC
PORTC Data Direction Register
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON
TRISA
SSPSTAT
WCOL
—
SMP
SSPOV
SSPEN
1111 1111 1111 1111
CKP
SSPM3
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
SSPM0
PORTA Data Direction Register
CKE
D/A
0000 000x 0000 000u
P
0000 0000 0000 0000
--11 1111 --11 1111
S
R/W
UA
BF
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
1999-2013 Microchip Technology Inc.
DS39026D-page 127
PIC18CXX2
14.4
MSSP I2C Operation
The MSSP module in I 2C mode, fully implements all
master and slave functions (including general call support) and provides interrupts on START and STOP bits
in hardware to determine a free bus (multi-master function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC bits.
The MSSP module functions are enabled by setting
MSSP enable bit SSPEN (SSPCON).
FIGURE 14-7:
MSSP BLOCK DIAGRAM
(I2C MODE)
Internal
Data Bus
Read
Write
Shift
Clock
SSPSR reg
RC4/
SDI/
SDA
MSb
Addr Match
14.4.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
START and
STOP bit Detect
a)
b)
SSPADD reg
Set, Reset
S, P bits
(SSPSTAT reg)
The MSSP module has six registers for I2C operation.
These are the:
MSSP Control Register1 (SSPCON1)
MSSP Control Register2 (SSPCON2)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
MSSP Shift Register (SSPSR) - Not directly
accessible
• MSSP Address Register (SSPADD)
DS39026D-page 128
Selection of any I 2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, provided these pins are programmed to be inputs by setting the appropriate TRISC bits.
There are certain conditions that will cause the MSSP
module not to give this ACK pulse. These are if either
(or both):
LSb
Match Detect
•
•
•
•
•
I2C Master mode, clock = OSC/4 (SSPADD +1)
I 2C Slave mode (7-bit address)
I 2C Slave mode (10-bit address)
I 2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled
• I 2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled
• I 2C Firmware controlled master operation, slave
is idle
•
•
•
•
When an address is matched or the data transfer after
an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value currently in the SSPSR register.
SSPBUF reg
RC3/SCK/SCL
The SSPCON1 register allows control of the I 2C operation. Four mode selection bits (SSPCON) allow
one of the following I 2C modes to be selected:
The buffer full bit BF (SSPSTAT) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.4.1.1
Addressing
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
The SSPSR register value is loaded into the
SSPBUF register.
The buffer full bit BF is set.
An ACK pulse is generated.
MSSP interrupt flag bit SSPIF (PIR1) is set
(interrupt is generated if enabled) on the falling
edge of the ninth SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘1111 0
A9 A8 0’, where A9 and A8 are the two MSbs of the
address. The sequence of events for 10-bit address is
as follows, with steps 7-9 for slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Receive first (high) byte of Address (bits SSPIF,
BF and bit UA (SSPSTAT) are set).
Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
Update the SSPADD register with the first (high)
byte of Address. If match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive Repeated START condition.
Receive first (high) byte of Address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
1999-2013 Microchip Technology Inc.
14.4.1.2
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT) is
set, or bit SSPOV (SSPCON) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1) must be cleared in software. The SSPSTAT register is used to determine the
status of the byte.
14.4.1.3
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON). The master must monitor
the SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 14-9).
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the
master-receiver is latched on the rising edge of the
ninth SCL input pulse. If the SDA line is high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset (resets
SSPSTAT register) and the slave monitors for another
occurrence of the START bit. If the SDA line was low
(ACK), the transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR register. Pin RC3/SCK/SCL should be enabled by setting bit
CKP.
DS39026D-page 129
PIC18CXX2
I 2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 14-8:
Receiving Address
Receiving Data
R/W=0
Receiving Data
Not ACK
ACK
ACK
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
1
S
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SSPIF
P
Bus Master
terminates
transfer
BF (SSPSTAT)
Cleared in software
SSPBUF register is read
SSPOV (SSPCON1)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
I 2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
FIGURE 14-9:
Receiving Address
A7
SDA
SCL
S
A6
1
2
Data in
sampled
R/W = 1
A5
A4
A3
A2
A1
3
4
5
6
7
ACK
8
9
R/W = 0
Not ACK
Transmitting Data
D7
1
SCL held low
while CPU
responds to SSPIF
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
P
SSPIF
BF (SSPSTAT)
Cleared in software
SSPBUF is written in software
From SSP Interrupt
Service Routine
CKP (SSPCON1)
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
DS39026D-page 130
1999-2013 Microchip Technology Inc.
1999-2013 Microchip Technology Inc.
2
UA (SSPSTAT)
BF (SSPSTAT)
(PIR1)
SSPIF
1
S
SCL
1
4
1
5
0
6
7
A9 A8
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
3
1
8
9
ACK
Receive First Byte of Address R/W = 0
1
1
3
4
5
Cleared in software
2
7
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated.
6
A6 A5 A4 A3 A2 A1
8
A0
Receive Second Byte of Address
Dummy read of SSPBUF
to clear BF flag
A7
9
ACK
2
3
1
4
1
Cleared in software
1
1
Cleared by hardware when
SSPADD is updated.
Dummy read of SSPBUF
to clear BF flag
Sr
1
5
0
6
7
A9 A8
Receive First Byte of Address
8
9
R/W=1
ACK
1
3
4
5
6
7
8
9
ACK
P
Write of SSPBUF
initiates transmit
Cleared in software
Bus Master
terminates
transfer
CKP has to be set for clock to be released
2
D4 D3 D2 D1 D0
Transmitting Data Byte
D7 D6 D5
Master sends NACK
Transmit is complete
FIGURE 14-10:
SDA
Clock is held low until
update of SSPADD has
taken place
PIC18CXX2
I2C SLAVE MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS)
DS39026D-page 131
DS39026D-page 132
UA (SSPSTAT)
BF (SSPSTAT)
(PIR1)
SSPIF
1
SCL
S
1
2
1
3
1
5
0
6
A9
7
A8
8
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
4
1
9
ACK
R/W = 0
1
2
3
A5
4
A4
Cleared in software
A6
5
A3
6
A2
7
A1
8
A0
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with
low byte of address.
Dummy read of SSPBUF
to clear BF flag
A7
Receive Second Byte of Address
9
ACK
3
D5
4
D4
5
D3
Cleared in software
2
D6
Cleared by hardware when
SSPADD is updated with
high byte of address.
Dummy read of SSPBUF
to clear BF flag
1
D7
Receive Data Byte
6
D2
7
D1
8
D0
9
ACK
R/W = 1
Read of SSPBUF
clears BF flag
P
Bus Master
terminates
transfer
FIGURE 14-11:
SDA
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
PIC18CXX2
I2C SLAVE MODE WAVEFORM (RECEPTION 10-BIT ADDRESS)
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.4.2
GENERAL CALL ADDRESS
SUPPORT
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit),
the SSPIF interrupt flag bit is set.
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually determines which device will be the slave addressed by the
master. The exception is the general call address which
can address all devices. When this address is used, all
devices should, in theory, respond with an acknowledge.
When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit address mode, then the second
half of the address is not necessary, the UA bit will not
be set, and the slave will begin receiving data after the
Acknowledge (Figure 14-12).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0.
The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2
is set). Following a START bit detect, 8-bits are shifted
into the SSPSR and the address is compared against
the SSPADD. It is also compared to the general call
address and fixed in hardware.
FIGURE 14-12:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
Address is compared to General Call Address
after ACK, set interrupt
R/W = 0
ACK D7
General Call Address
SDA
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
SCL
S
1
2
3
4
5
6
7
8
9
1
9
SSPIF
BF (SSPSTAT)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1)
'0'
GCEN (SSPCON2)
'1'
14.4.3
MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET or when the MSSP module is
disabled. Control of the I 2C bus may be taken when the
P bit is set, or the bus is idle, with both the S and P bits
clear.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt, if enabled):
•
•
•
•
•
START condition
STOP condition
Data transfer byte transmitted/received
Acknowledge Transmit
Repeated START
In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware.
1999-2013 Microchip Technology Inc.
DS39026D-page 133
PIC18CXX2
I2C MASTER MODE SUPPORT
Note:
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. Once Master mode is enabled, the user
has six options.
1.
2.
3.
4.
5.
6.
Assert a START condition on SDA and SCL.
Assert a Repeated START condition on SDA
and SCL.
Write to the SSPBUF register initiating transmission of data/address.
Generate a STOP condition on SDA and SCL.
Configure the I2C port to receive data.
Generate an Acknowledge condition at the end
of a received byte of data.
FIGURE 14-13:
The MSSP module, when configured in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
imitate transmission, before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
MSSP BLOCK DIAGRAM (I2C MASTER MODE)
SSPM3:SSPM0
SSPADD
Internal
Data Bus
Read
Write
SSPBUF
Baud
Rate
Generator
Shift
Clock
SDA
SDA in
SCL in
Bus Collision
DS39026D-page 134
MSb
LSb
START bit, STOP bit,
Acknowledge
Generate
START bit Detect
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
Clock Cntl
SCL
Receive Enable
SSPSR
Clock Arbitrate/WCOL Detect
(hold off clock source)
14.4.4
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.4.4.1
I2C Master Mode Operation
A typical transmit sequence would go as follows:
The master device generates all of the serial clock
pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a Repeated
START condition. Since the Repeated START condition is also the beginning of the next serial transfer, the
I2C bus will not be released.
a)
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic '0'. Serial data is
transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the
end of a serial transfer.
c)
In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic '1'. Thus, the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an Acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
The baud rate generator used for the SPI mode operation is now used to set the SCL clock frequency for
either 100 kHz, 400 kHz, or 1 MHz I2C operation. The
baud rate generator reload value is contained in the
lower 7 bits of the SSPADD register. The baud rate
generator will automatically begin counting on a write to
the SSPBUF. Once the given operation is complete,
(i.e., transmission of the last data bit is followed by
ACK), the internal clock will automatically stop counting
and the SCL pin will remain in its last state.
1999-2013 Microchip Technology Inc.
b)
d)
e)
f)
g)
h)
i)
j)
k)
l)
The user generates a START condition by setting
the
START
enable
bit,
SEN
(SSPCON2).
SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
The user loads the SSPBUF with the address to
transmit.
Address is shifted out the SDA pin until all 8 bits
are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The user loads the SSPBUF with eight bits of
data.
Data is shifted out the SDA pin until all 8 bits are
transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The user generates a STOP condition by setting
the STOP enable bit, PEN (SSPCON2).
Interrupt is generated once the STOP condition
is complete.
DS39026D-page 135
PIC18CXX2
14.4.5
BAUD RATE GENERATOR
remented twice per instruction cycle (TCY) on the Q2
and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically. If Clock Arbitration is taking
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 14-15).
In I2C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 14-14). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is dec-
FIGURE 14-14:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPM3:SSPM0
Reload
SCL
Control
SSPADD
Reload
CLKOUT
FIGURE 14-15:
BRG Down Counter
FOSC/4
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL de-asserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count.
BRG
Reload
DS39026D-page 136
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.4.6
I2C MASTER MODE START
CONDITION TIMING
14.4.6.1
If the user writes the SSPBUF when a START
sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t
occur).
To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2). If the SDA
and SCL pins are sampled high, the baud rate generator is reloaded with the contents of SSPADD and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the START condition
and causes the S bit (SSPSTAT) to be set. Following this, the baud rate generator is reloaded with the
contents of SSPADD and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2) will be automatically cleared
by hardware, the baud rate generator is suspended
leaving the SDA line held low and the START condition
is complete.
Note:
WCOL Status Flag
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
If, at the beginning of the START condition,
the SDA and SCL pins are already sampled low, or if during the START condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF is set, the START condition is
aborted, and the I2C module is reset into its
IDLE state.
FIGURE 14-16:
FIRST START BIT TIMING
Set S bit (SSPSTAT)
Write to SEN bit occurs here.
SDA = 1,
SCL = 1
TBRG
At completion of START bit,
Hardware clears SEN bit
and sets SSPIF bit
TBRG
Write to SSPBUF occurs here
1st Bit
SDA
2nd Bit
TBRG
SCL
TBRG
S
1999-2013 Microchip Technology Inc.
DS39026D-page 137
PIC18CXX2
14.4.7
I2C MASTER MODE REPEATED
START CONDITION TIMING
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode), or eight bits of data (7-bit
mode).
A Repeated START condition occurs when the RSEN
bit (SSPCON2) is programmed high and the I2C
logic module is in the idle state. When the RSEN bit is
set, the SCL pin is asserted low. When the SCL pin is
sampled low, the baud rate generator is loaded with the
contents of SSPADD and begins counting. The
SDA pin is released (brought high) for one baud rate
generator count (TBRG). When the baud rate generator
times out, if SDA is sampled high, the SCL pin will be
de-asserted (brought high). When SCL is sampled
high, the baud rate generator is reloaded with the contents of SSPADD and begins counting. SDA and
SCL must be sampled high for one TBRG. This action is
then followed by assertion of the SDA pin (SDA = 0) for
one TBRG, while SCL is high. Following this, the RSEN
bit (SSPCON2) will be automatically cleared and
the baud rate generator will not be reloaded, leaving
the SDA pin held low. As soon as a START condition is
detected on the SDA and SCL pins, the S bit
(SSPSTAT) will be set. The SSPIF bit will not be set
until the baud rate generator has timed out.
14.4.7.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated
START sequence is in progress, the WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated
START condition occurs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
FIGURE 14-17:
REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT)
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change)
SDA = 1,
SCL = 1
TBRG
TBRG
At completion of START bit,
hardware clear RSEN bit
and set SSPIF
TBRG
1st Bit
SDA
Falling edge of ninth clock
End of Xmit
SCL
Write to SSPBUF occurs here.
TBRG
TBRG
Sr = Repeated START
DS39026D-page 138
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.4.8
I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address, or the
other half of a 10-bit address, is accomplished by simply writing a value to the SSPBUF register. This action
will set the buffer full flag bit, BF, and allow the baud
rate generator to begin counting and start the next
transmission. Each bit of address/data will be shifted
out onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification parameter
106). SCL is held low for one baud rate generator rollover count (TBRG). Data should be valid before SCL is
released high (see Data setup time specification
parameter 107). When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
allowing the slave device being addressed to respond
with an ACK bit during the ninth bit time, if an address
match occurs, or if data was received properly. The status of ACK is written into the ACKDT bit on the falling
edge of the ninth clock. If the master receives an
Acknowledge, the Acknowledge status bit, ACKSTAT,
is cleared. If not, the bit is set. After the ninth clock, the
SSPIF bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into
the SSPBUF, leaving SCL low and SDA unchanged
(Figure 14-18).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will de-assert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2).
Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is
cleared and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
14.4.8.1
BF Status Flag
14.4.8.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2) is
cleared when the slave has sent an Acknowledge
(ACK = 0), and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
14.4.9
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
receive enable bit, RCEN (SSPCON2).
Note:
The MSSP module must be in an IDLE
state before the RCEN bit is set, or the
RCEN bit will be disregarded.
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the baud rate generator is suspended from counting, holding SCL low. The
MSSP is now in IDLE state, awaiting the next command. When the buffer is read by the CPU, the BF flag
bit is automatically cleared. The user can then send an
Acknowledge bit at the end of reception, by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2).
14.4.9.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
14.4.9.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
14.4.9.3
WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
In Transmit mode, the BF bit (SSPSTAT) is set
when the CPU writes to SSPBUF and is cleared, when
all 8 bits are shifted out.
14.4.8.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress, (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
1999-2013 Microchip Technology Inc.
DS39026D-page 139
DS39026D-page 140
S
R/W
PEN
SEN
BF (SSPSTAT)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
3
4
5
cleared in software
2
6
7
8
9
After START condition SEN cleared by hardware.
SSPBUF written
1
D7
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
SSPBUF written with 7 bit address and R/W
start transmit
A7
Transmit Address to Slave
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
SSPBUF is written in software
Cleared in software service routine
From SSP interrupt
2
D6
Transmitting Data or Second Half
of 10-bit Address
From slave clear ACKSTAT bit SSPCON2
P
Cleared in software
9
ACK
ACKSTAT in
SSPCON2 = 1
FIGURE 14-18:
SEN = 0
Write SSPCON2 SEN = 1
START condition begins
PIC18CXX2
I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
1999-2013 Microchip Technology Inc.
1999-2013 Microchip Technology Inc.
S
ACKEN
SSPOV
BF
(SSPSTAT)
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
SCL
SDA
1
A7
2
4
5
Cleared in software
3
6
A6 A5 A4 A3 A2
Transmit Address to Slave
7
A1
8
9
R/W = 1
ACK
ACK from Slave
2
3
5
6
7
8
D0
9
ACK
2
3
4
5
6
7
Cleared in software
Set SSPIF interrupt
at end of Acknowledge
sequence
Data shifted in on falling edge of CLK
1
D7 D6 D5 D4 D3 D2 D1
Cleared in
software
Set SSPIF at end
of receive
9
ACK is not sent
ACK
P
Set SSPIF interrupt
at end of Acknowledge sequence
Bus Master
terminates
transfer
Set P bit
(SSPSTAT)
and SSPIF
PEN bit = 1
written here
SSPOV is set because
SSPBUF is still full
8
D0
RCEN cleared
automatically
Set ACKEN start Acknowledge sequence
SDA = ACKDT = 1
Receiving Data from Slave
RCEN = 1 start
next receive
ACK from Master
SDA = ACKDT = 0
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared in software
Set SSPIF interrupt
at end of receive
4
Cleared in software
1
D7 D6 D5 D4 D3 D2 D1
Receiving Data from Slave
RCEN cleared
automatically
Master configured as a receiver
by programming SSPCON2, (RCEN = 1)
FIGURE 14-19:
SEN = 0
Write to SSPBUF occurs here
Start XMIT
Write to SSPCON2 (SEN = 1)
Begin START Condition
Write to SSPCON2
to start Acknowledge sequence
SDA = ACKDT (SSPCON2) = 0
PIC18CXX2
I 2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
DS39026D-page 141
PIC18CXX2
14.4.10
ACKNOWLEDGE SEQUENCE
TIMING
14.4.11
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the STOP sequence enable
bit, PEN (SSPCON2). At the end of a receive/transmit, the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low. When the SDA line is sampled
low, the baud rate generator is reloaded and counts
down to 0. When the baud rate generator times out, the
SCL pin will be brought high, and one TBRG (baud rate
generator rollover count) later, the SDA pin will be
de-asserted. When the SDA pin is sampled high while
SCL is high, the P bit (SSPSTAT) is set. A TBRG
later, the PEN bit is cleared and the SSPIF bit is set
(Figure 14-21).
An Acknowledge sequence is enabled by setting the
Acknowledge
sequence
enable
bit,
ACKEN
(SSPCON2). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
is presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate generator then counts for one rollover period (TBRG) and the
SCL pin is de-asserted (pulled high). When the SCL pin
is sampled high (clock arbitration), the baud rate generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the
baud rate generator is turned off and the MSSP module
then goes into IDLE mode (Figure 14-20).
14.4.10.1
14.4.11.1
WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t
occur).
WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 14-20:
STOP CONDITION TIMING
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
TBRG
TBRG
SDA
SCL
D0
ACK
8
9
SSPIF
Set SSPIF at the end
of receive
Cleared in
software
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one baud rate generator period.
DS39026D-page 142
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 14-21:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for Tbrg, followed by SDA = 1 for Tbrg
after SDA sampled high. P bit (SSPSTAT) is set
Write to SSPCON2
Set PEN
PEN bit (SSPCON2) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup STOP condition.
Note: TBRG = one baud rate generator period.
14.4.12
CLOCK ARBITRATION
14.4.13
Clock arbitration occurs when the master, during any
receive, transmit, or Repeated START/STOP condition, de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 14-22).
FIGURE 14-22:
SLEEP OPERATION
While in SLEEP mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the MSSP interrupt is enabled).
14.4.14
EFFECT OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1, Load BRG with
SSPADD, and start count
to measure high time interval
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SCL = 1 BRG starts counting
clock high interval.
SCL
SCL line sampled once every machine cycle (TOSC² 4).
Hold off BRG until SCL is sampled high.
SDA
TBRG
1999-2013 Microchip Technology Inc.
TBRG
TBRG
DS39026D-page 143
PIC18CXX2
14.4.15
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET, or
when the MSSP module is disabled. Control of the I 2C
bus may be taken when the P bit (SSPSTAT) is set,
or the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will generate the interrupt when the STOP condition occurs.
In multi-master operation, the SDA line must be monitored, for arbitration, to see if the signal level is the
expected output level. This check is performed in hardware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
•
•
•
•
•
Address Transfer
Data Transfer
A START Condition
A Repeated START Condition
An Acknowledge Condition
14.4.16
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision Interrupt Service Routine, and if the
I2C bus is free, the user can resume communication by
asserting a START condition.
If a START, Repeated START, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine, and if
the I2C bus is free, the user can resume communication
by asserting a START condition.
The master will continue to monitor the SDA and SCL
pins. If a STOP condition occurs, the SSPIF bit will be
set.
MULTI -MASTER
COMMUNICATION, BUS
COLLISION, AND BUS
ARBITRATION
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the transmitter left off when the bus collision occurred.
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
FIGURE 14-23:
SDA is a '1' and the data sampled on the SDA pin = '0',
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its IDLE state (Figure 14-23).
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0
SDA line pulled low
by another source
SDA released
by master
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
Bus collision has occurred.
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
DS39026D-page 144
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.4.16.1
Bus Collision During a START
Condition
During a START condition, a bus collision occurs if:
a)
SDA or SCL are sampled low at the beginning of
the START condition (Figure 14-24).
SCL is sampled low before SDA is asserted low
(Figure 14-25).
b)
During a START condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 14-26). If, however, a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0, and during this time, if the SCL pins
are sampled as '0', a bus collision does not occur. At
the end of the BRG count, the SCL pin is asserted low.
Note:
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the START condition is aborted,
• the BCLIF flag is set, and
• the MSSP module is reset to its IDLE state
(Figure 14-24).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
FIGURE 14-24:
The reason that bus collision is not a factor
during a START condition, is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address following the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START, or STOP conditions.
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
. Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
Set SEN, enable START
condition if SDA = 1, SCL=1
SEN cleared automatically because of bus collision.
SSP module reset into idle state.
SEN
BCLIF
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software
1999-2013 Microchip Technology Inc.
DS39026D-page 145
PIC18CXX2
FIGURE 14-25:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable START
sequence if SDA = 1, SCL = 1
SCL
SCL = 0 before SDA = 0,
Bus collision occurs, set BCLIF
SEN
SCL = 0 before BRG time-out,
Bus collision occurs, set BCLIF
BCLIF
Interrupt cleared
in software
S
'0'
'0'
SSPIF
'0'
'0'
FIGURE 14-26:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Less than TBRG
Set SSPIF
TBRG
SDA SDA pulled low by other master.
Reset BRG and assert SDA.
SCL
S
SCL pulled low after BRG
Time-out
SEN
BCLIF
Set SEN, enable START
sequence if SDA = 1, SCL = 1
'0'
S
SSPIF
SDA = 0, SCL = 1
Set SSPIF
DS39026D-page 146
Interrupts cleared
in software
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.4.16.2
Bus Collision During a Repeated
START Condition
reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs
because no two masters can assert SDA at exactly the
same time.
During a Repeated START condition, a bus collision
occurs if:
a)
b)
If SCL goes from high to low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ’1’ during the Repeated START condition, Figure 14-28.
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ’1’.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is
complete.
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD
and counts down to 0. The SCL pin is then de-asserted,
and when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ’0’,
Figure 14-27). If SDA is sampled high, the BRG is
FIGURE 14-27:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
'0'
S
'0'
SSPIF
FIGURE 14-28:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
BCLIF
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL.
Interrupt cleared
in software
RSEN
S
'0'
SSPIF
1999-2013 Microchip Technology Inc.
DS39026D-page 147
PIC18CXX2
14.4.16.3
Bus Collision During a STOP
Condition
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data '0' (Figure 14-29). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master attempting to drive a data '0' (Figure 14-30).
Bus collision occurs during a STOP condition if:
a)
b)
After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is de-asserted, SCL is sampled low before SDA goes high.
FIGURE 14-29:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG
TBRG
SDA sampled
low after TBRG,
Set BCLIF
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
'0'
SSPIF
'0'
FIGURE 14-30:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
Assert SDA
SCL
SCL goes low before SDA goes high
Set BCLIF
PEN
BCLIF
P
'0'
SSPIF
'0'
DS39026D-page 148
1999-2013 Microchip Technology Inc.
PIC18CXX2
15.0
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
In order to configure pins RC6/TX/CK and RC7/RX/DT
as the Universal Synchronous Asynchronous Receiver
Transmitter:
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured
as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc.
REGISTER 15-1:
• bit SPEN (RCSTA) must be set (= 1), and
• bits TRISC must be cleared (= 0).
Register 15-1 shows the Transmit Status and Control
Register (TXSTA) and Register 15-2 shows the
Receive Status and Control Register (RCSTA).
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
bit 7
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note:
bit 4
R/W-0
BRGH
R-1
TRMT
R/W-0
TX9D
bit 0
SREN/CREN overrides TXEN in SYNC mode.
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
Unimplemented: Read as '0'
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0
TX9D: 9th bit of transmit data. Can be Address/Data bit or a parity bit.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
1999-2013 Microchip Technology Inc.
x = Bit is unknown
DS39026D-page 149
PIC18CXX2
REGISTER 15-2:
RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
bit 7
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
ADDEN
R-0
FERR
R-0
OERR
R-x
RX9D
bit 0
bit 7
SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Unused in this mode
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load of the receive buffer
when RSR is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: 9th bit of received data, can be Address/Data bit or a parity bit.
Legend:
DS39026D-page 150
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
1999-2013 Microchip Technology Inc.
PIC18CXX2
15.1
USART Baud Rate Generator
(BRG)
Example 15-1 shows the calculation of the baud rate
error for the following conditions:
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 15-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internal clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 15-1. From this, the error in
baud rate can be determined.
•
•
•
•
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting the new baud rate.
15.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
EXAMPLE 15-1:
CALCULATING BAUD RATE ERROR
Desired Baud Rate
=
FOSC / (64 (X + 1))
X
X
X
=
=
=
( (FOSC / Desired Baud rate) / 64 ) - 1
((16000000 / 9600) / 64) - 1
[25.042] = 25
Calculated Baud Rate
=
=
16000000 / (64 (25 + 1))
9615
Error
=
(Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
(9615 - 9600) / 9600
0.16%
Solving for X:
=
=
TABLE 15-1:
BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
Baud Rate = FOSC/(16(X+1))
NA
0
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
1
Legend: X = value in SPBRG (0 to 255)
TABLE 15-2:
Name
TXSTA
RCSTA
SPBRG
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
1999-2013 Microchip Technology Inc.
DS39026D-page 151
PIC18CXX2
TABLE 15-3:
BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 40 MHz
BAUD
RATE
(K)
FOSC = 20 MHz
SPBRG Actua
value
l Rate
(decimal)
(K)
FOSC = 16 MHz
SPBRG Actual
value
Rate
(decimal)
(K)
FOSC = 10 MHz
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG
value
(decimal)
NA
—
—
NA
—
—
—
NA
—
—
—
—
9.766
+1.73
255
19.23
+0.16
207
19.23
+0.16
129
76.92
+0.16
51
75.76
-1.36
32
95.24
-0.79
41
96.15
+0.16
25
307.69
+2.56
12
312.5
+4.17
7
4
Actual
Rate (K)
%
Error
0.3
NA
—
—
NA
—
—
NA
—
—
1.2
NA
—
—
NA
—
—
NA
—
—
2.4
NA
—
—
NA
—
—
NA
—
9.6
NA
—
—
NA
—
—
NA
19.2
NA
—
—
19.53
+1.73
255
76.8
76.92
0
129
76.92
+0.16
64
96
96.15
0
103
96.15
+0.16
51
300
303.03
-0.01
32
294.1
-1.96
16
%
Error
%
Error
500
500.00
0
19
500
0
9
500
0
7
500
0
HIGH
39.06
—
255
5000
—
0
4000
—
0
2500
—
0
LOW
10000.00
—
0
19.53
—
255
15.625
—
255
9.766
—
255
FOSC = 7.15909 MHz
BAUD
RATE
(K)
FOSC = 5.0688 MHz
FOSC = 4 MHz
FOSC = 3.579545 MHz
Actual
Rate
(K)
%
Error
0.3
NA
—
—
NA
—
—
NA
—
——
1.2
NA
—
—
NA
—
—
NA
—
—
2.4
NA
—
—
NA
—
—
NA
—
—
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG
value
(decimal)
NA
—
—
NA
—
—
NA
—
—
9.6
9.622
+0.23
185
9.6
0
131
9.615
+0.16
103
9.622
+0.23
92
19.2
19.24
+0.23
92
19.2
0
65
19.231
+0.16
51
19.04
-0.83
46
76.8
77.82
+1.32
22
79.2
+3.13
15
76.923
+0.16
12
74.57
-2.90
11
96
94.20
-1.88
18
97.48
+1.54
12
1000
+4.17
9
99.43
+3.57
8
300
298.3
-0.57
5
316.8
+5.60
3
NA
—
—
298.3
-0.57
2
—
500
NA
—
—
NA
—
—
NA
—
—
NA
—
HIGH
1789.8
—
0
1267
—
0
100
—
0
894.9
—
0
LOW
6.991
—
255
4.950
—
255
3.906
—
255
3.496
—
255
FOSC = 1 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
%
Error
FOSC = 32.768 kHz
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG
value
(decimal)
26
0.3
NA
—
—
0.303
+1.14
1.2
1.202
+0.16
207
1.170
-2.48
6
2.4
2.404
+0.16
103
NA
—
—
9.6
9.615
+0.16
25
NA
—
—
19.2
19.24
+0.16
12
NA
—
—
76.8
83.34
+8.51
2
NA
—
—
96
NA
—
—
NA
—
—
300
NA
—
—
NA
—
—
500
NA
—
—
NA
—
—
HIGH
250
—
0
8.192
—
0
LOW
0.9766
—
255
0.032
—
255
DS39026D-page 152
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 15-4:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 40 MHz
BAUD
RATE
(K)
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
Actual
Rate
(K)
%
Error
0.3
NA
—
—
NA
—
—
NA
—
—
NA
—
—
1.2
NA
—
—
1.221
+1.73
255
1.202
+0.16
207
1.202
+0.16
129
2.4
2.44
-1.70
255
2.404
+0.16
129
2.404
+0.16
103
2.404
+0.16
64
15
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG
value
(decimal)
9.6
9.62
-0.16
64
9.469
-1.36
32
9.615
+0.16
25
9.766
+1.73
19.2
18.94
+1.38
32
19.53
+1.73
15
19.23
+0.16
12
19.53
+1.73
7
76.8
78.13
-1.70
7
78.13
+1.73
3
83.33
+8.51
2
78.13
+1.73
1
96
89.29
+7.52
6
104.2
+8.51
2
NA
—
—
NA
—
—
300
312.50
-4.00
1
312.5
+4.17
0
NA
—
—
NA
—
—
500
625.00
-20.00
0
NA
—
—
NA
—
—
NA
—
—
HIGH
2.44
—
255
312.5
—
0
250
—
0
156.3
—
0
LOW
625.00
—
0
1.221
—
255
0.977
—
255
0.6104
—
255
FOSC = 7.15909 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
%
Error
FOSC = 5.0688 MHz
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
FOSC = 4 MHz
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
FOSC = 3.579545 MHz
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG
value
(decimal)
0.3
NA
—
—
0.31
+3.13
255
0.3005
-0.17
207
0.301
+0.23
185
1.2
1.203
+0.23
92
1.2
0
65
1.202
+1.67
51
1.190
-0.83
46
2.4
2.380
-0.83
46
2.4
0
32
2.404
+1.67
25
2.432
+1.32
22
5
9.6
9.322
-2.90
11
9.9
+3.13
7
NA
—
—
9.322
-2.90
19.2
18.64
-2.90
5
19.8
+3.13
3
NA
—
—
18.64
-2.90
2
76.8
NA
—
—
79.2
+3.13
0
NA
—
—
NA
—
—
96
NA
—
—
NA
—
—
NA
—
—
NA
—
—
300
NA
—
—
NA
—
—
NA
—
—
NA
—
—
500
NA
—
—
NA
—
—
NA
—
—
NA
—
—
HIGH
111.9
—
0
79.2
—
0
62.500
—
0
55.93
—
0
LOW
0.437
—
255
0.3094
—
255
3.906
—
255
0.2185
—
255
FOSC = 1 MHz
BAUD
RATE
(K)
FOSC = 32.768 kHz
Actual
Rate
(K)
%
Error
0.3
0.300
+0.16
51
0.256
-14.67
1
1.2
1.202
+0.16
12
NA
—
—
2.4
2.232
-6.99
6
NA
—
—
9.6
NA
—
—
NA
—
—
19.2
NA
—
—
NA
—
—
76.8
NA
—
—
NA
—
—
96
NA
—
—
NA
—
—
300
NA
—
—
NA
—
—
500
NA
—
—
NA
—
—
HIGH
15.63
—
0
0.512
—
0
LOW
0.0610
—
255
0.0020
—
255
SPBRG Actual
value
Rate
(decimal)
(K)
1999-2013 Microchip Technology Inc.
%
Error
SPBRG
value
(decimal)
DS39026D-page 153
PIC18CXX2
TABLE 15-5:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 40 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
%
Error
FOSC = 20 MHz
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
FOSC = 16 MHz
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
FOSC = 10 MHz
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG
value
(decimal)
64
9.6
9.77
-1.70
255
9.615
+0.16
129
9.615
+0.16
103
9.615
+0.16
19.2
19.23
-0.16
129
19.230
+0.16
64
19.230
+0.16
51
18.939
-1.36
32
38.4
38.46
-0.16
64
37.878
-1.36
32
38.461
+0.16
25
39.062
+1.7
15
10
57.6
58.14
-0.93
42
56.818
-1.36
21
58.823
+2.12
16
56.818
-1.36
115.2
113.64
+1.38
21
113.63
-1.36
10
111.11
-3.55
8
125
+8.51
4
250
250.00
0
9
250
0
4
250
0
3
NA
—
—
625
625.00
0
3
625
0
1
NA
—
—
625
0
0
1250
1250.00
0
1
1250
0
0
NA
—
—
NA
—
—
FOSC = 7.16MHz
BAUD
RATE
(K)
FOSC = 5.068 MHz
Actual
Rate
(K)
%
Error
9.520
-0.83
46
9.6
19.2
19.454
+1.32
22
38.4
37.286
-2.90
11
57.6
55.930
-2.90
115.2
111.860
250
9.6
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
FOSC = 4 MHz
SPBRG Actual
value
Rate
(decimal)
(K)
+1.32
22
-2.94
16
1.202
+0.17
207
18.643
-2.90
11
39.6
+3.12
7
2.403
+0.13
103
37.286
-2.90
5
7
52.8
-8.33
5
9.615
+0.16
25
55.930
-2.90
3
-2.90
3
105.6
-8.33
2
19.231
+0.16
12
111.86
-2.90
1
NA
—
—
NA
—
—
NA
—
—
223.72
-10.51
0
625
NA
—
—
NA
—
—
NA
—
—
NA
—
—
1250
NA
—
—
NA
—
—
NA
—
—
NA
—
—
%
Error
FOSC = 32.768 kHz
SPBRG Actual
value
Rate
(decimal)
(K)
%
Error
SPBRG
value
(decimal)
9.6
8.928
-6.99
6
NA
—
—
19.2
20.833
+8.51
2
NA
—
—
38.4
31.25
-18.61
1
NA
—
—
57.6
62.5
+8.51
0
NA
—
—
115.2
NA
—
—
NA
—
—
250
NA
—
—
NA
—
—
625
NA
—
—
NA
—
—
1250
NA
—
—
NA
—
—
DS39026D-page 154
9.727
SPBRG
value
(decimal)
18.645
Actual
Rate
(K)
—
%
Error
32
FOSC = 1 MHz
—
SPBRG Actual
value
Rate
(decimal)
(K)
0
BAUD
RATE
(K)
NA
%
Error
FOSC = 3.579545 MHz
1999-2013 Microchip Technology Inc.
PIC18CXX2
15.2
USART Asynchronous Mode
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit, TXIE
( PIE1). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicated the status of the TXREG register, another bit TRMT
(TXSTA) shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
In this mode, the USART uses standard non-return-tozero (NRZ) format (one START bit, eight or nine data
bits and one STOP bit). The most common data format
is 8-bits. An on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and
receives the LSb first. The USART’s transmitter and
receiver are functionally independent, but use the
same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift
rate, depending on bit BRGH (TXSTA). Parity is not
supported by the hardware, but can be implemented in
software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA).
2: Flag bit TXIF is set when enable bit TXEN
is set.
The USART Asynchronous module consists of the following important elements:
•
•
•
•
To set up an asynchronous transmission:
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
15.2.1
1.
2.
USART ASYNCHRONOUS
TRANSMITTER
3.
4.
The USART transmitter block diagram is shown in
Figure 15-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
FIGURE 15-1:
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 15.1).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts transmission).
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG Register
TXIE
8
MSb
LSb
(8)
Pin Buffer
and Control
0
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
1999-2013 Microchip Technology Inc.
DS39026D-page 155
PIC18CXX2
FIGURE 15-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(shift clock)
RC6/TX/CK (pin)
START Bit
Bit 0
TXIF bit
(Transmit buffer
reg. empty flag)
Bit 1
Word 1
Bit 7/8
STOP Bit
Word 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
FIGURE 15-3:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 1
BRG Output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
START Bit
TRMT bit
(Transmit shift
reg. empty flag)
Note:
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
SPBRG
Legend:
Note 1:
Bit 0
Bit 1
Word 1
Bit 7/8
STOP Bit
START Bit
Bit 0
Word 2
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
This timing diagram shows two consecutive transmissions.
TABLE 15-6:
Name
Word 2
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
RESETS
RBIF
0000 000x 0000 000u
PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEL
PSPIF(1)
ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PSPIE(1) ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PSPIP(1) ADIP
RCIP
TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
USART Transmit Register
0000 0000 0000 0000
CSRC
TX9
TXEN SYNC
—
BRGH TRMT
TX9D
0000 -010 0000 -010
Baud Rate Generator Register
0000 0000 0000 0000
x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Transmission.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
GIE/GIEH
DS39026D-page 156
1999-2013 Microchip Technology Inc.
PIC18CXX2
15.2.2
USART ASYNCHRONOUS
RECEIVER
15.2.3
The receiver block diagram is shown in Figure 15-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter operates at the bit rate, or at FOSC. This mode would typically be used in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is required,
set the BRGH bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
7. The RCIF bit will be set when reception is complete. The interrupt will be acknowledged if the
RCIE and GIE bits are set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
To set up an Asynchronous Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 15.1).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
Enable the reception by setting bit CREN.
Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable
bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
FIGURE 15-4:
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
64
or
16
Baud Rate Generator
RSR Register
MSb
STOP (8)
7
1
LSb
0 START
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
Interrupt
RCIF
Data Bus
RCIE
1999-2013 Microchip Technology Inc.
DS39026D-page 157
PIC18CXX2
FIGURE 15-5:
ASYNCHRONOUS RECEPTION
START
bit
bit0
RX (pin)
bit1
bit7/8 STOP
bit
Rcv shift
reg
Rcv buffer reg
START
bit
bit0
START
bit
bit7/8
STOP
bit
Word 2
RCREG
Word 1
RCREG
Read Rcv
buffer reg
RCREG
bit7/8 STOP
bit
RCIF
(interrupt flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing
the OERR (overrun) bit to be set.
TABLE 15-7:
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
Bit 6
INTCON
GIE/GIEH
PIR1
PIE1
IPR1
RCSTA
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
PEIE/
GIEL
ADIF
ADIE
ADIP
RX9
RCREG
TXSTA
SPBRG
Bit 5
Bit 4
TMR0IE INT0IE
RCIF
RCIE
RCIP
SREN
Bit 3
RBIE
TXIF
SSPIF
TXIE SSPIE
TXIP SSPIP
CREN ADDEN
Bit 2
Bit 0
Value on
POR,
BOR
Value on
all other
RESETS
RBIF
0000 000x
0000 000u
TMR2IF TMR1IF 0000 0000
TMR2IE TMR1IE 0000 0000
TMR2IP TMR1IP 0000 0000
OERR RX9D 0000 -00x
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
Bit 1
TMR0IF INT0IF
CCP1IF
CCP1IE
CCP1IP
FERR
USART Receive Register
CSRC
TX9
TXEN
Baud Rate Generator Register
SYNC
—
BRGH
TRMT
TX9D
0000 -00x
Legend: x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
DS39026D-page 158
1999-2013 Microchip Technology Inc.
PIC18CXX2
15.3
USART Synchronous Master
Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner, (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA). In
addition, enable bit SPEN (RCSTA) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA).
15.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 15-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG is empty and inter-
TABLE 15-8:
Name
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
SPBRG
Legend:
Note 1:
Bit 7
rupt bit TXIF (PIR1) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE, and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA)
shows the status of the TSR register. TRMT is a read
only bit, which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
To set up a Synchronous Master Transmission:
1.
2.
3.
4.
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate (Section 15.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
GIE/
PEIE/
TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF
0000 000x 0000 000u
GIEH
GIEL
PSPIF(1) ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PSPIE(1) ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PSPIP(1) ADIP
RCIP
TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
0000 -00x 0000 -00x
USART Transmit Register
0000 0000 0000 0000
CSRC
TX9
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
Baud Rate Generator Register
0000 0000 0000 0000
x = unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Master Transmission.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
1999-2013 Microchip Technology Inc.
DS39026D-page 159
PIC18CXX2
FIGURE 15-6:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT
pin
Bit 0
Bit 1
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit 2
Bit 7
Word 1
Bit 0
Bit 1
Word 2
Bit 7
RC6/TX/CK pin
Write to
TXREG reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt flag)
TRMT bit TRMT
TXEN bit
Note:
'1'
'1'
Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.
FIGURE 15-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit0
bit1
bit2
bit6
bit7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS39026D-page 160
1999-2013 Microchip Technology Inc.
PIC18CXX2
15.3.2
USART SYNCHRONOUS MASTER
RECEPTION
3.
4.
5.
6.
Ensure bits CREN and SREN are clear.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA), or enable bit CREN (RCSTA). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
Initialize the SPBRG register for the appropriate
baud rate (Section 15.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
TABLE 15-9:
Name
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend:
Note 1:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Value on
POR,
BOR
Bit 0
Value on all
other
RESETS
GIE/
PEIE/
TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF
0000 000x 0000 000u
GIEH
GIEL
PSPIF(1) ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PSPIE(1) ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PSPIP(1) ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
USART Receive Register
0000 0000 0000 0000
CSRC
TX9
TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
Baud Rate Generator Register
0000 0000 0000 0000
x = unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Master Reception.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
FIGURE 15-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit
'0'
'0'
RCIF bit
(interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = '1' and bit BRGH = '0'.
1999-2013 Microchip Technology Inc.
DS39026D-page 161
PIC18CXX2
15.4
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA).
15.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the SLEEP
mode.
7.
Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
If enable bit TXIE is set, the interrupt will wake the
chip from SLEEP. If the global interrupt is enabled,
the program will branch to the interrupt vector.
TABLE 15-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
SPBRG
Legend:
Note 1:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
RBIF 0000 000x 0000 000u
GIE/
PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEH
GIEL
PSPIF(1) ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PSPIE(1) ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PSPIP(1) ADIP
RCIP
TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
USART Transmit Register
0000 0000 0000 0000
CSRC
TX9
TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
Baud Rate Generator Register
0000 0000 0000 0000
x = unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Slave Transmission.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
DS39026D-page 162
1999-2013 Microchip Technology Inc.
PIC18CXX2
15.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
To set up a Synchronous Slave Reception:
1.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode and bit SREN, which is a “don't care” in Slave
mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register,
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector.
2.
3.
4.
5.
6.
7.
8.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is complete. An interrupt will be generated if enable bit
RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
TABLE 15-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend:
Note 1:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
RESETS
RBIF 0000 000x 0000 000u
GIE/
PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEH
GIEL
PSPIF(1) ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PSPIE(1) ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PSPIP(1) ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
USART Receive Register
0000 0000 0000 0000
CSRC
TX9
TXEN
SYNC
—
BRGH TRMT
TX9D 0000 -010 0000 -010
Baud Rate Generator Register
0000 0000 0000 0000
x = unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Slave Reception.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
1999-2013 Microchip Technology Inc.
DS39026D-page 163
PIC18CXX2
NOTES:
DS39026D-page 164
1999-2013 Microchip Technology Inc.
PIC18CXX2
16.0
COMPATIBLE 10-BIT ANALOGTO-DIGITAL CONVERTER (A/D)
MODULE
The A/D module has four registers. These registers
are:
•
•
•
•
The analog-to-digital (A/D) converter module has five
inputs for the PIC18C2x2 devices and eight for the
PIC18C4x2 devices. This module has the ADCON0
and ADCON1 register definitions that are compatible
with the mid-range A/D module.
The ADCON0 register, shown in Register 16-1, controls the operation of the A/D module. The ADCON1
register, shown in Register 16-2, configures the functions of the port pins.
The A/D allows conversion of an analog input signal to
a corresponding 10-bit digital number.
REGISTER 16-1:
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
ADCON0 REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
bit 7
bit 7-6
bit 5-3
bit 0
ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)
ADCON1
ADCON0
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
Clock Conversion
FOSC/2
FOSC/8
FOSC/32
FRC (clock derived from the internal A/D RC oscillator)
FOSC/4
FOSC/16
FOSC/64
FRC (clock derived from the internal A/D RC oscillator)
CHS2:CHS0: Analog Channel Select bits
000 = channel 0 (AN0)
001 = channel 1 (AN1)
010 = channel 2 (AN2)
011 = channel 3 (AN3)
100 = channel 4 (AN4)
101 = channel 5 (AN5)
110 = channel 6 (AN6)
111 = channel 7 (AN7)
Note:
The PIC18C2X2 devices do not implement the full 8 A/D channels; the unimplemented selections
are reserved. Do not select any unimplemented channel.
bit 2
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically
cleared by hardware when the A/D conversion is complete)
0 = A/D conversion not in progress
bit 1
Unimplemented: Read as '0'
bit 0
ADON: A/D On bit
1 = A/D converter module is powered up
0 = A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
1999-2013 Microchip Technology Inc.
x = Bit is unknown
DS39026D-page 165
PIC18CXX2
REGISTER 16-2:
ADCON1 REGISTER
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’.
bit 6
ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)
ADCON1
ADCON0
FOSC/2
FOSC/8
FOSC/32
FRC (clock derived from the internal A/D RC oscillator)
FOSC/4
FOSC/16
FOSC/64
FRC (clock derived from the internal A/D RC oscillator)
00
01
10
11
00
01
10
11
0
0
0
0
1
1
1
1
Clock Conversion
bit 5-4
Unimplemented: Read as '0'
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits
PCFG
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
VREF+
VREF-
C/R
0000
A
A
A
A
A
A
A
A
VDD
VSS
8/0
0001
A
A
A
A
VREF+
A
A
A
AN3
VSS
7/1
0010
D
D
D
A
A
A
A
A
VDD
VSS
5/0
0011
D
D
D
A
VREF+
A
A
A
AN3
VSS
4/1
0100
D
D
D
D
A
D
A
A
VDD
VSS
3/0
0101
D
D
D
D
VREF+
D
A
A
AN3
VSS
2/1
011x
D
D
D
D
D
D
D
D
—
—
0/0
1000
A
A
A
A
VREF+
VREF-
A
A
AN3
AN2
6/2
1001
D
D
A
A
A
A
A
A
VDD
VSS
6/0
1010
D
D
A
A
VREF+
A
A
A
AN3
VSS
5/1
1011
D
D
A
A
VREF+
VREF-
A
A
AN3
AN2
4/2
1100
D
D
D
A
VREF+
VREF-
A
A
AN3
AN2
3/2
1101
D
D
D
D
VREF+
VREF-
A
A
AN3
AN2
2/2
1110
D
D
D
D
D
D
D
A
VDD
VSS
1/0
1111
D
D
D
D
VREF+
VREF-
D
A
AN3
AN2
1/2
A = Analog input D = Digital I/O
C/R = # of analog input channels/# of A/D voltage references
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
Note:
DS39026D-page 166
x = Bit is unknown
On any device RESET, the port pins that are multiplexed with analog functions (ANx) are
forced to be an analog input.
1999-2013 Microchip Technology Inc.
PIC18CXX2
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS) or the voltage level on the RA3/AN3/
VREF+ pin and RA2/AN2/VREF-.
Each port pin associated with the A/D converter can be
configured as an analog input (RA3 can also be a voltage reference) or as a digital I/O.
The ADRESH and ADRESL registers contain the result
of the A/D conversion. When the A/D conversion is
complete, the result is loaded into the ADRESH/
ADRESL registers, the GO/DONE bit (ADCON0) is
cleared, and A/D interrupt flag bit ADIF is set. The block
diagram of the A/D module is shown in Figure 16-1.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off and
any conversion is aborted.
FIGURE 16-1:
A/D BLOCK DIAGRAM
CHS2:CHS0
111
110
101
100
VAIN
011
(Input Voltage)
010
10-bit
Converter
A/D
001
PCFG0
000
VDD
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
VREF+
Reference
voltage
VREFVSS
1999-2013 Microchip Technology Inc.
DS39026D-page 167
PIC18CXX2
16.1
The value that is in the ADRESH/ADRESL registers is
not modified for a Power-on Reset. The ADRESH/
ADRESL registers will contain unknown data after a
Power-on Reset.
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 16-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 k. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 16.1.
After this acquisition time has elapsed, the A/D conversion can be started. The following steps should be followed for doing an A/D conversion:
1.
2.
3.
4.
5.
A/D Acquisition Requirements
Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
Note:
When the conversion is started, the holding capacitor is disconnected from the
input pin.
OR
6.
7.
• Waiting for the A/D interrupt
Read A/D Result registers (ADRESH/ADRESL);
clear bit ADIF if required.
For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 16-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
Rs
VAIN
RIC 1k
ANx
CPIN
5 pF
VT = 0.6V
SS
RSS
I leakage
± 500 nA
CHOLD = 120 pF
VSS
Legend: CPIN
= input capacitance
= threshold voltage
VT
I LEAKAGE = leakage current at the pin due to
various junctions
= interconnect resistance
RIC
= sampling switch
SS
= sample/hold capacitance (from DAC)
CHOLD
DS39026D-page 168
VDD
6V
5V
4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch (k)
1999-2013 Microchip Technology Inc.
PIC18CXX2
To calculate the minimum acquisition time,
Equation 16-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
EQUATION 16-1:
TACQ
ACQUISITION TIME
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 16-2:
VHOLD =
or
TC
=
A/D MINIMUM CHARGING TIME
(VREF - (VREF/2048)) • (1 - e(-Tc/CHOLD(RIC + RSS + RS)))
-(120 pF)(1 k + RSS + RS) ln(1/2047)
Example 16-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system assumptions:
•
•
•
•
•
•
=
CHOLD
Rs
=
Conversion Error
VDD
=
Temperature
=
VHOLD
=
EXAMPLE 16-1:
TACQ =
120 pF
2.5 k
1/2 LSb
5V Rss = 7 k
50C (system max.)
0V @ time = 0
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25C.
TACQ =
TC
=
TACQ =
2 s + Tc + [(Temp - 25C)(0.05 s/C)]
-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 k + 7 k + 2.5 k) ln(0.0004885)
-120 pF (10.5 k) ln(0.0004885)
-1.26 s (-7.6241)
9.61 s
2 s + 9.61 s + [(50C - 25C)(0.05 s/C)]
11.61 s + 1.25 s
12.86 s
1999-2013 Microchip Technology Inc.
DS39026D-page 169
PIC18CXX2
16.2
Selecting the A/D Conversion
Clock
16.3
The ADCON1, TRISA and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their corresponding
TRIS bits set (input). If the TRIS bit is cleared (output),
the digital output level (VOH or VOL) will be converted.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 12 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. The seven possible options for TAD are:
•
•
•
•
•
•
•
Configuring Analog Port Pins
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
2TOSC
4TOSC
8TOSC
16TOSC
32TOSC
64TOSC
Internal RC oscillator
Note 1: When reading the port register, all pins configured as analog input channels will read as
cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will
not affect the conversion accuracy.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
2: Analog levels on any pin that is defined as
a digital input (including the AN4:AN0
pins) may cause the input buffer to consume current that is out of the devices
specification.
Table 16-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 16-1:
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Operation
ADCS2:ADCS0
Device Frequency
40 MHz
20 MHz
5 MHz
1.25 MHz
333.33 kHz
2TOSC
000
50 ns
100
1.6 s
6 s
4TOSC
100
100 ns
200 ns(2)
800 ns(2)
3.2 s
12 s
8TOSC
001
200 ns
400 ns(2)
1.6 s
6.4 s
24 s(3)
ns(2)
3.2 s
12.8 s
48 s(3)
6.4 s
25.6 s(3)
96 s(3)
s(3)
192 s(3)
2 - 6 s(1)
2 - 6 s(1)
16TOSC
101
400 ns
32TOSC
010
800 ns
800
ns(2)
400
1.6 s
ns(2)
64TOSC
110
1.6 s
3.2 s
12.8 s
RC
011
2 - 6 s(1)
2 - 6 s(1)
2 - 6 s(1)
Legend:
Note 1:
2:
3:
51.2
Shaded cells are outside of recommended range.
The RC source has a typical TAD time of 4 s.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
TABLE 16-2:
TAD vs. DEVICE OPERATING FREQUENCIES (FOR EXTENDED, LC, DEVICES)
AD Clock Source (TAD)
Operation
ADCS2:ADCS0
Device Frequency
4 MHz
ns(2)
2 MHz
s(2)
1.25 MHz
333.33 kHz
s(2)
6 s
2TOSC
000
500
4TOSC
100
1.0 s(2)
2.0 s(2)
3.2 s(2)
12 s
8TOSC
001
2.0 s(2)
4.0 s
6.4 s
24 s(3)
16TOSC
101
s(2)
8.0 s
12.8 s
48 s(3)
32TOSC
010
16.0 s
25.6 s(3)
96 s(3)
s(3)
192 s(3)
4.0
8.0 s
1.0
64TOSC
110
16.0 s
32.0 s
RC
011
3 - 9 s(1,4)
3 - 9 s(1,4)
Legend:
Note 1:
2:
3:
1.6
51.2
3 - 9 s(1,4)
3 - 9 s(1,4)
Shaded cells are outside of recommended range.
The RC source has a typical TAD time of 6 s.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
DS39026D-page 170
1999-2013 Microchip Technology Inc.
PIC18CXX2
16.4
A/D Conversions
16.5
Figure 16-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, acquisition on the selected channel is
automatically started.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Use of the CCP2 Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON) be programmed as 1011 and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion and
the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a
conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D module, but will still reset the Timer1 (or Timer3) counter.
FIGURE 16-3:
A/D CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b0
b1
b3
b0
b4
b2
b5
b7
b6
b8
b9
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
1999-2013 Microchip Technology Inc.
DS39026D-page 171
PIC18CXX2
TABLE 16-3:
SUMMARY OF A/D REGISTERS
Value on all
other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0000 0000 0000 0000
PIR2
—
—
—
—
BCLIF
LVDIF
TMR3IF
CCP2IF
---- 0000 ---- 0000
PIE2
—
—
—
—
BCLIE
LVDIE
TMR3IE
CCP2IE
---- 0000 ---- 0000
IPR2
—
—
—
—
BCLIP
LVDIP
TMR3IP
CCP2IP
ADRESH
A/D Result Register
ADRESL
A/D Result Register
ADCON0
ADCS1
ADCS0
ADCON1
---- 0000 ---- 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CHS2
CHS1
CHS0
GO/
DONE
—
ADON
0000 00-0 0000 00-0
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
---- -000 ---- -000
PORTA
—
RA6
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000 --0u 0000
TRISA
—
PORTE
—
—
—
RE2
RE1
RE0
---- -000 ---- -000
LATE2
LATE1
LATE0
---- -xxx ---- -uuu
PORTA Data Direction Register
—
—
--11 1111 --11 1111
LATE
—
—
—
—
—
TRISE
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction bits
0000 -111 0000 -111
Legend: x = unknown, u = unchanged, — = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
DS39026D-page 172
1999-2013 Microchip Technology Inc.
PIC18CXX2
17.0
LOW VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application software can do “housekeeping tasks” before the device
voltage exits the valid operating range. This can be
done using the Low Voltage Detect module.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When the voltage of the device becomes lower then the
specified point, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the interrupt vector address and the software can then respond
to that interrupt source.
Figure 17-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage VA,
the LVD logic generates an interrupt. This occurs at
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to shut-down the system. Voltage point VB is the
minimum valid operating voltage specification. This
occurs at time TB. The difference TB - TA is the total
time for shut-down.
TYPICAL LOW VOLTAGE DETECT APPLICATION
Voltage
FIGURE 17-1:
The Low Voltage Detect circuitry is completely under
software control. This allows the circuitry to be “turned
off” by the software, which minimizes the current consumption for the device.
VA
VB
Legend:
VA = LVD trip point
VB = Minimum valid device
operating voltage
Time
TA
TB
The block diagram for the LVD module is shown in
Figure 17-2. A comparator uses an internally generated reference voltage as the set point. When the
selected tap output of the device voltage crosses the
set point (is lower than), the LVDIF bit is set.
Each node in the resistor divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate
before the LVD module asserts an interrupt. When the
1999-2013 Microchip Technology Inc.
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array is equal to the 1.2V
internal reference voltage generated by the voltage
reference module. The comparator then generates an
interrupt signal setting the LVDIF bit. This voltage is
software programmable to any one of 16 values (see
Figure 17-2). The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON).
DS39026D-page 173
PIC18CXX2
FIGURE 17-2:
LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM
LVDIN
LVD Control
Register
16 to 1 MUX
VDD
Internally Generated
Nominal Reference Voltage
1.2V
LVDEN
The LVD module has an additional feature that allows
the user to supply the trip voltage to the module from
an external source. This mode is enabled when bits
LVDL3:LVDL0 are set to 1111. In this state, the comparator input is multiplexed from the external input pin
LVDIN (Figure 17-3).
FIGURE 17-3:
LVDIF
This gives flexibility, because it allows a user to configure the Low Voltage Detect interrupt to occur at any
voltage in the valid operating range.
LOW VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD
VDD
16 to 1 MUX
LVD Control
Register
LVDIN
Externally Generated
Trip Point
LVDEN
LVD
VxEN
BODEN
EN
BGAP
DS39026D-page 174
1999-2013 Microchip Technology Inc.
PIC18CXX2
17.1
Control Register
The Low Voltage Detect Control register controls the
operation of the Low Voltage Detect circuitry.
REGISTER 17-1:
LVDCON REGISTER
U-0
U-0
R-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
—
—
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5
IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the Low Voltage Detect logic will generate the interrupt flag at the
specified voltage range
0 = Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
bit 4
LVDEN: Low Voltage Detect Power Enable bit
1 = Enables LVD, powers up LVD circuit
0 = Disables LVD, powers down LVD circuit
bit 3-0
LVDL3:LVDL0: Low Voltage Detection Limit bits
1111 = External analog input is used (input comes from the LVDIN pin)
1110 = 4.5V min. - 4.77V max.
1101 = 4.2V min. - 4.45V max.
1100 = 4.0V min. - 4.24V max.
1011 = 3.8V min. - 4.03V max.
1010 = 3.6V min. - 3.82V max.
1001 = 3.5V min. - 3.71V max.
1000 = 3.3V min. - 3.50V max.
0111 = 3.0V min. - 3.18V max.
0110 = 2.8V min. - 2.97V max.
0101 = 2.7V min. - 2.86V max.
0100 = 2.5V min. - 2.65V max.
0011 = 2.4V min. - 2.54V max.
0010 = 2.2V min. - 2.33V max.
0001 = 2.0V min. - 2.12V max.
0000 = 1.8V min. - 1.91V max.
Note:
LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage
of the device are not tested.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
1999-2013 Microchip Technology Inc.
DS39026D-page 175
PIC18CXX2
17.2
Operation
The following steps are needed to set up the LVD module:
Depending on the power source for the device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for
short periods, where the voltage is checked. After
doing the check, the LVD module may be disabled.
1.
Each time that the LVD module is enabled, the circuitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
4.
2.
3.
5.
6.
Write the value to the LVDL3:LVDL0 bits (LVDCON register), which selects the desired LVD
Trip Point.
Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared, or the GIE bit is cleared).
Enable the LVD module (set the LVDEN bit in
the LVDCON register).
Wait for the LVD module to stabilize (the IRVST
bit to become set).
Clear the LVD interrupt flag, which may have
falsely become set until the LVD module has
stabilized (clear the LVDIF bit).
Enable the LVD interrupt (set the LVDIE and the
GIE bits).
Figure 17-4 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 17-4:
LOW VOLTAGE DETECT WAVEFORMS
CASE 1:
LVDIF may not be set
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference stable
50 ms
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference stable
50 ms
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since LVD condition still exists
DS39026D-page 176
1999-2013 Microchip Technology Inc.
PIC18CXX2
17.2.1
REFERENCE VOLTAGE SET POINT
The Internal Reference Voltage of the LVD module may
be used by other internal circuitry (the Programmable
Brown-out Reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires a time to become stable before a low voltage
condition can be reliably detected. This time is invariant
of system clock speed. This start-up time is specified in
electrical specification parameter #36. The low voltage
interrupt flag will not be enabled until a stable reference
voltage is reached. Refer to the waveform in Figure 17-4.
17.2.2
17.3
Operation During SLEEP
When enabled, the LVD circuitry continues to operate
during SLEEP. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wakeup from SLEEP. Device execution will continue from
the interrupt vector address, if interrupts have been globally enabled.
17.4
Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the LVD module to be turned off.
CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
1999-2013 Microchip Technology Inc.
DS39026D-page 177
PIC18CXX2
NOTES:
DS39026D-page 178
1999-2013 Microchip Technology Inc.
PIC18CXX2
18.0
SPECIAL FEATURES OF THE
CPU
There are several features intended to maximize system reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection. These are:
• OSC Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-circuit Serial Programming
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
18.1
Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h - 3FFFFFh),
which can only be accessed using table reads and
table writes.
All PIC18CXX2 devices have a Watchdog Timer, which
is permanently enabled via the configuration bits or
software-controlled. It runs off its own RC oscillator for
added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up
Timer (OST), intended to keep the chip in RESET until
the crystal oscillator is stable. The other is the Powerup Timer (PWRT), which provides a fixed delay on
power-up only, designed to keep the part in RESET
while the power supply stabilizes. With these two timers on-chip, most applications need no external
RESET circuitry.
TABLE 18-1:
CONFIGURATION BITS AND DEVICE IDS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Default/
Unprogrammed
Value
Bit 0
300000h
CONFIG1L
CP
CP
CP
CP
CP
CP
CP
CP
1111 1111
300001h
CONFIG1H
—
—
OSCSEN
—
—
FOSC2
FOSC1
FOSC0
111- -111
300002h
CONFIG2L
—
—
—
—
BORV1
BORV0
BODEN
PWRTEN
---- 1111
300003h
CONFIG2H
—
—
—
—
WDTPS2
WDTPS1
WDTPS0
WDTEN
---- 1111
300005h
CONFIG3H
—
—
—
—
—
—
—
CCP2MX
---- ---1
300006h
CONFIG4L
—
—
—
—
—
—
LVEN
STVREN
---- --11
3FFFFEh DEVID1
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
0000 0000
3FFFFFh DEVID2
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
0000 0010
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’
1999-2013 Microchip Technology Inc.
DS39026D-page 179
PIC18CXX2
REGISTER 18-1:
CONFIGURATION REGISTER 1 HIGH (CONFIG1H: BYTE ADDRESS 300001h)
R/P-1
R/P-1
R/P-1
U-0
U-0
R/P-1
R/P-1
R/P-1
Reserved
Reserved
OSCSEN
—
—
FOSC2
FOSC1
FOSC0
bit 7
bit 0
bit 7-6
Reserved: Read as ’1’
bit 5
OSCSEN: Oscillator System Clock Switch Enable bit
1 = Oscillator system clock switch option is disabled (main oscillator is source)
0 = Oscillator system clock switch option is enabled (oscillator switching is enabled)
bit 4-3
Unimplemented: Read as ’0’
bit 2-0
FOSC2:FOSC0: Oscillator Selection bits
111 = RC oscillator w/OSC2 configured as RA6
110 = HS oscillator with PLL enabled/Clock frequency = (4 x FOSC)
101 = EC oscillator w/OSC2 configured as RA6
100 = EC oscillator w/OSC2 configured as divide-by-4 clock output
011 = RC oscillator
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
REGISTER 18-2:
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
CONFIGURATION REGISTER 1 LOW (CONFIG1L: BYTE ADDRESS 300000h)
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
CP
CP
CP
CP
CP
CP
CP
CP
bit 7
bit 7-0
bit 0
CP: Code Protection bits (apply when in Code Protected Microcontroller mode)
1 = Program memory code protection off
0 = All of program memory code protected
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
DS39026D-page 180
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
1999-2013 Microchip Technology Inc.
PIC18CXX2
REGISTER 18-3:
CONFIGURATION REGISTER 2 HIGH (CONFIG2H: BYTE ADDRESS 300003h)
U-0
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
—
—
—
—
WDTPS2
WDTPS1
WDTPS0
WDTEN
bit 7
bit 0
bit 7-4
Unimplemented: Read as ’0’
bit 3-1
WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits
111 = 1:1
110 = 1:2
101 = 1:4
100 = 1:8
011 = 1:16
010 = 1:32
001 = 1:64
000 = 1:128
bit 0
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
REGISTER 18-4:
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
CONFIGURATION REGISTER 2 LOW (CONFIG2L: BYTE ADDRESS 300002h)
U-0
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
—
—
—
—
BORV1
BORV0
BOREN
PWRTEN
bit 7
bit 0
bit 7-4
Unimplemented: Read as ’0’
bit 3-2
BORV1:BORV0: Brown-out Reset Voltage bits
11 = VBOR set to 2.5V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR set to 4.5V
bit 1
BOREN: Brown-out Reset Enable bit(1)
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
Note:
bit 0
Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT),
regardless of the value of bit PWRTEN. Ensure the Power-up Timer is enabled any
time Brown-out Reset is enabled.
PWRTEN: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
Note:
Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT),
regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled any
time Brown-out Reset is enabled.
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
1999-2013 Microchip Technology Inc.
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
DS39026D-page 181
PIC18CXX2
REGISTER 18-5:
CONFIGURATION REGISTER 3 HIGH (CONFIG3H: BYTE ADDRESS 300005h)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/P-1
—
—
—
—
—
—
—
CCP2MX
bit 7
bit 0
bit 7-1
Unimplemented: Read as ’0’
bit 0
CCP2MX: CCP2 Mux bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
REGISTER 18-6:
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
CONFIGURATION REGISTER 4 LOW (CONFIG4L: BYTE ADDRESS 300006h)
U-0
U-0
U-0
U-0
U-0
U-0
R/P-1
R/P-1
—
—
—
—
—
—
Reserved
STVREN
bit 7
bit 0
bit 7-2
Unimplemented: Read as ’0’
bit 1
Reserved: Maintain this bit set
bit 0
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack Full/Underflow will cause RESET
0 = Stack Full/Underflow will not cause RESET
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
DS39026D-page 182
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
1999-2013 Microchip Technology Inc.
PIC18CXX2
18.2
Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT
will run, even if the clock on the OSC1/CLKI and OSC2/
CLKO/RA6 pins of the device has been stopped, for
example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the RCON register
will be cleared upon a WDT time-out.
The Watchdog Timer is enabled/disabled by a device
configuration bit. If the WDT is enabled, software execution may not disable this function. When the WDTEN
configuration bit is cleared, the SWDTEN bit enables/
disables the operation of the WDT.
REGISTER 18-7:
The WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
Values for the WDT postscaler may be assigned using
the configuration bits.
Note:
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out
and generating a device RESET condition.
Note:
When a CLRWDT instruction is executed
and the postscaler is assigned to the WDT,
the postscaler count will be cleared, but the
postscaler assignment is not changed.
18.2.1
CONTROL REGISTER
Register 18-7 shows the WDTCON register. This is a
readable and writable register, which contains a control
bit that allows software to override the WDT enable
configuration bit, only when the configuration bit has
disabled the WDT.
WDTCON REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
SWDTEN
bit 7
bit 0
bit 7-1
Unimplemented: Read as ’0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is turned off if the WDTEN configuration bit in the configuration
register = ’0’
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset
1999-2013 Microchip Technology Inc.
DS39026D-page 183
PIC18CXX2
18.2.2
WDT POSTSCALER
The WDT has a postscaler that can extend the WDT
Reset period. The postscaler is selected at the time of
device programming, by the value written to the
CONFIG2H configuration register.
FIGURE 18-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDT Timer
Postscaler
8
8 - to - 1 MUX
WDTEN
Configuration bit
WDTPS2:WDTPS0
SWDTEN bit
WDT
Time-out
Note:
TABLE 18-2:
WDPS2:WDPS0 are bits in register CONFIG2H.
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
CONFIG2H
RCON
WDTCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
—
WDTPS2
WDTPS2
WDTPS0
WDTEN
IPEN
LWRT
—
RI
TO
PD
POR
BOR
—
—
—
—
—
—
—
SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
DS39026D-page 184
1999-2013 Microchip Technology Inc.
PIC18CXX2
18.3
Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared, but
keeps running, the PD bit (RCON) is cleared, the
TO (RCON) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
18.3.1
WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1.
2.
3.
External RESET input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change, or a
Peripheral Interrupt.
The following peripheral interrupts can wake the device
from SLEEP:
1.
2.
3.
4.
5.
6.
7.
8.
9.
PSP read or write.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
TMR3 interrupt. Timer3 must be operating as an
asynchronous counter.
CCP capture mode interrupt.
Special event trigger (Timer1 in Asynchronous
mode using an external clock).
MSSP (START/STOP) bit detect interrupt.
MSSP transmit or receive in Slave mode
(SPI/I2C).
USART RX or TX (Synchronous Slave mode).
A/D conversion (when A/D clock source is RC).
When the SLEEP instruction is being executed, the next
instruction (PC + 2) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
18.3.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If an interrupt condition (interrupt flag bit and interrupt enable bits are set) occurs before the execution of a SLEEP instruction, the SLEEP instruction
will complete as a NOP. Therefore, the WDT and
WDT postscaler will not be cleared, the TO bit will
not be set and PD bits will not be cleared.
• If the interrupt condition occurs during or after
the execution of a SLEEP instruction, the device
will immediately wake up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and will cause a “wake-up”. The TO and PD
bits in the RCON register can be used to determine the
cause of the device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared, if a WDT time-out occurred (and caused
wake-up).
1999-2013 Microchip Technology Inc.
DS39026D-page 185
PIC18CXX2
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
FIGURE 18-2:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF Flag
(INTCON)
Interrupt Latency(3)
GIEH bit
(INTCON)
Processor in
SLEEP
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note 1:
2:
3:
4:
18.4
PC
PC+2
Inst(PC) = SLEEP
Inst(PC + 2)
Inst(PC + 4)
SLEEP
Inst(PC + 2)
Inst(PC - 1)
PC+4
18.5
PC + 4
Dummy cycle
0008h
000Ah
Inst(0008h)
Inst(000Ah)
Dummy cycle
Inst(0008h)
XT, HS or LP oscillator mode assumed.
GIE = '1' assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
TOST = 1024TOSC (drawing not to scale) This delay will not occur for RC and EC osc modes.
CLKOUT is not available in these osc modes, but shown here for timing reference.
Program Verification/Code
Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
Note:
PC+4
Microchip Technology does not recommend code protecting windowed devices.
ID Locations
18.6
In-Circuit Serial Programming
PIC18CXXX microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firmware to be programmed.
Five memory locations (200000h - 200004h) are designated as ID locations, where the user can store checksum or other code identification numbers. These
locations are accessible during normal execution
through the TBLRD instruction or during program/verify.
The ID locations can be read when the device is code
protected.
DS39026D-page 186
1999-2013 Microchip Technology Inc.
PIC18CXX2
19.0
INSTRUCTION SET SUMMARY
The PIC18CXXX instruction set adds many enhancements to the previous PIC instruction sets, while maintaining an easy migration from these PIC MCU
instruction sets.
Most instructions are a single program memory word
(16-bits), but there are three instructions that require
two program memory locations.
Each single word instruction is a 16-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
•
•
•
•
Byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
The PIC18CXXX instruction set summary in Table 19-2
lists byte-oriented, bit-oriented, literal and control
operations. Table 19-1 shows the opcode field descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.
The file register (specified by ‘f’)
The destination of the result (specified by ‘d’)
The accessed memory (specified by ‘a’)
The file register designator 'f' specifies which file register is to be used by the instruction.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If 'd' is zero, the
result is placed in the WREG register. If 'd' is one, the
result is placed in the file register specified in the
instruction.
All bit-oriented instructions have three operands:
1.
2.
3.
The file register (specified by ‘f’)
The bit in the file register (specified by ‘b’)
The accessed memory (specified by ‘a’)
The control instructions may use some of the following
operands:
• A program memory address (specified by ‘n’)
• The mode of the Call or Return instructions
(specified by ‘s’)
• The mode of the Table Read and Table Write
instructions (specified by ‘m’)
• No operand required (specified by ‘—’)
All instructions are a single word, except for three double word instructions. These three instructions were
made double word instructions so that all the required
information is available in these 32-bits. In the second
word, the 4 MSb’s are 1’s. If this second word is executed as an instruction (by itself), it will execute as a
NOP.
All single word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruction. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
The double word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two word branch instructions (if true) would take 3 s.
Figure 19-1 shows the general formats that the instructions can have.
All examples use the format ‘nnh’ to represent a
hexadecimal number, where ‘h’ signifies a hexadecimal digit.
The Instruction Set Summary, shown in Table 19-2,
lists the instructions recognized by the Microchip
assembler (MPASMTM).
Section 19.1 provides a description of each instruction.
The bit field designator 'b' selects the number of the bit
affected by the operation, while the file register designator 'f' represents the number of the file in which the
bit is located.
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required (specified by ‘—’)
1999-2013 Microchip Technology Inc.
DS39026D-page 187
PIC18CXX2
TABLE 19-1:
OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
Bit address within an 8-bit file register (0 to 7)
BSR
Bank Select Register. Used to select the current RAM bank.
d
Destination select bit;
d = 0: store result in WREG,
d = 1: store result in file register f.
dest
Destination either the WREG register or the specified register file location
f
8-bit Register file address (0x00 to 0xFF)
fs
12-bit Register file address (0x000 to 0xFFF). This is the source address.
fd
12-bit Register file address (0x000 to 0xFFF). This is the destination address.
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
label
Label name
mm
The mode of the TBLPTR register for the Table Read and Table Write instructions
Only used with Table Read and Table Write instructions:
*
No Change to register (such as TBLPTR with Table reads and writes)
*+
Post-Increment register (such as TBLPTR with Table reads and writes)
*-
Post-Decrement register (such as TBLPTR with Table reads and writes)
Pre-Increment register (such as TBLPTR with Table reads and writes)
+*
n
The relative address (2’s complement number) for relative branch instructions, or the direct address for
Call/Branch and Return instructions
PRODH
Product of Multiply high byte
PRODL
Product of Multiply low byte
s
Fast Call/Return mode select bit.
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
u
Unused or Unchanged
WREG
Working register (accumulator)
x
Don't care (0 or 1)
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.
TBLPTR
21-bit Table Pointer (points to a Program Memory location)
TABLAT
8-bit Table Latch
TOS
Top-of-Stack
PC
Program Counter
PCL
Program Counter Low Byte
PCH
Program Counter High Byte
PCLATH
Program Counter High Byte Latch
PCLATU
Program Counter Upper Byte Latch
GIE
Global Interrupt Enable bit
WDT
Watchdog Timer
TO
Time-out bit
PD
Power-down bit
C, DC, Z, OV, N
ALU status bits Carry, Digit Carry, Zero, Overflow, Negative
[
]
Optional
(
)
Contents
Assigned to
< >
Register bit field
In the set of
italics
User defined term (font is courier)
DS39026D-page 188
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 19-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15
10
9 8 7
OPCODE d
a
Example Instruction
0
ADDWF MYREG, W, B
f (FILE #)
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
OPCODE
15
0
f (Source FILE #)
12 11
MOVFF MYREG1, MYREG2
0
f (Destination FILE #)
1111
f = 12-bit file register address
Bit-oriented file register operations
15
12 11
9 8 7
OPCODE b (BIT #) a
0
BSF MYREG, bit, B
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
OPCODE
0
MOVLW 0x7F
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
OPCODE
15
0
GOTO Label
n (literal)
12 11
0
n (literal)
1111
n = 20-bit immediate value
15
8 7
OPCODE
15
S
0
CALL MYFUNC
n (literal)
12 11
0
n (literal)
S = Fast bit
15
11 10
OPCODE
15
OPCODE
1999-2013 Microchip Technology Inc.
0
BRA MYFUNC
n (literal)
8 7
n (literal)
0
BC MYFUNC
DS39026D-page 189
PIC18CXX2
TABLE 19-2:
PIC18CXXX INSTRUCTION SET
Mnemonic,
Operands
16-bit Instruction Word
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
1
f, d, a Add WREG and f
0010 01da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and Carry bit to f
1
0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF
1
f, d, a AND WREG with f
1,2
0001 01da ffff ffff Z, N
Clear f
CLRF
1
f, a
2
0110 101a ffff ffff Z
COMF
1
f, d, a Complement f
1, 2
0001 11da ffff ffff Z, N
Compare f with WREG, skip =
CPFSEQ
1 (2 or 3) 0110 001a ffff ffff None
f, a
4
Compare f with WREG, skip >
CPFSGT
1 (2 or 3) 0110 010a ffff ffff None
f, a
4
Compare f with WREG, skip <
CPFSLT
1 (2 or 3) 0110 000a ffff ffff None
f, a
1, 2
DECF
1
f, d, a Decrement f
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ
1 (2 or 3) 0010 11da ffff ffff None
f, d, a Decrement f, Skip if 0
1, 2, 3, 4
DCFSNZ
1 (2 or 3) 0100 11da ffff ffff None
f, d, a Decrement f, Skip if Not 0
1, 2
INCF
1
f, d, a Increment f
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ
1 (2 or 3) 0011 11da ffff ffff None
f, d, a Increment f, Skip if 0
4
INFSNZ
1 (2 or 3) 0100 10da ffff ffff None
f, d, a Increment f, Skip if Not 0
1, 2
IORWF
1
f, d, a Inclusive OR WREG with f
1, 2
0001 00da ffff ffff Z, N
MOVF
1
f, d, a Move f
1
0101 00da ffff ffff Z, N
MOVFF
2
fs, fd Move fs (source) to 1st word
1100 ffff ffff ffff None
fd (destination)2nd word
1111 ffff ffff ffff
f, a
Move WREG to f
MOVWF
1
0110 111a ffff ffff None
f, a
Multiply WREG with f
MULWF
1
0000 001a ffff ffff None
f, a
Negate f
NEGF
1
0110 110a ffff ffff C, DC, Z, OV, N 1, 2
f, d, a Rotate Left f through Carry
RLCF
1
0011 01da ffff ffff C, Z, N
f, d, a Rotate Left f (No Carry)
RLNCF
1
1, 2
0100 01da ffff ffff Z, N
f, d, a Rotate Right f through Carry
RRCF
1
0011 00da ffff ffff C, Z, N
f, d, a Rotate Right f (No Carry)
RRNCF
1
0100 00da ffff ffff Z, N
f, a
Set f
SETF
1
0110 100a ffff ffff None
SUBFWB f, d, a Subtract f from WREG with
1
0101 01da ffff ffff C, DC, Z, OV, N 1, 2
borrow
f, d, a Subtract WREG from f
SUBWF
1
0101 11da ffff ffff C, DC, Z, OV, N
SUBWFB f, d, a Subtract WREG from f with
1
0101 10da ffff ffff C, DC, Z, OV, N 1, 2
borrow
f, d, a Swap nibbles in f
SWAPF
1
4
0011 10da ffff ffff None
f, a
Test f, skip if 0
TSTFSZ
1 (2 or 3) 0110 011a ffff ffff None
1, 2
f, d, a Exclusive OR WREG with f
XORWF
1
0001 10da ffff ffff Z, N
BIT-ORIENTED FILE REGISTER OPERATIONS
1, 2
BCF
f, b, a Bit Clear f
1
1001 bbba ffff ffff None
1, 2
BSF
f, b, a Bit Set f
1
1000 bbba ffff ffff None
3, 4
BTFSC
f, b, a Bit Test f, Skip if Clear
1 (2 or 3) 1011 bbba ffff ffff None
3, 4
BTFSS
f, b, a Bit Test f, Skip if Set
1 (2 or 3) 1010 bbba ffff ffff None
1, 2
BTG
f, d, a Bit Toggle f
1
0111 bbba ffff ffff None
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39026D-page 190
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 19-2:
Mnemonic,
Operands
PIC18CXXX INSTRUCTION SET (CONTINUED)
16-bit Instruction Word
Description
CONTROL OPERATIONS
BC
n
Branch if Carry
BN
n
Branch if Negative
BNC
n
Branch if Not Carry
BNN
n
Branch if Not Negative
BNOV
n
Branch if Not Overflow
BNZ
n
Branch if Not Zero
BOV
n
Branch if Overflow
BRA
n
Branch Unconditionally
BZ
n
Branch if Zero
CALL
n, s
Call subroutine1st word
2nd word
CLRWDT —
Clear Watchdog Timer
DAW
—
Decimal Adjust WREG
GOTO
n
Go to address1st word
2nd word
NOP
—
No Operation
NOP
—
No Operation (Note 4)
POP
—
Pop top of return stack (TOS)
PUSH
—
Push top of return stack (TOS)
RCALL
n
Relative Call
RESET
Software device RESET
RETFIE
s
Return from interrupt enable
Cycles
MSb
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2
1
1
2
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
LSb
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
Status
Affected
Notes
None
None
None
None
None
None
None
None
None
None
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
RETLW
k
Return with literal in WREG
2
0000 1100 kkkk kkkk None
RETURN
s
Return from Subroutine
2
0000 0000 0001 001s None
SLEEP
—
Go into standby mode
1
0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
1999-2013 Microchip Technology Inc.
1
1
1
1
2
1
2
DS39026D-page 191
PIC18CXX2
TABLE 19-2:
PIC18CXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
16-bit Instruction Word
Description
Cycles
MSb
LSb
Status
Affected
Notes
LITERAL OPERATIONS
ADDLW
k
Add literal and WREG
1
0000 1111 kkkk
kkkk C, DC, Z, OV, N
ANDLW
k
AND literal with WREG
1
0000 1011 kkkk
kkkk Z, N
IORLW
k
Inclusive OR literal with WREG 1
0000 1001 kkkk
kkkk Z, N
LFSR
f, k
Move literal (12-bit) 2nd word
2
1110 1110 00ff
kkkk None
to FSRx 1st word
1111 0000 kkkk
kkkk
MOVLB
k
Move literal to BSR
1
0000 0001 0000
kkkk None
MOVLW
k
Move literal to WREG
1
0000 1110 kkkk
kkkk None
MULLW
k
Multiply literal with WREG
1
0000 1101 kkkk
kkkk None
RETLW
k
Return with literal in WREG
2
0000 1100 kkkk
kkkk None
SUBLW
k
Subtract WREG from literal
1
0000 1000 kkkk
kkkk C, DC, Z, OV, N
XORLW
k
Exclusive OR literal with WREG 1
0000 1010 kkkk
kkkk Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
1000 None
TBLRD*
Table Read
2
0000 0000 0000
1001 None
TBLRD*+
Table Read with post-increment
0000 0000 0000
1010 None
TBLRD*Table Read with post-decrement
0000 0000 0000
1011 None
TBLRD+*
Table Read with pre-increment
0000 0000 0000
1100 None
TBLWT*
Table Write
2 (5)
0000 0000 0000
1101 None
TBLWT*+
Table Write with post-increment
0000 0000 0000
1110 None
TBLWT*Table Write with post-decrement
0000 0000 0000
1111 None
TBLWT+*
Table Write with pre-increment
0000 0000 0000
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39026D-page 192
1999-2013 Microchip Technology Inc.
PIC18CXX2
19.1
Instruction Set
ADDLW
ADD literal to WREG
ADDWF
ADD WREG to f
Syntax:
[ label ] ADDLW
Syntax:
[ label ] ADDWF
Operands:
0 k 255
Operands:
Operation:
(WREG) + k WREG
Status Affected:
N,OV, C, DC, Z
0 f 255
d [0,1]
a [0,1]
Operation:
(WREG) + (f) dest
Status Affected:
N,OV, C, DC, Z
Encoding:
Description:
0000
1
Cycles:
1
Q Cycle Activity:
Q1
Example:
kkkk
kkkk
The contents of WREG are added
to the 8-bit literal 'k' and the result is
placed in WREG.
Words:
Decode
1111
k
Q2
Q3
Q4
Read
literal 'k'
Process
Data
Write to
WREG
ADDLW
0x15
Before Instruction
Encoding:
0010
01da
f [,d [,a] f [,d [,a]
ffff
ffff
Description:
Add WREG to register 'f'. If 'd' is 0,
the result is stored in WREG. If 'd'
is 1, the result is stored back in register 'f' (default). If ‘a’ is 0, the
Access Bank will be selected. If ‘a’
is 1, the BSR is used.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
WREG = 0x10
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
ADDWF
REG, 0, 0
After Instruction
WREG = 0x25
Example:
Before Instruction
WREG
REG
=
=
0x17
0xC2
After Instruction
WREG
REG
1999-2013 Microchip Technology Inc.
=
=
0xD9
0xC2
DS39026D-page 193
PIC18CXX2
ADDWFC
ADD WREG and Carry bit to f
ANDLW
AND literal with WREG
Syntax:
[ label ] ADDWFC
Syntax:
[ label ] ANDLW
Operands:
0 f 255
d [0,1]
a [0,1]
f [,d [,a]
Operation:
(WREG) + (f) + (C) dest
Status Affected:
N,OV, C, DC, Z
Encoding:
0010
Description:
ffff
1
Cycles:
1
Operands:
0 k 255
Operation:
(WREG) .AND. k WREG
Status Affected:
N,Z
Encoding:
ffff
Add WREG, the Carry Flag and data
memory location 'f'. If 'd' is 0, the
result is placed in WREG. If 'd' is 1,
the result is placed in data memory
location 'f'. If ‘a’ is 0, the Access
Bank will be selected. If ‘a’ is 1, the
BSR will not be overridden.
Words:
0000
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
ADDWFC
kkkk
kkkk
The contents of WREG are ANDed
with the 8-bit literal 'k'. The result is
placed in WREG.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read literal
'k'
Process
Data
Write to
WREG
ANDLW
0x5F
Before Instruction
WREG
=
0xA3
After Instruction
WREG
Example:
1011
Description:
Example:
Q Cycle Activity:
Q1
Decode
00da
k
=
0x03
REG, 0, 1
Before Instruction
Carry bit= 1
REG
=
0x02
WREG
=
0x4D
After Instruction
Carry bit= 0
REG
=
0x02
WREG
=
0x50
DS39026D-page 194
1999-2013 Microchip Technology Inc.
PIC18CXX2
ANDWF
AND WREG with f
Syntax:
[ label ] ANDWF
Operands:
0 f 255
d [0,1]
a [0,1]
f [,d [,a]
Operation:
(WREG) .AND. (f) dest
Status Affected:
N,Z
Encoding:
0001
BC
Branch if Carry
Syntax:
[ label ] BC
Operands:
-128 n 127
Operation:
if carry bit is ’1’
(PC) + 2 + 2n PC
Status Affected:
None
Encoding:
01da
ffff
ffff
1110
n
0010
nnnn
nnnn
Description:
Description:
The contents of WREG are AND’ed
with register 'f'. If 'd' is 0, the result
is stored in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected. If ‘a’ is 1, the
BSR will not be overridden
(default).
If the Carry bit is ’1’, then the program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
Example:
ANDWF
REG, 0, 0
Before Instruction
WREG
REG
=
=
0x17
0xC2
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Decode
After Instruction
WREG
REG
=
=
0x02
0xC2
Q2
Q3
Q4
Read literal
'n'
Process
Data
No
operation
Example:
HERE
BC
5
Before Instruction
PC
=
address (HERE)
=
=
=
1;
address (HERE+12)
0;
address (HERE+2)
After Instruction
If Carry
PC
If Carry
PC
1999-2013 Microchip Technology Inc.
DS39026D-page 195
PIC18CXX2
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 f 255
0b7
a [0,1]
Operation:
0 f
Status Affected:
None
Encoding:
1001
Description:
Branch if Negative
Syntax:
[ label ] BN
Operands:
-128 n 127
Operation:
if negative bit is ’1’
(PC) + 2 + 2n PC
Status Affected:
None
Encoding:
bbba
ffff
ffff
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write
register 'f'
Example:
BCF
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
FLAG_REG,
1110
n
0110
nnnn
nnnn
Description:
If the Negative bit is ’1’, then the
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Bit 'b' in register 'f' is cleared. If ‘a’
is 0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
Decode
f,b[,a]
BN
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
7, 0
If No Jump:
Q1
Decode
Example:
Q2
Q3
Q4
Read literal
'n'
Process
Data
No
operation
HERE
BN
Jump
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative =
PC
=
If Negative
PC
=
DS39026D-page 196
1;
address (Jump)
0;
address (HERE+2)
1999-2013 Microchip Technology Inc.
PIC18CXX2
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
[ label ] BNC
Syntax:
[ label ] BNN
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if carry bit is ’0’
(PC) + 2 + 2n PC
Operation:
if negative bit is ’0’
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
n
0011
nnnn
nnnn
Encoding:
1110
n
0111
nnnn
nnnn
Description:
If the Carry bit is ’0’, then the program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Description:
If the Negative bit is ’0’, then the
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
Write to PC
Decode
Read literal
'n'
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Read literal
'n'
Process
Data
No
operation
If No Jump:
Q1
Decode
Example:
HERE
BNC
Jump
Before Instruction
PC
Decode
Example:
Q2
Q3
Q4
Read literal
'n'
Process
Data
No
operation
HERE
BNN
Jump
Before Instruction
=
address (HERE)
After Instruction
If Carry
PC
If Carry
PC
If No Jump:
Q1
PC
=
address (HERE)
After Instruction
=
=
=
0;
address (Jump)
1;
address (HERE+2)
1999-2013 Microchip Technology Inc.
If Negative
PC
=
If Negative =
PC
=
0;
address (Jump)
1;
address (HERE+2)
DS39026D-page 197
PIC18CXX2
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
[ label ] BNOV
Syntax:
[ label ] BNZ
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if overflow bit is ’0’
(PC) + 2 + 2n PC
Operation:
if zero bit is ’0’
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
n
0101
nnnn
nnnn
Encoding:
1110
n
0001
nnnn
nnnn
Description:
If the Overflow bit is ’0’, then the
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Description:
If the Zero bit is ’0’, then the program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
Write to PC
Decode
Read literal
'n'
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Read literal
'n'
Process
Data
No
operation
If No Jump:
Q1
Decode
Example:
HERE
BNOV Jump
Before Instruction
PC
Decode
Example:
Q2
Q3
Q4
Read literal
'n'
Process
Data
No
operation
HERE
BNZ
Jump
Before Instruction
=
address (HERE)
After Instruction
If Overflow =
PC
=
If Overflow
PC
=
DS39026D-page 198
If No Jump:
Q1
PC
=
address (HERE)
=
=
=
0;
address (Jump)
1;
address (HERE+2)
After Instruction
0;
address (Jump)
1;
address (HERE+2)
If Zero
PC
If Zero
PC
1999-2013 Microchip Technology Inc.
PIC18CXX2
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
[ label ] BRA
Syntax:
[ label ] BSF
Operands:
-1024 n 1023
Operands:
Operation:
(PC) + 2 + 2n PC
Status Affected:
None
0 f 255
0b7
a [0,1]
Operation:
1 f
Status Affected:
None
Encoding:
Description:
1101
1
Cycles:
2
Q Cycle Activity:
Q1
No
operation
0nnn
nnnn
nnnn
Add the 2’s complement number
’2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a twocycle instruction.
Words:
Decode
n
Q2
Q3
Q4
Read literal
'n'
Process
Data
Write to PC
No
operation
No
operation
No
operation
Encoding:
HERE
BRA
PC
=
address (HERE)
1
Cycles:
1
Q Cycle Activity:
Q1
PC
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write
register 'f'
BSF
=
FLAG_REG, 7, 1
Before Instruction
0x0A
After Instruction
FLAG_REG=
After Instruction
ffff
Words:
FLAG_REG=
Before Instruction
ffff
Bit 'b' in register 'f' is set. If ‘a’ is 0
Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
Decode
Jump
bbba
Description:
Example:
Example:
1000
f,b[,a]
0x8A
address (Jump)
1999-2013 Microchip Technology Inc.
DS39026D-page 199
PIC18CXX2
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSC f,b[,a]
Syntax:
[ label ] BTFSS f,b[,a]
Operands:
0 f 255
0b7
a [0,1]
Operands:
0 f 255
0b
工商网监
湘ICP备2023018690号
