39541a.book Page 1 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
High-Performance ROM-less Microcontrollers
with External Memory Bus
High Performance RISC CPU:
Advanced Analog Features:
• C compiler optimized architecture instruction set
• Linear program memory addressing up to 2 Mbytes
• Linear data memory addressing to 4 Kbytes
• 10-bit Analog-to-Digital Converter module (A/D)
with:
- Fast sampling rate
- Conversion available during SLEEP
- DNL = ±1 LSb, INL = ±1 LSb
- Up to 12 channels available
• Programmable Low Voltage Detection (LVD)
module
- Supports interrupt on Low Voltage Detection
External Program Memory
On-Chip
Device
PIC18C601
PIC18C801
Maximum
Addressing
(bytes)
Maximum
Single Word
Instructions
256K
2M
128K
1M
On-Chip
RAM (bytes)
1.5K
1.5K
• Up to 160 ns instruction cycle:
- DC - 25 MHz clock input
- 4 MHz - 6 MHz clock input with PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 8 x 8 Single Cycle Hardware Multiplier
Peripheral Features:
•
•
•
•
•
•
•
•
•
•
•
High current sink/source 25 mA/25 mA
Up to 47 I/O pins with individual direction control
Three external interrupt pins
Timer0 module: 8-bit/16-bit timer/counter with
8-bit programmable prescaler
Timer1 module: 16-bit timer/counter (time-base for
CCP)
Timer2 module: 8-bit timer/counter with 8-bit
period register
Timer3 module: 16-bit timer/counter
Secondary oscillator clock option - Timer1/Timer3
Two Capture/Compare/PWM (CCP) modules
CCP pins can be configured as:
- Capture input: 16-bit, max. resolution 10 ns
- Compare is 16-bit, max. resolution 160 ns (TCY)
- PWM output: PWM resolution is 1- to 10-bit
Max. PWM freq. @:
8-bit resolution = 99 kHz
10-bit resolution = 24.4 kHz
Master Synchronous Serial Port (MSSP) with two
modes of operation:
- 3-wire SPI™ (Supports all 4 SPI modes)
- I2C™ Master and Slave mode
Addressable USART module: Supports Interrupt
on Address bit
2001-2013 Microchip Technology Inc.
Special Microcontroller Features:
• Power-on Reset (POR), Power-up Timer (PWRT),
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator
• On-chip Boot RAM for boot loader application
• 8-bit or 16-bit external memory interface modes
• Up to two software programmable chip select signals (CS1 and CS2)
• One programmable chip I/O select signal (CSIO)
for memory mapped I/O expansion
• Power saving SLEEP mode
• Different oscillator options, including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
CMOS Technology:
•
•
•
•
•
Low power, high speed CMOS technology
Fully static design
Wide operating voltage range (2.0V to 5.5V)
Industrial and Extended temperature ranges
Low power consumption
Advance Information
DS39541B-page 1
39541a.book Page 2 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
Pin Diagrams
RD4/AD4
RD5/AD5
RD6/AD6
RD7/AD7
RE5/AD13
RE6/AD14
RE7/AD15
RD0/AD0
VDD
VSS
RD1/AD1
RD2/AD2
RD3/AD3
RE2/AD10
RE3/AD11
RE4/AD12
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RE1/AD9
1
48
RB0/INT0
RE0/AD8
2
47
RB1/INT1
RG0/ALE
3
46
RB2/INT2
RG1/OE
4
45
RB3/CCP2
RG2/WRL
5
44
RB4
RG3/WRH
6
43
RB5
MCLR/VPP
RG4/BA0
7
42
RB6
VSS
PIC18C601
8
41
VSS
9
40
OSC2/CLKO
VDD
10
39
OSC1/CLKI
RF7/UB
11
38
VDD
RF6/LB
12
37
RB7
RF5/CS1
13
36
RC5/SDO
RF4/A16
14
35
RC4/SDI/SDA
RF3/CSIO
15
34
RC3/SCK/SCL
RF2/AN7
16
33
RC2/CCP1
DS39541B-page 2
Advance Information
RC0/T1OSO/T13CKI
RC6/TX/CK
RC7/RX/DT
RA4/T0CKI
RC1/T1OSI
VDD
RA5/SS/AN4/LVDIN
RA0/AN0
VSS
AVSS
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1
RF0/AN5
AVDD
RF1/AN6
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2001-2013 Microchip Technology Inc.
39541a.book Page 3 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
Pin Diagrams (Cont.’d)
RE2/AD10
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/AD15
RD0/AD0
VDD
NC
VSS
RD1/AD1
RD2/AD2
RD3/AD3
RD4/AD4
RD5/AD5
RD6/AD6
RD7/AD7
68-Pin PLCC
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
RE1/AD9
RE0/AD8
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
MCLR/VPP
RG4/BA0
NC
VSS
VDD
RF7/UB
RF6/LB
RF5/CS1
RF4/A16
RF3/CSIO
RF2/AN7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PIC18C601
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RB5
RB6
VSS
NC
OSC2/CLKO
OSC1/CLKI
VDD
RB7
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
2001-2013 Microchip Technology Inc.
VDD
RA5/SS/AN4/LVDIN
RA4/T0CKI
RC1/T1OSI
RC0/T1OSO/T13CKI
RC6/TX/CK
RC7/RX/DT
RF1/AN6
RF0/AN5
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1
RA0/AN0
NC
VSS
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Advance Information
DS39541B-page 3
39541a.book Page 4 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
Pin Diagrams (Cont.’d)
RD4/AD4
RD5/AD5
RD6/AD6
RD7/AD7
RJ0/D7
RJ1/D6
RE5/AD13
RE6/AD14
RE7/AD15
RD0/AD0
VDD
VSS
RD1/AD1
RD2/AD2
RD3/AD3
RH1/A17
RH0/A16
RE2/AD10
RE3/AD11
RE4/AD12
80-Pin TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2/A18
1
60
RJ5/D5
RH3/A19
2
59
RE1/AD9
3
58
RJ4/D4
RB0/INT0
RE0/AD8
4
57
RB1/INT1
RG0/ALE
5
56
RB2/INT2
RG1/OE
6
55
RB3/CCP2
RG2/WRL
7
54
RB4
RG3/WRH
8
53
RB5
MCLR/VPP
9
52
RB6
RG4/BA0
10
51
VSS
VSS
11
50
OSC2/CLKO
VDD
12
49
OSC1/CLKI
RF7/UB
13
48
VDD
RF6/LB
14
47
RB7
RF5/CS1
15
46
RC5/SDO
RF4/CS2
16
45
RC4/SDI/SDA
RF3/CSIO
17
44
RC3/SCK/SCL
RF2/AN7
18
43
RC2/CCP1
RH4/AN8
19
42
RJ3/D3
RH5/AN9
20
41
RJ2/D2
PIC18C801
DS39541B-page 4
Advance Information
RJ0/D0
RJ1/D1
RC0/T1OSO/T13CKI
RC6/TX/CK
RC7/RX/DT
RA4/T0CKI
RC1/T1OSI
RA5/SS/AN4/LVDIN
RA1/AN1
RA0/AN0
VSS
VDD
RF0/AN5
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RF1/AN6
RH6/AN10
RH7/AN11
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
2001-2013 Microchip Technology Inc.
39541a.book Page 5 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
Pin Diagrams (Cont.’d)
RH1/A17
RH0/A16
RE2/AD10
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/AD15
RD0/AD0
VDD
NC
VSS
RD1/AD1
RD2/AD2
RD3/AD3
RD4/AD4
RD5/AD5
RD6/AD6
RD7/AD7
RJ7/D7
RJ6/D6
84-Pin PLCC
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
RH2/A18
RH3/A19
RE1/AD9
RE0/AD8
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
MCLR/VPP
RG4/BA0
NC
VSS
VDD
RF7/UB
RF6/LB
RF5/CS1
RF4/CS2
RF3/CSIO
RF2/AN7
RH4/AN8
RH5/AN9
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
PIC18C801
RJ5/D5
RJ4/D4
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RB5
RB6
VSS
NC
OSC2/CLKO
OSC1/CLKI
VDD
RB7
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RJ3/D3
RJ2/D2
2001-2013 Microchip Technology Inc.
Advance Information
RJ1/D1
RH6/AN10
RH7/AN11
RF1/AN6
RF0/AN5
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1
RA0/AN0
NC
VSS
VDD
RA5/SS/AN4/LVDIN
RA4/T0CKI
RC1/T1OSI
RC0/T1OSO/T13CKI
RC6/TX/CK
RC7/RX/DT
RJ0/D0
33 3435 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
DS39541B-page 5
39541a.book Page 6 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
Table of Contents
1.0
Device Overview.................................................................................................................................................. 9
2.0
Oscillator Configurations.................................................................................................................................... 21
3.0
RESET............................................................................................................................................................... 29
4.0
Memory Organization ........................................................................................................................................ 39
5.0
External Memory Interface................................................................................................................................. 63
6.0
Table Reads/Table Writes ................................................................................................................................. 73
7.0
8 X 8 Hardware Multiplier .................................................................................................................................. 85
8.0
Interrupts............................................................................................................................................................ 89
9.0
I/O Ports........................................................................................................................................................... 103
10.0 Timer0 Module................................................................................................................................................. 127
11.0 Timer1 Module................................................................................................................................................. 130
12.0 Timer2 Module................................................................................................................................................. 135
13.0 Timer3 Module................................................................................................................................................. 137
14.0 Capture/Compare/PWM (CCP) Modules......................................................................................................... 141
15.0 Master Synchronous Serial Port (MSSP) Module............................................................................................ 149
16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ..................................... 177
17.0 10-bit Analog-to-Digital Converter (A/D) Module ............................................................................................. 193
18.0 Low Voltage Detect.......................................................................................................................................... 203
19.0 Special Features of the CPU ........................................................................................................................... 207
20.0 Instruction Set Summary ................................................................................................................................. 215
21.0 Development Support ...................................................................................................................................... 259
22.0 Electrical Characteristics ................................................................................................................................. 265
23.0 DC and AC Characteristics Graphs and Tables .............................................................................................. 295
24.0 Packaging Information ..................................................................................................................................... 297
Appendix A: Data Sheet Revision History.................................................................................................................. 303
Appendix B: Device Differences ................................................................................................................................ 303
Appendix C: Device Migrations .................................................................................................................................. 304
Appendix D: Migrating from other PICmicro Devices ................................................................................................. 304
Appendix E: Development Tool Version Requirements ............................................................................................. 305
Index ........................................................................................................................................................................... 307
On-Line Support .......................................................................................................................................................... 315
Reader Response ....................................................................................................................................................... 316
Product Identification System...................................................................................................................................... 317
DS39541B-page 6
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 7 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Customer Notification System
Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 7
39541a.book Page 8 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
NOTES:
DS39541B-page 8
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 9 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
1.0
DEVICE OVERVIEW
An overview of features is shown in Table 1-1.
This document contains device specific information for
the following two devices:
1.
2.
PIC18C601
PIC18C801
Device block diagrams are provided in Figure 1-1 for
the 64/68-pin configuration, and Figure 1-2 for the 80/
84-pin configuration. The pinouts for both packages
are listed in Table 1-2.
The PIC18C601 is available in 64-pin TQFP and 68-pin
PLCC packages. The PIC18C801 is available in 80-pin
TQFP and 84-pin PLCC packages.
TABLE 1-1:
DEVICE FEATURES
Features
Operating Frequency
External
Program Memory
PIC18C601
PIC18C801
DC - 25 MHz
DC - 25 MHz
Bytes
256K
2M
Max. # of Single Word
Instructions
128K
1M
1536
1536
Data Memory (Bytes)
Interrupt Sources
15
15
Ports A - G
Ports A - H, J
Timers
4
4
Capture/Compare/PWM modules
2
2
MSSP,
Addressable USART
MSSP,
Addressable USART
8 input channels
12 input channels
POR,
RESET Instruction, Stack Full,
Stack Underflow (PWRT, OST)
POR,
RESET Instruction, Stack Full,
Stack Underflow (PWRT, OST)
I/O Ports
Serial Communications
10-bit Analog-to-Digital Module
RESETS (and Delays)
Programmable Low Voltage Detect
Yes
Yes
8-bit External Memory Interface
Yes
Yes
8-bit De-multiplexed External
Memory Interface
No
Yes
16-bit External Memory Interfaces
Yes
Yes
On-chip Chip Select Signals
CS1
CS1, CS2
On-chip I/O Chip Select Signal
Instruction Set
Packages
2001-2013 Microchip Technology Inc.
Yes
Yes
75 Instructions
75 Instructions
64-pin TQFP
68-pin PLCC
80-pin TQFP
84-pin PLCC
Advance Information
DS39541B-page 9
39541a.book Page 10 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 1-1:
PIC18C601 BLOCK DIAGRAM
Data Bus
AD7:AD0
Table Pointer
21
21
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
Data Latch
5
8
8
Data RAM
1 Kbyte
inc/dec logic
Address Latch
20
PCLATU PCLATH
System Bus Interface
PCU PCH PCL
Program Counter
12
4
BSR
Program Memory
(up to 256 Kbytes)
PORTB
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RB5
RB6
RB7
12
Address
21
Address Latch
PORTA
31 Level Stack
Data Latch
4
Bank0,F
FSR0
FSR1
FSR2
12
PORTC
16
Decode
Table Latch
inc/dec
logic
RC0/T1OSO/T13CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
8
ROM Latch
IR
A16, AD15:AD8
OSC2/CLKO
OSC1/CLKI
RD7:RD0/AD7:AD0
PRODH PRODL
3
Timing
Generation
T1OSI
T1OSO
PORTD
8
Instruction
Decode &
Control
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Low Voltage
Detect
MCLR
8 x 8 Multiply
8
PORTE
BITOP
8
WREG
8
8
RE7:RE0/AD15:AD8
8
ALU
PORTF
8
RF0/AN5
RF1/AN6
RF2/AN7
RF3/CSIO
RF4/A16
RF5/CS1
RF6/LB
RF7/UB
VDD, VSS
PORTG
Timer0
Timer1
Timer2
CCP1
CCP2
Synchronous
Serial Port
Timer3
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
RG4/BA0
USART1
10-bit A/D
DS39541B-page 10
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 11 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 1-2:
PIC18C801 BLOCK DIAGRAM
Data Bus
AD7:AD0
TablePointer
21
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
Data Latch
5
21
8
8
Data RAM
1 Kbyte
inc/dec logic
PORTB
Address Latch
20
PCLATU PCLATH
System Bus Interface
PCU PCH PCL
Program Counter
12
4
BSR
Program Memory
(up to 2 Mbytes)
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RB5
RB6
RB7
12
Address
21
Address Latch
PORTA
31 Level Stack
Data Latch
16
Decode
Table Latch
4
Bank0,F
FSR0
FSR1
FSR2
12
PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
inc/dec
logic
8
ROM Latch
IR
PORTD
A19:A16, AD15:AD0
8
Instruction
Decode &
Control
OSC2/CLKO
OSC1/CLKI
T1OSI
T1OSO
RD7:RD0/AD7:AD0
PRODH PRODL
3
Timing
Generation
Power-up
Timer
Oscillator
Start-upTimer
Power-on
Reset
Watchdog
Timer
Low Voltage
Detect
MCLR
PORTE
8 x 8 Multiply
8
BITOP
8
WREG
8
RE7:RE0/AD15:AD8
8
PORTF
8
RF0/AN5
RF1/AN6
RF2/AN7
RF3/CSIO
RF4/CS2
RF5/CS1
RF6/LB
RF7/UB
ALU
8
VDD, VSS
PORTG
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
RG4/BA0
Timer0
Timer1
Timer2
Timer3
PORTH
RH3:RH0/A19:A16
RH4/AN8
RH5/AN9
RH6/AN10
RH7/AN11
CCP1
CCP2
Synchronous
Serial Port
USART1
PORTJ
RJ7:RJ0/D7:D0
10-bit A/D
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 11
39541a.book Page 12 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
PIC18C601
MCLR/VPP
MCLR
PIC18C801
TQFP
PLCC
TQFP
PLCC
7
16
9
20
VPP
NC
—
OSC1/CLKI
OSC1
39
1, 18,
35, 52
50
—
49
1, 22,
43, 64
62
CLKI
OSC2/CLKO
OSC2
40
51
50
TTL =
ST =
I
=
P =
TTL compatible input
Schmitt Trigger input with CMOS levels
Input
Power
DS39541B-page 12
Buffer
Type
Description
I
ST
Master clear (RESET) input. This pin is
an active low RESET to the device.
Programming voltage input.
These pins should be left
unconnected.
P
—
—
I
CMOS/ST
I
CMOS
O
—
O
—
Oscillator crystal input or external clock
source input. ST buffer when in RC
mode. Otherwise CMOS.
External clock source input.
Always associated with pin function
OSC1 (see OSC1/CLKI, OSC2/CLKO
pins).
63
CLKO
Legend:
Pin
Type
CMOS
Analog
O
OD
=
=
=
=
Oscillator crystal output.
Connects to crystal or resonator in
Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO,
which has 1/4 the
frequency of OSC1 and denotes the
instruction cycle rate.
CMOS compatible input or output
Analog input
Output
Open Drain (no P diode to VDD)
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 13 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PIC18C601
PIC18C801
TQFP
PLCC
TQFP
PLCC
24
34
30
42
Pin
Type
Buffer
Type
Description
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/VREFRA2
AN2
VREFRA3/AN3/VREF+
RA3
AN3
VREF+
RA4/T0CKI
RA4
23
22
21
28
33
32
31
39
29
28
27
34
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
I/O
ST/OD
I
ST
Digital I/O – Open drain when
configured as output.
Timer0 external clock input.
41
40
39
47
T0CKI
27
38
33
46
RA5/AN4/SS/LVDIN
RA5
AN4
SS
LVDIN
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I
= Input
P = Power
2001-2013 Microchip Technology Inc.
I/O
I
I/O
I
I
I
TTL
Digital I/O.
Analog
Analog input 4.
ST
SPI slave select input.
Analog
Low voltage detect input.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
OD
= Open Drain (no P diode to VDD)
Advance Information
DS39541B-page 13
39541a.book Page 14 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PIC18C601
TQFP
PLCC
PIC18C801
TQFP
Pin
Type
Buffer
Type
PLCC
Description
PORTB is a bi-directional I/O port. PORTB
can be software programmed for internal
weak pull-ups on all inputs.
RB0/INT0
RB0
INT0
RB1/INT1
RB1
INT1
RB2/INT2
RB2
INT2
RB3/CCP2
RB3
CCP2
48
RB4
RB5
RB6
44
43
42
56
55
54
54
53
52
68
67
66
RB7
37
48
47
60
Legend:
TTL =
ST =
I
=
P =
47
46
45
60
59
58
57
58
57
56
55
72
TTL
ST
Digital I/O.
External interrupt 0.
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
I/O
I/O
TTL
ST
71
70
69
TTL compatible input
Schmitt Trigger input with CMOS levels
Input
Power
DS39541B-page 14
I/O
I
Digital I/O.
Capture2 input, Compare2 output,
PWM2 output.
I/O
TTL
Digital I/O, Interrupt-on-change pin.
I/O
TTL
Digital I/O, Interrupt-on-change pin.
I/O
TTL
Digital I/O, Interrupt-on-change pin.
I
ST
ICSP programming clock.
I/O
TTL
Digital I/O, Interrupt-on-change pin.
I/O
ST
ICSP programming data.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
OD
= Open Drain (no P diode to VDD)
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 15 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PIC18C601
PIC18C801
TQFP
PLCC
TQFP
PLCC
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
RC1/T1OSI
RC1
T1OSI
RC2/CCP1
RC2
CCP1
30
41
36
49
RC3/SCK/SCL
RC3
SCK
34
Pin
Type
Buffer
Type
Description
PORTC is a bi-directional I/O port.
29
33
40
44
45
35
43
44
35
RC5/SDO
RC5
SDO
RC6/TX/CK
RC6
TX
CK
RC7/RX/DT
RC7
RX
DT
Legend: TTL =
ST =
I
=
P =
36
31
32
46
47
42
43
45
46
37
38
—
ST
I/O
I
ST
CMOS
I/O
I/O
ST
ST
Digital I/O.
Capture1 input/Compare1
output/PWM1 output.
I/O
I/O
ST
ST
I/O
ST
Digital I/O.
Synchronous serial clock
input/output for SPI mode.
Synchronous serial clock
input/output for I2C mode.
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
ST
—
Digital I/O.
SPI data out.
I/O
O
I/O
ST
—
ST
Digital I/O.
USART asynchronous transmit.
USART synchronous clock.
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Digital I/O.
Timer1 oscillator input.
56
57
58
59
50
51
I/O
I
I/O
TTL compatible input
Schmitt Trigger input with CMOS levels
Input
Power
2001-2013 Microchip Technology Inc.
ST
48
SCL
RC4/SDI/SDA
RC4
SDI
SDA
I/O
O
I
ST
Digital I/O.
ST
USART asynchronous receive.
ST
USART synchronous data.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
OD
= Open Drain (no P diode to VDD)
Advance Information
DS39541B-page 15
39541a.book Page 16 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PIC18C601
TQFP
PLCC
PIC18C801
TQFP
Pin
Type
Buffer
Type
PLCC
Description
PORTD is a bi-directional I/O port. These
pins have TTL input buffers when external
memory is enabled.
RD0/AD0
RD0
AD0
RD1/AD1
RD1
AD1
RD2/AD2
RD2
AD2
RD3/AD3
RD3
AD3
RD4/AD4
RD4
AD4
RD5/AD5
RD5
AD5
RD6/AD6
RD6
AD6
RD7/AD7
RD7
AD7
Legend: TTL =
ST =
I
=
P =
58
55
54
53
52
51
50
49
3
67
66
65
64
63
62
61
72
69
68
67
66
65
64
63
3
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 0.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 1.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 2.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 3.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 4.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 5.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 6.
83
82
81
80
79
78
77
I/O
I/O
TTL compatible input
Schmitt Trigger input with CMOS levels
Input
Power
DS39541B-page 16
ST
Digital I/O.
TTL
External memory address/data 7.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
OD
= Open Drain (no P diode to VDD)
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 17 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PIC18C601
PIC18C801
TQFP
PLCC
TQFP
PLCC
2
11
4
15
Pin
Type
Buffer
Type
Description
PORTE is a bi-directional I/O port.
RE0/AD8
RE0
AD8
RE1/AD9
RE1
AD9
RE2/AD10
RE2
AD10
RE3/AD11
RE3
AD11
RE4/AD12
RE4
AD12
RE5/AD13
RE5
AD13
RE6/AD14
RE6
AD14
RE7/AD15
RE7
AD15
Legend: TTL =
ST =
I
=
P =
1
64
63
62
61
60
59
10
9
8
7
6
5
4
3
78
77
76
75
74
73
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 8.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 9.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 10.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 11.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 12.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 13.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 14.
14
9
8
7
6
5
4
I/O
I/O
TTL compatible input
Schmitt Trigger input with CMOS levels
Input
Power
2001-2013 Microchip Technology Inc.
ST
Digital I/O.
ST
External memory address/data 15.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
OD
= Open Drain (no P diode to VDD)
Advance Information
DS39541B-page 17
39541a.book Page 18 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PIC18C601
PIC18C801
TQFP
PLCC
TQFP
PLCC
18
28
24
36
Pin
Type
Buffer
Type
Description
PORTF is a bi-directional I/O port.
RF0/AN5
RF0
AN5
RF1/AN6
RF1
AN6
RF2/AN7
RF2
AN7
RF3/CSIO
RF3
CSIO
RF4/A16
RF4/CS2
RF4
A16
CS2
RF5/CS1
RF5
CS1
RF6/LB
RF6
LB
17
16
15
Legend:
25
18
17
—
—
16
28
11
22
21
14
13
ST
Analog
Digital I/O.
Analog input 6.
I/O
I
ST
Analog
Digital I/O.
Analog input 7.
I/O
I/O
ST
ST
Digital I/O.
System bus chip select I/O.
I/O
I/O
O
ST
TTL
TTL
Digital I/O.
External memory address 16.
Chip select 2.
I/O
O
ST
TTL
Digital I/O.
Chip select 1.
I/O
O
ST
TTL
Digital I/O.
Low byte select signal for external
memory interface.
I/O
O
ST
TTL
27
26
25
TTL compatible input
Schmitt Trigger input with CMOS levels
Input
Power
DS39541B-page 18
I/O
I
29
—
15
Digital I/O.
Analog input 5.
30
24
23
ST
Analog
35
—
12
TTL =
ST =
I
=
P =
26
23
14
13
RF7/UB
RF7
UB
27
I/O
I
CMOS
Analog
O
OD
=
=
=
=
Digital I/O.
High byte select signal for external
memory interface.
CMOS compatible input or output
Analog input
Output
Open Drain (no P diode to VDD)
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 19 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PIC18C601
PIC18C801
TQFP
PLCC
TQFP
PLCC
RG0/ALE
RG0
ALE
RG1/OE
RG1
OE
RG2/WRL
RG2
WRL
RG3/WRH
RG3
WRH
RG4/BA0
RG4
BA0
3
12
5
16
RH0/A16
RH0
A16
RH1/A17
RH1
A17
RH2/A18
RH2
A18
RH3/A19
RH3
A19
RH4/AN8
RH4
AN8
RH5/AN9
RH5
AN9
RH6/AN10
RH6
AN10
RH7/AN11
RH7
AN11
Legend: TTL =
ST =
I
=
P =
—
Pin
Type
Buffer
Type
Description
PORTG is a bi-directional I/O port.
4
5
6
8
—
—
—
—
—
—
—
13
14
15
17
—
—
—
—
—
—
—
—
6
7
8
10
79
80
1
2
19
20
21
22
I/O
O
ST
TTL
Digital I/O.
Address Latch Enable.
I/O
O
ST
TTL
Digital I/O.
Output Enable.
I/O
O
ST
TTL
Digital I/O.
Write Low control.
I/O
O
ST
TTL
Digital I/O.
Write High control.
I/O
O
ST
TTL
I/O
O
ST
TTL
Digital I/O.
External memory address 16.
I/O
O
ST
Digital I/O.
External memory address 17.
I/O
O
ST
I/O
O
ST
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
I/O
I
ST
Analog
Digital I/O.
Analog input 10.
17
18
19
21
10
11
—
12
—
Digital I/O.
External memory address 18.
13
—
Digital I/O.
External memory address 19.
31
32
33
34
I/O
I
TTL compatible input
Schmitt Trigger input with CMOS levels
Input
Power
2001-2013 Microchip Technology Inc.
Digital I/O.
System bus byte address 0.
PORTH is a bi-directional I/O port.
ST
Digital I/O.
Analog
Analog input 11.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
OD
= Open Drain (no P diode to VDD)
Advance Information
DS39541B-page 19
39541a.book Page 20 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PIC18C601
PIC18C801
TQFP
PLCC
TQFP
PLCC
—
—
39
52
Pin
Type
Buffer
Type
Description
PORTJ is a bi-directional I/O port.
RJ0/D0
RJ0
D0
RJ1/D1
RJ1
D1
RJ2/D2
RJ2
D2
RJ3/D3
RJ3
D3
RJ4/D4
RJ4
D4
RJ5/D5
RJ5
D5
RJ6/D6
RJ6
D6
RJ7/D7
RJ7
D7
VSS
—
—
—
—
—
—
—
VDD
AVSS
AVDD
Legend:
TTL =
ST =
I
=
P =
—
—
—
—
—
—
—
40
41
42
59
60
61
62
ST
TTL
Digital I/O.
System bus data bit 0.
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 1.
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 2.
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 3.
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 4.
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 5.
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 6.
I/O
I/O
P
ST
TTL
—
Digital I/O.
System bus data bit 7.
Ground reference for logic and I/O pins.
P
—
Positive supply for logic and I/O pins.
P
P
—
—
CMOS =
Analog =
O
=
OD
=
53
54
55
73
74
75
76
9, 25, 19, 36, 11,31, 23, 44,
41, 56 53, 68 51, 70 65, 84
10,26, 2, 20, 12,32, 2, 24,
38, 57 37, 49 48, 71 45, 61
20
30
26
38
19
29
25
37
TTL compatible input
Schmitt Trigger input with CMOS levels
Input
Power
DS39541B-page 20
I/O
I/O
Ground reference for analog modules.
Positive supply for analog modules.
CMOS compatible input or output
Analog input
Output
Open Drain (no P diode to VDD)
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 21 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
2.0
OSCILLATOR
CONFIGURATIONS
2.1
Oscillator Types
FIGURE 2-1:
PIC18C601/801 can be operated in one of four oscillator modes, programmable by configuration bits
FOSC1:FOSC0 in CONFIG1H register:
1.
2.
3.
4.
LP
HS
RC
EC
2.2
C1(1)
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS OR LP OSC
CONFIGURATION)
OSC1
XTAL
Low Power Crystal
High Speed Crystal/Resonator
External Resistor/Capacitor
External Clock
RS(2)
C2(1)
Crystal Oscillator/Ceramic
Resonators
OSC2
To
Internal
Logic
RF(3)
SLEEP
PIC18C601/801
Note 1: See Table 2-1 and Table 2-2 for recommended values of C1 and C2.
In LP or HS oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to
establish oscillation. Figure 2-1 shows the pin connections. An external clock source may also be connected
to the OSC1 pin, as shown in Figure 2-3 and Figure 2-4.
2: A series resistor (R S) may be required for AT
strip cut crystals.
3: RF varies with the crystal chosen.
PIC18C601/801 oscillator design requires the use of a
parallel cut crystal.
Note:
Use of a series cut crystal may give a frequency out of the crystal manufacturer’s
specifications.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 21
39541a.book Page 22 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 2-1:
CERAMIC RESONATORS
Ranges Tested:
Mode
Freq.
OSC1
OSC2
HS
8.0 MHz
10 - 68 pF
10 - 68 pF
16.0 MHz
10 - 22 pF
10 - 22 pF
20.0 MHz
TBD
TBD
25.0 MHz
TBD
TBD
HS+PLL 4.0 MHz
TBD
TBD
These values are for design guidance only.
See notes on this page.
Resonators Used:
4.0 MHz Murata Erie CSA4.00MG
0.5%
8.0 MHz Murata Erie CSA8.00MT
0.5%
16.0 MHz Murata Erie CSA16.00MX
0.5%
All resonators used did not have built-in capacitors.
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc Type
Crystal
Freq.
LP
32.0 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
HS
HS+PLL
Cap. Range
C1
Cap. Range
C2
4.0 MHz
15 pF
15 pF
8.0 MHz
15-33 pF
15-33 pF
20.0 MHz
15-33 pF
15-33 pF
25.0 MHz
TBD
TBD
4.0 MHz
15 pF
15 pF
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 2-1).
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components.
4: Rs may be required in HS mode to avoid
overdriving crystals with low drive level
specification.
2.3
For timing insensitive applications, the "RC" oscillator
mode offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C components used. Figure 2-2 shows how the RC combination
is connected.
In the RC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
FIGURE 2-2:
These values are for design guidance only.
See notes on this page.
Crystals Used
32.0 kHz
Epson C-001R32.768K-A
RC Oscillator
RC OSCILLATOR MODE
VDD
REXT
OSC1
± 20 PPM
200 kHz
STD XTL 200.000kHz
± 20 PPM
1.0 MHz
ECS ECS-10-13-1
± 50 PPM
4.0 MHz
ECS ECS-40-20-1
± 50 PPM
8.0 MHz
EPSON CA-301 8.000M-C
± 30 PPM
20.0 MHz EPSON CA-301 20.000M-C
± 30 PPM
CEXT
PIC18C601/801
VSS
FOSC/4
or I/O
Recommended values:
DS39541B-page 22
Internal
Clock
Advance Information
OSC2/CLKO
3 k REXT 100 k
CEXT > 20pF
2001-2013 Microchip Technology Inc.
39541a.book Page 23 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
2.4
External Clock Input
2.5
The EC oscillator mode requires an external clock
source to be connected to the OSC1 pin. The feedback
device between OSC1 and OSC2 is turned off in these
modes to save current. There is no oscillator start-up
time required after a Power-on Reset or after a
recovery from SLEEP mode.
In the EC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-3 shows the pin connections for the EC
oscillator mode.
FIGURE 2-3:
The PLL is enabled by configuring HS oscillator mode
and setting the PLLEN bit in the OSCON register. If HS
oscillator mode is not selected, or PLLEN bit in
OSCCON register is clear, the PLL is not enabled and
the system clock will come directly from OSC1. HS
oscillator mode is the default for PIC18C601/801. In all
other modes, the PLLEN bit and the SCS1 bit are
forced to ‘0’.
EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out, referred to as TPLL.
OSC1
Clock from
ext. system
PIC18C601/801
FOSC/4
FIGURE 2-4:
HS4 (PLL)
A Phase Lock Loop (PLL) circuit is provided as a software programmable option for users that want to multiply the frequency of the incoming crystal oscillator
signal by 4. For an input clock frequency of 6 MHz, the
internal clock frequency will be multiplied to 24 MHz.
This is useful for customers who are concerned with
EMI due to high frequency crystals.
OSC2
PLL BLOCK DIAGRAM
HS Osc
PLL Enable
OSCOUT
Phase
Comparator
FIN
OSCIN
Loop
Filter
VCO
FOUT
Feedback Divider
3
2001-2013 Microchip Technology Inc.
2
Advance Information
1
0
MUX
Crystal
Osc
CVCO
SYSCLK
DS39541B-page 23
39541a.book Page 24 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
2.6
Oscillator Switching Feature
2.6.1
PIC18C601/801 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low frequency clock source.
For PIC18C601/801 devices, this alternate clock
source is the Timer1 oscillator. If a low frequency crystal (32 kHz, for example) has been attached to the
Timer1 oscillator pins and the Timer1 oscillator has
been enabled, the device can switch to a low power
execution mode. Figure 2-5 shows a block diagram of
the system clock sources.
FIGURE 2-5:
SYSTEM CLOCK SWITCH BIT
The system clock source switching is performed under
software control. The system clock switch bit, SCS0
(OSCCON register), controls the clock switching. When
the SCS0 bit is ’0’, the system clock source comes from
the main oscillator, selected by the FOSC2:FOSC0 configuration bits in CONFIG1H register. When the SCS0 bit
is set, the system clock source will come from the Timer1
oscillator. The SCS0 bit is cleared on all forms of RESET.
Note:
The Timer1 oscillator must be enabled to
switch the system clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 control register
(T1CON). If the Timer1 oscillator is not
enabled, any write to the SCS0 bit will be
ignored (SCS0 bit forced cleared) and the
main oscillator will continue to be the system clock source.
DEVICE CLOCK SOURCES
PIC18C601/801
Main Oscillator
OSC2
SLEEP
TOSC/4
Timer 1 Oscillator
T1OSO
MUX
TOSC
OSC1
T1OSI
4 x PLL
TSCLK
TT1P
Clock
Source
T1OSCEN
Enable
Oscillator
Clock Source option
for other modules
Note: I/O pins have diode protection to VDD and VSS.
DS39541B-page 24
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 25 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 2-1:
OSCCON REGISTER
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
LOCK
PLLEN
SCS1
SCS0
bit 7
bit 0
bit 7-4
Unimplemented: Read as '0'
bit 3
LOCK: Phase Lock Loop Lock Status bit
1 = Phase Lock Loop output is stable as system clock
0 = Phase Lock Loop output is not stable and cannot be used as system clock
bit 2
PLLEN: Phase Lock Loop Enable bit
1 = Enable Phase Lock Loop output as system clock
0 = Disable Phase Lock Loop
bit 1
SCS1: System Clock Switch bit 1
When PLLEN and LOCK bit are set:
1 = Use PLL output
0 = Use primary oscillator/clock input pin
When PLLEN bit or LOCK bit is cleared:
Bit is forced clear
bit 0
SCS0: System Clock Switch bit 0
When T1OSCEN bit is set:
1 = Switch to Timer1 oscillator/clock pin
0 = Use primary oscillator/clock input pin
When T1OSCEN is cleared:
Bit is forced clear
Legend:
2.6.2
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
OSCILLATOR TRANSITIONS
PIC18C601/801 devices contain circuitry to prevent
"glitches" when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to.
This ensures that the new clock source is stable and
that its pulse width will not be less than the shortest
pulse width of the two clock sources.
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in Figure 2-6.
The Timer1 oscillator is assumed to be running all the
time. After the SCS0 bit is set, the processor is frozen
at the next occurring Q1 cycle. After eight synchronization cycles are counted from the Timer1 oscillator, operation resumes. No additional delays are required after
the synchronization cycles.
2001-2013 Microchip Technology Inc.
x = Bit is unknown
The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external crystal (HS, LP), the transition will take place after an oscillator start-up time (TOST) has occurred. A timing
diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS and LP modes is
shown in Figure 2-7.
Advance Information
DS39541B-page 25
39541a.book Page 26 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 2-6:
TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1 Q2
Q3 Q4
Q1
Q1
Q2
Q4
Q3
Q1
Q2
Q3
Q4
Q1
TT1P
1
T1OSI
2
3
4
5
6
7
8
TSCS
OSC1
TOSC
Internal
System
Clock
SCS0
(OSCCON)
Program
Counter
Note:
TDLY
PC
PC + 4
PC + 2
Delay on internal system clock is eight oscillator cycles for synchronization.
FIGURE 2-7:
TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, LP)
Q3
Q4
Q1
Q1
TT1P
Q2 Q3
Q4
Q1
Q2
Q3
T1OSI
1
OSC1
2
3
TOST
4
5
6
7
8
TSCS
OSC2
Internal System
Clock
TOSC
SCS0
(OSCCON)
Program Counter
Note:
PC
PC + 2
PC + 4
TOST = 1024TOSC (drawing not to scale).
DS39541B-page 26
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 27 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
put is not used, so the system oscillator will come from
OSC1 directly and additional delay of TPLL is not
required. A timing diagram indicating the transition from
the Timer1 oscillator to the main oscillator for HS4
mode is shown in Figure 2-9.
If the main oscillator is configured for HS4 (PLL) mode
with SCS1 bit set to ‘1’, an oscillator start-up time
(TOST), plus an additional PLL time-out (TPLL) will
occur. The PLL time-out is typically 2 ms and allows the
PLL to lock to the main oscillator frequency. A timing
diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS4 mode is shown in
Figure 2-8.
If the main oscillator is configured in the RC or EC
modes, there is no oscillator start-up time-out. Operation will resume after eight cycles of the main oscillator
have been counted. A timing diagram indicating the
transition from the Timer1 oscillator to the main oscillator for RC and EC modes is shown in Figure 2-10.
If the main oscillator is configured for HS4 (PLL) mode,
with SCS1 bit set to ‘0’, only oscillator start-up time
(TOST) will occur. Since SCS1 bit is set to ‘0’, PLL out-
FIGURE 2-8:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS4 WITH SCS1 = 1)
Q4
TT1P
Q1
Q1
Q2 Q3 Q4
Q1 Q2 Q3 Q4
T1OSI
OSC1
TOST
TPLL
OSC2
TSCS
TOSC
PLL Clock
Input
1
2
3
4
5
6
7
8
Internal System
Clock
SCS0
(OSCCON)
Program Counter
PC
PC + 2
PC + 4
Note: TOST = 1024TOSC (drawing not to scale).
FIGURE 2-9:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS4 WITH SCS = 0)
Q4
TT1P
Q1
Q1
Q2
Q3
Q4
Q1
Q2
T1OSI
OSC1
TOSC
TOST
OSC2
TSCS
PLL
Clock
Output
TPLL
Internal
System
Clock
TDLY
SCS0
(OSCCON)
Program
Counter
Note:
PC
PC + 2
PC + 4
TOST = 1024TOSC (drawing not to scale).
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 27
39541a.book Page 28 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3
Q4
Q1
Q1 Q2
TT1P
T1OSI
TOSC
OSC1
1
2
3
4
5
6
7
Q3
Q4 Q1 Q2 Q3 Q4
8
OSC2
Internal System
Clock
SCS0
(OSCCON)
TSCS
Program Counter
Note:
2.6.3
PC
RC oscillator mode assumed.
SCS0, SCS1 PRIORITY
If both SCS0 and SCS1 are set to ‘1’ simultaneously,
the SCS0 bit has priority over the SCS1 bit. This means
that the low power option will take precedence over the
PLL option. If both bits are cleared simultaneously, the
system clock will come from OSC1, after a TOST timeout. If only the SCS0 bit is cleared, the system clock will
come from the PLL output, following TOST and TPLL
time.
TABLE 2-3:
SCS0, SCS1 PRIORITY
SCS1
SCS0
0
0
1
1
0
1
0
1
2.7
PC + 4
PC + 2
Clock Source
Ext Oscillator OSC1
Timer1 Oscillator
HS + PLL
Timer1 Oscillator
Effects of SLEEP Mode on the
On-Chip Oscillator
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during SLEEP, will increase the cur-
TABLE 2-4:
OSC Mode
rent consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset, or through an interrupt.
2.8
Power-up Delays
Power-up delays are controlled by two timers, so that
no external RESET circuitry is required for most applications. The delays ensure that the device is kept in
RESET until the device power supply and clock are stable. For additional information on RESET operation,
see Section 3.0 RESET.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of TPWRT (parameter
#33) on power-up only. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in
RESET until the crystal oscillator is stable.
PIC18C601/801 devices provide a configuration bit,
PWRTEN in CONFIG2L register, to enable or disable
the Power-up Timer. By default, the Power-up Timer is
enabled.
With the PLL enabled (HS4 oscillator mode), the time-out
sequence following a Power-on Reset is different from
other oscillator modes. The time-out sequence is as follows: the PWRT time-out is invoked after a POR time
delay has expired, then, the Oscillator Start-up Timer
(OST) is invoked. However, this is still not a sufficient
amount of time to allow the PLL to lock at high frequencies. The PWRT timer is used to provide an additional
time-out, called TPLL (parameter #7), to allow the PLL
ample time to lock to the incoming clock frequency.
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin
OSC2 Pin
RC
Floating, external resistor should pull high
At logic low
EC
Floating
At logic low
LP and HS Feedback inverter disabled, at quiescent voltage level Feedback inverter disabled, at quiescent voltage level
Note: See Table 3-1 in Section 3.0 RESET, for time-outs due to SLEEP and MCLR Reset.
DS39541B-page 28
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 29 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
3.0
RESET
PIC18C601/801 devices differentiate between various
kinds of RESET:
a)
b)
c)
d)
e)
f)
g)
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during SLEEP
Watchdog Timer (WDT) Reset during normal
operation
RESET Instruction
Stack Full Reset
Stack Underflow Reset
Most registers are unaffected by a RESET. Their status
is unknown on POR and unchanged by all other
RESETS. The other registers are forced to a “RESET”
state on Power-on Reset, MCLR, WDT Reset, MCLR
Reset during SLEEP, and by the RESET instruction.
FIGURE 3-1:
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD
and POR, are set or cleared differently in different
RESET situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
RESET. See Table 3-3 for a full description of the
RESET states of all registers.
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 3-1.
PIC18C601/801 has a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
A WDT Reset does not drive MCLR pin low.
SIMPLIFIED BLOCK DIAGRAM OF THE ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLR
SLEEP
WDT
Module
WDT
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
S
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
R
OSC1
Q
PWRT
On-chip
RC OSC(1)
10-bit Ripple Counter
Enable PWRT
Enable OST(2)
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 3-1 for time-out situations.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 29
39541a.book Page 30 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
3.1
Power-on Reset (POR)
3.3
A Power-on Reset pulse is generated on-chip when a
VDD rise is detected. To take advantage of the POR circuitry, connect the MCLR pin directly (or through a
resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset
delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (exits the
RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating conditions are met. Power-on Reset may be used to meet
the voltage start-up condition.
FIGURE 3-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
D
R
R1
MCLR
C
PIC18C601/801
Note 1: External Power-on Reset circuit is required only
if the VDD power-up slope is too slow. The diode
D helps discharge the capacitor quickly when
VDD powers down.
2: R < 40 k is recommended to make sure that
the voltage drop across R does not violate the
device’s electrical specification.
3: R1 = 100 to 1 k will limit any current flowing
into MCLR from external capacitor C, in the
event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD), or Electrical
Overstress (EOS).
3.2
The OST time-out is invoked only for LP, HS and HS4
modes and only on Power-on Reset or wake-up from
SLEEP.
3.4
PLL Lock Time-out
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to provide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(TPLL) is typically 1 ms and follows the oscillator startup time-out (OST).
3.5
VDD
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
Time-out Sequence
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired; then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18C601/801 device
operating in parallel.
Table 3-2 shows the RESET conditions for some
Special Function Registers, while Table 3-3 shows the
RESET conditions for all registers.
Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33), only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in RESET as long as the PWRT is
active. The PWRT time delay allows VDD to rise to an
acceptable level. PIC18C601/801 devices are available with PWRT enabled or disabled.
The power-up time delay will vary from chip to chip, due
to VDD, temperature and process variation. See DC
parameter #33 for details.
DS39541B-page 30
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 31 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 3-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2)
Oscillator
Configuration
PWRTEN = 0
PWRTEN = 1
Wake-up from
SLEEP or
Oscillator Switch(1)
HS with PLL enabled(1)
HS, LP
EC
External RC
72 ms + 1024TOSC
72 ms + 1024TOSC
72 ms
72 ms
1024TOSC
1024TOSC
—
—
1024TOSC + 1 ms
1024TOSC
—
—
Note 1: 1 ms is the nominal time required for the 4X PLL to lock. Maximum time is 2 ms.
2: 72 ms is the nominal Power-up Timer delay.
REGISTER 3-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
U-0
IPEN
r
—
RI
TO
PD
POR
r
bit 7
TABLE 3-2:
bit 0
STATUS BITS, THEIR SIGNIFICANCE, AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Register
RI
TO
PD
POR
Power-on Reset
00000h
0r-1 110r
1
1
1
0
u
u
MCLR Reset during normal
operation
00000h
0r-u uuur
u
u
u
u
u
u
Software Reset during normal
operation
00000h
0r-0 uuur
0
u
u
u
u
u
Stack Full Reset during normal
operation
00000h
0r-u uu1r
u
u
u
1
u
1
Stack Underflow Reset during normal
operation
00000h
0r-u uu1r
u
u
u
1
1
u
MCLR Reset during SLEEP
00000h
0r-u 10ur
u
1
0
u
u
u
WDT Reset
00000h
0r-u 01ur
u
0
1
u
u
u
WDT Wake-up
PC + 2
ur-u 00ur
u
0
0
u
u
u
PC + 2(1)
ur-u 00ur
u
0
0
u
u
u
Condition
Interrupt wake-up from SLEEP
STKFUL STKUNF
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', r = reserved, maintain ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (000008h or 000018h).
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 31
39541a.book Page 32 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 3-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS39541B-page 32
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 33 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 3-6:
SLOW RISE TIME (MCLR TIED TO VDD)
5V
VDD
1V
0V
MCLR
INTERNAL POR
TDEADTIME
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-7:
TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
IINTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
TPLL
OST TIME-OUT
PLL TIME-OUT
INTERNAL RESET
TOST = 1024 clock cycles.
TPLL 2 ms max. First three stages of the PWRT timer.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 33
39541a.book Page 34 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable
Devices
Power-on Reset
MCLR Reset
WDT Reset
Reset Instruction
Stack Over/Underflow Reset
Wake-up via WDT or
Interrupt
TOSU
601
801
---0 0000
---0 0000
---u uuuu(3)
TOSH
601
801
0000 0000
0000 0000
uuuu uuuu(3)
TOSL
601
801
0000 0000
0000 0000
uuuu uuuu(3)
STKPTR
601
801
00-0 0000
00-0 0000
uu-u uuuu(3)
PCLATU
601
801
---0 0000
---0 0000
---u uuuu
PCLATH
601
801
0000 0000
0000 0000
uuuu uuuu
PCL
601
801
0000 0000
0000 0000
PC + 2(2)
TBLPTRU
601
801
--00 0000
--00 0000
--uu uuuu
TBLPTRH
601
801
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
601
801
0000 0000
0000 0000
uuuu uuuu
TABLAT
601
801
0000 0000
0000 0000
uuuu uuuu
PRODH
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
601
801
0000 000x
0000 000u
uuuu uuuu(1)
INTCON2
601
801
1111 -1-1
1111 -1-1
uuuu -u-u(1)
INTCON3
601
801
11-0 0-00
11-0 0-00
uu-u u-uu(1)
INDF0
601
801
(Note 5)
(Note 5)
(Note 5)
POSTINC0
601
801
(Note 5)
(Note 5)
(Note 5)
POSTDEC0
601
801
(Note 5)
(Note 5)
(Note 5)
PREINC0
601
801
(Note 5)
(Note 5)
(Note 5)
PLUSW0
601
801
(Note 5)
(Note 5)
(Note 5)
FSR0H
601
801
---- 0000
---- 0000
---- uuuu
FSR0L
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
601
801
(Note 5)
(Note 5)
(Note 5)
POSTINC1
601
801
(Note 5)
(Note 5)
(Note 5)
POSTDEC1
601
801
(Note 5)
(Note 5)
(Note 5)
PREINC1
601
801
(Note 5)
(Note 5)
(Note 5)
PLUSW1
601
801
(Note 5)
(Note 5)
(Note 5)
FSR1H
601
801
---- 0000
---- 0000
---- uuuu
FSR1L
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
601
801
---- 0000
---- 0000
---- uuuu
INDF2
601
801
(Note 5)
(Note 5)
(Note 5)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition,
r = reserved, maintain ‘0’
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (00008h or 00018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH, and TOSL are
updated with the current value of the PC. The SKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: This is not a physical register. It is an indirect pointer that addresses another register. The contents
returned is the value contained in the addressed register.
DS39541B-page 34
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 35 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable
Devices
Power-on Reset
MCLR Reset
WDT Reset
Reset Instruction
Stack Over/Underflow Reset
Wake-up via WDT or
Interrupt
POSTINC2
601
801
(Note 5)
(Note 5)
(Note 5)
POSTDEC2
601
801
(Note 5)
(Note 5)
(Note 5)
PREINC2
601
801
(Note 5)
(Note 5)
(Note 5)
PLUSW2
601
801
(Note 5)
(Note 5)
(Note 5)
FSR2H
601
801
---- 0000
---- 0000
---- uuuu
FSR2L
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
601
801
---x xxxx
---u uuuu
---u uuuu
TMR0H
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR0L
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
601
801
1111 1111
1111 1111
uuuu uuuu
OSCCON
601
801
--00 0-00
--uu u-u0
--uu u-uu
LVDCON
601
801
--00 0101
--00 0101
--uu uuuu
WDTCON
601
801
---- 1111
---- uuuu
---- uuuu
RCON(4)
601
801
0r-1 11qr
0r-1 qqur
ur-u qqur
TMR1H
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
601
801
0-00 0000
u-uu uuuu
u-uu uuuu
TMR2
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
PR2
601
801
1111 1111
1111 1111
1111 1111
T2CON
601
801
-000 0000
-000 0000
-uuu uuuu
SSPBUF
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
601
801
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
601
801
0000 0000
0000 0000
uuuu uuuu
SSPCON1
601
801
0000 0000
0000 0000
uuuu uuuu
SSPCON2
601
801
0000 0000
0000 0000
uuuu uuuu
ADRESH
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
601
801
--00 0000
--00 0000
--uu uuuu
ADCON1
601
801
-000 0000
-000 0000
-uuu uuuu
ADCON2
601
801
0--- -000
0--- -000
u--- -uuu
CCPR1H
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
601
801
--00 0000
--00 0000
--uu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition,
r = reserved, maintain ‘0’
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (00008h or 00018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH, and TOSL are
updated with the current value of the PC. The SKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: This is not a physical register. It is an indirect pointer that addresses another register. The contents
returned is the value contained in the addressed register.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 35
39541a.book Page 36 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable
Devices
Power-on Reset
MCLR Reset
WDT Reset
Reset Instruction
Stack Over/Underflow Reset
Wake-up via WDT or
Interrupt
CCPR2H
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
601
801
--00 0000
--00 0000
--uu uuuu
TMR3H
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
601
801
0000 0000
uuuu uuuu
uuuu uuuu
SPBRG
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
RCREG
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXREG
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXSTA
601
801
0000 -01x
0000 -01u
uuuu -uuu
RCSTA
601
801
0000 000x
0000 000u
uuuu uuuu
IPR2
601
801
-1-- 1111
-1-- 1111
-u-- uuuu
PIR2
601
801
-1-- 0000
-1-- 0000
-u-- uuuu(1)
PIE2
601
801
-1-- 0000
-1-- 0000
-u-- uuuu
IPR1
601
801
1111 1111
1111 1111
uuuu uuuu
601
801
-111 1111
-111 1111
-uuu uuuu
601
801
0000 0000
0000 0000
uuuu uuuu(1)
601
801
-000 0000
-000 0000
-uuu uuuu(1)
601
801
0000 0000
0000 0000
uuuu uuuu
601
801
-000 0000
-000 0000
-uuu uuuu
MEMCON
601
801
0000 --00
0000 --00
uuuu --uu
TRISJ
601
801
1111 1111
1111 1111
uuuu uuuu
TRISH
601
801
1111 1111
1111 1111
uuuu uuuu
TRISG
601
801
---1 1111
---1 1111
---u uuuu
TRISF
601
801
1111 1111
1111 1111
uuuu uuuu
TRISE
601
801
1111 1111
1111 1111
uuuu uuuu
TRISD
601
801
1111 1111
1111 1111
uuuu uuuu
TRISC
601
801
1111 1111
1111 1111
uuuu uuuu
TRISB
601
801
1111 1111
1111 1111
uuuu uuuu
TRISA
601
801
--11 1111
--11 1111
--uu uuuu
LATG
601
801
---x xxxx
---u uuuu
---u uuuu
LATF
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATE
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIR1
PIE1
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition,
r = reserved, maintain ‘0’
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (00008h or 00018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH, and TOSL are
updated with the current value of the PC. The SKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: This is not a physical register. It is an indirect pointer that addresses another register. The contents
returned is the value contained in the addressed register.
DS39541B-page 36
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 37 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable
Devices
Power-on Reset
MCLR Reset
WDT Reset
Reset Instruction
Stack Over/Underflow Reset
Wake-up via WDT or
Interrupt
LATD
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATA
601
801
--xx xxxx
--uu uuuu
--uu uuuu
PORTJ
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTH
601
801
0000 xxxx
0000 uuuu
uuuu uuuu
PORTG
601
801
---x xxxx
---u uuuu
---u uuuu
PORTF
601
801
xxxx x000
uuuu u000
uuuu uuuu
PORTE
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTD
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
601
801
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
601
801
--0x 0000
--0u 0000
--uu uuuu
CSEL2
601
801
1111 1111
uuuu uuuu
uuuu uuuu
CSELIO
601
801
1111 1111
uuuu uuuu
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition,
r = reserved, maintain ‘0’
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (00008h or 00018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH, and TOSL are
updated with the current value of the PC. The SKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: This is not a physical register. It is an indirect pointer that addresses another register. The contents
returned is the value contained in the addressed register.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 37
39541a.book Page 38 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
NOTES:
DS39541B-page 38
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 39 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
4.0
MEMORY ORGANIZATION
There are two memory blocks in PIC18C601/801
devices. These memory blocks are:
• Program Memory
• Data Memory
Each block has its own bus so that concurrent access
can occur.
4.1
Program Memory Organization
PIC18C601/801 devices have a 21-bit program counter that is capable of addressing up to 2 Mbyte of external program memory space. The PIC18C601 has an
external program memory address space of 256
Kbytes. Any program fetch or TBLRD from a program
location greater than 256K will return all NOPs. The
PIC18C801 has an external program memory address
space of 2Mbytes. Refer to Section 5.0 (“External
Memory Interface”) for additional details.
The RESET vector address is mapped to 000000h and
the interrupt vector addresses are at 000008h and
000018h. PIC18C601/801 devices have a 31-level stack
to store the program counter values during subroutine
calls and interrupts. Figure 4-1 shows the program
memory map and stack for PIC18C601. Figure 4-2
shows the program memory map and stack for the
PIC18C801.
4.1.1
“BOOT RAM” PROGRAM MEMORY
PIC18C601/801 devices have a provision for configuring the last 512 bytes of general purpose user RAM as
program memory, called “Boot RAM”. This is achieved
by configuring the PGRM bit in the MEMCON register
to ‘1’. (Refer to Section 5.0, “External Memory Interface” for more information.) When the PGRM bit is ‘1’,
the RAM located in data memory locations 400h
through 5FFh (bank 4 through 5) is mapped to program
memory locations 1FFE00h to 1FFFFFh.
When configured as program memory, the Boot RAM is
to be used as a temporary “boot loader” for programming purposes. It can only be used for program execution. A read from locations 400h to 5FFh in data
memory returns all ‘0’s. Any attempt to write this RAM
as data memory when PGRM = 1, does not modify any
of these locations. TBLWT instructions to these locations will cause writes to occur on the external memory
bus. The boot RAM program memory cannot be modified using TBLWT instruction. TBLRD instructions from
boot RAM will read memory located on the external
memory bus, not from the on-board RAM. Constants
that are stored in boot RAM are retrieved using the
RETLW instruction.
The default RESET state (power-up) for the PGRM bit
is ‘0’, which configures 1.5K of data RAM and all program memory as external. The PGRM bit can be set
and cleared in the software.
When execution takes place from “Boot RAM”, the
external system bus and all of its control signals will be
deactivated. If execution takes place from outside of
“Boot RAM”, the external system bus and all of its control signals are activated again.
Figure 4-3 and Figure 4-4 show the program memory
map and stack for PIC18C601 and PIC18C801, when
the PGRM bit is set.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 39
39541a.book Page 40 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC18C601 (PGRM = 0)
FIGURE 4-2:
PC
PROGRAM MEMORY MAP
AND STACK FOR
PIC18C801 (PGRM = 0)
PC
21
21
Stack Level 1
Stack Level 1
Stack Level 31
Stack Level 31
RESET Vector
RESET Vector
0000h
0000h
High Priority Interrupt Vector 0008h
High Priority Interrupt Vector 0008h
Low Priority Interrupt Vector
Low Priority Interrupt Vector
3FFFFh
40000h
0018h
User Memory Space
External
Program Memory
User Memory Space
0018h
External
Program Memory
Read '0'
1FFFFFh
DS39541B-page 40
1FFFFFh
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 41 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 4-3:
PROGRAM MEMORY MAP AND STACK FOR PIC18C601 (PGRM = 1)
PC
21
Stack Level 1
Stack Level 31
RESET Vector
0000h
High Priority Interrupt Vector 0008h
0018h
External
Program Memory
03FFFFh
040000h
User Memory Space
Low Priority Interrupt Vector
Read '0'
1FFE00h
1FFDFFh
1FFE00h
1FFFFFh
1FFFFFh
On-Chip
Boot RAM
INTERNAL MEMORY
2001-2013 Microchip Technology Inc.
EXTERNAL MEMORY
Advance Information
DS39541B-page 41
39541a.book Page 42 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 4-4:
PROGRAM MEMORY MAP AND STACK FOR PIC18C801 (PGRM = 1)
PC
21
Stack Level 1
Stack Level 31
RESET Vector
0000h
High Priority Interrupt Vector 0008h
0018h
User Memory Space
Low Priority Interrupt Vector
External
Program Memory
1FFDFFh
1FFE00h
1FFE00h
External
Table Memory
On-Chip
Boot RAM
1FFFFFh
1FFFFFh
INTERNAL MEMORY
DS39541B-page 42
EXTERNAL MEMORY
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 43 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
4.1.2
BOOT LOADER
4.2.1
When configured as Program Memory, Boot RAM can
be used as a temporary “Boot Loader” for programming
purposes. If an external memory device is used as program memory, any updates performed by the user program will have to be performed in the “Boot RAM”,
because the user program cannot program and fetch
from external memory, simultaneously.
A typical boot loader execution and external memory
programming sequence would be as follows:
• The boot loader program is transferred from the
external program memory to the last 2 banks of
data RAM by TBLRD and MOVWF instructions.
• Once the “boot loader” program is loaded into
internal memory and verified, open combination
lock and set PGRM bit to configure the data RAM
into program RAM.
• Jump to beginning of Boot code in Boot RAM.
Program execution begins in Boot RAM to begin
programming the external memory. System bus
changes to an inactive state.
• Boot loader program performs the necessary
external TBLWT and TBLWRD instructions to
perform programming functions.
• When the boot loader program is finished programming external memory, jump to known valid
external program memory location and clear
PGRM bit in MEMCON register to set Boot RAM
as data memory, or reset the part.
4.2
Return Address Stack
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL, allow
access to the contents of the stack location indicated by
the STKPTR register. This allows users to implement a
software stack, if necessary. After a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
The user should disable the global interrupt enable bits
during this time to prevent inadvertent stack operations.
4.2.2
RETURN STACK POINTER
(STKPTR)
The STKPTR register contains the stack pointer value,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-1 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when values are pushed onto the stack and decrements when
values are popped off the stack. At RESET, the stack
pointer value will be 0. The user may read and write the
stack pointer value. This feature can be used by a Real
Time Operating System for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR. Any subsequent push operation that causes
stack overflow will be ignored.
The return address stack allows any combination of up to
31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a PUSH,
CALL or RCALL instruction is executed, or an interrupt is
acknowledged. The PC value is pulled off the stack on a
RETURN, RETLW or a RETFIE instruction. PCLATU and
PCLATH are not affected by any of the return instructions.
The action that takes place when the stack becomes
full, depends on the state of STVREN (stack overflow
RESET enable) configuration bit in CONFIG4L register. Refer to Section 4.2.4 for more information. If
STVREN is set (default), stack over/underflow will set
the STKFUL bit, and reset the device. The STKFUL bit
will remain set and the stack pointer will be set to 0.
The stack operates as a 31-word by 21-bit stack memory
and a five-bit stack pointer, with the stack pointer initialized to 00000b after all RESETS. There is no RAM associated with stack pointer 00000b. This is only a RESET
value. During a CALL type instruction, causing a push
onto the stack, the stack pointer is first incremented and
the RAM location pointed to by the stack pointer is written
with the contents of the PC. During a RETURN type
instruction, causing a pop from the stack, the contents of
the RAM location indicated by the STKPTR is transferred
to the PC and then the stack pointer is decremented.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31. All
subsequent push attempts will be ignored and
STKPTR remains at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at 0. The STKUNF bit will remain set
until cleared in software, or a POR occurs.
Note:
The stack space is not part of either program or data
space. The stack pointer is readable and writable, and
the data on the top of the stack is readable and writable
through SFR registers. Status bits STKOVF and
STKUNF in STKPTR register, indicate whether stack
over/underflow has occurred or not.
2001-2013 Microchip Technology Inc.
Advance Information
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the RESET vector, where the
stack conditions can be verified and appropriate actions can be taken.
DS39541B-page 43
39541a.book Page 44 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 4-1:
STKPTR - STACK POINTER REGISTER
R/C-0
STKFUL
bit 7
R/C-0
STKUNF
U-0
—
R/W-0
SP4
bit 7
STKFUL: Stack Full Flag bit
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6
STKUNF: Stack Underflow Flag bit
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5
Unimplemented: Read as '0'
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note:
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
bit 0
Bit 7 and bit 6 can only be cleared in user software, or by a POR.
Legend:
FIGURE 4-5:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
C = Clearable bit
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
11111
11110
11101
TOSU
00h
TOSH
1Ah
STKPTR
00010
TOSL
34h
Top-of-Stack
00011
001A34h 00010
000D58h 00001
000000h 00000(1)
Note 1: No RAM is associated with this address; always maintained ‘0’s.
DS39541B-page 44
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 45 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
4.2.3
PUSH AND POP INSTRUCTIONS
4.3
Fast Register Stack
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pop values
off the stack, without disturbing normal program execution, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the stack pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place a return address on the
stack.
A “fast return” option is available for interrupts and calls.
A fast register stack is provided for the STATUS, WREG
and BSR registers, and is only one layer in depth. The
stack is not readable or writable and is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. The values in the fast
register stack are then loaded back into the working registers, if the fast return instruction is used to return
from the interrupt.
The POP instruction discards the current TOS by decrementing the stack pointer. The previous value pushed
onto the stack then becomes the TOS value.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority
interrupt will be overwritten.
4.2.4
STACK FULL/UNDERFLOW RESETS
These RESETS are enabled/disabled by programming
the STVREN configuration bit in CONFIG4L register.
When the STVREN bit is disabled, a full or underflow
condition will set the appropriate STKFUL or STKUNF
bit, but not cause a RESET. When the STVREN bit is
enabled, a full or underflow will set the appropriate
STKFUL or STKUNF bit and then cause a RESET. The
STKFUL or STKUNF bits are only cleared by the user
software or a POR.
If high priority interrupts are not disabled during low priority interrupts, users must save the key registers in
software during a low priority interrupt.
If no interrupts are used, the fast register stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the fast register
stack for a subroutine call, a fast call instruction
must be executed.
Example 4-1 shows a source code example that uses
the fast register stack.
EXAMPLE 4-1:
CALL SUB1, FAST
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
RETURN FAST
SUB1
2001-2013 Microchip Technology Inc.
Advance Information
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
DS39541B-page 45
39541a.book Page 46 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
4.4
PCL, PCLATH and PCLATU
The contents of PCLATH and PCLATU will be transferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (See Section 4.8.1).
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called
the PCH register. This register contains the PC
bits and is not directly readable or writable. Updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC bits and is not directly
readable or writable. Updates to the PCU register may
be performed through the PCLATU register.
4.5
The clock input (from OSC1 or PLL output) is internally
divided by four to generate four non-overlapping
quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every
Q1, the instruction is fetched from the program memory
and latched into the instruction register in Q4. The
instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 4-6.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSb of the PCL is fixed to a value of ’0’.
The PC increments by 2 to address sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
FIGURE 4-6:
Clocking Scheme/Instruction
Cycle
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
DS39541B-page 46
PC
Fetch INST (PC)
Execute INST (PC-2)
PC+2
Fetch INST (PC+2)
Execute INST (PC)
Advance Information
PC+4
Fetch INST (PC+4)
Execute INST (PC+2)
2001-2013 Microchip Technology Inc.
39541a.book Page 47 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
4.6
Instruction Flow/Pipelining
4.7
Instructions in Program Memory
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined, such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
two cycles are required to complete the instruction
(Example 4-2).
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = ’0’). Figure 4-1 shows an
example of how instruction words are stored in the program memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ’0’ (see Section 4.4).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
The CALL and GOTO instructions have an absolute program memory address embedded into the instruction.
Since instructions are always stored on word boundaries, the data contained in the instruction is a word
address. The word address is written to PC,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 4-1 shows how the
instruction “GOTO 0x06” is encoded in the program
memory. Program branch instructions that encode a
relative address offset operate in the same manner.
The offset value stored in a branch instruction represents the number of single word instructions by which
the PC will be offset. Section 20.0 provides further
details of the instruction set.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
EXAMPLE 4-2:
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
TCY0
TCY1
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
TCY3
TCY4
TCY5
Execute 2
Fetch 3
3. BRA SUB_1
4. BSF
TCY2
Execute 3
Fetch 4
PORTA, BIT3 (Forced NOP)
Flush
Fetch SUB_1 Execute SUB_1
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
TABLE 4-1:
INSTRUCTIONS IN PROGRAM MEMORY
Instruction
Opcode
Memory
—
—
—
000007h
MOVLW 055h
0E55h
55h
000008h
GOTO 000006h
EF03h, F000h
MOVFF 123h, 456h
—
2001-2013 Microchip Technology Inc.
C123h, F456h
—
Advance Information
Address
0Eh
000009h
03h
00000Ah
EFh
00000Bh
00h
00000Ch
F0h
00000Dh
23h
00000Eh
C1h
00000Fh
56h
000010h
F4h
000011h
—
000012h
DS39541B-page 47
39541a.book Page 48 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
4.7.1
TWO-WORD INSTRUCTIONS
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
PIC18C601/801 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second
word of these instructions has the four MSB’s set to 1’s
and is a special kind of NOP instruction. The lower 12
bits of the second word contain data to be used by the
instruction. If the first word of the instruction is executed, the data in the second word is accessed. If the
second word of the instruction is executed by itself (first
word was skipped), it will execute as a NOP. This action
is necessary when the two-word instruction is preceded
by a conditional instruction that changes the PC and
skips one instruction. A program example that demonstrates this concept is shown in Example 4-3. Refer to
Section 19.0 for further details of the instruction set.
4.8
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
Warning: The LSb of the PCL is fixed to a value of ‘0’.
Hence, computed GOTO to an odd address
is not possible.
4.8.2
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Lookup table data may be stored as 2 bytes per program word by using table reads and writes. The table
pointer (TBLPTR) specifies the byte address and the
table latch (TABLAT) contains the data that is read
from, or written to, program memory. Data is transferred to/from program memory one byte at a time.
Lookup Tables
Lookup tables are implemented two ways:
• Computed GOTO
• Table Reads
4.8.1
A description of the Table Read/Table Write operation
is shown in Section 6.0.
COMPUTED GOTO
Note:
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL).
A lookup table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table, before executing a call to that table. The first instruction of the called
routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions that returns the value 0xnn to the calling function.
EXAMPLE 4-3:
TABLE READS/TABLE WRITES
If execution is taking place from Boot RAM
Program Memory, RETLW instructions
must be used to read lookup values from
the Boot RAM itself.
Two-Word Instructions
CASE 1:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; No, execute 2-word instruction
ADDWF
REG3
; continue code
1111 0100 0101 0110
0010 0100 0000 0000
; 2nd operand holds address of REG2
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; Yes
ADDWF
REG3
; continue code
1111 0100 0101 0110
0010 0100 0000 0000
DS39541B-page 48
; 2nd operand executed as NOP
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 49 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
4.9
Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 4-8 shows
the data memory organization for PIC18C601/801
devices.
The data memory map is divided into banks that contain 256 bytes each. The lower four bits of the Bank
Select Register (BSR) select which bank will be
accessed. The upper 4 bits for the BSR are not implemented.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFR’s are used for control and status of the controller
and peripheral functions, while GPR’s are used for data
storage and scratch pad operations in the user’s application. The SFR’s start at the last location of Bank 15
(0FFFh) and grow downwards. GPR’s start at the first
location of Bank 0 and grow upwards. Any read of an
unimplemented location will read as ’0’s.
GPR banks 4 and 5 serve as a Program Memory called
“Boot RAM”, when PGRM bit in MEMCON is set. When
PGRM bit is set, any read from “Boot RAM” returns ‘0’s,
while any write to it is ignored.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSR). Each FSR holds a 12-bit
address value that can be used to access any location
in the Data Memory map without banking.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing, or by the use of the MOVFF instruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access bank. Section 4.10 provides a detailed description of the Access bank.
4.9.1
GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly or indirectly. Indirect addressing operates through the File
Select Registers (FSR). The operation of indirect
addressing is shown in Section 4.12.
PIC18C601/801 devices have banked memory in the
GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other RESETS.
Data RAM is available for use as GPR registers by all
instructions. Bank 15 (0F80h to 0FFFh) contains
SFR’s. All other banks of data memory contain GPR
registers starting with bank 0.
4.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these
registers is given in Table 4-2.
The SFR’s can be classified into two sets: those associated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The SFRs are typically distributed among the peripherals whose functions they control.
The unused SFR locations are unimplemented and
read as '0's. See Table 4-2 for addresses for the SFRs.
4.9.3
SECURED ACCESS REGISTERS
PIC18C601/801 devices contain software programming options for safety critical peripherals. Because
these safety critical peripherals can be programmed in
software, registers used to control these peripherals
are given limited access by the user code. This way,
errant code will not accidentally change settings in
peripherals that could cause catastrophic results.
The registers that are considered safety critical are the
Watchdog Timer register (WDTCON), the External
Memory Control register (MEMCON), the Oscillator
Control register (OSCCON) and the Chip Select registers (CSSEL2 and CSELIO).
Two bits called Combination Lock (CMLK) bits, located
in the lower two bits of the PSPCON register, must be
set in sequence by user code to gain access to
Secured Access registers.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 49
39541a.book Page 50 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 4-2:
PSPCON REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
W-0
W-0
—
—
—
—
—
—
CMLK1
CMLK0
bit 7
bit 0
bit 7-2
Unimplemented: Read as '0'
bit 1-0
CMLK: Combination Lock bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
The Combination Lock bits must be set sequentially,
meaning that as soon as Combination Lock bit CMLK1
is set, the second Combination Lock bit CMLK0 must be
set on the following instruction cycle. If user waits more
than one machine cycle to set the second bit after setting the first, both bits will automatically be cleared in
hardware and the lock will remain closed. To satisfy this
condition, all interrupts must be disabled before attempting to unlock the Combination Lock. Once secured registers are modified, interrupts may be re-enabled.
Each instruction must only modify one combination lock
bit at a time. This means, user code must use the BSF
instruction to set CMLK bits in the PSPCON register.
Note:
When the Combination Lock is opened, the user will
have three instruction cycles to modify the safety critical register of choice. After three instruction cycles
have expired, the CMLK bits are cleared, the lock will
close and the user will have to set the CMLK bits again,
in order to open the lock. Since there are only three
instruction cycles allowed after the Combination Lock is
opened, if a subroutine is used to unlock Combination
Lock bits, user code must preload WREG with the
desired value, call unlock subroutine, and write to the
desired safety critical register itself.
Note:
The Combination Lock bits are write-only
bits. These bits will always return ‘0’ when
read.
EXAMPLE 4-4:
x = Bit is unknown
Successive attempts to unlock the Combination Lock must be separated by at least
three instruction cycles.
COMBINATION UNLOCK SUBROUTINE EXAMPLE CODE
MOVLW 5Ah
BCF INTCON, GIE
CALL UNLOCK
;
;
;
;
Preload WREG with data to be stored in a safety critical register
Disable all interrupts
Now unlock it
Write must take place in next instruction cycle
MOVWF OSCCON
BSF INTCON, GIE
UNLOCK
BSF PSPCON, CMLK1
BSF PSPCON, CMLK0
RETURN
DS39541B-page 50
; Lock is closed
; Re-enable interrupts
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 51 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
EXAMPLE 4-5:
COMBINATION UNLOCK MACRO EXAMPLE CODE
UNLOCK_N_MODIFY @REG
MACRO
BCF INTCON,
BSF PSPCON,
BSF PSPCON,
MOVWF @REG
BSF INTCON,
ENDM
GIE
CMLK1
CMLK0
; Disable interrupts
; Modify given register
; Enable interrupts
GIE
MOVLW 5Ah
UNLOCK_N_MODIFY OSCCON
FIGURE 4-7:
THE DATA MEMORY MAP FOR PIC18C801/601 (PGRM = 0)
BSR
= 0000b
= 0001b
Data Memory Map
00h
Access GPR’s
FFh
00h
GPR
Bank 0
FFh
00h
Bank 2
= 0100b
1FFh
200h
GPR
2FFh
300h
FFh
00h
GPR
Bank 3
FFh
00h
Bank 4
3FFh
400h
GPR
GPR
Bank 5
5FFh
FFh
= 0110b
= 1110b
= 1111b
Access RAM Bank
4FFh
500h
FFh
00h
= 0101b
000h
07Fh
080h
0FFh
100h
GPR
Bank 1
= 0010b
= 0011b
; Preload WREG for OSCCON register
; Modify OSCCON
Bank 6
to
Bank 14
Unused
Read ’00h’
00h
Unused
FFh
Access SFR’s
Bank 15
2001-2013 Microchip Technology Inc.
EFFh
F00h
F7Fh
F80h
FFFh
Advance Information
00h
Access Bank Low
(GPR’s)
7Fh
Access Bank High 80h
(SFR’s)
FFh
When a = 0,
the BSR is ignored and this
Access RAM bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The next 128 bytes are Special
Function Registers (from
Bank 15).
When a = 1,
the BSR is used to specify
the RAM location that the
instruction uses.
DS39541B-page 51
39541a.book Page 52 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 4-8:
DATA MEMORY MAP FOR PIC18C601/801 (PGRM = 1)
BSR
= 0000b
= 0001b
Data Memory Map
00h
Access GPR’s
FFh
00h
GPR
Bank 0
GPR
Bank 1
FFh
00h
= 0010b
Bank 2
= 0011b
000h
07Fh
080h
0FFh
100h
1FFh
200h
GPR
2FFh
300h
FFh
00h
GPR
Bank 3
FFh
3FFh
Access RAM Bank
00h
Access Bank Low
(GPR’s)
7Fh
Access Bank High 80h
(SFR’s)
FFh
= 0100b
= 1110b
= 1111b
DS39541B-page 52
Bank 4
to
Bank 14
Unused
Read ’00h’
00h
Unused
FFh
Access SFR’s
Bank 15
EFFh
F00h
F7Fh
F80h
FFFh
Advance Information
When a = 0,
the BSR is ignored and this
Access RAM bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The next 128 bytes are Special
Function Registers (from
Bank 15).
When a = 1,
the BSR is used to specify
the RAM location that the
instruction uses.
2001-2013 Microchip Technology Inc.
39541a.book Page 53 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 4-9:
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
FEEh
FEDh
FECh
FEBh
FEAh
FE9h
FE8h
FE7h
FE6h
FE5h
FE4h
FE3h
FE2h
FE1h
FE0h
SPECIAL FUNCTION REGISTER MAP
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
FSR1L
BSR
FDFh
FDEh
FDDh
FDCh
FDBh
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
2001-2013 Microchip Technology Inc.
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
Reserved
OSCCON
LVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
FBFh
FBEh
FBDh
FBCh
FBBh
FBAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
Reserved
Reserved
Reserved
—
—
—
TMR3H
TMR3L
T3CON
PSPCON
SPBRG
RCREG
TXREG
TXSTA
RCSTA
—
—
—
CSEL2
CSELIO
—
—
—
IPR2
PIR2
PIE2
Advance Information
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
IPR1
PIR1
PIE1
MEMCON
—
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
DS39541B-page 53
39541a.book Page 54 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 4-2:
File Name
REGISTER FILE SUMMARY - PIC18C601/801
Bit 7
Bit 6
Bit 5
—
—
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
all other
RESETS(1)
FFFh
TOSU
FFEh
TOSH
Top-of-Stack High Byte (TOS)
FFDh
TOSL
Top-of-Stack Low Byte (TOS)
FFCh
STKPTR
STKOVF
STKUNF
—
Return Stack Pointer
00-0 0000 00-0 0000
FFBh
PCLATU
—
—
—
Holding Register for PC
---0 0000 ---0 0000
FFAh
PCLATH
Holding Register for PC
FF9h
PCL
PC Low Byte (PC)
FF8h
TBLPTRU
FF7h
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR)
0000 0000 0000 0000
FF6h
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR)
0000 0000 0000 0000
FF5h
TABLAT
Program Memory Table Latch
0000 0000 0000 0000
FF4h
PRODH
Product Register High Byte
xxxx xxxx uuuu uuuu
FF3h
PRODL
Product Register Low Byte
FF2h
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0E
RBIE
TMR0IF
INT0F
RBIF
0000 000x 0000 000u
FF1h
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
—
T0IP
—
RBIP
1111 -1-1 1111 -1-1
FF0h
INTCON3
INT2P
INT1P
—
INT2E
INT1E
—
INT2F
INT1F
11-0 0-00 11-0 0-00
FEFh
INDF0
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
N/A
N/A
FEEh
POSTINC0
Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)
N/A
N/A
FEDh
POSTDEC0
Uses contents of FSR0 to address data memory - value of FSR0 post-decremented
(not a physical register)
N/A
N/A
FECh
PREINC0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented
(not a physical register)
N/A
N/A
FEBh
PLUSW0
Uses contents of FSR0 to address data memory -value of FSR0 offset by WREG
(not a physical register)
N/A
N/A
—
Top-of-Stack Upper Byte (TOS)
Value on
POR
---0 0000 ---0 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
—
r
Program Memory Table Pointer Upper Byte (TBLPTR)
--r0 0000 --r0 0000
xxxx xxxx uuuu uuuu
FEAh
FSR0H
FE9h
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx uuuu uuuu
FE8h
WREG
Working Register
xxxx xxxx uuuu uuuu
FE7h
INDF1
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
N/A
N/A
FE6h
POSTINC1
Uses contents of FSR1 to address data memory - value of FSR1 post-incremented
(not a physical register)
N/A
N/A
FE5h
POSTDEC1
Uses contents of FSR1 to address data memory - value of FSR1 post-decremented
(not a physical register)
N/A
N/A
FE4h
PREINC1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)
N/A
N/A
FE3h
PLUSW1
Uses contents of FSR1 to address data memory - value of FSR1 offset by WREG (not a physical register)
N/A
N/A
FE2h
FSR1H
—
—
—
—
—
—
—
—
Indirect Data Memory Address Pointer 0 High
Indirect Data Memory Address Pointer 1 High
---- xxxx ---- uuuu
FE1h
FSR1L
FE0h
BSR
FDFh
INDF2
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
N/A
N/A
FDEh
POSTINC2
Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)
N/A
N/A
FDDh
POSTDEC2
Uses contents of FSR2 to address data memory - value of FSR2 post-decremented
(not a physical register)
N/A
N/A
FDCh
PREINC2
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)
N/A
N/A
FDBh
PLUSW2
Uses contents of FSR2 to address data memory -value of FSR2 offset by WREG (not a physical register)
N/A
N/A
FDAh
FSR2H
FD9h
FSR2L
FD8h
STATUS
Legend
Indirect Data Memory Address Pointer 1 Low Byte
---- xxxx ---- uuuu
—
—
—
—
—
—
—
—
xxxx xxxx uuuu uuuu
Bank Select Register
---- 0000 ---- 0000
Indirect Data Memory Address Pointer 2 High
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
---- xxxx ---- uuuu
xxxx xxxx uuuu uuuu
OV
Z
DC
C
---x xxxx ---u uuuu
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved
Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
2: These registers can only be modified when the Combination Lock is open.
3: These registers are available on PIC18C801 only.
DS39541B-page 54
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 55 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 4-2:
File Name
REGISTER FILE SUMMARY - PIC18C601/801 (CONTINUED)
Bit 7
Bit 6
FD7h
TMR0H
Timer0 Register High Byte
FD6h
TMR0L
Timer0 Register Low Byte
FD5h
T0CON
FD4h
Reserved
FD3h
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
RESETS(1)
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
TMR0ON
16BIT
T0CS
T0SE
T0PS3
T0PS2
T0PS1
T0PS0
1111 1111 1111 1111
OSCCON(2)
—
—
—
—
LOCK
PLLEN
SCS1
SCS0
---- 0000 ---- uuu0
FD2h
LVDCON(2)
—
—
IRVST
LVDEN
LVV3
LVV2
LVV1
LVV0
--00 0101 --00 0101
FD1h
WDTCON(2)
—
—
—
—
WDPS2
WDPS1
WDPS0
FD0h
RCON
IPEN
r
—
RI
TO
PD
POR
FCFh
TMR1H
Timer1 Register High Byte
FCEh
TMR1L
Timer1 Register Low Byte
FCDh
T1CON
rrrr rrrr rrrr rrrr
RD16
—
FCCh
TMR2
Timer2 Register
FCBh
PR2
Timer2 Period Register
FCAh
T2CON
—
SWDTEN ---- 0000 ---- xxxx
r
00-1 11qq 00-q qquu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON 0-00 0000 u-uu uuuu
0000 0000 0000 0000
TOUTPS3
1111 1111 1111 1111
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0 -000 0000 -000 0000
FC9h
SSPBUF
SSP Receive Buffer/Transmit Register
FC8h
SSPADD
SSP Address Register in I2C Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode
FC7h
SSPSTAT
SMP
FC6h
SSPCON1
WCOL
SSPOV
FC5h
SSPCON2
GCEN
ACKSTAT
FC4h
ADRESH
A/D Result Register High Byte
FC3h
ADRESL
A/D Result Register Low Byte
FC2h
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
--00 0000 --00 0000
FC1h
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
--00 0000 --00 0000
FC0h
ADCON2
ADFM
—
—
—
—
ADCS2
ADCS1
ADCS0
0--- -000 0--- -000
FBFh
CCPR1H
Capture/Compare/PWM Register1 High Byte
FBEh
CCPR1L
Capture/Compare/PWM Register1 Low Byte
FBDh
CCP1CON
FBCh
CCPR2H
Capture/Compare/PWM Register2 High Byte
FBBh
CCPR2L
Capture/Compare/PWM Register2 Low Byte
FBAh
CCP2CON
FB9h
Reserved
rrrr rrrr rrrr rrrr
FB8h
Reserved
rrrr rrrr rrrr rrrr
FB7h
Reserved
rrrr rrrr rrrr rrrr
—
—
CKE
—
—
xxxx xxxx uuuu uuuu
D/A
0000 0000 0000 0000
P
S
R/W
UA
BF
0000 0000 0000 0000
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000 0000 0000
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
DC1B1
DC2B1
DC1B0
DC2B0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000 --uu uuuu
FB6h
FB5h
FB4h
FB3h
TMR3H
Timer3 Register High Byte
FB2h
TMR3L
Timer3 Register Low Byte
FB1h
T3CON
Legend
RD16
T3CCP2
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON 0000 0000 uuuu uuuu
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved
Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
2: These registers can only be modified when the Combination Lock is open.
3: These registers are available on PIC18C801 only.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 55
39541a.book Page 56 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 4-2:
File Name
FB0h
PSPCON
FAFh
SPBRG
REGISTER FILE SUMMARY - PIC18C601/801 (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
—
—
—
CMLK1
CMLK0
Value on
POR
Value on
all other
RESETS(1)
---- --00 ---- --00
USART Baud Rate Generator
0000 0000 0000 0000
0000 0000 0000 0000
FAEh
RCREG
USART Receive Register
FADh
TXREG
USART Transmit Register
FACh
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
FABh
RCSTA
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
FAAh
FA9h
FA8h
FA7h
CSEL2(2)
CSL7
CSL6
CSL5
CSL4
CSL3
CSL2
CSL1
CSL0
1111 1111 uuuu uuuu
FA6h
CSELIO (2)
CSIO7
CSIO6
CSIO5
CSIO4
CSIO3
CSIO2
CSIO1
CSIO0
1111 1111 uuuu uuuu
FA5h
FA4h
FA3h
FA2h
IPR2
—
—
—
—
BCLIP
LVDIP
TMR3IP
CCP2IP
---- 1111 ---- 1111
FA1h
PIR2
—
—
—
—
BCLIF
LVDIF
TMR3IF
CCP2IF
---- 0000 ---- 0000
FA0h
PIE2
—
—
—
—
BCLIE
LVDIE
TMR3IE
CCP2IE
---- 0000 ---- 0000
F9Fh
IPR1
—
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
-111 1111 -111 1111
F9Eh
PIR1
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000 -000 0000
F9Dh
PIE1
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000 -000 0000
F9Ch
MEMCON(2)
EBDIS
PGRM
WAIT1
WAIT0
—
—
WM1
WM0
0000 --00 0000 --00
F9Bh
F9Ah
TRISJ(3)
Data Direction Control Register for PORTJ
F99h
TRISH(3)
Data Direction Control Register for PORTH
F98h
TRISG
F96h
TRISF
Read PORTF Data Latch, Write PORTF Data Latch
1111 1111 1111 1111
F96h
TRISE
Data Direction Control Register for PORTE
1111 1111 1111 1111
F95h
TRISD
Data Direction Control Register for PORTD
1111 1111 1111 1111
F94h
TRISC
Data Direction Control Register for PORTC
1111 1111 1111 1111
F93h
TRISB
Data Direction Control Register for PORTB
1111 1111 1111 1111
F92h
TRISA
F91h
LATJ(3)
Read PORTJ Data Latch, Write PORTJ Data Latch
F90h
LATH(3)
Read PORTH Data Latch, Write PORTH Data Latch
F8Fh
LATG
—
—
—
—
—
—
—
1111 1111 1111 1111
1111 1111 1111 1111
Read PORTG Data Latch, Write PORTG Data Latch
Data Direction Control Register for PORTA
—
---1 1111 ---1 1111
--11 1111 --11 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Read PORTG Data Latch, Write PORTG Data Latch
---x xxxx ---u uuuu
F8Eh
LATF
Read PORTF Data Latch, Write PORTF Data Latch
xxxx xxxx uuuu uuuu
F8Dh
LATE
Read PORTE Data Latch, Write PORTE Data Latch
xxxx xxxx uuuu uuuu
F8Ch
LATD
Read PORTD Data Latch, Write PORTD Data Latch
xxxx xxxx uuuu uuuu
F8Bh
LATC
Read PORTC Data Latch, Write PORTC Data Latch
xxxx xxxx uuuu uuuu
F8Ah
LATB
Read PORTB Data Latch, Write PORTB Data Latch
xxxx xxxx uuuu uuuu
F89h
LATA
F88h
PORTJ(3)
Read PORTJ Pins, Write PORTJ Data Latch
F87h
PORTH(3)
Read PORTH pins, Write PORTH Data Latch
F86h
PORTG
F85h
PORTF
Legend
—
—
—
—
Read PORTA Data Latch, Write PORTA Data Latch
—
--xx xxxx --uu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Read PORTG pins, Write PORTG Data Latch
Read PORTF pins, Write PORTF Data Latch
---x xxxx ---u uuuu
xxxx xx00 uuuu uu00
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved
Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
2: These registers can only be modified when the Combination Lock is open.
3: These registers are available on PIC18C801 only.
DS39541B-page 56
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 57 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 4-2:
File Name
REGISTER FILE SUMMARY - PIC18C601/801 (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
RESETS(1)
F84h
PORTE
Read PORTE Pins, Write PORTE Data Latch
xxxx xxxx uuuu uuuu
F83h
PORTD
Read PORTD pins, Write PORTD Data Latch
xxxx xxxx uuuu uuuu
F82h
PORTC
Read PORTC pins, Write PORTC Data Latch
xxxx xxxx uuuu uuuu
F81h
PORTB
Read PORTB pins, Write PORTB Data Latch
F80h
PORTA
Legend
—
—
Read PORTA pins, Write PORTA Data Latch
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved
Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
2: These registers can only be modified when the Combination Lock is open.
3: These registers are available on PIC18C801 only.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 57
39541a.book Page 58 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
4.10
Access Bank
4.11
Bank Select Register (BSR)
The Access Bank is an architectural enhancement that
is very useful for C compiler code optimization. The
techniques used by the C compiler are also useful for
programs written in assembly.
The need for a large general purpose memory space
dictates a RAM banking scheme. When using direct
addressing, the BSR should be configured for the
desired bank.
This data memory region can be used for:
BSR holds the upper 4 bits of the 12-bit RAM
address. The BSR bits will always read ’0’s, and
writes will have no effect.
•
•
•
•
•
Intermediate computational values
Local variables of subroutines
Faster context saving/switching of variables
Common variables
Faster evaluation/control of SFR’s (no banking)
A MOVLB instruction has been provided in the instruction set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
The Access Bank is comprised of the upper 128 bytes
in Bank 15 (SFR’s) and the lower 128 bytes in Bank 0.
These two sections will be referred to as Access Bank
High and Access Bank Low, respectively. Figure 4-8
indicates the Access Bank areas.
Each Bank extends up to 0FFh (256 bytes). All data
memory is implemented as static RAM.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register, or in
the Access Bank.
A MOVFF instruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 provides a description of indirect addressing, which allows linear addressing of the entire RAM
space.
When forced in the Access Bank (a = ’0’), the last
address in Access Bank Low is followed by the first
address in Access Bank High. Access Bank High maps
all Special Function Registers so that these registers
can be accessed without any software overhead.
FIGURE 4-10:
DIRECT ADDRESSING
Direct Addressing
BSR
bank select(2)
7
from opcode(3)
0
location select(3)
00h
01h
0Eh
0Fh
000h
100h
E00h
F00h
0FFh
1FFh
EFFh
FFFh
Bank 14
Bank 15
Data
Memory(1)
Bank 0
Bank 1
Note 1: For register file map detail, see Table 4-2.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR) to the
registers of the Access Bank.
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
DS39541B-page 58
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 59 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
4.12
Indirect Addressing, INDF and
FSR Registers
Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction
is not fixed. A SFR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-11
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address
specified by the value of the FSR register.
Indirect addressing is possible by using one of the
INDFn (0 n 2) registers. Any instruction using the
INDFn register actually accesses the register indicated
by the File Select Register, FSRn (0 n 2). Reading
the INDFn register itself indirectly (FSRn = '0'), will read
00h. Writing to the INDFn register indirectly, results in a
no-operation. The FSRn register contains a 12-bit
address, which is shown in Figure 4-11.
Example 4-6 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 4-6:
LFSR
NEXTCLRF
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
FSR0, 100h
POSTINC0
BTFSS FSR0H, 1
BRA
NEXT
CONTINUE;
:
;
;
;
;
;
;
;
Clear INDF
register
& inc pointer
All done
with Bank1?
NO, clear next
; YES, continue
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bit wide. To store the 12-bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
1.
2.
3.
FSR0: composed of FSR0H:FSR0L
FSR1: composed of FSR1H:FSR1L
FSR2: composed of FSR2H:FSR2L
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect addressing, with the value in the corresponding FSR register
being the address of the data.
If INDF0, INDF1, or INDF2 are read indirectly via an
FSR, all '0's are read (zero bit is set). Similarly, if
INDF0, INDF1, or INDF2 are written to indirectly, the
operation will be equivalent to a NOP instruction and the
STATUS bits are not affected.
4.12.1
INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Performing an operation on one of these five registers determines how the FSR will be modified during indirect
addressing.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
• Do nothing to FSRn after an indirect access (no
change) - INDFn
• Auto-decrement FSRn after an indirect access
(post-decrement) - POSTDECn
• Auto-increment FSRn after an indirect access
(post-increment) - POSTINCn
• Auto-increment FSRn before an indirect access
(pre-increment) - PREINCn
• Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) - PLUSWn
When using the auto-increment or auto-decrement features, the effect on the FSR is not reflected in the
STATUS register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
Incrementing or decrementing an FSR affects all 12
bits. That is, when FSRnL overflows from an increment,
FSRnH will be incremented automatically.
Adding these features allows the FSRn to be used as a
software stack pointer, in addition to its uses for table
operations in data memory.
Each FSR has an address associated with it that performs an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configured to add the 2’s complement value in the
WREG register and the value in FSR to form the
address before an indirect access. The FSR value is
not changed.
If an indirect addressing operation is done where the
target address is an FSRnH or FSRnL register, the
write operation will dominate over the pre- or postincrement/decrement functions.
If an instruction writes a value to INDF0, the value will
be written to the address indicated by FSR0H:FSR0L.
A read from INDF1 reads the data from the address
indicated by FSR1H:FSR1L. INDFn can be used in
code anywhere an operand can be used.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 59
39541a.book Page 60 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 4-11:
INDIRECT ADDRESSING
Indirect Addressing
11
8
FSR Register
7
FSRnH
0
FSRnL
Location Select
0000h
Data
Memory(1)
0FFFh
Note 1: For register file map detail, see Table 4-2.
DS39541B-page 60
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 61 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
4.13
STATUS Register
The STATUS register, shown in Register 4-3, contains
the arithmetic status of the ALU. The STATUS register
can be the destination for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV, or N bits,
then the write to these five bits is disabled. These bits
are set or cleared according to the device logic. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.
REGISTER 4-3:
For example, CLRF STATUS will clear all implemented
bits and set the Z bit. This leaves the STATUS register
as ---0 0100 (where - = unimplemented).
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to
alter the STATUS register, because these instructions
do not affect the Z, C, DC, OV, or N bits from the
STATUS register. For other instructions which do not
affect the status bits, see Table 20-2.
Note:
The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
STATUS REGISTER
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
N
OV
Z
DC
C
bit 7
bit 0
bit 7-5
Unimplemented: Read as '0'
bit 4
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result of the ALU
operation was negative (ALU MSb = 1).
1 = Result was negative
0 = Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude, which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit
For arithmetic addition and subtraction instructions
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
Note:
bit 0
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRCF, RRNCF, RLCF, and
RLNCF) instructions, this bit is loaded with either the bit 4, or bit 3 of the source
register.
C: Carry/borrow bit
For arithmetic addition and subtraction instructions
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRCF, RLCF) instructions, this bit
is loaded with either the high, or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Advance Information
x = Bit is unknown
DS39541B-page 61
39541a.book Page 62 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
4.14
RCON Register
Note:
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device RESET. These flags include the TO, PD, POR
and RI bits. This register is readable and writable.
REGISTER 4-4:
It is recommended that the POR bit be set
after a Power-on Reset has been detected,
so that subsequent Power-on Resets may
be detected.
RCON REGISTER
R/W-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-0
U-0
IPEN
r
—
RI
TO
PD
POR
r
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6
Reserved: Maintain as ‘0’
bit 5
Unimplemented: Read as '0'
bit 4
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed
0 = The RESET instruction was executed causing a device RESET
(must be set in software after RESET instruction was executed)
bit 3
TO: Watchdog Time-out Flag bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 2
PD: Power-down Detection Flag bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 1
POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred
0 = A Power-on Reset occurred
(must be set in software after a Power-on Reset occurs)
bit 0
Reserved: Maintain as ‘0’
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
r
DS39541B-page 62
x = Bit is unknown
= Reserved
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 63 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
5.0
EXTERNAL MEMORY
INTERFACE
The External Memory Interface is a feature of the
PIC18C601/801 that allows the processor to access
external memory devices, such as FLASH, EPROM,
SRAM, etc. Memory mapped peripherals may also be
accessed.
The External Memory Interface physical implementation includes up to 26 pins on the PIC18C601 and up to
38 pins on the PIC18C801. These pins are reserved for
external address/data bus functions.
REGISTER 5-1:
These pins are multiplexed with I/O port pins, but the
I/O functions are only enabled when program execution
takes place in internal Boot RAM and the EBDIS bit in
the MEMCON register is set (see Register 5-1).
5.1
Memory Control Register
(MEMCON)
Register 5-1 shows the Memory Control Register
(MEMCON). This register contains bits used to control
the operation of the External Memory Interface.
MEMCON REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
EBDIS
PGRM
WAIT1
WAIT0
—
—
WM1
WM0
bit7
bit0
bit 7
EBDIS: External Bus Disable
1 = External system bus disabled, all external bus drivers are mapped as I/O ports
0 = External system bus enabled, and I/O ports are disabled
bit 6
PGRM: Program RAM Enable
1 = 512 bytes of internal RAM enabled as internal program memory from location 1FFE00h to
1FFFFFh, external program memory at these locations is unused. Internal GPR memory
from 400h to 5FFh is disabled and returns 00h.
0 = Internal RAM enabled as internal GPR memory from 400h to 5FFh. Program memory from
location 1FFE00h to 1FFFFFh is configured as external program memory.
bit 5-4
WAIT: Table Reads and Writes Bus Cycle Wait Count
11 = Table reads and writes will wait 0 TCY
10 = Table reads and writes will wait 1 TCY
01 = Table reads and writes will wait 2 TCY
00 = Table reads and writes will wait 3 TCY
bit 3-2
Unimplemented: Read as '0'
bit 1-0
WM: TABLWT Operation with 16-bit Bus
1X = Word Write mode: TABLAT0 and TABLAT1 word output, WRH active when TABLAT1 written
01 = Byte Select mode: TABLAT data copied on both MS and LS Byte, WRH and (UB or LB) will
activate
00 = Byte Write mode: TABLAT data copied on both MS and LS Byte, WRH or WRL will activate
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Advance Information
x = Bit is unknown
DS39541B-page 63
39541a.book Page 64 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
5.2
8-bit Mode
Therefore, the designer must choose external memory
devices according to timing calculations based on 1/2
Tcy (2 times instruction rate). For proper memory
speed selection, glue logic propagation delay times
must be considered along with setup and hold times.
The External Memory Interface can operate in 8-bit
mode. The mode selection is not software configurable,
but is programmable via the configuration bits.
There are two types of connections in 8-bit mode. They
are referred to as:
The Address Latch Enable (ALE) pin indicates that the
address bits A are available on the External
Memory Interface bus. The OE output enable signal will
enable one byte of program memory for a portion of the
instruction cycle, then BA0 will change and the second
byte will be enabled to form the 16-bit instruction word.
The least significant bit of the address, BA0, must be
connected to the memory devices in this mode.
Figure 5-1 shows an example of 8-bit Multiplexed
mode on the PIC18C601. The control signals used in
8-bit Multiplexed mode are outlined in Table 5-1.
Register 5-2 describes 8-bit Multiplexed mode timing.
• 8-bit Multiplexed
• 8-bit De-Multiplexed
5.2.1
8-BIT MULTIPLEXED MODE
The 8-bit Multiplexed mode applies only to the
PIC18C601. Data and address lines are multiplexed on
port pins and must be decoded with glue logic.
For 8-bit Multiplexed mode on the PIC18C601, the
instructions will be fetched as two 8-bit bytes on a
shared data/address bus (PORTD). The two bytes are
sequentially fetched within one instruction cycle (TCY).
FIGURE 5-1:
8-BIT MULTIPLEXED MODE EXAMPLE
D
A
AD
A
373
A0
ALE
D
PIC18C601
CE
OE WR(2)
BA0
A16, AD
CS1
OE
WRL
Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes.
TABLE 5-1:
8-BIT MULTIPLEXED MODE CONTROL SIGNALS
Name
8-bit Mux
Mode
RG0/ALE
ALE
RG1/OE
OE
RG2/WRL
WRL
Write Low (WRL) control pin
Byte address bit 0
Function
Address Latch Enable (ALE) control pin
Output Enable (OE) control pin
RG4/BA0
BA0
RF3/CSIO
CSIO
Chip Select I/O (See Section 5.4)
RF5/CS1
CS1
Chip Select 1 (See Section 5.4)
DS39541B-page 64
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 65 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 5-2:
8-BIT MULTIPLEXED MODE TIMING
Q1
Q2
Q4
03Ah
A16, AD
AD
Q3
ABh
55h
0Eh
BA0
ALE
OE
Opcode Fetch
MOVLW 55h
from 007556h
5.2.2
8-BIT DE-MULTIPLEXED MODE
The 8-bit De-Multiplexed mode applies only to the
PIC18C801. Data and address lines are available separately. External components are not necessary in this
mode.
For 8-bit De-Multiplexed mode on the PIC18C801, the
instructions are fetched as two 8-bit bytes on a dedicated data bus (PORTJ). The address will be presented for the entire duration of the fetch cycle on a
separate address bus. The two instruction bytes are
sequentially fetched within one instruction cycle (TCY).
Therefore, the designer must choose external memory
devices according to timing calculations, based on 1/2
TCY (2 times instruction rate). For proper memory speed
selection, setup and hold times must be considered.
2001-2013 Microchip Technology Inc.
The Address Latch Enable (ALE) pin is left unconnected, since glue logic is not necessary. The OE output enable signal will enable one byte of program
memory for a portion of the instruction cycle, then BA0
will change and the second byte will be enabled to form
the 16-bit instruction word. The least significant bit of
the address, BA0, must be connected to the memory
devices in this mode. Figure 5-3 shows an example of
8-bit De-Multiplexed mode on the PIC18C801. The
control signals used in 8-bit De-Multiplexed mode are
outlined in Register 5-2. Register 5-4 describes 8-bit
De-Multiplexed mode timing.
Advance Information
DS39541B-page 65
39541a.book Page 66 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 5-3:
8-BIT DE-MULTIPLEXED MODE EXAMPLE
BA0
A0
A
A
A, AD
D
D
D
PIC18C801
CE
OE WR(1)
ALE
CS1
OE
WRL
Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes.
TABLE 5-2:
8-BIT DE-MULTIPLEXED MODE CONTROL SIGNALS
Name
8-bit De-Mux Mode
RG0/ALE
ALE
Function
Address Latch Enable (ALE) control pin
RG1/OE
OE
RG2/WRL
WRL
Write Low (WRL) control pin
Output Enable (OE) control pin
Byte address bit 0
RG4/BA0
BA0
RF3/CSIO
CSIO
Chip Select I/O (See Section 5.4)
RF4/CS2
CS2
Chip Select 2 (See Section 5.4)
RF5/CS1
CS1
Chip Select 1 (See Section 5.4)
FIGURE 5-4:
8-BIT DE-MULTIPLEXED MODE TIMING
Q1
A16, AD
Q2
Q3
Q4
03Ah
55h
AD
0Eh
BA0
ALE
OE
Opcode Fetch
MOVLW 55h
from 007556h
DS39541B-page 66
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 67 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
5.3
16-bit Mode
The External Memory Interface can operate in 16-bit
mode. The mode selection is not software configurable,
but is programmable via the configuration bits.
The WM bits in the MEMCON register determine
three types of connections in 16-bit mode. They are
referred to as:
• 16-bit Byte Write
• 16-bit Word Write
• 16-bit Byte Select
These three different configurations allow the designer
maximum flexibility in using 8-bit and 16-bit memory
devices.
FIGURE 5-5:
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits A are available on the External Memory Interface bus. Following
the address latch, the output enable signal (OE ) will
enable both bytes of program memory at once to form
a 16-bit instruction word.
In Byte Select mode, JEDEC standard FLASH memories will require BA0 for the byte address line, and one
I/O line, to select between byte and word mode. The
other 16-bit modes do not need BA0. JEDEC standard
static RAM memories will use the UB or UL signals for
byte selection.
5.3.1
16-BIT BYTE WRITE MODE
Figure 5-5 shows an example of 16-bit Byte Write
mode for the PIC18C601/801.
16-BIT BYTE WRITE MODE EXAMPLE
D
(MSB)
PIC18C801
AD
373
A
D
A
D
CE
AD
373
(LSB)
A
OE
D
D
CE
WR(1)
OE
WR(1)
ALE
A
CS1
OE
WRH
WRL
Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 67
39541a.book Page 68 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
5.3.2
16-BIT WORD WRITE MODE
Figure 5-6 shows an example of 16-bit Word Write
mode for the PIC18C801.
FIGURE 5-6:
16-BIT WORD WRITE MODE EXAMPLE
PIC18C801
373
AD
A
JEDEC Word
EPROM Memory
A
D
D
CE
AD
OE
WR(1)
373
ALE
A
CS1
OE
WRH
Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes.
5.3.3
16-BIT BYTE SELECT MODE
Figure 5-7 shows an example of 16-bit Byte Select
mode for the PIC18C801.
FIGURE 5-7:
16-BIT BYTE SELECT MODE EXAMPLE
PIC18C801
AD
373
A
A
JEDEC Word
FLASH Memory
D
D
CE
A0
AD
373
ALE
BYTE/WORD
OE WR(1)
A
OE
WRH
WRL
BA0
A
A
JEDEC Word
SRAM Memory
I/O
CS1
CS2
D
D
CE
LB
LB
UB
UB
OE
WR (1)
Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes.
DS39541B-page 68
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 69 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
5.3.4
16-BIT MODE CONTROL SIGNALS
Table 5-3 describes the 16-bit mode control signals for
the PIC18C601/801.
TABLE 5-3:
PIC18C601/801 16-BIT MODE CONTROL SIGNALS
Name
18C601 16-bit
Mode
18C801 16-bit
Mode
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
RG4/BA0
RF3/CSIO
RF4/CS2
RF5/CS1
RF6/UB
RF7/LB
I/O
ALE
OE
WRL
WRH
BA0
CSIO
N/A
CS1
UB
LB
I/O
ALE
OE
WRL
WRH
BA0
CSIO
CS2
CS1
UB
LB
I/O
5.3.5
Function
Address Latch Enable (ALE) control pin
Output Enable (OE) control pin
Write Low (WRL) control pin
Write High (WRH) control pin
Byte address bit 0
Chip Select I/O (See Section 5.4)
Chip Select 2 (See Section 5.4)
Chip Select 1 (See Section 5.4)
Upper Byte Enable (UB) control pin
Lower Byte Enable (LB) control pin
I/O as BYTE/WORD control pin for JEDEC FLASH
16-BIT MODE TIMING
Figure 5-8 describes the 16-bit mode timing for the
PIC18C601/801.
FIGURE 5-8:
16-BIT MODE TIMING
Q1
Q4
Q3
Q2
03Ah
A16, AD
3AABh
AD
0E55h
BA0
ALE
OE
WRH
‘1’
WRL
‘1’
Opcode Fetch
MOVLW 55h
from 007556h
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 69
39541a.book Page 70 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
5.4
Chip Selects
Chip select signals are used to select regions of external memory and I/O devices for access. The
PIC18C801 has three chip selects and all are programmable. The chip select signals are CS1, CS2 and
CSIO. CS1 and CS2 are general purpose chip selects
that are used to enable large portions of program memory. CSIO is used to enable external I/O expansion.
The PIC18C601uses two of these programmable chip
selects: CS1 and CSIO.
REGISTER 5-2:
Two SFRs are used to control the chip select signals.
These are CSEL2 and CSELIO (see Register 5-2 and
Register 5-3). A chip select signal is asserted low when
the CPU makes an access to a dedicated range of
addresses specified in the chip select registers, CSEL2
and CSELIO. The 8-bit value found in either of these
registers is decoded as one of 256, 8K banks of program memory. If both chip select registers are 00h, all
of the chip select signals are disabled and their corresponding pins are configured as I/O. Since the last 512
bytes of program memory are dedicated to internal program RAM, the chip select signals will not activate if the
program memory address falls in this range.
CSEL2 REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CSL7
CSL6
CSL5
CSL4
CSL3
CSL2
CSL1
CSL0
bit 7
bit 7-0
bit 0
CSL: Chip Select 2 Address Decode bits
XXh = All eight bits are compared to the Most Significant bits PC of the program
counter. If PC CSL register, then the CS2 signal is low.
If PC < CSL, CS2 is high.
00h = CS2 is inactive
Legend:
REGISTER 5-3:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
CSELIO REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CSIO7
CSIO6
CSIO5
CSIO4
CSIO3
CSIO2
CSIO1
CSIO0
bit7
bit 7-0
bit0
CSIO: Chip Select IO Address Decode bits
XXh = All eight bits are compared to the Most Significant bits PC of the program
counter. If PC CSIO, then the CSIO signal is low. If not, CSIO is high.
00h = CSIO is inactive
Legend:
DS39541B-page 70
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Advance Information
x = Bit is unknown
2001-2013 Microchip Technology Inc.
39541a.book Page 71 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
5.4.1
CHIP SELECT 1 (CS1)
CS1 is enabled by writing a value other than 00h into
either the CSEL2 register, or the CSELIO register. If
both of the chip select registers are programmed to
00h, the CS1 signal is not enabled and the RF5 pin is
configured as I/O.
CS1 is low for all addresses in which CS2 and CSELIO
are high. Therefore, if CSEL2 = 20h and CSELIO = 80h,
then the CS1 signal will be low for the address that falls
between 000000h and (2000h x 20h) - 1 = 03FFFFh.
CS1 will always be low for the lower 8K of program
memory. Figure 5-9 shows an example address map for
CS1.
5.4.2
CHIP SELECT 2 (CS2)
CS2 is enabled for program memory accesses, starting
at the address derived by the 8-bit value contained in
CSEL2. For example, if the value contained in the
CSEL2 register is 80h, then the CS2 signal will be
asserted low whenever the address is greater than or
equal to 2000h x 80h = 100000h.
FIGURE 5-9:
A 00h value in the CSEL2 register will disable the CS2
signal and will configure the RF4 pin as I/O. Figure 5-9
shows an example address map for CS2.
5.4.3
CHIP SELECT I/O (CSIO)
CSIO is enabled for a fixed 8K address range starting
at the address defined by the 8-bit value contained in
CSELIO. If, for instance, the value contained in the
CSELIO register is 80h, then the CSIO signal will be
low for the address range between 100000h and
101FFFh.
If the 8K address block overlaps the address range
specified in the CSEL2 register, the CSIO signal will be
low, and the CS2 signal will be high, for that region.
A 00h value in the CSELIO register will disable the
CSIO signal and will configure the RF3 pin as I/O.
Figure 5-9 shows an example address map for CSIO.
EXAMPLE CONFIGURATION ADDRESS MAP FOR CS1, CS2, AND CSIO
CSEL2 = FFh (DEFAULT)
CSELIO = FFh (DEFAULT)
PROGRAM MEMORY
CSEL2 = 80h
CSELIO = 00h
CSEL2 = 20h
CSELIO = 80h
PROGRAM MEMORY
000000h
PROGRAM MEMORY
000000h
000000h
03FFFFh
040000h
0FFFFFh
100000h
0FFFFFh
100000h
101FFFh
102000h
1FFDFFh
1FFE00h
1FFFFFh
= CS1 ACTIVE
2001-2013 Microchip Technology Inc.
1FFDFFh
1FFE00h
1FFFFFh
= CS2 ACTIVE
= CSIO ACTIVE
Advance Information
1FFDFFh
1FFE00h
1FFFFFh
= NO CHIP SELECT ACTIVE
INTERNAL EXECUTION IF
PGRM = 1
DS39541B-page 71
39541a.book Page 72 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
5.5
External Wait Cycles
The external memory interface supports wait cycles.
Wait cycles only apply to Table Read and Table Write
operations over the external bus. See Section 6.0 for
more details.
Since the device execution is tied to instruction fetches,
there is no need to execute faster than the fetch rate.
So, if the program needs to be slowed, the processor
speed must be slowed with a different TCY time.
DS39541B-page 72
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 73 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
6.0
TABLE READS/TABLE WRITES
Table Read operations retrieve data from external program memory and place it into the data memory space.
Figure 6-1 shows the operation of a Table Read with
program and data memory.
PIC18C601/801 devices use two memory spaces: the
external program memory space and the data memory
space. Table Reads and Table Writes have been provided to move data between these two memory spaces
through an 8-bit register (TABLAT).
Table Write operations store data from the data memory space into external program memory. Figure 6-2
shows the operation of a Table Write with external program and data memory.
The operations that allow the processor to move data
between the data and external program memory
spaces are:
Table operations work with byte entities. A table block
containing data is not required to be word aligned, so a
table block can start and end at any byte address. If a
Table Write is being used to write an executable program to program memory, program instructions must
be word aligned.
• Table Read (TBLRD)
• Table Write (TBLWT)
FIGURE 6-1:
TABLE READ OPERATION
Table Latch (8-bit)
Table Pointer(1)
TBLPTRU
TBLPTRH
TABLAT
TBLPTRL
External Program Memory
Program Memory
(TBLPTR)
Instruction: TBLRD*
Note 1: Table Pointer points to a byte in external program memory.
FIGURE 6-2:
TABLE WRITE OPERATION
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TABLAT
TBLPTRL
External Program Memory
Instruction: TBLWT*
External
Program Memory
(TBLPTR)
Note 1: Table Pointer points to a byte in external program memory.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 73
39541a.book Page 74 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
6.1
Control Registers
6.1.2
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include:
• TABLAT register
• TBLPTR registers
6.1.1
TABLAT - TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program memory and data memory.
TABLE 6-1:
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers (Table Pointer Upper byte, High
byte and Low byte). These three registers
(TBLPTRU:TBLPTRH:TBLPTRL) join to form a 21-bit
wide pointer. The 21-bits allow the device to address up
to 2 Mbytes of program memory space.
The table pointer TBLPTR is used by the TBLRD and
TBLWRT instructions. These instructions can update
the TBLPTR in one of four ways, based on the table
operation. These operations are shown in Table 6-1.
These operations on the TBLPTR only affect the low
order 21-bits.
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example
TBLRD*
TBLWT*
Operation on Table Pointer
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
DS39541B-page 74
TBLPTR - TABLE POINTER
REGISTER
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 75 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
6.2
Table Read
Table Reads from external program memory are
performed one byte at a time. If the external interface is
8-bit, the bus interface circuitry in TABLAT will load the
external value into TABLAT. If the external interface is
16-bit, interface circuitry in TABLAT will select either the
high or low byte of the data from the 16-bit bus, based
on the least significant bit of the address.
The TBLRD instruction is used to retrieve data from
external program memory and place it into data
memory.
TBLPTR points to a byte address in external program
memory space. Executing TBLRD places the byte into
TABLAT. In addition, TBLPTR can be modified automatically for the next Table Read operation.
EXAMPLE 6-1:
; Read
CLRF
CLRF
MOVLW
MOVWF
TBLRD*
Example 6-1describes how to use TBLRD. Figure 6-3
and Figure 6-4 show Table Read timings for an 8-bit
external interface, and Figure 6-5 describes Table
Read timing for a 16-bit interface.
TABLE READ CODE EXAMPLE
a byte from location 0020h
TBLPTRU
; clear upper 5 bits of TBLPTR
TBLPTRH
; clear higher 8 bits of TBLPTR
20h
; Load 20h into
TBLPTRL
; TBLPTRL
; Data is in TABLAT
FIGURE 6-3:
TBLRD EXTERNAL INTERFACE TIMING (8-BIT MULTIPLEXED MODE)
Q1
Q2
A
AD
Q3
Q4
Q1
Q2
03Ah
AAh
08h
Q3
Q4
Q1
Q2
03Ah
00h
ABh
55h
Q3
Q4
Q1
Q2
CCFh
0Eh
33h
Q3
Q4
03Ah
92h
ACh
55h
0Fh
BA0
ALE
OE
'1'
WRH '1'
'1'
WRL '1'
Memory
Cycle
Instruction
Execution
Opcode Fetch
TBLRD*
from 007554h
Opcode Fetch
MOVLW 55h
from 007556h
TABLRD 92h
from 199E67h
INST(PC-2)
TBLRD Cycle1
TBLRD Cycle2
2001-2013 Microchip Technology Inc.
Advance Information
Opcode Fetch
ADDLW 55h
from 007558h
MOVLW
DS39541B-page 75
39541a.book Page 76 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 6-4:
TBLRD EXTERNAL INTERFACE TIMING (8-BIT DE-MULTIPLEXED MODE)
Q1
Q2
Q3
A
03AAAh
AD
08h
Q4
Q1
Q2
Q3
Q4
Q1
03AABh
00h
55h
Q2
Q3
Q4
Q1
CCF33h
0Eh
Q2
Q3
Q4
03AACh
55h
92h
BA0
ALE
OE
'1'
'1'
'1'
'1'
WRH
WRL
Memory
Cycle
Instruction
Execution
FIGURE 6-5:
Opcode Fetch
TBLRD*
from 007554h
Opcode Fetch
MOVLW 55h
from 007556h
TABLRD 92h
from 199E67h
INST(PC-2)
TBLRD Cycle1
TBLRD Cycle2
MOVLW
TBLRD EXTERNAL BUS TIMING (16-BIT MODE)
Q1
Q2
A
Q3
Q4
Q1
Q2
3AAAh
Q3
Q4
Q1
Q2
0h
0h
AD
Opcode Fetch
ADDLW 55h
from 007558h
0008h
3AABh
Q3
Q4
Q1
Q2
Ch
0E55h
CF33h
Q3
Q4
0h
9256h
3AACh
0F55h
BA0
ALE
OE
'1'
'1'
'1'
'1'
WRH
WRL
Memory
Cycle
Instruction
Execution
DS39541B-page 76
Opcode Fetch
TBLRD*
from 007554h
Opcode Fetch
MOVLW 55h
from 007556h
TABLRD 92h
from 199E67h
INST(PC-2)
TBLRD Cycle1
TBLRD Cycle2
Advance Information
Opcode Fetch
ADDLW 55h
from 007558h
MOVLW
2001-2013 Microchip Technology Inc.
39541a.book Page 77 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
6.3
Table Write
Table Write operations store data from the data memory space into external program memory.
PIC18C601/801devices perform Table Writes one byte
at a time. Table Writes to external memory are two-cycle
instructions, unless wait states are enabled. The last
cycle writes the data to the external memory location.
16-bit interface Table Writes depend on the type of
external device that is connected and the WM
bits in the MEMCON register (See Figure 5-2).
Example 6-2 describes how to use TBLWT.
EXAMPLE 6-2:
; Write
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
TBLWT*
TABLE WRITE CODE EXAMPLE
a byte to location 0020h
TBLPTRU
; clear upper 5 bits of TBLPTR
TBLPTRH
; clear higher 8 bits of TBLPTR
20h
; Load 20h into
TBLPTRL
; TBLPTRL
55h
; Load 55h into
TBLAT
; TBLAT
; Write it
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 77
39541a.book Page 78 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
6.3.1
8-BIT EXTERNAL TABLE WRITES
When the external bus is 8-bit, the byte-wide Table
Write exactly corresponds to the bus length and there
are no special considerations required.
The WRL signal is used as the active write signal.
Figure 6-6 and Figure 6-7 show the timings associated
with the 8-bit modes.
FIGURE 6-6:
TBLWT EXTERNAL INTERACE TIMING (8-BIT MULTIPLEXED MODE)
Q1
Q2
A
AD
Q3
Q4
Q1
Q2
03Ah
AAh
08h
Q3
Q4
Q1
Q2
03Ah
00h
ABh
55h
Q3
Q4
Q1
Q2
CCFh
0Eh
33h
Q3
Q4
03Ah
92h
ACh
55h
0Fh
BA0
ALE
OE
WRH '1'
WRL
Memory
Cycle
Instruction
Execution
DS39541B-page 78
Opcode Fetch
TBLWT*
from 007554h
Opcode Fetch
MOVLW 55h
from 007556h
INST(PC-2)
TBLWT Cycle1
TBLWT 92h
to 199E67h
TBLWT Cycle2
Advance Information
Opcode Fetch
ADDLW 55h
from 007558h
MOVLW
2001-2013 Microchip Technology Inc.
39541a.book Page 79 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 6-7:
TBLWT EXTERNAL INTERFACE TIMING (8-BIT DE-MULTIPLEXED MODE)
Q1
A
AD
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q2
03Ah
03Ah
08h
Q1
00h
55h
Q3
Q4
CCFh
0Eh
Q1
Q2
Q3
Q4
03Ah
92h
55h
0Fh
BA0
ALE
OE
WRH '1'
WRL
Memory
Cycle
Instruction
Execution
Opcode Fetch
TBLWT*
from 007554h
Opcode Fetch
MOVLW 55h
from 007556h
INST(PC-2)
TBLWT Cycle1
2001-2013 Microchip Technology Inc.
TBLWT 92h
to 199E67h
TBLWT Cycle2
Advance Information
Opcode Fetch
ADDLW 55h
from 007558h
MOVLW
DS39541B-page 79
39541a.book Page 80 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
6.3.2
16-BIT EXTERNAL TABLE WRITE
(BYTE WRITE MODE)
This mode allows Table Writes to byte-wide external
memories. During a TBLWT cycle, the TABLAT data is
presented on the upper and lower byte of the
AD bus. The appropriate WRH or WRL line is
strobed based on the LSb of the TBLPTR. Figure 6-8
shows the timing associated with this mode.
FIGURE 6-8:
TBLWT EXTERNAL INTERFACE TIMING (16-BIT BYTE WRITE MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A
AD
0h
0h
3AAAh
000Dh
3AABh
Ch
6FF4h
CF33h
0h
5656h
3AACh
0h
000Ch
3AADh
Ch
0E55h
CF33h
9292h
BA0
ALE
OE
WRH
WRL
UB
LB
Memory
Cycle
Instruction
Execution
Opcode Fetch
Opcode Fetch
TBLWT 56h
Opcode Fetch
Opcode Fetch
TBLWT 92h
TBLWT*+
from 007554h
MOVWF TABLAT
from 007556h
to 199E66h
TBLWT*
from 007558h
MOVLW 55h
from 00755Ah
to 199E67h
INST(PC-2)
TBLWT*+ Cycle1
TBLWT*+ Cycle2
MOVWF
TBLWT* Cycle1
TBLWT* Cycle2
DS39541B-page 80
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 81 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
6.3.3
EXTERNAL TABLE WRITE IN 16-BIT
WORD WRITE MODE
This mode allows Table Writes to any type of wordwide external memories.
This method makes a distinction between TBLWT
cycles to even or odd addresses.
During a TBLWT cycle to an even address, where
TBLPTR = 0, the TABLAT data is transferred to a
holding latch and the external address data bus is tristated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 6-9:
During a TBLWT cycle to an odd address, where
TBLPTR = 1, the TABLAT data is presented on the
upper byte of the AD bus. The contents of the
holding latch are presented on the lower byte of the
AD bus. The WRH line is strobed for each
write cycle and the WRL line is unused. The BA0 line
indicates the LSb of TBLPTR, but it is unnecessary.
The UB and LB lines are active to select both bytes.
The obvious limitation to this method is that the TBLWT
must be done in pairs on a specific word boundary to
correctly write a word location.
Figure 6-9 shows the timing associated with this mode.
TBLWT EXTERNAL INTERFACE TIMING (16-BIT WORD WRITE MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A
AD
0h
0h
3AAAh
000Dh
3AABh
Ch
0h
0h
Ch
CF33h
3AACh
Opcode Fetch
TBLWT 56h
Opcode Fetch
Opcode Fetch
TBLWT 92h
MOVWF TABLAT
from 007556h
to 199E66h
TBLWT*
from 007558h
MOVLW 55h
from 00755Ah
to 199E67h
MOVWF
TBLWT* Cycle1
TBLWT* Cycle2
6FF4h
000Ch
3AADh
0E55h
CF33h
9256h
BA0
ALE
OE
WRH
WRL '1'
UB
LB
Memory
Cycle
Instruction
Execution
Opcode Fetch
TBLWT*+
from 007554h
INST(PC-2)
TBLWT*+ Cycle1 TBLWT*+ Cycle2
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 81
39541a.book Page 82 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
6.3.4
16-BIT EXTERNAL TABLE WRITE
(BYTE SELECT MODE)
WRL line is unused. The BA0 or UB or UL lines are
used to select the byte to be written, based on the LSb
of the TBLPTR.
This mode allows Table Writes to word-wide external
memories that have byte selection capabilities. This
generally includes word-wide FLASH devices and
word-wide static RAM devices.
JEDEC standard flash memories will require a I/O port
line to become a BYTE/WORD input signal and will
use the BA0 signal as a byte address. JEDEC standard static RAM memories will use the UB or UL signals to select the byte.
During a TBLWT cycle, the TABLAT data is presented
on the upper and lower byte of the AD bus.
The WRH line is strobed for each write cycle and the
FIGURE 6-10:
Figure 6-10 shows the timing associated with this mode.
TBLWT EXTERNAL INTERFACE TIMING (16-BIT BYTE SELECT MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A
AD
0h
0h
3AAAh
000Dh
3AABh
Ch
6FF4h
CF33h
0h
5656h
3AACh
0h
000Ch
3AADh
Ch
0E55h
CF33h
9292h
BA0
ALE
OE
WRH
WRL '1'
UB
LB
Memory
Cycle
Instruction
Execution
Opcode Fetch
Opcode Fetch
TBLWT 56h
Opcode Fetch
Opcode Fetch
TBLWT 92h
TBLWT*+
from 007554h
MOVWF TABLAT
from 007556h
to 199E66h
TBLWT*
from 007558h
MOVLW 55h
from 00755Ah
to 199E67h
MOVWF
TBLWT* Cycle1
TBLWT* Cycle2
INST(PC-2)
DS39541B-page 82
TBLWT*+ Cycle1 TBLWT*+ Cycle2
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 83 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
6.4
Long Writes
The WAIT bits in the MEMCON register will select
0, 1, 2, or 3 extra TCY cycles per TBLRD/TBWLT cycle.
The wait will occur on Q4.
Long writes will not be supported on the PIC18C601/
801 to program FLASH configuration memory. The configuration locations can only be programmed in ICSP
mode.
6.5
The default setting of the wait on power-up is to assert
a maximum wait of 3TCY cycles. This insures that slow
memories will work in Microprocessor mode immediately after RESET.
External Wait Cycles
Figure 6-11 shows 8-bit external bus timing for a Table
Read with 2 wait cycles. Figure 6-12 shows 16-bit
external bus timing for a Table Read with 1 wait cycle.
The Table Reads and Writes have the capability to
insert wait states when accessing external memory.
These wait states only apply to the execution of a Table
Read or Write to external memory and not to instruction
fetches out of external memory. The guidelines presented in Section 5.0 must be followed to select the
proper memory speed grade for the device operating
frequency.
FIGURE 6-11:
Apparent Q
Actual Q
EXTERNAL INTERFACE TIMING (8-BIT MODE)
Q1 Q2
Q1 Q2
A
AD
Q3
Q3
Q4
Q4
Q1
Q1
Q2
Q2
03Ah
ABh
55h 0Eh
Q3
Q3
Q4
Q4
Q4
Q1
Q4
Q2
Q4
Q3
Q4
Q4
Q4
Q1
Q4
Q2
Q4
Q3
Q4
Q4
CCFh
33h
92h
BA0
ALE
OE
2TCY Wait
Opcode Fetch
MOVLW 55h
from 007556h
2001-2013 Microchip Technology Inc.
Table Read
of 92h
from 199E67h
Advance Information
DS39541B-page 83
39541a.book Page 84 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 6-12:
EXTERNAL INTERFACE TIMING (16-BIT MODE)
Apparent Q
Actual Q
Q1
Q1
Q2
Q2
A
Q3
Q3
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
0h
3AABh
AD
Q4
Q1
Q4
Q2
Q4
Q3
Q4
Q4
0Ch
0E55h
CF33h
9256h
BA0
ALE
OE
WRH
'1'
'1'
WRL
'1'
'1'
1TCY Wait
Opcode Fetch
MOVLW 55h
from 007556h
DS39541B-page 84
Table Read
of 92h
from 199E67h
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 85 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
7.0
8 X 8 HARDWARE MULTIPLIER
The performance increase allows the device to be used
in some applications previously reserved for Digital
Signal Processors.
An 8 x 8 hardware multiplier is included in the ALU of
PIC18C601/801 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product register pair (PRODH:PRODL). The multiplier does not
affect any flags in the STATUS register.
Table 7-1 shows a performance comparison between
enhanced devices using the single cycle hardware multiply, and performing the same function without the
hardware multiply.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
TABLE 7-1:
PERFORMANCE COMPARISON
Routine
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
Time
Program
Memory
(Words)
Cycles
(Max)
@ 25 MHz
@ 10 MHz
@ 4 MHz
Without hardware multiply
13
69
11.0 s
27.6 s
69.0 s
Hardware multiply
1
1
160.0 ns
400.0 ns
1.0 s
Without hardware multiply
33
91
14.6 s
36.4 s
91.0 s
Multiply Method
Hardware multiply
6
6
960.0 ns
2.4 s
6.0 s
Without hardware multiply
21
242
38.7 s
96.8 s
242.0 s
Hardware multiply
24
24
3.8 s
9.6 s
24.0 s
Without hardware multiply
52
254
40.6 s
102.6 s
254.0 s
Hardware multiply
36
36
5.8 s
14.4 s
36.0 s
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 85
39541a.book Page 86 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
7.1
Operation
EXAMPLE 7-3:
Example 7-1 shows the sequence to perform an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s most significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 7-1:
MOVFF
MULWF
8 x 8 UNSIGNED
MULTIPLY ROUTINE
ARG1, WREG
ARG2
EXAMPLE 7-2:
MOVFF
MULWF
ARG1, WREG
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH
MOVFF
BTFSC
SUBWF
ARG2, WREG
ARG1, SB
PRODH
;
;
;
;
;
ARG1 * ARG2 ->
PRODH:PRODL
Test Sign Bit
PRODH = PRODH
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
Example 7-3 shows the sequence to perform a 16 x 16
unsigned multiply. Equation 7-1 shows the algorithm
that is used. The 32-bit result is stored in 4 registers
RES3:RES0.
EQUATION 7-1:
RES3:RES0
=
=
DS39541B-page 86
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 216)+
(ARG1H ARG2L 28)+
(ARG1L ARG2H 28)+
(ARG1L ARG2L)
MOVFF
MULWF
ARG1L, WREG
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVFF
MULWF
ARG1H, WREG
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVFF
MULWF
ARG1L, WREG
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1
PRODH, W
RES2
WREG
RES3
MOVFF
MULWF
ARG1H, WREG
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1
PRODH, W
RES2
WREG
RES3
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
; ARG1 * ARG2 ->
;
PRODH:PRODL
8 x 8 SIGNED MULTIPLY
ROUTINE
16 x 16 UNSIGNED
MULTIPLY ROUTINE
;
;
;
;
;
;
;
;
ARG1L * ARG2H ->
PRODH:PRODL
Add cross
products
;
;
;
;
;
;
;
;
;
;
ARG1H * ARG2L ->
PRODH:PRODL
Add cross
products
Example 7-4 shows the sequence to perform a 16 x 16
signed multiply. Equation 7-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the arguments, each argument pairs’ most significant bit (MSb)
is tested and the appropriate subtractions are done.
EQUATION 7-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
= ARG1H:ARG1L ARG2H:ARG2L
+
= (ARG1H ARG2H 216)
+
(ARG1H ARG2L 28)
+
(ARG1L ARG2H 28)
(ARG1L ARG2L)
+
(-1 ARG2H ARG1H:ARG1L 216)
(-1 ARG1H ARG2H:ARG2L 216)
Advance Information
+
2001-2013 Microchip Technology Inc.
39541a.book Page 87 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
EXAMPLE 7-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
MOVFF
MULWF
ARG1L, WREG
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVFF
MULWF
ARG1H, WREG
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVFF
MULWF
ARG1L, WREG
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1
PRODH, W
RES2
WREG
RES3
MOVFF
MULWF
ARG1H, WREG
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1
PRODH, W
RES2
WREG
RES3
BTFSS
GOTO
MOVFF
SUBWF
MOVFF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, WREG
RES2
ARG1H, WREG
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, WREG
RES2
ARG2H, WREG
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
; ARG1L * ARG2L ->
;
PRODH:PRODL
;
;
;
; ARG1H * ARG2H ->
;
PRODH:PRODL
;
;
;
; ARG1L * ARG2H ->
;
PRODH:PRODL
;
; Add cross
;
products
;
;
;
;
;
; ARG1H * ARG2L ->
;
PRODH:PRODL
;
; Add cross
;
products
;
;
;
;
;
SIGN_ARG1
BTFSS
GOTO
MOVFF
SUBWF
MOVFF
SUBWFB
;
CONT_CODE
:
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 87
39541a.book Page 88 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
NOTES:
DS39541B-page 88
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 89 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
8.0
INTERRUPTS
PIC18C601/801 devices have 15 interrupt sources and
an interrupt priority feature that allows each interrupt
source to be assigned a high priority level, or a low priority level. The high priority interrupt vector is at
000008h and the low priority interrupt vector is at
000018h. High priority interrupt events will override any
low priority interrupts that may be in progress.
There are 10 registers that are used to control interrupt
operation. These registers are:
•
•
•
•
•
•
•
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2
PIE1, PIE2
IPR1, IPR2
It is recommended that the Microchip header files supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
Each interrupt source has three bits to control its operation. The functions of these bits are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are
compatible with PIC® mid-range devices. In Compatibility mode, the interrupt priority bits for each source
have no effect. The PEIE bit (INTCON register)
enables/disables all peripheral interrupt sources. The
GIE bit (INTCON register) enables/disables all interrupt
sources. All interrupts branch to address 000008h in
Compatibility mode.
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL
bit. High priority interrupt sources can interrupt a low
priority interrupt.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts, to avoid recursive interrupts.
The "return from interrupt" instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
The interrupt priority feature is enabled by setting the
IPEN bit (RCON register). When interrupt priority is
enabled, there are two bits that enable interrupts globally. Setting the GIEH bit (INTCON register) enables
all interrupts that have the priority bit set. Setting the
GIEL bit (INTCON register) enables all interrupts that
have the priority bit cleared. When the interrupt flag,
enable bit and appropriate global interrupt enable bit
are set, the interrupt will vector immediately to address
000008h or 000018h, depending on the priority level.
Individual interrupts can be disabled through their corresponding enable bits.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 89
39541a.book Page 90 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 8-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0F
INT0E
INT1F
INT1E
INT1P
INT2F
INT2E
INT2P
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Wake-up if in SLEEP mode
Interrupt to CPU
Vector to location
0008h
GIEH/GIE
TMR1IF
TMR1IE
TMR1IP
IPEN
IPEN
XXXXIF
XXXXIE
XXXXIP
GIEL/PEIE
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR0IF
TMR0IE
TMR0IP
TMR1IF
TMR1IE
TMR1IP
RBIF
RBIE
RBIP
XXXXIF
XXXXIE
XXXXIP
Interrupt to CPU
Vector to Location
0018h
GIEL\PEIE
INT0F
INT0E
Additional Peripheral Interrupts
INT1F
INT1E
INT1P
INT2F
INT2E
INT2P
DS39541B-page 90
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 91 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
8.1
Control Registers
8.1.1
This section contains the control and status registers.
REGISTER 8-1:
INTCON REGISTERS
The INTCON Registers are readable and writable
registers, which contain various enable, priority, and
flag bits.
INTCON REGISTER
R/W-0
R/W-0
GIE/GIEH PEIE/GIEL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
bit 7
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high priority interrupts
0 = Disables all high priority interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all priority peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Note:
x = Bit is unknown
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows software polling.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 91
39541a.book Page 92 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 8-2:
INTCON2 REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
U-0
R/W-1
U-0
R/W-1
RBPU
INTEDG0
INTEDG1
INTEDG2
—
TMR0IP
—
RBIP
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5
INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4
INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3
Unimplemented: Read as ’0’
bit 2
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
Unimplemented: Read as ’0’
bit 0
RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Note:
DS39541B-page 92
x = Bit is unknown
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows software polling.
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 93 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 8-3:
INTCON3 REGISTER
R/W-1
R/W-1
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
bit 7
bit 0
bit 7
INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
Unimplemented: Read as ’0’
bit 4
INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2
Unimplemented: Read as ’0’
bit 1
INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Note:
x = Bit is unknown
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows software polling.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 93
39541a.book Page 94 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
8.1.2
PIR REGISTERS
8.1.3
The Peripheral Interrupt Request (PIR) registers contain the individual flag bits for the peripheral interrupts
(Register 8-5). There are two Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2).
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON register).
2: User software should ensure the appropriate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
PIE REGISTERS
The Peripheral Interrupt Enable (PIE) registers contain
the individual enable bits for the peripheral interrupts
(Register 8-6). There are two two Peripheral Interrupt
Enable registers (PIE1, PIE2). When IPEN is clear, the
PEIE bit must be set to enable any of these peripheral
interrupts.
8.1.4
IPR REGISTERS
The Interrupt Priority (IPR) registers contain the individual priority bits for the peripheral interrupts (Register 8-9).
There are two Peripheral Interrupt Priority registers
(IPR1, IPR2). The operation of the priority bits requires
that the Interrupt Priority Enable bit (IPEN) be set.
8.1.5
RCON REGISTER
The Reset Control (RCON) register contains the bit that
is used to enable prioritized interrupts (IPEN).
REGISTER 8-4:
RCON REGISTER
R/W-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-0
U-0
IPEN
r
—
RI
TO
PD
POR
r
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6
Reserved: Maintain as '0'
bit 5
Unimplemented: Read as '0'
bit 4
RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-4
bit 3
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-4
bit 2
PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-4
bit 1
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-4
bit 0
Reserved: Maintain as '0'
Legend:
DS39541B-page 94
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Advance Information
x = Bit is unknown
2001-2013 Microchip Technology Inc.
39541a.book Page 95 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 8-5:
PIR1 REGISTER
U-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
Unimplemented: Read as ’0’
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
(must be cleared in software)
0 = The A/D conversion is not complete
bit 5
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer, RCREG, is full
(cleared when RCREG is read)
0 = The USART receive buffer is empty
bit 4
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer, TXREG, is empty
(cleared when TXREG is written)
0 = The USART transmit buffer is full
bit 3
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete
(must be cleared in software)
0 = Waiting to transmit/receive
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred
(must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred
(must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred
(must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed
(must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Advance Information
x = Bit is unknown
DS39541B-page 95
39541a.book Page 96 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 8-6:
PIR2 REGISTER
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
BCLIF
LVDIF
TMR3IF
CCP2IF
bit 7
bit 0
bit 7-4
Unimplemented: Read as’0’
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred
(must be cleared in software)
0 = No bus collision occurred
bit 2
LVDIF: Low Voltage Detect Interrupt Flag bit
1 = A low voltage condition occurred
(must be cleared in software)
0 = The device voltage is above the Low Voltage Detect trip point
bit 1
TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed
(must be cleared in software)
0 = TMR3 register did not overflow
bit 0
CCP2IF: CCPx Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred
(must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred
(must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
Legend:
DS39541B-page 96
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Advance Information
x = Bit is unknown
2001-2013 Microchip Technology Inc.
39541a.book Page 97 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 8-7:
PIE1 REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
Unimplemented: Read as ’0’
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Advance Information
x = Bit is unknown
DS39541B-page 97
39541a.book Page 98 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 8-8:
PIE2 REGISTER
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
BCLIE
LVDIE
TMR3IE
CCP2IE
bit 7
bit 0
bit 7-4
Unimplemented: Read as '0'
bit 3
BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
LVDIE: Low Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enables the TMR3 overflow interrupt
0 = Disables the TMR3 overflow interrupt
bit 0
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
DS39541B-page 98
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Advance Information
x = Bit is unknown
2001-2013 Microchip Technology Inc.
39541a.book Page 99 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 8-9:
IPR1 REGISTER
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
bit 7
Unimplemented: Read as ’0’
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RCIP: USART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TXIP: USART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Advance Information
x = Bit is unknown
DS39541B-page 99
39541a.book Page 100 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 8-10:
IPR2 REGISTER
U-0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
—
BCLIP
LVDIP
TMR3IP
CCP2IP
bit 7
bit 0
bit 7-4
Unimplemented: Read as '0'
bit 3
BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
LVDIP: Low Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
DS39541B-page 100
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Advance Information
x = Bit is unknown
2001-2013 Microchip Technology Inc.
39541a.book Page 101 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
8.1.6
INT INTERRUPTS
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge triggered: either rising, if the
corresponding INTEDGx bit is set in the INTCON2 register, or falling, if the INTEDGx bit is clear. When a valid
edge appears on the RBx/INTx pin, the corresponding
flag bit INTxIF is set. This interrupt can be disabled by
clearing the corresponding enable bit INTxIE. Flag bit
INTxIF must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wake-up the
processor from SLEEP, if bit INTxIE was set prior to
going into SLEEP. If the global interrupt enable bit GIE
is set, the processor will branch to the interrupt vector
following wake-up.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits INT1IP
(INTCON3 register) and INT2IP (INTCON3 register).
There is no priority bit associated with INT0; it is always
a high priority interrupt source.
8.1.7
TMR0 INTERRUPT
In 8-bit mode (which is the default), an overflow
(0FFh 00h) in the TMR0 register will set flag bit
TMR0IF. In 16-bit mode, an overflow (0FFFFh 0000h)
EXAMPLE 8-1:
in the TMR0H:TMR0L registers will set flag bit TMR0IF.
The interrupt can be enabled/disabled by setting/clearing enable bit TMR0IE (INTCON register). Interrupt priority for Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2 register). See
Section 10.0 for further details on the Timer0 module.
8.1.8
PORTB INTERRUPT-ON-CHANGE
An input change on PORTB sets flag bit RBIF
(INTCON register). The interrupt can be enabled/
disabled by setting/clearing enable bit RBIE (INTCON
register). Interrupt priority for PORTB interrupt-onchange is determined by the value contained in the
interrupt priority bit RBIP (INTCON2 register).
8.2
Context Saving During Interrupts
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return
from interrupt is not used (See Section 4.3), the user
may need to save the WREG, STATUS and BSR registers in software. Depending on the user’s application,
other registers may also need to be saved. Example 8-1
saves and restores the WREG, STATUS and BSR
registers during an Interrupt Service Routine.
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
W_TEMP
MOVFF
STATUS, STATUS_TEMP
MOVFF
BSR, BSR_TEMP
;
; USER ISR CODE
;
MOVFF
BSR_TEMP, BSR
MOVF
W_TEMP, W
MOVFF
STATUS_TEMP, STATUS
2001-2013 Microchip Technology Inc.
; W_TEMP is in Low Access bank
; STATUS_TEMP located anywhere
; BSR located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
Advance Information
DS39541B-page 101
39541a.book Page 102 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
NOTES:
DS39541B-page 102
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 103 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
9.0
I/O PORTS
EXAMPLE 9-1:
Depending on the device selected, there are up to 9
ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral
features on the device. In general, when a peripheral is
enabled, that pin may not be used as a general
purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
CLRF
PORTA
CLRF
LATA
MOVLW
MOVWF
MOVLW
07h
ADCON1
0CFh
MOVWF
TRISA
INITIALIZING PORTA
;
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTA by
clearing output
data latches
Alternate method
to clear output
data latches
Configure A/D
for digital inputs
Value used to
initialize data
direction
Set RA3:RA0 as inputs
RA5:RA4 as outputs
The data latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are driving.
9.1
FIGURE 9-1:
PORTA, TRISA and LATA
Registers
PORTA is a 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
On a Power-on Reset, these pins are configured as
analog inputs and read as '0'.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
RA3:RA0 AND RA5 PINS
BLOCK DIAGRAM
RD LATA
Data
Bus
D
Q
VDD
WR LATA
or
WR PORTA
CK
Q
D
CK
Note:
I/O pin(1)
VSS
Analog
Input
Mode
Q
TRIS Latch
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA4/
T0CKI pin is a Schmitt Trigger input and an open drain
output. All other RA port pins have TTL input levels and
full CMOS output drivers.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
N
Q
WR TRISA
Read-modify-write operations on the LATA register,
reads and writes the latched output value for PORTA.
The other PORTA pins are multiplexed with analog
inputs and the analog VREF+ and VREF- inputs. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register1). On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
P
Data Latch
RD TRISA
Q
D
TTL
Input
Buffer
EN
RD PORTA
SS Input (RA5 only)
To A/D Converter and LVD Modules
Note 1: I/O pins have diode protection to VDD and VSS.
On a Power-on Reset, PORTA pins
RA3:RA0 and RA5 default to analog inputs.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 103
39541a.book Page 104 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 9-2:
RA4/T0CKI PIN BLOCK
DIAGRAM
RD LATA
Data
Bus
Q
D
WR LATA
or
WR PORTA
CK
Q
WR TRISA
D
Q
CK
Q
I/O pin(1)
N
Data Latch
VSS
Schmitt
Trigger
Input
Buffer
TRIS Latch
RD TRISA
Q
D
ENEN
RD PORTA
TMR0 Clock Input
Note 1: I/O pin has diode protection to VSS only.
TABLE 9-1:
PORTA FUNCTIONS
Name
Bit#
Buffer
RA0/AN0
bit0
TTL
Input/output or analog input
RA1/AN1
bit1
TTL
Input/output or analog input
RA2/AN2/VREF-
bit2
TTL
Input/output or analog input or VREF-
RA3/AN3/VREF+
bit3
TTL
Input/output or analog input or VREF+
RA4/T0CKI
bit4
RA5/SS/AN4/LVDIN
bit5
Function
ST/OD Input/output or external clock input for Timer0, output is open drain type
TTL
Input/output or slave select input for synchronous serial port or analog
input or low voltage detect input
Legend: TTL = TTL input, ST = Schmitt Trigger input, OD = Open Drain
TABLE 9-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
—
—
RA5
RA4
RA3
RA2
RA1
RA0
LATA
—
Latch A Data Output Register
TRISA
—
PORTA Data Direction Register
ADCON1
—
—
VCFG1 VCFG0
PCFG3
Value on
POR,
BOR
Value on all
other
RESETS
--0x 0000 --uu uuuu
-xxx xxxx -uuu uuuu
-111 1111 -111 1111
PCFG2
PCFG1
PCFG0 --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by PORTA.
DS39541B-page 104
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 105 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
9.2
PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding PORTB pin an output ( i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATB register
read and write the latched output value for PORTB.
EXAMPLE 9-2:
CLRF
PORTB
CLRF
LATB
MOVLW
0CFh
MOVWF
TRISB
INITIALIZING PORTB
;
;
;
;
;
;
;
;
;
;
;
;
FIGURE 9-3:
Initialize PORTB by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RB3:RB0 as inputs
RB5:RB4 as outputs
RB7:RB6 as inputs
RB7:RB4 PINS BLOCK
DIAGRAM
VDD
RBPU(2)
Data Bus
WR LATB
or
WR PORTB
WR TRISB
Weak
P Pull-up
Data Latch
D
Q
I/O pin(1)
CK
TRIS Latch
D
Q
TTL
Input
Buffer
CK
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2 register). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Pin RB3 is multiplexed with the CCP input/output. The
weak pull-up for RB3 is disabled when the RB3 pin is
configured as CCP pin. By disabling the weak pull-up
when pin is configured as CCP, allows the remaining
weak pull-up devices of PORTB to be used while the
CCP is being used.
Four of PORTB’s pins, RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’d together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON register).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
ST
Buffer
RD TRISB
RD LATB
Latch
Q
D
EN
RD PORTB
Q1
Set RBIF
From other
RB7:RB4 pins
Q
D
RD PORTB
EN
Q3
RBx/INTx
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2 register).
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 105
39541a.book Page 106 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 9-4:
RB2:RB0 PINS BLOCK
DIAGRAM
VDD
RBPU(2)
Data Bus
Weak
P Pull-up
Data Latch
D
Q
I/O pin(1)
WR Port
CK
TRIS Latch
D
Q
WR TRIS
TTL
Input
Buffer
CK
RD TRIS
Q
RD Port
RBx/INTx
D
EN
Schmitt Trigger
Buffer
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2 register).
FIGURE 9-5:
RB3 PIN BLOCK DIAGRAM
VDD
RBPU(2)
CCP Enable
Weak
P Pull-up
CCP Output
1
VDD
P
Enable
CCP Output
0
Data Latch
Data Bus
D
WR LATB or
WR PORTB
CK
I/O pin(1)
Q
N
VSS
TRIS Latch
WR TRISB
D
Q
CK
Q
TTL
Input
Buffer
RD TRISB
RD LATB
Q
RD PORTB
D
EN
RD PORTB
CCP2 Input
Schmitt Trigger
Buffer
Note 1: I/O pin has diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2).
DS39541B-page 106
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 107 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 9-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
(1)
RB0/INT0
bit0
TTL/ST
Input/output pin or external interrupt 0 input. Internal software
programmable weak pull-up.
RB1/INT1
bit1
TTL/ST(1)
Input/output pin or external interrupt 1 input. Internal software
programmable weak pull-up.
RB2/INT2
bit2
TTL/ST(1)
Input/output pin or external interrupt 2 input. Internal software
programmable weak pull-up.
RB3/CCP2
bit3
TTL/ST(3)
Input/output pin or Capture2 input or Capture2 output or PWM2 output.
Internal software programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB6
bit6
TTL/ST(2)
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming clock.
RB7
bit7
TTL/ST(2)
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming data.
Legend:
Note 1:
2:
3:
TTL = TTL input, ST = Schmitt Trigger input
This pin is a Schmitt Trigger input when configured as the external interrupt.
This pin is a Schmitt Trigger input when used in Serial Programming mode.
This pin is a Schmitt Trigger input when used in a Capture input.
TABLE 9-4:
Name
PORTB
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx uuuu uuuu
LATB
LATB Data Output Register
TRISB
PORTB Data Direction Register
INTCON
Value on
all other
RESETS
Bit 7
GIE/GIEH PEIE/GIEL
INTCON2
RBPU
INTEDG0
INTCON3
INT2IP
INT1IP
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
TMR0IE
INT0IE
RBIE
TMR0IF INT0IF
INTEDG1 INTEDG2 INTEDG3 TMR0IP
—
INT2IE
INT1IE
—
—
RBIF
0000 000x 0000 000u
RBIP
1111 1111 1111 1111
INT2IF INT1IF 1100 0000 1100 0000
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTD.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 107
39541a.book Page 108 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
9.3
PORTC, TRISC and LATC
Registers
The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
EXAMPLE 9-3:
Read-modify-write operations on the LATC register,
read and write the latched output value for PORTC.
PORTC is multiplexed with several peripheral functions
(Table 9-5). PORTC pins have Schmitt Trigger input
buffers.
CLRF
PORTC
CLRF
LATC
MOVLW
0CFh
MOVWF
TRISC
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make
a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.
FIGURE 9-6:
INITIALIZING PORTC
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTC by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RC3:RC0 as inputs
RC5:RC4 as outputs
RC7:RC6 as inputs
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Peripheral Out Select
Peripheral Data Out
VDD
0
P
RD LATC
Data Bus
WR LATC
or
WR PORTC
WR TRISC
D
Q
CK
Q
1
I/O pin(1)
TRIS OVERRIDE
Data Latch
D
Q
CK
Q
N
VSS
TRIS
Override
TRIS Latch
Peripheral Enable
Schmitt
Trigger
RD TRISC
Q
D
EN
Pin
Override Peripheral
RC0
Yes
Timer1 OSC for
Timer1/Timer3
RC1
Yes
Timer1 OSC for
Timer1/Timer3
RC2
No
—
RC3
Yes
SPI/I2C Master Clock
RC4
Yes
I2C Data Out
RC5
Yes
SPI Data Out
RC6
Yes
USART Async Xmit,
Sync Clock
RC7
Yes
USART Sync Data Out
RD PORTC
Peripheral Data In
Note 1: I/O pins have diode protection to VDD and VSS.
DS39541B-page 108
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 109 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 9-5:
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0/T1OSO/T13CKI
bit0
ST
RC1/T1OSI
bit1
ST
Input/output port pin, Timer1 oscillator input.
RC2/CCP1
bit2
ST
Input/output port pin or Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
bit3
ST
Input/output port pin or synchronous serial clock for SPI/I2C.
RC4/SDI/SDA
bit4
ST
Input/output port pin or SPI Data in (SPI mode) or Data I/O
(I2C mode).
Input/output port pin or Timer1 oscillator output or Timer1/Timer3
clock input.
RC5/SDO
bit5
ST
Input/output port pin or Synchronous Serial Port Data output.
RC6/TX/CK
bit6
ST
Input/output port pin, Addressable USART Asynchronous Transmit, or
Addressable USART Synchronous Clock.
RC7/RX/DT
bit7
ST
Input/output port pin, Addressable USART Asynchronous Receive, or
Addressable USART Synchronous Data.
Legend: ST = Schmitt Trigger input
TABLE 9-6:
Name
PORTC
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
LATC
LATC Data Output Register
xxxx xxxx
uuuu uuuu
TRISC
PORTC Data Direction Register
1111 1111
1111 1111
Legend: x = unknown, u = unchanged
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 109
39541a.book Page 110 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
9.4
PORTD, TRISD and LATD
Registers
FIGURE 9-7:
PORTD is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISD bit (= 0) will
make the corresponding PORTD pin an output (i.e., put
the contents of the output latch on the selected pin).
Read-modify-write operations on the LATD register
reads and writes the latched output value for PORTD.
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or
output.
RD LATD
Data Bus
WR LATD
or
WR PORTD
On a Power-on Reset, PORTD defaults to
the system bus.
WR TRISD
CLRF
PORTD
CLRF
LATD
MOVLW
0CFh
MOVWF
TRISD
DS39541B-page 110
Q
I/O pin
CK
Data Latch
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
RD TRISD
Q
D
ENEN
RD PORTD
Note:
EXAMPLE 9-4:
D
D
PORTD is multiplexed with the system bus and is available only when the system bus is disabled, by setting
EBIDS bit in register MEMCON. When operating as
the system bus, PORTD is the low order byte of the
address/data bus (AD7:AD0), or as the low order
address byte (A15:A8) if the address and data buses
are de-multiplexed.
Note:
PORTD BLOCK DIAGRAM
IN I/O MODE
I/O pins have diode protection to VDD and VSS.
INITIALIZING PORTD
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTD by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RD3:RD0 as inputs
RD5:RD4 as outputs
RD7:RD6 as inputs
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 111 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 9-8:
PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
EN
RD PORTD
RD LATD
Data Bus
D
Q
Port
Data
WR LATD
or
PORTD
1
CK
Data Latch
D
WR TRISD
I/O pin(1)
0
Q
TTL
Input
Buffer
CK
TRIS Latch
Bus Enable
System Bus Data/TRIS Out
Control
Drive Bus
RD TRISD
Instruction Register
Instruction Read
Note 1: I/O pins have protection diodes to VDD and VSS.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 111
39541a.book Page 112 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 9-7:
PORTD FUNCTIONS
Name
Bit#
(2)
RD1/AD1/A1(2)
Buffer Type
Function
bit0
ST/TTL
(1)
Input/output port pin or system bus bit 0
bit1
ST/TTL(1)
Input/output port pin or system bus bit 1
RD2/AD2/A2(2)
bit2
ST/TTL(1)
Input/output port pin or system bus bit 2
RD3/AD3/A3(2)
bit3
ST/TTL(1)
Input/output port pin or system bus bit 3
RD4/AD4/A4(3)
bit4
ST/TTL(1)
Input/output port pin or system bus bit 4
RD5/AD5/A5(2)
bit5
ST/TTL(1)
Input/output port pin or system bus bit 5
RD6/AD6/A6(2)
bit6
ST/TTL(1)
Input/output port pin or system bus bit 6
RD7/AD7/A7(2)
bit7
ST/TTL(1)
Input/output port pin or system bus bit 7
RD0/AD0/A0
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus mode.
2: RDx is used as a multiplexed address/data bus for PIC18C601 and PIC18C801 in 16-bit mode, and as an
address only for PIC18C801 in 8-bit mode.
TABLE 9-8:
Name
PORTD
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
LATD
LATD Data Output Register
xxxx xxxx
uuuu uuuu
TRISD
PORTD Data Direction Register
1111 1111
1111 1111
0000 --00
0000 --00
MEMCON
EBDIS
PGRM
WAIT1
WAIT0
—
—
WM1
WM0
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.
DS39541B-page 112
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 113 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
9.5
PORTE, TRISE and LATE
Registers
byte of the address/data bus (AD15:AD8), or as the
high order address byte (A15:A8), if address and data
buses are de-multiplexed.
PORTE is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e., put
the contents of the output latch on the selected pin).
Note:
EXAMPLE 9-5:
Read-modify-write operations on the LATE register
reads and writes the latched output value for PORTE.
PORTE is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or
output. PORTE is multiplexed with several peripheral
functions (Table 9-9).
PORTE is multiplexed with the system bus and is available only when the system bus is disabled, by setting
EBDIS bit in register MEMCON. When operating as the
system bus, PORTE is configured as the high order
FIGURE 9-9:
On Power-on Reset, PORTE defaults to
the system bus.
CLRF
PORTE
CLRF
LATE
MOVLW
03h
MOVWF
TRISE
INITIALIZING PORTE
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTE by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RE1:RE0 as inputs
RE7:RE2 as outputs
PORTE BLOCK DIAGRAM IN I/O MODE
Peripheral Out Select
Peripheral Data Out
VDD
0
P
1
I/O pin(1)
RD LATE
Data Bus
WR LATE
or
WR PORTE
WR TRISE
D
Q
CK
Q
Data Latch
D
Q
CK
Q
N
TRIS OVERRIDE
VSS
TRIS
Override
Pin
Override
Peripheral
RE0
Yes
External Bus
RE1
Yes
External Bus
RE2
Yes
External Bus
RE3
Yes
External Bus
D
RE4
Yes
External Bus
EN
RE5
Yes
External Bus
RD PORTE
RE6
Yes
External Bus
Peripheral Data In
RE7
Yes
External Bus
TRIS Latch
Peripheral Enable
Schmitt
Trigger
RD TRISE
Q
Note 1: I/O pins have diode protection to VDD and VSS.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 113
39541a.book Page 114 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 9-10:
PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
EN
RD PORTE
RD LATD
Data Bus
D
Q
Port
Data
WR LATE
or
PORTE
1
CK
Data Latch
TRIS Latch
D
WR TRISE
External Enable
System Bus
Control
I/O pin(1)
0
Q
TTL
Input
Buffer
CK
RD TRISE
Data/Address Out
Drive System
To Instruction Register
Instruction Read
Note 1: I/O pins have diode protection to VDD and VSS.
DS39541B-page 114
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 115 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 9-9:
PORTE FUNCTIONS
Name
Bit#
Buffer Type
Function
RE0/AD8/A8(2)
bit0
ST/TTL(1)
Input/output port pin or Address/Data bit 8
RE1/AD9/A9(2)
bit1
ST/TTL(1)
Input/output port pin or Address/Data bit 9
RE2/AD10/A10(2)
bit2
ST/TTL(1)
Input/output port pin or Address/Data bit 10
RE3/AD11/A11(2)
bit3
ST/TTL(1)
Input/output port pin or Address/Data bit 11
RE4/AD12/A12(2)
bit4
ST/TTL(1)
Input/output port pin or Address/Data bit 12
RE5/AD13/A13(2)
bit5
ST/TTL(1)
Input/output port pin or Address/Data bit 13
RE6/AD14/A14(2)
bit6
ST/TTL(1)
Input/output port pin or Address/Data bit 14
RE7/AD15/A15(2)
bit7
ST/TTL(1)
Input/output port pin or Address/Data bit 15
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus mode.
2: REx is used as a multiplexed address/data bus for PIC18C601 and PIC18C801 in 16-bit mode, and as an
address only for PIC18C801 in 8-bit mode.
TABLE 9-10:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other
RESETS
TRISE
PORTE Data Direction Control Register
1111 1111
1111 1111
PORTE
Read PORTE pin/Write PORTE Data Latch
xxxx xxxx
uuuu uuuu
Read PORTE Data Latch/Write PORTE Data Latch
xxxx xxxx
uuuu uuuu
0000 --00
0000 --00
LATE
MEMCON
EBDIS
PGRM
WAIT1
WAIT0
—
—
WM1
WM0
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTE.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 115
39541a.book Page 116 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
9.6
PORTF, LATF, and TRISF
Registers
EXAMPLE 9-7:
PORTF is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISF. Setting a
TRISF bit (= 1) will make the corresponding PORTF pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISF bit (= 0) will
make the corresponding PORTF pin an output (i.e., put
the contents of the output latch on the selected pin).
Read-modify-write operations on the LATF register
reads and writes the latched output value for PORTF.
PORTF pins, RF2:RF0, are multiplexed with analog
inputs. The operation of these pins are selected by
ADCON0 and ADCON1 registers.
PORTF pins, RF3 and RF5, are multiplexed with two of
the integrated chip select signals CSIO and CS1. For
PIC18C801, pin RF4 is multiplexed with chip select signal CS2, while for PIC18C601, it is multiplexed with
system bus signal A16. For PIC18C801 devices, both
CSEL2 and CSELIO registers must set to all zero, to
enable these pins as I/O pins, while for PIC18C601
devices, only CSELIO register needs to be set to zero.
For PIC18C601 devices, pin RF4 can only be configured as I/O when the EBDIS bit is set and execution is
taking place in internal Boot RAM.
PORTF pins, RF7:RF6, are multiplexed with the system bus control signal UB and LB, respectively, when a
device with 16-bit bus execution is used. These pins
can be configured as I/O pins by setting WM bits in the
MEMCON register to any value other than ’01’.
Note 1: On Power-on Reset, PORTF
RF2:RF0 default to A/D inputs.
CLRF
PORTF
CLRF
LATF
MOVLW
MOVWF
MOVLW
0Fh
ADCON1
0CFh
MOVWF
TRISF
; Program chip select to activate CS1
; for all address less than 03FFFFh,
; while activate CS2 for rests of the
; addresses
; CSEL2 register is secured register.
; Before it can be modified it,
; combination lock must be opened
MOVLW 20h
; Preload WREG with
; correct CSEL2 valu
BCF INTCON, GIE
; Disable interrupts
CALL UNLOCK
; Now unlock it
; Lock is open. Modify CSEL2...
MOVWF CSEL2
; Lock is closed
BSF INTCON, GIE
; Re-enable interrupts
; Chip select is programmed.
UNLOCK
BSF PSPCON, CMLK1
BSF PSPCON, CMLK0
RETURN
FIGURE 9-11:
RD LATF
Data Bus
D
Q
CK
Q
VDD
WR LATF
or
WR PORTF
P
Data Latch
D
Q
CK
Q
N
I/O pin
INITIALIZING PORTF
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTF by
clearing output
data latches
Alternate method
to clear output
data latches
Set PORTF as digital I/O
Value used to
initialize data
direction
Set RF3:RF0 as inputs
RF5:RF4 as outputs
RF7:RF6 as inputs
WR TRISF
VSS
Analog
Input
Mode
TRIS Latch
ST
Input
Buffer
RD TRISF
Q
D
EN
RD PORTF
To A/D Converter
Note:
DS39541B-page 116
RF2:RF0 PINS BLOCK
DIAGRAM
pins
2: On Power-on Reset, PORTF pins
RF7:RF3 for PIC18C801 and pins
RF7:RF5, RF3 for PIC18C601, default to
system bus signals.
EXAMPLE 9-6:
PROGRAMMING CHIP
SELECT SIGNALS
Advance Information
I/O pins have diode protection to VDD and VSS.
2001-2013 Microchip Technology Inc.
39541a.book Page 117 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 9-12:
RF5:RF3 PINS BLOCK DIAGRAM
Q
D
EN
EN
RD PORTF
RD LATF
Data Bus
WR LATF
or
PORTF
D
Data
1
Data Latch
TRIS Latch
Q
CK
RD TRISF
CS Out
System Bus
Control
I/O pin(1)
0
CK
D
WR TRISF
Port
Q
External Enable
Drive System
Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 9-13:
RF7:RF6 PINS BLOCK DIAGRAM
Q
D
EN
EN
RD PORTF
RD LATF
Data Bus
D
Q
Port
Data
WR LATF
or
PORTF
UB/LB Out
System Bus
Control WM = ’01’
Drive System
1
CK
Data Latch
TRIS Latch
D
WR TRISF
I/O pin(1)
0
Q
CK
RD TRISF
Note 1: I/O pins have diode protection to VDD and VSS.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 117
39541a.book Page 118 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 9-11:
PORTF FUNCTIONS
Name
Bit#
Buffer Type
RF0/AN5
bit0
ST
RF1/AN6
bit1
ST
RF2/AN7
bit2
ST
RF3/CSIO
bit3
ST
RF4/A16/CS2(1)
bit4
ST
RF5/CS1
bit5
ST
RF6/LB
bit6
ST
RF7/UB
bit7
ST
Legend: ST = Schmitt Trigger input
Function
Input/output port pin or analog input
Input/output port pin or analog input
Input/output port pin or analog input
Input/output port pin or I/O chip select
Input/output port pin or chip select 2 or address bit 16
Input/output port pin or chip select 1
Input/output port pin or low byte select signal for external memory
Input/output port pin or high byte select signal for external memory
Note 1: CS2 is available only on PIC18C801.
TABLE 9-12:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other
RESETS
TRISF
PORTF Data Direction Control Register
1111 1111
1111 1111
PORTF
Read PORTF pin/Write PORTF Data Latch
xxxx xxxx
uuuu uuuu
Read PORTF Data Latch/Write PORTF Data Latch
0000 0000
uuuu uuuu
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
--00 0000
--00 0000
WAIT1
0000 --00
0000 --00
LATF
ADCON1
—
—
MEMCON
EBDIS
PGRM
WAIT0
—
—
WM1
WM0
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTF.
DS39541B-page 118
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 119 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
9.7
PORTG, LATG, and TRISG
Registers
FIGURE 9-14:
PORTG is a 5-bit wide, bi-directional port. The corresponding data direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISG bit (= 0) will
make the corresponding PORTG pin an output (i.e., put
the contents of the output latch on the selected pin).
Read-modify-write operations on the LATG register
read and write the latched output value for PORTG.
PORTG is multiplexed with system bus control signals
ALE, OE, WRH, WRL and BA0. The WRH signal is the
only signal that is disabled and configured as a port pin
(RG3) during external program execution in 8-bit mode.
All other pins are by default, system bus control signals. PORTG can be configured as an I/O port by setting EBDIS bit in the MEMCON register and when
execution is taking place in internal program RAM.
Note:
RD LATG
Data
Bus
WR LATG
or
PORTG
PORTG BLOCK DIAGRAM
IN I/O MODE
D
Q
I/O pin(1)
CK
Data Latch
D
WR TRISG
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
RD TRISG
Q
On Power-on Reset, PORTG defaults to
system bus signals.
D
ENEN
RD PORTG
EXAMPLE 9-8:
CLRF
PORTG
CLRF
LATG
MOVLW
04h
MOVWF
TRISG
INITIALIZING PORTG
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTG by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RG1:RG0 as outputs
RG2 as input
RG4:RG3 as outputs
2001-2013 Microchip Technology Inc.
Note 1: I/O pins have diode protection to VDD and VSS.
Advance Information
DS39541B-page 119
39541a.book Page 120 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 9-15:
PORTG BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
EN
RD PORTG
RD LATG
Data Bus
D
Q
Port
Data
WR LATG
or
PORTG
I/O pin(1)
0
1
CK
Data Latch
D
WR TRISG
Q
CK
TRIS Latch
RD TRISG
Control Out
System Bus
Control
External Enable
Drive System
Note 1: I/O pins have diode protection to VDD and VSS.
TABLE 9-13:
Name
PORTG FUNCTIONS
Bit#
Buffer Type
RG0/ALE
bit0
ST
RG1/OE
bit1
ST
RG2/WRL
bit2
ST
RG3/WRH
bit3
ST
RG4/BA0
bit4
ST
Legend: ST = Schmitt Trigger input
TABLE 9-14:
Name
Function
Input/output port pin or Address Latch Enable signal for external memory
Input/output port pin or Output Enable signal for external memory
Input/output port pin or Write Low byte signal for external memory
Input/output port pin or Write High byte signal for external memory
Input/output port pin or Byte Address 0 signal for external memory
SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other
RESETS
TRISG
PORTG Data Direction Control Register
---1 1111
---1 1111
PORTG
Read PORTG pin/Write PORTG Data Latch
---x xxxx
---u uuuu
Read PORTG Data Latch/Write PORTG Data Latch
---x xxxx
---u uuuu
0000 --00
0000 --00
LATG
MEMCON
EBDIS
PGRM
WAIT1
WAIT0
—
—
WM1 WM0
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTG.
DS39541B-page 120
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 121 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
9.8
Note:
PORTH, LATH, and TRISH
Registers
FIGURE 9-16:
RH3:RH0 PINS BLOCK
DIAGRAM IN I/O MODE
PORTH is available only on PIC18C801
devices.
PORTH is an 8-bit wide, bi-directional I/O port. The corresponding data direction register is TRISH. Setting a
TRISH bit (= 1) will make the corresponding PORTH
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISH bit (= 0) will
make the corresponding PORTH pin an output (i.e., put
the contents of the output latch on the selected pin).
Read-modify-write operations on the LATH register
read and write the latched output value for PORTH.
RD LATH
Data
Bus
WR LATH
or
PORTH
D
Q
I/O pin(1)
CK
Data Latch
D
WR TRISH
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
Pins RH7:RH4 are multiplexed with analog inputs
AN18:AN11, while pins RH3:RH0 are multiplexed with
system address bus A19:A16. By default, pins
RH7:RH4 will setup as A/D inputs and pins RH3:RH0
will setup as system address bus. Register ADCON1
configures RH7:RH4 as I/O or A/D inputs. Register
MEMCON configures RH3:RH0 as I/O or system bus
pins.
RD TRISH
Q
D
ENEN
RD PORTH
Note 1: On Power-on Reset, PORTH pins
RH7:RH4 default to A/D inputs and read
as ’0’.
2: On Power-on Reset, PORTH pins
RH3:RH0 default to system bus signals.
EXAMPLE 9-9:
CLRF
CLRF
PORTH
LATH
MOVLW
MOVWF
MOVLW
0Fh
ADCON1
0CFh
MOVWF
TRISH
Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 9-17:
RH7:RH4 PINS BLOCK
DIAGRAM
INITIALIZING PORTH
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTH by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RH3:RH0 as inputs
RH5:RH4 as outputs
RH7:RH6 as inputs
RD LATH
Data
Bus
WR LATH
or
PORTH
D
Q
I/O pin(1)
CK
Data Latch
D
WR TRISH
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
RD TRISH
Q
D
ENEN
RD PORTH
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 121
39541a.book Page 122 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 9-18:
RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
EN
RD PORTH
RD LATD
Data Bus
WR LATH
or
PORTH
D
Q
Port 0
Data 1
CK
Data Latch
D
WR TRISH
Q
CK
TRIS Latch
External Enable.
System Bus
Control
I/O pin(1)
TTL
Input
Buffer
RD TRISH
Address Out
Drive System
To Instruction Register
Instruction Read
Note 1: I/O pins have diode protection to VDD and VSS.
DS39541B-page 122
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 123 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 9-15:
PORTH FUNCTIONS
Name
Bit#
Buffer Type
Function
RH0/A16(1)
bit0
ST
Input/output port pin or Address bit 16 for external memory interface
RH1/A17(1)
bit1
ST
Input/output port pin or Address bit 17 for external memory interface
RH2/A18(1)
bit2
ST
Input/output port pin or Address bit 18 for external memory interface
RH3/A19(1)
bit3
ST
Input/output port pin or Address bit 19 for external memory interface
RH4/AN8(1)
bit4
ST
Input/output port pin or analog input channel 8
RH5/AN9(1)
bit5
ST
Input/output port pin or analog input channel 9
RH6/AN10(1)
bit6
ST
Input/output port pin or analog input channel 10
RH7/AN11(1)
bit7
ST
Input/output port pin or analog input channel 11
Legend: ST = Schmitt Trigger input
Note 1: PORTH is available only on PIC18C801 devices.
TABLE 9-16:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other
RESETS
TRISH
PORTH Data Direction Control Register
1111 1111
1111 1111
PORTH
Read PORTH pin/Write PORTH Data Latch
xxxx xxxx
uuuu uuuu
Read PORTH Data Latch/Write PORTH Data Latch
xxxx xxxx
uuuu uuuu
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
--00 0000
--00 0000
WAIT1
0000 --00
0000 --00
LATH
ADCON1
—
—
MEMCON
EBDIS
PGRM
WAIT0
—
—
WM1
WM0
Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are not used by PORTH.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 123
39541a.book Page 124 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
9.9
Note:
PORTJ, LATJ, and TRISJ
Registers
FIGURE 9-19:
PORTJ is available only on PIC18C801
devices.
PORTJ is an 8-bit wide, bi-directional I/O port. The corresponding data direction register is TRISJ. Setting a
TRISJ bit (= 1) will make the corresponding PORTJ pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISJ bit (= 0) will
make the corresponding PORTJ pin an output (i.e., put
the contents of the output latch on the selected pin).
Read-modify-write operations on the LATJ register
read and write the latched output value for PORTJ.
RD LATJ
Data
Bus
WR LATJ
or
PORTJ
D
Q
I/O pin(1)
CK
Data Latch
D
WR TRISJ
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
PORTJ is multiplexed with de-multiplexed system data
bus D7:D0, when device is configured in 8-bit execution
mode. Register MEMCON configures PORTJ as I/O or
system bus pins.
Note:
PORTJ BLOCK DIAGRAM
IN I/O MODE
RD TRISJ
On Power-on Reset, PORTJ defaults to
system bus signals.
Q
D
ENEN
RD PORTJ
EXAMPLE 9-10:
CLRF
PORTJ
CLRF
LATJ
MOVLW
0CFh
MOVWF
TRISJ
DS39541B-page 124
INITIALIZING PORTJ
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTJ by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RJ3:RJ0 as inputs
RJ5:RJ4 as outputs
RJ7:RJ6 as inputs
Note 1: I/O pins have diode protection to VDD and VSS.
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 125 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 9-20:
PORTJ BLOCK DIAGRAM IN SYSTEM DATA BUS MODE
Q
D
EN
EN
RD PORTJ
RD LATD
Data Bus
WR LATJ
or
PORTJ
D
Q
Port 0
Data 1
I/O pin(1)
CK
Data Latch
TRIS Latch
WR TRISJ
External Enable
System Bus
Control
D
Q
CK
S
R
TTL
Input
Buffer
RD TRISJ
Data Out
Drive System
To Instruction Register
Instruction Read
Note 1: I/O pins have diode protection to VDD and VSS.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 125
39541a.book Page 126 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 9-17:
PORTJ FUNCTIONS
Name
Bit#
Buffer Type
Function
RJ0/D0(1)
bit0
ST/TTL
Input/output port pin
RJ1/D1(1)
bit1
ST/TTL
Input/output port pin
RJ2/D2(1)
bit2
ST/TTL
Input/output port pin
RJ3/D3(1)
bit3
ST/TTL
Input/output port pin
RJ4/D4(1)
bit4
ST/TTL
Input/output port pin
RJ5/D5(1)
bit5
ST/TTL
Input/output port pin
RJ6/D6(1)
bit6
ST/TTL
Input/output port pin
RJ7/D7(1)
bit7
ST/TTL
Input/output port pin
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: PORTJ is available only on PIC18C801 devices.
TABLE 9-18:
Name
or Data bit 0 for external memory interface
or Data bit 1 for external memory interface
or Data bit 2 for external memory interface
or Data bit 3 for external memory interface
or Data bit 4 for external memory interface
or Data bit 5 for external memory interface
or Data bit 6 for external memory interface
or Data bit 7 for external memory interface
SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other
RESETS
TRISJ
PORTJ Data Direction Control Register
1111 1111
1111 1111
PORTJ
Read PORTJ pin/Write PORTJ Data Latch
xxxx xxxx
uuuu uuuu
Read PORTJ Data Latch/Write PORTJ Data Latch
xxxx xxxx
uuuu uuuu
0000 --00
0000 --00
LATJ
MEMCON
EBDIS
PGRM
WAIT1
WAIT0
—
—
WM1
WM0
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTJ.
DS39541B-page 126
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 127 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
10.0
TIMER0 MODULE
Register 10-1 shows the Timer0 Control register
(T0CON).
The Timer0 module has the following features:
• Software selectable as an 8-bit or 16-bit timer/
counter
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt on overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
• Edge select for external clock
REGISTER 10-1:
Figure 10-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 10-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
The T0CON register is a readable and writable register
that controls all the aspects of Timer0, including the
prescale selection.
Note:
Timer0 is enabled on POR.
T0CON REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
bit 7
bit 0
bit 7
TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6
T08BIT: Timer0 8-bit/16-bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0
T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 prescale value
110 = 1:128 prescale value
101 = 1:64 prescale value
100 = 1:32 prescale value
011 = 1:16 prescale value
010 = 1:8 prescale value
001 = 1:4 prescale value
000 = 1:2 prescale value
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Advance Information
x = Bit is unknown
DS39541B-page 127
39541a.book Page 128 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 10-1:
TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus
FOSC/4
0
8
0
1
RA4/T0CKI
pin(2)
Programmable
Prescaler
1
Sync with
Internal
Clocks
TMR0L
(2 TCY delay)
T0SE
3
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
T0PS2, T0PS1, T0PS0
T0CS(1)
Note 1: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
2: I/O pins have diode protection to V DD and VSS.
FIGURE 10-2:
FOSC/4
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
0
0
1
Programmable
Prescaler
RA4/T0CKI
pin(2)
T0SE
1
Sync with
Internal
Clocks
TMR0
High Byte
TMR0L
8
(2 TCY delay)
3
Read TMR0L
T0PS2, T0PS1, T0PS0
T0CS
(1)
Set Interrupt
Flag bit TMR0IF
on Overflow
Write TMR0L
PSA
8
8
TMR0H
8
Data Bus
Note 1: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
2: I/O pins have diode protection to VDD and VSS.
DS39541B-page 128
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 129 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
10.1
Timer0 Operation
10.2.1
SWITCHING PRESCALER
ASSIGNMENT
Timer0 can operate as a timer or as a counter.
The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program
execution).
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0L register is written, the increment is inhibited for the following two instruction cycles. The user can work around
this by writing an adjusted value to the TMR0L register.
10.3
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or FFFFh
to 0000h in 16-bit mode. This overflow sets the TMR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IF bit must be cleared in software by the Timer0 module Interrupt Service Routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from SLEEP, since the
timer is shut-off during SLEEP.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment either on every
rising, or falling edge, of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source
Edge Select bit (T0SE). Clearing the T0SE bit selects
the rising edge. Restrictions on the external clock input
are discussed below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
10.2
10.4
Prescaler
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 10-1). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16-bits of Timer0 without
having to verify that the read of the high and low byte
were valid, due to a rollover between successive reads
of the high and low byte.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF TMR0,
MOVWF TMR0, BSF TMR0, x.... etc.) will clear the
prescaler count.
Name
A write to the high byte of Timer0 must also take place
through the TMR0H buffer register. Timer0 high byte is
updated with the contents of the buffered value of
TMR0H, when a write occurs to TMR0L. This allows all
16-bits of Timer0 to be updated at once.
Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the prescaler
count but will not change the prescaler
assignment.
TABLE 10-1:
16-Bit Mode Timer Reads and
Writes
Timer0 can be set in 16-bit mode by clearing T0CON
T08BIT. Registers TMR0H and TMR0L are used to
access 16-bit timer value.
An 8-bit counter is available as a prescaler for the
Timer0 module. The prescaler is not readable or
writable.
Note:
Timer0 Interrupt
REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
TMR0L
Timer0 Module’s Low Byte Register
xxxx xxxx
uuuu uuuu
TMR0H
Timer0 Module’s High Byte Register
0000 0000
0000 0000
INTCON
GIE/GIEH
0000 000x
0000 000u
T0CON
TMR0ON
T0PS1 T0PS0 1111 1111
1111 1111
TRISA
—
--11 1111
--11 1111
PEIE/GIEL TMR0IE INT0IE
T08BIT
T0CS
T0SE
RBIE
TMR0IF INT0IF
PSA
T0PS2
PORTA Data Direction Register
RBIF
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 129
39541a.book Page 130 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
11.0
TIMER1 MODULE
Register 11-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module as well as contains the Timer1 oscillator enable
bit (T1OSCEN). Timer1 can be enabled/disabled by
setting/clearing control bit TMR1ON (T1CON register).
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter
(Two 8-bit registers: TMR1H and TMR1L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• RESET from CCP module special event trigger
REGISTER 11-1:
Figure 11-1 is a simplified block diagram of the Timer1
module.
Note:
Timer1 is disabled on POR.
T1CON REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RD16
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register Read/Write of TImer1 in one 16-bit operation
0 = Enables register Read/Write of Timer1 in two 8-bit operations
bit 6
Unimplemented: Read as '0'
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 Oscillator is enabled
0 = Timer1 Oscillator is shut-off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
DS39541B-page 130
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Advance Information
x = Bit is unknown
2001-2013 Microchip Technology Inc.
39541a.book Page 131 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
11.1
Timer1 Operation
When TMR1CS is clear, Timer1 increments every
instruction cycle. When TMR1CS is set, Timer1 increments on every rising edge of the external clock input
or the Timer1 oscillator, if enabled.
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is set),
the RC1/T1OSI and RC0/T1OSO/T1CKI pins become
inputs. That is, the TRISC value is ignored.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON register).
Note:
Timer1 also has an internal “RESET input”. This RESET
can be generated by the CCP module (Table 14.0).
When Timer1 is configured in an Asynchronous mode, care must be taken to
make sure that there is no incoming pulse
while Timer1 is being turned off. If there is
an incoming pulse while Timer1 is being
turned off, Timer1 value may become
unpredictable.
If an application requires that Timer1 be
turned off and if it is possible that Timer1
may receive an incoming pulse while being
turned off, synchronize the external clock
first, by clearing the T1SYNC bit of register
T1CON. Please note that this may cause
Timer1 to miss up to one count.
FIGURE 11-1:
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag Bit
TMR1
TMR1H
0
CLR
TMR1L
1
TMR1ON
On/Off
T1SYNC
T1OSC
T13CKI/T1OSO
T1OSI
1
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
Synchronized
Clock Input
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
T1CKPS1:T1CKPS0
SLEEP Input
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 131
39541a.book Page 132 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 11-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus
8
TMR1H
8
8
Write TMR1L
Special Event Trigger
Read TMR1L
TMR1IF
Overflow
Interrupt
Flag bit
Timer 1
High Byte
Synchronized
Clock Input
0
TMR1
8
TMR1L
1
TMR1ON
On/Off
T1SYNC
T1OSC
T13CKI/T1OSO
T1OSI
1
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
SLEEP Input
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
DS39541B-page 132
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 133 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
11.2
Timer1 Oscillator
11.4
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON register). The
oscillator is a low power oscillator rated up to 200 kHz.
It will continue to run during SLEEP. It is primarily
intended for a 32 kHz crystal. Table 11-1 shows the
capacitor selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
TABLE 11-1:
Osc Type
LP
If the CCP module is configured in Compare mode
to
generate
a
“special
event
trigger"
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR registers).
CAPACITOR SELECTION FOR
THE ALTERNATE
OSCILLATOR
Timer1 must be configured for either Timer, or Synchronized Counter mode, to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
Freq
In the event that a write to Timer1 coincides with a special
event trigger from CCP1, the write will take precedence.
32 kHz
C1
TBD
(1)
C2
(1)
TBD
Crystal to be Tested:
32.768 kHz Epson C-001R32.768K-A 20 PPM
Note 1: Microchip suggests 33 pF as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components.
4: Capacitor values are for design guidance
only.
11.3
Resetting Timer1 using a CCP
Trigger Output
Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit TMR1IF (PIR registers). This interrupt can be enabled/disabled by setting/
clearing TMR1 interrupt enable bit TMR1IE (PIE
registers).
2001-2013 Microchip Technology Inc.
In this mode of operation, the CCPR1H:CCPR1L registers pair, effectively becomes the period register for
Timer1.
11.5
Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 11-2). When the RD16 control bit (T1CON
register) is set, the address for TMR1H is mapped to a
buffer register for the high byte of Timer1. A read from
TMR1L will load the contents of the high byte of Timer1
into the Timer1 high byte buffer. This provides the user
with the ability to accurately read all 16 bits of Timer1,
without having to determine whether a read of the high
byte followed by a read of the low byte is valid, due to
a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16-bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place
through the Timer1 high byte buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.
Advance Information
DS39541B-page 133
39541a.book Page 134 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 11-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000 -000 0000
PIE1
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000 -000 0000
—
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
-000 0000 -000 0000
IPR1
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
T1CON
Legend:
RD16
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC TMR1CS
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR1ON
0-00 0000 u-uu uuuu
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
DS39541B-page 134
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 135 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
12.0
TIMER2 MODULE
12.1
The Timer2 module timer has the following features:
•
•
•
•
•
•
•
8-bit timer (TMR2 register)
8-bit period register (PR2)
Readable and writable (both registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Interrupt on TMR2 match of PR2
SSP module optional use of TMR2 output to
generate clock shift
Register 12-1 shows the Timer2 Control register.
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON register), to minimize power consumption.
Figure 12-1 is a simplified block diagram of the Timer2
module. The prescaler and postscaler selection of
Timer2 are controlled by this register.
Timer2 Operation
Timer2 can be used as the PWM time-base for the PWM
mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device RESET.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4,
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON register). The match output of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2
interrupt (latched in flag bit TMR2IF, PIR registers).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device RESET (Power-on Reset, MCLR
Reset, or Watchdog Timer Reset)
TMR2 is not cleared when T2CON is written.
Note:
REGISTER 12-1:
Timer2 is disabled on POR.
T2CON REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Advance Information
x = Bit is unknown
DS39541B-page 135
39541a.book Page 136 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
12.2
Timer2 Interrupt
12.3
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
FIGURE 12-1:
Output of TMR2
The output of TMR2 (before the postscaler) is a clock
input to the Synchronous Serial Port module, which
optionally uses it to generate the shift clock.
TIMER2 BLOCK DIAGRAM
Sets Flag
bit TMR2IF
TMR2
Output(1)
Prescaler
FOSC/4
TMR2
1:1, 1:4, 1:16
2
RESET
Postscaler
Comparator
EQ
1:1 to 1:16
T2CKPS1:T2CKPS0
4
PR2
TOUTPS3:TOUTPS0
Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.
TABLE 12-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000 -000 0000
PIE1
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000 -000 0000
—
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
-000 0000 -000 0000
IPR1
TMR2
T2CON
PR2
Timer2 Module’s Register
—
0000 0000 0000 0000
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON
Timer2 Period Register
T2CKPS1 T2CKPS0 -000 0000 -000 0000
1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.
DS39541B-page 136
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 137 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
13.0
TIMER3 MODULE
Figure 13-1 is a simplified block diagram of the Timer3
module.
The Timer3 module timer/counter has the following
features:
• 16-bit timer/counter
(Two 8-bit registers: TMR3H and TMR3L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• RESET from CCP module trigger
Register 13-1 shows the Timer3 Control register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
Register 11-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 oscillator
enable bit (T1OSCEN), which can be a clock source for
Timer3.
Note:
REGISTER 13-1:
Timer3 is disabled on POR.
T3CON REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
bit 7
bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable
1 = Enables register Read/Write of Timer3 in one 16-bit operation
0 = Enables register Read/Write of Timer3 in two 8-bit operations
bit 6,3
T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the clock source for compare/capture CCP modules
01 = Timer3 is the clock source for compare/capture of CCP2,
Timer1 is the clock source for compare/capture of CCP1
00 = Timer1 is the clock source for compare/capture CCP modules
bit 5-4
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 2
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first
falling edge)
0 = Internal clock (FOSC/4)
bit 0
TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Advance Information
x = Bit is unknown
DS39541B-page 137
39541a.book Page 138 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
13.1
Timer3 Operation
When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC value is
ignored.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON register).
Timer3 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 13.0).
FIGURE 13-1:
TIMER3 BLOCK DIAGRAM
CCP Special Trigger
T3CCPx
0
TMR3IF
Overflow
Interrupt
Flag bit
TMR3H
CLR
TMR3L
1
TMR3ON
On/Off
T1OSC
T1OSO/
T13CKI
T3SYNC
(3)
1
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
T1OSI
Synchronized
Clock Input
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
SLEEP Input
TMR3CS
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
FIGURE 13-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus
8
TMR3H
8
8
Write TMR3L
Read TMR3L
TMR3IF Overflow
Interrupt Flag
bit
8
CCP Special Trigger
T3CCPx
0
TMR3
TMR3H
TMR3L
CLR
Synchronized
Clock Input
1
To Timer1 Clock Input
T1OSO/
T13CKI
T1OSI
TMR3ON
On/Off
T1OSC
T3SYNC
1
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
T3CKPS1:T3CKPS0
TMR3CS
SLEEP Input
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
DS39541B-page 138
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 139 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
13.2
Timer1 Oscillator
13.4
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN bit (T1CON Register). The oscillator is
a low power oscillator rated up to 200 kHz. Refer to
“Timer1 Module”, Section 11.0, for Timer1 oscillator
details.
13.3
Resetting Timer3 Using a CCP
Trigger Output
If the CCP module is configured in Compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer3.
Note:
The special event triggers from the CCP
module will not set interrupt flag bit
TMR3IF (PIR registers).
Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit TMR3IF (PIE
registers). This interrupt can be enabled/disabled by
setting/clearing TMR3 interrupt enable bit TMR3IE
(PIE registers).
TABLE 13-1:
Timer3 must be configured for either Timer, or Synchronized Counter mode, to take advantage of this feature. If
Timer3 is running in Asynchronous Counter mode, this
RESET operation may not work. In the event that a write
to Timer3 coincides with a special event trigger from
CCP1, the write will take precedence. In this mode of
operation, the CCPR1H:CCPR1L registers pair
becomes the period register for Timer3. Refer to
Section 14.0, “Capture/Compare/PWM (CCP) Modules”,
for CCP details.
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
RESETS
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
PIR2
—
—
—
—
BCLIF
LVDIF
TMR3IF
CCP2IF
---- 0000
-0-- 0000
PIE2
—
—
—
—
BCLIE
LVDIE
TMR3IE
CCP2IE
---- 0000
-0-- 0000
—
—
—
—
BCLIP
LVDIP
TMR3IP
CCP2IP
IPR2
---- 0000
-0-- 0000
TMR3L
Holding register for the Least Significant Byte of the 16-bit TMR3 register
xxxx xxxx
uuuu uuuu
TMR3H
Holding register for the Most Significant Byte of the 16-bit TMR3 register
xxxx xxxx
uuuu uuuu
T1CON
RD16
T3CON
RD16
Legend:
—
T1CKPS1 T1CKPS0 T1OSCEN
T3CCP2 T3CKPS1 T3CKPS0
T3CCP1
T1SYNC
TMR1CS TMR1ON 0-00 0000
u-uu uuuu
T3SYNC
TMR3CS TMR3ON 0000 0000
uuuu uuuu
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer3 module.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 139
39541a.book Page 140 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
NOTES:
DS39541B-page 140
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 141 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
14.0
CAPTURE/COMPARE/PWM
(CCP) MODULES
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register that can operate as a 16-bit capture
register, as a 16-bit compare register, or as a PWM
Duty Cycle register. Table 14-1 shows the timer
resources of the CCP module modes.
REGISTER 14-1:
CCP1CON
The operation of CCP1 is identical to that of CCP2, with
the exception of the special event trigger. Therefore,
operation of a CCP module in the following sections is
described, with respect to CCP1.
Table 14-2 shows the interaction of the CCP modules.
Register 14-1 shows the CCPx Control registers
(CCPxCON). For the CCP1 module, the register is
called CCP1CON and for the CCP2 module, the register is called CCP2CON.
CCP1CON REGISTER
CCP2CON REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
bit 7
CCP2CON
bit 0
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5-4
DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode,
Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set)
1001 = Compare mode,
Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set)
1010 = Compare mode,
Generate software interrupt on compare match
(CCPIF bit is set, CCP pin is unaffected)
1011 = Compare mode,
Trigger special event (CCPIF bit is set, reset TMR1 or TMR3)
11xx = PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Advance Information
x = Bit is unknown
DS39541B-page 141
39541a.book Page 142 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
14.1
CCP1 Module
14.3
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
14.2
CCP2 Module
Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
TABLE 14-1:
CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the 16-bit
value of the TMR1 or TMR3 registers, when an event
occurs on pin RC2/CCP1. An event is defined as:
•
•
•
•
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON). When a capture is made, the interrupt request flag bit CCP1IF (PIR registers) is set. It
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old captured value will be lost.
14.3.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC bit.
Note:
14.3.2
If the RC2/CCP1 is configured as an output, a write to the port can cause a capture
condition.
TIMER1/TIMER3 MODE SELECTION
The timers used with the capture feature (either Timer1
and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer
used with each CCP module is selected in the T3CON
register.
TABLE 14-2:
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
TMR1 or TMR3 time-base. Time-base can be different for each CCP.
Capture
Compare
The compare could be configured for the special event trigger, which clears either TMR1
or TMR3, depending upon which time-base is used.
Compare
Compare
The compare(s) could be configured for the special event trigger, which clears TMR1 or
TMR3, depending upon which time-base is used.
PWM
PWM
PWM
Capture
None.
PWM
Compare
None.
DS39541B-page 142
The PWMs will have the same frequency and update rate (TMR2 interrupt).
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 143 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
14.3.3
SOFTWARE INTERRUPT
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 14-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE registers) clear to avoid false interrupts
and should clear the flag bit CCP1IF, following any
such change in operating mode.
14.3.4
CCP PRESCALER
EXAMPLE 14-1:
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
CLRF
MOVLW
MOVWF
FIGURE 14-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON, F ; Turn CCP module off
NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
CCP1CON
; Load CCP1CON with
; this value
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
RC2/CCP1 pin
T3CCP2
Prescaler
1, 4, 16
RXB0IF or
RXB1IF
CCP1CON
TMR3L
Set Flag bit CCP1IF
TMR3
Enable
CCPR1H
and
edge detect
T3CCP2
CCPR1L
TMR1
Enable
TMR1H
TMR1L
TMR3H
TMR3L
CCP1M3:CCP1M0
Q’s
Set Flag bit CCP2IF
T3CCP1
T3CCP2
TMR3
Enable
Prescaler
1, 4, 16
RC1/CCP2 pin
CCPR2H
CCPR2L
TMR1
Enable
and
edge detect
T3CCP2
T3CCP1
TMR1H
TMR1L
CCP2M3:CCP2M0
Q’s
Note:
I/O pins have diode protection to VDD and VSS.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 143
39541a.book Page 144 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
14.4
Compare Mode
14.4.2
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against either the TMR1
register pair value, or the TMR3 register pair value.
When a match occurs, the RC2/CCP1 (RC1/CCP2) pin
can have one of the following actions:
•
•
•
•
TIMER1/TIMER3 MODE SELECTION
14.4.3
Driven high
Driven low
Toggle output (high to low or low to high)
Remains unchanged
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled).
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit CCP1IF (CCP2IF) is set.
14.4.4
14.4.1
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
The special trigger output of CCPx resets either the
TMR1, or TMR3 register pair. Additionally, the CCP2
Special Event Trigger will start an A/D conversion, if the
A/D module is enabled.
Note:
FIGURE 14-2:
SPECIAL EVENT TRIGGER
The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will:
Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit)
Set bit GO/DONE, which starts an A/D conversion (CCP2 only)
Special Event Trigger
Set Flag bit CCP1IF
CCPR1H CCPR1L
Q
RC2/CCP1
pin
TRISC
Output Enable
S
R
Output
Logic
Comparator
Match
CCP1M3:CCP1M0
Mode Select
0
T3CCP2
TMR1H
1
TMR1L
TMR3H
TMR3L
Special Event Trigger
Set Flag bit CCP2IF
Q
RC1/CCP2
pin
TRISC
Output Enable
Note:
S
R
Output
Logic
T3CCP1
T3CCP2
Match
0
1
Comparator
CCPR2H CCPR2L
CCP2M3:CCP2M0
Mode Select
I/O pins have diode protection to VDD and VSS.
DS39541B-page 144
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 145 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 14-3:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000 -000 0000
PIE1
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000 -000 0000
IPR1
—
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
-000 0000 -000 0000
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
T1CON
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN
CCPR1L
Capture/Compare/PWM Register1 (LSB)
CCPR1H
Capture/Compare/PWM Register1 (MSB)
CCP1CON
—
—
DC1B1
DC1B0
CCPR2L
Capture/Compare/PWM Register2 (LSB)
CCPR2H
Capture/Compare/PWM Register2 (MSB)
T1SYNC
TMR1CS TMR1ON 0-00 0000 u-uu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2CON
—
—
DC2B1
DC2B0
PIR2
—
—
—
—
BCLIF
LVDIF
TMR3IF
CCP2IF
---- 0000 ---- 0000
PIE2
—
—
—
—
BCLIE
LVDIE
TMR3IE
CCP2IE
---- 0000 ---- 0000
IPR2
—
—
—
—
BCLIP
LVDIP
TMR3IP
CCP2IP
---- 0000 ---- 0000
CCP2M3
CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
TMR3L
Holding register for the Least Significant Byte of the 16-bit TMR3 register
xxxx xxxx uuuu uuuu
TMR3H
Holding register for the Most Significant Byte of the 16-bit TMR3 register
xxxx xxxx uuuu uuuu
T3CON
Legend:
RD16
T3CCP2 T3CKPS1 T3CKPS0
T3CCP1
T3SYNC
TMR3CS TMR3ON 0000 0000 uuuu uuuu
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 145
39541a.book Page 146 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
14.5
PWM Mode
14.5.1
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Figure 14-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to setup the CCP
module for PWM operation, see Section 14.5.3.
FIGURE 14-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty Cycle Registers
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated by the
formula:
PWM period =
[(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
where PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
CCP1CON
The Timer2 postscaler (see Section 12.1)
is not used in the determination of the
PWM frequency. The postscaler could be
used to have a servo update rate at a different frequency than the PWM output.
CCPR1L (Master)
14.5.2
CCPR1H (Slave)
R
Comparator
Q
RC2/CCP1
(Note 1)
TMR2
S
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle =
TRISC
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock, or
2 bits of the prescaler, to create 10-bit time-base.
A PWM output (Figure 14-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 14-4:
PWM OUTPUT
Period
PWM DUTY CYCLE
(CCPR1L:CCP1CON) •
TOSC • (TMR2 prescale value)
CCPR1L and CCP1CON can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
F OSC
log ---------------
F PWM
PWM Resolution (max) = -----------------------------bits
log 2
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
Note:
TMR2 = PR2
DS39541B-page 146
Advance Information
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
2001-2013 Microchip Technology Inc.
39541a.book Page 147 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
14.5.3
SETUP FOR PWM OPERATION
3.
The following steps should be taken when configuring
the CCP module for PWM operation:
4.
1.
5.
2.
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON bits.
TABLE 14-4:
Make the CCP1 pin an output by clearing the
TRISC bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 25 MHz
PWM Frequency
1.53 kHz
6.10 kHz
24.41 kHz
97.66kHz
16
4
1
1
1
1
0FFh
FFh
FFh
3Fh
1Fh
17h
10
10
10
8
7
6.6
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 14-5:
195.31 kHz 260.42 kHz
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000 -000 0000
PIE1
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000 -000 0000
IPR1
—
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
-000 0000 -000 0000
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
TMR2
Timer2 Module’s Register
0000 0000 0000 0000
Timer2 Module’s Period Register
1111 1111 1111 1111
PR2
T2CON
—
CCPR1L
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Capture/Compare/PWM Register1 (LSB)
xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register1 (MSB)
CCP1CON
CCPR2L
—
—
DC1B1
DC1B0
xxxx xxxx uuuu uuuu
CCP1M3
CCP1M2 CCP1M1
CCP1M0
Capture/Compare/PWM Register2 (LSB)
xxxx xxxx uuuu uuuu
CCPR2H Capture/Compare/PWM Register2 (MSB)
xxxx xxxx uuuu uuuu
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3
PIR2
—
—
—
—
BCLIF
LVDIF
PIE2
—
—
—
—
BCLIE
IPR2
—
—
—
—
BCLIP
Legend:
--00 0000 --00 0000
CCP2M2 CCP2M1
CCP2M0
--00 0000 --00 0000
TMR3IF
CCP2IF
---- 0000 ---- 0000
LVDIE
TMR3IE
CCP2IE
---- 0000 ---- 0000
LVDIP
TMR3IP
CCP2IP
---- 0000 ---- 0000
x = unknown, u = unchanged, — = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 147
39541a.book Page 148 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
NOTES:
DS39541B-page 148
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 149 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
15.1
Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral InterfaceTM (SPI)
• Inter-Integrated CircuitTM (I2C)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 149
39541a.book Page 150 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.2
Control Registers
The MSSP module has three associated registers.
These include a status register and two control registers.
REGISTER 15-1:
Register 15-1 shows the MSSP Status Register
(SSPSTAT), Register 15-2 shows the MSSP Control
Register 1 (SSPCON1), and Register 15-3 shows the
MSSP Control Register 2 (SSPCON2).
SSPSTAT REGISTER
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select
CKP = 0:
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1:
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: STOP bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a STOP bit has been detected last (this bit is '0' on RESET)
0 = STOP bit was not detected last
bit 3
S: START bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a START bit has been detected last (this bit is '0' on RESET)
0 = START bit was not detected last
bit 2
R/W: Read/Write bit Information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from
the address match to the next START bit, STOP bit, or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress.
OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode.
bit 1
UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
DS39541B-page 150
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Advance Information
x = Bit is unknown
2001-2013 Microchip Technology Inc.
39541a.book Page 151 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 15-2:
SSPCON1 REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
Master mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started
0 = No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of
overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the
user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master
mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing
to the SSPBUF register. (Must be cleared in software.)
0 = No overflow
2
In I C mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a
"don’t care" in Transmit mode. (Must be cleared in software.)
0 = No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output.
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2 C Slave mode:
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2 C Master mode:
Unused in this mode
bit 3 - 0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1) )
1001 = Reserved
1010 = Reserved
1011 = I2C firmware controlled Master mode (Slave idle)
1100 = Reserved
1101 = Reserved
1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled
1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Advance Information
x = Bit is unknown
DS39541B-page 151
39541a.book Page 152 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 15-3:
SSPCON2 REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
bit 7
GCEN: General Call Enable bit (In I2C Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (In I2C Master mode only)
In Master Transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (In I2C Master mode only)
In Master Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3
RCEN: Receive Enable bit (In I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2
PEN: STOP Condition Enable bit (In I2C Master mode only)
SCK release control
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition idle
bit 1
RSEN: Repeated START Condition Enabled bit (In I2C Master mode only)
1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared
by hardware.
0 = Repeated START condition idle
bit 0
SEN: START Condition Enabled bit (In I2C Master mode only)
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition idle
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
DS39541B-page 152
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Advance Information
x = Bit is unknown
2001-2013 Microchip Technology Inc.
39541a.book Page 153 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.3
SPI Mode
FIGURE 15-1:
The SPI mode allows 8 bits of data to be synchronously
transmitted and received, simultaneously. All four
modes of SPI are supported. To accomplish communication, typically three pins are used:
MSSP BLOCK DIAGRAM
(SPI MODE)
Internal
Data Bus
Read
• Serial Data Out (SDO) - RC5/SDO
• Serial Data In (SDI) - RC4/SDI/SDA
• Serial Clock (SCK) - RC3/SCK/SCL/LVOIN
Write
SSPBUF reg
Additionally, a fourth pin may be used when in any
Slave mode of operation:
SSPSR reg
• Slave Select (SS) - RA5/SS/AN4
SDI
15.3.1
SDO
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits SSPCON1 and SSPSTAT.
These control bits allow the following to be specified:
•
•
•
•
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock polarity (Idle state of SCK)
Data input sample phase (middle or end of data
output time)
• Clock edge (output data on rising/falling edge of
SCK)
• Clock rate (Master mode only)
• Slave Select mode (Slave mode only)
SS Control
Enable
SS
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE 4
TMR2 Output
2
2
Edge
Select
Prescaler TOSC
4, 16, 64
(
SCK
Figure 15-1 shows the block diagram of the MSSP
module, when in SPI mode.
)
Data to TX/RX in SSPSR
TRIS bit
Note:
2001-2013 Microchip Technology Inc.
Shift
Clock
bit0
I/O pins have diode protection to VDD and VSS.
Advance Information
DS39541B-page 153
39541a.book Page 154 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then the buffer full detect bit, BF (SSPSTAT
register), and the interrupt flag bit, SSPIF (PIR registers), are set. This double buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit, WCOL
(SSPCON1 register), will be set. User software must
clear the WCOL bit so that it can be determined if the
following write(s) to the SSPBUF register completed
successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
buffer full (BF) bit (SSPSTAT register) indicates when
SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or
written. If the interrupt method is not going to be used,
then software polling can be done to ensure that a write
collision does not occur. Example 15-1 shows the
loading of the SSPBUF (SSPSR) for data transmission.
EXAMPLE 15-1:
The SSPSR is not directly readable or writable, and
can only be accessed by addressing the SSPBUF register. Additionally, the MSSP status register (SSPSTAT
register) indicates the various status conditions.
15.3.2
ENABLING SPI I/O
To enable the serial port, SSP enable bit, SSPEN
(SSPCON1 register), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers, and then set the SSPEN bit. This
configures the SDI, SDO, SCK, and SS pins as serial
port pins. For the pins to behave as the serial port function, corresponding pins must have their data direction
bits (in the TRIS register) appropriately programmed.
That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC bit cleared
• SCK (Master mode) must have TRISC bit
cleared
• SCK (Slave mode) must have TRISC bit set
• RA5 must be configured as digital I/O using
ADCON1 register
• SS must have TRISA bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF
BRA LOOP
MOVF SSPBUF, W
;Has data been received (transmit complete)?
;No
;WREG reg = contents of SSPBUF
MOVWF RXDATA
;Save in user RAM, if data is meaningful
MOVF TXDATA, W
MOVWF SSPBUF
;W reg = contents of TXDATA
;New data to xmit
DS39541B-page 154
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 155 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.3.3
MASTER MODE
The clock polarity is selected by appropriately programming the CKP bit (SSPCON1 register). This, then,
would give waveforms for SPI communication as
shown in Figure 15-2, Figure 15-4, and Figure 15-5,
where the MSb is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave is to broadcast data by the software
protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor” mode.
FIGURE 15-2:
•
•
•
•
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
Timer2 output/2
This allows a maximum data rate (at 25 MHz) of 6.25
Mbps.
Figure 15-2 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDO
(CKE = 1)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit0
bit7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 155
39541a.book Page 156 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.3.4
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times, as
specified in the electrical specifications.
the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating
output. External pull-up/pull-down resistors may be
desirable, depending on the application.
Note 1: When the SPI is in Slave mode with SS
pin control enabled, (SSPCON =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
15.3.5
When the SPI module resets, the bit counter is forced
to 0. This can be done by either forcing the SS pin to a
high level, or clearing the SSPEN bit.
SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control
enabled (SSPCON1 = 04h). The pin must not
be driven low for the SS pin to function as an input.
The data latch must be high. When the SS pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
FIGURE 15-3:
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function),
since it cannot create a bus conflict.
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit7
bit6
bit7
bit0
bit0
bit7
bit7
Input
Sample
(SMP = 0)
SSPIF
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
DS39541B-page 156
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 157 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 15-4:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
FIGURE 15-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Required
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 157
39541a.book Page 158 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.3.6
SLEEP OPERATION
15.3.8
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to transmit/
receive data.
Table 15-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE
control bits.
TABLE 15-1:
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode, and data to be
shifted into the SPI transmit/receive shift register.
When all eight bits have been received, the MSSP
interrupt flag bit will be set and, if enabled, will wake the
device from SLEEP.
15.3.7
SPI BUS MODES
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
EFFECTS OF A RESET
There is also a SMP bit that controls when the data will
be sampled.
A RESET disables the MSSP module and terminates
the current transfer.
TABLE 15-2:
BUS MODE COMPATIBILITY
REGISTERS ASSOCIATED WITH SPI OPERATION
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF TMR1IF -000 0000 -000 0000
PIE1
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE TMR1IE -000 0000 -000 0000
—
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP TMR1IP -000 0000 -000 0000
IPR1
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON
WCOL
TRISA
—
SSPSTAT
SMP
SSPOV SSPEN
CKP
SSPM3
SSPM2
xxxx xxxx uuuu uuuu
SSPM1
SSPM0 0000 0000 0000 0000
PORTA Data Direction Register
CKE
D/A
0000 000x 0000 000u
P
--11 1111 --11 1111
S
R/W
UA
BF
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'.
Shaded cells are not used by the MSSP in SPI mode.
DS39541B-page 158
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 159 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.4
MSSP I2 C Operation
2
The MSSP module in I C mode, fully implements all
master and slave functions (including general call support) and provides interrupts on START and STOP bits
in hardware to determine a free bus (Multi-Master
mode). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC bits.
The MSSP module functions are enabled by setting
MSSP Enable bit SSPEN (SSPCON1 register).
The MSSP module has these six registers for I2C operation:
•
•
•
•
•
MSSP Control Register1 (SSPCON1)
MSSP Control Register2 (SSPCON2)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
MSSP Shift Register (SSPSR) - Not directly
accessible
• MSSP Address Register (SSPADD)
FIGURE 15-6:
MSSP BLOCK DIAGRAM
(I2C MODE)
Internal
Data Bus
Read
15.4.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
When an address is matched, or the data transfer after
an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse and
load the SSPBUF register with the received value currently in the SSPSR register.
If either or both of the following conditions are true, the
MSSP module will not give this ACK pulse:
The buffer full bit BF (SSPCON1 register) was
set before the transfer was received.
The overflow bit SSPOV (SSPCON1 register)
was set before the transfer was received.
b)
SSPSR reg
In this event, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR registers) is set.
The BF bit is cleared by reading the SSPBUF register,
while bit SSPOV is cleared through software.
LSb
MSb
Match Detect
Addr Match
SSPADD reg
START and
STOP bit Detect
Note:
Selection of any I 2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting
the appropriate TRISC bits.
SSPBUF reg
Shift
Clock
RC4/
SDI/
SDA
I2C Master mode, clock = OSC/(4*(SSPADD +1))
I 2C Slave mode (7-bit address)
I 2C Slave mode (10-bit address)
I 2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled
• I 2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled
• I 2C firmware controlled master operation, slave is
idle
•
•
•
•
a)
Write
RC3/SCK/SCL
The SSPCON1 register allows control of the I 2C operation. The SSPM3:SSPM0 mode selection bits
(SSPCON1 register) allow one of the following I 2C
modes to be selected:
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, is shown in timing parameter #100 and
parameter #101.
Set, RESET
S, P bits
(SSPSTAT reg)
I/O pins have diode protection to VDD and VSS.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 159
39541a.book Page 160 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.4.1.1
Addressing
15.4.1.2
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START condition, the eight bits are shifted into the SSPSR register.
All incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
The SSPSR register value is loaded into the
SSPBUF register.
The buffer full bit BF is set.
An ACK pulse is generated.
MSSP interrupt flag bit SSPIF (PIR registers) is
set on the falling edge of the ninth SCL pulse
(interrupt is generated, if enabled).
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSb) of the first address byte, specify if this is a 10-bit
address. The R/W bit (SSPSTAT register) must specify
a write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal ‘1111 0 A9 A8 0’, where A9 and A8 are the
two MSb’s of the address.
The sequence of events for 10-bit addressing is as follows, with steps 7- 9 for slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Receive first (high) byte of address (the SSPIF,
BF and UA bits (SSPSTAT register) are set).
Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive repeated START condition.
Receive first (high) byte of address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
DS39541B-page 160
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT register) is
set or bit SSPOV (SSPCON1 register) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR registers) must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
15.4.1.3
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON1 register). The master must
monitor the SCL pin prior to asserting another clock
pulse. The slave devices may be holding off the master
by stretching the clock. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time
(Figure 15-8).
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line is high (not ACK), then the
data transfer is complete. When the ACK is latched by
the slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of
the START bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which
also loads the SSPSR register. Pin RC3/SCK/SCL
should be enabled by setting bit CKP.
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 161 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
I 2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 15-7:
Receiving Address R/W = 0
Receiving Data
Receiving Data
Not ACK
ACK
ACK
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
1
S
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SSPIF
P
Bus Master
Terminates
Transfer
BF
Cleared in software
SSPBUF register is read
SSPOV
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
I 2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
FIGURE 15-8:
R/W = 0
Receiving Address
SDA
SCL
A7
S
A6
1
2
Data in
Sampled
R/W = 1
A5
A4
A3
A2
A1
3
4
5
6
7
ACK
8
9
Not ACK
Transmitting Data
D7
1
SCL held low
while CPU
responds to SSPIF
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
P
SSPIF
BF
Cleared in software
SSPBUF is written in software
From SSP Interrupt
Service Routine
CKP
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 161
39541a.book Page 162 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.4.2
GENERAL CALL ADDRESS
SUPPORT
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF bit is set (eighth bit),
and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually determines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT register). If the general call address
is sampled when the GCEN bit is set and while the
slave is configured in 10-bit address mode, then the
second half of the address is not necessary. The UA bit
will not be set, and the slave will begin receiving data
after the Acknowledge (Figure 15-9).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0.
The general call address is recognized (enabled) when
the General Call Enable (GCEN) bit is set (SSPCON2
register). Following a START bit detect, eight bits are
shifted into the SSPSR and the address is compared
against the SSPADD. It is also compared to the general
call address and fixed in hardware.
FIGURE 15-9:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS)
Address is compared to General Call Address
after ACK, set interrupt
R/W = 0
ACK D7
General Call Address
SDA
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
SCL
S
1
2
3
4
5
6
7
8
9
1
9
SSPIF
BF
Cleared in software
SSPBUF is read
SSPOV
'0'
GCEN
'1'
DS39541B-page 162
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 163 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.4.3
MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I 2C bus may be taken when the
P bit is set, or the bus is idle, with both the S and P bits
clear.
1.
2.
Assert a START condition on SDA and SCL.
Assert a Repeated START condition on SDA
and SCL.
Write to the SSPBUF register initiating transmission of data/address.
Generate a STOP condition on SDA and SCL.
Configure the I2C port to receive data.
Generate an Acknowledge condition at the end
of a received byte of data.
3.
4.
5.
6.
In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
•
•
•
•
•
The MSSP module, when configured in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
imitate transmission, before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Note:
START condition
STOP condition
Data transfer byte transmitted/received
Acknowledge Transmit
Repeated START condition
I2C MASTER MODE SUPPORT
15.4.4
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. Once Master mode is enabled, the user
has the following six options:
MSSP BLOCK DIAGRAM (I2C MASTER MODE)
SSPM3:SSPM0
SSPADD
Internal
Data Bus
Read
Write
SSPBUF
Baud
Rate
Generator
Shift
Clock
SDA
SDA In
SSPSR
Receive Enable
START bit, STOP bit,
Acknowledge
Generate
SCL In
Bus Collision
Note:
LSb
START bit Detect
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
Clock Cntl
SCL
MSb
Clock arbitrate/WCOL Detect
(hold off clock source)
FIGURE 15-10:
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
I/O pins have diode protection to VDD and VSS.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 163
39541a.book Page 164 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.4.4.1
I2C Master Mode Operation
A typical transmit sequence would go as follows:
The master device generates all of the serial clock
pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a Repeated
START condition. Since the Repeated START condition is also the beginning of the next serial transfer, the
I2C bus will not be released.
a)
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic '0'. Serial data is
transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. START and
STOP conditions are output to indicate the beginning
and the end of a serial transfer.
c)
In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic '1'. Thus, the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received eight bits at a time. After
each byte is received, an Acknowledge bit is transmitted. START and STOP conditions indicate the beginning and end of transmission.
The baud rate generator used for the SPI mode operation is now used to set the SCL clock frequency for
either 100 kHz, 400 kHz, or 1 MHz I2C operation. The
baud rate generator reload value is contained in the
lower 7 bits of the SSPADD register. The baud rate
generator will automatically begin counting on a write to
the SSPBUF. Once the given operation is complete
(i.e., transmission of the last data bit is followed by
ACK), the internal clock will automatically stop counting
and the SCL pin will remain in its last state.
FIGURE 15-11:
b)
d)
e)
f)
g)
h)
i)
j)
k)
l)
15.4.5
BAUD RATE GENERATOR
In I2C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 15-11). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2
and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically. If clock arbitration is taking
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 15-12).
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPM3:SSPM0
Reload
SCL
Control
CLKOUT
DS39541B-page 164
The user generates a START condition by setting the START enable (SEN) bit (SSPCON2
register).
SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
The user loads the SSPBUF with the address to
transmit.
Address is shifted out the SDA pin until all eight
bits are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit (SSPCON2 register).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The user loads the SSPBUF with eight bits of
data.
Data is shifted out the SDA pin until all eight bits
are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit (SSPCON2 register).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The user generates a STOP condition by setting
the STOP enable bit PEN (SSPCON2 register).
Interrupt is generated once the STOP condition
is complete.
SSPADD
Reload
BRG Down Counter
Advance Information
FOSC/4
2001-2013 Microchip Technology Inc.
39541a.book Page 165 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 15-12:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL allowed to transition high
SCL de-asserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
reload
15.4.6
I2C MASTER MODE START
CONDITION TIMING
Note:
To initiate a START condition, the user sets the START
Condition Enable (SEN) bit (SSPCON2 register). If the
SDA and SCL pins are sampled high, the baud rate
generator is re-loaded with the contents of
SSPADD and starts its count. If SCL and SDA are
both sampled high when the baud rate generator times
out (TBRG), the SDA pin is driven low. The action of the
SDA being driven low while SCL is high, is the START
condition, and causes the S bit (SSPSTAT register) to
be set. Following this, the baud rate generator is
reloaded with the contents of SSPADD and
resumes its count. When the baud rate generator times
out (TBRG), the SEN bit (SSPCON2 register) will be
automatically cleared by hardware, the baud rate generator is suspended leaving the SDA line held low and
the START condition is complete.
FIGURE 15-13:
If at the beginning of the START condition,
the SDA and SCL pins are already sampled low, or if during the START condition
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag
BCLIF is set, the START condition is
aborted, and the I2C module is reset into its
IDLE state.
15.4.6.1
WCOL Status Flag
If the user writes the SSPBUF when a START
sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
FIRST START BIT TIMING
Set S bit (SSPSTAT)
Write to SEN bit occurs here
SDA = 1,
SCL = 1
TBRG
At completion of START bit,
Hardware clears SEN bit
and sets SSPIF bit
TBRG
Write to SSPBUF occurs here
1st bit
2nd bit
SDA
TBRG
SCL
TBRG
S
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 165
39541a.book Page 166 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.4.7
I2C MASTER MODE REPEATED
START CONDITION TIMING
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional
eight bits of address (10-bit mode) or eight bits of data
(7-bit mode).
A Repeated START condition occurs when the RSEN
bit (SSPCON2 register) is programmed high and the
I2C logic module is in the IDLE state. When the RSEN
bit is set, the SCL pin is asserted low. When the SCL
pin is sampled low, the baud rate generator is loaded
with the contents of SSPADD and begins counting. The SDA pin is released (brought high) for one
baud rate generator count (TBRG). When the baud rate
generator times out, if SDA is sampled high, the SCL pin
will be de-asserted (brought high). When SCL is sampled high, the baud rate generator is re-loaded with the
contents of SSPADD and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin (SDA
= 0) for one TBRG, while SCL is high. Following this, the
RSEN bit (SSPCON2 register) will be automatically
cleared and the baud rate generator will not be reloaded,
leaving the SDA pin held low. As soon as a START condition is detected on the SDA and SCL pins, the S bit
(SSPSTAT register) will be set. The SSPIF bit will not be
set until the baud rate generator has timed out.
15.4.7.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated
START sequence is in progress, the WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated
START condition occurs, if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
FIGURE 15-14:
REPEATED START CONDITION WAVEFORM
Set S (SSPSTAT)
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change)
SDA = 1,
SCL = 1
TBRG
TBRG
At completion of START bit,
hardware clear RSEN bit
and set SSPIF
TBRG
1st Bit
SDA
Write to SSPBUF occurs here
Falling edge of ninth clock
End of Xmit
TBRG
SCL
TBRG
Sr = Repeated START
DS39541B-page 166
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 167 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.4.8
I2C MASTER MODE
TRANSMISSION
15.4.8.2
Transmission of a data byte, a 7-bit address, or the
other half of a 10-bit address, is accomplished by simply writing a value to the SSPBUF register. This action
will set the Buffer Full bit, BF, and allow the baud rate
generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto
the SDA pin after the falling edge of SCL is asserted
(see data hold time specification parameter 106). SCL
is held low for one baud rate generator rollover count
(TBRG). Data should be valid before SCL is released
high (see data setup time specification parameter 107).
When the SCL pin is released high, it is held that way
for TBRG. The data on the SDA pin must remain stable
for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the
falling edge of the eighth clock), the BF bit is cleared
and the master releases SDA, allowing the slave
device being addressed to respond with an ACK bit
during the ninth bit time, if an address match occurs, or
if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth
clock. If the master receives an Acknowledge, the
Acknowledge Status bit, ACKSTAT, is cleared; if not,
the bit is set. After the ninth clock, the SSPIF bit is set
and the master clock (baud rate generator) is
suspended until the next data byte is loaded into the
SSPBUF, leaving SCL low and SDA unchanged
(Figure 15-15).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL, until all seven
address bits and the R/W bit, are completed. On the
falling edge of the eighth clock, the master will deassert the SDA pin, allowing the slave to respond with
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2
register). Following the falling edge of the ninth clock
transmission of the address, the SSPIF is set, the BF
bit is cleared and the baud rate generator is turned off,
until another write to the SSPBUF takes place, holding
SCL low and allowing SDA to float.
15.4.8.1
BF Status Flag
In Transmit mode, the BF bit (SSPSTAT register) is set
when the CPU writes to SSPBUF, and is cleared when
all eight bits are shifted out.
WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
15.4.8.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2
register) is cleared when the slave has sent an
Acknowledge (ACK = 0), and is set when the slave
does not Acknowledge (ACK = 1). A slave sends an
Acknowledge when it has recognized its address
(including a general call), or when the slave has
properly received its data.
15.4.9
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2 register).
Note:
The MSSP module must be in an IDLE
state before the RCEN bit is set, or the
RCEN bit will be disregarded.
The baud rate generator begins counting and on each
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the RCEN bit is
automatically cleared, the contents of the SSPSR are
loaded into the SSPBUF, the BF bit is set, the SSPIF
flag bit is set and the baud rate generator is suspended
from counting, holding SCL low. The MSSP is now in
IDLE state, awaiting the next command. When the
buffer is read by the CPU, the BF bit is automatically
cleared. The user can then send an Acknowledge bit at
the end of reception, by setting the Acknowledge
Sequence Enable bit ACKEN (SSPCON2 register).
15.4.9.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
15.4.9.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF bit is
already set from a previous reception.
15.4.9.3
WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 167
DS39541B-page 168
Advance Information
R/W
PEN
SEN
BF
SSPIF
SCL
SDA
S
A6
A5
A4
A3
A2
A1
3
4
5
Cleared in software
2
6
7
8
9
D7
1
SCL held low
while CPU
responds to SSPIF
After START condition, SEN cleared by hardware.
SSPBUF written
1
ACK = 0
R/W = 0
SSPBUF written with 7-bit address and R/W
start transmit
A7
Transmit Address to Slave
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
SSPBUF is written in software
Cleared in software service routine
From SSP interrupt
2
D6
Transmitting Data or Second Half
of 10-bit Address
From Slave, clear ACKSTAT bit SSPCON2
P
Cleared in software
9
ACK
ACKSTAT in
SSPCON2 = 1
FIGURE 15-15:
SEN = 0
Write SSPCON2 SEN = 1
START condition begins
39541a.book Page 168 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
2001-2013 Microchip Technology Inc.
2001-2013 Microchip Technology Inc.
S
Advance Information
ACKEN
SSPOV
BF
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
SCL
SDA
1
A7
2
4
5
Cleared in software
3
6
A6 A5 A4 A3 A2
Transmit Address to Slave
7
A1
8
9
R/W = 1
ACK
ACK from Slave
2
3
5
6
7
8
D0
9
ACK
2
3
4
5
6
7
Cleared in software
Set SSPIF interrupt
at end of Acknowledge
sequence
Data shifted in on falling edge of CLK
1
D7 D6 D5 D4 D3 D2 D1
Cleared in
software
Set SSPIF at end
of receive
9
ACK is not sent
ACK
P
Set SSPIF interrupt
at end of Acknowledge sequence
Bus Master
terminates
transfer
Set P bit
(SSPSTAT)
and SSPIF
PEN bit = 1
written here
SSPOV is set because
SSPBUF is still full
8
D0
RCEN cleared
automatically
Set ACKEN, start Acknowledge sequence
SDA = ACKDT = 1
Receiving Data from Slave
RCEN = 1 start
next receive
ACK from Master
SDA = ACKDT = 0
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared in software
Set SSPIF interrupt
at end of receive
4
Cleared in software
1
D7 D6 D5 D4 D3 D2 D1
Receiving Data from Slave
RCEN cleared
automatically
Master configured as a Receiver
by programming SSPCON2, (RCEN = 1)
FIGURE 15-16:
SEN = 0
Write to SSPBUF occurs here
Start XMIT
Write to SSPCON2 (SEN = 1)
Begin START condition
Write to SSPCON2
to start Acknowledge sequence
SDA = ACKDT (SSPCON2) = 0
39541a.book Page 169 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
I 2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
DS39541B-page 169
39541a.book Page 170 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.4.10
ACKNOWLEDGE SEQUENCE
TIMING
15.4.11
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence enable bit, ACKEN (SSPCON2
register). When this bit is set, the SCL pin is pulled low
and the contents of the Acknowledge Data bit (ACKDT)
is presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate generator then counts for one rollover period (TBRG) and the
SCL pin is de-asserted (pulled high). When the SCL pin
is sampled high (clock arbitration), the baud rate generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the
baud rate generator is turned off and the MSSP module
then goes into IDLE mode (Figure 15-17).
15.4.11.1
WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then the WCOL bit is set and the contents
of the buffer are unchanged (the write doesn’t occur).
15.4.10.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur).
FIGURE 15-17:
STOP CONDITION TIMING
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2 register). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sampled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one TBRG
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT register) is set.
A TBRG later, the PEN bit is cleared and the SSPIF bit
is set (Figure 15-18).
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
TBRG
TBRG
SDA
ACK
D0
SCL
8
9
SSPIF
Cleared in
software
Set SSPIF at the end
of receive
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one baud rate generator period.
FIGURE 15-18:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG , followed by SDA = 1 for TBRG
after SDA sampled high, P bit (SSPSTAT) is set
Write to SSPCON2
Set PEN
PEN bit (SSPCON2) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to set up STOP condition
Note:
TBRG = one baud rate generator period.
DS39541B-page 170
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 171 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.4.12
CLOCK ARBITRATION
15.4.13
Clock arbitration occurs when the master, during any
receive, transmit or Repeated START/STOP condition,
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 15-19).
FIGURE 15-19:
SLEEP OPERATION
While in SLEEP mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the MSSP interrupt is enabled).
15.4.14
EFFECT OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1, load BRG with
SSPADD and start count
to measure high time interval
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SCL = 1 BRG starts counting
clock high interval.
SCL
SCL line sampled once every machine cycle (TOSC² 4).
Hold off BRG until SCL is sampled high.
SDA
TBRG
2001-2013 Microchip Technology Inc.
TBRG
Advance Information
TBRG
DS39541B-page 171
39541a.book Page 172 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.4.15
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET, or
when the MSSP module is disabled. Control of the I 2C
bus may be taken when the P bit (SSPSTAT register) is
set, or the bus is idle, with both the S and P bits clear.
When the bus is busy, enabling the SSP interrupt will
generate the interrupt when the STOP condition
occurs.
In Multi-Master operation, the SDA line must be monitored for arbitration, to see if the signal level is the
expected output level. This check is performed in hardware, with the result placed in the BCLIF bit.
Arbitration can be lost in the following states:
•
•
•
•
•
Address transfer
Data transfer
A START condition
A Repeated START condition
An Acknowledge condition
15.4.16
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF bit is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision Interrupt Service Routine, and if the
I2C bus is free, the user can resume communication by
asserting a START condition.
If a START, Repeated START, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine, and if
the I2C bus is free, the user can resume communication
by asserting a START condition.
The master will continue to monitor the SDA and SCL
pins. If a STOP condition occurs, the SSPIF bit will be
set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the transmitter left off when the bus collision occurred.
MULTI -MASTER
COMMUNICATION, BUS
COLLISION, AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA, by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
FIGURE 15-20:
SDA is a '1' and the data sampled on the SDA pin = '0',
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag (BCLIF) and reset the
I2C port to its IDLE state. (Figure 15-20).
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0
SDA line pulled low
by another source
SDA released
by Master
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
Bus collision has occurred.
SDA
Set bus collision
interrupt (BCLIF)
SCL
BCLIF
DS39541B-page 172
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 173 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.4.16.1
Bus Collision During a START
Condition
During a START condition, a bus collision occurs if:
a)
SDA or SCL are sampled low at the beginning of
the START condition (Figure 15-21).
SCL is sampled low before SDA is asserted low
(Figure 15-22).
b)
During a START condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 15-23). If, however, a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0, and during this time, if the SCL pin is
sampled as '0', a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
Note:
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the START condition is aborted;
• the BCLIF flag is set, and
• the MSSP module is reset to its IDLE state
(Figure 15-21).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
FIGURE 15-21:
The reason that bus collision is not a factor
during a START condition, is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address following the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START or STOP conditions.
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
. Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
Set SEN, enable START
condition if SDA = 1, SCL=1
SEN cleared automatically because of bus collision.
SSP module reset into IDLE state.
SEN
BCLIF
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software.
S
SSPIF
SSPIF and BCLIF are
cleared in software.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 173
39541a.book Page 174 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 15-22:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable START
sequence if SDA = 1, SCL = 1
SCL
SCL = 0 before SDA = 0,
Bus collision occurs, set BCLIF
SEN
SCL = 0 before BRG time-out,
Bus collision occurs, set BCLIF
BCLIF
Interrupt cleared
in software
S
'0'
'0'
SSPIF
'0'
'0'
FIGURE 15-23:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Less than TBRG
SDA
SCL
Set SSPIF
TBRG
SDA pulled low by other Master.
Reset BRG and assert SDA.
S
SCL pulled low after BRG
Time-out
SEN
BCLIF
Set SEN, enable START
sequence if SDA = 1, SCL = 1
'0'
S
SSPIF
SDA = 0, SCL = 1
Set SSPIF
DS39541B-page 174
Advance Information
Interrupts cleared
in software
2001-2013 Microchip Technology Inc.
39541a.book Page 175 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.4.16.2
Bus Collision During a Repeated
START Condition
reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs
because no two masters can assert SDA at exactly the
same time.
During a Repeated START condition, a bus collision
occurs if:
a)
b)
If SCL goes from high to low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ’1’ during the Repeated START condition (Figure 15-25).
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ’1’.
If, at the end of the BRG time-out both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is
complete.
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD
and counts down to 0. The SCL pin is then de-asserted
and when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ’0’, see
Figure 15-24). If SDA is sampled high, the BRG is
FIGURE 15-24:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
'0'
S
'0'
SSPIF
FIGURE 15-25:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
BCLIF
SCL goes low before SDA.
Set BCLIF, release SDA and SCL.
Interrupt cleared
in software
RSEN
'0'
S
SSPIF
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 175
39541a.book Page 176 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
15.4.16.3
Bus Collision During a STOP
Condition
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data '0' (Figure 15-26). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master attempting to drive a data '0' (Figure 15-27).
Bus collision occurs during a STOP condition if:
a)
b)
After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is de-asserted, SCL is sampled low before SDA goes high.
FIGURE 15-26:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG
TBRG
SDA sampled
low after TBRG,
set BCLIF
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
'0'
SSPIF
'0'
FIGURE 15-27:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
Assert SDA
SCL
SCL goes low before SDA goes high,
set BCLIF
PEN
BCLIF
P
'0'
SSPIF
'0'
DS39541B-page 176
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 177 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
16.0
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
The SPEN (RCSTA register) and the TRISC bits
have to be set, and the TRISC bit must be
cleared, in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter.
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured
as a half duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc.
REGISTER 16-1:
Register 16-1 shows the Transmit Status and Control
Register (TXSTA) and Register 16-2 shows the
Receive Status and Control Register (RCSTA).
TXSTA REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SREN/CREN overrides TXEN in SYNC mode.
bit 4
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
Unimplemented: Read as '0'
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0
TX9D: 9th bit of Transmit Data. Can be Address/Data bit or a parity bit.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Advance Information
x = Bit is unknown
DS39541B-page 177
39541a.book Page 178 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 16-2:
RCSTA REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
SPEN: Serial Port Enable bit
1 = Serial port enabled (Configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - Slave:
Unused in this mode
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load of the receive buffer when RSR
is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: 9th bit of Received Data. Can be Address/Data bit or a parity bit.
Legend:
DS39541B-page 178
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Advance Information
x = Bit is unknown
2001-2013 Microchip Technology Inc.
39541a.book Page 179 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
16.1
USART Baud Rate Generator
(BRG)
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA register) also controls the
baud rate. In Synchronous mode, bit BRGH is ignored.
Table 16-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internal clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 16-1. From this, the error in
baud rate can be determined.
Example 16-1 shows the calculation of the baud rate
error for the following conditions:
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting the new baud rate.
16.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
EXAMPLE 16-1:
Desired Baud Rate
CALCULATING BAUD RATE ERROR
=
FOSC / (64 (X + 1))
X
X
X
=
=
=
( (FOSC / Desired Baud Rate) / 64 ) - 1
((16000000 / 9600) / 64) - 1
[25.042] = 25
Calculated Baud Rate
=
=
16000000 / (64 (25 + 1))
9615
Error
=
(Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
(9615 - 9600) / 9600
0.16%
Solving for X:
=
=
TABLE 16-1:
BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
Baud Rate = FOSC/(16(X+1))
NA
Legend: X = value in SPBRG (0 to 255)
TABLE 16-2:
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Name
Bit 7
TXSTA
CSRC
TX9
TXEN
RCSTA
SPEN
RX9
SREN
SPBRG
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SYNC
—
BRGH
CREN
ADDEN
FERR
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
TRMT
TX9D
0000 -010
0000 -010
OERR
RX9D
0000 000x
0000 000x
0000 0000
0000 0000
Bit 1
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 179
39541a.book Page 180 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 16-3:
BAUD RATES FOR SYNCHRONOUS MODE
FOSC =25 MHz
BAUD
RATE
(Kbps)
20 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
-
NA
-
-
-
-
NA
-
-
NA
-
-
NA
-
-
19.2
NA
-
-
NA
-
-
76.8
77.16
+0.47
80
76.92
+0.16
64
96
96.15
+0.16
64
96.15
+0.16
51
300
297.62
-0.79
20
294.12
-1.96
16
9
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
NA
-
1.2
NA
-
2.4
NA
9.6
500
480.77
-3.85
12
500
0
HIGH
6250
-
0
5000
-
0
LOW
24.41
-
255
19.53
-
255
FOSC = 16 MHz
BAUD
RATE
(Kbps)
10 MHz
7.15909 MHz
5.0688 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
-
NA
-
-
-
-
NA
-
-
+0.23
185
9.60
0
131
19.24
+0.23
92
19.20
0
65
77.82
+1.32
22
74.54
-2.94
16
94.20
-1.88
18
97.48
+1.54
12
7
298.35
-0.57
5
NA
-
-
4
NA
-
-
NA
-
-
-
0
1789.80
-
0
1267.20
-
0
-
255
6.99
-
255
4.95
-
255
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
NA
-
-
-
NA
NA
-
-
9.62
207
19.23
+0.16
129
51
75.76
-1.36
32
-0.79
41
96.15
+0.16
25
307.70
+2.56
12
312.50
+4.17
500
0
7
500
0
HIGH
4000
-
0
2500
LOW
15.63
-
255
9.77
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
NA
-
-
-
NA
-
-
19.23
+0.16
76.92
+0.16
96
95.24
300
500
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
NA
-
1.2
NA
-
2.4
NA
9.6
NA
19.2
76.8
FOSC = 4 MHz
BAUD
RATE
(Kbps)
3.579545 MHz
SPBRG
value
(decimal)
1 MHz
SPBRG
value
(decimal)
%
ERROR
32.768 kHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
0.30
+1.14
1.17
-2.48
SPBRG
value
(decimal)
KBAUD
%
ERROR
NA
-
NA
-
NA
-
-
1.20
+0.16
207
-
NA
-
-
2.40
+0.16
103
NA
-
-
103
9.62
+0.23
92
9.62
+0.16
25
NA
-
-
KBAUD
%
ERROR
0.3
NA
-
1.2
NA
-
-
2.4
NA
-
9.6
9.62
+0.16
KBAUD
6
19.2
19.23
+0.16
51
19.04
-0.83
46
19.23
+0.16
12
NA
-
76.8
76.92
+0.16
12
74.57
-2.90
11
NA
-
-
NA
-
-
96
1000
+4.17
9
99.43
+3.57
8
NA
-
-
NA
-
-
300
NA
-
-
298.30
-0.57
2
NA
-
-
NA
-
500
500
0
1
NA
-
-
NA
-
-
NA
-
-
HIGH
1000
-
0
894.89
-
0
250
-
0
8.20
-
0
LOW
3.91
-
255
3.50
-
255
0.98
-
255
0.03
-
255
DS39541B-page 180
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 181 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 16-4:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 25 MHz
BAUD
RATE
(Kbps)
20 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
NA
-
SPBRG
value
(decimal)
KBAUD
%
ERROR
0.3
NA
-
1.2
NA
-
-
NA
-
-
2.4
2.40
-0.15
162
2.40
+0.16
129
9.6
9.53
-0.76
40
9.47
-1.36
32
19.2
19.53
+1.73
19
19.53
+1.73
15
76.8
78.13
+1.73
4
78.13
+1.73
3
96
97.66
+1.73
3
NA
-
-
300
NA
-
-
312.50
+4.17
0
500
NA
-
-
NA
-
-
HIGH
390.63
-
0
312.50
-
0
LOW
1.53
-
255
1.22
-
255
FOSC = 16 MHz
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
10 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
7.15909 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
5.0688 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
NA
-
NA
-
NA
-
NA
-
1.2
1.20
+0.16
207
1.20
+0.16
129
1.20
+0.23
92
1.20
0
65
2.4
2.40
+0.16
103
2.40
+0.16
64
2.38
-0.83
46
2.40
0
32
9.6
9.62
+0.16
25
9.77
+1.73
15
9.32
-2.90
11
9.90
+3.13
7
19.2
19.23
+0.16
12
19.53
+1.73
7
18.64
-2.90
5
19.80
+3.13
3
76.8
NA
-
-
78.13
+1.73
1
NA
-
-
79.20
+3.13
0
96
NA
-
-
NA
-
-
NA
-
-
NA
-
-
300
NA
-
-
NA
-
-
NA
-
-
NA
-
-
500
NA
-
-
NA
-
-
NA
-
-
NA
-
-
HIGH
250
-
0
156.25
-
0
111.86
-
0
79.20
-
0
LOW
0.98
-
255
0.61
-
255
0.44
-
255
0.31
-
255
FOSC = 4 MHz
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
3.579545 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
1 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
32.768 kHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
0.30
-0.16
0.30
+0.23
0.30
+0.16
NA
-
1.2
1.20
+1.67
51
1.19
-0.83
46
1.20
+0.16
12
NA
-
-
2.4
2.40
+1.67
25
2.43
+1.32
22
NA
-
-
NA
-
-
9.6
NA
-
-
9.32
-2.90
5
NA
-
-
NA
-
-
19.2
NA
-
-
18.64
-2.90
2
NA
-
-
NA
-
-
76.8
NA
-
-
NA
-
-
NA
-
-
NA
-
-
96
NA
-
-
NA
-
-
NA
-
-
NA
-
-
300
NA
-
-
NA
-
-
NA
-
-
NA
-
-
500
NA
-
-
NA
-
-
NA
-
-
NA
-
-
HIGH
62.50
-
0
55.93
-
0
15.63
-
0
0.51
-
0
LOW
0.24
-
255
0.22
-
255
0.06
-
255
0.002
-
255
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 181
39541a.book Page 182 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 16-5:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 25 MHz
BAUD
RATE
(Kbps)
20 MHz
SPBRG
value
(decimal)
SPBRG
value
(decimal)
KBAUD
%
ERROR
NA
-
NA
-
-
NA
-
-
-0.15
162
9.62
+0.16
129
19.30
+0.47
80
19.23
+0.16
64
78.13
+1.73
19
78.13
+1.73
15
96
97.66
+1.73
15
96.15
+0.16
12
300
312.50
+4.17
4
312.50
+4.17
3
500
520.83
+4.17
2
NA
-
-
HIGH
1562.50
-
0
1250
-
0
LOW
6.10
-
255
4.88
-
255
KBAUD
%
ERROR
0.3
NA
-
1.2
NA
-
-
2.4
NA
-
9.6
9.59
19.2
76.8
FOSC = 16 MHz
BAUD
RATE
(Kbps)
-
10 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
0.3
NA
-
1.2
NA
-
-
2.4
NA
-
-
7.15909 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
NA
-
NA
-
-
NA
-
-
5.0688 MHz
SPBRG
value
(decimal)
SPBRG
value
(decimal)
KBAUD
%
ERROR
NA
-
NA
-
-
NA
-
-
2.41
+0.23
185
2.40
0
131
KBAUD
%
ERROR
NA
-
9.6
9.62
+0.16
103
9.62
+0.16
64
9.52
-0.83
46
9.60
0
32
19.2
19.23
+0.16
51
18.94
-1.36
32
19.45
+1.32
22
18.64
-2.94
16
76.8
76.92
+0.16
12
78.13
+1.73
7
74.57
-2.90
5
79.20
+3.13
3
96
100
+4.17
9
NA
-
-
NA
-
-
NA
-
-
300
NA
-
-
312.50
+4.17
1
NA
-
-
NA
-
-
500
500
0
1
NA
-
-
NA
-
-
NA
-
-
HIGH
1000
-
0
625
-
0
447.44
-
0
316.80
-
0
LOW
3.91
-
255
2.44
-
255
1.75
-
255
1.24
-
255
FOSC = 4 MHz
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
3.579545 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
1 MHz
SPBRG
value
(decimal)
KBAUD
32.768 kHz
%
ERROR
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
NA
-
-
NA
-
-
0.30
+0.16
207
0.29
-2.48
6
1.2
1.20
+0.16
207
1.20
+0.23
185
1.20
+0.16
51
NA
-
-
2.4
2.40
+0.16
103
2.41
+0.23
92
2.40
+0.16
25
NA
-
-
9.6
9.62
+0.16
25
9.73
+1.32
22
NA
-
-
NA
-
-
19.2
19.23
+0.16
12
18.64
-2.90
11
NA
-
-
NA
-
-
76.8
NA
-
-
74.57
-2.90
2
NA
-
-
NA
-
-
96
NA
-
-
NA
-
-
NA
-
-
NA
-
-
300
NA
-
-
NA
-
-
NA
-
-
NA
-
-
500
NA
-
-
NA
-
-
NA
-
-
NA
-
-
HIGH
250
-
0
55.93
-
0
62.50
-
0
2.05
-
0
LOW
0.98
-
255
0.22
-
255
0.24
-
255
0.008
-
255
DS39541B-page 182
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 183 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
16.2
USART Asynchronous Mode
Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG register is
empty and flag bit TXIF (PIR registers) is set. This interrupt can be enabled/disabled by setting/clearing
enable bit TXIE (PIE registers). Flag bit TXIF will be
set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new
data is loaded into the TXREG register. While flag bit
TXIF indicated the status of the TXREG register,
another bit TRMT (TXSTA register) shows the status of
the TSR register. Status bit TRMT is a read only bit,
which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
In this mode, data is transmitted in non-return-to-zero
(NRZ) format. Data consists of one START bit, eight or
nine data bits and one STOP bit. Data is transmitted in
serial fashion with LSb first. An on-chip 8-bit baud rate
generator can be programmed to generate the desired
baud rate. The baud rate generator produces a clock,
either x16 or x64 of the bit shift rate, depending on the
BRGH bit (TXSTA register). USART does not automatically calculate the parity bit for the given data byte. If
parity is to be transmitted, USART must be programmed to transmit nine bits and software must set/
clear ninth data bit as parity bit. Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
Asynchronous mode is selected by clearing the SYNC
bit (TXSTA register).
2: Flag bit TXIF is set when enable bit TXEN
is set.
The USART Asynchronous module consists of the following important elements:
•
•
•
•
Steps to follow when setting up an Asynchronous
Transmission:
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
16.2.1
1.
2.
USART ASYNCHRONOUS
TRANSMITTER
3.
4.
The USART transmitter block diagram is shown in
Figure 16-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The TSR register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the STOP
bit has been transmitted from the previous load. As
soon as the STOP bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
FIGURE 16-1:
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 16.1).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts transmission).
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG Register
TXIE
8
MSb
LSb
(8)
Pin Buffer
and Control
0
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
TX9
Baud Rate Generator
TX9D
Note:
I/O pins have diode protection to VDD and V SS.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 183
39541a.book Page 184 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 16-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START Bit
Bit 0
Bit 1
TXIF bit
(Transmit Buffer
Register Empty Flag)
TRMT bit
(Transmit Shift
Register Empty Flag)
FIGURE 16-3:
Bit 7/8
STOP Bit
Word 1
Word 1
Transmit Shift Reg
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START Bit
Bit 0
Bit 1
Word 1
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Bit 7/8
STOP Bit
START Bit
Bit 0
Word 2
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 16-6:
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
Bit 3
RBIE
Bit 2
Bit 1
TMR0IF INT0IF
Bit 0
Value on
POR,
BOR
Value on
all other
RESETS
RBIF
0000 000x
0000 000u
PIR1
—
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
-000 0000
-000 0000
PIE1
—
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
-000 0000
-000 0000
IPR1
—
ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP
-000 0000
-000 0000
RCSTA
SPEN
RX9
SREN
CREN
0000 -00x
0000 -00x
0000 0000
0000 0000
0000 0010
0000 0010
0000 0000
0000 0000
—
FERR
OERR
RX9D
TXREG USART Transmit Register
TXSTA
CSRC
TX9
TXEN
SYNC ADDEN BRGH
TRMT
SPBRG Baud Rate Generator Register
TX9D
Legend: x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Transmission.
DS39541B-page 184
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 185 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
16.2.2
USART ASYNCHRONOUS
RECEIVER
16.2.3
The receiver block diagram is shown in Figure 16-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter, operating at x16 times the
baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems.
This mode would typically be used in RS-485 systems.
Steps to follow when setting up an Asynchronous
Reception with Address Detect Enable:
1.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is required,
set the BRGH bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
7. The RCIF bit will be set when reception is complete. The interrupt will be acknowledged if the
RCIE and GIE bits are set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 16.1).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
Enable the reception by setting bit CREN.
Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable
bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
FIGURE 16-4:
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
64
or
16
Baud Rate Generator
RSR Register
MSb
STOP (8)
7
1
LSb
0 START
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
Interrupt
RCIF
Data Bus
RCIE
Note:
I/O pins have diode protection to V DD and VSS.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 185
39541a.book Page 186 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 16-5:
ASYNCHRONOUS RECEPTION
START
bit
bit0
RX (pin)
bit1
bit7/8 STOP
bit
Rcv Shift
Reg
Rcv Buffer Reg
START
bit
bit0
bit7/8 STOP
bit
bit7/8
STOP
bit
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
START
bit
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 16-7:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
INTCON
GIE/GIEH
PIR1
—
ADIF
RCIF
PIE1
—
ADIE
RCIE
IPR1
—
ADIP
RCSTA
SPEN
RX9
RCREG
TXSTA
SPBRG
Bit 6
Bit 5
Bit 0
Value on
POR,
BOR
Value on
all other
RESETS
RBIF
0000 000x
0000 000u
TMR1IF
-000 0000
-000 0000
CCP1IE TMR2IE TMR1IE
-000 0000
-000 0000
CCP1IP TMR2IP TMR1IP
-000 0000
-000 0000
0000 -00x
0000 -00x
0000 0000
0000 0000
0000 0010
0000 0010
0000 0000
0000 0000
Bit 3
Bit 2
Bit 1
INT0IE
RBIE
TMR0IF
INT0IF
TXIF
SSPIF
CCP1IF TMR2IF
TXIE
SSPIE
RCIP
TXIP
SSPIP
SREN
CREN
—
PEIE/GIEL TMR0IE
Bit 4
FERR
OERR
RX9D
USART Receive Register
CSRC
TX9
TXEN
SYNC
ADDEN
BRGH
TRMT
Baud Rate Generator Register
TX9D
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
DS39541B-page 186
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 187 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
16.3
USART Synchronous Master
Mode
bit TXIF (PIR registers) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE registers). Flag bit TXIF will be set, regardless of
the state of enable bit TXIE, and cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register. While flag bit TXIF indicates the
status of the TXREG register, another bit TRMT
(TXSTA register) shows the status of the TSR register.
TRMT is a read only bit, which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory,
so it is not available to the user.
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA register).
In addition, enable bit SPEN (RCSTA register) is set, in
order to configure the RC6/TX/CK and RC7/RX/DT I/O
pins to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA register).
16.3.1
Steps to follow when setting up a Synchronous Master
Transmission:
USART SYNCHRONOUS MASTER
TRANSMISSION
1.
The USART transmitter block diagram is shown in
Figure 16-1. The heart of the transmitter is the Transmit
(serial) Shift register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG is empty and interrupt
TABLE 16-8:
2.
3.
4.
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate (Section 16.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
PIR1
—
ADIF
RCIF
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
Bit 3
Bit 2
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
-000 0000
PIE1
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
IPR1
—
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
-000 0000
-000 0000
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
TXEN
SYNC
ADDEN
BRGH
TRMT
TX9D
0000 0010
0000 0010
0000 0000
0000 0000
TXREG
TXSTA
SPBRG
USART Transmit Register
CSRC
TX9
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 187
39541a.book Page 188 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 16-6:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT
pin
Bit 0
Bit 1
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit 2
Bit 7
Bit 0
Bit 1
Bit 7
Word 2
Word 1
RC6/TX/CK
pin
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit TRMT
TXEN bit
'1'
'1'
Note: Sync Master mode; SPBRG = '0'; continuous transmission of two 8-bit words.
FIGURE 16-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit0
bit1
bit2
bit6
bit7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS39541B-page 188
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 189 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
16.3.2
USART SYNCHRONOUS MASTER
RECEPTION
3.
4.
5.
6.
Ensure bits CREN and SREN are clear.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
Once Synchronous Master mode is selected, reception
is enabled by setting either enable bit SREN (RCSTA
register), or enable bit CREN (RCSTA register). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
When setting up a Synchronous Master reception, follow these steps:
1.
2.
Initialize the SPBRG register for the appropriate
baud rate (Section 16.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
TABLE 16-9:
Name
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
0000 000u
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
PIR1
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
PIE1
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
IPR1
—
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
-000 0000
-000 0000
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
INTCON GIE/GIEH PEIE/GIEL
RCREG USART Receive Register
TXSTA
SPBRG
CSRC
TX9
TXEN
SYNC
ADDEN
BRGH
TRMT
TX9D
Baud Rate Generator Register
0000 0010
0000 0010
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.
FIGURE 16-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit
'0'
'0'
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = '1' and bit BRGH = '0'.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 189
39541a.book Page 190 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
16.4
USART Synchronous Slave Mode
16.4.2
Synchronous Slave mode differs from the Master
mode, in that the shift clock is supplied externally at the
RC6/TX/CK pin (instead of being supplied internally in
Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA register).
USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode and bit SREN, which is a "don't care" in Slave
mode.
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the SLEEP
mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register,
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
When setting up a Synchronous Slave Reception,
follow these steps:
a)
1.
16.4.1
b)
c)
d)
e)
USART SYNCHRONOUS SLAVE
TRANSMIT
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will be set.
If enable bit TXIE is set, the interrupt will wake the
chip from SLEEP. If the global interrupt is enabled,
the program will branch to the interrupt vector.
2.
3.
4.
5.
6.
When setting up a Synchronous Slave Transmission,
follow these steps:
1.
2.
3.
4.
5.
6.
7.
7.
Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
8.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is complete. An interrupt will be generated if enable bit
RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
0000 000u
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
PIR1
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
PIE1
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
—
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
-000 0000
-000 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
0000 0010
0000 0010
0000 0000
0000 0000
INTCON
IPR1
RCSTA
TXREG
TXSTA
SPBRG
GIE/GIEH PEIE/GIEL TMR0IE
Bit 4
USART Transmit Register
CSRC
TX9
TXEN
SYNC
ADDEN
BRGH
TRMT
Baud Rate Generator Register
TX9D
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
DS39541B-page 190
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 191 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 16-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
0000 000u
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
PIR1
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
PIE1
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
IPR1
—
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
-000 0000
-000 0000
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
0000 0010
0000 0010
0000 0000
0000 0000
INTCON
RCREG
TXSTA
SPBRG
GIE/GIEH PEIE/GIEL TMR0IE
Bit 4
USART Receive Register
CSRC
TX9
TXEN
SYNC
ADDEN
BRGH
TRMT
Baud Rate Generator Register
TX9D
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Reception.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 191
39541a.book Page 192 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
NOTES:
DS39541B-page 192
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 193 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
17.0
10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The A/D module has five registers:
The analog-to-digital (A/D) converter module has 8
inputs for the PIC18C601 devices and 12 for the
PIC18C801 devices. This module has the ADCON0,
ADCON1, and ADCON2 registers.
The A/D allows conversion of an analog input signal
to a corresponding 10-bit digital number.
REGISTER 17-1:
•
•
•
•
•
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
A/D Control Register 2 (ADCON2)
The ADCON0 register, shown in Register 17-1, controls
the operation of the A/D module. The ADCON1 register,
shown in Register 17-2, configures the functions of the
port pins. The ADCON2, shown in Register 16-3, configures the A/D clock source and justification.
ADCON0 REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5-2
CHS3:CHS0: Analog Channel Select bits
0000 = channel 00, (AN0)
0001 = channel 01, (AN1)
0010 = channel 02, (AN2)
0011 = channel 03, (AN3)
0100 = channel 04, (AN4)
0101 = channel 05, (AN5)
0110 = channel 06, (AN6)
0111 = channel 07, (AN7)
1000 = channel 08, (AN8)(1)
1001 = channel 09, (AN9)(1)
1010 = channel 10, (AN10)(1)
1011 = channel 11, (AN11)(1)
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
These channels are not available on the PIC18C601 devices.
bit 1
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress. Setting this bit starts an A/D conversion cycle. This bit is
automatically cleared by hardware when the A/D conversion is complete.
0 = A/D conversion not in progress
bit 0
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Advance Information
x = Bit is unknown
DS39541B-page 193
39541a.book Page 194 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 17-2:
ADCON1 REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5-4
VCFG1:VCFG0: Voltage Reference Configuration bits
bit 3-0
A/D VREF+
A/D VREF-
00
AVDD
AVSS
01
External VREF+
AVSS
10
AVDD
External VREF-
11
External VREF+
External VREF-
PCFG3:PCFG0: A/D Port Configuration Control bits
AN9
AN8
AN7
AN6
AN5
AN4
0000
AN11 AN10
A
A
A
A
A
A
A
A
AN3 AN2 AN1 AN0
A
A
A
A
0001
A
A
A
A
A
A
A
A
A
A
A
A
0010
A
A
A
A
A
A
A
A
A
A
A
A
0011
A
A
A
A
A
A
A
A
A
A
A
A
0100
D
A
A
A
A
A
A
A
A
A
A
A
0101
D
D
A
A
A
A
A
A
A
A
A
A
0110
D
D
D
A
A
A
A
A
A
A
A
A
0111
D
D
D
D
A
A
A
A
A
A
A
A
1000
D
D
D
D
D
A
A
A
A
A
A
A
1001
D
D
D
D
D
D
A
A
A
A
A
A
1010
D
D
D
D
D
D
D
A
A
A
A
A
1011
D
D
D
D
D
D
D
D
A
A
A
A
1100
D
D
D
D
D
D
D
D
D
A
A
A
1101
D
D
D
D
D
D
D
D
D
D
A
A
1110
D
D
D
D
D
D
D
D
D
D
D
A
1111
D
D
D
D
D
D
D
D
D
D
D
D
A = Analog input
D = Digital I/O
Shaded cells = Additional A/D channels available on PIC18C801 devices.
Legend:
DS39541B-page 194
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Advance Information
x = Bit is unknown
2001-2013 Microchip Technology Inc.
39541a.book Page 195 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 17-3:
ADCON2 REGISTER
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
ADFM
—
—
—
—
ADCS2
ADCS1
ADCS0
bit 7
bit 7
bit 0
ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6-3
Unimplemented: Read as '0'
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock derived from an internal RC oscillator = 1 MHz max)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC (clock derived from an internal RC oscillator = 1 MHz max)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
The analog reference voltage is software selectable to
either the device’s positive and negative supply
voltage (VDD and VSS), or the voltage level on the
RA3/AN3/VREF+ pin and RA2/AN2/VREF-.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
x = Bit is unknown
Each port pin associated with the A/D converter can
be configured as an analog input (RA3 can also be a
voltage reference), or as a digital I/O.
The ADRESH and ADRESL registers contain the
result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the
ADRESH/ADRESL registers, the GO/DONE bit
(ADCON0 register) is cleared, and A/D interrupt flag
bit ADIF is set. The block diagram of the A/D module
is shown in Figure 17-1.
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off and
any conversion is aborted.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 195
39541a.book Page 196 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 17-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
0111
RF2/AN7
0110
RF1/AN6
0101
RF0/AN5
0100
RA5/AN4
0011
RA3/AN3/VREF+
0010
RA2/AN2/VREF0001
RA1/AN1
0000
VIN
RA0/AN0
(Input voltage)
A/D
Converter
AVDD
1011
RH7/AN11(1)
1010
RH6/AN10(1)
1001
RH5/AN9(1)
1000
RH4/AN8(1)
VREF+
(Reference
Voltage)
VCFG0
VREF(Reference
Voltage)
AVSS
VCFG1
Note 1: These channels are not available on the PIC18C601 devices.
DS39541B-page 196
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 197 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
The value in the ADRESH/ADRESL registers is not
modified for a Power-on Reset. The ADRESH/ADRESL
registers will contain unknown data after a Power-on
Reset.
2.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 17.1.
After this acquisition time has elapsed, the A/D conversion can be started. The following steps should be followed to do an A/D conversion:
3.
4.
1.
6.
5.
Configure the A/D module:
• Configure analog pins, voltage reference
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
FIGURE 17-2:
7.
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0 register)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared,
OR
• Waiting for the A/D interrupt
Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6 V
Rs
VAIN
RIC 1 k
ANx
CPIN
5 pF
VT = 0.6 V
SS
RSS
I leakage
± 500 nA
CHOLD = 120 pF
VSS
Legend: CPIN
= input capacitance
VT
= threshold voltage
I LEAKAGE = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
SS
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
RSS
= sampling switch resistance
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch ( k)
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 197
39541a.book Page 198 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
17.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 17-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5k. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
Note:
Example 17-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
VHOLD
=
=
=
=
=
120 pF
2.5 k
1/2 LSb
5V Rss = 7 k
50C (system max.)
0V @ time = 0
When the conversion is started, the holding capacitor is disconnected from the
input pin.
EQUATION 17-1:
TACQ
To calculate the minimum acquisition time,
Equation 17-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
ACQUISITION TIME
=
Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 17-2:
VHOLD
or
TC
A/D MINIMUM CHARGING TIME
=
(VREF - (VREF/2048)) • (1 - e(-Tc/CHOLD(RIC + RSS + RS)))
=
-(120 pF)(1 k + RSS + RS) ln(1/2047)
EXAMPLE 17-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
=
TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25C.
TACQ
=
2 s + TC + [(Temp - 25C)(0.05 s/C)]
TC
=
-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 k + 7 k + 2.5 k) ln(0.0004885)
-120 pF (10.5 k) ln(0.0004885)
-1.26 s (-7.6241)
9.61 s
TACQ
=
2 s + 9.61 s + [(50C - 25C)(0.05 s/C)]
11.61 s + 1.25 s
12.86 s
DS39541B-page 198
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 199 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
17.2
Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 12 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
•
•
•
•
•
•
•
2TOSC
4TOSC
8TOSC
16TOSC
32TOSC
64TOSC
Internal RC oscillator
17.3
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally
configured input will not affect the conversion accuracy.
2: Analog levels on any pin defined as a digital input may cause the input buffer to
consume current out of the device’s specification limits.
Table 17-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 17-1:
Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be
converted.
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Maximum Device Frequency
PIC18LC601/801(5)
Operation
ADCS2:ADCS0
PIC18C601/801
2TOSC
000
1.25 MHz
666 kHz
4TOSC
100
2.50 MHz
1.33 MHz
2.67 MHz
8TOSC
001
5.00 MHz
16TOSC
101
10.0 MHz
5.33 MHz
32TOSC
010
20.0 MHz
10.67 MHz
64TOSC
110
—
—
RC
x11
—
—
The RC source has a typical TAD time of s.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
For device frequencies above 1 MHz, the device must be in SLEEP for the entire conversion or the A/D
accuracy may be out of specification.
5: This column is for the LC devices only.
Note 1:
2:
3:
4:
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 199
39541a.book Page 200 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
17.4
A/D Conversions
17.5
Figure 17-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, acquisition on the selected channel is
automatically started.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 17-3:
Use of the CCP2 Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON) be programmed as 1011, and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/DONE
bit will be set, starting the A/D conversion and the Timer1
(or Timer3) counter will be reset to zero. Timer1 (or
Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving
ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the “special event trigger”
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D module, but will still reset the Timer1 (or Timer3) counter.
A/D CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9
b9
b0
b2
b1
b4
b3
b5
b6
b8
b7
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
DS39541B-page 200
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 201 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 17-2:
SUMMARY OF A/D REGISTERS
Name
Bit 7
Bit 6
Bit 5
INTCON
GIE/GIEH
PIR1
—
ADIF
RCIF
PEIE/GIEL TMR0IE
Bit 4
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
RESETS
Bit 3
Bit 2
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
-000 0000
PIE1
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-000 0000
-000 0000
IPR1
—
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
-000 0000
-000 0000
PIR2
—
—
—
—
BCLIF
LVDIF
TMR3IF
CCP2IF
-0-- 0000
-0-- 0000
PIE2
—
—
—
—
BCLIE
LVDIE
TMR3IE
CCP2IE
---- 0000
---- 0000
—
—
—
—
BCLIP
LVDIP
TMR3IP
CCP2IP
IPR2
---- 0000
---- 0000
ADRESH
A/D Result Register
xxxx xxxx
uuuu uuuu
ADRESL
A/D Result Register
xxxx xxxx
uuuu uuuu
0000 00-0
0000 00-0
ADCON0
—
—
CHS3
CHS3
CHS1
ADCON1
—
—
VCFG1
PCFG2
PCFG1
PCFG0
---- -000
---- -000
ADCON2
ADFM
—
—
—
—
ADCS2
ADCS1
ADCS0
0--- -000
0--- -000
PORTA
—
—
RA5
RA4
RA3
RA2
RA1
RA0
TRISA
—
VCFG0 PCFG3
CHS0
GO/DONE
ADON
PORTA Data Direction Register
--0x 0000
--0u 0000
--11 1111
--11 1111
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
x000 0000
u000 0000
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
TRISF
PORTF Data Direction Control Register
PORTH(1)
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
0000 xxxx
0000 xxxx
LATH(1)
LATH7
LATH6
LATH5
LATH4
LATH3
LATH2
LATH1
LATH0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
TRISH(1)
PORTH Data Direction Control Register
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Only available on PIC18C801 devices.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 201
39541a.book Page 202 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
NOTES:
DS39541B-page 202
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 203 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
18.0
LOW VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application software can do "housekeeping tasks", before the device
voltage exits the valid operating range. This can be
done using the Low Voltage Detect module.
This module is software programmable circuitry, where
a device voltage trip point can be specified (internal reference voltage or external voltage input). When the
voltage of the device becomes lower than the specified
point, an interrupt flag is set. If the interrupt is enabled,
the program execution will branch to the interrupt vector address and the software can then respond to that
interrupt source.
The Low Voltage Detect circuitry is completely under
software control. This allows the circuitry to be "turned
off" by the software, which minimizes the current consumption for the device.
Figure 18-2 shows the block diagram for the LVD module. A comparator uses an internally generated reference voltage as the set point. When the selected tap
output of the device voltage crosses the set point (is
lower than), the LVDIF bit (PIR registers) is set.
Each node in the resister divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate,
before the LVD module asserts an interrupt. When the
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array (or external LVDIN input
pin) is equal to the voltage generated by the internal
voltage reference module. The comparator then generates an interrupt signal setting the LVDIF bit. This voltage is software programmable to any one of 16 values
(see Figure 18-2). The trip point is selected by
programming the LVDL3:LVDL0 bits (LVDCON).
FIGURE 18-2:
VDD
Figure 18-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage VA,
the LVD logic generates an interrupt. This occurs at time
TA. The application software then has the time, until the
device voltage is no longer in valid operating range, to
shut-down the system. Voltage point VB is the minimum
valid operating voltage specification. This occurs at time
TB. TB - TA is the total time for shut-down.
Voltage
LVD Control
Register
16 to 1 MUX
FIGURE 18-1:
LOW VOLTAGE DETECT
(LVD) BLOCK DIAGRAM
TYPICAL LOW VOLTAGE
DETECT APPLICATION
VA
VB
LVDIF
LVDIN
LVDEN
Internally Generated
Reference Voltage
Time
TA
TB
Legend:
VA = LVD trip point
VB = Minimum valid device operating range
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 203
39541a.book Page 204 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
18.1
Control Register
The Low Voltage Detect Control register (Register 18-1)
controls the operation of the Low Voltage Detect
circuitry.
REGISTER 18-1:
LVDCON REGISTER
U-0
U-0
R-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
—
—
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5
IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the Low Voltage Detect logic will generate the interrupt flag at the specified
voltage range
0 = Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
bit 4
LVDEN: Low Voltage Detect Power Enable bit
1 = Enables LVD, powers up LVD circuit
0 = Disables LVD, powers down LVD circuit
bit 3-0
LVDL3:LVDL0: Low Voltage Detection Limit bits
1111 = External analog input is used (input comes from the LVDIN pin)
1110 = 4.5V
1101 = 4.2V
1100 = 4.0V - Reserved on PIC18C601/801
1011 = 3.8V - Reserved on PIC18C601/801
1010 = 3.6V - Reserved on PIC18C601/801
1001 = 3.5V - Reserved on PIC18C601/801
1000 = 3.3V - Reserved on PIC18C601/801
0111 = 3.0V - Reserved on PIC18C601/801
0110 = 2.8V - Reserved on PIC18C601/801
0101 = 2.7V - Reserved on PIC18C601/801
0100 = 2.5V - Reserved on PIC18C601/801
0011 = 2.4V - Reserved on PIC18C601/801
0010 = 2.2V - Reserved on PIC18C601/801
0001 = 2.0V - Reserved on PIC18C601/801
0000 = Reserved on PIC18C601/801 and PIC18LC801/601
LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage of the device
are not tested.
Legend:
DS39541B-page 204
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Advance Information
x = Bit is unknown
2001-2013 Microchip Technology Inc.
39541a.book Page 205 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
18.2
Operation
The following steps are needed to setup the LVD
module:
Depending on the power source for the device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be constantly operating. To decrease current consumption,
the LVD circuitry only needs to be enabled for short
periods, where the voltage is checked. After doing the
check, the LVD module may be disabled.
1.
2.
3.
Each time that the LVD module is enabled, the circuitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
4.
5.
6.
Write the value to the LVDL3:LVDL0 bits
(LVDCON register), which selects the desired
LVD trip point.
Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
Enable the LVD module (set the LVDEN bit in
the LVDCON register).
Wait for the LVD module to stabilize (the IRVST
bit to become set).
Clear the LVD interrupt flag, which may have
falsely become set, until the LVD module has
stabilized (clear the LVDIF bit).
Enable the LVD interrupt (set the LVDIE and the
GIE bits).
Figure 18-3 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 18-3:
LOW VOLTAGE DETECT WAVEFORMS
CASE 1:
LVDIF may not be set
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
50 ms
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
50 ms
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since LVD condition still exists
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 205
39541a.book Page 206 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
18.2.1
REFERENCE VOLTAGE SET POINT
The Internal Reference Voltage of the LVD module may
be used by other internal circuitry (the programmable
Brown-out Reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires time to become stable before a low voltage condition can be reliably detected. This time is invariant of
system clock speed. This start-up time is specified in
electrical specification parameter #36. The low voltage
interrupt flag will not be enabled until a stable reference
voltage is reached. Refer to the waveform in Figure 18-3.
18.2.2
CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
DS39541B-page 206
18.3
External Analog Voltage Input
The LVD module has an additional feature that allows
the user to supply the trip point voltage to the module
from an external source (the LVDIN pin). The LVDIN pin
is used as the trip point when the LVDL3:LVDL0 bits
equal ’1111’. This state connects the LVDIN pin voltage to the comparator. The other comparator input is
connected to an internal reference voltage source.
18.4
Operation During SLEEP
When enabled, the LVD circuitry continues to operate
during SLEEP. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wakeup from SLEEP. Device execution will continue from
the interrupt vector address, if interrupts have been
globally enabled.
18.5
Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the LVD module to be turned off.
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 207 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
19.0
SPECIAL FEATURES OF THE
CPU
while the power supply stabilizes. With these two timers on-chip, most applications need no external
RESET circuitry.
There are several features intended to maximize
system reliability, minimize cost through elimination of
external components and provide power saving
operating modes:
• OSC Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• ID Locations
19.1
PIC18C601/801 devices have a Watchdog Timer,
which can be permanently enabled/disabled via the
configuration bits, or it can be software controlled. By
default, the Watchdog Timer is disabled to allow software control. It runs off its own RC oscillator for cost
reduction. There are two timers that offer necessary
delays on power-up. One is the Oscillator Start-up
Timer (OST), intended to keep the chip in RESET until
the crystal oscillator is stable. The other is the Powerup Timer (PWRT), which provides a fixed delay on
power-up only, designed to keep the part in RESET
TABLE 19-1:
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up or through an interrupt. Several oscillator
options are also available to allow the part to fit the
application. The RC oscillator option saves system
cost, while the LP crystal option saves power. By
default, HS oscillator mode is selected. There are two
main modes of operations for external memory interface: 8-bit and 16-bit (default). A set of configuration
bits are used to select various options.
Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h - 3FFFFFh),
which can only be accessed using table reads and
table writes.
CONFIGURATION BITS AND DEVICE IDs
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
---- --11
300001h
CONFIG1H
—
—
—
—
—
—
FOSC1
FOSC0
300002h
CONFIG2L
—
BW
—
—
—
—
—
PWRTEN
-1-- ---1
300003h
CONFIG2H
—
—
—
—
WDTEN
---- 1110
WDTPS2 WDTPS1 WDTPS0
300006h
CONFIG4L
r
—
—
—
—
—
—
STVREN
1--- ---1
3FFFFEh
DEVID1
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
0000 0000
3FFFFFh
DEVID2
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, maintain ‘1’.
Shaded cells are unimplemented, read as ’0’.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 207
39541a.book Page 208 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 19-1:
CONFIGURATION REGISTER 1 HIGH (CONFIG1H: BYTE ADDRESS 0300001h)
U-0
U-0
U-0
U-0
U-0
U-0
R/P-1
R/P-1
—
—
—
—
—
—
FOSC1
FOSC0
bit 7
bit 0
bit 7-2
Unimplemented: Read as ’0’
bit 2-0
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = EC oscillator
00 = LP oscillator
Legend:
r = Reserved
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
REGISTER 19-2:
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
CONFIGURATION REGISTER 2 LOW (CONFIG2L: BYTE ADDRESS 300002h)
U-0
R/P-1
U-0
U-0
U-0
U-0
U-0
R/P-1
—
BW
—
—
—
—
—
PWRTEN
bit 7
bit 0
bit 7
Unimplemented: Read as ’0’
bit 6
BW: External Bus Data Width bit
1 = 16-bit external bus mode
0 = 8-bit external bus mode
bit 5-1
Unimplemented: Read as ’0’
bit 0
PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
Legend:
r = Reserved
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
DS39541B-page 208
Advance Information
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
2001-2013 Microchip Technology Inc.
39541a.book Page 209 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
REGISTER 19-3:
CONFIGURATION REGISTER 2 HIGH (CONFIG2H: BYTE ADDRESS 300003H)
U-0
U-0
U-0
U-0
R/P-1
—
—
—
—
WDTPS2
R/P-1
R/P-1
WDTPS1 WDTPS0
R/P-1
WDTEN
bit 7
bit 0
bit 7-4
Unimplemented: Read as ’0’
bit 3-1
WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits
000 =1:128
001 =1:64
010 =1:32
011 =1:16
100 =1:8
101 =1:4
110 =1:2
111 =1:1
bit 0
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)
Legend:
r = Reserved
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
REGISTER 19-4:
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
CONFIGURATION REGISTER 4 LOW (CONFIG4L: BYTE ADDRESS 300006H)
R/P-1
U-0
U-0
U-0
U-0
U-0
R/P-1
R/P-1
r
—
—
—
—
—
—
STVREN
bit 7
bit 0
bit 7
Reserved: Maintain as ‘1’
bit 6-1
Unimplemented: Read as ’0’
bit 0
STVREN: Stack Full/Underflow RESET Enable bit
1 = Stack Full/Underflow will cause RESET
0 = Stack Full/Underflow will not cause RESET
Legend:
r = Reserved
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
2001-2013 Microchip Technology Inc.
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
Advance Information
DS39541B-page 209
39541a.book Page 210 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
19.2
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscillator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKI pin. That means that the WDT will run,
even if the clock on the OSC1/CLKI and OSC2/CLKO
pins of the device has been stopped; for example, by
execution of a SLEEP instruction.
The WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
Values for the WDT postscaler may be assigned by
using configuration bits WDPS in CONFIG2H
register. If the Watchdog Timer is disabled by configuration, values for the WDT postscaler may be assigned
using the SWDPS bits in the WDTCON register.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating a device
RESET condition.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the RCON register
will be cleared upon a WDT time-out.
By default, the Watchdog Timer is disabled by configuration to allow software control over Watchdog Timer
operation. If the WDT is enabled by configuration, software execution may not disable this function. When the
Watchdog Timer is disabled by configuration, the
SWDTEN bit in the WDTCON register enables/
disables the operation of the WDT.
REGISTER 19-5:
2: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
19.2.1
CONTROL REGISTER
Register 19-5 shows the WDTCON register. This is a
readable and writable register. It contains control bits to
control the Watchdog Timer from user software. If the
Watchdog Timer is enabled by configuration, this register setting is ignored.
WDTCON REGISTER
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
SWDPS2
R/W-0
R/W-0
R/W-0
SWDPS1 SWDPS0 SWDTEN
bit 7
bit 0
bit 7-4
Unimplemented: Read as ’0’
bit 3-1
SWDPS2:SWDPS0: Software Watchdog Timer Postscale Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is turned off if it is not disabled
Legend:
DS39541B-page 210
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Advance Information
x = Bit is unknown
2001-2013 Microchip Technology Inc.
39541a.book Page 211 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
19.2.2
WDT POSTSCALER
the device will use predefined set postscaler value. If
the device has the Watchdog Timer disabled by configuration bits, user software can set desired postscaler
value. When the device has the Watchdog Timer
enabled by configuration bits, by default, Watchdog
postscaler of 1:128 is selected.
The WDT has a postscaler that can extend the WDT
Reset period. The postscaler may be programmed by
the user software or is selected by configuration bits
WDTPS in the CONFIG2H register. If the device
has the Watchdog Timer enabled by configuration bits,
FIGURE 19-1:
Watchdog Timer Block Diagram
WDT Timer
Postscaler
8
SWDTEN bit
8 - to - 1 MUX
WDTPS2:WDTPS0
WDT
Time-out
Note: WDPS2:WDPS0 are bits in a configuration register.
TABLE 19-2:
Name
CONFIG2H
RCON
WDTCON
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTEN
—
—
—
—
WDTPS2
WDTPS1
WDTPS0
IPEN
r
—
RI
TO
PD
POR
r
—
—
—
—
SWDPS2
SWDPS1
SWDPS0
SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 211
39541a.book Page 212 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
19.3
Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
Upon entering into Power-down mode, the following
actions are performed:
1.
2.
3.
4.
5.
Watchdog Timer is cleared and kept running.
PD bit in RCON register is cleared.
TO bit in RCON register is set.
Oscillator driver is turned off.
I/O ports maintain the status they had before the
SLEEP instruction was executed.
To achieve lowest current consumption, follow these
steps before switching to Power-down mode:
1.
2.
3.
4.
5.
Place all I/O pins at either VDD or VSS and
ensure no external circuitry is drawing current
from I/O pin.
Power-down A/D and external clocks.
Pull all hi-impedance inputs to high or low,
externally.
Place T0CKI at VSS or VDD.
Current consumption by PORTB on-chip pullups should be taken into account and disabled,
if necessary.
The MCLR pin must be at a logic high level (VIHMC).
19.3.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
External RESET input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change, or a
peripheral interrupt.
The following peripheral interrupts can wake the device
from SLEEP:
4.
TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
5. TMR3 interrupt. Timer3 must be operating as
an asynchronous counter.
6. CCP Capture mode interrupt.
7. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
8. MSSP (START/STOP) bit detect interrupt.
9. MSSP transmit or receive in Slave mode
(SPI/I2C).
10. USART RX or TX (Synchronous Slave mode).
11. A/D conversion (when A/D clock source is RC).
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and will cause a "wake-up". The TO and PD
bits in the RCON register can be used to determine the
cause of the device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared, if a WDT time-out occurred (and caused
wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 2) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
19.3.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If an interrupt condition (interrupt flag bit and interrupt enable bits are set) occurs before the execution of a SLEEP instruction, the SLEEP instruction
will complete as a NOP. Therefore, the WDT and
WDT postscaler will not be cleared, the TO bit will
not be set and PD bits will not be cleared.
• If the interrupt condition occurs during or after
the execution of a SLEEP instruction, the device
will immediately wake-up from sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
DS39541B-page 212
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 213 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
FIGURE 19-2:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTIF bit
Interrupt Latency(3)
GIEH bit
Processor in
SLEEP
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC
Inst(PC) = SLEEP
Inst(PC - 1)
PC+2
PC+4
PC+4
Inst(PC + 2)
Inst(PC + 4)
SLEEP
Inst(PC + 2)
PC + 4
Dummy cycle
0008h
000Ah
Inst(0008h)
Inst(000Ah)
Dummy cycle
Inst(0008h)
Note 1: HS or LP oscillator mode assumed.
2: GIE set is assumed. In this case, after wake- up, the processor jumps to the interrupt routine.
If GIE is cleared, execution will continue in-line.
3: TOST = 1024TOSC (drawing not to scale). This delay will not occur for RC and EC osc modes.
4: CLKOUT is not available in these oscillator modes, but shown here for timing reference.
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 213
39541a.book Page 214 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
NOTES:
DS39541B-page 214
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 215 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
20.0
INSTRUCTION SET SUMMARY
The PIC18C601/801 instruction set adds many
enhancements to the previous PIC® MCU instruction
sets, while maintaining an easy migration path from
them.
With few exceptions, instructions are a single program
memory word (16-bits). Each single word instruction is
divided into an OPCODE, which specifies the instruction type, and one or more operands which further
specify the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
•
•
•
•
Byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
The PIC18C601/801 instruction set summary in
Table 20-2 lists byte-oriented, bit-oriented, literal
and control operations. Table 20-1 shows the opcode
field descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.
The file register (represented by ’f’)
The destination of the result
(represented by ’d’)
The accessed memory
(represented by ’a’)
The file register designator ‘f’ specifies which file register is to be used by the instruction.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If 'd' is zero, the
result is placed in the WREG register. If 'd' is one, the
result is placed in the file register specified in the
instruction.
All bit-oriented instructions have three operands:
1.
2.
3.
The file register (represented by ’f’)
The bit in the file register
(represented by ’b’)
The accessed memory
(represented by ’a’)
• A literal value to be loaded into a file register
(represented by ’k’)
• The desired FSR register to load the literal value
into (represented by ’f’)
• No operand required
(specified by ’—’)
The control instructions may use some of the following
operands:
• A program memory address (represented by ’n’)
• The mode of the Call or Return instructions
(represented by ’s’)
• The mode of the Table Read and Table Write
instructions (represented by ’m’)
• No operand required
(specified by ’—’)
All instructions are a single word, except for four double
word instructions. These four instructions were made
double word instructions so that all the required information is available in these 32 bits. In the second word,
the 4 MSbs are 1’s. If this second word is executed as
an instruction (by itself), it will execute as a NOP.
All single word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
program counter is changed as a result of the instruction. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.The double word instructions execute in two
instruction cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two word branch instructions (if true) would take 3 s.
Figure 20-1 shows the general formats that the instructions can have. All examples use the format ‘nnh’ to
represent a hexadecimal number, where ‘h’ signifies
a hexadecimal digit.
The bit field designator 'b' selects the number of the bit
affected by the operation, while the file register designator 'f' represents the number of the file in which the
bit is located.
2001-2013 Microchip Technology Inc.
The literal instructions may use some of the following
operands:
The Instruction Set Summary, shown in Table 20-2,
lists the instructions recognized by the Microchip
assembler (MPASMTM).
Section 20.1 provides a description of each instruction.
Advance Information
DS39541B-page 215
39541a.book Page 216 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 20-1:
OPCODE FIELD DESCRIPTIONS
Field
a
ACCESS
BANKED
bbb
BSR
d
dest
f
fs
fd
k
label
mm
*
*+
*+*
n
PRODH
PRODL
s
u
W
WREG
x
TBLPTR
TABLAT
TOS
PC
PCL
PCH
PCLATH
PCLATU
GIE
WDT
TO
PD
C, DC, Z, OV, N
[
]
(
)
< >
italics
DS39541B-page 216
Description
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
ACCESS = 0: RAM access bit symbol
BANKED = 1: RAM access bit symbol
Bit address within an 8-bit file register (0 to 7)
Bank Select Register. Used to select the current RAM bank.
Destination select bit;
d = 0: store result in WREG,
d = 1: store result in file register f.
Destination either the WREG register or the specified register file location
8-bit Register file address (00h to FFh)
12-bit Register file address (000h to FFFh). This is the source address.
12-bit Register file address (000h to FFFh). This is the destination address.
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
Label name
The mode of the TBLPTR register for the Table Read and Table Write instructions
Only used with Table Read and Table Write instructions:
No change to register (such as TBLPTR with Table reads and writes)
Post-Increment register (such as TBLPTR with Table reads and writes)
Post-Decrement register (such as TBLPTR with Table reads and writes)
Pre-Increment register (such as TBLPTR with Table reads and writes)
The relative address (2’s complement number) for relative branch instructions, or the direct
address for Call/Branch and Return instructions
Product of Multiply high byte (Register at address FF4h)
Product of Multiply low byte (Register at address FF3h)
Fast Call / Return mode select bit.
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
Unused or Unchanged (Register at address FE8h)
W = 0: Destination select bit symbol
Working register (accumulator) (Register at address FE8h)
Don't care (0 or 1)
The assembler will generate code with x = 0. It is the recommended form of use for compatibility
with all Microchip software tools.
21-bit Table Pointer (points to a Program Memory location) (Register at address FF6h)
8-bit Table Latch (Register at address FF5h)
Top-of-Stack
Program Counter
Program Counter Low Byte (Register at address FF9h)
Program Counter High Byte
Program Counter High Byte Latch (Register at address FFAh)
Program Counter Upper Byte Latch (Register at address FFBh)
Global Interrupt Enable bit
Watchdog Timer
Time-out bit
Power-down bit
ALU status bits Carry, Digit Carry, Zero, Overflow, Negative
Optional
Contents
Assigned to
Register bit field
In the set of
User defined term (font is courier)
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 217 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
FIGURE 20-1:
GENERAL FORMAT FOR INSTRUCTIONS
Example Instruction
Byte-oriented file register operations
15
10
OPCODE
9
d
8 7
a
0
f (FILE #)
ADDWF MYREG, W
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select Bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
OPCODE
15
0
f (Source FILE #)
12 11
MOVFF MYREG1, MYREG2
0
f (Destination FILE #)
1111
f = 12-bit file register address
Bit-oriented file register operations
15
12 11
9 8 7
OPCODE b (BIT #) a
0
f (FILE #)
BSF MYREG, bit
b = 3-bit position of bit in file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select Bank
f = 8-bit file register address
Literal operations
15
8
7
0
OPCODE
k (literal)
MOVLW 7Fh
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
OPCODE
15
0
GOTO Label
n (literal)
12 11
0
n (literal)
1111
n = 20-bit immediate value
15
8 7
OPCODE
15
0
CALL MYFUNC
n (literal)
S
12 11
0
1111
n (literal)
S = Fast bit
15
11 10
OPCODE
0
15
8 7
OPCODE
0
6
OPCODE
2001-2013 Microchip Technology Inc.
4
f
11
1111
BC MYFUNC
n (literal)
15
15
BRA MYFUNC
n (literal)
7
0000
0
k(lit.)
LFSR FSR0, 100h
0
k (literal)
Advance Information
DS39541B-page 217
39541a.book Page 218 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 20-2:
PIC18C601/801 INSTRUCTION SET
Mnemonic,
Operands
16-Bit Instruction Word
Description
Cycles
MSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
f [,d [,a]] Add WREG and f
ADDWFC f [,d [,a]] Add WREG and Carry bit to f
ANDWF
f [,d [,a]] AND WREG with f
CLRF
Clear f
f [,a]
COMF
f [,d [,a]] Complement f
CPFSEQ f [,a]
Compare f with WREG, skip =
CPFSGT f [,a]
Compare f with WREG, skip >
CPFSLT f [,a]
Compare f with WREG, skip <
DECF
f [,d [,a]] Decrement f
DECFSZ f [,d [,a]] Decrement f, Skip if 0
DCFSNZ f [,d [,a]] Decrement f, Skip if Not 0
INCF
f [,d [,a]] Increment f
INCFSZ
f [,d [,a]] Increment f, Skip if 0
INFSNZ
f [,d [,a]] Increment f, Skip if Not 0
IORWF
f [,d [,a]] Inclusive OR WREG with f
MOVF
f [,d [,a]] Move f
MOVFF
Move fs (source) to 1st word
fs, fd
fd (destination)2nd word
Move WREG to f
MOVWF f [,a]
Multiply WREG with f
f [,a]
MULWF
Negate f
f [,a]
NEGF
f [,d [,a]] Rotate Left f through Carry
RLCF
f [,d [,a]] Rotate Left f (No Carry)
RLNCF
f [,d [,a]] Rotate Right f through Carry
RRCF
f [,d [,a]] Rotate Right f (No Carry)
RRNCF
Set f
f [,a]
SETF
SUBFWB f [,d [,a]] Subtract f from WREG with
borrow
f [,d [,a]] Subtract WREG from f
SUBWF
SUBWFB f [,d [,a]] Subtract WREG from f with
borrow
f [,d [,a]] Swap nibbles in f
SWAPF
Test f, skip if 0
TSTFSZ f [,a]
XORWF f [,d [,a]] Exclusive OR WREG with f
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
LSb
Status
Affected
Notes
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
1, 2, 6
1, 2, 6
1,2, 6
2, 6
1, 2, 6
4, 6
4, 6
1, 2, 6
1, 2, 3, 4, 6
1, 2, 3, 4, 6
1, 2, 6
1, 2, 3, 4, 6
4, 6
1, 2, 6
1, 2, 6
1, 6
None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
6
6
1, 2, 6
6
1, 2, 6
6
6
6
1, 2, 6
1
1
1
1
1
1
1
1
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
01da
01da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
1
1
0101
0101
11da
10da
ffff
ffff
ffff C, DC, Z, OV, N 6
ffff C, DC, Z, OV, N 1, 2, 6
1
0011
1 (2 or 3) 0110
1
0001
10da
011a
10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
4, 6
1, 2, 6
6
BIT-ORIENTED FILE REGISTER OPERATIONS
1, 2, 6
BCF
f, b [,a] Bit Clear f
1
1001 bbba ffff ffff None
f, b [,a] Bit Set f
1
1000 bbba ffff ffff None
1, 2, 6
BSF
3, 4, 6
BTFSC
f, b [,a] Bit Test f, Skip if Clear
1 (2 or 3) 1011 bbba ffff ffff None
3, 4, 6
BTFSS
f, b [,a] Bit Test f, Skip if Set
1 (2 or 3) 1010 bbba ffff ffff None
BTG
f [,d [,a]] Bit Toggle f
1
0111 bbba ffff ffff None
1, 2, 6
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an
external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
6: Microchip’s MPASMTM Assembler automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’,
according to address of register being used.
DS39541B-page 218
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 219 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 20-2:
Mnemonic,
Operands
PIC18C601/801 INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Description
Cycles
MSb
CONTROL OPERATIONS
BC
n
Branch if Carry
BN
n
Branch if Negative
BNC
n
Branch if Not Carry
BNN
n
Branch if Not Negative
BNOV
n
Branch if Not Overflow
BNZ
n
Branch if Not Zero
BOV
n
Branch if Overflow
BRA
n
Branch Unconditionally
BZ
n
Branch if Zero
CALL
n, s
Call subroutine1st word
2nd word
CLRWDT —
Clear Watchdog Timer
DAW
—
Decimal Adjust WREG
GOTO
n
Go to address1st word
2nd word
NOP
—
No Operation
NOP
—
No Operation (Note 4)
POP
—
Pop top of return stack (TOS)
PUSH
—
Push top of return stack (TOS)
RCALL
n
Relative Call
RESET
Software device RESET
RETFIE
s
Return from interrupt enable
RETLW
RETURN
SLEEP
Note 1:
2:
3:
4:
5:
6:
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2
1
1
2
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
LSb
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
Status
Affected
Notes
None
None
None
None
None
None
None
None
None
None
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
k
Return with literal in WREG
2
0000 1100 kkkk kkkk None
s
Return from Subroutine
2
0000 0000 0001 001s None
—
Go into Standby mode
1
0000 0000 0000 0011 TO, PD
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an
external device, the data will be written back with a '0'.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
If the table write starts the write cycle to internal memory, the write will continue until terminated.
Microchip’s MPASMTM Assembler automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’,
according to address of register being used.
2001-2013 Microchip Technology Inc.
1
1
1
1
2
1
2
Advance Information
DS39541B-page 219
39541a.book Page 220 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
TABLE 20-2:
PIC18C601/801 INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
16-Bit Instruction Word
Description
Cycles
MSb
LSb
Status
Affected
Notes
LITERAL OPERATIONS
ADDLW
k
Add literal and WREG
1
0000 1111 kkkk kkkk C, DC, Z, OV, N
ANDLW
k
AND literal with WREG
1
0000 1011 kkkk kkkk Z, N
IORLW
k
Inclusive OR literal with WREG 1
0000 1001 kkkk kkkk Z, N
LFSR
f, k
Load FSR (f) with a 12-bit
2
1110 1110 00ff kkkk None
literal (k)
1111 0000 kkkk kkkk
MOVLB
k
Move literal to BSR
1
0000 0001 0000 kkkk None
MOVLW
k
Move literal to WREG
1
0000 1110 kkkk kkkk None
MULLW
k
Multiply literal with WREG
1
0000 1101 kkkk kkkk None
RETLW
k
Return with literal in WREG
2
0000 1100 kkkk kkkk None
SUBLW
k
Subtract WREG from literal
1
0000 1000 kkkk kkkk C, DC, Z, OV, N
XORLW
k
Exclusive OR literal with WREG 1
0000 1010 kkkk kkkk Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
Table Read
2
0000 0000 0000 1000 None
TBLRD*
0000 0000 0000 1001 None
Table Read with post-increment
TBLRD*+
0000 0000 0000 1010 None
TBLRD*Table Read with post-decrement
0000 0000 0000 1011 None
Table Read with pre-increment
TBLRD+*
Table Write
2 (5)
0000 0000 0000 1100 None
TBLWT*
0000 0000 0000 1101 None
Table Write with post-increment
TBLWT*+
0000 0000 0000 1110 None
TBLWT*Table Write with post-decrement
0000 0000 0000 1111 None
Table Write with pre-increment
TBLWT+*
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an
external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
6: Microchip’s MPASMTM Assembler automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’,
according to address of register being used.
DS39541B-page 220
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 221 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
20.1
Instruction Set
ADDLW
ADD literal to WREG
Syntax:
[ label ] ADDLW
Operands:
0 k 255
k
Operation:
(WREG) + k WREG
Status Affected:
N,OV, C, DC, Z
Encoding:
0000
Description:
1111
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
literal 'k'
Process
Data
Write to
WREG
ADDLW
15h
Before Instruction
=
=
=
=
=
=
10h
?
?
?
?
?
=
=
=
=
=
=
Syntax:
[ label ] ADDWF
Operands:
0 f 255
d [0,1]
a [0,1]
f [,d [,a]]
Operation:
(WREG) + (f) dest
Status Affected:
N,OV, C, DC, Z
Encoding:
0010
Description:
ffff
ffff
Add WREG to register 'f'. If 'd' is 0,
the result is stored in WREG. If 'd' is
1, the result is stored back in register
'f' (default). If ’a’ is 0, the Access
Bank will be selected. If ’a’ is 1, the
Bank will be selected as per the BSR
value.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
01da
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
Example:
ADDWF
REG, W
Before Instruction
After Instruction
WREG
N
OV
C
DC
Z
ADD WREG to f
kkkk
The contents of WREG are added to
the 8-bit literal 'k' and the result is
placed in WREG.
Words:
WREG
N
OV
C
DC
Z
kkkk
ADDWF
25h
0
0
0
0
0
WREG
REG
N
OV
C
DC
Z
=
=
=
=
=
=
=
17h
0C2h
?
?
?
?
?
After Instruction
WREG
REG
N
OV
C
DC
Z
2001-2013 Microchip Technology Inc.
Advance Information
=
=
=
=
=
=
=
0D9h
0C2h
1
0
0
0
0
DS39541B-page 221
39541a.book Page 222 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
ADDWFC
ADD WREG and Carry bit to f
Syntax:
[ label ] ADDWFC
Operands:
0 f 255
d [0,1]
a [0,1]
f [,d [,a]]
Operation:
(WREG) + (f) + (C) dest
Status Affected:
N,OV, C, DC, Z
Encoding:
0010
Description:
1
Cycles:
1
Syntax:
[ label ] ANDLW
Operands:
0 k 255
(WREG) .AND. k WREG
Status Affected:
N,Z
0000
Description:
ffff
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Process
Data
Write to
destination
ADDWFC
REG, W
Example:
Before Instruction
=
=
=
=
=
=
=
1
02h
4Dh
?
?
?
?
1011
kkkk
kkkk
The contents of WREG are AND’ed
with the 8-bit literal 'k'. The result is
placed in WREG.
ffff
Read
register 'f'
k
Operation:
Q2
Q3
Q4
Read literal
'k'
Process
Data
Write to
WREG
Example:
Q Cycle Activity:
Q1
C
REG
WREG
N
OV
DC
Z
AND literal with WREG
Encoding:
Add WREG, the Carry Flag and data
memory location 'f'. If 'd' is 0, the
result is placed in WREG. If 'd' is 1,
the result is placed in data memory
location 'f'. If ’a’ is 0, the Access Bank
will be selected. If ’a’ is 1, the Bank
will be selected as per the BSR value.
Words:
Decode
00da
ANDLW
ANDLW
5Fh
Before Instruction
WREG
N
Z
=
=
=
0A3h
?
?
After Instruction
WREG
N
Z
=
=
=
03h
0
0
After Instruction
C
REG
WREG
N
OV
DC
Z
=
=
=
=
=
=
=
DS39541B-page 222
0
02h
50h
0
0
0
0
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 223 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
ANDWF
AND WREG with f
Syntax:
[ label ] ANDWF
Operands:
0 f 255
d [0,1]
a [0,1]
f [,d [,a]]
BC
Branch if Carry
Syntax:
[ label ] BC
Operands:
-128 n 127
Operation:
if carry bit is ’1’
(PC) + 2 + 2n PC
None
Operation:
(WREG) .AND. (f) dest
Status Affected:
Status Affected:
N,Z
Encoding:
Encoding:
0001
Description:
01da
ffff
ffff
Description:
The contents of WREG are AND’ed
with register 'f'. If 'd' is 0, the result is
stored in WREG. If 'd' is 1, the result
is stored back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected. If ’a’ is 1, the bank will be
selected as per the BSR value.
1110
1
Words:
1
Cycles:
1
Cycles:
1(2)
Decode
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write to
destination
Example:
ANDWF
REG, W
Before Instruction
WREG
REG
N
Z
=
=
=
=
17h
0C2h
?
?
0010
nnnn
nnnn
If the Carry bit is ’1’, then the program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Words:
Q Cycle Activity:
Q1
n
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Decode
Q2
Q3
Read literal
'n'
Q4
Process
Data
No
operation
After Instruction
WREG
REG
N
Z
=
=
=
=
02h
0C2h
0
0
Example:
HERE
BC
5
Before Instruction
PC
=
address (HERE)
=
=
=
1;
address (HERE+12)
0;
address (HERE+2)
After Instruction
If Carry
PC
If Carry
PC
2001-2013 Microchip Technology Inc.
Advance Information
DS39541B-page 223
39541a.book Page 224 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 f 255
0b7
a [0,1]
f, b [,a]
BN
Branch if Negative
Syntax:
[ label ] BN
Operands:
-128 n 127
Operation:
if negative bit is ’1’
(PC) + 2 + 2n PC
None
Operation:
0 f
Status Affected:
Status Affected:
None
Encoding:
Encoding:
1001
Description:
ffff
ffff
1110
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register 'f'
Process
Data
Write
register 'f'
Example:
BCF
Before Instruction
FLAG_REG = 0C7h
After Instruction
FLAG_REG = 47h
FLAG_REG,
7
0110
nnnn
nnnn
If the Negative bit is ’1’, then the program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Bit 'b' in register 'f' is cleared. If ’a’ is
0, the Access Bank will be selected,
overriding the BSR value. If ’a’ = 1,
the Bank will be selected as per the
BSR value.
Words:
Decode
bbba
n
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Decode
Q2
Q3
Q4
Read literal
'n'
Process
Data
No
operation
Example:
HERE
BN
Jump
Before Instruction
PC
=
address (HERE)
=
=
=
1;
address (Jump)
0;
address (HERE+2)
After Instruction
If Negative
PC
If Negative
PC
DS39541B-page 224
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 225 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
[ label ] BNC
Syntax:
[ label ] BNN
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if carry bit is ’0’
(PC) + 2 + 2n PC
Operation:
if negative bit is ’0’
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
Description:
1110
n
0011
nnnn
nnnn
Encoding:
1110
If the Carry bit is ’0’, then the
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Description:
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
n
0111
nnnn
nnnn
If the Negative bit is ’0’, then the
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
Write to PC
Decode
Read literal
'n'
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Read literal
'n'
Process
Data
No
operation
If No Jump:
Q1
Decode
Example:
HERE
BNC
Q2
Q3
Q4
Read literal
'n'
Process
Data
No
operation
HERE
BNN
Jump
Before Instruction
=
address (HERE)
PC
After Instruction
If Carry
PC
If Carry
PC
Decode
Example:
Jump
Before Instruction
PC
If No Jump:
Q1
=
address (HERE)
=
=
=
0;
address (Jump)
1;
address (HERE+2)
After Instruction
=
=
=
0;
address (Jump)
1;
address (HERE+2)
2001-2013 Microchip Technology Inc.
If Negative
PC
If Negative
PC
Advance Information
DS39541B-page 225
39541a.book Page 226 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
[ label ] BNOV
Syntax:
[ label ] BNZ
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if overflow bit is ’0’
(PC) + 2 + 2n PC
Operation:
if zero bit is ’0’
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
Description:
n
0101
nnnn
nnnn
Encoding:
1110
If the Overflow bit is ’0’, then the
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Description:
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
n
0001
nnnn
nnnn
If the Zero bit is ’0’, then the program
will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
Write to PC
Decode
Read literal
'n'
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Read literal
'n'
Process
Data
No
operation
If No Jump:
Q1
Decode
Example:
HERE
DS39541B-page 226
Q2
Q3
Q4
Read literal
'n'
Process
Data
No
operation
HERE
BNZ
Jump
Before Instruction
=
address (HERE)
PC
After Instruction
If Overflow
PC
If Overflow
PC
Decode
Example:
BNOV Jump
Before Instruction
PC
If No Jump:
Q1
=
address (HERE)
=
=
=
0;
address (Jump)
1;
address (HERE+2)
After Instruction
=
=
=
0;
address (Jump)
1;
address (HERE+2)
If Zero
PC
If Zero
PC
Advance Information
2001-2013 Microchip Technology Inc.
39541a.book Page 227 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
[ label ] BRA
Syntax:
[ label ] BSF
Operands:
-1024 n 1023
Operands:
0 f 255
0b7
a [0,1]
n
Operation:
(PC) + 2 + 2n PC
Status Affected:
None
Encoding:
Description:
1101
1
Cycles:
2
Q Cycle Activity:
Q1
No
operation
nnnn
nnnn
Add the 2’s complement number ’2n’
to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a twocycle instruction.
Words:
Decode
0nnn
Q2
Q3
Q4
Read literal
'n'
Process
Data
Write to PC
No
operation
No
operation
No
operation
HERE
BRA
Operation:
1 f
Status Affected:
None
Encoding:
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Jump
PC
=
address (HERE)
=
address (Jump)
PC
2001-2013 Microchip Technology Inc.
ffff
Q2
Q3
Q4
Process
Data
Write
register 'f'
BSF
FLAG_REG, 7
Before Instruction
=
0Ah
=
8Ah
After Instruction
FLAG_REG
After Instruction
ffff
Read
register 'f'
FLAG_REG
Before Instruction
bbba
Bit 'b' in register 'f' is set. If ’a’ is 0
Access Bank will be selected, overriding the BSR value. If ’a’ is 1, the
Bank will be selected as per the BSR
value (default).
Words:
Example:
Example:
1000
f, b [,a]
Advance Information
DS39541B-page 227
39541a.book Page 228 Tuesday, January 29, 2013 2:34 PM
PIC18C601/801
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSC f, b [,a]
Syntax:
[ label ] BTFSS f, b [,a]
Operands:
0 f 255
0b7
a [0,1]
Operands:
0 f 255
0b
工商网监
湘ICP备2023018690号
