PIC18F06Q41-I/ST

PIC18F06/16Q41 14/20-Pin, Low-Power, High-Performance Microcontroller with XLP Technology Introduction The PIC18-Q41 microcontroller family is available in 14/20-pin devices for sensor and real-time control applications. This analog-focused family features a 12-bit ADC with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced capacitive touch sensing, averaging, filtering, oversampling and threshold comparison, two 8-bit DAC modules and an Operational Amplifier. The family showcases a 16-bit PWM module that provides dual independent outputs on the same time base. Additional features include vectored interrupt controller with fixed latency for handling interrupts, system bus arbiter, Direct Memory Access (DMA) capabilities, UART with support for asynchronous, DMX, DALI and LIN protocols, SPI, I2C, and a programmable 32-bit CRC with Memory Scan. This family also includes memory features such as Memory Access Partition (MAP) to support users in data protection and bootloader applications, as well as Device Information Area (DIA) that stores factory calibration values to help improve temperature sensor accuracy. PIC18-Q41 Family Types Device Program Memory Flash (bytes) Data SRAM (bytes) Data EEPROM (bytes) Memory Access Partition/ Device Information Area I/O Pins/ Peripheral Pin Select 8-Bit Timer with HLT/ 16-Bit Timers 16-Bit Dual PWM/ CCP Complimentary Waveform Generator Signal Measurement Timer Numerically Controlled Oscillator Configurable Logic Cell 12-Bit ADCC (channels) 8-Bit DAC Operational Amplifier Comparator/ Zero-Cross Detect High-Low Voltage Detect SPI/I2C UART/ UART with Protocol Support Direct Memory Access (DMA) Windowed Watchdog Timer 32-Bit CRC with Scanner Vectored Interrupts Peripheral Module Disable Temperature Indicator Table 1. Devices Included in This Data Sheet PIC18F06Q41 64k 4096 512 Y/Y 12/Y 2/3 3/1 1 1 1 4 11 2 1 2/1 1 2/1 2/1 4 Y Y Y Y Y PIC18F16Q41 64k 4096 512 Y/Y 18/Y 2/3 3/1 1 1 1 4 17 2 1 2/1 1 2/1 2/1 4 Y Y Y Y Y © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 1 PIC18F06/16Q41 Peripheral Module Disable Windowed Watchdog Timer Direct Memory Access (DMA) UART/ UART with Protocol Support 2 1 2/1 1 2/1 2/1 4 Y Y Y Y Y 11 2 1 2/1 1 2/1 2/1 4 Y Y Y Y Y Temperature Indicator 11 4 Vectored Interrupts 4 1 32-Bit CRC with Scanner 1 1 SPI/I2C 1 1 High-Low Voltage Detect 1 3/1 Comparator/ Zero-Cross Detect 3/1 2/3 Operational Amplifier 2/3 12/Y 8-Bit DAC 12/Y Y/Y 12-Bit ADCC (channels) Y/Y 512 Configurable Logic Cell 512 2048 Numerically Controlled Oscillator I/O Pins/ Peripheral Pin Select Signal Measurement Timer Memory Access Partition/ Device Information Area 1024 32k 16-Bit Dual PWM/ CCP Data EEPROM (bytes) 16k PIC18F05Q41 8-Bit Timer with HLT/ 16-Bit Timers Data SRAM (bytes) PIC18F04Q41 Device Program Memory Flash (bytes) Complimentary Waveform Generator Table 2. Devices Not Included in This Data Sheet PIC18F14Q41 16k 1024 512 Y/Y 18/Y 2/3 3/1 1 1 1 4 17 2 1 2/1 1 2/1 2/1 4 Y Y Y Y Y PIC18F15Q41 32k 2048 512 Y/Y 18/Y 2/3 3/1 1 1 1 4 17 2 1 2/1 1 2/1 2/1 4 Y Y Y Y Y Features • • • • • • • • • • C Compiler Optimized RISC Architecture Operating Speed: – DC – 64 MHz clock input – 62.5 ns minimum instruction cycle Four Direct Memory Access (DMA) Controllers: – Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM, or SFR/GPR spaces – User-programmable source and destination sizes – Hardware and software triggered data transfers Vectored Interrupt Capability: – Selectable high/low priority – Fixed interrupt latency of three instruction cycles – Programmable vector table base address – Backwards compatible with previous interrupt capabilities 128-Level Deep Hardware Stack Low-Current Power-on Reset (POR) Configurable Power-up Timer (PWRT) Brown-out Reset (BOR) Low-Power BOR (LPBOR) Option Windowed Watchdog Timer (WWDT): – Watchdog Reset on too long or too short interval between watchdog clear events – Variable prescaler selection – Variable window size selection Memory • • • • • Up to 64 KB of Program Flash Memory Up to 4 KB of Data SRAM Memory 512 Bytes Data EEPROM Memory Access Partition: The Program Flash Memory Can Be Partitioned into: – Application Block – Boot Block – Storage Area Flash (SAF) Block Programmable Code Protection and Write Protection © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 2 PIC18F06/16Q41 • • • Device Information Area (DIA) Stores: – Temperature indicator factory calibrated data – Fixed Voltage Reference measurement data – Microchip Unique Identifier Device Characteristics Information (DCI) Area Stores: – Program/erase row sizes – Pin count details – EEPROM size Direct, Indirect and Relative Addressing Modes Operating Characteristics • • Operating Voltage Range: – 1.8V to 5.5V Temperature Range: – Industrial: -40°C to 85°C – Extended: -40°C to 125°C Power-Saving Functionality • • • • • Doze: CPU and Peripherals Running at Different Cycle Rates (Typically CPU Is Lower) Idle: CPU Halted While Peripherals Operate Sleep: Lowest Power Consumption Peripheral Module Disable (PMD): – Ability to selectively disable hardware module to minimize active power consumption of unused peripherals Low Power Mode Features: – Sleep: < 1 µA typical @ 3V – Operating Current: • 48 µA @ 32 kHz, 3V, typical Digital Peripherals • • • • • • Three 16-Bit Pulse-Width Modulators (PWM): – Dual outputs for each PWM module – Integrated 16-bit timer/counter – Double-buffered user registers for duty cycles – Right/Left/Center/Variable Aligned modes of operation – Multiple clock and Reset signal selections Three 16-Bit Timers (TMR0/1/3) Two 8-Bit Timers (TMR2/4) with Hardware Limit Timer (HLT) Four Configurable Logic Cell (CLC): – Integrated combinational and sequential logic One Complimentary Waveform Generator (CWG): – Rising and falling edge dead-band control – Full-bridge, half-bridge, 1-channel drive – Multiple signal sources – Programmable dead band – Fault-shutdown input One Capture/Compare/PWM (CCP) Module: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 3 PIC18F06/16Q41 • • • • • • • • • – 16-bit resolution for Capture/Compare modes – 10-bit resolution for PWM mode One Numerically Controlled Oscillator (NCO): – Generates true linear frequency control and increased frequency resolution – Input clock up to 64 MHz Signal Measurement Timer (SMT): – 24-bit timer/counter with prescaler – Several modes of operation like Time-of-Flight, Period and Duty Cycle Measurement, etc. Data Signal Modulator (DSM): – Multiplex two carrier clocks, with glitch prevention feature – Multiple sources for each carrier Programmable CRC with Memory Scan: – Reliable data/program memory monitoring for Fail-Safe operation (e.g., Class B) – Calculate 32-bit CRC over any portion of Program Flash Memory Three UART Modules: – One module (UART1) supports LIN host and client, DMX mode, DALI gear, and device protocols – Asynchronous UART, RS-232, RS-485 compatible – Automatic and user timed BREAK period generation – Automatic checksums – Programmable Stop bits (1, 1.5 and 2 Stop bits) – Wake-up on BREAK reception – DMA compatible Two SPI Modules: – Configurable length bytes – Arbitrary length data packets – Transmit-without-receive and receive-without-transmit options – Transfer byte counter – Separate transmit and receive buffers with 2-byte FIFO and DMA capabilities One I2C Module, SMBus, PMBus™ Compatible: – Supports Standard mode (100 kHz), Fast mode (400 kHz) and Fast mode Plus (1 MHz) modes of operation – 7-bit and 10-bit Addressing modes with Address Masking modes – Dedicated address, transmit and receive buffers, and DMA capabilities – Bus collision detection with arbitration – Bus time-out detection and handling – I2C, SMBus 2.0 and SMBus 3.0, and 1.8V input level selections – Separate transmit and receive buffers with 2-byte FIFO and DMA capabilities – Multi-Host mode, including self-addressing Device I/O Port Features: – 12 I/O pins (PIC18F04/05/06Q41) – 18 I/O pins (PIC18F14/15/16Q41) – Individually programmable I/O direction, open-drain, slew rate and weak pull-up control – Interrupt-on-change on most pins – Three programmable external interrupt pins Peripheral Pin Select (PPS): – Enables pin mapping of digital I/O Analog Peripherals • Analog-to-Digital Converter with Computation (ADCC): © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 4 PIC18F06/16Q41 • • • • • – Up to 17 external channels – Up to 140 KSPS – Automated math functions on input signals: • Averaging, filter calculations, oversampling and threshold comparison – Operates in Sleep – Four internal analog channels – Hardware Capacitive Voltage Divider (CVD) support: • Adjustable Sample-and-Hold capacitor array • Guard ring digital output drive • Automates touch sampling and reduces software size and CPU usage when touch or proximity sensing is required Two 8-Bit Digital-to-Analog Converters (DAC): – Buffered output available on two I/O pins – Internal connections to ADC and Comparators Two Comparators (CMP): – Four external inputs – Configurable output polarity – External output via Peripheral Pin Select One Operational Amplifier: – 5.5 MHz gain bandwidth – Programmable gain – Internal gain resistor ladder Zero-Cross Detect (ZCD): – Detect when the AC signal on pin crosses ground Voltage Reference: – Fixed Voltage Reference with 1.024V, 2.048V and 4.096V output levels – Internal connections to ADC, Comparator and DAC Clocking Structure • • • • • • High-Precision Internal Oscillator Block (HFINTOSC): – Selectable frequencies up to 64 MHz – ±1% at calibration – Active Clock Tuning of HFINTOSC for better accuracy 32 kHz Low-Power Internal Oscillator (LFINTOSC) External 32 kHz Crystal Oscillator (SOSC) External High-Frequency Oscillator Block: – Three Crystal/Resonator modes – Digital Clock Input mode – 4x PLL with external sources Fail-Safe Clock Monitor: – Allows for operational recovery if external clock stops Oscillator Start-up Timer (OST): – Ensures stability of crystal oscillator sources Programming/Debug Features • • • In-Circuit Serial Programming™ (ICSP™) via Two Pins In-Circuit Debug (ICD) with Three Breakpoints via Two Pins Debug Integrated On-Chip © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 5 PIC18F06/16Q41 PIC18-Q41 Block Diagram Ports PORTA PORTB PORTC PPS Modu le Peripherals Data Memory (RAM) Data Bus Data EEP RO M Pro gram Flash Memory Instruction Bus Program, Debug and Supervisory Modules Sing le-Sup ply Pro gramming In-Circuit Debug ger Power-up Timer Bro wn-out Reset Oscillator Start-up Timer Fail-Safe Clock Monitor Power-on Reset Temperature Indicato r WWDT PMD Pre cision Ban d G ap Re fere nce and its subsidiaries CLKREF SPI Timers I 2C CCP DMA CRC with Scanner CPU Interrupt Controller Oscillator and Clock SOSCI SOSCO OSC1 OSC2 SOS C EXTOS C EXTOS C + 4xPLL © 2020-2021 Microchip Technology Inc. UART SMT System Arbiter MCLR CLC PWM Interconnect Bus Memory HLVD FVR ADCC CWG DAC NCO CMP DSM ZCD OPA HFINTO SC with Acti ve Clock Tuning LFINTOSC Preliminary Datasheet DS40002214E-page 6 PIC18F06/16Q41 Table of Contents Introduction.....................................................................................................................................................1 PIC18-Q41 Family Types............................................................................................................................... 1 Features......................................................................................................................................................... 2 1. Packages.............................................................................................................................................. 10 2. Pin Diagrams......................................................................................................................................... 11 3. Pin Allocation Tables............................................................................................................................. 12 4. Guidelines for Getting Started with PIC18-Q41 Microcontrollers.......................................................... 16 5. Register and Bit Naming Conventions.................................................................................................. 21 6. Register Legend....................................................................................................................................23 7. PIC18 CPU............................................................................................................................................24 8. Device Configuration.............................................................................................................................42 9. Memory Organization............................................................................................................................56 10. NVM - Nonvolatile Memory Module...................................................................................................... 86 11. VIC - Vectored Interrupt Controller Module..........................................................................................111 12. OSC - Oscillator Module (With Fail-Safe Clock Monitor).................................................................... 172 13. CRC - Cyclic Redundancy Check Module with Memory Scanner.......................................................199 14. Resets................................................................................................................................................. 218 15. WWDT - Windowed Watchdog Timer..................................................................................................231 16. DMA - Direct Memory Access............................................................................................................. 242 17. Power-Saving Modes.......................................................................................................................... 279 18. PMD - Peripheral Module Disable.......................................................................................................287 19. I/O Ports.............................................................................................................................................. 295 20. IOC - Interrupt-on-Change.................................................................................................................. 310 21. PPS - Peripheral Pin Select Module................................................................................................... 316 22. CLC - Configurable Logic Cell.............................................................................................................327 23. CLKREF - Reference Clock Output Module........................................................................................347 24. TMR0 - Timer0 Module....................................................................................................................... 352 25. TMR1 - Timer1 Module with Gate Control...........................................................................................360 26. TMR2 - Timer2 Module....................................................................................................................... 375 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 7 PIC18F06/16Q41 27. SMT - Signal Measurement Timer...................................................................................................... 397 28. CCP - Capture/Compare/PWM Module.............................................................................................. 421 29. Capture, Compare, and PWM Timers Selection................................................................................. 434 30. PWM - Pulse-Width Modulator with Compare.....................................................................................437 31. CWG - Complementary Waveform Generator Module........................................................................463 32. NCO - Numerically Controlled Oscillator Module................................................................................ 490 33. DSM - Data Signal Modulator Module.................................................................................................499 34. UART - Universal Asynchronous Receiver Transmitter with Protocol Support................................... 510 35. SPI - Serial Peripheral Interface Module.............................................................................................556 36. I2C - Inter-Integrated Circuit Module................................................................................................... 589 37. HLVD - High/Low-Voltage Detect........................................................................................................ 675 38. FVR - Fixed Voltage Reference.......................................................................................................... 683 39. Temperature Indicator Module............................................................................................................ 687 40. ADCC - Analog-to-Digital Converter with Computation Module..........................................................692 41. DAC - Digital-to-Analog Converter Module......................................................................................... 737 42. OPA - Operational Amplifier................................................................................................................ 744 43. CMP - Comparator Module................................................................................................................. 756 44. ZCD - Zero-Cross Detection Module...................................................................................................767 45. Instruction Set Summary.....................................................................................................................774 46. ICSP™ - In-Circuit Serial Programming™........................................................................................... 859 47. Register Summary.............................................................................................................................. 862 48. Electrical Specifications...................................................................................................................... 875 49. DC and AC Characteristics Graphs and Tables.................................................................................. 907 50. Packaging Information.........................................................................................................................911 51. Appendix A: Revision History..............................................................................................................929 The Microchip Website...............................................................................................................................930 Product Change Notification Service..........................................................................................................930 Customer Support...................................................................................................................................... 930 Product Identification System.....................................................................................................................931 Microchip Devices Code Protection Feature.............................................................................................. 931 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 8 PIC18F06/16Q41 Legal Notice............................................................................................................................................... 932 Trademarks................................................................................................................................................ 932 Quality Management System..................................................................................................................... 933 Worldwide Sales and Service.....................................................................................................................934 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 9 PIC18F06/16Q41 Packages 1. Packages Table 1-1. Packages Device 14-Pin TSSOP 14-Pin SOIC 20-Pin PDIP 20-Pin SOIC 20-Pin SSOP 20-Pin VQFN PIC18F04Q41 ● ● PIC18F05Q41 ● ● PIC18F06Q41 ● ● PIC18F14Q41 ● ● ● ● PIC18F15Q41 ● ● ● ● PIC18F16Q41 ● ● ● ● © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 10 PIC18F06/16Q41 Pin Diagrams Pin Diagrams Figure 2-1. 14-Pin SOIC 14-Pin TSSOP VDD 1 14 VSS RA5 2 13 RA0/ICSPDAT RA4 3 12 RA1/ICSPCLK MCLR/VPP/RA3 4 11 RA2 RC5 RC4 5 10 RC0 6 9 RC1 RC3 7 8 RC2 Figure 2-2. 20-Pin PDIP 20-Pin SOIC 20-Pin SSOP VDD RA5 RA4 MCLR/VPP/RA3 RC5 RC4 RC3 RC6 RC7 RB7 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 VSS RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC1 RC2 RB4 RB5 RB6 RA0/ICSPDAT VSS VDD RA5 RA4 Figure 2-3. 20-Pin VQFN 20 19 18 17 16 MCLR/VPP/RA3 1 15 RA1/ICSPCLK RC3 4 12 RC1 RC6 5 11 RC2 6 7 8 9 10 RB4 13 RC0 RB5 RC4 3 RB6 14 RA2 RB7 RC5 2 RC7 2. Note:  It is recommended that the exposed bottom pad be connected to VSS; however, it must not be the only VSS connection to the device. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 11 3. Operational Amplifier Comparator ZCD Timers/SMT 16-Bit PWM/CCP CWG CLC SPI I2C UART DSM IOC Interrupts Basic Preliminary Datasheet Reference RA1 A/D RA0 14-Pin SOIC/TSSOP I/O rotatethispage90 13 ANA0 DAC1OUT1 OPA1IN3+ OPA1IN3- C1IN0+ — — — — — SS2(1) — — — IOCA0 — ICDDAT ICSPDAT ANA1 VREF+ (ADC) VREF+ (DAC1) VREF+ (DAC2) — C1IN0C2IN0- — — — — — — — — MDSRC(1) IOCA1 — ICDCLK ICSPCLK — ZCDIN T0CKI(1) — CWGIN(1) — — — — — IOCA2 INT0(1) — 12 VREF- (ADC) VREF(DAC1) OPA1IN2+ VREFOPA1IN2(DAC2) DAC1OUT2 RA2 11 ANA2 RA3 4 — — — — — — — — — — — — — IOCA3 — MCLR VPP RA4 3 ANA4 — — — — T1G(1) — — CLCIN3(1) — — RX3(1) — IOCA4 INT1(1) CLKOUT SOSCO OSC2 RA5 2 ANA5 — — — — T1CKI(1) T2IN(1) SMT1WIN(1) PWM1ERS(1) — — — — CTS3(1) — IOCA5 INT2(1) CLKIN SOSCI OSC1 RC0 10 ANC0 — OPA1IN0+ C2IN0+ — SMT1SIG(1) — — — SCK1(1) SCL1(3,4) — — IOCC0 — — — T4IN(1) PWM2ERS(1) — CLCIN2(1) SDI1(1) SDA1(3,4) RX2(1) — IOCC1 — — ANC1 — OPA1IN0- RC2 8 ANC2 ADACT(1) — OPA1OUT C1IN2C2IN2- — — PWM3ERS(1) — — — — CTS2(1) MDCARL(1) IOCC2 — — RC3 7 ANC3 — OPA1IN1+ OPA1IN1- C1IN3C2IN3- — — PWMIN2(1) — CLCIN0(1) SS1(1) — — — IOCC3 — — — T3G(1) — — CLCIN1(1) SCK2(1) — CTS1(1) — IOCC4 — — CCP1IN(1) PWMIN1(1) — — SDI2(1) RX1(1) MDCARH(1) IOCC5 — — RC4 6 ANC4 — — — 5 ANC5 — — — — T3CKI(1) VDD 1 — — — — — — — — — — — — — — — VDD VSS 14 — — — — — — — — — — — — — — — VSS RC5 PIC18F06/16Q41 9 Pin Allocation Tables DS40002214E-page 12 RC1 C1IN1C2IN1- Pin Allocation Tables © 2020-2021 Microchip Technology Inc. and its subsidiaries Table 3-1. 14-Pin Allocation Table UART DSM IOC Interrupts Basic CLC1OUT CLC2OUT CLC3OUT CLC4OUT SS1 SCK1 SD01 SS2 SCK2 SDO2 I2C TMR0 CWG1A CWG1B CWG1C CWG1D SPI — CWG ZCD Comparator A/D Operational Amplifier — PWM11 PWM12 PWM21 PWM22 PWM31 PWM32 CCP1 CLC — C1OUT C2OUT 16-Bit PWM/CCP — ADCGRDA ADCGRDB Timers/SMT OUT(2) Reference rotatethispage90 14-Pin SOIC/TSSOP I/O © 2020-2021 Microchip Technology Inc. and its subsidiaries ...........continued SDA1 SCL1 DTR1 RTS1 TX1 DTR2 RTS2 TX2 DTR3 RTS3 TX3 DSM1 — — — Notes:  Preliminary Datasheet 1. This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. 2. All digital output signals shown in these rows are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. 3. 4. This is a bidirectional signal. For normal module operation, the firmware may map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. 5. A 0.1 uF bypass capacitor to VSS is required on the VDD pin. PIC18F06/16Q41 Pin Allocation Tables DS40002214E-page 13 RA1 A/D Reference Operational Amplifier Comparator ZCD Timers/SMT 16-Bit PWM/CCP CWG CLC SPI I2C UART DSM IOC Interrupts Basic RA0 20-Pin VQFN rotatethispage90 20-Pin PDIP/SOIC/SSOP I/O © 2020-2021 Microchip Technology Inc. and its subsidiaries Table 3-2. 20-Pin Allocation Table 19 16 ANA0 DAC1OUT1 OPA1IN3+ OPA1IN3- C1IN0+ — — — — — — — — — IOCA0 — ICDDAT ICSPDAT 18 15 Preliminary Datasheet ANA1 VREF+ (ADC) VREF+ (DAC1) VREF+ (DAC2) — C1IN0C2IN0- — — — — — SS2(1) — — MDSRC(1) IOCA1 — ICDCLK ICSPCLK OPA1IN2+ OPA1IN2- — ZCDIN — — CWGIN(1) CLCIN0(1) — — — — IOCA2 — — 14 ANA2 RA3 4 1 — — — — — — — — — — — — — IOCA3 — MCLR VPP RA4 3 20 ANA4 — — — — T1G(1) SMT1SIG(1) — — — — — — — IOCA4 — CLKOUT SOSCO OSC2 RA5 2 19 ANA5 — — — — PWM1ERS(1) — — — — — — IOCA5 — CLKIN SOSCI OSC1 RB4 13 10 ANB4 — OPA1IN0- — — — — — CLCIN2(1) SDI1(1) SDA1(3,4) — — IOCB4 — — RB5 12 9 ANB5 — OPA1IN0+ — — — — — CLCIN3(1) SDI2(1) — RX1(1) — IOCB5 — — RB6 11 8 ANB6 — — — — — — — — SCK1(1) SCL1(3,4) — — IOCB6 — — — CTS1(1) — IOCB7 — — — — — IOCC0 INT0(1) — — IOCC1 INT1(1) — T2IN(1) SMT1WIN(1) RB7 10 7 ANB7 — — — — — — — — SCK2(1) RC0 16 13 ANC0 — — C2IN0+ — — — — — — — T4IN(1) PWM2ERS(1) — — — — RX2(1) DS40002214E-page 14 RC1 15 12 ANC1 — — C1IN1C2IN1- RC2 14 11 ANC2 ADACT(1) — OPA1OUT C1IN2C2IN2- — — PWM3ERS(1) — — — — CTS2(1) MDCARL(1) IOCC2 INT2(1) — RC3 7 4 ANC3 — OPA1IN1+ OPA1IN1- C1IN3C2IN3- — — PWMIN2(1) — CLCIN1(1) — — RX3(1) — IOCC3 — — RC4 6 3 ANC4 — — — — T3G(1) — — — — — — — IOCC4 — — — T3CKI(1) T0CKI(1) CCP1IN(1) PWMIN1(1) — — — — CTS3(1) MDCARH(1) IOCC5 — — RC5 5 2 ANC5 — — — PIC18F06/16Q41 17 Pin Allocation Tables RA2 VREF- (ADC) VREF(DAC1) VREF(DAC2) DAC1OUT2 — T1CKI(1) — — — SS1(1) — — — IOCC6 — — — — — — — — — — — IOCC7 — — VDD 1 18 — — — — — — — — — — — — — — — VDD VSS 20 17 — — — — — — — — — — — — — — — VSS SDA1 SCL1 DTR1 RTS1 TX1 DTR2 RTS2 TX2 DTR3 RTS3 TX3 DSM1 — — — OUT(2) — — ADCGRDA ADCGRDB — — C1OUT C2OUT — TMR0 Preliminary Datasheet PWM11 PWM12 PWM21 PWM22 PWM31 PWM32 CCP1 CWG1A CWG1B CWG1C CWG1D CLC1OUT CLC2OUT CLC3OUT CLC4OUT SS1 SCK1 SD01 SS2 SCK2 SDO2 Basic IOC — — Interrupts DSM — — UART — — I2C SPI ANC6 ANC7 CWG CLC 16-Bit PWM/CCP Timers/SMT 5 6 Reference 8 9 rotatethispage90 A/D ZCD Comparator Operational Amplifier 20-Pin VQFN 20-Pin PDIP/SOIC/SSOP RC6 RC7 I/O © 2020-2021 Microchip Technology Inc. and its subsidiaries ...........continued Notes:  1. This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. 2. All digital output signals shown in these rows are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. 3. 4. This is a bidirectional signal. For normal module operation, the firmware may map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. 5. A 0.1 uF bypass capacitor to VSS is required on the VDD pin. PIC18F06/16Q41 Pin Allocation Tables DS40002214E-page 15 PIC18F06/16Q41 Guidelines for Getting Started with PIC18-Q41 Micr... 4. Guidelines for Getting Started with PIC18-Q41 Microcontrollers 4.1 Basic Connection Requirements Getting started with the PIC18-Q41 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • • All VDD and VSS pins (see the Power Supply Pins section) MCLR pin (see the Master Clear (MCLR) Pin section) These pins must also be connected if they are being used in the end application: • • ICSPCLK/ICSPDAT pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see the In-Circuit Serial Programming (ICSP) Pins section) OSCI and OSCO pins when an external oscillator source is used (see the External Oscillator Pins section) Additionally, the following pins may be required: • VREF+/VREF- pins are used when external voltage reference for analog modules is implemented The minimum mandatory connections are shown in the figure below. Figure 4-1. Recommended Minimum Connections Rev. 10-000249C 4/1/2019 VDD VDD R1 R2 VSS C2 MCLR C1 PIC® MCU VSS Key: C1: 0.1 F, 20V ceramic (recommended) R1: 10 kΩ (recommended) R2: 100Ω to 470Ω (recommended) C2: 0.1 F, 20V ceramic (required) 4.2 Power Supply Pins 4.2.1 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins (VDD and VSS) is required. Consider the following criteria when using decoupling capacitors: • • Value and type of capacitor: A 0.1 μF (100 nF), 10-20V capacitor is recommended. The capacitor needs to be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. Placement on the printed circuit board: The decoupling capacitors need to be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 16 PIC18F06/16Q41 Guidelines for Getting Started with PIC18-Q41 Micr... • • 4.2.2 Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 μF to 0.001 μF. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 μF in parallel with 0.001 μF). Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. Tank Capacitors On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor will be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor that meets the acceptable voltage sag at the device. Typical values range from 4.7 μF to 47 μF. 4.3 Master Clear (MCLR) Pin The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 4-1. Other circuit designs may be implemented, depending on the application’s requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 4-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin need to be placed within 0.25 inch (6 mm) of the pin. Figure 4-2. Example of MCLR Pin Connections VDD Rev. 30-000058A 4/5/2017 R1 R2 JP MCLR PIC® MCU C1 Notes:  1. R1 ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL   specifications are met.  2. R2 ≤ 470Ω will limit any current flowing into MCLR from the extended capacitor, C1, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin   VIH and VIL specifications are met. 4.4 In-Circuit Serial Programming™ (ICSP™) Pins The ICSPCLK and ICSPDAT pins are used for ICSP and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100Ω. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 17 PIC18F06/16Q41 Guidelines for Getting Started with PIC18-Q41 Micr... Pull-up resistors, series diodes and capacitors on the ICSPCLK and ICSPDAT pins are not recommended as they can interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they need to be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits, and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the “Communication Channel Select” (i.e., ICSPCLK/ICSPDAT pins), programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. 4.5 External Oscillator Pins Many microcontrollers have options for at least two oscillators: A high-frequency primary oscillator and a lowfrequency secondary oscillator. The oscillator circuit needs to be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors have to be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour needs to be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Layout suggestions are shown in the following figure. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 18 PIC18F06/16Q41 Guidelines for Getting Started with PIC18-Q41 Micr... Figure 4-3. Suggested Placement of the Oscillator Circuit In planning the application’s routing and I/O assignments, ensure that adjacent PORT pins, and other signals in close proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). For additional information and design guidance on oscillator circuits, refer to these Microchip application notes, available at the corporate website (www.microchip.com): • • • • ® AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro Devices” ® AN849, “Basic PICmicro Oscillator Design” ® AN943, “Practical PICmicro Oscillator Analysis and Design” AN949, “Making Your Oscillator Work” © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 19 PIC18F06/16Q41 Guidelines for Getting Started with PIC18-Q41 Micr... 4.6 Unused I/Os Unused I/O pins need to be configured as outputs and driven to a Logic Low state. Alternatively, connect a 1 kΩ to 10 kΩ resistor to VSS on unused pins to drive the output to logic low. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 20 PIC18F06/16Q41 Register and Bit Naming Conventions 5. Register and Bit Naming Conventions 5.1 Register Names When there are multiple instances of the same peripheral in a device, the Peripheral Control registers will be depicted as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The Control registers section will show just one instance of all the register names with an ‘x’ in the place of the peripheral instance number. This naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device to maintain compatibility with other devices in the family that contain more than one. 5.2 Bit Names There are two variants for bit names: • • 5.2.1 Short name: Bit function abbreviation Long name: Peripheral abbreviation + short name Short Bit Names Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit. The bit names shown in the registers are the short name variant. Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short name is RegisterNamebits.ShortName. For example, the enable bit, ON, in the ADCON0 register can be set in C programs with the instruction ADCON0bits.ON = 1. Short names are generally not useful in assembly programs because the same name may be used by different peripherals in different bit positions. When it occurs, during the include file generation, the short bit name instances are appended with an underscore plus the name of the register where the bit resides, to avoid naming contentions. 5.2.2 Long Bit Names Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to the peripheral, thereby making every long bit name unique. The long bit name for the ADC enable bit is the ADC prefix, AD, appended with the enable bit short name, ON, resulting in the unique bit name ADON. Long bit names are useful in both C and assembly programs. For example, in C the ADCON0 enable bit can be set with the ADON = 1 instruction. In assembly, this bit can be set with the BSF ADCON0,ADON instruction. 5.2.3 Bit Fields Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention. For example, the three Least Significant bits of the ADCON2 register contain the ADC Operating Mode Selection bit. The short name for this field is MD and the long name is ADMD. Bit field access is only possible in C programs. The following example demonstrates a C program instruction for setting the ADC to operate in Accumulate mode: ADCON2bits.MD = 0b001; Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended with the number of the bit position within the field. For example, the Most Significant MODE bit has the short bit name MD2 and the long bit name is ADMD2. The following two examples demonstrate assembly program sequences for setting the ADC to operate in Accumulate mode: MOVLW ANDWF MOVLW IORWF ~(1 Main Priority In this case, interrupt routines and peripheral operation (DMAx, Scanner) will stall the Main loop. Interrupt will preempt peripheral operation, which results in lowest interrupt latency. 7.2.4 Peripheral 1 Priority > ISR Priority > Main Priority > Peripheral 2 Priority In this case, the Peripheral 1 will stall the execution of the CPU. However, Peripheral 2 can access the memory in cycles unused by Peripheral 1, ISR and the Main Routine. 7.3 8x8 Hardware Multiplier This device includes an 8x8 hardware multiplier as part of the ALU within the CPU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register, PROD. The multiplier’s operation does not affect any flags in the STATUS register. Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the device to be used in many applications previously reserved for digital signal processors. A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 7-2. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 26 PIC18F06/16Q41 PIC18 CPU Table 7-2. Performance Comparison for Various Multiply Operations Routine 8x8 unsigned 8x8 signed 16x16 unsigned 16x16 signed 7.3.1 Program Time Cycles Memory (Max) @ 64 MHz @ 40 MHz @ 10 MHz @ 4 MHz (Words) Multiply Method Without hardware multiply 13 69 4.3 μs 6.9 μs 27.6 μs 69 μs Hardware multiply 1 1 62.5 ns 100 ns 400 ns 1 μs Without hardware multiply 33 91 5.7 μs 9.1 μs 36.4 μs 91 μs Hardware multiply 6 6 375 ns 600 ns 2.4 μs 6 μs Without hardware multiply 21 242 15.1 μs 24.2 μs 96.8 μs 242 μs Hardware multiply 28 28 1.8 μs 2.8 μs 11.2 μs 28 μs Without hardware multiply 52 254 15.9 μs 25.4 μs 102.6 μs 254 μs Hardware multiply 35 40 2.5 μs 4.0 μs 16.0 μs 40 μs Operation Example 7-3 shows the instruction sequence for an 8x8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 7-4 shows the sequence to do an 8x8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. Example 7-3. 8x8 Unsigned Multiply Routine MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> PRODH:PRODL Example 7-4. 8x8 Signed Multiply Routine MOVF MULWF BTFSC SUBWF MOVF BTFSC SUBWF 7.3.2 ARG1, W ARG2 ARG2, SB PRODH, F ARG2, W ARG1, SB PRODH, F ; ARG1 * ARG2 -> PRODH:PRODL ; Test Sign Bit ; PRODH = PRODH - ARG1 ; Test Sign Bit ; PRODH = PRODH - ARG2 16x16 Unsigned Multiplication Algorithm Example 7-6 shows the sequence to do a 16x16 unsigned multiplication. Example 7-5 shows the algorithm that is used. The 32-bit result is stored in four registers. Example 7-5. 16x16 Unsigned Multiply Algorithm RES3: RES0 = ARG1H: ARG1L • ARG2H: ARG2L = ARG1H • ARG2H • 216 + ARG1H • ARG2L • 28 + ARG1L • ARG2H • 28 + ARG1L • ARG2L © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 27 PIC18F06/16Q41 PIC18 CPU Example 7-6. 16x16 Unsigned Multiply Routine ; ; ; 7.3.3 MOVF MULWF MOVFF MOVFF ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ; ARG1L * ARG2L → PRODH:PRODL ; ; MOVF MULWF MOVFF MOVFF ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ; ; ARG1H * ARG2H → PRODH:PRODL ; ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1L * ARG2H → PRODH:PRODL ; ; Add cross products ; ; ; ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ; ARG1H * ARG2L → PRODH:PRODL ; ; Add cross products ; ; ; ; 16x16 Signed Multiplication Algorithm Example 7-8 shows the sequence to do a 16x16 signed multiply. Example 7-7 shows the algorithm used. The 32-bit result is stored in four registers. To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done. Example 7-7. 16x16 Signed Multiply Algorithm RES3: RES0 = ARG1H: ARG1L • ARG2H: ARG2L = ARG1H • ARG2H • 216 + ARG1H • ARG2L • 28 + ARG1L • ARG2H • 28 + ARG1L • ARG2L + − 1 • ARG2H < 7 > • ARG1H: ARG1L • 216 + − 1 • ARG1H < 7 > • ARG2H: ARG2L • 216 Example 7-8. 16x16 Signed Multiply Routine ; ; ; MOVF MULW MOVF MOVFF ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ; ARG1L * ARG2L → PRODH:PRODL ; ; MOVF MULWF MOVFF MOVFF ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ; ARG1H * ARG2H → PRODH:PRODL ; ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1L * ARG2H → PRODH:PRODL ; ; Add cross products ; ; ; ; MOVF MULWF ARG1H, W ARG2L ; ; ARG1H * ARG2L → PRODH:PRODL © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 28 PIC18F06/16Q41 PIC18 CPU ; ; MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ; Add cross products ; ; ; ; BTFSS BRA MOVF SUBWF MOVF SUBWFB ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; SIGN_ARG1: BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE: : 7.4 PIC18 Instruction Cycle 7.4.1 Instruction Flow/Pipelining An “Instruction Cycle” consists of four cycles of the oscillator clock. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the Program Counter (PC) to change (e.g., GOTO), then two cycles are required to complete the instruction (Figure 7-3). A fetch cycle begins with the Program Counter (PC) incrementing followed by the execution cycle. In the execution cycle, the fetched instruction is latched onto the Instruction Register (IR). This instruction is then decoded and executed during the next few oscillator clock cycles. Data memory is read (operand read) and written (destination write) during the execution cycle as well. Figure 7-3. Instruction Pipeline Flow Rev. 10-000 337A 2/28/201 9 TCY0 TCY1 Fetch 1 Execute 1 1. MOVLW 55h 2. MOVWF PORTB 3. BRA Sub_1 4. BSF PORTA, BITS (Forced NOP) Fetch 2 TCY2 TCY3 TCY4 TCY5 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch Sub_1 5. Instruction @ address Sub_1 Execute Sub_1 Note:  There are some instructions that take multiple cycles to execute. Refer to the “Instruction Set Summary” section for details. 7.4.2 Instructions in Program Memory The program memory is addressed in bytes. Instructions are stored as either two bytes, four bytes, or six bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of two and the LSb will always read ‘0’. See the “Program Counter” section in the “Memory Organization” chapter for more details. The instructions in the Program Memory figure below shows how instruction words are stored in the program memory. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 29 PIC18F06/16Q41 PIC18 CPU The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to the corresponding bits of the Program Counter register, which accesses the desired byte address in program memory. Instruction #2 in the example shows how the instruction GOTO 0006h is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Figure 7-4. Instructions in Program Memory LSB = 1 LSB = 0 Word Address Program Memory Byte Locations 7.4.3 Instruction 1: Instruction 2: MOVLW GOTO 055h 0006h Instruction 3: MOVFF 123h, 456h Instruction 4: MOVFFL 123h, 456h 0Fh EFh F0h C1h F4h 00h F4h F4h 55h 03h 00h 23h 56h 60h 8Ch 56h 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h 000016h 000018h 00001Ah Multi-Word Instructions The standard PIC18 instruction set has six two-word instructions: CALL, MOVFF, GOTO, LFSR, MOVSF and MOVSS and two three-word instructions: MOVFFL and MOVSFL. In all cases, the second and the third word of the instruction always has 1111 as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. The use of 1111 in the four MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence, immediately after the first word, the data in the second word is accessed and used by the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Table 7-3 and Table 7-4 show more details of how two-word instructions work. Table 7-5 and Table 7-6 show more details of how three-word instructions work. Important:  See the “PIC18 Instruction Execution and the Extended Instruction Set” section for information on two-word instructions in the extended instruction set. Table 7-3. Two-Word Instructions (Case 1) Object Code Source Code Comment 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0101 0011 MOVFF REG1,REG2 ; No, skip this word 1111 0100 0101 0110 0010 0100 0000 0000 ; Execute this word as NOP ADDWF REG3 © 2020-2021 Microchip Technology Inc. and its subsidiaries ; continue code Preliminary Datasheet DS40002214E-page 30 PIC18F06/16Q41 PIC18 CPU Table 7-4. Two-Word Instructions (Case 2) Object Code Source Code Comment 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0101 0011 MOVFF REG1,REG2 ; Yes, execute this word 1111 0100 0101 0110 0010 0100 0000 0000 ; 2nd word of instruction ADDWF REG3 ; continue code Table 7-5. Three-Word Instructions (Case 1) Object Code Source Code Comment 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 0000 0000 0110 0000 MOVFFL REG1,REG2 ; Yes, skip this word 1111 0100 1000 1100 ; Execute this word as NOP 1111 0100 0101 0110 ; Execute this word as NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code Table 7-6. Three-Word Instructions (Case 2) Object Code Source Code Comment 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 0000 0000 0110 0000 MOVFFL REG1,REG2 ; No, execute this word 1111 0100 1000 1100 ; 2nd word of instruction 1111 0100 0101 0110 ; 3rd word of instruction 0010 0100 0000 0000 7.5 ADDWF REG3 ; continue code STATUS Register The STATUS register contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed. Therefore, the result of an instruction with the STATUS register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’). It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions that do not affect Status bits, see the instruction set summaries. Important:  The C and DC bits operate as the Borrow and Digit Borrow bits, respectively, in subtraction. 7.6 Call Shadow Register When CALL instruction is used, the WREG, BSR and STATUS are automatically saved in hardware and can be accessed using the WREG_CSHAD, BSR_CSHAD and STATUS_CSHAD registers. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 31 PIC18F06/16Q41 PIC18 CPU Important:  The contents of these registers need to be handled correctly to avoid erroneous code execution. 7.7 Register Definitions: System Arbiter © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 32 PIC18F06/16Q41 PIC18 CPU 7.7.1 ISRPR Name:  Address:  ISRPR 0x0BF Interrupt Service Routine Priority Register Bit 7 6 5 4 3 Access Reset 2 R/W 1 1 PR[2:0] R/W 1 0 R/W 1 Bits 2:0 – PR[2:0] Interrupt Service Routine Priority Selection Value Description 111 110 101 100 011 010 001 000 System Arbiter Priority Level: 7 (Lowest Priority) System Arbiter Priority Level: 6 System Arbiter Priority Level: 5 System Arbiter Priority Level: 4 System Arbiter Priority Level: 3 System Arbiter Priority Level: 2 System Arbiter Priority Level: 1 System Arbiter Priority Level: 0 (Highest Priority) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 33 PIC18F06/16Q41 PIC18 CPU 7.7.2 MAINPR Name:  Address:  MAINPR 0x0BE Main Routine Priority Register Bit 7 6 5 4 3 Access Reset 2 R/W 1 1 PR[2:0] R/W 1 0 R/W 1 Bits 2:0 – PR[2:0] Main Routine Priority Selection Value Description 111 110 101 100 011 010 001 000 System Arbiter Priority Level: 7 (Lowest Priority) System Arbiter Priority Level: 6 System Arbiter Priority Level: 5 System Arbiter Priority Level: 4 System Arbiter Priority Level: 3 System Arbiter Priority Level: 2 System Arbiter Priority Level: 1 System Arbiter Priority Level: 0 (Highest Priority) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 34 PIC18F06/16Q41 PIC18 CPU 7.7.3 DMAxPR Name:  Address:  DMAxPR 0x0B6,0x0B7,0x0B8,0x0B9 DMAx Priority Register Bit 7 6 5 4 3 Access Reset 2 R/W 1 1 PR[2:0] R/W 1 0 R/W 1 Bits 2:0 – PR[2:0] DMAx Priority Selection Value Description 111 110 101 100 011 010 001 000 System Arbiter Priority Level: 7 (Lowest Priority) System Arbiter Priority Level: 6 System Arbiter Priority Level: 5 System Arbiter Priority Level: 4 System Arbiter Priority Level: 3 System Arbiter Priority Level: 2 System Arbiter Priority Level: 1 System Arbiter Priority Level: 0 (Highest Priority) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 35 PIC18F06/16Q41 PIC18 CPU 7.7.4 SCANPR Name:  Address:  SCANPR 0x0B5 Scanner Priority Register Bit 7 6 5 4 3 Access Reset 2 R/W 1 1 PR[2:0] R/W 1 0 R/W 1 Bits 2:0 – PR[2:0] Scanner Priority Selection Value Description 111 110 101 100 011 010 001 000 System Arbiter Priority Level: 7 (Lowest Priority) System Arbiter Priority Level: 6 System Arbiter Priority Level: 5 System Arbiter Priority Level: 4 System Arbiter Priority Level: 3 System Arbiter Priority Level: 2 System Arbiter Priority Level: 1 System Arbiter Priority Level: 0 (Highest Priority) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 36 PIC18F06/16Q41 PIC18 CPU 7.7.5 PRLOCK Name:  Address:  PRLOCK 0x0B4 Priority Lock Register Bit 7 6 5 4 3 Access Reset 2 1 0 PRLOCKED R/W 0 Bit 0 – PRLOCKED PR Register Lock Value Description 1 Priority registers are locked and cannot be written; Peripherals do not have access to the memory 0 Priority registers can be modified by write operations; Peripherals do not have access to the memory Important:  1. The PRLOCKED bit can only be set or cleared after the unlock sequence. 2. If the Configuration Bit PR1WAY = 1, the PRLOCKED bit cannot be cleared after it has been set. A device Reset will clear the bit and allow one more set. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 37 PIC18F06/16Q41 PIC18 CPU 7.7.6 PROD Name:  Address:  PROD 0x4F3 Timer Register Product Register Pair Bit Access Reset Bit 15 14 13 R/W 0 R/W 0 R/W 0 7 6 5 12 11 PROD[15:8] R/W R/W 0 0 4 10 9 8 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W x R/W x R/W x R/W x PROD[7:0] Access Reset R/W x R/W x R/W x R/W x Bits 15:0 – PROD[15:0] PROD Most Significant Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • PRODH: Accesses the high byte PROD[15:8] • PRODL: Accesses the low byte PROD[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 38 PIC18F06/16Q41 PIC18 CPU 7.7.7 STATUS Name:  Address:  STATUS 0x4D8 STATUS Register Bit 7 Access Reset 6 TO R 1 5 PD R 1 4 N R/W 0 3 OV R/W 0 2 Z R/W 0 1 DC R/W 0 0 C R/W 0 Bit 6 – TO Time-Out Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 Set at power-up or by execution of the CLRWDT or SLEEP instruction 0 A WDT time-out occurred Bit 5 – PD Power-Down Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 Set at power-up or by execution of the CLRWDT instruction 0 Cleared by execution of the SLEEP instruction Bit 4 – N Negative Used for signed arithmetic (two’s complement); indicates if the result is negative (ALU MSb = 1). Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 The result is negative 0 The result is positive Bit 3 – OV Overflow Used for signed arithmetic (two’s complement); indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 Overflow occurred for current signed arithmetic operation 0 No overflow occurred Bit 2 – Z Zero Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 The result of an arithmetic or logic operation is zero 0 The result of an arithmetic or logic operation is not zero Bit 1 – DC  Digit Carry / Borrow ADDWF, ADDLW, SUBLW, SUBWF instructions(1) Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 A carry-out from the 4th low-order bit of the result occurred 0 No carry-out from the 4th low-order bit of the result © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 39 PIC18F06/16Q41 PIC18 CPU Bit 0 – C  Carry / Borrow ADDWF, ADDLW, SUBLW, SUBWF instructions(1,2) Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 A carry-out from the Most Significant bit of the result occurred 0 No carry-out from the Most Significant bit of the result occurred Notes:  1. For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. 2. For Rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low-order bit of the Source register. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 40 PIC18F06/16Q41 PIC18 CPU 7.8 Address 0x00 ... 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA ... 0xBD 0xBE 0xBF 0xC0 ... 0x0372 0x0373 0x0374 0x0375 0x0376 0x0377 0x0378 0x0379 0x037A 0x037C 0x037E 0x0380 0x0382 0x0384 ... 0x04D7 0x04D8 0x04D9 ... 0x04F2 0x04F3 Register Summary - System Arbiter Control Name Bit Pos. 7 6 5 4 3 2 1 0 Reserved PRLOCK SCANPR DMA1PR DMA2PR DMA3PR DMA4PR 7:0 7:0 7:0 7:0 7:0 7:0 PR[2:0] PR[2:0] PR[2:0] PR[2:0] PR[2:0] PRLOCKED 7:0 7:0 PR[2:0] PR[2:0] Reserved MAINPR ISRPR Reserved STATUS_CSHAD WREG_CSHAD BSR_CSHAD Reserved STATUS_SHAD WREG_SHAD BSR_SHAD PCLAT_SHAD FSR0_SHAD FSR1_SHAD FSR2_SHAD PROD_SHAD 7:0 7:0 7:0 TO 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 TO 7:0 TO PD N OV Z DC C Z DC C DC C WREG[7:0] BSR[5:0] PD N OV WREG[7:0] BSR[5:0] PCLATH[7:0] PCLATU[4:0] FSRL[7:0] FSRH[5:0] FSRL[7:0] FSRH[5:0] FSRL[7:0] FSRH[5:0] PROD[7:0] PROD[15:8] Reserved STATUS PD N OV Z Reserved PROD 7:0 15:8 © 2020-2021 Microchip Technology Inc. and its subsidiaries PROD[7:0] PROD[15:8] Preliminary Datasheet DS40002214E-page 41 PIC18F06/16Q41 Device Configuration 8. 8.1 Device Configuration Configuration Settings The Configuration settings allow the user to set up the device with several choices of oscillators, Resets and memory protection options. These are implemented at 0x300000 - 0x300009. Important:  The DEBUG Configuration bit is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit needs to be maintained as a ‘1’. 8.2 Code Protection Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting. A single code-protect bit controls the access for both program memory and data EEPROM memory. The entire program memory and Data EEPROM space is protected from external reads and writes by the CP bit. When CP = 0, external reads and writes are inhibited and a read will return all ‘0’s. The CPU can continue to read the memory, regardless of the protection bit settings. Self-writing the program memory is dependent upon the write protection setting. 8.3 User ID 32 words in the memory space (0x200000 - 0x20003F) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See the “User ID, Device ID and Configuration Settings Access, DIA and DCI” section for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC18-Q41 Family Programming Specification” (DS40002143). 8.4 Device ID and Revision ID The 16-bit device ID word is located at 0x3FFFFE and the 16-bit revision ID is located at 0x3FFFFC. These locations are read-only and cannot be erased or modified. Development tools, such as device programmers and debuggers, may be used to read the Device ID, Revision ID and Configuration bits. Refer to the “NVM - Nonvolatile Memory Module” section for more information on accessing these locations. 8.5 Register Definitions: Configuration Settings © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 42 PIC18F06/16Q41 Device Configuration 8.5.1 CONFIG1 Name:  Address:  CONFIG1 0x300000 Configuration Byte 1 Bit 7 Access Reset 6 R/W 1 5 RSTOSC[2:0] R/W 1 4 3 R/W 1 2 R/W 1 1 FEXTOSC[2:0] R/W 1 0 R/W 1 Bits 6:4 – RSTOSC[2:0] Power-Up Default Value for COSC This value is the Reset default value for COSC and selects the oscillator first used by user software. Refer to COSC operation. Value Description 111 EXTOSC operating per FEXTOSC bits 110 HFINTOSC with HFFRQ = 4 MHz and CDIV = 4:1. Resets COSC/NOSC to b'110'. 101 LFINTOSC 100 SOSC 011 Reserved 010 EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits 001 Reserved 000 HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1. Resets COSC/NOSC to b'110'. Bits 2:0 – FEXTOSC[2:0] External Oscillator Mode Selection Value Description 111 ECH (external clock) above 8 MHz 110 ECM (external clock) for 500 kHz to 8 MHz 101 ECL (external clock) below 500 kHz 100 Oscillator not enabled 011 Reserved (do not use) 010 HS (crystal oscillator) above 4 MHz 001 XT (crystal oscillator) above 500 kHz, below 4 MHz 000 LP (crystal oscillator) optimized for 32.768 kHz © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 43 PIC18F06/16Q41 Device Configuration 8.5.2 CONFIG2 Name:  Address:  CONFIG2 0x300001 Configuration Byte 2 Bit Access Reset 7 FCMENS R/W 1 6 FCMENP R/W 1 5 FCMEN R/W 1 4 3 CSWEN R/W 1 2 1 PR1WAY R/W 1 0 CLKOUTEN R/W 1 Bit 7 – FCMENS Fail-Safe Clock Monitor Enable - Secondary XTAL Enable Value Description 1 Fail-Safe Clock Monitor enabled; the timer will flag the FSCMS bit and OSFIF interrupt on SOSC failure 0 Fail-Safe Clock Monitor disabled Bit 6 – FCMENP Fail-Safe Clock Monitor Enable - Primary XTAL Enable Value Description 1 Fail-Safe Clock Monitor enabled; the timer will flag the FSCMP bit and OSFIF interrupt on EXTOSC failure 0 Fail-Safe Clock Monitor disabled Bit 5 – FCMEN Fail-Safe Clock Monitor Enable Value Description 1 Fail-Safe Clock Monitor enabled 0 Fail-Safe Clock Monitor disabled Bit 3 – CSWEN Clock Switch Enable Value Description 1 Writing to NOSC and NDIV is allowed 0 The NOSC and NDIV bits cannot be changed by user software Bit 1 – PR1WAY PRLOCKED One-Way Set Enable Value Description 1 The PRLOCKED bit can be cleared and set only once; Priority registers remain locked after one clear/set cycle 0 The PRLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence) Bit 0 – CLKOUTEN Clock Out Enable If FEXTOSC = HS, XT, LP, then this bit is ignored. Otherwise: Value Description 1 CLKOUT function is disabled; I/O function on OSC2 0 CLKOUT function is enabled; FOSC/4 clock appears at OSC2 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 44 PIC18F06/16Q41 Device Configuration 8.5.3 CONFIG3 Name:  Address:  CONFIG3 0x300002 Configuration Byte 3 Bit Access Reset 7 6 BOREN[1:0] R/W R/W 0 1 5 LPBOREN R/W 1 4 IVT1WAY R/W 1 3 MVECEN R/W 1 2 1 PWRTS[1:0] R/W R/W 1 1 0 MCLRE R/W 1 Bits 7:6 – BOREN[1:0] Brown-out Reset Enable When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit. Value Description 11 Brown-out Reset enabled, the SBOREN bit is ignored 10 Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored 01 Brown-out Reset enabled according to SBOREN 00 Brown-out Reset disabled Bit 5 – LPBOREN Low-Power BOR Enable Value Description 1 Low-Power Brown-out Reset is disabled 0 Low-Power Brown-out Reset is enabled Bit 4 – IVT1WAY IVTLOCK One-Way Set Enable Value Description 1 The IVTLOCK bit can be cleared and set only once; IVT registers remain locked after one clear/set cycle 0 The IVTLOCK bit can be set and cleared repeatedly (subject to the unlock sequence) Bit 3 – MVECEN Multivector Enable Value Description 1 Multivector is enabled; vector table used for interrupts 0 Legacy interrupt behavior Bits 2:1 – PWRTS[1:0] Power-up Timer Selection Value Description 11 PWRT is disabled 10 PWRT is set at 64 ms 01 PWRT is set at 16 ms 00 PWRT is set at 1 ms Bit 0 – MCLRE  Master Clear (MCLR) Enable Value Condition Description x If LVP = 1 RA3 pin function is MCLR 1 If LVP = 0 RA3 pin function is MCLR 0 If LVP = 0 RA3 pin function is a port-defined function © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 45 PIC18F06/16Q41 Device Configuration 8.5.4 CONFIG4 Name:  Address:  CONFIG4 0x300003 Configuration Byte 4 Bit Access Reset 7 XINST R/W 1 6 5 LVP R/W 1 4 STVREN R/W 1 3 PPS1WAY R/W 1 2 ZCD R/W 1 1 0 BORV[1:0] R/W 1 R/W 1 Bit 7 – XINST Extended Instruction Set Enable Value Description 1 Extended Instruction Set and Indexed Addressing mode disabled (Legacy mode) 0 Extended Instruction Set and Indexed Addressing mode enabled Bit 5 – LVP Low-Voltage Programming Enable The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode, or accidentally eliminating LVP mode from the Configuration state. Value Description 1 Low-Voltage Programming enabled. MCLR/VPP pin function is MCLR. The MCLRE Configuration bit is ignored. 0 HV on MCLR/VPP must be used for programming Bit 4 – STVREN Stack Overflow/Underflow Reset Enable Value Description 1 Stack Overflow or Underflow will cause a Reset 0 Stack Overflow or Underflow will not cause a Reset Bit 3 – PPS1WAY PPSLOCKED One-Way Set Enable Value Description 1 The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once PPSLOCK is set, all future changes to PPS registers are prevented 0 The PPSLOCKED bit can be set and cleared as needed (unlocking sequence is required) Bit 2 – ZCD ZCD Disable Value Description 1 ZCD disabled, ZCD can be enabled by setting the ZCDSEN bit of ZCDCON 0 ZCD always enabled, PMDx[ZCDMD] bit is ignored Bits 1:0 – BORV[1:0]  Brown-out Reset Voltage Selection(1) Value Description 11 Brown-out Reset Voltage (VBOR) set to 1.90V 10 Brown-out Reset Voltage (VBOR) set to 2.45V 01 Brown-out Reset Voltage (VBOR) set to 2.7V 00 Brown-out Reset Voltage (VBOR) set to 2.85V Note:  1. The higher voltage setting is recommended for an operation at or above 16 MHz. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 46 PIC18F06/16Q41 Device Configuration 8.5.5 CONFIG5 Name:  Address:  CONFIG5 0x300004 Configuration Byte 5 Bit 7 6 5 4 3 R/W 1 R/W 1 R/W 1 2 WDTCPS[4:0] R/W 1 WDTE[1:0] Access Reset R/W 1 1 0 R/W 1 R/W 1 Bits 6:5 – WDTE[1:0] WDT Operating Mode Value Description 11 WDT enabled regardless of Sleep; the SEN bit in WDTCON0 is ignored 10 WDT enabled while Sleep = 0, suspended when Sleep = 1; the SEN bit in WDTCON0 is ignored 01 WDT enabled/disabled by the SEN bit in WDTCON0 00 WDT disabled, the SEN bit in WDTCON0 is ignored Bits 4:0 – WDTCPS[4:0] WDT Period Select WDTCPS WDTCON0[WDTPS] at POR Typical Time-Out Value Divider Ratio (FIN = 31 kHz) 1:65536 216 2s Yes 11110 to 10011 1:32 25 1 ms No 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 1:8388608 1:4194304 1:2097152 1:1048576 1:524288 1:262144 1:131072 1:65536 1:32768 1:16384 223 222 221 220 219 218 217 216 215 214 256s 128s 64s 32s 16s 8s 4s 2s 1s 512 ms No No No No No No No No No No 1:8192 1:4096 1:2048 1:1024 1:512 1:256 1:128 1:64 1:32 213 212 211 210 29 28 27 26 25 256 ms 128 ms 64 ms 32 ms 16 ms 8 ms 4 ms 2 ms 1 ms No No No No No No No No No 11111 01011 11110 to 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 © 2020-2021 Microchip Technology Inc. and its subsidiaries Software Control of WDTPS? Preliminary Datasheet DS40002214E-page 47 PIC18F06/16Q41 Device Configuration 8.5.6 CONFIG6 Name:  Address:  CONFIG6 0x300005 Configuration Byte 6 Bit 7 6 5 Access Reset R/W 1 4 WDTCCS[2:0] R/W 1 3 2 R/W 1 R/W 1 1 WDTCWS[2:0] R/W 1 0 R/W 1 Bits 5:3 – WDTCCS[2:0] WDT Input Clock Selector Value Condition Description x WDTE = 00 These bits have no effect 111 WDTE ≠ 00 Software control 110 to WDTE ≠ 00 Reserved 011 010 WDTE ≠ 00 WDT reference clock is the SOSC 001 WDTE ≠ 00 WDT reference clock is the 31.25 kHz MFINTOSC 000 WDTE ≠ 00 WDT reference clock is the 31.0 kHz LFINTOSC Bits 2:0 – WDTCWS[2:0] WDT Window Select WDTCON1[WINDOW] at POR WDTCWS 111 110 101 100 011 010 001 000 Value Window Delay Percent of Time Window Opening Percent of Time 111 110 101 100 011 010 001 000 n/a n/a 25 37.5 50 62.5 75 87.5 100 100 75 62.5 50 37.5 25 12.5 © 2020-2021 Microchip Technology Inc. and its subsidiaries Software Control of WINDOW Keyed Access Required? Yes No No Yes Preliminary Datasheet DS40002214E-page 48 PIC18F06/16Q41 Device Configuration 8.5.7 CONFIG7 Name:  Address:  CONFIG7 0x300006 Configuration Byte 7 Bit 7 6 5 DEBUG R/W 1 Access Reset 4 SAFEN R/W 1 3 BBEN R/W 1 2 1 BBSIZE[2:0] R/W 1 R/W 1 0 R/W 1 Bit 5 – DEBUG Debugger Enable Value Description 1 Background debugger disabled 0 Background debugger enabled Bit 4 – SAFEN  Storage Area Flash (SAF) Enable(1) Value Description 1 SAF is disabled 0 SAF is enabled Bit 3 – BBEN  Boot Block Enable(1) Value Description 1 Boot Block is disabled 0 Boot Block is enabled Bits 2:0 – BBSIZE[2:0]  Boot Block Size Selection(2) Table 8-1. Boot Block Size BBEN BBSIZE End Address of Boot Block 1 0 0 0 0 0 0 0 0 xxx 111 110 101 100 011 010 001 000 – 00 03FFh 00 07FFh 00 0FFFh 00 1FFFh 00 3FFFh 00 7FFFh 00 FFFFh 01 FFFFh Boot Block Size (words) PIC18Fx4Q41 PIC18Fx5Q41 PIC18Fx6Q41 – 512 1024 2048 4096 – 8192 – 16384 – – Notes:  1. Once protection is enabled through ICSP™ or a self-write, it can only be reset through a Bulk Erase. 2. BBSIZE[2:0] bits can only be changed when BBEN = 1. Once BBEN = 0, BBSIZE[2:0] can only be changed through a Bulk Erase. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 49 PIC18F06/16Q41 Device Configuration 8.5.8 CONFIG8 Name:  Address:  CONFIG8 0x300007 Configuration Byte 8 Bit Access Reset 7 WRTAPP R/W 1 6 5 4 3 WRTSAF R/W 1 2 WRTD R/W 1 1 WRTC R/W 1 0 WRTB R/W 1 Bit 7 – WRTAPP  Application Block Write Protection(1) Value Description 1 Application Block is not write-protected 0 Application Block is write-protected Bit 3 – WRTSAF  Storage Area Flash (SAF) Write Protection(1,2) Value Description 1 SAF is not write-protected 0 SAF is write-protected Bit 2 – WRTD  Data EEPROM Write Protection(1) Value Description 1 Data EEPROM is not write-protected 0 Data EEPROM is write-protected Bit 1 – WRTC  Configuration Register Write Protection(1) Value Description 1 Configuration registers are not write-protected 0 Configuration registers are write-protected Bit 0 – WRTB  Boot Block Write Protection(1,3) Value Description 1 Boot Block is not write-protected 0 Boot Block is write-protected Notes:  1. Once protection is enabled through ICSP™ or a self-write, it can only be reset through a Bulk Erase. 2. Applicable only if SAFEN = 0. 3. Applicable only if BBEN = 0. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 50 PIC18F06/16Q41 Device Configuration 8.5.9 CONFIG9 Name:  Address:  CONFIG9 0x300008 Configuration Byte 9 Bit 7 6 5 4 3 2 Access Reset 1 0 CP R/W 1 Bit 0 – CP  User Program Flash Memory and Data EEPROM Code Protection Value Description 1 User Program Flash Memory and Data EEPROM code protection are disabled 0 User Program Flash Memory and Data EEPROM code protection are enabled © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 51 PIC18F06/16Q41 Device Configuration 8.6 Address 0x00 ... 0x2FFFFF 0x300000 0x300001 0x300002 0x300003 0x300004 0x300005 0x300006 0x300007 0x300008 8.7 Register Summary - Configuration Settings Name Bit Pos. 7 6 5 4 3 IVT1WAY STVREN CSWEN MVECEN PPS1WAY 2 1 0 Reserved CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 CONFIG7 CONFIG8 CONFIG9 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 RSTOSC[2:0] FCMENS FCMENP FCMEN BOREN[1:0] LPBOREN XINST LVP WDTE[1:0] DEBUG WDTCCS[2:0] SAFEN WRTAPP BBEN WRTSAF FEXTOSC[2:0] PR1WAY CLKOUTEN PWRTS[1:0] MCLRE ZCD BORV[1:0] WDTCPS[4:0] WDTCWS[2:0] BBSIZE[2:0] WRTD WRTC WRTB CP Register Definitions: Device ID and Revision ID © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 52 PIC18F06/16Q41 Device Configuration 8.7.1 Device ID Name:  Address:  DEVICEID 0x3FFFFE Device ID Register Bit 15 14 13 12 11 10 9 8 R q R q R q R q 3 2 1 0 R q R q R q R q DEV[15:8] Access Reset R q R q R q R q Bit 7 6 5 4 DEV[7:0] Access Reset R q R q R q R q Bits 15:0 – DEV[15:0] Device ID Device Device ID PIC18F04Q41 PIC18F05Q41 PIC18F06Q41 PIC18F14Q41 PIC18F15Q41 PIC18F16Q41 7540h 7500h 7580h 7520h 74E0h 7560h © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 53 PIC18F06/16Q41 Device Configuration 8.7.2 Revision ID Name:  Address:  REVISIONID 0x3FFFFC Revision ID Register Bit 15 14 13 12 11 10 9 8 R q R q R q 2 1 0 R q R q R q 1010[3:0] Access Reset R 1 Bit 7 MJRREV[5:2] R 0 R 1 R 0 R q 6 5 4 3 MJRREV[1:0] Access Reset R q MNRREV[5:0] R q R q R q R q Bits 15:12 – 1010[3:0]  Read as ‘b1010 These bits are fixed with value ‘b1010 for all devices in this family. Bits 11:6 – MJRREV[5:0] Major Revision ID These bits are used to identify a major revision (A0, B0, C0, etc.). Revision A = ‘b00 0000 Revision B = ‘b00 0001 Bits 5:0 – MNRREV[5:0] Minor Revision ID These bits are used to identify a minor revision. Revision A0 = ‘b00 0000 Revision B0 = ‘b00 0000 Revision B1 = ‘b00 0001 Tip:  For example, the REVISIONID register value for revision B1 will be 0xA041. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 54 PIC18F06/16Q41 Device Configuration 8.8 Register Summary - DEVID/REVID Address Name 0x00 ... 0x3FFFFB Reserved 0x3FFFFC REVISIONID 0x3FFFFE Bit Pos. DEVICEID 7:0 15:8 7:0 15:8 7 6 4 3 MJRREV[1:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries 5 2 1 0 MNRREV[5:0] 1010[3:0] MJRREV[5:2] DEV[7:0] DEV[15:8] Preliminary Datasheet DS40002214E-page 55 PIC18F06/16Q41 Memory Organization 9. Memory Organization There are three types of memory in PIC18 microcontroller devices: • • • Program Memory Data RAM Data EEPROM In Harvard architecture devices, the data and program memories use separate buses that allow for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers. Additional detailed information on the operation of the Program Flash Memory and data EEPROM memory is provided in the “NVM - Nonvolatile Memory Module” section. 9.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit Program Counter, which is capable of addressing a 2 Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2 Mbyte address will return all ‘0’s (a NOP instruction). Refer to the following tables for device memory maps and code protection Configuration bits associated with the various sections of PFM. The Reset vector address is at 000000h. The PIC18-Q41 devices feature a vectored interrupt controller with a dedicated interrupt vector table stored in the program memory. Refer to the “VIC - Vectored Interrupt Controller Module” chapter for more details. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 56 PIC18F06/16Q41 Memory Organization Figure 9-1. Program and Data Memory Map Rev. 40-000101E 4/20/2017 Device Address PIC18Fx4Q41 00 0000h to 00 3FFFh PIC18Fx5Q41 Program Flash Memory (8KW)(1) 00 4000h to 00 7FFFh 00 8000h to 00 FFFFh Not Present(2) 01 0000h to 01 FFFFh Program Flash Memory (16 KW)(1) Not Present(2) 02 0000h to 1F FFFFh 20 0000h to 20 003Fh 20 0040h to 2B FFFFh 2C 0000h to 2C 00FFh 2C 0100h to 2F FFFFh 30 0000h to 30 0009h 30 000Ah to 37 FFFFh 38 0000h to 38 01FFh 38 0200h to 3B FFFFh 3C 0000h to 3C 0009h PIC18Fx6Q41 Program Flash Memory (32 KW)(1) Not Present(2) User IDs (32 Words)(3) Reserved Device Information Area (DIA)(3,5) Reserved Configuration Bytes(3) Reserved Data EEPROM (512 Bytes) Reserved Device Configuration Information(3,4,5) 3C 000Ah to 3F FFFBh Reserved 3F FFFCh to 3F FFFDh Revision ID (1 Word)(3,4,5) 3F FFFEh to 3F FFFFh Device ID (1 Word)(3,4,5) Notes: 1. Storage Area Flash is implemented as the last 128 Words of User Flash, if enabled. 2. The addresses do not roll over. The region is read as ‘0’. 3. Not code-protected. 4. Hard-coded in silicon. 5. This region cannot be written by the user and it is not affected by a Bulk Erase. 9.1.1 Memory Access Partition In the PIC18-Q41 devices, the program memory can be further partitioned into the following sub-blocks: • Application block • Boot block • Storage Area Flash (SAF) block Refer to the Program Flash Memory Partition table for more details. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 57 PIC18F06/16Q41 Memory Organization 9.1.1.1 Application Block Application block is where the user’s firmware resides by default. Default settings of the Configuration bits (BBEN = 1 and SAFEN = 1) assign all memory in the program Flash memory area to the application block. The WRTAPP Configuration bit is used to write-protect the application block. 9.1.1.2 Boot Block Boot block is an area in program memory that is ideal for storing bootloader code. Code placed in this area can be executed by the CPU. The boot block can be write-protected, independent of the main application block. The Boot Block is enabled by the BBEN Configuration bit and size is based on the value of the BBSIZE Configuration bits. The WRTB Configuration bit is used to write-protect the Boot Block. 9.1.1.3 Storage Area Flash Storage Area Flash (SAF) is the area in program memory that can be used as data storage. SAF is enabled by the SAFEN Configuration bit. If enabled, the code placed in this area cannot be executed by the CPU. The SAF block is placed at the end of memory and spans 128 Words. The WRTSAF Configuration bit is used to write-protect the Storage Area Flash. Important:  If write-protected locations are written to, memory is not changed and the WRERR bit is set. Table 9-1. Program Flash Memory Partition Partition(3) Region Address BBEN = 1 SAFEN = 1 BBEN = 1 SAFEN = 0 00 0000h .... Last Boot Block Memory Address Last Boot Block Memory Address(1) + 1 BBEN = 0 SAFEN = 1 BBEN = 0 SAFEN = 0 Boot Block Boot Block Application Block .... Program Flash Memory Application Block Last Program Application Block Memory Address(2) - 100h Last Program Memory Address(2) FEh(4) .... Application Block Storage Area Flash Block Storage Area Flash Block Last Program Memory Address(2) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 58 PIC18F06/16Q41 Memory Organization Notes:  1. Last Boot Block address is based on BBSIZE bits. Refer to the “Device Configuration” chapter for more details. 2. For Last Program Memory address refer the table above. 3. Refer to the “Device Configuration” chapter for BBEN and SAFEN bit definitions. 4. Storage Area Flash is implemented as the last 128 Words of user Flash memory. 9.1.2 Program Counter The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC[15:8] bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC[20:16] bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the Program Counter by any operation that writes PCL. Similarly, the upper two bytes of the Program Counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see the Computed GOTO section). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of ‘0’. The PC increments by two to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the Program Counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the Program Counter. 9.1.3 Return Address Stack The return address stack allows any combination of up to 127 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack (TOS) Special File registers. Data can also be pushed to, or popped from the stack, using these registers. A CALL type instruction causes a push onto the stack; the Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack; the contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to 0x00 after all Resets. 9.1.3.1 Top-of-Stack Access Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (see Figure 9-2). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the Global Interrupt Enable (GIE) bits while accessing the stack to prevent inadvertent stack corruption. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 59 PIC18F06/16Q41 Memory Organization Figure 9-2. Return Address Stack and Associated Registers Return Address Stack 1111111 1111110 1111101 STKPTR 0000010 Top-of-Stack Registers TOSU 00h TOSH 1Ah TOSL 34h 0000011 Top-of-Stack 001A34h 0000010 000D58h 0000001 0000000 9.1.3.2 Return Stack Pointer The STKPTR register contains the Stack Pointer value. The STKOVF (Stack Overflow) Status bit and the STKUNF (Stack Underflow) Status bit can be accessed using the PCON0 register. The value of the Stack Pointer can be zero through 127. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. After the PC is pushed onto the stack 128 times (without popping any values off the stack), the STKOVF bit is set. The STKOVF bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. If STVREN is set (default), a Reset will be generated and a Stack Overflow will be indicated by the STKOVF bit. This includes CALL and CALLW instructions, as well as stacking the return address during an interrupt response. The STKOVF bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKOVF bit will be set on the 128th push and the Stack Pointer will remain at 127 but no Reset will occur. Any additional pushes will overwrite the 127st push but the STKPTR will remain unchanged. Setting STKOVF = 1 in software will change the bit, but will not generate a Reset. The STKUNF bit is set when a stack pop returns a value of ‘0’. The STKUNF bit is cleared by software or by POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. If STVREN is set (default) and the stack has been popped enough times to unload the stack, the next pop will return a value of ‘0’ to the PC, it will set the STKUNF bit and a Reset will be generated. This condition can be generated by the RETURN, RETLW and RETFIE instructions. If STVREN is cleared, the STKUNF bit will be set, but no Reset will occur. Important:  Returning a value of ‘0’ to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected. 9.1.3.3 PUSH and POP Instructions Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 60 PIC18F06/16Q41 Memory Organization 9.1.3.4 Fast Register Stack There are three levels of fast stack registers available - one for CALL type instructions and two for interrupts. A fast register stack is provided for the STATUS, WREG and BSR registers, to provide a “fast return” option for interrupts. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the stack registers. The values in the registers are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return from the interrupt. Refer to the “Call Shadow Register” section for interrupt call shadow registers. The following example shows a source code example that uses the Fast Register Stack during a subroutine call and return. Example 9-1. Fast Register Stack Code Example CALL SUB1, FAST ;STATUS, WREG, BSR SAVED IN FAST REGISTER STACK • • SUB1: • • RETURN, FAST ;RESTORE VALUES SAVED IN FAST REGISTER STACK 9.1.4 Look-up Tables in Program Memory There may be programming situations that require the creation of data structures, or Look-up Tables, in program memory. For PIC18 devices, Look-up Tables can be implemented in two ways: 9.1.4.1 • Computed GOTO • Table reads Computed GOTO A computed GOTO is accomplished by adding an offset to the Program Counter. An example is shown in the following code example. A Look-up Table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value ‘nn’ to the calling function. The offset value (in WREG) specifies the number of bytes that the Program Counter will advance and must be multiples of two (LSb = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. Example 9-2. Computed GOTO Using an Offset Value RLNCF CALL ORG TABLE: ADDWF RETLW RETLW RETLW . . . 9.1.4.2 OFFSET, W TABLE ; W must be an even number, Max OFFSET = 127 nn00h ; 00 in LSByte ensures no addition overflow PCL A B C ; ; ; ; Add OFFSET to program counter Value @ OFFSET=0 Value @ OFFSET=1 Value @ OFFSET=2 Program Flash Memory Access A more compact method of storing data in program memory allows two bytes of data to be stored in each instruction location. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 61 PIC18F06/16Q41 Memory Organization Look-up Table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in the “Table Read Operations” and “Table Write Operations” sections in the “NVM - Nonvolatile Memory Module” chapter. 9.2 Device Information Area The Device Information Area (DIA) is a dedicated region in the program memory space. The DIA contains the calibration data for the internal temperature indicator module, the Microchip Unique Identifier words, and the Fixed Voltage Reference voltage readings measured in mV. The complete DIA table is shown below, followed by a description of each region and its functionality. The data is mapped from 2C0000h to 2C003Fh. These locations are read-only and cannot be erased or modified. The data is programmed into the device during manufacturing. Table 9-2. Device Information Area Address Range Name of Region Standard Device Information MUI0 MUI1 MUI2 MUI3 2C0000h-2C0011h MUI4 Microchip Unique Identifier (9 Words) MUI5 MUI6 MUI7 MUI8 2C0012h-2C0013h MUI9 Reserved (1 Word) EUI0 EUI1 EUI2 2C0014h-2C0023h EUI3 EUI4 Optional External Unique Identifier (8 Words) EUI5 EUI6 EUI7 2C0024h-2C0025h TSLR1(1) 2C0026h-2C0027h TSLR2(1) × 256 Gain = 0.1C count (low range setting) 2C0028h-2C0029h TSLR3(1) Offset (low range setting) 2C002Ah-2C002Bh TSHR1(2) 2C002Ch-2C002Dh TSHR2(2) × 256 Gain = 0.1C count (high range setting) © 2020-2021 Microchip Technology Inc. and its subsidiaries Temperature indicator ADC reading at 90°C (low range setting) Temperature indicator ADC reading at 90°C (high range setting) Preliminary Datasheet DS40002214E-page 62 PIC18F06/16Q41 Memory Organization ...........continued Address Range Name of Region 2C002Eh-2C002Fh TSHR3(2) Offset (high range setting) 2C0030h-2C0031h FVRA1X ADC FVR1 Output voltage for 1x setting (in mV) 2C0032h-2C0033h FVRA2X ADC FVR1 Output Voltage for 2x setting (in mV) 2C0034h-2C0035h FVRA4X ADC FVR1 Output Voltage for 4x setting (in mV) 2C0036h-2C0037h FVRC1X Comparator FVR2 output voltage for 1x setting (in mV) 2C0038h-2C0039h FVRC2X Comparator FVR2 output voltage for 2x setting (in mV) 2C003Ah-2C003Bh FVRC4X Comparator FVR2 output voltage for 4x setting (in mV) 2C003Ch-2C003Fh Standard Device Information Unassigned (2 Words) Notes:  1. TSLR: Address 2C0024h-2C0029h store the measurements for the low range setting of the temperature sensor at VDD = 3V, VREF+ = 2.048V from FVR1. 2. TSHR: Address 2C002Ah-2C002Fh store the measurements for the high range setting of the temperature sensor at VDD = 3V, VREF+ = 2.048V from FVR1. 9.2.1 Microchip Unique Identifier (MUI) This family of devices is individually encoded during final manufacturing with a Microchip Unique Identifier (MUI). The MUI cannot be user-erased. This feature allows for manufacturing traceability of Microchip Technology devices in applications where this is required. It may also be used by the application manufacturer for a number of functions that require unverified unique identification, such as: • Tracking the device • Unique serial number The MUI is stored in read-only locations, located between 2C0000h to 2C0013h in the DIA space. The DIA table lists the addresses of the identifier words. Important:  For applications that require verified unique identification, contact the Microchip Technology sales office to create a Serialized Quick Turn Programming option. 9.2.2 External Unique Identifier (EUI) The EUI data is stored at locations 2C0014h-2C0023h in the program memory region. This region is an optional space for placing application specific information. The data is coded per customer requirements during manufacturing. The EUI cannot be erased by a Bulk Erase command. Important:  Data is stored in this address range on receiving a request from the customer. The customer may contact the local sales representative or Field Applications Engineer, and provide them the unique identifier information that is required to be stored in this region. 9.2.3 Standard Parameters for the Temperature Sensor The purpose of the temperature indicator module is to provide a temperature-dependent voltage that can be measured by an analog module. The DIA table contains standard parameters for the temperature sensor for low and high range. The values are measured during test and are unique to each device. The calibration data can be used to plot the approximate sensor output voltage, VTSENSE vs. Temperature curve. The “Temperature Indicator Module” chapter explains the operation of the Temperature Indicator module and defines terms such as the low range and high range settings of the sensor. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 63 PIC18F06/16Q41 Memory Organization 9.2.4 Fixed Voltage Reference Data The DIA stores measured FVR voltages for this device in mV for different buffer settings of 1x, 2x or 4x at program memory locations. For more information on the FVR, refer to the “FVR - Fixed Voltage Reference” chapter. 9.3 Device Configuration Information The Device Configuration Information (DCI) is a dedicated region in the program memory mapped from 3C0000h to 3C0009h. The data stored in these location is read-only and cannot be erased. Refer to the table below for the complete DCI table address and description. The DCI holds information about the device, which is useful for programming and Bootloader applications. The erase size is the minimum erasable unit in the PFM, expressed as rows. The total device Flash memory capacity is (Erase size * Number of user-erasable pages). Table 9-3. Device Configuration Information for PIC18FxxQ41 Devices Address Name Description 3C0000h-3C0001h ERSIZ 3C0002h-3C0003h Value Units PIC18F04/14Q41 PIC18F05/15Q41 PIC18F06/16Q41 Erase page size 128 128 128 Words WLSIZ Number of write latches per row 0 0 0 Words 3C0004h-3C0005h URSIZ Number of usererasable pages 64 128 256 Pages 3C0006h-3C0007h EESIZ Data EEPROM memory size 512 512 512 Bytes 3C0008h-3C0009h PCNT Pin count 14/20 14/20 14/20 Pins 9.4 Data Memory Organization Important:  The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See the PIC18 Instruction Execution and the Extended Instruction Set section for more information. The data memory in PIC18 devices is implemented as static RAM. The memory space is divided into as many as 64 banks with 256 bytes each. Figure 9-3 shows the data memory organization for all devices in the device family. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’s application. Any read of an unimplemented location will read as ‘0’. The value in the Bank Select Register (BSR) determines which bank is being accessed. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a virtual 256-byte memory space that provides fast access to SFRs and the top half of GPR Bank 5 without using the Bank Select Register. The Access Bank section provides a detailed description of the Access RAM. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 64 PIC18F06/16Q41 Memory Organization Figure 9-3. Data Memory Map PIC18F BanK BSR addr[13:8] 0 'b00 0000 0x00-0x5F 1 'b00 0001 0x00-0xFF 2 'b00 0010 0x00-0xFF 3 'b00 0011 0x00-0xFF 'b00 0100 0x00-0x5F Virtual Access Bank 'b00 0100 0x60-0xFF Access RAM 0x00-0x5F 'b00 0101 0x00-0x5F Fast SFR 0x60-0xFF 'b00 0101 0x60-0xFF 6 'b00 0110 0x00-0xFF 7 'b00 0111 0x00-0xFF 8 'b00 1000 0x00-0xFF 4 5 addr[7:0] x4Q41 x5Q41 x6Q41 9 'b00 1001 0x00-0xFF 10 'b00 1010 0x00-0xFF 11 'b00 1011 0x00-0xFF 12 'b00 1100 0x00-0xFF 13 'b00 1101 0x00-0xFF 14 'b00 1110 0x00-0xFF 15 0x00-0xFF 16 'b00 1111 'b01 0000 17 'b01 0001 0x00-0xFF 18 'b01 0010 0x00-0xFF 19 'b01 0011 0x00-0xFF 20 'b01 0100 0x00-0xFF 21 'b01 0101 0x00-0xFF 22 'b01 0110 0x00-0xFF 23 'b01 0111 0x00-0xFF 24 'b01 1000 0x00-0xFF 25 'b01 1001 0x00-0xFF 26 'b01 1010 0x00-0xFF 27 'b01 1011 0x00-0xFF 28 'b01 1100 0x00-0xFF 29 'b01 1101 0x00-0xFF 30 'b01 1110 0x00-0xFF 31 'b01 1111 0x00-0xFF 32 'b10 0000 0x00-0xFF 33 'b10 0001 0x00-0xFF 34 'b10 0010 0x00-0xFF 35 'b10 0011 0x00-0xFF 36 'b10 0100 0x00-0xFF 37 'b10 0101 0x00-0xFF GPR 38 'b10 0110 0x00-0xFF SFR 0x00-0xFF to - - Buffer RAM 63 'b11 1111 0x00-0xFF Unimplemented © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 65 PIC18F06/16Q41 Memory Organization 9.4.1 Bank Select Register To rapidly access the RAM space in PIC18 devices, the memory is split using the banking scheme. This divides the memory space into contiguous banks of 256 bytes each. Depending on the instruction, each location can be addressed directly by its full address, or an 8-bit low-order address and a bank pointer. Most instructions in the PIC18 instruction set make use of the bank pointer known as the Bank Select Register (BSR). This SFR holds the Most Significant bits of a location’s address; the instruction itself includes the eight Least Significant bits. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory being accessed; the eight bits in the instruction show the location in the bank and can be thought of as an offset from the bank’s lower boundary. The relationship between the BSR’s value and the bank division in data memory is shown in Figure 9-4. When writing the firmware in assembly, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. When using the C compiler to write the firmware, the BSR is tracked and maintained by the compiler. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’. Refer Figure 9-3 for a list of implemented banks. Figure 9-4. Use of the Bank Select Register (Direct Addressing) 7 0 0 0 0 0 Rev. 30-000108B 02/28/2019 Data Memory BSR(1) 0 0 1 0000h 0 0100h Bank Select 0200h Bank 0 Bank 1 Bank 2 0300h 00h FFh 00h From Opcode 7 1 1 1 1 1 1 0 1 1 FFh 00h FFh Bank 3 through Bank 61 3E00h Bank 62 3F00h 3FFFh Note 1: 9.4.2 Bank 63 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR value) to the registers of the Access Bank. Access Bank While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with a virtual Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 96 bytes of memory in Bank 5 (0500h-055Fh) and the last 160 bytes of memory in Bank 4 (0460h-04FFh). The upper half is known as the “Access RAM” and is composed of GPRs. The lower half is where the device’s SFRs are mapped. These two areas are mapped contiguously as the virtual Access Bank and can be addressed in a linear fashion by an 8-bit address (see the Data Memory Map section). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 66 PIC18F06/16Q41 Memory Organization The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, the instruction ignores the BSR and uses the Access Bank address map. Using this “forced” addressing allows the instruction to operate on a data address in a single cycle, without updating the BSR first. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in the Mapping the Access Bank in Indexed Liberal Offset Mode section. 9.5 Data Addressing Modes Important:  The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See the Data Memory and the Extended Instruction Set section for more information. Information in the data memory space can be addressed in several ways. For most instructions, the Addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The Addressing modes are: • • • • Inherent Literal Direct Indirect An additional Addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in the Indexed Addressing with Literal Offset section. 9.5.1 Inherent and Literal Addressing Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device or they operate implicitly on one register. This Addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a program memory address. 9.5.2 Direct Addressing Direct Addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. In the core PIC18 instruction set, bit-oriented and byte-oriented instructions use some version of Direct Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (see the Data Memory Organization section) or a location in the Access Bank (see the Access Bank section) as the data source for the instruction. The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (see the Bank Select Register section) are used with the address to determine the complete 12-bit address of the register. When ‘a’ is ‘0’, the address is interpreted as being a register in the Access Bank. The destination of the operation’s results is determined by the destination bit ‘d’. When ‘d’ is ‘1’, the results are stored back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results are stored in the W register. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 67 PIC18F06/16Q41 Memory Organization Instructions without the ‘d’ argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register. 9.5.3 Indirect Addressing Indirect Addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations which are to be read or written. Since the FSRs are themselves located in RAM as Special File Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using loops, such as the following example of clearing an entire RAM bank. Example 9-3. How to Clear RAM (Bank 1) Using Indirect Addressing LFSR FSR0,100h ; Set FSR0 to beginning of Bank1 CLRF POSTINC0 ; Clear location in Bank1 then increment FSR0 BTFSS BRA FSR0H,1 NEXT ; Has high FSR0 byte incremented to next bank? ; NO, clear next byte in Bank1 NEXT: CONTINUE: 9.5.3.1 ; YES, continue FSR Registers and the INDF Operand At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represent a pair of 8-bit registers, FSRnH and FSRnL. Each FSR pair holds the full address of the RAM location. The FSR value can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Indirect Addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can be thought of as “virtual” registers; they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target. The INDF operand is just a convenient way of using the pointer. Because Indirect Addressing uses a full address, the FSR value can target any location in any bank regardless of the BSR value. However, the Access RAM bit must be cleared to zero to ensure that the INDF register in Access space is the object of the operation instead of a register in one of the other banks. The assembler default value for the Access RAM bit is zero when targeting any of the indirect operands. 9.5.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be directly read or written. Accessing these registers actually accesses the location to which the associated FSR register pair points, and also performs a specific action on the FSR value. They are: • • • • POSTDEC: Accesses the location to which the FSR points, then automatically decrements the FSR by 1 afterwards POSTINC: Accesses the location to which the FSR points, then automatically increments the FSR by 1 afterwards PREINC: Automatically increments the FSR by one, then uses the location to which the FSR points in the operation PLUSW: Adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the location to which the result points in the operation. In this context, accessing an INDF register uses the value in the associated FSR register without changing it. Similarly, accessing a PLUSW register gives the FSR value an offset in the W register; however, neither W nor the FSR is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR register. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 68 PIC18F06/16Q41 Memory Organization Figure 9-5. Indirect Addressing Data Memory 0000h ADDWF, INDF1, 0 Using an instruction with one of the indirect addressing registers as the operand.... 0100h 0200h ...uses the 14-bit address stored in the FSR pair associated with that register.... FSR1H:FSR1L 7 0 x x 11 1 1 1 0 7 Bank 1 Bank 2 0300h 00h FFh 00h FFh 00h FFh 0 Bank 3 through Bank 61 1 1 0 0 1 1 0 0 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains 3ECCh. This means the contents of location 3ECCh will be added to that of the W register and stored back in 3ECCh. Bank 0 Rev. 30-000109A 4/18/2017 3E00h Bank 62 3F00h 3FFFh Bank 63 00h FFh 00h FFh Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In  some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 9.5.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains the address of INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to either the INDF2 or POSTDEC2 register will write the same value to the FSR2H:FSR2L. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users need to proceed cautiously when working on these registers, particularly if their code uses Indirect Addressing. Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users need to exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 9.6 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different; this is due to the introduction of a new Addressing mode for the data memory space. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 69 PIC18F06/16Q41 Memory Organization Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. 9.6.1 Indexed Addressing with Literal Offset Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair within Access RAM. Under the proper conditions, instructions that use the Access Bank – that is, most bit-oriented and byte-oriented instructions – can invoke a form of Indexed Addressing using an offset specified in the instruction. This special Addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. When using the extended instruction set, this Addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0) and • The file address argument is less than or equal to 5Fh. Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing), or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer, specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. 9.6.2 Instructions Affected by Indexed Literal Offset Mode Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the Access Bank (Access RAM bit is ‘1’), or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible Addressing modes when the extended instruction set is enabled is shown in the following figure. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode need to note the changes to assembler syntax for this mode. This is described in more detail in the “Extended Instruction Syntax” section. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 70 PIC18F06/16Q41 Memory Organization Figure 9-6. Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When ‘a’ = 0 and f ≥ 60h The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations 460h to 4FFh (Bank4) of data memory. Locations below 60h are not available in this Addressing mode. 0000h Bank 0 - 3 0400h 0460h 04FFh Bank 4 00h Access SFRs 60h FFh Bank 5-63 Access RAM 3FFFh Data Memory When ‘a’ = 0 and f ≤ 5 Fh The instruction executes in Indexed Literal Offset mode. ‘f’ is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. 0000h Bank 0 - 3 0400h Bank 4 0460h 04FFh 0500h 0560h Access SFRs Access GPR Bank 5-63 FSR2H 3FFFh 9.6.3 FSR2L Data Memory ADDWF [k], d where ‘k’ is the same as ‘f’. The instruction executes in Direct mode (also known as Direct Long mode). ‘f’ is interpreted as a location in one of the 63 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. ffff ffff + Note that in this mode, the correct syntax is now: When ‘a’ = 1 (all values of f) 0010 01da 0000h Bank 0 - 3 0400h Bank 4 0460h 04FFh Access SFRs BSR 0000 1010 Bank 5-63 Bank 10 0010 01da ffff ffff 3FFFh Data Memory Mapping the Access Bank in Indexed Literal Offset Mode The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the top section of Bank 5, this mode maps the contents from a user defined “window” that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see the Access Bank section). An example of Access Bank remapping in this Addressing mode is shown in the following figure. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 71 PIC18F06/16Q41 Memory Organization Figure 9-7. Remapping the Access Bank with Indexed Literal Offset Addressing EXAMPLE: ADDWF, f, d, a FSR2H:FSR2L = 0x0A20 0000h Bank 0 - 3 0400h Bank 4 0460h Locations in the region from the FSR2 pointer (A20h) to the pointer plus 05Fh (A7Fh) are mapped to the Access RAM (000h-05Fh). Special File Registers at 460h through 4FFh are mapped to 60h through FFh, as usual. Bank 4 addresses below 5Fh can still be addressed by using the BSR. Access SFRs 0500h 00h Bank 10 Window Bank 5-9 60h SFRs 0A20h Bank 10 Window 0A7Fh Bank 10 FFh Access RAM Bank 11 - 63 3FFFh Data Memory Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. 9.6.4 PIC18 Instruction Execution and the Extended Instruction Set Enabling the extended instruction set adds additional commands to the existing PIC18 instruction set. These instructions are executed as described in the “Extended Instruction Set” section. 9.7 Register Definitions: Memory Organization © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 72 PIC18F06/16Q41 Memory Organization 9.7.1 PCL Name:  Address:  PCL 0x4F9 Low byte of the Program Counter Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 PCL[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – PCL[7:0] Provides direct read and write access to the Program Counter © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 73 PIC18F06/16Q41 Memory Organization 9.7.2 PCLAT Name:  Address:  PCLAT 0x4FA Program Counter Latches Holding register for bits [21:9] of the Program Counter (PC). Reads of the PCL register transfer the upper PC bits to the PCLAT register. Writes to PCL register transfer the PCLAT value to the PC. Bit 15 14 13 Access Reset Bit Access Reset 7 6 5 R/W 0 R/W 0 R/W 0 12 11 R/W 0 R/W 0 4 3 PCLATH[7:0] R/W R/W 0 0 10 PCLATU[4:0] R/W 0 9 8 R/W 0 R/W 0 2 1 0 R/W 0 R/W 0 R/W 0 Bits 12:8 – PCLATU[4:0] Upper PC Latch Register Holding register for Program Counter [21:17] Bits 7:0 – PCLATH[7:0] High PC Latch Register Holding register for Program Counter [16:8] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 74 PIC18F06/16Q41 Memory Organization 9.7.3 TOS Name:  Address:  TOS 0x4FD Top-of-Stack Register Contents of the stack pointed to by the STKPTR register. This is the value that will be loaded into the Program Counter upon a RETURN or RETFIE instruction. Bit 23 22 21 Access Reset Bit 15 14 13 20 19 R/W 0 12 17 16 R/W 0 18 TOS[20:16] R/W 0 R/W 0 R/W 0 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 TOS[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 TOS[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 20:0 – TOS[20:0] Top-of-Stack Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • TOSU: Accesses the upper byte TOS[20:16] • TOSH: Accesses the high byte TOS[15:8] • TOSL: Accesses the low byte TOS[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 75 PIC18F06/16Q41 Memory Organization 9.7.4 STKPTR Name:  Address:  STKPTR 0x4FC Stack Pointer Register Bit 7 Access Reset 6 5 4 R/W 0 R/W 0 R/W 0 3 STKPTR[6:0] R/W 0 2 1 0 R/W 0 R/W 0 R/W 0 Bits 6:0 – STKPTR[6:0] Stack Pointer Location © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 76 PIC18F06/16Q41 Memory Organization 9.7.5 WREG Name:  Address:  WREG 0x4E8 Working Data Register Bit 7 6 5 4 3 2 1 0 R/W x R/W x R/W x R/W x WREG[7:0] Access Reset R/W x R/W x R/W x R/W x Bits 7:0 – WREG[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 77 PIC18F06/16Q41 Memory Organization 9.7.6 INDF Name:  Address:  INDFx 0x4EF,0x4E7,0x4DF Indirect Data Register This is a virtual register. The GPR/SFR register addressed by the FSRx register is the target for all operations involving the INDFx register. Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 INDF[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – INDF[7:0] Indirect data pointed to by the FSRx register © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 78 PIC18F06/16Q41 Memory Organization 9.7.7 POSTDEC Name:  Address:  POSTDECx 0x4ED,0x4E5,0x4DD Indirect Data Register with post decrement This is a virtual register. The GPR/SFR register addressed by the FSRx register is the target for all operations involving the POSTDECx register. FSRx is decrememted after the read or write operation. Bit Access Reset 7 6 5 R/W 0 R/W 0 R/W 0 4 3 POSTDEC[7:0] R/W R/W 0 0 2 1 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – POSTDEC[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 79 PIC18F06/16Q41 Memory Organization 9.7.8 POSTINC Name:  Address:  POSTINCx 0x4EE,0x4E6,0x4DE Indirect Data Register with post increment This is a virtual register. The GPR/SFR register addressed by the FSRx register is the target for all operations involving the POSTINCx register. FSRx is incremented after the read or write operation. Bit Access Reset 7 6 5 R/W 0 R/W 0 R/W 0 4 3 POSTINC[7:0] R/W R/W 0 0 2 1 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – POSTINC[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 80 PIC18F06/16Q41 Memory Organization 9.7.9 PREINC Name:  Address:  PREINCx 0x4EC,0x4E4,0x4DC Indirect Data Register with pre-increment This is a virtual register. The GPR/SFR register addressed by the FSRx register plus 1 is the target for all operations involving the PREINCx register. FSRx is incremented before the read or write operation. Bit Access Reset 7 6 5 R/W 0 R/W 0 R/W 0 4 3 PREINC[7:0] R/W R/W 0 0 2 1 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – PREINC[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 81 PIC18F06/16Q41 Memory Organization 9.7.10 PLUSW Name:  Address:  PLUSWx 0x4EB,0x4E3,0x4DB Indirect Data Register with WREG offset This is a virtual register. The GPR/SFR register addressed by the sum of the FSRx register plus the signed value of the W register is the target for all operations involving the PLUSWx register. Bit Access Reset 7 6 5 R/W 0 R/W 0 R/W 0 4 3 PLUSW[7:0] R/W R/W 0 0 2 1 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – PLUSW[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 82 PIC18F06/16Q41 Memory Organization 9.7.11 FSR Name:  Address:  FSRx 0x4E9,0x4E1,0x4D9 Indirect Address Register The FSR value is the address of the data to which the INDF register points. Bit 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 FSRH[5:0] Access Reset Bit 7 R/W 0 R/W 0 5 4 6 FSRL[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 13:8 – FSRH[5:0] Most Significant address of INDF data Bits 7:0 – FSRL[7:0] Least Significant address of INDF data © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 83 PIC18F06/16Q41 Memory Organization 9.7.12 BSR Name:  Address:  BSR 0x4E0 Bank Select Register The BSR indicates the data memory bank of the GPR address. Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 BSR[5:0] Access Reset R/W 0 R/W 0 R/W 0 Bits 5:0 – BSR[5:0] Most Significant bits of the data memory address © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 84 PIC18F06/16Q41 Memory Organization 9.8 Register Summary - Memory Organization Address Name 0x00 ... 0x04D8 Reserved 0x04D9 FSR2 0x04DB 0x04DC 0x04DD 0x04DE 0x04DF 0x04E0 PLUSW2 PREINC2 POSTDEC2 POSTINC2 INDF2 BSR 0x04E1 FSR1 0x04E3 0x04E4 0x04E5 0x04E6 0x04E7 0x04E8 PLUSW1 PREINC1 POSTDEC1 POSTINC1 INDF1 WREG 0x04E9 FSR0 0x04EB 0x04EC 0x04ED 0x04EE 0x04EF 0x04F0 ... 0x04F8 0x04F9 PLUSW0 PREINC0 POSTDEC0 POSTINC0 INDF0 0x04FA PCLAT 0x04FC STKPTR 0x04FD TOS Bit Pos. 7 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 6 5 4 3 2 1 0 FSRL[7:0] FSRH[5:0] PLUSW[7:0] PREINC[7:0] POSTDEC[7:0] POSTINC[7:0] INDF[7:0] BSR[5:0] FSRL[7:0] FSRH[5:0] PLUSW[7:0] PREINC[7:0] POSTDEC[7:0] POSTINC[7:0] INDF[7:0] WREG[7:0] FSRL[7:0] FSRH[5:0] PLUSW[7:0] PREINC[7:0] POSTDEC[7:0] POSTINC[7:0] INDF[7:0] Reserved PCL 7:0 7:0 15:8 7:0 7:0 15:8 23:16 © 2020-2021 Microchip Technology Inc. and its subsidiaries PCL[7:0] PCLATH[7:0] PCLATU[4:0] STKPTR[6:0] TOS[7:0] TOS[15:8] TOS[20:16] Preliminary Datasheet DS40002214E-page 85 PIC18F06/16Q41 NVM - Nonvolatile Memory Module 10. NVM - Nonvolatile Memory Module The Nonvolatile Memory (NVM) module provides run-time read and write access to the Program Flash Memory (PFM), Data Flash Memory (DFM) and Configuration bits. PFM includes the program memory and user ID space. DFM is also referred to as EEPROM which is accessed one byte at a time and the erase before write is automatic. The Table Pointer provides read-only access to the PFM, DFM and Configuration bits. The NVM controls provide both read and write access to PFM, DFM and Configuration bits. Reads and writes to and from the DFM are limited to single byte operations, whereas those for PFM are 16-bit word or 128-word page operations. The page buffer memory occupies one full bank of RAM space located in the RAM bank following the last occupied GPR bank. Refer to the “Memory Organization” chapter for more details about the buffer RAM. The registers used for control, address and data are as follows: • NVMCON0 - Operation start and active status • NVMCON1 - Operation type and error status • NVMLOCK - Write-only register to guard against accidental writes • NVMADR - Read/write target address (multibyte register) • NVMDAT - Read/write target data (multibyte register) • TBLPTR - Table Pointer PFM target address for reads and buffer RAM address for writes (multibyte register) • TABLAT - Table Pointer read/write target data (single byte register) The write and erase times are controlled by an on-chip timer. The write and erase voltages are generated by an on-chip charge pump rated to function over the operating voltage range of the device. PFM and DFM can be protected in two ways: code protection and write protection. Code protection (Configuration bit CP) disables read and write access through an external device programmer. Write protection prevents user software writes to NVM areas tagged for protection by the WRTn Configuration bits. Code protection does not affect the self-write and erase functionality, whereas write protection does. Attempts to write a protected location will set the WRERR bit. Code protection and write protection can only be reset on a Bulk Erase performed by an external programmer. The Bulk Erase command is used to completely erase different memory regions. The area to be erased is selected using a bit field combination. The Bulk Erase command can only be issued through an external programmer. There is no run time access for this command. If the device is code-protected and a Bulk Erase command for the configuration memory is issued; all other memory regions are also erased. Refer to the ”Programming Specifications” for more details. 10.1 Operations NVM write operations are controlled by selecting the desired action with the NVMCMD bits and then starting the operation by executing the unlock sequence. NVM read operations are started by setting the GO bit after setting the read operation. Available NVM operations are shown in the following table. Table 10-1. NVM Operations NVMCMD Unlock Operation DFM PFM Source/Destination WRERR INT 000 No Read byte word NVM to NVMDAT No No 001 No Read and Post Increment byte word NVM to NVMDAT No No 010 No Read Page — page NVM to Buffer RAM No No 011 Yes Write byte word NVMDAT to NVM Yes Yes 100 Yes Write and Post Increment byte word NVMDAT to NVM Yes Yes 101 Yes Write Page — page Buffer RAM to NVM Yes Yes © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 86 PIC18F06/16Q41 NVM - Nonvolatile Memory Module ...........continued NVMCMD Unlock Operation DFM PFM Source/Destination WRERR INT 110 Yes Erase Page — page n/a Yes Yes 111 No Reserved (No Operation) — — — No No Important:  When the GO bit is set, writes operations are blocked on all NVM registers. The GO bit is cleared by hardware when the operation is complete. The GO bit cannot be cleared by software. 10.2 Unlock Sequence As an additional layer of protection against memory corruption, a specific code execution unlock sequence is required to initiate a write or erase operation. All interrupts need to be disabled before starting the unlock sequence to ensure proper execution. Example 10-1. Unlock Sequence in C NVMLOCK = 0x55; NVMLOCK = 0xAA; NVMCON0bits.GO = 1; 10.3 Program Flash Memory (PFM) The Program Flash Memory is readable, writable and erasable over the entire VDD range. A 128-word PFM page is the only size that can be erased by user software. A Bulk Erase operation cannot be issued from user code. A read from program memory is executed either one byte, one word or a 128-word page at a time. A write to program memory can be executed as either 1 or 128 words at a time. Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, so code cannot execute. An internal programming timer controls the write time of program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. It is important to understand the PFM memory structure for erase and programming operations. Program memory word size is 16 bits wide. After a page has been erased, all or a portion of this page can be programmed. Data can be written directly into PFM one 16-bit word at a time using the NVMADR, NVMDAT and NVMCON1 controls or as a full page from the buffer RAM. The buffer RAM is directly accessible as any other SFR/GPR register and also may be loaded via sequential writes using the TABLAT and TBLPTR registers. Important:  To modify only a portion of a previously programmed page, the contents of the entire page must be read and saved in the buffer RAM prior to the page erase. The Read Page operation is the easiest way to do this. The page needs to be erased so that the new data can be written into the buffer RAM to reprogram the page of PFM. However, any unprogrammed locations can be written using the single word Write operation without first erasing the page. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 87 PIC18F06/16Q41 NVM - Nonvolatile Memory Module 10.3.1 Page Erase The erase size is always 128 words. Only through the use of an external programmer can larger areas of program memory be Bulk Erased. Word erase in the program memory is not supported. When initiating an erase sequence from user code, a page of 128 words of program memory is erased. The NVMADR[21:8] bits point to the page being erased. The NVMADR[7:0] bits are ignored. The NVMCON0 and NVMCON1 registers command the erase operation. The NVMCMD bits are set to select the erase operation. The GO bit is set to initiate the erase operation as the last step in the unlock sequence. The NVM unlock sequence described in the Unlock Sequence section must be used; this guards against accidental writes. Instruction execution is halted during the erase cycle. The erase cycle is terminated by the internal programming timer. The sequence of events for erasing a page of PFM is: 1. 2. Set the NVMADR registers to an address within the intended page. Set the NVMCMD control bits to ‘b110 (Page Erase). 3. 4. 5. 6. 7. 8. Disable all interrupts. Perform the unlock sequence as described in the Unlock Sequence section. Set the GO bit to start the PFM page erase. Monitor the GO bit or NVMIF interrupt flag to determine when the erase has completed. Interrupts can be enabled after the GO bit is clear. Set the NVMCMD control bits to ‘b000. If the PFM address is write-protected, the GO bit will be cleared, the erase operation will not take place, and the WRERR bit will be set. While erasing the PFM page, the CPU operation is suspended and then resumes when the operation is complete. Upon erase completion, the GO bit is cleared in hardware, the NVMIF is set, and an interrupt will occur (if the NVMIE bit is set and interrupts are enabled). The buffer RAM data are not affected by erase operations and the NVMCMD bits will remain unchanged throughout the erase opeation. Figure 10-1. PFM Page Erase Flowchart Start Erase Operation Load the NVMADR register with address in the page to be erased Set NVM Command to erase (NVMCMD = ‘b110) Disable interrupts (GIE = 0) Execute unlock sequence including setting the GO bit CPU stalls while erase executes Enable interrupts (GIE = 1) Clear NVM Command (NVMCMD = ‘b000) End Erase Operation © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 88 PIC18F06/16Q41 NVM - Nonvolatile Memory Module Example 10-2. Erasing a Page of Program Flash Memory in C // Code sequence to erase one page of PFM // PFM target address is specified by PAGE_ADDR // Save interrupt enable bit value uint8_t GIEBitValue = INTCON0bits.GIE; // Load NVMADR with the base address of the memory page NVMADR = PAGE_ADDR; NVMCON1bits.CMD = 0x06; // Set the page erase command INTCON0bits.GIE = 0; // Disable interrupts //––––––––– Required Unlock Sequence ––––––––– NVMLOCK = 0x55; NVMLOCK = 0xAA; NVMCON0bits.GO = 1; // Start page erase //––––––––––––––––––––––––––––––––––––––––––––– while (NVMCON0bits.GO); // Wait for the erase operation to complete // Verify erase operation success and call the recovery function if needed if (NVMCON1bits.WRERR){ ERASE_FAULT_RECOVERY(); } INTCON0bits.GIE = GIEBitValue; NVMCON1bits.CMD = 0x00; // Restore interrupt enable bit value // Disable writes to memory Important:  • If a write or erase operation is terminated by an unexpected Reset, the WRERR bit will be set and the user can check to decide whether a rewrite of the location(s) is needed. • If a write or erase operation is attempted on a write-protected area, the WRERR bit will be set. • If a write or erase operation is attempted on an invalid address location, the WRERR bit is set. (Refer to the Program and Data Memory Map in the “Memory Organization” chapter for more information on valid address locations.) 10.3.2 Page Read PFM can be read one word or 128-word page at a time. A page is read by setting the NVMADR registers to an address within the target page and setting the NVMCMD bits to ‘b010. The page content is then transferred from PFM to the buffer RAM by starting the read operation by setting the GO bit. The sequence of events for reading a 128-word page of PFM is: 1. 2. Set the NVMADR registers to an address within the intended page. Set the NVMCMD control bits to ‘b010 (Page Read). 3. 4. Set the GO bit to start the PFM page read. Monitor the GO bit or NVMIF interrupt flag to determine when the read has completed. Example 10-3. Reading a Page of Program Flash Memory in C // Code sequence to read one page of PFM to Buffer Ram // PFM target address is specified by PAGE_ADDR // Load NVMADR with the base address of the memory page NVMADR = PAGE_ADDR; NVMCON1bits.CMD = 0x02; NVMCON0bits.GO = 1; while (NVMCON0bits.GO); © 2020-2021 Microchip Technology Inc. and its subsidiaries // Set the page read command // Start page read // Wait for the read operation to complete Preliminary Datasheet DS40002214E-page 89 PIC18F06/16Q41 NVM - Nonvolatile Memory Module 10.3.3 Word Read A single 16-bit word is read by setting the NVMADR registers to the target address and setting the NVMCMD bits to ‘b000. The word is then transferred from PFM to the NVMDAT registers by starting the read operation by setting the GO bit. The sequence of events for reading a word of PFM is: 1. 2. Set the NVMADR registers to the target address. Set the NVMCMD control bits to ‘b000 (Word Read). 3. 4. Set the GO bit to start the PFM word read. Monitor the GO bit or NVMIF interrupt flag to determine when the read has completed. Example 10-4. Reading a Word from Program Flash Memory in C // Code sequence to read one word from PFM // PFM target address is specified by WORD_ADDR // Variable to store the word value from desired location in PFM uint16_t WordValue; // Load NVMADR with the desired word address NVMADR = WORD_ADDR; NVMCON1bits.CMD = 0x00; // Set the word read command NVMCON0bits.GO = 1; // Start word read while (NVMCON0bits.GO); // Wait for the read operation to complete WordValue = NVMDAT; // Store the read value to a variable 10.3.4 Page Write A page is written by first loading the buffer registers in the buffer RAM. All buffer registers are then written to PFM by setting the NVMADR to an address within the intended address range of the target PFM page, setting the NVMCMD bits to ‘b101, and then executing the unlock sequence and setting the GO bit. If the PFM address in the NVMADR is write-protected, or if NVMADR points to an invalid location, the GO bit is cleared without any effect and the WRERR bit is set. CPU operation is suspended during a page write cycle and resumes when the operation is complete. The page write operation completes in one extended instruction cycle. When complete, the GO bit is cleared by hardware and NVMIF is set. An interrupt will occur if NVMIE is also set. The buffer registers and NVMCMD bits are not changed throughout the write operation. The internal programming timer controls the write time. The write/erase voltages are generated by an on-chip charge pump and rated to operate over the voltage range of the device. Important:  Individual bytes of program memory may be modified, provided that the modification does not attempt to change any NVM bit from a ‘0’ to a ‘1’. When modifying individual bytes with a page write operation, it is necessary to load all buffer registers with either 0xFF or the existing contents of memory before executing a page write operation. The fastest way to do this is by performing a page read operation. In this device a PFM page is 128 words (256 bytes). This is the same size as one bank of general purpose RAM (GPR). This area of GPR space is dedicated as a buffer area for NVM page operations. The buffer areas for each device in the family are shown in the following table: Table 10-2. NVM Buffer Banks Device GPR Bank Number PIC18Fx6Q41 21 PIC18Fx5Q41 13 PIC18Fx4Q41 9 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 90 PIC18F06/16Q41 NVM - Nonvolatile Memory Module There are several ways to address the data in the GPR buffer space: • Using the TBLRD and TBLWT instructions • • Using the indirect FSR registers Direct read and writes to specific GPR locations Neglecting the bank select bits, the 8 address bits of the GPR buffer space correspond to the 8 LSbs of each PFM page. In other words, there is a one-to-one correspondence between the NVMADRL register and the FSRxL register, where the x in FSRx is 0, 1 or 2. The sequence of events for programming a page of PFM is: 1. 2. Set the NVMADR registers to an address within the intended page. Set the NVMCMD to ‘b110 (Erase Page). 3. 4. 5. 6. 7. Disable all interrupts. Perform the unlock sequence as described in the Unlock Sequence section. Set the GO bit to start the PFM page erase. Monitor the GO bit or NVMIF interrupt flag to determine when the erase has completed. Set NVMCMD to ‘b101 (Page Write). 8. 9. 10. 11. 12. Perform the unlock sequence. Set the GO bit to start the PFM page write. Monitor the GO bit or NVMIF interrupt flag to determine when the write has completed. Interrupts can be enabled after the GO bit is clear. Set the NVMCMD control bits to ‘b000. Example 10-5. Writing a Page of Program Flash Memory in C // Code sequence to write a page of PFM // Input[] is the user data that needs to be written to PFM // PFM target address is specified by PAGE_ADDR #define PAGESIZE 128 // PFM page size // Save Interrupt Enable bit Value uint8_t GIEBitValue = INTCON0bits.GIE; // The BufferRAMStartAddr will be changed based on the device, refer // to the "Memory Organization" chapter for more details uint16_t bufferRAM __at(BufferRAMStartAddr); // Defining a pointer to the first location of the Buffer RAM uint16_t *bufferRamPtr = (uint16_t*) & bufferRAM; //Copy application buffer contents to the Buffer RAM for (uint8_t i = 0; i < PAGESIZE; i++) { *bufferRamPtr++ = Input[i]; } // Load NVMADR with the base address of the memory page NVMADR = PAGE_ADDR; NVMCON1bits.CMD = 0x06; // Set the page erase command INTCON0bits.GIE = 0; // Disable interrupts //––––––––– Required Unlock Sequence ––––––––– NVMLOCK = 0x55; NVMLOCK = 0xAA; NVMCON0bits.GO = 1; // Start page erase //––––––––––––––––––––––––––––––––––––––––––––– while (NVMCON0bits.GO); // Wait for the erase operation to complete // Verify erase operation success and call the recovery function if needed if (NVMCON1bits.WRERR){ ERASE_FAULT_RECOVERY(); } // NVMADR is already pointing to target page NVMCON1bits.CMD = 0x05; // Set the page write command //––––––––– Required Unlock Sequence ––––––––– NVMLOCK = 0x55; NVMLOCK = 0xAA; © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 91 PIC18F06/16Q41 NVM - Nonvolatile Memory Module NVMCON0bits.GO = 1; // Start page write //––––––––––––––––––––––––––––––––––––––––––––– while (NVMCON0bits.GO); // Wait for the write operation to complete // Verify write operation success and call the recovery function if needed if (NVMCON1bits.WRERR){ WRITE_FAULT_RECOVERY(); } INTCON0bits.GIE = GIEBitValue; NVMCON1bits.CMD = 0x00; 10.3.5 // Restore interrupt enable bit value // Disable writes to memory Word Write PFM can be written one word at a time to a pre-erased memory location. Refer to the “Word Modify” section for more information on writing to a prewritten memory location. A single word is written by setting the NVMADR to the target address and loading NVMDAT with the desired word. The word is then transferred to PFM by setting the NVMCMD bits to ‘b011 then executing the unlock sequence and setting the GO bit. The sequence of events for programming single word to a pre-erased location of PFM is: 1. 2. 3. Set the NVMADR registers to the target address. Load the NVMDAT with desired word. Set the NVMCMD control bits to ‘b011 (Word Write). 4. 5. 6. 7. 8. 9. Disable all interrupts. Perform the unlock sequence as described in the Unlock Sequence section. Set the GO bit to start the PFM word write. Monitor the GO bit or NVMIF interrupt flag to determine when the write has completed. Interrupts can be enabled after the GO bit is clear. Set the NVMCMD control bits to ‘b000. Example 10-6. Writing a Word of Program Flash Memory in C // Code sequence to program one word to a pre-erased location in PFM // PFM target address is specified by WORD_ADDR // Target data is specified by WordValue // Save interrupt enable bit value uint8_t GIEBitValue = INTCON0bits.GIE; // Load NVMADR with the target address of the word NVMADR = WORD_ADDR; NVMDAT = WordValue; // Load NVMDAT with the desired value NVMCON1bits.CMD = 0x03; // Set the word write command INTCON0bits.GIE = 0; // Disable interrupts //––––––––– Required Unlock Sequence ––––––––– NVMLOCK = 0x55; NVMLOCK = 0xAA; NVMCON0bits.GO = 1; // Start word write //––––––––––––––––––––––––––––––––––––––––––––––– while (NVMCON0bits.GO); // Wait for the write operation to complete // Verify word write operation success and call the recovery function if needed if (NVMCON1bits.WRERR){ WRITE_FAULT_RECOVERY(); } INTCON0bits.GIE = GIEBitValue; NVMCON1bits.CMD = 0x00; 10.3.6 // Restore interrupt enable bit value // Disable writes to memory Word Modify Changing a word in PFM requires erasing the word before it is rewritten. However, the PFM cannot be erased by less than a page at a time. Changing a single word requires reading the page, erasing the page, and then rewriting the page with the modified word. The NVM command set includes page operations to simplify this task. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 92 PIC18F06/16Q41 NVM - Nonvolatile Memory Module The steps necessary to change one or more words in PFM space are as follows: 1. Set the NVMADR registers to the target address. 2. Set the NVMCMD to ‘b010 (Page Read). 3. 4. 5. 6. Set the GO bit to start the PFM read into the GPR buffer. Monitor the GO bit or NVMIF interrupt flag to determine when the read has completed. Make the desired changes to the GPR buffer data. Set NVMCMD to ‘b110 (Page Erase). 7. 8. 9. 10. 11. Disable all interrupts. Perform the unlock sequence as described in the Unlock Sequence section. Set the GO bit to start the PFM page erase. Monitor the GO bit or NVMIF interrupt flag to determine when the erase has completed. Set NVMCMD to ‘b101 (Page Write). 12. 13. 14. 15. 16. Perform the unlock sequence. Set the GO bit to start the PFM page write. Monitor the GO bit or NVMIF interrupt flag to determine when the write has completed. Interrupts can be enabled after the GO bit is clear. Set the NVMCMD control bits to ‘b000. Example 10-7. Modifying a Word in Program Flash Memory in C // Code sequence to modify one word in a programmed page of PFM // The variable with desired value is specified by ModifiedWord // PFM target address is specified by WORD_ADDR // PFM page size is specified by PAGESIZE // The Buffer RAM start address is specified by BufferRAMStartAddr. This value // will be changed based on the device, refer to the "Memory Organization" //chapter for more details. // Save Interrupt Enable bit Value uint8_t GIEBitValue = INTCON0bits.GIE; uint16_t bufferRAM __at(BufferRAMStartAddr); // Defining a pointer to the first location of the Buffer RAM uint16_t *bufferRamPtr = (uint16_t*) & bufferRAM; // Load NVMADR with the base address of the memory page NVMADR = WORD_ADDR; NVMCON1bits.CMD = 0x02; // Set the page read command INTCON0bits.GIE = 0; // Disable interrupts NVMCON0bits.GO = 1; // Start page read while (NVMCON0bits.GO); // Wait for the read operation to complete // NVMADR is already pointing to target page NVMCON1bits.CMD = 0x06; // Set the page erase command //––––––––– Required Unlock Sequence ––––––––– NVMLOCK = 0x55; NVMLOCK = 0xAA; NVMCON0bits.GO = 1; // Start page erase //––––––––––––––––––––––––––––––––––––––––––––– while (NVMCON0bits.GO); // Wait for the erase operation to complete // Verify erase operation success and call the recovery function if needed if (NVMCON1bits.WRERR){ ERASE_FAULT_RECOVERY(); } //Modify Buffer RAM for the given word to be written to PFM uint8_t offset = (uint8_t) ((WORD_ADDR & ((PAGESIZE * 2) - 1)) / 2); bufferRamPtr += offset; *bufferRamPtr = ModifiedWord; // NVMADR is already pointing to target page NVMCON1bits.CMD = 0x05; // Set the page write command //––––––––– Required Unlock Sequence ––––––––– NVMLOCK = 0x55; NVMLOCK = 0xAA; © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 93 PIC18F06/16Q41 NVM - Nonvolatile Memory Module NVMCON0bits.GO = 1; // Start page write //––––––––––––––––––––––––––––––––––––––––––––– while (NVMCON0bits.GO); // Wait for the write operation to complete // Verify write operation success and call the recovery function if needed if (NVMCON1bits.WRERR){ WRITE_FAULT_RECOVERY(); } INTCON0bits.GIE = GIEBitValue; NVMCON1bits.CMD = 0x00; 10.3.7 // Restore interrupt enable bit value // Disable writes to memory Write Verify Depending on the application, good programming practice can dictate that the value written to the memory shall be verified against the original value. This can be used in applications where excessive writes can stress bits near the specification limit. Since program memory is stored as a full page, the stored program memory contents are compared with the intended data stored in the buffer RAM after the last write is complete. Figure 10-2. Program Flash Memory Write Verify Flowchart Rev. 10-000051= 1/30/2019 Start Verify Operation This routine assumes that the last page of data written was from the buffer RAM. This image will be used to verify the data currently stored in PFM Set NVMCMD to Read and Post Increment Set GO bit NVMDAT = RAM image ? Yes No No Fail Verify Operation Last word ? Yes End Verify Operation © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 94 PIC18F06/16Q41 NVM - Nonvolatile Memory Module 10.3.8 Unexpected Termination of Write Operation If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed needs to be verified and reprogrammed, if needed. If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the WRERR bit will be set, which the user can check to decide whether a rewrite of the location(s) is needed. 10.3.9 User ID, Device ID, Configuration Settings Access, DIA and DCI The NVMADR value determines which NVM address space is accessed. The User IDs and Configuration areas allow read and write access, whereas Device and Revision IDs are limited to read-only. Reading and writing User ID space is identical to reading and writing PFM space as described in the preceding paragraphs. Writing to the Configuration bits is performed in the same manner as writing to the Data Flash Memory (DFM). Configuration settings are modified one byte at a time with the NVM Read and Write operations. When a Write operation is performed on a Configuration byte, an erase byte is performed automatically before the new byte is written. Any code protection settings that are not enabled will remain not enabled after the Write operation, unless the new values enable them. However, any code protection settings that are enabled cannot be disabled by a self-write of the configuration space. The user can modify the configuration space by the following steps: 1. Read the target Configuration byte by setting the NVMADR with the target address. 2. Retrieve the Configuration byte with the Read operation (NVMCMD = ‘b000). 3. 4. Modify the Configuration byte in NVMDAT register. Write the NVMDAT register to the Configuration byte using the Write operation (NVMCMD = ‘b011) and unlock sequence. 10.3.10 Table Pointer Operations To read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: • Table Read (TBLRD*) • Table Write (TBLWT*) The SFR registers associated with these operations include: • TABLAT register • TBLPTR registers The program memory space is 16 bits wide, while the data RAM space is eight bits wide. The TBLPTR registers determine the address of one byte of the NVM memory. Table reads move one byte of data from NVM space to the TABLAT register, and table writes move the TABLAT data to the buffer RAM ready for a subsequent write to NVM space with the NVM controls. 10.3.10.1 Table Pointer Register The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR comprises three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer (bits 0 through 21). The bits 0 through 20 allow the device to address up to 2 Mbytes of program memory space. Bit 21 allows access to the Device ID, the User ID, Configuration bits as well as the DIA and DCI. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can increment and decrement TBLPTR, depending on specific appended characters shown in the following table. The increment and decrement operations on the TBLPTR affect only bits 0 through 20. Table 10-3. Table Pointer Operations with TBLRD and TBLWT Instructions Example Operation on Table Pointer TBLRD* TBLWT* TBLPTR is not modified © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 95 PIC18F06/16Q41 NVM - Nonvolatile Memory Module TBLRD*+ TBLWT*+ TBLPTR is incremented after the read/write TBLRD*TBLWT*- TBLPTR is decremented after the read/write TBLRD+* TBLWT+* TBLPTR is incremented before the read/write 10.3.10.2 Table Latch Register The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register receives one byte of NVM data resulting from a TBLRD* instruction and is the source of the 8-bit data sent to the holding register space as a result of a TBLWT* instruction. 10.3.10.3 Table Read Operations The table read operation retrieves one byte of data directly from program memory pointed to by the TBLPTR registers and places it into the TABLAT register. The following figure shows the operation of a table read. Figure 10-3. Table Read Operation Instruction: TBLRD* Table Pointer(1) Program Memory TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT Program Memory (TBLPTR) Note: 1. The Table Pointer register points to a byte in program memory. 10.3.10.4 Table Write Operations The table write operation stores one byte of data from the TABLAT register into a buffer RAM register. The following figure shows the operation of a table write from the TABLAT register to the buffer RAM space. The procedure to write the contents of the buffer RAM into program memory is detailed in the “Page Write” section. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 96 PIC18F06/16Q41 NVM - Nonvolatile Memory Module Figure 10-4. Table Write Operation Instruction: TBLWT* GPR Space Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Buffer RAM Program Memory (TBLPTR[MSbs]) Note 1: During table writes the Table Pointer does not point directly to program memory. TBLPTRL actually points to an address within the buffer registers. TBLPTRU:TBLPTRH points to program memory where the entire buffer space will eventually be written with the NVM commands. Table operations work with byte entities. Tables containing data, rather than program instructions, are not required to be word-aligned. Therefore, a table can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. 10.3.10.5 Table Pointer Boundaries The TBLPTR register is used in reads of the Program Flash Memory. Writes using the TBLPTR register go into a buffer RAM from which the data can eventually be transferred to Program Flash Memory using the NVMADR register and NVM commands. When a TBLRD instruction is executed, all 22 bits of the TBLPTR determine which byte is read from program memory directly into the TABLAT register. When a TBLWT instruction is executed, the byte in the TABLAT register is written not to Flash memory but to a buffer register in preparation for a program memory write. All the buffer registers form a write block of size 128 words/256 bytes. The LSbs of the TBLPTR register determine to which specific address within the buffer register block the write affects. The size of the write block determines the number of LSbs that are affected. The MSbs of the TBLPTR register have no effect during TBLWT operations. When a program memory page write is executed, the entire buffer register block is written to the Flash memory at the address determined by the MSbs of the NVMADR register. The LSbs are ignored during Flash memory writes. The following figure illustrates the relevant boundaries of the TBLPTR register based on NVM operations. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 97 PIC18F06/16Q41 NVM - Nonvolatile Memory Module Figure 10-5. Table Pointer Boundaries Based on Operation 21 TBLPTRU 16 TBLPTRH 15 8 NVMADRH NVMADRU 7 TBLPTRL 0 TBLPTRL Table Write TBLPTR[7:0] Page Erase/Write NVMADR[21:8] Table Read - TBLPTR[21:0] Note:  1. Refer to the “Memory Organization” chapter for more details about the size of the buffer registers block. 10.3.10.6 Reading the Program Flash Memory The TBLRD instruction retrieves data from program memory at the location to which the TBLPTR register points and places it into the TABLAT SFR register. Table reads from program memory are performed one byte at a time. The instruction set includes incrementing the TBLPTR register automatically for the next table read operation. The CPU operation is suspended during the read, and resumes operation immediately after. From the user point of view, the value in the TABLAT register is valid in the next instruction cycle. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. The following figure illustrates the interface between the internal program memory and the TABLAT register. Figure 10-6. Reads from Program Flash Memory Program Flash Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 Instruction Register (IR) FETCH © 2020-2021 Microchip Technology Inc. and its subsidiaries TBLRD Preliminary Datasheet TBLPTR = xxxxx0 TABLAT Read Register DS40002214E-page 98 PIC18F06/16Q41 NVM - Nonvolatile Memory Module Figure 10-7. Program Flash Memory Read Flowchart Start Read Operation Select Byte Address (TBLPTR Register) Initiate Read Operation (TBLRD) Data read now in TABLAT register End Read Operation Example 10-8. Reading a Program Flash Memory Word MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_WORD: TBLRD*+ MOVF MOVWF TBLRD*+ MOVFW MOVF 10.4 CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL TABLAT, W WORD_EVEN TABLAT, W WORD_ODD ; Load TBLPTR with the base ; address of the word ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data Data Flash Memory (DFM) The Data Flash Memory is a nonvolatile memory array, also referred to as EEPROM. The DFM is mapped above program memory space. The DFM can be accessed using the Table Pointer or NVM Special Function Registers (SFRs). The DFM is readable and writable during normal operation over the entire VDD range. The DFM can only be read and written one byte at a time. When interfacing to the data memory block, the NVMDATL register holds the 8-bit data for read/write and the NVMADR register holds the address of the DFM location being accessed. The DFM is rated for high erase/write cycle endurance. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an internal programming timer; it will vary with voltage and temperature as well as from device-to-device. Refer to the data EEPROM memory parameters in the “Electrical Specifications” chapter for the limits. 10.4.1 Reading the DFM To read a DFM location, the user must write the address to the NVMADR register, set the NVMCMD bits for a single read operation (NVMCMD = ‘b000), and then set the GO control bit. The data is available on the very next instruction cycle. Therefore, the NVMDATL register can be read by the next instruction. NVMDATL will hold this value until another read operation, or until it is written to by the user (during a write operation). Note:  Only byte reads are supported for DFM. Reading DFM with the Read Page operation is not supported. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 99 PIC18F06/16Q41 NVM - Nonvolatile Memory Module The sequence of events for reading a byte of DFM is: 1. 2. Set the NVMADR registers to an address within the intended page. Set the NVMCMD control bits to ‘b000 (Byte Read). 3. 4. Set the GO bit to start the DFM byte read. Monitor the GO bit or NVMIF interrupt flag to determine when the read has completed. This process is also shown in the following flowchart. Figure 10-8. DFM Read Flowchart Start Read Operation Set DFM Byte Address (NVMADR = Address) Set NVM Read Command (NVMCMD = ‘b000) Initiate Read (GO = 1) Data read now in NVMDATL End Read Operation Example 10-9. Reading a Byte from Data Flash Memory in C // Code sequence to read one byte from DFM // DFM target address is specified by DFM_ADDR // Variable to store the byte value from desired location in DFM uint8_t ByteValue; // Load NVMADR with the desired byte address NVMADR = DFM_ADDR; NVMCON1bits.CMD = 0x00; // Set the byte read command NVMCON0bits.GO = 1; // Start byte read while (NVMCON0bits.GO); // Wait for the read operation to complete ByteValue = NVMDATL; // Store the read value to a variable 10.4.2 Writing to DFM To write a DFM location, the address must first be written to the NVMADR register, the data written to the NVMDATL register, and the Write operation command set in the NVMCMD bits. The sequence shown in Unlock Sequence must be followed to initiate the write cycle. Multibyte Page writes are not supported for the DFM. The write will not begin if the NVM unlock sequence is not exactly followed for each byte. It is strongly recommended to disable interrupts during this code segment. When not actively writing to the DFM, the NVMCMD bits need to be kept clear at all times as an extra precaution against accidental writes. The NVMCMD bits are not cleared by hardware. After a write sequence has been initiated, NVMCON0, NVMCON1, NVMADR and NVMDAT cannot be modified. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 100 PIC18F06/16Q41 NVM - Nonvolatile Memory Module Each DFM write operation includes an implicit erase cycle for that byte. CPU execution continues in parallel and at the completion of the write cycle, the GO bit is cleared in hardware and the NVM Interrupt Flag (NVMIF) bit is set. The user can either enable the interrupt or poll the bit. NVMIF must be cleared by software. The sequence of events for programming one byte of DFM is: 1. 2. 3. Set NVMADR registers with the target byte address. Load NVMDATL register with desired byte. Set the NVMCMD control bits to ‘b011 (Byte Write). 4. 5. 6. 7. 8. 9. Disable all interrupts. Perform the unlock sequence as described in the Unlock Sequence section. Set the GO bit to start the DFM byte write. Monitor the GO bit or NVMIF interrupt flag to determine when the write has been completed. Interrupts can be enabled after the GO bit is clear. Set the NVMCMD control bits to ‘b000. Example 10-10. Writing a Byte to Data Flash Memory in C // Code sequence to write one byte to a DFM // DFM target address is specified by DFM_ADDR // Target data is specified by ByteValue // Save interrupt enable bit value uint8_t GIEBitValue = INTCON0bits.GIE; // Load NVMADR with the target address of the byte NVMADR = DFM_ADDR; NVMDATL = ByteValue; // Load NVMDAT with the desired value NVMCON1bits.CMD = 0x03; // Set the byte write command INTCON0bits.GIE = 0; // Disable interrupts //––––––––– Required Unlock Sequence ––––––––– NVMLOCK = 0x55; NVMLOCK = 0xAA; NVMCON0bits.GO = 1; // Start byte write //––––––––––––––––––––––––––––––––––––––––––––––– while (NVMCON0bits.GO); // Wait for the write operation to complete // Verify byte write operation success and call the recovery function if needed if (NVMCON1bits.WRERR){ WRITE_FAULT_RECOVERY(); } INTCON0bits.GIE = GIEBitValue; NVMCON1bits.CMD = 0; 10.4.3 // Restore interrupt enable bit value // Disable writes to memory Erasing the DFM The DFM does not support the Page Erase operation. However, the DFM can be erased by writing 0xFF to all locations in the memory that need to be erased. The simple code example bellow shows how to erase ‘n’ number of bytes in DFM. Refer to the “Memory Organization” chapter for more details about the DFM size and valid address locations. Example 10-11. Erasing n Bytes of Data Flash Memory in C // Code sequence to erase n bytes of DFM // DFM target start address is specified by PAGE_ADDR // Number of bytes to be eares is specified by n // Save interrupt enable bit value uint8_t GIEBitValue = INTCON0bits.GIE; // Load NVMADR with the target address of the byte NVMADR = DFM_ADDR; NVMDATL = 0xFF; // Load NVMDATL with 0xFF NVMCON1bits.CMD = 0x04; // Set the write and post increment command INTCON0bits.GIE = 0; // Disable interrupts © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 101 PIC18F06/16Q41 NVM - Nonvolatile Memory Module for (uint8_t i = 0; i < n; i++}( NVMLOCK = 0x55; NVMLOCK = 0xAA; NVMCON0bits.GO = 1; } // Verify byte erase operation success and call the recovery function if needed if (NVMCON1bits.WRERR){ ERASE_FAULT_RECOVERY(); } INTCON0bits.GIE = GIEBitValue; NVMCON1bits.CMD = 0; 10.4.4 // Restore interrupt enable bit value // Disable writes to memory DFM Write Verify Depending on the application, good programming practice can dictate that the value written to the memory shall be verified against the original value. This can be used in applications where excessive writes can stress bits near the specification limit to ensure that the intended values are written correctly to the specified memory locations. 10.4.5 Operation During Code-Protect and Write-Protect The DFM can be code-protected using the CP Configuration bit. In-Circuit Serial Programming read and write operations are disabled when code protection is enabled. However, internal reads operate normally. Internal writes operate normally, provided that write protection is not enabled. If the DFM is write-protected or if NVMADR points at an invalid address location, attempts to set the GO bit will fail and the WRERR bit will be set. 10.4.6 Protection Against Spurious Writes A write sequence is valid only when both the following conditions are met. This prevents spurious writes that might lead to data corruption. 1. 2. 10.5 All NVM read, write and erase operations are enabled with the NVMCMD control bits. It is suggested to have the NVMCMD bits cleared at all times except during memory writes. This prevents memory operations if any of the control bits are set accidentally. The NVM unlock sequence must be performed each time before all operations except the memory read operation. Register Definitions: NVM © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 102 PIC18F06/16Q41 NVM - Nonvolatile Memory Module 10.5.1 NVMCON0 Name:  Address:  NVMCON0 0x040 Nonvolatile Memory Control Register 0 Bit 7 6 5 4 3 2 1 0 GO R/S/HC 0 Access Reset Bit 0 – GO Start Operation Control Start the operation specified by the NVMCMD bits Value Description 1 Start operation (must be set after UNLOCK sequence for all operations except READ) 0 Operation is complete © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 103 PIC18F06/16Q41 NVM - Nonvolatile Memory Module 10.5.2 NVMCON1 Name:  Address:  NVMCON1 0x041 Nonvolatile Memory Control Register 1 Bit Access Reset 7 WRERR R/C/HS 0 6 5 4 3 2 R/W 0 1 NVMCMD[2:0] R/W 0 0 R/W 0 Bit 7 – WRERR NVM Write Error Reset States: POR = 0 All other Resets = u Value Description 1 A write operation was interrupted by a Reset, or a write or erase operation was attempted on a write-protected area, or a write or erase operation was attempted on an unimplemented area, or a write or erase operation was attempted while locked, or a page operation was directed to a DFM area 0 All write/erase operations have completed successfully Bits 2:0 – NVMCMD[2:0] NVM Command Table 10-4. NVM Operations NVMCMD Unlock 000 001 010 011 100 101 110 111 No No No Yes Yes Yes Yes No Operation DFM PFM Source/Destination WRERR INT Read Read and Post Increment Read Page Write Write and Post Increment Write Page Erase Page Reserved (No Operation) byte byte — byte byte — — — word word page word word page page — NVM to NVMDAT NVM to NVMDAT NVM to Buffer RAM NVMDAT to NVM NVMDAT to NVM Buffer RAM to NVM n/a — No No No Yes Yes Yes Yes No No No No Yes Yes Yes Yes No © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 104 PIC18F06/16Q41 NVM - Nonvolatile Memory Module 10.5.3 NVMLOCK Name:  Address:  NVMLOCK 0x042 Nonvolatile Memory Write Restriction Control Register NVM write and erase operations require writing 0x55 then 0xAA to this register immediately before the operation execution. Bit Access Reset 7 6 5 WO 0 WO 0 WO 0 4 3 NVMLOCK[7:0] WO WO 0 0 2 1 0 WO 0 WO 0 WO 0 Bits 7:0 – NVMLOCK[7:0] Reading this register always returns ‘0’. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 105 PIC18F06/16Q41 NVM - Nonvolatile Memory Module 10.5.4 NVMADR Name:  Address:  NVMADR 0x043 Nonvolatile Memory Address Register Bit 23 22 Access Reset Bit Access Reset Bit Access Reset 21 20 R/W 0 R/W 0 15 14 13 R/W 0 R/W 0 R/W 0 7 6 5 R/W 0 R/W 0 R/W 0 19 18 NVMADR[21:16] R/W R/W 0 0 12 11 NVMADR[15:8] R/W R/W 0 0 4 3 NVMADR[7:0] R/W R/W 0 0 17 16 R/W 0 R/W 0 10 9 8 R/W 0 R/W 0 R/W 0 2 1 0 R/W 0 R/W 0 R/W 0 Bits 21:0 – NVMADR[21:0] NVM Address Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • NVMADRU: Accesses the upper byte NVMADR[21:16] • NVMADRH: Accesses the high byte NVMADR[15:8] • NVMADRL: Accesses the low byte NVMADR[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 106 PIC18F06/16Q41 NVM - Nonvolatile Memory Module 10.5.5 NVMDAT Name:  Address:  NVMDAT 0x046 Nonvolatile Memory Data Register Bit Access Reset Bit Access Reset 15 14 13 R/W 0 R/W 0 R/W 0 7 6 5 R/W 0 R/W 0 R/W 0 12 11 NVMDAT[15:8] R/W R/W 0 0 4 3 NVMDAT[7:0] R/W R/W 0 0 10 9 8 R/W 0 R/W 0 R/W 0 2 1 0 R/W 0 R/W 0 R/W 0 Bits 15:0 – NVMDAT[15:0] NVM Data Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • NVMDATH: Accesses the high byte NVMDAT[15:8] • NVMDATL: Accesses the low byte NVMDAT[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 107 PIC18F06/16Q41 NVM - Nonvolatile Memory Module 10.5.6 TBLPTR Name:  Address:  TBLPTR 0x4F6 Table Pointer Register Bit 23 22 Access Reset Bit Access Reset Bit Access Reset 21 TBLPTR21 R/W 0 15 14 13 R/W 0 R/W 0 R/W 0 7 6 5 R/W 0 R/W 0 R/W 0 20 19 R/W 0 R/W 0 18 TBLPTR[20:16] R/W 0 17 16 R/W 0 R/W 0 10 9 8 R/W 0 R/W 0 R/W 0 2 1 0 R/W 0 R/W 0 R/W 0 12 11 TBLPTR[15:8] R/W R/W 0 0 4 3 TBLPTR[7:0] R/W R/W 0 0 Bit 21 – TBLPTR21 NVM Most Significant Address bit Value Description 1 Access Configuration, User ID, Device ID, and Revision ID spaces 0 Access Program Flash Memory space Bits 20:0 – TBLPTR[20:0] NVM Address bits Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • TBLPTRU: Accesses the upper byte TBLPTR[21:16] • TBLPTRH: Accesses the high byte TBLPTR[15:8] • TBLPTRL: Accesses the low byte TBLPTR[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 108 PIC18F06/16Q41 NVM - Nonvolatile Memory Module 10.5.7 TABLAT Name:  Address:  TABLAT 0x4F5 Table Latch Register Bit Access Reset 7 6 5 R/W 0 R/W 0 R/W 0 4 3 TABLAT[7:0] R/W R/W 0 0 2 1 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – TABLAT[7:0] The value of the NVM memory byte returned from the address contained in TBLPTR after a TBLRD command, or the data written to the latch by a TBLWT command. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 109 PIC18F06/16Q41 NVM - Nonvolatile Memory Module 10.6 Address Register Summary - NVM Name 0x00 ... 0x3F 0x40 0x41 0x42 NVMCON0 NVMCON1 NVMLOCK 0x43 NVMADR 0x46 NVMDAT 0x48 ... 0x04F4 0x04F5 0x04F6 Bit Pos. 7 6 5 4 3 2 1 0 Reserved 7:0 7:0 7:0 7:0 15:8 23:16 7:0 15:8 GO WRERR NVMCMD[2:0] NVMLOCK[7:0] NVMADR[7:0] NVMADR[15:8] NVMADR[21:16] NVMDAT[7:0] NVMDAT[15:8] Reserved TABLAT TBLPTR 7:0 7:0 15:8 23:16 © 2020-2021 Microchip Technology Inc. and its subsidiaries TABLAT[7:0] TBLPTR[7:0] TBLPTR[15:8] TBLPTR21 Preliminary Datasheet TBLPTR[20:16] DS40002214E-page 110 PIC18F06/16Q41 VIC - Vectored Interrupt Controller Module 11. VIC - Vectored Interrupt Controller Module 11.1 Overview The Vectored Interrupt Controller (VIC) module reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the CPU. This module includes the following major features: • • • • • • Interrupt Vector Table (IVT) with a unique vector for each interrupt source Fixed and ensured interrupt latency Programmable base address for IVT with lock Two user-selectable priority levels - High priority and low priority Two levels of context saving Interrupt state Status bits to indicate the current execution status of the CPU The VIC module assembles all of the interrupt request signals and resolves the interrupts based on both a fixed natural order priority (i.e., determined by the IVT), and a user-assigned priority (i.e., determined by the IPRx registers), thereby eliminating scanning of interrupt sources. 11.2 Interrupt Control and Status Registers The devices in this family implement the following registers for the interrupt controller: • • • • • • INTCON0, INTCON1 Control Registers PIRx - Peripheral Interrupt Status Registers PIEx - Peripheral Interrupt Enable Registers IPRx - Peripheral Interrupt Priority Registers IVTBASE Address Registers IVTLOCK Register Global interrupt control functions and external interrupts are controlled from the INTCON0 register. The INTCON1 register contains the status flags for the interrupt controller. The PIRx registers contain all of the interrupt request flags. Each source of interrupt has a Status bit, which is set by the respective peripherals or an external signal, and is either cleared via software or automatically cleared by hardware upon clearing of the interrupt condition, depending on the peripheral and bit. The PIEx registers contain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. The IPRx registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to either a high or low priority. The IVTBASE register is user-programmable and is used to determine the start address of the IVT and the IVTLOCK register is used to prevent any unintended writes to the IVTBASE register. There are two other Configuration bits that control the way the interrupt controller can be configured: The MVECEN and the IVT1WAY bits. The MVECEN bit determines whether the IVT is used to determine the interrupt priorities. The IVT1WAY bit determines the number of times the IVTLOCKED bit can be cleared and set after a device Reset. See the Interrupt Vector Table Address Calculation section for details. 11.3 Interrupt Vector Table The interrupt controller supports an IVT that contains the vector address location for each interrupt request source. The IVT resides in program memory, starting at the address location determined by IVTBASE. The IVT contains one vector for each source of interrupt. Each interrupt vector location contains the starting address of the associated Interrupt Service Routine (ISR). The MVECEN Configuration bit controls the availability of the vector table. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 111 PIC18F06/16Q41 VIC - Vectored Interrupt Controller Module 11.3.1 Interrupt Vector Table Base Address (IVTBASE) The start address of the vector table is user-programmable through the IVTBASE. The user must ensure the start address is such that it can encompass the entire vector table inside the program memory. Each vector address is a 16-bit word (or two address locations on PIC18 devices). For ‘n’ interrupt sources, there are ‘2n’ address locations necessary to hold the table, starting from IVTBASE as the first location. Thus, the starting address needs to be chosen such that the address range from IVTBASE to “IVTBASE+2n-1” can be encompassed within the program Flash memory. For example, if the highest vector number was 81, IVTBASE needs to be chosen such that “IVTBASE+0xA1” is less than the last memory location in program Flash memory. A programmable vector table base address is useful in situations to switch between different sets of vector tables, depending on the application. It can also be used when the application program needs to update the existing vector table (vector address values). Important:  It is required that the user assign an even address to IVTBASE for correct operation. 11.3.2 Interrupt Vector Table Contents MVECEN = 0 When MVECEN = 0, the address location pointed to by IVTBASE has a GOTO instruction for a high-priority interrupt. Similarly, the corresponding low-priority vector also has a GOTO instruction, which is executed in case of a low-priority interrupt. MVECEN = 1 When MVECEN = 1, the value in the vector table of each interrupt points to the address location of the first instruction of the Interrupt Service Routine, hence: ISR Location = Interrupt Vector Table entry HADR (and a data cycle is not occurring) or when CRCGO = 0. 4. 5. The CRCEN and CRCGO bits must be set before setting the SGO bit. See Table 13-2. Table 13-2. Scanner Operating Modes TRIGEN BURSTMD Scanner Operation 0 0 Memory access is requested when the CRC module is ready to accept data; the request is granted if no other higher priority source request is pending. 1 0 Memory access is requested when the CRC module is ready to accept data and trigger selection is true; the request is granted if no other higher priority source request is pending. x 1 Memory access is always requested; the request is granted if no other higher priority source request is pending. Note:  Refer to the “System Arbitration” and the “Memory Access Scheme” sections for more details about Priority selection and Memory Access Scheme. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 213 PIC18F06/16Q41 CRC - Cyclic Redundancy Check Module with Memory S... 13.12.9 SCANLADR Name:  Address:  SCANLADR 0x35A Scan Low Address Registers Bit 23 22 Access Reset Bit Access Reset Bit Access Reset 21 20 R/W 0 R/W 0 15 14 13 R/W 0 R/W 0 R/W 0 7 6 5 R/W 0 R/W 0 R/W 0 19 18 SCANLADRU[5:0] R/W R/W 0 0 12 11 SCANLADRH[7:0] R/W R/W 0 0 4 3 SCANLADRL[7:0] R/W R/W 0 0 17 16 R/W 0 R/W 0 10 9 8 R/W 0 R/W 0 R/W 0 2 1 0 R/W 0 R/W 0 R/W 0 Bits 21:16 – SCANLADRU[5:0] Scan Start/Current Address upper byte Upper bits of the current address to be fetched from, value increments on each fetch of memory. Bits 15:8 – SCANLADRH[7:0] Scan Start/Current Address high byte High byte of the current address to be fetched from, value increments on each fetch of memory. Bits 7:0 – SCANLADRL[7:0] Scan Start/Current Address low byte Low byte of the current address to be fetched from, value increments on each fetch of memory. Notes:  1. Registers SCANLADRU/H/L form a 22-bit value, but are not guarded for atomic or asynchronous access; registers may only be read or written while SGO = 0. 2. While SGO = 1, writing to this register is ignored. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 214 PIC18F06/16Q41 CRC - Cyclic Redundancy Check Module with Memory S... 13.12.10 SCANHADR Name:  Address:  SCANHADR 0x35D Scan High Address Registers Bit 23 22 Access Reset Bit Access Reset Bit Access Reset 21 20 R/W 1 R/W 1 15 14 13 R/W 1 R/W 1 R/W 1 7 6 5 R/W 1 R/W 1 R/W 1 19 18 SCANHADRU[5:0] R/W R/W 1 1 12 11 SCANHADRH[7:0] R/W R/W 1 1 4 3 SCANHADRL[7:0] R/W R/W 1 1 17 16 R/W 1 R/W 1 10 9 8 R/W 1 R/W 1 R/W 1 2 1 0 R/W 1 R/W 1 R/W 1 Bits 21:16 – SCANHADRU[5:0] Scan End Address Upper bits of the address at the end of the designated scan Bits 15:8 – SCANHADRH[7:0] Scan End Address High byte of the address at the end of the designated scan Bits 7:0 – SCANHADRL[7:0] Scan End Address Low byte of the address at the end of the designated scan Notes:  1. Registers SCANHADRU/H/L form a 22-bit value but are not guarded for atomic or asynchronous access; registers may only be read or written while SGO = 0. 2. While SGO = 1, writing to this register is ignored. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 215 PIC18F06/16Q41 CRC - Cyclic Redundancy Check Module with Memory S... 13.12.11 SCANTRIG Name:  Address:  SCANTRIG 0x361 SCAN Trigger Selection Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 TSEL[3:0] Access Reset R/W 0 R/W 0 Bits 3:0 – TSEL[3:0] Scanner Data Trigger Input Selection Table 13-3. Scanner Data Trigger Input Sources TSEL Value 1111 - 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Trigger Input Sources — CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT SMT1_OUT TMR4_Postscaler_OUT TMR3_OUT TMR2_Postscaler_OUT TMR1_OUT TMR0_OUT CLCKREF_OUT LFINTOSC(1) Note:  1. The number of implemented bits varies by device. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 216 PIC18F06/16Q41 CRC - Cyclic Redundancy Check Module with Memory S... 13.13 Register Summary - CRC Address Name 0x00 ... 0x034D Reserved 0x034E CRCDATA 0x0352 CRCOUT 0x0352 CRCSHIFT 0x0352 CRCXOR 0x0356 0x0357 0x0358 0x0359 CRCCON0 CRCCON1 CRCCON2 Reserved 0x035A SCANLADR 0x035D SCANHADR 0x0360 0x0361 SCANCON0 SCANTRIG Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 15:8 23:16 7:0 15:8 23:16 7:0 7:0 7 EN EN © 2020-2021 Microchip Technology Inc. and its subsidiaries 6 GO TRIGEN 5 BUSY SGO 4 3 2 CRCDATAL[7:0] CRCDATAH[7:0] CRCDATAU[7:0] CRCDATAT[7:0] CRCOUTL[7:0] CRCOUTH[7:0] CRCOUTU[7:0] CRCOUTT[7:0] CRCSHIFTL[7:0] CRCSHIFTH[7:0] CRCSHIFTU[7:0] CRCSHIFTT[7:0] CRCXORL[7:0] CRCXORH[7:0] CRCXORU[7:0] CRCXORT[7:0] ACCM SETUP[1:0] PLEN[4:0] DLEN[4:0] 1 0 SHIFTM FULL SCANLADRL[7:0] SCANLADRH[7:0] SCANLADRU[5:0] SCANHADRL[7:0] SCANHADRH[7:0] SCANHADRU[5:0] MREG BURSTMD TSEL[3:0] Preliminary Datasheet BUSY DS40002214E-page 217 PIC18F06/16Q41 Resets 14. Resets There are multiple ways to reset the device: • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Low-Power Brown-out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction • • • • • • Stack Overflow Stack Underflow Programming mode exit Memory Execution Violation Reset Main LDO Voltage Regulator Reset Configuration Memory Reset A simplified block diagram of the On-Chip Reset Circuit is shown in the block diagram below. Figure 14-1. Simplified Block Diagram of On-Chip Reset Circuit Re v. 10 -00 00 06 G 3/7/20 19 ICSP Programming Mode Exit RESET Instruction Memory Violation Main LDO Voltage Regulator Configuration Memory Stack Underflow Stack Overflow VPP /MCLR MCLRE WWDT Time-out/ Window violation Device Reset Power-on Reset VDD Brown-out Reset Power-up Timer LFINTOSC LPBOR Reset 2 PWRTS Note:  1. See the BOR Operating Modes table for BOR active conditions. 14.1 Power-on Reset (POR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The POR bit will be set to ‘0’ if a Power-on Reset has occurred. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 218 PIC18F06/16Q41 Resets 14.2 Brown-out Reset (BOR) The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. The BOR bit will be set to ‘0’ if a Brown-out Reset has occurred. The Brown-out Reset module has four operating modes controlled by the BOREN Configuration bits. The four operating modes are: • • • • BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off Refer to the BOR Operating Modes table for more information. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. Refer to the “Electrical Specifications” chapter for more details. 14.2.1 BOR Is Always On When the BOREN Configuration bits are programmed to ‘b11, the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. 14.2.2 BOR Is Off in Sleep When the BOREN Configuration bits are programmed to ‘b10, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. 14.2.3 BOR Controlled by Software When the BOREN Configuration bits are programmed to ‘b01, the BOR is controlled by the SBOREN bit. The device start-up is not delayed by the BOR Ready condition or the VDD level. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit. BOR protection selected by SBOREN bit is unchanged by Sleep. 14.2.4 BOR Is Always Off When the BOREN Configuration bits are programmed to ‘b00, the BOR is off at all times. The device start-up is not delayed by the BOR Ready condition or the VDD level. Table 14-1. BOR Operating Modes BOREN SBOREN Device Mode BOR Mode 11(1) 10 X Release of POR Wake-Up from Sleep X Active Wait for release of BOR (BORRDY = 1) Begins immediately Awake Active Wait for release of BOR (BORRDY = 1) N/A Sleep Hibernate N/A Wait for release of BOR (BORRDY = 1) X © 2020-2021 Microchip Technology Inc. and its subsidiaries Instruction Execution upon: Preliminary Datasheet DS40002214E-page 219 PIC18F06/16Q41 Resets ...........continued Instruction Execution upon: BOREN SBOREN Device Mode BOR Mode 01 00 1 X Active 0 X Hibernate X X Disabled Release of POR Wake-Up from Sleep Wait for release of BOR (BORRDY = 1) Begins immediately Begins immediately Note:  1. In this specific case, “Release of POR” and “Wake-up from Sleep”, there is no BOR ready delay in start-up. The BOR Ready flag (BORRDY = 1) will be set before the CPU is ready to execute instructions, because the BOR circuit is forced on by the BOREN bits. Figure 14-2. Brown-Out Situations Rev. 30-000092A 4/12/2017 VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset TPWRT(1) Note:  1. TPWRT delay only if the Configuration bits enable the Power-up Timer. 14.2.5 BOR and Bulk Erase BOR is forced ON during PFM Bulk Erase operations to make sure that the system code protection cannot be compromised by reducing VDD. During Bulk Erase, the BOR is enabled at the lowest BOR threshold level, even if it is configured to some other value. If VDD falls, the erase cycle will be aborted, but the device will not be reset. 14.3 Low-Power Brown-out Reset (LPBOR) The Low-Power Brown-out Reset (LPBOR) provides an additional BOR circuit for low-power operation. Refer to the figure below to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 220 PIC18F06/16Q41 Resets Figure 14-3. LPBOR, BOR, POR Relationship Rev. 30-000091B 6/21/2017 Any Reset BOR BOR Event REARM POR Event To PCON indicator bit POR LPBOR POR Event LPBOR Event Reset logic 14.3.1 Enabling LPBOR The LPBOR is controlled by the LPBOREN Configuration bit. When the device is erased, the LPBOR module defaults to disabled. 14.3.2 LPBOR Module Output The output of the LPBOR module indicates whether or not a Reset is to be asserted. This signal is OR’d with the Reset signal of the BOR module to provide the generic BOR signal, which goes to the PCON0 register and to the power control block. 14.4 MCLR Reset MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE and LVP Configuration bits (see the table below). The RMCLR bit will be set to ‘0’ if a MCLR has occurred. Table 14-2. MCLR Configuration 14.4.1 MCLRE LVP MCLR x 1 Enabled 1 0 Enabled 0 0 Disabled MCLR Enabled When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. Important:  An internal Reset event (RESET instruction, BOR, WWDT, POR, STKOVF, STKUNF) does not drive the MCLR pin low. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 221 PIC18F06/16Q41 Resets 14.4.2 MCLR Disabled When MCLR is disabled, the MCLR pin becomes input-only and pin functions such as internal weak pull-ups are under software control. 14.5 Windowed Watchdog Timer (WWDT) Reset The Windowed Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period or window set. The TO and PD bits in the STATUS register and the RWDT bit are changed to indicate a WDT Reset. The WDTWV bit indicates if the WDT Reset has occurred due to a time-out or a window violation. 14.6 RESET Instruction A RESET instruction will cause a device Reset. The RI bit will be set to ‘0’. See Table 14-3 for default conditions after a RESET instruction has occurred. 14.7 Stack Overflow/Underflow Reset The device can be reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits indicate the Reset condition. These Resets are enabled by setting the STVREN Configuration bit. 14.8 Programming Mode Exit Upon exit of Programming mode, the device will operate as if a POR had just occurred. 14.9 Power-up Timer (PWRT) The Power-up Timer provides a selected time-out duration on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for VDD to rise to an acceptable level. The Power-up Timer is selected by setting the PWRTS Configuration bits accordingly. The Power-up Timer starts after the release of the POR and BOR/LPBOR if enabled, as shown in Figure 14-4. 14.10 Start-Up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. 3. Power-up Timer runs to completion (if enabled). Oscillator Start-up Timer runs to completion (if required for selected oscillator source). MCLR must be released (if enabled). The total time-out will vary based on the oscillator configuration and Power-up Timer configuration. The Power-up Timer and Oscillator Start-up Timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and Oscillator Start-up Timer will expire. Upon bringing MCLR high, the device will begin execution after 10 FOSC cycles (see the figure below). This is useful for testing purposes or to synchronize more than one device operating in parallel. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 222 PIC18F06/16Q41 Resets Figure 14-4. Reset Start-Up Sequence Rev. 30-000093A 4/12/2017 VDD Internal POR TPWRT Power-up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 14.10.1 Memory Execution Violation A memory execution violation Reset occurs if executing an instruction being fetched from outside the valid execution area. The invalid execution areas are: 1. Addresses outside implemented program memory. 2. Storage Area Flash (SAF) inside program memory, if it is enabled. When a memory execution violation is generated, the device is reset and the MEMV bit is cleared to signal the cause of the Reset. The MEMV bit must be set in the user code after a memory execution violation Reset has occurred to detect further violation Resets. 14.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON0 registers are updated to indicate the cause of the Reset. The following table shows the Reset conditions of these registers. Table 14-3. Reset Condition for Special Registers Program Counter STATUS Register(1,2) PCON0 Register PCON1 Register Power-on Reset 0 -110 0000 0011 110x ---- -111 Brown-out Reset 0 -110 0000 0011 11u0 ---- -u1u Condition © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 223 PIC18F06/16Q41 Resets ...........continued Program Counter STATUS Register(1,2) PCON0 Register PCON1 Register MCLR Reset during normal operation 0 -uuu uuuu uuuu 0uuu ---- -uuu MCLR Reset during Sleep 0 -10u uuuu uuuu 0uuu ---- -uuu WDT Time-out Reset 0 -0uu uuuu uuu0 uuuu ---- -uuu WDT Wake-up from Sleep PC + 2 -00u uuuu uuuu uuuu ---- -uuu 0 -uuu uuuu uu0u uuuu ---- -uuu Interrupt Wake-up from Sleep PC + 2(3) -10u uuuu uuuu uuuu ---- -uuu RESET Instruction Executed 0 -uuu uuuu uuuu u0uu ---- -uuu Stack Overflow Reset (STVREN = 1) 0 -uuu uuuu 1uuu uuuu ---- -uuu Stack Underflow Reset (STVREN = 1) 0 -uuu uuuu u1uu uuuu ---- -uuu Data Protection (Fuse Fault) 0 -uuu uuuu uuuu uuuu ---- -uu0 VREG or ULP Ready Fault 0 -110 0000 0011 110u ---- -0u1 Memory Violation Reset 0 -uuu uuuu uuuu uuuu ---- -u0u Condition WWDT Window Violation Reset Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Notes:  1. If a Status bit is not implemented, that bit will be read as ‘0’. 2. 3. 14.12 Status bits Z, C, DC are reset by POR/BOR. When the wake-up is due to an interrupt and Global Interrupt Enable (GIE) bit is set, the return address is pushed on the stack and PC is loaded with the corresponding interrupt vector (depending on source, high or low priority) after execution of PC + 2. Power Control (PCON0/PCON1) Registers The Power Control (PCON0/PCON1) registers contain flag bits to differentiate between the following Reset events: • • • • • • • • • Brown-out Reset (BOR) Power-on Reset (POR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Watchdog Window Violation (WDTWV) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) Configuration Memory Reset (RCM) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 224 PIC18F06/16Q41 Resets • • Memory Violation Reset (MEMV) Main LDO Voltage Regulator Reset (RVREG) Hardware will change the corresponding register bit or bits as a result of the Reset event. Bits for other Reset events remain unchanged. See Table 14-3 for more details. Software will reset the bit to the Inactive state after restart (hardware will not reset the bit). Software may also set any PCON0 bit to the Active state, so that user code may be tested, but no Reset action will be generated. 14.13 Register Definitions: Power Control © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 225 PIC18F06/16Q41 Resets 14.13.1 BORCON Name:  Address:  BORCON 0x049 Brown-out Reset Control Register Bit Access Reset 7 SBOREN R/W 1 6 5 4 3 2 1 0 BORRDY R q Bit 7 – SBOREN Software Brown-out Reset Enable Reset States: POR/BOR = 1 All Other Resets = u Value Condition Description — If BOREN ≠ 01 SBOREN is read/write, but has no effect on the BOR 1 If BOREN = 01 BOR Enabled 0 If BOREN = 01 BOR Disabled Bit 0 – BORRDY Brown-out Reset Circuit Ready Status Reset States: POR/BOR = q All Other Resets = u Value Description 1 The Brown-out Reset Circuit is active and armed 0 The Brown-out Reset Circuit is disabled or is warming up © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 226 PIC18F06/16Q41 Resets 14.13.2 PCON0 Name:  Address:  PCON0 0x4F0 Power Control Register 0 Bit Access Reset 7 STKOVF R/W/HS 0 6 STKUNF R/W/HS 0 5 WDTWV R/W/HC 1 4 RWDT R/W/HC 1 3 RMCLR R/W/HC 1 2 RI R/W/HC 1 1 POR R/W/HC 0 0 BOR R/W/HC q Bit 7 – STKOVF Stack Overflow Flag Reset States: POR/BOR = 0 All Other Resets = q Value Description 1 A Stack Overflow occurred (more CALLs than fit on the stack) 0 A Stack Overflow has not occurred or set to ‘0’ by firmware Bit 6 – STKUNF Stack Underflow Flag Reset States: POR/BOR = 0 All Other Resets = q Value Description 1 A Stack Underflow occurred (more RETURNs than CALLs) 0 A Stack Underflow has not occurred or set to ‘0’ by firmware Bit 5 – WDTWV Watchdog Window Violation Flag Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 A WDT window violation has not occurred or set to ‘1’ by firmware 0 A CLRWDT instruction was issued when the WDT Reset window was closed (set to ‘0’ in hardware when a WDT window violation Reset occurs) Bit 4 – RWDT WDT Reset Flag Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 A WDT overflow/Time-out Reset has not occurred or set to ‘1’ by firmware 0 A WDT overflow/Time-out Reset has occurred (set to ‘0’ in hardware when a WDT Reset occurs) Bit 3 – RMCLR  MCLR Reset Flag Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 A MCLR Reset has not occurred or set to ‘1’ by firmware 0 A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs) Bit 2 – RI  RESET Instruction Flag Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 A RESET instruction has not been executed or set to ‘1’ by firmware 0 A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET instruction) Bit 1 – POR Power-on Reset Status © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 227 PIC18F06/16Q41 Resets Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 No Power-on Reset occurred or set to ‘1’ by firmware 0 A Power-on Reset occurred (set to ‘0’ in hardware when a Power-on Reset occurs) Bit 0 – BOR Brown-out Reset Status Reset States: POR/BOR = q All Other Resets = u Value Description 1 No Brown-out Reset occurred or set to ‘1’ by firmware 0 A Brown-out Reset occurred (set to ‘0’ in hardware when a Brown-out Reset occurs) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 228 PIC18F06/16Q41 Resets 14.13.3 PCON1 Name:  Address:  PCON1 0x4F1 Power Control Register 1 Bit 7 6 5 4 3 Access Reset 2 RVREG R/W/HC 1 1 MEMV R/W/HC 0 0 RCM R/W/HC q Bit 2 – RVREG Main LDO Voltage Regulator Reset Flag Reset States: POR/BOR = 1 All Other Resets = q Value Description 1 No LDO or ULP “ready” Reset has occurred or set to ‘1’ by firmware 0 LDO or ULP “ready” Reset has occurred (VDDCORE reached its minimum spec) Bit 1 – MEMV Memory Violation Reset Flag Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 No memory violation Reset occurred or set to ‘1’ by firmware 0 A memory violation Reset occurred (set to ‘0’ in hardware when a Memory Violation occurs) Bit 0 – RCM Configuration Memory Reset Flag Reset States: POR/BOR = q All Other Resets = u Value Description 1 A Reset occurred due to corruption of the configuration and/or calibration data latches 0 The configuration and calibration latches have not been corrupted © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 229 PIC18F06/16Q41 Resets 14.14 Address 0x00 ... 0x48 0x49 0x4A ... 0x04EF 0x04F0 0x04F1 Register Summary - BOR Control and Power Control Name Bit Pos. 7 7:0 SBOREN 7:0 7:0 STKOVF 6 5 4 3 2 1 0 Reserved BORCON BORRDY Reserved PCON0 PCON1 © 2020-2021 Microchip Technology Inc. and its subsidiaries STKUNF WDTWV RWDT RMCLR Preliminary Datasheet RI RVREG POR MEMV BOR RCM DS40002214E-page 230 PIC18F06/16Q41 WWDT - Windowed Watchdog Timer 15. WWDT - Windowed Watchdog Timer A Watchdog Timer (WDT) is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. A Watchdog Timer is typically used to recover the system from unexpected events. The Windowed Watchdog Timer (WWDT) differs from nonwindowed operation in that CLRWDT instructions are only accepted when they are performed within a specific window during the time-out period. The WWDT has the following features: • Selectable clock source • Multiple operating modes – WWDT is always on – WWDT is off when in Sleep – WWDT is controlled by software – WWDT is always off • Configurable time-out period from 1 ms to 256s (nominal) • Configurable window size from 12.5% to 100% of the time-out period • Multiple Reset conditions © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 231 PIC18F06/16Q41 WWDT - Windowed Watchdog Timer Figure 15-1. Windowed Watchdog Timer Block Diagram WWDT Armed WDT Window Violation Window Closed CLRWDT Window Sizes Comparator WINDOW RESET .. . See WDTCON1 Register .. . R 18-bit Prescale Counter E CS PS R 5-bit WDT Counter Overflow Latch WDT Time-out WDTE = b01 SEN WDTE = b11 WDTE = b10 Sleep 15.1 Independent Clock Source The WWDT can derive its time base from either the 31 KHz LFINTOSC or 31.25 kHz MFINTOSC internal oscillators, depending on the value of WDT Operating Mode (WDTE) Configuration bits. If WDTE = ‘b1x, then the clock source will be enabled depending on the WDTCCS Configuration bits. If WDTE = ‘b01, the SEN bit will be set by software to enable WWDT, and the clock source is enabled by the CS bits. Time intervals in this chapter are based on a minimum nominal interval of 1 ms. See the device Electrical Specifications for LFINTOSC and MFINTOSC tolerances. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 232 PIC18F06/16Q41 WWDT - Windowed Watchdog Timer 15.2 WWDT Operating Modes The Windowed Watchdog Timer module has four operating modes that are controlled by the WDTE Configuration bit. The table below summarizes the different WWDT operating modes. Table 15-1. WWDT Operating Modes WDTE SEN Device Mode WWDT Mode 11 X X Active 10 X Awake Active Sleep Disabled 1 X Active 0 X Disabled X X Disabled 01 00 15.2.1 WWDT Is Always On When the WDTE Configuration bits are set to ‘b11, the WWDT is always on. WWDT protection is active during Sleep. 15.2.2 WWDT Is Off in Sleep When the WDTE Configuration bits are set to ‘b10, the WWDT is on, except in Sleep mode. WWDT protection is not active during Sleep. 15.2.3 WWDT Controlled by Software hen the WDTE Configuration bits are set to ‘b01, the WWDT is controlled by the SEN bit. WWDT protection is unchanged by Sleep. See Table 15-1 for more details. 15.3 Time-Out Period When the WDTCPS Configuration bits are set to the default value of ‘b11111, the PS bits set the time-out period from 1 ms to 256 seconds (nominal). If any value other than the default value is assigned to the WDTCPS Configuration bits, then the timer period will be based on the WDTCPS Configuration bits. After a Reset, the default time-out period is 2s. 15.4 Watchdog Window The Windowed Watchdog Timer has an optional Windowed mode that is controlled by either the WDTCWS Configuration bits or the WINDOW bits. In the Windowed mode (WINDOW < ‘b1111), the CLRWDT instruction must occur within the allowed window of the WDT period. Any CLRWDT instruction that occurs outside of this window will trigger a window violation and will cause a WWDT Reset, similar to a WWDT time-out. See Figure 15-2 for an example. When the WDTCWS Configuration bits are ‘b111 then the window size is controlled by the WINDOW bits, otherwise the window size is controlled by the WDTCWS bits. The five Most Significant bits of the WDTTMR register are used to determine whether the window is open, as defined by the window size. In the event of a window violation, a Reset will be generated and the WDTWV bit of the PCON0 register will be cleared. This bit is set by a POR and can be set by software. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 233 PIC18F06/16Q41 WWDT - Windowed Watchdog Timer Figure 15-2. Window Period and Delay CLRWDT Instruction (or other WDT Reset) Window Period Window Closed Window Open Window Delay (window violation can occur) 15.5 Time-out Event Clearing the Watchdog Timer The Watchdog Timer is cleared when any of the following conditions occur: • Any Reset • A valid CLRWDT instruction is executed • • • • • 15.5.1 The device enters Sleep The devices exits Sleep by Interrupt The WWDT is disabled The Oscillator Start-up Timer (OST) is running Any write to the WDTCON0 or WDTCON1 registers CLRWDT Considerations (Windowed Mode) When in Windowed mode, the WWDT must be armed before a CLRWDT instruction will clear the timer. This is performed by reading the WDTCON0 register. Executing a CLRWDT instruction without performing such an arming action will trigger a window violation regardless of whether the window is open or not. See Table 15-2 for more information. 15.6 Operation During Sleep When the device enters Sleep, the Watchdog Timer is cleared. If the WWDT is enabled during Sleep, the Watchdog Timer resumes counting. When the device exits Sleep, the Watchdog Timer is cleared again. The Watchdog Timer remains clear until the Oscillator Start-up Timer (OST) completes, if enabled. When a WWDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. The RWDT bit in the PCON0 register indicates that a Watchdog Reset has occurred. Table 15-2. WWDT Clearing Conditions Conditions WWDT WDTE = ‘b00 WDTE = ‘b01 and SEN = 0 WDTE = ‘b10 and enter Sleep Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) © 2020-2021 Microchip Technology Inc. and its subsidiaries Unaffected Preliminary Datasheet DS40002214E-page 234 PIC18F06/16Q41 WWDT - Windowed Watchdog Timer 15.7 Register Definitions: Windowed Watchdog Timer Control Long bit name prefixes for the Windowed Watchdog Timer peripherals are shown in the following table. Refer to the "Long Bit Names" section in the “Register and Bit Naming Conventions” chapter for more information. Table 15-3. WWDT Long Bit Name Prefixes Peripheral Bit Name Prefix WDT WDT © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 235 PIC18F06/16Q41 WWDT - Windowed Watchdog Timer 15.7.1 WDTCON0 Name:  Address:  WDTCON0 0x078 Watchdog Timer Control Register 0 Bit 7 6 Access Reset 5 4 R/W q R/W q 3 PS[4:0] R/W q 2 1 R/W q R/W q 0 SEN R/W 0 Bits 5:1 – PS[4:0]  Watchdog Timer Prescaler Select(2) Value Description 11111 to Reserved. Results in minimum interval (1 ms) 10011 10010 1:8388608 (223) (Interval 256s nominal) 10001 1:4194304 (222) (Interval 128s nominal) 10000 1:2097152 (221) (Interval 64s nominal) 01111 1:1048576 (220) (Interval 32s nominal) 01110 1:524288 (219) (Interval 16s nominal) 01101 1:262144 (218) (Interval 8s nominal) 01100 1:131072 (217) (Interval 4s nominal) 01011 1:65536 (Interval 2s nominal) (Reset value) 01010 1:32768 (Interval 1s nominal) 01001 1:16384 (Interval 512 ms nominal) 01000 1:8192 (Interval 256 ms nominal) 00111 1:4096 (Interval 128 ms nominal) 00110 1:2048 (Interval 64 ms nominal) 00101 1:1024 (Interval 32 ms nominal) 00100 1:512 (Interval 16 ms nominal) 00011 1:256 (Interval 8 ms nominal) 00010 1:128 (Interval 4 ms nominal) 00001 1:64 (Interval 2 ms nominal) 00000 1:32 (Interval 1 ms nominal) Bit 0 – SEN Software Enable/Disable for Watchdog Timer Value Condition Description x 1 0 x If WDTE = 1x If WDTE = 01 If WDTE = 01 If WDTE = 00 This bit is ignored WDT is turned on WDT is turned off This bit is ignored Notes:  1. When the WDTCPS Configuration bits = ‘b11111, the Reset value (q) of WDTPS is ‘b01011. Otherwise, the Reset value of WDTPS is equal to the WDTCPS in Configuration bits. 2. When the WDTCPS in Configuration bits ≠ ‘b11111, these bits are read-only. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 236 PIC18F06/16Q41 WWDT - Windowed Watchdog Timer 15.7.2 WDTCON1 Name:  Address:  WDTCON1 0x079 Watchdog Timer Control Register 1 Bit 7 Access Reset 6 5 CS[2:0] R/W q R/W q 4 3 2 R/W q R/W q 1 WINDOW[2:0] R/W q 0 R/W q Bits 6:4 – CS[2:0]  Watchdog Timer Clock Select(1,3) CS Clock Source 111-100 011 010 001 000 Reserved EXTOSC SOSC MFINTOSC (31.25 kHz) LFINTOSC (31 kHz) Bits 2:0 – WINDOW[2:0]  Watchdog Timer Window Select(2,4) WINDOW Window Delay Percent of Time Window Opening Percent of Time 111 110 101 100 011 010 001 000 N/A 12.5 25 37.5 50 62.5 75 87.5 100 87.5 75 62.5 50 37.5 25 12.5 Notes:  1. When the WDTCCS in Configuration bits = ‘0b111, the Reset value of WDTCS is ‘b000. 2. 3. The Reset value (q) of WINDOW is determined by the value of WDTCWS in the Configuration bits. When the WDTCCS in Configuration bits ≠ ‘b111, these bits are read-only. 4. When the WDTCWS in Configuration bits ≠ ‘b111, these bits are read-only. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 237 PIC18F06/16Q41 WWDT - Windowed Watchdog Timer 15.7.3 WDTPSH Name:  Address:  WDTPSH 0x07B WWDT Prescaler Select Register (Read-Only) Bit 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 PSCNTH[7:0] Access Reset R 0 R 0 R 0 R 0 Bits 7:0 – PSCNTH[7:0]  Prescaler Select High Byte(1) Note:  1. The 18-bit WDT prescaler value, PSCNT[17:0] includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR registers. PSCNT[17:0] is intended for debug operations and will be read during normal operation. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 238 PIC18F06/16Q41 WWDT - Windowed Watchdog Timer 15.7.4 WDTPSL Name:  Address:  WDTPSL 0x07A WWDT Prescaler Select Register (Read-Only) Bit 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 PSCNTL[7:0] Access Reset R 0 R 0 R 0 R 0 Bits 7:0 – PSCNTL[7:0]  Prescaler Select Low Byte(1) Note:  1. The 18-bit WDT prescaler value, PSCNT[17:0] includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR registers. PSCNT[17:0] is intended for debug operations and will be read during normal operation. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 239 PIC18F06/16Q41 WWDT - Windowed Watchdog Timer 15.7.5 WDTTMR Name:  Address:  WDTTMR 0x07C WDT Timer Register (Read-Only) Bit Access Reset 7 6 R 0 R 0 5 TMR[4:0] R 0 4 3 R 0 2 STATE R 0 R 0 1 0 PSCNT[17:16] R 0 R 0 Bits 7:3 – TMR[4:0] Watchdog Window Value WINDOW 111 110 101 100 011 010 001 000 WDT Window State Open Percent Closed Open N/A 00000-00011 00000-00111 00000-01011 00000-01111 00000-10011 00000-10111 00000-11011 00000-11111 00100-11111 01000-11111 01100-11111 10000-11111 10100-11111 11000-11111 11100-11111 100 87.5 75 62.5 50 37.5 25 12.5 Bit 2 – STATE WDT Armed Status Value Description 1 WDT is armed 0 WDT is not armed Bits 1:0 – PSCNT[17:16]  Prescaler Select Upper Byte(1) Note:  1. The 18-bit WDT prescaler value, PSCNT[17:0] includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR registers. PSCNT[17:0] is intended for debug operations and will not be read during normal operation. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 240 PIC18F06/16Q41 WWDT - Windowed Watchdog Timer 15.8 Address 0x00 ... 0x77 0x78 0x79 0x7A 0x7B 0x7C Register Summary - WDT Control Name Bit Pos. 7 6 5 4 3 2 1 0 Reserved WDTCON0 WDTCON1 WDTPSL WDTPSH WDTTMR 7:0 7:0 7:0 7:0 7:0 © 2020-2021 Microchip Technology Inc. and its subsidiaries PS[4:0] SEN CS[2:0] WINDOW[2:0] PSCNTL[7:0] PSCNTH[7:0] TMR[4:0] Preliminary Datasheet STATE PSCNT[17:16] DS40002214E-page 241 PIC18F06/16Q41 DMA - Direct Memory Access 16. DMA - Direct Memory Access The Direct Memory Access (DMA) module is designed to service data transfers between different memory regions directly, without intervention from the CPU. By eliminating the need for CPU-intensive management of handling interrupts intended for data transfers, the CPU now can spend more time on other tasks. The DMA modules can be independently programmed to transfer data between different memory locations, move different data sizes, and use a wide range of hardware triggers to initiate transfers. The DMA modules can even be programmed to work together, to carry out more complex data transfers without CPU overhead. Key features of the DMA module include: • Support access to the following memory regions: – GPR and SFR space (R/W) – Program Flash memory (R only) – Data EEPROM memory (R only) • Programmable priority between the DMA and CPU operations. Refer to the “System Arbitration” section in the “PIC18 CPU” chapter for details. • Programmable Source and Destination Address modes: – Fixed address – Post-increment address – Post-decrement address • Programmable source and destination sizes • Source and Destination Pointer register, dynamically updated and reloadable • Source and Destination Count register, dynamically updated and reloadable • Programmable auto-stop based on source or destination counter • Software triggered transfers • Multiple user-selectable sources for hardware triggered transfers • Multiple user-selectable sources for aborting DMA transfers 16.1 DMA Registers The operation of the DMA module is controlled by the following registers: • • • • • • • • • • • • • DMA Instance Selection (DMASELECT) register Control (DMAnCON0, DMAnCON1) registers Data Buffer (DMAnBUF) register Source Start Address (DMAnSSA) register Source Pointer (DMAnSPTR) register Source Message Size (DMAnSSZ) register Source Count (DMAnSCNT) register Destination Start Address (DMAnDSA) register Destination Pointer (DMAnDPTR) register Destination Message Size (DMAnDSZ) register Destination Count (DMAnDCNT) register Start Interrupt Request Source (DMAnSIRQ) register Abort Interrupt Request Source (DMAnAIRQ) register The registers are detailed in Register Definitions: DMA. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 242 PIC18F06/16Q41 DMA - Direct Memory Access 16.2 DMA Organization The DMA module is designed to move data by using the existing instruction bus and data bus without the need for any dual-porting of memory or peripheral systems (Figure 16-1). The DMA accesses the required bus when granted by the system arbiter. Figure 16-1. DMA Functional Block Diagram Rev. 10-000271A 11/8/2018 DMA1 Control Registers Source Start Address Source Size Destination Start Address .. .. .       Program Flash Memory System Arbiter Destination Size     Data EEPROM GPR/SFR RAM Space DMAn Control Registers Source Start Address Source Size Priority Destination Start Address Destination Size Depending on the priority of the DMA with respect to CPU execution (refer to the “Memory Access Scheme” section in the “PIC18 CPU” chapter for more information), the DMA Controller can move data through two methods: • • 16.3 Stalling the CPU execution until it has completed its transfers (DMA has higher priority over the CPU in this mode of operation) Utilizing unused CPU cycles for DMA transfers (CPU has higher priority over the DMA in this mode of operation). Unused CPU cycles are referred to as bubbles, which are instruction cycles available for use by the DMA to perform read and write operations. In this way, the effective bandwidth for handling data is increased; at the same time, DMA operations can proceed without causing a processor stall. DMA Interface The DMA module transfers data from the source to the destination one byte at a time, this smallest data movement is called a DMA data transaction. A DMA message refers to one or more DMA data transactions. Each DMA data transaction consists of two separate actions: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 243 PIC18F06/16Q41 DMA - Direct Memory Access • • Reading the source address memory and storing the value in the DMA Buffer register Writing the contents of the DMA Buffer register to the destination address memory Important:  DMA data movement is a two-cycle operation. The XIP bit is a Status bit to indicate whether or not the data in the DMAnBUF register has been written to the destination address. If the bit is set, then data is waiting to be written to the destination. If clear, it means that either data has been written to the destination or that no source read has occurred. The DMA has read access to PFM, Data EEPROM, and SFR/GPR space, and write access to SFR/GPR space. Based on these memory access capabilities, the DMA can support the following memory transactions: Table 16-1. DMA Memory Access Read Source Write Destination Program Flash Memory GPR Program Flash Memory SFR Data EE GPR Data EE SFR GPR GPR GPR SFR SFR GPR SFR SFR Important:  Even though the DMA module has access to all memory and peripherals that are also available to the CPU, it is recommended that the DMA does not access any register that is part of the system arbitration. The DMA, as a system arbitration client must not be read or written by itself or by another DMA instantiation. The following sections discuss the various control interfaces required for DMA data transfers. 16.3.1 Special Function Registers with DMA Access only The DMA can transfer data to any GPR or SFR location. For better user accessibility, some of the more commonly used SFR spaces have their mirror registers placed in a separate data memory location. These mirror registers can be only accessed by the DMA module through the DMA Source and Destination Address registers. The figure below shows the register map for these registers. These registers are useful to multiple peripherals together like the Timers, PWMs and also other DMA modules using one of the DMA modules. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 244 PIC18F06/16Q41 DMA - Direct Memory Access Figure 16-2. Special Function Register Map (DMA Access Only) 16.3.2 40FFh 40FEh 40FDh 40FCh 40FBh 40FAh 40F9h 40F8h 40F7h 40F6h 40F5h 40F4h 40F3h 40F2h 40F1h 40F0h 40EFh 40EEh 40EDh 40ECh 40CBh 40EAh 40E9h 40E8h 40E7h 40E6h 40E5h 40E4h 40E3h 40E2h 40E1h 40E0h ADPREH_M2 ADPREL_M2 ADRESH_M2 ADRESL_M2 ADPCH_M2 ADCAP_M2 ADACQH_M2 ADACQL_M2 ADPREVH_M2 ADPREVL_M2 ADRPT_M2 ADCNT_M2 ADACCU_M2 ADACCH_M2 ADACCL_M2 ADFLTRH_M2 ADFLTRL_M2 ADSTPTH_M2 ADSTPTL_M2 ADERRH_M2 ADERRL_M2 ADUTHH_M2 ADUTHL_M2 ADLTHH_M2 ADLTHL_M2 40DFh 40DEh 40DDh 40DCh 40DBh 40DAh 40D9h 40D8h 40D7h 40D6h 40D5h 40D4h 40D3h 40D2h 40D1h 40D0h 40CFh 40CEh 40CDh 40CCh 40CBh 40CAh 40C9h 40C8h 40C7h 40C6h 40C5h 40C4h 40C3h 40C2h 40C1h 40C0h - 40BFh 40BEh 40BDh 40BCh 40BBh 40BAh 40B9h 40B8h 40B7h 40B6h 40B5h 40B4h 40B3h 40B2h 40B1h 40B0h 40AFh 40AEh 40ADh 40ACh 40ABh 40AAh 40A9h 40A8h 40A7h 40A6h 40A5h 40A4h 40A3h 40A2h 40A1h 40A0h - 409Fh 409Eh 409Dh 409Ch 409Bh 409Ah 4099h 4098h 4097h 4096h 4095h 4094h 4093h 4092h 4091h 4090h 408Fh 408Eh 408Dh 408Ch 408Bh 408Ah 4089h 4088h 4087h 4086h 4085h 4084h 4083h 4082h 4081h 4080h - 407Fh 407Eh 407Dh 407Ch 407Bh 407Ah 4079h 4078h 4077h 4076h 4075h 4074h 4073h 4072h 4071h 4070h 406Fh 406Eh 406Dh 406Ch 406Bh 406Ah 4069h 4068h 4067h 4066h 4065h 4064h 4063h 4062h 4061h 4060h ADPREH_M1 ADPREL_M1 ADRESH_M1 ADRESL_M1 ADPCH_M1 ADCLK_M1 ADACT_M1 ADREF_M1 ADCON3_M1 ADCON2_M1 ADCON1_M1 ADCON0_M1 ADCAP_M1 ADACQH_M1 ADACQL_M1 ADPREVH_M1 ADPREVL_M1 ADRPT_M1 ADCNT_M1 ADACCU_M1 ADACCH_M1 ADACCL_M1 ADFLTRH_M1 ADFLTRL_M1 ADSTPTH_M1 ADSTPTL_M1 ADERRH_M1 ADERRL_M1 ADUTHH_M1 ADUTHL_M1 ADLTHH_M1 ADLTHL_M1 405Fh 405Eh 405Dh 405Ch 405Bh 405Ah 4059h 4058h 4057h 4056h 4055h 4054h 4053h 4052h 4051h 4050h 404Fh 404Eh 404Dh 404Ch 404Bh 404Ah 4049h 4048h 4047h 4046h 4045h 4044h 4043h 4042h 4041h 4040h T4PR_M1 T2PR_M1 CCPR1H_M2 CCPR1L_M2 403Fh 403Eh 403Dh 403Ch 403Bh 403Ah 4039h 4038h 4037h 4036h 4035h 4034h 4033h 4032h 4031h 4030h 402Fh 402Eh 402Dh 402Ch 402Bh 402Ah 4029h 4028h 4027h 4026h 4025h 4024h 4023h 4022h 4021h 4020h PWM3PRH_M1 PWM3PRL_M1 PWM3S1P2H_M2 PWM3S1P2L_M2 PWM3S1P1H_M3 PWM3S1P1L_M3 PWM2PRH_M1 PWM2PRL_M1 PWM2S1P2H_M2 PWM2S1P2L_M2 PWM2S1P1H_M3 PWM2S1P1L_M3 PWM1PRH_M1 PWM1PRL_M1 PWM1S1P2H_M2 PWM1S1P2L_M2 PWM1S1P1H_M3 PWM1S1P1L_M3 401Fh 401Eh 401Dh 401Ch 401Bh 401Ah 4019h 4018h 4017h 4016h 4015h 4014h 4013h 4012h 4011h 4010h 400Fh 400Eh 400Dh 400Ch 400Bh 400Ah 4009h 4008h 4007h 4006h 4005h 4004h 4003h 4002h 4001h 4000h PWM3S1P2H_M1 PWM3S1P2L_M1 PWM3S1P1H_M2 PWM3S1P1L_M2 PWM2S1P2H_M1 PWM2S1P2L_M1 PWM2S1P1H_M2 PWM2S1P1L_M2 PWM1S1P2H_M1 PWM1S1P2L_M1 PWM1S1P1H_M2 PWM1S1P1L_M2 PWM3S1P1H_M1 PWM3S1P1L_M1 PWM2S1P1H_M1 PWM2S1P1L_M1 PWM1S1P1H_M1 PWM1S1P1L_M1 CCPR1H_M1 CCPR1L_M1 41FFh 41FEh 41FDh 41FCh 41FBh 41FAh 41F9h 41F8h 41F7h 41F6h 41F5h 41F4h 41F3h 41F2h 41F1h 41F0h 41EFh 41EEh 41EDh 41ECh 41CBh 41EAh 41E9h 41E8h 41E7h 41E6h 41E5h 41E4h 41E3h 41E2h 41E1h 41E0h TMR3H_M1 TMR3L_M1 TMR1H_M1 TMR1L_M1 IOCCF_M1 IOCBF_M1 IOCAF_M1 41DFh 41DEh 41DDh 41DCh 41DBh 41DAh 41D9h 41D8h 41D7h 41D6h 41D5h 41D4h 41D3h 41D2h 41D1h 41D0h 41CFh 41CEh 41CDh 41CCh 41CBh 41CAh 41C9h 41C8h 41C7h 41C6h 41C5h 41C4h 41C3h 41C2h 41C1h 41C0h - 41BFh 41BEh 41BDh 41BCh 41BBh 41BAh 41B9h 41B8h 41B7h 41B6h 41B5h 41B4h 41B3h 41B2h 41B1h 41B0h 41AFh 41AEh 41ADh 41ACh 41ABh 41AAh 41A9h 41A8h 41A7h 41A6h 41A5h 41A4h 41A3h 41A2h 41A1h 41A0h - 419Fh 419Eh 419Dh 419Ch 419Bh 419Ah 4199h 4198h 4197h 4196h 4195h 4194h 4193h 4192h 4191h 4190h 418Fh 418Eh 418Dh 418Ch 418Bh 418Ah 4189h 4188h 4187h 4186h 4185h 4184h 4183h 4182h 4181h 4180h - 417Fh 417Eh 417Dh 417Ch 417Bh 417Ah 4179h 4178h 4177h 4176h 4175h 4174h 4173h 4172h 4171h 4170h 416Fh 416Eh 416Dh 416Ch 416Bh 416Ah 4169h 4168h 4167h 4166h 4165h 4164h 4163h 4162h 4161h 4160h - 415Fh 415Eh 415Dh 415Ch 415Bh 415Ah 4159h 4158h 4157h 4156h 4155h 4154h 4153h 4152h 4151h 4150h 414Fh 414Eh 414Dh 414Ch 414Bh 414Ah 4149h 4148h 4147h 4146h 4145h 4144h 4143h 4142h 4141h 4140h DMAnSIRQ_DMA4 DMAnAIRQ_DMA4 DMAnCON1_DMA4 DMAnCON0_DMA4 DMAnSSAU_DMA4 DMAnSSAH_DMA4 DMAnSSAL_DMA4 DMAnSSZH_DMA4 DMAnSSZL_DMA4 DMAnSPTRU_DMA4 DMAnSPTRH_DMA4 DMAnSPTRL_DMA4 DMAnSCNTH_DMA4 DMAnSCNTL_DMA4 DMAnDSAH_DMA4 DMAnDSAL_DMA4 DMAnDSZH_DMA4 DMAnDSZL_DMA4 DMAnDPTRH_DMA4 DMAnDPTRL_DMA4 DMAnDCNTH_DMA4 DMAnDCNTL_DMA4 DMAnBUF_DMA4 DMAnSIRQ_DMA3 DMAnAIRQ_DMA3 DMAnCON1_DMA3 DMAnCON0_DMA3 DMAnSSAU_DMA3 413Fh 413Eh 413Dh 413Ch 413Bh 413Ah 4139h 4138h 4137h 4136h 4135h 4134h 4133h 4132h 4131h 4130h 412Fh 412Eh 412Dh 412Ch 412Bh 412Ah 4129h 4128h 4127h 4126h 4125h 4124h 4123h 4122h 4121h 4120h DMAnSSAH_DMA3 DMAnSSAL_DMA3 DMAnSSZH_DMA3 DMAnSSZL_DMA3 DMAnSPTRU_DMA3 DMAnSPTRH_DMA3 DMAnSPTRL_DMA3 DMAnSCNTH_DMA3 DMAnSCNTL_DMA3 DMAnDSAH_DMA3 DMAnDSAL_DMA3 DMAnDSZH_DMA3 DMAnDSZL_DMA3 DMAnDPTRH_DMA3 DMAnDPTRL_DMA3 DMAnDCNTH_DMA3 DMAnDCNTL_DMA3 DMAnBUF_DMA3 DMAnSIRQ_DMA2 DMAnAIRQ_DMA2 DMAnCON1_DMA2 DMAnCON0_DMA2 DMAnSSAU_DMA2 DMAnSSAH_DMA2 DMAnSSAL_DMA2 DMAnSSZH_DMA2 DMAnSSZL_DMA2 DMAnSPTRU_DMA2 DMAnSPTRH_DMA2 DMAnSPTRL_DMA2 DMAnSCNTH_DMA2 DMAnSCNTL_DMA2 411Fh 411Eh 411Dh 411Ch 411Bh 411Ah 4119h 4118h 4117h 4116h 4115h 4114h 4113h 4112h 4111h 4110h 410Fh 410Eh 410Dh 410Ch 410Bh 410Ah 4109h 4108h 4107h 4106h 4105h 4104h 4103h 4102h 4101h 4100h DMAnDSAH_DMA2 DMAnDSAL_DMA2 DMAnDSZH_DMA2 DMAnDSZL_DMA2 DMAnDPTRH_DMA2 DMAnDPTRL_DMA2 DMAnDCNTH_DMA2 DMAnDCNTL_DMA2 DMAnBUF_DMA2 DMAnSIRQ_DMA1 DMAnAIRQ_DMA1 DMAnCON1_DMA1 DMAnCON0_DMA1 DMAnSSAU_DMA1 DMAnSSAH_DMA1 DMAnSSAL_DMA1 DMAnSSZH_DMA1 DMAnSSZL_DMA1 DMAnSPTRU_DMA1 DMAnSPTRH_DMA1 DMAnSPTRL_DMA1 DMAnSCNTH_DMA1 DMAnSCNTL_DMA1 DMAnDSAH_DMA1 DMAnDSAL_DMA1 DMAnDSZH_DMA1 DMAnDSZL_DMA1 DMAnDPTRH_DMA1 DMAnDPTRL_DMA1 DMAnDCNTH_DMA1 DMAnDCNTL_DMA1 DMAnBUF_DMA1 DMA Addressing The start addresses for the source read and destination write operations are set using the DMAnSSA and DMAnDSA registers, respectively. When the DMA message transfers are in progress, the DMAnSPTR and DMAnDPTR registers contain the current Address Pointers for each source read and destination write operation. These registers are modified after each transaction based on the Address mode selection bits. The SMODE and DMODE bits determine the Address modes of operation by controlling how the DMAnSPTR and DMAnDPTR registers are updated after every DMA data transaction (Figure 16-3). Each address can be separately configured to: • Remain unchanged • Increment by 1 • Decrement by 1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 245 PIC18F06/16Q41 DMA - Direct Memory Access Figure 16-3. DMA Pointers Block Diagram DMAnSSA DMAnDSA DMAnSPTR DMAnDPTR +1 0 -1 +1 0 -1 SMODE DMODE The DMA can initiate data transfers from the PFM, Data EEPROM or SFR/GPR space. The SMR bits are used to select the type of memory being pointed to by the Source Address Pointer. The SMR bits are required because the PFM and SFR/GPR spaces have overlapping addresses that do not allow the specified address to uniquely define the memory location to be accessed. Important:  1. For proper memory read access to occur, the combination of address and space selection must be valid. 2. The destination does not have space selection bits because it can only write to the SFR/GPR space. 16.3.3 DMA Message Size/Counters A transaction is the transfer of one byte. A message consists of one or more transactions. A complete DMA process consists of one or more messages. The size registers determine how many transactions are in a message. The DMAnSSZ registers determine the source size and DMAnDSZ registers determine the destination size. When a DMA transfer is initiated, the size registers are copied to corresponding counter registers that control the duration of the message. The DMAnSCNT registers count the source transactions and the DMAnDCNT registers count the destination transactions. Both are simultaneously decremented by one after each transaction. A message is started by setting the DGO bit and terminates when the smaller of the two counters reaches zero. When either counter reaches zero, the DGO bit is cleared and the counter and pointer registers are immediately reloaded with the corresponding size and address data. If the other counter did not reach zero, then the next message will continue with the count and address corresponding to that register. Refer to Figure 16-4. When the Source and Destination Size registers are not equal, then the ratio of the largest to the smallest size determines how many messages are in the DMA process. For example, when the destination size is six and the source size is two, then each message will consist of two transactions and the complete DMA process will consist of three messages. When the larger size is not an even integer of the smaller size, then the last message in the process will terminate early when the larger count reaches zero. In that case, the larger counter will reset and the smaller counter will have a remainder skewing any subsequent messages by that amount. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 246 PIC18F06/16Q41 DMA - Direct Memory Access Table 16-2 has a few examples of configuring DMA Message sizes. Important:  Reading the DMAnSCNT or DMAnDCNT registers will never return zero. When either register is decremented from ‘1’, it is immediately reloaded from the corresponding size register. Table 16-2. Example Message Size Operation Example SCNT DCNT Read from single SFR location to RAM UART Receive Buffer 1 N N equals the number of bytes desired in the destination buffer. N ≥ 1. Write to single SFR location from RAM UART Transmit Buffer N 1 N equals the number of bytes desired in the source buffer. N ≥ 1. Read from multiple SFR location ADC Result registers 2 2*N N equals the number of ADC results to be stored in memory. N ≥ 1 PWM Duty Cycle registers 2*N 2 Write to Multiple SFR registers Comments N equals the number of PWM duty cycle values to be loaded from a memory table. N ≥ 1 Figure 16-4. DMA Counters Block Diagram DMAnSSZ DMAnDSZ DMAnSCNT DMAnDCNT 1 16.3.4 1 DMA Message Transfers Once the Enable bit is set to start DMA message transfers, the Source/Destination Pointer and Counter registers are initialized to the conditions shown in the table below. Table 16-3. DMA Initial Conditions Register Value Loaded DMAnSPTR DMAnSSA DMAnSCNT DMAnSSZ DMAnDPTR DMAnDSA DMAnDCNT DMAnDSZ © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 247 PIC18F06/16Q41 DMA - Direct Memory Access During the DMA operation after each transaction, Table 16-4 and Table 16-5 indicate how the Source/Destination Pointer and Counter registers are modified. The following sections discuss how to initiate and terminate DMA transfers. Table 16-4. DMA Source Pointer/Counter During Operation Register Modified Source Counter/Pointer Value DMAnSCNT = DMAnSCNT -1 DMAnSCNT != 1 SMODE = 00: DMAnSPTR = DMAnSPTR SMODE = 01: DMAnSPTR = DMAnSPTR + 1 SMODE = 10: DMAnSPTR = DMAnSPTR - 1 DMAnSCNT = DMAnSSZ DMAnSCNT == 1 DMAnSPTR = DMAnSSA Table 16-5. DMA Destination Pointer/Counter During Operation Register Modified Destination Counter/Pointer Value DMAnDCNT = DMAnDCNT -1 DMAnDCNT != 1 DMODE = 00: DMAnDPTR = DMAnDPTR DMODE = 01: DMAnDPTR = DMAnDPTR + 1 DMODE = 10: DMAnDPTR = DMAnDPTR - 1 DMAnDCNT = DMAnDSZ DMAnDCNT == 1 DMAnDPTR = DMAnDSA 16.3.4.1 Starting DMA Message Transfers The DMA can initiate data transactions by either of the following two conditions: • User software control • Hardware trigger, SIRQ 16.3.4.1.1 User Software Control Software starts or stops DMA transaction by setting/clearing the DGO bit. The DGO bit is also used to indicate whether a DMA hardware trigger has been received and a message is in progress. Important:  1. Software start can only occur when the EN bit is set. 2. If the CPU writes to the DGO bit while it is already set, there is no effect on the system, the DMA will continue to operate normally. 16.3.4.1.2 Hardware Trigger, SIRQ A hardware trigger is an interrupt request from another module sent to the DMA with the purpose of starting a DMA message. The DMA start trigger source is user-selectable using the DMAnSIRQ register. The SIRQEN bit is used to enable sampling of external interrupt triggers by which a DMA transfer can be started. When set, the DMA will sample the selected interrupt source and when cleared, the DMA will ignore the interrupt source. Clearing the SIRQEN bit does not stop a DMA transaction currently in progress, it only stops more hardware request signals from being received. 16.3.4.2 Stopping DMA Message Transfers The DMA controller can stop data transactions by any of the following conditions: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 248 PIC18F06/16Q41 DMA - Direct Memory Access • • • • • Clearing the DGO bit Hardware abort trigger, AIRQ Source count reload Destination count reload Clearing the EN bit 16.3.4.2.1 User Software Control If the user clears the DGO bit, the message will be stopped and the DMA will remain in the current configuration. For example, if the user clears the DGO bit after source data has been read, but before it is written to the destination, then the data in the DMAnBUF register will not reach its destination. This is also referred to as a soft-stop as the operation can resume, if desired, by setting the DGO bit again. 16.3.4.2.2 Hardware Trigger, AIRQ The AIRQEN bit is used to enable sampling of external interrupt triggers by which a DMA transaction can be aborted. Once an abort interrupt request has been received, the DMA will perform a soft-stop by clearing the DGO bit, as well as clearing the SIRQEN bit so overruns do not occur. The AIRQEN bit is also cleared to prevent additional abort signals from triggering false aborts. If desired, the DGO bit can be set again and the DMA will resume operation from where it left off after the soft stop had occurred, as none of the DMA state information is changed in the event of an abort. 16.3.4.2.3 Source Count Reload A DMA message is considered to be complete when the Source Count register is decremented from 1 and then reloaded (i.e., once the last byte from either the source read or destination write has occurred). When the SSTP bit is set and the Source Count register is reloaded, then further message transfer is stopped. 16.3.4.2.4 Destination Count Reload A DMA message is considered to be complete when the Destination Count register is decremented from 1 and then reloaded (i.e., once the last byte from either the source read or destination write has occurred). When the DSTP bit is set and the Destination Count register is reloaded then further message transfer is stopped. Important:  Reading the DMAnSCNT or DMAnDCNT registers will never return zero. When either register is decremented from ‘1’, it is immediately reloaded from the corresponding size register. 16.3.4.2.5 Clearing the EN Bit If the user clears the EN bit, the message will be stopped and the DMA will return to its default configuration. This is also referred to as a hard stop, as the DMA cannot resume operation from where it was stopped. Important:  After the DMA message transfer is stopped, it requires an extra instruction cycle before the Stop condition takes effect. Thus, after the Stop condition has occurred, a source read or a destination write can occur depending on the source or destination bus availability. 16.4 Disable DMA Message Transfer Upon Completion Once the DMA message is complete, it may be desirable to disable the trigger source to prevent overrun or under run of data. This can be done by any of the following methods: • Clearing the SIRQEN bit • Setting the SSTP bit • Setting the DSTP bit © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 249 PIC18F06/16Q41 DMA - Direct Memory Access 16.4.1 Clearing the SIRQEN Bit Clearing the SIRQEN bit stops the sampling of external start interrupt triggers, hence preventing further DMA message transfers. An example is a communications peripheral with a level-triggered interrupt. The peripheral will continue to request data (because its buffer is empty) even though there is no more data to be moved. Disabling the SIRQEN bit prevents the DMA from processing these requests. 16.4.2 Source/Destination Stop The SSTP and DSTP bits determine whether or not to disable the hardware triggers (SIRQEN = 0), once a DMA message has completed. When the SSTP bit is set and the DMAnSCNT = 0, then the SIRQEN bit will be cleared. Similarly, when the DSTP bit is set and the DMAnDCNT = 0, the SIRQEN bit will be cleared. Important:  The SSTP and DSTP bits are independent functions and do not depend on each other. It is possible for a message to be stopped by either counter at message end or both counters at message end. 16.5 Types of Hardware Triggers The DMA has two different trigger inputs, the source trigger and the abort trigger. Each of these trigger sources is user configurable using the DMAnSIRQ and DMAnAIRQ registers. Based on the source selected for each trigger, there are two types of requests that can be sent to the DMA: • Edge triggers • Level triggers 16.5.1 Edge Trigger Requests An edge request occurs only once when a given module interrupt requirements are true. Examples of edge triggers are the ADC conversion complete and the interrupt-on-change interrupts. 16.5.2 Level Trigger Requests A level request is asserted as long as the condition that causes the interrupt is true. Examples of level triggers are the UART receive and transmit interrupts. 16.6 Types of Data Transfers Based on the memory access capabilities of the DMA (see Table 16-1), the following sections discuss the different types of data movement between the source and destination memory regions. • • • • N:1 This type of transfer is common when sending predefined data packets (such as strings) through a single interface point (such as communications modules transmit registers). N:N This type of transfer is useful for moving information out of the program Flash or Data EEPROM to SRAM for manipulation by the CPU or other peripherals. 1:1 This type of transfer is common when bridging two different modules data streams together (communications bridge). 1:N This type of transfer is useful for moving information from a single data source into a memory buffer (communications receive registers). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 250 PIC18F06/16Q41 DMA - Direct Memory Access 16.7 DMA Interrupts Each DMA has its own set of four interrupt flags, used to indicate a range of conditions during data transfers. The interrupt flag bits can be accessed using the corresponding PIR registers (refer to the “VIC - Vectored Interrupt Controller” chapter). 16.7.1 DMA Source Count Interrupt The Source Count Interrupt Flag (DMAxSCNTIF) is set every time the DMAnSCNT register reaches zero and is reloaded to its starting value. 16.7.2 DMA Destination Count Interrupt The Destination Count Interrupt Flag (DMAxDCNTIF) is set every time the DMAnDCNT register reaches zero and is reloaded to its starting value. The DMA source and destination count interrupts signal the CPU when the DMA messages are completed. 16.7.3 Abort Interrupt The Abort Interrupt Flag (DMAxAIF) is used to signal that the DMA has halted activity due to an abort signal from one of the abort sources. This is used to indicate that the transaction has been halted by a hardware event. 16.7.4 Overrun Interrupt When the DMA receives a trigger to start a new message before the current message is completed, then the Overrun Interrupt Flag (DMAxORIF) bit is set. This condition indicates that the DMA is being requested before its current transaction is finished. This implies that the active DMA may not be able to keep up with the demands from the peripheral module being serviced, which may result in data loss. The DMAxORIF flag being set does not cause the current DMA transfer to terminate. The overrun interrupt is only available for trigger sources that are edge-based and not available for sources that are level-based. Therefore, a level-based interrupt source does not trigger a DMA overrun error due to the potential latency issues in the system. An example of an interrupt that can use the overrun interrupt is a timer overflow (or period match) interrupt. This event only happens every time the timer rolls over and is not dependent on any other system conditions. An example of an interrupt that does not allow the overrun interrupt is the UART TX buffer. The UART will continue to assert the interrupt until the DMA is able to process the message. Due to latency issues, the DMA may not be able to service an empty buffer immediately, but the UART continues to assert its transmit interrupt until it is serviced. If overrun was allowed in this case, the overrun would occur almost immediately as the module samples the interrupt sources every instruction cycle. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 251 PIC18F06/16Q41 DMA - Direct Memory Access 16.8 DMA Setup and Operation The following steps illustrate how to configure the DMA for data transfer: 1. 2. Select the desired DMA using the DMASELECT register. Program the appropriate source and destination addresses for the transaction into the DMAnSSA and DMAnDSA registers. 3. Select the source memory region that is being addressed by the DMAnSSA register, using the SMR bits. 4. Program the SMODE and DMODE bits to select the Addressing mode. 5. Program the source size (DMAnSSZ) and destination size (DMAnDSZ) registers with the number of bytes to be transferred. It is recommended for proper operation that the size registers be a multiple of each other. 6. If the user desires to disable data transfers once the message has completed, then the SSTP and DSTP bits need to be set. (See the Source/Destination Stop section). 7. If using hardware triggers for data transfer, set up the hardware trigger interrupt sources for the starting and aborting DMA transfers (DMAnSIRQ and DMAnAIRQ), and set the corresponding Interrupt Request Enable (SIRQEN and AIRQEN) bits. 8. Select the priority level for the DMA (see the “System Arbitration” section in the “PIC18 CPU” chapter) and lock the priorities (see the “Priority Lock” section in the “PIC18 CPU” chapter). 9. Enable the DMA by setting the EN bit. 10. If using software control for data transfer, set the DGO bit, else this bit will be set by the hardware trigger. Once the DMA is set up, Figure 16-5 describes the sequence of operation when the DMA uses hardware triggers and utilizes the unused CPU cycles (bubble) for DMA transfers. The following sections describe with visual reference the sequence of events for different configurations of the DMA module. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 252 PIC18F06/16Q41 DMA - Direct Memory Access Figure 16-5. DMA Operation with Hardware Trigger Configure DMA Module EN = 1 DMA Source/ Destination Pointers/ Counters are loaded N SIRQEN = 1 & Trigger? Y DGO = 1 Y N Bubble? Y DMAnBUF = &DMAnSPTR XIP = 1 Source Read N Bubble? Y &DMAnDPTR = DMABUF XIP = 0 Destination Write Y DMAnSCNT = 0 Reload DMAnSCNT & DMAnSPTR DMAxSCNTIF =1 DGO = 0 N Update DMAnSSA, DMAnSCNT SIRQEN = 0 Y SSTP = 1 N DMAnDCNT = 0 Y Reload DMAnDCNT & DMAnDPTR DMAnDCNTIF =1 DGO = 0 N Update DMAnDSA, DMAnDCNT AIRQEN = 0 Y DSTP = 1 N N DGO = 0 Y End Process © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 253 PIC18F06/16Q41 DMA - Direct Memory Access 16.8.1 Source Stop When the Source Stop bit is set (SSTP = 1) and the DMAnSCNT register reloads, the DMA clears the SIRQEN bit to stop receiving new start interrupt request signals and sets the DMAnSCNTIF flag. Refer to the figure below for more details. Figure 16-6. GPR-GPR Transactions with Hardware Triggers, SSTP = 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Instruction Clock EN SIRQEN Source Hardware Trigger DGO DMAnSPTR 0x100 0x101 0x102 0x103 0x100 DMAnDPTR 0x200 0x201 0x200 0x201 0x200 DMAnSCNT 4 3 2 1 4 DMAnDCNT 2 1 2 1 2 DMA STATE SR(1) DW(2) SR(1) DW(2) IDLE IDLE SR(1) DW(2) SR(1) DW(2) IDLE DMAxSCNTIF DMAxDCNTIF DMAnSSA 0x100 DMAnDSA 0x200 DMAnSSZ 0x4 DMAnDSZ 0x2 Notes:  1. SR - Source Read 2. DW - Destination Write © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 254 PIC18F06/16Q41 DMA - Direct Memory Access 16.8.2 Destination Stop When the Destination Stop bit is set (DSTP = 1) and the DMAnDCNT register reloads, the DMA clears the SIRQEN bit to stop receiving new start interrupt request signals and sets the DMAxDCNTIF flag. Figure 16-7. GPR-GPR Transactions with Hardware Triggers, DSTP = 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Instruction Clock EN SIRQEN Source Hardware Trigger DGO DMAnSPTR 0x100 0x101 0x100 0x101 0x100 DMAnDPTR 0x200 0x201 0x202 0x203 0x200 DMAnSCNT 2 1 2 1 2 DMAnDCNT 4 3 2 1 4 DMA STATE SR(1) DW(2) SR(1) DW(2) IDLE IDLE SR(1) DW(2) SR(1) DW(2) IDLE DMAxSCNTIF DMAxDCNTIF DMAnSSA 0x100 DMAnDSA 0x200 DMAnSSZ 0x2 DMAnDSZ 0x4 Notes:  1. SR - Source Read 2. DW - Destination Write © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 255 PIC18F06/16Q41 DMA - Direct Memory Access 16.8.3 Continuous Transfer When the Source or the Destination Stop bit is cleared (SSTP, DSTP = 0), the transactions continue unless stopped by the user. The DMAxSCNTIF and DMAxDCNTIF flags are set whenever the respective counter registers are reloaded. Figure 16-8. GPR-GPR Transactions with Hardware Triggers, SSTP, DSTP = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 32 Instruction Clock EN SIRQEN Source Hardware Trigger DGO DMAnSPTR 0x100 0x101 0x100 0x101 0x100 0x101 0x100 0x101 0x100 DMAnDPTR 0x200 0x201 0x202 0x203 0x200 0x201 0x202 0x203 0x202 DMAnSCNT 2 1 2 1 2 1 2 1 2 DMAnDCNT 4 3 2 1 4 3 2 1 2 DMA STATE IDLE SR(1)DW(2) SR(1) DW(2) IDLE SR(1) DW(2) SR(1) DW(2) IDLE SR(1) DW(2) SR(1) DW(2) IDLE SR(1) DW(2) SR(1) DW(2) IDLE DMAxSCNTIF DMAxDCNTIF DMAnSSA 0x100 DMAnDSA 0x200 DMAnSSZ 0x2 DMAnDSZ 0x4 Notes:  1. SR - Source Read 2. DW - Destination Write © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 256 PIC18F06/16Q41 DMA - Direct Memory Access 16.8.4 Transfer from SFR to GPR The following visual reference describes the sequence of events when copying ADC results to a GPR location. The ADC interrupt flag can be chosen as the source hardware trigger, the source address can be set to point to the ADC Result registers (e.g., at 0x3EEF), and the destination address can be set to point to any chosen GPR location (e.g., at 0x100). Figure 16-9. SFR Space to GPR Space Transfer 1 2 3 4 5 6 7 8 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+x Instruction Clock EN SIRQEN Source Hardware Trigger DGO DMAnSPTR 0x3EEF 0x3EF0 0x3EEF 0x3EF0 0x3EEF DMAnDPTR 0x100 0x101 0x102 0x103 0x103 DMAnSCNT 2 1 2 1 2 DMAnDCNT 10 9 8 7 6 DMA STATE SR(1) DW(2) SR(1) DW(2) IDLE IDLE SR(1) DW(2) SR(1) DW(2) IDLE DMAxSCNTIF DMAxDCNTIF DMAnSSA 0x3EEF DMAnDSA 0x100 DMAnSSZ 0x2 DMAnDSZ 0xA SMODE 0x1 DMODE 0x1 Notes:  1. SR - Source Read 2. DW - Destination Write © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 257 PIC18F06/16Q41 DMA - Direct Memory Access 16.8.5 Overrun Condition The Overrun Interrupt flag is set if the DMA receives a trigger to start a new message before the current message is completed. Figure 16-10. Overrun Interrupt 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Instruction Clock EN SIRQEN Source Hardware Trigger DGO DMAnSPTR 0x100 0x101 0x100 0x101 0x100 DMAnDPTR 0x200 0x201 0x202 0x203 0x200 DMAnSCNT 2 1 2 1 2 DMAnDCNT 4 3 2 1 4 DMA STATE SR(1) DW(2) SR(1) DW(2) IDLE IDLE SR(1) DW(2) SR(1) DW(2) IDLE DMAxSCNTIF DMAxDCNTIF DMAxORIF DMAnCON1bits.SMA = 01 DMAnSSA 0x100 DMAnDSA 0x200 DMAnSSZ 0x2 DMAnDSZ 0x20 Notes:  1. SR - Source Read 2. DW - Destination Write © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 258 PIC18F06/16Q41 DMA - Direct Memory Access 16.8.6 Abort Trigger, Message Complete The AIRQEN needs to be set in order for the DMA to sample abort interrupt sources. When an abort interrupt is received, the SIRQEN bit is cleared and the AIRQEN bit is cleared to avoid receiving further abort triggers. Figure 16-11. Abort at the End of Message 1 2 3 4 5 6 7 8 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 Instruction Clock EN SIRQEN AIRQEN Source Hardware Trigger Abort Hardware Trigger DGO DMAnSPTR 0x3EEF 0x3EF0 0x3EEF 0x3EF0 0x3EEF DMAnDPTR 0x100 0x101 0x109 0x10A 0x100 DMAnSCNT 2 1 2 1 2 DMAnDCNT 10 9 2 1 10 DMA STATE SR(1) DW(2) SR(1) DW(2) IDLE IDLE SR(1) DW(2) SR(1) DW(2) IDLE DMAxSCNTIF DMAxDCNTIF DMAxAIF DMAnSSA 0x3EEF DMAnDSA 0x100 DMAnSSZ 0x2 DMAnDSZ 0xA Notes:  1. SR - Source Read 2. DW - Destination Write © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 259 PIC18F06/16Q41 DMA - Direct Memory Access 16.8.7 Abort Trigger, Message in Progress When an abort interrupt request is received in a DMA transaction, the DMA will perform a soft-stop by clearing the DGO bit (i.e., if the DMA was reading the source register, it will complete the read operation and then clear the DGO bit). The SIRQEN bit is cleared to prevent any overrun and the AIRQEN bit is cleared to prevent any false aborts. When the DGO bit is set again, the DMA will resume operation from where it left off after the soft-stop. Figure 16-12. Abort During Message Transfer 1 2 3 4 5 6 7 8 9 10 11 10 12 Instruction Clock EN SIRQEN AIRQEN Source Hardware Trigger Abort Hardware Trigger DGO DMAnSPTR 0x3EEF 0x3EF0 0x3EEF DMAnDPTR 0x100 0x101 0x102 DMAnSCNT 2 1 2 DMAnDCNT 10 9 8 IDLE DMA STATE SR(1) IDLE DW(2) SR(1) DW(2) IDLE DMAnCONbits.XIP DMAxAIF DMAnSSA 0x3EEF DMAnDSA 0x100 DMAnSSZ 0x2 DMAnDSZ 0xA Notes:  1. SR - Source Read 2. DW - Destination Write © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 260 PIC18F06/16Q41 DMA - Direct Memory Access 16.9 Reset The DMA registers are set to the default state on any Reset. The registers are also reset to the default state when the enable bit is cleared (EN = 0). User firmware needs to setup all the registers to resume DMA operation. 16.10 Power-Saving Mode Operation The DMA utilizes system clocks and it is treated as a peripheral when it comes to power-saving operations. Like other peripherals, the DMA also uses Peripheral Module Disable bits to further tailor its operation in low-power states. 16.10.1 Sleep Mode When the device enters Sleep mode, the system clock to the module is shut down, therefore no DMA operation is supported in Sleep. Once the system clock is disabled, the requisite read and write clocks are also disabled, without which the DMA cannot perform any of its tasks. Any transfers that may be in progress are resumed on exiting from Sleep mode. Register contents are not affected by the device entering or leaving Sleep mode. It is recommended that DMA transactions be allowed to finish before entering Sleep mode. 16.10.2 Idle Mode In Idle mode, all of the system clocks (including the read and write clocks) are still operating, but the CPU is not using them to save power. Therefore, every instruction cycle is available to the system arbiter and if the bubble is granted to the DMA, it may be utilized to move data. 16.10.3 Doze Mode Similar to the Idle mode, the CPU does not utilize all of the available instruction cycles slots that are available to it to save power. It only executes instructions based on its Doze mode settings. Therefore, every instruction not used by the CPU is available for system arbitration and may be utilized by the DMA, if granted by the arbiter. 16.10.4 Peripheral Module Disable The Peripheral Module Disable (PMD) registers provide a method to disable DMA by gating all clock sources supplied to it. The respective DMAxMD bit needs to be set to disable the DMA. 16.11 Example Setup Code This code example illustrates using DMA1 to transfer 10 bytes of data from 0x1000 in Flash memory to the UART transmit buffer. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 261 PIC18F06/16Q41 DMA - Direct Memory Access void initializeDMA(){ //Select DMA1 by setting DMASELECT register to 0x00 DMASELECT = 0x00; //DMAnCON1 - DPTR remains, Source Memory Region PFM, SPTR increments, SSTP DMAnCON1 = 0x0B; //Source registers //Source size DMAnSSZH = 0x00; DMAnSSZL = 0x0A; //Source start address, 0x1000 DMAnSSAU = 0x00; DMAnSSAH = 0x10; DMAnSSAL = 0x00; //Destination registers //Destination size DMAnDSZH = 0x00; DMAnDSZL = 0x01; //Destination start address, DMAnDSA = &U1TXB; //Start trigger source U1TX. Refer the datasheet for the correct code DMAnSIRQ = 0xnn; //Change arbiter priority if needed and perform lock operation DMA1PR = 0x01; // Change the priority only if needed PRLOCK = 0x55; // This sequence PRLOCK = 0xAA; // is mandatory PRLOCKbits.PRLOCKED = 1; // for DMA operation //Enable the DMA & the trigger to start DMA transfer DMAnCON0 = 0xC0; } 16.12 Register Overlay All DMA instances in this device share the same set of registers. Only one DMA instance is accessible at a time. The value in the DMASELECT register is one less than the selected DMA instance. For example, a DMASELECT value of ‘0’ selects DMA1. 16.13 Register Definitions: DMA © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 262 PIC18F06/16Q41 DMA - Direct Memory Access 16.13.1 DMASELECT Name:  Address:  DMASELECT 0x0E8 DMA Instance Selection Register Selects which DMA instance is accessed by the DMA registers Bit 7 6 5 4 3 Access Reset 2 R/W 0 1 SLCT[2:0] R/W 0 0 R/W 0 Bits 2:0 – SLCT[2:0] DMA Instance Selection Value Description n Shared DMA registers of instance n+1 are selected for read and write operations © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 263 PIC18F06/16Q41 DMA - Direct Memory Access 16.13.2 DMAnCON0 Name:  Address:  DMAnCON0 0x0FC DMA Control Register 0 Bit Access Reset 7 EN R/W 0 6 SIRQEN R/W/HC 0 5 DGO R/W/HS/HC 0 4 3 2 AIRQEN R/W/HC 0 1 0 XIP R/HS/HC 0 Bit 7 – EN DMA Module Enable Value Description 1 Enables module 0 Disables module Bit 6 – SIRQEN Start of Transfer Interrupt Request Enable Value Description 1 Hardware triggers are allowed to start DMA transfers 0 Hardware triggers are not allowed to start the DMA transfers Bit 5 – DGO DMA Transaction Value Description 1 DMA transaction is in progress 0 DMA transaction is not in progress Bit 2 – AIRQEN Abort of Transfer Interrupt Request Enable Value Description 1 Hardware triggers are allowed to abort DMA transfers 0 Hardware triggers are not allowed to abort the DMA transfers Bit 0 – XIP Transfer in Progress Status Value Description 1 The DMA buffer register currently holds contents from a read operation and has not transferred data to the destination 0 The DMA buffer register is empty or has successfully transferred data to the destination address © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 264 PIC18F06/16Q41 DMA - Direct Memory Access 16.13.3 DMAnCON1 Name:  Address:  DMAnCON1 0x0FD DMA Control Register 1 Bit Access Reset 7 6 DMODE[1:0] R/W R/W 0 0 5 DSTP R/W 0 4 3 SMR[1:0] R/W 0 R/W 0 2 1 SMODE[1:0] R/W R/W 0 0 0 SSTP R/W 0 Bits 7:6 – DMODE[1:0] Destination Address Mode Selection Value Description 11 Reserved, do not use 10 Destination Pointer (DMADPTR) is decremented after each transfer 01 Destination Pointer (DMADPTR) is incremented after each transfer 00 Destination Pointer (DMADPTR) remains unchanged after each transfer Bit 5 – DSTP Destination Counter Reload Stop Value Description 1 SIRQEN bit is cleared when destination counter reloads 0 SIRQEN bit is not cleared when destination counter reloads Bits 4:3 – SMR[1:0] Source Memory Region Selection Value Description 1x Data EEPROM is selected as the DMA source memory 01 Program Flash Memory is selected as the DMA source memory 00 SFR/GPR data space is selected as the DMA source memory Bits 2:1 – SMODE[1:0] Source Address Mode Selection Value Description 11 Reserved, do not use 10 Source Pointer (DMASPTR) is decremented after each transfer 01 Source Pointer (DMASPTR) is incremented after each transfer 00 Source Pointer (DMASPTR) remains unchanged after each transfer Bit 0 – SSTP Source Counter Reload Stop Value Description 1 SIRQEN bit is cleared when source counter reloads 0 SIRQEN bit is not cleared when source counter reloads © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 265 PIC18F06/16Q41 DMA - Direct Memory Access 16.13.4 DMAnBUF Name:  Address:  DMAnBUF 0x0E9 DMA Data Buffer Register Bit 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 BUF[7:0] Access Reset R 0 R 0 R 0 R 0 Bits 7:0 – BUF[7:0] DMA Data Buffer Description These bits reflect the content of the internal data buffer the DMA peripheral uses to hold the data being moved from the source to destination. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 266 PIC18F06/16Q41 DMA - Direct Memory Access 16.13.5 DMAnSSA Name:  Address:  DMAnSSA 0x0F9 DMA Source Start Address Register Bit 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 SSA[21:16] Access Reset Bit 15 R/W 0 R/W 0 13 12 14 SSA[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 SSA[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 21:0 – SSA[21:0] Source Start Address Notes:  The individual bytes in this multibyte register can be accessed with the following register names. 1. DMAnSSAU: Accesses the upper most byte [23:16]. 2. DMAnSSAH: Accesses the high byte [15:8]. 3. DMAnSSAL: Access the low byte [7:0]. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 267 PIC18F06/16Q41 DMA - Direct Memory Access 16.13.6 DMAnSSZ Name:  Address:  DMAnSSZ 0x0F7 DMA Source Size Register Bit 15 14 13 12 11 10 9 8 SSZ[11:8] Access Reset Bit 7 6 5 4 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 SSZ[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 11:0 – SSZ[11:0] Source Message Size Notes:  The individual bytes in this multibyte register can be accessed with the following register names. 1. DMAnSSZH: Accesses the high byte [15:8]. 2. DMAnSSZL: Access the low byte [7:0]. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 268 PIC18F06/16Q41 DMA - Direct Memory Access 16.13.7 DMAnSCNT Name:  Address:  DMAnSCNT 0x0F2 DMA Source Count Register Bit 15 14 13 12 11 10 9 8 SCNT[11:8] Access Reset Bit 7 6 5 4 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 SCNT[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 11:0 – SCNT[11:0] Current Source Byte Count Notes:  The individual bytes in this multibyte register can be accessed with the following register names. 1. DMAnSCNTH: Accesses the high byte [15:8]. 2. DMAnSCNTL: Access the low byte [7:0]. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 269 PIC18F06/16Q41 DMA - Direct Memory Access 16.13.8 DMAnSPTR Name:  Address:  DMAnSPTR 0x0F4 DMA Source Pointer Register Bit 23 22 21 20 19 18 17 16 R 0 R 0 R 0 R 0 11 10 9 8 R 0 R 0 R 0 R 0 3 2 1 0 R 0 R 0 R 0 R 0 SPTR[21:16] Access Reset Bit 15 14 R 0 R 0 13 12 SPTR[15:8] Access Reset R 0 R 0 R 0 R 0 Bit 7 6 5 4 SPTR[7:0] Access Reset R 0 R 0 R 0 R 0 Bits 21:0 – SPTR[21:0] Current Source Address Pointer Notes:  The individual bytes in this multibyte register can be accessed with the following register names. 1. DMAnSPTRU: Accesses the upper most byte [23:16]. 2. DMAnSPTRH: Accesses the high byte [15:8]. 3. DMAnSPTRL: Access the low byte [7:0]. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 270 PIC18F06/16Q41 DMA - Direct Memory Access 16.13.9 DMAnDSA Name:  Address:  DMAnDSA 0x0F0 DMA Destination Start Address Register Bit 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 DSA[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 DSA[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 15:0 – DSA[15:0] Destination Start Address Notes:  The individual bytes in this multibyte register can be accessed with the following register names. 1. DMAnDSAH: Accesses the high byte [15:8]. 2. DMAnDSAL: Access the low byte [7:0]. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 271 PIC18F06/16Q41 DMA - Direct Memory Access 16.13.10 DMAnDSZ Name:  Address:  DMAnDSZ 0x0EE DMA Destination Size Register Bit 15 14 13 12 11 10 9 8 DSZ[11:8] Access Reset Bit 7 6 5 4 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 DSZ[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 11:0 – DSZ[11:0] Destination Message Size Notes:  The individual bytes in this multibyte register can be accessed with the following register names. 1. DMAnDSZH: Accesses the high byte [15:8]. 2. DMAnDSZL: Access the low byte [7:0]. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 272 PIC18F06/16Q41 DMA - Direct Memory Access 16.13.11 DMAnDCNT Name:  Address:  DMAnDCNT 0x0EA DMA Destination Count Register Bit 15 14 13 12 11 10 9 8 DCNT[11:8] Access Reset Bit 7 6 5 4 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 DCNT[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 11:0 – DCNT[11:0] Current Destination Byte Count Notes:  The individual bytes in this multibyte register can be accessed with the following register names. 1. DMAnDCNTH: Accesses the high byte [15:8]. 2. DMAnDCNTL: Access the low byte Destination Message Size bits [7:0]. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 273 PIC18F06/16Q41 DMA - Direct Memory Access 16.13.12 DMAnDPTR Name:  Address:  DMAnDPTR 0x0EC DMA Destination Pointer Register Bit 15 14 13 12 11 10 9 8 R 0 R 0 R 0 R 0 3 2 1 0 R 0 R 0 R 0 R 0 DPTR[15:8] Access Reset R 0 R 0 R 0 R 0 Bit 7 6 5 4 DPTR[7:0] Access Reset R 0 R 0 R 0 R 0 Bits 15:0 – DPTR[15:0] Current Destination Address Pointer Notes:  The individual bytes in this multibyte register can be accessed with the following register names. 1. DMAnDPTRH: Accesses the high byte [15:8]. 2. DMAnDPTRL: Access the low byte [7:0]. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 274 PIC18F06/16Q41 DMA - Direct Memory Access 16.13.13 DMAnSIRQ Name:  Address:  DMAnSIRQ 0x0FF DMA Start Interrupt Request Source Selection Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 SIRQ[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – SIRQ[7:0] DMA Start Interrupt Request Source Selection Table 16-6. DMAxSIRQ and DMAxAIRQ Interrupt Sources Vector Number Interrupt source 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x10 0x11 - 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 HLVD (High/Low-Voltage Detect) OSF (Oscillator Fail) CSW (Clock Switching) NVM CLC1 (Configurable Logic Cell) CRC (Cyclic Redundancy Check) IOC (Interrupt-On-Change) INT0 ZCD (Zero-Cross Detection) AD (ADC Conversion Complete) ACT (Active Clock Tuning) CM1 (Comparator) SMT1 (Signal Measurement Timer) SMT1PWA ADT DMA1SCNT (Direct Memory Access) DMA1DCNT DMA1OR DMA1A SPI1RX (Serial Peripheral Interface) SPI1TX SPI1 TMR2 TMR1 TMR1G CCP1 (Capture/Compare/PWM) TMR0 U1RX U1TX © 2020-2021 Microchip Technology Inc. and its subsidiaries Vector Number Interrupt source (cont.) (cont.) 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F INT1 CWG1 (Complementary Waveform Generator) NCO1 (Numerically Controlled Oscillator) DMA2SCNT DMA2DCNT DMA2OR DMA2A I2C1RX I2C1TX I2C1 I2C1E CLC3 PWM3RINT PWM3GINT U2RX U2TX U2E U2 CLC4 SCAN U3RX U3TX U3E U3 DMA3SCNT DMA3DCNT DMA3OR DMA3A Preliminary Datasheet DS40002214E-page 275 PIC18F06/16Q41 DMA - Direct Memory Access ...........continued Vector Number Interrupt source 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F U1E U1 TMR3 TMR3G PWM1RINT PWM1GINT SPI2RX SPI2TX SPI2 CM2 (Comparator) CLC2 PWM2RINT PWM2GINT © 2020-2021 Microchip Technology Inc. and its subsidiaries Vector Number Interrupt source (cont.) (cont.) 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D INT2 TMR4 DMA4SCNT DMA4DCNT DMA4OR DMA4A PWM1.S1P1 (PWM1 Parameter 1 of Slice 1) PWM1.S1P2 (PWM1 Parameter 2 of Slice 1) PWM2S1P1 PWM2S1P2 PWM3S1P1 PWM3S1P2 Preliminary Datasheet DS40002214E-page 276 PIC18F06/16Q41 DMA - Direct Memory Access 16.13.14 DMAnAIRQ Name:  Address:  DMAnAIRQ 0x0FE DMA Abort Interrupt Request Source Selection Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 AIRQ[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – AIRQ[7:0] DMA Abort Interrupt Request Source Selection Refer to the DMA Interrupt Sources table. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 277 PIC18F06/16Q41 DMA - Direct Memory Access 16.14 Address Register Summary - DMA Name 0x00 ... 0xE7 0xE8 0xE9 DMASELECT DMAnBUF 0xEA DMAnDCNT DMAnDPTR 0xEE DMAnDSZ 0xF0 DMAnDSA 0xF2 DMAnSCNT 0xF7 7 6 5 4 3 2 1 0 Reserved 0xEC 0xF4 Bit Pos. DMAnSPTR DMAnSSZ 0xF9 DMAnSSA 0xFC 0xFD 0xFE 0xFF DMAnCON0 DMAnCON1 DMAnAIRQ DMAnSIRQ 7:0 7:0 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 23:16 7:0 15:8 7:0 15:8 23:16 7:0 7:0 7:0 7:0 SLCT[2:0] BUF[7:0] DCNT[7:0] DCNT[11:8] DPTR[7:0] DPTR[15:8] DSZ[7:0] DSZ[11:8] DSA[7:0] DSA[15:8] SCNT[7:0] SCNT[11:8] SPTR[7:0] SPTR[15:8] SPTR[21:16] SSZ[7:0] SSZ[11:8] SSA[7:0] SSA[15:8] EN SIRQEN DMODE[1:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries DGO DSTP SMR[1:0] AIRQ[7:0] SIRQ[7:0] Preliminary Datasheet SSA[21:16] AIRQEN SMODE[1:0] XIP SSTP DS40002214E-page 278 PIC18F06/16Q41 Power-Saving Modes 17. Power-Saving Modes The purpose of the Power-Saving modes is to reduce power consumption. There are three Power-Saving modes: • • • 17.1 Doze mode Sleep mode Idle mode Doze Mode Doze mode allows for power saving by reducing CPU operation and Program Flash Memory (PFM) access, without affecting peripheral operation. Doze mode differs from Sleep mode because the band gap and system oscillators continue to operate, while only the CPU and PFM are affected. The reduced execution saves power by eliminating unnecessary operations within the CPU and memory. When the Doze Enable bit is set (DOZEN = ‘b1) the CPU executes only one instruction cycle out of every N cycles as defined by the DOZE bits. For example, if DOZE = 001, the instruction cycle ratio is 1:4. The CPU and memory execute for one instruction cycle and then lay Idle for three instruction cycles. During the unused cycles, the peripherals continue to operate at the system clock speed. 17.1.1 Doze Operation The Doze operation is illustrated in Figure 17-1. As with normal operation, the instruction is fetched for the next instruction cycle while the previous instruction is executed. The Q-clocks to the peripherals continue throughout the periods in which no instructions are fetched or executed. The following configuration settings apply for this example: • Doze enabled (DOZEN = 1) • • CPU instruction cycle to peripheral instruction cycle ratio of 1:4 Recover-on-Interrupt enabled (ROI = 1) Figure 17-1. Doze Mode Operation Example System Clock 1 1 2 Instruction Period 1 2 3 2 3 4 1 1 4 2 2 3 3 4 1 2 3 4 1 2 3 4 1 2 2 3 4 1 1 3 4 1 2 3 4 1 2 3 4 1 2 3 4 2 3 4 4 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 PFM Op s Fetch Fetch Push 0004h Fetch Fetch CPU Op s Exec Exec Exec(1,2) NOP Exec Exec CPU Clock 3 Exec Interrupt (ROI = 1) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 279 PIC18F06/16Q41 Power-Saving Modes Notes:  1. Multicycle instructions are executed to completion before fetching 0x0004. 2. 17.1.2 If the prefetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will resume execution at full speed. Interrupts During Doze System behavior for interrupts that may occur during Doze mode are configured using the ROI and DOE bits. Refer to the example below for details about system behavior in all cases for a transition from Main to ISR back to Main. Example 17-1. Doze Software Example // Mainline operation bool somethingToDo = FALSE; void main() { initializeSystem(); // DOZE = 64:1 (for example) // ROI = 1; GIE = 1; // enable interrupts while (1) { // If ADC completed, process data if (somethingToDo) { doSomething(); DOZEN = 1; // resume low-power } } } // Data interrupt handler void interrupt() { // DOZEN = 0 because ROI = 1 if (ADIF) { somethingToDo = TRUE; DOE = 0; // make main() go fast ADIF = 0; } // else check other interrupts... if (TMR0IF) { timerTick++; DOE = 1; // make main() go slow TMR0IF = 0; } } Note:  User software can change the DOE bit in the ISR. 17.2 Sleep Mode Sleep mode provides the greatest power savings because both the CPU and selected peripherals cease to operate. However, some peripheral clocks continue to operate during Sleep. The peripherals that use those clocks also continue to operate. Sleep mode is entered by executing the SLEEP instruction, while the IDLEN bit is clear. Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 7. The WDT will be cleared, but keeps running if enabled for operation during Sleep. The PD bit of the STATUS register is cleared. The TO bit of the STATUS register is set. The CPU clock is disabled. LFINTOSC, SOSC, HFINTOSC and ADCRC (FRC) are unaffected. Peripherals using them may continue operation during Sleep. I/O ports maintain the status they had before Sleep was executed (driving high, low, or high-impedance). Resets other than WDT are not affected by Sleep mode. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 280 PIC18F06/16Q41 Power-Saving Modes Important:  Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, consider the following conditions: • • • • • I/O pins must not be floating External circuitry sinking current from I/O pins Internal circuitry sourcing current to I/O pins Current draw from pins with internal weak pull-ups Peripherals using clock source unaffected by Sleep I/O pins that are high-impedance inputs need to be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be consuming current include modules such as the DAC and FVR peripherals. 17.2.1 Wake-Up from Sleep The device can wake up from Sleep through one of the following events: 1. 2. 3. 4. 5. 6. External Reset input on MCLR pin, if enabled. BOR Reset, if enabled. Low-Power Brown-out Reset (LPBOR), if enabled. POR Reset. Windowed Watchdog Timer, if enabled. All interrupt sources except clock switch interrupt can wake up the part. Important:  The first five events will cause a device Reset. The last event in the list is considered a continuation of program execution. Fore more information about determining whether a device Reset or wake-up event occurred, refer to the “Resets” chapter. When the SLEEP instruction is being executed, the next instruction (PC + 2) is prefetched. For the device to wake up through an interrupt event, the corresponding Interrupt Enable bit must be enabled in the PIEx register. Wake-up will occur regardless of the state of the Global Interrupt Enable (GIE) bit. If the GIE bit is disabled, the device will continue execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction and then call the Interrupt Service Routine (ISR). Important:  It is recommended to add a NOP as the immediate instruction after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. Upon a wake-fromSleep event, the core will wait for a combination of three conditions before beginning execution. The conditions are: • • • 17.2.2 PFM Ready System Clock Ready BOR Ready (unless BOR is disabled) Wake-Up Using Interrupts When global interrupts are disabled (GIE cleared) and any interrupt source, with the exception of the clock switch interrupt, has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 281 PIC18F06/16Q41 Power-Saving Modes – The SLEEP instruction will execute as a NOP • – WDT and WDT prescaler will not be cleared – The TO bit of the STATUS register will not be set – The PD bit of the STATUS register will not be cleared If the interrupt occurs during or after the execution of a SLEEP instruction: – The SLEEP instruction will be completely executed – – – – Device will immediately wake up from Sleep WDT and WDT prescaler will be cleared The TO bit of the STATUS register will be set The PD bit of the STATUS register will be cleared In the event where flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. Figure 17-2. Wake-Up from Sleep through Interrupt CLKIN(1) TOS T(3) CLKOUT (2) Inte rrupt Flag Interrupt Latency(4) Glo bal Interru pt Ena ble Processor in Sleep Instruction Flo w PC Instruction Fetche d Instruction Fetche d PC PC + 1 Inst(PC) = Slee p Inst(PC + 1) PC + 2 Inst(PC + 2) Inst(PC - 1) Sleep Inst(PC + 1) PC + 2 PC + 2 Forced NOP 0004h 0005h Inst(0x0004) Inst(0x0005) Forced NOP Inst(0x0004) Notes:  1. External clock - High, Medium, Low mode assumed. 2. CLKOUT is shown here for timing reference. 3. TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes. 4. GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0x0004. If GIE = 0, execution will continue in-line. 17.2.3 Low-Power Sleep Mode This device family contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to VDD while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active in Sleep but can operate in different Power modes. This allows the user to optimize the operating current in Sleep mode, depending on the application requirements. 17.2.3.1 Sleep Current vs. Wake-Up Time The Low-Power Sleep mode can be selected by setting the VREGPM bits as following: • VREGPM = ‘b00; the voltage regulator is in High Power mode. In this mode, the voltage regulator and reference circuitry remain in the normal configuration while in Sleep. Hence, there is no delay needed for these circuits to stabilize after wake-up (fastest wake-up from Sleep). • VREGPM = ‘b01; the voltage regulator is in Low Power mode. In this mode, when waking up from Sleep, an extra delay time is required for the voltage regulator and reference circuitry to return to the normal configuration and stabilize (faster wake-up from Sleep). • VREGPM = ‘b10; the voltage regulator is in Ultra-Low Power mode. In this mode, the voltage regulator and reference circuitry are in the lowest current consumption mode and all the auxiliary circuits remain shut down. Wake-up from Sleep in this mode needs the longest delay time for the voltage regulator and reference circuitry to stabilize (lowest current consumption). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 282 PIC18F06/16Q41 Power-Saving Modes • VREGPM = ‘b11; this mode is the similar to the Ultra-Low Power mode (VREGPM = ‘b10), and is recommended ONLY for extended temperature ranges at or above 70℃. 17.2.3.2 Peripheral Usage in Sleep Some peripherals that can operate in High-Power Sleep mode (VREGPM = ‘b00) will not operate as intended in the Low-Power Sleep modes (VREGPM = ‘b01 and ‘b11). The Low-Power Sleep modes are intended for use with the following peripherals: • • • Brown-out Reset (BOR) Windowed Watchdog Timer (WWDT) External interrupt pin/interrupt-on-change pins It is the responsibility of the end user to determine what is acceptable for their application when setting the VREGPM settings to ensure correct operation in Sleep. 17.3 Idle Mode When the IDLEN bit is clear, the SLEEP instruction will put the device into full Sleep mode. When IDLEN is set, the SLEEP instruction will put the device into Idle mode. In Idle mode, the CPU and memory operations are halted, but the peripheral clocks continue to run. This mode is similar to Doze mode, except that in Idle both the CPU and program memory are shut off. Important:  1. Peripherals using FOSC will continue to operate while in Idle (but not in Sleep). Peripherals using HFINTOSC:LFINTOSC will continue running in both Idle and Sleep. 2. When the Clock Out Enable (CLKOUTEN) Configuration bit is cleared, the CLKOUT pin will continue operating while in Idle. 17.3.1 Idle and Interrupts Idle mode ends when an interrupt occurs (even if global interrupts are disabled), but IDLEN is not changed. The device can re-enter Idle by executing the SLEEP instruction. If Recover-on-Interrupt is enabled (ROI = 1), the interrupt that brings the device out of Idle also restores full-speed CPU execution when Doze is also enabled. 17.3.2 Idle and WWDT When in Idle, the WWDT Reset is blocked and will instead wake the device. The WWDT wake-up is not an interrupt, therefore ROI does not apply. Important:  The WWDT can bring the device out of Idle, in the same way it brings the device out of Sleep. The DOZEN bit is not affected. 17.4 Peripheral Operation in Power-Saving Modes All selected clock sources and the peripherals running from them are active in both Idle and Doze modes. Only in Sleep mode, both the FOSC and FOSC/4 clocks are unavailable. However, all other clock sources enabled specifically or through peripheral clock selection before the part enters Sleep, remain operating in Sleep. 17.5 Register Definitions: Power-Savings Control © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 283 PIC18F06/16Q41 Power-Saving Modes 17.5.1 CPUDOZE Name:  Address:  CPUDOZE 0x4F2 Doze and Idle Register Bit Access Reset 7 IDLEN R/W 0 6 DOZEN R/W/HC/HS 0 5 ROI R/W 0 4 DOE R/W/HC/HS 0 3 2 R/W 0 1 DOZE[2:0] R/W 0 0 R/W 0 Bit 7 – IDLEN Idle Enable Value Description 1 A SLEEP instruction places device into Idle mode 0 A SLEEP instruction places the device into Sleep mode Bit 6 – DOZEN  Doze Enable(1) Value Description 1 Places devices into Doze setting 0 Places devices into Normal mode Bit 5 – ROI  Recover-on-Interrupt(1) Value Description 1 Entering the Interrupt Service Routine (ISR) makes DOZEN = 0 0 Entering the Interrupt Service Routine (ISR) does not change DOZEN Bit 4 – DOE  Doze-on-Exit(1) Value Description 1 Exiting the ISR makes DOZEN = 1 0 Exiting the ISR does not change DOZEN Bits 2:0 – DOZE[2:0] Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles Value Description 111 1:256 110 1:128 101 1:64 100 1:32 011 1:16 010 1:8 001 1:4 000 1:2 Note:  1. When ROI = 1 or DOE = 1. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 284 PIC18F06/16Q41 Power-Saving Modes 17.5.2 VREGCON Name:  Address:  VREGCON 0x048 Voltage Regulator Control Register Bit 7 6 5 4 3 PMSYS[1:0] Access Reset R q R q 2 1 0 VREGPM[1:0] R/W R/W 1 0 Bits 5:4 – PMSYS[1:0] System Power Mode Status Value Description 11 Regulator in Ultra-Low Power (ULP) mode for extended temperature range is active 10 Regulator in Ultra-Low Power (ULP) mode is active 01 Regulator in Low Power (LP) mode is active 00 Regulator in High Power (HP) mode is active Bits 1:0 – VREGPM[1:0] Voltage Regulator Power Mode Selection Value Description 11 Regulator in Ultra-Low Power (ULP) mode. Use ONLY for extended temperature range 10 Regulator in Ultra-Low Power (ULP) mode (lowest current consumption) 01 Regulator in Low Power (LP) mode (faster wake-up from Sleep) 00 Regulator in High Power (HP) mode (fastest wake-up from Sleep) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 285 PIC18F06/16Q41 Power-Saving Modes 17.6 Address 0x00 ... 0x47 0x48 0x49 ... 0x04F1 0x04F2 Register Summary - Power-Savings Control Name Bit Pos. 7 6 5 4 3 2 1 0 Reserved VREGCON 7:0 PMSYS[1:0] VREGPM[1:0] Reserved CPUDOZE 7:0 IDLEN © 2020-2021 Microchip Technology Inc. and its subsidiaries DOZEN ROI DOE Preliminary Datasheet DOZE[2:0] DS40002214E-page 286 PIC18F06/16Q41 PMD - Peripheral Module Disable 18. PMD - Peripheral Module Disable 18.1 Overview This module provides the ability to selectively enable or disable a peripheral. Disabling a peripheral places it in its lowest possible Power state. The user can selectively disable unused modules to reduce the overall power consumption. Important:  All modules are ON by default following any system Reset. 18.2 Disabling a Module A peripheral can be disabled by setting the corresponding peripheral disable bit in the PMDx register. Disabling a module has the following effects: 18.3 • • The module is held in Reset and does not function. All the SFRs pertaining to that peripheral become “unimplemented” – Writing is disabled – Reading returns 0x00 • Module outputs are disabled Enabling a Module Clearing the corresponding module disable bit in the PMDx register, re-enables the module and the SFRs will reflect the Power-on Reset values. Important:  There will be no reads/writes to the module SFRs for at least two instruction cycles after it has been re-enabled. 18.4 Register Definitions: Peripheral Module Disable © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 287 PIC18F06/16Q41 PMD - Peripheral Module Disable 18.4.1 PMD0 Name:  Address:  PMD0 0x063 PMD Control Register 0 Bit Access Reset 7 SYSCMD R/W 0 6 FVRMD R/W 0 5 HLVDMD R/W 0 4 CRCMD R/W 0 3 SCANMD R/W 0 2 1 CLKRMD R/W 0 0 IOCMD R/W 0 Bit 7 – SYSCMD  Disable Peripheral System Clock Network(1) Value Description 1 System clock network disabled (FOSC) 0 System clock network enabled Bit 6 – FVRMD Disable Fixed Voltage Reference Disable Fixed Voltage Reference Value Description 1 FVR module disabled 0 FVR module enabled Bit 5 – HLVDMD Disable High/Low-Voltage Detect Value Description 1 HLVD module disabled 0 HLVD module enabled Bit 4 – CRCMD Disable CRC Module Value Description 1 CRC module disabled 0 CRC module enabled Bit 3 – SCANMD Disable NVM Memory Scanner Value Description 1 NVM memory scanner module disabled 0 NVM memory scanner module enabled Bit 1 – CLKRMD Disable Clock Reference Value Description 1 Clock reference module disabled 0 Clock reference module enabled Bit 0 – IOCMD Disable Interrupt-on-Change Value Description 1 Interrupt-on-change module is disabled 0 Interrupt-on-change module is enabled Note:  1. Clearing the SYSCMD bit disables the system clock (FOSC) to peripherals, however peripherals clocked by FOSC/4 are not affected. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 288 PIC18F06/16Q41 PMD - Peripheral Module Disable 18.4.2 PMD1 Name:  Address:  PMD1 0x064 PMD Control Register 1 Bit Access Reset 7 C1MD R/W 0 6 ZCDMD R/W 0 5 SMT1MD R/W 0 4 TMR4MD R/W 0 3 TMR3MD R/W 0 2 TMR2MD R/W 0 1 TMR1MD R/W 0 0 TMR0MD R/W 0 Bit 7 – C1MD Disable Comparator 1 Value Description 1 CM1 module disabled 0 CM1 module enabled Bit 6 – ZCDMD  Disable Zero-Cross Detect(1) Value Description 1 ZCD module disabled 0 ZCD module enabled Bit 5 – SMT1MD Disable SMT1 Module Value Description 1 SMT1 module disabled 0 SMT1 module enabled Bits 0, 1, 2, 3, 4 – TMRnMD Disable Timer TMRn Value Description 1 TMRn module disabled 0 TMRn module enabled Note:  1. Subject to the value of ZCD Configuration bit. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 289 PIC18F06/16Q41 PMD - Peripheral Module Disable 18.4.3 PMD2 Name:  Address:  PMD2 0x065 PMD Control Register 2 Bit Access Reset 7 CCP1MD R/W 0 6 CWG1MD R/W 0 5 DSM1MD R/W 0 4 NCO1MD R/W 0 3 ACTMD R/W 0 2 DAC1MD R/W 0 1 ADCMD R/W 0 0 C2MD R/W 0 Bit 7 – CCP1MD Disable Capture Compare 1 Value Description 1 CCP1 module disabled 0 CCP1 module enabled Bit 6 – CWG1MD Disable Complimentary Waveform Generator 1 Value Description 1 CWG1 module disabled 0 CWG1 module enabled Bit 5 – DSM1MD Disable Digital Signal Modulator Value Description 1 DSM module disabled 0 DSM module enabled Bit 4 – NCO1MD Disable Numerically Controlled Oscillator 1 Value Description 1 NCO1 module disabled 0 NCO1 module enabled Bit 3 – ACTMD Disable Active Clock Tuning Value Description 1 Active Clock Tuning disabled 0 Active Clock Tuning enabled Bit 2 – DAC1MD Disable Digital-to-Analog Converter Value Description 1 DAC module disabled 0 DAC module enabled Bit 1 – ADCMD Disable Analog-to-Digital Converter Value Description 1 ADC module disabled 0 ADC module enabled Bit 0 – C2MD Disable Comparator 2 Value Description 1 CM2 module disabled 0 CM2 module enabled © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 290 PIC18F06/16Q41 PMD - Peripheral Module Disable 18.4.4 PMD3 Name:  Address:  PMD3 0x066 PMD Control Register 3 Bit Access Reset 7 U2MD R/W 0 6 U1MD R/W 0 5 SPI2MD R/W 0 4 SPI1MD R/W 0 3 I2C1MD R/W 0 2 PWM3MD R/W 0 1 PWM2MD R/W 0 0 PWM1MD R/W 0 Bits 6, 7 – UnMD Disable UART Un Value Description 1 UARTn module disabled 0 UARTn module enabled Bit 5 – SPI2MD Disable Serial Peripheral Interface 2 Value Description 1 SPI2 module disabled 0 SPI2 module enabled Bit 4 – SPI1MD Disable Serial Peripheral Interface 1 Value Description 1 SPI1 module disabled 0 SPI1 module enabled Bit 3 – I2C1MD  Disable I2C Value Description 1 I2C1 module disabled 0 I2C1 module enabled Bit 2 – PWM3MD Disable Pulse-Width Modulator 3 Value Description 1 PWM3 module disabled 0 PWM3 module enabled Bit 1 – PWM2MD Disable Pulse-Width Modulator 2 Value Description 1 PWM2 module disabled 0 PWM2 module enabled Bit 0 – PWM1MD Disable Pulse-Width Modulator 1 Value Description 1 PWM1 module disabled 0 PWM1 module enabled © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 291 PIC18F06/16Q41 PMD - Peripheral Module Disable 18.4.5 PMD4 Name:  Address:  PMD4 0x067 PMD Control Register 4 Bit Access Reset 7 DMA3MD R/W 0 6 DMA2MD R/W 0 5 DMA1MD R/W 0 4 CLC4MD R/W 0 3 CLC3MD R/W 0 2 CLC2MD R/W 0 1 CLC1MD R/W 0 0 U3MD R/W 0 Bits 5, 6, 7 – DMAnMD Disable DMAn Value Description 1 DMAn module disabled 0 DMAn module enabled Bits 1, 2, 3, 4 – CLCnMD Disable CLCn Value Description 1 CLCn module disabled 0 CLCn module enabled Bit 0 – UnMD Disable UART Un Value Description 1 UARTn module disabled 0 UARTn module enabled © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 292 PIC18F06/16Q41 PMD - Peripheral Module Disable 18.4.6 PMD5 Name:  Address:  PMD5 0x068 PMD Control Register 5 Bit 7 6 5 4 3 Access Reset 2 OPA1MD R/W 0 1 DAC2MD R/W 0 0 DMA4MD R/W 0 Bit 2 – OPA1MD Disable Operational Amplifier Value Description 1 OPA module disabled 0 OPA module enabled Bit 1 – DAC2MD Disable Digital-to-Analog Converter Value Description 1 DAC module disabled 0 DAC module enabled Bit 0 – DMAnMD Disable DMAn Value Description 1 DMAn module disabled 0 DMAn module enabled © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 293 PIC18F06/16Q41 PMD - Peripheral Module Disable 18.5 Address 0x00 ... 0x62 0x63 0x64 0x65 0x66 0x67 0x68 Register Summary - PMD Name Bit Pos. 7 6 5 4 3 7:0 7:0 7:0 7:0 7:0 7:0 SYSCMD C1MD CCP1MD U2MD DMA3MD FVRMD ZCDMD CWG1MD U1MD DMA2MD HLVDMD SMT1MD DSM1MD SPI2MD DMA1MD CRCMD TMR4MD NCO1MD SPI1MD CLC4MD SCANMD TMR3MD ACTMD I2C1MD CLC3MD 2 1 0 TMR2MD DAC1MD PWM3MD CLC2MD OPA1MD CLKRMD TMR1MD ADCMD PWM2MD CLC1MD DAC2MD IOCMD TMR0MD C2MD PWM1MD U3MD DMA4MD Reserved PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 294 PIC18F06/16Q41 I/O Ports 19. I/O Ports 19.1 Overview Table 19-1. Port Availability per Device Device PORTA 14-pin devices ●(1) 20-pin devices ●(1) PORTB PORTC ●(3) ●(2) ● Notes:  1. Pins RA0 - RA5 only. 2. Pins RB4 - RB7 only. 3. Pins RC0 - RC5 only. Each port has eight registers to control the operation. These registers are: • • • • • • • • PORTx registers (reads the levels on the pins of the device) LATx registers (output latch) TRISx registers (data direction) ANSELx registers (analog select) WPUx registers (weak pull-up) INLVLx (input level control) SLRCONx registers (slew rate control) ODCONx registers (open-drain control) In this section, the generic names such as PORTx, LATx, TRISx, etc. can be associated with PORTA, PORTB, PORTC, etc., depending on availability per device. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in the following figure: Figure 19-1. Generic I/O Port Operation Re v. 10 -00 00 52 A 2/11 /20 19 Read LATx TRISx D Q Write LATx Write PORTx VDD CK Data Register Data bus I/O pin Read PORTx To digital peripherals ANSELx To analog peripherals VSS © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 295 PIC18F06/16Q41 I/O Ports 19.2 PORTx - Data Register PORTx is a bidirectional port, and its corresponding data direction register is TRISx. Reading the PORTx register reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are Read-Modify-Write operations. Therefore, a write to a port implies that the PORT pins are read, and this value is modified, then written to the PORT data latch (LATx). The PORT data latch LATx holds the output port data and contains the latest value of a LATx or PORTx write. The example below shows how to initialize PORTA. Example 19-1. Initializing PORTA in Assembly ; This code example illustrates initializing the PORTA register. ; The other ports are initialized in the same manner. BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTA PORTA LATA LATA ANSELA ANSELA TRISA B'00111000' TRISA ; ;Clear PORTA ; ;Clear Data Latch ; ;Enable digital drivers ; ;Set RA[5:3] as inputs ;and set others as outputs Example 19-2. Initializing PORTA in C // This code example illustrates initializing the PORTA register. // The other ports are initialized in the same manner. PORTA LATA ANSELA TRISA = = = = 0x00; 0x00; 0x00; 0x38; // // // // Clear PORTA Clear Data Latch Enable digital drivers Set RA[5:3] as inputs and set others as outputs Important:  Most PORT pins share functions with device peripherals, both analog and digital. In general, when a peripheral is enabled on a PORT pin, that pin cannot be used as a general purpose output; however, the pin can still be read. 19.3 LATx - Output Latch The Data Latch (LATx registers) is useful for Read-Modify-Write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Important:  As a general rule, output operations to a port must use the LAT register to avoid ReadModify-Write issues. For example, a bit set or clear operation reads the port, modifies the bit, and writes the result back to the port. When two bit operations are executed in succession, output loading on the changed bit may delay the change at the output in which case the bit will be misread in the second bit operation and written to an unexpected level. The LAT registers are isolated from the port loading and therefore changes are not delayed. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 296 PIC18F06/16Q41 I/O Ports 19.4 TRISx - Direction Control The TRISx register controls the PORTx pin output drivers, even when the pins are being used as analog inputs. The user must ensure the bits in the TRISx register are set when using the pins as analog inputs. I/O pins configured as analog inputs always read ‘0’. Setting a TRISx bit (TRISx = 1) will make the corresponding PORTx pin an input (i.e., disable the output driver). Clearing a TRISx bit (TRISx = 0) will make the corresponding PORTx pin an output (i.e., it enables output driver and puts the contents of the output latch on the selected pin). 19.5 ANSELx - Analog Control Ports that support analog inputs have an associated ANSELx register. The ANSELx register is used to configure the Input mode of an I/O pin to analog. Setting an ANSELx bit high will disable the digital input buffer associated with that bit and cause the corresponding input value to always read ‘0’, whether the value is read in PORTx register or selected by PPS as a peripheral input. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. The state of the ANSELx bits has no effect on digital or analog output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing Read-Modify-Write instructions on the PORTx register. Important:  The ANSELx bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be changed to ‘0’ by the user. 19.6 WPUx - Weak Pull-Up Control The WPUx register controls the individual weak pull-ups for each PORT pin. When a WPUx bit is set (WPUx = 1), the weak pull-up will be enabled for the corresponding pin. When a WPUx bit is cleared (WPUx = 0), the weak pull-up will be disabled for the corresponding pin. 19.7 INLVLx - Input Threshold Control The INLVLx register controls the input voltage threshold for each of the available PORTx input pins. A selection between the Schmitt Trigger CMOS or the TTL compatible thresholds is available. If that feature is enabled, the input threshold is important in determining the value of a read of the PORTx register and also all other peripherals which are connected to the input. Refer to the I/O Ports table in the “Electrical Specifications” chapter for more details on threshold levels. Important:  Changing the input threshold selection must be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. 19.8 SLRCONx - Slew Rate Control The SLRCONx register controls the slew rate option for each PORT pin. Slew rate for each PORT pin can be controlled independently. When a SLRCONx bit is set (SLRCONx = 1), the corresponding PORT pin drive is slew © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 297 PIC18F06/16Q41 I/O Ports rate limited. When a SLRCONx bit is cleared (SLRCONx = 0), The corresponding PORT pin drive slews at the maximum rate possible. 19.9 ODCONx - Open-Drain Control The ODCONx register controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When a ODCONx bit is set (ODCONx = 1), the corresponding port output becomes an open-drain driver capable of sinking current only. When a ODCONx bit is cleared (ODCONx = 0), the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. Important:  It is necessary to set open-drain control when using the pin for I2C. 19.10 Edge Selectable Interrupt-on-Change An interrupt can be generated by detecting a signal at the PORT pin that has either a rising edge or a falling edge. Individual pins can be independently configured to generate an interrupt. Refer to the “IOC - Interrupt-on-Change” chapter for more details. 19.11 I2C Pad Control For this family of devices, the I2C specific pads are available on RB4, RB6, RC0 and RC1 pins. The I2C characteristics of each of these pins is controlled by the RxyI2C registers. These characteristics include enabling I2C specific slew rate (over standard GPIO slew rate), selecting internal pull-ups for I2C pins, and selecting appropriate input threshold as per SMBus specifications. Important:  Any peripheral using the I2C pins reads the I2C input levels when enabled via RxyI2C. 19.12 I/O Priorities Each pin defaults to the data latch after Reset. Other functions are selected with the Peripheral Pin Select logic. Refer to the “PPS - Peripheral Pin Select Module” chapter for more details. Analog input functions, such as ADC and comparator inputs, are not shown in the Peripheral Pin Select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx register. Digital output functions may continue to control the pin when it is in Analog mode. Analog outputs, when enabled, take priority over digital outputs and force the digital output driver into a HighImpedance state. The pin function priorities are as follows: 1. 2. 3. 4. Port functions determined by the Configuration bits. Analog outputs (input buffers must be disabled). Analog inputs. Port inputs and outputs from PPS. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 298 PIC18F06/16Q41 I/O Ports 19.13 MCLR/VPP/RA3 Pin The MCLR/VPP pin is an input-only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a PORT pin (MCLRE = 0), it functions as a digital input-only pin; as such, it does not have TRISx and LATx bits associated with its operation. Otherwise, it functions as the device’s Master Clear input. In either configuration, the MCLR/VPP pin also functions as the programming voltage input pin during high-voltage programming. The MCLR/VPP pin is a read-only bit and will read ‘1’ when MCLRE = 1 (i.e., Master Clear enabled). Important:  On a Power-on Reset (POR), the MCLR/VPP pin is enabled as a digital input-only if Master Clear functionality is disabled. The MCLR/VPP pin has an individually controlled internal weak pull-up. When set, the corresponding WPU bit enables the pull-up. When the MCLR/VPP pin is configured as MCLR (MCLRE = 1 and, LVP = 0), or configured for Low-Voltage Programming (MCLRE = x and LVP = 1), the pull-up is always enabled and the WPU bit has no effect. 19.14 Register Definitions: Port Control © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 299 PIC18F06/16Q41 I/O Ports 19.14.1 PORTx Name:  PORTx PORTx Register Bit Access Reset 7 Rx7 R/W x 6 Rx6 R/W x 5 Rx5 R/W x 4 Rx4 R/W x 3 Rx3 R/W x 2 Rx2 R/W x 1 Rx1 R/W x 0 Rx0 R/W x Bits 0, 1, 2, 3, 4, 5, 6, 7 – Rxn Port I/O Value Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu Value Description 1 PORT pin is ≥ VIH 0 PORT pin is ≤ VIL Important:  • Writes to PORTx are actually written to the corresponding LATx register. Reads from PORTx register return actual I/O pin values. • The PORT bit associated with the MCLR pin is read-only and will read ‘1’ when the MCLR function is enabled (LVP = 1 or (LVP = 0 and MCLRE = 1)) • • Refer to the “Pin Allocation Table” for details about MCLR pin and pin availability per port Unimplemented bits will read back as ‘0’ © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 300 PIC18F06/16Q41 I/O Ports 19.14.2 LATx Name:  LATx Output Latch Register Bit Access Reset 7 LATx7 R/W x 6 LATx6 R/W x 5 LATx5 R/W x 4 LATx4 R/W x 3 LATx3 R/W x 2 LATx2 R/W x 1 LATx1 R/W x 0 LATx0 R/W x Bits 0, 1, 2, 3, 4, 5, 6, 7 – LATxn Output Latch Value Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu Important:  • Writes to LATx are equivalent to writes to the corresponding PORTx register. Reads from LATx register return register values, not I/O pin values. • Refer to the “Pin Allocation Table” for details about pin availability per port • Unimplemented bits will read back as ‘0’ © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 301 PIC18F06/16Q41 I/O Ports 19.14.3 TRISx Name:  TRISx Tri-State Control Register Bit Access Reset 7 TRISx7 R/W 1 6 TRISx6 R/W 1 5 TRISx5 R/W 1 4 TRISx4 R/W 1 3 TRISx3 R/W 1 2 TRISx2 R/W 1 1 TRISx1 R/W 1 0 TRISx0 R/W 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 – TRISxn Port I/O Tri-state Control Value Description 1 PORTx output driver is disabled. PORTx pin configured as an input (tri-stated) 0 PORTx output driver is enabled. PORTx pin configured as an output Important:  • The TRIS bit associated with the MCLR pin is read-only and the value is ‘1’ • • Refer to the “Pin Allocation Table” for details about MCLR pin and pin availability per port Unimplemented bits will read back as ‘0’ © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 302 PIC18F06/16Q41 I/O Ports 19.14.4 ANSELx Name:  ANSELx Analog Select Register Bit Access Reset 7 ANSELx7 R/W 1 6 ANSELx6 R/W 1 5 ANSELx5 R/W 1 4 ANSELx4 R/W 1 3 ANSELx3 R/W 1 2 ANSELx2 R/W 1 1 ANSELx1 R/W 1 0 ANSELx0 R/W 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 – ANSELxn Analog Select on RX Pin Value Description 1 Analog input. Pin is assigned as analog input. Digital input buffer disabled. 0 Digital I/O. Pin is assigned to port or digital special function. Important:  • When setting a pin as an analog input, the corresponding TRIS bit must be set to Input mode to allow external control of the voltage on the pin • Refer to the “Pin Allocation Table” for details about pin availability per port • Unimplemented bits will read back as ‘0’ © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 303 PIC18F06/16Q41 I/O Ports 19.14.5 WPUx Name:  WPUx Weak pull-up Register Bit Access Reset 7 WPUx7 R/W 0 6 WPUx6 R/W 0 5 WPUx5 R/W 0 4 WPUx4 R/W 0 3 WPUx3 R/W 0 2 WPUx2 R/W 0 1 WPUx1 R/W 0 0 WPUx0 R/W 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 – WPUxn Weak Pull-up PORTx Control Value Description 1 Weak pull-up enabled 0 Weak pull-up disabled Important:  • The weak pull-up device is automatically disabled if the pin is configured as an output, but this register remains unchanged • If MCLRE = 1, the weak pull-up on MCLR pin is always enabled and the corresponding WPU bit is not affected • Refer to the “Pin Allocation Table” for details about pin availability per port • Unimplemented bits will read back as ‘0’ © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 304 PIC18F06/16Q41 I/O Ports 19.14.6 INLVLx Name:  INLVLx Input Level Control Register Bit Access Reset 7 INLVLx7 R/W 1 6 INLVLx6 R/W 1 5 INLVLx5 R/W 1 4 INLVLx4 R/W 1 3 INLVLx3 R/W 1 2 INLVLx2 R/W 1 1 INLVLx1 R/W 1 0 INLVLx0 R/W 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 – INLVLxn Input Level Select on RX Pin Value Description 1 ST input used for port reads and interrupt-on-change 0 TTL input used for port reads and interrupt-on-change Important:  • Refer to the “Pin Allocation Table” for details about pin availability per port • Unimplemented bits will read back as ‘0’ © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 305 PIC18F06/16Q41 I/O Ports 19.14.7 SLRCONx Name:  SLRCONx Slew Rate Control Register Bit Access Reset 7 SLRx7 R/W 1 6 SLRx6 R/W 1 5 SLRx5 R/W 1 4 SLRx4 R/W 1 3 SLRx3 R/W 1 2 SLRx2 R/W 1 1 SLRx1 R/W 1 0 SLRx0 R/W 1 Bits 0, 1, 2, 3, 4, 5, 6, 7 – SLRxn Slew Rate Control on RX Pin Value Description 1 PORT pin slew rate is limited 0 PORT pin slews at maximum rate Important:  • Refer to the “Pin Allocation Table” for details about pin availability per port • Unimplemented bits will read back as ‘0’ © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 306 PIC18F06/16Q41 I/O Ports 19.14.8 ODCONx Name:  ODCONx Open-Drain Control Register Bit Access Reset 7 ODCx7 R/W 0 6 ODCx6 R/W 0 5 ODCx5 R/W 0 4 ODCx4 R/W 0 3 ODCx3 R/W 0 2 ODCx2 R/W 0 1 ODCx1 R/W 0 0 ODCx0 R/W 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 – ODCxn Open-Drain Configuration on Rx Pin Value Description 1 PORT pin operates as open-drain drive (sink current only) 0 PORT pin operates as standard push-pull drive (source and sink current) Important:  • Refer to the “Pin Allocation Table” for details about pin availability per port • Unimplemented bits will read back as ‘0’ © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 307 PIC18F06/16Q41 I/O Ports 19.14.9 RxyI2C Name:  RxyI2C I2C Pad Rxy Control Register Bit 7 6 5 SLEW[1:0] Access Reset R/W 0 4 3 2 1 0 PU[1:0] R/W 0 R/W 0 TH[1:0] R/W 0 R/W 0 R/W 0 Bits 7:6 – SLEW[1:0]  I2C Specific Slew Rate Limiting Control Value Description 11 I2C Fast mode Plus (1 MHz) slew rate enabled. The SLRxy bit is ignored. 10 Reserved 01 I2C Fast mode (400 kHz) slew rate enabled. The SLRxy bit is ignored. 00 Standard GPIO Slew Rate; enabled/disabled via the SLRxy bit Bits 5:4 – PU[1:0]  I2C Pull-Up Selection Bits 1:0 – TH[1:0]  I2C Input Threshold Selection Value Description 11 SMBus 3.0 (1.35V) input threshold 10 SMBus 2.0 (2.1V) input threshold 01 I2C-specific input thresholds 00 Standard GPIO Input pull-up, enabled via the INLVLxy registers Important:  • Refer to the “Pin Allocation Table” for details about pin availability per port • Unimplemented bits will read back as ‘0’ © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 308 PIC18F06/16Q41 I/O Ports 19.15 Address 0x00 ... 0x0285 0x0286 0x0287 0x0288 0x0289 0x028A ... 0x03FF 0x0400 0x0401 0x0402 0x0403 0x0404 0x0405 ... 0x0407 0x0408 0x0409 0x040A 0x040B 0x040C 0x040D ... 0x040F 0x0410 0x0411 0x0412 0x0413 0x0414 0x0415 ... 0x04BD 0x04BE 0x04BF 0x04C0 0x04C1 ... 0x04C5 0x04C6 0x04C7 0x04C8 0x04C9 ... 0x04CD 0x04CE 0x04CF 0x04D0 Register Summary - IO Ports Name Bit Pos. 7 6 5 4 3 2 1 0 Reserved RB6I2C RB4I2C RC1I2C RC0I2C 7:0 7:0 7:0 7:0 SLEW[1:0] SLEW[1:0] SLEW[1:0] SLEW[1:0] PU[1:0] PU[1:0] PU[1:0] PU[1:0] TH[1:0] TH[1:0] TH[1:0] TH[1:0] Reserved ANSELA WPUA ODCONA SLRCONA INLVLA 7:0 7:0 7:0 7:0 7:0 ANSELA5 WPUA5 ODCA5 SLRA5 INLVLA5 ANSELA4 WPUA4 ODCA4 SLRA4 INLVLA4 ANSELA3 WPUA3 INLVLA3 ANSELA2 WPUA2 ODCA2 SLRA2 INLVLA2 ANSELA1 WPUA1 ODCA1 SLRA1 INLVLA1 ANSELA0 WPUA0 ODCA0 SLRA0 INLVLA0 ANSELC3 WPUC3 ODCC3 SLRC3 INLVLC3 ANSELC2 WPUC2 ODCC2 SLRC2 INLVLC2 ANSELC1 WPUC1 ODCC1 SLRC1 INLVLC1 ANSELC0 WPUC0 ODCC0 SLRC0 INLVLC0 LATA2 LATA1 LATA0 LATC3 LATC2 LATC1 LATC0 Reserved ANSELB WPUB ODCONB SLRCONB INLVLB 7:0 7:0 7:0 7:0 7:0 ANSELB7 WPUB7 ODCB7 SLRB7 INLVLB7 ANSELB6 WPUB6 ODCB6 SLRB6 INLVLB6 ANSELB5 WPUB5 ODCB5 SLRB5 INLVLB5 ANSELB4 WPUB4 ODCB4 SLRB4 INLVLB4 7:0 7:0 7:0 7:0 7:0 ANSELC7 WPUC7 ODCC7 SLRC7 INLVLC7 ANSELC6 WPUC6 ODCC6 SLRC6 INLVLC6 ANSELC5 WPUC5 ODCC5 SLRC5 INLVLC5 ANSELC4 WPUC4 ODCC4 SLRC4 INLVLC4 7:0 7:0 7:0 LATB7 LATC7 LATB6 LATC6 LATA5 LATB5 LATC5 LATA4 LATB4 LATC4 7:0 7:0 7:0 TRISA4 TRISB4 TRISC4 TRISA2 TRISA1 TRISA0 TRISB6 TRISC6 TRISA5 TRISB5 TRISC5 Reserved TRISB7 TRISC7 TRISC3 TRISC2 TRISC1 TRISC0 7:0 7:0 7:0 RA4 RB4 RC4 RA2 RA1 RA0 RB6 RC6 RA5 RB5 RC5 RA3 RB7 RC7 RC3 RC2 RC1 RC0 Reserved ANSELC WPUC ODCONC SLRCONC INLVLC Reserved LATA LATB LATC Reserved TRISA TRISB TRISC Reserved PORTA PORTB PORTC © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 309 PIC18F06/16Q41 IOC - Interrupt-on-Change 20. IOC - Interrupt-on-Change 20.1 Overview The pins denoted in the table below can be configured to operate as interrupt-on-change (IOC) pins for this device. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORT pin, or combination of PORT pins, can be configured to generate an interrupt. Table 20-1. IOC Pin Availability per Device Device PORTA 14-pin devices ● 20-pin devices ● PORTB PORTC ● ● ● Important:  If MCLRE = 1 or LVP = 1, the MCLR pin port functionality is disabled and IOC on that pin is not available. The interrupt-on-change module has the following features: • Interrupt-on-change enable (Host Switch) • Individual pin configuration • Rising and falling edge detection • Individual pin interrupt flags The following figure is a block diagram of the IOC module. Figure 20-1. Interrupt-on-Change Block Diagram (PORTA Example) Positive Edge Detect IOCAPx RAx IOC Flag Set/Reset Logic IOCIE Negative Edge Detect IOCANx 20.2 Write to IOCAFx flag IOC interrupt to CPU core From all other IOCnFx flags Enabling the Module For individual PORT pins to generate an interrupt, the IOC Interrupt Enable (IOCIE) bit of the Peripheral Interrupt Enable (PIEx) register must be set. If the IOC Interrupt Enable bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 310 PIC18F06/16Q41 IOC - Interrupt-on-Change 20.3 Individual Pin Configuration A rising edge detector and a falling edge detector are present for each PORT pin. To enable a pin to detect a rising edge, the associated bit of the IOCxP register must be set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register must be set. A PORT pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively. 20.4 Interrupt Flags The bits located in the IOCxF registers are status flags that correspond to the interrupt-on-change pins of each port. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit located in the corresponding Peripheral Interrupt Request (PIRx) register, is all the IOCxF bits ORd together. The IOCIF bit is read-only. All of the IOCxF Status bits must be cleared to clear the IOCIF bit. 20.5 Clearing Interrupt Flags The individual status flags (IOCxF register bits) will be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. To ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits must be performed. The following sequence is an example of clearing an IOC interrupt flag using this method. Example 20-1. Clearing Interrupt Flags (PORTA Example) MOVLW XORWF ANDWF 20.6 0xff IOCAF, W IOCAF, F Operation in Sleep An interrupt-on-change event will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCxF register will be updated prior to the first instruction executed out of Sleep. 20.7 Register Definitions: Interrupt-on-Change Control © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 311 PIC18F06/16Q41 IOC - Interrupt-on-Change 20.7.1 IOCxF Name:  IOCxF Interrupt-on-Change Flag Register Bit Access Reset 7 IOCxF7 R/W/HS 0 6 IOCxF6 R/W/HS 0 5 IOCxF5 R/W/HS 0 4 IOCxF4 R/W/HS 0 3 IOCxF3 R/W/HS 0 2 IOCxF2 R/W/HS 0 1 IOCxF1 R/W/HS 0 0 IOCxF0 R/W/HS 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCxFn Interrupt-on-Change Flag Value Condition Description 1 IOCxP[n] = 1 A positive edge was detected on the Rx[n] pin 1 IOCxN[n] = 1 A negative edge was detected on the Rx[n] pin 0 IOCxP[n] = x and IOCxN[n] = x No change was detected, or the user cleared the detected change Important:  • If MCLRE = 1 or LVP = 1, the MCLR pin port functionality is disabled and IOC on that pin is not available • Refer to the “Pin Allocation Table” for details about pins with configurable IOC per port © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 312 PIC18F06/16Q41 IOC - Interrupt-on-Change 20.7.2 IOCxN Name:  IOCxN Interrupt-on-Change Negative Edge Register Example Bit Access Reset 7 IOCxN7 R/W 0 6 IOCxN6 R/W 0 5 IOCxN5 R/W 0 4 IOCxN4 R/W 0 3 IOCxN3 R/W 0 2 IOCxN2 R/W 0 1 IOCxN1 R/W 0 0 IOCxN0 R/W 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCxNn Interrupt-on-Change Negative Edge Enable Value Description 1 Interrupt-on-change enabled on the IOCx pin for a negative-going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 Falling edge interrupt-on-change disabled for the associated pin Important:  • If MCLRE = 1 or LVP = 1, the MCLR pin port functionality is disabled and IOC on that pin is not available • Refer to the “Pin Allocation Table” for details about pins with configurable IOC per port © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 313 PIC18F06/16Q41 IOC - Interrupt-on-Change 20.7.3 IOCxP Name:  IOCxP Interrupt-on-Change Positive Edge Register Bit Access Reset 7 IOCxP7 R/W 0 6 IOCxP6 R/W 0 5 IOCxP5 R/W 0 4 IOCxP4 R/W 0 3 IOCxP3 R/W 0 2 IOCxP2 R/W 0 1 IOCxP1 R/W 0 0 IOCxP0 R/W 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCxPn Interrupt-on-Change Positive Edge Enable Value Description 1 Interrupt-on-change enabled on the IOCx pin for a positive-going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 Rising edge interrupt-on-change disabled for the associated pin. Important:  • If MCLRE = 1 or LVP = 1, the MCLR pin port functionality is disabled and IOC on that pin is not available • Refer to the “Pin Allocation Table” for details about pins with configurable IOC per port © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 314 PIC18F06/16Q41 IOC - Interrupt-on-Change 20.8 Address 0x00 ... 0x0404 0x0405 0x0406 0x0407 0x0408 ... 0x040C 0x040D 0x040E 0x040F 0x0410 ... 0x0414 0x0415 0x0416 0x0417 Register Summary - Interrupt-on-Change Control Name Bit Pos. 7 6 5 4 3 2 1 0 IOCAP5 IOCAN5 IOCAF5 IOCAP4 IOCAN4 IOCAF4 IOCAP3 IOCAN3 IOCAF3 IOCAP2 IOCAN2 IOCAF2 IOCAP1 IOCAN1 IOCAF1 IOCAP0 IOCAN0 IOCAF0 IOCCP3 IOCCN3 IOCCF3 IOCCP2 IOCCN2 IOCCF2 IOCCP1 IOCCN1 IOCCF1 IOCCP0 IOCCN0 IOCCF0 Reserved IOCAP IOCAN IOCAF 7:0 7:0 7:0 Reserved IOCBP IOCBN IOCBF 7:0 7:0 7:0 IOCBP7 IOCBN7 IOCBF7 IOCBP6 IOCBN6 IOCBF6 IOCBP5 IOCBN5 IOCBF5 IOCBP4 IOCBN4 IOCBF4 7:0 7:0 7:0 IOCCP7 IOCCN7 IOCCF7 IOCCP6 IOCCN6 IOCCF6 IOCCP5 IOCCN5 IOCCF5 IOCCP4 IOCCN4 IOCCF4 Reserved IOCCP IOCCN IOCCF © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 315 PIC18F06/16Q41 PPS - Peripheral Pin Select Module 21. PPS - Peripheral Pin Select Module 21.1 Filename: Overview PPS Block Diagram.vsdx Title: The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital Last Edit: 3/26/2019 signals areFirst included Used: in the selections. Notes: Important:  All analog inputs and outputs remain fixed to their assigned pins and cannot be changed through PPS. Input and output selections are independent as shown in the figure below. Figure 21-1. PPS Block Diagram abcPPS RA0PPS RA0 Peripheral abc RA0 Rxy Peripheral xyz Rxy RxyPPS xyzPPS Input selections 21.2 Output selections PPS Inputs Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register with which the input pin to the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while devices with 28 leads or more allow PPS routing to I/Os contained within two ports (see the table below). Important:  The notation “xxx” in the generic register name is a placeholder for the peripheral identifier. For example, xxx = T0CKI for the T0CKIPPS register. Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 316 PIC18F06/16Q41 PPS - Peripheral Pin Select Module Table 21-1. PPS Input Selection Table Peripheral PPS Input Register 14-Pin Devices 20-Pin Devices Default Pin Register Available Default Pin Register Available Selection Reset Input Port Selection Reset Input Port at POR Value at at POR Value at POR POR ‘b000 010 A ‘b010 000 A Interrupt 0 INT0PPS RA2 — C RC0 B C ‘b000 100 ‘b010 001 Interrupt 1 INT1PPS RA4 A — C RC1 A B C ‘b000 101 A ‘b010 010 A Interrupt 2 INT2PPS RA5 — C RC2 B C ‘b000 010 A ‘b010 101 A Timer0 Clock T0CKIPPS RA2 — C RC5 B C ‘b000 101 ‘b010 110 Timer1 Clock T1CKIPPS RA5 A — C RC6 A B C ‘b000 100 A ‘b000 100 A Timer1 Gate T1GPPS RA4 — C RA4 B C ‘b010 101 A ‘b010 101 A Timer3 Clock T3CKIPPS RC5 — C RC5 B C ‘b010 100 A ‘b010 100 A Timer3 Gate T3GPPS RC4 — C RC4 B C ‘b000 101 A ‘b000 101 A Timer2 Input T2INPPS RA5 — C RA5 B C ‘b010 001 ‘b010 001 Timer4 Input T4INPPS RC1 A — C RC1 A B C ‘b010 101 A ‘b010 101 A CCP1 CCP1PPS RC5 — C RC5 B C ‘b000 101 A ‘b000 101 A SMT1 Window SMT1WINPPS RA5 — C RA5 B C ‘b010 000 ‘b000 100 SMT1 Signal SMT1SIGPPS RC0 A — C RA4 A B C ‘b010 101 A ‘b010 101 A PWM Input 0 PWMIN0PPS RC5 — C RC5 B C ‘b010 011 A ‘b010 011 A PWM Input 1 PWMIN1PPS RC3 — C RC3 B C ‘b000 101 A ‘b000 101 A PWM1 PWM1ERSPPS RA5 — C RA5 B C External Reset Source ‘b010 001 A ‘b010 001 A PWM2 PWM2ERSPPS RC1 — C RC1 B C External Reset Source ‘b010 010 A ‘b010 010 A PWM3 PWM3ERSPPS RC2 — C RC2 B C External Reset Source ‘b000 010 A ‘b000 010 A CWG1 CWG1PPS RA2 — C RA2 B C ‘b010 010 A ‘b010 010 A DSM1 Carrier MD1CARLPPS RC2 — C RC2 B C Low ‘b010 101 A ‘b010 101 A DSM1 Carrier MD1CARHPPS RC5 — C RC5 B C High ‘b000 001 A ‘b000 001 A DSM1 Source MD1SRCPPS RA1 — C RA1 B C ‘b010 011 A ‘b000 010 A CLCx Input 1 CLCIN0PPS RC3 — C RA2 B C ‘b010 100 A ‘b010 011 A CLCx Input 2 CLCIN1PPS RC4 — C RC3 B C ‘b010 001 A ‘b001 100 A CLCx Input 3 CLCIN2PPS RC1 — C RB4 B C ‘b000 100 ‘b001 101 CLCx Input 4 CLCIN3PPS RA4 A — C RB5 A B C ‘b010 010 A ‘b010 010 A ADC ADACTPPS RC2 — C RC2 B C Conversion Trigger ‘b010 000 A ‘b001 110 A SPI1 Clock SPI1SCKPPS RC0 — C RB6 B C ‘b010 001 A ‘b001 100 A SPI1 Data SPI1SDIPPS RC1 — C RB4 B C ‘b010 011 ‘b010 110 SPI1 Client SPI1SSPPS RC3 A — C RC6 A B C Select ‘b010 100 A ‘b001 111 A SPI2 Clock SPI2SCKPPS RC4 — C RB7 B C ‘b010 101 A ‘b001 101 A SPI2 Data SPI2SDIPPS RC5 — C RB5 B C © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 317 PIC18F06/16Q41 PPS - Peripheral Pin Select Module ...........continued Peripheral PPS Input Register SPI2 Client Select I2C1 Clock I2C1 Data UART1 Receive UART1 Clear to Send UART2 Receive UART2 Clear to Send UART3 Receive UART3 Clear to Send SPI2SSPPS RA0 14-Pin Devices 20-Pin Devices Register Available Default Pin Register Available Reset Input Port Selection Reset Input Port Value at at POR Value at POR POR ‘b000 000 A ‘b000 001 A — C RA1 B C I2C1SCLPPS(1) I2C1SDAPPS(1) U1RXPPS RC0 RC1 RC5 ‘b010 000 A ‘b010 001 A ‘b010 101 A — — — C C C RB6 RB4 RB5 ‘b001 110 ‘b001 100 ‘b001 101 A A A B B B C C C U1CTSPPS RC4 ‘b010 100 A — C RB7 ‘b001 111 A B C U2RXPPS RC1 ‘b010 001 A — C RC1 ‘b010 001 A B C U2CTSPPS RC2 ‘b010 010 A — C RC2 ‘b010 010 A B C U3RXPPS RA4 ‘b000 100 A — C RC3 ‘b010 011 A B C U3CTSPPS RA5 ‘b000 101 A — C RC5 ‘b010 101 A B C Default Pin Selection at POR Note:  1. Bidirectional pin. The corresponding output must select the same pin. 21.3 PPS Outputs Each digital peripheral has a dedicated Pin Rxy Output Source Selection (RxyPPS) register with which the pin output source is selected. With few exceptions, the port TRIS control associated with that pin retains control over the pin output driver. Peripherals that control the pin output driver as part of the peripheral operation will override the TRIS control as needed. The I2C module is an example of such a peripheral. Important:  The notation ‘Rxy’ is a placeholder for the pin identifier. The ‘x’ holds the place of the PORT letter and the ‘y’ holds the place of the bit number. For example, Rxy = RA0 for the RA0PPS register. The table below shows the output codes for each peripheral, as well as the available Port selections. Table 21-2. PPS Output Selection Table RxyPPS 0x28 0x27 0x26 0x25 0x24 0x23 0x22 0x21 0x20 Output Source ADGRDB ADGRDA DSM1 CLKR NCO1 TMR0 I2C1 SDA(1) I2C1 SCL(1) SPI2 SS © 2020-2021 Microchip Technology Inc. and its subsidiaries A A A A A A A A A Available Output Ports 14-Pin Devices 20-Pin Devices — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B Preliminary Datasheet C C C C C C C C C DS40002214E-page 318 PIC18F06/16Q41 PPS - Peripheral Pin Select Module ...........continued RxyPPS Output Source 0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 SPI2 SDO SPI2 SCK SPI1 SS SPI1 SDO SPI1 SCK C2OUT C1OUT UART3 RTS UART3 TXDE UART3 TX UART2 RTS UART2 TXDE UART2 TX UART1 RTS UART1 TXDE UART1 TX PWM3S1P2_OUT PWM3S1P1_OUT PWM2S1P2_OUT PWM2S1P1_OUT PWM1S1P2_OUT PWM1S1P1_OUT CCP1 CWG1D CWG1C CWG1B CWG1A CLC4OUT CLC3OUT CLC2OUT CLC1OUT LATxy A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Available Output Ports 14-Pin Devices 20-Pin Devices — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B — C A B C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C Note:  1. Bidirectional pin. The corresponding input must select the same pin. 21.4 Bidirectional Pins PPS selections for peripherals with bidirectional signals on a single pin must be made so that the PPS input and PPS output select the same pin. The I2C Serial Clock (SCL) and Serial Data (SDA) are examples of such pins. Important:  The I2C default pins and a limited number of other alternate pins are I2C and SMBus compatible. SDA and SCL signals can be routed to any pin; however, pins without I2C compatibility will operate at standard TTL/ST logic levels as selected by the port’s INLVL register. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 319 PIC18F06/16Q41 PPS - Peripheral Pin Select Module 21.5 PPS Lock The PPS module provides an extra layer of protection to prevent inadvertent changes to the PPS selection registers. The PPSLOCKED bit is used in combination with specific code execution blocks to lock/unlock the PPS selection registers. Important:  The PPSLOCKED bit is clear by default (PPSLOCKED = 0), which allows the PPS selection registers to be modified without an unlock sequence. PPS selection registers are locked when the PPSLOCKED bit is set (PPSLOCKED = 1). Setting the PPSLOCKED bit requires a specific lock sequence as shown in the examples below in both C and assembly languages. PPS selection registers are unlocked when the PPSLOCKED bit is clear (PPSLOCKED = 0). Clearing the PPSLOCKED bit requires a specific unlock sequence as shown in the examples below in both C and assembly languages. Important:  All interrupts must be disabled before starting the lock/unlock sequence to ensure proper execution. Example 21-1. PPS Lock Sequence (assembly language) ; suspend interrupts BCF INTCON0,GIE BANKSEL PPSLOCK ; required sequence, next 5 instructions MOVLW 0x55 MOVWF PPSLOCK MOVLW 0xAA MOVWF PPSLOCK ; Set PPSLOCKED bit BSF PPSLOCK,PPSLOCKED ; restore interrupts BSF INTCON0,GIE Example 21-2. PPS Lock Sequence (C language) INTCON0bits.GIE = 0; PPSLOCK = 0x55; PPSLOCK = 0xAA; PPSLOCKbits.PPSLOCKED = 1; INTCON0bits.GIE = 1; //Suspend interrupts //Required sequence //Required sequence //Set PPSLOCKED bit //Restore interrupts Example 21-3. PPS Unlock Sequence (assembly language) ; suspend interrupts BCF INTCON0,GIE BANKSEL PPSLOCK ; required sequence, next 5 instructions MOVLW 0x55 MOVWF PPSLOCK MOVLW 0xAA MOVWF PPSLOCK ; Clear PPSLOCKED bit BCF PPSLOCK,PPSLOCKED © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 320 PIC18F06/16Q41 PPS - Peripheral Pin Select Module ; restore interrupts BSF INTCON0,GIE Example 21-4. PPS Unlock Sequence (C language) INTCON0bits.GIE = 0; PPSLOCK = 0x55; PPSLOCK = 0xAA; PPSLOCKbits.PPSLOCKED = 0; INTCON0bits.GIE = 1; 21.5.1 //Suspend interrupts //Required sequence //Required sequence //Clear PPSLOCKED bit //Restore interrupts PPS One-Way Lock The PPS1WAY Configuration bit can also be used to prevent inadvertent modification to the PPS selection registers. When the PPS1WAY bit is set (PPS1WAY = 1), the PPSLOCKED bit can only be set one time after a device Reset. Once the PPSLOCKED bit has been set, it cannot be cleared again unless a device Reset is executed. When the PPS1WAY bit is clear (PPS1WAY = 0), the PPSLOCKED bit can be set or cleared as needed; however, the PPS lock/unlock sequences must be executed. 21.6 Operation During Sleep PPS input and output selections are unaffected by Sleep. 21.7 Effects of a Reset A device Power-on Reset (POR) or Brown-out Reset (BOR) returns all PPS input selection registers to their default values and clears all PPS output selection registers. All other Resets leave the selections unchanged. Default input selections are shown in the PPS input register details table. The PPSLOCKED bit is cleared in all Reset conditions. 21.8 Register Definitions: Peripheral Pin Select (PPS) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 321 PIC18F06/16Q41 PPS - Peripheral Pin Select Module 21.8.1 xxxPPS Name:  xxxPPS Peripheral Input Selection Register Bit 7 Access Reset 6 5 R/W m 4 PORT[2:0] R/W m 3 2 R/W m R/W m 1 PIN[2:0] R/W m 0 R/W m Bits 5:3 – PORT[2:0]  Peripheral Input PORT Selection(1) See the PPS Input Selection Table for the list of available Ports and default pin locations. Reset States: POR = mmm All other Resets = uuu Value Description 010 PORTC 001 PORTB 000 PORTA Bits 2:0 – PIN[2:0]  Peripheral Input PORT Pin Selection(2) Reset States: POR = mmm All other Resets = uuu Value Description 111 Peripheral input is from PORTx Pin 7 (Rx7) 110 Peripheral input is from PORTx Pin 6 (Rx6) 101 Peripheral input is from PORTx Pin 5 (Rx5) 100 Peripheral input is from PORTx Pin 4 (Rx4) 011 Peripheral input is from PORTx Pin 3 (Rx3) 010 Peripheral input is from PORTx Pin 2 (Rx2) 001 Peripheral input is from PORTx Pin 1 (Rx1) 000 Peripheral input is from PORTx Pin 0 (Rx0) Notes:  1. The Reset value ‘m’ is determined by device default locations for that input. 2. Refer to the “Pin Allocation Table” for details about available pins per port. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 322 PIC18F06/16Q41 PPS - Peripheral Pin Select Module 21.8.2 RxyPPS Name:  RxyPPS Pin Rxy Output Source Selection Register Bit 7 Access Reset 6 5 4 R/W 0 R/W 0 R/W 0 3 RxyPPS[6:0] R/W 0 2 1 0 R/W 0 R/W 0 R/W 0 Bits 6:0 – RxyPPS[6:0] Pin Rxy Output Source Selection See the PPS Output Selection Table for the list of RxyPPS Output Source codes Reset States: POR = 0000000 All other Resets = uuuuuuu © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 323 PIC18F06/16Q41 PPS - Peripheral Pin Select Module 21.8.3 PPSLOCK Name:  PPSLOCK PPS Lock Register Bit 7 6 5 4 3 Access Reset 2 1 0 PPSLOCKED R/W 0 Bit 0 – PPSLOCKED PPS Locked Reset States: POR = 0 All other Resets = 0 Value Description 1 PPS is locked. PPS selections cannot be changed. Writes to any PPS register are ignored. 0 PPS is not locked. PPS selections can be changed, but may require the PPS lock/unlock sequence. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 324 PIC18F06/16Q41 PPS - Peripheral Pin Select Module 21.9 Address 0x00 ... 0x01FF 0x0200 0x0201 0x0202 0x0203 0x0204 0x0205 0x0206 0x0207 ... 0x020C 0x020D 0x020E 0x020F 0x0210 0x0211 0x0212 0x0213 0x0214 0x0215 0x0216 0x0217 0x0218 0x0219 ... 0x023D 0x023E 0x023F 0x0240 0x0241 0x0242 0x0243 0x0244 0x0245 0x0246 ... 0x0247 0x0248 0x0249 0x024A ... 0x024E 0x024F 0x0250 0x0251 0x0252 0x0253 0x0254 ... 0x0256 0x0257 0x0258 0x0259 0x025A Register Summary - Peripheral Pin Select Module Name Bit Pos. 7 6 5 4 3 2 1 0 Reserved PPSLOCK RA0PPS RA1PPS RA2PPS Reserved RA4PPS RA5PPS 7:0 7:0 7:0 7:0 RA0PPS[5:0] RA1PPS[5:0] RA2PPS[5:0] PPSLOCKED 7:0 7:0 RA4PPS[5:0] RA5PPS[5:0] 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 RB4PPS[5:0] RB5PPS[5:0] RB6PPS[5:0] RB7PPS[5:0] RC0PPS[5:0] RC1PPS[5:0] RC2PPS[5:0] RC3PPS[5:0] RC4PPS[5:0] RC5PPS[5:0] RC6PPS[5:0] RC7PPS[5:0] Reserved RB4PPS RB5PPS RB6PPS RB7PPS RC0PPS RC1PPS RC2PPS RC3PPS RC4PPS RC5PPS RC6PPS RC7PPS Reserved INT0PPS INT1PPS INT2PPS T0CKIPPS T1CKIPPS T1GPPS T3CKIPPS T3GPPS 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 PORT PORT[1:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] 7:0 7:0 PORT[2:0] PORT[2:0] PIN[2:0] PIN[2:0] 7:0 PORT[2:0] PIN[2:0] 7:0 7:0 7:0 PORT[1:0] PORT[2:0] PORT[1:0] PIN[2:0] PIN[2:0] PIN[2:0] 7:0 7:0 7:0 7:0 PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] Reserved T2INPPS T4INPPS Reserved CCP1PPS Reserved PWM1ERSPPS PWM2ERSPPS PWM3ERSPPS Reserved PWMIN0PPS PWMIN1PPS SMT1WINPPS SMT1SIGPPS © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 325 PIC18F06/16Q41 PPS - Peripheral Pin Select Module ...........continued Address Name Bit Pos. 7 6 5 4 3 2 1 0x025B 0x025C ... 0x025D 0x025E 0x025F 0x0260 0x0261 0x0262 0x0263 0x0264 0x0265 ... 0x0268 0x0269 0x026A 0x026B 0x026C 0x026D 0x026E 0x026F 0x0270 0x0271 0x0272 0x0273 0x0274 0x0275 0x0276 0x0277 CWG1PPS 7:0 PORT[2:0] PIN[2:0] 7:0 7:0 7:0 7:0 7:0 7:0 7:0 PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[1:0] PORT[1:0] PORT PORT PORT[1:0] PORT[1:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] 0 Reserved MD1CARLPPS MD1CARHPPS MD1SRCPPS CLCIN0PPS CLCIN1PPS CLCIN2PPS CLCIN3PPS Reserved ADACTPPS SPI1SCKPPS SPI1SDIPPS SPI1SSPPS SPI2SCKPPS SPI2SDIPPS SPI2SSPPS I2C1SDAPPS I2C1SCLPPS U1RXPPS U1CTSPPS UxRXPPS UxCTSPPS U3RXPPS U3CTSPPS © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 326 PIC18F06/16Q41 CLC - Configurable Logic Cell CLC - Configurable Logic Cell The Configurable Logic Cell (CLC) module provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 256 input signals and, through the use of configurable gates, reduces those inputs to four logic lines that drive one of eight selectable single-output logic functions. Input sources are a combination of the following: • I/O pins • Internal clocks • Peripherals • Register bits The output can be directed internally to peripherals and to an output pin. The following figure is a simplified diagram showing signal flow through the CLC. Possible configurations include: • Combinatorial Logic – AND – NAND – AND-OR – AND-OR-INVERT – OR-XOR – OR-XNOR • Latches – SR – Clocked D with Set and Reset – Transparent D with Set and Reset Figure 22-1. CLC Simplified Block Diagram D OUT CLCxOUT Q Q1 LCx_in[0] LCx_in[1] LCx_in[2] . . . LCx_in[n-2] LCx_in[n-1] LCx_in[n] CLCx_out Input Data Selection Gates(1) 22. EN lcx g1 lcx g2 lcx g3 to Peripherals RxyPPS Logic lcxq Function PPS CLCx (2) lcx g4 POL MODE TRIS Interrupt det INTP INTN set bit CLCxIF Interrupt det © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 327 PIC18F06/16Q41 CLC - Configurable Logic Cell Notes:  1. See Figure 22-2 for input data selection and gating. 2. See Figure 22-3 for programmable logic functions. 22.1 CLC Setup Programming the CLC module is performed by configuring the four stages in the logic signal flow. The four stages are: • Data selection • Data gating • Logic function selection • Output polarity Each stage is set up at run time by writing to the corresponding CLC Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution. 22.1.1 Data Selection Data inputs are selected with CLCnSEL0 through CLCnSEL3 registers. Important:  Data selections are undefined at power-up. Depending on the number of bits implemented in the CLCnSELy registers, there can be as many as 256 sources available as inputs to the configurable logic. Four multiplexers are used to independently select these inputs to pass on to the next stage as indicated on the left side of the following diagram. Data inputs in the figure are identified by a generic numbered input name. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 328 PIC18F06/16Q41 CLC - Configurable Logic Cell Figure 22-2. Input Data Selection and Gating Data Selection LCx_in[0] Data GATE 1 G1D1T d1T G1D1N d1N G1D2T LCx_in[n] G1D2N D1S lcxg1 G1D3T LCx_in[0] d2T d2N LCx_in[n] G1POL G1D3N G1D4T G1D4N D2S LCx_in[0] Data GATE 2 d3T lcxg2 d3N (Same as Data GATE 1) LCx_in[n] D3S Data GATE 3 LCx_in[0] lcxg3 (Same as Data GATE 1) d4T d4N Data GATE 4 LCx_in[n] lcxg4 D4S (Same as Data GATE 1) Note: are All undefined controls are undefined at power up Note:  All controls at power-up. The CLC Input Selection table correlates the generic input name to the actual signal for each CLC module. The table column labeled ‘DyS Value’ indicates the MUX selection code for the selected data input. DyS is an abbreviation for the MUX select input codes, D1S through D4S, where ‘y’ is the gate number. 22.1.2 Data Gating Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or noninverted data. Directed signals are ANDed together in each gate. The output of each gate can be inverted before going on to the logic function stage. The gating is in essence a 1-to-4 input AND/NAND/OR/NOR gate. When every input is inverted and the output is inverted, the gate is an AND of all enabled data inputs. When the inputs and output are not inverted, the gate is an OR or all enabled inputs. Table 22-1 summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. The table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are selected, the output will be ‘0’ or ‘1’, depending on the gate output polarity bit. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 329 PIC18F06/16Q41 CLC - Configurable Logic Cell Table 22-1. Data Gating Logic CLCnGLSy 0x55 0x55 0xAA 0xAA GyPOL 1 0 0x00 0 Gate Logic AND NAND NOR OR Logic ‘0’ 0x00 1 Logic ‘1’ 1 0 It is possible (but not recommended) to select both the true and negated values of an input. When this is done, the gate output is ‘0’, regardless of the other inputs, but may emit logic glitches (transient-induced pulses). If the output of the channel must be ‘0’ or ‘1’, the recommended method is to set all gate bits to ‘0’ and use the gate polarity bit to set the desired level. Data gating is configured with the logic gate select registers as follows: • Gate 1: CLCnGLS0 • Gate 2: CLCnGLS1 • Gate 3: CLCnGLS2 • Gate 4: CLCnGLS3 Note:  Register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register. Data gating is indicated in the right side of Figure 22-2. Only one gate is shown in detail. The remaining three gates are configured identically, except when the data enables correspond to the enables for that gate. 22.1.3 Logic Function There are eight available logic functions including: • • • • • • • • AND-OR OR-XOR AND SR Latch D Flip-Flop with Set and Reset D Flip-Flop with Reset J-K Flip-Flop with Reset Transparent Latch with Set and Reset Logic functions are shown in the following diagram. Each logic function has four inputs and one output. The four inputs are the four data gate outputs of the previous stage. The output is fed to the inversion stage and from there to other peripherals, an output pin, and back to the CLC itself. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 330 PIC18F06/16Q41 CLC - Configurable Logic Cell Figure 22-3. Programmable Logic Functions Rev. 10-000122B 9/13/2016 AND-OR OR-XOR lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxq lcxg3 lcxg3 lcxg4 lcxg4 MODE = 000 MODE = 001 4-input AND S-R Latch lcxg1 lcxg1 S lcxg2 lcxg2 lcxg3 lcxg4 Q lcxq R lcxg4 MODE = 010 MODE = 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R lcxg4 D lcxg1 S Q lcxq lcxg4 D lcxg2 lcxg1 R lcxg3 lcxg2 lcxq lcxq lcxg3 lcxg2 Q R lcxg3 MODE = 100 MODE = 101 J-K Flip-Flop with R 1-Input Transparent Latch with S and R J Q lcxq lcxg4 lcxg2 D lcxg3 LE S Q lcxq lcxg1 lcxg4 K R lcxg3 MODE = 110 22.1.4 R lcxg1 MODE = 111 Output Polarity The last stage in the Configurable Logic Cell is the output polarity. Setting the POL bit inverts the output signal from the logic stage. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. 22.2 CLC Interrupts An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose. The CLCxIF bit of the associated PIR register will be set when either edge detector is triggered and its associated enable bit is set. The INTP bit enables rising edge interrupts and the INTN bit enables falling edge interrupts. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 331 PIC18F06/16Q41 CLC - Configurable Logic Cell To fully enable the interrupt, set the following bits: • CLCxIE bit of the respective PIE register • INTP bit (for a rising edge detection) • INTN bit (for a falling edge detection) If priority interrupts are not used: 1. Clear the IPEN bit of the INTCON register. 2. Set the GIE bit of the INTCON register. 3. Set the GIEL bit of the INTCON register. If the CLC is a high priority interrupt: 1. Set the IPEN bit of the INTCON register. 2. Set the CLCxIP bit of the respective IPR register. 3. Set the GIEH bit of the INTCON register. If the CLC is a low priority interrupt: 1. Set the IPEN bit of the INTCON register. 2. Clear the CLCxIP bit of the respective IPR register. 3. Set the GIEL bit of the INTCON register. The CLCxIF bit of the respective PIR register must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 22.3 Effects of a Reset The CLCnCON register is cleared to ‘0’ as the result of a Reset. All other selection and gating values remain unchanged. 22.4 Output Mirror Copies Mirror copies of all CLCxOUT bits are contained in the CLCDATA register. Reading this register reads the outputs of all CLCs simultaneously. This prevents any reading skew introduced by testing or reading the OUT bits in the individual CLCnCON registers. 22.5 Operation During Sleep The CLC module operates independently from the system clock and will continue to run during Sleep, provided that the input sources selected remain Active. The HFINTOSC remains Active during Sleep when the CLC module is enabled and the HFINTOSC is selected as an input source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as both the system clock and as a CLC input source then, when the CLC is enabled, the CPU will go Idle during Sleep, but the CLC will continue to operate and the HFINTOSC will remain Active. This will have a direct effect on the Sleep mode current. 22.6 CLC Setup Steps These steps need to be followed when setting up the CLC: 1. 2. 3. 4. Disable the CLC by clearing the EN bit. Select the desired inputs using the CLCnSEL0 through CLCnSEL3 registers. Clear any ANSEL bits associated with CLC input pins. Set all TRIS bits associated with inputs. However, a CLC input will also operate if the pin is configured as an output, in which case the TRIS bits must be cleared. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 332 PIC18F06/16Q41 CLC - Configurable Logic Cell 5. 6. 7. 8. Enable the chosen inputs through the four gates using the CLCnGLS0 through CLCnGLS3 registers. Select the gate output polarities with the GyPOL bits. Select the desired logic function with the MODE bits. Select the desired polarity of the logic output with the POL bit (this step may be combined with the previous gate output polarity step). 9. If driving a device pin, configure the associated pin PPS control register and also clear the TRIS bit corresponding to that output. 10. Configure the interrupts (optional). See the CLC Interrupts section. 11. Enable the CLC by setting the EN bit. 22.7 Register Overlay All CLCs in this device share the same set of registers. Only one CLC instance is accessible at a time. The value in the CLCSELECT register is one less than the selected CLC instance. For example, a CLCSELECT value of ‘0’ selects CLC1. 22.8 Register Definitions: Configurable Logic Cell © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 333 PIC18F06/16Q41 CLC - Configurable Logic Cell 22.8.1 CLCSELECT Name:  Address:  CLCSELECT 0x0D5 CLC Instance Selection Register Selects which CLC instance is accessed by the CLC registers Bit 7 6 5 4 3 2 1 0 SLCT[1:0] Access Reset R/W 0 R/W 0 Bits 1:0 – SLCT[1:0] CLC instance selection Value Description n Shared CLC registers of instance n+1 are selected for read and write operations © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 334 PIC18F06/16Q41 CLC - Configurable Logic Cell 22.8.2 CLCnCON Name:  Address:  CLCnCON 0x0D6 Configurable Logic Cell Control Register Bit Access Reset 7 EN R/W 0 6 5 OUT R 0 4 INTP R/W 0 3 INTN R/W 0 2 R/W 0 1 MODE[2:0] R/W 0 0 R/W 0 Bit 7 – EN CLC Enable Value Description 1 Configurable logic cell is enabled and mixing signals 0 Configurable logic cell is disabled and has logic zero output Bit 5 – OUT Logic cell output data, after LCPOL. Sampled from CLCxOUT. Bit 4 – INTP Configurable Logic Cell Positive Edge Going Interrupt Enable Value Description 1 CLCxIF will be set when a rising edge occurs on CLCxOUT 0 Rising edges on CLCxOUT have no effect on CLCxIF Bit 3 – INTN Configurable Logic Cell Negative Edge Going Interrupt Enable Value Description 1 CLCxIF will be set when a falling edge occurs on CLCxOUT 0 Falling edges on CLCxOUT have no effect on CLCxIF Bits 2:0 – MODE[2:0] Configurable Logic Cell Functional Mode Selection Value Description 111 Cell is 1-input transparent latch with Set and Reset 110 Cell is J-K flip-flop with Reset 101 Cell is 2-input D flip-flop with Reset 100 Cell is 1-input D flip-flop with Set and Reset 011 Cell is SR latch 010 Cell is 4-input AND 001 Cell is OR-XOR 000 Cell is AND-OR © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 335 PIC18F06/16Q41 CLC - Configurable Logic Cell 22.8.3 CLCnPOL Name:  Address:  CLCnPOL 0x0D7 Signal Polarity Control Register Bit Access Reset 7 POL R/W 0 6 5 4 3 G4POL R/W x 2 G3POL R/W x 1 G2POL R/W x 0 G1POL R/W x Bit 7 – POL CLCxOUT Output Polarity Control Value Description 1 The output of the logic cell is inverted 0 The output of the logic cell is not inverted Bits 0, 1, 2, 3 – GyPOL Gate Output Polarity Control Reset States: POR/BOR = xxxx All Other Resets = uuuu Value Description 1 The gate output is inverted when applied to the logic cell 0 The output of the gate is not inverted © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 336 PIC18F06/16Q41 CLC - Configurable Logic Cell 22.8.4 CLCnSEL0 Name:  Address:  CLCnSEL0 0x0D8 Generic CLCn Data 1 Select Register Bit 7 Access Reset 6 5 4 R/W x R/W x R/W x 3 D1S[6:0] R/W x 2 1 0 R/W x R/W x R/W x Bits 6:0 – D1S[6:0] CLCn Data1 Input Selection Table 22-2. CLC Input Selection DyS Input Source DyS (cont.) Input Source (cont.) [0] 0000 0000 CLCIN0PPS [26] 0001 1010 PWM3S1P2_OUT [1] 0000 0001 CLCIN1PPS [27] 0001 1011 NCO1 [2] 0000 0010 CLCIN2PPS [28] 0001 1100 CMP1_OUT [3] 0000 0011 CLCIN3PPS [29] 0001 1101 CMP2_OUT [4] 0000 0100 FOSC [30] 0001 1110 ZCD [5] 0000 0101 HFINTOSC(1) [31] 0001 1111 IOC [6] 0000 0110 LFINTOSC(1) [32] 0010 0000 DSM1 [7] 0000 0111 MFINTOSC(1) [33] 0010 0001 HLVD_OUT [8] 0000 1000 MFINTOSC (32 kHz)(1) [34] 0010 0010 CLC1 [9] 0000 1001 SFINTOSC (1 MHz)(1) [35] 0010 0011 CLC2 [10] 0000 1010 SOSC(1) [36] 0010 0100 CLC3 [11] 0000 1011 EXTOSC(1) [37] 0010 0101 CLC4 [12] 0000 1100 ADCRC(1) [38] 0010 0110 U1TX [13] 0000 1101 CLKR [39] 0010 0111 U2TX [14] 0000 1110 TMR0 [40] 0010 1000 U3TX [15] 0000 1111 TMR1 [41] 0010 1001 SPI1_SDO SPI1_SCK [16] 0001 0000 TMR2 [42] 0010 1010 [17] 0001 0001 TMR3 [43] 0010 1011 SPI1_SS [18] 0001 0010 TMR4 [44] 0010 1100 SPI2_SDO SPI2_SCK [19] 0001 0011 SMT1 [45] 0010 1101 [20] 0001 0100 CCP1 [46] 0010 1110 SPI2_SS [21] 0001 0101 PWM1S1P1_OUT [47] 0010 1111 I2C_SCL [22] 0001 0110 PWM1S1P2_OUT [48] 0011 0000 I2C_SDA [23] 0001 0111 PWM2S1P1_OUT [49] 0011 0001 CWG1A [24] 0001 1000 PWM2S1P2_OUT [50] 0011 0010 CWG1B [25] 0001 1001 PWM3S1P1_OUT [51] 0011 0011 - Note:  1. Requests clock. Reset States: POR/BOR = xxxxxxx All Other Resets = uuuuuuu © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 337 PIC18F06/16Q41 CLC - Configurable Logic Cell 22.8.5 CLCnSEL1 Name:  Address:  CLCnSEL1 0x0D9 Generic CLCn Data 1 Select Register Bit 7 Access Reset 6 5 4 R/W x R/W x R/W x 3 D2S[6:0] R/W x 2 1 0 R/W x R/W x R/W x Bits 6:0 – D2S[6:0] CLCn Data2 Input Selection Reset States: POR/BOR = xxxxxxx All Other Resets = uuuuuuu Value Description n Refer to the CLC Input Selection table for input selections © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 338 PIC18F06/16Q41 CLC - Configurable Logic Cell 22.8.6 CLCnSEL2 Name:  Address:  CLCnSEL2 0x0DA Generic CLCn Data 1 Select Register Bit 7 Access Reset 6 5 4 R/W x R/W x R/W x 3 D3S[6:0] R/W x 2 1 0 R/W x R/W x R/W x Bits 6:0 – D3S[6:0] CLCn Data3 Input Selection Reset States: POR/BOR = xxxxxxx All Other Resets = uuuuuuu Value Description n Refer to the CLC Input Selection table for input selections © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 339 PIC18F06/16Q41 CLC - Configurable Logic Cell 22.8.7 CLCnSEL3 Name:  Address:  CLCnSEL3 0x0DB Generic CLCn Data 4 Select Register Bit 7 Access Reset 6 5 4 R/W x R/W x R/W x 3 D4S[6:0] R/W x 2 1 0 R/W x R/W x R/W x Bits 6:0 – D4S[6:0] CLCn Data4 Input Selection Reset States: POR/BOR = xxxxxxx All Other Resets = uuuuuuu Value Description n Refer to the CLC Input Selection table for input selections © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 340 PIC18F06/16Q41 CLC - Configurable Logic Cell 22.8.8 CLCnGLS0 Name:  Address:  CLCnGLS0 0x0DC CLCn Gate1 Logic Select Register Bit Access Reset 7 G1D4T R/W x 6 G1D4N R/W x 5 G1D3T R/W x 4 G1D3N R/W x 3 G1D2T R/W x 2 G1D2N R/W x 1 G1D1T R/W x 0 G1D1N R/W x Bits 1, 3, 5, 7 – G1DyT dyT: Gate1 Data ‘y’ True (noninverted) Reset States: POR/BOR = xxxx All Other Resets = uuuu Value Description 1 dyT is gated into g1 0 dyT is not gated into g1 Bits 0, 2, 4, 6 – G1DyN dyN: Gate1 Data ‘y’ Negated (inverted) Reset States: POR/BOR = xxxx All Other Resets = uuuu Value Description 1 dyN is gated into g1 0 dyN is not gated into g1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 341 PIC18F06/16Q41 CLC - Configurable Logic Cell 22.8.9 CLCnGLS1 Name:  Address:  CLCnGLS1 0x0DD CLCn Gate2 Logic Select Register Bit Access Reset 7 G2D4T R/W x 6 G2D4N R/W x 5 G2D3T R/W x 4 G2D3N R/W x 3 G2D2T R/W x 2 G2D2N R/W x 1 G2D1T R/W x 0 G2D1N R/W x Bits 1, 3, 5, 7 – G2DyT dyT: Gate2 Data ‘y’ True (noninverted) Reset States: POR/BOR = xxxx All Other Resets = uuuu Value Description 1 dyT is gated into g2 0 dyT is not gated into g2 Bits 0, 2, 4, 6 – G2DyN dyN: Gate2 Data ‘y’ Negated (inverted) Reset States: POR/BOR = xxxx All Other Resets = uuuu Value Description 1 dyN is gated into g2 0 dyN is not gated into g2 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 342 PIC18F06/16Q41 CLC - Configurable Logic Cell 22.8.10 CLCnGLS2 Name:  Address:  CLCnGLS2 0x0DE CLCn Gate3 Logic Select Register Bit Access Reset 7 G3D4T R/W x 6 G3D4N R/W x 5 G3D3T R/W x 4 G3D3N R/W x 3 G3D2T R/W x 2 G3D2N R/W x 1 G3D1T R/W x 0 G3D1N R/W x Bits 1, 3, 5, 7 – G3DyT dyT: Gate3 Data ‘y’ True (noninverted) Reset States: POR/BOR = xxxx All Other Resets = uuuu Value Description 1 dyT is gated into g3 0 dyT is not gated into g3 Bits 0, 2, 4, 6 – G3DyN dyN: Gate3 Data ‘y’ Negated (inverted) Reset States: POR/BOR = xxxx All Other Resets = uuuu Value Description 1 dyN is gated into g3 0 dyN is not gated into g3 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 343 PIC18F06/16Q41 CLC - Configurable Logic Cell 22.8.11 CLCnGLS3 Name:  Address:  CLCnGLS3 0x0DF CLCn Gate4 Logic Select Register Bit Access Reset 7 G4D4T R/W x 6 G4D4N R/W x 5 G4D3T R/W x 4 G4D3N R/W x 3 G4D2T R/W x 2 G4D2N R/W x 1 G4D1T R/W x 0 G4D1N R/W x Bits 1, 3, 5, 7 – G4DyT dyT: Gate4 Data ‘y’ True (noninverted) Reset States: POR/BOR = xxxx All Other Resets = uuuu Value Description 1 dyT is gated into g4 0 dyT is not gated into g4 Bits 0, 2, 4, 6 – G4DyN dyN: Gate4 Data ‘y’ Negated (inverted) Reset States: POR/BOR = xxxx All Other Resets = uuuu Value Description 1 dyN is gated into g4 0 dyN is not gated into g4 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 344 PIC18F06/16Q41 CLC - Configurable Logic Cell 22.8.12 CLCDATA Name:  Address:  CLCDATA 0x0D4 CLC Data Output Register Mirror copy of CLC outputs Bit 7 6 5 4 Access Reset 3 CLC4OUT R/W 0 2 CLC3OUT R/W 0 1 CLC2OUT R/W 0 0 CLC1OUT R/W 0 Bits 0, 1, 2, 3 – CLCxOUT Mirror copy of CLCx_out Value Description 1 CLCx_out is 1 0 CLCx_out is 0 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 345 PIC18F06/16Q41 CLC - Configurable Logic Cell 22.9 Address 0x00 ... 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF Register Summary - CLC Control Name Bit Pos. 7 6 5 4 3 2 CLC4OUT CLC3OUT 1 0 Reserved CLCDATA CLCSELECT CLCnCON CLCnPOL CLCnSEL0 CLCnSEL1 CLCnSEL2 CLCnSEL3 CLCnGLS0 CLCnGLS1 CLCnGLS2 CLCnGLS3 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 EN POL G1D4T G2D4T G3D4T G4D4T © 2020-2021 Microchip Technology Inc. and its subsidiaries OUT G1D4N G2D4N G3D4N G4D4N G1D3T G2D3T G3D3T G4D3T INTP G1D3N G2D3N G3D3N G4D3N INTN G4POL D1S[6:0] D2S[6:0] D3S[6:0] D4S[6:0] G1D2T G2D2T G3D2T G4D2T Preliminary Datasheet G3POL G1D2N G2D2N G3D2N G4D2N CLC2OUT CLC1OUT SLCT[1:0] MODE[2:0] G2POL G1POL G1D1T G2D1T G3D1T G4D1T G1D1N G2D1N G3D1N G4D1N DS40002214E-page 346 PIC18F06/16Q41 CLKREF - Reference Clock Output Module 23. CLKREF - Reference Clock Output Module The reference clock output module provides the ability to send a clock signal to the clock reference output pin (CLKR). The reference clock output can be routed internally as an input signal for other peripherals, such as the timers and CLCs. The reference clock output module has the following features: • • • Selectable clock source using the CLKRCLK register Programmable clock divider Selectable duty cycle The figure below shows the simplified block diagram of the clock reference module. Figure 23-1. Clock Reference Block Diagram Rev. 10-000261B 1/23/2019 DIV EN Counter Reset Reference Clock Divider 128 See CLKRCLK Register 64 32 16 8 4 2 110 DC RxyPPS 101 100 011 CLKR Duty Cycle PPS 010 001 To Peripherals 000 EN CLK 111 Figure 23-2. Clock Reference Timing Rev. 10-000264B 1/23/2019 P1 P2 CLKRCLK EN CLKR Output DIV = 001 DC = 10 Duty Cycle (50%) CLKR Output CLKRCLK/2 DIV = 001 DC = 01 Duty Cycle (25%) 23.1 Clock Source The clock source of the reference clock peripheral is selected with the CLK bits. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 347 PIC18F06/16Q41 CLKREF - Reference Clock Output Module 23.1.1 Clock Synchronization The CLKR output signal is ensured to be glitch-free when the EN bit is set to start the module and enable the CLKR output. When the reference clock output is disabled, the output signal will be disabled immediately. 23.2 Programmable Clock Divider The module takes the clock input and divides it based on the value of the DIV bits. The following configurations are available: • • • • • • • • 23.3 Base clock frequency value Base clock frequency divided by 2 Base clock frequency divided by 4 Base clock frequency divided by 8 Base clock frequency divided by 16 Base clock frequency divided by 32 Base clock frequency divided by 64 Base clock frequency divided by 128 Selectable Duty Cycle The DC bits are used to modify the duty cycle of the output clock. A duty cycle of 0%, 25%, 50%, or 75% can be selected for all clock rates when the DIV value is not 0b000. When DIV = 0b000, the duty cycle defaults to 50% for all values of DC except 0b00, in which case the duty cycle is 0% (constant low output). Important:  The DC value at Reset is 10. This makes the default duty cycle 50% and not 0%. Important:  Clock dividers and clock duty cycles can be changed while the module is enabled but doing so may cause glitches to occur on the output. To avoid possible glitches, clock dividers and clock duty cycles will be changed only when the EN bit is clear. 23.4 Operation in Sleep Mode The reference clock module continues to operate and provide a signal output in Sleep for all clock source selections except FOSC (CLK = 0). 23.5 Register Definitions: Reference Clock Long bit name prefixes for the Reference Clock peripherals are shown in the following table. Refer to the “Long Bit Names” section in the “Register and Bit Naming Conventions” chapter for more information. Table 23-1. CLKREF Long Bit Name Prefixes Peripheral Bit Name Prefix CLKR CLKR © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 348 PIC18F06/16Q41 CLKREF - Reference Clock Output Module 23.5.1 CLKRCON Name:  Address:  CLKRCON 0x039 Reference Clock Control Register Bit Access Reset 7 EN R/W 0 6 5 4 3 2 R/W 0 R/W 0 DC[1:0] R/W 1 1 DIV[2:0] R/W 0 0 R/W 0 Bit 7 – EN Reference Clock Module Enable Value Description 1 Reference clock module enabled 0 Reference clock module is disabled Bits 4:3 – DC[1:0]  Reference Clock Duty Cycle(1) Value Description 11 Clock outputs duty cycle of 75% 10 Clock outputs duty cycle of 50% 01 Clock outputs duty cycle of 25% 00 Clock outputs duty cycle of 0% Bits 2:0 – DIV[2:0] Reference Clock Divider Value Description 111 Base clock value divided by 128 110 Base clock value divided by 64 101 Base clock value divided by 32 100 Base clock value divided by 16 011 Base clock value divided by 8 010 Base clock value divided by 4 001 Base clock value divided by 2 000 Base clock value Note:  1. Bits are valid for DIV ≥ 001. For DIV = 000, duty cycle is fixed at 50%. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 349 PIC18F06/16Q41 CLKREF - Reference Clock Output Module 23.5.2 CLKRCLK Name:  Address:  CLKRCLK 0x03A Clock Reference Clock Selection Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 CLK[3:0] Access Reset R/W 0 R/W 0 Bits 3:0 – CLK[3:0] CLKR Clock Selection Table 23-2. Clock Reference Module Clock Sources CLK Clock Source 1111 - 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Reserved CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT NCO1_OUT EXTOSC SOSC MFINTOSC (32 kHz) MFINTOSC (500 kHz) LFINTOSC HFINTOSC FOSC © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 350 PIC18F06/16Q41 CLKREF - Reference Clock Output Module 23.6 Address 0x00 ... 0x38 0x39 0x3A Register Summary - Reference CLK Name Bit Pos. 7 7:0 7:0 EN 6 5 4 3 2 1 0 Reserved CLKRCON CLKRCLK © 2020-2021 Microchip Technology Inc. and its subsidiaries DC[1:0] Preliminary Datasheet DIV[2:0] CLK[3:0] DS40002214E-page 351 PIC18F06/16Q41 TMR0 - Timer0 Module 24. TMR0 - Timer0 Module The Timer0 module has the following features: • • • • • • • • • 8-bit timer with programmable period 16-bit timer Selectable clock sources Synchronous and asynchronous operation Programmable prescaler (Independent of Watchdog Timer) Programmable postscaler Interrupt on match or overflow Output on I/O pin (via PPS) or to other peripherals Operation during Sleep Figure 24-1. Timer0 Block Diagram Rev. Tim er0 Blo 2/12/201 9 See T0CON1 Register T0CKPS Peripherals TMR0 bod y T0OUTPS T0IF 1 Prescaler SYNC 0 IN OUT TMR0 FOSC/4 T016BIT T0ASYNC PPS T0_out Postscaler Q D T0CKIPPS PPS RxyPPS CK Q T0CS 16-bit TMR0 Body Diagram (T016BIT = 1) 8-bit TMR0 Body Diagram (T016BIT = 0) IN TMR0L R Clear IN TMR0L Timer 0 High Byte OUT 8 Read TMR0L COMPARATOR OUT Write TMR0L T0_match 8 8 TMR0H Timer 0 High Byte Latch Enable 8 TMR0H 8 Internal Data Bus 24.1 Timer0 Operation Timer0 can operate as either an 8-bit or 16-bit timer. The mode is selected with the MD16 bit. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 352 PIC18F06/16Q41 TMR0 - Timer0 Module 24.1.1 8-Bit Mode In this mode, Timer0 increments on the rising edge of the selected clock source. A prescaler on the clock input gives several prescale options (see the prescaler control bits, CKPS). In this mode, as shown in Figure 24-1, a buffered version of TMR0H is maintained. This is compared with the value of TMR0L on each cycle of the selected clock source. When the two values match, the following events occur: • TMR0L is reset • The contents of TMR0H are copied to the TMR0H buffer for next comparison 24.1.2 16-Bit Mode In this mode, Timer0 increments on the rising edge of the selected clock source. A prescaler on the clock input gives several prescale options (see the prescaler control bits, CKPS). In this mode, TMR0H:TMR0L form the 16-bit timer value. As shown in Figure 24-1, reads and writes of the TMR0H register are buffered. The TMR0H register is updated with the contents of the high byte of Timer0 when the TMR0L register is read. Similarly, writing the TMR0L register causes a transfer of the TMR0H register value to the Timer0 high byte. This buffering allows all 16 bits of Timer0 to be read and written at the same time. Timer0 rolls over to 0x0000 on incrementing past 0xFFFF. This makes the timer free-running. While actively operating in 16-bit mode, the Timer0 value can be read but not written. 24.2 Clock Selection Timer0 has several options for clock source selections, the option to operate synchronously/asynchronously and an available programmable prescaler. The CS bits are used to select the clock source for Timer0. 24.2.1 Synchronous Mode When the ASYNC bit is clear, Timer0 clock is synchronized to the system clock (FOSC/4). When operating in Synchronous mode, Timer0 clock frequency cannot exceed FOSC/4. During Sleep mode the system clock is not available and Timer0 cannot operate. 24.2.2 Asynchronous Mode When the ASYNC bit is set, Timer0 increments with each rising edge of the input source (or output of the prescaler, if used). Asynchronous mode allows Timer0 to continue operation during Sleep mode provided the selected clock source operates during Sleep. 24.2.3 Programmable Prescaler Timer0 has 16 programmable input prescaler options ranging from 1:1 to 1:32768. The prescaler values are selected using the CKPS bits. The prescaler counter is not directly readable or writable. The prescaler counter is cleared on the following events: • • • 24.2.4 A write to the TMR0L register A write to either the T0CON0 or T0CON1 registers Any device Reset Programmable Postscaler Timer0 has 16 programmable output postscaler options ranging from 1:1 to 1:16. The postscaler values are selected using the OUTPS bits. The postscaler divides the output of Timer0 by the selected ratio. The postscaler counter is not directly readable or writable. The postscaler counter is cleared on the following events: • • • A write to the TMR0L register A write to either the T0CON0 or T0CON1 registers Any device Reset © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 353 PIC18F06/16Q41 TMR0 - Timer0 Module 24.3 24.3.1 Timer0 Output and Interrupt Timer0 Output TMR0_out toggles on every match between TMR0L and TMR0H in 8-bit mode, or when TMR0H:TMR0L rolls over in 16-bit mode. If the output postscaler is used, the output is scaled by the ratio selected. The Timer0 output can be routed to an I/O pin via the RxyPPS output selection register, or internally to a number of Core Independent Peripherals. The Timer0 output can be monitored through software via the OUT output bit. 24.3.2 Timer0 Interrupt The Timer0 Interrupt Flag (TMR0IF) bit is set when the TMR0_out toggles. If the Timer0 interrupt is enabled (TMR0IE), the CPU will be interrupted when the TMR0IF bit is set. When the postscaler bits (T0OUTPS) are set to 1:1 operation (no division), the T0IF flag bit will be set with every TMR0 match or rollover. In general, the TMR0IF flag bit will be set every T0OUTPS +1 matches or rollovers. 24.3.3 Timer0 Example Timer0 Configuration: • Timer0 mode = 16-bit • Clock Source = FOSC/4 (250 kHz) • Synchronous operation • Prescaler = 1:1 • Postscaler = 1:2 (T0OUTPS = 1) In this case, the TMR0_out toggles every two rollovers of TMR0H:TMR0L. i.e., (0xFFFF)*2*(1/250 kHz) = 524.28 ms 24.4 Operation During Sleep When operating synchronously, Timer0 will halt when the device enters Sleep mode. When operating asynchronously and the selected clock source is active, Timer0 will continue to increment and wake the device from Sleep mode if the Timer0 interrupt is enabled. 24.5 Register Definitions: Timer0 Control © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 354 PIC18F06/16Q41 TMR0 - Timer0 Module 24.5.1 T0CON0 Name:  Address:  T0CON0 0x31A Timer0 Control Register 0 Bit Access Reset 7 EN R/W 0 6 5 OUT R 0 4 MD16 R/W 0 3 R/W 0 2 1 OUTPS[3:0] R/W R/W 0 0 0 R/W 0 Bit 7 – EN TMR0 Enable Value Description 1 The module is enabled and operating 0 The module is disabled Bit 5 – OUT TMR0 Output Bit 4 – MD16 16-Bit Timer Operation Select Value Description 1 TMR0 is a 16-bit timer 0 TMR0 is an 8-bit timer Bits 3:0 – OUTPS[3:0] TMR0 Output Postscaler (Divider) Select Value Description 1111 1:16 Postscaler 1110 1:15 Postscaler 1101 1:14 Postscaler 1100 1:13 Postscaler 1011 1:12 Postscaler 1010 1:11 Postscaler 1001 1:10 Postscaler 1000 1:9 Postscaler 0111 1:8 Postscaler 0110 1:7 Postscaler 0101 1:6 Postscaler 0100 1:5 Postscaler 0011 1:4 Postscaler 0010 1:3 Postscaler 0001 1:2 Postscaler 0000 1:1 Postscaler © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 355 PIC18F06/16Q41 TMR0 - Timer0 Module 24.5.2 T0CON1 Name:  Address:  T0CON1 0x31B Timer0 Control Register 1 Bit Access Reset 7 R/W 0 6 CS[2:0] R/W 0 5 R/W 0 4 ASYNC R/W 0 3 2 1 0 R/W 0 R/W 0 CKPS[3:0] R/W 0 R/W 0 Bits 7:5 – CS[2:0] Timer0 Clock Source Select Value Description 111 110 101 100 011 010 001 000 CLC1_OUT SOSC MFINTOSC (500 kHz) LFINTOSC HFINTOSC FOSC/4 Pin selected by T0CKIPPS (Inverted) Pin selected by T0CKIPPS (Noninverted) Bit 4 – ASYNC TMR0 Input Asynchronization Enable Value Description 1 The input to the TMR0 counter is not synchronized to system clocks 0 The input to the TMR0 counter is synchronized to Fosc/4 Bits 3:0 – CKPS[3:0] Prescaler Rate Select Value Description 1111 1:32768 1110 1:16384 1101 1:8192 1100 1:4096 1011 1:2048 1010 1:1024 1001 1:512 1000 1:256 0111 1:128 0110 1:64 0101 1:32 0100 1:16 0011 1:8 0010 1:4 0001 1:2 0000 1:1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 356 PIC18F06/16Q41 TMR0 - Timer0 Module 24.5.3 TMR0H Name:  Address:  TMR0H 0x319 Timer0 Period/Count High Register Bit Access Reset 7 6 5 R/W 1 R/W 1 R/W 1 4 3 TMR0H[7:0] R/W R/W 1 1 2 1 0 R/W 1 R/W 1 R/W 1 Bits 7:0 – TMR0H[7:0] TMR0 Most Significant Counter Value Condition Description 0 to 255 MD16 = 0 8-bit Timer0 Period Value. TMR0L continues counting from 0 when this value is reached. 0 to 255 MD16 = 1 16-bit Timer0 Most Significant Byte © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 357 PIC18F06/16Q41 TMR0 - Timer0 Module 24.5.4 TMR0L Name:  Address:  TMR0L 0x318 Timer0 Period/Count Low Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 TMR0L[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – TMR0L[7:0] TMR0 Least Significant Counter Value Condition Description 0 to 255 MD16 = 0 8-bit Timer0 Counter bits 0 to 255 MD16 = 1 16-bit Timer0 Least Significant Byte © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 358 PIC18F06/16Q41 TMR0 - Timer0 Module 24.6 Address 0x00 ... 0x0317 0x0318 0x0319 0x031A 0x031B Register Summary - Timer0 Name Bit Pos. 7 6 5 4 3 2 1 0 Reserved TMR0L TMR0H T0CON0 T0CON1 7:0 7:0 7:0 7:0 EN © 2020-2021 Microchip Technology Inc. and its subsidiaries OUT CS[2:0] TMR0L[7:0] TMR0H[7:0] MD16 ASYNC Preliminary Datasheet OUTPS[3:0] CKPS[3:0] DS40002214E-page 359 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control 25. TMR1 - Timer1 Module with Gate Control The Timer1 module is a 16-bit timer/counter with the following features: • • • • • • • • • • • • • • • 16-bit timer/counter register pair (TMRxH:TMRxL) Programmable internal or external clock source 2-bit prescaler Clock source for optional comparator synchronization Multiple Timer1 gate (count enable) sources Interrupt-on-overflow Wake-up on overflow (external clock, Asynchronous mode only) 16-bit read/write operation Time base for the capture/compare function with the CCP modules Special event trigger (with CCP) Selectable gate source polarity Gate Toggle mode Gate Single Pulse mode Gate value status Gate event interrupt Important:  References to the module Timer1 apply to all the odd numbered timers on this device. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 360 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control Figure 25-1. Timer1 Block Diagram TxGATE 4 TxGPPS GSPM PPS 00 00 1 0 NOTE (5) 1 11 11 D D Single Pulse Acq. Control Q1 Q GPOL GGO/DONE CK Q Interrupt ON R set bit TMRxGIF det GTM GE set flag bit TMRxIF ON EN (2) Tx_overflow GVAL Q 0 To Comparators (6) TMRx TMRxH TMRxL Q Synchronized Clock Input 0 D 1 TxCLK SYNC TxCLK 4 TxCKIPPS (1) PPS 0000 Note Prescaler 1,2,4,8 (4) Synchronize(3) det 111 1 2 CKPS Fosc/2 Internal Clock Sleep Input Notes:  1. This signal comes from the pin selected by Timer1 PPS register. 2. TMRx register increments on rising edge. 3. Synchronize does not operate while in Sleep. 4. See TxCLK for clock source selections. 5. See TxGATE for gate source selections. 6. Synchronized comparator output must not be used in conjunction with synchronized input clock. 25.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter accessed through the TMRx register. Writes to TMRx directly update the counter. When used with an internal clock source, the module is a timer that increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the ON and GE bits. Table 25-1 shows the possible Timer1 enable selections. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 361 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control Table 25-1. Timer1 Enable Selections 25.2 ON GE Timer1 Operation 1 1 Count enabled 1 0 Always on 0 1 Off 0 0 Off Clock Source Selection The CS bits select the clock source for Timer1. These bits allow the selection of several possible synchronous and asynchronous clock sources. 25.2.1 Internal Clock Source When the internal clock source is selected, the TMRx register will increment on multiples of FOSC as determined by the Timer1 prescaler. When the FOSC internal clock source is selected, the TMRx register value will increment by four counts every instruction clock cycle. Due to this condition, a two LSB error in resolution will occur when reading the TMRx value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. Important:  In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • Timer1 enabled after POR • Write to TMRxH or TMRxL • Timer1 is disabled • Timer1 is disabled (ON = 0) when TxCKI is high, then Timer1 is enabled (ON = 1) when TxCKI is low. Refer to the figure below. Figure 25-2. Timer1 Incrementing Edge TxCKI = 1 When TMRx Enabled TxCKI = 0 When TMRx Enabled Notes:  1. Arrows indicate counter increments. 2. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 25.2.2 External Clock Source When the external clock source is selected, the TMRx module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input of the TxCKIPPS pin. This external clock source can be synchronized to the system clock or it can run asynchronously. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 362 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control 25.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The CKPS bits control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMRx. 25.4 Secondary Oscillator A secondary low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. The secondary oscillator is not dedicated only to Timer1; it can also be used by other modules. The oscillator circuit is enabled by setting the SOSCEN bit of the OSCEN register. This can be used as one of the Timer1 clock sources selected with the CS bits. The oscillator will continue to run during Sleep. Important:  The oscillator requires a start-up and stabilization time before use. Thus, the SOSCEN bit of the OSCEN register must be set and a suitable delay observed prior to enabling Timer1. A software check can be performed to confirm if the secondary oscillator is enabled and ready to use. This is done by polling the secondary oscillator ready Status bit. Refer to the “OSC - Oscillator Module (with Fail-Safe Clock Monitor)” chapter for more details. 25.5 Timer1 Operation in Asynchronous Counter Mode When the SYNC control bit is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If the external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake up the processor. However, special precautions in software are needed to read/write the timer. Important:  When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. 25.5.1 Reading and Writing TMRx in Asynchronous Counter Mode Reading TMRxH or TMRxL while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user must keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems, since there may be a carry-out of TMRxL to TMRxH between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMRxH:TMRxL register pair. 25.6 Timer1 16-Bit Read/Write Mode Timer1 can be configured to read and write all 16 bits of data to and from the 8-bit TMRxL and TMRxH registers, simultaneously. The 16-bit read and write operations are enabled by setting the RD16 bit. To accomplish this function, the TMRxH register value is mapped to a buffer register called the TMRxH buffer register. While in 16-bit mode, the TMRxH register is not directly readable or writable and all read and write operations take place through the use of this TMRxH buffer register. When a read from the TMRxL register is requested, the value of the TMRxH register is simultaneously loaded into the TMRxH buffer register. When a read from the TMRxH register is requested, the value is provided from the TMRxH buffer register instead. This provides the user with the ability to accurately read all 16 bits of the Timer1 value from a © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 363 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control single instance in time (refer to Figure 25-3 for more details). In contrast, when not in 16-bit mode, the user must read each register separately and determine if the values have become invalid due to a rollover that may have occurred between the read operations. When a write request of the TMRxL register is requested, the TMRxH buffer register is simultaneously updated with the contents of the TMRxH register. The value of TMRxH must be preloaded into the TMRxH buffer register prior to the write request for the TMRxL register. This provides the user with the ability to write all 16 bits to the TMRx register at the same time. Any requests to write to TMRxH directly does not clear the Timer1 prescaler value. The prescaler value is only cleared through write requests to the TMRxL register. Figure 25-3. Timer1 16-Bit Read/Write Mode Block Diagram From TMRx Circuitr y TMRx High Byte TMRxL Set TMRxIF on Overflow 8 Read TMRxL Write TMRxL 8 8 TMRxH 8 8 25.7 Inte rnal Da ta Bus Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 gate enable. Timer1 gate can also be driven by multiple selectable sources. 25.7.1 Timer1 Gate Enable The Timer1 Gate Enable mode is enabled by setting the GE bit. The polarity of the Timer1 Gate Enable mode is configured using the GPOL bit. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate signal is inactive, the timer will not increment and hold the current count. Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 25-4 for timing details. Table 25-2. Timer1 Gate Enable Selections TMRxCLK GPOL TxG Timer1 Operation ↑ 1 1 Counts ↑ 1 0 Holds Count ↑ 0 1 Holds Count ↑ 0 0 Counts © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 364 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control Figure 25-4. Timer1 Gate Enable Mode TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1 25.7.2 Timer1 Gate Source Selection The gate source for Timer1 is selected using the GSS bits. The polarity selection for the gate source is controlled by the GPOL bit. Any of the above mentioned signals can be used to trigger the gate. The output of the CMPx can be synchronized to the Timer1 clock or left asynchronous. For more information refer to the “Comparator Output Synchronization” section. 25.7.3 Timer1 Gate Toggle Mode When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 Gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See the figure below for timing details. Timer1 Gate Toggle mode is enabled by setting the GTM bit. When the GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary to control which edge is measured. Important:  Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 365 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control Figure 25-5. Timer1 Gate Toggle Mode TMRxGE TxGPOL TxGTM TxTxG_IN TxCKI TxGVAL Timer1 25.7.4 Timer1 Gate Single Pulse Mode When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single Pulse mode is first enabled by setting the GSPM bit. Next, the GGO/DONE must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the GGO/DONE bit is once again set in software. Figure 25-6. Timer1 Gate Single Pulse Mode TMRxGE TxGPOL TxGSPM TxGGO/ DONE Cleared by hardware on falling edge of TxGVAL Set by software Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1 TMRxGIF Cleared by software © 2020-2021 Microchip Technology Inc. and its subsidiaries Set by hardware on falling edge of TxGVAL Preliminary Datasheet Cleared by software DS40002214E-page 366 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control Clearing the GSPM bit will also clear the GGO/DONE bit. See the figure below for timing details. Enabling the Toggle mode and the Single Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See the figure below for timing details. Figure 25-7. Timer1 Gate Single Pulse and Toggle Combined Mode TMRxGE TxGPOL TxGSPM TxGTM Cleared by hardware on falling edge of TxGVAL Set by software TxGGO/ DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1 TMRxGIF 25.7.5 Cleared by software Set by hardware on falling edge of TxGVAL Cleared by software Timer1 Gate Value Status When Timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the GVAL bit in the TxGCON register. The GVAL bit is valid even when the Timer1 gate is not enabled (GE bit is cleared). 25.7.6 Timer1 Gate Event Interrupt When Timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of GVAL occurs, the TMRxGIF flag bit in one of the PIR registers will be set. If the TMRxGIE bit in the corresponding PIE register is set, then an interrupt will be recognized. The TMRxGIF flag bit operates even when the Timer1 gate is not enabled (GE bit is cleared). 25.8 Timer1 Interrupt The TMRx register increments to FFFFh and rolls over to 0000h. When TMRx rolls over, the Timer1 interrupt flag bit of the PIRx register is set. To enable the interrupt-on-rollover, the following bits must be set: • • • ON bit of the TxCON register TMRxIE bits of the PIEx register Global interrupts must be enabled The interrupt is cleared by clearing the TMRxIF bit as a task in the Interrupt Service Routine. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 367 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control Important:  The TMRx register and the TMRxIF bit must be cleared before enabling interrupts. 25.9 Timer1 Operation During Sleep Timer1 can only operate during Sleep when configured as an asynchronous counter. In this mode, many clock sources can be used to increment the counter. To set up the timer to wake the device: • • • • • The ON bit must be set The TMRxIE bit of the PIEx register must be set Global interrupts must be enabled The SYNC bit must be set Configure the TxCLK register for using any clock source other than FOSC and FOSC/4 The device will wake up on an overflow and execute the next instruction. If global interrupts are enabled, the device will call the IRS. The secondary oscillator will continue to operate in Sleep regardless of the SYNC bit setting. 25.10 CCP Capture/Compare Time Base The CCP modules use TMRx as the time base when operating in Capture or Compare mode. In Capture mode, the value in TMRx is copied into the CCPRx register on a capture event. In Compare mode, an event is triggered when the value in the CCPRx register matches the value in TMRx. This event can be a Special Event Trigger. 25.11 CCP Special Event Trigger When any of the CCPs are configured to trigger a special event, the trigger will clear the TMRx register. This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPRx register becomes the period register for Timer1. Timer1 must be synchronized and FOSC/4 must be selected as the clock source to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMRxH or TMRxL coincides with a Special Event Trigger from the CCP, the write will take precedence. 25.12 Peripheral Module Disable When a peripheral is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power consumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module’s clock source. The Module Disable bits for Timer1 (TMR1MD) are in the PMDx register. See the “PMD - Peripheral Module Disable” chapter for more information. 25.13 Register Definitions: Timer1 Control Long bit name prefixes for the Timer registers are shown in the table below, where ‘x’ refers to the Timer instance number. Refer to the “Long Bit Names” section in the “Register and Bit Naming Conventions” chapter for more information. Table 25-3. Timer1 Register Long Bit Name Prefixes Peripheral Bit Name Prefix Timer1 T1 Timer3 T3 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 368 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control 25.13.1 TxCON Name:  Address:  TxCON 0x314,0x325 Timer Control Register Bit 7 6 5 4 3 CKPS[1:0] Access Reset R/W 0 R/W 0 2 SYNC R/W 0 1 RD16 R/W 0 0 ON R/W 0 Bits 5:4 – CKPS[1:0] Timer Input Clock Prescaler Select Reset States: POR/BOR = 00 All Other Resets = uu Value Description 11 1:8 Prescaler value 10 1:4 Prescaler value 01 1:2 Prescaler value 00 1:1 Prescaler value Bit 2 – SYNC Timer External Clock Input Synchronization Control Reset States: POR/BOR = 0 All Other Resets = u Value Condition Description x CS = FOSC/4 or FOSC This bit is ignored. Timer uses the incoming clock as is. 1 All other clock sources Do not synchronize external clock input 0 All other clock sources Synchronize external clock input with system clock Bit 1 – RD16 16-Bit Read/Write Mode Enable Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 Enables register read/write of Timer in one 16-bit operation 0 Enables register read/write of Timer in two 8-bit operations Bit 0 – ON Timer On Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 Enables Timer 0 Disables Timer © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 369 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control 25.13.2 TxGCON Name:  Address:  TxGCON 0x315,0x326 Timer Gate Control Register Bit Access Reset 7 GE R/W 0 6 GPOL R/W 0 5 GTM R/W 0 4 GSPM R/W 0 3 GGO/DONE R/W 0 2 GVAL R x 1 0 Bit 7 – GE Timer Gate Enable Reset States: POR/BOR = 0 All Other Resets = u Value Condition Description 1 ON = 1 Timer counting is controlled by the Timer gate function 0 ON = 1 Timer is always counting X ON = 0 This bit is ignored Bit 6 – GPOL Timer Gate Polarity Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 Timer gate is active-high (Timer counts when gate is high) 0 Timer gate is active-low (Timer counts when gate is low) Bit 5 – GTM Timer Gate Toggle Mode Timer Gate flip-flop toggles on every rising edge when Toggle mode is enabled. Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 Timer Gate Toggle mode is enabled 0 Timer Gate Toggle mode is disabled and Toggle flip-flop is cleared Bit 4 – GSPM Timer Gate Single Pulse Mode Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 Timer Gate Single Pulse mode is enabled and is controlling Timer gate 0 Timer Gate Single Pulse mode is disabled Bit 3 – GGO/DONE Timer Gate Single Pulse Acquisition Status This bit is automatically cleared when TxGSPM is cleared. Reset States: POR/BOR = 0 All Other Resets = u Value Description 1 Timer Gate Single Pulse Acquisition is ready, waiting for an edge 0 Timer Gate Single Pulse Acquisition has completed or has not been started Bit 2 – GVAL Timer Gate Current State Indicates the current state of the timer gate that can be provided to TMRxH:TMRxL Unaffected by the Timer Gate Enable (GE) bit © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 370 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control 25.13.3 TxCLK Name:  Address:  TxCLK 0x317,0x328 Timer Clock Source Selection Register Bit 7 6 5 Access Reset 4 3 R/W 0 R/W 0 2 CS[4:0] R/W 0 1 0 R/W 0 R/W 0 Bits 4:0 – CS[4:0] Timer Clock Source Selection Table 25-4. Timer Clock Sources CS Clock Source Timer1 11111 - 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 Timer3 Reserved CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT TMR3_OUT Reserved Reserved TMR1_OUT TMR0_OUT CLKREF_OUT EXTOSC SOSC MFINTOSC (32 kHz) MFINTOSC (500 kHz) LFINTOSC HFINTOSC FOSC FOSC/4 Pin selected by T1CKIPPS Pin selected by T3CKIPPS Reset States: POR/BOR = 00000 All Other Resets = uuuuu © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 371 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control 25.13.4 TxGATE Name:  Address:  TxGATE 0x316,0x327 Timer Gate Source Selection Register Bit 7 6 Access Reset 5 4 3 R/W 0 R/W 0 2 GSS[4:0] R/W 0 1 0 R/W 0 R/W 0 Bits 4:0 – GSS[4:0] Timer Gate Source Selection Table 25-5. Timer Gate Sources GSS Gate Source Timer1 11111 - 10110 10101 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 © 2020-2021 Microchip Technology Inc. and its subsidiaries Timer3 Reserved CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT ZCD_OUT CMP2_OUT CMP1_OUT NCO1_OUT PWM3S1P2_OUT PWM3S1P1_OUT PWM2S1P2_OUT PWM2S1P1_OUT PWM1S1P2_OUT PWM1S1P1_OUT CCP1_OUT SMT1_OUT TMR4_Postscaler_OUT TMR3_OUT Reserved TMR2_Postscaler_OUT Reserved TMR1_OUT TMR0_OUT Pin selected by T1GPPS Preliminary Datasheet Pin selected by T3GPPS DS40002214E-page 372 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control 25.13.5 TMRx Name:  Address:  TMRx 0x312,0x323 Timer Register Bit 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 TMRx[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 TMRx[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 15:0 – TMRx[15:0] Timer Register Value Reset States: POR/BOR = 0000000000000000 All Other Resets = uuuuuuuuuuuuuuuu Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • TMRxH: Accesses the high byte TMRx[15:8] • TMRxL: Accesses the low byte TMRx[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 373 PIC18F06/16Q41 TMR1 - Timer1 Module with Gate Control 25.14 Register Summary - Timer1 Address Name 0x00 ... 0x0311 Reserved 0x0312 TMR1 0x0314 0x0315 0x0316 0x0317 0x0318 ... 0x0322 T1CON T1GCON T1GATE T1CLK Bit Pos. 7:0 15:8 7:0 7:0 7:0 7:0 7 6 5 4 3 2 1 0 SYNC GVAL GSS[4:0] CS[4:0] RD16 ON SYNC GVAL GSS[4:0] CS[4:0] RD16 ON TMR1[7:0] TMR1[15:8] GE GPOL CKPS[1:0] GTM GSPM GGO/DONE Reserved 0x0323 TMR3 0x0325 0x0326 0x0327 0x0328 T3CON T3GCON T3GATE T3CLK 7:0 15:8 7:0 7:0 7:0 7:0 TMR3[7:0] TMR3[15:8] GE © 2020-2021 Microchip Technology Inc. and its subsidiaries GPOL CKPS[1:0] GTM GSPM GGO/DONE Preliminary Datasheet DS40002214E-page 374 PIC18F06/16Q41 TMR2 - Timer2 Module 26. TMR2 - Timer2 Module The Timer2 module is an 8-bit timer that incorporates the following features: • • • • • • • • • • • 8-bit timer and period registers Readable and writable Software programmable prescaler (1:1 to 1:128) Software programmable postscaler (1:1 to 1:16) Interrupt on T2TMR match with T2PR One-shot operation Full asynchronous operation Includes Hardware Limit Timer (HLT) Alternate clock sources External timer Reset signal sources Configurable timer Reset operation See figure below for a block diagram of Timer2. Important:  References to module Timer2 apply to all the even numbered timers on this device (Timer2, Timer4, etc.). Figure 26-1. Timer2 with Hardware Limit Timer (HLT) Block Diagram RSEL TxINPPS TxIN PPS Rev. 10-000168D 4/29/2019 MODE External Reset Sources(2) TMRx_ers Edge Detector Level Detector Mode Control (2 clock Sync) reset CCP_pset(1) MODE[4:3] = 'b01 enable CKPOL CS TxINPPS TxIN PPS MODE[3] TMRx_clk Prescaler See TxCLKCON register(3) CKPS Sync (2 Clocks) D MODE[4:1] = 'b1011 0 Sync 1 Fosc/4 PSYNC 1 TxTMR Q Clear ON R Set flag bit TMRxIF Comparator Postscaler TxPR OUTPS TMRx_postscaled 0 ON CSYNC Notes:  1. Signal to the CCP peripheral for PWM pulse trigger in PWM mode. 2. See RSEL for external Reset sources. 3. See CS for clock source selections. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 375 PIC18F06/16Q41 TMR2 - Timer2 Module 26.1 Timer2 Operation Timer2 operates in three major modes: • • • Free-Running Period One Shot Monostable Within each operating mode, there are several options for starting, stopping and Reset. Table 26-1 lists the options. In all modes, the T2TMR count register increments on the rising edge of the clock signal from the programmable prescaler. When T2TMR equals T2PR, a high level output to the postscaler counter is generated. T2TMR is cleared on the next clock input. An external signal from hardware can also be configured to gate the timer operation or force a T2TMR count Reset. In Gate modes, the counter stops when the gate is disabled and resumes when the gate is enabled. In Reset modes, the T2TMR count is reset on either the level or edge from the external source. The T2TMR and T2PR registers are both directly readable and writable. The T2TMR register is cleared and the T2PR register initializes to 0xFF on any device Reset. Both the prescaler and postscaler counters are cleared on the following events: • • • • A write to the T2TMR register A write to the T2CON register Any device Reset External Reset source event that resets the timer Important:  T2TMR is not cleared when T2CON is written. 26.1.1 Free-Running Period Mode The value of T2TMR is compared to that of the period register, T2PR, on each clock cycle. When the two values match, the comparator resets the value of T2TMR to 0x00 on the next cycle and increments the output postscaler counter. When the postscaler count equals the value in the OUTPS bits of the T2CON register then a one clock period wide pulse occurs on the TMR2_postscaled output, and the postscaler count is cleared. 26.1.2 One Shot Mode The One Shot mode is identical to the Free-Running Period mode except that the ON bit is cleared and the timer is stopped when T2TMR matches T2PR and will not restart until the ON bit is cycled off and on. Postscaler (OUTPS) values other than zero are ignored in this mode because the timer is stopped at the first period event and the postscaler is reset when the timer is restarted. 26.1.3 Monostable Mode Monostable modes are similar to One Shot modes except that the ON bit is not cleared and the timer can be restarted by an external Reset event. 26.2 Timer2 Output The Timer2 module’s primary output is TMR2_postscaled, which pulses for a single TMR2_clk period upon each match of the postscaler counter and the OUTPS bits of the T2CON register. The postscaler is incremented each time the T2TMR value matches the T2PR value. This signal can also be selected as an input to other Core Independent Peripherals. In addition, the Timer2 is also used by the CCP module for pulse generation in PWM mode. See the “PWM Overview” and “PWM Period” sections in the “CCP - Capture/Compare/PWM Module” chapter for more details on setting up Timer2 for use with the CCP and PWM modules. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 376 PIC18F06/16Q41 TMR2 - Timer2 Module 26.3 External Reset Sources In addition to the clock source, the Timer2 can also be driven by an external Reset source input. This external Reset input is selected for each timer with the corresponding TxRST register. The external Reset input can control starting and stopping of the timer, as well as resetting the timer, depending on the mode used. 26.4 Timer2 Interrupt Timer2 can also generate a device interrupt. The interrupt is generated when the postscaler counter matches the selected postscaler value (OUTPS bits of T2CON register). The interrupt is enabled by setting the TMR2IE interrupt enable bit. Interrupt timing is illustrated in the figure below. Figure 26-2. Timer2 Prescaler, Postscaler, and Interrupt Timing Diagram Rev. 10-000 205B 3/6/201 9 CKPS ‘b010 TxPR 1 ‘b0001 OUTPS TMRx_clk TxTMR 0 1 0 1 0 1 0 TMRx_postscaled TMRxIF (1) (2) (1) Notes: 1. Setting the interrupt flag is synchronized with the instruction clock. Synchronization may take as many as two instruction cycles. 2. Cleared by software. 26.5 PSYNC Bit Setting the PSYNC bit synchronizes the prescaler output to FOSC/4. Setting this bit is required for reading the Timer2 counter register while the selected Timer clock is asynchronous to FOSC/4. Note:  Setting PSYNC requires that the output of the prescaler is slower than FOSC/4. Setting PSYNC when the output of the prescaler is greater than or equal to FOSC/4 may cause unexpected results. 26.6 CSYNC Bit All bits in the Timer2 SFRs are synchronized to FOSC/4 by default, not the Timer2 input clock. As such, if the Timer2 input clock is not synchronized to FOSC/4, it is possible for the Timer2 input clock to transition at the same time as the ON bit is set in software, which may cause undesirable behavior and glitches in the counter. Setting the CSYNC bit remedies this problem by synchronizing the ON bit to the Timer2 input clock instead of FOSC/4. However, as this synchronization uses an edge of the TMR2 input clock, up to one input clock cycle will be consumed and not counted by the Timer2 when CSYNC is set. Conversely, clearing the CSYNC bit synchronizes the ON bit to FOSC/4, which does not consume any clock edges, but has the previously stated risk of glitches. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 377 PIC18F06/16Q41 TMR2 - Timer2 Module 26.7 Operating Modes The mode of the timer is controlled by the MODE bits. Edge Triggered modes require six Timer clock periods between external triggers. Level Triggered modes require the triggering level to be at least three Timer clock periods long. External triggers are ignored while in Debug mode. Table 26-1. Operating Modes Table Mode MODE [4:3] [2:0] Free-Running Period 00 Output Operation Operation Start Reset Stop 000 Software gate (Figure 26-3) ON = 1 — ON = 0 001 Hardware gate, active-high (Figure 26-4) ON = 1 and TMRx_ers = 1 — ON = 0 or TMRx_ers = 0 010 Hardware gate, active-low ON = 1 and TMRx_ers = 0 — ON = 0 or TMRx_ers = 1 011 100 Rising or falling edge Reset Rising edge Reset (Figure 26-5) TMRx_ers ↕ TMRx_ers ↑ Falling edge Reset TMRx_ers ↓ 101 110 Period Pulse Period Pulse with Hardware Reset Low-level Reset One-shot ON = 0 or TMRx_ers = 1 TMRx_ers = 1 ON = 1 — Rising edge start (Figure 26-8) ON = 1 and TMRx_ers ↑ — Falling edge start ON = 1 and TMRx_ers ↓ — 011 Any edge start ON = 1 and TMRx_ers ↕ — 100 Rising edge start and Rising edge Reset (Figure 26-9) ON = 1 and TMRx_ers ↑ TMRx_ers ↑ Falling edge start and Falling edge Reset ON = 1 and TMRx_ers ↓ TMRx_ers ↓ 001 Edge-Triggered Start 010 (Note 1) Edge-Triggered Start 101 110 and Hardware Reset (Note 1) 111 © 2020-2021 Microchip Technology Inc. and its subsidiaries ON = 0 or Next clock after Rising edge start and Low-level Reset (Figure 26-10) ON = 1 and TMRx_ers ↑ TMRx_ers = 0 Falling edge start and High-level Reset ON = 1 and TMRx_ers ↓ TMRx_ers = 1 Preliminary Datasheet ON = 0 ON = 0 or TMRx_ers = 0 TMRx_ers = 0 Software start (Figure 26-7) 000 01 ON = 1 High-level Reset (Figure 26-6) 111 One Shot Timer Control TxTMR = TxPR (Note 2) DS40002214E-page 378 PIC18F06/16Q41 TMR2 - Timer2 Module ...........continued MODE Mode Output Operation [4:3] [2:0] Timer Control Operation Start Reset Stop Rising edge start (Figure 26-11) ON = 1 and TMRx_ers ↑ — ON = 0 or Falling edge start ON = 1 and TMRx_ers ↓ — Any edge start ON = 1 and TMRx_ers ↕ — 000 Reserved 001 Edge-Triggered Start Monostable 010 10 (Note 1) 011 Next clock after TxTMR = TxPR (Note 3) Reserved Reserved 100 101 One Shot ON = 1 and High-level start and ON = 0 or 110 Level-Triggered Start Low-level Reset (Figure 26-12) TMRx_ers = 1 TMRx_ers = 0 Held in Reset and ON = 1 and Low-level start and (Note 2) Hardware Reset 111 High-level Reset TMRx_ers = 0 TMRx_ers = 1 Reserved 11 xxx Reserved Reserved Reserved Notes:  1. If ON = 0, then an edge is required to restart the timer after ON = 1. 26.8 2. When T2TMR = T2PR, the next clock clears ON and stops T2TMR at 00h. 3. When T2TMR = T2PR, the next clock stops T2TMR at 00h but does not clear ON. Operation Examples Unless otherwise specified, the following notes apply to the following timing diagrams: • • • • 26.8.1 Both the prescaler and postscaler are set to 1:1 (both the CKPS and OUTPS bits). The diagrams illustrate any clock except FOSC/4 and show clock-sync delays of at least two full cycles for both ON and TMRx_ers. When using FOSC/4, the clock-sync delay is at least one instruction period for TMRx_ers; ON applies in the next instruction period. ON and TMRx_ers are somewhat generalized, and clock-sync delays may produce results that are slightly different than illustrated. The PWM Duty Cycle and PWM output are illustrated assuming that the timer is used for the PWM function of the CCP module as described in the “PWM Overview” section. The signals are not a part of the Timer2 module. Software Gate Mode This mode corresponds to legacy Timer2 operation. The timer increments with each clock input when ON = 1 and does not increment when ON = 0. When the TxTMR count equals the TxPR period count the timer resets on the next clock and continues counting from 0. Operation with the ON bit software controlled is illustrated in Figure 26-3. With TxPR = 5, the counter advances until TxTMR = 5, and goes to zero with the next clock. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 379 PIC18F06/16Q41 TMR2 - Timer2 Module Figure 26-3. Software Gate Mode Timing Diagram (MODE = ‘b00000) Rev. 10-000 195C 3/6/201 9 TMRx_clk Instruction(1) BSF BCF BSF ON 5 TxPR TxTMR 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 380 PIC18F06/16Q41 TMR2 - Timer2 Module 26.8.2 Hardware Gate Mode The Hardware Gate modes operate the same as the Software Gate mode except the TMRx_ers external signal can also gate the timer. When used with the CCP, the gating extends the PWM period. If the timer is stopped when the PWM output is high, then the duty cycle is also extended. When MODE = ‘b00001 then the timer is stopped when the external signal is high. When MODE = ‘b00010, then the timer is stopped when the external signal is low. Figure 26-4 illustrates the Hardware Gating mode for MODE = ‘b00001 in which a high input level starts the counter. Figure 26-4. Hardware Gate Mode Timing Diagram (MODE = ‘b00001) Rev. 10-000 196C 3/6/201 9 TMRx_clk TMRx_ers TxPR TxTMR 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 381 PIC18F06/16Q41 TMR2 - Timer2 Module 26.8.3 Edge Triggered Hardware Limit Mode In Hardware Limit mode, the timer can be reset by the TMRx_ers external signal before the timer reaches the period count. Three types of Resets are possible: • Reset on rising or falling edge (MODE = ‘b00011) • Reset on rising edge (MODE = ‘b00100) • Reset on falling edge (MODE = ‘b00101) When the timer is used in conjunction with the CCP in PWM mode then an early Reset shortens the period and restarts the PWM pulse after a two clock delay. Refer to Figure 26-5. Figure 26-5. Edge Triggered Hardware Limit Mode Timing Diagram (MODE = ‘b00100) Rev. 10-000197C 3/6/2019 TMRx_clk 5 TxPR Instruction(1) BSF BCF BSF ON TMRx_ers TxTMR 0 1 2 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 382 PIC18F06/16Q41 TMR2 - Timer2 Module 26.8.4 Level Triggered Hardware Limit Mode In the Level Triggered Hardware Limit Timer modes the counter is reset by high or low levels of the external signal TMRx_ers, as shown in Figure 26-6. Selecting MODE = ‘b00110 will cause the timer to reset on a low-level external signal. Selecting MODE = ‘b00111 will cause the timer to reset on a high-level external signal. In the example, the counter is reset while TMRx_ers = 1. ON is controlled by BSF and BCF instructions. When ON = 0, the external signal is ignored. When the CCP uses the timer as the PWM time base, then the PWM output will be set high when the timer starts counting and then set low only when the timer count matches the CCPRx value. The timer is reset when either the timer count matches the TxPR value or two clock periods after the external Reset signal goes true and stays true. The timer starts counting, and the PWM output is set high, on either the clock following the TxPR match or two clocks after the external Reset signal relinquishes the Reset. The PWM output will remain high until the timer counts up to match the CCPRx pulse-width value. If the external Reset signal goes true while the PWM output is high, then the PWM output will remain high until the Reset signal is released allowing the timer to count up to match the CCPRx value. Figure 26-6. Level Triggered Hardware Limit Mode Timing Diagram (MODE = ‘b00111) Rev. 10-000 198C 3/5/201 9 TMRx_clk TxPR 5 Instruction(1) BSF BCF BSF ON TMRx_ers TxTMR 0 1 2 0 1 2 3 4 5 0 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 383 PIC18F06/16Q41 TMR2 - Timer2 Module 26.8.5 Software Start One Shot Mode In One Shot mode, the timer resets and the ON bit is cleared when the timer value matches the TxPR period value. The ON bit must be set by software to start another timer cycle. Setting MODE = ‘b01000 selects One Shot mode which is illustrated in Figure 26-7. In the example, ON is controlled by BSF and BCF instructions. In the first case, a BSF instruction sets ON and the counter runs to completion and clears ON. In the second case, a BSF instruction starts the cycle, the BCF/BSF instructions turn the counter off and on during the cycle, and then it runs to completion. When One Shot mode is used in conjunction with the CCP PWM operation, the PWM pulse drive starts concurrent with setting the ON bit. Clearing the ON bit while the PWM drive is active will extend the PWM drive. The PWM drive will terminate when the timer value matches the CCPRx pulse-width value. The PWM drive will remain off until the software sets the ON bit to start another cycle. If the software clears the ON bit after the CCPRx match but before the TxPR match, then the PWM drive will be extended by the length of time the ON bit remains cleared. Another timing cycle can only be initiated by setting the ON bit after it has been cleared by a TxPR period count match. Figure 26-7. Software Start One Shot Mode Timing Diagram (MODE = ‘b01000) Rev. 10-000 199C 3/6/201 9 TMRx_clk TxPR Instruction(1) 5 BSF BSF BCF BSF ON TxTMR 0 1 2 3 4 5 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 384 PIC18F06/16Q41 TMR2 - Timer2 Module 26.8.6 Edge Triggered One Shot Mode The Edge Triggered One Shot modes start the timer on an edge from the external signal input, after the ON bit is set, and clear the ON bit when the timer matches the TxPR period value. The following edges will start the timer: • Rising edge (MODE = ‘b01001) • Falling edge (MODE = ‘b01010) • Rising or Falling edge (MODE = ‘b01011) If the timer is halted by clearing the ON bit, then another TMRx_ers edge is required after the ON bit is set to resume counting. Figure 26-8 illustrates operation in the rising edge One Shot mode. When Edge Triggered One Shot mode is used in conjunction with the CCP, then the edge-trigger will activate the PWM drive and the PWM drive will deactivate when the timer matches the CCPRx pulse-width value and stay deactivated when the timer halts at the TxPR period count match. Figure 26-8. Edge Triggered One Shot Mode Timing Diagram (MODE = ‘b01001) Rev. 10-000 200C 3/6/201 9 TMRx_clk TxPR Instruction(1) 5 BSF BSF BCF ON TMRx_ers TxTMR 0 1 2 3 4 5 0 1 2 CCP_pset TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 385 PIC18F06/16Q41 TMR2 - Timer2 Module 26.8.7 Edge Triggered Hardware Limit One Shot Mode In Edge Triggered Hardware Limit One Shot modes, the timer starts on the first external signal edge after the ON bit is set and resets on all subsequent edges. Only the first edge after the ON bit is set is needed to start the timer. The counter will resume counting automatically two clocks after all subsequent external Reset edges. Edge triggers are as follows: • Rising edge start and Reset (MODE = ‘b01100) • Falling edge start and Reset (MODE = ‘b01101) The timer resets and clears the ON bit when the timer value matches the TxPR period value. External signal edges will have no effect until after software sets the ON bit. Figure 26-9 illustrates the rising edge hardware limit one-shot operation. When this mode is used in conjunction with the CCP, then the first starting edge trigger, and all subsequent Reset edges, will activate the PWM drive. The PWM drive will deactivate when the timer matches the CCPRx pulse-width value and stay deactivated until the timer halts at the TxPR period match unless an external signal edge resets the timer before the match occurs. Figure 26-9. Edge Triggered Hardware Limit One Shot Mode Timing Diagram (MODE = ‘b01100) Rev. 10-000 201C 3/6/201 9 TMRx_clk TxPR Instruction(1) 5 BSF BSF ON TMRx_ers TxTMR 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 386 PIC18F06/16Q41 TMR2 - Timer2 Module 26.8.8 Level Reset, Edge Triggered Hardware Limit One Shot Modes In Level Triggered One Shot mode, the timer count is reset on the external signal level and starts counting on the rising/falling edge of the transition from Reset level to the active level while the ON bit is set. Reset levels are selected as follows: • Low Reset level (MODE = ‘b01110) • High Reset level (MODE = ‘b01111) When the timer count matches the TxPR period count, the timer is reset and the ON bit is cleared. When the ON bit is cleared by either a TxPR match or by software control, a new external signal edge is required after the ON bit is set to start the counter. When Level-Triggered Reset One Shot mode is used in conjunction with the CCP PWM operation, the PWM drive goes active with the external signal edge that starts the timer. The PWM drive goes inactive when the timer count equals the CCPRx pulse-width count. The PWM drive does not go active when the timer count clears at the TxPR period count match. Figure 26-10. Low Level Reset, Edge Triggered Hardware Limit One Shot Mode Timing Diagram (MODE = ‘b01110) Rev. 10-000 202C 3/6/201 9 TMRx_clk TxPR Instruction(1) 5 BSF BSF ON TMRx_ers TxTMR 0 1 2 3 4 5 0 1 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 26.8.9 Edge Triggered Monostable Modes The Edge Triggered Monostable modes start the timer on an edge from the external Reset signal input, after the ON bit is set, and stop incrementing the timer when the timer matches the TxPR period value. The following edges will start the timer: • Rising edge (MODE = ‘b10001) • Falling edge (MODE = ‘b10010) • Rising or Falling edge (MODE = ‘b10011) When an Edge Triggered Monostable mode is used in conjunction with the CCP PWM operation, the PWM drive goes active with the external Reset signal edge that starts the timer, but will not go active when the timer matches the TxPR value. While the timer is incrementing, additional edges on the external Reset signal will not affect the CCP PWM. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 387 PIC18F06/16Q41 TMR2 - Timer2 Module Figure 26-11. Rising Edge Triggered Monostable Mode Timing Diagram (MODE = ‘b10001) Rev. 10-000203B 3/6/2019 TMRx_clk 5 TxPR Instruction(1) BSF BCF BSF BCF BSF ON TMRx_ers TxTMR 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 26.8.10 Level Triggered Hardware Limit One Shot Modes The Level Triggered Hardware Limit One Shot modes hold the timer in Reset on an external Reset level and start counting when both the ON bit is set and the external signal is not at the Reset level. If one of either the external signal is not in Reset or the ON bit is set, then the other signal being set/made active will start the timer. Reset levels are selected as follows: • Low Reset level (MODE = ‘b10110) • High Reset level (MODE = ‘b10111) When the timer count matches the TxPR period count, the timer is reset and the ON bit is cleared. When the ON bit is cleared by either a TxPR match or by software control, the timer will stay in Reset until both the ON bit is set and the external signal is not at the Reset level. When Level Triggered Hardware Limit One Shot modes are used in conjunction with the CCP PWM operation, the PWM drive goes active with either the external signal edge or the setting of the ON bit, whichever of the two starts the timer. Figure 26-12. Level Triggered Hardware Limit One Shot Mode Timing Diagram (MODE = ‘b10110) Rev. 10-000 204B 3/6/201 9 TMRx_clk TxPR Instruction (1) 5 BSF BSF BCF BSF ON TMRx_ers TxTMR 0 1 2 3 4 5 0 1 2 3 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle D3 PWM Output Note: 1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 388 PIC18F06/16Q41 TMR2 - Timer2 Module 26.9 Timer2 Operation During Sleep When PSYNC = 1, Timer2 cannot be operated while the processor is in Sleep mode. The contents of the T2TMR and T2PR registers will remain unchanged while the processor is in Sleep mode. When PSYNC = 0, Timer2 will operate in Sleep as long as the clock source selected is also still running. If any internal oscillator is selected as the clock source, it will stay active during Sleep mode. 26.10 Register Definitions: Timer2 Control Long bit name prefixes for the Timer2 peripherals are shown in the table below. Refer to the “Long Bit Names” section of the “Register and Bit Naming Conventions” chapter for more information. Table 26-2. Timer2 Long Bit Name Prefixes Peripheral Bit Name Prefix Timer2 T2 Timer4 T4 Important:  References to module Timer2 apply to all the even numbered timers on this device (Timer2, Timer4, etc.). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 389 PIC18F06/16Q41 TMR2 - Timer2 Module 26.10.1 TxTMR Name:  Address:  TxTMR 0x31C,0x329 Timer Counter Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 TxTMR[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – TxTMR[7:0] Timerx Counter © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 390 PIC18F06/16Q41 TMR2 - Timer2 Module 26.10.2 TxPR Name:  Address:  TxPR 0x31D,0x32A Timer Period Register Bit 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 TxPR[7:0] Access Reset R/W 1 R/W 1 R/W 1 R/W 1 Bits 7:0 – TxPR[7:0] Timer Period Register Value Description 0 to 255 The timer restarts at ‘0’ when TxTMR reaches the TxPR value © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 391 PIC18F06/16Q41 TMR2 - Timer2 Module 26.10.3 TxCON Name:  Address:  TxCON 0x31E,0x32B Timerx Control Register Bit Access Reset 7 ON R/W/HC 0 6 R/W 0 5 CKPS[2:0] R/W 0 4 3 R/W 0 R/W 0 2 1 OUTPS[3:0] R/W R/W 0 0 0 R/W 0 Bit 7 – ON  Timer On(1) Value Description 1 Timer is on 0 Timer is off: All counters and state machines are reset Bits 6:4 – CKPS[2:0] Timer Clock Prescale Select Value Description 111 1:128 Prescaler 110 1:64 Prescaler 101 1:32 Prescaler 100 1:16 Prescaler 011 1:8 Prescaler 010 1:4 Prescaler 001 1:2 Prescaler 000 1:1 Prescaler Bits 3:0 – OUTPS[3:0] Timer Output Postscaler Select Value Description 1111 1:16 Postscaler 1110 1:15 Postscaler 1101 1:14 Postscaler 1100 1:13 Postscaler 1011 1:12 Postscaler 1010 1:11 Postscaler 1001 1:10 Postscaler 1000 1:9 Postscaler 0111 1:8 Postscaler 0110 1:7 Postscaler 0101 1:6 Postscaler 0100 1:5 Postscaler 0011 1:4 Postscaler 0010 1:3 Postscaler 0001 1:2 Postscaler 0000 1:1 Postscaler Note:  1. In certain modes, the ON bit will be auto-cleared by hardware. See Table 26-1. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 392 PIC18F06/16Q41 TMR2 - Timer2 Module 26.10.4 TxHLT Name:  Address:  TxHLT 0x31F,0x32C Timer Hardware Limit Control Register Bit 7 PSYNC R/W 0 Access Reset 6 CPOL R/W 0 5 CSYNC R/W 0 4 3 R/W 0 R/W 0 2 MODE[4:0] R/W 0 1 0 R/W 0 R/W 0 Bit 7 – PSYNC  Timer Prescaler Synchronization Enable(1, 2) Value Description 1 Timer Prescaler Output is synchronized to FOSC/4 0 Timer Prescaler Output is not synchronized to FOSC/4 Bit 6 – CPOL  Timer Clock Polarity Selection(3) Value Description 1 Falling edge of input clock clocks timer/prescaler 0 Rising edge of input clock clocks timer/prescaler Bit 5 – CSYNC  Timer Clock Synchronization Enable(4, 5) Value Description 1 ON bit is synchronized to timer clock input 0 ON bit is not synchronized to timer clock input Bits 4:0 – MODE[4:0]  Timer Control Mode Selection(6, 7) Value Description 00000 to See Table 26-1 11111 Notes:  1. Setting this bit ensures that reading TxTMR will return a valid data value. 2. When this bit is ‘1’, the Timer cannot operate in Sleep mode. 3. CKPOL must not be changed while ON = 1. 4. 5. 6. Setting this bit ensures glitch-free operation when the ON is enabled or disabled. When this bit is set, then the timer operation will be delayed by two input clocks after the ON bit is set. Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting the value of TxTMR). When TxTMR = TxPR, the next clock clears TxTMR, regardless of the operating mode. 7. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 393 PIC18F06/16Q41 TMR2 - Timer2 Module 26.10.5 TxCLKCON Name:  Address:  TxCLKCON 0x320,0x32D Timer Clock Source Selection Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 CS[3:0] Access Reset R/W 0 R/W 0 Bits 3:0 – CS[3:0] Timer Clock Source Selection Table 26-3. Clock Source Selection CS 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Clock Source Timer2 Timer4 CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT ZCD_OUT NCO1_OUT CLKREF_OUT EXTOSC SOSC MFINTOSC (32 kHz) MFINTOSC (500 kHz) LFINTOSC HFINTOSC FOSC FOSC/4 Pin selected by T2INPPS © 2020-2021 Microchip Technology Inc. and its subsidiaries Pin selected by T4INPPS Preliminary Datasheet DS40002214E-page 394 PIC18F06/16Q41 TMR2 - Timer2 Module 26.10.6 TxRST Name:  Address:  TxRST 0x321,0x32E Timer External Reset Signal Selection Register Bit 7 6 Access Reset 5 4 3 R/W 0 R/W 0 2 RSEL[4:0] R/W 0 1 0 R/W 0 R/W 0 Bits 4:0 – RSEL[4:0] External Reset Source Selection Table 26-4. External Reset Sources RSEL 11111 - 11000 10111 10110 10101 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 © 2020-2021 Microchip Technology Inc. and its subsidiaries Reset Source TMR2 TMR4 Reserved U3TX_Edge (Positive/Negative) U3RX_Edge (Positive/Negative) U2TX_Edge (Positive/Negative) U2RX_Edge (Positive/Negative) U1TX_Edge (Positive/Negative) U1RX_Edge (Positive/Negative) CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT ZCD_OUT CMP2_OUT CMP1_OUT PWM3S1P2_OUT PWM3S1P1_OUT PWM2S1P2_OUT PWM2S1P1_OUT PWM1S1P2_OUT PWM1S1P1_OUT CCP1_OUT Reserved TMR4_Postscaler_OUT Reserved Pin selected by T2INPPS Preliminary Datasheet Reserved Reserved TMR2_Postscaler_OUT Pin selected by T4INPPS DS40002214E-page 395 PIC18F06/16Q41 TMR2 - Timer2 Module 26.11 Address 0x00 ... 0x031B 0x031C 0x031D 0x031E 0x031F 0x0320 0x0321 0x0322 ... 0x0328 0x0329 0x032A 0x032B 0x032C 0x032D 0x032E Register Summary - Timer2 Name Bit Pos. 7 6 5 4 3 2 1 0 Reserved T2TMR T2PR T2CON T2HLT T2CLKCON T2RST 7:0 7:0 7:0 7:0 7:0 7:0 T2TMR[7:0] T2PR[7:0] ON PSYNC CPOL CKPS[2:0] CSYNC OUTPS[3:0] MODE[4:0] CS[3:0] RSEL[4:0] Reserved T4TMR T4PR T4CON T4HLT T4CLKCON T4RST 7:0 7:0 7:0 7:0 7:0 7:0 T4TMR[7:0] T4PR[7:0] ON PSYNC © 2020-2021 Microchip Technology Inc. and its subsidiaries CPOL CKPS[2:0] CSYNC Preliminary Datasheet OUTPS[3:0] MODE[4:0] CS[3:0] RSEL[4:0] DS40002214E-page 396 PIC18F06/16Q41 SMT - Signal Measurement Timer 27. SMT - Signal Measurement Timer The Signal Measurement Timer (SMT) is a 24-bit counter with advanced clock and gating logic, which can be configured for measuring a variety of digital signal parameters such as pulse width, frequency and duty cycle, and the time difference between edges on two signals. Features of the SMT include: • 24-Bit Timer/Counter • Two 24-Bit Measurement Capture Registers • One 24-Bit Period Match Register • Multi-Mode Operation, Including Relative Timing Measurement • Interrupt-on-Period Match and Acquisition Complete • Multiple Clock, Signal and Window Sources Below is the block diagram for the SMT module. Figure 27-1. Signal Measurement Timer Block Diagram Rev. 10-000161E 11/13/2018 Period Latch SMT_window SMT Clock Sync Circuit SMT_signal SMT Clock Sync Circuit Set SMTxPRAIF SMTxPR Control Logic Set SMTxIF Comparator Reset Enable SMT Clock Sources Prescaler SMTxTMR Window Latch 24-bit Buffer SMTxCPR 24-bit Buffer SMTxCPW Set SMTxPWAIF CSEL 27.1 SMT Operation 27.1.1 Clock Source Selection The SMT clock source is selected by configuring the CSEL bits. The clock source is prescaled by using the PS bits. The prescaled clock source is used to clock both the counter and any synchronization logic used by the module. The polarity of the clock source is selected by using the CPOL bit. 27.1.2 Signal and Window Source Selection The SMT signal and window sources are selected by configuring the SSEL bits and the WSEL bits (refer to the figure below). The polarity of the signal and window sources is selected by using the SPOL and WPOL bits, respectively. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 397 PIC18F06/16Q41 SMT - Signal Measurement Timer Figure 27-2. SMT Signal and SMT Window Source Selections Rev. 10-000173D 11/13/2018 See SMTxSIG Register SMT_signal SMT_window WSEL SSEL 27.1.3 See SMTxWIN Register Time Base The SMTxTMR register is the 24-bit counter/timer used for measurement in each of the modes of the SMT. Setting the RST bit clears the SMTxTMR register to 0x000000. It can be written to and read by software. It is not guarded for atomic access, therefore reads and writes to the SMTxTMR register must be made only when GO = 0. The counter can be prevented from resetting at the end of the timer period by using the STP bit. When STP = 1, the SMTxTMR will stop and remain equal to the SMTxPR register. When STP = 0, the SMTxTMR register resets to 0x000000 at the end of the period. 27.1.4 Pulse-Width and Period Captures The SMTxCPW and SMTxCPR registers are used to latch in the value of the SMTxTMR register, based on the SMT mode of operation. These registers can also be updated with the current value of the SMTxTMR value by setting the CPWUP and CPRUP bits, respectively. 27.1.5 Status Information The SMT provides input status information for the user without requiring the need to monitor the raw incoming signals. Go Status: Timer run status is indicated by the TS bit. The TS bit is delayed in time by synchronizer delays in non-counter modes. Signal Status: Signal status is indicated by the AS bit. This bit is used in all modes, except Window Measure, Timeof-Flight, and Capture modes, and is only valid when TS = 1. The signal status is delayed in time by synchronizer delays in non-counter modes. Window Status: Window status is indicated by the WS bit. This bit is only used in Windowed Measure, Gated Counter, and Gated Window Measure modes, and is only valid when TS = 1. Window status is delayed in time by synchronizer delays in non-counter modes. 27.1.6 Modes of Operation The modes of operation are summarized in the table below. The sections following the table provide descriptions and examples of how each mode can be used. Note that all waveforms assume WPOL/SPOL/CPOL = 0. For all modes, the REPEAT bit controls whether the acquisition happens only once or is repeated. When REPEAT = 0 (Single Acquisition mode), the timer will stop incrementing and the GO bit will be cleared upon the completion of an acquisition. Otherwise, the timer will continue and allow for continued acquisitions to overwrite the previous ones, until the timer is stopped by software. Table 27-1. Modes of Operation MODE Mode of Operation Synchronous Operation 1111-1011 Reserved - © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 398 PIC18F06/16Q41 SMT - Signal Measurement Timer ...........continued MODE Mode of Operation Synchronous Operation 1010 Windowed Counter No 1001 Gated Counter No 1000 Counter No 0111 Capture Yes 0110 Time of Flight Measurement Yes 0101 Gated Windowed Measurement Yes 0100 Windowed Measurement Yes 0011 High and Low Time Measurement Yes 0010 Period and Duty Cycle Measurement Yes 0001 Gated Timer Yes 0000 Timer Yes 27.1.6.1 Timer Mode Timer mode is the basic mode of operation where the SMTxTMR register is used as a 24-bit timer. No data acquisition takes place in this mode. The timer increments as long as the GO bit has been set by software. No SMT window or SMT signal events affect the GO bit. Everything is synchronized to the SMT clock source. When the timer experiences a period match (SMTxTMR = SMTxPR), the SMTxTMR register is reset and the period match interrupt is set. Refer to the figure below. Figure 27-3. Timer Mode Timing Diagram Rev. 10-000174A 11/13/2018 SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxPR SMTxTMR 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 SMTxIF 27.1.6.2 Gated Timer Mode Gated Timer mode uses the SMT_signal input, selected with the SSEL bits, to control whether or not the SMTxTMR register will increment. Upon a falling edge of the signal, the SMTxCPW register will update to the current value of the SMTxTMR register. Example waveforms for both repeated and single acquisitions are provided in the figures below. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 399 PIC18F06/16Q41 SMT - Signal Measurement Timer Figure 27-4. Gated Timer Mode, Repeat Acquisition Timing Diagram Rev. 10-000176A 11/15/2018 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync 0xFFFFFF SMTxPR 0 SMTxTMR 1 2 3 4 5 6 7 5 SMTxCPW 7 SMTxPWAIF Figure 27-5. Gated Timer Mode, Single Acquisition Timing Diagram Rev. 10-000175A 11/15/2018 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxPR SMTxTMR 0xFFFFFF 0 1 2 3 4 5 SMTxCPW 5 SMTxPWAIF © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 400 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.1.6.3 Period and Duty Cycle Measurement Mode In this mode, either the duty cycle or period of the input signal can be acquired relative to the SMT clock. The SMTxCPW register is updated on a falling edge of the signal, and the SMTxCPR register is updated on a rising edge of the signal. The rising edge also resets the SMTxTMR register to 0x000001. The GO bit is reset on a rising edge when the SMT is in Single Acquisition mode. Refer to the figures below. Figure 27-6. Period and Duty Cycle, Repeat Acquisition Mode Timing Diagram Rev. 10-000177A 11/15/2018 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 6 7 8 SMTxCPW 9 10 11 1 2 3 4 5 5 2 SMTxCPR 11 SMTxPWAIF SMTxPRAIF Figure 27-7. Period and Duty Cycle, Single Acquisition Mode Timing Diagram Rev. 10-000178A 11/15/2018 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 6 SMTxCPW 7 8 9 10 11 1 5 SMTxCPR 11 SMTxPWAIF SMTxPRAIF © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 401 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.1.6.4 High and Low Measurement Mode This mode measures the high and low pulse time of the SMT_signal, relative to the SMT clock. The SMTxTMR register starts incrementing on a rising edge of the input signal. On the falling edge, the SMTxTMR register value is written to the SMTxCPW register. The SMTxTMR register is then reset and continues to increment. On the next rising edge, the SMTxTMR register value is written to the SMTxCPR register. The SMTxTMR register is then reset and continues to increment. Refer to the figures below. Figure 27-8. High and Low Measurement Mode, Repeat Acquisition Timing Diagram Rev. 10-000180A 11/15/2018 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 1 2 3 SMTxCPW 4 5 6 1 2 1 2 3 5 2 SMTxCPR 6 SMTxPWAIF SMTxPRAIF Figure 27-9. High and Low Measurement Mode, Single Acquisition Timing Diagram Rev. 10-000179A 11/15/2018 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 1 SMTxCPW 2 3 4 5 6 5 SMTxCPR 6 SMTxPWAIF SMTxPRAIF © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 402 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.1.6.5 Windowed Measurement Mode This mode measures the period of the SMT_window input, selected with the WSEL bits, relative to the SMT clock. On the rising edge of the window input, the SMTxTMR register value is written to the SMTxCPR register. In Repeat mode, the SMTxTMR register is reset and continues to increment. The capture and Reset process repeats on the next rising edge. Refer to the figures below. Figure 27-10. Windowed Measurement Mode, Repeat Acquisition Timing Diagram Rev. 10-000182A 11/15/2018 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 12 SMTxCPR 1 2 3 4 8 SMTxPRAIF Figure 27-11. Windowed Measurement Mode, Single Acquisition Timing Diagram Rev. 10-000181A 11/15/2018 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 SMTxCPR 12 SMTxPRAIF © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 403 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.1.6.6 Gated Window Measurement Mode This mode measures the duty cycle of the SMT_signal input over a known input window. It does so by incrementing the SMTxTMR register on each rising edge of the SMTx clock signal when the SMT_signal input is high. The accumulated SMTxTMR register value is written to the SMTxCPR register, and the SMTxTMR register is reset on every rising edge of the window input after the first. Refer to the figures below. Figure 27-12. Gated Windowed Measurement Mode, Repeat Acquisition Timing Diagram Rev. 10-000184A 11/15/2018 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 6 0 1 2 3 6 SMTxCPR 0 3 SMTxPRAIF Figure 27-13. Gated Windowed Measurement Mode, Single Acquisition Timing Diagram Rev. 10-000183A 11/15/2018 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 6 6 SMTxCPR SMTxPRAIF © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 404 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.1.6.7 Time-of-Flight Measurement Mode This mode measures the time interval between a rising edge on the SMT_window input and a rising edge on the SMT_signal input. The SMTxTMR register starts incrementing on the rising edge of the window input. The SMTxTMR register value is written to the SMTxCPR register and the SMTxTMR register is reset on a rising edge of the signal input. In the event of two rising edges of the window signal without a signal rising edge, the SMTxCPW register will be written with the current value of the SMTxTMR register, which will then be reset. Refer to the figures below. Figure 27-14. Time-of-Flight Mode, Repeat Acquisition Timing Diagram Rev. 10-000186A 11/15/2018 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 13 SMTxCPW SMTxCPR 4 SMTxPWAIF SMTxPRAIF Figure 27-15. Time-of-Flight Mode, Single Acquisition Timing Diagram Rev. 10-000185A 11/15/2018 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 SMTxCPW SMTxCPR 4 SMTxPWAIF SMTxPRAIF © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 405 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.1.6.8 Capture Mode This mode captures the SMTxTMR register value based on a rising or falling edge of the SMT_window input and triggers an interrupt. This mimics the capture feature of a CCP module. The timer begins incrementing upon the GO bit being set. The SMTxTMR register value is written to the SMTxCPR register on each rising edge of the SMT_window input. The SMTxTMR register value is written to the SMTxCPW register on each falling edge of the SMT_window input. The timer is not reset by any hardware conditions in this mode and must be reset by software, if desired. Refer to the figures below. Figure 27-16. Capture Mode, Repeat Acquisition Timing Diagram Rev. 10-000188A 11/15/2018 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3 SMTxCPW SMTxCPR 19 2 18 32 31 SMTxPWAIF SMTxPRAIF Figure 27-17. Capture Mode, Single Acquisition Timing Diagram Rev. 10-000187A 11/15/2018 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 3 SMTxCPW SMTxCPR 2 SMTxPWAIF SMTxPRAIF © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 406 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.1.6.9 Counter Mode This mode increments the SMTxTMR register on each rising edge of the SMT_signal input. This mode is asynchronous to the SMT clock and uses the SMT_signal input as a time source. The SMTxCPW register will be updated with the current SMTxTMR register value on the falling edge of the SMT_window input. Refer to the figure below. Figure 27-18. Counter Mode Timing Diagram Rev. 10-000189A 11/15/2018 SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 SMTxCPW 12 27 25 27.1.6.10 Gated Counter Mode This mode counts rising edges on the SMT_signal input, gated by the SMT_window input. It increments the SMTxTMR register for each rising edge of the SMT_signal input while the SMT_window input is high. The SMTxTMR register value is written to the SMTxCPW register upon a falling edge of the SMT_window input. Refer to the figures below. Figure 27-19. Gated Counter Mode, Repeat Acquisition Timing Diagram Rev. 10-000190A 11/15/2018 SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR 0 1 2 3 4 5 6 7 8 SMTxCPW 9 10 11 12 8 13 13 SMTxPWAIF Figure 27-20. Gated Counter Mode, Single Acquisition Timing Diagram Rev. 10-000191A 11/15/2018 SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR 0 1 2 3 4 5 6 7 SMTxCPW 8 8 SMTxPWAIF © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 407 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.1.6.11 Windowed Counter Mode This mode counts rising edges of the SMT_signal between rising edges of the SMT_window input. Beginning with the rising edge of the SMT_window input, the SMTxTMR register is incremented for every rising edge of the SMT_signal input. The SMTxTMR register value is written to the SMTxCPW register on the falling edge of the SMT_window input and the SMTxTMR register continues to increment. The SMTxTMR register value is written to the SMTxCPR register, then reset on each rising edge of the SMT_window input after the first. Refer to the figures below. Figure 27-21. Windowed Counter Mode, Repeat Acquisition Timing Diagram Rev. 10-000192A 11/15/2018 SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 SMTxCPW 2 3 4 9 5 5 16 SMTxCPR SMTxPWAIF SMTxPRAIF Figure 27-22. Windowed Counter Mode, Single Acquisition Timing Diagram Rev. 10-000193A 11/15/2018 SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SMTxCPW 9 16 SMTxCPR SMTxPWAIF SMTxPRAIF 27.1.7 Interrupts The SMT has three interrupts located in one of the PIR registers: • Pulse-Width Acquisition Interrupt (SMTxPWAIF): Interrupt triggers when the SMTxCPW register is updated with the SMTxTMR register value. • Period Acquisition Interrupt (SMTxPRAIF): Interrupt triggers when the SMTxCPR register is updated with the SMTxTMR register value. • Counter Period Match Interrupt (SMTxIF): Interrupt triggers when the SMTxTMR register equals the SMTxPR register. Each of the above interrupts can be enabled/disabled using the corresponding bits in the PIE register. 27.1.8 Operation During Sleep The SMT can operate during Sleep mode, provided that the clock and signal sources continue to function. In general, internal clock sources, such as HFINTOSC, continue to operate in Sleep mode when selected as the clock source, whereas external oscillators, such as FOSC and FOSC/4 cease to operate in Sleep. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 408 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.2 Register Definitions: SMT Control Long bit name prefixes for the SMT peripherals are shown in the table below. Replace the x in SMTx with the SMT peripheral instance number. Refer to the “Long Bit Names” section in the “Register and Nit Naming Conventions” chapter for more information. Table 27-2. SMT Long Bit Name Prefixes Peripheral Bit Name Prefix SMT1 SMT1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 409 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.2.1 SMTxCON0 Name:  Address:  SMTxCON0 0x030C SMT Control Register 0 Bit Access Reset 7 EN R/W 0 6 5 STP R/W 0 4 WPOL R/W 0 3 SPOL R/W 0 2 CPOL R/W 0 1 0 PS[1:0] R/W 0 R/W 0 Bit 7 – EN SMT Enable Value Description 1 SMT is enabled 0 SMT is disabled; internal states are reset, clock requests are disabled Bit 5 – STP SMT Counter Halt Enable Value Condition Description 1 When SMTxTMR = SMTxPR Counter remains at SMTxPR; period match interrupt occurs when clocked 0 When SMTxTMR = SMTxPR Counter resets to 0x000000; period match interrupt occurs when clocked Bit 4 – WPOL SMT_window Input Polarity Control Value Description 1 SMT_window input is active-low/falling edge enabled 0 SMT_window input is active-high/rising edge enabled Bit 3 – SPOL SMT_signal Input Polarity Control Value Description 1 SMT_signal input is active-low/falling edge enabled 0 SMT_signal input is active-high/rising edge enabled Bit 2 – CPOL SMT Clock Input Polarity Control Value Description 1 SMTxTMR increments on the falling edge of the selected clock signal 0 SMTxTMR increments on the rising edge of the selected clock signal Bits 1:0 – PS[1:0] SMT Prescale Select Value Description 11 Prescaler = 1:8 10 Prescaler = 1:4 01 Prescaler = 1:2 00 Prescaler = 1:1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 410 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.2.2 SMTxCON1 Name:  Address:  SMTxCON1 0x030D SMT Control Register 1 Bit Access Reset 7 GO R/W 0 6 REPEAT R/W 0 5 4 3 2 1 0 R/W 0 R/W 0 MODE[3:0] R/W 0 R/W 0 Bit 7 – GO SMT GO Data Acquisition Value Description 1 Incrementing, acquiring data is enabled 0 Incrementing, acquiring data is disabled Bit 6 – REPEAT SMT Repeat Acquisition Enable Value Description 1 Repeat Data Acquisition mode is enabled 0 Single Acquisition mode is enabled Bits 3:0 – MODE[3:0] SMT Operation Mode Select Value Description 1111 Reserved 1110 Reserved 1101 Reserved 1100 Reserved 1011 Reserved 1010 Windowed Counter 1001 Gated Counter 1000 Counter 0111 Capture 0110 Time-of-Flight 0101 Gated Windowed Measurement 0100 Windowed Measurement 0011 High and Low Time Measurement 0010 Period and Duty Cycle Acquisition 0001 Gated Timer 0000 Timer © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 411 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.2.3 SMTxSTAT Name:  Address:  SMTxSTAT 0x030E SMT Status Register Bit Access Reset 7 CPRUP R/W/HC 0 6 CPWUP R/W/HC 0 5 RST R/W 0 4 3 2 TS R 0 1 WS R 0 0 AS R 0 Bit 7 – CPRUP SMT Manual Period Buffer Update Value Description 1 Request write of SMTxTMR value to SMTxCPR registers 0 SMTxCPR registers update is complete Bit 6 – CPWUP SMT Manual Pulse-Width Buffer Update Value Description 1 Request write of SMTxTMR value to SMTxCPW registers 0 SMTxCPW registers update is complete Bit 5 – RST SMT Manual Timer Reset Value Description 1 Request Reset to SMTxTMR registers 0 SMTxTMR registers update is complete Bit 2 – TS SMT GO Value Status Value Description 1 SMTxTMR is incrementing 0 SMTxTMR is not incrementing Bit 1 – WS SMT Window Status Value Description 1 SMT window is open 0 SMT window is closed Bit 0 – AS SMT Signal Value Status Value Description 1 SMT acquisition is in progress 0 SMT acquisition is not in progress © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 412 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.2.4 SMTxCLK Name:  Address:  SMTxCLK 0x030F SMT Clock Selection Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 CSEL[3:0] Access Reset R/W 0 R/W 0 Bits 3:0 – CSEL[3:0] SMT Clock Selection CSEL Value 1111-1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 © 2020-2021 Microchip Technology Inc. and its subsidiaries Source Reserved CLKR EXTOSC SOSC MFINTOSC (32 kHz) MFINTOSC (500 kHz) LFINTOSC HFINTOSC FOSC FOSC/4 Preliminary Datasheet Active in Sleep No No Yes Yes Yes Yes Yes Yes No No DS40002214E-page 413 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.2.5 SMTxWIN Name:  Address:  SMTxWIN 0x0311 SMT Window Input Select Register Bit 7 6 Access Reset 5 4 3 R/W 0 R/W 0 2 WSEL[4:0] R/W 0 1 0 R/W 0 R/W 0 Bits 4:0 – WSEL[4:0] SMT Window Signal Selection WSEL Value 11111 - 11000 10111 10110 10101 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 © 2020-2021 Microchip Technology Inc. and its subsidiaries Window Source Reserved CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT ZCD_OUT CMP2_OUT CMP1_OUT NCO1_OUT PWM3S1P2_OUT PWM3S1P1_OUT PWM2S1P2_OUT PWM2S1P1_OUT PWM1S1P2_OUT PWM1S1P1_OUT CCP1_OUT TMR4_Postscaler_OUT TMR2_Postscaler_OUT TMR0_OUT CLKREF EXTOSC SOSC MFINTOSC (32 kHz) LFINTOSC SMT1WINPPS Preliminary Datasheet Active in Sleep No No No No No No No No No No No No No No No No No No No No Yes Yes Yes Yes No DS40002214E-page 414 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.2.6 SMTxSIG Name:  Address:  SMTxSIG 0x0310 SMT Signal Selection Register Bit 7 6 5 Access Reset 4 3 R/W 0 R/W 0 2 SSEL[4:0] R/W 0 1 0 R/W 0 R/W 0 Bits 4:0 – SSEL[4:0] SMT Signal Selection SSEL Value 11111 - 10101 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 © 2020-2021 Microchip Technology Inc. and its subsidiaries Source Reserved CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT ZCD_OUT CMP2_OUT CMP1_OUT NCO1_OUT PWM3S1P2_OUT PWM3S1P1_OUT PWM2S1P2_OUT PWM2S1P1_OUT PWM1S1P2_OUT PWM1S1P1_OUT CCP1_OUT TMR4_Postscaler_OUT TMR3_OUT TMR2_Postscaler_OUT TMR1_OUT TMR0_OUT SMT1SIGPPS Preliminary Datasheet DS40002214E-page 415 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.2.7 SMTxTMR Name:  Address:  SMTxTMR 0x0300 SMT Timer Register Bit 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 TMR[23:16] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 TMR[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 TMR[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 23:0 – TMR[23:0] SMT Timer Value Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • SMTxTMRU: Accesses the upper byte TMR[23:16] • SMTxTMRH: Accesses the high byte TMR[15:8] • SMTxTMRL: Accesses the low byte TMR[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 416 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.2.8 SMTxCPR Name:  Address:  SMTxCPR 0x0303 SMT Captured Period Register Bit 23 22 21 20 19 18 17 16 R x R x R x R x 11 10 9 8 R x R x R x R x 3 2 1 0 R x R x R x R x CPR[23:16] Access Reset R x R x R x R x Bit 15 14 13 12 CPR[15:8] Access Reset R x R x R x R x Bit 7 6 5 4 CPR[7:0] Access Reset R x R x R x R x Bits 23:0 – CPR[23:0] SMTxTMR Value at Time of Period Capture Event Reset States: POR/BOR = xxxxxxxxxxxxxxxxxxxxxxxx All Other Resets = uuuuuuuuuuuuuuuuuuuuuuuu Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • SMTxCPRU: Accesses the upper byte CPR[23:16] • SMTxCPRH: Accesses the high byte CPR[15:8] • SMTxCPRL: Accesses the low byte CPR[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 417 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.2.9 SMTxCPW Name:  Address:  SMTxCPW 0x0306 SMT Captured Pulse-Width Register Bit 23 22 21 20 19 18 17 16 R x R x R x R x 11 10 9 8 R x R x R x R x 3 2 1 0 R x R x R x R x CPW[23:16] Access Reset R x R x R x R x Bit 15 14 13 12 CPW[15:8] Access Reset R x R x R x R x Bit 7 6 5 4 CPW[7:0] Access Reset R x R x R x R x Bits 23:0 – CPW[23:0] SMTxTMR Value at Time of Capture Event Reset States: POR/BOR = xxxxxxxxxxxxxxxxxxxxxxxx All Other Resets = uuuuuuuuuuuuuuuuuuuuuuuu Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • SMTxCPWU: Accesses the upper byte CPW[23:16] • SMTxCPWH: Accesses the high byte CPW[15:8] • SMTxCPWL: Accesses the low byte CPW[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 418 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.2.10 SMTxPR Name:  Address:  SMTxPR 0x0309 SMT Period Register Bit 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 PR[23:16] Access Reset Bit R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 PR[15:8] Access Reset Bit R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 PR[7:0] Access Reset R/W 1 R/W 1 R/W 1 R/W 1 Bits 23:0 – PR[23:0] The SMTxTMR Value at Which the SMTxTMR Resets to Zero Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • SMTxPRU: Accesses the upper byte PR[23:16] • SMTxPRH: Accesses the high byte PR[15:8] • SMTxPRL: Accesses the low byte PR[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 419 PIC18F06/16Q41 SMT - Signal Measurement Timer 27.3 Register Summary - SMT Control Address Name 0x00 ... 0x02FF Reserved 0x0300 SMT1TMR 0x0303 SMT1CPR 0x0306 SMT1CPW 0x0309 SMT1PR 0x030C 0x030D 0x030E 0x030F 0x0310 0x0311 SMT1CON0 SMT1CON1 SMT1STAT SMT1CLK SMT1SIG SMT1WIN Bit Pos. 7:0 15:8 23:16 7:0 15:8 23:16 7:0 15:8 23:16 7:0 15:8 23:16 7:0 7:0 7:0 7:0 7:0 7:0 7 EN GO CPRUP © 2020-2021 Microchip Technology Inc. and its subsidiaries 6 5 STP REPEAT CPWUP 4 3 TMR[7:0] TMR[15:8] TMR[23:16] CPR[7:0] CPR[15:8] CPR[23:16] CPW[7:0] CPW[15:8] CPW[23:16] PR[7:0] PR[15:8] PR[23:16] WPOL SPOL RST Preliminary Datasheet 2 1 CPOL PS[1:0] MODE[3:0] TS WS CSEL[3:0] SSEL[4:0] WSEL[4:0] 0 AS DS40002214E-page 420 PIC18F06/16Q41 CCP - Capture/Compare/PWM Module 28. CCP - Capture/Compare/PWM Module The Capture/Compare/PWM module is a peripheral that allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. Each individual CCP module can select the timer source that controls the module. The default timer selection is Timer1 when using Capture/Compare mode and Timer2 when using PWM mode in the CCPx module. Note that the Capture/Compare mode operation is described with respect to Timer1 and the PWM mode operation is described with respect to Timer2 in the following sections. The Capture and Compare functions are identical for all CCP modules. Important:  In devices with more than one CCP module, it is very important to pay close attention to the register names used. Throughout this section, the prefix “CCPx” is used as a generic replacement for specific numbering. A number placed where the “x” is in the prefix is used to distinguish between separate modules. For example, CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 28.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (CCPxCON), a capture input selection register (CCPxCAP) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). 28.1.1 CCP Modules and Timer Resources The CCP modules utilize Timers 1 through 4 that vary with the selected mode. Various timers are available to the CCP modules in Capture, Compare or PWM modes, as shown in the table below. Table 28-1. CCP Mode - Timer Resources CCP Mode Timer Resource Capture Timer1, Timer3 Compare PWM Timer2, Timer4 The assignment of a particular timer to a module is selected as shown in the “Capture, Compare, and PWM Timers Selection” chapter. All of the modules may be active at once and may share the same timer resource if they are configured to operate in the same mode (Capture/Compare or PWM) at the same time. 28.1.2 Open-Drain Output Option When operating in Output mode (the Compare or PWM modes), the drivers for the CCPx pins can be optionally configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor and allows the output to communicate with external circuits without the need for additional level shifters. 28.2 Capture Mode Capture mode makes use of the 16-bit odd numbered timer resources (Timer1, Timer3, etc.). When an event occurs on the capture source, the 16-bit CCPRx register captures and stores the 16-bit value of the TMRx register. An event is defined as one of the following and is configured by the MODE bits: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 421 PIC18F06/16Q41 CCP - Capture/Compare/PWM Module • • • • • Every falling edge of CCPx input Every rising edge of CCPx input Every 4th rising edge of CCPx input Every 16th rising edge of CCPx input Every edge of CCPx input (rising or falling) When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRx register is read, the old captured value is overwritten by the new captured value. The following figure shows a simplified diagram of the capture operation. Important:  If an event occurs during a 2-byte read, the high and low-byte data will be from different events. It is recommended while reading the CCPRx register pair to either disable the module or read the register pair twice for data integrity. Figure 28-1. Capture Mode Operation Block Diagram Rev. 10-000158E 3/11/2019 RxyPPS CCPx PPS CTS TRIS CCPRx Capture Trigger Sources See CCPxCAP register Prescaler 1,4,16 and Edge Detect set CCPxIF 16 16 CCPx PPS MODE TMR1 CCPxPPS 28.2.1 Capture Sources The capture source is selected with the CTS bits. In Capture mode, the CCPx pin must be configured as an input by setting the associated TRIS control bit. Important:  If the CCPx pin is configured as an output, a write to the port can cause a capture event. 28.2.2 Timer1 Mode for Capture Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. See the “TMR1 - Timer1 Module with Gate Control” chapter for more information on configuring Timer1. 28.2.3 Software Interrupt Mode When the Capture mode is changed, a false capture interrupt may be generated. The user will keep the CCPxIE Interrupt Enable bit of the PIEx register clear to avoid false interrupts. Additionally, the user will clear the CCPxIF Interrupt Flag bit of the PIRx register following any change in Operating mode. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 422 PIC18F06/16Q41 CCP - Capture/Compare/PWM Module Important:  Clocking Timer1 from the system clock (FOSC) must not be used in Capture mode. For Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. 28.2.4 CCP Prescaler There are four prescaler settings specified by the MODE bits. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler. The example below demonstrates the code to perform this function. Example 28-1. Changing between Capture Prescalers BANKSEL CLRF MOVLW MOVWF 28.2.5 CCP1CON CCP1CON NEW_CAPT_PS CCP1CON ;only needed when CCP1CON is not in ACCESS space ;Turn CCP module off ;CCP ON and Prescaler select → W ;Load CCP1CON with this value Capture During Sleep Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. 28.3 Compare Mode The Compare mode function described in this section is available and identical for all CCP modules. Compare mode makes use of the 16-bit odd numbered Timer resources (Timer1, Timer3, etc.). The 16-bit value of the CCPRx register is constantly compared against the 16-bit value of the TMRx register. When a match occurs, one of the following events can occur: • • • • • • Toggle the CCPx output and clear TMRx Toggle the CCPx output without clearing TMRx Set the CCPx output Clear the CCPx output Generate a Pulse output Generate a Pulse output and clear TMRx The action on the pin is based on the value of the MODE control bits. All Compare modes can generate an interrupt. When MODE = ‘b0001 or ‘b1011, the CCP resets the TMRx register. The following figure shows a simplified diagram of the compare operation. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 423 PIC18F06/16Q41 CCP - Capture/Compare/PWM Module Figure 28-2. Compare Mode Operation Block Diagram MODE Auto-conversion Trigger CCPRx CCPx PPS Q S R Output Logic RxyPPS Comparator TMR1 TRIS Set CCPxIF Interrupt Flag 28.3.1 CCPx Pin Configuration The CCPx pin must be configured as an output in software by clearing the associated TRIS bit and defining the appropriate output pin through the RxyPPS registers. See the “PPS - Peripheral Pin Select Module” section for more details. The CCP output can also be used as an input for other peripherals. Important:  Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. 28.3.2 Timer1 Mode for Compare In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. See the “TMR1 - Timer1 Module with Gate Control” section for more information on configuring Timer1. Important:  Clocking Timer1 from the system clock (FOSC) must not be used in Compare mode. For Compare mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. 28.3.3 Compare During Sleep Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep, unless the timer is running. The device will wake on interrupt (if enabled). 28.4 PWM Overview Pulse-Width Modulation (PWM) is a scheme that controls power to a load by switching quickly between fully ON and fully OFF states. The PWM signal resembles a square wave where the high portion of the signal is considered the ON state and the low portion of the signal is considered the OFF state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of ON and OFF time combined. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 424 PIC18F06/16Q41 CCP - Capture/Compare/PWM Module PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the power applied to the load. The term duty cycle describes the proportion of the ON time to the OFF time and is expressed in percentages, where 0% is fully OFF and 100% is fully ON. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. The figure below shows a typical waveform of the PWM signal. Figure 28-3. CCP PWM Output Signal Period Pulse Width TMR2 = PR2 TMR2 = CCPRx TMR2 = 0 28.4.1 Standard PWM Operation The standard PWM function described in this section is available and identical for all CCP modules. It generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to ten bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • • • • Even numbered TxPR registers (T2PR, T4PR, etc.) Even numbered TxCON registers (T2CON, T4CON, etc.) 16-bit CCPRx registers CCPxCON registers It is required to have FOSC/4 as the clock input to TxTMR for correct PWM operation. The following figure shows a simplified block diagram of the PWM operation. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 425 PIC18F06/16Q41 CCP - Capture/Compare/PWM Module Figure 28-4. Simplified PWM Block Diagram Rev. 10-000 157C 2/20/201 9 Duty cycle registers CCPRxH CCPRxL CCPx_out 10-bit Latch(2) (Not accessible by user) Comparator R S Q PPS RxyPPS TMR2 Module R TMR2 to peripherals set CCPIF CCPx TRIS Control (1) ERS logic Comparator CCPx_pset PR2 Notes: 1. An 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to create 10-bit time base. 2. The alignment of the 10 bits from the CCPR register is determined by the CCPxFMT bit. Important:  The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 28.4.2 Setup for PWM Operation The following steps illustrate how to configure the CCP module for standard PWM operation: 1. 2. 3. 4. 5. 6. Select the desired output pin with the RxyPPS control to select CCPx as the source. Disable the selected pin output driver by setting the associated TRIS bit. The output will be enabled later at the end of the PWM setup. Load the selected timer TxPR period register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRx register with the PWM duty cycle value and configure the FMT bit to set the proper register alignment. Configure and start the selected timer: – Clear the TMRxIF Interrupt Flag bit of the PIRx register. See the Note below. – Select the timer clock source to be as FOSC/4. This is required for correct operation of the PWM module. – Configure the TxCKPS bits of the TxCON register with the desired timer prescale value. – Enable the timer by setting the TxON bit. Enable the PWM output: – Wait until the timer overflows and the TMRxIF bit of the PIRx register is set. See the Note below. – Enable the CCPx pin output driver by clearing the associated TRIS bit. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 426 PIC18F06/16Q41 CCP - Capture/Compare/PWM Module Important:  To send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. 28.4.3 Timer2 Timer Resource The PWM Standard mode makes use of the 8-bit Timer2 timer resources to specify the PWM period. 28.4.4 PWM Period The PWM period is specified by the T2PR register of Timer2. The PWM period can be calculated using the formula in the equation below. Equation 28-1. PWM Period PWM Period = T2PR + 1 • 4 • TOSC • TMR2 Prescale Value where TOSC = 1/FOSC When T2TMR is equal to T2PR, the following three events occur on the next increment event: • • • T2TMR is cleared The CCPx pin is set (Exception: If the PWM duty cycle = 0%, the pin will not be set) The PWM duty cycle is transferred from the CCPRx register into a 10-bit buffer Important:  The Timer postscaler (see the “Timer2 Interrupt” section) is not used in the determination of the PWM frequency. 28.4.5 PWM Duty Cycle The PWM duty cycle is specified by writing a 10-bit value to the CCPRx register. The alignment of the 10-bit value is determined by the FMT bit (see Figure 28-5). The CCPRx register can be written to at any time. However, the duty cycle value is not latched onto the 10-bit buffer until after a match between T2PR and T2TMR. The equations below are used to calculate the PWM pulse width and the PWM duty cycle ratio. Figure 28-5. PWM 10-Bit Alignment CCP RxH CCP RxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 FMT = 1 FMT = 0 CCP RxH CCP RxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 10-bit Duty Cycle 9 8 7 6 5 4 3 2 1 0 Equation 28-2. Pulse Width Pulse Widtℎ = CCPRxH: CCPRxL register value • TOSC • TMR2 Prescale Value Equation 28-3. Duty Cycle CCPRxH: CCPRxL register value DutyCycleRatio = 4 T2PR + 1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 427 PIC18F06/16Q41 CCP - Capture/Compare/PWM Module The CCPRx register is used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer T2TMR register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPRx register, then the CCPx pin is cleared (see Figure 28-4). 28.4.6 PWM Resolution The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when T2PR is 0xFF. The resolution is a function of the T2PR register value, as shown below. Equation 28-4. PWM Resolution log 4 T2PR + 1 Resolution = bits log 2 Important:  If the pulse-width value is greater than the period, the assigned PWM pin(s) will remain unchanged. Table 28-2. Example PWM Frequencies and Resolutions (FOSC = 20 MHz) PWM Frequency Timer Prescale T2PR Value Maximum Resolution (bits) 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 Table 28-3. Example PWM Frequencies and Resolutions (FOSC = 8 MHz) PWM Frequency Timer Prescale T2PR Value Maximum Resolution (bits) 28.4.7 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Operation in Sleep Mode In Sleep mode, the T2TMR register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, T2TMR will continue from the previous state. 28.4.8 Changes in System Clock Frequency The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See the “OSC - Oscillator Module (with Fail-Safe Clock Monitor)” chapter for additional details. 28.4.9 Effects of Reset Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 28.5 Register Definitions: CCP Control Long bit name prefixes for the CCP peripherals are shown in the following table. Refer to the “Long Bit Names” section in the “Register and Bit Naming Conventions” chapter for more information. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 428 PIC18F06/16Q41 CCP - Capture/Compare/PWM Module Table 28-4. CCP Long Bit Name Prefixes Peripheral Bit Name Prefix CCP1 CCP1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 429 PIC18F06/16Q41 CCP - Capture/Compare/PWM Module 28.5.1 CCPxCON Name:  Address:  CCPxCON 0x0342 CCP Control Register Bit 7 EN R/W 0 Access Reset 6 5 OUT R x 4 FMT R/W 0 3 2 1 0 R/W 0 R/W 0 MODE[3:0] R/W 0 R/W 0 Bit 7 – EN CCP Module Enable Value Description 1 CCP is enabled 0 CCP is disabled Bit 5 – OUT CCP Output Data (read-only) Bit 4 – FMT CCPxRH:L Value Alignment (PWM mode) Value Condition x Capture mode x Compare mode 1 PWM mode 0 PWM mode Description Not used Not used Left aligned format Right aligned format Bits 3:0 – MODE[3:0] CCP Mode Select Table 28-5. CCPx Mode Select MODE Value Operating Mode 11xx 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 PWM Compare Capture Compare Operation PWM operation Pulse output; clear TMR1(2) Pulse output Clear output(1) Set output(1) Every 16th rising edge of CCPx input Every 4th rising edge of CCPx input Every rising edge of CCPx input Every falling edge of CCPx input Every edge of CCPx input Toggle output Toggle output; clear TMR1(2) Disabled Set CCPxIF Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes — Notes:  1. The set and clear operations of the Compare mode are reset by setting MODE = ‘b0000 or EN = 0. 2. When MODE = ‘b0001 or ‘b1011, then the timer associated with the CCP module is cleared. TMR1 is the default selection for the CCP module, so it is used for indication purposes only. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 430 PIC18F06/16Q41 CCP - Capture/Compare/PWM Module 28.5.2 CCPxCAP Name:  Address:  CCPxCAP 0x343 Capture Trigger Input Selection Register Bit 7 6 5 4 3 Access Reset 2 R/W 0 1 CTS[2:0] R/W 0 0 R/W 0 Bits 2:0 – CTS[2:0] Capture Trigger Input Selection Table 28-6. Capture Trigger Sources CTS Value 111 110 101 100 011 010 001 000 © 2020-2021 Microchip Technology Inc. and its subsidiaries Source CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT IOC Interrupt CMP2_OUT CMP1_OUT Pin selected by CCPxPPS Preliminary Datasheet DS40002214E-page 431 PIC18F06/16Q41 CCP - Capture/Compare/PWM Module 28.5.3 CCPRx Name:  Address:  CCPRx 0x340 Capture/Compare/Pulse-Width Register Bit 15 14 13 12 11 10 9 8 R/W x R/W x R/W x R/W x 3 2 1 0 R/W x R/W x R/W x R/W x CCPR[15:8] Access Reset Bit R/W x R/W x R/W x R/W x 7 6 5 4 CCPR[7:0] Access Reset R/W x R/W x R/W x R/W x Bits 15:0 – CCPR[15:0] Capture/Compare/Pulse-Width Reset States: POR/BOR = xxxxxxxxxxxxxxxx All other Resets = uuuuuuuuuuuuuuuu Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • When MODE = Capture or Compare – CCPRxH: Accesses the high byte CCPR[15:8] – CCPRxL: Accesses the low byte CCPR[7:0] • When MODE = PWM and FMT = 0 • – CCPRx[15:10]: Not used – CCPRxH[1:0]: Accesses the two Most Significant bits CCPR[9:8] – CCPRxL: Accesses the eight Least Significant bits CCPR[7:0] When MODE = PWM and FMT = 1 – CCPRxH: Accesses the eight Most Significant bits CCPR[9:2] – CCPRxL[7:6]: Accesses the two Least Significant bits CCPR[1:0] – CCPRx[5:0]: Not used © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 432 PIC18F06/16Q41 CCP - Capture/Compare/PWM Module 28.6 Register Summary - CCP Control Address Name 0x00 ... 0x033F Reserved 0x0340 CCPRx 0x0342 0x0343 CCP1CON CCPxCAP Bit Pos. 7:0 15:8 7:0 7:0 7 EN © 2020-2021 Microchip Technology Inc. and its subsidiaries 6 5 OUT 4 CCPR[7:0] CCPR[15:8] FMT Preliminary Datasheet 3 2 1 0 MODE[3:0] CTS[2:0] DS40002214E-page 433 PIC18F06/16Q41 Capture, Compare, and PWM Timers Selection 29. Capture, Compare, and PWM Timers Selection Each of these modules has an independent timer selection which can be accessed using the timer selection register. The default timer selection is Timer1 for capture or compare functions and Timer2 for PWM functions. 29.1 Register Definitions: Capture, Compare, and PWM Timers Selection © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 434 PIC18F06/16Q41 Capture, Compare, and PWM Timers Selection 29.1.1 CCPTMRS0 Name:  Address:  CCPTMRS0 0x34C CCP Timers Selection Register Bit 7 6 Access Reset 5 4 C3TSEL[1:0] R/W R/W 0 1 3 2 C2TSEL[1:0] R/W R/W 0 1 1 0 C1TSEL[1:0] R/W R/W 0 1 Bits 0:1, 2:3, 4:5 – CnTSEL CCPn Timer Selection CnTSEL Value 11 10 01 00 © 2020-2021 Microchip Technology Inc. and its subsidiaries Capture/Compare PWM Reserved Timer3 Timer1 Timer4 Timer2 Reserved Preliminary Datasheet DS40002214E-page 435 PIC18F06/16Q41 Capture, Compare, and PWM Timers Selection 29.2 Address 0x00 ... 0x034B 0x034C Register Summary - Capture, Compare, and PWM Timers Selection Name Bit Pos. 7 6 5 4 3 2 1 0 Reserved CCPTMRS0 7:0 © 2020-2021 Microchip Technology Inc. and its subsidiaries C3TSEL[1:0] Preliminary Datasheet C2TSEL[1:0] C1TSEL[1:0] DS40002214E-page 436 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30. PWM - Pulse-Width Modulator with Compare This module is a 16-bit Pulse-Width Modulator (PWM) with a compare feature and multiple outputs. The outputs are grouped in slices where each slice has two outputs. There can be up to four slices in each PWM module. The EN bit enables the PWM operation for all slices simultaneously. The prescale counter, postscale counter, and all internal logic is held in Reset while the EN bit is low. Features of this module include the following: • Five main operating modes: – Left Aligned – Right Aligned – Center-Aligned – Variable Aligned – Compare • Pulsed • Toggled • Push-pull operation (available in Left and Right Aligned modes only) • Independent 16-bit period timer • Programmable clock sources • Programmable trigger sources for synchronous duty cycle and period changes • Programmable synchronous/asynchronous Reset sources • Programmable Reset source polarity control • Programmable PWM output polarity control • Up to four two-output slices per module Block diagrams of each PWM mode are shown in their respective sections. 30.1 Output Slices A PWM module can have up to four output slices. An output slice consists of two PWM outputs, PWMx_SaP1_out and PWMx_SaP2_out. Both share the same operating mode. However, other slices may operate in a different mode. PWMx_SaP1_out and PWMx_SaP2_out have independent duty cycles which are set with the respective P1 and P2 parameter registers. 30.1.1 Output Polarity The polarity for the PWMx_SaP1_out and PWMx_SaP2_out is controlled with the respective POL1 and POL2 bits. Setting the polarity bit inverts the output Active state to low true. Toggling the polarity bit toggles the output whether or not the PWM module is enabled. 30.1.2 Operating Modes Each output slice can operate in one of six modes selected with the MODE bits. The Left and Right Aligned modes can also be operated in Push-Pull mode by setting the PPEN bit. The following sections provide more details on each mode, including block diagrams. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 437 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.1.2.1 Left Aligned Mode In Left Aligned mode, the active part of the duty cycle is at the beginning of the period. The outputs start active and stay active for the number of prescaled PWM clock periods specified by the P1 and P2 parameter registers, then go inactive for the remainder of the period. Block and timing diagrams follow. Figure 30-1. Left-Aligned Block Diagram P1 Buffer Duty Cycle Reset PR Buffer PWMx_SaP1_out Q Set Clock Sources Prescale PWMx_clk Period Event Timer Set PWMxCLK PWMx_SaP2_out Q Reset Duty Cycle P2 Buffer Figure 30-2. Left-Aligned Timing Diagram PWMx_clk PWMx_timer 0 1 2 3 4 5 0 1 2 3 4 5 0 1 SaP1_out SaP2_out SaP1IF SaP2IF Reset by software PWMxPIF PWMxIF Note: MODE = ‘b000, PR = 5, P1 = 4, P2 = 2. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 438 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.1.2.2 Right Aligned Mode In Right Aligned mode, the active part of the duty cycle is at the end of the period. The outputs start in the Inactive state and then go Active the number of prescaled PWM clock periods specified by the P1 and P2 parameter registers before the end of the period. Block and timing diagrams follow. Figure 30-3. Right-Aligned Block Diagram P1 Buffer Duty Cycle Set PR Buffer PWMx_SaP1_out Q Reset Clock Sources Prescale PWMx_clk Period Event Timer Reset PWMxCLK PWMx_SaP2_out Q Set Duty Cycle P2 Buffer Figure 30-4. Right-Aligned Timing Diagram PWMx_clk PWMx_timer 0 1 2 3 4 5 0 1 2 3 4 5 0 1 SaP1_out SaP2_out SaP2IF SaP1IF Reset by software Note: MODE = ‘b001, PR = 5, P1 = 4, P2 = 2. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 439 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.1.2.3 Center-Aligned Mode In Center-Aligned mode, the active duty cycle is centered in the period. The period for this mode is twice that of other modes, as shown in the following equation. Equation 30-1. Center-Aligned Period PR + 1 × 2 Period = FPWMx_clk The parameter register specifies the number of PWM clock periods that the output goes Active before the period center. The output goes inactive the same number of prescaled PWM clock periods after the period center. Block and timing diagrams follow. Figure 30-5. Center-Aligned Block Diagram P1 Buffer Duty Cycle Reset PR Buffer PWMx_SaP1_out Q Set Clock Sources Prescale PWMx_clk Period Event Timer Set PWMxCLK PWMx_SaP2_out Q Reset Duty Cycle P2 Buffer Figure 30-6. Center-Aligned Timing Diagram PWMx_clk PWMx_timer 0 1 2 3 4 5 0 1 2 3 4 5 0 1 SaP1_out SaP2_out SaP1IF Reset by software SaP2IF Note: MODE = ‘b010, PR = 5, P1 = 4, P2 = 2. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 440 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.1.2.4 Variable Alignment Mode In Variable Alignment mode, the active part of the duty cycle starts when the parameter 1 value (P1) matches the timer and ends when the parameter 2 value (P2) matches the timer. Both outputs are identical because both parameter values are used for the same duty cycle. Block and timing diagrams follow. Figure 30-7. Variable Alignment Block Diagram P1 Buffer = PR Buffer Set PWMx_SaP1_out Q Clock Sources Prescale PWMx_clk Reset Period Event Timer PWMxCLK PWMx_SaP2_out = P2 Buffer Figure 30-8. Variable Alignment Timing Diagram PWMx_clk PWMx_timer 0 1 2 3 4 5 0 1 2 3 4 5 0 1 SaP1_out SaP2_out SaP1IF Reset by software SaP1IF PWMxPIF Note: MODE = ‘b011, PR = 5, P1 = 4, P2 = 2. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 441 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.1.2.5 Compare Modes In the Compare modes, the PWM timer is compared to the P1 and P2 parameter values. When a match occurs, the output is either pulsed or toggled. In Pulsed Compare mode, the duty cycle is always one prescaled PWM clock period. In Toggle Compare mode, the duty cycle is always one full PWM period. Refer to the following sections for more details. 30.1.2.5.1 Pulsed Compare Mode In Pulsed Compare mode, the duty cycle is one prescaled PWM clock period that starts when the timer matches the parameter value and ends one prescaled PWM clock period later. The outputs start in the Inactive state and then go Active during the duty cycle. Block and timing diagrams follow. Figure 30-9. Pulsed Compare Block Diagram P1 Buffer = Pulse Clock Sources Prescale PWMx_clk Period Event Timer PWMx_SaP1_out Q PR Buffer PWMx_SaP2_out Q Pulse PWMxCLK = P2 Buffer Figure 30-10. Pulsed Compare Timing Diagram PWMx_clk PWMx_timer 0 1 2 3 4 5 0 1 2 3 4 5 0 1 SaP1_out SaP2_out SaP1IF Reset by software SaP1IF PWMxPIF Note: MODE = ‘b100, PR = 5, P1 = 4, P2 = 2. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 442 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.1.2.5.2 Toggled Compare In Toggled Compare mode, the duty cycle is alternating full PWM periods. The output goes Active when the PWM timer matches the P1 or P2 parameter value and goes Inactive in the next period at the same match point. Block and timing diagrams follow. Figure 30-11. Toggled Compare Block Diagram P1 Buffer = Toggle Clock Sources Prescale PWMx_clk Period Event Timer PWMx_SaP1_out Q PR Buffer PWMx_SaP2_out Q Toggle PWMxCLK = P2 Buffer Figure 30-12. Toggled Compare Timing Diagram PWMx_clk PWMx_timer 0 1 2 3 4 5 0 1 2 3 4 5 0 1 SaP1_out SaP2_out SaP1IF Reset by software SaP1IF PWMxPIF Note: MODE = ‘b101, PR = 5, P1 = 4, P2 = 2. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 443 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.1.3 Push-Pull Mode The Push-Pull mode is enabled by setting the PPEN bit. Push-Pull operates only in the Left Aligned and Right Aligned modes. In the Push-Pull mode, the outputs are Active every other PWM period. PWMx_SaP1_out is Active when the PWMx_SaP2_out is not and the PWMx_SaP2_out is Active when the PWMx_SaP1_out is not. When the parameter value (P1 or P2) is greater than the period value (PR), then the corresponding output is Active for one full PWM period. The following figures illustrate timing examples of Left and Right Aligned Push-Pull modes. Figure 30-13. Left Aligned Push-Pull Mode Timing Diagram PWMx_clk PWMx_timer 0 1 2 3 4 5 0 1 2 3 4 5 0 1 SaP1_out SaP2_out SaP1IF SaP2IF Reset by software Note: MODE = ‘b000, PR = 5, P1 = 4, P2 = 2, PPEN = 1. Figure 30-14. Right Aligned Push-Pull Mode Timing Diagram PWMx_clk PWMx_timer 0 1 2 3 4 5 0 1 2 3 4 5 0 1 SaP1_out SaP2_out SaP1IF Reset by software SaP2IF Note: MODE = ‘b001, PR = 5, P1 = 6, P2 = 2, PPEN = 1. 30.2 Period Timer All slices in a PWM instance operate with the same period. The value written to the PWMxPR register is one less than the number of prescaled PWM clock periods (PWM_clk) in the PWM period. The PWMxPR register is double-buffered. When the PWM is operating, writes to the PWMxPR register are transferred to the period buffer only after the LD bit is set or an external load event occurs. The transfer occurs at the next period Reset event. If the LD bit is set less than three PWM clock periods before the end of the period, then the transfer may be one full period later. Loading the buffers of multiple PWM instances can be coordinated using the PWMLOAD register. See the Buffered Period and Parameter Registers section for more details. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 444 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.3 Clock Sources The time base for the PWM period prescaler is selected with the CLK bits. Changes take effect immediately when written. Clearing the EN bit before making clock source changes is recommended to avoid unexpected behavior. 30.3.1 Clock Prescaler The PWM clock frequency can be reduced with the clock prescaler. There are 256 prescale selections from 1:1 to 1:256. The CPRE bits select the prescale value. Changes to the prescale value take effect immediately. Clearing the EN bit before making prescaler changes is recommended to avoid unexpected behavior. The prescale counter is reset when the EN bit is cleared. 30.4 External Period Resets The period timer can be reset and held at zero by a logic level from one of various sources. The Reset event also resets the postscaler counter. The resetting source is selected with the ERS bits. The Reset can be configured with the ERSNOW bit to occur on either the next PWM clock or the next PWM period Reset event. When the ERSNOW bit is set, then the Reset will occur on the next PWM clock. When the ERSNOW bit is cleared, then the Reset will be held off until the period normally resets at the end of the period. The difference between a normal period Reset and an ERS Reset is that once the timer is reset, it is held at zero until the ERS signal goes false. The following timing diagrams illustrate the two types of external Reset. Figure 30-15. Right Aligned Mode with ERSNOW = 1 PWMx_clk PWMx_timer 0 1 2 3 4 5 0 1 2 3 0 0 0 1 5 0 0 0 1 2 3 4 5 PWMx_ers SaP1_out SaP2_out Note: PR = 5, P1 = 4, P2 = 2. Figure 30-16. Left Aligned Mode with ERSNOW = 0 PWMx_clk PWMx_timer 0 1 2 3 4 PWMx_ers SaP1_out SaP2_out Note: PR = 5, P1 = 4, P2 = 2. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 445 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.5 Buffered Period and Parameter Registers The PWMxPR, PWMxSaP1 and PWMxSaP2 registers are double-buffered. The PWM module operates on the buffered copies. The values in all these registers are copied to the buffer registers when the PWM module is enabled. Changes to the PWMxPR, PWMxSaP1 and PWMxSaP2 registers do not affect the buffer registers while the PWM is operating until either software sets the LD bit or an external load event occurs. For all operating modes except Center-Aligned, the values are copied to the buffer registers when the PWM timer is reloaded at the end of the period in which the load request occurred. In the Center-Aligned mode, the buffer update occurs on every other period Reset event because one full center-aligned period uses two period cycles. Load requests occurring three or less clocks before the end of the period may not be serviced until the following period. A list of external load trigger sources is shown in the PWMxLDS register. Software can set the LD bits of multiple PWM instances simultaneously with the PWMLOAD register. Important:  No changes are allowed after the LD bit is set until after the LD bit is cleared by hardware. Unexpected behavior may result if the LD bit is cleared by software. 30.6 Synchronizing Multiple PWMs To synchronize multiple PWMs, the PWMEN register is used to enable selected PWMs simultaneously. The bits in the PWMEN register are mirror copies of the EN bit of every PWM in the device. Setting or clearing the EN bits in the PWMEN register enables or disables all the corresponding PWMs simultaneously. 30.7 Interrupts Each PWM instance has a period interrupt and interrupts associated with the mode and parameter settings. 30.7.1 Period Interrupt The period interrupt occurs when the PWMx timer value matches the PR value, thereby also resetting the PWMx timer. Refer to Figure 30-2 for a timing example. The period interrupt is indicated with the PWMxPIF flag bit in one of the PIR registers and is set whether or not the interrupt is enabled. This flag must be reset by software. The PWMxPIF interrupt is enabled with the PWMxPIE bit in the corresponding PIE register. 30.7.1.1 Period Interrupt Postscaler The frequency of the period interrupt events can be reduced with the period interrupt postscaler. A postscaler counter suppresses period interrupts until the postscale count is reached. Only one PWM period interrupt is generated for every postscale counts. There are 256 postscale selections from 1:1 to 1:256. The PIPOS bits select the postscale value. Changes to the postscale value take effect immediately. Clearing the EN bit before making postscaler changes is recommended to avoid unexpected behavior. The postscale counter is reset when the EN bit is cleared. 30.7.2 Parameter Interrupts The P1 and P2 parameters in each slice have interrupts that occur depending on the selected mode. The individual parameter interrupts are indicated in the PWMxGIR register and enabled by the corresponding bits in the PWMxGIE register. A timing example is shown in Figure 30-2. Refer to the timing diagrams of each of the other modes for more details. All the enabled PWMxGIR interrupts of one PMW instance are OR’d together into the PWMxIF bit in one of the PIR registers. The PWMxIF bit is read-only. When any of the PWMxGIR bits are set then the PWMxIF bit is true. All PWMxGIF flags must be reset to clear the PWMxIF bit. The PWMxIF interrupt is enabled with the PWMxIE bit in the corresponding PIE register. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 446 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.8 Operation During Sleep The PWM module operates in Sleep only if the PWM clock is Active. Some internal clock sources are automatically enabled to operate in Sleep when a peripheral using them is enabled. Those clock sources are identified in the clock source table shown in the PWMxCLK clock source selection register. 30.9 Register Definitions: PWM Control Long bit name prefixes for the PWM peripherals are shown in the table below. Refer to the “Long Bit Names” section in the “Register and Bit Naming Conventions” chapter for more information. Table 30-1. PWM Long Bit Name Prefixes Peripheral Bit Name Prefix PWM1 PWM1 PWM2 PWM2 PWM3 PWM3 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 447 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.9.1 PWMxERS Name:  Address:  PWMxERS 0x460,0x46F,0x47E PWMx External Reset Source Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 ERS[3:0] Access Reset R/W 0 R/W 0 Bits 3:0 – ERS[3:0] External Reset Source Select ERS 1111 - 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 PWM1 PWM3S1P2_OUT PWM3S1P1_OUT PWM2S1P2_OUT PWM2S1P1_OUT Reserved Reserved PWM1ERSPPS © 2020-2021 Microchip Technology Inc. and its subsidiaries Reset Source PWM2 Reserved (ERS Disabled) CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT PWM3S1P2_OUT PWM3S1P1_OUT Reserved Reserved PWM1S1P2_OUT PWM1S1P1_OUT PWM2ERSPPS ERS Disabled Preliminary Datasheet PWM3 Reserved Reserved PWM2S1P2_OUT PWM2S1P1_OUT PWM1S1P2_OUT PWM1S1P1_OUT PWM3ERSPPS DS40002214E-page 448 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.9.2 PWMxCLK Name:  Address:  PWMxCLK 0x461,0x470,0x47F PWMx Clock Source Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 CLK[3:0] Access Reset R/W 0 R/W 0 Bits 3:0 – CLK[3:0] PWM Clock Source Select CLK 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Source Operates in Sleep Reserved N/A CLC4_OUT Yes(1) CLC3_OUT Yes(1) CLC2_OUT Yes(1) CLC1_OUT Yes(1) NCO1_OUT Yes(1) CLKREF Yes(1) EXTOSC Yes SOSC Yes MFINTOSC (32 kHz) Yes MFINTOSC (500 kHz) Yes LFINTOSC Yes HFINTOSC Yes FOSC No PWMIN1PPS Yes(1) PWMIN0PPS Yes(1) Note:  Operation during Sleep is possible if the clock supplying the source peripheral operates in Sleep. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 449 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.9.3 PWMxLDS Name:  Address:  PWMxLDS 0x462,0x471,0x480 PWMx Auto-load Trigger Source Select Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 LDS[3:0] Access Reset R/W 0 R/W 0 Bits 3:0 – LDS[3:0] Auto-load Trigger Source Select LDS 1111 - 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 © 2020-2021 Microchip Technology Inc. and its subsidiaries Source Auto-load Disabled DMA4_Destination_Count_Done DMA3_Destination_Count_Done DMA2_Destination_Count_Done DMA1_Destination_Count_Done CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT PWMIN1PPS PWMIN0PPS Auto-load Disabled Preliminary Datasheet DS40002214E-page 450 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.9.4 PWMxPR Name:  Address:  PWMxPR 0x463,0x472,0x481 PWMx Period Register Determines the PWMx period Bit 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 PR[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 PR[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 15:0 – PR[15:0] PWM Period Number of PWM clocks periods in the PWM period Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • PWMxPRH: Accesses the high byte PR[15:8] • PWMxPRL: Accesses the low byte PR[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 451 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.9.5 PWMxCPRE Name:  Address:  PWMxCPRE 0x465,0x474,0x483 PWMx Clock Prescaler Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 CPRE[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – CPRE[7:0] PWM Clock Prescale Value Value Description n PWM clock is prescaled by n+1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 452 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.9.6 PWMxPIPOS Name:  Address:  PWMxPIPOS 0x466,0x475,0x484 PWMx Period Interrupt Postscaler Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 PIPOS[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – PIPOS[7:0] Period Interrupt Postscale Value Value Description n Period interrupt occurs after n+1 period events © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 453 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.9.7 PWMxGIR Name:  Address:  PWMxGIR 0x467,0x476,0x485 PWMx Interrupt Register Bit 7 6 5 4 3 Access Reset 2 1 S1P2 R/W/HS 0 0 S1P1 R/W/HS 0 Bit 1 – SaP2 Slice “a” Parameter 2 Interrupt Flag Value Mode Description 1 Variable Aligned or Compare Compare match between P2 and PWM counter has occurred 1 Center-Aligned PWMx_SaP2_out has changed 1 Right Aligned Left edge of PWMx_SaP2_out pulse has occurred 1 Left Aligned Right edge of PWMx_SaP2_out pulse has occurred 0 All Interrupt event has not occurred Bit 0 – SaP1 Slice “a” Parameter 1 Interrupt Flag Value Mode Description 1 Variable Aligned or Compare Compare match between P1 and PWM counter has occurred 1 Center-Aligned PWMx_SaP1_out has changed 1 Right Aligned Left edge of PWMx_SaP1_out pulse has occurred 1 Left Aligned Right edge of PWMx_SaP1_out pulse has occurred 0 All Interrupt event has not occurred © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 454 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.9.8 PWMxGIE Name:  Address:  PWMxGIE 0x468,0x477,0x486 PWMx Interrupt Enable Register Bit 7 6 5 4 3 Access Reset 2 1 S1P2 R/W 0 0 S1P1 R/W 0 Bit 1 – SaP2 Slice “a” Parameter 2 Interrupt Enable Value Description 1 Slice “a” Parameter 2 match interrupt is enabled 0 Slice “a” Parameter 2 match interrupt is not enabled Bit 0 – SaP1 Slice “a” Parameter 1 Interrupt Enable Value Description 1 Slice “a” Parameter 1 match interrupt is enabled 0 Slice “a” Parameter 1 match interrupt is not enabled © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 455 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.9.9 PWMxCON Name:  Address:  PWMxCON 0x469,0x478,0x487 PWM Control Register Bit Access Reset 7 EN R/W 0 6 5 4 3 2 LD R/W/HC 0 1 ERSPOL R/W 0 0 ERSNOW R/W 0 Bit 7 – EN PWM Module Enable Value Description 1 PWM module is enabled 0 PWM module is disabled. The prescaler, postscaler, and all internal logic is reset. Outputs go to their default states. Register values remain unchanged. Bit 2 – LD Reload Registers Reload the period and duty cycle registers on the next period event Value Description 1 Reload PR/P1/P2 registers 0 Reload not enabled or reload complete Bit 1 – ERSPOL External Reset Polarity Select Value Description 1 External Reset input is active-low 0 External Reset input is active-high Bit 0 – ERSNOW External Reset Mode Select Determines when an external Reset event takes effect. Value Description 1 Stop counter on the next PWM clock. Output goes to the Inactive state. 0 Stop counter at the end of the period. Output goes to the Inactive state. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 456 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.9.10 PWMxSaCFG Name:  PWMxSaCFG PWM Slice “a” Configuration Register(1) Bit Access Reset 7 POL2 R/W 0 6 POL1 R/W 0 5 4 3 PPEN R/W 0 2 R/W 0 1 MODE[2:0] R/W 0 0 R/W 0 Bit 7 – POL2 PWM Slice “a” Parameter 2 Output Polarity Value Description 1 PWMx_SaP2_out is low true 0 PWMx_SaP2_out is high true Bit 6 – POL1 PWM Slice “a” Parameter 1 Output Polarity Value Description 1 PWMx_SaP1_out is low true 0 PWMx_SaP1_out is high true Bit 3 – PPEN Push-Pull Mode Enable Each period the output alternates between PWMx_SaP1_out and PWMx_SaP2_out. Only Left and Right Aligned modes are supported. Other modes may exhibit unexpected results. Value Description 1 PWMx Slice “a” Push-Pull mode is enabled 0 PWMx Slice “a” Push-Pull mode is not enabled Bits 2:0 – MODE[2:0] PWM Module Slice “a” Operating Mode Select Selects operating mode for both PWMx_SaP1_out and PWMx_SaP2_out Value Description 11x Reserved. Outputs go to Reset state. 101 Compare mode: Toggle PWMx_SaP1_out and PWMx_SaP2_out on PWM timer match with corresponding parameter register 100 Compare mode: Set PWMx_SaP1_out and PWMx_SaP2_out high on PWM timer match with corresponding parameter register 011 Variable Aligned mode 010 Center-Aligned mode 001 Right Aligned mode 000 Left Aligned mode Note:  1. Changes to this register must be done only when the EN bit is cleared. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 457 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.9.11 PWMxSaP1 Name:  PWMxSaP1 PWM Slice “a” Parameter 1 Register Determines the active period of slice “a”, parameter 1 output Bit 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 P1[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 P1[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 15:0 – P1[15:0] Parameter 1 Value Value Mode Description n Compare Compare match event occurs when PWMx timer = n (Refer to MODE selections) n Variable Aligned PWMx_SaP1_out and PWMx_SaP2 both go high when PWMx timer = n n Center-Aligned PWMx_SaP1_out is high 2*n PWMx clock periods centered around PWMx period event n Right Aligned PWMx_SaP1_out is high n PWMx clock periods at end of PWMx period n Left Aligned PWMx_SaP1_out is high n PWMx clock periods at beginning of PWMx period Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • PWMxSaP1H: Accesses the high byte P1[15:8] • PWMxSaP1L: Accesses the low byte P1[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 458 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.9.12 PWMxSaP2 Name:  PWMxSaP2 PWM Slice “a” Parameter 2 Register Determines the active period of slice “a”, parameter 2 output Bit 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 P2[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 P2[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 15:0 – P2[15:0] Parameter 2 Value Value Mode Description n Compare Compare match event occurs when PWMx timer = n (Refer to MODE selections) n Variable Aligned PWMx_SaP1_out and PWMx_SaP2 both go low when PWMx timer = n n Center-Aligned PWMx_SaP2_out is high 2*n PWMx clock periods centered around PWMx period event n Right Aligned PWMx_SaP2_out is high n PWMx clock periods at end of PWMx period n Left Aligned PWMx_SaP2_out is high n PWMx clock periods at beginning of PWMx period Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • PWMxSaP2H: Accesses the high byte P2[15:8] • PWMxSaP2L: Accesses the low byte P2[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 459 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.9.13 PWMLOAD Name:  Address:  PWMLOAD 0x49C Mirror copies of all PWMxLD bits Bit 7 6 5 4 3 Access Reset 2 MPWM3LD R/W 0 1 MPWM2LD R/W 0 0 MPWM1LD R/W 0 Bits 0, 1, 2 – MPWMxLD Mirror copy of PWMxLD bit Mirror copies of all PWMxLD bits can be set simultaneously to synchronize the load event across all PWMs Value Description 1 PWMx parameter and period values will be transferred to their buffer registers at the next period Reset event 0 There are no PWMx period and parameter value transfers pending © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 460 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.9.14 PWMEN Name:  Address:  PWMEN 0x49D Mirror copies of all PWMxEN bits Bit 7 6 5 4 3 Access Reset 2 MPWM3EN R/W 0 1 MPWM2EN R/W 0 0 MPWM1EN R/W 0 Bits 0, 1, 2 – MPWMxEN Mirror copy of PWMxEN bit Mirror copies of all PWMxEN bits can be set simultaneously to synchronize the enable event across all PWMs Value Description 1 PWMx is enabled 0 PWMx is not enabled © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 461 PIC18F06/16Q41 PWM - Pulse-Width Modulator with Compare 30.10 Address Register Summary - PWM Name 0x00 ... 0x045F 0x0460 0x0461 0x0462 PWM1ERS PWM1CLK PWM1LDS 0x0463 PWM1PR 0x0465 0x0466 0x0467 0x0468 0x0469 0x046A PWM1CPRE PWM1PIPOS PWM1GIR PWM1GIE PWM1CON PWM1S1CFG 0x046B PWM1S1P1 0x046D PWM1S1P2 0x046F 0x0470 0x0471 PWM2ERS PWM2CLK PWM2LDS 0x0472 PWM2PR 0x0474 0x0475 0x0476 0x0477 0x0478 0x0479 PWM2CPRE PWM2PIPOS PWM2GIR PWM2GIE PWM2CON PWM2S1CFG 0x047A PWM2S1P1 0x047C PWM2S1P2 0x047E 0x047F 0x0480 PWM3ERS PWM3CLK PWM3LDS 0x0481 PWM3PR 0x0483 0x0484 0x0485 0x0486 0x0487 0x0488 PWM3CPRE PWM3PIPOS PWM3GIR PWM3GIE PWM3CON PWM3S1CFG 0x0489 PWM3S1P1 0x048B PWM3S1P2 0x048D ... 0x049B 0x049C 0x049D Bit Pos. 7 6 5 4 3 2 1 0 S1P2 S1P2 ERSPOL MODE[2:0] S1P1 S1P1 ERSNOW Reserved 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 ERS[3:0] CLK[3:0] LDS[3:0] PR[7:0] PR[15:8] CPRE[7:0] PIPOS[7:0] EN POL2 LD POL1 PPEN P1[7:0] P1[15:8] P2[7:0] P2[15:8] ERS[3:0] CLK[3:0] LDS[3:0] PR[7:0] PR[15:8] CPRE[7:0] PIPOS[7:0] EN POL2 S1P2 S1P2 ERSPOL MODE[2:0] LD POL1 PPEN S1P1 S1P1 ERSNOW P1[7:0] P1[15:8] P2[7:0] P2[15:8] ERS[3:0] CLK[3:0] LDS[3:0] PR[7:0] PR[15:8] CPRE[7:0] PIPOS[7:0] EN POL2 LD POL1 PPEN S1P2 S1P2 ERSPOL MODE[2:0] S1P1 S1P1 ERSNOW MPWM2LD MPWM2EN MPWM1LD MPWM1EN P1[7:0] P1[15:8] P2[7:0] P2[15:8] Reserved PWMLOAD PWMEN 7:0 7:0 © 2020-2021 Microchip Technology Inc. and its subsidiaries MPWM3LD MPWM3EN Preliminary Datasheet DS40002214E-page 462 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31. CWG - Complementary Waveform Generator Module The Complementary Waveform Generator (CWG) produces half-bridge, full-bridge, and steering of PWM waveforms. It is backwards compatible with previous CCP functions. The CWG has the following features: • • • • • 31.1 Six Operating modes: – Synchronous Steering mode – Asynchronous Steering mode – Full Bridge mode, Forward – Full Bridge mode, Reverse – Half Bridge mode – Push-Pull mode Output Polarity Control Output Steering Independent 6-bit Rising and Falling Event Dead-Band Timers: – Clocked dead band – Independent rising and falling dead-band enables Auto-Shutdown Control with: – Selectable shutdown sources – Auto-restart option – Auto-shutdown pin override control Fundamental Operation The CWG generates two output waveforms from the selected input source. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby creating a time delay immediately where neither output is driven. This is referred to as dead time and is covered in the Dead-Band Control section. It may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or not at all. In this case, the active drive must be terminated before the Fault condition causes damage. This is referred to as auto-shutdown and is covered in the Auto-Shutdown section. 31.2 Operating Modes The CWG module can operate in six different modes, as specified by the MODE bits: • • • • • • Half Bridge mode Push-Pull mode Asynchronous Steering mode Synchronous Steering mode Full Bridge mode, Forward Full Bridge mode, Reverse All modes accept a single pulse input, and provide up to four outputs as described in the following sections. All modes include auto-shutdown control as described in the Auto-Shutdown section. Important:  Except as noted for Full Bridge mode, mode changes must only be performed while EN = 0. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 463 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.2.1 Half Bridge Mode In Half Bridge mode, two output signals are generated as true and inverted versions of the input as illustrated in Figure 31-1. A nonoverlap (dead band) time is inserted between the two outputs to prevent shoot-through current in various power supply applications. Dead-band control is described in the Dead-Band Control section. The output steering feature cannot be used in this mode. A basic block diagram of this mode is shown in Figure 31-2. The unused outputs CWGxC and CWGxD drive similar signals as CWGxA and CWGxB, with polarity independently controlled by the POLC and POLD bits, respectively. Figure 31-1. CWG Half Bridge Mode Operation Rev. 30-000097A 4/14/2017 CWGx_clock CWGxA CWGxC Rising event dead band Rising event dead band Falling event dead band Falling event dead band CWGxB CWGxD CWGx_data © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 464 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... Figure 31-2. Simplified CWG Block Diagram (Half Bridge Mode, MODE = ‘b100) LSAC 1 0 High-Z clock data out CWG Data 11 10 01 00 Rising Dead-Band Block CWG Clock Re v. 10 -00 02 09 D 1/29 /20 19 1 CWG Data A data in 0 POLA CWGxA LSBD 1 11 0 10 High-Z 01 Falling Dead-Band Block clock data out CWG Data B data in 00 1 CWG Data CWG Data Input 0 POLB D CWGxB Q E LSAC EN 1 11 0 10 High-Z 01 00 1 0 CWGxC POLC Auto-shutdown source (CWGxAS1 register) S Q LSBD R REN SHUTDO WN = 0 1 11 0 10 High-Z 01 00 1 0 CWG1D POLD SHUTDO WN FREEZE D Q CWG Data © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 465 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.2.2 Push-Pull Mode In Push-Pull mode, two output signals are generated, alternating copies of the input as illustrated in Figure 31-3. This alternation creates the Push-Pull effect required for driving some transformer-based power supply designs. Steering modes are not used in Push-Pull mode. A basic block diagram for the Push-Pull mode is shown in Figure 31-4. The Push-Pull sequencer is reset whenever EN = 0 or if an auto-shutdown event occurs. The sequencer is clocked by the first input pulse, and the first output appears on CWGxA. The unused outputs CWGxC and CWGxD drive copies of CWGxA and CWGxB, respectively, but with polarity controlled by the POLC and POLD bits, respectively. Figure 31-3. CWG Push-Pull Mode Operation Rev. 30-000098A 4/14/2017 CWGx clock CWG Data Input CWGxA CWGxB © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 466 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... Figure 31-4. Simplified CWG Block Diagram (Push-Pull Mode, MODE = ‘b101) LSAC Re v. 10 -00 02 10 D 1/29 /20 19 1 11 0 10 High-Z 01 00 CWG Data 1 CWG Data A 0 CWGxA POLA D LSBD Q Q 1 11 0 10 High-Z 01 00 CWG Data B 1 CWG Data Input CWG Data D 0 CWGxB POLB Q LSAC E 1 11 0 10 High-Z 01 EN 00 1 0 CWGxC POLC Auto-shutdown source (CWGxAS1 register) S Q LSBD R 1 11 0 10 High-Z 01 REN SHUTDO WN = 0 00 1 0 CWGxD POLD SHUTDO WN FREEZE D Q CWG Data © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 467 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.2.3 Full Bridge Mode In Forward and Reverse Full Bridge modes, three outputs drive static values while the fourth is modulated by the input data signal. The mode selection may be toggled between forward and reverse by toggling the MODE[0] bit of the CWGxCON0 register while keeping the MODE[2:1] bits static, without disabling the CWG module. When connected, as shown in Figure 31-5, the outputs are appropriate for a full-bridge motor driver. Each CWG output signal has independent polarity control, so the circuit can be adapted to high-active and low-active drivers. A simplified block diagram for the Full Bridge modes is shown in Figure 31-6. Figure 31-5. Example of Full-Bridge Application Re v. 10 -00 02 63 A 2/8/20 19 VDD FET Driver QA QC FET Driver CWG1A LOAD CWG1B CWG1C FET Driver CWG1D © 2020-2021 Microchip Technology Inc. and its subsidiaries FET Driver QB Preliminary Datasheet QD DS40002214E-page 468 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... Figure 31-6. Simplified CWG Block Diagram (Forward and Reverse Full Bridge Modes) MODE = ‘b010: Forward Re v. 10 -00 02 12 D 2/7/20 19 LSAC MODE = ‘b011: Reverse Rising Dead-Band Block CWG Clock clock signal out signal in 1 11 0 10 High-Z 01 00 CWG Data 1 CWG Data A 0 POLA MODE[0] D CWG Data CWGA Q Q LSBD cwg data signal in signal out clock CWG Clock 1 11 0 10 High-Z 01 00 Falling Dead-Band Block CWG Data Input CWG Data 1 CWG Data B 0 CWGxB POLB D Q LSAC E EN 1 11 0 10 High-Z 01 00 1 CWG Data C 0 CWGxC POLC Auto-shutdown source (CWGxAS1 register) S Q LSBD R REN SHUTDO WN = 0 1 11 0 10 High-Z 01 00 1 CWG Data D 0 CWGxD POLD SHUTDO WN FREEZE D Q CWG Data © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 469 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... In Forward Full Bridge mode (MODE = ‘b010), CWGxA is driven to its Active state, CWGxB and CWGxC are driven to their Inactive state, and CWGxD is modulated by the input signal, as shown in Figure 31-7. In Reverse Full Bridge mode (MODE = ‘b011), CWGxC is driven to its Active state, CWGxA and CWGxD are driven to their Inactive states, and CWGxB is modulated by the input signal, as shown in Figure 31-7. In Full Bridge mode, the dead-band period is used when there is a switch from forward to reverse or vice versa. This dead-band control is described in the Dead-Band Control section, with additional details in the Rising Edge and Reverse Dead Band and Falling Edge and Forward Dead Band sections. Steering modes are not used with either of the Full Bridge modes. Figure 31-7. Example of Full-Bridge Output Rev. 30-000099A 4/14/2017 Forward Mode Period CWGxA (2) CWGxB (2) CWGxC (2) Pulse Width CWGxD (2) (1) Reverse Mode (1) Period CWGxA (2) Pulse Width CWGxB (2) CWGxC (2) CWGxD (2) (1) (1) Notes:  1. A rising CWG data input creates a rising event on the modulated output. 2. Output signals shown as active-high; all POLy bits are clear. 31.2.3.1 Direction Change in Full Bridge Mode In Full Bridge mode, changing the MODE[0] bit controls the forward/reverse direction. Direction changes occur on the next rising edge of the modulated input. The sequence, described as follows, is illustrated in Figure 31-8. 1. 2. 3. The associated active output CWGxA and the inactive output CWGxC are switched to drive in the opposite direction. The previously modulated output CWGxD is switched to the Inactive state, and the previously inactive output CWGxB begins to modulate. CWG modulation resumes after the direction-switch dead band has elapsed. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 470 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... Figure 31-8. Example of PWM Direction Change at Near 100% Duty Cycle Rev. 30-000100A 4/14/2017 Forward Period t1 Reverse Period CWGxA Pulse Width CWGxB CWGxC CWGxD Pulse Width TON External Switch C TOFF External Switch D Potential ShootThrough Current T = TOFF - TON 31.2.3.2 Dead-Band Delay in Full Bridge Mode Dead-band delay is important when either of the following conditions is true: • • The direction of the CWG output changes when the duty cycle of the data input is at or near 100%. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. The dead-band delay is inserted only when changing directions, and only the modulated output is affected. The statically-configured outputs (CWGxA and CWGxC) are not afforded dead band, and switch essentially simultaneously. Figure 31-8 shows an example of the CWG outputs changing directions from forward to reverse, at near 100% duty cycle. In this example, at time t1, the output of CWGxA and CWGxD becomes inactive, while the output of CWGxC becomes active. Since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current will flow through the power devices QC and QD for the duration of ‘T’. The same phenomenon will occur to power devices QA and QB for the CWG direction change from reverse to forward. When changing the CWG direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. 2. 31.2.4 Reduce the CWG duty cycle for one period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. Steering Modes In both Synchronous and Asynchronous Steering modes, the CWG Data can be steered to any combination of four CWG outputs. A fixed value will be presented on all the outputs not used for the PWM output. Each output has independent polarity, steering, and shutdown options. Dead-band control is not used in either Steering mode. For example, when STRA = 0, the corresponding pin is held at the level defined by OVRA. When STRA = 1, the pin is driven by the CWG Data signal. The POLy bits control the signal polarity only when STRy = 1. The CWG auto-shutdown operation also applies in Steering modes as described in the Auto-Shutdown section. An auto-shutdown event will only affect pins that have STRy = 1. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 471 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... Figure 31-9. Simplified CWG Block Diagram (Output Steering Modes) MODE = ‘b000: Asynchronous LSAC MODE = ‘b001: Synchronous 1 11 0 10 High-Z 01 Re v. 10 -00 02 11 D 2/7/20 19 00 CWG Data A 1 1 POLA 0 CWGxA 0 OVRA STRA CWG Data CWG Data Input LSBD 1 11 0 10 High-Z 01 00 D CWG Data B Q E 1 1 POLB 0 CWGxB 0 OVRB EN STRB LSAC 1 11 0 10 High-Z 01 00 CWG Data C Auto-shutdown source (CWGxAS1 register) S Q 1 1 POLC 0 CWGxC 0 R OVRC STRC REN LSBD SHUTDO WN = 0 1 11 0 10 High-Z 01 00 CWG Data D 1 POLD 0 1 0 CWGxD OVRD SHUTDO WN STRD FREEZE D Q CWG Data © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 472 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.2.4.1 Synchronous Steering Mode In Synchronous Steering mode (MODE = ‘b001), the changes to steering selection registers take effect on the next rising edge of CWG Data (see the figure below). In Synchronous Steering mode, the output will always produce a complete waveform. Important:  Only the STRx bits are synchronized; the OVRx bits are not synchronized. Figure 31-10. Example of Synchronous Steering (MODE = ‘b001) Rev. 30-000101A 4/14/2017 CWGx clock CWG Data CWGxA CWGxB 31.2.4.2 Asynchronous Steering Mode In Asynchronous mode (MODE = ‘b000), steering takes effect at the end of the instruction cycle that writes to STRx. In Asynchronous Steering mode, the output signal may be an incomplete waveform (see the figure below). This operation may be useful when the user firmware needs to immediately remove a signal from the output pin. Figure 31-11. Example of Asynchronous Steering (MODE = ‘b000) Rev. 30-000102A 4/14/2017 CWG Data End of Instruction Cycle End of Instruction Cycle STRA CWGxA CWG1A Follows CWG1 data input 31.2.4.3 Start-Up Considerations The application hardware must use the proper external pull-up and/or pull-down resistors on the CWG output pins. This is required because all I/O pins are forced to high-impedance at Reset. The Polarity Control (POLy) bits allow the user to choose whether the output signals are active-high or active-low. 31.3 Clock Source The clock source is used to drive the dead-band timing circuits. The CWG module allows the following clock sources to be selected: • • FOSC (system clock) HFINTOSC When the HFINTOSC is selected, the HFINTOSC will be kept running during Sleep. Therefore, the CWG modes requiring dead band can operate in Sleep, provided that the CWG data input is also active during Sleep. The clock sources are selected using the CS bit. The system clock FOSC is disabled in Sleep and thus dead-band control cannot be used. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 473 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.4 Selectable Input Sources The CWG generates the output waveforms from the input sources which are selected with the ISM bits. Refer to the CWGxISM register for more details. 31.5 31.5.1 Output Control CWG Output Each CWG output can be routed to a Peripheral Pin Select (PPS) output via the RxyPPS register. Refer to the “PPS - Peripheral Pin Select Module” chapter for more details. 31.5.2 Polarity Control The polarity of each CWG output can be selected independently. When the output polarity bit is set, the corresponding output is active-high. Clearing the output polarity bit configures the corresponding output as active-low. However, polarity does not affect the override levels. Output polarity is selected with the POLy bits. Auto-shutdown and steering options are unaffected by polarity. 31.6 Dead-Band Control The dead-band control provides nonoverlapping complementary outputs to prevent shoot-through current when the outputs switch. Dead-band operation is employed for Half Bridge and Full Bridge modes. The CWG contains two 6-bit dead-band counters. One is used for the rising edge of the input source control in Half Bridge mode or for reverse direction change dead band in Full Bridge mode. The other is used for the falling edge of the input source control in Half Bridge mode or for forward direction change dead band in Full Bridge mode. Dead band is timed by counting CWG clock periods from zero up to the value in the rising or falling dead-band counter registers. 31.6.1 Dead-Band Functionality in Half Bridge Mode In Half Bridge mode, the dead-band counters dictate the delay between the falling edge of the normal output and the rising edge of the inverted output. This can be seen in Figure 31-1. 31.6.2 Dead-Band Functionality in Full Bridge Mode In Full Bridge mode, the dead-band counters are used when undergoing a direction change. The MODE[0] bit can be set or cleared while the CWG is running, allowing for changes from Forward to Reverse mode. The CWGxA and CWGxC signals will change immediately upon the first rising input edge following a direction change, but the modulated signals (CWGxB or CWGxD, depending on the direction of the change) will experience a delay dictated by the dead-band counters. 31.7 Rising Edge and Reverse Dead Band In Half Bridge mode, the rising edge dead band delays the turn-on of the CWGxA output after the rising edge of the CWG data input. In Full Bridge mode, the reverse dead-band delay is only inserted when changing directions from Forward mode to Reverse mode, and only the modulated output, CWGxB, is affected. The CWGxDBR register determines the duration of the dead-band interval on the rising edge of the input source signal. This duration is from 0 to 64 periods of the CWG clock. The following figure illustrates different dead-band delays for rising and falling CWG Data events. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 474 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... Figure 31-12. Dead-Band Operation, CWGxDBR = 0x01, CWGxDBF = 0x02 Rev. 30-000103A 4/14/2017 cwg_clock CWG Data CWGxA CWGxB Dead band is always initiated on the edge of the input source signal. A count of zero indicates that no dead band is present. If the input source signal reverses polarity before the dead-band count is completed, then no signal will be seen on the respective output. The CWGxDBR register value is double-buffered. When EN = 0, the buffer is loaded when CWGxDBR is written. When EN = 1, the buffer will be loaded at the rising edge following the first falling edge of the CWG Data, after the LD bit is set. 31.8 Falling Edge and Forward Dead Band In Half Bridge mode, the falling edge dead band delays the turn-on of the CWGxB output at the falling edge of the CWG data input. In Full Bridge mode, the forward dead-band delay is only inserted when changing directions from Reverse mode to Forward mode, and only the modulated output, CWGxD, is affected. The CWGxDBF register determines the duration of the dead-band interval on the falling edge of the input source signal. This duration is from 0 to 64 periods of the CWG clock. Dead-band delay is always initiated on the edge of the input source signal. A count of zero indicates that no dead band is present. If the input source signal reverses polarity before the dead-band count is completed, then no signal will be seen on the respective output. Figure 31-13. Dead-Band Operation, CWGxDBR = 0x03, CWGxDBF = 0x06, Source Shorter Than Dead Band Rev. 30-000104A 4/14/2017 cwg_clock CWG Data CWGxA CWGxB source shorter than dead band The CWGxDBF register value is double-buffered. When EN = 0, the buffer is loaded when CWGxDBF is written. When EN = 1, the buffer will be loaded at the rising edge following the first falling edge of the data input after the LD bit is set. 31.9 Dead-Band Jitter When the rising and falling edges of the input source are asynchronous to the CWG clock, it creates jitter in the dead-band time delay. The maximum jitter is equal to one CWG clock period. Refer to the equations below for more details. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 475 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... Equation 31-1. Dead-Band Delay Time Calculation 1 TDEAD − BAND_MIN = • DBx FCWG_CLOCK TDEAD − BAND_MAX = 1 • DBx + 1 FCWG_CLOCK T JITTER = TDEAD − BAND_MAX − TDEAD − BAND_MIN T JITTER = 1 FCWG_CLOCK TDEAD − BAND_MAX = TDEAD − BAND_MIN + T JITTER Dead-Band Delay Example Calculation DBx = 0x0A = 10 FCWG_CLOCK = 8 MHz 1 T JITTER = = 125 ns 8 MHz TDEAD − BAND_MIN = 125 ns • 10 = 1.25 μs TDEAD − BAND_MAX = 1.25 μs + 0.125 μs = 1.37 μs 31.10 Auto-Shutdown Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit. The Shutdown state can be either cleared automatically or held until cleared by software. The auto-shutdown circuit is illustrated in the following figure. Figure 31-14. CWG Shutdown Block Diagram Write 1 to SHUTDOWN bit Re v. 10 -00 01 72 F 2/8/20 19 Auto-shutdown source (CWGxAS1 register) S Q SHUTDOWN S D FREEZE REN Write 0 to SHUTDOWN bit Q CWG_shutdown R CWG_data CK 31.10.1 Shutdown The Shutdown state can be entered by either of the following two methods: • • Software Generated External Input 31.10.2 Software Generated Shutdown Setting the SHUTDOWN bit will force the CWG into the Shutdown state. When the auto-restart is disabled, the Shutdown state will persist as long as the SHUTDOWN bit is set. When auto-restart is enabled, the SHUTDOWN bit will clear automatically and resume operation on the next rising edge event. The SHUTDOWN bit indicates when a Shutdown condition exists. The bit may be set or cleared in software or by hardware. 31.10.3 External Input Source External shutdown inputs provide the fastest way to safely suspend CWG operation in the event of a Fault condition. When any of the selected shutdown inputs goes active, the CWG outputs will immediately go to the selected override levels without software delay. The override levels are selected by the LSBD and LSAC bits. Several input sources can be selected to cause a Shutdown condition. All input sources are active-low. The shutdown input sources are individually enabled by the ASyE bits. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 476 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... Important:  Shutdown inputs are level sensitive, not edge sensitive. The Shutdown state cannot be cleared, except by disabling auto-shutdown, as long as the shutdown input level persists. 31.10.4 Pin Override Levels The levels driven to the CWG outputs during an auto-shutdown event are controlled by the LSBD and LSAC bits. The LSBD bits control CWGxB/D output levels, while the LSAC bits control the CWGxA/C output levels. 31.10.5 Auto-Shutdown Interrupts When an auto-shutdown event occurs, either by software or hardware setting SHUTDOWN, the CWGxIF flag bit of the PIRx register is set. 31.11 Auto-Shutdown Restart After an auto-shutdown event has occurred, there are two ways to resume operation: • • Software controlled Auto-restart In either case, the shutdown source must be cleared before the restart can take place. That is, either the Shutdown condition must be removed, or the corresponding ASyE bit must be cleared. 31.11.1 Software-Controlled Restart When the REN bit is clear (REN = 0), the CWG module must be restarted after an auto-shutdown event through software. Once all auto-shutdown sources are removed, the software must clear the SHUTDOWN bit. Once SHUTDOWN is cleared, the CWG module will resume operation upon the first rising edge of the CWG data input. Important:  The SHUTDOWN bit cannot be cleared in software if the Auto-Shutdown condition is still present. Figure 31-15. Shutdown Functionality, Auto-Restart Disabled (REN = 0, LSAC = ‘b01, LSBD = ‘b01) Rev. 30-000105A 4/14/2017 Shutdown Event Ceases REN Cleared by Software CWG Input Shutdown Source SHUTDOWN CWGxA CWGxC Tri-State (No Pulse) CWGxB CWGxD Tri-State (No Pulse) No Shutdown Shutdown Output Resumes 31.11.2 Auto-Restart When the REN bit is set (REN = 1), the CWG module will restart from the Shutdown state automatically. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 477 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... Once all Auto-Shutdown conditions are removed, the hardware will automatically clear the SHUTDOWN bit. Once SHUTDOWN is cleared, the CWG module will resume operation upon the first rising edge of the CWG data input. Important:  The SHUTDOWN bit cannot be cleared in software if the Auto-Shutdown condition is still present. Figure 31-16. Shutdown Functionality, Auto-Restart Enabled (REN = 1, LSAC = ‘b01, LSBD = ‘b01) Rev. 30-000106A 4/14/2017 Shutdown Event Ceases REN auto-cleared by hardware CWG Input Shutdown Source SHUTDOWN CWGxA CWGxC Tri-State (No Pulse) CWGxB CWGxD Tri-State (No Pulse) No Shutdown Shutdown 31.12 Output Resumes Operation During Sleep The CWG module operates independently from the system clock and will continue to run during Sleep, provided that the clock and input sources selected remain active. The HFINTOSC remains active during Sleep when all the following conditions are met: • • • CWG module is enabled Input source is active HFINTOSC is selected as the clock source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and the CWG clock source, when the CWG is enabled and the input source is active, then the CPU will go Idle during Sleep, but the HFINTOSC will remain active and the CWG will continue to operate. This will have a direct effect on the Sleep mode current. 31.13 Configuring the CWG 1. Ensure that the TRIS control bits corresponding to CWG outputs are set so that all are configured as inputs, ensuring that the outputs are inactive during setup. External hardware must ensure that pin levels are held to safe levels. 2. Clear the EN bit, if not already cleared. 3. Configure the MODE bits to set the output operating mode. 4. Configure the POLy bits to set the output polarities. 5. Configure the ISM bits to select the data input source. 6. If a Steering mode is selected, configure the STRy bits to select the desired output on the CWG outputs. 7. Configure the LSBD and LSAC bits to select the Auto-Shutdown Output Override states (this is necessary even if not using auto-shutdown, because start-up will be from a Shutdown state). 8. If auto-restart is desired, set the REN bit. 9. If auto-shutdown is desired, configure the ASyE bits to select the shutdown source. 10. Set the desired rising and falling dead-band times with the CWGxDBR and CWGxDBF registers. 11. Select the clock source with the CS bit. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 478 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 12. Set the EN bit to enable the module. 13. Clear the TRIS bits that correspond to the CWG outputs to set them as outputs. If auto-restart is to be used, set the REN bit and the SHUTDOWN bit will be cleared automatically. Otherwise, clear the SHUTDOWN bit in software to start the CWG. 31.14 Register Definitions: CWG Control Long bit name prefixes for the CWG peripherals are shown in the table below. Refer to the “Long Bit Names” section in the “Register and Bit Naming Conventions” chapter for more information. Table 31-1. CWG Long Bit Name Prefixes Peripheral Bit Name Prefix CWG1 CWG1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 479 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.14.1 CWGxCON0 Name:  Address:  CWGxCON0 0x03C0 CWG Control Register 0 Bit Access Reset 7 EN R/W 0 6 LD R/W/HC 0 5 4 3 2 R/W 0 1 MODE[2:0] R/W 0 0 R/W 0 Bit 7 – EN CWG Enable Value Description 1 Module is enabled 0 Module is disabled Bit 6 – LD  CWG1 Load Buffers(1) Value Description 1 Dead-band count buffers to be loaded on CWG data rising edge, following first falling edge after this bit is set 0 Buffers remain unchanged Bits 2:0 – MODE[2:0] CWG Mode Value Description 111 Reserved 110 Reserved 101 CWG outputs operate in Push-Pull mode 100 CWG outputs operate in Half Bridge mode 011 CWG outputs operate in Reverse Full Bridge mode 010 CWG outputs operate in Forward Full Bridge mode 001 CWG outputs operate in Synchronous Steering mode 000 CWG outputs operate in Asynchronous Steering mode Note:  1. This bit can only be set after EN = 1; it cannot be set in the same cycle when EN is set. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 480 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.14.2 CWGxCON1 Name:  Address:  CWGxCON1 0x03C1 CWG Control Register 1 Bit 7 6 Access Reset 5 IN R x 4 3 POLD R/W 0 2 POLC R/W 0 1 POLB R/W 0 0 POLA R/W 0 Bit 5 – IN CWG Input Value (read-only) Value Description 1 CWG data input is a logic ‘1’ 0 CWG data input is a logic ‘0’ Bits 0, 1, 2, 3 – POLy CWG Output ‘y’ Polarity Value Description 1 Signal output is inverted polarity 0 Signal output is normal polarity © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 481 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.14.3 CWGxCLK Name:  Address:  CWGxCLK 0x03BC CWG Clock Input Selection Register Bit 7 6 5 4 3 Access Reset 2 1 0 CS R/W 0 Bit 0 – CS CWG Clock Source Selection Select Value Description 1 HFINTOSC (remains operating during Sleep) 0 FOSC © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 482 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.14.4 CWGxISM Name:  Address:  CWGxISM 0x03BD CWGx Input Selection Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 ISM[3:0] Access Reset R/W 0 R/W 0 Bits 3:0 – ISM[3:0] CWG Data Input Source Select ISM 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 © 2020-2021 Microchip Technology Inc. and its subsidiaries Input Selection CWG1 CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT DSM1_OUT CMP2_OUT CMP1_OUT NCO1_OUT PWM3S1P2_OUT PWM3S1P1_OUT PWM2S1P2_OUT PWM2S1P1_OUT PWM1S1P2_OUT PWM1S1P1_OUT CCP1_OUT Pin selected by CWG1PPS Preliminary Datasheet DS40002214E-page 483 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.14.5 CWGxSTR Name:  Address:  CWGxSTR 0x03C4 CWG Steering Control Register(1) Bit 7 OVRD R/W 0 Access Reset 6 OVRC R/W 0 5 OVRB R/W 0 4 OVRA R/W 0 3 STRD R/W 0 2 STRC R/W 0 1 STRB R/W 0 0 STRA R/W 0 Bits 4, 5, 6, 7 – OVRy Steering Data OVR'y' Value Condition Description x STRy = 1 CWGx'y' output has the CWG data input waveform with polarity control from POLy bit 1 STRy = 0 and POLy = x CWGx'y' output is high 0 STRy = 0 and POLy = x CWGx'y' output is low Bits 0, 1, 2, 3 – STRy  STR'y' Steering Enable(2) Value Description 1 CWGx'y' output has the CWG data input waveform with polarity control from the POLy bit 0 CWGx'y' output is assigned to value of the OVRy bit Notes:  1. The bits in this register apply only when MODE = ‘b00x (CWGxCON0, Steering modes). 2. This bit is double-buffered when MODE = ‘b001. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 484 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.14.6 CWGxAS0 Name:  Address:  CWGxAS0 0x03C2 CWG Auto-Shutdown Control Register 0 Bit 7 SHUTDOWN Access R/W/HS/HC Reset 0 6 REN R/W 0 5 4 3 LSBD[1:0] R/W 0 2 1 0 LSAC[1:0] R/W 1 R/W 0 R/W 1 Bit 7 – SHUTDOWN  Auto-Shutdown Event Status(1,2) Value Description 1 An Auto-Shutdown state is in effect 0 No auto-shutdown event has occurred Bit 6 – REN Auto-Restart Enable Value Description 1 Auto-restart is enabled 0 Auto-restart is disabled Bits 5:4 – LSBD[1:0] CWGxB and CWGxD Auto-Shutdown State Control Value Description 11 A logic ‘1’ is placed on CWGxB/D when an auto-shutdown event occurs 10 A logic ‘0’ is placed on CWGxB/D when an auto-shutdown event occurs 01 Pin is tri-stated on CWGxB/D when an auto-shutdown event occurs 00 The Inactive state of the pin, including polarity, is placed on CWGxB/D after the required dead-band interval when an auto-shutdown event occurs Bits 3:2 – LSAC[1:0] CWGxA and CWGxC Auto-Shutdown State Control Value Description 11 A logic ‘1’ is placed on CWGxA/C when an auto-shutdown event occurs 10 A logic ‘0’ is placed on CWGxA/C when an auto-shutdown event occurs 01 Pin is tri-stated on CWGxA/C when an auto-shutdown event occurs 00 The Inactive state of the pin, including polarity, is placed on CWGxA/C after the required dead-band interval when an auto-shutdown event occurs Notes:  1. This bit may be written while EN = 0, to place the outputs into the shutdown configuration. 2. The outputs will remain in Auto-Shutdown state until the next rising edge of the CWG data input after this bit is cleared. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 485 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.14.7 CWGxAS1 Name:  Address:  CWGxAS1 0x03C3 CWG Auto-Shutdown Control Register 1 Bit 7 AS7E R/W 0 Access Reset 6 AS6E R/W 0 5 AS5E R/W 0 4 AS4E R/W 0 3 AS3E R/W 0 2 AS2E R/W 0 1 AS1E R/W 0 0 AS0E R/W 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 – ASyE  CWG Auto-Shutdown Source Enable(1,2) ASyE AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E Auto-Shutdown Source CWG1 Reserved CLC4_OUT CLC2_OUT CMP2_OUT CMP1_OUT TMR4_Postscaler_OUT TMR2_Postscaler_OUT Pin selected by CWG1PPS Notes:  1. This bit may be written while EN = 0, to place the outputs into the shutdown configuration. 2. The outputs will remain in Auto-Shutdown state until the next rising edge of the CWG data input after this bit is cleared. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 486 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.14.8 CWGxDBR Name:  Address:  CWGxDBR 0x03BE CWG Rising Dead-Band Count Register Bit 7 6 5 4 3 2 1 0 R/W x R/W x R/W x DBR[5:0] Access Reset R/W x R/W x R/W x Bits 5:0 – DBR[5:0] CWG Rising Edge-Triggered Dead-Band Count Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu Value Description n Dead band is active no less than n and no more than n+1 CWG clock periods after the rising edge 0 0 CWG clock periods. Dead-band generation is bypassed. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 487 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.14.9 CWGxDBF Name:  Address:  CWGxDBF 0x03BF CWG Falling Dead-Band Count Register Bit 7 6 5 4 3 2 1 0 R/W x R/W x R/W x DBF[5:0] Access Reset R/W x R/W x R/W x Bits 5:0 – DBF[5:0] CWG Falling Edge-Triggered Dead-Band Count Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu Value Description n Dead band is active no less than n and no more than n+1 CWG clock periods after the falling edge 0 0 CWG clock periods. Dead-band generation is bypassed. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 488 PIC18F06/16Q41 CWG - Complementary Waveform Generator Mod... 31.15 Address 0x00 ... 0x03BB 0x03BC 0x03BD 0x03BE 0x03BF 0x03C0 0x03C1 0x03C2 0x03C3 0x03C4 Register Summary - CWG Name Bit Pos. 7 6 5 4 3 2 1 0 Reserved CWG1CLK CWG1ISM CWG1DBR CWG1DBF CWG1CON0 CWG1CON1 CWG1AS0 CWG1AS1 CWG1STR 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 CS ISM[3:0] DBR[5:0] DBF[5:0] EN IN SHUTDOWN AS7E OVRD © 2020-2021 Microchip Technology Inc. and its subsidiaries LD REN AS6E OVRC LSBD[1:0] AS5E AS4E OVRB OVRA POLD POLC LSAC[1:0] AS3E AS2E STRD STRC Preliminary Datasheet MODE[2:0] POLB POLA AS1E STRB AS0E STRA DS40002214E-page 489 PIC18F06/16Q41 NCO - Numerically Controlled Oscillator Mo... 32. NCO - Numerically Controlled Oscillator Module The Numerically Controlled Oscillator (NCO) module is a timer that uses overflow from the addition of an increment value to divide the input frequency. The advantage of the addition method over a simple counter driven timer is that the output frequency resolution does not vary with the divider value. The NCO is most useful for applications that require frequency accuracy and fine resolution at a fixed duty cycle. Features of the NCO include: • 20-Bit Increment Function • Fixed Duty Cycle (FDC) mode • Pulse Frequency (PF) mode • Output Pulse-Width Control • Multiple Clock Input Sources • Output Polarity Control • Interrupt Capability The following figure is a simplified block diagram of the NCO module. Figure 32-1. Numerically Controlled Oscillator Module Simplified Block Diagram NCOxINC 20 (1) INCxBUF 20 NCO_overflow NCOx Cloc k Sources 20 Adder 20 NCOx_clk NCOxACC See NCOxCLK Register 20 NCO_interrupt Set NCOxIF Fixed Duty Cycle Mode Circuitry CKS D Q D Q TRIS control 0 NCOx_out _ PPS 1 NCOxOUT Q RxyPPS PFM POL To Peripherals S EN Q _ Ripple Counter R Q Synchronizer OUT bit in NCOxCO N Register Pulse Frequency Mode Circuitry R PWS Note 1: The increment registers are double-buffered to allow for value changes to be made without first disabling the NCO module. The full increment value is loaded into the buffer registers on the second rising edge of the NCOx_clk signal that occurs immediately after a write to the NCOxINCL register. The buffers are not useraccessible and are shown here for reference. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 490 PIC18F06/16Q41 NCO - Numerically Controlled Oscillator Mo... 32.1 NCO Operation The NCO operates by repeatedly adding a fixed value to an accumulator. Additions occur at the input clock rate. The accumulator will overflow with a carry periodically, which is the raw NCO output (NCO_overflow). This effectively reduces the input clock by the ratio of the addition value to the maximum accumulator value. See the following equation. Equation 32-1. NCO Overflow Frequency NCO Clock Frequency × Increment Value FOVERFLOW = 220 It is apparent from the equation that there is a linear relationship between the increment value and the overflow frequency. This linear advantage over divide-by-n timers comes at the cost of output jitter. However, the jitter is always plus or minus one NCO clock period that occurs periodically, depending on the division remainder. For example, when there is no division remainder then there is no jitter, whereas a division remainder of 0.5 will result in a jitter frequency one half of the overflow frequency. 32.1.1 NCO Clock Sources The NCO can be clocked from a variety of sources including the system clock, internal timers, and other peripherals. The NCO clock source is selected by configuring the CKS bits. 32.1.2 Accumulator The accumulator is a 20-bit register. Read and write access to the accumulator is available through three registers: • NCOxACCL • NCOxACCH • NCOxACCU 32.1.3 Adder The NCO adder is a full adder, which operates synchronously from the source clock. The addition of the previous result and the increment value replaces the accumulator value on the rising edge of each input clock. 32.1.4 Increment Registers The increment value is stored in three registers making up a 20-bit word. In order of LSB to MSB, they are: • NCOxINCL • NCOxINCH • NCOxINCU The increment registers are readable and writable and are double-buffered to allow value changes to be made without first disabling the NCO module. When the NCO module is enabled, the NCOxINCU and NCOxINCH registers will be written first, then the NCOxINCL register. Writing to the NCOxINCL register initiates the increment buffer registers to be loaded simultaneously on the second rising edge of the NCO_clk signal. When the NCO module is disabled, the increment buffers are loaded immediately after a write to the increment registers. Important:  The increment buffer registers are not user-accessible. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 491 PIC18F06/16Q41 NCO - Numerically Controlled Oscillator Mo... 32.2 Fixed Duty Cycle Mode In Fixed Duty Cycle (FDC) mode, every time the accumulator overflows, the output is toggled. This provides a 50% duty cycle at half the FOVERFLOW frequency, provided that the increment value remains constant. For more information, see the figure below. The FDC mode is selected by clearing the PFM bit. Figure 32-2. FDC Output Mode Timing Diagram Rev. 10-000029A 11/12/2018 NCOx Clock Source NCOx Increment Value NCOx Accumulator Value 4000h 00000h 04000h 08000h 4000h FC000h 00000h 04000h 08000h 4000h FC000h 00000h 04000h 08000h NCO_overflow NCO_interrupt NCOx Output FDC Mode NCOx Output PF Mode NCOxPWS = 000 NCOx Output PF Mode NCOxPWS = 001 32.3 Pulse Frequency Mode In Pulse Frequency (PF) mode, the output becomes active on the rising clock edge immediately following the overflow event, and goes inactive 1 to 128 clock periods later, determined by the PWS bits. This provides a pulsed output at the FOVERFLOW frequency. For more information, refer to the figure above. Important:  When the selected pulse width is greater than the accumulator overflow time frame, then the NCO output does not toggle. The level of the Active and Inactive states is determined by the POL bit. PF mode is selected by setting the PFM bit. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 492 PIC18F06/16Q41 NCO - Numerically Controlled Oscillator Mo... 32.4 Output Polarity Control The last stage in the NCO module is the output polarity. The POL bit selects the output polarity. The active level of the Pulse Frequency mode is high true when the POL bit is cleared. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. The NCO output signal (NCOx_out) is available by internal routing to several other peripherals. 32.5 Interrupts When the accumulator overflows, the NCO Interrupt Flag bit, NCOxIF, in the associated PIR register is set. To enable interrupt service on this event, the following bits must be set: • EN bit • NCOxIE bit in the associated PIE register • Peripheral and Global Interrupt Enable bits The interrupt must be cleared by software by clearing the NCOxIF bit in the Interrupt Service Routine. 32.6 Effects of a Reset All of the NCO registers are cleared to zero as the result of any Reset. 32.7 Operation in Sleep The NCO module operates independently from the system clock and will continue to run during Sleep, provided that the clock source selected remains active. The HFINTOSC remains active during Sleep when the NCO module is enabled and the HFINTOSC is selected as the clock source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and the NCO clock source, when the NCO is enabled, the CPU will go Idle during Sleep, but the NCO will continue to operate and the HFINTOSC will remain active. With a clock running, it will have a direct effect on the Sleep mode current. 32.8 Register Definitions: NCO Long bit name prefixes for the NCO peripherals are shown in the table below. Refer to the “Long Bit Names” section in the “Register and Bit Naming Conventions” chapter for more information. Table 32-1. NCO Long Bit Name Prefixes Peripheral Bit Name Prefix NCO1 NCO1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 493 PIC18F06/16Q41 NCO - Numerically Controlled Oscillator Mo... 32.8.1 NCOxCON Name:  Address:  NCOxCON 0x0446 NCO Control Register Bit Access Reset 7 EN R/W 0 6 5 OUT R 0 4 POL R/W 0 3 2 1 0 PFM R/W 0 Bit 7 – EN NCO Enable Value Description 1 NCO module is enabled 0 NCO module is disabled Bit 5 – OUT NCO Output Displays the current logic level of the NCO module output. Bit 4 – POL NCO Polarity Value Description 1 NCO output signal is inverted 0 NCO output signal is not inverted Bit 0 – PFM NCO Pulse Frequency Mode Value Description 1 NCO operates in Pulse Frequency mode. Output frequency is FOVERFLOW. 0 NCO operates in Fixed Duty Cycle mode. Output frequency is FOVERFLOW divided by 2. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 494 PIC18F06/16Q41 NCO - Numerically Controlled Oscillator Mo... 32.8.2 NCOxCLK Name:  Address:  NCOxCLK 0x0447 NCO Input Clock Control Register Bit Access Reset 7 R/W 0 6 PWS[2:0] R/W 0 5 4 3 2 1 0 R/W 0 R/W 0 CKS[3:0] R/W 0 R/W 0 R/W 0 Bits 7:5 – PWS[2:0]  NCO Output Pulse-Width Select(1) Value Description 111 NCO output is active for 128 input clock periods 110 NCO output is active for 64 input clock periods 101 NCO output is active for 32 input clock periods 100 NCO output is active for 16 input clock periods 011 NCO output is active for 8 input clock periods 010 NCO output is active for 4 input clock periods 001 NCO output is active for 2 input clock periods 000 NCO output is active for 1 input clock periods Bits 3:0 – CKS[3:0]  NCO Clock Source Select CKS Value 1111 - 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Clock Source NCO1 Reserved CLC4_OUT CLC3_out CLC2_OUT CLC1_OUT TMR4_OUT TMR2_OUT CLKREF EXTOSC SOSC MFINTOSC MFINTOSC LFINTOSC HFINTOSC FOSC Active in Sleep No No No No No No No Yes Yes Yes Yes Yes Yes No Note:  1. PWS applies only when operating in Pulse Frequency mode. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 495 PIC18F06/16Q41 NCO - Numerically Controlled Oscillator Mo... 32.8.3 NCOxACC Name:  Address:  NCOxACC 0x0440 NCO Accumulator Register Bit 23 22 21 20 19 18 17 16 ACC[19:16] Access Reset Bit 15 14 13 12 R/W 0 R/W 0 R/W 0 R/W 0 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 ACC[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 ACC[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 19:0 – ACC[19:0] Accumulated sum of NCO additions Notes:  1. The individual bytes in this multibyte register can be accessed with the following register names: – NCOxACCU: Accesses the upper byte ACC[23:16] – NCOxACCH: Accesses the high byte ACC[15:8] – NCOxACCL: Accesses the low byte ACC[7:0]. 2. The accumulator spans registers NCOxACCU:NCOxACCH:NCOxACCL. The 24 bits are reserved, but not all are used. This register updates in real-time, asynchronously to the CPU; there is no provision to ensure atomic access to this 24-bit space using an 8-bit bus. Writing to this register while the module is operating will produce undefined results. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 496 PIC18F06/16Q41 NCO - Numerically Controlled Oscillator Mo... 32.8.4 NCOxINC Name:  Address:  NCOxINC 0x0443 NCO Increment Register Bit 23 22 21 20 19 18 17 16 INC[19:16] Access Reset Bit 15 14 13 12 R/W 0 R/W 0 R/W 0 R/W 0 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 1 INC[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 INC[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 19:0 – INC[19:0] Value by which the NCOxACC is increased by each NCO clock Notes:  1. The individual bytes in this multibyte register can be accessed with the following register names: – NCOxINCU: Accesses the upper byte INC[19:16] – NCOxINCH: Accesses the high byte INC[15:8] – NCOxINCL: Accesses the low byte INC[7:0]. 2. The logical increment spans NCOxINCU:NCOxINCH:NCOxINCL. 3. NCOxINC is double-buffered as INCBUF: – INCBUF is updated on the next falling edge of NCOxCLK after writing to NCOxINCL – NCOxINCU and NCOxINCH will be written prior to writing NCOxINCL. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 497 PIC18F06/16Q41 NCO - Numerically Controlled Oscillator Mo... 32.9 Register Summary - NCO Address Name 0x00 ... 0x043F Reserved 0x0440 NCO1ACC 0x0443 NCO1INC 0x0446 0x0447 NCO1CON NCO1CLK Bit Pos. 7:0 15:8 23:16 7:0 15:8 23:16 7:0 7:0 7 5 4 3 2 1 0 ACC[7:0] ACC[15:8] ACC[19:16] INC[7:0] INC[15:8] INC[19:16] EN © 2020-2021 Microchip Technology Inc. and its subsidiaries 6 OUT POL PWS[2:0] PFM CKS[3:0] Preliminary Datasheet DS40002214E-page 498 PIC18F06/16Q41 DSM - Data Signal Modulator Module 33. DSM - Data Signal Modulator Module The Data Signal Modulator (DSM) is a peripheral that allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. Both the carrier and the modulator signals are supplied to the DSM module either internally, from the output of a peripheral, or externally through an input pin. The modulated output signal is generated by performing a logical “AND” operation of both the carrier and modulator signals, and then provided to the DSM_out pin. The carrier signal is comprised of two distinct and separate signals. A Carrier High (CARH) signal and a Carrier Low (CARL) signal. During the time in which the modulator (MOD) signal is in a Logic High state, the DSM mixes the CARH signal with the modulator signal. When the modulator signal is in a Logic Low state, the DSM mixes the CARL signal with the modulator signal. Using this method, the DSM can generate the following types of key modulation schemes: • • • Frequency Shift Keying (FSK) Phase-Shift Keying (PSK) ON-OFF Keying (OOK) Additionally, the following features are provided within the DSM module: • • • • • Carrier Synchronization Carrier Source Polarity Select Programmable Modulator Data Modulated Output Polarity Select Peripheral Module Disable, which provides the ability to place the DSM module in the lowest power consumption mode The figure below shows a simplified block diagram of the data signal modulator peripheral. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 499 PIC18F06/16Q41 DSM - Data Signal Modulator Module Figure 33-1. Simplified Block Diagram of the Data Signal Modulator CH Data Signal Modulator See MDxCARH Register CARH CHPOL D SYNC Q 1 MS 0 CHSYNC RxyPPS See MDxSRC Register MOD PPS DSM_out OPOL CL D SYNC Q 1 0 See MDxCARL Register CARL CLSYNC CLPOL 33.1 DSM Operation The DSM module is enabled by setting the EN bit. Clearing the EN bit disables the output of the module, but retains the carrier and source signal selections. The module will resume operation when the EN bit is set again. The output of the DSM module can be rerouted to several pins using the PPS output source selection register. When the EN bit is cleared the output pin is held low. 33.1.1 Modulator Signal Sources The modulator signal can be supplied from several different sources, and is selected by configuring the MS bits. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 500 PIC18F06/16Q41 DSM - Data Signal Modulator Module 33.1.2 Carrier Signal Sources The carrier high signal and carrier low signal can be supplied from several different sources, and is selected by the CH bits and CL bits, respectively. 33.2 Carrier Synchronization During the time when the DSM switches between carrier high and carrier low signal sources, the carrier data in the modulated output signal can become truncated. To prevent this, the carrier signal can be synchronized to the modulator signal. When synchronization is enabled, the carrier pulse that is being mixed at the time of the transition is allowed to transition low before the DSM switches over to the next carrier source. Synchronization is enabled separately for the carrier high and carrier low signal sources. Synchronization for the carrier high signal is enabled by setting the CHSYNC bit. Synchronization for the carrier low signal is enabled by setting the CLSYNC bit. The figures below show the timing diagrams of using various synchronization methods. Figure 33-2. On-Off Keying (OOK) Synchronization carrier_low carrier_high Modula tor DSM_out CHSYNC = 1 CLSYNC = 0 DSM_out CHSYNC = 1 CLSYNC = 1 DSM_out CHSYNC = 0 CLSYNC = 0 DSM_out CHSYNC = 0 CLSYNC = 1 Figure 33-3. No Synchronization (CHSYNC = 0, CLSYNC = 0) carrier_high carrier_low Modula tor DSM_out Acti ve Carrier State carrier_high © 2020-2021 Microchip Technology Inc. and its subsidiaries carrier_low Preliminary Datasheet carrier_high carrier_low DS40002214E-page 501 PIC18F06/16Q41 DSM - Data Signal Modulator Module Figure 33-4. Carrier High Synchronization (CHSYNC = 1, CLSYNC = 0) carrier_high carrier_low Modula tor DSM_out Acti ve Carrier State carrier_high both carrier_low carrier_high both carrier_low Figure 33-5. Carrier Low Synchronization (CHSYNC = 0, CLSYNC = 1) carrier_high carrier_low Modula tor DSM_out Acti ve Carrier State carrier_high carrier_low carrier_high carrier_low Figure 33-6. Full Synchronization (CHSYNC = 1, CLSYNC = 1) carrier_high carrier_low Modula tor Falling edg es used to sync DSM_out Acti ve Carrier State 33.3 carrier_high carrier_low carrier_high CL Carrier Source Polarity Select The signal provided from any selected input source for the carrier high and carrier low signals can be inverted. Inverting the signal for the carrier high and low source is enabled by setting the CHPOL bit and the CLPOL bit, respectively. 33.4 Programmable Modulator Data The BIT control bit can used to generate the modulation signal. This gives the user the ability to provide software driven modulation. 33.5 Modulated Output Polarity The modulated output signal provided on the DSM_out pin can also be inverted. Inverting the modulated output signal is enabled by setting the OPOL bit. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 502 PIC18F06/16Q41 DSM - Data Signal Modulator Module 33.6 Operation in Sleep Mode The DSM can operate during Sleep, if the carrier and modulator input sources are also operable during Sleep. Refer to the “Power-Saving Modes” chapter for more details. 33.7 Effects of a Reset Upon any device Reset, the DSM module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. All the registers are reset to their default values. 33.8 Peripheral Module Disable The DSM module can be completely disabled using the PMD module to achieve maximum power saving. When the DSMMD bit of the PMD registers is set, the DSM module is completely disabled. This puts the module in its lowest power consumption state. When enabled again all the registers of the DSM module default to POR status. 33.9 Register Definitions: Modulation Control Long bit name prefixes for the modulation control peripherals are shown in the table below. Refer to the “Long Bit Names” section in the “Register and Bit Naming Conventions” chapter for more information. Table 33-1. Modulation Control Long Bit Name Prefixes Peripheral Bit Name Prefix DSM1 MD1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 503 PIC18F06/16Q41 DSM - Data Signal Modulator Module 33.9.1 MDxCON0 Name:  Address:  MDxCON0 0x6A Modulation Control Register 0 Bit Access Reset 7 EN R/W 0 6 5 OUT R/W 0 4 OPOL R/W 0 3 2 1 0 BIT R/W 0 Bit 7 – EN Modulator Module Enable Value Description 1 DSM is enabled and mixing input signals 0 DSM is disabled and has no output Bit 5 – OUT  Modulator Output(1) Displays the current DSM_out value Bit 4 – OPOL Modulator Output Polarity Select Value Description 1 DSM output signal is inverted; idle high output 0 DSM output signal is not inverted; idle low output Bit 0 – BIT  Modulation Source Signal(2) Allows direct software control of the modulation signal Notes:  1. The modulated output frequency can be greater and asynchronous from the clock that updates this register bit. The bit value may not be valid for higher speed modulator or carrier signals. 2. MDBIT must be selected as the modulation source in the MDxSRC register for this operation. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 504 PIC18F06/16Q41 DSM - Data Signal Modulator Module 33.9.2 MDxCON1 Name:  Address:  MDxCON1 0x6B Modulation Control Register 1 Bit 7 Access Reset 6 5 CHPOL R/W 0 4 CHSYNC R/W 0 3 2 1 CLPOL R/W 0 0 CLSYNC R/W 0 Bit 5 – CHPOL Modulator High Carrier Polarity Select Value Description 1 Selected high carrier signal is inverted 0 Selected high carrier signal is not inverted Bit 4 – CHSYNC Modulator High Carrier Synchronization Enable Value Description 1 Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low time carrier 0 Modulator output is not synchronized to the high time carrier signal(1) Bit 1 – CLPOL Modulator Low Carrier Polarity Select Value Description 1 Selected low carrier signal is inverted 0 Selected low carrier signal is not inverted Bit 0 – CLSYNC Modulator Low Carrier Synchronization Enable Value Description 1 Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high time carrier 0 Modulator output is not synchronized to the low time carrier signal(1) Note:  1. Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 505 PIC18F06/16Q41 DSM - Data Signal Modulator Module 33.9.3 MDxCARH Name:  Address:  MDxCARH 0x6E Modulation High Carrier Control Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 CH[3:0] Access Reset R/W 0 R/W 0 Bits 3:0 – CH[3:0] Modulator Carrier High Selection CH Connection 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Reserved Reserved CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT NCO1_OUT PWM3S1P1_OUT PWM2S1P1_OUT PWM1S1P1_OUT CCP1_OUT CLKREF_OUT EXTOSC HFINTOSC FOSC (System Clock) Pin selected by MDCARHPPS © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 506 PIC18F06/16Q41 DSM - Data Signal Modulator Module 33.9.4 MDxCARL Name:  Address:  MDxCARL 0x6D Modulation Low Carrier Control Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 CL[3:0] Access Reset R/W 0 R/W 0 Bits 3:0 – CL[3:0] Modulator Carrier Low Input Selection CL Connection 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Reserved Reserved CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT NCO1_OUT PWM3S1P2_OUT PWM2S1P2_OUT PWM1S1P2_OUT CCP1_OUT CLKREF_OUT EXTOSC HFINTOSC FOSC (System Clock) Pin selected by MDCARLPPS © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 507 PIC18F06/16Q41 DSM - Data Signal Modulator Module 33.9.5 MDxSRC Name:  Address:  MDxSRC 0x6C Modulation Source Control Register Bit 7 6 5 Access Reset 4 3 R/W 0 R/W 0 2 MS[4:0] R/W 0 1 0 R/W 0 R/W 0 Bits 4:0 – MS[4:0] Modulator Source Selection MS Connection 10101 - 11111 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 Reserved SPI2_SDO SPI1_SDO UART3_TX UART2_TX UART1_TX CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT CMP2_OUT CMP1_OUT NCO1_OUT PWM3S1P2_OUT PWM3S1P1_OUT PWM2S1P2_OUT PWM2S1P1_OUT PWM1S1P2_OUT PWM1S1P1_OUT CCP1_OUT MDBIT Pin selected by MDSRCPPS © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 508 PIC18F06/16Q41 DSM - Data Signal Modulator Module 33.10 Address 0x00 ... 0x69 0x6A 0x6B 0x6C 0x6D 0x6E Register Summary - DSM Name Bit Pos. 7 7:0 7:0 7:0 7:0 7:0 EN 6 5 4 OUT CHPOL OPOL CHSYNC 3 2 1 0 CLPOL BIT CLSYNC Reserved MD1CON0 MD1CON1 MD1SRC MD1CARL MD1CARH © 2020-2021 Microchip Technology Inc. and its subsidiaries MS[4:0] CL[3:0] CH[3:0] Preliminary Datasheet DS40002214E-page 509 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34. UART - Universal Asynchronous Receiver Transmitter with Protocol Support The Universal Asynchronous Receiver Transmitter (UART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer, independent of device program execution. The UART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or one of several automated protocols. The Full Duplex mode is useful for communications with peripheral systems, such as wireless modems and USB to serial interface modules. Supported protocols include: • • • LIN Host and Client DMX Controller and Receiver DALI Control Gear and Control Device The UART module includes the following capabilities: • • • • • • • • • • • • • • • • • • Half and full-duplex asynchronous transmit and receive Two-byte input buffer One-byte output buffer Programmable 7-bit or 8-bit byte width 9th bit address detection 9th bit even or odd parity Input buffer overrun error detection Receive framing error detection Hardware and software flow control Automatic checksum calculation and verification Programmable 1, 1.5, and 2 Stop bits Programmable data polarity Manchester encoder/decoder Operation in Sleep Automatic detection and calibration of the baud rate Wake-up on Break reception Automatic and user timed Break period generation RX and TX inactivity time-outs (with Timer2) The operation of the UART module is controlled through 19 8-bit registers: • • • • • • • • • Three control registers (UxCON0-UxCON2) Error enable and status (UxERRIE, UxERRIR, UxUIR) UART buffer status and control (UxFIFO) Three 9-bit protocol parameters (UxP1-UxP3) 16-bit Baud Rate Generator (UxBRG) Transmit buffer write (UxTXB) Receive buffer read (UxRXB) Receive checksum (UxRXCHK) Transmit checksum (UxTXCHK) The UART transmit output (TX_out) is available to the TX pin and internally to various peripherals. Block diagrams of the UART transmitter and receiver are shown in the following figures. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 510 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... Figure 34-1. UART Transmitter Block Diagram Data bus Rev. 10-000113D 11/2/2018 8 UxTXIE Interrupt FIFO (if equipped) UxTXB register UxTXIF 8 UxTXCHK + TXEN MSb LSb (8) 0 RxyPPS TX pin Mode Control Transmit Shift Register (TSR) PPS TX_out Baud Rate Generator FOSC TXMTIF Address or Parity mode ÷n n +1 Multiplier x4 x16 BRGS 1 0 UxBRGH UxBRGL Figure 34-2. UART Receiver Block Diagram Rev. 10-000114C 11/2/2018 RXFOIF RXIDL RXEN RXPPS RSR Register MSb RX pin Pin Buffer and Control PPS Baud Rate Generator FOSC Mode Data Recovery Stop (8) 0 Start UxRXCHK + Address or Parity Mode Multiplier x4 x16 BRGS 1 0 UxBRGH UxBRGL 1 ÷n n +1 7 LSb FERIF PERIF UxRXB Register FIFO 8 Data Bus UxRXIF UxRXIE 34.1 Interrupt UART I/O Pin Configuration The RX input pin is selected with the UxRPPS register. The TX output pin is selected with each pin’s RxyPPS register. When the TRIS control for the pin corresponding to the TX output is cleared, the UART will control the logic level on the TX pin. Changing the TXPOL bit in UxCON2 will immediately change the TX pin logic level, regardless of the value of EN or TXEN. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 511 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.2 UART Asynchronous Modes The UART has five Asynchronous modes: • • • • • 7-bit 8-bit 8-bit with even parity in the 9th bit 8-bit with odd parity in the 9th bit 8-bit with address indicator in the 9th bit The UART transmits and receives data using the standard Non-Return-to-Zero (NRZ) format. NRZ is implemented with two levels: A VOH Mark state, which represents a ‘1’ data bit, and a VOL Space state, which represents a ‘0’ data bit. NRZ implies that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state. Each character transmission consists of one Start bit followed by seven or eight data bits, one optional parity or address bit, and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is eight bits with no parity. Each transmitted bit persists for a period of 1/ (Baud Rate). An on-chip dedicated 16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See the UART Baud Rate Generator section for more information. In all Asynchronous modes, the UART transmits and receives the LSb first. The UART’s transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is supported by the hardware with even and odd parity modes. 34.2.1 UART Asynchronous Transmitter The UART transmitter block diagram is shown in Figure 34-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the UxTXB register. 34.2.1.1 Enabling the Transmitter The UART transmitter is enabled for asynchronous operations by configuring the following control bits: • TXEN = 1 • MODE = 0000 through 0011 • • • • UxBRG = desired baud rate BRGS = desired baud rate multiplier RxyPPS = code for desired output pin ON = 1 All other UART control bits are assumed to be in their default state. Setting the TXEN bit enables the transmitter circuitry of the UART. The MODE bits select the desired mode. Setting the ON bit enables the UART. When TXEN is set and the transmitter is not Idle, the TX pin is automatically configured as an output. When the transmitter is Idle, the TX pin drive is relinquished to the port TRIS control. If the TX pin is shared with an analog peripheral, the analog I/O function will be disabled by clearing the corresponding ANSEL bit. Important:  The UxTXIF Transmitter Interrupt flag is set when the TXEN Enable bit is set and the UxTXB register can accept data. 34.2.1.2 Transmitting Data A transmission is initiated by writing a character to the UxTXB register. If this is the first character, or the previous character has been completely transmitted from the TSR, the data in the UxTXB is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the UxTXB until the previous character transmission is complete. The pending character in the UxTXB is then transferred to the TSR at the beginning of the previous character Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the completion of all of the previous character’s Stop bits. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 512 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.2.1.3 Transmit Data Polarity The polarity of the transmit data is controlled with the TXPOL bit. The default state of this bit is ‘0’, which selects high true transmit Idle and data bits. Setting the TXPOL bit to ‘1’ will invert the transmit data, resulting in low true Idle and data bits. The TXPOL bit controls transmit data polarity in all modes. 34.2.1.4 Transmit Interrupt Flag The UxTXIF Interrupt Flag bit in the PIR register is set whenever the UART transmitter is enabled and no character is being held for transmission in the UxTXB register. In other words, the UxTXIF bit is clear only when the TSR is busy with a character and a new character has been queued for transmission in the UxTXB register. The UxTXIF interrupt is enabled by setting the UxTXIE Interrupt Enable bit in the PIE register. However, the UxTXIF Flag bit will be set whenever the UxTXB register is empty, regardless of the state of the UxTXIE Enable bit. The UxTXIF bit is read-only and cannot be set or cleared by software. To use interrupts when transmitting data, set the UxTXIE bit only when there is more data to send. Clear the UxTXIE Interrupt Enable bit upon writing the UxTXB register with the last character of the transmission. 34.2.1.5 TSR Status The TXMTIF bit indicates the status of the TSR. This is a read-only bit. The TXMTIF bit is set when the TSR is empty and Idle. The TXMTIF bit is cleared when a character is transferred to the TSR from the UxTXB. The TXMTIF bit remains clear until all bits, including the Stop bits, have been shifted out of the TSR and a byte is not waiting in the UxTXB register. The TXMTIF will generate a summary UxEIF interrupt when the TXMTIE bit is set. Important:  The TSR is not mapped in data memory, so it is not available to the user. 34.2.1.6 Transmitter 7-Bit Mode The 7-bit mode is selected when the MODE bits are set to ‘0001’. In 7-bit mode, only the seven Least Significant bits of the data written to UxTXB are transmitted. The Most Significant bit is ignored. 34.2.1.7 Transmitter Parity Modes When Odd or Even Parity mode is selected, all data is sent as nine bits. The first eight bits are data and the 9th bit is parity. Even and odd parity is selected when the MODE bits are set to ‘0011’ and ‘0010’, respectively. Parity is automatically determined by the module and inserted in the serial data stream. 34.2.1.8 Asynchronous Transmission Setup Use the following steps as a guide for configuring the UART for asynchronous transmissions. 1. 2. 3. 4. 5. 6. 7. 8. 9. Initialize the UxBRG register pair and the BRGS bit to achieve the desired baud rate. Set the MODE bits to the desired Asynchronous mode. Set the TXPOL bit if inverted TX output is desired. Enable the asynchronous serial port by setting the ON bit. Enable the transmitter by setting the TXEN Control bit. This will cause the UxTXIF Interrupt flag to be set. If the device has PPS, configure the desired I/O pin RxyPPS register with the code for the TX output. If interrupts are desired, set the UxTXIE Interrupt Enable bit in the respective PIE register. An interrupt will occur immediately provided that global interrupts are also enabled. Write one byte of data into the UxTXB register. This will start the transmission. Subsequent bytes may be written when the UxTXIF bit is ‘1’. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 513 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... Figure 34-3. UART Asynchronous Transmission Rev. 10-000115B 9/1/2017 Word 1 Write to UxTXB BRG Output (Shift Clock) TX pin UxTXIF (Transmit Buffer Reg Empty Flag) bit TXMTIF (Transmit Shift Reg Empty Flag) bit Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 1 TCY Figure 34-4. UART Asynchronous Transmission (Back-to-Back) Word 1 Rev. 10-000116B 9/1/2017 Word 2 Write to UxTXB BRG Output (Shift Clock) TX pin UxTXIF (Transmit Buffer Reg Empty Flag) bit TXMTIF (Transmit Shift Reg Empty Flag) bit 34.2.2 Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit Word 1 bit 0 Word 2 1 TCY UART Asynchronous Receiver The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 34-2. The data is received on the RX pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 4 or 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all bits of the character have been shifted in, they are immediately transferred to a two-character First-In First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must begin servicing the UART receiver. The FIFO registers and RSR are not directly accessible by software. Access to the received data is made via the UxRXB register. 34.2.2.1 Enabling the Receiver The UART receiver is enabled for asynchronous operation by configuring the following control bits: • RXEN = 1 • MODE = 0000 through 0011 • • • • UxBRG = desired baud rate BRGS = desired baud rate multiplier RXPPS = code for desired input pin Input pin ANSEL bit = 0 • ON = 1 All other UART control bits are assumed to be in their default state. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 514 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... Setting the RXEN bit enables the receiver circuitry of the UART. Setting the MODE bits configures the UART for the desired Asynchronous mode. Setting the ON bit enables the UART. The TRIS bit corresponding to the selected RX I/O pin must be set to configure the pin as an input. Important:  If the RX function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. 34.2.2.2 Receiving Data Data is recovered from the bit stream by timing to the center of the bits and sampling the input level. In High Speed mode, there are four BRG clocks per bit and only one sample is taken per bit. In Normal Speed mode, there are 16 BRG clocks per bit and three samples are taken per bit. The receiver data recovery circuit initiates character reception on the falling edge of the Start bit. The Start bit is always a ‘0’. The Start bit is qualified in the middle of the bit. In Normal Speed mode only, the Start bit is also qualified at the leading edge of the bit. The following paragraphs describe the majority-detect sampling of the Normal Speed mode without inverted polarity. The falling edge starts the Baud Rate Generator (BRG) clock. The input is sampled at the first and second BRG clocks. If both samples are high, then the falling edge is deemed a glitch and the UART returns to the Start bit detection state without generating an error. If either sample is low, the data recovery circuit continues counting BRG clocks and takes samples at clock counts: 7, 8 and 9. When less than two samples are low, the Start bit is deemed invalid and the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. When two or more samples are low, the Start bit is deemed valid and the data recovery continues. After a valid Start bit is detected, the BRG clock counter continues and resets at count 16. This is the beginning of the first data bit. The data recovery circuit counts the BRG clocks from the beginning of the bit and takes samples at clocks 7, 8 and 9. The bit value is determined from the majority of the samples. The resulting ‘0’ or ‘1’ is shifted into the RSR. The BRG clock counter continues and resets at count 16. This sequence repeats until all data bits have been sampled and shifted into the RSR. After all data bits have been shifted in, the first Stop bit is sampled. Stop bits are always a ‘1’. If the bit sampling determines that a ‘0’ is in the Stop bit position, the framing error is set for this character. Otherwise, the framing error is cleared for this character. See the Receive Framing Error section for more information on framing errors. 34.2.2.3 Receive Data Polarity The polarity of the receive data is controlled with the RXPOL bit. The default state of this bit is ‘0’, which selects high true receive Idle and data bits. Setting the RXPOL bit to ‘1’ will invert the receive data, resulting in low true Idle and data bits. The RXPOL bit controls receive data polarity in all modes. 34.2.2.4 Receive Interrupts Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the UART receive FIFO. The UxRXIF Interrupt flag in the respective PIR register is set at this time, provided it is not being suppressed. The UxRXIF is suppressed by any of the following: • • FERIF when FERIE is set PERIF when PERIE is set When the UART uses DMA for reception, suppressing the UxRXIF suspends the DMA transfer of data until software processes the error and reads UxRXB to advance the FIFO beyond the error. The UxRXIF interrupts are enabled by setting all of the following bits: • • UxRXIE, Interrupt Enable bit in the PIE register Global Interrupt Enable bits © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 515 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... The UxRXIF Interrupt Flag bit will be set when it is not suppressed and there is an unread character in the FIFO, regardless of the state of interrupt enable bits. Reading the UxRXB register will transfer the top character out of the FIFO and reduce the FIFO contents by one. The UxRXIF Interrupt Flag bit is read-only and therefore cannot be set or cleared by software. 34.2.2.5 Receive Framing Error Each character in the receive FIFO buffer has a corresponding Framing Error Flag bit. A framing error indicates that the Stop bit was not seen at the expected time. For example, a Break condition will be received as a 0x00 byte with the framing error bit set. The Framing Error flag is accessed via the FERIF bit. The FERIF bit represents the frame status of the top unread character of the receive FIFO. Therefore, the FERIF bit must be read before reading UxRXB. The FERIF bit is read-only and only applies to the top unread character of the receive FIFO. A framing error (FERIF = 1) does not preclude reception of additional characters. It is neither necessary nor possible to clear the FERIF bit directly. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error, if any. The FERIF bit is cleared when the character at the top of the FIFO does not have a framing error or when all bytes in the receive FIFO have been read. Clearing the ON bit resets the receive FIFO, thereby also clearing the FERIF bit. A framing error will generate a summary UxEIF interrupt when the FERIE bit is set. The summary error is reset when the FERIF bit of the top of the FIFO is ‘0’ or when all FIFO characters have been retrieved. Important:  When FERIE is set, UxRXIF interrupts are suppressed by FERIF = 1. 34.2.2.6 Receiver Parity Modes Even or odd parity is automatically detected when the MODE bits are set to ‘0011’ or ‘0010’, respectively. The parity modes receive eight data bits and one parity bit for a total of nine bits for each character. The PERIF bit represents the parity error of the top unread character of the receive FIFO rather than the parity bit itself. The parity error must be read before the UxRXB register is read because reading the UxRXB register will advance the FIFO pointer to the next byte with its associated PERIF flag. A parity error will generate a summary UxEIF interrupt when the PERIE bit is set. The summary error is reset when the PERIF bit of the top of the FIFO is ‘0’ or when all FIFO characters have been retrieved. Important:  When PERIE is set, the UxRXIF interrupts are suppressed by PERIF = 1. 34.2.2.7 Receive FIFO Overflow When more characters are received than the receive FIFO can hold, the RXFOIF bit is set. The character causing the Overflow condition is discarded. The RUNOVF bit determines how the receive circuit responds to characters while the Overflow condition persists. When RUNOVF is set, the receive shifter stays synchronized to the incoming data stream by responding to Start, data, and Stop bits. However, all received bytes not already in the FIFO are discarded. When RUNOVF is cleared, the receive shifter ceases operation and Start, data, and Stop bits are ignored. The Receive Overflow condition is cleared by reading the UxRXB register and clearing the RXFOIF bit. If the UxRXB register is not read, thereby opening a space in the FIFO, the next character received will be discarded and cause another Overflow condition. A receive overflow error will generate a summary UxEIF interrupt when the RXFOIE bit is set. 34.2.2.8 Asynchronous Reception Setup Use the following steps as a guide for configuring the UART for asynchronous reception: 1. Initialize the UxBRG register pair and the BRGS bit to achieve the desired baud rate. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 516 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 2. 3. 4. 5. 6. 7. 8. 9. 10. Configure the RXPPS register for the desired RX pin. Clear the ANSEL bit for the RX pin (if applicable). Set the MODE bits to the desired Asynchronous mode. Set the RXPOL bit if the data stream is inverted. Enable the serial port by setting the ON bit. If interrupts are desired, set the UxRXIE bit in the PIEx register and enable global interrupts. Enable reception by setting the RXEN bit. Read the UxERRIR register to get the error flags. The UxRXIF Interrupt Flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the UxRXIE interrupt enable bit is also set. 11. Read the UxRXB register to get the received byte. 12. If an overrun occurred, clear the RXFOIF bit. Figure 34-5. UART Asynchronous Reception Rev. 10-000117B 1/24/2019 RX pin Start bit bit 0 Last bit Stop bit Start bit Word 1 Rcv Shift Reg Rcv Buffer Reg bit 0 Last bit Stop bit Start bit Word 2 Word 1 UxRXB bit 0 Last bit Stop bit Word 3 Word 2 UxRXB RXIDL Read UxRXB UxRXIF (Interrupt flag) RXFOIF Flag Cleared by software Note: This timing diagram shows three bytes appearing on the RX input. The UxRXB is not read before the third word is received, causing the RXFOIF (FIFO overrun) bit to be set. STPMD = 0, STP = 00. 34.2.3 Asynchronous Address Mode A special Address Detection mode is available for use when multiple receivers share the same transmission line, as seen in RS-485 systems. When Asynchronous Address mode is enabled, all data is transmitted and received as 9-bit characters. The 9th bit determines whether the character is address or data. When the 9th bit is set, the eight Least Significant bits are the address. When the 9th bit is clear, the Least Significant bits are data. In either case, the 9th bit is stored in PERIF when the byte is written to the receive FIFO. When PERIE is also set, the RXIF will be suppressed, thereby suspending DMA transfers allowing software to process the received address. An address character will enable all receivers that match the address and disable all other receivers. Once a receiver is enabled, all non-address characters will be received until an address character that does not match is received. 34.2.3.1 Address Mode Transmit The UART transmitter is enabled for asynchronous address operation by configuring the following control bits: • TXEN = 1 • MODE = 0100 • UxBRG = desired baud rate © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 517 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... • • • BRGS = desired baud rate multiplier RxyPPS = code for desired output pin ON = 1 Addresses are sent by writing to the UxP1L register. This transmits the written byte with the 9th bit set, which indicates that the byte is an address. Data is sent by writing to the UxTXB register. This transmits the written byte with the 9th bit cleared, which indicates that the byte is data. To send data to a particular device on the transmission bus, first transmit the address of the intended device. All subsequent data will be accepted only by that device until an address of another device is transmitted. Writes to UxP1L take precedence over writes to UxTXB. When both the UxP1L and UxTXB registers are written while the TSR is busy, the next byte to be transmitted will be from UxP1L. To ensure all data intended for one device are sent before the address is changed, wait until the TXMTIF bit is high before writing UxP1L with the new address. 34.2.3.2 Address Mode Receive The UART receiver is enabled for asynchronous address operation by configuring the following control bits: • RXEN = 1 • MODE = 0100 • • • • UxBRG = desired baud rate BRGS = desired baud rate multiplier RXPPS = code for desired input pin Input pin ANSEL bit = 0 • • • UxP2L = receiver address UxP3L = address mask ON = 1 In Address mode, no data will be transferred to the input FIFO until a valid address is received. This is the default state. Any of the following conditions will cause the UART to revert to the default state: • ON = 0 • RXEN = 0 • Received address does not match When a character with the 9th bit set is received, the Least Significant eight bits of that character will be qualified by the values in the UxP2L and UxP3L registers. The byte is XORed with UxP2L then ANDed with UxP3L. A match occurs when the result is 0h, in which case, the unaltered received character is stored in the receive FIFO, thereby setting the UxRXIF Interrupt bit. The 9th bit is stored in the corresponding PERIF bit, identifying this byte as an address. An address match also enables the receiver for all data such that all subsequent characters without the 9th bit set will be stored in the receive FIFO. When the 9th bit is set and a match does not occur, the character is not stored in the receive FIFO and all subsequent data is ignored. The UxP3L register mask allows a range of addresses to be accepted. Software can then determine the sub-address of the range by processing the received address character. 34.3 DMX Mode (Full-Featured UARTs Only) DMX is a protocol used in stage and show equipment. This includes lighting, fog machines, motors, etc. The protocol consists of a controller that sends out commands, and a receiver such as theater lights that receive these commands. The DMX protocol is usually unidirectional, but can be a bidirectional protocol in either Half or Full Duplex mode. An example of a Half Duplex mode is the RDM (Remote Device Management) protocol that sits on DMX512A. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 518 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... The controller transmits commands and the receiver receives them. There are no Error conditions or retransmit mechanisms. DMX, or DMX512A, consists of a “universe” of 512 channels. This means that one controller can output up to 512 bytes on a single DMX link. Each piece of equipment on the line is programmed to listen to a consecutive sequence of one or more of these bytes. For example, a fog machine connected to one of the universes may be programmed to receive one byte, starting at byte number 10, and a lighting unit may be programmed to receive four bytes starting at byte number 22. 34.3.1 DMX Controller The DMX Controller mode is configured with the following settings: • MODE = 1010 • TXEN = 1 • RXEN = 0 • TXPOL = 0 • • • UxP1 = one less than the number of bytes to transmit (excluding the Start code) UxBRG = value to achieve 250K baud rate STP = 10 for two Stop bits • • RxyPPS = TX pin output code ON = 1 Each DMX transmission begins with a Break followed by a byte called the “Start Code”. The width of the Break is fixed at 25 bit times. The Break is followed by a “Mark After Break” (MAB) Idle period. After this Idle period, the first through the ‘n’th byte is transmitted, where ‘n-1’ is the value in UxP1. See the following figure. Figure 34-6. DMX Transmit Sequence Start Code Byte 1 Byte 2 Byte 3 Rev. 10-000329A 9/5/2017 Start Code Byte 1 Byte n Write to UxTXB TX pin Break MAB(1) Start Code Byte 1 Byte 2 Byte n Software Delay Break MAB(1) Start Code UxTXIF (Transmit Buffer Reg Empty Flag) bit TXMTIF (Transmit Shift Reg Empty Flag) bit TXEN (optional synchronization) bit Note: 1. The MAB period is fixed at 3 bit times. Software sends the Start Code and the ‘n’ data bytes by writing the UxTXB register with each byte to be sent in the desired order. A UxTXIF value of ‘1’ indicates when the UxTXB is ready to accept the next byte. The internal byte counter is not accessible to software. Software needs to keep track of the number of bytes written to UxTXB to ensure that no more and no less than ‘n’ bytes are sent because the DMX state machine will automatically insert a Break and reset its internal counter after ‘n’ bytes are written. One way to ensure synchronization between hardware and software is to toggle TXEN after the last byte of the universe is completely free of the transmit shift register, as indicated by the TXMTIF bit. 34.3.2 DMX Receiver The DMX Receiver mode is configured with the following settings: • MODE = 1010 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 519 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... • TXEN = 0 • RXEN = 1 • RXPOL = 0 • • • • UxP2 = number of first byte to receive UxP3 = number of last byte to receive UxBRG = value to achieve 250K baud rate STP = 10 for two Stop bits • ON = 1 • • UxRXPPS = code for desired input pin Input pin ANSEL bit = 0 When configured as a DMX Receiver, the UART listens for a Break character that is at least 23 bit periods wide. If the Break is shorter than 23 bit times, the Break is ignored and the DMX state machine remains in Idle mode. Upon receiving the Break, the DMX counters will be reset to align with the incoming data stream. Immediately after the Break, the UART will see the “Mark after Break” (MAB). This space is ignored by the UART. The Start Code follows the MAB and will always be stored in the receive FIFO. After the Start Code, the first through the 512th byte will be received, but not all of them are stored in the receive FIFO. The UART ignores all received bytes until the ones of interest are received. This is done using the UxP2 and UxP3 registers. The UxP2 register holds the value of the byte number to start the receive process. The byte counter starts at ‘0’ for the first byte after the Start Code. For example, to receive four bytes starting at the 10th byte after the Start Code, write 009h (9 decimal) to UxP2H:L and 00Ch (12 decimal) to UxP3H:L. The receive FIFO depth is limited, therefore the bytes must be retrieved by reading UxRXB as they come in to avoid a receive FIFO Overrun condition. Typically, two Stop bits are inserted between bytes. If either Stop bit is detected as a ‘0’, the framing error for that byte will be set. Since the DMX sequence always starts with a Break, the software can verify that it is in sync with the sequence by monitoring the RXBKIF flag to ensure that the next byte received after the RXBKIF flag is processed as the Start Code and subsequent bytes are processed as the expected data. 34.4 LIN Modes (Full-Featured UARTs Only) LIN is a protocol used primarily in automotive applications. The LIN network consists of two kinds of software processes: A Host process and a Client process. Each network has only one Host process and one or more Client processes. From a physical layer point of view, the UART on one processor may be driven by both a Host and a Client process, as long as only one Host process exists on the network. A LIN transaction consists of a Host process followed by a Client process. The Client process may involve more than one client where one is transmitting and the other(s) receiving. The transaction begins by the following Host process transmission sequence: 1. 2. 3. 4. Break. Delimiter bit. Sync Field. PID byte. The PID determines which Client processes are expected to respond to the host. When the PID byte is complete, the TX output remains in the Idle state. One or more of the Client processes may respond to the Host process. If no one responds within the inter-byte period, the host is free to start another transmission. The inter-byte period is timed by software using a means other than the UART. The Client process follows the Host process. When the client software recognizes the PID, that Client process responds by either transmitting the required response or by receiving the transmitted data. Only Client processes send data. Therefore, Client processes receiving data are receiving that of another Client process. When a client sends data, the client UART automatically calculates the checksum for the transmitted bytes as they are sent and appends the inverted checksum byte to the client response. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 520 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... When a client receives data, the checksum is accumulated on each byte as it is received using the same algorithm as the sending process. The last byte, which is the inverted checksum value calculated by the sending process, is added to the locally calculated checksum by the UART. The check passes when the result is all ‘1’s, otherwise the check fails and the CERIF bit is set. Two methods for computing the checksum are available: legacy and enhanced. The legacy checksum includes only the data bytes. The enhanced checksum includes the PID and the data. The C0EN control bit determines the checksum method. Setting C0EN to ‘1’ selects the enhanced method. Software must select the appropriate method before the Start bit of the checksum byte is received. 34.4.1 LIN Host/Client Mode The LIN Host mode includes capabilities to generate client processes. The host process stops at the PID transmission. Any data that is transmitted in Host/Client mode is done as a client process. LIN Host/Client mode is configured by the following settings: • MODE = 1100 • TXEN = 1 • RXEN = 1 • • UxBRG = value to achieve desired baud rate TXPOL = 0 (for high Idle state) • • • • STP = desired Stop bits selection C0EN = desired Checksum mode RxyPPS = TX pin selection code TX pin TRIS control = 0 • ON = 1 Important:  The TXEN bit must be set before the Host process is received and remain set while in LIN mode whether or not the Client process is a transmitter. The Host process is started by writing the PID to the UxP1L register when UxP2 is ‘0’ and the UART is Idle. The UxTXIF will not be set in this case. Only the six Least Significant bits of UxP1L are used in the PID transmission. The two Most Significant bits of the transmitted PID are PID parity bits. PID[6] is the exclusive-or of PID bits 0, 1, 2 and 4. PID[7] is the inverse of the exclusive-or of PID bits 1, 3, 4 and 5. The UART hardware calculates and inserts these bits in the serial stream. Writing UxP1L automatically clears the UxTXCHK and UxRXCHK registers and generates the Break, the delimiter bit, the Sync character (55h), and the PID transmission portion of the transaction. The data portion of the transaction that follows, if there is one, is a Client process. See the LIN Client Mode section for more details of that process. The host receives its own PID if RXEN is set. Software performs the Client process corresponding to the PID that was sent and received. Attempting to write UxP1L before an active Host process is complete will not succeed. Instead, the TXWRE bit will be set. 34.4.2 LIN Client Mode The LIN Client mode is configured by the following settings: • MODE = 1011 • TXEN = 1 • RXEN = 1 • • • • UxP2 = number of data bytes to transmit UxP3 = number of data bytes to receive UxBRG = value to achieve default baud rate TXPOL = 0 (for high Idle state) • STP = desired Stop bits selection © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 521 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... • • • C0EN = desired Checksum mode RxyPPS = TX pin selection code TX pin TRIS control = 0 • ON = 1 The Client process starts upon detecting a Break on the RX pin. The Break clears the UxTXCHK, UxRXCHK, UxP2 and UxP3 registers. At the end of the Break, the auto-baud circuity is activated and the baud rate is automatically set using the Sync character following the Break. The character following the Sync character is received as the PID code and is saved in the receive FIFO. The UART computes the two PID parity bits from the six Least Significant bits of the PID. If either parity bit does not match the corresponding bit of the received PID code, the PERIF flag is set and saved at the same FIFO location as the PID code. The UxRXIF bit is set indicating that the PID is available. Software retrieves the PID by reading the UxRXB register and determines the Client process to execute from that. The checksum method, number of data bytes, and whether to send or receive data are defined by software according to the PID code. 34.4.2.1 LIN Client Receiver When the Client process is a Receiver, the software performs the following tasks: • • • The UxP3 register is written with a value equal to the number of data bytes to receive. The C0EN bit is set or cleared to select the appropriate checksum. This must be completed before the Start bit of the checksum byte is received. Each byte of the process response is read from UxRXB when UxRXIF is set. The UART updates the checksum on each received byte. When the last data byte is received, the computed checksum total is stored in the UxRXCHK register. The next received byte is saved in the receive FIFO and added with the value in UxRXCHK. The result of this addition is not accessible. However, if the result is not all ‘1’s, the CERIF bit is set. The CERIF flag persists until cleared by software. Software needs to read UxRXB to remove the checksum byte from the FIFO, but the byte can be discarded if not needed for any other purpose. After the checksum is received, the UART ignores all activity on the RX pin until a Break starts the next transaction. 34.4.2.2 LIN Client Transmitter When the Client process is a transmitter, software performs the following tasks in the order shown: • The UxP2 register is written with a value equal to the number of bytes to transmit. This will enable the UxTXIF flag which is disabled when UxP2 is ‘0’. • • The C0EN bit is set or cleared to select the appropriate checksum Each byte of the process response is written to UxTXB when UxTXIF is set The UART accumulates the checksum as each byte is written to UxTXB. After the last byte is written, the UART stores the calculated checksum in the UxTXCHK register and transmits the inverted result as the last byte in the response. The UxTXIF flag is disabled when the number of bytes specified by the value in the UxP2 register have been written. Any writes to UxTXB that exceed the UxP2 count will be ignored and set the TXWRE flag. 34.5 DALI Mode (Full-Featured UARTs Only) DALI is a protocol used for intelligent lighting control for building automation. The protocol consists of Control Devices and Control Gear. A Control Device is an application controller that sends out commands to the light fixtures. The light fixture itself is termed as a Control Gear. The communication is done using Manchester encoding, which is performed by the UART hardware. Manchester encoding consists of the clock and data in a single bit stream (refer to Figure 34-9). A high-to-low or a low-to-high transition always occurs in the middle of the bit period and may or may not occur at the bit period boundaries. When the consecutive bits in the bit stream are of the same value (i.e., consecutive ‘1’s or consecutive ‘0’s) a transition occurs at the bit boundary. However, when the bit value changes, there is no transition at the bit boundary. According to the standard, a half-bit time is typically 416.7 μs long. A double half-bit time or a single bit is typically 833.3 μs. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 522 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... The protocol is inherently half-duplex. Communication over the bus occurs in the form of forward and backward frames. Wait times between the frames are defined in the standard to prevent collision between the frames. A Control Device transmission is termed as the forward frame. In the DALI 2.0 standard, a forward frame can be two or three bytes in length. The two-byte forward frame is used for communication between Control Device and Control Gear whereas the three-byte forward frame is used for communication between Control Devices on the bus. The first byte in the forward frame is the control byte and is followed by either one or two data bytes. The transaction begins when the Control Device starts a transmission. Unlike other protocols, each byte in the frame is transmitted MSb first. Typical frame timing is shown below. Figure 34-7. DALI Frame Timing Control Code Control Code Byte 1 Byte 1 Rev. 10-000331A 9/5/2017 Write to UxTXB Start bit TX pin Stop bits CC CC CC byte1 Wait Period Start bit byte1 UxTXIF (Transmit Buffer Reg Empty Flag) bit TXMTIF (Transmit Shift Reg Empty Flag) bit During the communication between two Control Devices, three bytes are required to be transmitted. In this case, the software must write the third byte to UxTXB as soon as UxTXIF goes true and before the output shifter becomes empty. This ensures that the three bytes of the forward frame are transmitted back-to-back without any interruption. All Control Gear on the bus receive the forward frame. If the forward frame requires a reply to be sent, one of the Control Gear may respond with a single byte, called the backward frame. The 2.0 standard requires the Control Gear to begin transmission of the backward frame between 5.5 ms to 10.5 ms (~14 to 22 half-bit times) after reception of the forward frame. Once the backward frame is received by the Control Device, it is required to wait a minimum of 2.4 ms (~6 half-bit times). After this wait time, the Control Device is free to transmit another forward frame. Refer to the figure below. Figure 34-8. DALI Forward/Backward Frame Timing Rev. 10-000332A 9/7/2017 forward wait period Device TX Forward Frame forward wait period Forward Frame Gear TX backward wait period Forward Frame Backward Frame Gear UxTXB write A Start bit is used to indicate the start of the forward and backward frames. When ABDEN = 0, the receiver bit rate is determined by the BRG register. When ABDEN = 1, the first bit synchronizes the receiver with the transmitter and sets the receiver bit rate. The low period of the Start bit is measured and is used as the timing reference for all data bits in the forward and backward frames. The ABDOVF bit is set if the Start bit low period causes the measurement counter to overflow. All the bits following the Start bit are data bits. The bit stream terminates when no transition is detected in the middle of a bit period. Refer to the figure below. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 523 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... Figure 34-9. Manchester Timing Rev. 10-000330A 9/5/2017 Byte 0 Byte 1 Byte 0 Write to UxTXB Start bit byte 1 byte 0 Stop bits idle Start bit TX pin UxTXIF (Transmit Buffer Reg Empty Flag) bit TXMTIF (Transmit Shift Reg Empty Flag) bit b7 = 1 b6 = 0 b5 = 0 b4 = 1 b0 = 1 b7 = 0 b6 = 1 b0 = 0 The forward and backward frames are terminated by two Idle bit periods or Stop bits. Normally, these start in the first bit period of a byte. If both Stop bits are valid, the byte reception is terminated. If either of the Stop bits is invalid, the frame is tagged as invalid by saving it as a null byte and setting the framing error in the receive FIFO. A framing error also occurs when no transition is detected on the bus in the middle of a bit period when the byte reception is not complete. In such a scenario, the byte will be saved with the FERIF bit set. 34.5.1 Control Device The Control Device mode is configured with the following settings: • MODE = ‘b1000 • TXEN = 1 • RXEN = 1 • • • • UxP1 = forward frames are held for transmission with this number of half-bit periods after the completion of a forward or backward frame UxP2 = forward/backward frame threshold delimiter. Any reception that starts this number of half-bit periods after the completion of a forward or backward frame is detected as forward frame and sets the PERIF flag of the corresponding received byte. UxBRG = value to achieve 1200 baud rate TXPOL = appropriate polarity for interface circuit STP = ‘b10 for two Stop bits • • RxyPPS = TX pin selection code TX pin TRIS control = 0 • ON = 1 • A forward frame is initiated by writing the control byte to the UxTXB register. After sending the control byte, each data byte must be written to the UxTXB register as soon as UxTXIF goes true. It is necessary to perform every write after UxTXIF goes true, to ensure that the transmit buffer is ready to accept the byte. Each write must also occur before the TXMTIF bit goes true, to ensure that the bit stream of the forward frame is generated without interruption. When TXMTIF goes true, indicating the transmit shift register has completed sending the last byte in the frame, the TX output is held in Idle state for the number of half-bit periods selected by the STP bits. After the last Stop bit, the TX output is held in the Idle state for an additional wait time determined by the half-bit period count in the UxP1 register. For example, a 2450 μs delay (~6 half-bit times) requires a value of 6 in UxP1L. Any writes to the UxTXB register that occur after TXMTIF goes true, but before the UxP1 wait time expires, are held and then transmitted immediately following the wait time. If a backward frame is received during the wait time, any bytes that may have been written to UxTXB will be transmitted after completion of the backward frame reception plus the UxP1 wait time. The wait timer is reset by the backward frame and starts over immediately following the reception of the Stop bits of the backward frame. Data pending in the transmit shift register will be sent when the wait time elapses. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 524 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... To replace or delete any pending forward frame data, the TXBE bit needs to be set to flush the shift register and transmit buffer. A new control byte can then be written to the UxTXB register. The control byte will be held in the buffer and sent at the beginning of the next forward frame following the UxP1 wait time. In Control Device mode, PERIF is set when a forward frame is received. This helps the software to determine whether the received byte is part of a forward frame from a Control Device (either from the Control Device under consideration or from another Control Device on the bus) or a backward frame from a Control Gear. 34.5.2 Control Gear The Control Gear mode is configured with the following settings: • MODE = ‘b1001 • TXEN = 1 • RXEN = 1 • • • • • UxP1 = back frames are held for transmission with this number of half-bit periods after the completion of a forward frame UxP2 = forward/back frame threshold delimiter. Idle periods longer than this number of half-bit periods are detected as forward frames. UxBRG = value to achieve 1200 baud rate TXPOL = appropriate polarity for interface circuit RXPOL = same as TXPOL STP = ‘b10 for two Stop bits • • RxyPPS = TX pin output code TX pin TRIS control = 0 • • RXPPS = RX pin selection code RX pin TRIS control = 1 • Input pin ANSEL bit = 0 • ON = 1 • The UART starts listening for a forward frame when the Control Gear mode is entered. Only the frames that follow an Idle period longer than UxP2 half-bit periods are detected as forward frames. Backward frames from other Control Gear are ignored. Only forward frames will be stored in UxRXB. This is necessary because a backward frame can be sent only as a response to a forward frame. The forward frame is received one byte at a time in the receive FIFO and retrieved by reading the UxRXB register. The end of the forward frame starts a timer to delay the backward frame response by a wait time equal to the number of half-bit periods stored in UxP1. The data received in the forward frame is processed by the application software. If the application decides to send a backward frame in response to the forward frame, the value of the backward frame is written to UxTXB. This value is held for transmission in the transmit shift register until the wait time expires, being transmitted afterwards. If the backward frame data is written to UxTXB after the wait time has expired, it is held in the UxTXB register until the end of the wait time following the next forward frame. The TXMTIF bit is false when the backward frame data is held in the transmit shift register. Receiving a UxRXIF interrupt before the TXMTIF goes true indicates that the backward frame write was too late and another forward frame was received before sending the backward frame. The pending backward frame is flushed by setting the TXBE bit to prevent it from being sent after the next forward frame. 34.6 General Purpose Manchester (Full-Featured UARTs Only) General purpose Manchester is a subset of the DALI mode. When the UxP1L register is cleared, there is no minimum wait time between frames. This allows full and half-duplex operation because writes to the UxTXB register are not held waiting for a receive operation to complete. General purpose Manchester operation maintains all other aspects of DALI mode as shown in Figure 34-9 such as: • • Single-pulse Start bit Most Significant bit first © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 525 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... • No stop periods between back-to-back bytes The general purpose Manchester mode is configured with the following settings: • MODE = ‘b1000 • TXEN = 1 • RXEN = 1 • UxP1 = 0h • • • • • UxBRG = desired baud rate TXPOL and RXPOL = desired Idle state STP = desired number of stop periods RxyPPS = TX pin selection code TX pin TRIS control = 0 • • RXPPS = RX pin selection code RX pin TRIS control = 1 • Input pin ANSEL bit = 0 • ON = 1 The Manchester bit stream timing is shown in Figure 34-9. 34.7 Polarity Receive and transmit polarity is user selectable and affects all modes of operation. The idle level is programmable with the TXPOL and RXPOL polarity control bits. Both control bits default to ‘0’, which selects a high idle level for transmit and receive. The low level Idle state is selected by setting the control bit to ‘1’. TXPOL controls the TX idle level. RXPOL controls the RX idle level. 34.8 Stop Bits The number of Stop bits is user selectable with the STP bits. The STP bits affect all modes of operation. Stop bits selections are shown in the table below: Table 34-1. Stop Bits Selections Transmitter Stop Bits Receiver Verification 1 Verify Stop bit 1.5 Verify first Stop bit 2 Verify both Stop bits 2 Verify only first Stop bit In all modes, except DALI, the transmitter is Idle for the number of Stop bit periods between each consecutively transmitted word. In DALI, the Stop bits are generated after the last bit in the transmitted data stream. The input is checked for the idle level in the middle of the first Stop bit, when receive verify on first is selected, as well as in the middle of the second Stop bit, when verify on both is selected. If any Stop bit verification indicates a nonidle level, the framing error FERIF bit is set for the received word. 34.8.1 Delayed Receive Interrupt When operating in Half Duplex mode, where the microcontroller needs to reverse the transceiver direction after a reception, it may be more convenient to hold off the UxRXIF interrupt until the end of the Stop bits to avoid line contention. The user selects when the UxRXIF interrupt occurs with the STPMD bit. When STPMD is ‘1’, the UxRXIF interrupt occurs at the end of the last Stop bit. When STPMD is ‘0’, the UxRXIF interrupt occurs when the received © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 526 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... byte is stored in the receive FIFO. When STP = 10, the store operation is performed in the middle of the second Stop bit, otherwise, it is performed in the middle of the first Stop bit. The FERIF and PERIF interrupts are not delayed with STPMD. When STPMD is set, the preferred indicator for reversing transceiver direction is the UxRXIF interrupt because it is delayed whereas the others are not. 34.9 Operation After FIFO Overflow The Receive Shift Register (RSR) can be configured to stop or continue running during a receive FIFO Overflow condition. Stopped operation is the Legacy mode. When the RSR continues to run during an Overflow condition, the first word received after clearing the overflow will always be valid. When the RSR is stopped during an Overflow condition, the synchronization with the Start bits is lost. Therefore, the first word received after the overflow is cleared may start in the middle of a word. Operation during overflow is selected with the RUNOVF bit. When the RUNOVF bit is set, the receiver maintains synchronization with the Start bits throughout the Overflow condition. 34.10 Receive and Transmit Buffers The UART uses small buffer areas to transmit and receive data. These are sometimes referred to as FIFOs. The receiver has a Receive Shift Register (RSR) and two or more buffer registers. The buffer at the top of the FIFO (earliest byte to enter the FIFO) is by retrieved by reading the UxRXB register. The transmitter has one or more Transmit Shift Register (TSR) and one buffer register. Writes to UxTXB go to the transmit buffer then immediately to the TSR, if it is empty. When the TSR is not empty, writes to UxTXB are held then transferred to the TSR when it becomes available. 34.10.1 FIFO Status The UxFIFO register contains several Status bits for determining the state of the receive and transmit buffers. The RXBE bit indicates that the receive FIFO is empty. This bit is essentially the inverse of UxRXIF. The RXBF bit indicates that the receive FIFO is full. The TXBE bit indicates that the transmit buffer is empty (same as UxTXIF) and the TXBF bit indicates that the buffer is full. A third transmitter Status bit, TXWRE (transmit write error), is set whenever a UxTXB write is performed when the TXBF bit is set. This indicates that the write was unsuccessful. 34.10.2 FIFO Reset All modes support resetting the receive and transmit buffers. The receive buffer is flushed and all unread data discarded when the RXBE bit is written to ‘1’. Instead of using a BSF instruction to set RXBE, the MOVWF instruction with the TXBE bit cleared will be used to avoid inadvertently clearing a byte pending in the TSR when UxTXB is empty. Data written to UxTXB when TXEN is low will be held in the Transmit Shift Register (TSR), then sent when TXEN is set. The transmit buffer and inactive TSR are flushed by setting the TXBE bit. Setting TXBE while a character is actively transmitting from the TSR will complete the transmission without being flushed. Clearing the ON bit will discard all received data and transmit data pending in the TSR and UxTXB. 34.11 Flow Control This section does not apply to the LIN, DALI, or DMX modes. Flow control is the means by which a sending UART data stream can be suspended by a receiving UART. Flow control prevents input buffers from overflowing without software intervention. The UART supports both hardware and XON/XOFF methods of flow control. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 527 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... The flow control method is selected with the FLO bits. Flow control is disabled when both bits are cleared. 34.11.1 Hardware Flow Control The hardware flow control is selected by setting the FLO bits to ‘10’. The hardware flow control consists of three lines. The RS-232 signal names for two of these are RTS and CTS. Both are low true. The third line is called TXDE for transmit drive enable which may be used to control an RS-485 transceiver. This output is high when the TX output is actively sending a character and low at all other times. The UART is configured as DTE (computer) equipment, which means RTS is an output and CTS is an input. The RTS and CTS signals work as a pair to control the transmission flow. A DTE-to-DTE configuration connects the RTS output of the receiving UART to the CTS input of the sending UART. Refer to the following figure. Figure 34-10. Hardware Flow Control Connections Rev. 10-000333A 1/11/2019 UART 1 RX RTS TX CTS UART 2 TX CTS RX RTS The UART receiving data asserts the RTS output low when the input FIFO is empty. When a character is received, the RTS output goes high until the UxRXB is read to free up both FIFO locations. When the CTS input goes high after a byte has started to transmit, the transmission will complete normally. The receiver accommodates this by accepting the character in the second FIFO location even when the CTS input is high. 34.11.2 RS-485 Transceiver Control The hardware flow control can be used to control the direction of an RS-485 transceiver as shown in the following figure. The CTS input will be configured to be always enabled by setting the UxCTSPPS selection to an unimplemented PORT pin, such as RD0. When the signal and control lines are configured as shown in the figure below, the UART will not receive its own transmissions. To verify that there are no collisions on the RS-485 lines, the transceiver RE control can be disconnected from TXDE and tied low, thereby enabling loopback reception of all transmissions. See the Collision Detection section for more information. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 528 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... Figure 34-11. RS-485 Configuration Rev. 10-000334A 9/6/2017 UART SN75176 Vcc R RX RE TXDE 4k7 A DE B D TX CTS(1) 4k7 Gnd Note 1: Configure UxCTSPPS to an unimplemented input such as RD0. (e.g. UxCTSPPS = 0x18) 34.11.3 XON/XOFF Flow Control XON/XOFF flow control is selected by setting the FLO bits to ‘01’. XON/XOFF is a data-based flow control method. The signals to suspend and resume transmission are special characters sent by the receiver to the transmitter. The advantage is that additional hardware lines are not needed. XON/XOFF flow control requires full-duplex operation because the transmitter must be able to receive the signal to suspend transmitting while the transmission is in progress. Although XON and XOFF are not defined in the ASCII code, the generally accepted values are 13h for XOFF and 11h for XON. The UART uses those codes. The transmitter defaults to XON, or transmitter enabled. This state is also indicated by the read-only XON bit. When an XOFF character is received, the transmitter stops transmitting after completing the character actively being transmitted. The transmitter remains disabled until an XON character is received. XON will be forced on when software toggles the TXEN bit. When the RUNOVF bit is set, the XON and XOFF characters continue to be received and processed without the need to clear the input FIFO by reading UxRXB. However, if the RUNOVF bit is clear then UxRXB must be read to avoid a receive overflow which will suspend flow control when the receive buffer overflows. 34.12 Checksum (Full-Featured UARTs Only) This section does not apply to the LIN mode, which handles checksums automatically. The transmit and receive checksum adders are enabled when the C0EN bit is set. When enabled, the adders accumulate every byte that is transmitted or received. The accumulated sum includes the carry of the addition. Software is responsible for clearing the checksum registers before a transaction and performing the check at the end of the transaction. The following examples illustrate how the checksum registers can be used in the Asynchronous modes. 34.12.1 Transmit Checksum Method 1. 2. 3. 4. Clear the UxTXCHK register. Set the C0EN bit. Send all bytes of the transaction output. Invert UxTXCHK and send the result as the last byte of the transaction. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 529 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.12.2 Receive Checksum Method 1. 2. 3. 4. 5. Clear the UxRXCHK register. Set the C0EN bit. Receive all bytes in the transaction including the checksum byte. Set MSb of UxRXCHK if 7-bit mode is selected. Add ‘1’ to UxRXCHK. 6. If the result is ‘0’, the checksum passes, otherwise it fails. The CERIF Checksum Interrupt flag is not active in any mode other than LIN. 34.13 Collision Detection (Full-Featured UARTs Only) External forces that interfere with the transmit line are detected in all modes of operation with collision detection. Collision detection is always active when RXEN and TXEN are both set. When the receive input is connected to the transmit output through either the same I/O pin or external circuitry, a character will be received for every character transmitted. The collision detection circuit provides a warning when the word received does not match the word transmitted. The TXCIF flag is used to signal collisions. This signal is only useful when the TX output is looped back to the RX input and everything that is transmitted is expected to be received. If more than one transmitter is active at the same time, it can be assumed that the TX word will not match the RX word. The TXCIF detects this mismatch and flags an interrupt. The TXCIF bit will also be set in DALI mode transmissions when the received bit is missing the expected mid-bit transition. Collision detection is always active, regardless of whether or not the RX input is connected to the TX output. It is up to the user to disable the TXCIE bit when collision interrupts are not required. The software overhead of unloading the receive buffer of transmitted data is avoided by setting the RUNOVF bit and ignoring the receive interrupt and letting the receive buffer overflow. When the transmission is complete, prepare for receiving data by flushing the receive buffer (see the FIFO Reset section) and clearing the RXFOIF overflow flag. 34.14 RX/TX Activity Time-Out The UART works in conjunction with the HLT timers to monitor activity on the RX and TX lines. Use this feature to determine when there has been no activity on the receive or transmit lines for a user-specified period of time. To use this feature, set the HLT to the desired time-out period by a combination of the HLT clock source, timer prescale value, and timer period registers. Configure the HLT to reset on the UART TX or RX line and start the HLT at the same time the UART is started. UART activity will keep resetting the HLT to prevent a full HLT period from elapsing. When there has been no activity on the selected TX or RX line for longer than the HLT period, then an HLT interrupt will occur signaling the time-out event. For example, the following register settings will configure HLT2 for a 5 ms time-out of no activity on U1RX: • T2PR = 0x9C (156 prescale periods) • 34.15 T2CLKCON = 0x05 (500 kHz internal oscillator) • T2HLT = 0x04 (free-running, Reset on rising edge) • T2RST = 0x15 (Reset on U1RX) • T2CON = 0xC0 (Timer2 on with 1:16 prescale) Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value of the OSCTUNE register allows for fine resolution changes to the system clock source. See the “HFINTOSC Frequency Tuning” section for more information. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 530 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... The other method adjusts the value of the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see the Auto-Baud Detect section). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change of the peripheral clock frequency. 34.16 UART Baud Rate Generator The Baud Rate Generator (BRG) is a 16-bit timer that is dedicated to the support of the UART operation. The UxBRG register pair determines the period of the free-running baud rate timer. The multiplier of the baud rate period is determined by the BRGS bit. The high baud rate range (BRGS = 1) is intended to extend the baud rate range up to a faster rate when the desired baud rate is not possible otherwise, and to improve the baud rate resolution at high baud rates. Using the normal baud rate range (BRGS = 0) is recommended when the desired baud rate is achievable with either range. Important:  BRGS = 1 is not supported in the DALI mode. Writing a new value to UxBRG causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RXIDL bit to make sure that the receive operation is Idle before changing the system clock. The following table contains formulas for determining the baud rate. Table 34-2. Baud Rate Formulas BRGS BRG/UART Mode Baud Rate Formula 1 High Rate Fosc/[4(UxBRG+1)] 0 Normal Rate Fosc/[16(UxBRG+1)] The following example provides a sample calculation for determining the baud rate and baud rate error. Example 34-1. Baud Rate Error Calculation For a device with Fosc of 16 MHz, desired baud rate of 9600, Asynchronous mode, and BRGS = 0. DesiredBaudrate = Solving for UxBRG: UxBRG = FOSC 16 × UxBRG + 1 FOSC −1 16 × DesiredBaudrate UxBRG = 16000000 − 1 16 × 9600 UxBRG = 103.17 ≃ 103 CalculatedBaudrate = 16000000 16 × 103 + 1 CalculatedBaudrate = 9615 Error = CalculatedBaudrate − DesiredBaudrate DesiredBaudrate Error = 9615 − 9600 9600 Error ≃ 0.16 % © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 531 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.16.1 Auto-Baud Detect The UART module supports automatic detection and calibration of the baud rate in the 8-bit Asynchronous and LIN modes. However, setting ABDEN to start auto-baud detection is neither necessary, nor possible in LIN mode because that mode supports auto-baud detection automatically at the beginning of every data packet. Enabling auto-baud detect with the ABDEN bit applies to the Asynchronous modes only. When Auto-Baud Detect (ABD) is active, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”), which is the Sync character for the LIN bus. The unique feature of this character is that it has five falling edges, including the Start bit edge, and five rising edges, including the Stop bit edge. In 8-bit Asynchronous mode, setting the ABDEN bit enables the auto-baud calibration sequence. The first falling edge of the RX input after ABDEN is set will start the auto-baud calibration sequence. While the ABD sequence takes place, the UART state machine is held in Idle. On the first falling edge of the receive line, the UxBRG begins counting up using the BRG counter clock, as shown in the following figure. The fifth falling edge will occur on the RX pin at the beginning of the bit 7 period. At that time, an accumulated value totaling the proper BRG period is left in the UxBRG register pair, the ABDEN bit is automatically cleared and the ABDIF interrupt flag is set. ABDIF must be cleared by software. Figure 34-12. Automatic Baud Rate Calibration Rev. 10-000120B 9/6/2017 BRG Value XXXXh 0000h 001Ch Edge #2 Edge #1 RX pin Edge #3 Edge #4 Edge #5 start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 BRG Clock ABDEN Set by user in 8-bit mode Auto cleared RXIDL Cleared by software ABDIF (Interrupt Flag) bit UxBRG XXXXh 001Ch RXIDL indicates that the sync input is active. RXIDL will go low on the first falling edge and go high on the fifth rising edge. The BRG auto-baud clock is determined by the BRGS bit, as shown in the following table. Table 34-3. BRG Counter Clock Rates BRGS BRG Base Clock BRG ABD Clock 1 Fosc/4 Fosc/32 0 Fosc/16 Fosc/128 During ABD, the internal BRG register is used as a 16-bit counter. However, the UxBRG registers retain the previous BRG value until the auto-baud process is successfully completed. While calibrating the baud rate period, the internal BRG register is clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed and is transferred to the UxBRG registers when complete. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 532 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... Important:  1. When both the WUE and ABDEN bits are set, the auto-baud detection will occur on the byte following the Break character (see the Auto Wake-on-Break section). 2. It is up to the user to verify the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and UART baud rates are not possible. 34.16.2 Auto-Baud Overflow During the course of automatic baud detection, the ABDOVF bit will be set if the baud rate counter overflows before the fifth falling edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the UxBRG register pair. After the ABDOVF bit has been set, the state machine continues to search until the fifth falling edge is detected on the RX pin. Upon detecting the fifth falling RX edge, the hardware will set the ABDIF Interrupt flag and clear the ABDEN bit. The UxBRG register values retain their previous value. The ABDIF flag and ABDOVF flag can be cleared by software directly. To generate an interrupt on an Auto-Baud Overflow condition, all the following bits must be set: • ABDOVE bit • UxEIE bit in the PIEx register • Global Interrupt Enable bits To terminate the auto-baud process before the ABDIF flag is set, clear the ABDEN bit, then clear the ABDOVF bit. 34.16.3 Auto Wake-on-Break During Sleep mode, all clocks to the UART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto Wake-on-Break feature allows the controller to wake up due to activity on the RX line. The Auto-Wake-up feature is enabled by setting both the WUE bit and the UxIE bit in the PIEx register. Once set, the normal receive sequence on RX is disabled, and the UART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a transition out of the Idle state on the RX line (this coincides with the start of a Break or a wake-up signal character for the LIN protocol). The UART module generates a WUIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 34-13), and asynchronously, if the device is in Sleep mode (Figure 34-14). The interrupt condition is cleared by clearing the WUIF bit. Figure 34-13. Auto-Wake-Up Timing During Normal Operation Rev. 10-000326B 1/11/2019 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 FOSC WUE bit Bit set by user Auto cleared RX line WUIF Cleared by software Note 1: The UART remains in Idle while the WUE bit is set. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 533 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... Figure 34-14. Auto-Wake-Up Timing During Sleep Rev. 10-000327B 9/6/2017 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 FOSC WUE bit Bit set by user Auto cleared RX line WUIF Cleared by software Sleep command executed Sleep ends Note 1: The UART remains in Idle while the WUE bit is set. To generate an interrupt on a wake-up event, all the following bits must be set: • The UxIE bit in the PIEx register • Global interrupt enables The WUE bit is automatically cleared by the transition to the Idle state on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the UART module is in Idle mode, waiting to receive the next character. 34.16.3.1 Auto-Wake-Up Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, all bits in the character causing the Wake event must be zero. When the wake-up is enabled, the function works independent of the low time on the data stream. If the WUE bit is set and a valid nonzero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits of the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character of the transmission must be all zeros. This must be eleven or more bit times, 13 bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Start-Up Time The oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL modes). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the UART. The WUE Bit To ensure that no actual data is lost, check the RXIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. 34.17 Transmitting a Break The UART module has the capability of sending either a fixed length Break period or a software-timed Break period. The fixed length Break consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. The software-timed Break is generated by setting and clearing the BRKOVR bit. To send the fixed length Break, set the SENDB and TXEN bits. The Break sequence is then initiated by a write to UxTXB. The timed Break will occur first, followed by the character written to UxTXB that initiated the Break. The initiating character is typically the Sync character of the LIN specification. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 534 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... SENDB is disabled in the LIN and DMX modes because those modes generate the Break sequence automatically. The SENDB bit is automatically reset by hardware after the Break Stop bit is complete. The TXMTIF bit indicates when the transmit operation is Active or Idle, just as it does during normal transmission. The following figure illustrates the Break sequence. Figure 34-15. Send-Break Sequence Sync Write Rev. 10-000118B 9/6/2017 Write to UxTXB BRG Output (Shift Clock) TX pin Start bit bit 0 bit 1 Stop bit Sync start Break UxTXIF (Transmit Buffer Reg Empty Flag) bit TXMTIF (Transmit Shift Reg Empty Flag) bit SENDB (send break control bit) 34.18 bit 11 Auto cleared Receiving a Break The UART has counters to detect when the RX input remains in the Space state for an extended period of time. When this happens, the RXBKIF bit is set. A Break is detected when the RX input remains in the Space state for 11 bit periods for asynchronous and LIN modes, and 23 bit periods for DMX mode. The user can select to receive the Break interrupt as soon as the Break is detected or at the end of the Break, when the RX input returns to the Idle state. When the RXBIMD bit is ‘1’, then RXBKIF is set immediately upon Break detection. When RXBIMD is ‘0’, then RXBKIF is set when the RX input returns to the Idle state. 34.19 UART Operation During Sleep The UART ceases to operate during Sleep. The safe way to wake the device from Sleep by a serial operation is to use the Wake-on-Break feature of the UART. See the Auto Wake-on-Break section. 34.20 Register Definitions: UART Long bit name prefixes for the UART peripherals are shown in the following table. Refer to the “Long Bit Names” section in the “Register and Bit Naming Conventions” chapter for more information. Table 34-4. UART Long Bit Name Prefixes Peripheral Bit Name Prefix UART1 (full featured) U1 UART2 (limited features) U2 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 535 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... ...........continued Peripheral Bit Name Prefix UART3 (limited features) U3 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 536 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.1 UxCON0 Name:  Address:  UxCON0 0x2AB,0x2BE,0x2D1 UART Control Register 0 Bit 7 BRGS R/W 0 Access Reset 6 ABDEN R/W 0 5 TXEN R/W 0 4 RXEN R/W 0 3 2 1 0 R/W 0 R/W 0 MODE[3:0] R/W 0 R/W 0 Bit 7 – BRGS Baud Rate Generator Speed Select Value Description 1 Baud Rate Generator is high speed with 4 baud clocks per bit 0 Baud Rate Generator is normal speed with 16 baud clocks per bit Bit 6 – ABDEN  Auto-Baud Detect Enable(3) Value Description 1 Auto-baud is enabled. Receiver is waiting for Sync character (0x55). 0 Auto-baud is not enabled or auto-baud is complete Bit 5 – TXEN  Transmit Enable Control(2) Value Description 1 Transmit is enabled. TX output pin drive is forced on when transmission is active, and controlled by PORT TRIS control when transmission is Idle. 0 Transmit is disabled. TX output pin drive is controlled by PORT TRIS control. Bit 4 – RXEN  Receive Enable Control(2) Value Description 1 Receiver is enabled 0 Receiver is disabled Bits 3:0 – MODE[3:0]  UART Mode Select(1) Value Description 1111 Reserved 1101 1100 LIN Host/Client mode(4) 1011 LIN Client Only mode(4) 1010 DMX mode(4) 1001 DALI Control Gear mode(4) 1000 DALI Control Device mode(4) 0111 Reserved 0101 0100 Asynchronous 9-bit UART Address mode. 9th bit: 1 = address, 0 = data 0011 Asynchronous 8-bit UART mode with 9th bit even parity 0010 Asynchronous 8-bit UART mode with 9th bit odd parity 0001 Asynchronous 7-bit UART mode 0000 Asynchronous 8-bit UART mode Notes:  1. Changing the UART MODE while ON = 1 may cause unexpected results. 2. 3. Clearing TXEN or RXEN will not clear the corresponding buffers. Use TXBE or RXBE to clear the buffers. ABDEN is read-only when MODE > ‘b0111. 4. Full-featured UARTs only. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 537 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.2 UxCON1 Name:  Address:  UxCON1 0x2AC,0x2BF,0x2D2 UART Control Register 1 Bit Access Reset 7 ON R/W 0 6 5 4 WUE R/W/HC 0 3 RXBIMD R/W 0 2 1 BRKOVR R/W 0 0 SENDB R/W/HC 0 Bit 7 – ON Serial Port Enable Value Description 1 Serial port enabled 0 Serial port disabled (held in Reset) Bit 4 – WUE Wake-Up Enable Value Description 1 Receiver is waiting for falling RX input edge which will set the UxIF bit. Cleared by hardware on wake-up event. Also requires the UxIE bit of PIEx to enable wake. 0 Receiver operates normally Bit 3 – RXBIMD Receive Break Interrupt Mode Select Value Description 1 Set RXBKIF immediately when RX in has been low for the minimum Break time 0 Set RXBKIF on rising RX input after RX in has been low for the minimum Break time Bit 1 – BRKOVR Send Break Software Override Value Description 1 TX output is forced to non-Idle state 0 TX output is driven by transmit shift register Bit 0 – SENDB  Send Break Control(1) Value Description 1 Output Break upon UxTXB write. Written byte follows Break. Bit is cleared by hardware. 0 Break transmission completed or disabled Note:  1. This bit is read-only in LIN, DMX and DALI modes. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 538 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.3 UxCON2 Name:  UxCON2 UART Control Register 2 Bit Access Reset 7 RUNOVF R/W 0 6 RXPOL R/W/HC 0 5 4 STP[1:0] R/W 0 R/W 0 3 C0EN R/W 0 2 TXPOL R/W 0 1 0 FLO[1:0] R/W 0 R/W 0 Bit 7 – RUNOVF Run During Overflow Control Value Description 1 RX input shifter continues to synchronize with Start bits after Overflow condition 0 RX input shifter stops all activity on receiver Overflow condition Bit 6 – RXPOL Receive Polarity Control Value Description 1 Invert RX polarity, Idle state is low 0 RX polarity is not inverted, Idle state is high Bits 5:4 – STP[1:0]  Stop Bit Mode Control(1) Value Description 11 Transmit 2 Stop bits, receiver verifies first Stop bit 10 Transmit 2 Stop bits, receiver verifies first and second Stop bits 01 Transmit 1.5 Stop bits, receiver verifies first Stop bit 00 Transmit 1 Stop bit, receiver verifies first Stop bit Bit 3 – C0EN  Checksum Mode Select(2) Value Condition Description 1 MODE = LIN Enhanced LIN checksum includes PID in sum 0 MODE = LIN Legacy LIN checksum does not include PID in sum 1 MODE = not LIN Checksum is the sum of all TX and RX characters 0 MODE = not LIN Checksum is disabled Bit 2 – TXPOL  Transmit Control Polarity(1) Value Description 1 Output data is inverted, TX output is low in Idle state 0 Output data is not inverted, TX output is high in Idle state Bits 1:0 – FLO[1:0] Handshake Flow Control Value Description 11 Reserved 10 RTS/CTS and TXDE Hardware flow control 01 XON/XOFF Software flow control 00 Flow control is off Notes:  1. All modes transmit selected number of Stop bits. 2. Full-featured UARTs only. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 539 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.4 UxERRIR Name:  UxERRIR UART Error Interrupt Flag Register Bit Access Reset 7 TXMTIF R/S/C 1 6 PERIF R/W/HC 0 5 ABDOVF R/W/S 0 4 CERIF R/W/S 0 3 FERIF R/S/C 0 2 RXBKIF R/W/S 0 1 RXFOIF R/W/S 0 0 TXCIF R/W/S 0 Bit 7 – TXMTIF Transmit Shift Register Empty Interrupt Flag Value Description 1 Transmit shift register is empty (Set at end of Stop bits) 0 Transmit shift register is actively shifting data Bit 6 – PERIF Parity Error Interrupt Flag Value Condition 1 MODE = LIN or Parity 0 MODE = LIN or Parity 1 MODE = DALI Device 0 MODE = DALI Device 1 MODE = Address 0 MODE = Address x MODE = All others Description Unread byte at top of input FIFO has parity error Unread byte at top of input FIFO does not have parity error Unread byte at top of input FIFO received as Forward Frame Unread byte at top of input FIFO received as Back Frame Unread byte at top of input FIFO received as address Unread byte at top of input FIFO received as data Not used Bit 5 – ABDOVF Auto-baud Detect Overflow Interrupt Flag Value Condition Description 1 MODE = DALI Start bit measurement overflowed counter 0 MODE = DALI No overflow during Start bit measurement 1 MODE = All others Baud Rate Generator overflowed during the auto-detection sequence 0 MODE = All others Baud Rate Generator has not overflowed Bit 4 – CERIF Checksum Error Interrupt Flag Value Condition 1 MODE = LIN 0 MODE = LIN x MODE = not LIN Description Checksum error No checksum error Not used Bit 3 – FERIF Framing Error Interrupt Flag Value Description 1 Unread byte at top of input FIFO has framing error 0 Unread byte at top of input FIFO does not have framing error Bit 2 – RXBKIF Break Reception Interrupt Flag Value Description 1 Break detected 0 No break detected Bit 1 – RXFOIF Receive FIFO Overflow Interrupt Flag Value Description 1 Receive FIFO has overflowed 0 Receive FIFO has not overflowed Bit 0 – TXCIF  Transmit Collision Interrupt Flag(1) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 540 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... Value 1 0 Description Transmitted word is not equal to the word received during transmission Transmitted word equals the word received during transmission Note:  1. Full-featured UARTs only. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 541 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.5 UxERRIE Name:  UxERRIE UART Error Interrupt Enable Register Bit Access Reset 7 TXMTIE R/W 0 6 PERIE R/W 0 5 ABDOVE R/W 0 4 CERIE R/W 0 3 FERIE R/W 0 2 RXBKIE R/W 0 1 RXFOIE R/W 0 0 TXCIE R/W 0 Bit 7 – TXMTIE Transmit Shift Register Empty Interrupt Enable Value Description 1 Interrupt enabled 0 Interrupt not enabled Bit 6 – PERIE Parity Error Interrupt Enable Value Description 1 Interrupt enabled 0 Interrupt not enabled Bit 5 – ABDOVE Auto-baud Detect Overflow Interrupt Enable Value Description 1 Interrupt enabled 0 Interrupt not enabled Bit 4 – CERIE Checksum Error Interrupt Enable Value Description 1 Interrupt enabled 0 Interrupt not enabled Bit 3 – FERIE Framing Error Interrupt Enable Value Description 1 Interrupt enabled 0 Interrupt not enabled Bit 2 – RXBKIE Break Reception Interrupt Enable Value Description 1 Interrupt enabled 0 Interrupt not enabled Bit 1 – RXFOIE Receive FIFO Overflow Interrupt Enable Value Description 1 Interrupt enabled 0 Interrupt not enabled Bit 0 – TXCIE  Transmit Collision Interrupt Enable(1) Value Description 1 Interrupt enabled 0 Interrupt not enabled Note:  1. Full-featured UARTs only. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 542 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.6 UxUIR Name:  Address:  UxUIR 0x2B1,0x2C4,0x2D7 UART General Interrupt Flag Register Bit Access Reset 7 WUIF R/W/S 0 6 ABDIF R/W/S 0 5 4 3 2 ABDIE R/W 0 1 0 Bit 7 – WUIF Wake-Up Interrupt Value Description 1 Idle to non-Idle transition on RX line detected when WUE is set. Also sets UxIF. (WUIF must be cleared by software to clear UxIF) 0 WUE not enabled by software or no transition detected Bit 6 – ABDIF Auto-Baud Detect Interrupt Value Description 1 Auto-baud detection complete. Status shown in UxIF when ABDIE is set. (Must be cleared by software) 0 Auto-baud not enabled or auto-baud enabled and auto-baud detection not complete Bit 2 – ABDIE Auto-Baud Detect Interrupt Enable Value Description 1 ABDIF will set the UxIF bit in the PIRx register 0 ABDIF will not set UxIF © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 543 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.7 UxFIFO Name:  Address:  UxFIFO 0x2B0,0x2C3,0x2D6 UART FIFO Status Register Bit Access Reset 7 TXWRE R/W/S 0 6 STPMD R/W 0 5 TXBE R/W/S/C 1 4 TXBF R/S/C 0 3 RXIDL R/S/C 1 2 XON S/C 1 1 RXBE R/W/S/C 1 0 RXBF R/S/C 0 Bit 7 – TXWRE Transmit Write Error Status (must be cleared by software) Value Condition Description 1 MODE = LIN Host UxP1L was written when a host process was active 1 MODE = LIN Client UxTXB was written when UxP2 = 0 or more than UxP2 bytes have been written to UxTXB since last Break 1 MODE = Address detect UxP1L was written before the previous data in UxP1L was transferred to TX shifter 1 MODE = All A new byte was written to UxTXB when the output FIFO was full 0 MODE = All No error Bit 6 – STPMD Stop Bit Detection Mode Value Condition Description 1 STP = 11 Assert UxRXIF at end of first Stop bit 1 STP ≠ 11 Assert UxRXIF at end of last Stop bit 0 STP = xx Assert UxRXIF in middle of first Stop bit Bit 5 – TXBE Transmit Buffer Empty Status Value Description 1 Transmit buffer is empty. Setting this bit will clear the transmit buffer and output shift register. 0 Transmit buffer is not empty. Software cannot clear this bit. Bit 4 – TXBF Transmit Buffer Full Status Value Description 1 Transmit buffer is full 0 Transmit buffer is not full Bit 3 – RXIDL Receive Pin Idle Status Value Description 1 Receive pin is in Idle state 0 UART is receiving Start, Stop, Data, Auto-baud, or Break Bit 2 – XON Software Flow Control Transmit Enable Status Value Description 1 Transmitter is enabled 0 Transmitter is disabled Bit 1 – RXBE Receive Buffer Empty Status Value Description 1 Receive buffer is empty. Setting this bit will clear the RX buffer(1). 0 Receive buffer is not empty. Software cannot clear this bit. Bit 0 – RXBF Receive Buffer Full Status Value Description 1 Receive buffer is full © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 544 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... Value 0 Description Receive buffer is not full Note:  1. The BSF instruction will not be used to set RXBE because doing so will clear a byte pending in the transmit shift register when the UxTXB register is empty. Instead, use the MOVWF instruction with a ‘0’ in the TXBE bit location. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 545 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.8 UxBRG Name:  Address:  UxBRG 0x2AE,0x2C1,0x2D4 UART Baud Rate Generator Bit 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 BRG[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 BRG[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 15:0 – BRG[15:0] Baud Rate Generator Value The UART Baud Rate equals [Fosc*(1+(BRGS*3)]/[(16*(BRG-1))] Notes:  1. The individual bytes in this multibyte register can be accessed with the following register names: – UxBRGH: Accesses the high byte BRG[15:8] – UxBRGL: Accesses the low byte BRG[7:0] 2. The UxBRG registers will only be written when ON = 0. 3. Maximum BRG value when MODE = ‘100x and BRGS = 1 is 0x7FFE. 4. Maximum BRG value when MODE = ‘100x and BRGS = 0 is 0x1FFE. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 546 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.9 UxRXB Name:  Address:  UxRXB 0x2A1,0x2B4,0x2C7 UART Receive Register Bit 7 6 5 4 3 2 1 0 R x R x R x R x RXB[7:0] Access Reset R x R x R x R x Bits 7:0 – RXB[7:0] Top of Receive FIFO © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 547 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.10 UxTXB Name:  Address:  UxTXB 0x2A3,0x2B6,0x2C9 UART Transmit Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 TXB[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – TXB[7:0] Bottom of Transmit FIFO © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 548 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.11 UxP1 Name:  UxP1 UART Parameter 1 Bit 15 14 13 12 7 6 5 4 11 10 9 8 P1[8] R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 Access Reset Bit P1[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bit 8 – P1[8] Parameter 1 Most Significant bit UART mode operating parameter values Value Condition Description n MODE = DMX Most Significant bit of number of bytes to transmit between Start Code and automatic Break generation n MODE = DALI Control Most Significant bit of Idle time delay after which a Forward Frame is Device sent. Measured in half-bit periods. n MODE = DALI Control Gear Most Significant bit of delay between the end of a Forward Frame and the start of the Back Frame. Measured in half-bit periods. x All other modes/Limited Not used featured UART Bits 7:0 – P1[7:0] Parameter 1 Least Significant bits UART mode operating parameter values Value Condition Description n MODE = DMX Least Significant bits of number of bytes to transmit between Start Code and automatic Break generation n MODE = DALI Control Device Least Significant bits of Idle time delay after which a Forward Frame is sent. Measured in half-bit periods. n MODE = DALI Control Gear Least Significant bits of delay between the end of a Forward Frame and the start of the Back Frame. Measured in half-bit periods. n MODE = LIN PID to transmit (Only Least Significant six bits used) n MODE = Asynchronous Address to transmit (9th transmit bit automatically set to ‘1’) Address x All other modes Not used Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • UxP1H: Accesses the high byte P1[8] • UxP1L: Accesses the low byte P1[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 549 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.12 UxP2 Name:  UxP2 UART Parameter 2 Bit 15 14 13 12 7 6 5 4 11 10 9 8 P2[8] R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 Access Reset Bit P2[7:0] Access Reset R/W 0 R/W 0 R/W 0 Bit 8 – P2[8] Parameter 2 Most Significant bit UART mode operating parameter values Value Condition n MODE = DMX n MODE = DALI x All other modes/Limited featured UART R/W 0 Description Most Significant bit of first address of receive block Most Significant bit of number of half-bit periods of Idle time in Forward Frame detection threshold Not used Bits 7:0 – P2[7:0] Parameter 2 Least Significant bits UART mode operating parameter values Value Condition Description n MODE = DMX Least Significant bits of first address of receive block n MODE = DALI Least Significant bits of number of half-bit periods of Idle time in Forward Frame detection threshold n MODE = LIN Number of data bytes to transmit n MODE = Asynchronous Address Receiver address x All other modes Not used Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • UxP2H: Accesses the high byte P2[8] • UxP2L: Accesses the low byte P2[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 550 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.13 UxP3 Name:  UxP3 UART Parameter 3 Bit 15 14 13 12 7 6 5 4 11 10 9 8 P3[8] R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 Access Reset Bit P3[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bit 8 – P3[8] Parameter 3 Most Significant bit UART mode operating parameter values Value Condition n MODE = DMX x All other modes/Limited featured UART Description Most Significant bit of last address of receive block Not used Bits 7:0 – P3[7:0] Parameter 3 Least Significant bits UART mode operating parameter values Value Condition Description n MODE = DMX Least Significant bits of last address of receive block n MODE = LIN Client Number of data bytes to receive n MODE = Asynchronous Address Receiver address mask. Received address is XOR’d with UxP2L, then AND’d with UxP3L. Match occurs when result is zero. x All other modes Not used Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • UxP3H: Accesses the high byte P3[8] • UxP3L: Accesses the low byte P3[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 551 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.14 UxTXCHK Name:  Address:  UxTXCHK 0x02A4 UART Transmit Checksum Result Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 TXCHK[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – TXCHK[7:0] Transmit Checksum Value Value Condition n MODE = LIN and C0EN = 1 n MODE = LIN and C0EN = 0 n MODE = All others and C0EN = 1 x MODE = All others and C0EN = 0 © 2020-2021 Microchip Technology Inc. and its subsidiaries Description Sum of all transmitted bytes including PID Sum of all transmitted bytes except PID Sum of all transmitted bytes since last clear Not used Preliminary Datasheet DS40002214E-page 552 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.20.15 UxRXCHK Name:  Address:  UxRXCHK 0x02A2 UART Receive Checksum Result Register Bit Access Reset 7 6 5 R/W 0 R/W 0 R/W 0 3 RXCHK[7:0] R/W R/W 0 0 Bits 7:0 – RXCHK[7:0] Receive Checksum Value Value Condition n MODE = LIN and C0EN = 1 n MODE = LIN and C0EN = 0 n MODE = All others and C0EN = 1 x MODE = All others and C0EN = 0 © 2020-2021 Microchip Technology Inc. and its subsidiaries 4 2 1 0 R/W 0 R/W 0 R/W 0 Description Sum of all received bytes including PID Sum of all received bytes except PID Sum of all received bytes since last clear Not used Preliminary Datasheet DS40002214E-page 553 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... 34.21 Address Register Summary - UART Name 0x00 ... 0x02A0 0x02A1 0x02A2 0x02A3 0x02A4 U1RXB U1RXCHK U1TXB U1TXCHK 0x02A5 U1P1 Bit Pos. 7 6 5 4 3 2 1 0 Reserved 0x02A7 U1P2 0x02A9 U1P3 0x02AB 0x02AC 0x02AD U1CON0 U1CON1 U1CON2 0x02AE U1BRG 0x02B0 0x02B1 0x02B2 0x02B3 0x02B4 0x02B5 0x02B6 0x02B7 U1FIFO U1UIR U1ERRIR U1ERRIE U2RXB Reserved U2TXB Reserved 0x02B8 U2P1 0x02BA U2P2 0x02BC U2P3 0x02BE 0x02BF 0x02C0 U2CON0 U2CON1 U2CON2 0x02C1 U2BRG 0x02C3 0x02C4 0x02C5 0x02C6 0x02C7 0x02C8 0x02C9 0x02CA U2FIFO U2UIR U2ERRIR U2ERRIE U3RXB Reserved U3TXB Reserved 0x02CB U3P1 0x02CD U3P2 0x02CF U3P3 0x02D1 0x02D2 0x02D3 U3CON0 U3CON1 U3CON2 0x02D4 U3BRG 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 RXB[7:0] RXCHK[7:0] TXB[7:0] TXCHK[7:0] P1[7:0] P1[8] P2[7:0] P2[8] P3[7:0] BRGS ON RUNOVF ABDEN TXWRE WUIF TXMTIF TXMTIE STPMD ABDIF PERIF PERIE RXEN WUE RXBIMD STP[1:0] C0EN BRG[7:0] BRG[15:8] TXBE TXBF RXIDL ABDOVF ABDOVE CERIF FERIF CERIE FERIE RXB[7:0] 7:0 TXB[7:0] 7:0 15:8 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 P1[7:0] P3[8] MODE[3:0] BRKOVR SENDB TXPOL FLO[1:0] XON ABDIE RXBKIF RXBKIE RXBE RXBF RXFOIF RXFOIE TXCIF TXCIE P2[7:0] P3[7:0] BRGS ON RUNOVF ABDEN TXWRE WUIF TXMTIF TXMTIE STPMD ABDIF PERIF PERIE RXPOL TXEN RXEN WUE RXBIMD STP[1:0] BRG[7:0] BRG[15:8] TXBE TXBF RXIDL ABDOVF ABDOVE CERIF FERIF CERIE FERIE RXB[7:0] 7:0 TXB[7:0] 7:0 15:8 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 15:8 P1[7:0] MODE[3:0] BRKOVR SENDB TXPOL FLO[1:0] XON ABDIE RXBKIF RXBKIE RXBE RXBF RXFOIF RXFOIE P2[7:0] P3[7:0] BRGS ON RUNOVF © 2020-2021 Microchip Technology Inc. and its subsidiaries RXPOL TXEN ABDEN RXPOL TXEN RXEN WUE RXBIMD STP[1:0] BRG[7:0] BRG[15:8] Preliminary Datasheet MODE[3:0] BRKOVR SENDB TXPOL FLO[1:0] DS40002214E-page 554 PIC18F06/16Q41 UART - Universal Asynchronous Receiver Tra... ...........continued Address Name Bit Pos. 7 6 5 4 3 2 1 0 0x02D6 0x02D7 0x02D8 0x02D9 U3FIFO U3UIR U3ERRIR U3ERRIE 7:0 7:0 7:0 7:0 TXWRE WUIF TXMTIF TXMTIE STPMD ABDIF PERIF PERIE TXBE TXBF RXIDL RXBE RXBF ABDOVF ABDOVE CERIF CERIE FERIF FERIE XON ABDIE RXBKIF RXBKIE © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet RXFOIF RXFOIE DS40002214E-page 555 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35. SPI - Serial Peripheral Interface Module The Serial Peripheral Interface (SPI) module is a synchronous serial data communication bus that operates in Full Duplex mode. Devices communicate in a host/client environment where the host device initiates the communication. A client device is typically controlled through a chip select known as Client Select. Some examples of client devices include serial EEPROMs, shift registers, display drivers, A/D converters, and other PIC® devices with SPI capabilities. The SPI bus specifies four signal connections: • Serial Clock (SCK) • Serial Data Out (SDO) • Serial Data In (SDI) • Client Select (SS) The following figure shows the block diagram of the SPI module. Figure 35-1. SPI Module Simplified Block Diagram Data bus Rev. 10-000076B 11/2/2018 Read Write 8 8 Receive FIFO (2 deep) Transmit FIFO (2 deep) 8 SDI SPIxSDIPPS 8 Receive Shift Register SDIP SS_in SPIxSSPPS RXR 1 SDO Transmit Serializer(1) TXR RxyPPS SDOP 1 SCK_out 0 RxyPPS SSP SSET CKP SPI Control Module and Transfer Counter 1 See SPIxCLK Register SCK Generator 1 SS_out 0 1 0 RxyPPS SSP SSET SPIxBAUD MST CLKSEL SCK_in SPIxSCKPPS CKP Note: 1. If the transmit FIFO is empty and TXR = 1, the previous value of the receive shift register will be sent to the transmit serializer. The SPI transmit output (SDO_out) is available to the remappable PPS SDO pin and internally to the select peripherals. The SPI bus typically operates with a single host device and one or more client devices. When multiple client devices are used, an independent Client Select connection is required from the host device to each client device. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 556 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module The host selects only one client at a time. Most client devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. Transmissions typically involve Shift registers, eight bits in size, one in the host and one in the client. With either the host or the client device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new bit is shifted into the device. Unlike older Microchip devices, the SPI module on this device contains one register for incoming data and another register for outgoing data. Both registers also have multibyte FIFO buffers and allow for DMA bus connections. The figure below shows a typical connection between two devices configured as host and client devices. Figure 35-2. SPI Host/Client Connection with FIFOs Rev. 10-000080C 1/11/2019 SPI Host: MST = 1 LSb MSb Transmit Shift Register Transmit FIFO (SPIxTXB) SDOx SDIx Receive FIFO (SPIxRXB) (Note 1) Receive FIFO (SPIxRXB) Receive Shift Register MSb LSb Device 1 SPI Client: MST = 0 LSb MSb Receive Shift Register (Note 1) Transmit FIFO (SPIxTXB) SDIx SCKx SSxOUT/ GPIO SDOx Serial clock Client Select (optional) SCKx SSxIN Transmit Shift Register MSb LSb Device 2 Notes: 1. In some modes, if the Transmit FIFO is empty, the most recently received byte of data will be transmitted. 2. This diagram assumes that the LSBF bit is cleared (communications are MSb-first). When LSBF is set, the communications will be LSb-first. Data is shifted out of the transmit FIFO on the programmed clock edge and into the receive Shift register on the opposite edge of the clock. The host device transmits information on its SDO output pin which is connected to, and received by, the client’s SDI input pin. The client device transmits information on its SDO output pin, which is connected to, and received by, the host’s SDI input pin. The host device sends out the clock signal. Both the host and the client devices need to be configured for the same clock phase and clock polarity. During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the host device is sending out the MSb from its output register (on its SDO pin) and the client device is reading this bit and saving it as the LSb of its input register. The client device is also sending out the MSb from its Shift register (on its SDO pin) and the host device is reading this bit and saving it as the LSb of its input register. After eight bits have been shifted out, the host and client have exchanged register values and stored the incoming data into the receiver FIFOs. If there is more data to exchange, the registers are loaded with new data and the process repeats. Whether the data is meaningful or not (dummy data) depends on the application software. This leads to three scenarios for data transmission: • Host sends useful data and client sends dummy data • Host sends useful data and client sends useful data • Host sends dummy data and client sends useful data © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 557 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module In this SPI module, dummy data may be sent without software involvement. Dummy transmit data is automatically handled by clearing the TXR bit and receive data is ignored by clearing the RXR bit. See Table 35-1 as well as Host Mode and Client Mode for further TXR/RXR setting details. This SPI module can send transmissions of any number of bits, and can send information in segments of varying size (from 1-8 bits in width). As such, transmissions may involve any number of clock cycles, depending on the amount of data to be transmitted. When there is no more data to be transmitted, the host stops sending the clock signal and deselects the client. Every client device connected to the bus that has not been selected through its Client Select line disregards the clock and transmission signals and does not transmit out any data of its own. 35.1 SPI Controls The following registers control the SPI operation: • SPI Interrupt Flag (SPIxINTF) Register • SPI Interrupt Enable (SPIxINTE) Register • SPI Byte Count High and Low (SPIxTCNTH/L) Registers • SPI Bit Count (SPIxTWIDTH) Register • SPI Baud Rate (SPIxBAUD) Register • SPI Control (SPIxCON0) Register 0 • SPI Control (SPIxCON1) Register 1 • SPI Control (SPIxCON2) Register 2 • SPI FIFO Status (SPIxSTATUS) Register • SPI Receiver Buffer (SPIxRXB) Register • SPI Transmit Buffer (SPIxTXB) Register • SPI Clock Select (SPIxCLK) Register SPIxCON0, SPIxCON1 and SPIxCON2 are control registers for the SPI module. SPIxSTATUS reflects the status of both the SPI module and the receive and transmit FIFOs. SPIxBAUD and SPIxCLK control the Baud Rate Generator (BRG) of the SPI module when in Host mode. The SPIxCLK selects the clock source that is used by the BRG. The SPIxBAUD configures the clock divider used on that clock source. More information on the BRG is available in the Host Mode SPI Clock Configuration section. SPIxTxB and SPIxRxB are the Transmit and Receive Buffer registers used to send and receive data on the SPI bus. The Transmit and Receive Buffer registers offer indirect access to Shift registers that are used for shifting the data in and out. Both registers access the multibyte FIFOs, allowing for multiple transmissions or receptions to be stored between software transfers of the data. The SPIxTCNTH:L register pair either count or control the number of bits or bytes in a data transfer. When BMODE = 1, the SPIxTCNT value signifies bytes and the SPIxTWIDTH value signifies the number of bits in a byte. When BMODE = 0, the SPIxTCNT value is concatenated with the SPIxTWIDTH register to signify bits. In Host Receive Only mode (TXR = 0 and RXR = 1), the data transfer is initiated by writing SPIxTCNT with the desired bit or byte value to transfer. In Host Transmit mode (TXR = 1), the data transfer is initiated by writing the SPIxTxB register, in which case the SPIxTCNT is a down counter for the bits or bytes transferred. The SPIxINTF and SPIxINTE are the flags and enables, respectively, for SPI specific interrupts. They are tied to the SPIxIF flag and SPIxIE enable bit in the PIR and PIE registers, which is triggered when any interrupt contained in the SPIxINTF/SPIxINTE registers is triggered. The PIR/PIE registers also contain SPIxTXIF/SPIxTXIE bits, which are the Interrupt flag and Enable bit for the SPI Transmit Interrupt, as well as the SPIxRXIF/SPIxRXIE bits, which are the Interrupt flag and Enable bit for the SPI receive interrupt. 35.2 SPI Operation When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits of the SPIxCON0, SPIxCON1 and SPIxCON2 registers. These control bits allow the following to be configured: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 558 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module • • • • • • • • • • • 35.2.1 Host mode (SCK is the clock output) Client mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Input, Output, and Client Select Polarity Data Input Sample Phase (middle or end of data output time) Clock Edge (output data on first/second edge of SCK) Clock Rate (Host mode only) Client Select mode (Host or Client mode) MSB-First or LSB-First Receive/Transmit modes: – Full Duplex – Receive Only (receive without transmit) – Transmit Only (transmit without receive) Transfer Counter mode (only available in Transmit Only mode) Enabling and Disabling the SPI Module Setting the EN bit enables the SPI peripheral. However, to reset or reconfigure the SPI mode, the EN bit must be cleared. Setting the EN bit enables the SPI inputs and outputs: SDI, SDO, SCK_out, SCK_in, SS_out and SS_in. The pins for all of these inputs and outputs are selected by the PPS controls, and thus must have their functions mapped properly to the device pins to function. Refer to the “PPS - Peripheral Pin Select Module” chapter for more details. SS_out and SCK_out must have the pins to which they are assigned set as outputs (TRIS bits must be ‘0’) to properly output. Clearing the TRIS bit of the SDO pin will cause the SPI module to always control that pin, but is not necessary for SDO functionality (see the Input and Output Polarity Control section). Configurations selected by the following registers will not be changed while the EN bit is set: • SPIxBAUD • SPIxCON1 • SPIxCON0 (with the exception of clearing the EN bit) Clearing the EN bit aborts any transmissions in progress, disables the setting of interrupt flags by hardware, and resets the FIFO occupancy (see the Transmit and Receive FIFOs section). 35.2.2 BUSY Bit While a data transfer is in progress, the SPI hardware sets the BUSY bit. This bit can be polled by the user to determine the current status of the SPI module, and to know when a communication is complete. The following registers and bits will not be changed by software while the BUSY bit is set: • SPIxTCNT • SPIxTWIDTH • SPIxCON2 • The CLB bit Important:  1. The BUSY bit is subject to synchronization delay of up to two instruction cycles. The user must wait for it to set after loading the transmit buffer (SPIxTXB register) before using it to determine the status of the SPI module. 2. It is also not recommended to read SPIxTCNT while the BUSY bit is set, as the value in the registers may not be a reliable indicator of the transfer counter. Use the TCZIF bit to accurately determine that the transfer counter has reached zero. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 559 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.2.3 Transmit and Receive FIFOs The transmission and reception of data from the SPI module is handled by two FIFOs, one for reception and one for transmission. These are addressed by the SFRs, SPIxRXB and SPIxTXB, respectively. The transmit FIFO is written to by software and is read by the SPI module to shift the data onto the SDO pin. The receive FIFO is written to by the SPI module as it shifts in the data from the SDI pin and is read by software. Setting the CLB bit resets the occupancy for both FIFOs, emptying both buffers. The FIFOs are also reset by clearing the EN bit, thus disabling the SPI module. Important:  The transmit and receive FIFO occupancy refer to the number of bytes that are currently being stored in each FIFO. These values are used in this chapter to illustrate the function of these FIFOs and are not directly accessible through software. The SPIxRXB register addresses the receive FIFO and is read-only. Reading from this register will read from the first FIFO location that was written to by hardware and decrease the receive FIFO occupancy. If the FIFO is empty, reading from this register will instead return a value of ’0’ and set the RXRE (Receive Buffer Read Error) bit. The RXRE bit must then be cleared in software to properly reflect the status of the read error. When the receive FIFO is full, the RXBF bit will be set. The SPIxTXB register addresses the transmit FIFO and is write-only. Writing to the register will write to the first empty FIFO location and increase the occupancy. If the FIFO is full, writing to this register will not affect the data and will set the TXWE bit. When the transmit FIFO is empty, the TXBE bit will be set. More details on enabling and disabling the receive and transmit functions is summarized in Table 35-1 and Client Mode Transmit Options. 35.2.4 LSb vs. MSb-First Operation Typically, the SPI communication outputs the Most Significant bit first, but some devices or buses may not conform to this standard. In this case, the LSBF bit may be used to alter the order in which bits are shifted out during the data exchange. In both Host and Client mode, the LSBF bit controls whether data is shifted MSb or LSb first. Clearing the bit (default) configures the data to transfer MSb first, which conforms to traditional SPI operation, while setting the bit configures the data to transfer LSb first. 35.2.5 Input and Output Polarity Control SPIxCON1 has three bits that control the polarity of the SPI inputs and outputs: • The SDIP bit controls the polarity of the SDI input • The SDOP bit controls the polarity of the SDO output • The SSP bit controls the polarity of both the client SS input and the host SS output For all three bits, when the bit is clear, the input or output is active-high, and when the bit is set, the input or output is active-low. When the EN bit is cleared, SS_out and SCK_out both revert to the Inactive state dictated by their polarity bits. The SDO Output state, when the EN bit is cleared, is determined by several factors as follows: • When the associated TRIS bit for the SDO pin is cleared, and the SPI goes Idle after a transmission, the SDO output will remain at the last bit level. • When the associated TRIS bit for the SDO pin is set, its behavior varies in Client and Host modes: – In Client mode, the SDO pin tri-states when any of the following is true: • Client Select is inactive • EN = 0 • TXR = 0 – In Host mode: • The SDO pin tri-states when TXR = 0 • When TXR = 1 and the SPI goes Idle after a transmission, the SDO output will remain at the last bit level. The SDO pin will revert to the Idle state when EN is cleared. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 560 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.2.6 Transfer Counter In all Host modes, the transfer counter can be used to determine how many data transfers the SPI will send/receive. The transfer counter is comprised of the SPIxTCNT registers, and is also partially controlled by the SPIxTWIDTH register. The transfer counter has two primary modes, determined by the BMODE bit. Each mode uses the SPIxTCNT and SPIxTWIDTH registers to determine the number and size of the transfers. In both modes, when the transfer counter reaches zero, the TCZIF interrupt flag is set. Important:  In all Client modes and when BMODE = 1 in Host modes, the transfer counter will still decrement as transfers occur and can be used to count the number of messages sent/received, control SS_out, and trigger TCZIF. Also, when BMODE = 1, the SPIxTWIDTH register can be used in Host and Client modes to determine the size of messages sent and received by the SPI, even if the transfer counter is not being actively used to control the number of messages being sent/received by the SPI module. 35.2.6.1 Total Bit Count Mode (BMODE = 0) In this mode, SPIxTCNT and SPIxTWIDTH are concatenated to determine the total number of bits to be transferred. These bits will be loaded from/into the transmit/receive FIFOs in 8-bit increments and the transfer counter will be decremented by eight until the total number of remaining bits is less than eight. If there are any remaining bits (SPIxTWIDTH ≠ 0), the transmit FIFO will send out one final message with any extra bits greater than the remainder ignored. The SPIxTWIDTH is the remaining bit count but the value does not change as it does for the SPIxTCNT value. The receiver will load a final byte into the receiver FIFO, and pad the extra bits with zeros. The LSBF bit determines whether the Most Significant or Least Significant bits of this final byte are ignored or padded. For example, when LSBF = 0 and the final transfer contains only two bits, then if the last byte sent was 0x5F, the RXB of the receiver will contain 0x40 which are the two MSbs of the final byte padded with zeros in the LSbs. In this mode, the SPI host will only transmit messages when the SPIxTCNT value is greater than zero, regardless of the TXR and RXR settings. In Host Transmit mode, the transfer starts with the data write to the SPIxTXB register or the count value written to the SPIxTCNTL register, whichever occurs last. In Host Receive Only mode, the transfer clocks start when the SPIxTCNTL value is written. Transfer clocks are suspended when the receive FIFO is full and resume as the FIFO is read. 35.2.6.2 Variable Transfer Size Mode (BMODE = 1) In this mode, SPIxTWIDTH specifies the width of every individual piece of the data transfer in bits. SPIxTCNT specifies the number of transfers of this bit length. If SPIxTWIDTH = 0, each piece is a full byte of data. If SPIxTWIDTH ≠ 0, then only that specified number of bits from the transmit FIFO are shifted out, with the unused bits ignored. Received data is padded with zeros in the unused bit areas when transferred into the receive FIFO. The LSBF bit determines whether the Most Significant or Least Significant bits of the transfers are ignored or padded. In this mode, the transfer counter being zero only stops messages from being sent or received when in Receive Only mode. Important:  With BMODE = 1, it is possible for the transfer counter (SPIxTCNT) to decrement below zero, although when in Host Receive Only mode, transfer clocks will cease when the transfer counter reaches zero. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 561 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.2.6.3 Transfer Counter in Client Mode In Client mode, the transfer counter will still decrement as data is shifted in and out of the SPI module, but it will not control data transfers. The BMODE bit along with the transfer counter is used to determine when the device will look for Client Select faults. When BMODE = 0, the SSFLT bit will be set if Client Select transitions from its Active to Inactive state during bytes of data, or if it transitions before the last bit sent during the final byte (if SPIxTWIDTH ≠ 0). When BMODE = 1, the SSFLT bit will be set if Client Select transitions from its Active to Inactive state before the final bit of each individual transfer is completed. Note:  SSFLT does not have an associated interrupt, so it will be checked in software. An ideal time to do this is when the End of Client Select Interrupt (EOSIF) is triggered (see the Start of Client Select and End of Client Select Interrupts section). 35.3 Host Mode In Host mode, the device controls the SCK line, and as such, initiates data transfers and determines when any clients broadcast data onto the SPI bus. Host mode can be configured in four different modes, configured by the TXR and RXR bits: • Full Duplex mode • Receive Only mode • Transmit Only mode • Transfer Off mode The modes are illustrated in the following table: Table 35-1. Host Mode TXR/RXR Settings RXR = 1 TXR = 1 TXR = 0 Full Duplex mode BMODE = 1: Transfer when RxFIFO is not full and TxFIFO is not empty Receive Only mode Transfer when RxFIFO is not full and the Transfer Counter is nonzero BMODE = 0: Transfer when RXFIFO is not full, TXFIFO is not empty, and the Transfer Counter is nonzero Transmitted data is either the top of the FIFO or the most recently received data Transmit Only mode BMODE = 1: Transfer when TxFIFO is not empty RXR = 0 BMODE = 0: Transfer when TXFIFO is not empty and the Transfer Counter is nonzero No Transfers Received data is not stored 35.3.1 Full Duplex Mode When both TXR and RXR are set, the SPI host is in Full Duplex mode. In this mode, data transfer triggering is affected by the BMODE bit. When BMODE = 1, data transfers will occur whenever the receive FIFO is not full and data is present in the transmit FIFO. In practice, as long as the receive FIFO is not full, data will be transmitted/received as soon as the SPIxTXB register is written to, matching the functionality of SPI (MSSP) modules on older 8-bit Microchip devices. The SPIxTCNT will decrement with each transfer. However, when SPIxTCNT is zero, the next transfer is not inhibited and the corresponding SPIxTCNT decrement will cause the count to roll over to the maximum value. The following figure shows an example of a communication using this mode. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 562 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module Figure 35-3. SPI Host Operation - Data Exchange, RXR = 1, TXR = 1 Rev. 10-000281A 11/9/2018 Software Write to SPIxTCNT SPIxTCNT Note 2 0 5 4 3 2 1 0 Software Write To TXR TXR Software Write to RXR RXR SCK_out Note 3 SDO_out `HX `HX SRMTIF TCZIF Note 2 Software Write to SPIxTXB TXFIFO Occupancy 0 1 2 1 2 1 2 1 0 1 0 SPIxTIF Software Read from SPIxRXB RXFIFO Occupancy 0 1 0 1 0 1 0 1 0 1 0 SPIxRIF Notes: 1. SS(out) is not shown on this diagram. 2. SPIxTCNT write is optional when TXR/RXR = 1/1 and BMODE = 1. If BMODE = 0, a write to SPIxTCNT is required to start transmission; TCZIF signals the transition of SPIxTCNT from 1 to 0. 3. Transmission gap occurs while waiting for transmitter data. When BMODE = 0, the transfer counter (SPIxTCNT) must also be written to before transfers will occur. Transfers will cease when the transfer counter reaches ‘0’. For example, if SPIxTXB is written twice and then SPIxTCNTL is written with ‘3’, the transfer will start with the SPIxTCNTL write. The two bytes in the TXFIFO will be sent after which the transfer will suspend until the third and last byte is written to SPIxTXB. 35.3.2 Transmit Only Mode When TXR is set and RXR is clear, the SPI host is in Transmit Only mode. In this mode, data transfer triggering is affected by the BMODE bit. When BMODE = 1, data transfers will occur whenever the transmit FIFO is not empty. Data will be transmitted as soon as the SPIxTXB register is written to, matching the functionality of the SPI (MSSP) modules on previous 8-bit devices. The SPIxTCNT will decrement with each transfer. However, when SPIxTCNT is zero the next transfer is not inhibited and the corresponding SPIxTCNT decrement will cause the count to roll over to the maximum value. Any data received in this mode is not stored in the receive FIFO. The following figure shows an example of sending a command and then sending a byte of data, using this mode. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 563 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module Figure 35-4. SPI Host Operation - Command+Write Data, TXR = 1, RXR = 0 Rev. 10-000282A 11/6/2018 Software Write to TXTCNTL Note 2 0 SPIxTXCNT -1 -2 3 2 1 0 Software Write to TXR TXR Software Write to RXR RXR SCK_out SDO_out Shifted data out SRMTIF Note 3 BCZIF Software Write to SPIxTXB TxFIFO Occupancy Note 4 0 1 2 1 0 1 2 1 2 1 0 SPIxTIF Notes: 1. SS_out is not shown. 2. The byte counter is optional when TXR/RXR = 1/0. 3. After the command bytes, wait for SRMTIF before loading SPIxTXB, otherwise the command data will decrement SPIxTXCNT. Alternatively, load SPIxTXCNT = 5 and count the command bytes also; TCZIF signals the end of the transmission. 4. Transmit data interrupt handler (or DMA) must write only the bytes necessary; the byte counter is not available as an indicator. 5. Reading the SPIxRXB is not required because RXR = 0. When BMODE = 0, the transfer counter (SPIxTCNT) must also be written to before transfers will occur, and transfers will cease when the transfer counter reaches ‘0’. For example, if SPIxTXB is written twice and then SPIxTCNTL is written with ‘3’, the transfer will start with the SPIxTCNTL write. The two bytes in the TXFIFO will be sent after which the transfer will suspend until the third and last byte is written to SPIxTXB. 35.3.3 Receive Only Mode When RXR is set and TXR is clear, the SPI host is in Receive Only mode. In this mode, data transfers when the receive FIFO is not full and the transfer counter is nonzero. In this mode, writing a value to SPIxTCNTL will start the clocks for transfer. The clocks will suspend while the receive FIFO is full and cease when the SPIxTCNT reaches zero (see the Transfer Counter section). If there is any data in the transmit FIFO, the first data written to SPIxTXB will be transmitted on each data exchange, although the transmit FIFO occupancy will not change, meaning that the same message will be sent on each transmission. If there is no data in the transmit FIFO, the most recently received data will be transmitted. The following figure shows an example of sending a command using the Transmit Only mode and then receiving a byte of data using the Receive Only mode. Important:  When operating in Receive Only mode and the size of every SPI transaction is less than 8 bits, it is recommended to operate in BMODE = 1 mode. The size of the packet can be configured using the SPIxTWIDTH register. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 564 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module Figure 35-5. SPI Host Operation - Command+Read Data, TXR = 0, RXR = 1 Rev. 10-000283A 11/6/2018 Software Write to TxCNTL 0 SPIxTXCNT -1 -2 3 2 1 0 Software Write to TXR TXR Software Write to RXR RXR SCK_out SDO_out Shifted data out Note 2 SRMTIF TCZIF Software Write to SPIxTXB TXFIFO Occupancy 0 1 2 1 0 Software Read from SPIxRXB RXFIFO Occupancy 0 1 0 1 0 1 0 SPIxRIF Notes: 1. SS_out is not shown. 2. Software must wait for shift-register empty (SRMTIF) before changing TXR, RXR, SPIxTCNT and SPIxTWIDTH controls. This is not considered an imposition in this case, because the client likely needs time to load output data. 35.3.4 Transfer Off Mode When both TXR and RXR are cleared, the SPI host is in Transfer Off mode. In this mode, SCK will not toggle and no data is exchanged. However, writes to SPIxTXB will be transferred to the transmit FIFO which will then be transmitted when the TXR bit is set. 35.3.5 Host Mode Client Select Control 35.3.5.1 Hardware Client Select Control The SPI module allows for direct hardware control of a Client Select output. The Client Select output (SS_out) is controlled both directly, through the SSET bit, and indirectly by the hardware while the transfer counter is nonzero (see the Transfer Counter section). The SS_out pin is selected with the PPS controls. The SS_out polarity is controlled by the SSP bit. Setting the SSET bit will assert SS_out. Clearing the SSET bit will leave SS_out to be controlled by the transfer counter. When the transfer counter is loaded, the SPI module will automatically assert SS_out. When the transfer counter decrements to zero, the SPI module will deassert SS_out either one baud period after the final SCK pulse of the final transfer (when CKE/SMP = 0/1) or one half baud period otherwise, as shown in the following figure. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 565 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module Figure 35-6. SPI Host SS Operation - CKE = 0, BMODE = 1, TWIDTH = 0, SSP = 0 Rev. 10-000284A 11/6/2018 SPIEN baud_clock Software Write to SPIxTCNTL Transfer Counter 1 0 SS_out minimum 1 baud clock when FST = 0 approx. 1 baud clock SCK_out SDO_bit_number 7 6 5 4 3 2 1 0 Notes: 1. SDO bit number illustrates the transmitted bit number, and is not intended to imply SDO_out tristate operation. 2. Assumes SPIxTXB holds data when SPIxTCNTL is written. 35.3.5.2 Software Client Select Control Client Select can be controlled through software via a general purpose I/O pin. In this case, ensure that the desired pin is configured as a general purpose output with the PPS and TRIS controls. In this case, SSET will not affect the Client Select, the Transfer Counter will not automatically control the Client Select output, and all setting and clearing of the Client Select output line must be directly controlled by software. 35.3.6 Host Mode SPI Clock Configuration 35.3.6.1 SPI Clock Selection The clock source for SPI Host modes is selected by the SPIxCLK register. The SPIxBAUD register allows for dividing this clock. The frequency of the SCK output is defined by the following equation: Equation 35-1. SCK Output Frequency FCSEL FBAUD = 2 × BAUD + 1 where FBAUD is the baud rate frequency output on the SCK pin, FCSEL is the frequency of the input clock selected by the SPIxCLK register, and BAUD is the value contained in the SPIxBAUD register. 35.3.6.2 Clock and Data Change Alignment The CKP, CKE and SMP bits control the relationship between the SCK clock output, SDO output data changes, and SDI input data sampling. The bit functions are as follows: • CKP controls SCK output polarity • CKE controls SDO output change relative to the SCK clock • SMP controls SDI input sampling relative to the clock edges The CKE bit, when set, inverts the low Idle state of the SCK output to a high Idle state. The following figures illustrate the eight possible combinations of the CKP, CKE and SMP bit selections. Important:  All timing diagrams assume the LSBF bit is cleared. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 566 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module Figure 35-7. Clocking Detail - Host Mode, CKE = 0, SMP = 0 Rev. 10-000276A 11/6/2018 MST = 1,CKE = 0, SMP = 0 A SCK SDO Previous bit 0 I A I A I A I A I A I A I A bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 A A A A A A A A I CKP = 0 input sample clock SCK SDO Previous bit 0 I bit 7 I bit 6 I bit 5 I bit 4 I bit 3 I bit 2 I bit 1 I CKP = 1 bit 0 input sample clock TXFIFO determined RXFIFO Occupancy increments TXFIFO Occupancy decrements SPIxRIF and SPIxTIF interrupts trigger Open RXFIFO latch Figure 35-8. Clocking Detail - Host Mode, CKE = 1, SMP = 1 Rev. 10-000315A 11/6/2018 MST = 1, CKE = 1, SMP = 1 A SCK bit 7 SDO input sample clock input sample clock A I A I A I A I A I A I A bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 I I I I I I I I next tx_buf write A SCK SDO I bit 7 A bit 6 A bit 5 A bit 4 A bit 3 A bit 2 A bit 1 tx_buf write TXFIFO determined © 2020-2021 Microchip Technology Inc. and its subsidiaries Open RXFIFO latch Preliminary Datasheet A bit 0 CKP = 0 I next CKP = 1 RXFIFO Occupancy increments TXFIFO Occupancy decrements SPIxRIF and SPIxTIF interrupts trigger DS40002214E-page 567 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module Figure 35-9. Clocking Detail - Host Mode, CKE = 0, SMP = 1 Rev. 10-000277A 11/6/2018 MST = 1, CKE = 0, SMP = 1 SCK A SDO previous bit 0 bit 7 bit 6 SCK A A SDO previous bit 0 bit 7 I A I A I A bit 5 I A bit 4 I A bit 3 I A bit 2 I bit 1 A I CKP = 0 bit 0 input sample clock I I I A bit 6 A bit 5 I I A bit 4 I A bit 3 A bit 2 I bit 1 A I CKP = 1 bit 0 input sample clock TXFIFO determined Open RXFIFO latch RXFIFO Occupancy increments, TXFIFO Occupancy decrements, SPIxRIF and SPIxTIF interrupts trigger Figure 35-10. Clocking Detail - Host Mode, CKE = 1, SMP = 0 Rev. 10-000278A 11/6/2018 MST = 1, CKE = 1, SMP = 0 SCK A I I SDO bit 7 A I A I A I A I I A A I A bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 I I I I I I I CKP = 0 tx_buf write input sample clock SCK I SDO A bit 7 A bit 6 A bit 5 A bit 4 A bit 3 A bit 2 A bit 1 A bit 0 CKP = 1 tx_buf write input sample clock TXFIFO to SDO Open RXFIFO latch RXFIFO Occupancy increments, TXFIFO Occupancy decrements, SPIxRIF and SPIxTIF interrupts trigger 35.3.6.3 SCK Start-Up Delay When starting an SPI data exchange, the host device asserts the SS output, by either setting the SSET bit or loading the TCNT value, and then triggers the module to send data by writing SPIxTXB. These data triggers are synchronized to the clock selected by the SPIxCLK register before the first SCK pulse appears, usually requiring one or two clock periods of the selected SPI source clock. The SPI module includes additional synchronization delays on SCK generation specifically designed to ensure that the Client Select output timing is correct, without requiring precision software timing loops. By default, this synchronization delay is ½ baud period. When the value of the SPIxBAUD register is a small number (indicating higher SCK frequencies), the code execution delay between asserting SS and writing SPIxTXB is relatively long compared to the added synchronization delay before the first SCK edge. With larger values of SPIxBAUD (indicating lower SCK frequencies), the code execution delay is much smaller relative to the synchronization delay. Therefore, the first SCK edge after SS is asserted will be closer to the synchronization delay. Setting the FST bit removes the synchronization delay, allowing systems with low SPIxBAUD values (and thus, long synchronization delays) to forgo this extra delay, in which case the time between the SS assertion and the first SCK edge depends entirely on the code execution delay. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 568 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.4 Client Mode 35.4.1 Client Mode Transmit Options The SDO output of the SPI module in Client mode is controlled by the following: • TXR bit • TRIS bit associated with the SDO pin • Client Select input • Current state of the transmit FIFO This control is summarized in the following table where TRISxn refers to the bit in the TRIS register corresponding to the pin that SDO has been assigned with PPS, TXR is the Transmit Data Required Control bit, SS is the state of the Client Select input, and TXBE is the transmit FIFO Buffer Empty bit. Table 35-2. Client Mode Transmit TRISxn(1) TXR SS TXBE 0 0 FALSE 0 Drives state determined by LATxn(2) 0 0 FALSE 1 Drives state determined by LATxn(2) 0 0 TRUE 0 Outputs the oldest byte in the transmit FIFO Does not remove data from the transmit FIFO 0 0 TRUE 1 Outputs the most recently received byte 0 1 FALSE 0 Drives state determined by LATxn(2) 0 1 FALSE 1 Drives state determined by LATxn(2) 0 1 TRUE 0 Outputs the oldest byte in the transmit FIFO Removes transmitted byte from the transmit FIFO Decrements occupancy of transmit FIFO 0 1 TRUE 1 Outputs the most recently received byte Sets the TXUIF bit 1 0 FALSE 0 Tri-stated 1 0 FALSE 1 Tri-stated 1 0 TRUE 0 Tri-stated 1 0 TRUE 1 Tri-stated 1 1 FALSE 0 Tri-stated 1 1 FALSE 1 Tri-stated 1 1 TRUE 0 Outputs the oldest byte in the transmit FIFO Removes transmitted byte from the transmit FIFO Decrements the FIFO occupancy 1 1 TRUE 1 Outputs the most recently received byte Sets the TXUIF bit SDO State Notes:  1. TRISxn is the bit in the TRISx register corresponding to the pin to which SDO has been assigned with PPS. 2. LATxn is the bit in the LATx register corresponding to the pin to which SDO has been assigned with PPS. 35.4.1.1 SDO Drive/Tri-state The TRIS bit associated with the SDO pin controls whether the SDO pin will tri-state. When this TRIS bit is cleared, the pin will always be driving to a level, even when the SPI module is inactive. When the SPI module is inactive © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 569 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module (either due to the host not clocking the SCK line or the SS being false), the SDO pin will be driven to the value of the LAT bit associated with the SDO pin. When the SPI module is active, its output is determined by both TXR and whether there is data in the transmit FIFO. When the TRIS bit associated with the SDO pin is set, the pin will only have an output level driven to it when TXR = 1 and the Client Select input is true. In all other cases, the pin will be tri-stated. Table 35-3. Client Mode Transmit TRISxn(1) TXR SS TXBE 0 0 FALSE 0 Output level determined by LATxn(2) 0 0 FALSE 1 Output level determined by LATxn(2) 0 0 TRUE 0 Outputs the oldest byte in the TXFIFO. Does not remove data from the TXFIFO. 0 0 TRUE 1 Outputs the most recently received byte 0 1 FALSE 0 Output level determined by LATxn(2) 0 1 FALSE 1 Output level determined by LATxn(2) 0 1 TRUE 0 Outputs the oldest byte in the TXFIFO. Removes transmitted byte from the TXFIFO. Decrements occupancy of TXFIFO. 0 1 TRUE 1 Outputs the most recently received byte. Sets the TXUIF bit. 1 0 FALSE 0 Tri-stated 1 0 FALSE 1 Tri-stated 1 0 TRUE 0 Tri-stated 1 0 TRUE 1 Tri-stated 1 1 FALSE 0 Tri-stated 1 1 FALSE 1 Tri-stated 1 1 TRUE 0 Outputs the oldest byte in the TXFIFO. Removes transmitted byte from the TXFIFO. Decrements occupancy of TXFIFO. 1 1 TRUE 1 Outputs the most recently received byte. Sets the TXUIF bit. SDO State Notes:  1. TRISxn is the bit in the TRISx register corresponding to the pin that SDO has been assigned with PPS. 2. LATxn is the bit in the LATx register corresponding to the pin that SDO has been assigned with PPS. 35.4.1.2 SDO Output Data The TXR bit controls the nature of the data that is transmitted in Client mode. When TXR is set, transmitted data is taken from the transmit FIFO. If the FIFO is empty, the most recently received data will be transmitted and the TXUIF flag will be set to indicate that a transmit FIFO underflow has occurred. When TXR is cleared, the data will be taken from the transmit FIFO, and the FIFO occupancy will not decrease. If the transmit FIFO is empty, the most recently received data will be transmitted, and the TXUIF bit will not be set. However, if the TRIS bit associated with the SDO pin is set, clearing the TXR bit will cause the SPI module to not output any data to the SDO pin. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 570 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.4.2 Client Mode Receive Options The RXR bit controls the nature of receptions in Client mode. When RXR is set, the SDI input data will be stored in the receive FIFO if it is not full. If the receive FIFO is full, the RXOIF bit will be set to indicate a receive FIFO overflow error and the data is discarded. When RXR is cleared, all received data will be ignored and not stored in the receive FIFO (although it may still be used for transmission if the transmit FIFO is empty). The following figure presents a typical Client mode communication, showing a case where the host writes two then three bytes, showing interrupts as well as the behavior of the transfer counter in Client mode (see the Transfer Counter in Client Mode section for more details on the transfer counter in Client mode as well as the SPI Interrupts section for more information on interrupts). Figure 35-11. SPI Client Mode Operation – Interrupt-Driven, Host Writes 2+3 Bytes Rev. 10-000285A 11/8/2018 SS_in SCK_in SDO_out SOSIF Note 1 Output data Note 2 EOSIF Transfer Counter 0 Software Write to SPIxTCNTL -1 -2 3 2 1 0 Note 3 TCZIF Software Write to TXR TXR Software Write to RXR RXR Receiver process SPIxRIF Software Read from SPIxRXB Notes: 1. This delay is exaggerated for illustration, and can be as short as1/2 bit period. 2. If the device is sleeping, SOSIF will wake it up for interrupt service. 3. Setting SPIxTCNTL is optional in this example, otherwise it will count -3, -4, -5, and TCZIF will not occur. 35.4.3 Client Mode Client Select In Client mode, an external Client Select signal can be used to synchronize communication with the host device. The Client Select line is held in its Inactive state (high by default) until the host device is ready to communicate. When the Client Select transitions to its Active state, the client knows that a new transmission is starting. When the Client Select goes false at the end of the transmission, the receive function of the selected SPI client device returns to the Inactive state. The client is then ready to receive a new transmission when the Client Select goes true again. The Client Select signal is received on the SS input pin. This pin is selected with the SPIxSSPPS register (refer to the “PPS Inputs” section). When the input on this pin is true, transmission and reception are enabled, and the SDO pin is driven. When the input on this pin is false, the SDO pin is either tri-stated (if the TRIS bit associated with the SDO pin is set) or driven to the value of the LAT bit associated with the SDO pin (if the TRIS bit associated with the SDO pin is cleared). The SCK input is ignored when the SS input is false. If the SS input goes false, while a data transfer is still in progress, it is considered a Client Select fault. The SSFLT bit indicates whether such an event has occurred. The transfer counter value determines the number of bits in a valid data transfer (see the Transfer Counter section for more details). The Client Select polarity is controlled by the SSP bit. When SSP is set (its default state), the Client Select input is active-low, and when it is cleared, the Client Select input is active-high. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 571 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module The Client Select for the SPI module is controlled by the SSET bit. When SSET is cleared (its default state), the Client Select will act as described above. When the bit is set, the SPI module will behave as if the SS input is always in its Active state. Important:  When SSET is set, the effective SS_in signal is always active. Hence, the SSFLT bit may be disregarded. 35.4.4 Client Mode Clock Configuration In Client mode, SCK is an input, and must be configured to the same polarity and clock edge as the host device. As in Host mode, the polarity of the clock input is controlled by the CKP bit and the clock edge used for transmitting data is controlled by the CKE bit. 35.4.5 Daisy-Chain Configuration The SPI bus can be connected in a daisy-chain configuration. The first client output is connected to the second client input, the second client output is connected to the third client input, and so on. The final client output is connected to the host input. Each client sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Client Select line from the host device connected to all client devices (alternately, the client devices can be configured to ignore the Client Select line by setting the SSET bit). In a typical daisy-chain configuration, the SCK signal from the host is connected to each of the client device SCK inputs. However, the SCK input and output are separate signals selected by the PPS control. When the PPS selection is made to configure the SCK input and SCK output on separate pins then, the SCK output will follow the SCK input, allowing for SCK signals to be daisy-chained like the SDO/SDI signals. The following two figures show block diagrams of a typical daisy-chain connection, and a daisy-chain connection with daisy-chained SPI clocks, respectively. Figure 35-12. Traditional SPI Daisy-Chain Connection Rev. 10-000082B 11/8/2018 SCK SCK SDOx SDIx SDIx SDOx SSxOUT/GPIO SSxIN SPI Host SPI Client #1 SCK SDIx SPI Client #2 SDOx SSxIN SCK SDIx SPI Client #3 SDOx SSxIN © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 572 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module Figure 35-13. SPI Daisy-Chain Connection with Chained SCK Rev. 10-000082C 11/8/2018 SCK(in) SCK SPI Host SDOx SPI Client #1 SDIx SDIx SSxIN SSxOUT/GPIO SCK(out) SDOx SCK(in) SDIx SSxIN SPI Client #2 SCK(out) SDOx SCK(in) SDIx SSxIN SPI Client #3 SDOx 35.5 SPI Operation in Sleep Mode The SPI Host mode will operate in Sleep, provided the clock source selected by SPIxCLK is active in Sleep mode. FIFOs will operate as they would when the part is awake. When TXR = 1, the transmit FIFO will need to contain data in order for transfers to take place in Sleep. All interrupts will still set the interrupt flags in Sleep, but only enabled interrupts will wake the device from Sleep. The SPI Client mode will operate in Sleep because the clock is provided by an external host device. FIFOs will still operate and interrupts will set interrupt flags, and enabled interrupts will wake the device from Sleep. 35.6 SPI Interrupts There are three top level SPI interrupts in the PIRx register: • • • SPI Transmit (SPIxTXIF) SPI Receive (SPIxRXIF) SPI Module status (SPIxIF) The SPI Module status interrupts are enabled at the module level in the SPIxINTE register. Only enabled status interrupts will cause the single top level SPIxIF flag to be set. 35.6.1 SPI Receive Interrupt The SPI receive interrupt is set when the receive FIFO contains data, and is cleared when the receive FIFO is empty. The interrupt flag, SPIxRXIF, is located in one of the PIR registers. The interrupt enable, SPIxRXIE, is located in the corresponding PIE register. The SPIxRXIF interrupt flag is read-only. 35.6.2 SPI Transmit Interrupt The SPI Transmit interrupt is set when the transmit FIFO is not full and can accept a character, and is cleared when the transmit FIFO is full and cannot accept a character. The interrupt flag, SPIxTXIF, is located in one of the PIR registers. The interrupt enable, SPIxTXIE, is located in the corresponding PIE register. The SPIxTXIF interrupt flag is read-only. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 573 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.6.3 SPI Status Interrupts The SPIxIF flag is located in one of the PIR registers. This flag is set when any of the individual status flags in SPIxINTF and their respective SPIxINTE bits are set. For any specific interrupt flag to interrupt normal program flow, both the SPIxIE bit, in the PIE register corresponding to the PIR register, and the specific bit in SPIxINTE associated with that interrupt must be set. The Status Interrupts include the following: • • • • • • Shift Register Empty (SRMTIF) Transfer Counter is Zero (TCZIF) Start of Client Select (SOSIF) End of Client Select (EOSIF) Receiver Overflow (RXOIF) Transmitter Underflow (TXUIF) 35.6.3.1 Shift Register Empty Interrupt The Shift Register Empty Interrupt Flag and Shift Register Empty Interrupt Enable are the SRMTIF and SRMTIE bits respectively. This interrupt is only available in Host mode and triggers when a data transfer completes and conditions are not present to start a new transfer, as dictated by the TXR and RXR bits (see Table 35-1 for conditions for starting a new Host mode data transfer with different TXR/ RXR settings). This interrupt will be triggered at the end of the last full bit period, after SCK has been low for one ½-baud period. See the figure below for more details of the timing of this interrupt as well as other interrupts. This bit will not clear itself when the conditions for starting a new transfer occur, and must be cleared in software. Figure 35-14. Transfer And Client Select Interrupt Timing Rev. 10-000286A 11/8/2018 SS_in SCK 7 SDO_bit_number 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 SRMTIF SOSIF Note 3 TCZIF EOSIF Notes: Note 3 1. SRMTIF available only in Host mode. 2. Clearing of interrupt flags is shown for illustration; actual interrupt flags must be cleared in software. 3. SOSIF and EOSIF are set according to SS_in, even in Host mode. 35.6.3.2 Transfer Counter Is Zero Interrupt The Transfer Counter Is Zero Interrupt Flag and Transfer Counter Is Zero Interrupt Enable are the TCZIF and TCZIE bits, respectively. This interrupt will trigger when the transfer counter (defined by BMODE, SPIxTCNT and SPIxTWIDTH) decrements from one to zero. See Figure 35-14 for more details on the timing of this interrupt as well as other interrupts. This bit must be cleared in software. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 574 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module Important:  The TCZIF flag only indicates that the transfer counter has decremented from one to zero, and may not indicate that the entire data transfer process is complete. Either poll the BUSY bit and wait for it to be cleared or use the Shift Register Empty Interrupt (SRMTIF) to determine when a data transfer is fully complete. 35.6.3.3 Start of Client Select and End of Client Select Interrupts The Start of Client Select Interrupt Flag and Start of Client Select Interrupt Enable are the SOSIF and SOSIE bits, respectively. The End of Client Select Interrupt Flag and End of Client Select Interrupt Enable are the EOSIF and EOSIE bits, respectively. These interrupts trigger at the leading and trailing edges of the Client Select input. The interrupts are active in both Host and Client mode, and will trigger on transitions of the Client Select input regardless of which mode the SPI is in. In Host mode, the PPS controls will be used to assign the Client Select input to the same pin as the Client Select output, allowing these interrupts to trigger on changes to the Client Select output. In Client mode, changing the SSET bit can trigger these interrupts, as it changes the effective input value of Client Select. Both SOSIF and EOSIF must be cleared in software. 35.6.3.4 Receiver Overflow and Transmitter Underflow Interrupts The receiver overflow interrupt triggers if data is received when the receive FIFO is already full and RXR = 1. In this case, the data will be discarded and the RXOIF bit will be set. The Receiver Overflow Interrupt Enable bit is RXOIE. The Transmitter Underflow Interrupt flag triggers if a data transfer begins when the transmit FIFO is empty and TXR = 1. In this case, the most recently received data will be transmitted and the TXUIF bit will be set. The Transmitter Underflow Interrupt Enable bit is TXUIE. Both these interrupts will only occur in Client mode, as Host mode will not allow the receive FIFO to overflow or the transmit FIFO to underflow. 35.7 Register Definitions: Serial Peripheral Interface Long bit name prefixes for the SPI peripherals are shown in the table below where “x” refers to the SPI instance number. Refer to the “Long Bit Names” section in the “Register and Bit Naming Conventions” chapter for more information. Table 35-4. SPI Long Bit Name Prefixes Peripheral Bit Name Prefix SPI1 SPI1 SPI2 SPI2 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 575 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.7.1 SPIxCON0 Name:  Address:  SPIxCON0 0x084,0x091 SPI Control Register 0 Bit Access Reset 7 EN R/W 0 6 5 4 3 2 LSBF R/W 0 1 MST R/W 0 0 BMODE R/W 0 Bit 7 – EN SPI Enable Value Description 1 SPI is enabled 0 SPI is disabled Bit 2 – LSBF  LSb-First Data Exchange Select(1) Value Description 1 Data is exchanged LSb first 0 Data is exchanged MSb first (traditional SPI operation) Bit 1 – MST  SPI Host Operating Mode Select(1) Value Description 1 SPI module operates as the bus host 0 SPI module operates as a bus client Bit 0 – BMODE  Bit-Length Mode Select(1) Value Description 1 SPIxTWIDTH setting applies to every byte: total bits sent is SPIxTWIDTH*SPIxTCNT, end-of-packet occurs when SPIxTCNT = 0 0 SPIxTWIDTH setting applies only to the last byte exchanged; total bits sent is SPIxTWIDTH + (SPIxTCNT*8) Note:  1. Do not change this bit when EN = 1. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 576 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.7.2 SPIxCON1 Name:  Address:  SPIxCON1 0x085,0x092 SPI Control Register 1 Bit Access Reset 7 SMP R/W 0 6 CKE R/W 0 5 CKP R/W 0 4 FST R/W 0 3 2 SSP R/W 1 1 SDIP R/W 0 0 SDOP R/W 0 Bit 7 – SMP SPI Input Sample Phase Control Value Mode Description 1 Client Reserved 1 Host SDI input is sampled at the end of data output time 0 Client or Host SDI input is sampled in the middle of data output time Bit 6 – CKE Clock Edge Select Value Description 1 Output data changes on transition from Active to Idle clock state 0 Output data changes on transition from Idle to Active clock state Bit 5 – CKP Clock Polarity Select Value Description 1 Idle state for SCK is high level 0 Idle state for SCK is low level Bit 4 – FST Fast Start Enable Value Mode Description x Client This bit is ignored 1 Host Delay to first SCK may be less than ½ baud period 0 Host Delay to first SCK will be at least ½ baud period Bit 2 – SSP Client Select Input/Output Polarity Control Value Description 1 SS is active-low 0 SS is active-high Bit 1 – SDIP SPI Input Polarity Control Value Description 1 SDI input is active-low 0 SDI input is active-high Bit 0 – SDOP SPI Output Polarity Control Value Description 1 SDO output is active-low 0 SDO output is active-high © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 577 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.7.3 SPIxCON2 Name:  Address:  SPIxCON2 0x086,0x093 SPI Control Register 2(3) Bit Access Reset 7 BUSY R 0 6 SSFLT R 0 5 4 3 2 SSET R/W 0 1 TXR R/W 0 0 RXR R/W 0 Bit 7 – BUSY  SPI Module Busy Status(1) Value Description 1 Data exchange is busy 0 Data exchange is not taking place Bit 6 – SSFLT SS_in Fault Status Value Condition Description x SSET = 1 This bit is unchanged 1 SSET = 0 SS_in ended the transaction unexpectedly, and the data byte being received was lost 0 SSET = 0 SS_in ended normally Bit 2 – SSET Client Select Enable Value Mode Description 1 Host SS_out is driven to the Active state continuously 0 Host SS_out is driven to the Active state while the transmit counter is not zero 1 Client SS_in is ignored and data is clocked on all SCK_in (as though SS = TRUE at all times) 0 Client SS_in enables/disables data input and tri-states SDO if the TRIS bit associated with the SDO pin is set (see the Client Mode Transmit table for details) Bit 1 – TXR  Transmit Data-Required Control(2) Value Description 1 TxFIFO data is required for a transfer 0 TxFIFO data is not required for a transfer Bit 0 – RXR  Receive FIFO Space-Required Control(2) Value Description 1 Data transfers are suspended when RxFIFO is full 0 Received data is not stored in the FIFO Notes:  1. The BUSY bit is subject to synchronization delay of up to two instruction cycles. The user must wait after loading the transmit buffer (the SPIxTXB register) before using it to determine the status of the SPI module. 2. See the Host Mode TXR/RXR Settings table as well as the Host Mode and Client Mode sections for more details pertaining to TXR and RXR function. 3. This register will not be written to while a transfer is in progress (the BUSY bit is set). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 578 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.7.4 SPIxCLK Name:  Address:  SPIxCLK 0x08C,0x099 SPI Clock Selection Register Bit 7 6 5 4 Access Reset 3 R/W 0 2 1 CLKSEL[3:0] R/W R/W 0 0 0 R/W 0 Bits 3:0 – CLKSEL[3:0] SPI Clock Source Selection Table 35-5. SPI CLK Source Selections CLK Selection 1111 - 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Reserved CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT SMT1_OUT TMR4_Postscaler_OUT TMR2_Postscaler_OUT TMR0_OUT Clock Reference Output EXTOSC MFINTOSC (500 kHz) HFINTOSC FOSC (System Clock) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 579 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.7.5 SPIxBAUD Name:  Address:  SPIxBAUD 0x089,0x096 SPI Baud Rate Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 BAUD[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – BAUD[7:0] Baud Clock Prescaler Select Value Description n SCK high or low time: TSC = SPI Clock Period*(n+1) SCK toggle frequency: FSCK = FBAUD = SPI Clock Frequency/(2*(n+1)) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 580 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.7.6 SPIxTCNT Name:  Address:  SPIxTCNT 0x082,0x08F SPI Transfer Counter Register Bit 15 14 13 12 11 R/W 0 9 TCNTH[2:0] R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 Access Reset Bit 7 6 5 4 10 8 TCNTL[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 10:8 – TCNTH[2:0] SPI Transfer Counter Most Significant Byte Value Condition Description n BMODE = 0 Bits 13-11 of the transfer bit count n BMODE = 1 Bits 10-8 of the transfer byte count Bits 7:0 – TCNTL[7:0] SPI Transfer Counter Least Significant Byte Value Condition Description n BMODE = 0 Bits 10-3 of the transfer bit count n BMODE = 1 Bits 7-0 of the transfer byte count © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 581 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.7.7 SPIxTWIDTH Name:  Address:  SPIxTWIDTH 0x088,0x095 SPI Transfer Width Register Bit 7 6 5 4 3 Access Reset 2 R/W 0 1 TWIDTH[2:0] R/W 0 0 R/W 0 Bits 2:0 – TWIDTH[2:0] SPI Transfer Count Byte Width or three LSbs of the Transfer Bit Count Value Condition Description n BMODE = 0 Bits 2-0 of the transfer bit count n BMODE = 1 Number of bits in each transfer byte count. Bits = n (when n > 0) or 8 (when n = 0). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 582 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.7.8 SPIxSTATUS Name:  Address:  SPIxSTATUS 0x087,0x094 SPI Status Register Bit Access Reset 7 TXWE R/C/HS 0 6 5 TXBE R 1 4 3 RXRE R/C/HS 0 2 CLB S 0 1 0 RXBF R 0 Bit 7 – TXWE Transmit Buffer Write Error Value Description 1 SPIxTXB was written while TxFIFO was full 0 No error has occurred Bit 5 – TXBE Transmit Buffer Empty Value Description 1 Transmit buffer TxFIFO is empty 0 Transmit buffer is not empty Bit 3 – RXRE Receive Buffer Read Error Value Description 1 SPIxRXB was read while RxFIFO was empty 0 No error has occurred Bit 2 – CLB Clear Buffer Control Value Description 1 Reset the receive and transmit buffers, making both buffers empty 0 Take no action Bit 0 – RXBF Receive Buffer Full Value Description 1 Receive buffer is full 0 Receive buffer is not full © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 583 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.7.9 SPIxRXB Name:  Address:  SPIxRXB 0x080,0x08D SPI Receive Buffer Bit 7 6 5 4 3 2 1 0 R x R x R x R x RXB[7:0] Access Reset R x R x R x Bits 7:0 – RXB[7:0] Receive Buffer Value Condition n Receive buffer is not empty 0 Receive buffer is empty © 2020-2021 Microchip Technology Inc. and its subsidiaries R x Description Contains the top-most byte of the RXFIFO. Reading this register will remove the RXFIFO top-most byte and decrease the occupancy of the RXFIFO by 1. Reading this register will return ‘0’, leave the occupancy unchanged, and set the RXRE Status bit Preliminary Datasheet DS40002214E-page 584 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.7.10 SPIxTXB Name:  Address:  SPIxTXB 0x081,0x08E SPI Transmit Buffer Bit 7 6 5 4 3 2 1 0 W x W x W x W x TXB[7:0] Access Reset W x W x W x Bits 7:0 – TXB[7:0] Transmit Buffer Value Condition n Transmit buffer is not full x Transmit buffer is full © 2020-2021 Microchip Technology Inc. and its subsidiaries W x Description Writing to this register adds the data to the top of the TXFIFO and increases the occupancy of the TXFIFO by 1. Writing to this register does not affect the data in the TXFIFO or the occupancy count. The TXWE Status bit will be set. Preliminary Datasheet DS40002214E-page 585 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.7.11 SPIxINTE Name:  Address:  SPIxINTE 0x08B,0x098 SPI Interrupt Enable Register Bit Access Reset 7 SRMTIE R/W 0 6 TCZIE R/W 0 5 SOSIE R/W 0 4 EOSIE R/W 0 3 2 RXOIE R/W 0 1 TXUIE R/W 0 0 Bit 7 – SRMTIE Shift Register Empty Interrupt Enable Value Description 1 Interrupt is enabled 0 Interrupt is not enabled Bit 6 – TCZIE Transfer Counter is Zero Interrupt Enable Value Description 1 Interrupt is enabled 0 Interrupt is not enabled Bit 5 – SOSIE Start of Client Select Interrupt Enable Value Description 1 Interrupt is enabled 0 Interrupt is not enabled Bit 4 – EOSIE End of Client Select Interrupt Enable Value Description 1 Interrupt is enabled 0 Interrupt is not enabled Bit 2 – RXOIE Receiver Overflow Interrupt Enable Value Description 1 Interrupt is enabled 0 Interrupt is not enabled Bit 1 – TXUIE Transmitter Underflow Interrupt Enable Value Description 1 Interrupt is enabled 0 Interrupt is not enabled © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 586 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.7.12 SPIxINTF Name:  Address:  SPIxINTF 0x08A,0x097 SPI Interrupt Flag Register Bit Access Reset 7 SRMTIF R/W/HS 0 6 TCZIF R/W/HS 0 5 SOSIF R/W/HS 0 4 EOSIF R/W/HS 0 3 2 RXOIF R/W/HS 0 1 TXUIF R/W/HS 0 0 Bit 7 – SRMTIF Shift Register Empty Interrupt Flag Value Mode Description x Client This bit is ignored 1 Host The data transfer is complete 0 Host Either no data transfers have occurred or a data transfer is in progress Bit 6 – TCZIF Transfer Counter is Zero Interrupt Flag Value Description 1 The transfer counter has decremented to zero 0 No interrupt pending Bit 5 – SOSIF Start of Client Select Interrupt Flag Value Description 1 SS_in transitioned from false to true 0 No interrupt pending Bit 4 – EOSIF End of Client Select Interrupt Flag Value Description 1 SS_in transitioned from true to false 0 No interrupt pending Bit 2 – RXOIF Receiver Overflow Interrupt Flag Value Description 1 Data transfer completed when RXBF = 1 (edge-triggered) and RXR = 1 0 No interrupt pending Bit 1 – TXUIF Transmitter Underflow Interrupt Flag Value Description 1 Client Data transfer started when TXBE = 1 and TXR = 1 0 No interrupt pending © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 587 PIC18F06/16Q41 SPI - Serial Peripheral Interface Module 35.8 Address 0x00 ... 0x7F 0x80 0x81 Register Summary - SPI Control Name Bit Pos. 7 6 5 4 3 2 RXRE LSBF SSP SSET CLB 1 0 Reserved SPI1RXB SPI1TXB 0x82 SPI1TCNT 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E SPI1CON0 SPI1CON1 SPI1CON2 SPI1STATUS SPI1TWIDTH SPI1BAUD SPI1INTF SPI1INTE SPI1CLK SPI2RXB SPI2TXB 0x8F SPI2TCNT 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 SPI2CON0 SPI2CON1 SPI2CON2 SPI2STATUS SPI2TWIDTH SPI2BAUD SPI2INTF SPI2INTE SPI2CLK 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 RXB[7:0] TXB[7:0] TCNTL[7:0] EN SMP BUSY TXWE CKE SSFLT CKP FST TXBE TCNTH[2:0] MST SDIP TXR BMODE SDOP RXR RXBF TWIDTH[2:0] SRMTIF SRMTIE TCZIF TCZIE SOSIF SOSIE BAUD[7:0] EOSIF EOSIE RXOIF TXUIF RXOIE TXUIE CLKSEL[3:0] RXB[7:0] TXB[7:0] TCNTL[7:0] EN SMP BUSY TXWE CKE SSFLT CKP TXBE FST RXRE LSBF SSP SSET CLB TCNTH[2:0] MST SDIP TXR BMODE SDOP RXR RXBF TWIDTH[2:0] SRMTIF SRMTIE © 2020-2021 Microchip Technology Inc. and its subsidiaries TCZIF TCZIE SOSIF SOSIE BAUD[7:0] EOSIF EOSIE Preliminary Datasheet RXOIF TXUIF RXOIE TXUIE CLKSEL[3:0] DS40002214E-page 588 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36. I2C - Inter-Integrated Circuit Module The Inter-Integrated Circuit (I2C) bus is a multi-host serial data communication bus. Devices communicate in a host/client environment where the host devices initiate the communication. A client device is controlled through addressing. The following figure shows a block diagram of the I2C interface module, and shows both Host and Client modes together. Figure 36-1. I2C Block Diagram I2CxADR0/1/2/3 TH (See RxyI2C Register) TX Shift Register RX Shift Register SDA (in) See I2CxCLK Register SDAHT (See I2CxCON2 Register) I2CxADB0/1 Address compare I2CxSDAPPS CLK ABD (See I2CxCON2 Register) Receive Buffer I2CxRXB ABD (See I2CxCON2 Register) I2CxADB0/1 SDA (out) RxyPPS Transmit Buffer I2CxTXB I2C Control Unit See I2CxBTO Register SCL (in) RxyPPS BTO Client Module I2CxSCLPPS TH (See RxyI2C Register) 36.1 SCL (out) Host Module Interrupt Controller I2CxPIR I2C Features The I2C supports the following modes and features: • • Modes – Host mode – Client mode – Multi-Host mode Features – Supports Standard mode (100 kHz), Fast mode (400 kHz) and Fast mode Plus (1 MHz) modes of operation – Dedicated Address, Receive, and Transmit buffers – Up to four unique Client addresses – General Call addressing – 7-bit and 10-bit addressing with optional masking – Interrupts for: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 589 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module – – – – – – – 36.2 • Start condition • Restart condition • Stop condition • Address match • Data Write • Acknowledge Status • NACK detection • Data Byte Count • Bus Collision • Bus Time-out Clock Stretching for: • RX buffer full • TX buffer empty • Incoming address match • Data Write • Acknowledge Status Bus Collision Detection with Arbitration Bus Time-out Detection • Selectable clock sources • Clock prescaler Selectable Serial Data (SDA) Hold Time Dedicated I2C Pad (I/O) Control • Standard GPIO or I2C-specific slew rate control • Selectable I2C pull-up levels • I2C-specific, SMBus 2.0/3.0, or standard GPIO input threshold level selections Integrated Direct Memory Access (DMA) support Remappable pin locations using Peripheral Pin Select (PPS) I2C Terminology The I2C communication protocol terminology used throughout this document have been adapted from the Phillips I2C Specification and can be found in the table below. I2C Bus Terminology and Definitions Term Definition Host The device that initiates a transfer, generates the clock signal and terminates a transfer Client The device addressed by the host Multi-Host A bus containing more than one host device that can initiate communication Transmitter The device that shifts data out onto the bus Receiver The device that shifts data in from the bus Arbitration Procedure that ensures only one host at a time controls the bus Synchronization Procedure that synchronizes the clock signal between two or more devices on the bus Idle The state in which no activity occurs on the bus and both bus lines are at a high logic level Active The state in which one or more devices are communicating on the bus Matching Address The address byte received by a client that matches the value that is stored in the I2CxADR0/1/2/3 registers © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 590 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.3 Addressed Client Client device that has received a matching address and is actively being clocked by a host device Write Request Host transmits an address with the R/W bit clear indicating that it wishes to transmit data to a client device Read Request Host transmits an address with the R/W bit set indicating that it wishes to receive data from a client device Clock Stretching The action in which a device holds the SCL line low to stall communication Bus Collision Occurs when the module samples the SDA line and returns a low state while expecting a high state Bus Time-out Occurs whenever communication stalls for a period longer than acceptable I2C Module Overview The I2C module provides a synchronous serial interface between the microcontroller and other I2C-compatible devices using a bidirectional two-wire bus. Devices operate in a host/client environment that may contain one or more host devices and one or more client devices. The host device always initiates communication. The I2C bus consists of two signal connections: • • Serial Clock (SCL) Serial Data (SDA) Both the SCL and SDA connections are open-drain lines, each line requiring pull-up resistors to the application’s supply voltage. Pulling the line to ground is considered a logic ‘0’, while allowing the line to float is considered a logic ‘1’. It is important to note that the voltage levels of the logic low and logic high are not fixed and are dependent on the bus supply voltage. According to the I2C Specification, a logic low input level is up to 30% of VDD (VIL ≤ 0.3 VDD), while the logic high input level is 70% to 100% of VDD (VIH ≥ 0.7 VDD). Both signal connections are considered bidirectional, although the SCL signal can only be an output in Host mode and an input in Client mode. All transactions on the bus are initiated and terminated by the host device. Depending on the direction of the data being transferred, there are four main operations performed by the I2C module: • • • • Host Transmit: Host is transmitting data to a client Host Receive: Host is receiving data from a client Client Transmit: Client is transmitting data to a host Client Receive: Client is receiving data from a host The I2C interface allows for a multi-host bus, meaning that there can be several host devices present on the bus. A host can select a client device by transmitting a unique address on the bus. When the address matches a client’s address, the client responds with an Acknowledge (ACK) condition, and communication between the host and that client can commence. All other devices connected to the bus must ignore any transactions not intended for them. The following figure shows a typical I2C bus configuration with one host and two clients. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 591 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Figure 36-2. I2C Host-Client Connections Receive Buffer Receive Buffer Shift Register SDA SDA Shift Register SCK Transmit Buffer I2C Client 1 Transmit Buffer SCK Receive Buffer I2C Host SDA SCK Shift Register Transmit Buffer I2C Client 2 36.3.1 Byte Format As previously mentioned, all I2C communication is performed in 9-bit segments. The transmitting device sends a byte to a receiver, and once the byte is processed by the receiver, the receiver returns an Acknowledge bit. There are no limits to the amount of data bytes in a I2C transmission. After the 8th falling edge of the SCL line, the transmitting device releases control of the SDA line to allow the receiver to respond with either an Acknowledge (ACK) sequence or a Not Acknowledge (NACK) sequence. At this point, if the receiving device is a client, it can hold the SCL line low (clock stretch) to allow itself time to process the incoming byte. Once the byte has been processed, the receiving device releases the SCL line, allowing the host device to provide the 9th clock pulse, within which the client responds with either an ACK or a NACK sequence. If the receiving device is a host, it may also hold the SCL line low until it has processed the received byte. Once the byte has been processed, the host device will generate the 9th clock pulse and transmit the ACK or NACK sequence. Data is valid to change only while the SCL signal is in a Low state, and sampled on the rising edge of SCL. Changes on the SDA line while the SCL line is high indicate either a Start or Stop condition. 36.3.2 SDA and SCL Pins The SDA and SCL pins must be configured as open-drain outputs. Open-drain configuration is accomplished by setting the appropriate bits in the Open-Drain Control (ODCONx) registers, while output direction configuration is handled by clearing the appropriate bits in the Tri-State Control (TRISx) registers. Input threshold, slew rate, and internal pull-up settings are configured using the RxyI2C registers. The RxyI2C registers are used exclusively on the default I2C pin locations, and provide the following selections: • Input threshold levels: – SMBus 3.0 (1.35V) input threshold – SMBus 2.0 (2.1V) input threshold – I2C-specific input thresholds © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 592 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module • • – Standard GPIO input thresholds (controlled by the Input Level Control (INLVLx) registers) Slew rate limiting: – I2C-specific slew rate limiting – Standard GPIO slew rate (controlled by the Slew Rate Control (SLRCONx) registers) 2 I C pull-ups: – Programmable ten or two times the current of the standard internal pull-up – Standard GPIO pull-up (controlled by the Weak Pull-Up Control (WPUx) registers) Important:  The pin locations for SDA and SCL are remappable through the Peripheral Pin Select (PPS) registers. If new pin locations for SDA and SCL are desired, user software must configure the INLVLx, SLRCONx, ODCONx, and TRISx registers for each new pin location. The RxyI2C registers cannot be used since they are dedicated to the default pin locations. Additionally, the internal pull-ups for non-I2C pins are not strong enough to drive the pins; therefore, external pull-up resistors must be used. 36.3.2.1 Filename: Title: Last Edit: First Used: SDA Hold Time Notes: SDA Hold Time.vsdx 11/15/2018 SDA hold time refers to the amount of time between the low threshold region of the falling edge of SCL (VIL ≤ 0.3 VDD) and either the low threshold region of the rising edge of SDA (VIL ≤ 0.3 VDD) or the high threshold region of the falling edge of SDA (VIH ≥ 0.7 VDD) (see Figure 36-3). If the SCL fall time is long or close to the maximum allowable time set by the I2C Specification, data may be sampled in the undefined Logic state between the 70% and 30% region of the falling SCL edge, leading to data corruption. The I2C module offers selectable SDA hold times, which can be useful to ensure valid data transfers at various bus data rates and capacitance loads. Figure 36-3. SDA Hold Time VIH 0.7 VDD Change of data allowed SCL VIL 0.3 VDD VIH SDA SDA Hold Time VIL 36.3.3 0.7 VDD 0.3 VDD Start Condition All I2C transmissions begin with a Start condition. The Start condition is used to synchronize the SCL signals between the host and client devices. The I2C Specification defines a Start condition as a transition of the SDA line from a logic high level (Idle state) to a logic low level (Active state) while the SCL line is at a logic high (see Figure 36-4). A Start condition is always generated by the host, and is initiated by either writing to the Start (S) bit or by writing to the I2C Transmit Buffer (I2CxTXB) register, depending on the Address Buffer Disable (ABD) bit setting. When the I2C module is configured in Host mode, module hardware waits until the bus is free (Idle state). Module hardware checks the Bus Free Status (BFRE) bit to ensure the bus is Idle before initiating a Start condition. When the BFRE bit is set, the bus is considered Idle, and indicates that the SCL and SDA lines have been in a Logic High state © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 593 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Filename: Start Condition.vsdx for the amount of I2C clock cycles as selected by the Bus Free Time Selection (BFRET) bits. When a Start condition Title: is detected on the Last bus,Edit: module hardware clears the BFRE bit, indicating an active bus. 11/15/2018 First In Multi-Host mode, it isUsed: possible for two host devices to issue Start conditions at the same time. If two or more Notes: hosts initiate a Start at the same time, a bus collision will occur; however, the I2C Specification states that a bus collision cannot occur on a Start. In this case, the competing host devices must go through bus arbitration during the addressing phase. The figure below shows a Start condition. Figure 36-4. Start Condition Start Condition SDA SCL 36.3.4 Acknowledge Sequence The 9th SCL pulse for any transferred address/data byte is reserved for the Acknowledge (ACK) sequence. During an Acknowledge sequence, the transmitting device relinquishes control of the SDA line to the receiving device. At this time, the receiving device must decide whether to pull the SDA line low (ACK) or allow the line to float high (NACK). Since the Acknowledge sequence is an active-low signal, pulling the SDA line low informs the transmitter that the receiver has successfully received the transmitted data. The Acknowledge Data (ACKDT) bit holds the value to be transmitted during an Acknowledge sequence while the I2CxCNT register is nonzero (I2CxCNT != 0). When a client device receives a matching address, or a receiver receives valid data, the ACKDT bit is cleared by user software to indicate an ACK. If the client does not receive a matching address, user software sets the ACKDT bit, indicating a NACK. In Client or Multi-Host modes, if the Address Interrupt and Hold Enable (ADRIE) or Write Interrupt and Hold Enable (WRIE) bits are set, the clock is stretched after receiving a matching address or after the 8th falling edge of SCL when a data byte is received. This allows user software time to determine the ACK/NACK response to send back to the transmitter. The Acknowledge End of Count (ACKCNT) bit holds the value that will be transmitted once the I2CxCNT register reaches a zero value (I2CxCNT = 0). When the I2CxCNT register reaches a zero value, the ACKCNT bit can be cleared (ACKCNT = 0), indicating an ACK, or ACKCNT can be set (ACKCNT = 1), indicating a NACK. Important:  The ACKCNT bit is only used when the I2CxCNT register is zero, otherwise the ACKDT bit is used for ACK/NACK sequences. In Host Write or Client Read modes, the Acknowledge Status (ACKSTAT) bit holds the result of the Acknowledge sequence transmitted by the receiving device. The ACKSTAT bit is cleared when the receiver sends an ACK, and is set when the receiver does not Acknowledge (NACK). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 594 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module The Acknowledge Time Status (ACKT) bit indicates whether or not the bus is in an Acknowledge sequence. The ACKT bit is set during an ACK/NACK sequence on the 8th falling edge of SCL, and is cleared on the 9th rising edge of SCL, indicating that the bus is not in an ACK/NACK sequence. Certain conditions will cause a NACK sequence to be sent automatically. A NACK sequence is generated by module hardware when any of the following bits are set: • • • • Transmit Write Error Status (TXWE) Transmit Underflow Status (TXU) Receive Read Error Status (RXRE) Receive Overflow Status (RXO) Filename: Title: Last Edit: First Used: Notes: Acknowledge Sequence.vsdx 1/8/2019 Important:  Once a NACK is detected on the bus, all subsequent Acknowledge sequences will consist of a NACK until all Error conditions are cleared. The following figure shows ACK and NACK sequences. Figure 36-5. ACK/NACK Sequences Rev. Acknowledg 1/8/2019 8th falling edge 9th rising edge SCL 9th rising edge SCL Acknowledge (ACK) SDA 36.3.5 8th falling edge SDA Not Acknowledge (NACK) Restart Condition A Restart condition is essentially the same as a Start condition – the SDA line transitions from an idle level to an active level while the SCL line is Idle – but may be used in place of a Stop condition whenever the host device has completed its current transfer but wishes to keep control of the bus. A Restart condition has the same effect as a Start condition, resetting all client logic and preparing it to receive an address. A Restart condition is also used when the host wishes to use a combined data transfer format. A combined data transfer format is used when a host wishes to communicate with a specific register address or memory location. In a combined format, the host issues a Start condition, followed by the client’s address, followed by a data byte which represents the desired client register or memory address. Once the client address and data byte have been acknowledged by the client, the host issues a Restart condition, followed by the client address. If the host wishes to write data to the client, the LSb of the client address, the Read/not Write (R/W) bit, will be clear. If the host wishes to read data from the client, the R/W bit will be set. Once the client has acknowledged the second address byte, the host issues a Restart condition, followed by the upper byte of the client address with the R/W bit set. Client logic will then acknowledge the upper byte, and begin to transmit data to the host. Important:  In 10-bit Client mode, a Restart is required for the host to read data out of the client, regardless of which data transfer format is used – host read-only or combined. For example, if the host wishes to perform a bulk read, it will transmit the client’s 10-bit address with the R/W bit clear. The figure below shows a Restart condition. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 595 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Figure 36-6. Restart Condition Restart Condition SDA SCL 36.3.6 Filename: Stop condition.vsdx Title: Stop Condition Last Edit: 11/15/2018 First Used: All I2C transmissions end with a Stop condition. A Stop condition occurs when the SDA line transitions from a logic low (active) level to Notes: a logic high (idle) level while the SCL line is at a logic high level. A Stop condition is always generated by the host device, and is generated by module hardware when a Not Acknowledge (NACK) is detected on the bus, a bus time-out event occurs, or when the I2C Byte Count (I2CxCNT) register reaches a zero count. A Stop condition may also be generated through software by setting the Stop (P) bit. The figure below shows a Stop condition. Figure 36-7. Stop Condition SCL Stop Condition SDA 36.3.7 Bus Time-Out The SMBus protocol requires a bus watchdog to prevent a stalled device from holding the bus indefinitely. The I2C Bus Time-Out Clock Source Selection (I2CxBTOC) register provides several clock sources that can be used as the time-out time base. The I2C Bus Time-Out (I2CxBTO) register is used to determine the actual bus time-out time period, as well as how the module responds to a time-out. The bus time-out hardware monitors for the following conditions: • SCL = 0 (regardless of whether or not the bus is Active) • SCL = 1 and SDA = 0 while the bus is Active If either of these conditions are true, an internal time-out counter increments, and continues to increment as long as the condition stays true, or until the time-out period has expired. If these conditions change (e.g. SCL = 1), the internal time-out counter is reset by module hardware. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 596 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module The Bus Time-Out Clock Source Selection (BTOC) bits select the time-out clock source. If an oscillator is selected as the time-out clock source, such as the LFINTOSC, the time-out clock base period is approximately 1 ms. If a timer is selected as the time-out clock source, the timer can be configured to produce a variety of time periods. Remember:  The SMBus protocol dictates a 25 ms time-out for client devices and a 35 ms time-out for host devices. The Time-Out Time Selection (TOTIME) bits and the Time-Out Prescaler Extension Enable (TOBY32) bit are used to determine the time-out period. The value written into TOTIME multiplies the base time-out clock period. For example, if a value of ‘35’ is written into the TOTIME bits, and the LFINTOSC is selected as the time-out clock source, the time-out period is approximately 35 ms (35 x 1 ms). If the TOBY32 bit is set (TOBY32 = 1), the time-out period determined by the TOTIME bits is multiplied by 32. If TOBY32 is clear (TOBY32 = 0), the time-out period determined by the TOTIME bits is used as the time-out period. The examples below illustrate possible time-out configurations. Example 36-1. 35 ms BTO Period Configuration void Init_BTO_35(void) { I2C1BTOC = 0x06; I2C1BTObits.TOREC = 1; I2C1BTObits.TOBY32 = 0; I2C1BTObits.TOTIME = 0x23; // Selections produce a 35 ms BTO period // // // // // LFINTOSC as BTO clock source Reset I2C interface, set BTOIF BTO time = TOTIME * TBTOCLK TOTIME = TBTOCLK * 35 = 1 ms * 35 = 35 ms } Example 36-2. 64 ms BTO Configuration void Init_BTO_64(void) // Selections produce a 64 ms BTO period { I2C1BTOC = 0x06; // LFINTOSC as BTO clock source I2C1BTObits.TOREC = 1; // Reset I2C interface, set BTOIF I2C1BTObits.TOBY32 = 1; // BTO time = TOTIME * TBTOCLK * 32 // = 2 ms * 32 = 64 ms I2C1BTObits.TOTIME = 0x02; // TOTIME = TBTOCLK * 2 // = 1 ms * 2 = 2 ms } The Time-Out Recovery Selection (TOREC) bit determines how the module will respond to a bus time-out. When a bus time-out occurs and TOREC is set (TOREC = 1), the I2C module is reset and module hardware sets the Bus Time-Out Interrupt Flag (BTOIF). If the Bus Time-Out Interrupt Enable (BTOIE) is also set, an interrupt will be generated. If a bus time-out occurs and TOREC is clear (TOREC = 0), the BTOIF bit is set, but the module is not reset. If the module is configured in Client mode with TOREC set (TOREC = 1), and a bus time-out event occurs (regardless of the state of the Client Mode Active (SMA) bit), the module is immediately reset, the SMA and Client Clock Stretching (CSTR) bits are cleared, and the Bus Time-Out Interrupt Flag (BTOIF) bit is set. If the module is configured in Client mode with TOREC clear (TOREC = 0), and a bus time-out event occurs (regardless of the state of the Client Mode Active (SMA) bit), the BTOIF bit is set, but user software must reset the module. Important:  It is recommended to set TOREC (TOREC = 1) when operating in Client mode. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 597 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module If the module is configured in Host mode with TOREC set (TOREC = 1), and the bus time-out event occurs while the Host is active (Host Mode Active (MMA) = 1), the Host Data Ready (MDR) bit is cleared, the module will immediately attempt to transmit a Stop condition, and sets the BTOIF bit. Stop condition generation may be delayed if a client device is stretching the clock, but will resume once the clock is released, or if the client holding the bus also has a time-out event occur. The MMA bit is only cleared after the Stop condition has been generated. Filename: Host Mode BTO Event Example .vsdx Title: If the module is configured in Host mode with TOREC clear (TOREC = 0), and the bus time-out event occurs while Last Edit: 1/9/2019 theFirst Host is active (Host Mode Active (MMA) = 1), the MDR bit is cleared and the BTOIF bit is set, but user software Used: Notes: must initiate the Stop condition by setting the P bit. The figure below shows an example of a Bus Time-Out event when the module is operating in Host mode. Figure 36-8. Host Mode Bus Time-Out Example Client releases SCL, Host begins Stop SDA SCL Host waits for ACK/NACK D0 I2CxTXIF = 1 TXBE = 1 8 Host attempts to issue Stop , but must wait until SCL = 1 Enable Timer2 T2_Postscaled_out BTOIF = 1 T2TMR_T2PR_Match TMR2IF = 1 Software clears BTOIF, TMR2IF Hardware clears MMA MMA 36.3.8 Stop detected PCIF = 1 Address Buffers The I2C module has two address buffer registers, I2CxADB0 and I2CxADB1, which can be used as address receive buffers in Client mode, address transmit buffers in Host mode, or both address transmit and address receive buffers in 7-bit Multi-Host mode (see Table 36-1). The address buffers are enabled/disabled via the Address Buffer Disable (ABD) bit. When the ABD bit is clear (ABD = 0), the buffers are enabled, which means: • • • • • In 7-bit Host mode, the desired client address with the R/W value is transmitted from the I2CxADB1 register, bypassing the I2C Transmit Buffer (I2CxTXB). I2CxADB0 is unused. In 10-bit Host mode, I2CxADB1 holds the upper bits and R/W value of the desired client address, while I2CxADB0 holds the lower eight bits of the desired client address. Host hardware copies the contents of I2CxADB1 to the transmit shift register, and waits for an ACK from the client. Once the ACK is received, host hardware copies the contents of I2CxADB0 to the transmit shift register. In 7-bit Client mode, a matching received address is loaded into I2CxADB0, bypassing the I2C Receive Buffer (I2CxRXB). I2CxADB1 is unused. In 10-bit Client mode, I2CxADB0 is loaded with the lower eight bits of the matching received address, while I2CxADB1 is loaded with the upper bits and R/W value of the matching received address. In 7-bit Multi-Host mode, the device can be both a host and a client depending on the sequence of events on the bus. When being addressed as a client, the matching received address with R/W value is stored into I2CxADB0. When being used as a host, the desired client address and R/W value are loaded into the I2CxADB1 register. When the ABD bit is set (ABD = 1), the buffers are disabled, which means: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 598 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module • • In Host mode, the desired client address is transmitted from the I2CxTXB register. In Client mode, a matching received address is loaded into the I2CxRXB register. Table 36-1. Address Buffer Direction 36.3.9 Mode I2CxADB0 I2CxADB1 Client (7-bit) RX Unused Client (10-bit) RX (address low byte) RX (address high byte) Host (7-bit) Unused TX Host (10-bit) TX (address low byte) TX (address high byte) Multi-Host (7-bit) RX TX Transmit Buffer The I2C module has a dedicated transmit buffer, I2CxTXB, which is independent from the receive buffer. The transmit buffer is loaded with an address byte (when ABD = 1), or a data byte, that is copied into the transmit shift register and transmitted onto the bus. When the I2CxTXB register does not contain any transmit data, the Transmit Buffer Empty Status (TXBE) bit is set (TXBE = 1), allowing user software or the DMA to load a new byte into the buffer. When the TXBE bit is set and the I2CxCNT register is nonzero (I2CxCNT != 0), the I2C Transmit Interrupt Flag (I2CxTXIF) bit of the PIR registers is set, and can be used as a DMA trigger. A write to I2CxTXB will clear both the TXBE and I2CxTXIF bits. Setting the Clear Buffer (CLRBF) bit clears I2CxTXIF, the I2Cx Receive Buffer (I2CxRXB) and I2CxTXB. If user software attempts to load I2CxTXB while it is full, the Transmit Write Error Status (TXWE) bit is set, a NACK is generated, and the new data is ignored. If TXWE is set, user software must clear the bit before attempting to load the buffer again. When module hardware attempts to transfer the contents of I2CxTXB to the transmit shift register while I2CxTXB is empty (TXBE = 1), the Transmit Underflow Status (TXU) bit is set, I2CxTXB is loaded with 0xFF, and a NACK is generated. Important:  A transmit underflow can only occur when clock stretching is disabled (Clock Stretching Disable (CSD) bit = 1). Clock stretching prevents transmit underflows because the clock is stretched after the 8th falling SCL edge, and is only released upon the write of new data into I2CxTXB. 36.3.10 Receive Buffer The I2C module has a dedicated receive buffer, I2CxRXB, which is independent from the transmit buffer. Data received through the shift register is transferred to I2CxRXB when the byte is complete. User software or the DMA can access the byte by reading the I2CxRXB register. When new data is loaded into I2CxRXB, the Receive Buffer Full Status (RXBF) bit is set, allowing user software or the DMA to read the new data. When the RXBF bit is set, the I2C Receive Interrupt Flag (I2CxRXIF) bit of the PIR registers is set, and can be used to trigger the DMA. A read of the I2CxRXB register will clear both RXBF and I2CxRXIF bits. Setting the CLRBF bit clears the I2CxRXIF bit, and the I2CxRXB and I2CxTXB registers. If the buffer is read while empty (RXBF = 0), the Receive Read Error Status (RXRE) bit is set, and the module generates a NACK. User software must clear RXRE to resume normal operation. When the module attempts to transfer the contents of the receive shift register to I2CxRXB while I2CxRXB is full (RXBF = 1), the Receive Overflow Status (RXO) bit is set, and a NACK is generated. The data currently stored in I2CxRXB remains unchanged, but the data in the receive shift register is lost. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 599 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Important:  A receive overflow can only occur when clock stretching is disabled. Clock stretching prevents receive overflows because the receive shift register cannot receive any more data until user software or the DMA reads I2CxRXB and the SCL line is released. 36.3.11 Clock Stretching Clock stretching occurs when a client device holds the SCL line low to pause bus communication. A client device may stretch the clock to allow more time to process incoming data, prepare a response for the host device, or to prevent Receive Overflow or Transmit Underflow conditions. Clock stretching is enabled by clearing the Clock Stretch Disable (CSD) bit, and is only available in Client and Multi-Host modes. When clock stretching is enabled (CSD = 0), the Client Clock Stretching (CSTR) bit can be used to determine if the Filename: Receive Buffer Clock Stretching.vsdx clockTitle: is currently being stretched. While the client is actively stretching the clock, CSTR is set by hardware (CSTR Edit: 5/8/2019 = 1).Last Once the client has completed its current transaction and clock stretching is no longer required, either module First Used: hardware or user software must clear CSTR to release the clock and resume communication. Notes: 36.3.11.1 Clock Stretching for Buffer Operations When enabled (CSD = 0), clock stretching is forced during buffer read/write operations. This allows the client device time to either load I2CxTXB with transmit data, or read data from I2CxRXB to clear the buffer. In Client Receive mode, clock stretching prevents receive data overflows. When the first seven bits of a new byte are received into the receive shift register while I2CxRXB is full (RXBF = 1), client hardware automatically stretches the clock and sets CSTR. When the client has read the data in I2CxRXB, client hardware automatically clears CSTR to release the SCL line and continue communication (see Figure 36-9). Figure 36-9. Receive Buffer Clock Stretching Hardware reads RXBF = 1 SCL 1 2 3 4 5 6 7 8 Client releases SCL Clock stretched SDA D7 D6 D5 D4 D3 D2 D1 D0 Software reads I2CxRXB RXBF CSTR Hardware sets CSTR = 1 Hardware clears RXBF Hardware clears CSTR In Client Transmit mode, clock stretching prevents transmit underflows. When I2CxTXB is empty (TXBE = 1) and the I2CxCNT register is nonzero (I2CxCNT != 0), client hardware stretches the clock and sets CSTR upon the 8th falling SCL edge. Once the client has loaded new data into I2CxTXB, client hardware automatically clears CSTR to release the SCL line and allow further communication (see Figure 36-10). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 600 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Figure 36-10. Transmit Buffer Clock Stretching Client releases SCL Hardware reads TXBE = 1 SCL 1 2 3 4 5 6 7 8 Host releases SDA to allow ACK SDA 9 Clock Stretched D7 D6 D5 D4 D3 D2 D1 D0 Software loads I2CxTXB TXBE CSTR Hardware sets CSTR = 1 Client copies ACKDT onto SDA (ACKDT = 0) Hardware clears TXBE Hardware clears CSTR 36.3.11.2 Clock Stretching for Other Client Operations The I2C module provides three Interrupt and Hold Enable features: • Address Interrupt and Hold Enable • Data Write Interrupt and Hold Enable • Acknowledge Status Time Interrupt and Hold Enable When clock stretching is enabled (CSD = 0), the Interrupt and Hold Enable features provide an interrupt response, and stretches the clock to allow time for address recognition, data processing, or an ACK/NACK response. The Address Interrupt and Hold Enable feature will generate an interrupt event and stretch the SCL line when a matching address is received. This feature is enabled by setting the Address Interrupt and Hold Enable (ADRIE) bit. When enabled (ADRIE = 1), the CSTR bit and the Address Interrupt Flag (ADRIF) bit are set by module hardware, and the SCL line is stretched following the 8th falling SCL edge of a received matching address. Once the client has completed processing the address, software determines whether to send an ACK or a NACK back to the host device. Client software must clear both the ADRIF and CSTR bits to resume communication. Important:  In 10-bit Client Addressing mode, clock stretching occurs only after the client receives a matching low address byte, or a matching high address byte with the R/W bit = 1 (Host read) while the Client Mode Active (SMA) bit is set (SMA = 1). Clock stretching does not occur after the client receives a matching high address byte with the R/W bit = 0 (Host write). The Data Write Interrupt and Hold Enable feature provides an interrupt event and stretches the SCL signal after the client receives a data byte. This feature is enabled by setting the Data Write Interrupt and Hold Enable (WRIE) bit. When enabled (WRIE = 1), module hardware sets both the CSTR bit and the Data Write Interrupt Flag (WRIF) bit and stretches the SCL line after the 8th falling edge of SCL. Once the client has read the new data, software determines whether to send an ACK or a NACK back to the host device. Client software must clear both the CSTR and WRIF bits to resume communication. The Acknowledge Status Time Interrupt and Hold Enable feature generates an interrupt event and stretches the SCL line after the acknowledgement phase of a transaction. This feature is enabled by setting the Acknowledge Status Time Interrupt and Hold Enable (ACKTIE) bit. When enabled (ACKTIE = 1), module hardware sets the CSTR bit and the Acknowledge Status Time Interrupt Flag (ACKTIF) bit and stretches the clock after the 9th falling edge of © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 601 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module SCL for all address, read, or write operations. Client software must clear both the ACKTIF and CSTR bits to resume communication. 36.3.12 Data Byte Count The data byte count refers to the number of data bytes in a complete I2C packet. The data byte count does not include address bytes. The I2C Byte Count (I2CxCNT) register is used to specify the length, in bytes, of the complete transaction. The value loaded into I2CxCNT will be decremented by module hardware each time a data byte is transmitted or received by the module. Important:  The I2CxCNT register will not decrement past a zero value. When a byte transfer causes the I2CxCNT register to decrement to ‘0’, the Byte Count Interrupt Flag (CNTIF) bit is set, and if the Byte Count Interrupt Enable (CNTIE) is set, the general purpose I2C Interrupt Flag (I2CxIF) bit of the Peripheral Interrupt Registers (PIR) is also set. If the I2C Interrupt Enable (I2CxIE) bit of the Peripheral Interrupt Enable (PIE) registers is set, module hardware will generate an interrupt event. Important:  The I2CxIF bit is read-only and can only be cleared by clearing all the interrupt flag bits of the I2CxPIR register. The I2CxCNT register can be read at any time, but it is recommended that a double read is performed to ensure a valid count value. The I2CxCNT register can be written to; however, care is required to prevent register corruption. If the I2CxCNT register is written to during the 8th falling SCL edge of a reception, or during the 9th falling SCL edge of a transmission, the register value may be corrupted. In Client mode, I2CxCNT can be safely written to any time the clock is not being stretched (CSTR = 0), or after a Stop condition has been received (Stop Condition Interrupt Flag (PCIF) = 1). In Host mode, I2CxCNT can be safely written to any time the Host Data Ready (MDR) or Bus Free (BFRE) bits are set. If the I2C packet is longer than 65,536 bytes, the I2CxCNT register can be updated mid-message to prevent the count from reaching zero; however, the preventative measures listed above must be followed. When in either Client Read or Host Write mode and the I2CxCNT value is nonzero (I2CxCNT != 0), the value of the ACKDT bit is used as the acknowledgement response. When I2CxCNT reaches zero (I2CxCNT = 0), the value of the Acknowledge End of Count (ACKCNT) bit is used for the acknowledgement response. In Host read or write operations, when the I2CxCNT register is clear (I2CxCNT = 0) and the Restart Enable (RSEN) bit is clear, host hardware automatically generates a Stop condition upon the 9th falling edge of SCL. When I2CxCNT is clear (I2CxCNT = 0) and RSEN is set (RSEN = 1), host hardware will stretch the clock while it waits for the Start (S) bit to be set (S = 1). When the Start bit has been set, module hardware transmits a Restart condition followed by the address of the client it wishes to communicate with. 36.3.12.1 Auto-Load I2CxCNT The I2CxCNT register can be automatically loaded. Auto-loading of the I2CxCNT register is enabled when the Auto-Load I2C Count Register Enable (ACNT) bit is set (ACNT = 1). In Host Transmit mode, the first two bytes following either the 7-bit or 10-bit client address are transferred from I2CxTXB into both I2CxCNT and the transmit shift register. Important:  When using the auto-load feature in any Transmit mode (Client, Host, Multi-Host), the first of the two bytes following the address is the I2CxCNT register’s high byte, followed by the I2CxCNT register’s low byte. If the order of these two bytes is switched, the value loaded into the I2CxCNT register will not be correct. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 602 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module In Host Reception mode, the first two bytes received from the client are loaded into both I2CxCNT and I2CxRXB. The value of the Acknowledge Data (ACKDT) bit is used as the host’s acknowledgement response to prevent a false NACK from being generated before the I2CxCNT register is updated with the new count value. In Client Reception mode, the first two bytes received after a receiving a matching 7-bit or 10-bit address are loaded into both I2CxCNT and I2CxRXB, and the value of the ACKDT bit is used as the client’s acknowledgement response. In Client Transmit mode, the first two bytes loaded into I2CxTXB following the reception of a matching 7-bit or 10-bit address are transferred into both I2CxCNT and the transmit shift register. Important:  It is not necessary to preload the I2CxCNT register when using the auto-load feature. If no value is loaded by the 9th falling SCL edge following an address transmission or reception, the Byte Count Interrupt Flag (CNTIF) will be set by module hardware, and must be cleared by software to prevent an interrupt event before I2CxCNT is updated. Alternatively, I2CxCNT can be preloaded with a nonzero value to prevent the CNTIF from being set. In this case, the preloaded value will be overwritten once the new count value has been loaded into I2CxCNT. 36.3.13 DMA Integration The I2C module can be used with the DMA for data transfers. The DMA can be triggered through software via the DMA Transaction (DGO) bit, or through the use of the following hardware triggers: • • • • I2C Transmit Interrupt Flag (I2CxTXIF) I2C Receive Interrupt Flag (I2CxRXIF) I2C Interrupt Flag (I2CxIF) I2C Error Interrupt Flag (I2CxEIF) For I2C communication, the I2CxTXIF is commonly used as the hardware trigger source for host or client transmission, and I2CxRXIF is commonly used as the hardware trigger source for host or client reception. 36.3.13.1 7-Bit Host Transmission When address buffers are enabled (ABD = 0), I2CxADB1 is loaded with the client address, and I2CxCNT is loaded with a count value. At this point, I2CxTXB does not contain data, and the Transmit Buffer Empty (TXBE) bit is set (TXBE = 1). The I2CxTXIF bit is not set since it can only be set when the Host Mode Active (MMA) and TXBE bits are set. Once software sets the Start (S) bit, the MMA bit is set and hardware transmits the client address. Upon the 8th falling SCL edge, since TXBE = 1, the Host Data Request (MDR) and I2CxTXIF bits are set, and hardware stretches the clock while the DMA loads I2CxTXB with data. Once the DMA loads I2CxTXB, the TXBE, MDR and I2CxTXIF bits are cleared by hardware, and the DMA waits for the next occurrence of I2CxTXIF being set. When address buffers are disabled (ABD = 1), software must load I2CxTXB with the client address to begin transmission. This is because I2CxTXIF can only be set when MMA = 1, and since a Start has not occurred, MMA = 0. Once the address has been transmitted, I2CxTXIF will be set, triggering the DMA to load I2CxTXB with data. 36.3.13.2 10-Bit Host Transmission When address buffers are enabled (ABD = 0), I2CxADB1 is loaded with the client high address, I2CxADB0 is loaded with the client low address, and I2CxCNT is loaded with a count value. Once software sets the Start (S) bit, the MMA bit is set and hardware transmits the 10-bit client address. Upon the 8th falling SCL edge of the transmitted address low byte, since TXBE = 1, the MDR and I2CxTXIF bits are set, and hardware stretches the clock while the DMA loads I2CxTXB with data. Once the DMA loads I2CxTXB, the TXBE, MDR and I2CxTXIF bits are cleared by hardware, and the DMA waits for the next occurrence of I2CxTXIF being set. When address buffers are disabled (ABD = 1), software must load I2CxTXB with the client high address to begin transmission. Once the client high address has been transmitted, I2CxTXIF will be set, triggering the DMA to load I2CxTXB with client low address. Once the DMA loads I2CxTXB with the client low address, the TXBE, MDR and I2CxTXIF bits are cleared by hardware, and the DMA waits for the next occurrence of I2CxTXIF being set. 36.3.13.3 7/10-Bit Host Reception In both 7-bit and 10-bit Host Receive modes, the state of the ABD bit is ignored. Once the complete 7-bit or 10-bit address has been received by the client, the client will transmit a data byte. Once the byte has been received by the © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 603 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module host, hardware sets the I2CxRXIF bit, which triggers the DMA to read I2CxRXB. Once the DMA has read I2CxRXB, I2CxRXIF is cleared by hardware and the DMA waits for the next occurrence of I2CxRXIF being set. 36.3.13.4 7-Bit Client Transmission In 7-bit Client Transmission mode, the state of ABD is ignored. If the client receives the matching 7-bit address and TXBE is set, I2CxTXIF is set by hardware, triggering the DMA to load data into I2CxTXB. Once the data is transmitted from I2CxTXB, I2CxTXIF is set by hardware, triggering the DMA to once again load I2CxTXB with data. The DMA will continue to load data into I2CxTXB until I2CxCNT reaches a zero value. Once I2CxCNT reaches zero and the data is transmitted from I2CxTXB, I2CxTXIF will not be set, and the DMA will stop loading data. 36.3.13.5 10-Bit Client Transmission In 10-bit Client Transmission mode, the state of ABD is ignored. If there is no data in I2CxTXB after the client has received the address high byte with the R/W bit set, hardware sets I2CxTXIF, triggering the DMA to load I2CxTXB. The DMA will continue to load data into I2CxTXB until I2CxCNT reaches a zero value. Once I2CxCNT reaches zero and the data is transmitted from I2CxTXB, I2CxTXIF will not be set, and the DMA will stop loading data. 36.3.13.6 7/10-Bit Client Reception When address buffers are enabled (ABD = 0), client hardware loads I2CxADB0/1 with the matching address, while all data is received by I2CxRXB. Once the client loads I2CxRXB with a received data byte, hardware sets I2CxRXIF, which triggers the DMA to read I2CxRXB. The DMA will continue to read I2CxRXB whenever I2CxRXIF is set. When address buffers are disabled (ABD = 1), the client loads I2CxRXB with the matching address byte(s) as they are received. Each received address byte sets I2CxRXIF, which triggers the DMA to read I2CxRXB. The DMA will continue to read I2CxRXB whenever I2CxRXIF is set. 36.3.14 Interrupts The I2C module offers several interrupt features designed to assist with communication functions. The interrupt hardware contains four high-level interrupts and several condition-specific interrupts. 36.3.14.1 High-Level Interrupts Module hardware provides four high-level interrupts: • Transmit • Receive • General Purpose • Error These flag bits are read-only bits, and cannot be cleared by software. The I2C Transmit Interrupt Flag (I2CxTXIF) bit is set when the I2CxCNT register is nonzero (I2CxCNT != 0), and the transmit buffer, I2CxTXB, is empty as indicated by the Transmit Buffer Empty Status (TXBE) bit (TXBE = 1). If the I2C Transmit Interrupt Enable (I2CxTXIE) bit is set, an interrupt event will occur when the I2CxTXIF bit becomes set. Writing new data to I2CxTXB, or setting the Clear Buffer (CLRBF) bit, will clear the interrupt condition. The I2CxTXIF bit is also used by the DMA as a trigger source. Important:  I2CxTXIF can only be set when either the Client Mode Active (SMA) or Host Mode Active (MMA) bits are set, and the I2CxCNT register is nonzero (I2CxCNT != 0). The SMA bit is only set after an address has been successfully acknowledged by a client device, which prevents false interrupts from being triggered on address reception. The MMA bit is set once the host completes the transmission of a Start condition. The I2C Receive Interrupt Flag (I2CxRXIF) bit is set when the receive shift register has loaded new data into the receive buffer, I2CxRXB. When new data is loaded into I2CxRXB, the Receive Buffer Full Status (RXBF) bit is set (RXBF = 1), which also sets I2CxRXIF. If the I2C Receive Interrupt Enable (I2CxRXIE) bit is set, an interrupt event will occur when the I2CxRXIF bit becomes set. Reading data from I2CxRXB, or setting the CLRBF bit, will clear the interrupt condition. The I2CxRXIF bit is also used by the DMA as a trigger source. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 604 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Important:  I2CxRXIF can only be set when either the Client Mode Active (SMA) or Host Mode Active (MMA) bits are set. The I2C Interrupt Flag (I2CxIF) is the general purpose interrupt. I2CxIF is set whenever any of the interrupt flag bits contained in the I2C Peripheral Interrupt (I2CxPIR) Register and the associated interrupt enable bits contained in the I2C Peripheral Interrupt Enable (I2CxPIE) Register are set. If I2CxIF becomes set while the I2C Interrupt Enable (I2CxIE) bit is set, an interrupt event will occur. I2CxIF is cleared by module hardware when all enabled interrupt flag bits in I2CxPIR are clear. The I2C Error Interrupt Flag (I2CxEIF) is set whenever any of the interrupt flag bits contained in the I2C Error (I2CxERR) Register and their associated interrupt enable bits are set. If I2CxEIF becomes set while the I2C Error Interrupt Enable (I2CxEIE) bit is set, an interrupt event will occur. I2CxEIF is cleared by hardware when all enabled error interrupt flag bits in the I2CxERR register are clear. 36.3.14.2 Condition-Specific Interrupts In addition to the high-level interrupts, module hardware provides several condition-specific interrupts. The I2C Peripheral Interrupt (I2CxPIR) Register contains the following interrupt flag bits: • • • • • • • CNTIF: Byte Count Interrupt Flag ACKTIF: Acknowledge Status Time Interrupt Flag WRIF: Data Write Interrupt Flag ADRIF: Address Interrupt Flag PCIF: Stop Condition Interrupt Flag RSCIF: Restart Condition Interrupt Flag SCIF: Start Condition Interrupt Flag When any of the flag bits in I2CxPIR becomes set and the associated interrupt enable bits in I2CxPIE are set, the generic I2CxIF is also set. If the generic I2CxIE bit is set, an interrupt event is generated whenever one of the I2CxPIR flag bits becomes set. If the I2CxIE bit is clear, the I2CxPIR flag bit will still be set by hardware; however, no interrupt event will be triggered. CNTIF becomes set (CNTIF = 1) when the I2CxCNT register value reaches zero, indicating that all data bytes in the I2C packet have been transmitted or received. CNTIF is set after the 9th falling SCL edge when I2CxCNT reaches zero (I2CxCNT = 0). ACKTIF is set (ACKTIF = 1) by the 9th falling edge of SCL for any byte when the device is addressed as a client in any Client or Multi-Host mode. If the Acknowledge Interrupt and Hold Enable (ACKTIE) bit is set and ACKTIF becomes set: • If an ACK is detected, clock stretching is also enabled (CSTR = 1) • If a NACK is detected, no clock stretching occurs (CSTR = 0) WRIF is set (WRIF = 1) after the 8th falling edge of SCL when the module receives a data byte in Client or Multi-Host modes. Once the data byte is received, WRIF is set, as is the Receive Buffer Full Status (RXBF) and the I2CxRXIF bits, and if the Data Write Interrupt and Hold Enable (WRIE) bit is set, the generic I2CxIF bit is also set. WRIF is a read/write bit and must be cleared in software, while the RXBF, I2CxRXIF and I2CxIF bits are read-only and are cleared by reading I2CxRXB or by setting the Clear Buffer bit (CLRBF = 1). ADRIF is set on the 8th falling edge of SCL after the module has received a matching 7-bit address, after receiving a matching 10-bit upper address byte, and after receiving a matching 10-bit lower address byte in Client or Multi-Host modes. Upon receiving a matching 7-bit address or 10-bit upper address, the address is copied to I2CxADB0, the R/W bit setting is copied to the Read Information (R) bit, the Data (D) bit is cleared, and the ADRIF bit is set. If the Address Interrupt and Hold Enable (ADRIE) bit is set, I2CxIF is set, and the clock will be stretched while the module determines whether to ACK or NACK the transmitter. Upon receiving the matching 10-bit lower address, the address is copied to I2CxADB1, and the ADRIF bit is set. If ADRIE is also set, the clock is stretched while the module determines the ACK/NACK response to return to the transmitter. PCIF is set whenever a Stop condition is detected on the bus. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 605 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module RSCIF is set upon the detection of a Restart condition. SCIF is set upon the detection of a Start condition. In addition to the I2CxPIR register, the I2C Error (I2CxERR) register contains three interrupt flag bits that are used to detect bus errors. These read/write bits are set by module hardware, but must be cleared by user software. The I2CxERR register also includes the interrupt enable bits for these three Error conditions, and when set, will cause an interrupt event whenever the associated interrupt flag bit becomes set. I2CxERR contains the following interrupt flag bits: • • • BTOIF: Bus Time-Out Interrupt Flag BCLIF: Bus Collision Interrupt Flag NACKIF: NACK Detect Interrupt Flag BTOIF is set when a bus time-out occurs. The bus time-out period is configured using one of the time-out sources selected by the I2C Bus Time-Out Clock Source Selection (I2CxBTOC) register. If the module is configured in Client mode with TOREC set (TOREC = 1), and a bus time-out event occurs (regardless of the state of the Client Mode Active (SMA) bit), the module is immediately reset, the SMA and Client Clock Stretching (CSTR) bits are cleared, and the BTOIF bit is set. If the Bus Time-Out Interrupt Enable (BTOIE) bit is set, the generic I2C Error Interrupt Flag (I2CxEIF) bit is set. If the module is configured in Client mode with TOREC clear (TOREC = 0), and a bus time-out event occurs (regardless of the state of the Client Mode Active (SMA) bit), the BTOIF bit is set, but user software must reset the module. If the Bus Time-Out Interrupt Enable (BTOIE) bit is set, the generic I2C Error Interrupt Flag (I2CxEIF) bit is set. If the module is configured in Host mode with TOREC set (TOREC = 1), and the bus time-out event occurs while the Host is active (Host Mode Active (MMA) = 1), the Host Data Ready (MDR) bit is cleared, the module will immediately attempt to transmit a Stop condition, and sets the BTOIF bit. Stop condition generation may be delayed if a client device is stretching the clock, but will resume once the clock is released, or if the client holding the bus also has a time-out event occur. The MMA bit is only cleared after the Stop condition has been generated. If the Bus Time-Out Interrupt Enable (BTOIE) bit is set, the generic I2C Error Interrupt Flag (I2CxEIF) bit is set. If the module is configured in Host mode with TOREC clear (TOREC = 0), and the bus time-out event occurs while the Host is active (Host Mode Active (MMA) = 1), the MDR bit is cleared and the BTOIF bit is set, but user software must initiate the Stop condition by setting the P bit. If the Bus Time-Out Interrupt Enable (BTOIE) bit is set, the generic I2C Error Interrupt Flag (I2CxEIF) bit is set. BCLIF is set upon the detection of a bus collision. A bus collision occurs any time the SDA line is sampled at a logic low while the module expects both SCL and SDA lines to be at a high logic level. When a bus collision occurs, BCLIF is set, and if the Bus Collision Detect Interrupt Enable (BCLIE) bit is set, I2CxEIF is also set, and the module is reset. NACKIF is set when either the host or client is active (SMA = 1 || MMA = 1) and a NACK response is detected on the bus. A NACK response occurs during the 9th SCL pulse in which the SDA line is released to a logic high. In Host mode, a NACK can be issued when the host has finished receiving data from a client, or when the host receives incorrect data. In Client mode, a NACK is issued when the client does not receive a matching address, or when it receives incorrect data. A NACK can also be automatically issued when any of the following bits becomes set, which will also set NACKIF and I2CxEIF: • • • • TXWE: Transmit Write Error Status RXRE: Receive Read Error Status TXU: Transmit Underflow Status RXO: Receive Overflow Status Important:  The I2CxEIF bit is read-only, and is only cleared by hardware after all enabled I2CxERR error flags have been cleared. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 606 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.3.15 Operation in Sleep The I2C module can operate while in Sleep mode. In Client mode, the module can transmit and receive data as long as the system clock source operates in Sleep. If the generic I2C Interrupt Enable (I2CxIE) bit is set and the client receives or transmits a complete byte, I2CxIF is set and the device wakes up from Sleep. In Host mode, both the system clock and the selected I2CxCLK source must be able to operate in Sleep. If the I2CxIE bit is set and the I2CxIF bit becomes set, the device wakes from Sleep. 36.4 I2C Operation All I2C communication is performed in 9-bit segments consisting of an 8-bit address/data segment followed by a 1-bit acknowledgement segment. Address and data bytes are transmitted with the Most Significant bit (MSb) first. Interaction between the I2C module and other devices on the bus is controlled and monitored through several I2C Control, Status, and Interrupt registers. To begin any I2C communication, mater hardware checks to ensure that the bus is in an Idle state as indicated by the Bus Free Status (BFRE) bit. When BFRE = 1, both SDA and SCL lines are floating to a logic high and the bus is considered ‘Idle’. When the host detects an Idle bus, it transmits a Start condition, followed by the address of the client it intends to communicate with. The client address can be either 7-bit or 10-bit, depending on the application design. In 7-bit Addressing mode, the Least Significant bit (LSb) of the 7-bit client address is reserved for the Read/not Write (R/W) bit, while in 10-bit Addressing mode, the LSb of the high address byte is reserved as the R/W bit. If the R/W bit is clear (R/W = 0), the host intends to read information from the client. If R/W is set (R/W = 1), the host intends to write information to the client. If the addressed client exists on the bus, it must respond with an Acknowledgement (ACK) sequence. Once a client has been successfully addressed, the host will continue to receive data from the client, write data to the client, or a combination of both. Data is always transmitted Most Significant bit (MSb) first. When the host has completed its transactions, it can either issue a Stop condition, signaling to the client that communication is to be terminated, or a Restart condition, informing the bus that the current host wishes to hold the bus to communicate with the same or other client devices. 36.4.1 I2C Client Mode Operation The I2C module provides four Client Operation modes as selected by the I2C Mode Select (MODE) bits: • • • • I2C Client mode with recognition of up to four 7-bit addresses I2C Client mode with recognition of up to two masked 7-bit addresses I2C Client mode with recognition of up to two 10-bit addresses I2C Client mode with recognition of one masked 10-bit address During operation, the client device waits until module hardware detects a Start condition on the bus. Once the Start condition is detected, the client waits for the incoming address information to be received by the receive shift register. The address is then compared to the addresses stored in the I2C Address 0/1/2/3 registers (I2CxADR0, I2CxADR1, I2CxADR2, I2CxADR3), and if an address match is detected, client hardware transfers the matching address into either the I2CxADB0/I2CxADB1 registers or the I2CxRXB register, depending on the state of the Address Buffer Disable (ABD) bit. If there are no address matches, there is no response from the client. 36.4.1.1 Client Addressing Modes The I2CxADR0, I2CxADR1, I2CxADR2 and I2CxADR3 registers contain the client’s addresses. The first byte (7-bit mode) or first and second bytes (10-bit mode) following a Start or Restart condition are compared to the values stored in the I2CxADR registers (see Figure 36-11). If an address match occurs, the valid address is transferred to the I2CxADB0/I2CxADB1 registers or I2CxRXB register, depending on the Addressing mode and the state of the ABD bit. Table 36-2. I2C Address Registers Mode I2CxADR0 © 2020-2021 Microchip Technology Inc. and its subsidiaries I2CxADR1 I2CxADR2 Preliminary Datasheet I2CxADR3 DS40002214E-page 607 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 7-bit 7-bit address 7-bit address 7-bit address 7-bit address 7-bit w/ masking 7-bit address 7-bit mask for I2CxADR0 7-bit address 7-bit mask for I2CxADR2 10-bit Address low byte Address high byte Address low byte Address high byte 10-bit w/ masking Address low byte Address high byte Address low byte mask Address high byte mask Filename: Masking Example.vsdx Title: In 7-bit Address mode, the received address byte is compared to all four I2CxADR registers independently to Last Edit: 1/8/2019 determine a match. The R/W bit is ignored during address comparison. If a match occurs, the matching received First Used: address Notes: is transferred from the receive shift register to either the I2CxADB0 register (when ABD = 0) or to the I2CxRXB register (when ABD = 1), and the value of the R/W bit is loaded into the Read Information (R) bit. In 7-bit Address with Masking mode, I2CxADR0 holds one client address and I2CxADR1 holds the mask value for I2CxADR0, while I2CxADR2 holds a second client address and I2CxADR3 holds the mask value for I2CxADR2. A zero bit in a mask register means that the associated bit in the address register is a ‘don’t care’, which means that the particular address bit is not used in the address comparison between the received address in the shift register and the address stored in either I2CxADR0 or I2CxADR2 (see Figure 36-11). Figure 36-11. 7-Bit Address with Masking Example 7-bit address I2CxRSR (receive shift register) 1 1 0 0 1 I2CxADR1 (Address Mask) R/W 0 X Bits ignored (masked) X X Bits compared I2CxADR0 (Client Address) 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 X X Mask bit = 0: associated address bit is ignored In 10-bit Address mode, I2CxADR0 and I2CxADR1, and I2CxADR2 and I2CxADR3 are combined to create two 10-bit addresses. I2CxADR0 and I2CxADR2 hold the lower eight bits of the address, while I2CxADR1 and I2CxADR3 hold the upper two bits of the address, the R/W bit, and the five-digit ‘11110’ code assigned to the five Most Significant bits of the high address byte. Important:  The ‘11110’ code is specified by the I2C Specification, but is not supported by Microchip. It is up to the user to ensure the correct bit values are loaded into the address high byte. If a host device has included the five-digit code in the address it intends to transmit, the client must also include those bits in client address. The upper received address byte is compared to the values in I2CxADR1 and I2CxADR3. If a match occurs, the address is stored in either I2CxADB1 (when ABD = 0) or in I2CxRXB (when ABD = 1), and the value of the R/W bit is transferred into the R bit. The lower received address byte is compared to the values in I2CxADR0 and I2CxADR2, and if a match occurs, the address is stored in either I2CxADB0 (when ABD = 0) or in I2CxRXB (when ABD = 1). In 10-bit Address with Masking mode, I2CxADR0 and I2CxADR1 are combined to form the 10-bit address, while I2CxADR2 and I2CxADR3 are combined to form the 10-bit mask. The upper received address byte is compared to the masked value in I2CxADR1. If a match occurs, the address is stored in either I2CxADB1 (when ABD = 0) or in I2CxRXB (when ABD = 1), and the value of the R/W bit is transferred into the R bit. The lower received address byte is compared to the value in I2CxADR0, and if a match occurs, the address is stored in either I2CxADB0 (when ABD = 0) or in I2CxRXB (when ABD = 1). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 608 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.4.1.2 General Call Addressing Support The I2C Specification reserves the address 0x00 as the General Call address. The General Call address is used to address all client modules connected to the bus at the same time. When a host issues a General Call, all client devices may respond with an ACK. The General Call Enable (GCEN) bit determines whether client hardware will respond to a General Call address. When GCEN is set (GCEN = 1), client hardware will respond to a General Call with an ACK, and when GCEN is clear (GCEN = 0), the General Call is ignored, and the client responds with a NACK. When the module receives a General Call, the ADRIF bit is set and the address is stored in I2CxADB0. If the ADRIE bit is set, the module will generate an interrupt and stretch the clock after the 8th falling edge of SCL. This allows the Filename: General Addressing.vsdx client to determine the Call acknowledgement response to return to the host (see Figure 36-12). Title: Last Edit: First Used: Notes: 1/8/2019 Important:  When using the General Call addressing feature, loading the I2CxADR0/1/2/3 registers with the 0x00 address is not recommended. Additionally, client hardware only supports General Call addressing in 7-bit Addressing modes. Figure 36-12. General Call Addressing Rev. General Ca 1/8/2019 Start (S) SDA SCL General Call Address (0x00) 1 2 3 4 5 ACK 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 Cleared by software ADRIF General Call address loaded into I2CxADB0 36.4.1.3 Client Operation in 7-Bit Addressing Modes The upper seven bits of an address byte are used to determine a client’s address, while the LSb of the address byte is reserved as the Read/not Write (R/W) bit. When R/W is set (R/W = 1), the host device intends to read data from the client. When R/W is clear (R/W = 0), the host device intends to write data to the client. When an address match occurs, the R/W bit is copied to the Read Information (R) bit, and the 7-bit address is copied to I2CxADB0. 36.4.1.3.1 Client Transmission (7-Bit Addressing Mode) The following section describes the sequence of events that occur when the module is transmitting data in 7-bit Addressing mode: 1. 2. 3. The host device issues a Start condition. Once the Start condition has been detected, client hardware sets the Start Condition Interrupt Flag (SCIF) bit. If the Start Condition Interrupt Enable (SCIE) bit is also set, the generic I2CxIF is also set. Host hardware transmits the 7-bit client address with the R/W bit set, indicating that it intends to read data from the client. The received address is compared to the values in the I2CxADR registers. If the client is configured in 7-bit Addressing mode (no masking), the received address is independently compared to each of the I2CxADR0/1/2/3 registers. In 7-bit Addressing with Masking mode, the received address is compared to the masked value of I2CxADR0 and I2CxADR2. If an address match occurs: – The Client Mode Active (SMA) bit is set by module hardware. – The R/W bit value is copied to the Read Information (R) bit by module hardware. – The Data (D) bit is cleared by hardware, indicating the last received byte was an address. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 609 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module – The Address Interrupt Flag (ADRIF) bit is set. If the Address Interrupt and Hold Enable (ADRIE) bit is set, and the Clock Stretching Disable (CSD) bit is clear, hardware sets the Client Clock Stretching (CSTR) bit and the generic I2CxIF bit. This allows time for the client to read either I2CxADB0 or I2CxRXB and selectively ACK/NACK based on the received address. When the client has finished processing the address, software must clear CSTR to resume operation. – The matching received address is loaded into either the I2CxADB0 register or into the I2CxRXB register as determined by the Address Buffer Disable (ABD) bit. When ABD is clear (ABD = 0), the matching address is copied to I2CxADB0. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which also sets the Receive Buffer Full Status (RXBF) bit and the I2C Receive Interrupt Flag (I2CxRXIF) bit. I2CxRXIF is a read-only bit, and must be cleared by either reading I2CxRXB or by setting the Clear Buffer (CLRBF) bit (CLRBF = 1). 4. 5. 6. 7. 8. 9. If no address match occurs, the module remains Idle. If the Transmit Buffer Empty Status (TXBE) bit is set (TXBE = 1), I2CxCNT has a nonzero value (I2CxCNT != 0), and the I2C Transmit Interrupt Flag (I2CxTXIF) is set (I2CxTXIF = 1), client hardware sets CSTR, stretches the clock (when CSD = 0), and waits for software to load I2CxTXB with data. I2CxTXB must be loaded to clear I2CxTXIF. Once data is loaded into I2CxTXB, hardware automatically clears CSTR to resume communication. The host device transmits the 9th clock pulse, and client hardware transfers the value of the ACKDT bit onto the SDA line. If there are pending errors, such as a receive overflow (RXO = 1), client hardware automatically generates a NACK condition. NACKIF is set, and the module goes Idle. Upon the 9th falling SCL edge, the data byte in I2CxTXB is transferred to the transmit shift register, and I2CxCNT is decremented by one. Additionally, the Acknowledge Status Time Interrupt Flag (ACKTIF) bit is set. If the Acknowledge Status Time Interrupt and Hold Enable (ACKTIE) bit is also set, the generic I2CxIF is set, and if client hardware generated an ACK, the CSTR bit is also set and the clock is stretched (when CSD = 0). If a NACK was generated, the CSTR bit remains unchanged. Once complete, software must clear CSTR and ACKTIF to release the clock and continue operation. If the client generated an ACK and I2CxCNT is nonzero, host hardware transmits eight clock pulses, and client hardware begins to shift the data byte out of the shift register starting with the Most Significant bit (MSb). After the 8th falling edge of SCL, client hardware checks the status of TXBE and I2CxCNT. If TXBE is set and I2CxCNT has a nonzero count value, hardware sets CSTR and the clock is stretched (when CSD = 0) until software loads I2CxTXB with new data. Once I2CxTXB has been loaded, hardware clears TXBE, I2CxTXIF, and CSTR to resume communication. Once the host hardware clocks in all eight data bits, it transmits the 9th clock pulse along with the ACK/ NACK response back to the client. Client hardware copies the ACK/NACK value to the Acknowledge Status (ACKSTAT) bit and sets ACKTIF. If ACKTIE is also set, client hardware sets the generic I2CxIF bit and CSTR, and stretches the clock (when CSD = 0). Software must clear CSTR to resume operation. 10. After the 9th falling edge of SCL, data currently loaded in I2CxTXB is transferred to the transmit shift register, setting both TXBE and I2CxTXIF. I2CxCNT is decremented by one. If I2CxCNT is zero (I2CxCNT = 0), CNTIF is set. 11. If I2CxCNT is nonzero and the host issued an ACK on the last byte (ACKSTAT = 0), the host transmits eight clock pulses, and client hardware begins to shift data out of the shift register. 12. Repeat steps 8 – 11 until the host has received all the requested data (I2CxCNT = 0). Once all data has been received, the host issues a NACK, followed by either a Stop or Restart condition. Once the NACK has been received by the client, hardware sets NACKIF and clears SMA. If the NACK Detect Interrupt Enable (NACKIE) bit is also set, the generic I2C Error Interrupt Flag (I2CxEIF) is set. If the host issued a Stop condition, client hardware sets the Stop Condition Interrupt Flag (PCIF). If the host issued a Restart condition, client hardware sets the Restart Condition Interrupt Flag (RSCIF). If the associated interrupt enable bits are also set, the generic I2CxIF is also set. Important:  I2CxEIF is read-only, and is cleared by hardware when all enable interrupt flag bits in I2CxERR are cleared. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 610 © 2020-2021 Microchip Technology Inc. and its subsidiaries Figure 36-13. 7-Bit Client Mode Transmission (No Clock Stretching) rotatethispage90 5: 6WDUW 6'$ $ $ $ $ $ $ $  ELWDGGUHVV 6&/ 60$ $&. IURP host) ' ' ' ' ' ' ' ' 1$&. IURP host) 5HY,&6ODYH  6WRS +DUGZDUHVHWV 3&,) ' ' ' ' ' ' ' ' +DUGZDUHVHWV 1$&.,) $&.IURPclient                            +DUGZDUHVHWV 60$ +DUGZDUHFOHDUV 60$ 5 +DUGZDUHFOHDUV'ELW ODVWE\WHZDVDGGUHVV ' ,&[&17 +DUGZDUHVHWV'ELW ODVWE\WHZDVGDWD [ +DUGZDUHVHWV &17,) [ [ Host¶V$&.FRSLHG WR$&.67$7 Host¶V1$&. FRSLHGWR$&.67$7 DS40002214E-page 611 %HIRUH6WDUWVRIWZDUH ORDGVGDWDLQWR,&[7;% 'DWDE\WHWUDQVIHUUHGWRVKLIWUHJLVWHU ,&[7;,)127VHW 7;%( ,&[7;,)VHW GDWDE\WHWUDQVIHUUHGWRVKLIWUHJLVWHU 6RIWZDUHORDGVGDWDLQWR ,&[7;%FOHDULQJ,&[7;,) PIC18F06/16Q41 $&.67$7 I2C - Inter-Integrated Circuit Module Preliminary Datasheet +DUGZDUHFRSLHV 5:YDOXHWR5ELW © 2020-2021 Microchip Technology Inc. and its subsidiaries Figure 36-14. 7-Bit Client Mode Transmission (ADRIE = 1) rotatethispage90 6WDUW 6'$ $ $ $ $ $ $ $  ELWDGGUHVV 6&/ $&. IURP host) 5:         ' ' ' ' ' ' ' ' 1$&. IURP host) 6WRS ' ' ' ' ' ' ' ' $&.IURPclient   2 3 4 5 6             +DUGZDUHVHWV $'5,) 6RIWZDUHFOHDUV $'5,) &675 +DUGZDUHVHWV &675 6RIWZDUHFOHDUV &675 +DUGZDUHVHWV &17,) Host¶V1$&. FRSLHGWR$&.67$7 Host¶V$&.FRSLHG WR$&.67$7 $&.67$7 ,&[&17 %HIRUH6WDUWVRIWZDUH ORDGVGDWDLQWR,&[7;% DS40002214E-page 612 ,&[7;,)VHW GDWDE\WHWUDQVIHUUHGWRVKLIWUHJLVWHU [ [ 'DWDE\WHWUDQVIHUUHGWRVKLIWUHJLVWHU ,&[7;,)127VHW 6RIWZDUHORDGVGDWDLQWR ,&[7;%FOHDULQJ,&[7;,) PIC18F06/16Q41 7;%( [ I2C - Inter-Integrated Circuit Module Preliminary Datasheet $'5,) © 2020-2021 Microchip Technology Inc. and its subsidiaries Figure 36-15. 7-Bit Client Mode Transmission (ACKTIE = 1) rotatethispage90 Start SDA R/W A7 A6 A5 A4 A3 A2 A1 0 7-bit address SCL Matching received address loaded into I2CxADB0 Hardware sets ACKT ACKTIF Hardware sets ACKTIF D7 D6 D5 D4 D3 D2 D1 D0 NACK 1 2 3 4 5 6 7 8 9 Software reads I2CxRXB, clearing I2CxRXIF Software clears CSTR Hardware clears ACKT Software clears ACKTIF Hardware sets CNTIF 0x02 0x01 0x00 DS40002214E-page 613 PIC18F06/16Q41 I2CxCNT I2C - Inter-Integrated Circuit Module Preliminary Datasheet ACKT 1 2 3 4 5 6 7 8 9 I2CxRXIF set, data byte transferred to I2CxRXB RXBF Hardware sets CSTR D7 D6 D5 D4 D3 D2 D1 D0 Stop ACKCNT value copied to SDA ACK 1 2 3 4 5 6 7 8 9 CSTR ACKDT value copied to SDA PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.4.1.3.2 Client Reception (7-Bit Addressing Mode) The following section describes the sequence of events that occur when the module is receiving data in 7-bit Addressing mode: 1. 2. 3. The host issues a Start condition. Once the Start is detected, client hardware sets the Start Condition Interrupt Flag (SCIF) bit. If the Start Condition Interrupt Enable (SCIE) bit is also set, the generic I2CxIF bit is also set. The host transmits the 7-bit client address with the R/W bit clear, indicating that it intends to write data to the client. The received address is compared to the values in the I2CxADR registers. If the client is configured in 7-bit Addressing mode (no masking), the received address is independently compared to each of the I2CxADR0/1/2/3 registers. In 7-bit Addressing with Masking mode, the received address is compared to the masked value of I2CxADR0 and I2CxADR2. If an address match occurs: – The Client Mode Active (SMA) bit is set by module hardware. – The R/W bit value is copied to the Read Information (R) bit by module hardware. – The Data (D) bit is cleared (D = 0) by hardware, indicating the last received byte was an address. – The Address Interrupt Flag (ADRIF) bit is set (ADRIF = 1). If the Address Interrupt and Hold Enable (ADRIE) bit is set (ADRIE = 1), and the Clock Stretching Disable (CSD) bit is clear (CSD = 0), hardware sets the Client Clock Stretching (CSTR) bit and the generic I2CxIF bit. This allows time for the client to read either I2CxADB0 or I2CxRXB and selectively ACK/NACK based on the received address. When the client has finished processing the address, software must clear CSTR to resume operation. – The matching received address is loaded into either the I2CxADB0 register or into the I2CxRXB register as determined by the Address Buffer Disable (ABD) bit. When ABD is clear (ABD = 0), the matching address is copied to I2CxADB0. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which also sets the Receive Buffer Full Status (RXBF) bit and the I2C Receive Interrupt Flag (I2CxRXIF) bit. I2CxRXIF is a read-only bit, and must be cleared by either reading I2CxRXB or by setting the Clear Buffer (CLRBF) bit (CLRBF = 1). 4. 5. 6. 7. 8. If no address match occurs, the module remains Idle. The host device transmits the 9th clock pulse, and client hardware transfers the value of the ACKDT bit onto the SDA line. If there are pending errors, such as a receive overflow (RXO = 1), client hardware automatically generates a NACK condition. NACKIF is set, and the module goes Idle. Upon the 9th falling SCL edge, the Acknowledge Status Time Interrupt Flag (ACKTIF) bit is set. If the Acknowledge Interrupt and Hold Enable (ACKTIE) bit is also set, the generic I2CxIF is set, and if client hardware generated an ACK, the CSTR bit is also set and the clock is stretched (when CSD = 0). If a NACK was generated, the CSTR bit remains unchanged. Once complete, software must clear CSTR and ACKTIF to release the clock and continue operation. If client hardware generated a NACK, host hardware generates a Stop condition, the Stop Condition Interrupt Flag (PCIF) bit is set when client hardware detects the Stop condition, and the client goes Idle. If an ACK was generated, host hardware transmits the first seven bits of the 8-bit data byte. If data remains in I2CxRXB (RXBF = 1 and I2CxRXIF = 1) when the first seven bits of the new byte are received by the shift register, CSTR is set, and if CSD is clear, the clock is stretched after the 7th falling edge of SCL. This allows time for the client to read I2CxRXB, which clears RXBF and I2CxRXIF, and prevents a receive buffer overflow. Once RXBF and I2CxRXIF are cleared, hardware releases SCL. Host hardware transmits the 8th bit of the current data byte into the client receive shift register. Client hardware then transfers the complete byte into I2CxRXB on the 8th falling edge of SCL, and sets the following bits: – I2CxRXIF – I2CxIF – Data Write Interrupt Flag (WRIF) – Data (D) – RXBF I2CxCNT is decremented by one. If the Data Write Interrupt and Hold Enable (WRIE) is set (WRIE = 1), hardware sets CSTR (when CSD = 0) and stretches the clock, allowing time for client software to read © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 614 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 9. I2CxRXB and determine the state of the ACKDT bit that is transmitted back to the host. Once the client determines the Acknowledgement response, software clears CSTR to allow further communication. Host hardware transmits the 9th clock pulse. If there are pending errors, such as receive buffer overflow, client hardware automatically generates a NACK condition, sets NACKIF, and the module goes Idle. If I2CxCNT is nonzero (I2CxCNT != 0), client hardware transmits the value of ACKDT as the acknowledgement response to the host. It is up to software to configure ACKDT appropriately. In most cases, the ACKDT bit must be clear (ACKDT = 0) so that the host receives an ACK response (logic low level on SDA during the 9th clock pulse). If I2CxCNT is zero (I2CxCNT = 0), client hardware transmits the value of the Acknowledge End of Count (ACKCNT) bit as the Acknowledgement response, rather than the value of ACKDT. It is up to software to configure ACKCNT appropriately. In most cases, ACKCNT must be set (ACKCNT = 1), which represents a NACK condition. When host hardware detects a NACK on the bus, it will generate a Stop condition. If ACKCNT is clear (ACKCNT = 0), an ACK will be issued, and host hardware will not issue a Stop condition. 10. Upon the 9th falling edge of SCL, the ACKTIF bit is set. If ACKTIE is also set, the generic I2CxIF is set, and if CSD is clear, client hardware sets CSTR and stretches the clock. This allows time for software to read I2CxRXB. Once complete, software must clear both CSTR and ACKTIF to release the clock and continue communication. 11. Repeat steps 6 -10 until the host has transmitted all the data (I2CxCNT = 0), or until the host issues a Stop or Restart condition. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 615 and its subsidiaries © 2020-2021 Microchip Technology Inc. Figure 36-16. 7-Bit Client Mode Reception (No Clock Stretching) rotatethispage90 Start SDA R/W A7 A6 A5 A4 A3 A2 A1 0 7-bit address SCL Stop Hardware sets PCIF D7 D6 D5 D4 D3 D2 D1 D0 NACK 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 I2CxRXIF set, data byte transferred to I2CxRXB RXBF Hardware sets NACKIF Software reads I2CxRXB, clearing I2CxRXIF Hardware clears SMA Hardware copies R/W value to R bit Hardware clears D bit, last byte was address D 0x01 Hardware sets CNTIF 0x00 PIC18F06/16Q41 DS40002214E-page 616 0x02 Hardware sets D bit, last byte was data I2C - Inter-Integrated Circuit Module Preliminary Datasheet Hardware sets SMA R I2CxCNT D7 D6 D5 D4 D3 D2 D1 D0 ACKCNT value copied to SDA ACK Matching received address loaded into I2CxADB0 SMA ACKDT value copied to SDA Notes: and its subsidiaries © 2020-2021 Microchip Technology Inc. Figure 36-17. 7-Bit Client Mode Reception (ADRIE = 1) Start SDA Rev. I2C Client 1/9/2019 rotatethispage90 R/W A7 A6 A5 A4 A3 A2 A1 0 7-bit address SCL ACKDT value copied to SDA D7 D6 D5 D4 D3 D2 D1 D0 ACKCNT value copied to SDA D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 Stop NACK 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Matching received address loaded into I2CxADB0 ADRIF Software clears ADRIF and CSTR CSTR I2CxRXIF set, data byte transferred to I2CxRXB RXBF DS40002214E-page 617 CNTIF 0x02 0x01 Hardware sets CNTIF 0x00 PIC18F06/16Q41 I2CxCNT Software reads I2CxRXB, clearing I2CxRXIF I2C - Inter-Integrated Circuit Module Preliminary Datasheet Hardware sets ADRIF and CSTR © 2020-2021 Microchip Technology Inc. and its subsidiaries Figure 36-18. 7-Bit Client Mode Reception (ACKTIE = 1) rotatethispage90 Start SDA R/W A7 A6 A5 A4 A3 A2 A1 0 7-bit address SCL Matching received address loaded into I2CxADB0 Hardware sets ACKT ACKTIF Hardware sets ACKTIF D7 D6 D5 D4 D3 D2 D1 D0 NACK 1 2 3 4 5 6 7 8 9 Software reads I2CxRXB, clearing I2CxRXIF Software clears CSTR Hardware clears ACKT Software clears ACKTIF Hardware sets CNTIF 0x02 0x01 0x00 DS40002214E-page 618 PIC18F06/16Q41 I2CxCNT I2C - Inter-Integrated Circuit Module Preliminary Datasheet ACKT 1 2 3 4 5 6 7 8 9 I2CxRXIF set, data byte transferred to I2CxRXB RXBF Hardware sets CSTR D7 D6 D5 D4 D3 D2 D1 D0 Stop ACKCNT value copied to SDA ACK 1 2 3 4 5 6 7 8 9 CSTR ACKDT value copied to SDA © 2020-2021 Microchip Technology Inc. and its subsidiaries Figure 36-19. 7-Bit Client Mode Reception (WRIE = 1) rotatethispage90 Start SDA R/W A7 A6 A5 A4 A3 A2 A1 0 7-bit address SCL ACKDT value copied to SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 NACK ACK 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 Stop ACKCNT value copied to SDA 9 1 2 3 4 5 6 7 8 9 Matching received address loaded into I2CxADB0 WRIF Software clears CSTR and WRIF CSTR I2CxRXIF set, data byte transferred to I2CxRXB RXBF DS40002214E-page 619 CNTIF 0x02 0x01 0x00 Hardware sets CNTIF PIC18F06/16Q41 I2CxCNT Software reads I2CxRXB, clearing I2CxRXIF I2C - Inter-Integrated Circuit Module Preliminary Datasheet Hardware sets CSTR and WRIF PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.4.1.4 Client Operation in 10-Bit Addressing Modes andthe Lower Address Bytes.vsdx InFilename: 10-bit AddressingUpper modes, first10-bit two bytes following a Start condition form the 10-bit address (see Figure 36-20). Title: The first byte (address high byte) holds the upper two address bits, the R/W bit, and a five digit code (11110) as Last Edit: 12/6/2018 defined by the I2C Specification. The second byte (address low byte) holds the lower eight address bits. In all 10-bit First Used: Addressing modes, the R/W value contained in the first byte must always be zero (R/W = 0). If the host intends to Notes: read data from the client, it must issue a Restart condition, followed by the address high byte with R/W set (R/W = 1). The first byte is compared to the values in the I2CxADR1 and I2CxADR3 registers in 10-bit Addressing mode, or to the masked value of I2CxADR1 in 10-bit Addressing with Masking mode. The second byte is compared to the values in the I2CxADR0 and I2CxADR2 registers in 10-bit Addressing mode, or to the masked value of I2CxADR0 in 10-bit Addressing with Masking mode. If an address high byte match occurs, the high address byte is copied to I2CxADB1 and the R/W bit value is copied to the Read Information (R) bit, and if an address low byte match occurs, the low address byte is copied to I2CxADB0. Figure 36-20. Upper and Lower 10-Bit Address Bytes Address High Byte 1 1 1 1 5-digit address code 0 Address Low Byte A9 A8 R/W Upper two address bits A7 A6 A5 A4 A3 A2 A1 A0 Lower eight address bits 36.4.1.4.1 Client Transmission (10-Bit Addressing Mode) The following section describes the sequence of events that occur when the module is transmitting data in 10-bit Addressing mode: 1. 2. 3. The host device issues a Start condition. Once the Start condition has been detected, client hardware sets the Start Condition Interrupt Flag (SCIF) bit. If the Start Condition Interrupt Enable (SCIE) bit is also set, the generic I2CxIF is also set. Host hardware transmits the 10-bit high address byte with the R/W bit clear (R/W = 0). Client hardware compares the received address to the values in the I2CxADR registers. If the client is configured in 10-bit Addressing mode (no masking), the received high address byte is compared to the values in I2CxADR1 and I2CxADR3. In 10-bit Addressing with Masking mode, the received high address byte is compared to the masked value of I2CxADR1. If an address match occurs: – The R/W value is copied to the Read Information (R) bit by module hardware. – The Data (D) bit is cleared by hardware. – The Address Interrupt Flag (ADRIF) bit is set (ADRIF = 1). – The matching address is loaded into either the I2CxADB1 register or into the I2CxRXB register as determined by the Address Buffer Disable (ABD) bit. When ABD is clear (ABD = 0), the matching address is copied to I2CxADB1. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which also sets the Receive Buffer Full Status (RXBF) bit and the I2C Receive Interrupt Flag (I2CxRXIF) bit. Important:  Regardless of whether the Address Interrupt and Hold Enable (ADRIE) bit is set, clock stretching does not occur when the R/W bit is clear in 10-bit Addressing modes. If no address match occurs, the module remains Idle. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 620 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 4. 5. The host device transmits the 9th clock pulse, and client hardware transfers the value of the ACKDT bit onto the SDA line. If there are pending errors, such as a receive buffer overflow (RXO = 1), client hardware generates a NACK and the module goes Idle. The host device transmits the low address byte. If the client is configured in 10-bit Addressing mode (no masking), the received low address byte is compared to the values in I2CxADR0 and I2CxADR2. In 10-bit Addressing with Masking mode, the received low address byte is compared to the masked value of I2CxADR0. If a match occurs: – The Client Mode Active (SMA) bit is set by module hardware. – ADRIF is set. If ADRIE is set, and the Clock Stretching Disable (CSD) bit is clear, hardware sets the Client Clock Stretching (CSTR) bit and the generic I2CxIF bit. This allows time for the client to read either I2CxADB0 or I2CxRXB and selectively ACK/NACK based on the received address. When the client has finished processing the address, software must clear CSTR to resume operation. – The matching received address is loaded into either the I2CxADB0 register or into the I2CxRXB register as determined by the ABD bit. When ABD is clear (ABD = 0), the matching address is copied to I2CxADB0. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which also sets RXBF and I2CxRXIF. I2CxRXIF is a read-only bit, and must be cleared by either reading I2CxRXB or by setting the Clear Buffer (CLRBF) bit (CLRBF = 1). 6. 7. 8. 9. If no match occurs, the module goes Idle. The host device transmits the 9th clock pulse, and client hardware transfers the value of the ACKDT bit onto the SDA line. If there are pending errors, such as a receive buffer overflow (RXO = 1), client hardware generates a NACK and the module goes Idle. After the 9th falling edge of SCL, the Acknowledge Status Time Interrupt Flag (ACKTIF) bit is set. If the Acknowledge Time Interrupt and Hold Enable (ACKTIE) bit is also set, the generic I2CxIF is set, and if client hardware generated an ACK, the CSTR bit is also set and the clock is stretched (when CSD = 0). If a NACK was generated, the CSTR bit remains unchanged. Once completed, software must clear CSTR and ACKTIF to release the clock and resume operation. Host hardware issues a Restart condition (cannot be a Start condition), and once the client detects the Restart, hardware sets the Restart Condition Interrupt Flag (RSCIF). If the Restart Condition Interrupt Enable (RSCIE) bit is also set, the generic I2CxIF is also set. Host hardware transmits the client’s high address byte with R/W set. If the received high address byte matches: – – – – The R/W bit value is copied to the R bit. The SMA bit is set. The D bit is cleared, indicating the last byte as an address. ADRIF is set. If ADRIE is set, and the CSD bit is clear, hardware sets CSTR and the generic I2CxIF bit. This allows time for the client to read either I2CxADB1 or I2CxRXB and selectively ACK/NACK based on the received address. When the client has finished processing the address, software must clear CSTR to resume operation. – The matching received address is loaded into either the I2CxADB1 register or into the I2CxRXB register as determined by the ABD bit. When ABD is clear (ABD = 0), the matching address is copied to I2CxADB1. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which also sets RXBF and I2CxRXIF. I2CxRXIF is a read-only bit, and must be cleared by either reading I2CxRXB or by setting CLRBF (CLRBF = 1). If the address does not match, the module goes Idle. 10. If the Transmit Buffer Empty Status (TXBE) bit is set (TXBE = 1), I2CxCNT has a nonzero value (I2CxCNT != 0), and the I2C Transmit Interrupt Flag (I2CxTXIF) is set (I2CxTXIF = 1), client hardware sets CSTR, stretches the clock (when CSD = 0), and waits for software to load I2CxTXB with data. I2CxTXB must be loaded to clear I2CxTXIF. Once data is loaded into I2CxTXB, hardware automatically clears CSTR to resume communication. 11. The host device transmits the 9th clock pulse, and client hardware transfers the value of the ACKDT bit onto the SDA line. If there are pending errors, such as a receive overflow (RXO = 1), client hardware automatically generates a NACK condition. NACKIF is set, and the module goes Idle. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 621 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 12. Upon the 9th falling SCL edge, the data byte in I2CxTXB is transferred to the transmit shift register, and I2CxCNT is decremented by one. Additionally, the ACKTIF bit is set. If the ACKTIE bit is also set, the generic I2CxIF is set, and if client hardware generated an ACK, the CSTR bit is also set and the clock is stretched (when CSD = 0). If a NACK was generated, the CSTR bit remains unchanged. Once complete, software must clear CSTR and ACKTIF to release the clock and continue operation. 13. If the client generated an ACK and I2CxCNT is nonzero, host hardware transmits eight clock pulses, and client hardware begins to shift the data byte out of the shift register starting with the Most Significant bit (MSb). 14. After the 8th falling edge of SCL, client hardware checks the status of TXBE and I2CxCNT. If TXBE is set and I2CxCNT has a nonzero count value, hardware sets CSTR and the clock is stretched (when CSD = 0) until software loads I2CxTXB with new data. Once I2CxTXB has been loaded, hardware clears CSTR to resume communication. 15. Once the host hardware clocks in all eight data bits, it transmits the 9th clock pulse along with the ACK/ NACK response back to the client. Client hardware copies the ACK/NACK value to the Acknowledge Status (ACKSTAT) bit and sets ACKTIF. If ACKTIE is also set, client hardware sets the generic I2CxIF bit and CSTR, and stretches the clock (when CSD = 0). Software must clear CSTR to resume operation. 16. After the 9th falling edge of SCL, data currently loaded in I2CxTXB is transferred to the transmit shift register, setting both TXBE and I2CxTXIF. I2CxCNT is decremented by one. If I2CxCNT is zero (I2CxCNT = 0), CNTIF is set. 17. If I2CxCNT is nonzero and the host issued an ACK on the last byte (ACKSTAT = 0), the host transmits eight clock pulses, and client hardware begins to shift data out of the shift register. 18. Repeat Steps 13-17 until the host has received all the requested data (I2CxCNT = 0). Once all data is received, host hardware transmits a NACK condition, followed by either a Stop or Restart condition. Once the NACK has been received by the client, hardware sets NACKIF and clears SMA. If the NACK Detect Interrupt Enable (NACKIE) bit is also set, the generic I2C Error Interrupt Flag (I2CxEIF) is set. If the host issued a Stop condition, client hardware sets the Stop Condition Interrupt Flag (PCIF). If the host issued a Restart condition, client hardware sets the Restart Condition Interrupt Flag (RSCIF) bit. If the associated interrupt enable bits are also set, the generic I2CxIF is also set. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 622 © 2020-2021 Microchip Technology Inc. and its subsidiaries Figure 36-21. 10-Bit Client Mode Transmission rotatethispage90 R/W SDA 1 1 1 1 0 A9 A8 0 High address SCL ACK (from client) A7 A6 A5 A4 A3 A2 A1 A0 Low address 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Hardware sets SMA SMA Hardware copies R/W value to R bit D Hardware clears D bit for address bytes 1 1 1 1 0 A9 A8 1 High address Stop D7 D6 D5 D4 D3 D2 D1 D0 ACK (from client) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Hardware clears SMA Hardware sets NACKIF, CNTIF Hardware copies R/W value to R bit Hardware sets D bit, last byte was data I2CxCNT 0x01 DS40002214E-page 623 Before Start, software loads data into I2CxTXB Data byte transferred to shift register, I2CxTXIF NOT set PIC18F06/16Q41 Host's NACK copied to ACKSTAT ACKSTAT TXBE 0x00 I2C - Inter-Integrated Circuit Module Preliminary Datasheet R NACK (from host ) R/W Restart PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.4.1.4.2 Client Reception (10-Bit Addressing Mode) The following section describes the sequence of events that occur when the module is receiving data in 7-bit Addressing mode: 1. 2. 3. The host issues a Start condition. Once the Start is detected, client hardware sets the Start Condition Interrupt Flag (SCIF) bit. If the Start Condition Interrupt Enable (SCIE) bit is also set, the generic I2CxIF bit is also set. Host hardware transmits the address high byte with the R/W bit clear (R/W = 0). The received high address byte is compared to the values in the I2CxADR registers. If the client is configured in 10-bit Addressing mode (no masking), the received high address byte is compared to the values in the I2CxADR1 and I2CxADR3 registers. If the client is configured in 10-bit Addressing with Masking mode, the received high address byte is compared to the masked value in the I2CxADR1 register. If a high address match occurs: – The R/W bit value is copied to the Read Information (R) bit by module hardware. – The Data (D) bit is cleared (D = 0) by hardware, indicating the last received byte was an address. – The Address Interrupt Flag (ADRIF) bit is set (ADRIF = 1). It is important to note that regardless of whether the Address Interrupt and Hold Enable (ADRIE) bit is set, clock stretching does not occur when the R/W bit is clear in 10-bit Addressing modes. – The matching address is loaded into either the I2CxADB1 register or into the I2CxRXB register as determined by the Address Buffer Disable (ABD) bit. When ABD is clear (ABD = 0), the matching address is copied to I2CxADB1. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which also sets the Receive Buffer Full Status (RXBF) bit and the I2C Receive Interrupt Flag (I2CxRXIF) bit. 4. 5. If no address match occurs, the module remains Idle. The host device transmits the 9th clock pulse, and client hardware transfers the value of the ACKDT bit onto the SDA line. If there are pending errors, such as a receive buffer overflow (RXO = 1), client hardware generates a NACK and the module goes Idle. The host device transmits the low address byte. If the client is configured in 10-bit Addressing mode (no masking), the received low address byte is compared to the values in I2CxADR0 and I2CxADR2. In 10-bit Addressing with Masking mode, the received low address byte is compared to the masked value of I2CxADR0. If a match occurs: – The Client Mode Active (SMA) bit is set by module hardware. – ADRIF is set. If ADRIE is set, and the Clock Stretching Disable (CSD) bit is clear, hardware sets the Client Clock Stretching (CSTR) bit and the generic I2CxIF bit. This allows time for the client to read either I2CxADB0 or I2CxRXB and selectively ACK/NACK based on the received address. When the client has finished processing the address, software must clear CSTR to resume operation. – The matching received address is loaded into either the I2CxADB0 register or into the I2CxRXB register as determined by the ABD bit. When ABD is clear (ABD = 0), the matching address is copied to I2CxADB0. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which also sets the RXBF and the I2CxRXIF bits. I2CxRXIF is a read-only bit, and must be cleared by either reading I2CxRXB or by setting the Clear Buffer (CLRBF) bit (CLRBF = 1). 6. 7. 8. 9. If no match occurs, the module goes Idle. The host device transmits the 9th clock pulse, and client hardware transfers the value of the ACKDT bit onto the SDA line. If there are pending errors, such as a receive buffer overflow (RXO = 1), client hardware generates a NACK and the module goes Idle. After the 9th falling edge of SCL, the Acknowledge Status Time Interrupt Flag (ACKTIF) bit is set. If the Acknowledge Time Interrupt and Hold Enable (ACKTIE) bit is also set, the generic I2CxIF is set, and if client hardware generated an ACK, the CSTR bit is also set and the clock is stretched (when CSD = 0). If a NACK was generated, the CSTR bit remains unchanged. Once completed, software must clear CSTR and ACKTIF to release the clock and resume operation. If client hardware generated a NACK, host hardware generates a Stop condition, the Stop Condition Interrupt Flag (PCIF) is set when client hardware detects the Stop condition, and the client goes Idle. If an ACK was generated, host hardware transmits the first seven bits of the 8-bit data byte. If data remains in I2CxRXB (RXBF = 1 and I2CxRXIF = 1) when the first seven bits of the new byte are received by the shift register, CSTR is set, and if CSD is clear, the clock is stretched after the 7th falling edge © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 624 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module of SCL. This allows time for the client to read I2CxRXB, which clears RXBF and I2CxRXIF, and prevents a receive buffer overflow. Once I2CxRXB has been read, RXBF and I2CxRXIF are cleared, and hardware releases SCL. 10. Host hardware transmits the 8th bit of the current data byte into the client receive shift register. Client hardware then transfers the complete byte into I2CxRXB on the 8th falling edge of SCL, and sets the following bits: – I2CxRXIF – I2CxIF – Data Write Interrupt Flag (WRIF) – Data (D) – RXBF I2CxCNT is decremented by one. If the Data Write Interrupt and Hold Enable (WRIE) bit is set (WRIE = 1), hardware sets CSTR (when CSD = 0) and stretches the clock, allowing time for client software to read I2CxRXB and determine the state of the ACKDT bit that is transmitted back to the host. Once the client determines the Acknowledgement response, software clears CSTR to allow further communication. 11. Upon the 9th falling edge of SCL, the ACKTIF bit is set. If ACKTIE is also set, the generic I2CxIF is set, and if CSD is clear, client hardware sets CSTR and stretches the clock. This allows time for software to read I2CxRXB. Once complete, software must clear both CSTR and ACKTIF to release the clock and continue communication. 12. Repeat Steps 8 – 11 until the host has transmitted all the data (I2CxCNT = 0), or until the host issues a Stop or Restart condition. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 625 © 2020-2021 Microchip Technology Inc. and its subsidiaries Figure 36-22. 10-Bit Client Mode Reception rotatethispage90 Start SDA R/W 1 1 1 1 0 A9 A8 0 ACKDT value copied to SDA A7 A6 A5 A4 A3 A2 A1 A0 High address SCL RXBF R D Hardware sets PCIF D7 D6 D5 D4 D3 D2 D1 D0 ACK NACK 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Matching received High address loaded into I2CxADB1 Matching received Low address loaded into I2CxADB0 Hardware sets NACKIF I2CxRXIF set, data byte transferred to I2CxRXB Hardware sets SMA Hardware clears SMA Hardware copies R/W value to R bit Hardware clears D bit, last byte was address 0x01 Hardware sets D bit, last byte was data Hardware sets CNTIF 0x00 DS40002214E-page 626 PIC18F06/16Q41 I2CxCNT Stop I2C - Inter-Integrated Circuit Module Preliminary Datasheet SMA ACKCNT value copied to SDA PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.4.2 I2C Host Mode Operation The I2C module provides two Host Operation modes as selected by the I2C Mode Select (MODE) bits: • • I2C Host mode with 7-bit addressing I2C Host mode with 10-bit addressing To begin any I2C communication, host hardware checks to ensure that the bus is in an Idle state, which means both the SCL and SDA lines are floating in a high Logic state as indicated by the Bus Free Status (BFRE) bit. Once Host hardware has determined that the bus is free (BFRE = 1), it examines the state of the Address Buffer Disable (ABD) bit. The ABD bit determines whether the I2CxADB registers are used. When ABD is clear (ABD = 0), address buffers I2CxADB0 and I2CxADB1 are active. In 7-bit Addressing mode, software loads I2CxADB1 with the 7-bit client address and R/W bit setting, and also loads I2CxTXB with the first byte of data . In 10-bit Addressing mode, software loads I2CxADB1 with the address high byte and I2CxADB0 with the address low byte, and also loads I2CxTXB with the first data byte. Software must issue a Start condition to initiate communication with the client. When ABD is set (ABD = 1), the address buffers are inactive. In this case, communication begins as soon as software loads the client address into I2CxTXB. Writes to the Start (S) bit are ignored. In 7-bit Addressing mode, the Least Significant bit (LSb) of the 7-bit address byte acts as the Read/not Write (R/W) information bit, while in 10-bit Addressing mode, the LSb of the address high byte is reserved as the R/W bit. When R/W is set, the host intends to read data from the client (see the figure below). When R/W is clear, the host intends to write data to the client (see the figure below). The host may also wish to read or write data to a specific location, such as writing to a specific EEPROM location. In this case, the host issues a Start condition, followed by the client’s address with the R/W bit clear. Once the client acknowledges the address, the first data byte following the 7-bit or 10-bit address is used as the client’s specific register location. If the host intends to read data from the specific location, it must issue a Restart condition, followed by the client address with the R/W bit set (see the figure below). If the addressed client device exists on the bus, it must respond with an Acknowledge (ACK) sequence. Once a client has acknowledged its address, the host begins to receive data from the client or transmits data to the client. Data is always transmitted Most Significant bit (MSb) first. When the host wishes to halt further communication, it transmits either a Stop condition, signaling to the client that communication is to be terminated, or a Restart condition, informing the bus that the current host wishes to hold the bus to communicate with the same or other client devices. Figure 36-23. 7-Bit Host Read Diagram S T S A6 A5 A4 A3 A2 A1 A0 1 A D7 D6 D5 D4 D3 D2 D1 D0 N O P Data 7-bit address R/W © 2020-2021 Microchip Technology Inc. and its subsidiaries ACK (from client) Preliminary Datasheet NACK (from host) DS40002214E-page 627 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Figure 36-24. 7-Bit Host Read Diagram (from a specific memory/register location) S A6 A5 A4 A3 A2 A1 A0 0 A RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 A R A6 A5 A4 A3 A2 A1 A0 1 A D7 D6 D5 D4 D3 D2 D1 D0 N S Register Address 7-bit address R/W ACK Data 7-bit address NACK R/W ACK ACK (from client) (from client) S T O P (from host ) (from client) Restart condition Figure 36-25. 10-Bit Host Read Diagram Address high byte S 1 1 1 1 Restart condition R/W 0 A9 A8 0 A A7 A6 A5 A4 A3 A2 A1 A0 A 5-digit 10-bit address address code MSb s R 1 S Address low byte ACK ACK Address high byte 1 1 1 0 A9 A8 1 A D7 D6 D5 D4 D3 D2 D1 D0 N 10-bit 5-digit address address MSb s code (from client) (from client) R/W S T O P Data NACK (from host) ACK (from client) Figure 36-26. 7-Bit Host Write Diagram S A6 A5 A4 A3 A2 A1 A0 0 A D7 D6 D5 D4 D3 D2 D1 D0 N Data 7-bit address R/W © 2020-2021 Microchip Technology Inc. and its subsidiaries S T O P ACK (from client) Preliminary Datasheet NACK (from client) DS40002214E-page 628 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Figure 36-27. 7-Bit Host Write Diagram (to a specific memory/register location) S A6 A5 A4 A3 A2 A1 A0 0 A RA7RA6RA5 RA4 RA3RA2 RA1RA0 A D7 D6 D5 D4 D3 D2 D1 D0 N Register Address 7-bit address R/W S T O P Data NACK (from client) ACK ACK (from client) (from client) Figure 36-28. 10-Bit Host Write Diagram Address high byte S 1 1 1 1 5-digit address code R/W 0 A9 A8 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 N 10-bit address MSb s Data Address low byte ACK ACK (from client) S T O P (from client) NACK (from client) 36.4.2.1 Bus Free Time The Bus Free Status (BFRE) bit indicates the activity status of the bus. When BFRE is set (BFRE = 1), the bus is in an Idle state (both SDA and SCL are floating high), and any host device residing on the bus can compete for control of the bus. When BFRE is clear (BFRE = 0), the bus is in an Active state, and any attempts by a host to control the bus will cause a collision. The Bus Free Time (BFRET) bits determine the length of time, in terms of I2C clock pulses, before the bus is considered Idle. Once module hardware detects logic high levels on both SDA and SCL, it monitors the I2C clock signal, and when the desired number of pulses have occurred, module hardware sets BFRE. The BFRET bits are also used to ensure that the module meets the minimum Stop hold time as defined by the I2C Specification. 36.4.2.2 Host Clock Timing The Serial Clock (SCL) signal is generated by module hardware via the I2C Clock Selection (I2CxCLK) Register, the I2C Baud Rate Prescaler (I2CxBAUD) Register, and the Fast Mode Enable (FME) bit. The figure below illustrates the SCL clock generation. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 629 Notes: PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Figure 36-29. SCL Clock Generation CLK[4:0] 11111 10111 10110 . . . I2CxBAUD FPRECLK = I2CxCLK (BAUD + 1) FME 1 FSCL 0 00010 00001 00000 I2CxCLK contains several clock source selections. The clock source selections typically include variants of the system clock and timer resources. Important:  When using a timer as the clock source, the timer must also be configured. Additionally, when using the HFINTOSC as a clock source, it is important to understand that the HFINTOSC frequency selected by the OSCFRQ register is used as the clock source. The clock divider selected by the NDIV bits is not used. For example, if OSCFRQ selects 4 MHz as the HFINTOSC clock frequency, and the NDIV bits select a divide by four scaling factor, the I2C Clock Frequency will be 4 MHz and not 1 MHz since the divider is ignored. I2CxBAUD is used to determine the prescaler (clock divider) for the I2CxCLK source. The FME bit acts as a secondary divider to the prescaled clock source. When FME is clear (FME = 0), one SCL period (TSCL) is equal to five clock periods of the prescaled I2CxCLK source. In other words, the prescaled I2CxCLK source is divided by five. For example, if the HFINTOSC (set to 4 MHz) clock source is selected, I2CxBAUD is loaded with a value of ‘7’, and the FME bit is clear, the actual SCL frequency is 100 kHz (see the equation below). Equation 36-1. SCL Frequency (FME = 0) Example: • I2CxCLK: HFINTOSC (4 MHz) • I2CxBAUD: 7 • FME: FME = 0 fSCL = fI2CxCLK BAUD + 1 FME = 4 MHz 8 5 = 100 kHz When FME is clear, host hardware uses the first prescaled I2CxCLK source period to drive SCL low (see Figure 36-30). During the second period, hardware verifies that SCL is in fact low. During the third period, hardware releases SCL, allowing it to float high. Host hardware then uses the fourth and fifth periods to sample SCL to verify that SCL is high. If a client is holding SCL low (clock stretch) during the fourth and/or fifth period, host hardware samples each successive prescaled I2CxCLK period until a high level is detected on SCL. Once the high level is detected, host hardware samples SCL during the next two I2CxCLK periods to verify that SCL is high. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 630 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Figure 36-30. SCL Timing (FME = 0) Host releases SCL Host drives SCL low I2C Prescaled Clock 1 2 Host drives SCL low 3 4 5 1 Host releases SCL, but client stretches clock 2 3 TSCL Host drives SCL low Client releases SCL 4 5 1 2 TSCL SCL Host samples SCL to ensure SCL is high Host samples SCL to ensure SCL is low Host samples SCL to ensure SCL is low Host samples SCL for high Host MUST detect SCL high twice When FME is set (FME = 1), one SCL period (TSCL) is equal to four clock periods of the prescaled I2CxCLK source. In other words, the prescaled I2CxCLK source is divided by four. Using the example from above, if the HFINTOSC (4 MHz) clock source is selected, I2CxBAUD is loaded with a value of ‘7’, and the FME bit is set, the actual SCL frequency is 125 kHz (see the equation below). Equation 36-2. SCL Frequency (FME = 1) Example: • I2CxCLK: HFINTOSC (4 MHz) • I2CxBAUD: 7 • FME: FME = 1 fSCL = fI2CxCLK BAUD + 1 Filename: FME = 4 MHz 8 4 FME = 1.vsdx = 125 kHz WhenTitle: FME is set, host hardware uses the first prescaled I2CxCLK source period to drive SCL low (see Figure Last Edit: 7/30/2019 36-31). the second prescaled period, hardware verifies that SCL is in fact low. During the third period, FirstDuring Used: Notes: hardware releases SCL, allowing it to float high. Host hardware then uses the fourth period to sample SCL to verify that SCL is high. If a client is holding SCL low (clock stretch) during the fourth period, host hardware samples each successive prescaled I2CxCLK period until a high level is detected on SCL. Once the high level is detected, host hardware samples SCL during the next period to verify that SCL is high. Figure 36-31. SCL Timing (FME = 1) Host releases SCL Host drives SCL low I2C Prescaled Clock 1 2 3 Rev. FME = 1.v s 7/30/2019 Host drives SCL low 4 TSCL 1 Host releases SCL, but client stretches clock 2 3 Client releases SCL 4 1 TSCL 2 3 Host drives SCL low 4 TSCL SCL Host samples SCL to ensure SCL is low © 2020-2021 Microchip Technology Inc. and its subsidiaries Host samples SCL to ensure SCL is high Host samples SCL to ensure SCL is low Host samples SCL for high Preliminary Datasheet Host MUST detect SCL high DS40002214E-page 631 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.4.2.3 Start Condition Timing A Start condition is initiated by either writing to the Start (S) bit (when ABD = 0), or by writing to I2CxTXB (when ABD = 1). When the Start condition is initiated, host hardware verifies that the bus is Idle, then begins to count the number of I2CxCLK periods as determined by the Bus Free Time Status (BFRET) bits. Once the Bus Free Time period has Filename: Start Condition Timing.vsdx Title: been reached, hardware sets BFRE (BFRE = 1), the Start condition is asserted on the bus, which pulls the SDA Last Edit: 1/28/2019 line low, and the Start Condition Interrupt Flag (SCIF) bit is set (SCIF = 1). Host hardware then waits one full SCL First Used: period Notes: (TSCL) before pulling the SCL line low, signaling the end of the Start condition. At this point, hardware loads the transmit shift register from either I2CxADB0/I2CxADB1 (ABD = 0) or I2CxTXB (ABD = 1). The figure below shows an example of a Start condition. Figure 36-32. Start Condition Timing Rev. St art Cond 1/28/2019 BFRE = 1 SCIF = 1 Start condition asserted Write to START (S) bit tHD:DAT(2) SDA SCL tHD:STA(1) Change of data allowed 2 I CxCLK (FME = 1) 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 BFRET = 00 (8 - I2C Clock Pulses) Completion of Start If ABD = 0: Hardware loads I2C Shift register from I2CxADB0/1 If ABD = 1: Hardware loads I2C Shift register with I2CxTXB Important:  1. See the device data sheet for Start condition hold time parameters. 2. SDA hold times are configured via the SDAHT bits. 36.4.2.4 Acknowledge Sequence Timing The 9th SCL pulse for any transferred address/data byte is reserved for the Acknowledge (ACK) sequence. During an Acknowledge sequence, the transmitting device relinquishes control of the SDA line to the receiving device. At this time, the receiving device must decide whether to pull the SDA line low (ACK) or allow the line to float high (NACK). An Acknowledge sequence is enabled automatically by module hardware following an address/data byte reception. On the 8th falling edge of SCL, the value of either the ACKDT or ACKCNT bits are copied to the SDA output, depending on the state of I2CxCNT. When I2CxCNT holds a nonzero value (I2CxCNT != 0), the value of ACKDT is copied to SDA (see Figure 36-33). When I2CxCNT reaches a zero count (I2CxCNT = 0), the value of ACKCNT is copied to SDA (see Figure 36-34). In most applications, the value of ACKDT needs to be zero (ACKDT = 0), which represents an ACK, while the value of ACKCNT needs to be one (ACKCNT = 1), which represents a NACK. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 632 Last Edit: First Used: Notes: 1/10/2019 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Figure 36-33. Acknowledge (ACK) Sequence Timing ACKDT copied to SDA D1 SDA D0 ACK ACK Complete SCL Filename: RXBF Title: 7 8 9 Software/DMA reads I2CxRXB, clearing I2CxRXIF and RXBF I2CxCNT = 1 NACK Sequence Timing.vsdx I2CxRXIF = 1 Last Edit: First Used: Notes: 1/10/2019 I2CxCLK 4 1 2 3 4 1 2 3 4 1 Begin ACK sequence Figure 36-34. Not Acknowledge (NACK) Sequence Timing ACKCNT copied to SDA SDA D1 SCL 7 RXBF D0 NACK 8 NACK Complete 9 CNTIF = 1 I2CxCNT = 0 I2CxRXIF = 1 I2CxCLK 4 1 2 3 Software/DMA reads I2CxRXB, clearing I2CxRXIF and RXBF 4 1 2 3 4 1 Begin NACK sequence 36.4.2.5 Restart Condition Timing A Restart condition is identical to a Start condition. A host device may issue a Restart instead of a Stop condition if it intends to hold the bus after completing the current data transfer. A Restart condition occurs when the Restart Enable (RSEN) bit is set (RSEN = 1), either I2CxCNT is zero (I2CxCNT = 0) or ACKSTAT is set (ACKSTAT = 1), and either host hardware (ABD = 1) or user software (ABD = 0) sets the Start (S) bit. When the Start bit is set, host hardware releases SDA (SDA floats high) for half of an SCL clock period (TSCL/2), and then releases SCL for another half of an SCL period, then samples SDA (see Figure 36-35). If SDA is sampled low while SCL is sampled high, a bus collision has occurred. In this case, the Bus Collision Detect Interrupt Flag (BCLIF) is set, and if the Bus Collision Detect Interrupt Enable (BCLIE) bit is also set, the generic I2CxEIF is set and the module goes Idle. If SDA is sampled high while SCL is also sampled high, host hardware issues a Start condition. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 633 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Once the Restart condition is detected on the bus, the Restart Condition Interrupt Flag (RSCIF) is set by hardware, and if the Restart Condition Interrupt Enable (RSCIE) bit is set, the generic I2CxIF is also set. Figure 36-35. Restart Condition Timing Hardware samples SDA Write to Start (S) bit Completion of Repeated Start SDA tSU:STA(1) If ABD = 0: I2C Shift register loaded from I2CxADB0/1 If ABD = 1: I2C Shift register loaded from I2CxTXB TSCL/2 SCL TSCL/2 I2CxCLK 1 2 3 Host releases SDA 4 1 2 3 4 Host releases SCL 1 2 3 4 1 2 3 4 1 2 Repeated Start condition detected RSCIF = 1 Important:  1. See the device data sheet for Restart condition setup times. 36.4.2.6 Stop Condition Timing A Stop condition occurs when SDA transitions from an Active state to an Idle state while SCL is Idle. Host hardware will issue a Stop condition when it has completed its current transmission and is ready to release control of the bus. A Stop condition is also issued after an Error condition occurs, such as a bus time-out, or when a NACK condition is detected on the bus. User software may also generate a Stop condition by setting the Stop (P) bit. After the ACK/NACK sequence of the final byte of the transmitted/received packet, hardware pulls SCL low for half of an SCL period (TSCL/2) (see Figure 36-36). After the half SCL period, hardware releases SCL, then samples SCL to ensure it is in an Idle state (SCL = 1). Host hardware then waits the duration of the Stop condition setup time (TSU:STO) and releases SDA, setting the Stop Condition Interrupt Flag (PCIF). If the Stop Condition Interrupt Enable (PCIE) bit is also set, the generic I2CxIF is also set. Important:  At least one SCL low period must appear before a Stop condition is valid. If the SDA line transitions low, then high again, while SCL is high, the Stop condition is ignored, and a Start condition will be detected by the receiver. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 634 Last Edit: First Used: Notes: 1/28/2019 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Figure 36-36. Stop Condition Timing Stop detected PCIF = 1 Stop condition begins D0 SDA TSU:STO(2) NACK THD:STO(2) TSCL/2(1) SCL 8 9 NACK SEQUENCE I2CxCLK 1 2 3 4 1 2 3 4 1 2 3 4 1 2 Important:  1. At least one SCL low period must appear before a Stop is valid. 2. See the device data sheet Electrical Specifications for Stop condition setup and hold times. 36.4.2.7 Host Operation in 7-Bit Addressing Modes In Host 7-bit Addressing modes, the client’s 7-bit address and R/W bit value are loaded into either I2CxADB1 or I2CxTXB, depending on the Address Buffer Disable (ABD) bit setting. When the host wishes to read data from the client, software must set the R/W bit (R/W = 1). When the host wishes to write data to the client, software must clear the R/W bit (R/W = 0). 36.4.2.7.1 Host Transmission (7-Bit Addressing Mode) The following section describes the sequence of events that occur when the module is transmitting data in 7-bit Addressing mode: 1. Depending on the configuration of the Address Buffer Disable (ABD) bit, one of two methods may be used to begin communication: a. When ABD is clear (ABD = 0), the address buffer, I2CxADB1, is enabled. In this case, the 7-bit client address and R/W bit are loaded into I2CxADB1, with the R/W bit clear (R/W = 0). The number of data bytes are loaded into I2CxCNT, and the first data byte is loaded into I2CxTXB. After these registers are loaded, software must set the Start (S) bit to begin communication. Once the S bit is set, host hardware waits for the Bus Free (BFRE) bit to be set before transmitting the Start condition to avoid bus collisions. b. When ABD is set (ABD = 1), the address buffer is disabled. In this case, the number of data bytes are loaded into I2CxCNT, and the client’s 7-bit address and R/W bit are loaded into I2CxTXB. A write to I2CxTXB will cause host hardware to automatically issue a Start condition once the bus is Idle (BFRE = 1). Software writes to the Start bit are ignored. 2. Host hardware waits for BFRE to be set, then shifts out the Start condition. Module hardware sets the Host Mode Active (MMA) bit and the Start Condition Interrupt Flag (SCIF). If the Start Condition Interrupt Enable (SCIE) bit is set, the generic I2CxIF is also set. Host hardware transmits the 7-bit client address and R/W bit. 3. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 635 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 4. 5. 6. 7. 8. If upon the 8th falling edge of SCL, I2CxTXB is empty (Transmit Buffer Empty Status (TXBE) = 1), I2CxCNT is nonzero (I2CxCNT != 0), and the Clock Stretching Disable (CSD) bit is clear (CSD = 0): – The I2C Transmit Interrupt Flag (I2CxTXIF) is set. If the I2C Transmit Interrupt Enable (I2CxTXIE) bit is also set, the generic I2CxIF is also set. – The Host Data Request (MDR) bit is set, and the clock is stretched, allowing time for software to load I2CxTXB with new data. Once I2CxTXB has been written, hardware releases SCL and clears MDR. Hardware transmits the 9th clock pulse and waits for an ACK/NACK response from the client. If the host receives an ACK, module hardware transfers the data from I2CxTXB into the transmit shift register, and I2CxCNT is decremented by one. If the host receives a NACK, hardware will attempt to issue a Stop condition. If the clock is currently being stretched by a client, the host must wait until the bus is free before issuing the Stop. Host hardware checks I2CxCNT for a zero value. If I2CxCNT is zero: a. If ABD is clear (ABD = 0), host hardware issues a Stop condition, or sets MDR if the Restart Enable (RSEN) bit is set and waits for software to set the Start bit to issue a Restart condition. CNTIF is set. b. If ABD is set (ABD = 1), host hardware issues a Stop condition, or sets MDR if RSEN is set and waits for software to load I2CxTXB with a new client address. CNTIF is set. Host hardware transmits the data byte. If upon the 8th falling edge of SCL I2CxTXB is empty (TXBE = 1), I2CxCNT is nonzero (I2CxCNT != 0), and CSD is clear (CSD = 0): – I2CxTXIF is set. If the I2CxTXIE bit is also set, the generic I2CxIF is also set. – The MDR bit is set, and the clock is stretched, allowing time for software to load I2CxTXB with new data. Once I2CxTXB has been written, hardware releases SCL and clears MDR. If TXBE is set (TXBE = 1) and I2CxCNT is zero (I2CxCNT = 0): 9. – I2CxTXIF is NOT set. – CNTIF is set. – Host hardware issues a Stop condition, setting PCIF. Repeat Steps 5 – 8 until all data has been transmitted. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 636 Notes: © 2020-2021 Microchip Technology Inc. and its subsidiaries Rev. I2C Host 1/9/2019 Figure 36-37. 7-Bit Host Mode Transmission rotatethispage90 R/W Start SDA A7 A6 A5 A4 A3 A2 A1 0 Stop ACK (from client) D7 D6 D5 D4 D3 D2 D1 D0 Hardware sets PCIF D7 D6 D5 D4 D3 D2 D1 D0 7-bit address SCL MMA 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0x02 Before Start, software loads data into I2CxTXB 0x00 Data byte transferred to shift register, I2CxTXIF NOT set Software loads data into I2CxTXB, clearing I2CxTXIF DS40002214E-page 637 PIC18F06/16Q41 I2CxTXIF set, data byte transferred to shift register 0x01 I2C - Inter-Integrated Circuit Module Preliminary Datasheet TXBE Hardware sets CNTIF; RSTEN = 0, so host issues Stop Client's ACK copied to ACKSTAT ACKSTAT I2CxCNT Hardware clears MMA Hardware sets MMA on detection of Start PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.4.2.7.2 Host Reception (7-Bit Addressing Mode) The following section describes the sequence of events that occur when the module is receiving data in 7-bit Addressing mode: 1. Depending on the configuration of the Address Buffer Disable (ABD) bit, one of two methods may be used to begin communication: a. When ABD is clear (ABD = 0), the address buffer, I2CxADB1, is enabled. In this case, the 7-bit client address and R/W bit are loaded into I2CxADB1, with the R/W bit set (R/W = 1). The number of expected received data bytes are loaded into I2CxCNT. After these registers are loaded, software must set the Start (S) bit to begin communication. Once the S bit is set, host hardware waits for the Bus Free (BFRE) bit to be set before transmitting the Start condition to avoid bus collisions. b. When ABD is set (ABD = 1), the address buffer is disabled. In this case, the number of expected received data bytes are loaded into I2CxCNT, and the client’s 7-bit address and R/W bit are loaded into I2CxTXB. A write to I2CxTXB will cause host hardware to automatically issue a Start condition once the bus is Idle (BFRE = 1). Software writes to the Start bit are ignored. 2. Host hardware waits for BFRE to be set, then shifts out the Start condition. Module hardware sets the Host Mode Active (MMA) bit and the Start Condition Interrupt Flag (SCIF). If the Start Condition Interrupt Enable (SCIE) bit is set, the generic I2CxIF is also set. Host hardware transmits the 7-bit client address and R/W bit. Host hardware samples SCL to determine if the client is stretching the clock, and continues to sample SCL until the line is sampled high. Host hardware transmits the 9th clock pulse, and receives the ACK/NACK response from the client. If an ACK is received, host hardware receives the first seven bits of the data byte into the receive shift register. 3. 4. 5. If a NACK is received, hardware sets the NACK Detect Interrupt Flag (NACKIF), and: a. b. 6. 7. 8. ABD = 0: Host generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for software to set the Start bit to generate a Restart condition. ABD = 1: Host generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for software to load a new address into I2CxTXB. Software writes to the Start bit are ignored. If the NACK Detect Interrupt Enable (NACKIE) is also set, hardware sets the generic I2CxEIF bit. If previous data remains in the I2C Receive Buffer (I2CxRXB) when the first seven bits of the new byte are received into the receive shift register (RXBF = 1), the MDR bit is set (MDR = 1), and the clock is stretched after the 7th falling edge of SCL. This allows the host time to read I2CxRXB, which clears the RXBF bit, and prevents receive buffer overflows. Once RXBF is clear, hardware releases SCL. The host clocks in the 8th bit of the data byte into the receive shift register, then transfers the full byte into I2CxRXB. Host hardware sets the I2C Receive Interrupt Flag (I2CxRXIF) and RXBF, and if the I2C Receive Interrupt Enable (I2CxRXIE) is set, the generic I2CxIF is also set. Finally, I2CxCNT is decremented by one. Host hardware checks I2CxCNT for a zero value. If I2CxCNT is nonzero (I2CxCNT != 0), hardware transmits the value of the Acknowledge Data (ACKDT) bit as the acknowledgement response to the client. It is up to user software to properly configure ACKDT. In most cases, ACKDT must be clear (ACKDT = 0), which indicates an ACK response. If I2CxCNT is zero (I2CxCNT = 0), hardware transmits the value of the Acknowledge End of Count (ACKCNT) bit as the acknowledgement response to the client. CNTIF is set, and host hardware either issues a Stop condition or a Restart condition. It is up to user software to properly configure ACKCNT. In most cases, ACKCNT must be set (ACKCNT = 1), which indicates a NACK response. When hardware detects a NACK on the bus, it automatically issues a Stop condition. If a NACK is not detected, the Stop will not be generated, which may lead to a stalled Bus condition. 9. Host hardware receives the first seven bits of the next data byte into the receive shift register. 10. Repeat Steps 6 – 9 until all expected bytes have been received. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 638 Notes: and its subsidiaries © 2020-2021 Microchip Technology Inc. Rev. I2C Host 1/9/2019 Figure 36-38. 7-Bit Host Mode Reception rotatethispage90 Start SDA A7 A6 A5 A4 A3 A2 A1 1 7-bit address SCL MMA ACK (from host ) R/W D7 D6 D5 D4 D3 D2 D1 D0 Hardware sets PCIF D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Hardware clears MMA Hardware sets MMA on detection of Start Host's NACK copied from ACKCNT 0x02 0x01 Software reads I2CxRXB, clearing I2CxRXIF PIC18F06/16Q41 DS40002214E-page 639 I2CxRXIF is set 0x00 I2C - Inter-Integrated Circuit Module Preliminary Datasheet Hardware sets CNTIF; RSTEN = 0, so host issues Stop Host's ACK copied from ACKDT ACKCNT RXBF Stop ACK (from client) ACKDT I2CxCNT NACK (from host ) PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.4.2.8 Host Operation in 10-Bit Addressing Modes In Host 10-bit Addressing modes, the client’s 10-bit address and R/W bit value are loaded into either the I2CxADB0 and I2CxADB1 registers (when ABD = 0), or I2CxTXB (when ABD = 1). When the host intends to read data from the client, it must first transmit the full 10-bit address with the R/W bit clear (R/W = 0), issue a Restart condition, then transmit the address high byte with the R/W bit set (R/W = 1). When the host intends to write data to the client, it must transmit the full 10-bit address with the R/W bit clear (R/W = 0). 36.4.2.8.1 Host Transmission (10-Bit) The following section describes the sequence of events that occur when the module is transmitting data in 10-bit Addressing mode: 1. 2. 3. 4. Depending on the configuration of the Address Buffer Disable (ABD) bit, one of two methods may be used to begin communication: a. When ABD is clear (ABD = 0), the address buffers, I2CxADB0 and I2CxADB1, are enabled. In this case, the address high byte is loaded into I2CxADB1 with the R/W bit clear, while the address low byte is loaded into I2CxADB0. I2CxCNT is loaded with the total number of data bytes to transmit, and the first data byte is loaded into I2CxTXB. After these registers are loaded, software must set the Start bit to begin communication. b. When ABD is set (ABD = 1), the address buffers are disabled. In this case, I2CxCNT must be loaded with the total number of bytes to transmit prior to loading I2CxTXB with the address high byte and R/W bit. A write to I2CxTXB forces module hardware to issue a Start condition automatically; software writes to the S bit are ignored. Host hardware waits for BFRE to be set, then shifts out the Start condition. Module hardware sets the Host Mode Active (MMA) bit and the Start Condition Interrupt Flag (SCIF). If the Start Condition Interrupt Enable (SCIE) bit is also set, the generic I2CxIF is also set. Host hardware transmits the address high byte and R/W bit from I2CxADB1. Host hardware transmits the 9th clock pulse and shifts in the ACK/NACK response from the client. If the host receives a NACK, it issues a Stop condition. If the host receives and ACK and: a. ABD = 0: Hardware transmits the address low byte from I2CxADB0. b. 5. 6. 7. 8. 9. ABD = 1: Hardware sets I2CxTXIF and the Host Data Request (MDR) bit and waits for software to load I2CxTXB with the address low byte. Software must load I2CxTXB to resume communication. If upon the 8th falling edge of SCL I2CxTXB is empty (TXBE = 1), I2CxCNT is nonzero (I2CxCNT != 0), and the Clock Stretching Disable (CSD) bit is clear (CSD = 0): – I2CxTXIF is set. If the I2C Transmit Interrupt Enable (I2CxTXIE) bit is also set, the generic I2CxIF is also set. – MDR bit is set, and the clock is stretched, allowing time for software to load I2CxTXB with the address low byte. Once I2CxTXB has been written, hardware releases SCL and clears MDR. Hardware transmits the 9th clock pulse and waits for an ACK/NACK response from the client. If the host receives an ACK, module hardware transfers the data from I2CxTXB into the transmit shift register, and I2CxCNT is decremented by one. If the host receives a NACK, hardware will attempt to issue a Stop condition. If the clock is currently being stretched by a client, the host must wait until the bus is free before issuing the Stop. Host hardware checks I2CxCNT for a zero value. If I2CxCNT is zero: a. If ABD is clear (ABD = 0), host hardware issues a Stop condition, or sets MDR if the Restart Enable (RSEN) bit is set and waits for software to set the Start bit to issue a Restart condition. CNTIF is set. b. If ABD is set (ABD = 1), host hardware issues a Stop condition, or sets MDR if RSEN is set and waits for software to load I2CxTXB with a new client address. CNTIF is set. Host hardware transmits the data byte. If upon the 8th falling edge of SCL I2CxTXB is empty (TXBE = 1), I2CxCNT is nonzero (I2CxCNT != 0), and CSD is clear (CSD = 0): – The I2CxTXIF bit is set. If the I2CxTXIE bit is also set, the generic I2CxIF is also set. – The MDR bit is set, and the clock is stretched, allowing time for software to load I2CxTXB with new data. Once I2CxTXB has been written, hardware releases SCL and clears MDR. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 640 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module If TXBE is set (TXBE = 1) and I2CxCNT is zero (I2CxCNT = 0): – I2CxTXIF is NOT set. – CNTIF is set. – Host hardware issues a Stop condition, setting PCIF. 10. Repeat Steps 6 – 9 until all data has been transmitted. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 641 and its subsidiaries © 2020-2021 Microchip Technology Inc. Figure 36-39. 10-Bit Host Mode Transmission rotatethispage90 Start SDA R/W 1 1 1 1 0 A9 A8 0 Stop ACK (from client) A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hardware sets PCIF High address SCL MMA 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0x01 Before Start, software loads data into I2CxTXB 0x00 DS40002214E-page 642 PIC18F06/16Q41 Data byte transferred to shift register, I2CxTXIF NOT set I2C - Inter-Integrated Circuit Module Preliminary Datasheet TXBE Hardware sets CNTIF; RSTEN = 0, so host issues Stop Client's ACK copied to ACKSTAT ACKSTAT I2CxCNT Hardware clears MMA Hardware sets MMA on detection of Start PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.4.2.8.2 Host Reception (10-Bit Addressing Mode) The following section describes the sequence of events that occur when the module is receiving data in 10-bit Addressing mode: 1. Depending on the configuration of the Address Buffer Disable (ABD) bit, one of two methods may be used to begin communication: a. When ABD is clear (ABD = 0), the address buffers, I2CxADB0 and I2CxADB1, are enabled. In this case, the address high byte and R/W bit are loaded into I2CxADB1, with R/W clear (R/W = 0). The address low byte is loaded into I2CxADB0, and the Restart Enable (RSEN) bit is set by software. After these registers are loaded, software must set the Start (S) bit to begin communication. Once the S bit is set, host hardware waits for the Bus Free (BFRE) bit to be set before transmitting the Start condition to avoid bus collisions. b. When ABD is set (ABD = 1), the address buffers are disabled. In this case, the number of expected received bytes are loaded into I2CxCNT, the address high byte and R/W bit are loaded into I2CxTXB, with R/W clear (R/W = 0). A write to I2CxTXB will cause host hardware to automatically issue a Start condition once the bus is Idle (BFRE = 1). Software writes to the Start bit are ignored. 2. Host hardware waits for BFRE to be set, then shifts out the Start condition. Module hardware sets the Host Mode Active (MMA) bit and the Start Condition Interrupt Flag (SCIF). If the Start Condition Interrupt Enable (SCIE) bit is set, the generic I2CxIF is also set. Host hardware transmits the address high byte and R/W bit. Host hardware samples SCL to determine if the client is stretching the clock, and continues to sample SCL until the line is sampled high. Host hardware transmits the 9th clock pulse, and receives the ACK/NACK response from the client. If a NACK was received, the NACK Detect Interrupt Flag (NACKIF) is set and the host immediately issues a Stop condition. 3. 4. 5. 6. 7. If an ACK was received, module hardware transmits the address low byte. Host hardware samples SCL to determine if the client is stretching the clock, and continues to sample SCL until the line is sampled high. Host hardware transmits the 9th clock pulse, and receives the ACK/NACK response from the client. If an ACK was received, hardware sets MDR, and waits for hardware or software to set the Start bit. If a NACK is received, hardware sets NACKIF, and: a. b. 8. 9. ABD = 0: Host generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for software to set the Start bit to generate a Restart condition. ABD = 1: Host generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for software to load a new address into I2CxTXB. Software writes to the Start bit are ignored. If the NACK Detect Interrupt Enable (NACKIE) is also set, hardware sets the generic I2CxEIF bit. Software loads I2CxCNT with the expected number of received bytes. If ABD is clear (ABD = 0), software sets the Start bit. If ABD is set (ABD = 1), software writes the address high byte with R/W bit into I2CxTXB, with R/W set (R/W = 1). 10. Host hardware transmits the Restart condition, which sets the Restart Condition Interrupt Flag (RSCIF) bit. If the Restart Condition Interrupt Enable (RSCIE) bit is set, the generic I2CxIF is set by hardware. 11. Host hardware transmits the high address byte and R/W bit. 12. Host hardware samples SCL to determine if the client is stretching the clock, and continues to sample SCL until the line is sampled high. 13. Host hardware transmits the 9th clock pulse, and receives the ACK/NACK response from the client. If an ACK is received, host hardware receives the first seven bits of the data byte into the receive shift register. If a NACK is received, and: a. b. ABD = 0: Host generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for software to set the Start bit to generate a Restart condition. ABD = 1: Host generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for software to load a new address into I2CxTXB. Software writes to the Start bit are ignored. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 643 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 14. If previous data is currently in I2CxRXB (RXBF = 1) when the first seven bits are received by the receive shift register, hardware sets MDR, and the clock is stretched after the 7th falling edge of SCL. This allows software to read I2CxRXB, which clears the RXBF bit, and prevents a receive buffer overflow. Once the RXBF bit is cleared, hardware releases SCL. 15. Host hardware clocks in the 8th bit of the data byte into the receive shift register, then transfers the complete byte into I2CxRXB, which sets the I2CxRXIF and RXBF bits. If I2CxRXIE is also set, hardware sets the generic I2CxIF bit. I2CxCNT is decremented by one. 16. Hardware checks I2CxCNT for a zero value. If I2CxCNT is nonzero (I2CxCNT != 0), hardware transmits the value of the Acknowledge Data (ACKDT) bit as the acknowledgement response to the client. It is up to user software to properly configure ACKDT. In most cases, ACKDT must be clear (ACKDT = 0), which indicates an ACK response. If I2CxCNT is zero (I2CxCNT = 0), hardware transmits the value of the Acknowledge End of Count (ACKCNT) bit as the acknowledgement response to the client. CNTIF is set, and host hardware either issues a Stop condition or a Restart condition. It is up to user software to properly configure ACKCNT. In most cases, ACKCNT must be set (ACKCNT = 1), which indicates a NACK response. When hardware detects a NACK on the bus, it automatically issues a Stop condition. If a NACK is not detected, the Stop will not be generated, which may lead to a stalled Bus condition. 17. Host hardware receives the first seven bits of the next data byte into the receive shift register. 18. Repeat Steps 14 – 17 until all expected bytes have been received. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 644 and its subsidiaries © 2020-2021 Microchip Technology Inc. Figure 36-40. 10-Bit Host Mode Reception rotatethispage90 R/W SDA 1 1 1 1 0 A9 A8 0 High address ACK (from client) A7 A6 A5 A4 A3 A2 A1 A0 Low address NACK (from host ) R/W Restart 1 1 1 1 0 A9 A8 1 High address Stop D7 D6 D5 D4 D3 D2 D1 D0 ACK (from client) SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 MMA Hardware sets MMA on detection of Start Software clears RSTEN before setting Start RSTEN Software sets RSTEN before setting Start 0x00 0x01 0x00 Client's ACK copied to ACKSTAT Received data transferred to I2CxRXB, I2CxRXIF is set PIC18F06/16Q41 DS40002214E-page 645 RXBF Hardware sets RSCIF Software loads I2CxCNT before setting Start I2CxCNT ACKSTAT Software sets Start, clearing MDR I2C - Inter-Integrated Circuit Module Preliminary Datasheet Hardware sets MDR, wait for Start MDR Hardware sets NACKIF, CNTIF PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.4.3 I2C Multi-Host Mode Operation In Multi-Host mode, multiple host devices reside on the same bus. A single device, or all devices, may act as both a host and a client. Control of the bus is achieved through clock synchronization and bus arbitration. The Bus Free (BFRE) bit is used to determine if the bus is free. When BFRE is set (BFRE = 1), the bus is in an Idle state, allowing a host device to take control of the bus. In Multi-Host mode, the Address Interrupt and Hold Enable (ADRIE) bit must be set (ADRIE = 1), and the Clock Stretching Disable (CSD) bit must be clear (CSD = 0), for a host device to be addressed as a client. When a matching address is received into the receive shift register, the SMA bit is set, and the Address Interrupt Flag (ADRIF) bit is set. Since ADRIE is also set, hardware sets the Client Clock Stretching (CSTR) bit, and hardware stretches the clock to allow time for software to respond to the host device being addressed as a client. Once the address has been processed, software must clear CSTR to resume communication. Important:  Client hardware has priority over host hardware in Multi-Host mode. Host mode communication can only be initiated when SMA = 0. 36.4.3.1 Multi-Host Mode Clock Synchronization In a multi-host system, each host may begin to generate a clock signal as soon as the bus is Idle. Clock synchronization allows all devices on the bus to use a single SCL signal. When a high-to-low transition on SCL occurs, all active host devices begin SCL low period timing, with their clocks held low until their low hold time expires and the High state is reached. If one host’s clock signal is still low, SCL will be held low until that host reaches its High state. During this time, all other host devices are held in a Wait state (see Figure 36-41). Once all hosts have counted off their low period times, SCL is released high, and all host devices begin counting their high periods. The first host to complete its high period pulls the SCL line low again. This means that when the clocks are synchronized, the SCL low period is determined by the host with the longest SCL low period, while the SCL high period is determined by the host device with the shortest SCL high period. Important:  The I2C Specification does not require the SCL signal to have a 50% duty cycle. In other words, one host’s clock signal may have a low time that is 60% of the SCL period and a high time that is 40% of the SCL period, while another host may be 50/50. This creates a timing difference between the two clock signals, which may result in data loss. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 646 Title: Last Edit: First Used: Notes: 1/9/2019 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Figure 36-41. Clock Synchronization During Arbitration Wait state Host 1 SCL Host 2 SCL Actual bus SCL Host 1 pulls SCL low first Host 1 releases SCL, but Host 2 continues to pull SCL low Host 2 releases SCL 36.4.3.2 Multi-Host Mode Bus Arbitration When the bus is Idle, any host device may attempt to take control of the bus. Two or more host devices may issue a Start condition within the minimum hold time (THD:STA), which triggers a valid Start on the bus. The host devices must then compete using bus arbitration to determine who takes control of the bus and completes their transaction. Bus arbitration takes place bit by bit, and it may be possible for two hosts who have identical messages to complete the entire transaction without either device losing arbitration. During every bit period, while SCL is high each host device compares the actual signal level of SDA to the signal level the host actually transmitted. SDA sampling is performed during the SCL high period because the SDA data must be stable during this period; therefore, the first host to detect a low signal level on SDA while it expects a high signal level loses arbitration. In this case, the ‘losing’ host device detects a bus collision and sets the Bus Collision Detect Interrupt Flag (BCLIF), and if the Bus Collision Detect Interrupt Enable (BCLIE) bit is set, the generic I2CxEIF is also set. Arbitration can be lost in any of the following states: • • • • • • Address transfer Data transfer Start condition Restart condition Acknowledge sequence Stop condition If a collision occurs during the data transfer phase, the transmission is halted and both SCL and SDA are released by hardware. If a collision occurs during a Start, Restart, Acknowledge, or Stop, the operation is aborted and hardware releases SCL and SDA. If a collision occurs during the addressing phase, the host that ‘wins’ arbitration may be © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 647 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module attempting to address the ‘losing’ host as a client. In this case, the host that lost arbitration must switch to its Client mode and check to see if an address matches. Filename: Title: Last Edit: First Used: Notes: Bus Collision.vsdx Important:  The I2C Specification states that a bus collision cannot occur during a Start condition. If a 1/9/2019 collision occurs during a Start, BCLIF will be set during the addressing phase. User software must clear BCLIF to resume operation. Figure 36-42. Bus Collision R Host 2 pulls SDA low Host 1 releases SDA Host 1 samples SDA low, but expects SDA high Expected SDA (SDA = 1) SDA Actual SDA (SDA = 0) SCL BCLIF Change of data allowed © 2020-2021 Microchip Technology Inc. and its subsidiaries Hardware sets BCLIF Preliminary Datasheet DS40002214E-page 648 Filename: Title: Last Edit: First Used: Notes: I2C Host Mode Transmission Waveforms .vsdx 1/9/2019 © 2020-2021 Microchip Technology Inc. and its subsidiaries Figure 36-43. Multi-Host Mode Transmission rotatethispage90 Stop Start SCL SDA (Host 1 ) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Host 1 wins arbitration, continues transmitting 1 1 0 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W SDA (Host 2 ) 1 1 1 ACK (from client) Host 2 loses arbitration, hardware releases SDA (Host 1) Host 2 loses arbitration, hardware clears MMA (Host 2 ) DS40002214E-page 649 0x02 I2CxTXIF set, data byte transferred to shift register 0x01 Software loads data into I2CxTXB, clearing I2CxTXIF 0x00 Data byte transferred to shift register, I2CxTXIF NOT set PIC18F06/16Q41 Client's ACK copied to ACKSTAT ACKSTAT TXBE Hardware clears MMA Host 2 loses arbitration, hardware sets BCLIF (software must clear BCLIF to resume communication) BCLIF I2CxCNT Hardware sets CNTIF; RSTEN = 0, so host issues Stop I2C - Inter-Integrated Circuit Module Preliminary Datasheet MMA MMA Hardware sets PCIF D7 D6 D5 D4 D3 D2 D1 D0 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5 Register Definitions: I2C Control Long bit name prefixes for the I2C peripherals are shown in the following table. Refer to the “Long Bit Names” section in the “Register and Bit Naming Conventions” chapter for more information. Table 36-3. I2C Long Bit Name Prefixes Peripheral Bit Name Prefix I2C1 I2C1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 650 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.1 I2CxCON0 Name:  Address:  I2CxCON0 0x0294 I2C Control Register 0 Bit 7 EN R/W 0 Access Reset 6 RSEN R/W 0 5 S R/W/HS/HC 0 4 CSTR R/C/HS/HC 0 3 MDR R 0 2 R/W 0 1 MODE[2:0] R/W 0 0 R/W 0 Bit 7 – EN  I2C Module Enable(1,2) Value Description 1 The I2C module is enabled 0 The I2C module is disabled Bit 6 – RSEN  Restart Enable (used only when MODE = 1xx) Value Description 1 Hardware sets MDR on 9th falling SCL edge (when I2CxCNT = 0 or ACKSTAT = 1) 0 Hardware issues Stop condition on 9th falling SCL edge (when I2CxCNT = 0 or ACKSTAT = 1) Bit 5 – S  Host Start (used only when MODE = 1xx) Value Condition Description 1 MMA = 0: Set by write to I2CxTXB or S bit, hardware issues Start condition 0 MMA = 0: Cleared by hardware after sending Start condition 1 MMA = 1 and MDR = 1: Set by write to I2CxTXB or S bit, communication resumes with a Restart condition 0 MMA = 1 and MDR = 1: Cleared by hardware after sending Restart condition Bit 4 – CSTR  Client Clock Stretching(3) Value Condition 1 0 SMA = 1 and RXBF = 1(6): SMA = 1 and TXBE = 1 and I2CxCNT != 0: when ADRIE = 1(4): SMA = 1 and WRIE = 1: SMA = 1 and ACKTIE = 1: Description Clock is held low (clock stretching) Enable clocking, SCL control is released Set by hardware on 7th falling SCL edge User must read I2CxRXB and clear CSTR to release SCL Set by hardware on 8th falling SCL edge User must write to I2CxTXB and clear CSTR to release SCL Set by hardware on 8th falling edge of matching received address User must clear CSTR to release SCL Set by hardware on 8th falling SCL edge of received data byte User must clear CSTR to release SCL Set by hardware on 9th falling SCL edge User must clear CSTR to release SCL Bit 3 – MDR  Host Data Request (Host pause) Value Condition 1 0 MMA = 1 and RXBF = 1 (pause for RX): MMA = 1 and TXBE = 1 and I2CxCNT != 0 (pause for TX): © 2020-2021 Microchip Technology Inc. and its subsidiaries Description Host state machine pauses until data is read/written (SCL is held low) Host clocking of data is enabled Set by hardware on 7th falling SCL edge User must read I2CxRXB to release SCL Set by hardware on the 8th falling SCL edge User must write to I2CxTXB to release SCL Preliminary Datasheet DS40002214E-page 651 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Value Condition RSEN = 1 and MMA = 1 and (I2CxCNT = 0 or ACKSTAT = 1) (pause for Restart): Description Set by hardware on 9th falling SCL edge User must set S bit or write to I2CxTXB to release SCL and issue a Restart condition Bits 2:0 – MODE[2:0]  I2C Mode Select Value Description 111 I2C Multi-Host mode (SMBus 2.0 Host)(5) 110 I2C Multi-Host mode (SMBus 2.0 Host)(5) 101 I2C Host mode, 10-bit address 100 I2C Host mode, 7-bit address 011 I2C Client mode, one 10-bit address with masking 010 I2C Client mode, two 10-bit addresses 001 I2C Client mode, two 7-bit addresses with masking 000 I2C Client mode, four 7-bit addresses Notes:  1. SDA and SCL pins must be configured as open-drain I/Os and use either internal or external pull-up resistors. 2. SDA and SCL signals must configure both the input and output PPS registers for each signal. 3. CSTR can be set by multiple hardware sources; all sources must be addressed by user software before the SCL line can be released. 4. SMA is set on the same SCL edge as CSTR for a matching received address. 5. In this mode, ADRIE needs to be set, allowing an interrupt to clear the BCLIF condition and the ACK of a matching address. 6. In 10-bit Client mode (when ABD = 1), CSTR will be set when the high address has not been read from I2CxRXB before the low address is shifted in. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 652 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.2 I2CxCON1 Name:  Address:  I2CxCON1 0x0295 I2C Control Register 1 Bit Access Reset 7 ACKCNT R/W 0 6 ACKDT R/W 0 5 ACKSTAT R 0 4 ACKT R 0 3 P R/S/HC 0 2 RXO R/W/HS 0 1 TXU R/W/HS 0 0 CSD R/W 0 Bit 7 – ACKCNT  Acknowledge End of Count(2) Value Condition Description 1 I2CxCNT = 0 Not Acknowledge (NACK) copied to SDA output 0 I2CxCNT = 0 Acknowledge (ACK) copied to SDA output Bit 6 – ACKDT  Acknowledge Data(1,2) Value Condition 1 Matching received address 0 Matching received address 1 I2CxCNT != 0 0 I2CxCNT != 0 Description Not Acknowledge (NACK) copied to SDA output Acknowledge (ACK) copied to SDA output Not Acknowledge (NACK) copied to SDA output Acknowledge (ACK) copied to SDA output Bit 5 – ACKSTAT  Acknowledge Status (Transmission only) Value Description 1 Acknowledge was not received for the most recent transaction 0 Acknowledge was received for the most recent transaction Bit 4 – ACKT Acknowledge Time Status Value Description 1 Indicates that the bus is in an Acknowledge sequence, set on the 8th falling SCL edge 0 Not in an Acknowledge sequence, cleared on the 9th rising SCL edge Bit 3 – P  Host Stop(4) Value Condition 1 MMA = 1 0 MMA = 1 Description Initiate a Stop condition Cleared by hardware after sending Stop Bit 2 – RXO  Receive Overflow Status (used only when MODE = 0xx or MODE = 11x)(3) Value Description 1 Set when SMA = 1 and a host receives data when RXBF = 1 0 No client receive Overflow condition Bit 1 – TXU  Transmit Underflow Status (used only when MODE = 0xx or MODE = 11x)(3) Value Description 1 Set when SMA = 1 and a host transmits data when TXBE = 1 0 No client transmit Underflow condition Bit 0 – CSD  Clock Stretching Disable (used only when MODE = 0xx or MODE = 11x) Value Description 1 When SMA = 1, the CSTR bit will not be set 0 Client clock stretching proceeds normally © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 653 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module Notes:  1. Software writes to ACKDT must be followed by a minimum SDA setup time before clearing CSTR. 2. A NACK may still be generated by hardware when bus errors are present as indicated by the I2CxSTAT1 or I2CxERR registers. 3. This bit can only be set when CSD = 1. 4. If SCL is high (SCL = 1) when this bit is set, the current clock pulse will complete (SCL = 0) with the proper SCL/SDA timing required for a valid Stop condition; any data in the transmit or receive shift registers will be lost. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 654 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.3 I2CxCON2 Name:  Address:  I2CxCON2 0x0296 I2C Control Register 2 Bit Access Reset 7 ACNT R/W 0 6 GCEN R/W 0 5 FME R/W 0 4 ABD R/W 0 3 2 1 0 SDAHT[1:0] R/W 0 BFRET[1:0] R/W 0 R/W 0 R/W 0 Bit 7 – ACNT  Auto-Load I2C Count Register Enable Value Description 1 The first transmitted/received byte after the address is automatically loaded into the I2CxCNT register 0 Auto-load of I2CxCNT is disabled Bit 6 – GCEN  General Call Address Enable (used when MODE = 00x or MODE = 11x) Value Description 1 General Call Address (0x00) causes an address match event 0 General Call Addressing is disabled Bit 5 – FME Fast Mode Enable Value Description 1 SCL frequency (FSCL) = FI2CxCLK/4 0 SCL frequency (FSCL) = FI2CxCLK/5 Bit 4 – ABD Address Buffer Disable Value Description 1 Address buffers are disabled. Received address is loaded into I2CxRXB, address to transmit is loaded into I2CxTXB. 0 Address buffers are enabled. Received address is loaded into I2CxADB0/I2CxADB1, address to transmit is loaded into I2CxADB0/ I2CxADB1. Bits 3:2 – SDAHT[1:0] SDA Hold Time Selection Value Description 11 Reserved 10 Minimum of 30 ns hold time on SDA after the falling SCL edge 01 Minimum of 100 ns hold time on SDA after the falling SCL edge 00 Minimum of 300 ns hold time on SDA after the falling SCL edge Bits 1:0 – BFRET[1:0] Bus Free Time Selection Value Description 11 64 I2CxCLK pulses 10 32 I2CxCLK pulses 01 16 I2CxCLK pulses 00 8 I2CxCLK pulses © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 655 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.4 I2CxSTAT0 Name:  Address:  I2CxSTAT0 0x0298 I2C Status Register 0 Bit 7 BFRE R 0 Access Reset 6 SMA R 0 5 MMA R 0 4 R R 0 3 D R 0 2 1 0 Bit 7 – BFRE  Bus Free Status(2) Value Description 1 Indicates an Idle bus; both SCL and SDA have been high for the time selected by the BFRET bits 0 Bus is not Idle Bit 6 – SMA Client Mode Active Status Value Description 1 Client mode is active. Set after the 8th falling SCL edge of a received matching 7-bit client address. Set after the 8th falling SCL edge of a matching received 10-bit client low address. 0 Set after the 8th falling SCL edge of a received matching 10-bit client high w/read address, only after a previous received matching high and low w/write address. Client mode is not active. Cleared when any Restart/Stop condition is detected on the bus. Cleared by the BTOIF and BCLIF conditions. Bit 5 – MMA Host Mode Active Status Value Description 1 Host mode is active. Set when Host state machine asserts a Start condition. 0 Host mode is not active. Cleared when BCLIF is set. Cleared when Stop condition is issued. Cleared for the BTOIF condition after the host successfully shifts out a Stop condition. Bit 4 – R  Read Information(1) Value Description 1 Indicates that the last matching received address was a Read request 0 Indicates that the last matching received address was a Write request Bit 3 – D Data Value Description 1 Indicates that the last byte received or transmitted was data 0 Indicates that the last byte received or transmitted was an address Notes:  1. This bit holds the R/W bit information following the last received address match. Addresses transmitted by the host do not affect the host’s R bit, and addresses appearing on the bus without a match do not affect the R bit. 2. I2CxCLK must have a valid clock source selected for this bit to function. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 656 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.5 I2CxSTAT1 Name:  Address:  I2CxSTAT1 0x0299 I2C Status Register 1 Bit Access Reset 7 TXWE R/W/HS 0 6 5 TXBE R 1 4 3 RXRE R/W/HS 0 2 CLRBF R/S 0 1 0 RXBF R 0 Bit 7 – TXWE  Transmit Write Error Status(1) Value Description 1 A new byte of data was written into I2CxTXB when it was full (must be cleared by software) 0 No transmit write error occurred Bit 5 – TXBE  Transmit Buffer Empty Status(2) Value Description 1 I2CxTXB is empty (cleared by writing to the I2CxTXB register) 0 I2CxTXB is full Bit 3 – RXRE  Receive Read Error Status(1) Value Description 1 A byte of data was read from I2CxRXB when it was empty (must be cleared by software) 0 No receive overflow occurred Bit 2 – CLRBF  Clear Buffer(3) Value Description 1 Setting this bit clears/empties the receive and transmit buffers, causing a Reset of RXBF and TXBE Setting this bit clears the I2CxRXIF and I2CxTXIF interrupt flags Bit 0 – RXBF  Receive Buffer Full Status(2) Value Description 1 I2CxRXB is full (cleared by reading the I2CxRXB register) 0 I2CxRXB is empty Notes:  1. This bit, when set, will cause a NACK to be issued. 2. Used as a trigger source for DMA operations. 3. This bit is special function; it can only be set by user software and always reads ‘0’. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 657 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.6 I2CxPIR Name:  Address:  I2CxPIR 0x029A I2C Interrupt Flag Register Bit Access Reset 7 CNTIF R/W/HS 0 6 ACKTIF R/W/HS 0 5 4 WRIF R/W/HS 0 3 ADRIF R/W/HS 0 2 PCIF R/W/HS 0 1 RSCIF R/W/HS 0 0 SCIF R/W/HS 0 Bit 7 – CNTIF  Byte Count Interrupt Flag(1) Value Description 1 Set on the 9th falling SCL edge when I2CxCNT = 0 0 I2CxCNT value is not zero Bit 6 – ACKTIF  Acknowledge Status Time Interrupt Flag (used only when MODE = 0xx or MODE = 11x)(1,2) Value Description 1 Acknowledge sequence detected, set on the 9th falling SCL edge for any byte when addressed as a client 0 Acknowledge sequence not detected Bit 4 – WRIF  Data Write Interrupt Flag (used only when MODE = 0xx or MODE = 11x)(1) Value Description 1 Data byte detected, set on the 8th falling SCL edge for a received data byte 0 Data byte not detected Bit 3 – ADRIF  Address Interrupt Flag (used only when MODE = 0xx or MODE = 11x)(1) Value Description 1 Address detected, set on the 8th falling SCL edge for a matching received address byte 0 Address not detected Bit 2 – PCIF  Stop Condition Interrupt Flag(1) Value Description 1 Stop condition detected 0 Stop condition not detected Bit 1 – RSCIF  Restart Condition Interrupt Flag(1) Value Description 1 Restart condition detected 0 Restart condition not detected Bit 0 – SCIF  Start Condition Interrupt Flag(1) Value Description 1 Start condition detected 0 Start condition not detected Notes:  1. Enabled interrupt flags are OR’ed to produce the PIRx[I2CxIF] bit. 2. ACKTIF is not set by a matching 10-bit high address byte with the R/W bit clear. It is only set after the matching low address byte is shifted in. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 658 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.7 I2CxPIE Name:  Address:  I2CxPIE 0x029B I2C Interrupt and Hold Enable Register Bit 7 CNTIE R/W 0 Access Reset 6 ACKTIE R/W 0 5 4 WRIE R/W 0 3 ADRIE R/W 0 2 PCIE R/W 0 1 RSCIE R/W 0 0 SCIE R/W 0 Bit 7 – CNTIE  Byte Count Interrupt Enable(1) Value Description 1 Enables Byte Count interrupts 0 Disables Byte Count interrupts Bit 6 – ACKTIE  Acknowledge Status Time Interrupt and Hold Enable(1,2) Value Description 1 Enables Acknowledge Status Time Interrupt and Hold condition 0 Disables Acknowledge Status Time Interrupt and Hold condition Bit 4 – WRIE  Data Write Interrupt and Hold Enable(1,3) Value Description 1 Enables Data Write Interrupt and Hold condition 0 Disables Data Write Interrupt and Hold condition Bit 3 – ADRIE  Address Interrupt and Hold Enable(1,4) Value Description 1 Enables Address Interrupt and Hold condition 0 Disables Address Interrupt and Hold condition Bit 2 – PCIE  Stop Condition Interrupt Enable(1) Value Description 1 Enables interrupt on the detection of a Stop condition 0 Disables interrupt on the detection of a Stop condition Bit 1 – RSCIE  Restart Condition Interrupt Enable(1) Value Description 1 Enables interrupt on the detection of a Restart condition 0 Disables interrupt on the detection of a Restart condition Bit 0 – SCIE  Stop Condition Interrupt Enable(1) Value Description 1 Enables interrupt on the detection of a Start condition 0 Disables interrupt on the detection of a Start condition Notes:  1. Enabled interrupt flags are OR’ed to produce the PIRx[I2CxIF] bit. 2. When ACKTIE is set (ACKTIE = 1) and ACKTIF becomes set (ACKTIF = 1), if an ACK is generated, CSTR is also set. If a NACK is generated, CSTR remains unchanged. 3. When WRIE is set (WRIE = 1) and WRIF becomes set (WRIF = 1), CSTR is also set. 4. When ADRIE is set (ADRIE = 1) and ADRIF becomes set (ADRIF = 1), CSTR is also set. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 659 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.8 I2CxERR Name:  Address:  I2CxERR 0x0297 I2C Error Register Bit 7 Access Reset 6 BTOIF R/W/HS 0 5 BCLIF R/W/HS 0 4 NACKIF R/W/HS 0 3 2 BTOIE R/W 0 1 BLCIE R/W 0 0 NACKIE R/W 0 Bit 6 – BTOIF  Bus Time-Out Interrupt Flag(1,2) Value Description 1 Bus time-out event occurred 0 No bus time-out event occurred Bit 5 – BCLIF  Bus Collision Detect Interrupt Flag(1) Value Description 1 Bus collision detected 0 No bus collision occurred Bit 4 – NACKIF  NACK Detect Interrupt Flag(1,3,4) Value Description 1 NACK detected on the bus (when SMA = 1 or MMA = 1) 0 No NACK detected on the bus Bit 2 – BTOIE Bus Time-Out Interrupt Enable Value Description 1 Enable bus time-out interrupts 0 Disable bus time-out interrupts Bit 1 – BLCIE Bus Collision Detect Interrupt Enable Value Description 1 Enable Bus Collision interrupts 0 Disable Bus Collision interrupts Bit 0 – NACKIE NACK Detect Interrupt Enable Value Description 1 Enable NACK detect interrupts 0 Disable NACK detect interrupts Notes:  1. Enabled error interrupt flags are OR’ed to produce the PIRx[I2CxEIF] bit. 2. User software must select the bus time-out source in the I2CxBTOC register. 3. NACKIF is also set when any of the TXWE, RXRE, TXU, or RXO bits are set. 4. NACKIF is not set for the NACK response to a nonmatching client address. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 660 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.9 I2CxCLK Name:  Address:  I2CxCLK 0x029E I2C Clock Selection Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 CLK[3:0] Access Reset R/W 0 R/W 0 Bits 3:0 – CLK[3:0] I2C Clock Selection Table 36-4. CLK 1111 - 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 © 2020-2021 Microchip Technology Inc. and its subsidiaries Selection Reserved CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT SMT1_OUT TMR4_Postscaler_OUT TMR2_Postscaler_OUT TMR0_OUT EXTOSC Clock Reference Output MFINTOSC (500 kHz) HFINTOSC FOSC (System Clock) FOSC/4 Preliminary Datasheet DS40002214E-page 661 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.10 I2CxBAUD Name:  Address:  I2CxBAUD 0x029D I2C Baud Rate Prescaler Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 BAUD[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – BAUD[7:0] Baud Rate Prescaler Selection Value Description n Prescaled I2C Clock Frequency (FPRECLK) = I2CxCLK BAUD + 1 Note:  It is recommended to write this register only when the module is Idle (MMA = 0 or SMA = 0), or when the module is clock stretching (CSTR = 1 or MDR = 1). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 662 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.11 I2CxCNT Name:  Address:  I2CxCNT 0x028C I2C Byte Count Register(1,2) Bit 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 CNT[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 CNT[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 15:0 – CNT[15:0] Byte Count Condition Description If receiving data: Count value decremented on 8th falling SCL edge when a new byte is loaded into I2CxRXB If transmitting data: Count value is decremented on the 9th falling SCL edge when a new byte is moved from I2CxTXB Notes:  1. It is recommended to write this register only when the module is Idle (MMA = 0 or SMA = 0), or when the module is clock stretching (CSTR = 1 or MDR = 1). 2. CNTIF is set on the 9th falling SCL edge when I2CxCNT = 0. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 663 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.12 I2CxBTO Name:  Address:  I2CxBTO 0x029C I2C Bus Time-Out Register(1) Bit 7 TOREC R/W 0 Access Reset 6 TOBY32 R/W 0 5 4 R/W 0 R/W 0 3 2 TOTIME[5:0] R/W R/W 0 0 1 0 R/W 0 R/W 0 Bit 7 – TOREC Time-Out Recovery Selection Value Description 1 A BTO event will reset the I2C module and set BTOIF 0 A BTO event will set BTOIF, but will not reset the I2C module Bit 6 – TOBY32  Time-Out Prescaler Extension Enable(2) Value Description 1 BTO time = TOTIME * TBTOCLK 0 BTO time = TOTIME * TBTOCLK * 32 Bits 5:0 – TOTIME[5:0] Time-Out Time Selection Value Condition Description n TOBY32 = 1 Time-out is TOTIME periods of the prescaled BTO clock (TOTIME = n * TBTOCLK) n TOBY32 = 0 Time-out is TOTIME periods of the prescaled BTO clock multiplied by 32 (TOTIME = n * TBTOCLK * 32) Notes:  1. It is recommended to write this register only when the module is Idle (MMA = 0 or SMA = 0), or when the module is clock stretching (CSTR = 1 or MDR = 1). 2. When TOBY32 is set (TOBY32 = 1) and the LFINTOSC, MFINTOSC, or SOSC is selected as the BTO clock source, the time-out time (TOTIME) will be approximately in milliseconds. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 664 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.13 I2CxBTOC Name:  Address:  I2CxBTOC 0x029F I2C Bus Time-Out Clock Source Selection Bit 7 6 5 4 3 2 Access Reset R/W 0 1 BTOC[2:0] R/W 0 0 R/W 0 Bits 2:0 – BTOC[2:0] Bus Time-Out Clock Source Selection Table 36-5. BTOC Selection 111 110 101 100 011 010 001 000 Reserved Reserved SOSC MFINTOSC (32 kHz) LFINTOSC TMR4_postscaled TMR2_postscaled Reserved © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 665 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.14 [I2CxADB0] Name:  Address:  I2CxADB0 0x028E I2C Address Buffer 0 Register(1) Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 ADB[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – ADB[7:0]  I2C Address Buffer 0 Condition Description 7-bit Client/Multi-Host modes (MODE = 00x or 11x): ADB[7:1]: Received matching 7-bit client address ADB[0]: Received R/W value from 7-bit address 10-bit Client modes (MODE = 01x): ADB[7:0]: Received matching lower eight bits of 10-bit client address 7-bit Host mode (MODE = 100): Unused in this mode 10-bit Host mode (MODE = 101): ADB[7:0]: Eight Least Significant bits of the 10-bit client address Note:  1. This register is read-only except in Host 10-bit Address mode (MODE = 101). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 666 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.15 I2CxADB1 Name:  Address:  I2CxADB1 0x028F I2C Address Buffer 1 Register(1) Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 ADB[7:0] Access Reset R/W 0 R/W 0 R/W 0 Bits 7:0 – ADB[7:0] I2C Address Buffer 1 Condition 7-bit Client modes (MODE = 00x): 10-bit Client modes (MODE = 01x): 7-bit Host mode (MODE = 100): 10-bit Host mode (MODE = 101): 7-bit Multi-Host modes (MODE = 11x): R/W 0 Description Unused in this mode ADB[7:1]: Received matching 10-bit client address high byte ADB[0]: Received R/W value from 10-bit high address byte ADB[7:1]: 7-bit client address ADB[0]: R/W value ADB[7:1]: 10-bit client high address byte ADB[0]: R/W value ADB[7:1]: 7-bit client address ADB[0]: R/W value Note:  1. This register is read-only in 7-bit Client Address modes (MODE = 0xx). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 667 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.16 I2CxADR0 Name:  Address:  I2CxADR0 0x0290 I2C Address 0 Register Bit 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 ADR[7:0] Access Reset R/W 1 R/W 1 R/W 1 R/W 1 Bits 7:0 – ADR[7:0]  I2C Client Address 0 Condition 7-bit Client/Multi-Host modes (MODE = 00x or 11x): 10-bit Client modes (MODE = 01x): © 2020-2021 Microchip Technology Inc. and its subsidiaries Description ADR[7:1]: 7-bit client address ADR[0]: Unused; bit state is ‘don’t care’ ADR[7:0]: Eight Least Significant bits of first 10-bit address Preliminary Datasheet DS40002214E-page 668 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.17 I2CxADR1 Name:  Address:  I2CxADR1 0x0291 I2C Address 1 Register Bit Access Reset 7 6 5 R/W 1 R/W 1 R/W 1 4 ADR[6:0] R/W 1 Bits 7:1 – ADR[6:0]  I2C Client Address 1 Condition 7-bit Client/Multi-Host modes (MODE = 000 or 110): 7-bit Client/Multi-Host modes with Masking (MODE = 011 or 111): 10-bit Client mode (MODE = 010): 10-bit Client mode with Masking (MODE = 011): 3 2 1 0 R/W 1 R/W 1 R/W 1 Description 7-bit client address 1 7-bit client address mask for I2CxADR0 ADR[7:3]: Bit pattern (11110) as defined by the I2C Specification(1) ADR[2:1]: Two Most Significant bits of first 10-bit address ADR[7:3]: Bit pattern (11110) as defined by the I2C Specification(1) ADR[2:1]: Two Most Significant bits of 10-bit address Note:  1. The ‘11110’ bit pattern used in the 10-bit address high byte is defined by the I2C Specification. It is up to the user to define these bits. These bit values are compared to the received address by hardware to determine a match. The bit pattern transmitted by the host must be the same as the client address’s bit pattern used for comparison or a match will not occur. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 669 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.18 I2CxADR2 Name:  Address:  I2CxADR2 0x0292 I2C Address 2 Register Bit 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 ADR[7:0] Access Reset R/W 1 R/W 1 R/W 1 R/W 1 Bits 7:0 – ADR[7:0]  I2C Client Address 2 Condition 7-bit Client/Multi-Host modes (MODE = 000 or 110): 7-bit Client/Multi-Host modes with Masking (MODE = 001 or 111): 10-bit Client mode (MODE = 010): 10-bit Client mode with Masking (MODE = 011): © 2020-2021 Microchip Technology Inc. and its subsidiaries Description ADR[7:1]: 7-bit client address 2 ADR[0]: Unused; bit state is ‘don’t care’ ADR[7:1]: 7-bit client address ADR[0]: Unused; bit state is ‘don’t care’ ADR[7:0]: Eight Least Significant bits of the second 10bit address ADR[7:0]: Eight Least Significant bits of 10-bit address mask Preliminary Datasheet DS40002214E-page 670 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.19 I2CxADR3 Name:  Address:  I2CxADR3 0x0293 I2C Address 3 Register(1) Bit Access Reset 7 6 5 R/W 1 R/W 1 R/W 1 4 ADR[6:0] R/W 1 Bits 7:1 – ADR[6:0]  I2C Client Address 3 Name 7-bit Client/Multi-Host modes (MODE = 000 or 110): 7-bit Client/Multi-Host modes with Masking (MODE = 001 or 111): 10-bit Client mode (MODE = 010): 10-bit Client mode with Masking (MODE = 011): 3 2 1 0 R/W 1 R/W 1 R/W 1 Description 7-bit client address 3 7-bit client address mask for I2CxADR2 ADR[7:3]: Bit pattern (11110) as defined by the I2C Specification(1) ADR[2:1]: Two Most Significant bits of second 10-bit address ADR[7:3]: Bit pattern (11110) as defined by the I2C Specification(1) ADR[2:1]: Two Most Significant bits of 10-bit address mask Note:  1. The ‘11110’ bit pattern used in the 10-bit address high byte is defined by the I2C Specification. It is up to the user to define these bits. These bit values are compared to the received address by hardware to determine a match. The bit pattern transmitted by the host must be the same as the client address’s bit pattern used for comparison or a match will not occur. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 671 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.20 I2CxTXB Name:  Address:  I2CxTXB 0x028B I2C Transmit Buffer Register(1) Bit 7 6 5 4 3 2 1 0 W x W x W x W x TXB[7:0] Access Reset W x W x W x W x Bits 7:0 – TXB[7:0] I2C Transmit Buffer Note:  This register is write-only. Reading this register will return a value of 0x00. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 672 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.5.21 I2CxRXB Name:  Address:  I2CxRXB 0x028A I2C Receive Buffer(1) Bit 7 6 5 4 3 2 1 0 R x R x R x R x RXB[7:0] Access Reset R x R x R x R x Bits 7:0 – RXB[7:0] I2C Receive Buffer Note:  This register is read-only. Writes to this register are ignored. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 673 PIC18F06/16Q41 I2C - Inter-Integrated Circuit Module 36.6 Address 0x00 ... 0x0289 0x028A 0x028B Register Summary - I2C Name Bit Pos. 7 6 5 4 3 2 1 0 Reserved I2C1RXB I2C1TXB 0x028C I2C1CNT 0x028E 0x028F 0x0290 0x0291 0x0292 0x0293 0x0294 0x0295 0x0296 0x0297 0x0298 0x0299 0x029A 0x029B 0x029C 0x029D 0x029E 0x029F I2C1ADB0 I2C1ADB1 I2C1ADR0 I2C1ADR1 I2C1ADR2 I2C1ADR3 I2C1CON0 I2C1CON1 I2C1CON2 I2C1ERR I2C1STAT0 I2C1STAT1 I2C1PIR I2C1PIE I2C1BTO I2C1BAUD I2C1CLK I2C1BTOC 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 EN ACKCNT ACNT BFRE TXWE CNTIF CNTIE TOREC © 2020-2021 Microchip Technology Inc. and its subsidiaries RSEN ACKDT GCEN BTOIF SMA ACKTIF ACKTIE TOBY32 S ACKSTAT FME BCLIF MMA TXBE RXB[7:0] TXB[7:0] CNT[7:0] CNT[15:8] ADB[7:0] ADB[7:0] ADR[7:0] ADR[6:0] ADR[7:0] ADR[6:0] CSTR MDR MODE[2:0] ACKT P RXO TXU CSD ABD SDAHT[1:0] BFRET[1:0] NACKIF BTOIE BLCIE NACKIE R D RXRE CLRBF RXBF WRIF ADRIF PCIF RSCIF SCIF WRIE ADRIE PCIE RSCIE SCIE TOTIME[5:0] BAUD[7:0] CLK[3:0] BTOC[2:0] Preliminary Datasheet DS40002214E-page 674 PIC18F06/16Q41 HLVD - High/Low-Voltage Detect 37. HLVD - High/Low-Voltage Detect The HLVD module can be configured to monitor the device voltage. This is useful in battery monitoring applications. Complete control of the HLVD module is provided through the HLVDCON0 and HLVDCON1 registers. Refer below for a simplified block diagram of the HLVD module. Figure 37-1. HLVD Module Block Diagram VDD SEL Rev. 10-000256B 2/5/2019 EN OUT Trigger/ Interrupt Generation + RDY EN INTH HLVDIF INTL Bandgap Reference Volatge Since the HLVD can be software enabled through the EN bit, setting and clearing the enable bit does not produce a false HLVD event glitch. Each time the HLVD module is enabled, the RDY bit can be used to detect when the module is stable and ready to use. The INTH and INTL bits determine the overall operation of the module. When INTH is set, the module monitors for rises in VDD above the trip point set by the bits. When INTL is set, the module monitors for drops in VDD below the trip point set by the SEL bits. When both the INTH and INTL bits are set, any changes above or below the trip point set by the SEL bits can be monitored. The OUT bit can be read to determine if the voltage is greater than or less than the selected trip point. 37.1 Operation When the HLVD module is enabled, a comparator uses an internally generated voltage reference as the set point. The set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage. The “trip point” voltage is the voltage level at which the device detects a high or low-voltage event, depending on the configuration of the module. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal by setting the HLVDIF bit. The trip point voltage is software programmable using the SEL bits. 37.2 Setup To set up the HLVD module: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 675 PIC18F06/16Q41 HLVD - High/Low-Voltage Detect 1. 2. 3. 4. 5. Select the desired HLVD trip point by writing the value to the SEL bits. Depending on the application to detect high-voltage peaks or low-voltage drops or both, set the INTH or INTL bit appropriately. Enable the HLVD module by setting the EN bit. Clear the HLVD Interrupt Flag (HLVDIF), which may have been set from a previous interrupt. If interrupts are desired, enable the HLVD interrupt by setting the HLVDIE and GIE bits. An interrupt will not be generated until the RDY bit is set. Important:  Before changing any module settings (interrupts and tripping point), first disable the module (EN = 0), make the changes and re-enable the module. This prevents the generation of false HLVD events. 37.3 Current Consumption When the module is enabled, the HLVD comparator and voltage divider are enabled and consume static current. The total current consumption, when enabled, is specified in the “Electrical Specifications” chapter. Depending on the application, the HLVD module does not need to operate constantly. To reduce the current consumption, the module can disabled when not in use. Refer to the “PMD - Peripheral Module Disable” chapter for more details. 37.4 HLVD Start-Up Time If the HLVD or other circuits using the internal voltage reference are disabled to lower the device’s current consumption, the reference voltage circuit will require time to become stable before a Low or High Voltage condition can be reliably detected. This start-up time, TFVRST, is an interval that is independent of device clock speed. It is specified in the “Electrical Specifications” chapter of the device specific data sheet. The HLVD interrupt flag is not enabled until TFVRST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval (see the figures below). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 676 PIC18F06/16Q41 HLVD - High/Low-Voltage Detect Figure 37-2. Low-Voltage Detect Operation (INTL = 1) Rev. 30-000141A 5/26/2017 CASE 1: HLVDIF may not be Set VDD VHLVD HLVDIF EN TFVRST RDY Band Gap Reference Voltage is Stable CASE 2: HLVDIF Cleared in Software VDD VHLVD HLVDIF EN RDY TFVRST Band Gap Reference Voltage is Stable HLVDIF Cleared in Software HLVDIF Cleared in Software, HLVDIF Remains Set since HLVD Condition still Exists © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 677 PIC18F06/16Q41 HLVD - High/Low-Voltage Detect Figure 37-3. High-Voltage Detect Operation (INTH = 1) Rev. 30-000142A 5/26/2017 CASE 1: HLVDIF may not be Set VHLVD VDD HLVDIF EN TIRVST RDY HLVDIF Cleared in Software Band Gap Reference Voltage is Stable CASE 2: VHLVD VDD HLVDIF EN TIRVST RDY Band Gap Reference Voltage is Stable HLVDIF Cleared in Software HLVDIF Cleared in Software, HLVDIF Remains Set since HLVD Condition still Exists 37.5 Applications In many applications, it is desirable to detect a drop below, or rise above, a particular voltage threshold. For example, the HLVD module can be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a High-Voltage Detect from, for example, 3.3V to 5V (the voltage on USB) and vice versa for a detach. This feature can save a design a few extra components and an attach signal (input pin). For general battery applications, the figure below shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage, VA, the HLVD logic generates an interrupt at time, TA. The interrupt can cause the execution of an Interrupt Service Routine (ISR), which would allow the application to perform “housekeeping tasks” and a controlled shutdown before the device voltage exits the valid operating range at TB. This would give the application a time window, represented by the difference between TA and TB, to safely exit. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 678 PIC18F06/16Q41 HLVD - High/Low-Voltage Detect Figure 37-4. Typical Low-Voltage Detect Application Rev. 30-000143A 5/26/2017 Voltage VA VB Time TA TB Legend: VA = HLVD trip point VB = Minimum valid device operating voltage 37.6 Operation During Sleep When enabled, the HLVD circuitry continues to operate during Sleep. When the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake up from Sleep. If interrupts are enabled, the device will execute code from the interrupt vector. If interrupts are disabled, the device will continue execution from the next instruction after SLEEP. 37.7 Operation During Idle and Doze Modes The performance of the module is independent of the Idle and Doze modes. The module will generate the events based on the trip points. The response to these events will depend on the Doze and Idle mode settings. 37.8 Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off. User firmware has to configure the module again. 37.9 Register Definitions: HLVD Control Long bit name prefixes for the HLVD peripheral is shown in the following table. Refer to the “Long Bit Names” section in the “Register and Bits Naming Conventions” chapter for more information. Table 37-1. HLVD Long Bit Name Prefixes Peripheral Bit Name Prefix HLVD HLVD © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 679 PIC18F06/16Q41 HLVD - High/Low-Voltage Detect 37.9.1 HLVDCON0 Name:  Address:  HLVDCON0 0x04A High/Low-Voltage Detect Control Register 0 Bit Access Reset 7 EN R/W 0 6 5 OUT R x 4 RDY R x 3 2 1 INTH R/W 0 0 INTL R/W 0 Bit 7 – EN High/Low-voltage Detect Power Enable Value Description 1 Enables the HLVD module 0 Disables the HLVD module Bit 5 – OUT HLVD Comparator Output Value Description 1 Voltage < selected detection limit (SEL) 0 Voltage > selected detection limit (SEL) Bit 4 – RDY Band Gap Reference Voltages Stable Status Flag Value Description 1 Indicates HLVD Module is ready and output is stable 0 Indicates HLVD Module is not ready Bit 1 – INTH HLVD Positive going (High Voltage) Interrupt Enable Value Description 1 HLVDIF will be set when voltage ≥ selected detection limit (SEL) 0 HLVDIF will not be set Bit 0 – INTL HLVD Negative going (Low Voltage) Interrupt Enable Value Description 1 HLVDIF will be set when voltage ≤ selected detection limit (SEL) 0 HLVDIF will not be set © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 680 PIC18F06/16Q41 HLVD - High/Low-Voltage Detect 37.9.2 HLVDCON1 Name:  Address:  HLVDCON1 0x04B Low-Voltage Detect Control Register 1 Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 SEL[3:0] Access Reset R/W 0 R/W 0 Bits 3:0 – SEL[3:0] High/Low-Voltage Detection Limit Selection Table 37-2. HLVD Detection Limits SEL Detection Limit 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Reserved 4.63V 4.32V 4.12V 3.91V 3.71V 3.60V 3.40V 3.09V 2.88V 2.78V 2.57V 2.47V 2.26V 2.06V 1.85V Reset States: POR/BOR = 0000 All other Resets = uuuu © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 681 PIC18F06/16Q41 HLVD - High/Low-Voltage Detect 37.10 Address 0x00 ... 0x49 0x4A 0x4B Register Summary - HLVD Name Bit Pos. 7 7:0 7:0 EN 6 5 4 OUT RDY 3 2 1 0 INTH INTL Reserved HLVDCON0 HLVDCON1 © 2020-2021 Microchip Technology Inc. and its subsidiaries SEL[3:0] Preliminary Datasheet DS40002214E-page 682 PIC18F06/16Q41 FVR - Fixed Voltage Reference 38. FVR - Fixed Voltage Reference The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to analog peripherals such as those listed below. • • • • ADC input channel ADC positive reference Comparator input Digital-to-Analog Converter (DAC) The FVR can be enabled by setting the EN bit to ‘1’. Note:  Fixed Voltage Reference output cannot exceed VDD. 38.1 Independent Gain Amplifiers The output of the FVR is routed through two independent programmable gain amplifiers. Each amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels. The ADFVR bits are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Refer to the “ADCC - Analog-to-Digital Converter with Computation Module” chapter for additional information. The CDAFVR bits are used to enable and configure the gain amplifier settings for the reference supplied to the DAC and comparator modules. Refer to the “DAC - Digital-to-Analog Converter Module” and “CMP - Comparator Module” chapters for additional information. Refer to the figure below for the block diagram of the FVR module. Figure 38-1. Fixed Voltage Reference Block Diagram ADFVR To ADC module as reference and input channel 1x 2x 4x FVR Buffer 1 CDAFVR To DAC and Comparator modules, To ADC module as input channel only 1x 2x 4x FVR Buffer 2 EN Any peripheral requiring Fixed Reference 38.2 + _ RDY FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the RDY bit will be set. 38.3 Register Definitions: FVR Long bit name prefixes for the FVR peripherals are shown in the following table. Refer to the “Long Bit Names” section in the “Register and Bits Naming Conventions” chapter for more information. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 683 PIC18F06/16Q41 FVR - Fixed Voltage Reference Table 38-1. FVR Bit Name Prefixes Peripheral Bit Name Prefix FVR FVR © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 684 PIC18F06/16Q41 FVR - Fixed Voltage Reference 38.3.1 FVRCON Name:  Address:  FVRCON 0x3D7 FVR Control Register Important:  This register is shared between the Fixed Voltage Reference (FVR) module and the temperature indicator module. Bit Access Reset 7 EN R/W 0 6 RDY R q 5 TSEN R/W 0 4 TSRNG R/W 0 3 2 CDAFVR[1:0] R/W R/W 0 0 1 0 ADFVR[1:0] R/W 0 R/W 0 Bit 7 – EN Fixed Voltage Reference Enable Value Description 1 Enables module 0 Disables module Bit 6 – RDY Fixed Voltage Reference Ready Flag Value Description 1 Fixed Voltage Reference output is ready for use 0 Fixed Voltage Reference output is not ready for use or not enabled Bit 5 – TSEN Temperature Indicator Enable Value Description 1 Temperature Indicator is enabled 0 Temperature Indicator is disabled Bit 4 – TSRNG Temperature Indicator Range Selection Value Description 1 VOUT = 3VT (High Range) 0 VOUT = 2VT (Low Range) Bits 3:2 – CDAFVR[1:0]  FVR Buffer 2 Gain Selection(1) Value Description 11 FVR Buffer 2 Gain is 4x, (4.096V)(3) 10 FVR Buffer 2 Gain is 2x, (2.048V)(3) 01 FVR Buffer 2 Gain is 1x, (1.024V) 00 FVR Buffer 2 is OFF Bits 1:0 – ADFVR[1:0]  FVR Buffer 1 Gain Selection(2) Value Description 11 FVR Buffer 1 Gain is 4x, (4.096V)(3) 10 FVR Buffer 1 Gain is 2x, (2.048V)(3) 01 FVR Buffer 1 Gain is 1x, (1.024V) 00 FVR Buffer 1 is OFF Notes:  1. This output goes to the DAC and comparator modules, and to the ADC module as an input channel only. 2. This output goes to the ADC module as a reference and an input channel. 3. Fixed Voltage Reference output cannot exceed VDD. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 685 PIC18F06/16Q41 FVR - Fixed Voltage Reference 38.4 Address 0x00 ... 0x03D6 0x03D7 Register Summary - FVR Name Bit Pos. 7 6 5 4 7:0 EN RDY TSEN TSRNG 3 2 1 0 Reserved FVRCON © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet CDAFVR[1:0] ADFVR[1:0] DS40002214E-page 686 PIC18F06/16Q41 Temperature Indicator Module 39. Temperature Indicator Module This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The temperature indicator module provides a temperature-dependent voltage that can be measured by the internal Analog-to-Digital Converter. The circuit’s range of operating temperature falls between -40℃ and +125℃. The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A one-point calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. 39.1 Module Operation The temperature indicator module consists of a temperature-sensing circuit that provides a voltage to the device ADC. The analog voltage output varies inversely to the device temperature. The output of the temperature indicator is referred to as VMEAS. The following figure shows a simplified block diagram of the temperature indicator module. Figure 39-1. Temperature Indicator Module Block Diagram VDD TSRNG TSEN Temperature Indicator  Module Rev. 10-000069D 11/13/2017 VMEAS To ADC GND The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is reserved for the temperature circuit output. Refer to the “ADCC - Analog-to-Digital Converter with Computation Module” chapter for more details. The ON/OFF bit for the module is located in the FVRCON register. The circuit is enabled by setting the TSEN bit. When the module is disabled, the circuit draws no current. Refer to the “FVR - Fixed Reference Voltage” chapter for more details. 39.1.1 Temperature Indicator Range The temperature indicator circuit operates in either high or low range. The high range, selected by setting the TSRNG bit, provides a wider output voltage. This provides more resolution over the temperature range. High range requires a higher bias voltage to operate and thus, a higher VDD is needed. The low range is selected by clearing the TSRNG bit. The low range generates a lower sensor voltage and thus, a lower VDD voltage is needed to operate the circuit. The output voltage of the sensor is the highest value at -40℃ and the lowest value at +125℃. • High Range: The high range is used in applications with the reference for the ADC, VREF = 2.048V. This range may not be suitable for battery-powered applications. • Low Range: This mode is useful in applications in which the VDD is too low for high-range operation. The VDD in this mode can be as low as 1.8V. However, VDD must be at least 0.5V higher than the maximum sensor voltage depending on the expected low operating temperature. Important:  The standard parameters for the Temperature Sensor for both high range and low range are stored in the DIA table. Refer to the DIA table in the “Memory Organization” chapter for more details. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 687 PIC18F06/16Q41 Temperature Indicator Module 39.1.2 Minimum Operating VDD When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within the device specifications. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. The following table shows the recommended minimum VDD vs. Range setting. Table 39-1. Recommended VDD vs. Range 39.2 Min. VDD, TSRNG = 1 (High Range) Min. VDD, TSRNG = 0 (Low Range) ≥ 2.5 ≥ 1.8 Temperature Calculation This section describes the steps involved in calculating the die temperature, TMEAS: 1. Obtain the ADC count value of the measured analog voltage: The analog output voltage, VMEAS, is converted to a digital count value by the Analog-to-Digital Converter (ADC) and is referred to as ADCMEAS. 2. Obtain the Gain value from the DIA table. This parameter is TSLR1 for the low range setting or TSHR1 for the high range setting of the temperature indicator module. Refer to the DIA table in the “Memory Organization” chapter for more details. 3. Obtain the Offset value from the DIA table. This parameter is TSLR3 for the low range setting or TSHR3 for the high range setting of the temperature indicator module. Refer to the DIA table in the “Memory Organization” chapter for more details. The following equation provides an estimate for the die temperature based on the above parameters: Equation 39-1. Sensor Temperature (in ℃) TMEAS = ADCMEAS × Gain + Offset 256 10 Where: ADCMEAS = ADC reading at temperature being estimated Gain = Gain value stored in the DIA table Offset = Offset value stored in the DIA table Note:  It is recommended to take the average of ten measurements of ADCMEAS to reduce noise and improve accuracy. Example 39-1. Temperature Calculation (C) // // // // offset is int16_t data type gain is int16_t data type ADC_MEAS is uint16_t data type Temp_in_C is int24_t data type ADC_MEAS = ((ADRESH ADPREV no math functions Vref = Vdd & Vss select RA0/AN0 software controlled acquisition time default S&H capacitance no repeat measurements auto-conversion disabled ADC On, right-justified, ADCRC clock ; ; Set RA0 to input ; ; Set RA0 to analog ; Acquisiton delay ; ; ; ; ; ; ; ; Start conversion Is conversion done? No, test again Read upper byte store in GPR space Read lower byte Store in GPR space Example 40-2. ADC Conversion (C) /*This code block configures the ADC for polling, VDD and VSS references, ADCRC oscillator and AN0 input. Conversion start & polling for completion are included. */ void main() { //System Initialize initializeSystem(); //Setup ADC ADCON0bits.FM = 1; //right justify ADCON0bits.CS = 1; //ADCRC Clock ADPCH = 0x00; //RA0 is Analog channel TRISAbits.TRISA0 = 1; //Set RA0 to input ANSELAbits.ANSELA0 = 1; //Set RA0 to analog ADACQ = 32; //Set acquisition time ADCON0bits.ON = 1; //Turn ADC On } 40.3 while (1) { ADCON0bits.GO = 1; while (ADCON0bits.GO); resultHigh = ADRESH; resultLow = ADRESL; } //Start conversion //Wait for conversion done //Read result //Read result ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 40-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The maximum recommended impedance for analog sources is 10 kΩ. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an ADC acquisition time must be completed before the conversion can be started. To calculate the minimum acquisition time, Equation 40-1 may be used. This equation assumes an error of 1/2 LSb. The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 699 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... Equation 40-1. Acquisition Time Example Assumptions: Temperature = 50°C; External impedance = 10 kΩ; VDD = 5.0V TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient TACQ = TAMP + TC + TCOFF TACQ = 2 μs + TC + Temperature − 25°C 0.05 μs/°C The value for TC can be approximated with the following equations: VAPPLIED 1 − 1 n+1 2 −TC − 1 = VCHOLD ; [1] VCHOLD charged to within ½ LSb VAPPLIED 1 − e RC = VCHOLD ; [2] VCHOLD charge response to VAPPLIED VAPPLIED 1 − e RC = VAPPLIED 1 − −TC Note: Where n = ADC resolution in bits 1 n+1 2 − 1 ; Combining [1] and [2] Solving for TC: TC = − CHOLD RIC + RSS + RS ln 1/8191 TC = − 28 pF 1 kΩ + 7 kΩ + 10 kΩ ln 0.0001221 TC = 4.54 μs Therefore: TACQ = 2 μs + 4.54 μs + TACQ = 7.79 μs 50°C − 25°C 0.05 μs/°C Important:  • The reference voltage (VREF) has no effect on the equation, since it cancels itself out. • The charge holding capacitor (CHOLD) is not discharged after each conversion. • The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 700 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... Figure 40-4. Analog Input Model Sampling Switch VDD Analog Input pin RS CPIN 5 pF VA Legend: CPIN ILE AKAG E RIC RS VA VT SS RSS CHOLD VT 0.6V VT 0.6V RIC 1K SS RSS ILEAKAGE(1) CHOLD = 28 PF VSS Ref- = Input Capacitance = Leakage Current at the pin due to various junctions = Interconnect Resistance = Source Impedance = Analog Voltage = Diode Forward Voltage = Sampling Switch = Resistance of the Sampling Switch = Sample/Hold Capacitance Sampling Switch (K ) 11 10 9 8 7 6 5 RSS 2 3 4 5 6 VDD (V) Note: 1. Refer to the Electrical Specifications chapter. Figure 40-5. ADC Transfer Function Rev. 30-000115B 6/27/2017 Full-Scale Range FFFh FFEh ADC Output Code FFDh FFCh FFBh 03h 02h 01h 00h Analog Input Voltage 0.5 LSB REF- 40.4 Zero-Scale Transition 1.5 LSB Full-Scale Transition REF+ ADC Charge Pump The ADC module has a dedicated charge pump which can be controlled through the ADCP register. The primary purpose of the charge pump is to supply a constant voltage to the gates of transistor devices in the Analog-to-Digital Converter, signal and reference input pass-gates, to prevent degradation of transistor performance at low operating voltage. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 701 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... The charge pump can be enabled by setting the CPON bit. Once enabled, the pump will undergo a start-up time to stabilize the charge pump output. Once the output stabilizes and is ready for use, the CPRDY bit will be set. 40.5 Computation Operation The ADC module hardware is equipped with post-conversion computation features. These features provide postprocessing functions such as digital filtering/averaging and threshold comparison. Based on computation results, the module can be configured to take additional samples or stop conversions, and an interrupt may be asserted. Figure 40-6. Computational Features Simplified Block Diagram CALC TMD ADRES CRS Average/ Filter ADFLTR 1 0 Error Calculation ADERR Threshold Logic Set Interrupt Flag ADPREV ADSTPT ADUTH ADLTH PSIS The operation of the ADC computational features is controlled by the MD bits. The module can be operated in one of five modes: • • • • • Basic: This is a Legacy mode. In this mode, ADC conversion occurs on single (DSEN = 0) or double (DSEN = 1) samples. ADIF is set after each conversion is complete. ADTIF is set according to the Calculation mode. Accumulate: With each trigger, the ADC conversion result is added to the accumulator and CNT increments. ADIF is set after each conversion. ADTIF is set according to the Calculation mode. Average: With each trigger, the ADC conversion result is added to the accumulator. When the RPT number of samples have been accumulated, a threshold test is performed. Upon the next trigger, the accumulator is cleared. For the subsequent tests, additional ADRPT samples are required to be accumulated. Burst Average: At the trigger, the accumulator is cleared. The ADC conversion results are then collected repetitively until ADRPT samples are accumulated and finally the threshold is tested. Low-Pass Filter (LPF): With each trigger, the ADC conversion result is sent through a filter. When ADRPT samples have occurred, a threshold test is performed. Every trigger after that the ADC conversion result is sent through the filter and another threshold test is performed. The five modes are summarized in the following table. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 702 Table 40-2. Computation Modes © 2020-2021 Microchip Technology Inc. and its subsidiaries Mode rotatethispage90 Basic MD 0 Accumulate Average Burst Average 1 2 3 Value after Cycle(1) Completion Threshold Operations Value at ADTIF Interrupt ADACC and CNT ADACC ADCNT Retrigger Threshold Test Interrupt AOV ADFLTR ADCNT ACLR = 1 Unchanged Unchanged No Every Sample If threshold = true N/A N/A count ACLR = 1 S1 + ADACC or (S2 - S1) + ADACC If (ADCNT = 0xFF): ADCNT, otherwise: ADCNT+1 No Every Sample If threshold = true ADACC Overflow ADACC/2CRS count If (ADCNT = 0xFF): ADCNT, otherwise: ADCNT +1 No If ADCNT ≥ ADRPT If threshold = true ADACC Overflow ADACC/2CRS count Each repetition: same as Average End with ADCNT = ADRPT Repeat while ADCNT < ADRPT If ADCNT ≥ ADRPT If threshold = true ADACC Overflow ADACC/2CRS ADRPT If (ADCNT = 0xFF): ADCNT, otherwise: ADCNT +1 No If ADCNT ≥ ADRPT If threshold = true ADACC Overflow ACLR = 1 or S1 + ADACC or ADCNT ≥ ADRPT at GO (S2 -S1) + ADACC set or retrigger Each repetition: ACLR = 1 or at same as Average GO set or End with sum of all retrigger samples S1 + ADACCADACC/ ACLR = 1 2CRS or (S2 - S1) + ADACC-ADACC/ 2CRS ADACC/2CRS (Filtered Value) Notes:  1. When DSEN = 0, Cycle means one conversion. When DSEN = 1, Cycle means two conversions. 2. S1 and S2 are abbreviations for Sample 1 and Sample 2, respectively. When DSEN = 0, S1 = ADRES; When DSEN = 1, S1 = ADPREV and S2 = ADRES. count PIC18F06/16Q41 DS40002214E-page 703 ADCC - Analog-to-Digital Converter with Co... Preliminary Datasheet Low-pass Filter 4 Register Clear Event PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.5.1 Digital Filter/Average The digital filter/average module consists of an accumulator with data feedback options, and control logic to determine when threshold tests need to be applied. The accumulator can be accessed through the ADACC register. Upon each trigger event (the GO bit set or external event trigger), the ADC conversion result is added to or subtracted from the accumulator. If the accumulated value exceeds 2(accumulator_width)-1 = 218-1 = 262143, the AOV overflow bit is set. The number of samples to be accumulated is determined by the ADRPT (ADC Repeat Setting) register. Each time a sample is added to the accumulator, the ADCNT register is incremented. Once ADRPT samples are accumulated (ADCNT = ADRPT), the accumulator may be cleared automatically depending on ADC Operation mode. An accumulator clear command can be issued in software by setting the ACLR bit. Setting the ACLR bit will also clear the AOV (Accumulator Overflow) bit, as well as the ADCNT register. The ACLR bit is cleared by the hardware when accumulator clearing action is complete. Important:  When ADC is operating from ADCRC, up to five ADCRC clock cycles are required to execute the ADACC clearing operation. The CRS bits control the data shift on the accumulator result, which effectively divides the value in the accumulator registers. For the Accumulate mode of the digital filter, the shift provides a simple scaling operation. For the Average/ Burst Average mode, the calculated average is only accurate when the number of samples agrees with the number of bits shifted. For the Low-Pass Filter mode, the shift is an integral part of the filter, and determines the cutoff frequency of the filter. Table 40-3 shows the -3 dB cutoff frequency in ωT (radians) and the highest signal attenuation obtained by this filter at Nyquist frequency (ωT = π). Table 40-3. Low-Pass Filter -3 dB Cutoff Frequency 40.5.2 CRS ωT (radians) @ -3 dB Frequency dB @ FNyquist=1/(2T) 1 0.72 -9.5 2 0.284 -16.9 3 0.134 -23.5 4 0.065 -29.8 5 0.032 -36.0 6 0.016 -42.0 Basic Mode Basic mode (MD = ‘b000) disables all additional computation features. In this mode, no accumulation occurs but threshold error comparison is performed. Double sampling, Continuous mode, and all CVD features are still available, but no digital filter/average calculations are performed. 40.5.3 Accumulate Mode In Accumulate mode (MD = ‘b001), after every conversion, the ADC result is added to the ADACC register. The ADACC register is right-shifted by the value of the CRS bits. This right-shifted value is copied into the ADFLTR register. The Formatting mode does not affect the right-justification of the ADACC or ADFLTR values. Upon each sample, ADCNT is incremented, counting the number of samples accumulated. After each sample and accumulation, the ADFLTR value has a threshold comparison performed on it (see the Threshold Comparison section) and the ADTIF interrupt may trigger. 40.5.4 Average Mode In Average mode (MD = ‘b010), the ADACC registers accumulate with each ADC sample, much as in Accumulate mode, and the ADCNT register increments with each sample. The ADFLTR register is also updated with the rightshifted value of the ADACC register. The value of the CRS bits governs the number of right shifts. However, in Average mode, the threshold comparison is performed upon ADCNT being greater than or equal to a user-defined © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 704 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... ADRPT value. In this mode, when ADRPT = 2^CRS, the final accumulated value will be divided by the number of samples, allowing for a threshold comparison operation on the average of all gathered samples. 40.5.5 Burst Average Mode The Burst Average mode (MD = ‘b011) acts the same as the Average mode in most respects. The one way it differs is that it continuously retriggers ADC sampling until the CNT value is equal to ADRPT, even if Continuous Sampling mode (see the Continuous Sampling Mode section) is not enabled. This provides a threshold comparison on the average of a short burst of ADC samples. 40.5.6 Low-Pass Filter Mode The Low-Pass Filter mode (MD = ‘b100) acts similarly to the Average mode in how it handles samples (accumulates samples until the ADCNT value is greater than or equal to RPT, then triggers a threshold comparison), but instead of a simple average, it performs a low-pass filter operation on all of the samples, reducing the effect of high-frequency noise on the total, then performs a threshold comparison on the results. In this mode, the CRS bits determine the cutoff frequency of the low-pass filter (as demonstrated by Digital Filter/Average). Refer to the Computation Operation section for a more detailed description of the mathematical operation. For more information about Low-Pass Filter mode, refer to the following Microchip application note, available in the corporate website (www.microchip.com): • AN2749, “PIC18 12-bit ADCC in Low-Pass Filter Mode” 40.5.7 Threshold Comparison At the end of each computation: • • • The conversion results are captured at the end-of-conversion. The error (ADERR) is calculated based on a difference calculation which is selected by the CALC bits. The value can be one of the following calculations: – The first derivative of single measurements – The CVD result when double sampling is enabled – The current result vs. setpoint value in the ADSTPT register – The current result vs. the filtered/average result – The first derivative of the filtered/average value – Filtered/average value vs. setpoint value in the ADSTPT register The result of the calculation (ADERR) is compared to the upper and lower thresholds, ADUTH and ADLTH registers, to set the UTHR and LTHR flag bits. The threshold logic is selected by the TMD bits. The threshold trigger option can be one of the following: – Never interrupt – Error is less than lower threshold – Error is greater than or equal to lower threshold – Error is between thresholds (inclusive) – Error is outside of thresholds – Error is less than or equal to upper threshold – Error is greater than upper threshold – Always interrupt regardless of threshold test results – If the Threshold condition is met, the threshold interrupt flag ADTIF is set. Important:  • The threshold tests are signed operations. • If the AOV bit is set, a threshold interrupt is signaled. It is good practice for threshold interrupt handlers to verify the validity of the threshold by checking AOV bit. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 705 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.5.8 Repetition and Sampling Options 40.5.8.1 Continuous Sampling Mode Setting the CONT bit automatically retriggers a new conversion cycle after updating the ADACC register. That means the GO bit remains set to generate automatic retriggering. If SOI = 1, a Threshold Interrupt condition will clear GO bit and the conversion will stop. 40.5.8.2 Double Sample Conversion Double sampling is enabled by setting the DSEN bit. When this bit is set, two conversions are required before the module calculates the threshold error. Each conversion must be triggered separately when CONT = 0 but will repeat automatically form a single trigger when CONT = 1. The first conversion will set the MATH bit and update ADACC, but will not calculate ADERR or trigger ADTIF. When the second conversion completes, the first value is transferred to ADPREV (depending on the setting of PSIS) and the value of the second conversion is placed into ADRES. Only upon the completion of the second conversion is ADERR calculated and ADTIF triggered (depending on the value of CALC). 40.6 Capacitive Voltage Divider (CVD) Features The ADC module contains several features that allow the user to perform a relative capacitance measurement on any ADC channel using the internal ADC Sample-and-Hold capacitance as a reference. This relative capacitance measurement can be used to implement capacitive touch or proximity sensing applications. The following figure shows the basic block diagram of the CVD portion of the ADC module. Figure 40-7. Hardware Capacitive Voltage Divider Block Diagram VDD VDD PPOL & Precharge PPOL & Precharge Precharge ANx ADC Capacitive Sensor Node PPOL & Precharge PPOL & Precharge ANx Multiplexer ADCAP Additional Sample Capacitors This is an example on how to configure ADC for CVD operation: 1. Configure Port: a. Disable pin output driver (refer to the TRISx register) b. Configure pin as analog (refer to the ANSELx register) 2. Configure the ADC module: a. Select ADC conversion clock b. Configure voltage reference c. Select ADC input channel d. Configure precharge (ADPRE) and acquisition (ADACQ) time period e. Select precharge polarity (PPOL) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 706 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 3. 4. 5. 6. f. Enable Double Sampling (DSEN) g. Turn on ADC module Configure ADC interrupt (optional): a. Clear ADC interrupt flag b. Enable ADC interrupt c. Enable global interrupt (GIE bit)(1) Start double sample conversion by setting the GO bit. Wait for ADC conversion to complete by one of the following: a. Polling the GO bit b. Waiting for the ADC interrupt (if interrupt is enabled) Second ADC conversion depends on the state of CONT: a. If CONT = 1, both conversion will repeat automatically from a single trigger b. 7. 8. If CONT = 0, each conversion must be triggered separately The ADERR register contains the CVD result. Clear the ADC interrupt flag (if interrupt is enabled). Note:  1. With global interrupts disabled (GIE = 0), the device will wake from Sleep but will not enter an Interrupt Service Routine. 40.6.1 CVD Operation A CVD operation begins with the ADC’s internal Sample-and-Hold capacitor (CHOLD) being disconnected from the path which connects it to the external capacitive sensor node. While disconnected, CHOLD is precharged to VDD or discharged to VSS. The sensor node is either discharged or charged to VSS or VDD, respectively to the opposite level of CHOLD. When the precharge phase is complete, the VDD/VSS bias paths for the two nodes are disconnected and the paths between CHOLD and the external sensor node is reconnected, at which time the acquisition phase of the CVD operation begins. During acquisition, a capacitive voltage divider is formed between the precharged CHOLD and sensor nodes, which results in a final voltage level setting on CHOLD which is determined by the capacitances and precharge levels of the two nodes. After acquisition, the ADC converts the voltage level on CHOLD. This process is then repeated with the selected precharge levels inverted for both the CHOLD and the sensor nodes. The waveform for two CVD measurements, which is known as differential CVD measurement, is shown in the following figure. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 707 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... Figure 40-8. Differential CVD Measurement Waveform Precharge Acquire Convert Precharge Acquire Convert VDD Note 1 External Capacitive Sensor ADC Sample and Hold Capacitor Voltage Note 1 VSS Second Sample First Sample Time Note 1: 40.6.2 External Capacitive Sensor voltage during the conversion phase m ay vary as per the configuration of the corresponding pin. Precharge Control The Precharge stage is the period of time that brings the external channel and internal Sample-and-Hold capacitor to known voltage levels. Precharge is enabled by writing a nonzero value to the ADPRE register. This stage is initiated when an ADC conversion begins, either from setting the GO bit, a Special Event Trigger, or a conversion restart from the computation functionality. If the ADPRE register is cleared when an ADC conversion begins, this stage is skipped. During the precharge time, CHOLD is disconnected from the outer portion of the sample path that leads to the external capacitive sensor and is connected to either VDD or VSS, depending on the value of the PPOL bit. At the same time, the PORT pin logic of the selected analog channel is overridden to drive a digital high or low out, to precharge the outer portion of the ADC’s sample path, which includes the external sensor. The output polarity of this override is determined by the PPOL bit such that the external sensor cap is charged opposite of the internal CHOLD cap. The amount of time for precharge is controlled by the ADPRE register. Important:  The external charging overrides the TRIS/LAT/Guard outputs setting of the respective I/O pin. If there is a device attached to this pin, precharge will not be used. 40.6.3 Acquisition Control for CVD (ADPRE > 0) The Acquisition stage allows time for the voltage on the internal Sample-and-Hold capacitor to charge or discharge from the selected analog channel. This acquisition time is controlled by the ADACQ register. The acquisition stage begins when precharge stage ends. At the start of the acquisition stage, the PORT pin logic of the selected analog channel is overridden to turn off the digital high/low output drivers so they do not affect the final result of the charge averaging. Also, the selected ADC © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 708 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... channel is connected to CHOLD. This allows charge averaging to proceed between the precharged channel and the CHOLD capacitor. Important:  When ADPRE > 0 setting ADACQ to ‘0’ will set a maximum acquisition time. When precharge is disabled, setting ADACQ to ‘0’ will disable hardware acquisition time control. 40.6.4 Guard Ring Outputs Figure 40-9 shows a typical guard ring circuit. CGUARD represents the capacitance of the guard ring trace placed on the PCB. The user selects values for RA and RB that will create a voltage profile on CGUARD, which will match the selected acquisition channel. The purpose of the guard ring is to generate a signal in phase with the CVD sensing signal to minimize the effects of the parasitic capacitance on sensing electrodes. It also can be used as a mutual drive for mutual capacitive sensing. For more information about active guard and mutual drive, refer to the following Microchip application note, available on the corporate website (www.microchip.com): • AN1478, “mTouchTM Sensing Solution Acquisition Methods Capacitive Voltage Divider” The ADC has two guard ring drive outputs, ADGRDA and ADGRDB. These outputs are routed through PPS controls to I/O pins. Refer to the “PPS - Peripheral Pin Select Module” chapter for more details. The polarity of these outputs is controlled by the GPOL and IPEN bits. At the start of the first precharge stage, both outputs are set to match the GPOL bit. Once the acquisition stage begins, ADGRDA changes polarity, while ADGRDB remains unchanged. When performing a double sample conversion, setting the IPEN bit causes both guard ring outputs to transition to the opposite polarity of GPOL at the start of the second precharge stage, and ADGRDA toggles again for the second acquisition. For more information on the timing of the guard ring output, refer to Figure 40-10. Figure 40-9. Guard Ring Circuit Rev. 30-000120A 5/16/2017 ADGRDA RA RB CGUARD ADGRDB © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 709 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... Figure 40-10. Differential CVD with Guard Ring Output Waveform Precharge Acquire Convert Precharge Acquire Convert VDD Note 1 External Capacitive Sensor VSS Guard Ring Capacitance Voltage Note 1 Second Sample First Sample Time ADGRDA ADGRDB Note 1: 40.6.5 External Capacitive Sensor voltage during the conversion phase m ay vary as per the configuration of the corresponding pin. Additional Sample-and-Hold Capacitance Additional capacitance can be added in parallel with the internal Sample-and-Hold capacitor (CHOLD) by using the ADCAP register. This register selects a digitally programmable capacitance that is added to the ADC conversion bus, increasing the effective internal capacitance of the Sample-and-Hold capacitor in the ADC module. This is used to improve the match between internal and external capacitance for a better sensing performance. The additional capacitance does not affect analog performance of the ADC because it is not connected during conversion. 40.7 Register Definitions: ADC Control Long bit name prefixes for the ADC peripherals are shown in the following table. Refer to the “Long Bit Names” section of the “Register and Bit Naming Conventions” chapter for more information. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 710 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... Table 40-4. ADC Long Bit Name Prefixes Peripheral Bit Name Prefix ADC AD © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 711 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.1 ADCON0 Name:  Address:  ADCON0 0x3F3 ADC Control Register 0 Bit Access Reset 7 ON R/W 0 6 CONT R/W 0 5 4 CS R/W 0 3 2 FM R/W 0 1 0 GO R/W/HC/HS 0 Bit 7 – ON ADC Enable Value Description 1 ADC is enabled 0 ADC is disabled Bit 6 – CONT ADC Continuous Operation Enable Value Description 1 GO is retriggered upon completion of each conversion trigger until ADTIF is set (if SOI is set) or until GO is cleared (regardless of the value of SOI) 0 ADC is cleared upon completion of each conversion trigger Bit 4 – CS ADC Clock Selection Value Description 1 Clock supplied from ADCRC dedicated oscillator 0 Clock supplied by FOSC, divided according to ADCLK register Bit 2 – FM ADC Results Format/Alignment Selection Value Description 1 ADRES and ADPREV data are right justified 0 ADRES and ADPREV data are left justified, zero-filled Bit 0 – GO  ADC Conversion Status(1,2) Value Description 1 ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is cleared by hardware as determined by the CONT bit 0 ADC conversion completed/not in progress Notes:  1. This bit requires ON bit to be set. 2. If cleared by software while a conversion is in progress, the results of the conversion up to this point will be transferred to ADRES and the state machine will be reset, but the ADIF Interrupt Flag bit will not be set; filter and threshold operations will not be performed. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 712 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.2 ADCON1 Name:  Address:  ADCON1 0x3F4 ADC Control Register 1 Bit 7 PPOL R/W 0 Access Reset 6 IPEN R/W 0 5 GPOL R/W 0 4 3 2 1 0 DSEN R/W 0 Bit 7 – PPOL Precharge Polarity Action During 1st Precharge Stage Value Condition Description x ADPRE = 0 Bit has no effect 1 ADPRE > 0 External analog I/O pin is connected to VDD. 0 ADPRE > 0 Internal AD sampling capacitor (CHOLD) is connected to VSS. External analog I/O pin is connected to VSS. Internal AD sampling capacitor (CHOLD) is connected to VDD. Bit 6 – IPEN A/D Inverted Precharge Enable Value Condition Description x DSEN = 0 Bit has no effect 1 DSEN = 1 The precharge and guard signals in the second conversion cycle are the opposite polarity of the first cycle 0 DSEN = 1 Both conversion cycles use the precharge and guards specified by PPOL and GPOL Bit 5 – GPOL Guard Ring Polarity Selection Value Description 1 ADC guard Ring outputs start as digital high during Precharge stage 0 ADC guard Ring outputs start as digital low during Precharge stage Bit 0 – DSEN Double-Sample Enable Value Description 1 Two conversions are processed as a pair. The selected computation is performed after every second conversion. 0 Selected computation is performed after every conversion © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 713 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.3 ADCON2 Name:  Address:  ADCON2 0x3F5 ADC Control Register 2 Bit 7 PSIS R/W 0 Access Reset 6 R/W 0 5 CRS[2:0] R/W 0 4 R/W 0 3 ACLR R/W/HC 0 2 R/W 0 1 MD[2:0] R/W 0 0 R/W 0 Bit 7 – PSIS ADC Previous Sample Input Select Value Description 1 ADFLTR is transferred to ADPREV at start-of-conversion 0 ADRES is transferred to ADPREV at start-of-conversion Bits 6:4 – CRS[2:0] ADC Accumulated Calculation Right Shift Select Value Condition Description 1 to 6 MD =‘b100 Low-pass filter time constant is 2CRS, filter gain is 1:1(2) 1 to 6 MD =‘b011 to ‘b001 The accumulated value is right-shifted by CRS (divided by 2CRS)(1,2) x MD =‘b000 These bits are ignored Bit 3 – ACLR  A/D Accumulator Clear Command(3) Value Description 1 The ADACC and ADCNT registers and the AOV bit are cleared 0 Clearing action is complete (or not started) Bits 2:0 – MD[2:0]  ADC Operating Mode Selection(4) Value Description 111-101 Reserved 100 Low-Pass Filter mode 011 Burst Average mode 010 Average mode 001 Accumulate mode 000 Basic (Legacy) mode Notes:  1. To correctly calculate an average, the number of samples (set in ADRPT) must be 2CRS. 2. CRS = ‘b111 and ‘b000 are reserved. 3. 4. This bit is cleared by hardware when the accumulator operation is complete; depending on oscillator selections, the delay may be many instructions. See the Computation Operation section for full mode descriptions. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 714 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.4 ADCON3 Name:  Address:  ADCON3 0x3F6 ADC Control Register 3 Bit 7 Access Reset 6 R/W 0 5 CALC[2:0] R/W 0 4 R/W 0 3 SOI R/W/HC 0 2 R/W 0 1 TMD[2:0] R/W 0 0 R/W 0 Bits 6:4 – CALC[2:0] ADC Error Calculation Mode Select CALC 111 110 101 ADERR DSEN = 0 Single-Sample DSEN = 1 CVD Double-Sample Mode Mode(1) Reserved Reserved Reserved Reserved ADFLTR-ADSTPT ADFLTR-ADSTPT 100 ADPREV-ADFLTR ADPREV-ADFLTR 011 010 001 Reserved ADRES-ADFLTR ADRES-ADSTPT Reserved (ADRES-ADPREV)-ADFLTR (ADRES-ADPREV)-ADSTPT 000 ADRES-ADPREV ADRES-ADPREV Application Reserved Reserved Average/filtered value vs. setpoint First derivative of filtered value(3) (negative) Reserved Actual result vs. averaged/filtered value Actual result vs. setpoint First derivative of single measurement(2) Actual CVD result(2) Notes:  1. When DSEN = 1 and PSIS = 0, ADERR is computed only after every second sample. 2. When PSIS = 0. 3. When PSIS = 1. Bit 3 – SOI ADC Stop-on-Interrupt Value Condition Description x CONT = 0 This bit is not used 1 CONT = 1 GO is cleared when the threshold conditions are met, otherwise the conversion is retriggered 0 CONT = 1 GO is not cleared by hardware, must be cleared by software to stop retriggers Bits 2:0 – TMD[2:0] Threshold Interrupt Mode Select Value Description 111 Interrupt regardless of threshold test results 110 Interrupt if ADERR > ADUTH 101 Interrupt if ADERR ≤ ADUTH 100 Interrupt if ADERR < ADLTH or ADERR > ADUTH 011 Interrupt if ADERR > ADLTH and ADERR < ADUTH 010 Interrupt if ADERR ≥ ADLTH 001 Interrupt if ADERR < ADLTH 000 Never interrupt © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 715 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.5 ADSTAT Name:  Address:  ADSTAT 0x3F7 ADC Status Register Bit Access Reset 7 AOV R/C/HS/HC 0 6 UTHR R 0 5 LTHR R 0 4 MATH R/C/HS 0 3 2 R 0 1 STAT[2:0] R 0 0 R 0 Bit 7 – AOV ADC Accumulator Overflow Value Description 1 The ADACC or ADFLTR or ADERR registers have overflowed 0 The ADACC, ADFLTR and ADERR registers have not overflowed Bit 6 – UTHR ADC Module Greater-than Upper Threshold Flag Value Description 1 ADERR > ADUTH 0 ADERR ≤ ADUTH Bit 5 – LTHR ADC Module Less-than Lower Threshold Flag Value Description 1 ADERR < ADLTH 0 ADERR ≥ ADLTH Bit 4 – MATH ADC Module Computation Status ADC Module Computation Status(1) Value Description 1 The ADACC, ADFLTR, ADUTH and ADLTH registers and the AOV bit are updating or have already updated 0 Associated registers/bits have not changed since this bit was last cleared Bits 2:0 – STAT[2:0] ADC Module Cycle Multi-Stage Status Value Description 111 ADC module is in 2nd conversion stage 110 ADC module is in 2nd acquisition stage 101 ADC module is in 2nd precharge stage 100 ADC computation is suspended between 1st and 2nd sample; the computation results are incomplete and awaiting data from the 2nd sample(2,3) 011 ADC module is in 1st conversion stage 010 ADC module is in 1st acquisition stage 001 ADC module is in 1st precharge stage 000 ADC module is not converting Notes:  1. MATH bit cannot be cleared by software while STAT = ‘b100. 2. 3. If ADC clock source is ADCRC, and FOSC < ADCRC, the indicated status may not be valid. STAT = ‘b100 appears between the two triggers when DSEN = 1 and CONT = 0. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 716 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.6 ADCLK Name:  Address:  ADCLK 0x3FA ADC Clock divider Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 CS[5:0] Access Reset R/W 0 R/W 0 R/W 0 Bits 5:0 – CS[5:0] ADC Clock divider Select Value Description n ADC Clock frequency = FOSC/(2*(n+1)) Note:  ADC Clock divider is only available if FOSC is selected as the ADC clock source (CS = 0). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 717 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.7 ADREF Name:  Address:  ADREF 0x3F8 ADC Reference Selection Register Bit 7 6 Access Reset 5 4 NREF R/W 0 3 2 1 0 PREF[1:0] R/W 0 R/W 0 Bit 4 – NREF ADC Negative Voltage Reference Selection Value Description 1 VREF- is connected to external VREF0 VREF- is connected to AVSS Bits 1:0 – PREF[1:0] ADC Positive Voltage Reference Selection Value Description 11 VREF+ is connected to internal Fixed Voltage Reference (FVR) module 10 VREF+ is connected to external VREF+ 01 Reserved 00 VREF+ is connected to VDD © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 718 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.8 ADPCH Name:  Address:  ADPCH 0x3EC ADC Positive Channel Selection Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 PCH[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – PCH[7:0] ADC Positive Input Channel Selection PCH 11111111 - 10010100 10010011 10010010 - 10010001 10010000 10001111 - 10001110 10001101 10001100 - 10000011 10000010 10000001 10000000 01111111 - 01000000 00111111 00111110 00111101 00111100 00111011 00111010 00111001 00111000 - 00011000 00010111 00010110 00010101 00010100 00010011 00010010 00010001 00010000 00001111 00001110 00001101 00001100 00001011 - 00000110 00000101 00000100 00000011 © 2020-2021 Microchip Technology Inc. and its subsidiaries ADC Positive Channel Input Reserved. No channel connected. RC3 (OPA1IN1+)(6) Reserved. No channel connected. RC0 (OPA1IN0+)(5,6) Reserved. No channel connected. RB5 (OPA1IN0+)(4,6) Reserved. No channel connected. RA2 (OPA1IN2+)(6) Reserved. No channel connected. RA0 (OPA1IN3+)(6) Reserved. No channel connected. Fixed Voltage Reference (FVR) Buffer 2(1) Fixed Voltage Reference (FVR) Buffer 1(1) DAC1 output(2) Temperature Indicator(3) VSS (Analog Ground) DAC2 output(2) OPA positive input source Reserved. No channel connected. RC7/ANC7(4) RC6/ANC6(4) RC5/ANC5 RC4/ANC4 RC3/ANC3 RC2/ANC2 RC1/ANC1 RC0/ANC0 RB7/ANB7(4) RB6/ANB6(4) RB5/ANB5(4) RB4/ANB4(4) Reserved. No channel connected. RA5/ANA5 RA4/ANA4 RA3/ANA3 Preliminary Datasheet DS40002214E-page 719 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... ...........continued PCH 00000010 00000001 00000000 ADC Positive Channel Input RA2/ANA2 RA1/ANA1 RA0/ANA0 Notes:  1. Refer to the “Fixed Voltage Reference Module” chapter for more details. 2. Refer to the “Digital-to-Analog Converter Module” chapter for more details. 3. Refer to the “Temperature Indicator Module” chapter for more details. 4. 20-pin devices only. 5. 14-pin devices only. 6. This configuration routes the specified analog channel to the noninverting input of the OPA module (OPAxIN+), and connects the output of the OPA (OPAxOUT) to the input of the ADC for conversion. The OPA module must be configured accordingly to use this mode of operation. Refer to the "OPA - Analog Signal Conditioning" chapter for more details. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 720 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.9 ADPRE Name:  Address:  ADPRE 0x3F1 ADC Precharge Time Control Register Bit 15 14 13 Access Reset Bit 7 6 5 12 11 R/W 0 4 9 8 R/W 0 10 PRE[12:8] R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 PRE[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 12:0 – PRE[12:0] Precharge Time Select PRE 1 1111 1111 1111 1 1111 1111 1110 1 1111 1111 1101 ... 0 0000 0000 0010 0 0000 0000 0001 0 0000 0000 0000 Precharge Time CS = 0 CS = 1 8191 clocks of FOSC 8191 clocks of ADCRC 8190 clocks of FOSC 8190 clocks of ADCRC 8189 clocks of FOSC 8189 clocks of ADCRC ... ... 2 clocks of FOSC 2 clocks of ADCRC 1 clocks of FOSC 1 clocks of ADCRC Not included in the data conversion cycle Notes:  The individual bytes in this multibyte register can be accessed with the following register names: 1. ADPREH: Accesses the high byte ADPRE[12:8]. 2. ADPREL: Accesses the low byte ADPRE[7:0]. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 721 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.10 ADACQ Name:  Address:  ADACQ 0x3EE ADC Acquisition Time Control Register Bit 15 14 13 Access Reset Bit 7 6 5 12 11 R/W 0 4 9 8 R/W 0 10 ACQ[12:8] R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 ACQ[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 12:0 – ACQ[12:0] Acquisition (charge share time) Select ACQ 1 1111 1111 1111 1 1111 1111 1110 1 1111 1111 1101 ... 0 0000 0000 0010 0 0000 0000 0001 0 0000 0000 0000 Acquisition Time CS = 0 CS = 1 8191 clocks of FOSC 8191 clocks of ADCRC 8190 clocks of FOSC 8190 clocks of ADCRC 8189 clocks of FOSC 8189 clocks of ADCRC ... ... 2 clocks of FOSC 2 clocks of ADCRC 1 clocks of FOSC 1 clocks of ADCRC Not included in the data conversion cycle(1) Note:  1. If ADPRE is not equal to ‘0’, then ACQ = 0 means Acquisition Time is 8192 clocks of FOSC or ADCRC. Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • ADACQH: Accesses the high byte ADACQ[12:8] • ADACQL: Accesses the low byte ADACQ[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 722 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.11 ADCAP Name:  Address:  ADCAP 0x3F0 ADC Additional Sample Capacitor Selection Register Bit 7 6 Access Reset 5 4 3 R/W 0 R/W 0 2 CAP[4:0] R/W 0 1 0 R/W 0 R/W 0 Bits 4:0 – CAP[4:0] ADC Additional Sample Capacitor Selection Value Description 1 to 31 Number of pF in the additional capacitance 0 No additional capacitance © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 723 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.12 ADRPT Name:  Address:  ADRPT 0x3E7 ADC Repeat Setting Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 RPT[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – RPT[7:0] ADC Repeat Threshold Determines the number of times the ADC is triggered for a threshold check. When CNT reaches this value, the error threshold is checked. Used when the computation mode is Low-Pass Filter, Burst Average, or Average. See the Computation Operation section for more details. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 724 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.13 ADCNT Name:  Address:  ADCNT 0x3E6 ADC Repeat Counter Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 CNT[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – CNT[7:0] ADC Repeat Count Counts the number of times the ADC is triggered before the threshold is checked. When this value reaches RPT, the threshold is checked. Used when the computation mode is Low-Pass Filter, Burst Average, or Average. See the Computation Operation section for more details. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 725 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.14 ADFLTR Name:  Address:  ADFLTR 0x3E1 ADC Filter Register Bit 15 14 13 12 11 10 9 8 R x R x R x R x 3 2 1 0 R x R x R x R x FLTR[15:8] Access Reset R x R x R x R x Bit 7 6 5 4 FLTR[7:0] Access Reset R x R x R x R x Bits 15:0 – FLTR[15:0] ADC Filter Output - Signed Two’s Complement In Accumulate, Average and Burst Average modes, this is equal to ACC right shifted by the CRS bits. In LPF mode, this is the output of the Low-Pass Filter. Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • ADFLTRH: Accesses the high byte ADFLTR[15:8] • ADFLTRL: Accesses the low byte ADFLTR[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 726 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.15 ADRES Name:  Address:  ADRES 0x3EA ADC Result Register Bit 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 RES[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 RES[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 15:0 – RES[15:0] ADC Sample Result Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • ADRESH: Accesses the high byte ADRES[15:18] • ADRESL: Accesses the low byte ADRES[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 727 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.16 ADPREV Name:  Address:  ADPREV 0x3E8 ADC Previous Result Register Bit 15 14 13 12 11 10 9 8 R 0 R 0 R 0 R 0 3 2 1 0 R 0 R 0 R 0 R 0 PREV[15:8] Access Reset R 0 R 0 R 0 R 0 Bit 7 6 5 4 PREV[7:0] Access Reset R 0 R 0 R 0 R 0 Bits 15:0 – PREV[15:0] Previous ADC Result Value Condition Description n PSIS = 1 n = ADFLTR value at the start of current ADC conversion n PSIS = 0 n = ADRES at the start of current ADC conversion(1) Notes:  1. If PSIS = 0, ADPREV is formatted the same way as ADRES is, depending on the FM bit. 2. The individual bytes in this multibyte register can be accessed with the following register names: – ADPREVH: Accesses ADPREV[15:8] – ADPREVL: Accesses ADPREV[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 728 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.17 ADACC Name:  Address:  ADACC 0x3E3 ADC Accumulator Register(1) See the Computation Operation section for more details. Important:  This register contains signed two’s complement accumulator value and the upper unused bits contain copies of the sign bit. Bit 23 22 21 20 19 18 17 16 ACC[17:16] Access Reset Bit 15 14 13 12 R/W x R/W x 11 10 9 8 R/W x R/W x R/W x R/W x 3 2 1 0 R/W x R/W x R/W x R/W x ACC[15:8] Access Reset Bit R/W x R/W x R/W x R/W x 7 6 5 4 ACC[7:0] Access Reset R/W x R/W x R/W x R/W x Bits 17:0 – ACC[17:0] ADC Accumulator - Signed Two’s Complement Notes:  1. This register can only be written when GO = 0. 2. The individual bytes in this multibyte register can be accessed with the following register names: – ADACCU: Accesses the upper byte ADACC[17:16] – ADACCH: Accesses the high byte ADACC[15:8] – ADACCL: Accesses the low byte ADACC[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 729 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.18 ADSTPT Name:  Address:  ADSTPT 0x3DF ADC Threshold Setpoint Register Depending on CALC, may be used to determine ADERR. Bit 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 STPT[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 STPT[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 15:0 – STPT[15:0] ADC Threshold Setpoint - Signed Two’s Complement Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • ADSTPTH: Accesses the high byte ADSTPT[15:8] • ADSTPTH: Accesses the low byte ADSTPT[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 730 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.19 ADERR Name:  Address:  ADERR 0x3DD ADC Setpoint Error Register ADC Setpoint Error calculation is determined by the CALC bits. Bit 15 14 13 12 11 10 9 8 R x R x R x R x 3 2 1 0 R x R x R x R x ERR[15:8] Access Reset R x R x R x R x Bit 7 6 5 4 ERR[7:0] Access Reset R x R x R x R x Bits 15:0 – ERR[15:0] ADC Setpoint Error - Signed Two’s Complement Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • ADERRH: Accesses the high byte ADERR[15:8] • ADERRL: Accesses the low byte ADERR[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 731 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.20 ADLTH Name:  Address:  ADLTH 0x3D9 ADC Lower Threshold Register ADLTH and ADUTH are compared with ADERR to set the UTHR and LTHR bits. Depending on the setting of TMD, an interrupt may be triggered by the results of this comparison. Bit 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 LTH[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 LTH[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 15:0 – LTH[15:0] ADC Lower Threshold - Signed Two’s Complement Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • ADLTHH: Accesses the high byte ADLTH[15:8] • ADLTHL: Accesses the low byte ADLTH[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 732 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.21 ADUTH Name:  Address:  ADUTH 0x3DB ADC Upper Threshold Register ADLTH and ADUTH are compared with ADERR to set the UTHR and LTHR bits. Depending on the setting of TMD, an interrupt may be triggered by the results of this comparison. Bit 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 UTH[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 UTH[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 15:0 – UTH[15:0] ADC Upper Threshold - Signed Two’s Complement Notes:  The individual bytes in this multibyte register can be accessed with the following register names: • ADUTHH: Accesses the high byte ADUTH[15:8] • ADUTHL: Accesses the low byte ADUTH[7:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 733 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.22 ADACT Name:  Address:  ADACT 0x3F9 ADC Auto Conversion Trigger Source Selection Register Bit 7 6 Access Reset 5 4 3 R/W 0 R/W 0 2 ACT[4:0] R/W 0 1 0 R/W 0 R/W 0 Bits 4:0 – ACT[4:0] Auto-Conversion Trigger Select ACT 11111 - 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 © 2020-2021 Microchip Technology Inc. and its subsidiaries Auto-Conversion Trigger Source Reserved Software write to ADPCH Software read of ADRESH Software read of ADERRH CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT Interrupt-on-change Interrupt Flag CMP2_OUT CMP1_OUT NCO1_OUT PWM3S1P2_OUT PWM3S1P1_OUT PWM2S1P2_OUT PWM2S1P1_OUT PWM1S1P2_OUT PWM1S1P1_OUT CCP1_trigger SMT1_overflow TMR4_postscaled TMR3_overflow TMR2_postscaled TMR1_overflow TMR0_overflow Pin selected by ADACTPPS External Trigger Disabled Preliminary Datasheet DS40002214E-page 734 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.7.23 ADCP Name:  Address:  ADCP 0x3D8 ADC Charge Pump Control Register Bit Access Reset 7 CPON R/W 0 6 5 4 3 2 1 0 CPRDY R 0 Bit 7 – CPON Charge Pump On Control Value Description 1 Charge Pump On when requested by the ADC 0 Charge Pump Off Bit 0 – CPRDY Charge Pump Ready Status Value Description 1 Charge Pump is ready 0 Charge Pump is not ready (or never started) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 735 PIC18F06/16Q41 ADCC - Analog-to-Digital Converter with Co... 40.8 Address 0x00 ... 0x03D7 0x03D8 Register Summary - ADC Name Bit Pos. 7 7:0 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 23:16 7:0 7:0 7:0 15:8 7:0 15:8 7:0 CPON 6 5 4 3 2 1 0 Reserved ADCP 0x03D9 ADLTH 0x03DB ADUTH 0x03DD ADERR 0x03DF ADSTPT 0x03E1 ADFLTR 0x03E3 ADACC 0x03E6 0x03E7 ADCNT ADRPT 0x03E8 ADPREV 0x03EA ADRES 0x03EC 0x03ED ADPCH Reserved 0x03EE ADACQ 0x03F0 ADCAP 0x03F1 ADPRE 0x03F3 0x03F4 0x03F5 0x03F6 0x03F7 0x03F8 0x03F9 0x03FA ADCON0 ADCON1 ADCON2 ADCON3 ADSTAT ADREF ADACT ADCLK 7:0 15:8 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 CPRDY LTH[7:0] LTH[15:8] UTH[7:0] UTH[15:8] ERR[7:0] ERR[15:8] STPT[7:0] STPT[15:8] FLTR[7:0] FLTR[15:8] ACC[7:0] ACC[15:8] ACC[17:16] CNT[7:0] RPT[7:0] PREV[7:0] PREV[15:8] RES[7:0] RES[15:8] PCH[7:0] ACQ[7:0] ACQ[12:8] CAP[4:0] PRE[7:0] ON PPOL PSIS CONT IPEN AOV UTHR © 2020-2021 Microchip Technology Inc. and its subsidiaries PRE[12:8] FM CS GPOL CRS[2:0] CALC[2:0] LTHR ACLR SOI GO DSEN MD[2:0] TMD[2:0] STAT[2:0] PREF[1:0] MATH NREF ACT[4:0] CS[5:0] Preliminary Datasheet DS40002214E-page 736 PIC18F06/16Q41 DAC - Digital-to-Analog Converter Module 41. DAC - Digital-to-Analog Converter Module The Digital-to-Analog Converter (DAC) supplies a variable voltage reference, ratiometric with the input source, with programmable selectable output levels. The positive and negative input references (VREF+ and VREF-) can each be selected from several sources. The output of the DAC (DACx_output) can be selected as a reference voltage to several other peripherals or routed to output pins. The Digital-to-Analog Converter (DAC) is enabled by setting the EN bit. Important:  This family of devices has two DAC modules. The DAC1 module has a buffered output that can be connected to any of the designated DAC output pins. The DAC2 module has no output pins or buffer, and the output is only connected internally to the CMP and OPA modules. Figure 41-1. Digital-to-Analog Converter Block Diagram VSOURCE+ Positive Reference Sources DACxR R R PSS R R 2n Steps 2n to 1 MUX DACx_output To Peripherals EN R DACxOUTn(2) R OEn (1,2) R Negative Reference Sources VSOURCE- NSS Notes: 1. The output enable bits are configured so that they act as a “one-hot” system, meaning only one DAC output can be enabled at a time. 2. DAC2 has no output buffer; the output from DAC2 is only connected internally to the specified peripherals. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 737 PIC18F06/16Q41 DAC - Digital-to-Analog Converter Module 41.1 Output Voltage Selection The DAC has 2n voltage level ranges, where n is the number of bits in DACR. Each level is determined by the DACxR bits. The DAC output voltage can be determined by using Equation 41-1. Equation 41-1. DAC Output Equation DACx_output = 41.2 VREF + − VREF − × DACR + VREF − 2n Ratiometric Output Level The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in the “Electrical Specifications” chapter for each respective device. 41.3 Operation During Sleep When the device wakes from Sleep through an interrupt or a WWDT Time-out Reset, the contents of the DACxCON and DACxDATL registers are not affected. To minimize current consumption in Sleep mode, the voltage reference will be disabled. 41.4 Effects of a Reset A device Reset affects the following: • • • 41.5 The DAC module is disabled The DAC output voltage is removed from the DACxOUTn pin(s) The DACxR bits are cleared Register Definitions: DAC Control Long bit name prefixes for the DAC are shown in the table below. Refer to the “Long Bit Names” section in the “Register and Bit Naming Conventions” chapter for more information. Table 41-1. DAC Long Bit Name Prefixes Peripheral Bit Name Prefix DAC1 DAC1 DAC2 DAC2 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 738 PIC18F06/16Q41 DAC - Digital-to-Analog Converter Module 41.5.1 DACxCON Name:  Address:  DACxCON 0x7F Digital-to-Analog Converter Control Register Bit Access Reset 7 EN R/W 0 6 5 4 3 OE[1:0] R/W 0 2 1 0 NSS R/W 0 PSS[1:0] R/W 0 R/W 0 R/W 0 Bit 7 – EN DAC Enable Value Description 1 DAC is enabled 0 DAC is disabled Bits 5:4 – OE[1:0] DAC Output Enable OE DAC1 11 10 01 00 DACxOUT is disabled DACxOUT is enabled on pin RA2 only DACxOUT is enabled on pin RA0 only DACxOUT is disabled Bits 3:2 – PSS[1:0] DAC Positive Reference Selection PSS DAC Positive Reference 11 10 01 00 Reserved, do not use FVR Buffer 2 VREF+ VDD Bit 0 – NSS DAC Negative Reference Selection NSS DAC Negative Reference 1 0 VREFVSS © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 739 PIC18F06/16Q41 DAC - Digital-to-Analog Converter Module 41.5.2 DACxCON Name:  Address:  DACxCON 0xA2 Important:  This instance of the DAC module has no output pins or buffer; the output of this DAC is only connected internally to be used with the Comparator and OPAMP modules. Digital-to-Analog Converter Control Register Bit Access Reset 7 EN R/W 0 6 5 4 3 2 1 0 NSS R/W 0 PSS[1:0] R/W 0 R/W 0 Bit 7 – EN DAC Enable Value Description 1 DAC is enabled 0 DAC is disabled Bits 3:2 – PSS[1:0] DAC Positive Reference Selection PSS DAC Positive Reference 11 10 01 00 Reserved, do not use FVR Buffer 2 VREF+ VDD Bit 0 – NSS DAC Negative Reference Selection NSS DAC Negative Reference 1 0 VREFVSS © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 740 PIC18F06/16Q41 DAC - Digital-to-Analog Converter Module 41.5.3 DACxDATL Name:  Address:  DACxDATL 0x7D Digital-to-Analog Converter Data Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 DACxR[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – DACxR[7:0] Data Input Bits for DAC Value © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 741 PIC18F06/16Q41 DAC - Digital-to-Analog Converter Module 41.5.4 DACxDATL Name:  Address:  DACxDATL 0xA0 Digital-to-Analog Converter Data Register Bit 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 DACxR[7:0] Access Reset R/W 0 R/W 0 R/W 0 R/W 0 Bits 7:0 – DACxR[7:0] Data Input Bits for DAC Value © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 742 PIC18F06/16Q41 DAC - Digital-to-Analog Converter Module 41.6 Address 0x00 ... 0x7C 0x7D 0x7E 0x7F 0x80 ... 0x9F 0xA0 0xA1 0xA2 Register Summary - DAC Name Bit Pos. 7 6 5 4 3 2 1 0 Reserved DAC1DATL Reserved DAC1CON 7:0 7:0 DAC1R[7:0] EN OE[1:0] PSS[1:0] NSS PSS[1:0] NSS Reserved DAC2DATL Reserved DAC2CON 7:0 7:0 DAC2R[7:0] EN © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 743 PIC18F06/16Q41 OPA - Operational Amplifier 42. OPA - Operational Amplifier The Operational Amplifier (OPA) module features a standard general purpose three-terminal device with programmable gain options, adjustable input offset voltage and hardware override control capabilities. The OPA module has the following features: • • • • • • 5.5 MHz Gain Bandwidth – Dedicated external output (OPAxOUT) – Multiple noninverting input pins available (OPAxIN+) – Multiple inverting input pins available (OPAxIN-) Programmable Gain Options Using Built-in Internal Resistor Ladder Configurable Positive and Negative Source Selections Hardware Controlled Drive with Override Controls – Forced Unity Gain mode – Forced Rail Drive mode Programmable Input Offset Voltage Calibration Internal Connection to the ADC Module – Allows OPA to be used as programmable gain amplifier for the ADC Input Figure 42-1. Operational Amplifier Module Block Diagram GSEL NCH VSS 111 Reserved 110 Reserved 101 Reserved 100 OPAxIN3- (1) 011 (1) 010 OPAxIN1- (1) 001 OPAxIN0- (1) 000 OPAxIN2- Reserved 111 Reserved 110 DAC2_OUT 101 DAC1_OUT 100 Reserved 011 010 00 No Connection 01 VDD 10 11 Reserved 001 No Connection 000 NSS 1 PSS OPAxIN3+ (1) 11 (1) 10 OPAxIN1+ (1) 01 OPAxIN0+ (1) 00 OPAxIN2+ FMS Reserved 111 Reserved 110 DAC2_OUT 101 DAC1_OUT 100 VDD / 2 011 OPAxIN- - OPAxIN+ + 0 UG OPAx OPAxOUT EN 010 001 VSS 000 PCH Note:  1. Refer to the “Pin Allocation Table” for details about OPAxIN- and OPAxIN+ availability per port. 42.1 OPA Module Control The OPA module is enabled by setting the EN bit of the corresponding operational amplifier Configuration register. Once enabled, the OPA module forces the output driver of the output pin (OPAxOUT) into tri-state. Forcing the output © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 744 PIC18F06/16Q41 OPA - Operational Amplifier pin into tri-state prevents contention between the digital PORT driver of the pin and the output of the OPA during operation. The Software Output Control (SOC) bits are used to select the OPA mode of operation when hardware controlled override is not being used (OREN = 0). 42.1.1 Programmable Source Selection The noninverting input source of the OPA module is selected using the PCH bits and can be connected to multiple internal sources or to an external input pin (OPAxIN+). If an external pin is chosen as the noninverting input source, the PSS bits may then be used to select from the available OPA noninverting input pins for the device. The inverting input source of the OPA module is selected using the NCH bits and can be connected to multiple internal sources or to an external input pin (OPAxIN-). If an external pin is chosen as the inverting input source, the NSS bits may then be used to select from the available inverting OPA input pins for the device. 42.1.2 Programmable Gain Options The gain of the OPA module can be controlled either using external components to provide feedback, or internally using a built-in resistor ladder. When using the built-in programmable gain options of the OPA module, the internal resistor ladder must be enabled by setting the RESON bit. Once enabled, the nominal gain of the amplifier can be selected using the GSEL bits. The internal sources to the operational amplifier must be configured based on the OPA mode of operation, when using the built-in programmable gain options. The PCH and NCH bits can be used to connect the internal resistor ladder to the positive or negative input of the operational amplifier, respectively, creating the feedback network needed to control the gain of the circuit. 42.1.3 Unity Gain Mode The OPA module can be configured to operate in Unity Gain mode either in software or hardware, depending on the configuration of the Override Enable (OREN) bit. If the OREN bit has not been set, Unity Gain mode can be enabled in software by setting the Unity Gain Enable (UG) bit. Once Unity Gain mode has been enabled, the output of the OPA will be connected internally to the inverting input and the OPA will operate with unity gain feedback. If hardware-controlled override has been enabled by setting the OREN bit, the OPAxHWC register might be used to configure the OPA mode of operation, depending on the status of the override source. Refer to the Hardware Override Control section for more information. Tip:  Operating the OPA module in Unity Gain mode (software-controlled or hardware-controlled) relinquishes the need for an external inverting input pin (OPAxIN-), since it connects internally to the OPA output, which allows that pin to be used for general purpose I/O. 42.2 Hardware Override Control The OPA mode of operation can be switched core independently, using the hardware override control feature built into the peripheral. Hardware override control is enabled by setting the OREN bit and selecting an override source using the ORS bits. The OPA mode of operation is determined based on the level of the selected override signal. The Hardware Override Control Configuration bits (HWCH and HWCL) are used to select the OPA mode of operation, when the override source is high or low, respectively. The ORPOL bit can be used to invert the hardware controlled override input, meaning that when ORPOL = 1, the HWCH bits will determine the OPA mode of operation when the override source is low, and the HWCL bits will determine the OPA mode of operation when the override source is high. The hardware override control can be used to switch between the following OPA configurations: • • • Basic Operation with User Defined Feedback(1) Unity Gain Mode Rail Drive Mode – Forces the operational amplifier output to be driven to VDD or VSS, depending on the status of the override source and the configured override polarity. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 745 PIC18F06/16Q41 OPA - Operational Amplifier Note:  1. Feedback is based on the configuration of the internal gain options (GSEL) or external components, depending upon peripheral setup. 42.3 Input Offset Voltage Input offset voltage is a measure of the voltage difference between the noninverting and inverting input sources in a closed loop circuit, with the operational amplifier operating in its linear region. The offset voltage will appear as a DC offset in the output equal to the input offset voltage, multiplied by the gain of the circuit. The input offset voltage is also affected by the Common-mode voltage. The OPA module is factory calibrated to minimize the input offset voltage. 42.3.1 Offset Calibration The OPAxOFFSET register can be used to recalibrate or adjust the input offset voltage from the factory calibration. This can be accomplished by using the DAC module or an external constant-voltage source, in conjunction with the ADC module. The OPA input offset voltage can be recalibrated using the following steps: • • • • • Configure the DAC module to be used as a constant voltage reference connected to the noninverting input (OPAxIN+) of the OPA module. – An external constant voltage reference can be used, instead of the DAC, by connecting it to one of the external noninverting input pins. Configure the OPA module to operate in Unity Gain mode by setting the UG bit. – Use the PCH bits to connect the calibration source (either the DAC module or an external voltage reference) to the noninverting input (OPAxIN+) of the OPA. – If using an external voltage reference, the PSS must also be used to select which OPAxIN+ pin will be connected to the noninverting input. Perform an ADC conversion to measure the voltage of the selected calibration source. The value read by the ADC during this conversion will serve as the calibration target. Use the ADC Positive Channel Selection (ADPCH) register to select the OPA output (OPAxOUT), and then measure the output voltage of the OPA module using the ADC. The difference between the measured value of the calibration target and the measured value of the OPA output can be used to determine the value needed to calibrate the OPA input offset voltage using the OPAxOFFSET register. Important:  1. The OPA input offset voltage is factory calibrated, and any data written to the OPAxOFFSET register will adjust the input offset voltage from the factory calibrated value. The factory calibrated input offset voltage will be restored on a Reset event, overwriting any previous data that may have been written to the register. 2. The OPAxOFFSET register stores an unsigned value which can be use to optimize both positive and negative offset voltages. 42.4 OPA Operation with ADC The OPA module provides internal connections directly to the ADC, allowing it to be used for analog signal conditioning before a signal is converted by the ADC. In this mode of operation, the output of the OPA (OPAxOUT) will connect internally to the input of the ADC, and any ADC conversions will be performed on that signal. When using this mode of operation, the ADPCH register of the ADC module may be used to select one of the available noninverting OPA input pins (OPAxIN+) Both the ADC and the OPA module must be configured accordingly to use this mode of operation. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 746 PIC18F06/16Q41 OPA - Operational Amplifier Tip:  1. When using the OPA module with the ADC in this mode of operation, the OPA input pin selection determined using the ADC input channel selection registers will take precedence over the input pin selection using the NSS and PSS bits. 2. Although the output of the OPA (OPAxOUT) is connected internally to the ADC in this mode of operation, the OPAxOUT pin cannot be used as a general purpose I/O at this time. 42.5 Register Definitions: Operational Amplifier Long bit name prefixes for the OPA peripherals are shown in the table below. Refer to the “Long Bit Names” section in the “Register and Bit Naming Conventions” chapter for more information. Table 42-1. Operational Amplifier Long Bit Name Prefixes Peripheral Bit Name Prefix OPA1 OPA1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 747 PIC18F06/16Q41 OPA - Operational Amplifier 42.5.1 OPAxCON0 Name:  Address:  OPAxCON0 0xA3 Operational Amplifier Control Register 0 Bit Access Reset 7 EN R/W 0 6 5 CPON R/W 0 4 3 UG R/W 0 2 1 0 SOC[1:0] R/W 0 R/W 0 Bit 7 – EN Operational Amplifier Enable Value Description 1 Operational amplifier is enabled 0 Operational amplifier is disabled and consumes no active power Bit 5 – CPON Charge Pump On Control Value Description 1 OPA Charge Pump on 0 OPA Charge Pump off (Low Power mode) Bit 3 – UG Operational Amplifier Unity Gain Select Value Description 1 Operational amplifier output is connected to inverting input, OPAxIN- input pins are available for general purpose I/O. 0 Inverting input is connected to designated OPAxIN- pin. Bits 1:0 – SOC[1:0] Software Output Control Value Description 11 Reserved 10 Drive output to VDD 01 Drive output to VSS 00 Basic Operation; Operational amplifier configuration with user-defined or unity-gain feedback © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 748 PIC18F06/16Q41 OPA - Operational Amplifier 42.5.2 OPAxCON1 Name:  Address:  OPAxCON1 0xA4 Operational Amplifier Control Register 1 Bit 7 Access Reset 6 5 GSEL[2:0] R/W 0 R/W 0 4 R/W 0 3 RESON R/W 0 2 R/W 0 1 NSS[2:0] R/W 0 0 R/W 0 Bits 6:4 – GSEL[2:0] Operational Amplifier Gain Selection Table 42-2. Operational Amplifier Internal Resistor Ladder Selections GSEL[2:0] R1 R2 Inverting (R2/R1) Noninverting (1 + R2/R1) 111 1R 110 2R 101 4R 100 6R 011 8R 010 12R 001 14R 000 15R Note:  R = 20 kΩ nominal 15R 14R 12R 10R 8R 4R 2R 1R 15 7 3 5/3 1 1/3 1/7 1/15 16 8 4 8/3 2 4/3 8/7 16/15 Bit 3 – RESON Resistor Ladder Enable Value Description 1 Internal Resistor Ladder is enabled; OPA input is connected to the resistor ladder allowing GSEL to be used to control programmable gain. 0 Internal Resistor Ladder is disabled. External feedback to the OPA is required unless operating in Unity Gain mode. Bits 2:0 – NSS[2:0] Negative Source Selection Value Description 111 110 101 100 011 010 001 000 VSS Reserved Reserved Reserved OPAxIN3OPAxIN2OPAxIN1OPAxIN0- © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 749 PIC18F06/16Q41 OPA - Operational Amplifier 42.5.3 OPAxCON2 Name:  Address:  OPAxCON2 0xA5 Operational Amplifier Control Register 2 Bit Access Reset 7 6 5 NCH[2:0] R/W 0 R/W 0 4 3 2 R/W 0 R/W 0 1 PCH[2:0] R/W 0 0 R/W 0 Bits 6:4 – NCH[2:0] Operational Amplifier Inverting Input Channel Selection Value Description 111 110 101 100 011 010 001 000 Reserved Reserved DAC2_OUT DAC1_OUT Reserved OPAxIN- (NSS) Internal Resistor Ladder (GSEL) No Connection Bits 2:0 – PCH[2:0] Operational Amplifier Noninverting Input Channel Selection Value Description 111 110 101 100 011 010 001 000 Reserved Reserved DAC2_OUT DAC1_OUT VDD/2 OPAxIN+ (PSS) Internal Resistor Ladder (GSEL) VSS © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 750 PIC18F06/16Q41 OPA - Operational Amplifier 42.5.4 OPAxCON3 Name:  Address:  OPAxCON3 0xA6 Operational Amplifier Control Register 3 Bit 7 6 5 4 3 2 1 0 FMS[1:0] Access Reset R/W 0 PSS[1:0] R/W 0 R/W 0 R/W 0 Bits 7:6 – FMS[1:0] Feedback Mode Selection Value Description 11 Reserved 10 Operational Amplifier Output Pin (OPAxOUT) 01 VDD 00 No Connection Bits 1:0 – PSS[1:0] Positive Source Selection Value Description 11 10 01 00 OPAxIN3+ OPAxIN2+ OPAxIN1+ OPAxIN0+ © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 751 PIC18F06/16Q41 OPA - Operational Amplifier 42.5.5 OPAxHWC Name:  Address:  OPAxHWC 0xA7 Operational Amplifier Hardware Control Options Register Bit Access Reset 7 OREN R/W 0 6 5 HWCH[2:0] R/W 0 R/W 0 4 R/W 0 3 ORPOL R/W 0 2 R/W 0 1 HWCL[2:0] R/W 0 0 R/W 0 Bit 7 – OREN Override Enable Value Description 1 Hardware Override Control is enabled. OPA mode of operation is configured using the HWCH / HWCL bits. 0 Hardware Override Control is disabled. OPA mode of operation must be configured in software. Bits 6:4 – HWCH[2:0] Hardware Control Configuration High Value Description 111 110 101 100 011 010 001 000 Rail Drive to VDD Reserved Reserved Basic OPA configuration with unity gain feedback Reserved Reserved Reserved Basic OPA configuration with user-defined feedback Bit 3 – ORPOL Override Source Polarity Value Description 1 Hardware Control Input is Inverted (Active-Low) 0 Hardware Control Input is not Inverted (Active-High) Bits 2:0 – HWCL[2:0] Hardware Control Configuration Low Value Description 111 110 101 100 011 010 001 000 Rail Drive to VSS Reserved Reserved Basic OPA configuration with unity gain feedback Reserved Reserved Reserved Basic OPA configuration with user-defined feedback © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 752 PIC18F06/16Q41 OPA - Operational Amplifier 42.5.6 OPAxOFFSET Name:  Address:  OPAxOFFSET 0xA8 Operational Amplifier Input Offset Adjustment Register Bit Access Reset 7 6 5 R/W m R/W m R/W m 4 3 OFFSET[7:0] R/W R/W m m 2 1 0 R/W m R/W m R/W m Bits 7:0 – OFFSET[7:0] Operational Amplifier Input Offset Calibration Important:  If written by the user, the factory calibrated value of this register will be replaced and can only be restored on a Reset. Note:  The Reset value ‘m’ is determined by device default locations for that input. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 753 PIC18F06/16Q41 OPA - Operational Amplifier 42.5.7 OPAxORS Name:  Address:  OPAxORS 0xA9 Operational Amplifier Override Source Selection Register Bit 7 6 5 Access Reset 4 3 R/W 0 R/W 0 2 ORS[4:0] R/W 0 1 0 R/W 0 R/W 0 Bits 4:0 – ORS[4:0] Operational Amplifier Output Override Source Selection Value Description 10110 - 11111 10101 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 Reserved CLC4_OUT CLC3_OUT CLC2_OUT CLC1_OUT ZCD_OUT CM2_OUT CM1_OUT NCO1_OUT PWM3_S1P2 PWM3_S1P1 PWM2_S1P2 PWM2_S1P1 PWM1_S1P2 PWM1_S1P1 CCP1_OUT TMR4_OUT TMR3_OUT TMR2_OUT TMR1_OUT TMR0_OUT SOSC LFINTOSC © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 754 PIC18F06/16Q41 OPA - Operational Amplifier 42.6 Address 0x00 ... 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 Register Summary - Operational Amplifier Name Bit Pos. 7 7:0 7:0 7:0 7:0 7:0 7:0 7:0 EN 6 5 4 3 2 1 0 Reserved OPA1CON0 OPA1CON1 OPA1CON2 OPA1CON3 OPA1HWC OPA1OFFSET OPA1ORS FMS[1:0] OREN © 2020-2021 Microchip Technology Inc. and its subsidiaries CPON GSEL[2:0] NCH[2:0] UG RESON HWCH[2:0] ORPOL OFFSET[7:0] SOC[1:0] NSS[2:0] PCH[2:0] PSS[1:0] HWCL[2:0] ORS[4:0] Preliminary Datasheet DS40002214E-page 755 PIC18F06/16Q41 CMP - Comparator Module 43. CMP - Comparator Module Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: • • • • • • • 43.1 Programmable input selection Programmable output polarity Rising/falling output edge interrupts Wake-up from Sleep Selectable voltage reference ADC auto-trigger Inter-connections with other available modules (e.g., timer clocks) Comparator Overview A single comparator is shown in Figure 43-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. Figure 43-1. Single Comparator Rev. 30-000125A 5/17/2017 VIN+ + VIN- – Output VINVIN+ Output Note:  1. The black areas of the output of the comparator represent the uncertainty due to input offsets and response time. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 756 PIC18F06/16Q41 CMP - Comparator Module Figure 43-2. Comparator Module Simplified Block Diagram Re v. 10 -00 00 27 R 2/11 /20 19 INTP Interrupt Rising Edge EN(1) NCH set bit CxIF INTN Interrupt Falling Edge EN(1) CxVP See CMxNCH Register - Comparator Output Cx CxVN + HYS POL CxOUT_sync See CMxPCH Register TRIS bit 0 PPS PCH EN D (1) Q (From Timer1 Module) T1CLK Note 1: 43.2 To Other Peripherals SYNC CxOUT 1 RxyPPS When EN = 0, all multiplexer inputs are disconnected and the Comparator will produce a ‘0’ at the output. Comparator Control Each comparator has two control registers: CMxCON0 and CMxCON1. The CMxCON0 register contains Control and Status bits for the following: • • • • • Enable Output Output Polarity Hysteresis Enable Timer1 Output Synchronization The CMxCON1 register contains Control bits for the following: • Interrupt on Positive/Negative Edge Enables The CMxPCH and CMxNCH registers are used to select the positive and negative input channels, respectively. 43.2.1 Comparator Enable Setting the EN bit enables the comparator for operation. Clearing the EN bit disables the comparator, resulting in minimum current consumption. 43.2.2 Comparator Output The output of the comparator can be monitored in two different registers. Each output can be read individually by reading the OUT bit. Outputs of all the comparators can be collectively accessed by reading the CMOUT register. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 757 PIC18F06/16Q41 CMP - Comparator Module The comparator output can also be routed to an external pin through the RxyPPS register. Refer to the “PPS Peripheral Pin Select Module” chapter for more details. The corresponding TRIS bit must be clear to enable the pin as an output. Important:  The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 43.2.3 Comparator Output Polarity Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the POL bit. Clearing the POL bit results in a noninverted output. Table 43-1 shows the Output state versus Input conditions, including polarity control. Table 43-1. Comparator Output State vs. Input Conditions 43.3 Input Condition POL OUT CxVn > CxVp 0 0 CxVn < CxVp 0 1 CxVn > CxVp 1 1 CxVn < CxVp 1 0 Comparator Output Synchronization The output from a comparator can be synchronized with Timer1 by setting the SYNC bit. Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a Race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. A simplified block diagram of the comparator module is shown in Figure 43-2. Refer to the “TMR1 - Timer1 Module with Gate Control” chapter for more details. 43.4 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the HYS bit. See the “Comparator Specifications” section for more information. 43.5 Comparator Interrupt An interrupt can be generated for every rising or falling edge of the comparator output. When either edge detector is triggered and its associated enable bit is set (INTP and/or INTN bits), the Corresponding Interrupt Flag bit (CxIF bit of the respective PIR register) will be set. To enable the interrupt, the following bits must be set: • • • • • EN bit INTP bit (for a rising edge detection) INTN bit (for a falling edge detection) CxIE bit of the respective PIE register GIE bit of the INTCON0 register © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 758 PIC18F06/16Q41 CMP - Comparator Module The associated interrupt flag bit, CxIF bit of the respective PIR register, must be cleared in software to successfully detect another edge. Important:  Although a comparator is disabled, an interrupt will be generated by changing the output polarity with the POL bit. 43.6 Comparator Positive Input Selection Configuring the PCH bits direct an internal voltage reference or an analog pin to the noninverting input of the comparator. Any time the comparator is disabled (EN = 0), all comparator inputs are disabled. 43.7 Comparator Negative Input Selection The NCH bits direct an analog input pin, internal reference voltage or analog ground to the inverting input of the comparator. Important:  To use CxINy+ and CxINy- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. 43.8 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in the “Comparator Specifications” and “Fixed Voltage Reference (FVR) Specifications” sections for more details. 43.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 43-3. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and abnormal behavior may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, will have very little leakage current to minimize corrupting the result. Notes:  1. When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2. Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than specified. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 759 PIC18F06/16Q41 CMP - Comparator Module Figure 43-3. Analog Input Model Re v. 10 -00 00 71D 2/11 /20 19 VDD Analog Input pin RS VT 0.6V RIC To Comparator CPIN 5 pF VA VT 0.6V ILEAKAGE(1) VSS Legend: CPIN ILE AKAG E RIC RS VA VT = Input Capacitance = Leakage Current at the pin due to various junctions = Interconnect Resistance = Source Impedance = Analog Voltage = Diode Forward Voltage Note: 1. See the "Electrical Specifications" chapter. 43.10 Operation in Sleep Mode The comparator module can operate during Sleep. A comparator interrupt will wake the device from Sleep. The CxIE bits of the respective PIE register must be set to enable comparator interrupts. The comparator clock source is based on the Timer1 clock source. If the Timer1 clock source is either the system clock (FOSC) or the instruction clock (FOSC/4), Timer1 will not operate during Sleep, and synchronized comparator outputs will not operate. 43.11 ADC Auto-Trigger Source The output of the comparator module can be used to trigger an ADC conversion. When the ADACT register is set to trigger on a comparator output, an ADC conversion will trigger when the comparator output goes high. 43.12 Register Definitions: Comparator Control Long bit name prefixes for the Comparator peripherals are shown in the table below. Refer to the “Long Bit Names” section in the “Register and Bit Naming Conventions” chapter for more information. Table 43-2. Comparator Long Bit Name Prefixes Peripheral Bit Name Prefix C1 C1 C2 C2 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 760 PIC18F06/16Q41 CMP - Comparator Module 43.12.1 CMxCON0 Name:  Address:  CMxCON0 0x070,0x074 Comparator Control Register 0 Bit Access Reset 7 EN R/W 0 6 OUT R 0 5 4 POL R/W 0 3 2 1 HYS R/W 0 0 SYNC R/W 0 Bit 7 – EN Comparator Enable Value Description 1 Comparator is enabled 0 Comparator is disabled and consumes no active power Bit 6 – OUT Comparator Output Value Condition 1 If POL = 0 (noninverted polarity): 0 If POL = 0 (noninverted polarity): 1 If POL = 1 (inverted polarity): 0 If POL = 1 (inverted polarity): Description CxVP > CxVN CxVP < CxVN CxVP < CxVN CxVP > CxVN Bit 4 – POL Comparator Output Polarity Select Value Description 1 Comparator output is inverted 0 Comparator output is not inverted Bit 1 – HYS Comparator Hysteresis Enable Value Description 1 Comparator hysteresis enabled 0 Comparator hysteresis disabled Bit 0 – SYNC Comparator Output Synchronous Mode Value Description 1 Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 Comparator output to Timer1 and I/O pin is asynchronous © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 761 PIC18F06/16Q41 CMP - Comparator Module 43.12.2 CMxCON1 Name:  Address:  CMxCON1 0x071,0x075 Comparator Control Register 1 Bit 7 6 5 4 3 2 Access Reset 1 INTP R/W 0 0 INTN R/W 0 Bit 1 – INTP Comparator Interrupt on Positive-Going Edge Enable Value Description 1 The CxIF interrupt flag will be set upon a positive-going edge of the CxOUT bit 0 No interrupt flag will be set on a positive-going edge of the CxOUT bit Bit 0 – INTN Comparator Interrupt on Negative-Going Edge Enable Value Description 1 The CxIF interrupt flag will be set upon a negative-going edge of the CxOUT bit 0 No interrupt flag will be set on a negative-going edge of the CxOUT bit © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 762 PIC18F06/16Q41 CMP - Comparator Module 43.12.3 CMxNCH Name:  Address:  CMxNCH 0x072,0x076 Comparator Inverting Channel Select Register Bit 7 6 5 4 3 Access Reset 2 R/W 0 1 NCH[2:0] R/W 0 0 R/W 0 Bits 2:0 – NCH[2:0] Comparator Inverting Input Channel Select NCH 111 110 101 100 011 010 001 000 © 2020-2021 Microchip Technology Inc. and its subsidiaries Negative Input Sources VSS FVR_Buffer2 NCH not connected NCH not connected CxIN3CxIN2CxIN1CxIN0- Preliminary Datasheet DS40002214E-page 763 PIC18F06/16Q41 CMP - Comparator Module 43.12.4 CMxPCH Name:  Address:  CMxPCH 0x073,0x077 Comparator Noninverting Channel Select Register Bit 7 6 5 4 3 Access Reset 2 R/W 0 1 PCH[2:0] R/W 0 0 R/W 0 Bits 2:0 – PCH[2:0] Comparator Noninverting Input Channel Select PCH 111 110 101 100 011 010 001 000 © 2020-2021 Microchip Technology Inc. and its subsidiaries Positive Input Sources VSS FVR_Buffer2 DAC2_Output PCH not connected PCH not connected PCH not connected PCH not connected CxIN0+ Preliminary Datasheet DS40002214E-page 764 PIC18F06/16Q41 CMP - Comparator Module 43.12.5 CMOUT Name:  Address:  CMOUT 0x06F Comparator Output Register Bit 7 6 5 4 3 Access Reset 2 1 C2OUT R 0 0 C1OUT R 0 Bits 0, 1 – CxOUT Mirror copy of the CMxCON0.OUT © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 765 PIC18F06/16Q41 CMP - Comparator Module 43.13 Address 0x00 ... 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 Register Summary - Comparator Name Bit Pos. 7 6 5 4 EN OUT POL EN OUT POL 3 2 1 0 C2OUT HYS INTP NCH[2:0] PCH[2:0] HYS INTP NCH[2:0] PCH[2:0] C1OUT SYNC INTN Reserved CMOUT CM1CON0 CM1CON1 CM1NCH CM1PCH CM2CON0 CM2CON1 CM2NCH CM2PCH 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet SYNC INTN DS40002214E-page 766 PIC18F06/16Q41 ZCD - Zero-Cross Detection Module 44. ZCD - Zero-Cross Detection Module The ZCD module detects when an A/C signal crosses through the ground potential. The actual zero-crossing threshold is the zero-crossing reference voltage, ZCPINV, which is typically 0.75V above ground. The connection to the signal to be detected is through a series current-limiting resistor. The module applies a current source or sink to the ZCD pin to maintain a constant voltage on the pin, thereby preventing the pin voltage from forward biasing the ESD protection diodes. When the applied voltage is greater than the reference voltage, the module sinks current. When the applied voltage is less than the reference voltage, the module sources current. The current source and sink action keeps the pin voltage constant over the full range of the applied voltage. The ZCD module is shown in the following simplified block diagram. Figure 44-1. Simplified ZCD Block Diagram Rev. 10-000194E 3/4/2019 VPULLUP RPULLUP (optional) VDD - Zcpinv ZCDxIN RSERIES External voltage source + RPULLDOWN (optional) ZCD Output for other modules POL OUT pin Interrupt det INTP INTN Set ZCDxIF flag Interrupt det The ZCD module is useful when monitoring an A/C waveform for, but not limited to, the following purposes: • • A/C period measurement Accurate long term time measurement © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 767 PIC18F06/16Q41 ZCD - Zero-Cross Detection Module • • 44.1 Dimmer phase delayed drive Low EMI cycle switching External Resistor Selection The ZCD module requires a current-limiting resistor in series with the external voltage source. The impedance and rating of this resistor depends on the external source peak voltage. Select a resistor value that will drop all of the peak voltage when the current through the resistor is less than the maximum input current (ZC02). Refer to the “Electrical Specifications” chapter for more details. Make sure that the ZCD I/O pin internal weak pull-up is disabled so it does not interfere with the current source and sink. Equation 44-1. External Resistor V RSERIES = PEAK IZCD Figure 44-2. External Voltage Source Rev. 30-000001A 7/18/2017 VMAXPEAK VMINPEAK VPEAK Z CPINV 44.2 ZCD Logic Output The ZCD module includes a Status bit, which can be read to determine whether the current source or sink is active. The OUT bit is set when the current sink is active, and cleared when the current source is active. The OUT bit is affected by the polarity bit. The OUT signal can also be used as input to other modules. This is controlled by the registers of the corresponding module. 44.3 ZCD Logic Polarity The POL bit inverts the OUT bit relative to the current source and sink output. When the POL bit is set, a OUT high indicates that the current source is active, and a low output indicates that the current sink is active. The POL bit affects the ZCD interrupts. 44.4 ZCD Interrupts An interrupt will be generated upon a change in the ZCD logic output when the appropriate interrupt enables are set. The ZCD module has a rising edge detector and a falling edge detector. The ZCDIF bit of the PIRx register will be set when either edge detector is triggered and its associated enable bit is set. The INTP enables rising edge interrupts and the INTN bit enables falling edge interrupts. To fully enable the interrupt, the following bits must be set: • • • • ZCDIE bit of the PIEx register INTP bit for rising edge detection INTN bit for falling edge detection GIEL and GIE bits of the INTCON0 register Changing the POL bit will cause an interrupt, regardless of the level of the SEN bit. The ZCDIF bit of the PIRx register must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 768 PIC18F06/16Q41 ZCD - Zero-Cross Detection Module 44.5 Correction for ZCPINV Offset The actual voltage at which the ZCD switches is the reference voltage at the noninverting input of the ZCD op amp. For external voltage source waveforms other than square waves, this voltage offset from zero causes the zero-cross event to occur either too early or too late. 44.5.1 Correction by AC Coupling When the external voltage source is sinusoidal, the effects of the ZCPINV offset can be eliminated by isolating the external voltage source from the ZCD pin with a capacitor, in addition to the voltage reducing resistor. The capacitor will cause a phase shift resulting in the ZCD output switch in advance of the actual zero-crossing event. The phase shift will be the same for both rising and falling zero-crossings, which can be compensated for by either delaying the CPU response to the ZCD switch by a timer or other means, or selecting a capacitor value large enough that the phase shift is negligible. To determine the series resistor and capacitor values for this configuration, start by computing the impedance, Z, to obtain a peak current less than the maximum input current (ZC02). Refer to the "Electrical Specifications" chapter for more details. Next, arbitrarily select a suitably large nonpolar capacitor and compute its reactance, Xc, at the external voltage source frequency. Finally, compute the series resistor, capacitor peak voltage, and phase shift using the formulas shown below. When this technique is used and the input signal is not present, the ZCD will tend to oscillate. To avoid this oscillation, connect the ZCD pin to VDD or GND with a high-impedance resistor. Note:  In this example, the impedance value is calculated for a peak current of 300 μA. Equation 44-2. R-C Equations VPEAK = external voltage source peak voltage f = external voltage source frequency C = series capacitor R = series resistor VC = peak capacitor voltage Φ = capacitor induced zero-crossing phase advance in radians TΦ = time ZC event occurs before actual zero-crossing Z= 3 × 10−4 XC = R= VPEAK 1 2πfC Z2 − XC2 VC = XC 3 × 10−4 Φ = tan −1 TΦ = Φ 2πf XC R Equation 44-3. R-C Calculation Example Vrms = 120 VPEAK = Vrms × 2 = 169.7 f = 60 Hz © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 769 PIC18F06/16Q41 ZCD - Zero-Cross Detection Module C = 0.1 μF Z= VPEAK 3 × 10−4 XC = R= = 169.7 = 565.7 kΩ 3 × 10−4 1 = 1 = 26.53 kΩ 2πfC 2π × 60 × 10−7 Z2 − XC2 = 565.1 kΩ computed Ra = 560 kΩ used ZR = Ra2 + XC2 = 560.6 kΩ IPEAK = VPEAK = 302.7 × 10−6A ZR VC = XC × IPEAK = 8.0 V Φ = tan −1 XC = 0.047 radians R TΦ = Φ = 125.6 μs 2πf 44.5.2 Correction by Offset Current When the waveform is varying relative to VSS, the zero-cross is detected too early as the waveform falls and too late as the waveform rises. When the waveform is varying relative to VDD, the zero-cross is detected too late as the waveform rises and too early as the waveform falls. The actual offset time can be determined for sinusoidal waveforms with the corresponding equations shown below. Equation 44-4. ZCD Event Offset When External Voltage source is relative to VSS: Toffset = sin−1 ZCPINV VPEAK 2πf When External Voltage source is relative to VDD: Toffset = sin−1 VDD − ZCPINV VPEAK 2πf This offset time can be compensated for by adding a pull-up or pull-down biasing resistor to the ZCD pin. A pull-up resistor is used when the external voltage source is varying relative to VSS. A pull-down resistor is used when the voltage is varying relative to VDD. The resistor adds a bias to the ZCD pin so that the target external voltage source must go to zero to pull the pin voltage to the ZCPINV switching voltage. The pull-up or pull-down value can be determined with the equations shown below. Equation 44-5. ZCD Pull-up/Pull-down Resistor When External Voltage source is relative to VSS: Rpullup = RSERIES Vpullup − ZCPINV ZCPINV When External Voltage source is relative to VDD: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 770 PIC18F06/16Q41 ZCD - Zero-Cross Detection Module Rpulldown = 44.6 RSERIES ZCPINV VDD − ZCPINV Handling VPEAK Variations If the peak amplitude of the external voltage is expected to vary, the series resistor must be selected to keep the ZCD current source, and sink below the design maximum range specified by ZC02 and above a reasonable minimum range depending on the application. The compensating pull-up for this series resistance can be determined with the equations shown in Equation 44-5 because the pull-up value is independent from the peak voltage. Tip:  It is recommended that the maximum peak voltage be no more than six times the minimum peak voltage. 44.7 Operation During Sleep The ZCD current sources and interrupts are unaffected by Sleep. 44.8 Effects of a Reset The ZCD circuit can be configured to default to the Active or Inactive state on Power-on Reset (POR). When the ZCD Configuration bit is cleared, the ZCD circuit will be active at POR. When the ZCD Configuration bit is set, the SEN bit must be set to enable the ZCD module. 44.9 Disabling the ZCD Module The ZCD module can be disabled in two ways: 1. 2. 44.10 The ZCD Configuration bit disables the ZCD module when set. When this is the case then the ZCD module will be enabled by setting the SEN bit. When the ZCD bit is clear, the ZCD is always enabled and the SEN bit has no effect. The ZCD can also be disabled using the ZCDMD bit of the PMDx register. This is subject to the status of the ZCD bit. Register Definitions: ZCD Control Long bit name prefixes for the ZCD peripherals are shown in the table below. Refer to the “Long Bit Names” section of the “Register and Bit Naming Conventions” chapter for more information. Table 44-1. ZCD Long Bit Name Prefixes Peripheral Bit Name Prefix ZCD ZCD © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 771 PIC18F06/16Q41 ZCD - Zero-Cross Detection Module 44.10.1 ZCDCON Name:  Address:  ZCDCON 0x04C Zero-Cross Detect Control Register Bit Access Reset 7 SEN R/W 0 6 5 OUT R x 4 POL R/W 0 3 2 1 INTP R/W 0 0 INTN R/W 0 Bit 7 – SEN Zero-Cross Detect Software Enable This bit is ignored when the ZCD fuse is cleared. Value Condition Description X ZCD Config fuse = 0 Zero-cross detect is always enabled. This bit is ignored. 1 ZCD Config fuse = 1 Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current. 0 ZCD Config fuse = 1 Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls. Bit 5 – OUT Zero-Cross Detect Data Output Value Condition Description 1 POL = 0 ZCD pin is sinking current 0 POL = 0 ZCD pin is sourcing current 1 POL = 1 ZCD pin is sourcing current 0 POL = 1 ZCD pin is sinking current Bit 4 – POL Zero-Cross Detect Polarity Value Description 1 ZCD logic output is inverted 0 ZCD logic output is not inverted Bit 1 – INTP Zero-Cross Detect Positive-Going Edge Interrupt Enable Value Description 1 The ZCDIF bit is set on low-to-high ZCD_output transition 0 The ZCDIF bit is unaffected by low-to-high ZCD_output transition Bit 0 – INTN Zero-Cross Detect Negative-Going Edge Interrupt Enable Value Description 1 The ZCDIF bit is set on high-to-low ZCD_output transition 0 The ZCDIF bit is unaffected by high-to-low ZCD_output transition © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 772 PIC18F06/16Q41 ZCD - Zero-Cross Detection Module 44.11 Address 0x00 ... 0x4B 0x4C Register Summary - ZCD Name Bit Pos. 7 7:0 SEN 6 5 4 OUT POL 3 2 1 0 INTP INTN Reserved ZCDCON © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 773 PIC18F06/16Q41 Instruction Set Summary 45. Instruction Set Summary The PIC18 devices incorporate the standard set of PIC18 core instructions, as well as an extended set of instructions to optimize code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 45.1 Standard Instruction Set ® The standard PIC18 instruction set adds many enhancements to the previous PIC MCU instruction sets, while maintaining an easy migration from these PIC MCU instruction sets. Most instructions are a single program memory word (16 bits), but there are a few instructions that require two- or three-program memory locations. Each single-word instruction is a 16-bit word divided into an opcode that specifies the instruction type and one or more operands, which further specifies the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: • • • • Byte-oriented operations Bit-oriented operations Literal operations Control operations The PIC18 instruction set summary in Table 45-2 lists byte-oriented, bit-oriented, literal and control operations. Table 45-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: • • • The file register (specified by ‘f’) The destination of the result (specified by ‘d’) The accessed memory (specified by ‘a’) The file register designator ‘f’ specifies which file register is to be used by the instruction. The destination designator ‘d’ specifies where the result of the operation is to be placed. If ‘d’ is zero, the result is placed in the WREG register. If ‘d’ is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: • • • The file register (specified by ‘f’) The bit in the file register (specified by ‘b’) The accessed memory (specified by ‘a’) The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register designator ‘f’ represents the number of the file in which the bit is located. The literal instructions may use some of the following operands: • • • A literal value to be loaded into a file register (specified by ‘k’) The desired FSR register to load the literal value into (specified by ‘f’) No operand required (specified by ‘—’) The control instructions may use some of the following operands: • • A program memory address (specified by ‘n’) The mode of the CALL or RETURN instructions (specified by ‘s’) • • The mode of the table read and table write instructions (specified by ‘m’) No operand required (specified by ‘—’) All instructions are a single word, except for a few two- or three-word instructions. These instructions were made twoor three-word to contain the required information in 32 or 48 bits. In the second and third words, the four MSbs are ‘1’s. If this second or third word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the Program Counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 774 PIC18F06/16Q41 Instruction Set Summary The two-word instructions execute in two instruction cycles and three-word instructions execute in three instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 μs. If a conditional test is true, or the Program Counter is changed as a result of an instruction, the instruction execution time is 2 μs. Two-word branch instructions (if true) take 3 μs. Figure 45-1, Figure 45-2 and Figure 45-3 show the general formats that the instructions can have. All examples use the convention ‘nnh’ to represent a hexadecimal number. The Instruction Set Summary, shown in Table 45-2, lists the standard instructions recognized by the Microchip MPASMTM Assembler. Standard Instruction Set provides a description of each instruction. Table 45-1. Opcode Field Descriptions Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register (default) ACCESS ACCESS = 0: RAM access bit symbol BANKED BANKED = 1: RAM access bit symbol bbb Bit address within an 8-bit file register (0 to 7) BSR Bank Select Register (BSR). Used to select the current RAM bank. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f (default) dest Destination: either the WREG register or the specified register file location f 8-bit register file address (00h to FFh) fn FSR Number (0 to 2) fs 12-bit register file address (000h to FFFh) or 14-bit register file address (0000h to 3FFFh). This is the source address. fd 12-bit register file address (000h to FFFh) or 14-bit register file address (0000h to 3FFFh). This is the destination address. zs 7-bit literal offset for FSR2 to used as register file address (000h to FFFh). This is the source address. zd 7-bit literal offset for FSR2 to used as register file address (000h to FFFh). This is the destination address. k Literal field, constant data or label (may be either a 6-bit, 8-bit, 12-bit or a 20-bit value) label Label name mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 775 PIC18F06/16Q41 Instruction Set Summary ...........continued Field Description n The relative address (two’s complement number) for relative branch instructions, or the direct address for call/branch and return instructions. PRODH Product of multiply high byte PRODL Product of multiply low byte s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers (default) s = 1: certain registers loaded into/from shadow registers (Fast mode) u Unused or unchanged W W = 0: Destination select bit symbol WREG Working register (accumulator) x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. TBLPTR 21-bit Table Pointer (points to a program memory location) TABLAT 8-bit table latch TOS Top-of-stack (TOS) PC Program Counter PCL Program Counter low byte PCH Program Counter high byte PCLATH Program Counter high byte latch PCLATU Program Counter upper byte Latch GIE Global Interrupt Enable bit WDT Watchdog Timer TO Time-Out bit PD Power-Down bit C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative { } Optional argument [ ] Indexed address ( ) Contents < > Register bit field [expr] Specifies bit n of the register indicated by pointer expr → Assigned to ∈ In the set of italics User defined term (font is Courier) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 776 PIC18F06/16Q41 Instruction Set Summary Figure 45-1. General Format for Byte-Oriented Instructions Example Instruction Byte-oriented file register operations 15 10 OPCODE 9 8 7 0 d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (two-word) 15 12 11 0 OPCODE 15 12 Example Instruction f (Source FILE #) MOVFF MYREG1, MYREG2 11 0 f (Destination FILE #) 1111 f = 12-bit file register address Example Instruction Byte to Byte move operations (three-word) 15 4 OPCODE 15 12 MOVFFL MYREG1, MYREG2 0 FILE # 12 11 1111 © 2020-2021 Microchip Technology Inc. and its subsidiaries 0 FILE # 11 1111 15 3 0 FILE # Preliminary Datasheet DS40002214E-page 777 PIC18F06/16Q41 Instruction Set Summary Figure 45-2. General Format for Bit-Oriented and Literal Instructions Example Instruction Bit-oriented file register operations 15 12 OPCODE 11 9 8 7 b(BIT #) a 0 f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Example Instruction Literal operations 15 8 OPCODE 7 0 k (literal) MOVLW 7Fh k = 8-bit immediate value © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 778 PIC18F06/16Q41 Instruction Set Summary Figure 45-3. General Format for Control Instructions Control operations CALL, GOTO and Branch operations 15 8 7 OPCODE 15 12 Example Instruction 0 k (literal) 11 GOTO Label 0 OPCODE k (literal) k = 20-bit immediate value 15 9 OPCODE 15 12 8 7 s 0 k (literal) 11 CALL MYFUNC 0 OPCODE k (literal) k = 20-bit immediate value s = Fast bit 11 15 10 0 OPCODE n (literal) BRA MYFUNC n = 11-bit immediate value 15 8 OPCODE 0 7 n (literal) BC MYFUNC n = 8-bit immediate value © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 779 and its subsidiaries © 2020-2021 Microchip Technology Inc. Table 45-2. Standard Instruction Set Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes rotatethispage90 BYTE-ORIENTED FILE REGISTER INSTRUCTIONS Preliminary Datasheet ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1 CLRF f, a Clear f 1 0110 101a ffff ffff Z COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1 MOVF f, d, a Move f to WREG or f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (12-bit source) to fd (12-bit destination) 2 1100 fsfsfsfs fsfsfsfs fsfsfsfs 1111 fdfdfdfd fdfdfdfd fdfdfdfd None 1, 3, 4 0000 0000 0110 fsfsfsfs fs, fd Move fs (14-bit source) to fd (14-bit destination) 1111 fsfsfsfs fsfsfsfs fsfsfdfd None 1, 3 1111 fdfdfdfd fdfdfdfd fdfdfdfd MOVFFL 3 Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N 1 RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N 1 RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N 1 RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N 1 SETF f, a Set f 1 0110 100a ffff ffff None PIC18F06/16Q41 f, a Instruction Set Summary DS40002214E-page 780 MOVWF and its subsidiaries © 2020-2021 Microchip Technology Inc. ...........continued Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes rotatethispage90 SUBFWB f, d, a Subtract f from WREG with Borrow 1 0101 01da ffff ffff C, DC, Z, OV, N 1 SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1 SUBWFB f, d, a Subtract WREG from f with Borrow 1 0101 10da ffff ffff C, DC, Z, OV, N 1 SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 1 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N 1 BYTE-ORIENTED SKIP INSTRUCTIONS Preliminary Datasheet Compare f with WREG, skip if = 1–4 0110 001a ffff ffff None 1, 2 CPFSGT f, a Compare f with WREG, skip if > 1–4 0110 010a ffff ffff None 1, 2 CPFSLT f, a Compare f with WREG, skip if < 1–4 0110 000a ffff ffff None 1, 2 DECFSZ f, d, a Decrement f, Skip if 0 1–4 0010 11da ffff ffff None 1, 2 DCFSNZ f, d, a Decrement f, Skip if Not 0 1–4 0100 11da ffff ffff None 1, 2 INCFSZ f, d, a Increment f, Skip if 0 1–4 0011 11da ffff ffff None 1, 2 INFSNZ f, d, a Increment f, Skip if Not 0 1–4 0100 10da ffff ffff None 1, 2 TSTFSZ f, a Test f, skip if 0 1–4 0110 011a ffff ffff None 1, 2 BIT-ORIENTED FILE REGISTER INSTRUCTIONS DS40002214E-page 781 BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1 BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1 ffff ffff None 1, 2 BIT-ORIENTED SKIP INSTRUCTIONS BTFSC f, b, a Bit Test f, Skip if Clear 1–4 1011 bbba PIC18F06/16Q41 f, a Instruction Set Summary CPFSEQ and its subsidiaries © 2020-2021 Microchip Technology Inc. ...........continued Mnemonic, Operands 16-Bit Instruction Word Description Cycles Bit Test f, Skip if Set 1–4 LSb Status Affected Notes ffff ffff None 1, 2 MSb rotatethispage90 BTFSS f, b, a 1010 bbba CONTROL INSTRUCTIONS Preliminary Datasheet Branch if Carry 1–2 1110 0010 nnnn nnnn None 2 BN n Branch if Negative 1–2 1110 0110 nnnn nnnn None 2 BNC n Branch if Not Carry 1–2 1110 0011 nnnn nnnn None 2 BNN n Branch if Not Negative 1–2 1110 0111 nnnn nnnn None 2 BNOV n Branch if Not Overflow 1–2 1110 0101 nnnn nnnn None 2 BNZ n Branch if Not Zero 1–2 1110 0001 nnnn nnnn None 2 BOV n Branch if Overflow 1–2 1110 0100 nnnn nnnn None 2 BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None 2 BZ n Branch if Zero 1–2 1110 0000 nnnn nnnn None 2 CALL k, s Call subroutine 2 1110 110s kkkk kkkk 1111 kkkk kkkk kkkk None 2, 3 CALLW — Call subroutine using WREG 2 0000 0000 0001 0100 None 2 GOTO k Go to address 2 1110 1111 kkkk kkkk 1111 kkkk kkkk kkkk None 3 RCALL n Relative Call 2 1101 1nnn nnnn nnnn None 2 RETFIE s Return from interrupt enable 2 0000 0000 0001 000s INTCONx STAT bits 2 RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None 2 RETURN s Return from Subroutine 2 0000 0000 0001 001s None 2 0000 0100 TO, PD INHERENT INSTRUCTIONS CLRWDT — Clear Watchdog Timer 1 0000 0000 PIC18F06/16Q41 n Instruction Set Summary DS40002214E-page 782 BC and its subsidiaries © 2020-2021 Microchip Technology Inc. ...........continued Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes rotatethispage90 DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None POP — Pop top of return stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push top of return stack (TOS) 1 0000 0000 0000 0101 None RESET — Software device Reset 1 0000 0000 1111 1111 All SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD 3 Preliminary Datasheet LITERAL INSTRUCTIONS Add FSR (fn) with literal (k) 1 1110 1000 fnfnkk kkkk None ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR fn, k Load FSR(fn) with a 14-bit literal (k) 2 1110 1110 00fnfn kkkk 1111 00kk kkkk kkkk MOVLB k Move literal to BSR 1 0000 0001 00kk kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBFSR fn, k Subtract literal (k) from FSR (fn) 1 1110 1001 fnfnkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N None 3 PIC18F06/16Q41 fn, k Instruction Set Summary DS40002214E-page 783 ADDFSR and its subsidiaries © 2020-2021 Microchip Technology Inc. ...........continued Mnemonic, Operands 16-Bit Instruction Word Description Cycles Exclusive OR literal with WREG 1 MSb LSb Status Affected kkkk Z, N Notes rotatethispage90 XORLW k 0000 1010 kkkk DATA MEMORY – PROGRAM MEMORY INSTRUCTIONS Preliminary Datasheet TBLRD* — Table Read 2 0000 0000 0000 1000 None TBLRD*+ — Table Read with postincrement 2 0000 0000 0000 1001 None TBLRD*- — Table Read with postdecrement 2 0000 0000 0000 1010 None TBLRD+* — Table Read with preincrement 2 0000 0000 0000 1011 None TBLWT* — Table Write 2 0000 0000 0000 1100 None TBLWT*+ — Table Write with postincrement 2 0000 0000 0000 1101 None TBLWT*- — Table Write with postdecrement 2 0000 0000 0000 1110 None TBLWT+* — Table Write with preincrement 2 0000 0000 0000 1111 None If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 3. Some instructions are multi-word instructions. The extra words of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. fs and fd do not cover the full memory range. 2 MSbs of bank selection are forced to 0b00 to limit the range of these instructions to the lower 4k addressing space. 4. PIC18F06/16Q41 DS40002214E-page 784 2. Instruction Set Summary Notes:  1. When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. PIC18F06/16Q41 Instruction Set Summary 45.1.1 Standard Instruction Set Important:  All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). ADDFSR Add Literal to FSR Syntax ADDFSR fn, k Operands 0 ≤ k ≤ 63 fn ∈ [0, 1, 2] Operation (FSRfn) + k → FSRfn Status Affected None 1110 Encoding 1000 fnfnkk Description The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘fn’. Words 1 Cycles 1 kkkk Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to FSR Example: ADDFSR 2, 23h Before Instruction FSR2 = 03FFh After Instruction FSR2 = 0422h ADDLW Add Literal to W Syntax ADDLW k Operands 0 ≤ k ≤ 255 Operation (W) + k → W Status Affected N, OV, C, DC, Z 0000 Encoding 1111 kkkk kkkk Description The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W. Words 1 Cycles 1 Q Cycle Activity: Q1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Q2 Q3 Preliminary Datasheet Q4 DS40002214E-page 785 PIC18F06/16Q41 Instruction Set Summary Decode Read literal ‘k’ Process Data Write to W Example: ADDLW 15h Before Instruction W = 10h After Instruction W = 25h ADDWF Add W to f Syntax ADDWF f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (W) + (f) → dest Status Affected N, OV, C, DC, Z 0010 Encoding Description 01da ffff ffff Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h ADDWFC Add W and Carry Bit to f Syntax ADDWFC f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 786 PIC18F06/16Q41 Instruction Set Summary ...........continued ADDWFC Add W and Carry Bit to f Syntax ADDWFC f {,d {,a}} Operation (W) + (f) + (C) → dest Status Affected N, OV, C, DC, Z 0010 Encoding Description 00da ffff ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 02h W = 4Dh After Instruction Carry bit = 0 REG = 02h W = 50h ANDLW AND Literal with W Syntax ANDLW k Operands 0 ≤ k ≤ 255 Operation (W) .AND. k → W Status Affected N, Z 0000 Encoding 1011 kkkk kkkk Description The contents of W are AND’ed with the 8-bit literal ‘k’. The result is placed in W. Words 1 Cycles 1 Q Cycle Activity: Q1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Q2 Q3 Preliminary Datasheet Q4 DS40002214E-page 787 PIC18F06/16Q41 Instruction Set Summary Decode Read literal ‘k’ Process Data Write to W Example: ANDLW 05Fh Before Instruction W = A3h After Instruction W = 03h ANDWF AND W with f Syntax ANDWF f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (W) .AND. (f) → dest Status Affected N, Z 0001 Encoding Description 01da ffff ffff The contents of W are AND’ed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: ANDWF REG, 0, 0 Before Instruction W = 17h REG = C2h After Instruction W = 02h REG = C2h BC Branch if Carry Syntax BC n Operands -128 ≤ n ≤ 127 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 788 PIC18F06/16Q41 Instruction Set Summary ...........continued BC Branch if Carry Syntax BC n Operation If the Carry bit is ‘1’ (PC) + 2 + 2n → PC Status Affected None 1110 Encoding 0010 nnnn nnnn Description If the Carry bit is ‘1’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words 1 Cycles 1 (2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation If No Jump: Example: HERE BC 5 Before Instruction PC = address (HERE) After Instruction If Carry = 1; PC = address (HERE + 12) If Carry = 0; PC = address (HERE + 2) BCF Bit Clear f Syntax BCF f, b {,a} Operands 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0, 1] Operation 0 → f Status Affected None Encoding 1001 © 2020-2021 Microchip Technology Inc. and its subsidiaries bbba Preliminary Datasheet ffff ffff DS40002214E-page 789 PIC18F06/16Q41 Instruction Set Summary ...........continued BCF Bit Clear f Syntax BCF f, b {,a} Description Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: BCF FLAG_REG, 7, 0 Before Instruction FLAG_REG = C7h After Instruction FLAG_REG = 47h BN Branch if Negative Syntax BN n Operands -128 ≤ n ≤ 127 Operation If NEGATIVE bit is ‘1’ (PC) + 2 + 2n → PC Status Affected None 1110 Encoding 0110 nnnn nnnn Description If the NEGATIVE bit is ‘1’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words 1 Cycles 1 (2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 790 PIC18F06/16Q41 Instruction Set Summary Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BN Jump Before Instruction PC = address (HERE) After Instruction If NEGATIVE = 1; PC = address (Jump) If NEGATIVE = 0; PC = address (HERE + 2) BNC Branch if Not Carry Syntax BNC n Operands -128 ≤ n ≤ 127 Operation If the Carry bit is ‘0’ (PC) + 2 + 2n → PC Status Affected None 1110 Encoding 0011 nnnn nnnn Description If the Carry bit is ‘0’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words 1 Cycles 1 (2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation If No Jump: Example: HERE BNC Jump Before Instruction PC = address (HERE) After Instruction If Carry = 0; PC = address (Jump) If Carry = 1; PC = address (HERE + 2) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 791 PIC18F06/16Q41 Instruction Set Summary BNN Branch if Not Negative Syntax BNN n Operands -128 ≤ n ≤ 127 Operation If NEGATIVE bit is ‘0’ (PC) + 2 + 2n → PC Status Affected None 1110 Encoding 0111 nnnn nnnn Description If the NEGATIVE bit is ‘0’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words 1 Cycles 1 (2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation If No Jump: Example: HERE BNN Jump Before Instruction PC = address (HERE) After Instruction If NEGATIVE = 0; PC = address (Jump) If NEGATIVE = 1; PC = address (HERE + 2) BNOV Branch if Not Overflow Syntax BNOV n Operands -128 ≤ n ≤ 127 Operation If OVERFLOW bit is ‘0’ (PC) + 2 + 2n → PC Status Affected None Encoding Description 1110 nnnn nnnn If the OVERFLOW bit is ‘0’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. © 2020-2021 Microchip Technology Inc. and its subsidiaries 0101 Preliminary Datasheet DS40002214E-page 792 PIC18F06/16Q41 Instruction Set Summary ...........continued BNOV Branch if Not Overflow Syntax BNOV n Words 1 Cycles 1 (2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation If No Jump: Example: HERE BNOV Jump Before Instruction PC = address (HERE) After Instruction If OVERFLOW = 0; PC = address (Jump) If OVERFLOW = 1; PC = address (HERE + 2) BNZ Branch if Not Zero Syntax BNZ n Operands -128 ≤ n ≤ 127 Operation If ZERO bit is ‘0’ (PC) + 2 + 2n → PC Status Affected None 1110 Encoding 0001 nnnn nnnn Description If the ZERO bit is ‘0’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words 1 Cycles 1 (2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 793 PIC18F06/16Q41 Instruction Set Summary No operation No operation No operation No operation Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation If No Jump: Example: HERE BNZ Jump Before Instruction PC = address (HERE) After Instruction If ZERO = 0; PC = address (Jump) If ZERO = 1; PC = address (HERE + 2) BOV Branch if Overflow Syntax BOV n Operands -128 ≤ n ≤ 127 Operation If OVERFLOW bit is ‘1’ (PC) + 2 + 2n → PC Status Affected None 1110 Encoding 0100 nnnn nnnn Description If the OVERFLOW bit is ‘1’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words 1 Cycles 1 (2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation If No Jump: Example: HERE BOV Jump Before Instruction PC = address (HERE) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 794 PIC18F06/16Q41 Instruction Set Summary After Instruction If OVERFLOW = 1; PC = address (Jump) If OVERFLOW = 0; PC = address (HERE + 2) BRA Unconditional Branch Syntax BRA n Operands -1024 ≤ n ≤ 1023 Operation (PC) + 2 + 2n → PC Status Affected None 1101 Encoding 0nnn nnnn nnnn Description The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words 1 Cycles 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation Example: HERE BRA Jump Before Instruction PC = address (HERE) After Instruction PC = address (Jump) BSF Bit Set f Syntax BSF f, b {,a} Operands 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0, 1] Operation 1 → f Status Affected None 1000 Encoding Description bbba ffff ffff Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 795 PIC18F06/16Q41 Instruction Set Summary ...........continued BSF Bit Set f Syntax BSF f, b {,a} Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah BTFSC Bit Test File, Skip if Clear Syntax BTFSC f, b {,a} Operands 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0, 1] Operation Skip if (f) = 0 Status Affected None 1011 Encoding Description bbba ffff ffff If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction. Q Cycle Activity: If no skip: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation If skip: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 796 PIC18F06/16Q41 Instruction Set Summary Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation If skip and followed by two-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by three-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE BTFSC FALSE: TRUE: FLAG, 1, 0 Before Instruction PC = address (HERE) After Instruction If FLAG = 0; PC = address (TRUE) If FLAG = 1; PC = address (FALSE) BTFSS Bit Test File, Skip if Set Syntax BTFSS f, b {,a} Operands 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0, 1] Operation Skip if (f) = 1 Status Affected None Encoding Description 1010 bbba ffff ffff If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 797 PIC18F06/16Q41 Instruction Set Summary ...........continued BTFSS Bit Test File, Skip if Set Syntax BTFSS f, b {,a} Words 1 Cycles 1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction. Q Cycle Activity: If no skip: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation If skip: If skip and followed by two-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by three-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE BTFSS FALSE: TRUE: FLAG, 1, 0 Before Instruction PC = address (HERE) After Instruction If FLAG = 0; PC = address (FALSE) If FLAG = 1; PC = address (TRUE) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 798 PIC18F06/16Q41 Instruction Set Summary BTG Bit Toggle f Syntax BTG f, b {,a} Operands 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0, 1] Operation (f) → f Status Affected None 0111 Encoding Description bbba ffff ffff Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: BTG PORTC, 4, 0 Before Instruction PORTC = 0111 0101 [75h] After Instruction PORTC = 0110 0101 [65h] BZ Branch if Zero Syntax BZ n Operands -128 ≤ n ≤ 127 Operation If ZERO bit is ‘1’ (PC) + 2 + 2n → PC Status Affected None 1110 Encoding 0000 nnnn nnnn Description If the ZERO bit is ‘1’, then the program will branch. The two’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words 1 Cycles 1 (2) Q Cycle Activity: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 799 PIC18F06/16Q41 Instruction Set Summary If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation If No Jump: Example: HERE BOV Jump Before Instruction PC = address (HERE) After Instruction If ZERO = 1; PC = address (Jump) If ZERO = 0; PC = address (HERE + 2) CALL Subroutine Call Syntax CALL k {,s} Operands 0 ≤ k ≤ 1048575 s ∈ [0, 1] Operation (PC) + 4 → TOS k → PC If s = 1 (W) → WREG_CSHAD (STATUS) → STATUS_CSHAD (BSR) → BSR_CSHAD Status Affected None Encoding 1st word (k) 2nd word (k) 1110 110s k7kkk kkkk0 1111 k19kkk kkkk kkkk8 Description Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If ‘s’ = 1, the WREG, STATUS and BSR registers are also pushed into their respective shadow registers WREG_CSHAD, STATUS_CSHAD and BSR_CSHAD. If ‘s’ = 0, no update occurs (default). Then, the 20-bit value ‘k’ is loaded into PC. CALL is a two-cycle instruction. Words 2 Cycles 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ PUSH PC to stack Read literal ‘k’ Write to PC © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 800 PIC18F06/16Q41 Instruction Set Summary No operation No operation No operation No operation Example: HERE CALL THERE, 1 Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WREG_CSHAD = (WREG) BSR_CSHAD = (BSR) STATUS_CSHAD = (STATUS) CALLW Subroutine Call using WREG Syntax CALLW Operands None Operation (PC) + 2 → TOS (W) → PCL (PCLATH) → PCH (PCLATU) → PCU Status Affected None 0000 Encoding 0000 0001 0100 Description First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched onto PCH and PCU respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Unlike CALL, there is no option to update W, STATUS or BSR. Words 1 Cycles 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read WREG PUSH PC to stack No operation No operation No operation No operation No operation Example: HERE CALLW Before Instruction PC = address (HERE) PCLATH = 10h PCLATU = 00h W = 06h After Instruction PC = address 001006h TOS = address (HERE + 2) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 801 PIC18F06/16Q41 Instruction Set Summary PCLATH = 10h PCLATU = 00h W = 06h CLRF Clear f Syntax CLRF f {,a} Operands 0 ≤ f ≤ 255 a ∈ [0, 1] Operation 000h → f 1→Z Status Affected Z 0110 Encoding Description 101a ffff ffff Clears the contents of the specified register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: CLRF FLAG_REG, 1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h CLRWDT Clear Watchdog Timer Syntax CLRWDT Operands None Operation 000h → WDT 1 → TO 1 → PD Status Affected TO, PD 0000 Encoding 0000 0000 0100 Description CLRWDT instruction resets the Watchdog Timer. It also resets the STATUS bits, and TO and PD are set. Words 1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 802 PIC18F06/16Q41 Instruction Set Summary ...........continued CLRWDT Clear Watchdog Timer Syntax CLRWDT Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data No operation Example: CLRWDT Before Instruction WDT Counter = ? After Instruction WDT Counter = 00h TO = 1 PD = 1 COMF Complement f Syntax COMF f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (f) → dest Status Affected N, Z 0001 Encoding Description 11da ffff ffff The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: COMF REG0, 0, 0 Before Instruction REG = 13h © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 803 PIC18F06/16Q41 Instruction Set Summary After Instruction REG = 13h W = ECh CPFSEQ Compare f with W, Skip if f = W Syntax CPFSEQ f {,a} Operands 0 ≤ f ≤ 255 a ∈ [0, 1] Operation (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected None 0110 Encoding Description 001a ffff ffff Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. If the contents of ‘f’ are equal to the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction. Q Cycle Activity: If no skip: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation If skip: If skip and followed by two-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by three-word instruction: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 804 PIC18F06/16Q41 Instruction Set Summary Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE CPFSEQ NEQUAL: EQUAL: REG, 0 Before Instruction PC = address (HERE) W=? REG = ? After Instruction If REG = W; PC = address (EQUAL) If REG ≠ W; PC = address (NEQUAL) CPFSGT Compare f with W, Skip if f > W Syntax CPFSGT f {,a} Operands 0 ≤ f ≤ 255 a ∈ [0, 1] Operation (f) – (W), skip if (f) > (W) (unsigned comparison) Status Affected None 0110 Encoding Description 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. If the contents of ‘f’ are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction. Q Cycle Activity: If no skip: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 805 PIC18F06/16Q41 Instruction Set Summary If skip: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation If skip and followed by two-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by three-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE CPFSGT NGREATER: GREATER: REG, 0 Before Instruction PC = address (HERE) W=? REG = ? After Instruction If REG > W; PC = address (GREATER) If REG ≤ W; PC = address (NGREATER) CPFSLT Compare f with W, Skip if f < W Syntax CPFSLT f {,a} Operands 0 ≤ f ≤ 255 a ∈ [0, 1] Operation (f) – (W), skip if (f) < (W) (unsigned comparison) Status Affected None Encoding 0110 © 2020-2021 Microchip Technology Inc. and its subsidiaries 000a Preliminary Datasheet ffff ffff DS40002214E-page 806 PIC18F06/16Q41 Instruction Set Summary ...........continued CPFSLT Compare f with W, Skip if f < W Syntax CPFSLT f {,a} Description Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. If the contents of ‘f’ are less than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction. Q Cycle Activity: If no skip: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation If skip: If skip and followed by two-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by three-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 807 PIC18F06/16Q41 Instruction Set Summary Example: HERE CPFSLT NLESS: LESS: REG, 1 Before Instruction PC = address (HERE) W=? REG = ? After Instruction If REG < W; PC = address (LESS) If REG ≥ W; PC = address (NLESS) DAW Decimal Adjust W Register Syntax DAW Operands None Operation If [(W) > 9] or [DC = 1] then (W) + 6 → W; else (W) → W; If [(W) + DC > 9] or [C = 1] then (W) + 6 + DC → W; else (W) + DC → W Status Affected C 0000 Encoding 0000 0000 0111 Description DAW adjusts the 8-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register W Process Data Write register W Example 1: DAW Before Instruction W = A5h C=0 DC = 0 After Instruction W = 05h C=1 DC = 0 Example 2: DAW © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 808 PIC18F06/16Q41 Instruction Set Summary Before Instruction W = CEh C=0 DC = 0 After Instruction W = 34h C=1 DC = 0 DECF Decrement f Syntax DECF f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (f) – 1 → dest Status Affected C, DC, N, OV, Z 0000 Encoding Description 01da ffff ffff Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: DECF CNT, 1, 0 Before Instruction CNT = 01h Z=0 After Instruction CNT = 00h Z=1 DECFSZ Decrement f, Skip if 0 Syntax DECFSZ f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 809 PIC18F06/16Q41 Instruction Set Summary ...........continued DECFSZ Decrement f, Skip if 0 Syntax DECFSZ f {,d {,a}} Operation (f) – 1 → dest, skip if result = 0 Status Affected None 0010 Encoding Description 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction. Q Cycle Activity: If no skip: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination No operation No operation No operation No operation If skip: If skip and followed by two-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by three-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination No operation No operation No operation No operation No operation No operation No operation No operation © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 810 PIC18F06/16Q41 Instruction Set Summary No operation No operation No operation No operation Example: HERE DECFSZ GOTO CONTINUE CNT, 1, 1 LOOP Before Instruction CNT = ? PC = address (HERE) After Instruction CNT = CNT – 1 If CNT = 0; PC = address (CONTINUE) If CNT ≠ 0; PC = address (HERE + 2) DCFSNZ Decrement f, Skip if not 0 Syntax DCFSNZ f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (f) – 1 → dest, skip if result ≠ 0 Status Affected None 0100 Encoding Description 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is not ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction. Q Cycle Activity: If no skip: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination If skip: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 811 PIC18F06/16Q41 Instruction Set Summary No operation No operation No operation No operation If skip and followed by two-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by three-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE DCFSNZ ZERO: NZERO: TEMP, 1, 0 Before Instruction TEMP = ? PC = address (HERE) After Instruction TEMP = TEMP – 1 If TEMP = 0; PC = address (ZER0) If TEMP ≠ 0; PC = address (NZERO) GOTO Unconditional Branch Syntax GOTO k Operands 0 ≤ k ≤ 1048575 Operation k → PC Status Affected None Encoding 1st word (k) 2nd word (k) 1110 1111 k7kkk kkkk0 1111 k19kkk kkkk kkkk8 Description GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value ‘k’ is loaded into PC. GOTO is always a two-cycle instruction. Words 2 Cycles 2 Q Cycle Activity: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 812 PIC18F06/16Q41 Instruction Set Summary Q1 Q2 Q3 Q4 Decode Read literal ‘k’ No operation Read literal ‘k’ Write to PC No operation No operation No operation No operation Example: HERE GOTO THERE Before Instruction PC = address (HERE) After Instruction PC = address (THERE) INCF Increment f Syntax INCF f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (f) + 1 → dest Status Affected C, DC, N, OV, Z 0010 Encoding Description 10da ffff ffff The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z=0 C=? DC = ? After Instruction CNT = 00h Z=1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 813 PIC18F06/16Q41 Instruction Set Summary C=1 DC = 1 INCFSZ Increment f, Skip if 0 Syntax INCFSZ f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (f) + 1 → dest, skip if result = 0 Status Affected None 0011 Encoding Description 11da ffff ffff The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction. Q Cycle Activity: If no skip: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination No operation No operation No operation No operation If skip: If skip and followed by two-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by three-word instruction: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 814 PIC18F06/16Q41 Instruction Set Summary Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE INCFSZ NZERO: ZERO: CNT, 1, 0 Before Instruction CNT = ? PC = address (HERE) After Instruction CNT = CNT + 1 If CNT = 0; PC = address (ZERO) If CNT ≠ 0; PC = address (NZERO) INFSNZ Increment f, Skip if not 0 Syntax INFSNZ f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (f) + 1 → dest, skip if result ≠ 0 Status Affected None 0100 Encoding Description 10da ffff ffff The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is not ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction. Q Cycle Activity: If no skip: Q1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Q2 Q3 Preliminary Datasheet Q4 DS40002214E-page 815 PIC18F06/16Q41 Instruction Set Summary Decode Read register ‘f’ Process Data Write to destination Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination No operation No operation No operation No operation If skip: If skip and followed by two-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by three-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE INFSNZ ZERO: NZERO: REG, 1, 0 Before Instruction REG = ? PC = address (HERE) After Instruction REG = REG + 1 If REG = 0; PC = address (ZER0) If REG ≠ 0; PC = address (NZERO) IORLW Inclusive OR Literal with W Syntax IORLW k Operands 0 ≤ k ≤ 255 Operation (W) .OR. k → W Status Affected N, Z 0000 Encoding 1001 kkkk kkkk Description The contents of W are ORed with the 8-bit literal ‘k’. The result is placed in W. Words 1 Cycles 1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 816 PIC18F06/16Q41 Instruction Set Summary Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: IORLW 35h Before Instruction W = 9Ah After Instruction W = B5h IORWF Inclusive OR W with f Syntax IORWF f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (W) .OR. (f) → dest Status Affected N, Z 0001 Encoding Description 00da ffff ffff Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 817 PIC18F06/16Q41 Instruction Set Summary LFSR Load FSR Syntax LFSR fn, k Operands 0 ≤ fn ≤ 2 0 ≤ k ≤ 16383 Operation k → FSRfn Status Affected None Encoding 1110 1110 00fnfn k13kkk10 1111 00k9k kkkk kkkk0 Description The 14-bit literal ‘k’ is loaded into the File Select Register ‘fn’. Words 2 Cycles 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write literal ‘k’ to FSRfn No operation Read literal ‘k’ No operation Write literal ‘k’ to FSRfn Example: LFSR 2, 3ABh Before Instruction FSR2H = ? FSR2L = ? After Instruction FSR2H = 03h FSR2L = ABh MOVF Move f Syntax MOVF f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (f) → dest Status Affected N, Z Encoding Description 0101 00da ffff ffff The contents of register ‘f’ are moved to a destination. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 818 PIC18F06/16Q41 Instruction Set Summary ...........continued MOVF Move f Syntax MOVF f {,d {,a}} Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h MOVFF Move f to f Syntax MOVFF fs, fd Operands 0 ≤ fs ≤ 4095 0 ≤ fd ≤ 4095 Operation (fs) → fd Status Affected None Encoding Description 1100 fsfsfsfs fsfsfsfs fsfsfsfs 1111 fdfdfdfd fdfdfdfd fdfdfdfd The contents of source register ‘fs’ are moved to destination register ‘fd’. Location of source ‘fs’ can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination ‘fd’ can also be anywhere from 000h to FFFh. MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Note:  MOVFF has curtailed the source and destination range to the lower 4 Kbyte space of memory (Banks 1 through 15). For everything else, use MOVFFL. Words 2 Cycles 2 Q Cycle Activity: Q1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Q2 Q3 Preliminary Datasheet Q4 DS40002214E-page 819 PIC18F06/16Q41 Instruction Set Summary Decode Read register ‘fs’ Process Data No operation Decode No operation No dummy read No operation Write register ‘fd’ Example: MOVFF REG1, REG2 Before Instruction Address of REG1 = 100h Address of REG2 = 200h REG1 = 33h REG2 = 11h After Instruction Address of REG1 = 100h Address of REG2 = 200h REG1 = 33h REG2 = 33h MOVFFL Move f to f (Long Range) Syntax MOVFFL fs, fd Operands 0 ≤ fs ≤ 16383 0 ≤ fd ≤ 16383 Operation (fs) → fd Status Affected None Encoding Description 0000 0000 0110 fsfsfsfs 1111 fsfsfsfs fsfsfsfs fsfsfdfd 1111 fdfdfdfd fdfdfdfd fdfdfdfd The contents of source register ‘fs’ are moved to destination register ‘fd’. Location of source ‘fs’ can be anywhere in the 16 Kbyte data space (0000h to 3FFFh) and location of destination ‘fd’ can also be anywhere from 0000h to 3FFFh. Either source or destination can be W (a useful special situation). MOVFFL is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFFL instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Words 3 Cycles 3 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation Decode Read register ‘fs’ Process Data No operation Decode No operation No dummy read No operation Write register ‘fd’ © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 820 PIC18F06/16Q41 Instruction Set Summary Example: MOVFFL 2000h, 200Ah Before Instruction Contents of 2000h = 33h Contents of 200Ah = 11h After Instruction Contents of 2000h = 33h Contents of 200Ah = 33h MOVLB Move Literal to BSR Syntax MOVLB k Operands 0 ≤ k ≤ 63 Operation k → BSR Status Affected None 0000 Encoding 0001 00kk kkkk Description The 6-bit literal ‘k’ is loaded into the Bank Select Register (BSR). The value of BSR always remains ‘0’. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to BSR Example: MOVLB 5 Before Instruction BSR = 02h After Instruction BSR = 05h MOVLW Move Literal to W Syntax MOVLW k Operands 0 ≤ k ≤ 255 Operation k→W Status Affected None 0000 Encoding 1110 Description The 8-bit literal ‘k’ is loaded into W. Words 1 Cycles 1 kkkk kkkk Q Cycle Activity: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 821 PIC18F06/16Q41 Instruction Set Summary Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: MOVLW 5Ah Before Instruction W=? After Instruction W = 5Ah MOVWF Move W to f Syntax MOVWF f {,a} Operands 0 ≤ f ≤ 255 a ∈ [0, 1] Operation (W) → f Status Affected None 0110 Encoding Description 111a ffff ffff Move data from W to register ‘f’. Location ‘f’ can be anywhere in the 256-byte bank. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read W Process Data Write register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh MULLW Multiply literal with W Syntax MULLW k Operands 0 ≤ k ≤ 255 Operation (W) x k → PRODH:PRODL © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 822 PIC18F06/16Q41 Instruction Set Summary ...........continued MULLW Multiply literal with W Syntax MULLW k Status Affected None 0000 Encoding Description 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write registers PRODH:PRODL Example: MULLW 0C4h Before Instruction W = E2h PRODH = ? PRODL = ? After Instruction W = E2h PRODH = ADh PRODL = 08h MULWF Multiply W with f Syntax MULWF f {,a} Operands 0 ≤ f ≤ 255 a ∈ [0, 1] Operation (W) x (f) → PRODH:PRODL Status Affected None Encoding 0000 © 2020-2021 Microchip Technology Inc. and its subsidiaries 001a Preliminary Datasheet ffff ffff DS40002214E-page 823 PIC18F06/16Q41 Instruction Set Summary ...........continued MULWF Multiply W with f Syntax MULWF f {,a} Description An unsigned multiplication is carried out between the contents of W and the register file location ‘f’. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and ‘f’ are unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write registers PRODH:PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h NEGF Negate f Syntax NEGF f {,a} Operands 0 ≤ f ≤ 255 a ∈ [0, 1] Operation (f) + 1 → f Status Affected N, OV, C, DC, Z Encoding 0110 © 2020-2021 Microchip Technology Inc. and its subsidiaries 110a Preliminary Datasheet ffff ffff DS40002214E-page 824 PIC18F06/16Q41 Instruction Set Summary ...........continued NEGF Negate f Syntax NEGF f {,a} Description Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h] NOP No Operation Syntax NOP Operands None Operation No operation Status Affected None Encoding 0000 0000 0000 0000 1111 xxxx xxxx xxxx Description No operation. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation Example: None. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 825 PIC18F06/16Q41 Instruction Set Summary POP Pop Top of Return Stack Syntax POP Operands None Operation (TOS) → bit bucket Status Affected None 0000 Encoding 0000 0000 0110 Description The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. (See the PUSH instruction description). Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation POP TOS value No operation Example: POP GOTO NEW Before Instruction TOS = 0031A2h Stack (1 level down) = 014332h After Instruction TOS = 014332h PC = address (NEW) PUSH Push Top of Return Stack Syntax PUSH Operands None Operation (PC) + 2 → TOS Status Affected None 0000 Encoding 0000 0000 0101 Description The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. (See the POP instruction description). Words 1 Cycles 1 Q Cycle Activity: Q1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Q2 Q3 Preliminary Datasheet Q4 DS40002214E-page 826 PIC18F06/16Q41 Instruction Set Summary PUSH PC + 2 onto return stack Decode No operation No operation Example: PUSH Before Instruction TOS = 00345Ah PC = 000124h After Instruction TOS = 000126h PC = 000126h Stack (1 level down) = 00345Ah RCALL Relative Call Syntax RCALL n Operands -1024 ≤ n ≤ 1023 Operation (PC) + 2 → TOS (PC) + 2 + 2n → PC Status Affected None 1101 Encoding 1nnn nnnn nnnn Description Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the two’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words 1 Cycles 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ PUSH PC to stack Process Data Write to PC No operation No operation No operation No operation Example: HERE RCALL Jump Before Instruction PC = address (HERE) After Instruction PC = address (Jump) TOS = address (HERE + 2) RESET Reset Syntax RESET Operands None © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 827 PIC18F06/16Q41 Instruction Set Summary ...........continued RESET Reset Syntax RESET Operation Reset all registers and flags that are affected by a MCLR Reset. Status Affected All 0000 Encoding 0000 1111 Description This instruction provides a way to execute a MCLR Reset by software. Words 1 Cycles 1 1111 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Start Reset No operation No operation Example: RESET Before Instruction All Registers = ? All Flags = ? After Instruction All Registers = Reset Value All Flags = Reset Value RETFIE Return from Interrupt Syntax RETFIE {s} Operands s ∈ [0, 1] Operation (TOS) → PC If s = 1, context is restored into WREG, STATUS, BSR, FSR0H, FSR0L, FSR1H, FSR1L, FSR2H, FSR2L, PRODH, PRODL, PCLATH and PCLATU registers from the corresponding shadow registers. If s = 0, there is no change in status of any register. PCLATU, PCLATH are unchanged. Status Affected Encoding STAT bits in INTCONx register 0000 © 2020-2021 Microchip Technology Inc. and its subsidiaries 0000 Preliminary Datasheet 0001 000s DS40002214E-page 828 PIC18F06/16Q41 Instruction Set Summary ...........continued RETFIE Return from Interrupt Syntax RETFIE {s} Description Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority Global Interrupt Enable bit. If ‘s’ = 1, the contents of the shadow registers WREG_SHAD, STATUS_SHAD, BSR_SHAD, FSR0H_SHAD, FSR0L_SHAD, FSR1H_SHAD, FSR1L_SHAD, FSR2H_SHAD, FSR2L_SHAD, PRODH_SHAD, PRODL_SHAD, PCLATH_SHAD and PCLATU_SHAD are loaded into corresponding registers. There are two sets of shadow registers, main context and low context. The set retrieved on RETFIE instruction execution depends on what the state of operation of the CPU was when RETFIE was executed. If ‘s’ = 0, no update of these registers occurs (default). The upper and high address latches (PCLATU/H) remain unchanged. Words 1 Cycles 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data POP PC from stack No operation No operation No operation No operation Example: RETFIE 1 After Instruction PC = (TOS) WREG = (WREG_SHAD) BSR = (BSR_SHAD) STATUS = (STATUS_SHAD) FSR0H/L = (FSR0H/L_SHAD) FSR1H/L = (FSR1H/L_SHAD) FSR2H/L = (FSR2H/L_SHAD) PRODH/L = (PRODH/L_SHAD) PCLATH/U = (PCLATH/U_SHAD) RETLW Return Literal to W Syntax RETLW k Operands 0 ≤ k ≤ 255 Operation k→W (TOS) → PC PCLATU, PCLATH are unchanged Status Affected None 0000 Encoding 1100 kkkk kkkk Description W is loaded with the 8-bit literal ‘k’. The Program Counter is loaded from the top of the stack (the return address). The upper and high address latches (PCLATU/H) remain unchanged. Words 1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 829 PIC18F06/16Q41 Instruction Set Summary ...........continued RETLW Return Literal to W Syntax RETLW k Cycles 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data POP PC from stack Write to W No operation No operation No operation No operation Example: CALL BACK : : TABLE ADDWF RETLW RETLW : : RETLW TABLE ; W contains table offset value ; W now has table value (after RETLW) PCL k0 k1 ; W = offset ; Begin table ; kn ; End of table Before Instruction W = 07h After Instruction W = value of kn RETURN Return from Subroutine Syntax RETURN {s} Operands s ∈ [0, 1] Operation (TOS) → PC If s = 1 (WREG_CSHAD) → WREG (STATUS_CSHAD) → STATUS (BSR_CSHAD) → BSR PCLATU, PCLATH are unchanged Status Affected None 0000 Encoding 0000 0001 001s Description Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the Program Counter. If ‘s’ = 1, the contents of the shadow registers WREG_CSHAD, STATUS_CSHAD and BSR_CSHAD, are loaded into their corresponding registers. If ‘s’ = 0, no update of these registers occurs (default). The upper and high address latches (PCLATU/H) remain unchanged. Words 1 Cycles 2 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 830 PIC18F06/16Q41 Instruction Set Summary Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data POP PC from stack No operation No operation No operation No operation Example: RETURN 1 After Instruction PC = (TOS) WREG = (WREG_CSHAD) BSR = (BSR_CSHAD) STATUS = (STATUS_CSHAD) RLCF Rotate Left f through Carry Syntax RLCF f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (f) → dest (f) → C (C) → dest Status Affected C, N, Z 0011 Encoding Description 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. C Words 1 Cycles 1 register f Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 [E6h] W=? C=0 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 831 PIC18F06/16Q41 Instruction Set Summary After Instruction REG = 1110 0110 [E6h] W = 1100 1100 [CCh] C=1 RLNCF Rotate Left f (No Carry) Syntax RLNCF f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (f) → dest (f) → dest Status Affected N, Z 0100 Encoding Description 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. register f Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 [ABh] After Instruction REG = 0101 0111 [57h] RRCF Rotate Right f through Carry Syntax RRCF f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (f) → dest (f) → C (C) → dest © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 832 PIC18F06/16Q41 Instruction Set Summary ...........continued RRCF Rotate Right f through Carry Syntax RRCF f {,d {,a}} Status Affected C, N, Z 0011 Encoding Description 00da ffff ffff The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. C Words 1 Cycles 1 register f Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: RRCF REG, 0, 0 Before Instruction REG = 1110 0110 [E6h] W=? C=0 After Instruction REG = 1110 0110 [E6h] W = 0111 0011 [73h] C=0 RRNCF Rotate Right f (No Carry) Syntax RRNCF f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (f) → dest (f) → dest Status Affected N, Z Encoding 0100 © 2020-2021 Microchip Technology Inc. and its subsidiaries 00da Preliminary Datasheet ffff ffff DS40002214E-page 833 PIC18F06/16Q41 Instruction Set Summary ...........continued RRNCF Rotate Right f (No Carry) Syntax RRNCF f {,d {,a}} Description The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. register f Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 [D7h] After Instruction REG = 1110 1011 [EBh] Example 2: RRNCF REG, 0, 0 Before Instruction REG = 1101 0111 [D7h] W=? After Instruction REG = 1101 0111 [D7h] W = 1110 1011 [EBh] SETF Set f Syntax SETF f {,a} Operands 0 ≤ f ≤ 255 a ∈ [0, 1] Operation FFh → f Status Affected None Encoding 0110 © 2020-2021 Microchip Technology Inc. and its subsidiaries 100a Preliminary Datasheet ffff ffff DS40002214E-page 834 PIC18F06/16Q41 Instruction Set Summary ...........continued SETF Set f Syntax SETF f {,a} Description The contents of the specified register ‘f’ are set to FFh. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: SETF REG, 1 Before Instruction REG = 5Ah After Instruction REG = FFh SLEEP Enter Sleep Mode Syntax SLEEP Operands None Operation 00h → WDT 1 → TO 0 → PD Status Affected TO, PD 0000 Encoding 0000 0000 0011 Description The Power-down Status (PD) bit is cleared. The Time-Out Status TO) bit is set. Watchdog Timer is cleared. The processor is put into Sleep mode with the oscillator stopped. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data Go to Sleep Example: SLEEP © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 835 PIC18F06/16Q41 Instruction Set Summary Before Instruction TO = ? PD = ? After Instruction TO = 1 † PD = 0 † If WDT causes wake-up, this bit is cleared. SUBFSR Subtract Literal from FSR Syntax SUBFSR fn, k Operands 0 ≤ k ≤ 63 fn ∈ [0, 1, 2] Operation (FSRfn) – k → FSRfn Status Affected None 1110 Encoding 1001 fnfnkk kkkk Description The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘fn’. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to FSR Example: SUBFSR 2, 23h Before Instruction FSR2 = 03FFh After Instruction FSR2 = 03DCh SUBFWB Subtract f from W with Borrow Syntax SUBFWB f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (W) – (f) – (C) → dest Status Affected N, OV, C, DC, Z Encoding 0101 © 2020-2021 Microchip Technology Inc. and its subsidiaries 01da Preliminary Datasheet ffff ffff DS40002214E-page 836 PIC18F06/16Q41 Instruction Set Summary ...........continued SUBFWB Subtract f from W with Borrow Syntax SUBFWB f {,d {,a}} Description Subtract register ‘f’ and Carry flag (Borrow) from W (two’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example 1: SUBFWB REG, 1, 0 Before Instruction REG = 03h W = 02h C=1 After Instruction REG = FFh (two’s complement) W = 02h C=0 Z=0 N = 1 (result is negative) Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 02h W = 05h C=1 After Instruction REG = 02h W = 03h C=1 Z=0 N = 0 (result is positive) Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 01h W = 02h C=0 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 837 PIC18F06/16Q41 Instruction Set Summary After Instruction REG = 00h W = 02h C=1 Z = 1 (result is zero) N=0 SUBLW Subtract W from Literal Syntax SUBLW k Operands 0 ≤ k ≤ 255 Operation k – (W) → W Status Affected N, OV, C, DC, Z 0000 Encoding 1000 kkkk Description W is subtracted from the 8-bit literal ‘k’. The result is placed in W. Words 1 Cycles 1 kkkk Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example 1: SUBLW 02h Before Instruction W = 01h C=? After Instruction W = 01h C = 1 (result is positive) Z=0 N=0 Example 2: SUBLW 02h Before Instruction W = 02h C=? After Instruction W = 00h C=1 Z = 1 (result is zero) N=0 Example 3: SUBLW 02h Before Instruction W = 03h C=? © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 838 PIC18F06/16Q41 Instruction Set Summary After Instruction W = FFh (two’s complement) C=0 Z=0 N = 1 (result is negative) SUBWF Subtract W from f Syntax SUBWF f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (f) – (W) → dest Status Affected N, OV, C, DC, Z 0101 Encoding Description 11da ffff ffff Subtract W from register ‘f’ (two’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example 1: SUBWF REG, 1, 0 Before Instruction REG = 03h W = 02h C=? After Instruction REG = 01h (two’s complement) W = 02h C = 1 (result is positive) Z=0 N=0 Example 2: SUBWF REG, 0, 0 Before Instruction REG = 02h W = 02h C=? © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 839 PIC18F06/16Q41 Instruction Set Summary After Instruction REG = 02h W = 00h C=1 Z = 1 (result is zero) N=0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 01h W = 02h C=? After Instruction REG = FFh (two’s complement) W = 02h C=0 Z=0 N = 1 (result is negative) SUBWFB Subtract W from f with Borrow Syntax SUBWFB f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (f) – (W) – (C) → dest Status Affected N, OV, C, DC, Z 0101 Encoding Description 10da ffff ffff Subtract W and the Carry flag (Borrow) from register ‘f’ (two’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example 1: SUBWFB REG, 1, 0 Before Instruction REG = 19h (0001 1001) W = 0Dh (0000 1101) C=1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 840 PIC18F06/16Q41 Instruction Set Summary After Instruction REG = 0Ch (0000 1100) W = 0Dh (0000 1101) C = 1 (result is positive) Z=0 N=0 Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C=0 After Instruction REG = 1Bh (0001 1011) W = 00h C=1 Z = 1 (result is zero) N=0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1110) C=1 After Instruction REG = F5h (1111 0101) (two’s complement) W = 0Eh (0000 1110) C=0 Z=0 N = 1 (result is negative) SWAPF Swap f Syntax SWAPF f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (f) → dest (f) → dest Status Affected None 0011 Encoding Description 10da ffff ffff The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 841 PIC18F06/16Q41 Instruction Set Summary ...........continued SWAPF Swap f Syntax SWAPF f {,d {,a}} Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: SWAPF REG, 1, 0 Before Instruction REG = 53h After Instruction REG = 35h TBLRD Table Read Syntax TBLRD TBLRD TBLRD TBLRD Operands None Operation If TBLRD * (Prog Mem (TBLPTR)) → TABLAT TBLPTR – No Change * *+ *+* If TBLRD *+ (Prog Mem (TBLPTR)) → TABLAT (TBLPTR) + 1 → TBLPTR If TBLRD *(Prog Mem (TBLPTR)) → TABLAT (TBLPTR) – 1 → TBLPTR If TBLRD +* (TBLPTR) + 1 → TBLPTR (Prog Mem (TBLPTR)) → TABLAT Status Affected Encoding None 0000 0000 0000 10mm mm=0 mm=1 mm=2 mm=3 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet * *+ *+* DS40002214E-page 842 PIC18F06/16Q41 Instruction Set Summary ...........continued TBLRD Table Read Syntax TBLRD TBLRD TBLRD TBLRD Description This instruction is used to read the contents of Program Memory. To address the program memory, a pointer called Table Pointer (TBLPTR) is used. * *+ *+* The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: Words 1 Cycles 2 • no change (TBLRD *) • post-increment (TBLRD *+) • post-decrement (TBLRD *-) • pre-increment (TBLRD +*) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read Program Memory) No operation No operation (Write TABLAT) Example 1: TBLRD *+ Before Instruction TABLAT = 55h TBLPTR = 00A356h MEMORY (00A356h) = 34h After Instruction TABLAT = 34h TBLPTR = 00A357h Example 2: TBLRD +* Before Instruction TABLAT = AAh TBLPTR = 01A357h MEMORY (01A357h) = 12h MEMORY (01A358h) = 34h After Instruction TABLAT = 34h TBLPTR = 01A358h © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 843 PIC18F06/16Q41 Instruction Set Summary TBLWT Table Write Syntax TBLWT TBLWT TBLWT TBLWT Operands None Operation If TBLWT * (TABLAT) → Holding Register TBLPTR – No Change * *+ *+* If TBLWT *+ (TABLAT) → Holding Register (TBLPTR) + 1 → TBLPTR If TBLWT *(TABLAT) → Holding Register (TBLPTR) – 1 → TBLPTR If TBLWT +* (TBLPTR) + 1 → TBLPTR (TABLAT) → Holding Register Status Affected None 0000 Encoding 0000 0000 11mm mm=0 mm=1 mm=2 mm=3 Description * *+ *+* This instruction uses the three LSBs of TBLPTR to determine which of the eight holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory. (Refer to the “Program Flash Memory” section for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: Words 1 Cycles 2 • no change (TBLWT *) • post-increment (TBLWT *+) • post-decrement (TBLWT *-) • pre-increment (TBLWT +*) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 844 PIC18F06/16Q41 Instruction Set Summary No operation (Read TABLAT) No operation No operation No operation (Write to Holding Register) Example 1: TBLWT *+ Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instruction (table write completion) TABLAT = 55h TBLPTR = 00A357h HOLDING REGISTER (00A356h) = 55h Example 2: TBLWT +* Before Instruction TABLAT = 34h TBLPTR = 01389Ah HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = FFh After Instruction (table write completion) TABLAT = 34h TBLPTR = 01389Bh HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = 34h TSTFSZ Test f, Skip if 0 Syntax TSTFSZ f {,a} Operands 0 ≤ f ≤ 255 a ∈ [0, 1] Operation Skip if f = 0 Status Affected None 0110 Encoding Description 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 (2) Note: Three cycles if skip and followed by a two-word instruction. Four cycles if skip and followed by a three-word instruction. Q Cycle Activity: If no skip: © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 845 PIC18F06/16Q41 Instruction Set Summary Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation If skip: If skip and followed by two-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by three-word instruction: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE TSTFSZ NZERO: ZERO: CNT, 1 Before Instruction PC = address (HERE) After Instruction If CNT = 0; PC = address (ZERO) If CNT ≠ 0; PC = address (NZERO) XORLW Exclusive OR Literal with W Syntax XORLW k Operands 0 ≤ k ≤ 255 Operation (W) .XOR. k → W Status Affected N, Z 0000 Encoding 1010 kkkk kkkk Description The contents of W are XORed with the 8-bit literal ‘k’. The result is placed in W. Words 1 Cycles 1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 846 PIC18F06/16Q41 Instruction Set Summary Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: XORLW 0AFh Before Instruction W = B5h After Instruction W = 1Ah XORWF Exclusive OR W with f Syntax XORWF f {,d {,a}} Operands 0 ≤ f ≤ 255 d ∈ [0, 1] a ∈ [0, 1] Operation (W) .XOR. (f) → dest Status Affected N, Z 0001 Encoding Description 10da ffff ffff Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 847 PIC18F06/16Q41 Instruction Set Summary 45.2 Extended Instruction Set In addition to the standard instruction set, PIC18 devices also provide an optional extension to the core CPU functionality. The added features include additional instructions that augment Indirect and Indexed Addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions. The additional features of the extended instruction set are disabled by default. To enable them, users must set the XINST Configuration bit. The instructions in the extended set can all be classified as literal operations, which either manipulate the File Select registers, or use them for Indexed Addressing. Two of the standard instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2 as extended instructions. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. The extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include: • • • • Dynamic allocation and deallocation of software stack space when entering and leaving subroutines Function pointer invocation Software Stack Pointer manipulation Manipulation of variables located in a software stack A summary of the instructions in the extended instruction set is provided in 45.2.1 Extended Instruction Syntax. Detailed descriptions are provided in 45.2.2 Extended Instruction Set. The opcode field descriptions in Table 45-1 apply to both the standard and extended PIC18 instruction sets. Important:  The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler. Important:  Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. Refer to 45.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 45.2.1 Extended Instruction Syntax Most of the extended instructions use indexed arguments, using one of the File Select registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of Indexed Addressing, it is enclosed in square brackets (“[ ]”). This is done to indicate that the argument is used as an index or offset. MPASM™ assembler will flag an error if it determines that an index or offset value is not bracketed. When the extended instruction set is enabled, brackets are also used to indicate index arguments in byteoriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see 45.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 848 and its subsidiaries © 2020-2021 Microchip Technology Inc. Table 45-3. Extensions to the PIC18 Instruction Set Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes None 1, 3 None 2, 3, 4 None 2, 3 None 2, 3 rotatethispage90 ADDULNK k Add literal to FSR2 and return 2 MOVSF zs, fd Move zs (12-bit source) to fd (12-bit destination) 2 zs, fd Move zs (14-bit source) to fd (14-bit destination) MOVSFL 3 Preliminary Datasheet 1110 1000 11kk kkkk 1110 1011 0zszszs zszszszs 1111 fdfdfdfd fdfdfdfd fdfdfdfd 0000 0000 0000 0010 1111 xxxzs zszszszs zszsfdfd 1111 fdfdfdfd fdfdfdfd fdfdfdfd 1110 1011 1zszszs zszszszs 1111 xxxx xzdzdzd zdzdzdzd MOVSS zs, zd Move zs (source) to zd (destination) 2 PUSHL k Store literal at FSR2, decrement FSR2 1 1110 1010 kkkk kkkk None 3 SUBULNK k Subtract literal from FSR2 and return 2 1110 1001 11kk kkkk None 1, 3 Notes:  1. If Program Counter (PC) is modified or a conditional test is true, the instruction requires an additional cycle. The extra cycle is executed as a NOP. 2. PIC18F06/16Q41 DS40002214E-page 849 Instruction Set Summary 3. 4. Some instructions are multi-word instructions. The extra words of these instructions will be decoded as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. Only available when extended instruction set is enabled. fs and fd do not cover the full memory range. 2 MSbs of bank selection are forced to 0b00 to limit the range of these instructions to lower 4k addressing space. PIC18F06/16Q41 Instruction Set Summary 45.2.2 Extended Instruction Set Important:  All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s) ADDULNK Add Literal to FSR2 and Return Syntax ADDULNK k Operands 0 ≤ k ≤ 63 Operation (FSR2) + k → FSR2 (TOS) → PC Status Affected None 1110 Encoding 1000 11kk kkkk Description The 6-bit literal ‘k’ is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the ADDFSR instruction, where fn = 3 (binary ‘11’); it operates only on FSR2. Words 1 Cycles 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to destination No operation No operation No operation No operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) MOVSF Move Indexed to f Syntax MOVSF [zs], fd Operands 0 ≤ zs ≤ 127 0 ≤ fd ≤ 4095 Operation ((FSR2) + zs) → fd Status Affected None Encoding 1110 1011 0zszszs zszszszs 1111 fdfdfdfd fdfdfdfd fdfdfdfd © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 850 PIC18F06/16Q41 Instruction Set Summary ...........continued MOVSF Move Indexed to f Syntax MOVSF [zs], fd Description The contents of the source register are moved to destination register ‘fd’. The actual address of the source register is determined by adding the 7-bit literal offset ‘zs’ in the first word to the value of FSR2. The address of the destination register is specified by the 12-bit literal ‘fd’ in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh). Note:  MOVSF has curtailed the destination range to the lower 4 Kbyte space in memory (Banks 1 through 15). For everything else, use MOVSFL. Words 2 Cycles 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine source address Determine source address Read source register Decode No operation No dummy read No operation Write register ‘fd’ Example: MOVSF [05h], REG2 Before Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 11h Address of REG2 = 100h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h Address of REG2 = 100h MOVSFL Move Indexed to f (Long Range) Syntax MOVSFL [zs], fd Operands 0 ≤ zs ≤ 127 0 ≤ fd ≤ 16383 Operation ((FSR2) + zs) → fd Status Affected None Encoding 0000 0000 0110 0010 1111 xxxzs zszszszs zszsfdfd 1111 fdfdfdfd fdfdfdfd fdfdfdfd © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 851 PIC18F06/16Q41 Instruction Set Summary ...........continued MOVSFL Move Indexed to f (Long Range) Syntax MOVSFL [zs], fd Description The contents of the source register are moved to destination register ‘fd’. The actual address of the source register is determined by adding the 7-bit literal offset ‘zs’ in the first word to the value of FSR2 (14 bits). The address of the destination register is specified by the 14-bit literal ‘fd’ in the second word. Both addresses can be anywhere in the 16 Kbyte data space (0000h to 3FFFh). The MOVSFL instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. Words 3 Cycles 3 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation Decode Read source register Process Data No operation Decode No operation No dummy read No operation Write register ‘fd’ Example: MOVSFL [05h], REG2 Before Instruction FSR2 = 2080h Contents of 2085h = 33h REG2 = 11h Address of REG2 = 2000h After Instruction FSR2 = 2080h Contents of 2085h = 33h REG2 = 33h Address of REG2 = 2000h MOVSS Move Indexed to Indexed Syntax MOVSS [zs], [zd] Operands 0 ≤ zs ≤ 127 0 ≤ zd ≤ 127 Operation ((FSR2) + zs) → ((FSR2) + zd) Status Affected None Encoding 1110 1011 1zszszs zszszszs 1111 xxxx xzdzdzd zdzdzdzd © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 852 PIC18F06/16Q41 Instruction Set Summary ...........continued MOVSS Move Indexed to Indexed Syntax MOVSS [zs], [zd] Description The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets ‘zs’ or ‘zd’ respectively to the value of FSR2. Both registers can be located anywhere in the 16 Kbyte data memory space (0000h to 3FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the resultant destination address points to an indirect addressing register, the instruction will execute as a NOP. Words 2 Cycles 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine source address Determine source address Read source register Decode Determine destination address Determine destination address Write to destination register Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h PUSHL Store Literal at FSR2, Decrement FSR2 Syntax PUSHL k Operands 0 ≤ k ≤ 255 Operation k → FSR2 (FSR2) – 1 → FSR2 Status Affected None 1111 Encoding 1010 kkkk kkkk Description The 8-bit literal ‘k’ is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack. Words 1 Cycles 1 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 853 PIC18F06/16Q41 Instruction Set Summary Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to destination Example: PUSHL 08h Before Instruction FSR2 = 01ECh Contents of 01ECh = 00h After Instruction FSR2 = 01EBh Contents of 01ECh = 08h SUBULNK Subtract Literal from FSR2 and Return Syntax SUBULNK k Operands 0 ≤ k ≤ 63 Operation (FSR2) – k → FSR2 (TOS) → PC Status Affected None 1110 Encoding 1001 11kk kkkk Description The 6-bit literal ‘k’ is subtracted from the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where fn = 3 (binary ‘11’); it operates only on FSR2. Words 1 Cycles 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to destination No operation No operation No operation No operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 854 PIC18F06/16Q41 Instruction Set Summary 45.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode Important:  Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to the new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (the “Indexed Addressing with Literal Offset” section in the “Memory Organization” chapter). This has a significant impact on the way many commands of the standard PIC18 instruction set are interpreted. When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: Either as a location in the Access Bank (‘a’ = 0), or in a GPR bank designated by the BSR (‘a’ = 1). When the extended instruction set is enabled and ‘a’ = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions using the Access RAM bit as an argument – that is, all byte-oriented and bit-oriented instructions, or almost half of the core PIC18 instructions – may behave differently when the extended instruction set is enabled. When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines to preserve the Stack Pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see 45.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands). Although the Indexed Literal Offset Addressing mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset Addressing mode are provided in 45.2.4 Considerations when Enabling the Extended Instruction Set to show how execution is affected. The operand conditions shown in the examples are applicable to all instructions of these types. Related Links 9.6 Data Memory and the Extended Instruction Set 45.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands When the extended instruction set is enabled, the file register argument, ‘f’, in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value, ‘k’. As already noted, this occurs only when ‘f’ is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets (“[ ]”). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within brackets, will generate an error in the MPASM assembler. If the index argument is properly bracketed for Indexed Literal Offset Addressing, the Access RAM argument is never specified; it will automatically be assumed to be ‘0’. This is in contrast to standard operation (extended instruction set disabled) when ‘a’ is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM assembler. The destination argument, ‘d’, functions as before. In the latest versions of the MPASM™ assembler, language support for the extended instruction set must be explicitly invoked. This is done with either the command-line option, /y, or the PE directive in the source listing. Related Links 9.6 Data Memory and the Extended Instruction Set 45.2.4 Considerations when Enabling the Extended Instruction Set It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 855 PIC18F06/16Q41 Instruction Set Summary Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. When porting an application to a PIC18 device supporting extensions to the instruction set, it is very important to consider the type of code. A large, re-entrant application that is written in ‘C’ and benefits from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. ADDWF Add W to Indexed (Indexed Literal Offset Mode) Syntax ADDWF [k] {,d} Operands 0 ≤ k ≤ 95 d ∈ [0, 1] Operation (W) + ((FSR2) + k) → dest Status Affected N, OV, C, DC, Z 0010 Encoding 01d0 kkkk kkkk Description The contents of W are added to the contents of the register indicated by FSR2, offset by the value ‘k’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to destination Example: ADDWF [OFST] , 0 Before Instruction W = 17h OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction W = 37h Contents of 0A2Ch = 20h BSF Bit Set Indexed (Indexed Literal Offset Mode) Syntax BSF [k], b Operands 0 ≤ k ≤ 95 0≤b≤7 Operation 1 → ((FSR2) + k) Status Affected None Encoding Description 1000 kkkk kkkk Bit ‘b’ of the register indicated by FSR2, offset by the value ‘k’, is set. © 2020-2021 Microchip Technology Inc. and its subsidiaries bbb0 Preliminary Datasheet DS40002214E-page 856 PIC18F06/16Q41 Instruction Set Summary ...........continued BSF Bit Set Indexed (Indexed Literal Offset Mode) Syntax BSF [k], b Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to destination Example: BSF [FLAG_OFST], 7 Before Instruction FLAG_OFST = 0Ah FSR2 = 0A00h Contents of 0A0Ah = 55h After Instruction Contents of 0A0Ah = D5h SETF Set Indexed (Indexed Literal Offset Mode) Syntax SETF [k] Operands 0 ≤ k ≤ 95 Operation FFh → ((FSR2) + k) Status Affected None 0110 Encoding 1000 kkkk kkkk Description The contents of the register indicated by FSR2, offset by the value ‘k’, are set to FFh. Words 1 Cycles 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to destination Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 857 PIC18F06/16Q41 Instruction Set Summary 45.2.5 ® Special Considerations with Microchip MPLAB IDE Tools The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set on the PIC18 devices. This includes the MPLAB XC8 C compiler, MPASM assembler and MPLAB X Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB X IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is ‘0’, disabling the extended instruction set and Indexed Literal Offset Addressing mode. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: • • • A menu option, or dialog box within the environment, that allows the user to configure the language tool and its settings for the project A command-line option A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 858 PIC18F06/16Q41 ICSP™ 46. - In-Circuit Serial Programming™ ICSP™ - In-Circuit Serial Programming™ ICSP programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP programming: • • • • • ICSPCLK ICSPDAT MCLR/VPP VDD VSS In Program/Verify mode the program memory, User IDs and the Configuration bits are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP, refer to the “Family Programming Specification”. 46.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low, then raising the voltage on MCLR/VPP to VIH. 46.2 Low-Voltage Programming Entry Mode ® The Low-Voltage Programming Entry mode allows the PIC Flash MCUs to be programmed using VDD only, without high voltage. When the LVP Configuration bit is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See the MCLR section for more information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode. 46.3 Common Programming Interfaces Connection to a target device is typically done through an ICSP header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6-connector) configuration. See Figure 46-1. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 859 PIC18F06/16Q41 ICSP™ - In-Circuit Serial Programming™ Figure 46-1. ICD RJ-11 Style Connector Interface VDD VPP/MCLR ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 Target VSS PC Board Bottom Side Pin Description 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 46-2. For additional interface recommendations, refer to the specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 46-3 for more information. Figure 46-2. PICkit™ Programmer Style Connector Interface Pin 1 Indicator 1 2 3 4 5 6 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 860 PIC18F06/16Q41 ICSP™ - In-Circuit Serial Programming™ Pin Description(1): 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect Note:  1. The 6-pin header (0.100" spacing) accepts 0.025" square pins. Figure 46-3. Typical Connection for ICSP™ Programming External Programming VDD Signals Device to be Programmed VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 861 PIC18F06/16Q41 Register Summary 47. Address Register Summary Name Bit Pos. 7 7:0 7:0 EN 0x00 ... 0x38 0x39 0x3A 0x3B ... 0x3F 0x40 0x41 0x42 NVMCON0 NVMCON1 NVMLOCK 0x43 NVMADR 0x46 NVMDAT 0x48 0x49 0x4A 0x4B 0x4C 0x4D ... 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E VREGCON BORCON HLVDCON0 HLVDCON1 ZCDCON PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 Reserved MD1CON0 MD1CON1 MD1SRC MD1CARL MD1CARH 7:0 7:0 7:0 7:0 7:0 7:0 SYSCMD C1MD CCP1MD U2MD DMA3MD 7:0 7:0 7:0 7:0 7:0 EN 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 CMOUT CM1CON0 CM1CON1 CM1NCH CM1PCH CM2CON0 CM2CON1 CM2NCH CM2PCH WDTCON0 WDTCON1 WDTPSL WDTPSH WDTTMR DAC1DATL Reserved DAC1CON SPI1RXB SPI1TXB 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 6 5 4 3 2 1 0 Reserved CLKRCON CLKRCLK DC[1:0] DIV[2:0] CLK[3:0] Reserved 7:0 7:0 7:0 7:0 15:8 23:16 7:0 15:8 7:0 7:0 7:0 7:0 7:0 GO WRERR NVMCMD[2:0] NVMLOCK[7:0] NVMADR[7:0] NVMADR[15:8] NVMADR[21:16] NVMDAT[7:0] NVMDAT[15:8] PMSYS[1:0] VREGPM[1:0] BORRDY INTH INTL SBOREN EN OUT RDY SEN OUT POL HLVDMD SMT1MD DSM1MD SPI2MD DMA1MD CRCMD TMR4MD NCO1MD SPI1MD CLC4MD OUT CHPOL OPOL CHSYNC SEL[3:0] INTP INTN CLKRMD TMR1MD ADCMD PWM2MD CLC1MD DAC2MD IOCMD TMR0MD C2MD PWM1MD U3MD DMA4MD CLPOL BIT CLSYNC Reserved 7:0 7:0 7:0 SCANMD TMR3MD ACTMD I2C1MD CLC3MD TMR2MD DAC1MD PWM3MD CLC2MD OPA1MD MS[4:0] CL[3:0] CH[3:0] EN OUT POL EN OUT POL C2OUT HYS INTP NCH[2:0] PCH[2:0] HYS INTP NCH[2:0] PCH[2:0] PS[4:0] C1OUT SYNC INTN SYNC INTN SEN CS[2:0] WINDOW[2:0] PSCNTL[7:0] PSCNTH[7:0] TMR[4:0] STATE PSCNT[17:16] DAC1R[7:0] EN © 2020-2021 Microchip Technology Inc. and its subsidiaries FVRMD ZCDMD CWG1MD U1MD DMA2MD OE[1:0] PSS[1:0] NSS RXB[7:0] TXB[7:0] Preliminary Datasheet DS40002214E-page 862 PIC18F06/16Q41 Register Summary ...........continued Address Name Bit Pos. 0x82 SPI1TCNT 7:0 15:8 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E SPI1CON0 SPI1CON1 SPI1CON2 SPI1STATUS SPI1TWIDTH SPI1BAUD SPI1INTF SPI1INTE SPI1CLK SPI2RXB SPI2TXB 0x8F SPI2TCNT 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A ... 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA ... 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA ... 0xBD 0xBE 0xBF SPI2CON0 SPI2CON1 SPI2CON2 SPI2STATUS SPI2TWIDTH SPI2BAUD SPI2INTF SPI2INTE SPI2CLK 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7 6 5 4 3 2 1 RXRE LSBF SSP SSET CLB 0 TCNTL[7:0] TCNTH[2:0] EN SMP BUSY TXWE CKE SSFLT CKP FST TXBE MST SDIP TXR BMODE SDOP RXR RXBF TWIDTH[2:0] SRMTIF SRMTIE TCZIF TCZIE SOSIF SOSIE BAUD[7:0] EOSIF EOSIE RXOIF TXUIF RXOIE TXUIE CLKSEL[3:0] RXB[7:0] TXB[7:0] TCNTL[7:0] EN SMP BUSY TXWE CKE SSFLT CKP LSBF SSP SSET CLB FST TXBE RXRE TCNTH[2:0] MST SDIP TXR BMODE SDOP RXR RXBF TWIDTH[2:0] SRMTIF SRMTIE TCZIF TCZIE SOSIF SOSIE BAUD[7:0] EOSIF EOSIE RXOIF TXUIF RXOIE TXUIE CLKSEL[3:0] Reserved DAC2DATL Reserved DAC2CON OPA1CON0 OPA1CON1 OPA1CON2 OPA1CON3 OPA1HWC OPA1OFFSET OPA1ORS 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 DAC2R[7:0] EN EN PSS[1:0] UG RESON CPON GSEL[2:0] NCH[2:0] FMS[1:0] OREN HWCH[2:0] NSS SOC[1:0] NSS[2:0] PCH[2:0] PSS[1:0] HWCL[2:0] ORPOL OFFSET[7:0] ORS[4:0] Reserved ACTCON OSCCON1 OSCCON2 OSCCON3 OSCTUNE OSCFRQ OSCSTAT OSCEN PRLOCK SCANPR DMA1PR DMA2PR DMA3PR DMA4PR 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 ACTEN ACTUD ACTLOCK ACTORS NDIV[3:0] CDIV[3:0] NOSC[2:0] COSC[2:0] CSWHOLD SOSCPWR EXTOR EXTOEN HFOR HFOEN ORDY MFOR MFOEN LFOR LFOEN NOSCR TUN[5:0] SOR SOSCEN FRQ[3:0] ADOR ADOEN PLLR PLLEN PRLOCKED PR[2:0] PR[2:0] PR[2:0] PR[2:0] PR[2:0] Reserved MAINPR ISRPR 7:0 7:0 © 2020-2021 Microchip Technology Inc. and its subsidiaries PR[2:0] PR[2:0] Preliminary Datasheet DS40002214E-page 863 PIC18F06/16Q41 Register Summary ...........continued Address Name 0xC0 ... 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 ... 0xE7 0xE8 0xE9 DMASELECT DMAnBUF 0xEA DMAnDCNT CLCDATA CLCSELECT CLCnCON CLCnPOL CLCnSEL0 CLCnSEL1 CLCnSEL2 CLCnSEL3 CLCnGLS0 CLCnGLS1 CLCnGLS2 CLCnGLS3 6 5 4 3 2 1 CLC4OUT CLC3OUT 0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 EN POL G1D4T G2D4T G3D4T G4D4T OUT G1D4N G2D4N G3D4N G4D4N G1D3T G2D3T G3D3T G4D3T INTP G1D3N G2D3N G3D3N G4D3N INTN G4POL D1S[6:0] D2S[6:0] D3S[6:0] D4S[6:0] G1D2T G2D2T G3D2T G4D2T G3POL G1D2N G2D2N G3D2N G4D2N CLC2OUT CLC1OUT SLCT[1:0] MODE[2:0] G2POL G1POL G1D1T G2D1T G3D1T G4D1T G1D1N G2D1N G3D1N G4D1N Reserved DMAnDPTR 0xEE DMAnDSZ 0xF0 DMAnDSA 0xF2 DMAnSCNT 0xF7 7 Reserved 0xEC 0xF4 Bit Pos. DMAnSPTR DMAnSSZ 0xF9 DMAnSSA 0xFC 0xFD 0xFE 0xFF 0x0100 ... 0x01FF 0x0200 0x0201 0x0202 0x0203 0x0204 0x0205 0x0206 0x0207 ... 0x020C 0x020D 0x020E 0x020F 0x0210 DMAnCON0 DMAnCON1 DMAnAIRQ DMAnSIRQ 7:0 7:0 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 23:16 7:0 15:8 7:0 15:8 23:16 7:0 7:0 7:0 7:0 SLCT[2:0] BUF[7:0] DCNT[7:0] DCNT[11:8] DPTR[7:0] DPTR[15:8] DSZ[7:0] DSZ[11:8] DSA[7:0] DSA[15:8] SCNT[7:0] SCNT[11:8] SPTR[7:0] SPTR[15:8] SPTR[21:16] SSZ[7:0] SSZ[11:8] SSA[7:0] SSA[15:8] EN SIRQEN DMODE[1:0] DGO DSTP SMR[1:0] AIRQ[7:0] SIRQ[7:0] SSA[21:16] AIRQEN SMODE[1:0] XIP SSTP Reserved PPSLOCK RA0PPS RA1PPS RA2PPS Reserved RA4PPS RA5PPS 7:0 7:0 7:0 7:0 RA0PPS[5:0] RA1PPS[5:0] RA2PPS[5:0] PPSLOCKED 7:0 7:0 RA4PPS[5:0] RA5PPS[5:0] 7:0 7:0 7:0 7:0 RB4PPS[5:0] RB5PPS[5:0] RB6PPS[5:0] RB7PPS[5:0] Reserved RB4PPS RB5PPS RB6PPS RB7PPS © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 864 PIC18F06/16Q41 Register Summary ...........continued Address Name Bit Pos. 7 6 5 4 3 2 0x0211 0x0212 RC0PPS RC1PPS 7:0 7:0 RC0PPS[5:0] RC1PPS[5:0] 0x0213 0x0214 0x0215 0x0216 0x0217 0x0218 0x0219 ... 0x023D 0x023E 0x023F 0x0240 0x0241 0x0242 0x0243 0x0244 0x0245 0x0246 ... 0x0247 0x0248 0x0249 0x024A ... 0x024E 0x024F 0x0250 0x0251 0x0252 0x0253 0x0254 ... 0x0256 0x0257 0x0258 0x0259 0x025A 0x025B 0x025C ... 0x025D 0x025E 0x025F 0x0260 0x0261 0x0262 0x0263 0x0264 0x0265 ... 0x0268 0x0269 0x026A 0x026B 0x026C 0x026D 0x026E RC2PPS RC3PPS RC4PPS RC5PPS RC6PPS RC7PPS 7:0 7:0 7:0 7:0 7:0 7:0 RC2PPS[5:0] RC3PPS[5:0] RC4PPS[5:0] RC5PPS[5:0] RC6PPS[5:0] RC7PPS[5:0] 1 0 Reserved INT0PPS INT1PPS INT2PPS T0CKIPPS T1CKIPPS T1GPPS T3CKIPPS T3GPPS 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 PORT PORT[1:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] 7:0 7:0 PORT[2:0] PORT[2:0] PIN[2:0] PIN[2:0] 7:0 PORT[2:0] PIN[2:0] 7:0 7:0 7:0 PORT[1:0] PORT[2:0] PORT[1:0] PIN[2:0] PIN[2:0] PIN[2:0] 7:0 7:0 7:0 7:0 7:0 PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] 7:0 7:0 7:0 7:0 7:0 7:0 7:0 PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] 7:0 7:0 7:0 7:0 7:0 7:0 PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PORT[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] Reserved T2INPPS T4INPPS Reserved CCP1PPS Reserved PWM1ERSPPS PWM2ERSPPS PWM3ERSPPS Reserved PWMIN0PPS PWMIN1PPS SMT1WINPPS SMT1SIGPPS CWG1PPS Reserved MD1CARLPPS MD1CARHPPS MD1SRCPPS CLCIN0PPS CLCIN1PPS CLCIN2PPS CLCIN3PPS Reserved ADACTPPS SPI1SCKPPS SPI1SDIPPS SPI1SSPPS SPI2SCKPPS SPI2SDIPPS © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 865 PIC18F06/16Q41 Register Summary ...........continued Address Name Bit Pos. 0x026F 0x0270 SPI2SSPPS I2C1SDAPPS 7:0 7:0 PORT[2:0] PORT[2:0] PIN[2:0] PIN[2:0] 0x0271 0x0272 0x0273 0x0274 0x0275 0x0276 0x0277 0x0278 ... 0x0285 0x0286 0x0287 0x0288 0x0289 0x028A 0x028B I2C1SCLPPS U1RXPPS U1CTSPPS UxRXPPS UxCTSPPS U3RXPPS U3CTSPPS 7:0 7:0 7:0 7:0 7:0 7:0 7:0 PORT[2:0] PORT[1:0] PORT[1:0] PORT PORT PORT[1:0] PORT[1:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] 0x028C I2C1CNT 0x028E 0x028F 0x0290 0x0291 0x0292 0x0293 0x0294 0x0295 0x0296 0x0297 0x0298 0x0299 0x029A 0x029B 0x029C 0x029D 0x029E 0x029F 0x02A0 0x02A1 0x02A2 0x02A3 0x02A4 I2C1ADB0 I2C1ADB1 I2C1ADR0 I2C1ADR1 I2C1ADR2 I2C1ADR3 I2C1CON0 I2C1CON1 I2C1CON2 I2C1ERR I2C1STAT0 I2C1STAT1 I2C1PIR I2C1PIE I2C1BTO I2C1BAUD I2C1CLK I2C1BTOC Reserved U1RXB U1RXCHK U1TXB U1TXCHK 0x02A5 U1P1 0x02A7 7 6 5 4 3 2 1 0 Reserved RB6I2C RB4I2C RC1I2C RC0I2C I2C1RXB I2C1TXB U1P2 0x02A9 U1P3 0x02AB 0x02AC 0x02AD U1CON0 U1CON1 U1CON2 0x02AE U1BRG 0x02B0 0x02B1 0x02B2 0x02B3 0x02B4 U1FIFO U1UIR U1ERRIR U1ERRIE U2RXB 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 SLEW[1:0] SLEW[1:0] SLEW[1:0] SLEW[1:0] EN ACKCNT ACNT BFRE TXWE CNTIF CNTIE TOREC S ACKSTAT FME BCLIF MMA TXBE ACKTIF ACKTIE TOBY32 TH[1:0] TH[1:0] TH[1:0] TH[1:0] RXB[7:0] TXB[7:0] CNT[7:0] CNT[15:8] ADB[7:0] ADB[7:0] ADR[7:0] ADR[6:0] ADR[7:0] ADR[6:0] CSTR MDR MODE[2:0] ACKT P RXO TXU CSD ABD SDAHT[1:0] BFRET[1:0] NACKIF BTOIE BLCIE NACKIE R D RXRE CLRBF RXBF WRIF ADRIF PCIF RSCIF SCIF WRIE ADRIE PCIE RSCIE SCIE TOTIME[5:0] BAUD[7:0] CLK[3:0] BTOC[2:0] RXB[7:0] RXCHK[7:0] TXB[7:0] TXCHK[7:0] P1[7:0] P1[8] P2[7:0] P2[8] P3[7:0] BRGS ON RUNOVF ABDEN TXWRE WUIF TXMTIF TXMTIE STPMD ABDIF PERIF PERIE © 2020-2021 Microchip Technology Inc. and its subsidiaries RSEN ACKDT GCEN BTOIF SMA PU[1:0] PU[1:0] PU[1:0] PU[1:0] RXPOL TXEN RXEN WUE RXBIMD STP[1:0] C0EN BRG[7:0] BRG[15:8] TXBE TXBF RXIDL ABDOVF ABDOVE CERIF FERIF CERIE FERIE RXB[7:0] Preliminary Datasheet P3[8] MODE[3:0] BRKOVR SENDB TXPOL FLO[1:0] XON ABDIE RXBKIF RXBKIE RXBE RXBF RXFOIF RXFOIE TXCIF TXCIE DS40002214E-page 866 PIC18F06/16Q41 Register Summary ...........continued Address Name Bit Pos. 7 6 5 4 3 0x02B5 0x02B6 Reserved U2TXB 7:0 TXB[7:0] 0x02B7 Reserved 0x02B8 U2P1 P1[7:0] 0x02BA U2P2 0x02BC U2P3 0x02BE 0x02BF 0x02C0 U2CON0 U2CON1 U2CON2 0x02C1 U2BRG 0x02C3 0x02C4 0x02C5 0x02C6 0x02C7 0x02C8 0x02C9 0x02CA U2FIFO U2UIR U2ERRIR U2ERRIE U3RXB Reserved U3TXB Reserved 7:0 15:8 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 0x02CB U3P1 0x02CD U3P2 0x02CF U3P3 0x02D1 0x02D2 0x02D3 U3CON0 U3CON1 U3CON2 0x02D4 U3BRG 0x02D6 0x02D7 0x02D8 0x02D9 0x02DA ... 0x02FF U3FIFO U3UIR U3ERRIR U3ERRIE 0x0300 SMT1TMR 0x0303 SMT1CPR 0x0306 SMT1CPW 0x0309 SMT1PR 0x030C 0x030D 0x030E 0x030F 0x0310 0x0311 SMT1CON0 SMT1CON1 SMT1STAT SMT1CLK SMT1SIG SMT1WIN 2 1 0 P2[7:0] P3[7:0] BRGS ON RUNOVF ABDEN TXWRE WUIF TXMTIF TXMTIE STPMD ABDIF PERIF PERIE RXPOL TXEN RXEN WUE RXBIMD STP[1:0] BRG[7:0] BRG[15:8] TXBE TXBF RXIDL ABDOVF ABDOVE CERIF FERIF CERIE FERIE RXB[7:0] 7:0 TXB[7:0] 7:0 15:8 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 P1[7:0] MODE[3:0] BRKOVR SENDB TXPOL FLO[1:0] XON ABDIE RXBKIF RXBKIE RXBE RXBF RXFOIF RXFOIE P2[7:0] P3[7:0] BRGS ON RUNOVF ABDEN TXWRE WUIF TXMTIF TXMTIE STPMD ABDIF PERIF PERIE RXPOL TXEN RXEN WUE RXBIMD STP[1:0] BRG[7:0] BRG[15:8] TXBE TXBF RXIDL ABDOVF ABDOVE CERIF CERIE FERIF FERIE MODE[3:0] BRKOVR SENDB TXPOL FLO[1:0] XON ABDIE RXBKIF RXBKIE RXBE RXBF RXFOIF RXFOIE Reserved 7:0 15:8 23:16 7:0 15:8 23:16 7:0 15:8 23:16 7:0 15:8 23:16 7:0 7:0 7:0 7:0 7:0 7:0 EN GO CPRUP © 2020-2021 Microchip Technology Inc. and its subsidiaries STP REPEAT CPWUP TMR[7:0] TMR[15:8] TMR[23:16] CPR[7:0] CPR[15:8] CPR[23:16] CPW[7:0] CPW[15:8] CPW[23:16] PR[7:0] PR[15:8] PR[23:16] WPOL SPOL RST Preliminary Datasheet CPOL PS[1:0] MODE[3:0] TS WS CSEL[3:0] SSEL[4:0] WSEL[4:0] AS DS40002214E-page 867 PIC18F06/16Q41 Register Summary ...........continued Address Name Bit Pos. 0x0312 TMR1 7:0 15:8 0x0314 0x0315 0x0316 0x0317 0x0318 0x0319 0x031A 0x031B 0x031C 0x031D 0x031E 0x031F 0x0320 0x0321 0x0322 T1CON T1GCON T1GATE T1CLK TMR0L TMR0H T0CON0 T0CON1 T2TMR T2PR T2CON T2HLT T2CLKCON T2RST Reserved 0x0323 TMR3 0x0325 0x0326 0x0327 0x0328 0x0329 0x032A 0x032B 0x032C 0x032D 0x032E 0x032F ... 0x033F T3CON T3GCON T3GATE T3CLK T4TMR T4PR T4CON T4HLT T4CLKCON T4RST 0x0340 CCPRx 0x0342 0x0343 0x0344 ... 0x034B 0x034C 0x034D CCP1CON CCPxCAP 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7 6 5 4 3 2 1 0 SYNC GVAL GSS[4:0] CS[4:0] RD16 ON TMR1[7:0] TMR1[15:8] GE GPOL EN CKPS[1:0] GTM GSPM OUT CS[2:0] ON PSYNC CPOL GGO/DONE TMR0L[7:0] TMR0H[7:0] MD16 ASYNC T2TMR[7:0] T2PR[7:0] OUTPS[3:0] CKPS[3:0] CKPS[2:0] CSYNC OUTPS[3:0] MODE[4:0] CS[3:0] RSEL[4:0] TMR3[7:0] TMR3[15:8] GE GPOL CKPS[1:0] GTM GSPM GGO/DONE SYNC GVAL GSS[4:0] CS[4:0] RD16 ON T4TMR[7:0] T4PR[7:0] ON PSYNC CPOL CKPS[2:0] CSYNC OUTPS[3:0] MODE[4:0] CS[3:0] RSEL[4:0] Reserved 7:0 15:8 7:0 7:0 EN OUT CCPR[7:0] CCPR[15:8] FMT MODE[3:0] CTS[2:0] Reserved CCPTMRS0 Reserved 0x034E CRCDATA 0x0352 CRCOUT 0x0352 CRCSHIFT 0x0352 CRCXOR 0x0356 0x0357 CRCCON0 CRCCON1 7:0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 7:0 C3TSEL[1:0] EN © 2020-2021 Microchip Technology Inc. and its subsidiaries GO BUSY C2TSEL[1:0] CRCDATAL[7:0] CRCDATAH[7:0] CRCDATAU[7:0] CRCDATAT[7:0] CRCOUTL[7:0] CRCOUTH[7:0] CRCOUTU[7:0] CRCOUTT[7:0] CRCSHIFTL[7:0] CRCSHIFTH[7:0] CRCSHIFTU[7:0] CRCSHIFTT[7:0] CRCXORL[7:0] CRCXORH[7:0] CRCXORU[7:0] CRCXORT[7:0] ACCM SETUP[1:0] PLEN[4:0] Preliminary Datasheet C1TSEL[1:0] SHIFTM FULL DS40002214E-page 868 PIC18F06/16Q41 Register Summary ...........continued Address Name Bit Pos. 0x0358 0x0359 CRCCON2 Reserved 7:0 0x035A SCANLADR 0x035D SCANHADR 0x0360 0x0361 0x0362 ... 0x0366 0x0367 0x0368 0x0369 0x036A 0x036B 0x036C 0x036D 0x036E 0x036F 0x0370 0x0371 0x0372 0x0373 0x0374 0x0375 0x0376 0x0377 0x0378 0x0379 SCANCON0 SCANTRIG 0x037A 0x037C 0x037E 0x0380 0x0382 0x0384 ... 0x03BB 0x03BC 0x03BD 0x03BE 0x03BF 0x03C0 0x03C1 0x03C2 0x03C3 0x03C4 0x03C5 ... 0x03D6 0x03D7 0x03D8 7:0 15:8 23:16 7:0 15:8 23:16 7:0 7:0 7 6 5 4 3 2 1 0 DLEN[4:0] EN TRIGEN SGO SCANLADRL[7:0] SCANLADRH[7:0] SCANLADRU[5:0] SCANHADRL[7:0] SCANHADRH[7:0] SCANHADRU[5:0] MREG BURSTMD TSEL[3:0] BUSY Reserved IPR0 IPR1 IPR2 IPR3 IPR4 IPR5 IPR6 IPR7 IPR8 IPR9 IPR10 Reserved STATUS_CSHAD WREG_CSHAD BSR_CSHAD SHADCON STATUS_SHAD WREG_SHAD BSR_SHAD PCLAT_SHAD FSR0_SHAD FSR1_SHAD FSR2_SHAD PROD_SHAD 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 IOCIP CRCIP CLC1IP NVMIP SMT1PWAIP SMT1PRAIP SMT1IP CM1IP DMA1AIP DMA1ORIP DMA1DCNTIP DMA1SCNTIP TMR0IP CCP1IP TMR1GIP TMR1IP PWM1IP PWM1PIP TMR3GIP TMR3IP PWM2IP PWM2PIP CLC2IP CMIP DMA2AIP DMA2ORIP DMA2DCNTIP DMA2SCNTIP PWM3IP PWM3PIP CLC3IP SCANIP CLC4IP DMA3AIP DMA3ORIP DMA3DCNTIP DMA3SCNTIP DMA4AIP DMA4ORIP DMA4DCNTIP DMA4SCNTIP 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 TO PD CSWIP ACTIP OSFIP ADIP HLVDIP ZCDIP TMR2IP U1IP SPI1IP U1EIP SPI2IP CWG1IP I2C1IP U2EIP U3EIP SPI1TXIP U1TXIP SPI2TXIP Z DC C Z DC SHADLO C NCO1IP I2C1EIP U2IP U3IP TMR4IP N OV I2C1TXIP U2TXIP U3TXIP SWIP INT0IP ADTIP SPI1RXIP U1RXIP SPI2RXIP INT1IP I2C1RXIP U2RXIP U3RXIP INT2IP WREG[7:0] BSR[5:0] TO PD N OV WREG[7:0] BSR[5:0] PCLATH[7:0] PCLATU[4:0] FSRL[7:0] FSRH[5:0] FSRL[7:0] FSRH[5:0] FSRL[7:0] FSRH[5:0] PROD[7:0] PROD[15:8] Reserved CWG1CLK CWG1ISM CWG1DBR CWG1DBF CWG1CON0 CWG1CON1 CWG1AS0 CWG1AS1 CWG1STR 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 CS SHUTDOWN AS7E OVRD REN AS6E OVRC 7:0 7:0 EN CPON RDY ISM[3:0] DBR[5:0] DBF[5:0] EN LD IN LSBD[1:0] AS5E AS4E OVRB OVRA POLD POLC LSAC[1:0] AS3E AS2E STRD STRC MODE[2:0] POLB POLA AS1E STRB AS0E STRA Reserved FVRCON ADCP © 2020-2021 Microchip Technology Inc. and its subsidiaries TSEN TSRNG Preliminary Datasheet CDAFVR[1:0] ADFVR[1:0] CPRDY DS40002214E-page 869 PIC18F06/16Q41 Register Summary ...........continued Address Name Bit Pos. 0x03D9 ADLTH 7:0 15:8 LTH[7:0] LTH[15:8] 0x03DB ADUTH 0x03DD ADERR 0x03DF ADSTPT 0x03E1 ADFLTR 0x03E3 ADACC UTH[7:0] UTH[15:8] ERR[7:0] ERR[15:8] STPT[7:0] STPT[15:8] FLTR[7:0] FLTR[15:8] ACC[7:0] ACC[15:8] 0x03E6 0x03E7 ADCNT ADRPT 0x03E8 ADPREV 0x03EA ADRES 0x03EC 0x03ED ADPCH Reserved 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 23:16 7:0 7:0 7:0 15:8 7:0 15:8 7:0 0x03EE ADACQ 0x03F0 ADCAP 0x03F1 ADPRE 0x03F3 0x03F4 0x03F5 0x03F6 0x03F7 0x03F8 0x03F9 0x03FA 0x03FB ... 0x03FF 0x0400 0x0401 0x0402 0x0403 0x0404 0x0405 0x0406 0x0407 0x0408 0x0409 0x040A 0x040B 0x040C 0x040D 0x040E 0x040F 0x0410 0x0411 0x0412 0x0413 0x0414 0x0415 ADCON0 ADCON1 ADCON2 ADCON3 ADSTAT ADREF ADACT ADCLK 7:0 15:8 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7 6 5 4 3 2 1 0 ACC[17:16] CNT[7:0] RPT[7:0] PREV[7:0] PREV[15:8] RES[7:0] RES[15:8] PCH[7:0] ACQ[7:0] ACQ[12:8] CAP[4:0] PRE[7:0] ON PPOL PSIS CONT IPEN AOV UTHR PRE[12:8] FM CS GPOL CRS[2:0] CALC[2:0] LTHR ACLR SOI GO DSEN MD[2:0] TMD[2:0] STAT[2:0] PREF[1:0] MATH NREF ACT[4:0] CS[5:0] Reserved ANSELA WPUA ODCONA SLRCONA INLVLA IOCAP IOCAN IOCAF ANSELB WPUB ODCONB SLRCONB INLVLB IOCBP IOCBN IOCBF ANSELC WPUC ODCONC SLRCONC INLVLC IOCCP 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 ANSELB7 WPUB7 ODCB7 SLRB7 INLVLB7 IOCBP7 IOCBN7 IOCBF7 ANSELC7 WPUC7 ODCC7 SLRC7 INLVLC7 IOCCP7 © 2020-2021 Microchip Technology Inc. and its subsidiaries ANSELB6 WPUB6 ODCB6 SLRB6 INLVLB6 IOCBP6 IOCBN6 IOCBF6 ANSELC6 WPUC6 ODCC6 SLRC6 INLVLC6 IOCCP6 ANSELA5 WPUA5 ODCA5 SLRA5 INLVLA5 IOCAP5 IOCAN5 IOCAF5 ANSELB5 WPUB5 ODCB5 SLRB5 INLVLB5 IOCBP5 IOCBN5 IOCBF5 ANSELC5 WPUC5 ODCC5 SLRC5 INLVLC5 IOCCP5 ANSELA4 WPUA4 ODCA4 SLRA4 INLVLA4 IOCAP4 IOCAN4 IOCAF4 ANSELB4 WPUB4 ODCB4 SLRB4 INLVLB4 IOCBP4 IOCBN4 IOCBF4 ANSELC4 WPUC4 ODCC4 SLRC4 INLVLC4 IOCCP4 ANSELA3 WPUA3 INLVLA3 IOCAP3 IOCAN3 IOCAF3 ANSELA2 WPUA2 ODCA2 SLRA2 INLVLA2 IOCAP2 IOCAN2 IOCAF2 ANSELA1 WPUA1 ODCA1 SLRA1 INLVLA1 IOCAP1 IOCAN1 IOCAF1 ANSELA0 WPUA0 ODCA0 SLRA0 INLVLA0 IOCAP0 IOCAN0 IOCAF0 ANSELC3 WPUC3 ODCC3 SLRC3 INLVLC3 IOCCP3 ANSELC2 WPUC2 ODCC2 SLRC2 INLVLC2 IOCCP2 ANSELC1 WPUC1 ODCC1 SLRC1 INLVLC1 IOCCP1 ANSELC0 WPUC0 ODCC0 SLRC0 INLVLC0 IOCCP0 Preliminary Datasheet DS40002214E-page 870 PIC18F06/16Q41 Register Summary ...........continued Address Name Bit Pos. 7 6 5 4 3 2 1 0 0x0416 0x0417 IOCCN IOCCF 7:0 7:0 IOCCN7 IOCCF7 IOCCN6 IOCCF6 IOCCN5 IOCCF5 IOCCN4 IOCCF4 IOCCN3 IOCCF3 IOCCN2 IOCCF2 IOCCN1 IOCCF1 IOCCN0 IOCCF0 0x0418 ... 0x043F Reserved 0x0440 NCO1ACC 0x0443 NCO1INC 0x0446 0x0447 0x0448 ... 0x0457 0x0458 0x0459 NCO1CON NCO1CLK FSCMCON IVTLOCK 0x045A IVTAD 7:0 15:8 23:16 7:0 15:8 23:16 7:0 7:0 ACC[7:0] ACC[15:8] ACC[19:16] INC[7:0] INC[15:8] INC[19:16] EN OUT POL PFM PWS[2:0] CKS[3:0] Reserved 0x045D IVTBASE 0x0460 0x0461 0x0462 PWM1ERS PWM1CLK PWM1LDS 0x0463 PWM1PR 0x0465 0x0466 0x0467 0x0468 0x0469 0x046A PWM1CPRE PWM1PIPOS PWM1GIR PWM1GIE PWM1CON PWM1S1CFG 0x046B PWM1S1P1 0x046D PWM1S1P2 0x046F 0x0470 0x0471 PWM2ERS PWM2CLK PWM2LDS 0x0472 PWM2PR 0x0474 0x0475 0x0476 0x0477 0x0478 0x0479 PWM2CPRE PWM2PIPOS PWM2GIR PWM2GIE PWM2CON PWM2S1CFG 0x047A PWM2S1P1 0x047C PWM2S1P2 0x047E 0x047F 0x0480 PWM3ERS PWM3CLK PWM3LDS 0x0481 PWM3PR 7:0 7:0 7:0 15:8 23:16 7:0 15:8 23:16 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 15:8 FSCMSFI FSCMPFI FSCMPEV FSCMFFI FSCMFEV IVTLOCKED IVTADL[7:0] IVTADH[7:0] IVTADU[4:0] IVTBASEL[7:0] IVTBASEH[7:0] IVTBASEU[4:0] ERS[3:0] CLK[3:0] LDS[3:0] PR[7:0] PR[15:8] CPRE[7:0] PIPOS[7:0] EN POL2 LD POL1 PPEN S1P2 S1P2 ERSPOL MODE[2:0] S1P1 S1P1 ERSNOW P1[7:0] P1[15:8] P2[7:0] P2[15:8] ERS[3:0] CLK[3:0] LDS[3:0] PR[7:0] PR[15:8] CPRE[7:0] PIPOS[7:0] EN POL2 © 2020-2021 Microchip Technology Inc. and its subsidiaries FSCMSEV LD POL1 PPEN S1P2 S1P2 ERSPOL MODE[2:0] S1P1 S1P1 ERSNOW P1[7:0] P1[15:8] P2[7:0] P2[15:8] ERS[3:0] CLK[3:0] LDS[3:0] PR[7:0] PR[15:8] Preliminary Datasheet DS40002214E-page 871 PIC18F06/16Q41 Register Summary ...........continued Address Name Bit Pos. 0x0483 0x0484 PWM3CPRE PWM3PIPOS 7:0 7:0 0x0485 0x0486 0x0487 0x0488 PWM3GIR PWM3GIE PWM3CON PWM3S1CFG 0x0489 PWM3S1P1 0x048B PWM3S1P2 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 0x048D ... 0x049B 0x049C 0x049D 0x049E ... 0x04A7 0x04A8 0x04A9 0x04AA 0x04AB 0x04AC 0x04AD 0x04AE 0x04AF 0x04B0 0x04B1 0x04B2 0x04B3 0x04B4 0x04B5 0x04B6 0x04B7 0x04B8 0x04B9 0x04BA 0x04BB 0x04BC 0x04BD 0x04BE 0x04BF 0x04C0 0x04C1 ... 0x04C5 0x04C6 0x04C7 0x04C8 0x04C9 ... 0x04CD 0x04CE 0x04CF 0x04D0 0x04D1 ... 0x04D5 0x04D6 7 6 5 4 3 2 1 0 S1P2 S1P2 ERSPOL MODE[2:0] S1P1 S1P1 ERSNOW MPWM3LD MPWM3EN MPWM2LD MPWM2EN MPWM1LD MPWM1EN CSWIE ACTIE OSFIE ADIE HLVDIE ZCDIE TMR2IE U1IE SPI1IE U1EIE SPI2IE CWG1IE I2C1IE U2EIE U3EIE SPI1TXIE U1TXIE SPI2TXIE OSFIF ADIF HLVDIF ZCDIF SPI1IF U1EIF SPI2IF CWG1IF I2C1IF U2EIF U3EIF SPI1TXIF U1TXIF SPI2TXIF LATA2 LATA1 SWIE INT0IE ADTIE SPI1RXIE U1RXIE SPI2RXIE INT1IE I2C1RXIE U2RXIE U3RXIE INT2IE SWIF INT0IF ADTIF SPI1RXIF U1RXIF SPI2RXIF INT1IF I2C1RXIF U2RXIF U3RXIF INT2IF LATA0 LATC3 LATC2 LATC1 LATC0 CPRE[7:0] PIPOS[7:0] EN POL2 LD POL1 PPEN P1[7:0] P1[15:8] P2[7:0] P2[15:8] Reserved PWMLOAD PWMEN 7:0 7:0 Reserved PIE0 PIE1 PIE2 PIE3 PIE4 PIE5 PIE6 PIE7 PIE8 PIE9 PIE10 PIR0 PIR1 PIR2 PIR3 PIR4 PIR5 PIR6 PIR7 PIR8 PIR9 PIR10 LATA LATB LATC 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 IOCIE CRCIE CLC1IE NVMIE SMT1PWAIE SMT1PRAIE SMT1IE CM1IE DMA1AIE DMA1ORIE DMA1DCNTIE DMA1SCNTIE TMR0IE CCP1IE TMR1GIE TMR1IE PWM1IE PWM1PIE TMR3GIE TMR3IE PWM2IE PWM2PIE CLC2IE CM2IE DMA2AIE DMA2ORIE DMA2DCNTIE DMA2SCNTIE PWM3IE PWM3PIE CLC3IE SCANIE CLC4IE DMA3AIE DMA3ORIE DMA3DCNTIE DMA3SCNTIE DMA4AIE DMA4ORIE DMA4DCNTIE DMA4SCNTIE IOCIF CRCIF CLC1IF NVMIF SMT1PWAIF SMT1PRAIF SMT1IF CM1IF DMA1AIF DMA1ORIF DMA1DCNTIF DMA1SCNTIF TMR0IF CCP1IF TMR1GIF TMR1IF PWM1IF PWM1PIF TMR3GIF TMR3IF PWM2IF PWM2PIF CLC2IF CM2IF DMA2AIF DMA2ORIF DMA2DCNTIF DMA2SCNTIF PWM3IF PWM3PIF CLC3IF SCANIF CLC4IF DMA3AIF DMA3ORIF DMA3DCNTIF DMA3SCNTIF DMA4AIF DMA4ORIF DMA4DCNTIF DMA4SCNTIF LATA5 LATA4 LATB7 LATB6 LATB5 LATB4 LATC7 LATC6 LATC5 LATC4 NCO1IE I2C1EIE U2IE U3IE TMR4IE CSWIF ACTIF TMR2IF U1IF NCO1IF I2C1EIF U2IF U3IF TMR4IF I2C1TXIE U2TXIE U3TXIE I2C1TXIF U2TXIF U3TXIF Reserved TRISA TRISB TRISC 7:0 7:0 7:0 TRISA4 TRISB4 TRISC4 TRISA2 TRISA1 TRISA0 TRISB6 TRISC6 TRISA5 TRISB5 TRISC5 Reserved TRISB7 TRISC7 TRISC3 TRISC2 TRISC1 TRISC0 7:0 7:0 7:0 RA4 RB4 RC4 RA2 RA1 RA0 RB6 RC6 RA5 RB5 RC5 RA3 RB7 RC7 RC3 RC2 RC1 RC0 7:0 GIE/GIEH GIEL IPEN INT2EDG INT1EDG INT0EDG Reserved PORTA PORTB PORTC Reserved INTCON0 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 872 PIC18F06/16Q41 Register Summary ...........continued Address Name Bit Pos. 0x04D7 0x04D8 INTCON1 STATUS 7:0 7:0 0x04D9 FSR2 0x04DB 0x04DC 0x04DD 0x04DE 0x04DF 0x04E0 PLUSW2 PREINC2 POSTDEC2 POSTINC2 INDF2 BSR 0x04E1 FSR1 0x04E3 0x04E4 0x04E5 0x04E6 0x04E7 0x04E8 PLUSW1 PREINC1 POSTDEC1 POSTINC1 INDF1 WREG 0x04E9 FSR0 0x04EB 0x04EC 0x04ED 0x04EE 0x04EF 0x04F0 0x04F1 0x04F2 PLUSW0 PREINC0 POSTDEC0 POSTINC0 INDF0 PCON0 PCON1 CPUDOZE 0x04F3 PROD 0x04F5 TABLAT 0x04F6 TBLPTR 0x04F9 PCL 0x04FA PCLAT 0x04FC STKPTR 0x04FD TOS 0x0500 ... 0x2FFFFF 0x300000 0x300001 0x300002 0x300003 0x300004 0x300005 0x300006 0x300007 0x300008 0x300009 ... 0x3FFFFB CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 CONFIG7 CONFIG8 CONFIG9 0x3FFFFC REVISIONID 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 15:8 23:16 7:0 7:0 15:8 7:0 7:0 15:8 23:16 7 6 5 4 TO PD N 3 2 1 0 OV Z DC C STAT[1:0] FSRL[7:0] FSRH[5:0] PLUSW[7:0] PREINC[7:0] POSTDEC[7:0] POSTINC[7:0] INDF[7:0] BSR[5:0] FSRL[7:0] FSRH[5:0] PLUSW[7:0] PREINC[7:0] POSTDEC[7:0] POSTINC[7:0] INDF[7:0] WREG[7:0] FSRL[7:0] STKOVF STKUNF WDTWV IDLEN DOZEN ROI TBLPTR21 FSRH[5:0] PLUSW[7:0] PREINC[7:0] POSTDEC[7:0] POSTINC[7:0] INDF[7:0] RWDT RMCLR RI POR RVREG MEMV DOE DOZE[2:0] PROD[7:0] PROD[15:8] TABLAT[7:0] TBLPTR[7:0] TBLPTR[15:8] TBLPTR[20:16] PCL[7:0] PCLATH[7:0] PCLATU[4:0] STKPTR[6:0] TOS[7:0] TOS[15:8] TOS[20:16] BOR RCM Reserved 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 RSTOSC[2:0] FCMENS FCMENP FCMEN BOREN[1:0] LPBOREN XINST LVP WDTE[1:0] DEBUG WRTAPP IVT1WAY STVREN WDTCCS[2:0] SAFEN CSWEN MVECEN PPS1WAY BBEN WRTSAF FEXTOSC[2:0] PR1WAY CLKOUTEN PWRTS[1:0] MCLRE ZCD BORV[1:0] WDTCPS[4:0] WDTCWS[2:0] BBSIZE[2:0] WRTD WRTC WRTB CP Reserved 7:0 15:8 MJRREV[1:0] © 2020-2021 Microchip Technology Inc. and its subsidiaries MNRREV[5:0] 1010[3:0] Preliminary Datasheet MJRREV[5:2] DS40002214E-page 873 PIC18F06/16Q41 Register Summary ...........continued Address Name Bit Pos. 0x3FFFFE DEVICEID 7:0 15:8 7 © 2020-2021 Microchip Technology Inc. and its subsidiaries 6 5 4 3 2 1 0 DEV[7:0] DEV[15:8] Preliminary Datasheet DS40002214E-page 874 PIC18F06/16Q41 Electrical Specifications 48. Electrical Specifications 48.1 Absolute Maximum Ratings(†) Parameter Ambient temperature under bias Storage temperature Voltage on pins with respect to VSS Rating -40°C to +125°C -65°C to +150°C • on VDD pin: -0.3V to +6.5V • on MCLR pin: -0.3V to +9.0V • on all other pins: -0.3V to (VDD + 0.3V) Maximum current(1) • on VSS pin • on VDD pin (28-pin devices) • on VDD pin (40-pin devices) • on any standard I/O pin -40°C ≤ TA ≤ +85°C 85°C < TA ≤ +125°C -40°C ≤ TA ≤ +85°C 85°C < TA ≤ +125°C -40°C ≤ TA ≤ +85°C 85°C < TA ≤ +125°C Clamp current, IK (VPIN < 0 or VPIN > VDD) Total power dissipation(2) 350 mA 120 mA 250 mA 85 mA 350 mA 120 mA ±50 mA ±20 mA 800 mW Notes:  1. Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see the Thermal Characteristics section to calculate device specifications. 2. Power dissipation is calculated as follows: PDIS = VDD x {IDD - Σ IOH} + Σ {(VDD - VOH) x IOH} + Σ (VOI x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 875 PIC18F06/16Q41 Electrical Specifications 48.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: VDDMIN ≤ VDD ≤ VDDMAX Operating Temperature: TA_MIN ≤ TA ≤ TA_MAX Parameter VDD — Operating Supply Voltage(1) TA — Operating Ambient Temperature Range Industrial Temperature Extended Temperature VDDMIN VDDMAX Ratings +1.8V +5.5V TA_MIN TA_MAX TA_MIN TA_MAX -40°C +85°C -40°C +125°C Note:  1. See the Parameter Supply Voltage in the “DC Characteristics” chapter for more details. Figure 48-1. Voltage Frequency Graph, -40°C ≤ TA ≤ +125°C Notes:  • The shaded region indicates the permissible combinations of voltage and frequency. • Refer to the “External Clock/Oscillator Timing Requirements” table in the “AC Characteristics” chapter for each Oscillator mode’s supported frequencies. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 876 PIC18F06/16Q41 Electrical Specifications 48.3 48.3.1 DC Characteristics Supply Voltage Table 48-1. Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions 1.8 — 5.5 V 1.7 — — V Device in Sleep mode — 1.6 — V BOR and LPBOR disabled(3) — 1 — V BOR and LPBOR disabled(3) — — V/ms BOR and LPBOR disabled(3) Supply Voltage D002 VDD RAM Data Retention(1) D003 VDR Power-on Reset Release Voltage(2) D004 VPOR Power-on Reset Rearm Voltage(2) D005 VPORR VDD Rise Rate to ensure internal Power-on Reset signal(2) D006 SVDD 0.05 † Data in “Typ.” column is at 3.0V, 25℃ unless otherwise stated. These parameters are for design guidance only and are not tested. Notes:  1. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2. See the following figure, POR and POR REARM with Slow Rising VDD. 3. See the Reset, WDT, Oscillator Start-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications section for BOR and LPBOR trip point information. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 877 PIC18F06/16Q41 Electrical Specifications Figure 48-2. POR and POR Rearm with Slow Rising VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TPOR(2) TVLOW(3) Notes:  1. When NPOR is low, the device is held in Reset. 2. TPOR 1 μs typical. 3. TVLOW 2.7 μs typical. 48.3.2 Supply Current (IDD)(1,2,4) Table 48-2. Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics Min. Typ.† Max. Units Conditions VDD D100 IDDXT4 XT = 4 MHz — 640 870 μA 3.0V D100A IDDXT4 XT = 4 MHz — 490 700 μA 3.0V D101 IDDHFO16 HFINTOSC = 16 MHz — 2 2.5 mA 3.0V D101A IDDHFO16 HFINTOSC = 16 MHz — 1.5 1.9 mA 3.0V D102 IDDHFOPLL HFINTOSC = 64 MHz — 6.7 8.2 mA 3.0V D102A IDDHFOPLL HFINTOSC = 64 MHz — 4.5 5.4 mA 3.0V D103 IDDHSPLL64 HS+PLL = 64 MHz — 5.6 13.8 mA 3.0V D103A IDDHSPLL64 HS+PLL = 64 MHz — 3.8 11.5 mA 3.0V D104 IDDIDLE Idle mode, HFINTOSC = 16 MHz — 1.4 1.8 mA 3.0V D105 IDDDOZE(3) Doze mode, HFINTOSC = 16 MHz, Doze Ratio = 16 — 1.5 1.9 mA 3.0V © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet Note PMD’s all 1’s PMD’s all 1’s PMD’s all 1’s PMD’s all 1’s DS40002214E-page 878 PIC18F06/16Q41 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics Min. Typ.† Max. Units Conditions VDD Note † Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Notes:  1. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled. 2. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3. IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = Doze Ratio (see the CPUDOZE register). 4. PMD bits are all in the Default state, no modules are disabled. 48.3.3 Power-Down Current (IPD)(1,2) Table 48-3. Standard Operating Conditions (unless otherwise stated) Param. No. D200 Sym. IPD Device Characteristics IPD Base Min. Typ.† Max. +85°C Max. +125°C Units Conditions VDD VREGPM — 1.1 3.3 4.6 μA 3.0V ‘b11 — 0.9 12.1 33.3 μA 3.0V ‘b10 — 29.5 45.5 68.9 μA 3.0V ‘b01 — 152 190 198.5 μA 3.0V ‘b00 D201 IPD_WDT Low-Frequency Internal Oscillator/WDT — 1.5 3.8 5.1 μA 3.0V ‘b11 D202 IPD_SOSC Secondary Oscillator (SOSC) — 2.1 4.6 7.9 μA 3.0V ‘b11 D203 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) — 1.3 3.5 4.8 μA 3.0V ‘b11 D204 IPD_FVR_BUF1 FVR Buffer 1 (ADC) — 174.7 249.7 255.4 μA 3.0V ‘b11 D204A IPD_FVR_BUF2 FVR Buffer 2 (DAC/CMP) — 49.4 74.2 90.7 μA 3.0V ‘bx1 or ‘b10 D205 IPD_BOR Brown-out Reset (BOR) — 16.6 20.4 20.8 μA 3.0V ‘b11 D206 IPD_HLVD High/Low Voltage Detect (HLVD) — 16.9 20.8 22.5 μA 3.0V ‘b11 D207 IPD_ADCA ADC - Active — 483 789 790 μA 3.0V ‘bx1 or ‘b10 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet Note ADC is converting (Note 4) DS40002214E-page 879 PIC18F06/16Q41 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics Min. Typ.† Max. +85°C Max. +125°C Units Conditions VDD VREGPM Note D208 IPD_CMP Comparator — 52.5 84.2 105 μA 3.0V ‘b11 D209 IPD_OPA Operational Amplifier — 1.10 1.67 1.73 mA 3.0V ‘b01 Charge Pump On; VICM = VDD/2 — — — — μA 3.0V ‘b01 Charge Pump Off; VICM = VDD/2 * These parameters are characterized but not tested. † Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Notes:  1. The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The peripheral ∆ current can be determined by subtracting the base IDD or IPD current from this limit. Max. values must be used when calculating total current consumption. 2. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode with all I/O pins in high-impedance state and tied to VSS. 3. All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available. 4. ADC clock source is ADCRC. 48.3.4 I/O Ports Table 48-4. Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Min. Typ.† Characteristics Input Low Voltage VIL I/O PORT: D300 — — • with TTL buffer D301 — — D302 — — • with Schmitt Trigger buffer Max. Units Conditions 0.8 0.15 VDD 0.2 VDD V V V 4.5V ≤ VDD ≤ 5.5V 1.8V ≤ VDD < 4.5V 2.0V ≤ VDD ≤ 5.5V D303 • with I2C levels — — 0.3 VDD V 2.0V ≤ VDD ≤ 5.5V D304 • with SMBus 2.0 — — 0.8 V 2.7V ≤ VDD ≤ 5.5V D305 • with SMBus 3.0 — — 0.8 V — — 0.2 VDD V D306 High Low Voltage MCLR © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 880 PIC18F06/16Q41 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Min. Typ.† Characteristics VIH I/O PORT: D320 2.0 — • with TTL buffer D321 0.25 VDD — + 0.8 D322 0.8 VDD — • with Schmitt Trigger buffer D323 • with I2C levels D324 • D325 • Units Conditions — — V V 4.5V ≤ VDD ≤ 5.5V 1.8V ≤ VDD < 4.5V — V 2.0V ≤ VDD ≤ 5.5V 0.7 VDD — — V with SMBus 2.0 2.1 — — V with SMBus 3.0 1.35 — — V 0.7 VDD — — V — ±5 ±125 nA VSS ≤ VPIN ≤ VDD, Pin at highimpedance, 85°C — ±5 ±1000 nA VSS ≤ VPIN ≤ VDD, Pin at highimpedance, 125°C — ±50 ±200 nA VSS ≤ VPIN ≤ VDD, Pin at highimpedance, 85°C 80 140 200 μA VDD = 3.0V, VPIN = VSS D326 MCLR Input Leakage Current(1) D340 IIL I/O PORTS D341 D342 Max. MCLR(2) Weak Pull-up Current D350 IPUR 2.7V ≤ VDD ≤ 5.5V Output Low Voltage D360 VOL I/O PORTS — — 0.6 V IOL = 10.0 mA, VPIN = 3.0V Output High Voltage D370 VOH I/O PORTS VDD - 0.7 — — V IOH = 6.0 mA, VPIN = 3.0V All I/O Pins D380 CIO — 5 50 pF † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Notes:  1. Negative current is defined as current sourced by the pin. 2. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 881 PIC18F06/16Q41 Electrical Specifications 48.3.5 Memory Programming Specifications Table 48-5. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Device Characteristics Min. Typ† Max. Units Conditions 100k — — E/W -40°C ≤ TA ≤ +85°C — 40 — Year Provided no other specifications are violated VDDMIN — VDDMAX V — — 11 ms 10k — — E/W -40°C ≤ TA ≤ +85°C (Note 1) — 40 — Year Provided no other specifications are violated VDDMIN — VDDMAX V VDDMIN — VDDMAX V MEM35 TP_REW Self-Timed Page Write — — 10 ms MEM36 TSE Self-Timed Page Erase — — 11 ms MEM37 TP_WRD Self-Timed Word Write — — 75 μs Data EEPROM Memory Specifications MEM20 ED DataEE Byte Endurance MEM21 TD_RET Characteristic Retention MEM23 VD_RW VDD for Read or Erase/Write operation MEM24 TD_BEW Byte Erase and Write Cycle Time Program Flash Memory Specifications MEM30 EP Flash Memory Cell Endurance MEM32 TP_RET Characteristic Retention MEM33 VP_RD VDD for Read operation MEM34 VP_REW VDD for Row Erase or Write operation † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-Timed Write. 48.3.6 Thermal Characteristics Table 48-6. Standard Operating Conditions (unless otherwise stated) Param No. TH01 TH02 Sym. θJA TJMAX Characteristic Thermal Resistance Junction to Ambient Maximum Junction Temperature © 2020-2021 Microchip Technology Inc. and its subsidiaries Typ. Units 95.3 °C/W 14-pin SOIC package 100 °C/W 14-pin TSSOP package 62.2 °C/W 20-pin PDIP package 77.7 °C/W 20-pin SOIC package 87.3 °C/W 20-pin SSOP package 79.7 °C/W 20-pin VQFN package 150 °C Preliminary Datasheet Conditions DS40002214E-page 882 PIC18F06/16Q41 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Typ. Units Conditions Note:  1. See the “Absolute Maximum Ratings” section for total power dissipation. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 883 PIC18F06/16Q41 Electrical Specifications 48.4 AC Characteristics Figure 48-3. Load Conditions Load Condition Pin CL VSS Legend: CL = 50 pF for all pins 48.4.1 External Clock/Oscillator Timing Requirements Figure 48-4. Clock Timing Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS2/OS4/OS6 OS1/OS3/OS5/OS20 OS2/OS4/OS6 OS21 CLKOUT (CLKOUT Mode) Note:  See the table below. Table 48-7. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions ECL Oscillator OS1 FECL Clock Frequency — — 1 MHz OS2 TECL_DC Clock Duty Cycle 40 — 60 % ECM Oscillator OS3 FECM Clock Frequency — — 16 MHz OS4 TECM_DC Clock Duty Cycle 40 — 60 % Clock Frequency — — 64 MHz VDD > 2.7V — — 32 MHz VDD < 2.7V Clock Duty Cycle 40 — 60 % Clock Frequency — — 100 kHz (Note 4) Clock Frequency — — 4 MHz (Note 4) ECH Oscillator OS5 OS6 FECH TECH_DC LP Oscillator OS7 FLP XT Oscillator OS8 FXT HS Oscillator © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 884 PIC18F06/16Q41 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. OS9 Sym. FHS Characteristic Min. Typ. † Max. Units Conditions Clock Frequency — — 20 MHz VDD > 2.5V (Note 4) Clock Frequency 32.4 32.768 33.1 kHz (Note 4) (Note 2, Note 3) Secondary Oscillator OS10 FSEC System Oscillator OS20 FOSC System Clock Frequency — — 64 MHz OS21 FCY Instruction Frequency — FOSC/4 — MHz OS22 TCY Instruction Period 62.5 1/FCY — ns Notes:  1. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2. The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in the “Power Saving Operation Modes” section. 3. The system clock frequency (FOSC) must meet the voltage requirements defined in the “Standard Operating Conditions” section. 4. LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking the device with the external square wave, one of the EC mode selections must be used. 48.4.2 Internal Oscillator Parameters(1) Table 48-8. Standard Operating Conditions (unless otherwise stated) Param No. OS50 Sym. FHFOSC Characteristic Min. Typ. † Max. Units Precision Calibrated HFINTOSC Frequency — 4 — MHz Conditions (Note 2) 8 12 16 32 48 64 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 885 PIC18F06/16Q41 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. OS51 Sym. FHFOSCLP Characteristic Low-Power Optimized HFINTOSC Frequency Min. Typ. † Max. Units Conditions 0.91 1 1.09 MHz Fundamental Freq.1 MHz; -40°C to 85°C 1.76 2 2.24 MHz Fundamental Freq.2 MHz; -40°C to 85°C — — — MHz Fundamental Freq.1 MHz; -40°C to 125°C — — — MHz Fundamental Freq.2 MHz; -40°C to125°C OS52 FMFOSC Internal Calibrated MFINTOSC Frequency — 500 — kHz OS53* FLFOSC Internal LFINTOSC Frequency 27.9 31 34.1 kHz OS54* THFOSCST HFINTOSC Wake-up from Sleep Start-up Time — 13 40 μs VREGPM = 00 — 30 — μs VREGPM = 01 — 84 — μs VREGPM = 10 — 93 — μs VREGPM = 11 System Clock at 4 MHz OS56 TLFOSCST LFINTOSC Wake-up from Sleep Start-up Time — 0.3 — ms * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Notes:  1. To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. 2. See the figure below. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 886 PIC18F06/16Q41 Electrical Specifications Figure 48-5. Precision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Temperature 125 ± 5% Temperature (°C) 85 ± 3% 60 ± 2% 0 ± 5% -40 1.8 2.3 2.0 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 48.4.3 PLL Specifications Table 48-9. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units PLL01 FPLLIN PLL Input Frequency Range 4 — 16 MHz PLL02 FPLLOUT PLL Output Frequency Range 16 — 64 MHz PLL03* FPLLST PLL Lock Time — 200 — μs PLL04* FPLLJIT PLL Output Frequency Stability -0.25 — 0.25 % Conditions (Note 1) * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. The output frequency of the PLL must meet the FOSC requirements listed in Parameter D002. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 887 PIC18F06/16Q41 Electrical Specifications 48.4.4 I/O and CLKOUT Timing Specifications Figure 48-6. CLKOUT and I/O Timing Cycle Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC IO2 IO1 IO10 CLKOUT IO8 IO7 IO4 IO5 I/O pin (Input) IO3 I/O pin (Output) New Value Old Value IO7, IO8 Table 48-10. I/O and CLKOUT Timing Specifications Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions IO1* TCLKOUTH CLKOUT rising edge delay (rising edge FOSC (Q1 cycle) to falling edge CLKOUT — — 70 ns IO2* TCLKOUTL CLKOUT falling edge delay (rising edge FOSC (Q3 cycle) to rising edge CLKOUT — — 72 ns IO3* TIO_VALID Port output valid time (rising edge FOSC (Q1 cycle) to port valid) — 50 70 ns IO4* TIO_SETUP Port input setup time (Setup time before rising edge FOSC – Q2 cycle) 20 — — ns IO5* TIO_HOLD Port input hold time (Hold time after rising edge FOSC – Q2 cycle) 50 — — ns IO6* TIOR_SLREN Port I/O rise time, slew rate enabled — 25 — ns VDD = 3.0V IO7* TIOR_SLRDIS Port I/O rise time, slew rate disabled — 5 — ns VDD = 3.0V IO8* TIOF_SLREN Port I/O fall time, slew rate enabled — 25 — ns VDD = 3.0V IO9* TIOF_SLRDIS Port I/O fall time, slew rate disabled — 5 — ns VDD = 3.0V IO10* TINT INT pin high or low time to trigger an interrupt 25 — — ns IO11* TIOC Interrupt-on-Change minimum high or low time to trigger interrupt 25 — — ns * These parameters are characterized but not tested. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 888 PIC18F06/16Q41 Electrical Specifications 48.4.5 Reset, WDT, Oscillator Start-Up Timer, Power-Up Timer, Brown-Out Reset and Low-Power BrownOut Reset Specifications Figure 48-7. Reset, Watchdog Timer, Oscillator Start-Up Timer and Power-Up Timer Timing VDD MCLR RST01 Internal POR RST04 PWRT Time-out RST05 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) RST03 RST02 RST02 I/O pins Note:  1. Asserted low. Figure 48-8. Brown-out Reset Timing and Characteristics VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) RST08 Reset RST04(1) (due to BOR) Note:  1. Only if the PWRTE Configuration bit is programmed to ‘1’; 2 ms delay if PWRTE = 0. Table 48-11. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. RST01* TMCLR MCLR Pulse Width — Low to ensure Reset RST02* TIOZ I/O high-impedance — from Reset detection © 2020-2021 Microchip Technology Inc. and its subsidiaries Typ. † — Max. — Units μs — 2 μs Preliminary Datasheet Conditions DS40002214E-page 889 PIC18F06/16Q41 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. RST03 TWDT Watchdog Timer Time— out Period RST04* TPWRT Power-up Timer — Period RST05 TOST Oscillator Start-up — Timer Period(1,2) RST06 VBOR Brown-out Reset 2.7 Voltage 2.55 RST07 VBORHYS Brown-out Reset Hysteresis RST08 TBORDC Brown-out Reset Response Time RST09 VLPBOR Low-Power Brown-out Reset Voltage * These parameters are characterized but not tested. Typ. † 16 Max. — Units ms Conditions WDTCPS = 00100 65 — ms 1024 — TOSC 2.85 3.0 V BORV = 00 2.7 2.85 V BORV = 01 2.3 2.45 2.6 V BORV = 10 1.8 1.9 2.1 V BORV = 11 — 60 — mV BORV = 00 — 3 — μs 1.8 1.9 2.2 V † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Notes:  1. By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency. 2. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. 48.4.6 High/Low-Voltage Detect Characteristics Table 48-12. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. HLVD01 VDET Voltage Detect 1.73(1) © 2020-2021 Microchip Technology Inc. and its subsidiaries Typ. 1.90 Max. 2.07 Units V Conditions HLVDSEL = 0000 1.91 2.10 2.29 V HLVDSEL = 0001 2.05 2.25 2.45 V HLVDSEL = 0010 2.28 2.50 2.73 V HLVDSEL = 0011 2.37 2.60 2.83 V HLVDSEL = 0100 2.5 2.75 3.00 V HLVDSEL = 0101 2.64 2.90 3.16 V HLVDSEL = 0110 2.87 3.15 3.43 V HLVDSEL = 0111 3.05 3.35 3.65 V HLVDSEL = 1000 3.28 3.60 3.92 V HLVDSEL = 1001 3.41 3.75 4.09 V HLVDSEL = 1010 3.64 4.00 4.36 V HLVDSEL = 1011 3.82 4.20 4.58 V HLVDSEL = 1100 3.96 4.35 4.74 V HLVDSEL = 1101 4.23 4.65 5.07 V HLVDSEL = 1110 Preliminary Datasheet DS40002214E-page 890 PIC18F06/16Q41 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. * These parameters are characterized but not tested. Typ. Max. Units Conditions † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Device operation below VDD = 1.8 V is not recommended. 48.4.7 Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) Table 48-13. Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C, TAD = 500ns Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions AD01 NR Resolution — — 12 bit AD02 EIL Integral Non-Linearity Error — ±0.1 ±2.0 LSb ADCREF+ = 3.0V, ADCREF- = 0V AD03 EDL Differential Non-Linearity Error — ±0.1 ±1.0 LSb ADCREF+ = 3.0V, ADCREF- = 0V AD04 EOFF Offset Error — 0.5 6.0 LSb ADCREF+ = 3.0V, ADCREF- = 0V AD05 EGN Gain Error — ±0.2 ±6.0 LSb ADCREF+ = 3.0V, ADCREF- = 0V AD06 VADREF ADC Reference Voltage (ADREF+ ADREF-) 1.8 — VDD V AD07 VAIN Full-Scale Range ADREF- — ADREF+ V AD08 ZAIN Recommended Impedance of Analog Voltage Source — 1 — kΩ AD09 RVREF ADC Voltage Reference Ladder Impedance — 50 — kΩ (Note 3) * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Notes:  1. Total Absolute Error is the sum of the offset, gain and integral nonlinearity (INL) errors. 2. The ADC conversion result never decreases with an increase in the input and has no missing codes. 3. This is the impedance seen by the VREF pads when the external reference pads are selected. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 891 PIC18F06/16Q41 Electrical Specifications 48.4.8 Analog-to-Digital Converter (ADC) Conversion Timing Specifications Standard Operating Conditions (unless otherwise stated) Param No. Sym. AD20 TAD AD21 Characteristic ADC Clock Period TCNV Conversion Time AD22 THCD Sample-and-Hold Capacitor Disconnect Time Min. Typ. † Max. Units Conditions 0.5 — 9 μs Using FOSC as the ADC clock source ADOCS = 0 — 2 — μs Using ADCRC as the ADC clock source ADOCS = 1 — 14 TAD+2TCY — — Using FOSC as the ADC clock source ADOCS = 0 — 16 TAD+2TCY — — Using ADCRC as the ADC clock source ADOCS = 1 — 2 TAD+1TCY — — Using FOSC as the ADC clock source ADOCS = 0 — 3 TAD+2TCY — — Using ADCRC as the ADC clock source ADOCS = 1 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Figure 48-9. ADC Conversion Timing (ADC Clock FOSC-Based) BSF ADCON0, GO 1 TCY AD22 AD24 1 TCY 1 TCY AD20 ADC_clk ADRES OLD DATA NEW DATA ADIF GO Sample © 2020-2021 Microchip Technology Inc. and its subsidiaries DONE Sampling Stopped Preliminary Datasheet DS40002214E-page 892 PIC18F06/16Q41 Electrical Specifications Figure 48-10. ADC Conversion Timing (ADC Clock from ADCRC) BSF ADCON0, GO 1 TCY AD22 AD24 2 TCY(1) AD21 ADC_clk ADRES OLD DATA NEW DATA ADIF GO DONE Sample Sampling Stopped Note 1: If the ADC clock source is selected as ADCRC, a time of 1 TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed, if any. 48.4.9 Comparator Specifications Table 48-14. Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param No. Sym. Characteristic Min. Typ. † Max. Units CM01 VIOFF Input Offset Voltage — — ±50 mV CM02 VICM Input Common Mode Range GND — VDD V CM03 CMRR Common Mode Input Rejection Ratio — 50 — dB CM04 VHYST Comparator Hysteresis 10 25 40 mV CM05 TRESP(1) Response Time, Rising Edge — 300 600 ns Response Time, Falling Edge — 220 500 ns Conditions VICM = VDD/2 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 893 PIC18F06/16Q41 Electrical Specifications 48.4.10 8-Bit DAC Specifications Table 48-15. Standard Operating Conditions (unless otherwise stated)VDD = 3.0V, TA = 25°C Param No. Sym. Characteristic Min. Typ. † Max. Units DSB01 VLSB Step Size — (VDACREF+ VDACREF-)/256 — V DSB02 VACC Absolute Accuracy — — ±0.5 LSb DSB03* RUNIT Unit Resistor Value — 20 — kΩ DSB04* TST Settling Time(1) — 10 — μs DSB05* VDBO DAC Buffer Offset(2) — 20 65 mV Conditions * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Notes:  1. Settling time measured while DACR[7:0] transitions from ‘b00000000 to ‘b11111111. 2. This parameter only applies to the buffered DAC1 module, and does not apply to the unbuffered DAC2. 48.4.11 Operational Amplifier Specifications Table 48-16. Standard Operating Conditions (unless otherwise stated)VDD = 3.0V, TA = 25°C Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions OPA01* GBWP Gain Bandwidth Product — — 5.5 MHz OPA02 TON Turn-on Time — 0.9 — μs OPA03* PM Phase Margin — 80 — degrees OPA04* SR Slew Rate — 8 — V/μs OPA05 OFF Offset — ±2 — mV OPA06 CMRR Common-Mode Rejection Ratio 45 60 — dB 0.9VDD-0.1VDD OPA07* AOL Open-Loop Gain — 80 — dB Open-Loop Gain (Phase) OPA08* VICM Input Common-Mode Voltage VSS — VDD V Charge Pump On; VDD > 2.5V — — — Charge Pump Off; VDD > 2.5V OPA09* Eni Input Noise Voltage — 160 — OPA10* eni Input Noise Voltage Density — 70 — OPA11* PSRR Power Supply Rejection Ratio — 67 — dB OPA12* ISC Short Circuit Current — 10 — mA © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet μV nV/√(Hz) 10 kHz DS40002214E-page 894 PIC18F06/16Q41 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated)VDD = 3.0V, TA = 25°C Param No. Sym. Characteristic OPA13 VOS Voltage Output Swing OPA14 IO Maximum Output Current Min. Typ. † Max. Units (0.15) * VDD — (0.85) * VDD V — 0.5 — nA Conditions * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 48.4.12 Fixed Voltage Reference (FVR) Specifications Table 48-17. Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions FVR01 VFVR1 1x Gain (1.024V) -4 — -4 % VDD ≥ 2.5V, -40°C to 85°C FVR02 VFVR2 2x Gain (2.048V) -4 — +4 % VDD ≥ 2.5V, -40°C to 85°C FVR03 VFVR4 4x Gain (4.096V) -5 — +5 % VDD ≥ 4.75V, -40°C to 85°C FVR04 TFVRST FVR Start-up Time — 25 — μs 48.4.13 Zero-Cross Detect (ZCD) Specifications Table 48-18. Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param No. Sym. Characteristic Min. Typ. † Max. Units ZC01 VPINZC Voltage on Zero-Cross Pin — 0.9 — V ZC02 IZCD_MAX Maximum source or sink current — — 600 μA ZC03 TRESPH Response Time, Rising Edge — 1 — μs TRESPL Response Time, Falling Edge — 1 — μs Conditions † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 895 PIC18F06/16Q41 Electrical Specifications 48.4.14 Timer0 and Timer1 External Clock Requirements Table 48-19. Standard Operating Conditions (unless otherwise stated) Operating Temperature: -40°C≤TA≤+125°C Param No. 40* 41* Sym. TT0H TT0L Characteristic Min. Typ. † Max. Units T0CKI High No Prescaler Pulse With Prescaler Width 0.5TCY+20 — — ns 10 — — ns T0CKI Low Pulse Width 0.5TCY+20 — — ns 10 — — ns Greater of: 20 or (TCY+40)/N — — ns 0.5TCY+20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns Synchronous, No Prescaler 0.5TCY+20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns Synchronous Greater of: 30 or (TCY+40)/N — — ns Asynchronous 60 — — ns 2 TOSC — 7 TOSC — No Prescaler With Prescaler 42* TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Time Prescaler 46* 47* 49* TT1L TT1P T1CKI Low Time T1CKI Input Period TCKEZTMR1 Delay from External Clock Edge to Timer Increment Conditions N = Prescale value N = Prescale value Timers in Sync mode * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 896 PIC18F06/16Q41 Electrical Specifications Figure 48-11. Timer0 and Timing1 External Clock Timings T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 48.4.15 Capture/Compare/PWM Requirements (CCP) Table 48-20. Standard Operating Conditions (unless otherwise stated) Operating Temperature: -40°C ≤ TA ≤ +125°C Param No. CC01* CC02* CC03* Sym. TCCL TCCH TCCP Characteristic CCPx Input Low Time CCPx Input High Time Min. Typ. † Max. No Prescaler 0.5TCY+20 — — ns With Prescaler 20 — — ns No Prescaler 0.5TCY+20 — — ns With Prescaler 20 — — ns (3TCY+40)/N — — ns CCPx Input Period Units Conditions N = Prescale value * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Figure 48-12. Capture/Compare/PWM Timings (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note:  Refer to the Load Conditions figure for more details. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 897 PIC18F06/16Q41 Electrical Specifications 48.4.16 SPI Mode Requirements Table 48-21. SPI Host Mode Standard Operating Conditions (unless otherwise stated) Param No. Sym. TSCK SP70* TSSL2SCH, TSSL2SCL Characteristic SCK Cycle Time (2x Prescaled) SDO to SCK↓ or SCK↑ input Min. Typ. † Max. Units 61 — — ns — 16(1) — MHz 95 — — ns — 10(1) — MHz TSCK — — ns FST = 0 0 — — ns FST = 1 SP71* TSCH SCK output high time 0.5 TSCK - 12 — 0.5 TSCK + 12 ns SP72* TSCL SCK output low time 0.5 TSCK - 12 — 0.5 TSCK + 12 ns SP73* TDIV2SCH, Setup time of SDI data input to SCK edge 85 — — ns Hold time of SDI data input to SCK edge 0 — — ns Hold time of SDI data input to final SCK 0.5 TSCK TDIV2SCL SP74* TSCH2DIL, TSCL2DIL Conditions Transmit only mode Full Duplex mode ns CKE = 0, SMP = 1 SP75* TDOR SDO data output rise time — 10 25 ns CL = 50 pF SP76* TDOF SDO data output fall time — 10 25 ns CL = 50 pF SP78* TSCR SCK output rise time — 10 25 ns CL = 50 pF SP79* TSCF SCK output fall time — 10 25 ns CL = 50 pF SP80* TSCH2DOV, SDO data output valid after SCK edge -15 — 15 ns CL = 50 pF SDO data output valid to first SCK edge TSCK - 10 — — ns CL = 50 pF — — 50 ns TSCL2DOV SP81* TDOV2SCH, TDOV2SCL CKE = 1 SP82* TSSL2DOV SDO data output valid after SS↓ edge SP83* TSCH2SSH, SS ↑ after last SCK edge TSCK - 10 — — ns SS ↑ to SS↓ edge TSCK - 10 — — ns TSCL2SSH SP84* TSSH2SSL © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet CL = 20 pF DS40002214E-page 898 PIC18F06/16Q41 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. SMP bit in the SPIxCON1 register must be set and the slew rate control must be disabled on the clock and data pins (clear the corresponding bits in SLRCONx register) for SPI to operate over 4 MHz. Table 48-22. SPI Client Mode Standard Operating Conditions (unless otherwise stated) Param No. Sym. TSCK SP70* TSSL2SCH, TSSL2SCL Characteristic Min. Typ. † Max. Units SCK Total Cycle Time 47 — — ns — 20(1) — MHz 95 — — ns — 10(1) — MHz 0 — — ns CKE = 0 25 — — ns CKE = 1 SS↓ to SCK↓ or SCK↑ input SP71* TSCH SCK input high time 20 — — ns SP72* TSCL SCK input low time 20 — — ns SP73* TDIV2SCH, Setup time of SDI data input to SCK edge 10 — — ns Hold time of SDI data input to SCK edge 0 — — ns TDIV2SCL SP74* TSCH2DIL, TSCL2DIL Conditions Receive Only mode Full Duplex mode SP75* TDOR SDO data output rise time — 10 25 ns CL = 50 pF SP76* TDOF SDO data output fall time — 10 25 ns CL = 50 pF SP77* TSSH2DOZ SS↑ to SDO output high-impedance — — 85 ns SP80* TSCH2DOV, SDO data output valid after SCK edge — — 85 ns TSCL2DOV SP82* TSSL2DOV SDO data output valid after SS↓ edge — — 85 ns SP83* TSCH2SSH, SS ↑ after SCK edge 20 — — ns SS ↑ to SS↓ edge 47 — — ns TSCL2SSH SP84* TSSH2SSL © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 899 PIC18F06/16Q41 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. SMP bit in the SPIxCON1 register must be set and the slew rate control must be disabled on the clock and data pins (clear the corresponding bits in SLRCONx register) for SPI to operate over 4 MHz. Figure 48-13. SPI Host Mode Timing (CKE = 0, SMP = 0) SS SP81 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note:  Refer to the Load Conditions figure for more details. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 900 PIC18F06/16Q41 Electrical Specifications Figure 48-14. SPI Host Mode Timing (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SDO MSb SP78 LSb bit 6 - - - - - -1 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note:  Refer to the Load Conditions figure for more details. Figure 48-15. SPI Client Mode Timing (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note:  Refer to the Load Conditions figure for more details. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 901 PIC18F06/16Q41 Electrical Specifications Figure 48-16. SPI Client Mode Timing (CKE = 1) SP82 SS SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 MSb SDO bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note:  Refer to the Load Conditions figure for more details. 48.4.17 I2C Bus Start/Stop Bits Requirements Table 48-23. Standard Operating Conditions (unless otherwise stated) Param. No. SP90* Sym. Characteristic TSU:STA Start condition 100 kHz mode 4700 Setup time SP91* — 600 — — 1 MHz mode 260 — — THD:STA Start condition 100 kHz mode 4000 — — 400 kHz mode 600 — — 1 MHz mode 260 — — TSU:STO Stop condition 100 kHz mode 4000 — — Setup time SP93* — 400 kHz mode Hold time SP92* Min. Typ. † Max. Units 400 kHz mode 600 — — 1 MHz mode 260 — — THD:STO Stop condition 100 kHz mode 4700 — — 400 kHz mode 1300 — — 1 MHz mode — — Hold time 500 Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated ns ns * These parameters are characterized but not tested. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 902 PIC18F06/16Q41 Electrical Specifications Figure 48-17. I2C Bus Start/Stop Bits Timing SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note:  Refer to the Load Conditions figure for more details. 48.4.18 I2C Bus Data Requirements Table 48-24. Standard Operating Conditions (unless otherwise stated) Param. No. SP100* SP101* SP102* Sym. THIGH TLOW TR Characteristic Clock high time Clock low time SDA and SCL rise time © 2020-2021 Microchip Technology Inc. and its subsidiaries Min. Max. Units 100 kHz mode 4000 — ns Device must operate at a minimum of 1.5 MHz 400 kHz mode 600 — ns Device must operate at a minimum of 10 MHz 1 MHz mode 260 — ns Device must operate at a minimum of 10 MHz 100 kHz mode 4700 — ns Device must operate at a minimum of 1.5 MHz 400 kHz mode 1300 — ns Device must operate at a minimum of 10 MHz 1 MHz mode 500 — ns Device must operate at a minimum of 10 MHz 100 kHz mode — 1000 ns 400 kHz mode 20 300 ns 1 MHz mode — 120 Preliminary Datasheet Conditions CB is specified to be from 10-400 pF DS40002214E-page 903 PIC18F06/16Q41 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param. No. SP103* SP106* SP107* SP109* Sym. TF THD:DAT TSU:DAT TAA Characteristic Min. Max. Units 100 kHz mode — 250 ns 400 kHz mode 20 × (VDD/ 5.5V) 250 ns 1 MHz mode 20 × (VDD/ 5.5V) 120 ns 100 kHz mode 0 — ns 400 kHz mode 0 — ns 1 MHz mode 0 — ns Data input setup 100 kHz time mode 250 — ns 400 kHz mode 100 — ns 1 MHz mode 50 — ns 100 kHz mode — 3450 ns 400 kHz mode — 900 ns 450 ns SDA and SCL fall time Data input hold time Output valid from clock 1 MHz mode SP110* SP111 TBUF CB Bus free time Bus capacitive loading © 2020-2021 Microchip Technology Inc. and its subsidiaries 100 kHz mode 4700 — ns 400 kHz mode 1300 — ns 1 MHz mode 500 — ns 100 kHz mode — 400 pF 400 kHz mode — 400 pF 1 MHz mode — 26 pF Preliminary Datasheet Conditions CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start (Note 3) DS40002214E-page 904 PIC18F06/16Q41 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Max. Units Conditions * These parameters are characterized but not tested. Notes:  1. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. 3. Using internal I2C pull-ups. For greater bus capacitance use external pull-ups. Figure 48-18. I2C Bus Data Timing SP103 SCL SP100 SP90 SP102 SP101 SP106 SP107 SP92 SP91 SDA In SP110 SP109 SP109 SDA Out Note:  Refer to the Load Conditions figure for more details. 48.4.19 Configurable Logic Cell (CLC) Characteristics Table 48-25. Standard Operating Conditions (unless otherwise stated) Operating Temperature: -40°C≤TA≤+125°C Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions CLC01* TCLCIN CLC input time — 7 IO5 ns (Note 1) CLC02* TCLC CLC module input to output propagation time — 24 — ns VDD = 1.8V — 12 — ns VDD > 3.6V CLC output time Rise Time — IO6 — — (Note 1) Fall Time — IO8 — — (Note 1) — — OS20 — CLC03* CLC04* TCLCOUT FCLCMAX CLC maximum switching frequency * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. See the “I/O and CLKOUT Timing Specifications” section for OS7, OS8 and OS9 rise and fall times. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 905 PIC18F06/16Q41 Electrical Specifications Figure 48-19. CLC Propagation Timing CLCxINn CLC Input time CLCxINn CLC Input time LCx_in[n](1) LCx_in[n](1) CLC01 CLC Module LCx_out(1) CLC Output time CLCx CLC Module LCx_out(1) CLC Output time CLCx CLC02 CLC03 48.4.20 Temperature Indicator Requirements Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions TS01* TACQMIN Minimum ADC Acquisition Time Delay — 25 — µs TS02* MV Voltage Sensitivity High Range — -3.75 — mV/℃ TSRNG = 1 Low Range — -2.75 — mV/℃ TSRNG = 0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 906 PIC18F06/16Q41 DC and AC Characteristics Graphs and Tables 49. DC and AC Characteristics Graphs and Tables The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Unless otherwise noted, all graphs apply to both the L and LF devices. Note:  The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. Note:  “Typical” represents the mean of the distribution at 25°C. “Maximum”, “Max.”, “Minimum” or “Min.” represents (mean + 3σ) or (mean - 3σ) respectively, where σ is a standard deviation, over each temperature range. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 907 PIC18F06/16Q41 DC and AC Characteristics Graphs and Tables Operational Amplifier Graphs Figure 49-1. Input Offset Voltage at 25°C over VCM and VDD Figure 49-2. Input Offset Voltage at 25°C over VCM and VDD (CPON = 1) VDD [V] 5.0 2 1.0 5.5 5 0.0 -1.0 Offset [mV] Offset [mV] 4 1.0 5.5 0.0 -3.0 -4.0 -4.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -5.0 -0.5 6.0 5 -1.0 -2.0 0.5 3 4 -3.0 0.0 2.4 2.0 -2.0 -5.0 -0.5 2 3.0 3 2.0 1.8 4.0 2.4 3.0 VDD [V] 5.0 1.8 4.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input common mode [V] Input common mode [V] Figure 49-3. Input Offset Voltage at 3V over VCM and Temperature Figure 49-4. Input Offset Voltage at 5V over VCM and Temperature Temperature [°C] 5.0 25 2.0 1.0 1.0 Offset [mV] Offset [mV] 2.0 0.0 -2.0 -3.0 -4.0 -4.0 0.5 1.0 1.5 2.0 2.5 3.0 -5.0 -0.5 3.5 125 0.0 -3.0 0.0 85 -1.0 -2.0 -5.0 -0.5 25 3.0 125 -1.0 -40 4.0 85 3.0 Temperature [°C] 5.0 -40 4.0 0.0 0.5 1.0 1.5 Input common mode [V] 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input common mode [V] Figure 49-5. PSRR at 3V VDD and VCM = VDD/2 over Frequency and Temperature Figure 49-6. PSRR at DC and VCM = VDD/2 over VDD and Temperature Temperature [°C] 0 25 -40 25 -10 85 125 -20 Temperature [°C] 0 -40 -10 85 125 -20 -30 -30 PSRR [dB] PSRR [dB] 49.1 -40 -40 -50 -50 -60 -60 -70 -70 -80 100 200 300 500 1k 2k 3k 5k 10k 20k 30k 50k 100k 200k 400k 1M 2M 3M 5M 10M 20M 30M -80 1.5 2.0 2.5 Frequency [Hz] © 2020-2021 Microchip Technology Inc. and its subsidiaries 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD [V] Preliminary Datasheet DS40002214E-page 908 PIC18F06/16Q41 DC and AC Characteristics Graphs and Tables Figure 49-7. Open Loop Gain and Phase Bode Plot at Figure 49-8. Open Loop Gain at 25°C over VDD and 3V and 25°C VCM 100 0 Open-Loop Gain [dB] -30 -60 40 -90 20 -120 0 -150 -20 -180 -40 -210 Open Loop Gain [dB] 60 1.8 110 2.4 100 3 4 90 Phase [deg] Open-Loop Gain [dB] 80 VDD [V] 120 Phase [deg] 5.5 80 70 60 50 40 30 20 10 100 1k 10k 100k 1M 10 0 -0.5 0.0 0.5 1.0 1.5 10M 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input common mode [V] Frequency [Hz] Figure 49-9. Open Loop Gain at VCM = VDD/2 over VDD Figure 49-10. Slew Rate Fall Time over VDD and and Temperature Temperature Temperature [°C] 120 110 25 100 85 70 60 50 40 25 85 16 Output Slew Rate [V/µs] Open Loop Gain [dB] 80 -40 18 125 90 Temperature [°C] 20 -40 30 125 14 12 10 8 6 4 20 2 10 0 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.5 2.0 2.5 VDD [V] 3.5 4.0 4.5 5.0 5.5 6.0 VDD [V] Figure 49-11. Slew Rate Rise Time over VDD and Temperature Figure 49-12. VOH at 3V over Temperature and Load Current Temperature [°C] 20 Temperature [°C] 0.00 -40 -40 25 18 25 85 16 85 -0.02 125 125 14 12 VDD-VOH [V] Output Slew Rate [V/µs] 3.0 10 8 -0.04 -0.06 6 4 -0.08 2 0 -0.10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 VDD [V] © 2020-2021 Microchip Technology Inc. and its subsidiaries Output current [mA] Preliminary Datasheet DS40002214E-page 909 PIC18F06/16Q41 DC and AC Characteristics Graphs and Tables Figure 49-13. VOH at 5V over Temperature and Load Current Figure 49-14. VOL at 3V over Temperature and Load Current Temperature [°C] 0.00 Temperature [°C] 0.10 -40 -40 25 85 0.08 125 -0.04 125 0.06 VOL [V] VDD-VOH [V] 25 85 -0.02 -0.06 0.04 -0.08 0.02 -0.10 0.00 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 Output current [mA] Output current [mA] Figure 49-15. VOL at 5V over Temperature and Load Current Figure 49-16. Output Short Circuit Current Over VDD and Temperature Temperature [°C] 0.10 Temperature [°C] 0.10 -40 -40 25 25 85 0.08 85 0.08 125 VOL [V] 0.06 VOL [V] 0.06 125 0.04 0.04 0.02 0.02 0.00 0.00 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 Output current [mA] Output current [mA] Figure 49-17. IDD over VDD and Temperature (CPON = 1) Temperature [°C] -40 1500 25 1400 85 1300 130 1200 IDD [µA] 1100 1000 900 800 700 600 500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VDD [V] © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 910 PIC18F06/16Q41 Packaging Information 50. Packaging Information Package Marking Information Legend: XX...X Y YY WW NNN e3 Note: Customer-specific information or Microchip part number Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Rev. 30-009014B 09/21/2017 14-Lead TSSOP (4.4 mm) Example 18F06Q41 1950 e3 017 XXXXXXXX YYWW NNN 14-Lead SOIC (3.90 mm) Example PIC18F06Q41 /SL e3 1950017 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 911 PIC18F06/16Q41 Packaging Information Rev. 30-009020A 09/21/2017 20-Lead PDIP (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F16Q41 /P e3 1950017 Rev. 30-009020B 09/21/2017 20-Lead SSOP (5.30 mm) Example PIC18F16Q41 /SS e3 1950017 Rev. 30-009020C 09/21/2017 20-Lead SOIC (7.50 mm) Example PIC18F16Q41 /SO e3 1950017 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 912 PIC18F06/16Q41 Packaging Information 20-Lead VQFN (3x3x0.9 mm) PIN 1 50.1 PIC18F16Q41 Example XXX YYWW NNN PIN 1 DB0 2034 ERJ Package Details The following sections give the technical details of the packages. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 913 PIC18F06/16Q41 Packaging Information 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A NOTE 5 D N E 2 E2 2 E1 E 2X 0.10 C D NOTE 1 1 2 2X N/2 TIPS 0.20 C 3 e NX b B 0.25 NOTE 5 C A–B D TOP VIEW 0.10 C C A A2 SEATING PLANE 14X 0.10 C SIDE VIEW A1 h h R0.13 H R0.13 c SEE VIEW C L VIEW A–A (L1) VIEW C Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2 © 2017 Microchip Technology Inc. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 914 PIC18F06/16Q41 Packaging Information 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 § Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L Footprint L1 Lead Angle Foot Angle c Lead Thickness Lead Width b Mold Draft Angle Top Mold Draft Angle Bottom MIN 1.25 0.10 0.25 0.40 0° 0° 0.10 0.31 5° 5° MILLIMETERS NOM 14 1.27 BSC 6.00 BSC 3.90 BSC 8.65 BSC 1.04 REF - MAX 1.75 0.25 0.50 1.27 8° 0.25 0.51 15° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimension D does not include mold flash, protrusions or gate burrs, which shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion, which shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2 © 2017 Microchip Technology Inc. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 915 PIC18F06/16Q41 Packaging Information 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 14 SILK SCREEN C Y 1 2 X E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X14) X Contact Pad Length (X14) Y MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2065-SL Rev D © 2017 Microchip Technology Inc. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 916 PIC18F06/16Q41 Packaging Information 14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N E 2 E1 2 E1 E 1 2X 7 TIPS 0.20 C B A 2 e TOP VIEW A C A2 A SEATING PLANE 14X 0.10 C 14X b 0.10 A1 C B A A SIDE VIEW SEE DETAIL B VIEW A–A Microchip Technology Drawing C04-087 Rev D Sheet 1 of 2 © 2020 Microchip Technology Inc. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 917 PIC18F06/16Q41 Packaging Information 14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (θ2) R1 H R2 c L (θ3) θ1 (L1) DETAIL B Notes: Number of Terminals Pitch Overall Height Standoff Molded Package Thickness Overall Length Overall Width Molded Package Width Terminal Width Terminal Thickness Terminal Length Footprint Lead Bend Radius Lead Bend Radius Foot Angle Mold Draft Angle Mold Draft Angle Units Dimension Limits N e A A1 A2 D E E1 b c L L1 R1 R2 θ1 θ2 θ3 MIN – 0.05 0.80 4.90 4.30 0.19 0.09 0.45 0.09 0.09 0° – – MILLIMETERS NOM 14 0.65 BSC – – 1.00 5.00 6.40 BSC 4.40 – – 0.60 1.00 REF – – – 12° REF 12° REF MAX 1.20 0.15 1.05 5.10 4.50 0.30 0.20 0.75 – – 8° – – 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-087 Rev D Sheet 2 of 2 © 2020 Microchip Technology Inc. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 918 PIC18F06/16Q41 Packaging Information 14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging G SILK SCREEN C Y X E RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E Contact Pad Spacing C Contact Pad Width (Xnn) X Contact Pad Length (Xnn) Y Contact Pad to Contact Pad (Xnn) G MIN MILLIMETERS NOM 0.65 BSC 5.90 MAX 0.45 1.45 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2087 Rev D © 2020 Microchip Technology Inc. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 919 M PIC18F06/16Q41 Packaging Information Packaging Diagrams and Parameters 20-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 b eB e Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 20 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .300 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .980 1.030 1.060 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 b1 .045 .060 .070 b .014 .018 .022 eB – – Upper Lead Width Lower Lead Width Overall Row Spacing § .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-019B © 2007 Microchip Technology Inc. DS00049AR-page 52 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 920 PIC18F06/16Q41 Packaging Information 20-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A E 2 E1 2 E1 E 2X 10 TIPS 0.33 C NOTE 1 20X b 0.25 B e C A-B D TOP VIEW A 0.10 C A2 A C SEATING PLANE 20X A1 SIDE VIEW 0.10 C A h SEE DETAIL B h VIEW A–A Microchip Technology Drawing C04-094 Rev D Sheet 1 of 2 © 2020 Microchip Technology Inc. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 921 PIC18F06/16Q41 Packaging Information 20-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging θ2 θ1 R1 R H c θ3 θ L (L1) DETAIL B Notes: Number of Terminals Pitch Overall Height Standoff § Molded Package Thickness Overall Length Overall Width Molded Package Width Terminal Width Terminal Thickness Corner Chamfer Terminal Length Footprint Lead Bend Radius Lead Bend Radius Foot Angle Lead Angle Mold Draft Angle Mold Draft Angle Units Dimension Limits N e A A1 A2 D E E1 b c h L L1 R1 R2 θ θ1 θ2 θ3 MIN 0.10 2.05 0.31 0.25 0.25 0.41 0.07 0.07 0° 0° 5° 5° MILLIMETERS NOM 20 1.27 BSC 12.80 BSC 10.30 BSC 7.50 BSC 0.65 1.40 REF - MAX 2.65 0.30 - 0.51 0.75 0.41 0.89 8° 15° 15° 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 3. Dimension D does not include mold flash, protrusions or gate burrs, which shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion, which shall not exceed 0.25 mm per side. 4. § Significant Characteristic Microchip Technology Drawing C04-094 Rev D Sheet 2 of 2 © 2020 Microchip Technology Inc. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 922 PIC18F06/16Q41 Packaging Information 20-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging G1 20 SILK SCREEN C G Y 1 2 X E RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E Contact Pad Spacing C Contact Pad Width (X20) X Contact Pad Length (X20) Y Contact Pad to Contact Pad G Contact Pad to Contact Pad G1 MIN MILLIMETERS NOM 1.27 BSC 9.40 MAX 0.60 1.95 0.67 7.45 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2094 Rev D © 2020 Microchip Technology Inc. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 923 M PIC18F06/16Q41 Packaging Diagrams and Parameters Packaging Information 20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 Units Dimension Limits Number of Pins L MILLIMETERS MIN N NOM MAX 20 Pitch e Overall Height A – 0.65 BSC – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.20 Molded Package Width E1 5.00 5.30 5.60 Overall Length D 6.90 7.20 7.50 Foot Length L 0.55 0.75 0.95 Footprint L1 1.25 REF Lead Thickness c 0.09 – Foot Angle φ 0° 4° 0.25 8° Lead Width b 0.22 – 0.38 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-072B © 2007 Microchip Technology Inc. DS00049AR-page 114 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 924 PIC18F06/16Q41 Packaging Information 20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.65 0.45 SILK SCREEN c Y1 G X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X20) X1 Contact Pad Length (X20) Y1 Distance Between Pads G MIN MILLIMETERS NOM 0.65 BSC 7.20 MAX 0.45 1.75 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2072B © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 925 PIC18F06/16Q41 Packaging Information 20-Lead Very Thin Plastic Quad Flat, No Lead Package (REB) - 3x3 mm Body [VQFN] With 1.7 mm Exposed Pad; Atmel Legacy Global Package Code ZCL Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 16X 0.08 C D NOTE 1 A 0.10 C B N 1 2 E (DATUM B) (DATUM A) 2X 0.10 C 2X A1 TOP VIEW 0.10 C 0.10 (A3) C A B A SEATING C PLANE D2 SIDE VIEW 0.10 C A B E2 2 (CH) 1 NOTE 1 K N L e BOTTOM VIEW 20X b 0.10 0.05 C A B C Microchip Technology Drawing C04-21380 Rev A Sheet 1 of 2 © 2018 Microchip Technology Inc. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 926 PIC18F06/16Q41 Packaging Information 20-Lead Very Thin Plastic Quad Flat, No Lead Package (REB) - 3x3 mm Body [VQFN] With 1.7 mm Exposed Pad; Atmel Legacy Global Package Code ZCL Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Notes: Units Dimension Limits Number of Terminals N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Length D Exposed Pad Length D2 Overall Width E Exposed Pad Width E2 b Terminal Width Terminal Length L Terminal-to-Exposed-Pad K Pin 1 Index Chamfer CH MIN 0.80 0.00 1.60 1.60 0.15 0.35 0.20 MILLIMETERS NOM 20 0.40 BSC 0.85 0.035 0.203 REF 3.00 BSC 1.70 3.00 BSC 1.70 0.20 0.40 0.35 REF MAX 0.90 0.05 1.80 1.80 0.25 0.45 - 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-21380 Rev A Sheet 2 of 2 © 2018 Microchip Technology Inc. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 927 PIC18F06/16Q41 Packaging Information 20-Lead Very Thin Plastic Quad Flat, No Lead Package (REB) - 3x3 mm Body [VQFN] With 1.7 mm Exposed Pad; Atmel Legacy Global Package Code ZCL Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV ØV G2 C2 Y2 EV G1 Y1 X1 SILK SCREEN E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X20) X1 Contact Pad Length (X20) Y1 Contact Pad to Center Pad (X20) G1 Contact Pad to Contact Pad (X16) G2 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.40 BSC MAX 1.80 1.80 3.00 3.00 0.20 0.80 0.20 0.20 0.30 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-23380 Rev A © 2018 Microchip Technology Inc. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 928 PIC18F06/16Q41 Appendix A: Revision History 51. Appendix A: Revision History Doc. Rev. Date Comments E 09/2021 Updating the Interrupts chapter, Ports chapter, and the 20-lead VQFN marking examples D 05/2021 Updating the OPA chapter with structural changes and the DMA Special Function Register tables C 10/2020 Updating the NVM, I2C, and UART chapters with grammatical edits and features B 07/2020 Updated the Electrical Specifications chapter. Other minor changes. A 05/2020 Initial document release © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 929 PIC18F06/16Q41 The Microchip Website Microchip provides online support via our website at www.microchip.com/. This website is used to make files and information easily available to customers. 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Customer Support Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Embedded Solutions Engineer (ESE) Technical Support Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in this document. Technical support is available through the website at: www.microchip.com/support © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 930 PIC18F06/16Q41 Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device [X](1) –X /XX Tape Temperature and Reel Range Package Device: PIC18F04Q41, PIC18F14Q41, PIC18F05Q41, PIC18F15Q41, PIC18F06Q41, PIC18F16Q41 Tape & Reel Option: Blank = Standard Packaging (tube or tray) T = Tape & Reel I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) SL = 14-lead SOIC ST = 14-lead TSSOP P = 20-lead PDIP SO = 20-lead SOIC SS = 20-lead SSOP REB = 20-lead VQFN Temperature Range: Package: Examples: • PIC18F04Q41 T-E/ST: Tape and Reel, Extended temperature, 14-lead TSSOP • PIC18F15Q41 T-I/REB: Tape and Reel, Industrial temperature, 20-lead VQFN • PIC18F16Q41 T-I/SO: Tape and Reel, Industrial temperature, 20-lead SOIC Notes:  1. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2. Small form-factor packaging options may be available. Please check www.microchip.com/packaging for smallform factor package availability, or contact your local Sales Office. Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip products: • • • • Microchip products meet the specifications contained in their particular Microchip Data Sheet. Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions. Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 931 PIC18F06/16Q41 Legal Notice This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at www.microchip.com/en-us/support/ design-help/client-support-services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, NVM Express, NVMe, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAMICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, Symmcom, and Trusted Time are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 932 PIC18F06/16Q41 All other trademarks mentioned herein are property of their respective companies. © 2020-2021, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved. ISBN: 978-1-5224-8976-4 Quality Management System For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality. © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 933 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: www.microchip.com/support Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 Australia - Sydney Tel: 61-2-9868-6733 China - Beijing Tel: 86-10-8569-7000 China - Chengdu Tel: 86-28-8665-5511 China - Chongqing Tel: 86-23-8980-9588 China - Dongguan Tel: 86-769-8702-9880 China - Guangzhou Tel: 86-20-8755-8029 China - Hangzhou Tel: 86-571-8792-8115 China - Hong Kong SAR Tel: 852-2943-5100 China - Nanjing Tel: 86-25-8473-2460 China - Qingdao Tel: 86-532-8502-7355 China - Shanghai Tel: 86-21-3326-8000 China - Shenyang Tel: 86-24-2334-2829 China - Shenzhen Tel: 86-755-8864-2200 China - Suzhou Tel: 86-186-6233-1526 China - Wuhan Tel: 86-27-5980-5300 China - Xian Tel: 86-29-8833-7252 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 India - Bangalore Tel: 91-80-3090-4444 India - New Delhi Tel: 91-11-4160-8631 India - Pune Tel: 91-20-4121-0141 Japan - Osaka Tel: 81-6-6152-7160 Japan - Tokyo Tel: 81-3-6880- 3770 Korea - Daegu Tel: 82-53-744-4301 Korea - Seoul Tel: 82-2-554-7200 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 Malaysia - Penang Tel: 60-4-227-8870 Philippines - Manila Tel: 63-2-634-9065 Singapore Tel: 65-6334-8870 Taiwan - Hsin Chu Tel: 886-3-577-8366 Taiwan - Kaohsiung Tel: 886-7-213-7830 Taiwan - Taipei Tel: 886-2-2508-8600 Thailand - Bangkok Tel: 66-2-694-1351 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4485-5910 Fax: 45-4485-2829 Finland - Espoo Tel: 358-9-4520-820 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-72400 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Israel - Ra’anana Tel: 972-9-744-7705 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-72884388 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 © 2020-2021 Microchip Technology Inc. and its subsidiaries Preliminary Datasheet DS40002214E-page 934 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Microchip: PIC18F16Q41-E/SS PIC18F16Q41-I/SO PIC18F16Q41-I/SS PIC18F16Q41T-I/SS PIC18F16Q41-E/REB PIC18F06Q41T-I/ST PIC18F16Q41T-I/REB PIC18F16Q41-I/REB PIC18F16Q41-E/SO PIC18F06Q41-I/ST PIC18F06Q41-E/ST PIC18F16Q41-I/P PIC18F16Q41T-I/SO PIC18F16Q41-E/P PIC18F06Q41-I/SL PIC18F06Q41TI/SL PIC18F06Q41-E/SL