PIC18F66K80 FAMILY
28/40/44/64-Pin, Enhanced Flash Microcontrollers
with ECAN™ XLP Technology
Power-Managed Modes:
ECAN Bus Module Features (Continued):
•
•
•
•
•
•
•
•
•
•
•
•
• 16 Full, 29-Bit Acceptance Filters with Dynamic
Association
• Three Full, 29-Bit Acceptance Masks
• Automatic Remote Frame Handling
• Advanced Error Management Features
Run: CPU on, Peripherals on
Idle: CPU off, Peripherals on
Sleep: CPU off, Peripherals off
Two-Speed Oscillator Start-up
Fail-Safe Clock Monitor (FSCM)
Power-Saving Peripheral Module Disable (PMD)
Ultra Low-Power Wake-up
Fast Wake-up, 1 s, Typical
Low-Power WDT, 300 nA, Typical
Run mode Currents Down to Very Low 3.8 A, Typical
Idle mode Currents Down to Very Low 880 nA, Typical
Sleep mode Current Down to Very Low 13 nA, Typical
Special Microcontroller Features:
• Operating Voltage Range: 1.8V to 5.5V
• On-Chip 3.3V Regulator
• Operating Speed up to 64 MHz
• Up to 64 Kbytes On-Chip Flash Program Memory:
- 10,000 erase/write cycle, typical
- 20 years minimum retention, typical
• 1,024 Bytes of Data EEPROM:
- 100,000 Erase/write cycle data EEPROM
memory, typical
• 3.6 Kbytes of General Purpose Registers (SRAM)
• Three Internal Oscillators: LF-INTOSC (31 KHz),
MF-INTOSC (500 kHz) and HF-INTOSC (16 MHz)
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 4,194s
• In-Circuit Serial Programming™ (ICSP™) via Two Pins
• In-Circuit Debug via Two Pins
• Programmable BOR
• Programmable LVD
ECAN Bus Module Features:
• Conforms to CAN 2.0B Active Specification
• Three Operating modes:
- Legacy mode (full backward compatibility with
existing PIC18CXX8/FXX8 CAN modules)
- Enhanced mode
- FIFO mode or programmable TX/RX buffers
• Message Bit Rates up to 1 Mbps
• DeviceNet™ Data Byte Filter Support
• Six Programmable Receive/Transmit Buffers
• Three Dedicated Transmit Buffers with Prioritization
• Two Dedicated Receive Buffers
2010-2017 Microchip Technology Inc.
BORMV/LVD
DSM
28
28
28
28
40/44
40/44
40/44
40/44
64
64
64
64
MSSP
1,024
1,024
1,024
1,024
1,024
1,024
1,024
1,024
1,024
1,024
1,024
1,024
ECAN™
3,648
3,648
3,648
3,648
3,648
3,648
3,648
3,648
3,648
3,648
3,648
3,648
Comparators
32 Kbytes
32 Kbytes
64 Kbytes
64 Kbytes
32 Kbytes
32 Kbytes
64 Kbytes
64 Kbytes
32 Kbytes
32 Kbytes
64 Kbytes
64 Kbytes
I/O
EUSART
PIC18F25K80
PIC18LF25K80
PIC18F26K80
PIC18LF26K80
PIC18F45K80
PIC18LF45K80
PIC18F46K80
PIC18LF46K80
PIC18F65K80
PIC18LF65K80
PIC18F66K80
PIC18LF66K80
Data
Data EE
Memory
Pins
(Bytes)
(Bytes)
Timers
8-Bit/16-Bit
Program
Memory
CCP/
ECCP
Device
12-Bit A/D
Channels
DEVICE COMPARISON
CTMU
TABLE 1:
24
24
24
24
35
35
35
35
54
54
54
54
1
1
1
1
1
1
1
1
1
1
1
1
8-ch
8-ch
8-ch
8-ch
11-ch
11-ch
11-ch
11-ch
11-ch
11-ch
11-ch
11-ch
4/1
4/1
4/1
4/1
4/1
4/1
4/1
4/1
4/1
4/1
4/1
4/1
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
DS30009977G-page 1
PIC18F66K80 FAMILY
Peripheral Highlights:
• Five CCP/ECCP modules:
- Four Capture/Compare/PWM (CCP) modules
- One Enhanced Capture/Compare/PWM
(ECCP) module
• Five 8/16-Bit Timer/Counter modules:
- Timer0: 8/16-bit timer/counter with 8-bit
programmable prescaler
- Timer1, Timer3: 16-bit timer/counter
- Timer2, Timer4: 8-bit timer/counter
• Two Analog Comparators
• Configurable Reference Clock Output
• Charge Time Measurement Unit (CTMU):
- Capacitance measurement
- Time measurement with 1 ns typical resolution
- Integrated voltage reference
DS30009977G-page 2
• High-Current Sink/Source 25 mA/25 mA
(PORTB and PORTC)
• Up to Four External Interrupts
• One Master Synchronous Serial Port
(MSSP) module:
- 3/4-wire SPI (supports all four SPI modes)
- I2C™ Master and Slave modes
• Two Enhanced Addressable USART modules:
- LIN/J2602 support
- Auto-Baud Detect (ABD)
• 12-Bit A/D Converter with up to 11 Channels:
- Auto-acquisition and Sleep operation
- Differential Input mode of operation
• Data Signal Modulator module:
- Select modulator and carrier sources from
various module outputs
• Integrated Voltage Reference
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
Pin Diagrams
Note 1:
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/C2INA/ECCP1/P1A/CTPLS/KBI0
23
22
RB7/PGD/T3G/RX2/DT2/KBI3
RB6/PGC/TX2/CK2/KBI2
14
RC5/SDO
RC6/CANTX/TX1/CK1/CCP3
RC4/SDA/SDI
RC3/REFO/SCL/SCK
RC0/SOSCO/SCLKI
8
OSC2/CLKOUT/RA6
5
6
7
RC2/T1G/CCP2
VSS
OSC1/CLKIN/RA7
PIC18F2XK80
PIC18LF2XK80
9
10
11
12
13
VDDCORE/VCAP
RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI
1
2
3
4
RC1/SOSCI
RA2/VREF-/AN2
RA3/VREF+/AN3
25
24
RA0/CVREF/AN0/ULPWU
MCLR/RE3
28
27
26
RA1/AN1
28-Pin QFN(1)
21
20
19
18
17
16
15
RB3/CANRX/C2OUT/P1D/CTED2/INT3
RB2/CANTX/C1OUT/P1C/CTED1/INT2
RB1/AN8/C1INB/P1B/CTDIN/INT1
RB0/AN10/C1INA/FLT0/INT0
VDD
VSS
RC7/CANRX/RX1/DT1/CCP4
For the QFN package, it is recommended that the bottom pad be connected to VSS.
2010-2017 Microchip Technology Inc.
DS30009977G-page 3
PIC18F66K80 FAMILY
Pin Diagrams (Continued)
28-Pin SSOP/SPDIP/SOIC
MCLR/RE3
1
28
RB7/PGD/T3G/RX2/DT2/KBI3
RA0/CVREF/AN0/ULPWU
27
RB6/PGC/TX2/CK2/KBI2
RA1/AN1
2
3
RB5/T0CKI/T3CKI/CCP5/KBI1
RA2/VREF-/AN2
4
26
25
RA3/VREF+/AN3
5
6
RB4/AN9/C2INA/ECCP1/P1A/CTPLS/KBI0
24
RB3/CANRX/C2OUT/P1D/CTED2/INT3
23
RB2/CANTX/C1OUT/P1C/CTED1/INT2
22
RB1/AN8/C1INB/P1B/CTDIN/INT1
RB0/AN10/C1INA/FLT0/INT0
OSC2/CLKOUT/RA6
9
10
21
20
19
RC0/SOSCO/SCLKI
11
18
RC7/CANRX/RX1/DT1/CCP4
RC1/ISOSCI
17
16
RC6/CANTX/TX1/CK1/CCP3
RC2/T1G/CCP2
12
13
RC3/REFO/SCL/SCK
14
15
RC4/SDA/SDI
VDDCORE/VCAP
RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI
VSS
OSC1/CLKIN/RA7
7
8
PIC18F2XK80
PIC18LF2XK80
VDD
VSS
RC5/SDO
40-Pin PDIP
MCLR/RE3
1
40
RB7/PGD/T3G/KBI3
RA0/CVREF/AN0/ULPWU
39
RB6/PGC/KBI2
RA1/AN1/C1INC
2
3
RB5/T0CKI/T3CKI/CCP5/KBI1
RA2/VREF-/AN2/C2INC
4
38
37
RA3/VREF+/AN3
5
6
36
RB3/CANRX/CTED2/INT3
35
RB2/CANTX/CTED1/INT2
7
8
34
33
RB1/AN8/CTDIN/INT1
32
VDD
RE2/AN7/C2OUT/CS
9
10
31
VSS
VDD
11
30
RD7/RX2/DT2/P1D/PSP7
VSS
12
13
29
RD6/TX2/CK2/P1C/PSP6
28
RD5/P1B/PSP5
27
RD4/ECCP1/P1A/PSP4
26
25
RC7/CANRX/RX1/DT1/CCP4
RC1/SOSCI
14
15
16
RC2/T1G/CCP2
17
24
RC5/SDO
RC3/REFO/SCL/SCK
18
23
RC4/SDA/SDI
RD0/C1INA/PSP0
19
22
RD3/C2INB/CTMUI/PSP3
RD1/C1INB/PSP1
20
21
RD2/C2INA/PSP2
VDDCORE/VCAP
RA5/AN4/HLVDIN/T1CKI/SS
RE0/AN5/RD
RE1/AN6/C1OUT/WR
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
RC0/SOSCO/SCLKI
DS30009977G-page 4
PIC18F4XK80
PIC18LF4XK80
RB4/AN9/CTPLS/KBI0
RB0/AN10/FLT0/INT0
RC6/CANTX/TX1/CK1/CCP3
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
Pin Diagrams (Continued)
RD2/C2INA/PSP2
RD1/C1INB/PSP1
RD0/C1INA/PSP0
RC1/SOSCI
N/C
39
38
37
36
35
34
RB1/AN8/CTDIN/INT1
9
10
11
2010-2017 Microchip Technology Inc.
N/C
32
RC0/SOSCO/SCLKI
31
30
29
28
27
OSC2/CLKOUT/RA6
OSC1/CLKIN/RA7
18
19
20
21
22
MCLR/RE3
RA3/VREF+/AN3
RA2/VREF-/AN2/C2INC
17
RB7/PGD/T3G/KBI3
RA1/AN1/C1INC
14
15
16
RB4/AN9/CTPLS/KBI0
26
25
24
23
12
13
PIC18F4XK80
PIC18LF4XK80
33
N/C
RB3/CANRX/CTED2/INT3
RC2/T1G/CCP2
RC4/SDA/SDI
8
RB2/CANTX/CTED1/INT2
RC3/REFO/SCL/SCK
RC5/SDO
42
41
40
RB0/AN10/FLT0/INT0
VSS
RD3/C2INB/CTMUI/PSP3
RC6/CANTX/TX1/CK1/CCP3
43
VDD
5
6
7
RD7/RX2/DT2/P1D/PSP7
RA0/CVREF/AN0/ULPWU
RD6/TX2/CK2/P1C/PSP6
RB6/PGC/KBI2
RD5/P1B/PSP5
1
2
3
4
RB5/T0CKI/T3CKI/CCP5/KBI1
RD4/ECCP1/P1A/PSP4
N/C
RC7/CANRX/RX1/DT1/CCP4
44
44-Pin TQFP
VSS
VDD
RE2/AN7/C2OUT/CS
RE1/AN6/C1OUT/WR
RE0/AN5/RD
RA5/AN4/HLVDIN/T1CKI/SS
VDDCORE/VCAP
DS30009977G-page 5
PIC18F66K80 FAMILY
Pin Diagrams (Continued)
RD1/C1INB/PSP1
RD0/C1INA/PSP0
RC1/SOSCI
N/C
38
37
36
35
34
RC2/T1G/CCP2
RD2/C2INA/PSP2
39
RC3/REFO/SCL/SCK
RC4/SDA/SDI
42
41
40
RB1/AN8/CTDIN/INT1
9
10
11
RA2/VREF-/AN2/C2INC
RA1/AN1/C1INC
RA0/CVREF/AN0/ULPWU
13
14
15
16
17
N/C
32
RC0/SOSCO/SCLKI
31
30
29
28
27
OSC2/CLKOUT/RA6
OSC1/CLKIN/RA7
26
25
24
23
RE1/AN6/C1OUT/WR
18
19
20
21
22
12
N/C
N/C
PIC18F4XK80
PIC18LF4XK80
33
VSS
VDD
RE2/AN7/C2OUT/CS
RE0/AN5/RD
RA5/AN4/HLVDIN/T1CKI/SS
VDDCORE/VCAP
RA3/VREF+/AN3
8
RB2/CANTX/CTED1/INT2
RD3/C2INB/CTMUI/PSP3
RC5/SDO
43
RB0/AN10/FLT0/INT0
RB3/CANRX/CTED2/INT3
Note 1:
RC6/CANTX/TX1/CK1/CCP3
VDD
5
6
7
VSS
MCLR/RE3
RD7/RX2/DT2/P1D/PSP7
RB7/PGD/T3G/KBI3
RD6/TX2/CK2/P1C/PSP6
RB6/PGC/KBI2
RD5/P1B/PSP5
1
2
3
4
RB5/T0CKI/T3CKI/CCP5/KBI1
RD4/ECCP1/P1A/PSP4
RB4/AN9/CTPLS/KBI0
RC7/CANRX/RX1/DT1/CCP4
44
44-Pin QFN(1)
For the QFN package, it is recommended that the bottom pad be connected to VSS.
DS30009977G-page 6
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
Pin Diagrams (Continued)
RC7/CCP4
RD4/ECCP1/P1A/PSP4
RD5/P1B/PSP5
RD6/P1C/PSP6
RD7/P1D/PSP7
RG0/RX1/DT1
RG1/CANTX2
VSS
AVDD
VDD
RG2/T3CKI
RG3/TX1/CK1
RB0/AN10/FLT0/INT0
RB1/AN8/CTDIN/INT1
RB2/CANTX/CTED1/INT2
RC1/SOSCI
RC2/T1G/CCP2
RC3/REFO/SCL/SCK
RF6/MDOUT
RF7
RD0/C1INA/PSP0
RD1/C1INB/PSP1
VSS
VDD
RD2/C2INA/PSP2
RD3/C2INB/CTMUI/PSP3
RC4/SDA/SDI
62
61
60
RE6/RX2/DT2
RC5/SDO
63
59
58
57
56
55
54
53
52
51
50
49
RC6/CCP3
64
48
47
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
46
45
44
43
42
PIC18F6XK80
PIC18LF6XK80
RC0/SOSCO/SCLKI
OSC2/CLKOUT/RA6
OSC1/CLKIN/RA7
RF5
RF4/MDCIN2
VSS
AVSS
41
40
39
38
37
VDD
36
35
34
33
RF3
AVDD
RE2/AN7/C2OUT/CS
RE1/AN6/C1OUT/WR
RE0/AN5/RD
RF2/MDCIN1
RA5/AN4/HLVDIN/T1CKI/SS
VDDCORE/VCAP
Note 1:
RA3/VREF+/AN3
RA2/VREF-/AN2/C2INC
RA1/AN1/C1INC
RA0/CVREF/AN0/ULPWU
MCLR/RE3
RE4/CANRX
VSS
VDD
RE5/CANTX
RB6/PGC/KBI2
RB7/PGD/T3G/KBI3
RB5/T0CKI/T3CKI/CCP5/KBI1
RB4/AN9/CTPLS/KBI0
RF1
RG4/T0CKI
RF0/MDMIN
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RB3/CANRX/CTED2/INT3
RE7/TX2/CK2
64-Pin QFN(1)/TQFP
For the QFN package, it is recommended that the bottom pad be connected to VSS.
2010-2017 Microchip Technology Inc.
DS30009977G-page 7
PIC18F66K80 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 10
2.0 Guidelines for Getting Started with PIC18FXXKXX Microcontrollers ......................................................................................... 43
3.0 Oscillator Configurations ............................................................................................................................................................ 48
4.0 Power-Managed Modes ............................................................................................................................................................. 61
5.0 Reset .......................................................................................................................................................................................... 75
6.0 Memory Organization ................................................................................................................................................................. 97
7.0 Flash Program Memory ............................................................................................................................................................ 125
8.0 Data EEPROM Memory ........................................................................................................................................................... 134
9.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 140
10.0 Interrupts .................................................................................................................................................................................. 142
11.0 I/O Ports ................................................................................................................................................................................... 165
12.0 Data Signal Modulator.............................................................................................................................................................. 189
13.0 Timer0 Module ......................................................................................................................................................................... 199
14.0 Timer1 Module ......................................................................................................................................................................... 202
15.0 Timer2 Module ......................................................................................................................................................................... 214
16.0 Timer3 Module ......................................................................................................................................................................... 217
17.0 Timer4 Modules........................................................................................................................................................................ 227
18.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 229
19.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 247
20.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 259
21.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 281
22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 326
23.0 12-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 350
24.0 Comparator Module.................................................................................................................................................................. 365
25.0 Comparator Voltage Reference Module ................................................................................................................................... 373
26.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 376
27.0 ECAN Module........................................................................................................................................................................... 382
28.0 Special Features of the CPU .................................................................................................................................................... 447
29.0 Instruction Set Summary .......................................................................................................................................................... 473
30.0 Development Support............................................................................................................................................................... 523
31.0 Electrical Characteristics .......................................................................................................................................................... 527
32.0 Packaging Information.............................................................................................................................................................. 571
Appendix A: Revision History............................................................................................................................................................. 590
Appendix B: Migration to PIC18F66K80 Family................................................................................................................................. 591
The Microchip Web Site ..................................................................................................................................................................... 593
Customer Change Notification Service .............................................................................................................................................. 593
Customer Support .............................................................................................................................................................................. 593
Product Identification System............................................................................................................................................................. 595
DS30009977G-page 8
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2010-2017 Microchip Technology Inc.
DS30009977G-page 9
PIC18F66K80 FAMILY
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
•
•
•
•
•
•
PIC18F25K80
PIC18F26K80
PIC18F45K80
PIC18F46K80
PIC18F65K80
PIC18F66K80
•
•
•
•
•
•
PIC18LF25K80
PIC18LF26K80
PIC18LF45K80
PIC18LF46K80
PIC18LF65K80
PIC18LF66K80
This family combines the traditional advantages of all
PIC18 microcontrollers – namely, high computational
performance and a rich feature set – with an extremely
competitive price point. These features make the
PIC18F66K80 family a logical choice for many
high-performance applications where price is a primary
consideration.
1.1
1.1.1
Core Features
TECHNOLOGY
All of the devices in the PIC18F66K80 family incorporate a range of features that can significantly reduce
power consumption during operation. Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the Internal RC oscillator, power consumption during code execution
can be reduced.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further.
• On-the-Fly Mode Switching: The power-managed
modes are invoked by user code during operation,
allowing the user to incorporate power-saving ideas
into their application’s software design.
• XLP: An extra low-power BOR and low-power
Watchdog timer
1.1.2
OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC18F66K80 family offer
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• External Resistor/Capacitor (RC); RA6 available
• External Resistor/Capacitor with Clock Out (RCIO)
• Three External Clock modes:
- External Clock (EC); RA6 available
- External Clock with Clock Out (ECIO)
- External Crystal (XT, HS, LP)
DS30009977G-page 10
• A Phase Lock Loop (PLL) frequency multiplier,
available to the external oscillator modes which
allows clock speeds of up to 64 MHz. PLL can
also be used with the internal oscillator.
• An internal oscillator block that provides a 16 MHz
clock (±2% accuracy) and an INTOSC source
(approximately 31 kHz, stable over temperature
and VDD)
- Operates as HF-INTOSC or MF-INTOSC
when block is selected for 16 MHz or
500 kHz
- Frees the two oscillator pins for use as
additional general purpose I/O
The internal oscillator block provides a stable reference
source that gives the family additional features for
robust operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
1.1.3
MEMORY OPTIONS
The PIC18F66K80 family provides ample room for
application code, from 32 Kbytes to 64 Kbytes of code
space. The Flash cells for program memory are rated
to last up to 10,000 erase/write cycles. Data retention
without refresh is conservatively estimated to be
greater than 20 years.
The Flash program memory is readable and writable.
During normal operation, the PIC18F66K80 family also
provides plenty of room for dynamic application data
with up to 3.6 Kbytes of data RAM.
1.1.4
EXTENDED INSTRUCTION SET
The PIC18F66K80 family implements the optional
extension to the PIC18 instruction set, adding eight
new instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as ‘C’.
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
1.1.5
EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 28-pin,
40-pin, 44-pin and 64-pin members, or even jumping
from smaller to larger memory devices.
The PIC18F66K80 family is also largely pin compatible
with other PIC18 families, such as the PIC18F4580,
PIC18F4680 and PIC18F8680 families of microcontrollers with an ECAN module. This allows a new dimension to the evolution of applications, allowing
developers to select different price points within
Microchip’s PIC18 portfolio, while maintaining a similar
feature set.
1.2
Other Special Features
• Communications: The PIC18F66K80 family incorporates a range of serial communication peripherals,
including two Enhanced USARTs that support
LIN/J2602, one Master SSP module capable of both
SPI and I2C™ (Master and Slave) modes of
operation and an Enhanced CAN module.
• CCP Modules: PIC18F66K80 family devices
incorporate four Capture/Compare/PWM (CCP)
modules. Up to four different time bases can be
used to perform several different operations at
once.
• ECCP Modules: The PIC18F66K80 family has
one Enhanced CCP (ECCP) module to maximize
flexibility in control applications:
- Up to four different time bases for performing
several different operations at once
- Up to four PWM outputs
- Other beneficial features, such as polarity
selection, programmable dead time,
auto-shutdown and restart, and Half-Bridge
and Full-Bridge Output modes
• 12-Bit A/D Converter: The PIC18F66K80 family
has a differential A/D. It incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, and
thus, reducing code overhead.
2010-2017 Microchip Technology Inc.
• Charge Time Measurement Unit (CTMU): The
CTMU is a flexible analog module that provides
accurate differential time measurement between
pulse sources, as well as asynchronous pulse
generation.
Together with other on-chip analog modules, the
CTMU can precisely measure time, measure
capacitance or relative changes in capacitance, or
generate output pulses that are independent of the
system clock.
• LP Watchdog Timer (WDT): This enhanced
version incorporates a 22-bit prescaler, allowing
an extended time-out range that is stable across
operating voltage and temperature. See
Section 31.0 “Electrical Characteristics” for
time-out periods.
1.3
Details on Individual Family
Members
Devices in the PIC18F66K80 family are available in
28-pin, 40/44-pin and 64-pin packages. Block diagrams
for each package are shown in Figure 1-1, Figure 1-2
and Figure 1-3, respectively.
The devices are differentiated from each other in these
ways:
• Flash Program Memory:
- PIC18FX5K80 (PIC18F25K80, PIC18F45K80
and PIC18F45K80) – 32 Kbytes
- PIC18FX6K80 (PIC18F26K80, PIC18F46K80
and PIC18F66K80) – 64 Kbytes
• I/O Ports:
- PIC18F2XK80 (28-pin devices) –
Three bidirectional ports
- PIC18F4XK80 (40/44-pin devices) –
Five bidirectional ports
- PIC18F6XK80 (64-pin devices) –
Seven bidirectional ports
All other features for devices in this family are identical.
These are summarized in Table 1-1, Table 1-2 and
Table 1-3.
The pinouts for all devices are listed in Table 1-4,
Table 1-5 and Table 1-6.
DS30009977G-page 11
PIC18F66K80 FAMILY
TABLE 1-1:
DEVICE FEATURES FOR THE PIC18F2XK80 (28-PIN DEVICES)
Features
PIC18F25K80
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
PIC18F26K80
DC – 64 MHz
32K
64K
16,384
32,768
Data Memory (Bytes)
3.6K
Interrupt Sources
31
I/O Ports
Ports A, B, C
Parallel Communications
Parallel Slave Port (PSP)
Timers
Five
Comparators
Two
CTMU
Yes
Capture/Compare/PWM (CCP)
Modules
Four
Enhanced CCP (ECCP) Modules
Serial Communications
One
One MSSP and Two Enhanced USARTs (EUSART)
12-Bit Analog-to-Digital Module
Resets (and Delays)
Instruction Set
Eight Input Channels
POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR,
WDT (PWRT, OST)
75 Instructions, 83 with Extended Instruction Set Enabled
Packages
28-Pin QFN-S, SOIC, SPDIP and SSOP
TABLE 1-2:
DEVICE FEATURES FOR THE PIC18F4XK80 (40/44-PIN DEVICES)
Features
PIC18F45K80
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Interrupt Sources
I/O Ports
Parallel Communications
PIC18F46K80
DC – 64 MHz
32K
64K
16,384
32,768
3.6K
32
Ports A, B, C, D, E
Parallel Slave Port (PSP)
Timers
Five
Comparators
Two
CTMU
Yes
Capture/Compare/PWM (CCP)
Modules
Four
Enhanced CCP (ECCP) Modules
Serial Communications
12-Bit Analog-to-Digital Module
Resets (and Delays)
Instruction Set
Packages
DS30009977G-page 12
One
One MSSP and Two Enhanced USARTs (EUSART)
Eleven Input Channels
POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR,
WDT (PWRT, OST)
75 Instructions, 83 with Extended Instruction Set Enabled
40-Pin PDIP and 44-Pin QFN and TQFP
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-3:
DEVICE FEATURES FOR THE PIC18F6XK80 (64-PIN DEVICES)
Features
PIC18F65K80
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
PIC18F66K80
DC – 64 MHz
32K
64K
16,384
32,768
Data Memory (Bytes)
3.6K
Interrupt Sources
32
I/O Ports
Ports A, B, C, D, E, F, G
Parallel Communications
Parallel Slave Port (PSP)
Timers
Five
Comparators
Two
CTMU
Yes
Capture/Compare/PWM (CCP)
Modules
Four
Enhanced CCP (ECCP) Modules
DSM
Serial Communications
12-Bit Analog-to-Digital Module
Resets (and Delays)
Instruction Set
Packages
2010-2017 Microchip Technology Inc.
One
Yes
Yes
One MSSP and Two Enhanced USARTs (EUSART)
Eleven Input Channels
POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR,
WDT (PWRT, OST)
75 Instructions, 83 with Extended Instruction Set Enabled
64-Pin QFN and TQFP
DS30009977G-page 13
PIC18F66K80 FAMILY
FIGURE 1-1:
PIC18F2XK80 (28-PIN) BLOCK DIAGRAM
Data Bus
Table Pointer
8
inc/dec logic
Data Memory
(2/4 Kbytes)
PCLATU PCLATH
21
PORTA
RA
RA(1,2)
Data Latch
8
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address
31-Level Stack
4
BSR
Address Latch
STKPTR
Program Memory
8
4
Access
Bank
12
FSR0
FSR1
FSR2
Data Latch
PORTB
RB(1)
12
PORTC
RC(1)
inc/dec
logic
Table Latch
Address
Decode
ROM Latch
Instruction Bus
PORTE
RE3(1,3)
IR
8
Instruction
Decode and
Control
Timing
Generation
OSC2/CLKO
OSC1/CLKI
Note
8
W
8
8
8
8
8
ALU
Watchdog
Timer
8
BOR and
LVD
VDDCORE/VCAP
ECCP1
8 x 8 Multiply
BITOP
Power-on
Reset
Voltage
Regulator
CCP2/3/4/5
3
Oscillator
Start-up Timer
Precision
Band Gap
Reference
Timer1
PRODH PRODL
Power-up
Timer
INTOSC
Oscillator
16 MHz
Oscillator
Timer0
State Machine
Control Signals
VDD, VSS
Timer 2/4
EUSART1
MCLR
Timer 3
EUSART2
A/D
12-Bit
CTMU
MSSP
Comparator
1/2
ECAN
1:
See Table 1-4 for I/O port pin descriptions.
2:
RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator
Configurations”.
3:
RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0).
DS30009977G-page 14
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
FIGURE 1-2:
PIC18F4XK80 (40/44-PIN) BLOCK DIAGRAM
Data Bus
Table Pointer
8
inc/dec logic
Data Memory
(2/4 Kbytes)
PCLATU PCLATH
21
PORTA
RA
RA(1,2)
Data Latch
8
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address
31-Level Stack
4
BSR
Address Latch
STKPTR
Program Memory
8
4
Access
Bank
12
FSR0
FSR1
FSR2
Data Latch
PORTB
RB(1)
12
PORTC
RC7:0>(1)
inc/dec
logic
Table Latch
Address
Decode
ROM Latch
Instruction Bus
PORTD
RD(1)
IR
OSC2/CLKO
OSC1/CLKI
Timing
Generation
Note
ECCP1
8
W
8
8
8
8
8
ALU
Watchdog
Timer
8
BOR and
LVD
VDDCORE/VCAP
CCP
2/3/4/5
RE(1,3)
8 x 8 Multiply
BITOP
Power-on
Reset
Voltage
Regulator
Timer1
3
Oscillator
Start-up Timer
Precision
Band Gap
Reference
PORTE
PRODH PRODL
Power-up
Timer
INTOSC
Oscillator
16 MHz
Oscillator
Timer0
8
State Machine
Control Signals
Instruction
Decode and
Control
VDD, VSS
MCLR
Timer2/4
EUSART1
Timer3
EUSART2
MSSP
CTMU
ECAN
A/D
12-Bit
Comparator
1/2
PSP
1:
See Table 1-5 for I/O port pin descriptions.
2:
RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator
Configurations”.
3:
RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0).
2010-2017 Microchip Technology Inc.
DS30009977G-page 15
PIC18F66K80 FAMILY
FIGURE 1-3:
PIC18F6XK80 (64-PIN) BLOCK DIAGRAM
Data Bus
Table Pointer
inc/dec logic
Data Memory
(2/4 Kbytes)
PCLATU PCLATH
21
PORTA
RA
RA(1,2)
Data Latch
8
8
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address
31-Level Stack
4
BSR
Address Latch
STKPTR
Program Memory
8
4
Access
Bank
12
FSR0
FSR1
FSR2
Data Latch
PORTB
RB(1)
12
PORTC
RC(1)
inc/dec
logic
Table Latch
Address
Decode
ROM Latch
Instruction Bus
PORTD
RD(1)
IR
OSC2/CLKO
OSC1/CLKI
8
State Machine
Control Signals
Instruction
Decode and
Control
3
Timing
Generation
Power-up
Timer
INTOSC
Oscillator
16 MHz
Oscillator
Oscillator
Start-up Timer
RE(1,3)
8 x 8 Multiply
8
BITOP
W
8
8
8
8
Power-on
Reset
Precision
Band Gap
Reference
PORTE
PRODH PRODL
8
PORTF
RF(1)
ALU
Watchdog
Timer
8
BOR and
LVD
Voltage
Regulator
PORTG
RG(1)
VDDCORE/VCAP
Timer0
Timer1
CCP2/3/4/5
ECCP1
Note 1:
VDD, VSS
MCLR
Timer2/4
EUSART1
CTMU
Timer3
EUSART2
MSSP
ECAN
A/D
12-Bit
PSP
Comparator
1/2
DSM
See Table 1-6 for I/O port pin descriptions.
2:
RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator
Configurations”.
3:
RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0).
DS30009977G-page 16
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-4:
PIC18F2XK80 I/O DESCRIPTIONS
Pin Number
SSOP/ Pin Buffer
QFN SPDIP Type Type
/SOIC
Pin Name
26
MCLR/RE3
Description
1
MCLR
I
ST
Master Clear (input) or programming voltage (input). This
pin is an active-low Reset to the device.
RE3
I
ST
General purpose, input only pin.
OSC1
I
ST
Oscillator crystal input.
CLKIN
I
OSC1/CLKIN/RA7
6
9
RA7
I/O
OSC2/CLKOUT/RA6
7
CMOS External clock source input. Always associated with pin
function, OSC1. (See related OSC1/CLKI, OSC2/CLKO
pins.)
ST/
General purpose I/O pin.
CMOS
10
OSC2
O
—
Oscillator crystal output.
Connects to crystal or resonator in Crystal Oscillator mode.
CLKOUT
O
—
In certain oscillator modes, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
RA6
I/O
Legend: CMOS
ST
I
P
ST/
General purpose I/O pin.
CMOS
= CMOS compatible input or output
= Schmitt Trigger input with CMOS levels
= Input
= Power
2010-2017 Microchip Technology Inc.
I2C™
= I2C/SMBus input buffer
Analog = Analog input
O
= Output
DS30009977G-page 17
PIC18F66K80 FAMILY
TABLE 1-4:
PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
SSOP/ Pin Buffer
QFN SPDIP Type Type
/SOIC
Pin Name
Description
PORTA is a bidirectional I/O port.
RA0/CVREF/AN0/ULPWU
27
2
RA0
I/O
ST/
General purpose I/O pin.
CMOS
CVREF
O
Analog Comparator reference voltage output.
AN0
I
Analog Analog Input 0.
ULPWU
I
Analog Ultra Low-Power Wake-up input.
RA1/AN1
28
3
RA1
I/O
AN1
I
RA2/VREF-/AN2
1
ST/
Digital I/O.
CMOS
Analog Analog Input 1.
4
RA2
I/O
ST/
Digital I/O.
CMOS
VREF-
I
Analog A/D reference voltage (low) input.
AN2
I
Analog Analog Input 2.
RA3/VREF+/AN3
2
5
RA3
I/O
VREF+
AN3
RA5/AN4/C2INB/HLVDIN/
T1CKI/SS/CTMUI
4
ST/
Digital I/O.
CMOS
I
Analog A/D reference voltage (high) input.
I
Analog Analog Input 3.
7
RA5
I/O
AN4
I
Analog Analog Input 4.
C2INB
I
Analog Comparator 2 Input B.
HLVDIN
I
Analog High/Low-Voltage Detect input.
T1CKI
I
ST
SS
I
ST
CTMUI
Legend: CMOS
ST
I
P
ST/
Digital I/O.
CMOS
Timer1 clock input.
SPI slave select input.
CTMU pulse generator charger for the C2INB.
= CMOS compatible input or output
= Schmitt Trigger input with CMOS levels
= Input
= Power
DS30009977G-page 18
= I2C/SMBus input buffer
I2C™
Analog = Analog input
O
= Output
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-4:
PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
SSOP/ Pin Buffer
QFN SPDIP Type Type
/SOIC
Pin Name
Description
PORTB is a bidirectional I/O port.
RB0/AN10/C1INA/FLT0/
INT0
18
21
RB0
I/O
ST/
Digital I/O.
CMOS
AN10
I
Analog Analog Input 10.
C1INA
I
Analog Comparator 1 Input A.
FLT0
I
ST
Enhanced PWM Fault input for ECCP1.
INT0
I
ST
External Interrupt 0.
RB1/AN8/C1INB/P1B/
CTDIN/INT1
19
22
RB1
I/O
AN8
I
Analog Analog Input 8.
C1INB
I
Analog Comparator 1 Input B.
P1B
O
CMOS Enhanced PWM1 Output B.
CTDIN
I
ST
CTMU pulse delay input.
INT1
I
ST
External Interrupt 1.
RB2/CANTX/C1OUT/
P1C/CTED1/INT2
20
ST/
Digital I/O.
CMOS
23
RB2
I/O
ST/
Digital I/O.
CMOS
CANTX
O
CMOS CAN bus TX.
C1OUT
O
CMOS Comparator 1 output.
P1C
O
CMOS Enhanced PWM1 Output C.
CTED1
I
ST
CTMU Edge 1 input.
INT2
I
ST
External Interrupt 2.
RB3/CANRX/C2OUT/
P1D/CTED2/INT3
21
RB3
24
I/O
CANRX
I
ST/
Digital I/O.
CMOS
ST
CAN bus RX.
C2OUT
O
CMOS Comparator 2 output.
P1D
O
CMOS Enhanced PWM1 Output D.
CTED2
I
ST
CTMU Edge 2 input.
INT3
I
ST
External Interrupt 3.
Legend: CMOS
ST
I
P
= CMOS compatible input or output
= Schmitt Trigger input with CMOS levels
= Input
= Power
2010-2017 Microchip Technology Inc.
= I2C/SMBus input buffer
I2C™
Analog = Analog input
O
= Output
DS30009977G-page 19
PIC18F66K80 FAMILY
TABLE 1-4:
PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
SSOP/ Pin Buffer
QFN SPDIP Type Type
/SOIC
Pin Name
RB4/AN9/C2INA/ECCP1/
P1A/CTPLS/KBI0
22
Description
25
RB4
I/O
AN9
I
Analog Analog Input 9.
C2INA
I
Analog Comparator 2 Input A.
ECCP1
I/O
P1A
O
CTPLS
O
ST
CTMU pulse generator output.
I
ST
Interrupt-on-change pin.
KBI0
RB5/T0CKI/T3CKI/CCP5/
KBI1
23
ST/
Digital I/O.
CMOS
ST
Capture 1 input/Compare 1 output/PWM1 output.
CMOS Enhanced PWM1 Output A.
26
RB5
I/O
ST/
Digital I/O.
CMOS
T0CKI
I
ST
Timer0 external clock input.
T3CKI
I
ST
Timer3 external clock input.
CCP5
I/O
KBI1
I
RB6/PGC/TX2/CK2/KBI2
24
ST/
Capture 5 input/Compare 5 output/PWM5 output.
CMOS
ST
Interrupt-on-change pin.
27
RB6
I/O
PGC
I
TX2
O
CK2
I/O
ST
EUSART synchronous clock. (See related RX2/DT2.)
I
ST
Interrupt-on-change pin.
KBI2
RB7/PGD/T3G/RX2/DT2/
KBI3
25
ST/
Digital I/O.
CMOS
ST
In-Circuit Debugger and ICSP™ programming clock input
pin.
CMOS EUSART asynchronous transmit.
28
RB7
I/O
PGD
I/O
ST/
Digital I/O.
CMOS
ST
In-Circuit Debugger and ICSP programming data pin.
T3G
I
ST
Timer3 external clock gate input.
RX2
I
ST
EUSART asynchronous receive.
DT2
I/O
ST
EUSART synchronous data. (See related TX2/CK2.)
I
ST
Interrupt-on-change pin.
KBI3
Legend: CMOS
ST
I
P
= CMOS compatible input or output
= Schmitt Trigger input with CMOS levels
= Input
= Power
DS30009977G-page 20
= I2C/SMBus input buffer
I2C™
Analog = Analog input
O
= Output
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-4:
PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
SSOP/ Pin Buffer
QFN SPDIP Type Type
/SOIC
Pin Name
Description
PORTC is a bidirectional I/O port.
RC0/SOSCO/SCLKI
8
11
RC0
I/O
SOSCO
SCLKI
RC1/SOSCI
9
I
ST
Timer1 oscillator output.
I
ST
Digital SOSC input.
12
RC1
I/O
SOSCI
I
RC2/T1G/CCP2
10
ST/
Digital I/O.
CMOS
ST/
Digital I/O.
CMOS
CMOS SOSC oscillator input.
13
RC2
I/O
T1G
I
ST
Timer1 external clock gate input.
I/O
ST
Capture 2 input/Compare 2 output/PWM2 output.
CCP2
RC3/REFO/SCL/SCK
11
ST/
Digital I/O.
CMOS
14
RC3
I/O
ST/
Digital I/O.
CMOS
REFO
O
—
Reference clock out.
SCL
I/O
I2C
Synchronous serial clock input/output for I2C mode.
I/O
ST
Synchronous serial clock input/output for SPI mode.
SCK
RC4/SDA/SDI
12
15
RC4
I/O
SDA
I/O
I2C
I2C data input/output.
SDI
I
ST
SPI data in.
RC5/SDO
13
ST/
Digital I/O.
CMOS
16
RC5
I/O
ST/
Digital I/O.
CMOS
O
CMOS SPI data out.
RC6
I/O
ST/
Digital I/O.
CMOS
CANTX
O
CMOS CAN bus TX.
TX1
O
CMOS EUSART asynchronous transmit.
CK1
I/O
CCP3
I/O
SDO
RC6/CANTX/TX1/CK1/
CCP3
Legend: CMOS
ST
I
P
14
17
ST
EUSART synchronous clock. (See related RX1/DT1.)
ST/
Capture 3 input/Compare 3 output/PWM3 output.
CMOS
= CMOS compatible input or output
= Schmitt Trigger input with CMOS levels
= Input
= Power
2010-2017 Microchip Technology Inc.
= I2C/SMBus input buffer
I2C™
Analog = Analog input
O
= Output
DS30009977G-page 21
PIC18F66K80 FAMILY
TABLE 1-4:
PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED)
Pin Number
SSOP/ Pin Buffer
QFN SPDIP Type Type
/SOIC
Pin Name
RC7/CANRX/RX1/DT1/
CCP4
15
Description
18
RC7
I/O
CANRX
I
ST/
Digital I/O.
CMOS
ST
CAN bus RX.
RX1
I
ST
EUSART asynchronous receive.
DT1
I/O
ST
EUSART synchronous data. (See related TX2/CK2.)
CCP4
I/O
VSS
5
8
P
VSS
Ground reference for logic and I/O pins.
VSS
16
19
3
6
VSS
Ground reference for logic and I/O pins.
VDDCORE/VCAP
P
VDDCORE
External filter capacitor connection.
VCAP
External filter capacitor connection
VDD
17
VDD
Legend: CMOS
ST
I
P
ST
Capture 4 input/Compare 4 output/PWM4 output.
CMOS
20
P
Positive supply for logic and I/O pins.
= CMOS compatible input or output
= Schmitt Trigger input with CMOS levels
= Input
= Power
DS30009977G-page 22
= I2C/SMBus input buffer
I2C™
Analog = Analog input
O
= Output
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-5:
PIC18F4XK80 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
PDIP
MCLR/RE3
Pin Buffer
QFN/ Type Type
TQFP
1
Description
18
MCLR
I
ST
Master Clear (input) or programming voltage (input). This
pin is an active-low Reset to the device.
RE3
I
ST
General purpose, input only pin.
ST
Oscillator crystal input.
OSC1/CLKIN/RA7
13
30
OSC1
I
CLKIN
I
RA7
OSC2/CLKOUT/RA6
I/O
14
CMOS External clock source input. Always associated with pin
function, OSC1. (See related OSC1/CLKI, OSC2/CLKO
pins.)
ST/
General purpose I/O pin.
CMOS
31
OSC2
O
—
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
CLKOUT
O
—
In certain oscillator modes, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
RA6
I/O
ST/
General purpose I/O pin.
CMOS
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
2010-2017 Microchip Technology Inc.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
DS30009977G-page 23
PIC18F66K80 FAMILY
TABLE 1-5:
PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PDIP
Pin Buffer
QFN/ Type Type
TQFP
Description
PORTA is a bidirectional I/O port.
RA0/CVREF/AN0/ULPWU
2
19
RA0
I/O
ST/
General purpose I/O pin.
CMOS
CVREF
O
Analog Comparator reference voltage output.
AN0
I
Analog Analog Input 0.
ULPWU
I
Analog Ultra Low-Power Wake-up input.
RA1/AN1/C1INC
3
20
RA1
I/O
AN1
I
Analog Analog Input 1.
C1INC
I
Analog Comparator 1 Input C.
RA2/VREF-/AN2/C2INC
4
ST/
Digital I/O.
CMOS
21
RA2
I/O
ST/
Digital I/O.
CMOS
VREF-
I
Analog A/D reference voltage (low) input.
AN2
I
Analog Analog Input 2.
C2INC
I
Analog Comparator 2 Input C.
RA3/VREF+/AN3
5
22
RA3
I/O
ST/
Digital I/O.
CMOS
VREF+
I
Analog A/D reference voltage (high) input.
AN3
I
Analog Analog Input 3.
RA5/AN4/HLVDIN/T1CKI/
SS
7
24
RA5
I/O
ST/
Digital I/O.
CMOS
AN4
I
Analog Analog Input 4.
HLVDIN
I
Analog High/Low-Voltage Detect input.
T1CKI
I
ST
Timer1 clock input.
SS
I
ST
SPI slave select input.
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
DS30009977G-page 24
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-5:
PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PDIP
Pin Buffer
QFN/ Type Type
TQFP
Description
PORTB is a bidirectional I/O port.
RB0/AN10/FLT0/INT0
33
8
RB0
I/O
AN10
I
ST/
Digital I/O.
CMOS
Analog Analog Input 10.
FLT0
I
ST
Enhanced PWM Fault input for ECCP1.
INT0
I
ST
External Interrupt 0.
RB1/AN8/CTDIN/INT1
34
9
RB1
I/O
AN8
I
CTDIN
I
ST
CTMU pulse delay input.
I
ST
External Interrupt 1.
INT1
RB2/CANTX/CTED1/
INT2
35
ST/
Digital I/O.
CMOS
Analog Analog Input 8.
10
RB2
I/O
ST/
Digital I/O.
CMOS
CANTX
O
CMOS CAN bus TX.
CTED1
I
ST
CTMU Edge 1 input.
INT2
I
ST
External Interrupt 2.
RB3/CANRX/CTED2/
INT3
36
11
RB3
I/O
ST/
Digital I/O.
CMOS
CANRX
I
ST
CAN bus RX.
CTED2
I
ST
CTMU Edge 2 input.
INT3
I
ST
External Interrupt 3.
RB4/AN9/CTPLS/KBI0
37
14
RB4
I/O
ST/
Digital I/O.
CMOS
AN9
I
CTPLS
O
ST
CTMU pulse generator output.
I
ST
Interrupt-on-change pin.
KBI0
RB5/T0CKI/T3CKI/CCP5/
KBI1
38
RB5
Analog Analog Input 9.
15
I/O
ST/
Digital I/O.
CMOS
T0CKI
I
ST
Timer0 external clock input.
T3CKI
I
ST
Timer3 external clock input.
CCP5
I/O
ST
Capture 5 input/Compare 5 output/PWM5 output.
KBI1
I
ST
Interrupt-on-change pin.
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
2010-2017 Microchip Technology Inc.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
DS30009977G-page 25
PIC18F66K80 FAMILY
TABLE 1-5:
PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PDIP
RB6/PGC/KBI2
39
Pin Buffer
QFN/ Type Type
TQFP
Description
16
RB6
I/O
PGC
I
ST
In-Circuit Debugger and ICSP™ programming clock input
pin.
KBI2
I
ST
Interrupt-on-change pin.
RB7/PGD/T3G/KBI3
40
ST/
Digital I/O.
CMOS
17
RB7
I/O
PGD
I/O
ST/
Digital I/O.
CMOS
ST
In-Circuit Debugger and ICSP™ programming data pin.
T3G
I
ST
Timer3 external clock gate input.
KBI3
I
ST
Interrupt-on-change pin.
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
DS30009977G-page 26
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-5:
PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PDIP
Pin Buffer
QFN/ Type Type
TQFP
Description
PORTC is a bidirectional I/O port.
RC0/SOSCO/SCLKI
15
32
RC0
I/O
SOSCO
SCLKI
RC1/SOSCI
16
I
ST
SOSC oscillator output.
I
ST
Digital SOSC input.
35
RC1
I/O
SOSCI
RC2/T1G/CCP2
I
17
ST/
Digital I/O.
CMOS
ST/
Digital I/O.
CMOS
CMOS SOSC oscillator input.
36
RC2
I/O
T1G
I
CCP2
ST/
Digital I/O.
CMOS
ST
Timer1 external clock gate input.
I/O
ST/
Capture 2 input/Compare 2 output/PWM2 output.
CMOS
I/O
ST/
Digital I/O.
CMOS
REFO
O
CMOS Reference clock out.
SCL
I/O
I2C
Synchronous serial clock input/output for I2C mode.
I/O
ST
Synchronous serial clock input/output for SPI mode.
RC3/REFO/SCL/SCK
18
37
RC3
SCK
RC4/SDA/SDI
23
42
RC4
I/O
SDA
I/O
I2C
I2C data input/output.
SDI
I
ST
SPI data in.
RC5/SDO
24
ST/
Digital I/O.
CMOS
43
RC5
I/O
ST/
Digital I/O.
CMOS
O
CMOS SPI data out.
RC6
I/O
ST/
Digital I/O.
CMOS
CANTX
O
CMOS CAN bus TX.
TX1
O
CMOS EUSART synchronous transmit.
SDO
RC6/CANTX/TX1/CK1/
CCP3
25
44
CK1
I/O
ST
EUSART synchronous clock. (See related RX2/DT2.)
CCP3
I/O
ST
Capture 3 input/Compare 3 output/PWM3 output.
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
2010-2017 Microchip Technology Inc.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
DS30009977G-page 27
PIC18F66K80 FAMILY
TABLE 1-5:
PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PDIP
RC7/CANRX/RX1/DT1/
CCP4
RC7
26
Pin Buffer
QFN/ Type Type
TQFP
Description
1
I/O
ST/
Digital I/O.
CMOS
CANRX
I
ST
CAN bus RX.
RX1
I
ST
EUSART asynchronous receive.
DT1
I/O
ST
EUSART synchronous data. (See related TX2/CK2.)
CCP4
I/O
ST
Capture 4 input/Compare 4 output/PWM4 output.
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
DS30009977G-page 28
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-5:
PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PDIP
Pin Buffer
QFN/ Type Type
TQFP
Description
PORTD is a bidirectional I/O port.
RD0/C1INA/PSP0
19
38
RD0
I/O
ST/
Digital I/O.
CMOS
C1INA
I
PSP0
I/O
ST/
Parallel Slave Port data.
CMOS
I/O
ST/
Digital I/O.
CMOS
RD1/C1INB/PSP1
20
Analog Comparator 1 Input A.
39
RD1
C1INB
I
PSP1
I/O
ST/
Parallel Slave Port data.
CMOS
I/O
ST/
Digital I/O.
CMOS
RD2/C2INA/PSP2
21
Analog Comparator 1 Input B.
40
RD2
C2INA
I
PSP2
I/O
ST/
Parallel Slave Port data.
CMOS
I/O
ST/
Digital I/O.
CMOS
RD3/C2INB/CTMUI/
PSP3
22
Analog Comparator 2 Input A.
41
RD3
C2INB
I
Analog Comparator 2 Input B.
CTMUI
CTMU pulse generator charger for the C2INB.
PSP3
I/O
ST/
Parallel Slave Port data.
CMOS
RD4
I/O
ST/
Digital I/O.
CMOS
ECCP1
I/O
P1A
O
CMOS Enhanced PWM1 Output A.
PSP4
I/O
ST/
Parallel Slave Port data.
CMOS
RD5
I/O
ST/
Digital I/O.
CMOS
P1B
O
CMOS Enhanced PWM1 Output B.
PSP5
I/O
ST/
Parallel Slave Port data.
CMOS
RD4/ECCP1/P1A/PSP4
RD5/P1B/PSP5
27
28
2
ST
Capture 1 input/Compare 1 output/PWM1 output.
3
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
2010-2017 Microchip Technology Inc.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
DS30009977G-page 29
PIC18F66K80 FAMILY
TABLE 1-5:
PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PDIP
RD6/TX2/CK2/P1C/PSP6
29
Pin Buffer
QFN/ Type Type
TQFP
Description
4
RD6
I/O
ST/
Digital I/O.
CMOS
TX2
I
ST
EUSART asynchronous transmit.
CK2
I/O
ST
EUSART synchronous clock. (See related RX2/DT2.)
P1C
O
CMOS Enhanced PWM1 Output C.
PSP6
I/O
ST/
Parallel Slave Port data.
CMOS
RD7
I/O
ST/
Digital I/O.
CMOS
RX2
I
DT2
I/O
P1D
O
CMOS Enhanced PWM1 Output D.
PSP7
I/O
ST/
Parallel Slave Port data.
CMOS
RE0
I/O
ST/
Digital I/O.
CMOS
AN5
I
RD
I
RD7/RX2/DT2/P1D/PSP7
RE0/AN5/RD
30
8
RE1/AN6/C1OUT/WR
9
5
ST
EUSART asynchronous receive.
ST
EUSART synchronous data. (See related TX2/CK2.)
25
Analog Analog Input 5.
ST
Parallel Slave Port read strobe.
26
RE1
I/O
AN6
I
Analog Analog Input 6.
C1OUT
O
CMOS Comparator 1 output.
WR
I
RE2/AN7/C2OUT/CS
10
RE2
ST/
Digital I/O.
CMOS
ST
Parallel Slave Port write strobe.
27
I/O
ST/
Digital I/O.
CMOS
AN7
I
Analog Analog Input 7.
C2OUT
O
CMOS Comparator 2 output.
CS
I
ST
Parallel Slave Port chip select.
See the MCLR/RE3 pin.
RE3
2C™ = I2C/SMBus
Legend: I
ST
I
P
input buffer
= Schmitt Trigger input with CMOS levels
= Input
= Power
DS30009977G-page 30
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-5:
PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PDIP
VSS
Pin Buffer
QFN/ Type Type
TQFP
12
29
31
6
6
23
P
VSS
VSS
Ground reference for logic and I/O pins.
VSS
VDDCORE/VCAP
Description
Ground reference for logic and I/O pins.
P
VDDCORE
External filter capacitor connection
VCAP
External filter capacitor connection
VDD
11
28
P
VDD
VDD
Positive supply for logic and I/O pins.
32
VDD
7
P
Positive supply for logic and I/O pins.
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
2010-2017 Microchip Technology Inc.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
DS30009977G-page 31
PIC18F66K80 FAMILY
TABLE 1-6:
PIC18F6XK80 PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
MCLR
I
ST
Master Clear (input) or programming voltage (input). This pin is an
active-low Reset to the device.
RE3
I
ST
General purpose, input only pin.
OSC1
I
ST
Oscillator crystal input.
CLKIN
I
Pin Name
MCLR/RE3
OSC1/CLKIN/RA7
Pin
Num
28
46
RA7
OSC2/CLKOUT/RA6
Description
I/O
CMOS External clock source input. Always associated with pin function,
OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)
ST/ General purpose I/O pin.
CMOS
47
OSC2
O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode.
CLKOUT
O
—
In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4
the frequency of OSC1 and denotes the instruction cycle rate.
RA6
I/O
ST/ General purpose I/O pin.
CMOS
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
DS30009977G-page 32
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-6:
PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Num
Pin
Type
Buffer
Type
Description
PORTA is a bidirectional I/O port.
RA0/CVREF/AN0/
ULPWU
29
RA0
I/O
ST/ General purpose I/O pin.
CMOS
CVREF
O
Analog Comparator reference voltage output.
AN0
I
Analog Analog Input 0.
ULPWU
I
Analog Ultra Low-Power Wake-up input.
RA1/AN1/C1INC
30
RA1
I/O
AN1
I
Analog Analog Input 1.
C1INC
I
Analog Comparator 1 Input C.
RA2/VREF-/AN2/C2INC
ST/ Digital I/O.
CMOS
31
RA2
I/O
ST/ Digital I/O.
CMOS
VREF-
I
Analog A/D reference voltage (low) input.
AN2
I
Analog Analog Input 2.
I
Analog Comparator 2 Input C.
C2INC
RA3/VREF+/AN3
32
RA3
I/O
ST/ Digital I/O.
CMOS
VREF+
I
Analog A/D reference voltage (high) input.
AN3
I
Analog Analog Input 3.
RA5/AN4/HLVDIN/
T1CKI/SS
34
RA5
I/O
ST/ Digital I/O.
CMOS
AN4
I
Analog Analog Input 4.
HLVDIN
I
Analog High/Low-Voltage Detect input.
T1CKI
I
ST
Timer1 clock input.
SS
I
ST
SPI slave select input.
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
2010-2017 Microchip Technology Inc.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
DS30009977G-page 33
PIC18F66K80 FAMILY
TABLE 1-6:
PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Num
Pin
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port.
RB0/AN10/FLT0/INT0
13
RB0
I/O
AN10
I
FLT0
I
ST
Enhanced PWM Fault input for ECCP1.
I
ST
External Interrupt 0.
INT0
RB1/AN8/CTDIN/INT1
ST/ Digital I/O.
CMOS
Analog Analog Input 10.
14
RB1
I/O
ST/ Digital I/O.
CMOS
AN8
I
CTDIN
I
ST
CTMU pulse delay input.
I
ST
External Interrupt 1.
INT1
RB2/CANTX/CTED1/
INT2
Analog Analog Input 8.
15
RB2
I/O
ST/ Digital I/O.
CMOS
CANTX
O
CMOS CAN bus TX.
CTED1
I
ST
CTMU Edge 1 input.
INT2
I
ST
External Interrupt 2.
RB3/CANRX/CTED2/
INT3
16
RB3
I/O
ST/ Digital I/O.
CMOS
CANRX
I
ST
CAN bus RX.
CTED2
I
ST
CTMU Edge 2 input.
INT3
I
ST
External Interrupt 3.
RB4/AN9/CTPLS/KBI0
20
RB4
I/O
AN9
I
CTPLS
O
ST
CTMU pulse generator output.
KBI0
I
ST
Interrupt-on-change pin.
RB5/T0CKI/T3CKI/CCP5/
KBI1
RB5
T0CKI
ST/ Digital I/O.
CMOS
Analog Analog Input 9.
21
I/O
I
T3CKI
I
CCP5
I/O
KBI1
I
ST/ Digital I/O.
CMOS
ST
Timer0 external clock input.
ST
Timer3 external clock input.
ST/ Capture 5 input/Compare 5 output/PWM5 output.
CMOS
ST
Interrupt-on-change pin.
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
DS30009977G-page 34
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-6:
PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RB6/PGC/KBI2
Pin
Num
Pin
Type
Buffer
Type
Description
22
RB6
I/O
PGC
I
ST
In-Circuit Debugger and ICSP™ programming clock input pin.
I
ST
Interrupt-on-change pin.
KBI2
RB7/PGD/T3G/KBI3
ST/ Digital I/O.
CMOS
23
RB7
I/O
PGD
I/O
ST/ Digital I/O.
CMOS
ST
In-Circuit Debugger and ICSP™ programming data pin.
T3G
I
ST
Timer3 external clock gate input.
KBI3
I
ST
Interrupt-on-change pin.
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
2010-2017 Microchip Technology Inc.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
DS30009977G-page 35
PIC18F66K80 FAMILY
TABLE 1-6:
PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Num
Pin
Type
Buffer
Type
Description
PORTC is a bidirectional I/O port.
RC0/SOSCO/SCLKI
48
RC0
I/O
ST/ Digital I/O.
CMOS
SOSCO
I
ST
Timer1 oscillator output.
SCLKI
I
ST
Digital SOSC input.
RC1/SOSCI
49
RC1
I/O
SOSCI
RC2/T1G/CCP2
I
CMOS SOSC oscillator input.
50
RC2
I/O
T1G
CCP2
RC3/REFO/SCL/SCK
ST/ Digital I/O.
CMOS
ST/ Digital I/O.
CMOS
I
ST
Timer1 external clock gate input.
I/O
ST
Capture 2 input/Compare 2 output/PWM2 output.
51
RC3
I/O
ST/ Digital I/O.
CMOS
REFO
O
CMOS Reference clock out.
SCL
I/O
I2 C
Synchronous serial clock input/output for I2C mode.
SCK
I/O
ST
Synchronous serial clock input/output for SPI mode.
RC4/SDA/SDI
62
RC4
I/O
SDA
I/O
I2 C
I2C data input/output.
SDI
I
ST
SPI data in.
RC5/SDO
ST/ Digital I/O.
CMOS
63
RC5
I/O
ST/ Digital I/O.
CMOS
SDO
O
CMOS SPI data out.
RC6
I/O
ST/ Digital I/O.
CMOS
CCP3
I/O
ST/ Capture 3 input/Compare 3 output/PWM3 output.
CMOS
RC7
I/O
ST/ Digital I/O.
CMOS
CCP4
I/O
ST/ Capture 4 input/Compare 4 output/PWM4 output.
CMOS
RC6/CCP3
RC7/CCP4
64
1
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
DS30009977G-page 36
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-6:
PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Num
Pin
Type
Buffer
Type
Description
PORTD is a bidirectional I/O port.
RD0/C1INA/PSP0
54
RD0
I/O
ST/ Digital I/O.
CMOS
C1INA
I
PSP0
I/O
ST/ Parallel Slave Port data.
CMOS
I/O
ST/ Digital I/O.
CMOS
RD1/C1INB/PSP1
Analog Comparator 1 Input A.
55
RD1
C1INB
I
PSP1
I/O
ST/ Parallel Slave Port data.
CMOS
I/O
ST/ Digital I/O.
CMOS
RD2/C2INA/PSP2
Analog Comparator 1 Input B.
58
RD2
C2INA
I
PSP2
I/O
ST/ Parallel Slave Port data.
CMOS
I/O
ST/ Digital I/O.
CMOS
RD3/C2INB/CTMUI/
PSP3
Analog Comparator 2 Input A.
59
RD3
C2INB
I
Analog Comparator 2 Input B.
CTMUI
O
CMOS CTMU pulse generator charger for the C2INB.
PSP3
I/O
ST/ Parallel Slave Port data.
CMOS
RD4
I/O
ST/ Digital I/O.
CMOS
ECCP1
I/O
P1A
O
CMOS Enhanced PWM1 Output A.
PSP4
I/O
ST/ Parallel Slave Port data.
CMOS
I/O
ST/ Digital I/O.
CMOS
P1B
O
CMOS Enhanced PWM1 Output B.
PSP5
I/O
ST/ Parallel Slave Port data.
CMOS
RD4/ECCP1/P1A/PSP4
RD5/P1B/PSP5
2
ST
Capture 1 input/Compare 1 output/PWM1 output.
3
RD5
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
2010-2017 Microchip Technology Inc.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
DS30009977G-page 37
PIC18F66K80 FAMILY
TABLE 1-6:
PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
RD6/P1C/PSP6
Pin
Num
Pin
Type
Buffer
Type
Description
4
RD6
I/O
ST/ Digital I/O.
CMOS
P1C
O
CMOS Enhanced PWM1 Output C.
PSP6
I/O
ST/ Parallel Slave Port data.
CMOS
I/O
ST/ Digital I/O.
CMOS
P1D
O
CMOS Enhanced PWM1 Output D.
PSP7
I/O
ST/ Parallel Slave Port data.
CMOS
RD7/P1D/PSP7
RD7
5
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
DS30009977G-page 38
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-6:
PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Num
Pin Name
Pin
Type
Buffer
Type
Description
PORTE is a bidirectional I/O port.
37
RE0/AN5/RD
RE0
I/O
AN5
I
RD
I
RE1/AN6/C1OUT/WR
ST/ Digital I/O.
CMOS
Analog Analog Input 5.
ST
Parallel Slave Port read strobe.
38
RE1
I/O
AN6
I
Analog Analog Input 6.
C1OUT
O
CMOS Comparator 1 output.
WR
I
RE2/AN7/C2OUT/CS
ST/ Digital I/O.
CMOS
ST
Parallel Slave Port write strobe.
39
RE2
I/O
ST/ Digital I/O.
CMOS
AN7
I
Analog Analog Input 7.
C2OUT
O
CMOS Comparator 2 output.
CS
I
ST
Parallel Slave Port chip select.
See the MCLR/RE3 pin.
RE3
RE4/CANRX
27
RE4
I/O
CANRX
I
RE5/CANTX
ST/ Digital I/O.
CMOS
ST
CAN bus RX.
24
RE5
I/O
ST/ Digital I/O.
CMOS
CANTX
O
CMOS CAN bus TX.
I/O
ST/ Digital I/O.
CMOS
RE6/RX2/DT2
60
RE6
RX2
I
ST
EUSART asynchronous receive.
DT2
I/O
ST
EUSART synchronous data. (See related TX2/CK2.)
RE7/TX2/CK2
61
RE7
I/O
ST/ Digital I/O.
CMOS
TX2
O
CMOS EUSART asynchronous transmit.
CK2
I/O
2C™ =
Legend: I
ST
I
P
I2C/SMBus
ST
EUSART synchronous clock. (See related RX2/DT2.)
input buffer
= Schmitt Trigger input with CMOS levels
= Input
= Power
2010-2017 Microchip Technology Inc.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
DS30009977G-page 39
PIC18F66K80 FAMILY
TABLE 1-6:
PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Num
Pin
Type
Buffer
Type
Description
PORTF is a bidirectional I/O port.
RF0/MDMIN
17
RF0
I/O
MDMIN
RF1
I
MDCIN1
Modulator Carrier Input 1.
I/O
ST/ Digital I/O.
CMOS
I/O
ST/ Digital I/O.
CMOS
I
ST
Modulator Carrier Input 2.
I/O
ST/ Digital I/O.
CMOS
I/O
ST/ Digital I/O.
CMOS
O
CMOS Modulator output.
I/O
ST/ Digital I/O.
CMOS
52
RF6
MDOUT
RF7
ST
45
RF5
RF7
ST/ Digital I/O.
CMOS
44
MDCIN2
RF6/MDOUT
I/O
I
RF4
RF5
ST/ Digital I/O.
CMOS
36
RF3
RF4/MDCIN2
I/O
35
RF2
RF3
CMOS Modulator source input.
19
RF1
RF2/MDCIN1
ST/ Digital I/O.
CMOS
53
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
DS30009977G-page 40
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 1-6:
PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Num
Pin
Type
Buffer
Type
Description
PORTG is a bidirectional I/O port.
RG0/RX1/DT1
6
RG0
I/O
ST/ Digital I/O.
CMOS
RX1
I
ST
EUSART asynchronous receive.
DT1
I/O
ST
EUSART synchronous data. (See related TX2/CK2.)
RG1/CANTX2
7
RG1
CANTX2
RG2/T3CKI
ST/ Digital I/O.
CMOS
O
CMOS CAN bus complimentary transmit output or CAN bus time clock.
I/O
ST/ Digital I/O.
CMOS
11
RG2
T3CKI
RG3/TX1/CK1
I/O
I
ST
Timer3 clock input.
12
RG3
I/O
ST/ Digital I/O.
CMOS
TX1
O
CMOS EUSART asynchronous transmit.
CK1
RG4/T0CKI
I/O
ST
EUSART synchronous clock. (See related RX2/DT2.)
18
RG4
T0CKI
I/O
I
ST/ Digital I/O.
CMOS
ST
Timer0 external clock input.
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
2010-2017 Microchip Technology Inc.
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
DS30009977G-page 41
PIC18F66K80 FAMILY
TABLE 1-6:
PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
VSS
Pin
Num
Pin
Type
Buffer
Type
8
P
26
P
VSS
VSS
Ground reference for logic and I/O pins.
VSS
AVSS
Ground reference for logic and I/O pins.
42
P
AVSS
VSS
Ground reference for analog modules.
43
P
56
P
VSS
VSS
Ground reference for logic and I/O pins.
VSS
AVDD
Ground reference for logic and I/O pins.
9
P
AVDD
VDD
Positive supply for analog modules.
10
P
25
P
VDD
VDD
Positive supply for logic and I/O pins.
VDD
VDDCORE/VCAP
Positive supply for logic and I/O pins.
33
P
VDDCORE
External filter capacitor connection.
VCAP
AVDD
External filter capacitor connection.
40
P
AVDD
VDD
Positive supply for analog modules.
41
P
57
P
VDD
VDD
VDD
Description
Positive supply for logic and I/O pins.
Positive supply for logic and I/O pins.
Legend: I2C™ = I2C/SMBus input buffer
ST = Schmitt Trigger input with CMOS levels
I
= Input
P
= Power
DS30009977G-page 42
CMOS = CMOS compatible input or output
Analog = Analog input
O
= Output
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
2.0
GUIDELINES FOR GETTING
STARTED WITH PIC18FXXKXX
MICROCONTROLLERS
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTIONS
C2(2)
• All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”)
• All AVDD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
• ENVREG (if implemented) and VCAP/VDDCORE pins
(see Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)”)
VCAP/VDDCORE
C1
VSS
VDD
VDD
VSS
C3(2)
C6(2)
C4(2)
C5(2)
Key (all values are recommendations):
• PGC/PGD pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
R2: 100Ω to 470Ω
Note:
C7(2)
PIC18FXXKXX
C1 through C6: 0.1 F, 20V ceramic
• VREF+/VREF- pins are used when external voltage
reference for analog modules is implemented
(1) (1)
ENVREG
MCLR
These pins must also be connected if they are being
used in the end application:
Additionally, the following pins may be required:
VSS
VDD
R2
VSS
The following pins must always be connected:
R1
VDD
Getting started with the PIC18F66K80 family family of
8-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.
VDD
AVSS
Basic Connection Requirements
AVDD
2.1
R1: 10 kΩ
Note 1:
2:
See Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)” for
explanation of ENVREG pin connections.
The example shown is for a PIC18F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
The minimum mandatory connections are shown in
Figure 2-1.
2010-2017 Microchip Technology Inc.
DS30009977G-page 43
PIC18F66K80 FAMILY
2.2
2.2.1
Power Supply Pins
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2
TANK CAPACITORS
On boards with power traces running longer than
six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
DS30009977G-page 44
2.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: Device Reset, and Device Programming
and Debugging. If programming and debugging are
not required in the end application, a direct
connection to VDD may be all that is required. The
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R1
R2
JP
MCLR
PIC18FXXKXX
C1
Note 1:
R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2:
R2 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
2.4
Voltage Regulator Pins (ENVREG
and VCAP/VDDCORE)
The on-chip voltage regulator enable pin, ENVREG,
must always be connected directly to either a supply
voltage or to ground. Tying ENVREG to VDD enables
the regulator, while tying it to ground disables the
regulator. Refer to Section 28.3 “On-Chip Voltage
Regulator” for details on connecting and using the
on-chip regulator.
When the regulator is enabled, a low-ESR (< 5Ω)
capacitor is required on the VCAP/VDDCORE pin to
stabilize the voltage regulator output voltage. The
VCAP/VDDCORE pin must not be connected to VDD and
must use a capacitor of 10 µF connected to ground. The
type can be ceramic or tantalum. Suitable examples of
capacitors are shown in Table 2-1. Capacitors with
equivalent specifications can be used.
Some PIC18FXXKXX families, or some devices within
a family, do not provide the option of enabling or
disabling the on-chip voltage regulator:
• Some devices (with the name, PIC18LFXXKXX)
permanently disable the voltage regulator.
These devices do not have the ENVREG pin and
require a 0.1 F capacitor on the VCAP/VDDCORE
pin. The VDD level of these devices must comply
with the “voltage regulator disabled” specification
for Parameter D001, in Section 31.0 “Electrical
Characteristics”.
• Some devices permanently enable the voltage
regulator.
These devices also do not have the ENVREG pin.
The 10 F capacitor is still required on the
VCAP/VDDCORE pin.
FIGURE 2-3:
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
Designers may use Figure 2-3 to evaluate ESR
equivalence of candidate devices.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 31.0 “Electrical
Characteristics” for additional information.
10
1
ESR ()
When the regulator is disabled, the VCAP/VDDCORE pin
must be tied to a voltage supply at the VDDCORE level.
Refer to Section 31.0 “Electrical Characteristics” for
information on VDD and VDDCORE.
0.1
0.01
0.001
0.01
Note:
0.1
1
10
100
Frequency (MHz)
1000 10,000
Typical data measurement at 25°C, 0V DC bias.
.
TABLE 2-1:
SUITABLE CAPACITOR EQUIVALENTS
Make
Part #
Nominal
Capacitance
Base Tolerance
Rated Voltage
Temp. Range
TDK
C3216X7R1C106K
10 µF
±10%
16V
-55 to 125ºC
TDK
C3216X5R1C106K
10 µF
±10%
16V
-55 to 85ºC
Panasonic
ECJ-3YX1C106K
10 µF
±10%
16V
-55 to 125ºC
Panasonic
ECJ-4YB1C106K
10 µF
±10%
16V
-55 to 85ºC
Murata
GRM32DR71C106KA01L
10 µF
±10%
16V
-55 to 125ºC
Murata
GRM31CR61C106KC31L
10 µF
±10%
16V
-55 to 85ºC
2010-2017 Microchip Technology Inc.
DS30009977G-page 45
PIC18F66K80 FAMILY
CONSIDERATIONS FOR CERAMIC
CAPACITORS
In recent years, large value, low-voltage, surface-mount
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
physical size and other properties make ceramic
capacitors very attractive in many types of applications.
Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller. However,
some care is needed in selecting the capacitor to
ensure that it maintains sufficient capacitance over the
intended operating range of the application.
Typical low-cost, 10 F ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial tolerance specifications for these types of capacitors are
often specified as ±10% to ±20% (X5R and X7R), or
-20%/+80% (Y5V). However, the effective capacitance
that these capacitors provide in an application circuit will
also vary based on additional factors, such as the
applied DC bias voltage and the temperature. The total
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification.
The X5R and X7R capacitors typically exhibit satisfactory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer's data
sheets for exact specifications). However, Y5V capacitors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme
temperature tolerance, a 10 F nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum internal voltage regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
internal regulator if the application must operate over a
wide temperature range.
In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very significant, but is often overlooked or is not always
documented.
A typical DC bias voltage vs. capacitance graph for
X7R type and Y5V type capacitors is shown in
Figure 2-4.
FIGURE 2-4:
Capacitance Change (%)
2.4.1
DC BIAS VOLTAGE vs.
CAPACITANCE
CHARACTERISTICS
10
0
-10
16V Capacitor
-20
-30
-40
10V Capacitor
-50
-60
-70
6.3V Capacitor
-80
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DC Bias Voltage (VDC)
When selecting a ceramic capacitor to be used with the
internal voltage regulator, it is suggested to select a
high-voltage rating, so that the operating voltage is a
small percentage of the maximum rated capacitor voltage. For example, choose a ceramic capacitor rated at
16V for the 2.5V core voltage. Suggested capacitors
are shown in Table 2-1.
2.5
ICSP Pins
The PGC and PGD pins are used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communications to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin input voltage high
(VIH) and input low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGCx/PGDx pins), programmed
into the device, matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 30.0 “Development Support”.
DS30009977G-page 46
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
2.6
External Oscillator Pins
FIGURE 2-5:
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency
secondary
oscillator
(refer
to
Section 3.0 “Oscillator Configurations” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Single-Sided and In-Line Layouts:
Copper Pour
(tied to ground)
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design”
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
2.7
Unused I/Os
Primary Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
OSC1
C1
`
OSC2
GND
C2
`
T1OSO
T1OS I
Timer1 Oscillator
Crystal
Layout suggestions are shown in Figure 2-4. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
In planning the application’s routing and I/O assignments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times,
and other similar noise).
SUGGESTED
PLACEMENT OF THE
OSCILLATOR CIRCUIT
`
T1 Oscillator: C1
T1 Oscillator: C2
Fine-Pitch (Dual-Sided) Layouts:
Top Layer Copper Pour
(tied to ground)
Bottom Layer
Copper Pour
(tied to ground)
OSCO
C2
Oscillator
Crystal
GND
C1
OSCI
DEVICE PINS
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
2010-2017 Microchip Technology Inc.
DS30009977G-page 47
PIC18F66K80 FAMILY
3.0
OSCILLATOR
CONFIGURATIONS
3.1
Oscillator Types
The PIC18F66K80 family of devices can be operated in
the following oscillator modes:
• EC
• ECIO
External Clock, RA6 Available
External Clock, Clock Out RA6 (FOSC/4
on RA6)
• HS
High-Speed Crystal/Resonator
• XT
Crystal/Resonator
• LP
Low-Power Crystal
• RC
External Resistor/Capacitor, RA6
Available
• RCIO
External Resistor/Capacitor, Clock Out
RA6 (FOSC/4 on RA6)
• INTIO2 Internal Oscillator with I/O on RA6 and
RA7
• INTIO1 Internal Oscillator with FOSC/4 Output on
RA6 and I/O on RA7
There is also an option for running the 4xPLL on any of
the clock sources in the input frequency range of 4 to
16 MHz.
The PLL is enabled by setting the PLLCFG bit (CONFIG1H) or the PLLEN bit (OSCTUNE).
For the EC and HS modes, the PLLEN (software) or
PLLCFG (CONFIG1H) bit can be used to enable
the PLL.
For the INTIOx modes (HF-INTOSC):
• Only the PLLEN can enable the PLL (PLLCFG is
ignored).
• When the oscillator is configured for the internal
oscillator (FOSC = 100x), the PLL can be
enabled only when the HF-INTOSC frequency is
4, 8 or 16 MHz.
When the RA6 and RA7 pins are not used for an oscillator function or CLKOUT function, they are available
as general purpose I/Os.
DS30009977G-page 48
To optimize power consumption when using
EC/HS/XT/LP/RC as the primary oscillator, the frequency input range can be configured to yield an optimized power bias:
• Low-Power Bias – External frequency less than
160 kHz
• Medium Power Bias – External frequency
between 160 kHz and 16 MHz
• High-Power Bias – External frequency greater
than 16 MHz
All of these modes are selected by the user by
programming the FOSC Configuration bits
(CONFIG1H). In addition, PIC18F66K80 family
devices can switch between different clock sources,
either under software control, or under certain conditions, automatically. This allows for additional power
savings by managing device clock speed in real time
without resetting the application. The clock sources for
the PIC18F66K80 family of devices are shown in
Figure 3-1.
For the HS and EC mode, there are additional power
modes of operation, depending on the frequency of
operation.
HS1 is the Medium Power mode with a frequency
range of 4 MHz to 16 MHz. HS2 is the High-Power
mode, where the oscillator frequency can go from
16 MHz to 25 MHz. HS1 and HS2 are achieved by
setting the CONFIG1H bits correctly. (For details,
see Register 28-2 on Page 450.)
EC mode has these modes of operation:
• EC1 – For low power with a frequency range up to
160 kHz
• EC2 – Medium power with a frequency range of
160 kHz to 16 MHz
• EC3 – High power with a frequency range of
16 MHz to 64 MHz
EC1, EC2 and EC3 are achieved by setting the CONFIG1H correctly. (For details, see Register 28-2
on Page 450.)
Table 3-1 shows the HS and EC modes’ frequency
range and FOSC settings.
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 3-1:
HS, EC, XT, LP AND RC MODES: RANGES AND SETTINGS
Mode
Frequency Range
EC1 (low power)
FOSC Setting
1101
DC-160 kHz
(EC1 & EC1IO)
EC2 (medium power)
1100
1011
160 kHz-16 MHz
(EC2 & EC2IO)
EC3 (high power)
1010
0101
16 MHz-64 MHz
(EC3 & EC3IO)
0100
HS1 (medium power)
4 MHz-16 MHz
0011
HS2 (high power)
16 MHz-25 MHz
0010
XT
100 kHz-4 MHz
0001
LP
31.25 kHz
0000
0-4 MHz
001x
32 kHz-16 MHz
100x
(and OSCCON, OSCCON2)
RC (External)
INTIO
FIGURE 3-1:
PIC18F66K80 FAMILY CLOCK DIAGRAM
SOSCO
SOSCI
Peripherals
MUX
MUX
MUX
4x PLL
OSC2
CPU
OSC1
PLLEN
and PLLCFG
FOSC
IDLEN
16 MHz 111
HF-INTOSC
16 MHz to
31 kHz
8 MHz
4 MHz
4 MHz
2 MHz
2 MHz
1 MHz
1 MHz
250 kHz
500 kHz
250 kHz
31 kHz
MFIOSEL
LF-INTOSC
31 kHz
011
FOSC
IRCF
MUX
MF-INTOSC
500 kHz to
31 kHz
100
MUX
Postscaler
31 kHz
SCS
101
500 kHz
010
250 kHz
001
31 kHz
000
500 kHz
Clock Control
110
MUX
Postscaler
16 MHz
8 MHz
INTSRC
31 kHz
2010-2017 Microchip Technology Inc.
DS30009977G-page 49
PIC18F66K80 FAMILY
3.2
Control Registers
The OSCCON register (Register 3-1) controls the main
aspects of the device clock’s operation. It selects the
oscillator type to be used, which of the power-managed
modes to invoke and the output frequency of the
INTOSC source. It also provides status on the oscillators.
REGISTER 3-1:
The OSCTUNE register (Register 3-3) controls the
tuning and operation of the internal oscillator block. It also
implements the PLLEN bit which controls the operation of
the Phase Locked Loop (PLL) (see Section 3.5.3 “PLL
Frequency Multiplier”).
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0
R/W-1
IDLEN
IRCF2(2)
R/W-1
IRCF1
(2)
R/W-0
IRCF0
(2)
R(1)
OSTS
R-0
HFIOFS
R/W-0
(4)
SCS1
R/W-0
SCS0(4)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IDLEN: Idle Enable bit
1 = Device enters an Idle mode when a SLEEP instruction is executed
0 = Device enters Sleep mode when a SLEEP instruction is executed
bit 6-4
IRCF: Internal Oscillator Frequency Select bits(2)
111 = HF-INTOSC output frequency is used (16 MHz)
110 = HF-INTOSC/2 output frequency is used (8 MHz, default)
101 = HF-INTOSC/4 output frequency is used (4 MHz)
100 = HF-INTOSC/8 output frequency is used (2 MHz)
011 = HF-INTOSC/16 output frequency is used (1 MHz)
If INTSRC = 0 and MFIOSEL = 0:(3,5)
010 = HF-INTOSC/32 output frequency is used (500 kHz)
001 = HF-INTOSC/64 output frequency is used (250 kHz)
000 = LF-INTOSC output frequency is used (31.25 kHz)(6)
If INTSRC = 1 and MFIOSEL = 0:(3,5)
010 = HF-INTOSC/32 output frequency is used (500 kHz)
001 = HF-INTOSC/64 output frequency is used (250 kHz)
000 = HF-INTOSC/512 output frequency is used (31.25 kHz)
If INTSRC = 0 and MFIOSEL = 1:(3,5)
010 = MF-INTOSC output frequency is used (500 kHz)
001 = MF-INTOSC/2 output frequency is used (250 kHz)
000 = LF-INTOSC output frequency is used (31.25 kHz)(6)
If INTSRC = 1 and MFIOSEL = 1:(3,5)
010 = MF-INTOSC output frequency is used (500 kHz)
001 = MF-INTOSC/2 output frequency is used (250 kHz)
000 = MF-INTOSC/16 output frequency is used (31.25 kHz)
bit 3
OSTS: Oscillator Start-up Timer Time-out Status bit(1)
1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running, as defined by
FOSC
0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready – device is
running from internal oscillator (HF-INTOSC, MF-INTOSC or LF-INTOSC)
Note 1:
2:
3:
4:
5:
6:
The Reset state depends on the state of the IESO Configuration bit (CONFIG1H).
Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
The source is selected by the INTSRC bit (OSCTUNE).
Modifying these bits will cause an immediate clock source switch.
INTSRC = OSCTUNE and MFIOSEL = OSCCON2.
This is the lowest power option for an internal source.
DS30009977G-page 50
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
REGISTER 3-1:
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 2
HFIOFS: HF-INTOSC Frequency Stable bit
1 = HF-INTOSC oscillator frequency is stable
0 = HF-INTOSC oscillator frequency is not stable
bit 1-0
SCS: System Clock Select bits(4)
1x = Internal oscillator block (LF-INTOSC, MF-INTOSC or HF-INTOSC)
01 = SOSC oscillator
00 = Default primary oscillator (OSC1/OSC2 or HF-INTOSC with or without PLL; defined by the
FOSC Configuration bits, CONFIG1H)
Note 1:
2:
3:
4:
5:
6:
The Reset state depends on the state of the IESO Configuration bit (CONFIG1H).
Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
The source is selected by the INTSRC bit (OSCTUNE).
Modifying these bits will cause an immediate clock source switch.
INTSRC = OSCTUNE and MFIOSEL = OSCCON2.
This is the lowest power option for an internal source.
REGISTER 3-2:
OSCCON2: OSCILLATOR CONTROL REGISTER 2
U-0
R-0
U-0
R/W-1
R/W-0
U-0
R-x
R/W-0
—
SOSCRUN
—
SOSCDRV(1)
SOSCGO
—
MFIOFS
MFIOSEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
SOSCRUN: SOSC Run Status bit
1 = System clock comes from a secondary SOSC
0 = System clock comes from an oscillator other than SOSC
bit 5
Unimplemented: Read as ‘0’
bit 4
SOSCDRV: Secondary Oscillator Drive Control bit(1)
1 = High-power SOSC circuit is selected
0 = Low/high-power select is done via the SOSCSEL Configuration bits
bit 3
SOSCGO: Oscillator Start Control bit
1 = Oscillator is running even if no other sources are requesting it.
0 = Oscillator is shut off if no other sources are requesting it (When the SOSC is selected to run from
a digital clock input, rather than an external crystal, this bit has no effect.)
bit 2
Unimplemented: Read as ‘0’
bit 1
MFIOFS: MF-INTOSC Frequency Stable bit
1 = MF-INTOSC is stable
0 = MF-INTOSC is not stable
bit 0
MFIOSEL: MF-INTOSC Select bit
1 = MF-INTOSC is used in place of HF-INTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz
0 = MF-INTOSC is not used
Note 1:
When SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no effect.
2010-2017 Microchip Technology Inc.
DS30009977G-page 51
PIC18F66K80 FAMILY
REGISTER 3-3:
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTSRC
PLLEN
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock is derived from 16 MHz INTOSC source (divide-by-512 enabled, HF-INTOSC)
0 = 31 kHz device clock is derived from INTOSC 31 kHz oscillator (LF-INTOSC)
bit 6
PLLEN: Frequency Multiplier PLL Enable bit
1 = PLL is enabled
0 = PLL is disabled
bit 5-0
TUN: Fast RC Oscillator (INTOSC) Frequency Tuning bits
011111 = Maximum frequency
•
•
•
•
000001
000000 = Center frequency; fast RC oscillator is running at the calibrated frequency
111111
•
•
•
•
100000 = Minimum frequency
DS30009977G-page 52
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
3.3
Clock Sources and
Oscillator Switching
Essentially, PIC18F66K80 family devices have these
independent clock sources:
• Primary oscillators
• Secondary oscillators
• Internal oscillator
The primary oscillators can be thought of as the main
device oscillators. These are any external oscillators
connected to the OSC1 and OSC2 pins, and include
the External Crystal and Resonator modes and the
External Clock modes. If selected by the FOSC
Configuration bits (CONFIG1H), the internal
oscillator block may be considered a primary oscillator.
The internal oscillator block can be one of the following:
• 31 kHz LF-INTOSC source
• 31 kHz to 500 kHz MF-INTOSC source
• 31 kHz to 16 MHz HF-INTOSC source
In addition to being a primary clock source in some
circumstances, the internal oscillator is available as a
power-managed mode clock source. The LF-INTOSC
source is also used as the clock source for several
special features, such as the WDT and Fail-Safe Clock
Monitor. The internal oscillator block is discussed in
more detail in Section 3.6 “Internal Oscillator
Block”.
The PIC18F66K80 family includes features that allow
the device clock source to be switched from the main
oscillator, chosen by device configuration, to one of the
alternate clock sources. When an alternate clock
source is enabled, various power-managed operating
modes are available.
3.3.1
The OSC1/OSC2 oscillator block is used to provide the
oscillator modes and frequency ranges:
The particular mode is defined by the FOSCx
Configuration bits. The details of these modes are
covered in Section 3.5 “External Oscillator Modes”.
The secondary oscillators are external clock
sources that are not connected to the OSC1 or OSC2
pin. These sources may continue to operate, even
after the controller is placed in a power-managed
mode. PIC18F66K80 family devices offer the SOSC
(Timer1/3/5/7) oscillator as a secondary oscillator
source.
The SOSC can be enabled from any peripheral that
requests it. The SOSC can be enabled several ways by
doing one of the following:
• The SOSC is selected as the source by either of
the odd timers, which is done by each respective
SOSCEN bit (TxCON)
• The SOSC is selected as the CPU clock source
by the SCSx bits (OSCCON)
• The SOSCGO bit is set (OSCCON2)
The SOSCGO bit is used to warm up the SOSC so that
it is ready before any peripheral requests it.
The secondary oscillator has three Run modes. The
SOSCSEL bits (CONFIG1L) decide the
SOSC mode of operation:
• 11 = High-Power SOSC Circuit
• 10 = Digital (SCLKI) mode
• 11 = Low-Power SOSC Circuit
If a secondary oscillator is not desired and digital I/O on
port pins, RC0 and RC1, is needed, the SOSCSELx
bits must be set to Digital mode.
2010-2017 Microchip Technology Inc.
OSC1/OSC2 OSCILLATOR
Mode
Design Operating Frequency
LP
31.25-100 kHz
XT
100 kHz to 4 MHz
HS
4 MHz to 25 MHz
EC
0 to 64 MHz (external clock)
EXTRC
0 to 4 MHz (external RC)
The crystal-based oscillators (XT, HS and LP) have a
built-in start-up time. The operation of the EC and
EXTRC clocks is immediate.
3.3.2
CLOCK SOURCE SELECTION
The System Clock Select bits, SCS
(OSCCON), select the clock source. The available clock sources are the primary clock defined by the
FOSC Configuration bits, the secondary clock
(SOSC oscillator) and the internal oscillator. The clock
source changes after one or more of the bits is written
to, following a brief clock transition interval.
The
OSTS
(OSCCON)
and
SOSCRUN
(OSCCON2) bits indicate which clock source is
currently providing the device clock. The OSTS bit
indicates that the Oscillator Start-up Timer (OST) has
timed out and the primary clock is providing the device
clock in primary clock modes. The SOSCRUN bit indicates when the SOSC oscillator (from Timer1/3/5/7) is
providing the device clock in secondary clock modes.
In power-managed modes, only one of these bits will
be set at any time. If neither of these bits is set, the
INTOSC is providing the clock or the internal oscillator
has just started and is not yet stable.
The IDLEN bit (OSCCON) determines if the device
goes into Sleep mode or one of the Idle modes when
the SLEEP instruction is executed.
DS30009977G-page 53
PIC18F66K80 FAMILY
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
“Power-Managed Modes”.
Note 1: The Timer1/3/5/7 oscillator must be
enabled to select the secondary clock
source. The Timerx oscillator is enabled by
setting the SOSCEN bit in the Timerx Control register (TxCON). If the Timerx
oscillator is not enabled, then any attempt
to select a secondary clock source when
executing a SLEEP instruction will be
ignored.
2: It is recommended that the Timerx
oscillator be operating and stable before
executing the SLEEP instruction or a very
long delay may occur while the Timerx
oscillator starts.
3.3.2.1
System Clock Selection and Device
Resets
Since the SCSx bits are cleared on all forms of Reset,
this means the primary oscillator defined by the
FOSC Configuration bits is used as the primary
clock source on device Resets. This could either be the
internal oscillator block by itself, or one of the other
primary clock sources (HS, EC, XT, LP, External RC
and PLL-enabled modes).
In those cases when the internal oscillator block, without PLL, is the default clock on Reset, the Fast RC
Oscillator (INTOSC) will be used as the device clock
source. It will initially start at 8 MHz; the postscaler
selection that corresponds to the Reset value of the
IRCF bits (‘110’).
Regardless of which primary oscillator is selected,
INTOSC will always be enabled on device power-up. It
serves as the clock source until the device has loaded
its configuration values from memory. It is at this point
that the FOSCx Configuration bits are read and the
oscillator selection of the operational mode is made.
Note that either the primary clock source or the internal
oscillator will have two bit setting options for the possible
values of the SCS bits, at any given time.
3.3.3
3.4
RC Oscillator
For timing-insensitive applications, the RC and RCIO
Oscillator modes offer additional cost savings. The actual
oscillator frequency is a function of several factors:
• Supply voltage
• Values of the external resistor (REXT) and capacitor
(CEXT)
• Operating temperature
Given the same device, operating voltage and temperature, and component values, there will also be unit to unit
frequency variations. These are due to factors such as:
• Normal manufacturing variation
• Difference in lead frame capacitance between
package types (especially for low CEXT values)
• Variations within the tolerance of the limits of
REXT and CEXT
In the RC Oscillator mode, the oscillator frequency,
divided by 4, is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-2 shows how the R/C combination is
connected.
FIGURE 3-2:
RC OSCILLATOR MODE
VDD
REXT
Internal
Clock
OSC1
CEXT
PIC18F66K80
VSS
FOSC/4
OSC2/CLKO
Recommended values: 3 k REXT 100 k
20 pF CEXT 300 pF
The RCIO Oscillator mode (Figure 3-3) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 3-3:
RCIO OSCILLATOR MODE
VDD
OSCILLATOR TRANSITIONS
PIC18F66K80 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
REXT
Clock transitions are discussed in greater detail in
Section 4.1.2 “Entering Power-Managed Modes”.
Recommended values: 3 k REXT 100 k
20 pF CEXT 300 pF
DS30009977G-page 54
Internal
Clock
OSC1
CEXT
PIC18F66K80
VSS
RA6
I/O (OSC2)
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
3.5
External Oscillator Modes
3.5.1
TABLE 3-3:
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS (HS MODES)
In HS or HSPLL Oscillator modes, a crystal or ceramic
resonator is connected to the OSC1 and OSC2 pins to
establish oscillation. Figure 3-4 shows the pin
connections.
The oscillator design requires the use of a crystal rated
for parallel resonant operation.
Note:
Use of a crystal rated for series resonant
operation may give a frequency out of the
crystal manufacturer’s specifications.
TABLE 3-2:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Typical Capacitor Values Used:
Mode
Freq.
OSC1
OSC2
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Capacitor values are for design guidance only.
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Typical Capacitor Values
Tested:
Crystal
Freq.
Osc Type
HS
C1
C2
4 MHz
27 pF
27 pF
8 MHz
22 pF
22 pF
20 MHz
15 pF
15 pF
Capacitor values are for design guidance only.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
Refer to the Microchip application notes cited in
Table 3-2 for oscillator specific information. Also see
the notes following this table for additional
information.
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application. Refer
to the following application notes for oscillator-specific
information:
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external components.
• AN588, “PIC® Microcontroller Oscillator Design
Guide”
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC® and PIC® Devices”
• AN849, “Basic PIC® Oscillator Design”
• AN943, “Practical PIC® Oscillator Analysis and
Design”
• AN949, “Making Your Oscillator Work”
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
See the notes following Table 3-3 for additional
information.
3: Rs may be required to avoid overdriving
crystals with low drive level specification.
FIGURE 3-4:
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS OR HSPLL
CONFIGURATION)
C1(1)
OSC1
XTAL
RF(3)
OSC2
C2(1)
2010-2017 Microchip Technology Inc.
RS(2)
To
Internal
Logic
Sleep
PIC18F66K80
Note 1:
See Table 3-2 and Table 3-3 for initial values of
C1 and C2.
2:
A series resistor (RS) may be required for AT
strip cut crystals.
3:
RF varies with the oscillator mode chosen.
DS30009977G-page 55
PIC18F66K80 FAMILY
EXTERNAL CLOCK INPUT
(EC MODES)
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-5 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-5:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
OSC1/CLKI
Clock from
Ext. System
HSPLL and ECPLL Modes
The HSPLL and ECPLL modes provide the ability to
selectively run the device at four times the external
oscillating source to produce frequencies up to
64 MHz.
The PLL is enabled by setting the PLLEN bit
(OSCTUNE) or the PLLCFG bit (CONFIG1H).
For the HF-INTOSC as primary, the PLL must be
enabled with the PLLEN. This provides a software control for the PLL, enabling even if PLLCFG is set to ‘1’,
so that the PLL is enabled only when the HF-INTOSC
frequency is within the 4 MHz to16 MHz input range.
This also enables additional flexibility for controlling the
application’s clock speed in software. The PLLEN
should be enabled in HF-INTOSC mode only if the
input frequency is in the range of 4 MHz-16 MHz.
FIGURE 3-7:
PLL BLOCK DIAGRAM
PIC18F66K80
FOSC/4
FIGURE 3-6:
PLLCFG (CONFIG1H)
PLL Enable (OSCTUNE)
OSC2/CLKO
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-6. In
this configuration, the divide-by-4 output on OSC2 is
not available. Current consumption in this configuration
will be somewhat higher than EC mode, as the internal
oscillator’s feedback circuitry will be enabled (in EC
mode, the feedback circuit is disabled).
OSC2
HS or EC
Mode
OSC1
FIN
Phase
Comparator
FOUT
Loop
Filter
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
Clock from
Ext. System
4
VCO
SYSCLK
OSC1
PIC18F66K80
(HS Mode)
Open
3.5.3
3.5.3.1
MUX
3.5.2
OSC2
PLL FREQUENCY MULTIPLIER
A Phase Lock Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator.
DS30009977G-page 56
3.5.3.2
PLL and HF-INTOSC
The PLL is available to the internal oscillator block
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 64 MHz.
The operation of INTOSC with the PLL is described in
Section 3.6.2 “INTPLL Modes”. Care should be taken
that the PLL is enabled only if the HF-INTOSC
postscaler is configured for 4 MHz, 8 MHz or 16 MHz.
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
3.6
Internal Oscillator Block
The PIC18F66K80 family of devices includes an internal
oscillator block which generates two different clock
signals. Either clock can be used as the microcontroller’s
clock source, which may eliminate the need for an
external oscillator circuit on the OSC1 and/or OSC2 pins.
The Internal oscillator consists of three blocks,
depending on the frequency of operation. They are
HF-INTOSC, MF-INTOSC and LF-INTOSC.
In HF-INTOSC mode, the internal oscillator can provide
a frequency ranging from 31 KHz to 16 MHz, with the
postscaler
deciding
the
selected
frequency
(IRCF).
The INTSRC bit (OSCTUNE) and MFIOSEL bit
(OSCCON2) also decide which INTOSC provides
the lower frequency (500 kHz to 31 KHz). For the
HF-INTOSC to provide these frequencies, INTSRC = 1
and MFIOSEL = 0.
In HF-INTOSC, the postscaler (IRCF) provides
the frequency range of 31 kHz to 16 MHz. If
HF-INTOSC is used with the PLL, the input frequency
to the PLL should be 4 MHz to 16 MHz
(IRCF = 111, 110 or 101).
For MF-INTOSC mode to provide a frequency range of
500 kHz to 31 kHz, INTSRC = 1 and MFIOSEL = 1.
The postscaler (IRCF), in this mode, provides the
frequency range of 31 kHz to 500 kHz.
The LF-INTOSC can provide only 31 kHz if INTSRC = 0.
The LF-INTOSC provides 31 kHz and is enabled if it is
selected as the device clock source. The mode is
enabled automatically when any of the following are
enabled:
• Power-up Timer (PWRT)
• Fail-Safe Clock Monitor (FSCM)
• Watchdog Timer (WDT)
• Two-Speed Start-up
These features are discussed in greater detail in
Section 28.0 “Special Features of the CPU”.
The clock source frequency (HF-INTOSC, MF-INTOSC
or LF-INTOSC direct) is selected by configuring the
IRCFx bits of the OSCCON register, as well the
INTSRC and MFIOSEL bits. The default frequency on
device Resets is 8 MHz.
3.6.1
FIGURE 3-8:
INTIO1 OSCILLATOR MODE
I/O (OSC1)
RA7
PIC18F66K80
OSC2
FOSC/4
FIGURE 3-9:
RA7
INTIO2 OSCILLATOR MODE
I/O (OSC1)
PIC18F66K80
RA6
3.6.2
I/O (OSC2)
INTPLL MODES
The 4x Phase Lock Loop (PLL) can be used with the
HF-INTOSC to produce faster device clock speeds
than are normally possible with the internal oscillator
sources. When enabled, the PLL produces a clock
speed of 16 MHz or 64 MHz.
PLL operation is controlled through software. The
control bits, PLLEN (OSCTUNE) and PLLCFG
(CONFIG1H), are used to enable or disable its
operation. The PLL is available only to HF-INTOSC.
The other oscillator is set with HS and EC modes. Additionally, the PLL will only function when the selected
output frequency is either 4 MHz or 16 MHz
(OSCCON = 111, 110 or 101).
Like the INTIO modes, there are two distinct INTPLL
modes available:
• In INTPLL1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output. Externally, this is identical in appearance
to INTIO1 (see Figure 3-8).
• In INTPLL2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output. Externally, this is identical to INTIO2 (see
Figure 3-9).
INTIO MODES
Using the internal oscillator as the clock source eliminates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
oscillator configurations, which are determined by the
FOSCx Configuration bits, are available:
• In INTIO1 mode, the OSC2 pin (RA6) outputs
FOSC/4, while OSC1 functions as RA7 (see
Figure 3-8) for digital input and output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6 (see Figure 3-9). Both
are available as digital input and output ports.
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3.6.3
INTERNAL OSCILLATOR OUTPUT
FREQUENCY AND TUNING
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 16 MHz. It
can be adjusted in the user’s application by writing to
TUN (OSCTUNE) in the OSCTUNE
register (Register 3-3).
When the OSCTUNE register is modified, the INTOSC
(HF-INTOSC and MF-INTOSC) frequency will begin
shifting to the new frequency. The oscillator will require
some time to stabilize. Code execution continues
during this shift and there is no indication that the shift
has occurred.
3.6.4.3
Compensating with the CCP Module
in Capture Mode
A CCP module can use free-running Timer1 (or Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
The LF-INTOSC oscillator operates independently of
the HF-INTOSC or the MF-INTOSC source. Any
changes in the HF-INTOSC or the MF-INTOSC source,
across voltage and temperature, are not necessarily
reflected by changes in LF-INTOSC or vice versa. The
frequency of LF-INTOSC is not affected by OSCTUNE.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast. To compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow. To compensate, increment the OSCTUNE
register.
3.6.4
3.7
INTOSC FREQUENCY DRIFT
The INTOSC frequency may drift as VDD or temperature changes and can affect the controller operation in
a variety of ways. It is possible to adjust the INTOSC
frequency by modifying the value in the OSCTUNE
register. Depending on the device, this may have no
effect on the LF-INTOSC clock source frequency.
Tuning INTOSC requires knowing when to make the
adjustment, in which direction it should be made, and in
some cases, how large a change is needed. Three
compensation techniques are shown here.
3.6.4.1
Compensating with the EUSARTx
An adjustment may be required when the EUSARTx
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high. To
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low. To
compensate, increment OSCTUNE to increase the
clock frequency.
3.6.4.2
Compensating with the Timers
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the SOSC
oscillator.
Reference Clock Output
In addition to the FOSC/4 clock output, in certain
oscillator modes, the device clock in the PIC18F66K80
family can also be configured to provide a reference
clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user
to select a greater range of clock submultiples to drive
external devices in the application.
This reference clock output is controlled by the
REFOCON register (Register 3-4). Setting the ROON
bit (REFOCON) makes the clock signal available
on the REFO (RC3) pin. The RODIV bits enable
the selection of 16 different clock divider options.
The ROSSLP and ROSEL bits (REFOCON) control the availability of the reference output during Sleep
mode. The ROSEL bit determines if the oscillator on
OSC1 and OSC2, or the current system clock source,
is used for the reference clock output. The ROSSLP bit
determines if the reference source is available on RE3
when the device is in Sleep mode.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for an EC or HS mode. If
not, the oscillator on OSC1 and OSC2 will be powered
down when the device enters Sleep mode. Clearing the
ROSEL bit allows the reference output frequency to
change as the system clock changes during any clock
switches.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is much greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
DS30009977G-page 58
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
REGISTER 3-4:
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ROON
—
ROSSLP
ROSEL(1)
RODIV3
RODIV2
RODIV1
RODIV0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ROON: Reference Oscillator Output Enable bit
1 = Reference oscillator output is available on REFO pin
0 = Reference oscillator output is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
ROSSLP: Reference Oscillator Output Stop in Sleep bit
1 = Reference oscillator continues to run in Sleep
0 = Reference oscillator is disabled in Sleep
bit 4
ROSEL: Reference Oscillator Source Select bit(1)
1 = Primary oscillator (EC or HS) is used as the base clock
0 = System clock is used as the base clock; base clock reflects any clock switching of the device
bit 3-0
RODIV: Reference Oscillator Divisor Select bits
1111 = Base clock value divided by 32,768
1110 = Base clock value divided by 16,384
1101 = Base clock value divided by 8,192
1100 = Base clock value divided by 4,096
1011 = Base clock value divided by 2,048
1010 = Base clock value divided by 1,024
1001 = Base clock value divided by 512
1000 = Base clock value divided by 256
0111 = Base clock value divided by 128
0110 = Base clock value divided by 64
0101 = Base clock value divided by 32
0100 = Base clock value divided by 16
0011 = Base clock value divided by 8
0010 = Base clock value divided by 4
0001 = Base clock value divided by 2
0000 = Base clock value
Note 1:
For ROSEL (REFOCON), the primary oscillator is available only when configured as the default via the
FOSCx settings. This is regardless of whether the device is in Sleep mode.
2010-2017 Microchip Technology Inc.
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3.8
Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and SEC_IDLE), the SOSC oscillator is operating and providing
the device clock. The SOSC oscillator may also run in
all power-managed modes if required to clock SOSC.
In RC_RUN and RC_IDLE modes, the internal
oscillator provides the device clock source. The 31 kHz
LF-INTOSC output can be used directly to provide the
clock and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 28.2 “Watchdog Timer (WDT)” through
Section 28.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
3.9
Power-up Delays
Power-up delays are controlled by two timers, so that no
external Reset circuitry is required for most applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal circumstances and the primary clock is operating and stable.
For additional information on power-up delays, see
Section 5.6.1 “Power-up Timer (PWRT)”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up time of about 64 ms
(Parameter 33, Table 31-11); it is always enabled.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS, XT or LP modes). The
OST does this by counting 1,024 oscillator cycles
before allowing the oscillator to clock the device.
There is a delay of interval, TCSD (Parameter 38,
Table 31-11), following POR, while the controller
becomes ready to execute instructions.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents have
been stopped, Sleep mode achieves the lowest current
consumption of the device (only leakage currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTOSC is required to support WDT operation. The
SOSC oscillator may be operating to support Timer1 or
3. Other features may be operating that do not require a
device clock source (i.e., MSSP slave, INTx pins and
others). Peripherals that may add significant current consumption are listed in Section 31.2 “DC Characteristics: Power-Down and Supply Current PIC18F66K80
Family (Industrial/Extended)”.
TABLE 3-4:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode
OSC1 Pin
OSC2 Pin
EC, ECPLL
Floating, pulled by external clock
At logic low (clock/4 output)
HS, HSPLL
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
INTOSC, INTPLL1/2
I/O pin, RA6, direction controlled by
TRISA
I/O pin, RA6, direction controlled by
TRISA
Note:
See Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.
DS30009977G-page 60
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4.0
POWER-MANAGED MODES
The PIC18F66K80 family of devices offers a total of
seven operating modes for more efficient power management. These modes provide a variety of options for
selective power conservation in applications where
resources may be limited (such as battery-powered
devices).
There are three categories of power-managed mode:
• Run modes
• Idle modes
• Sleep mode
There is an Ultra Low-Power Wake-up (ULPWU) for
waking from Sleep mode.
These categories define which portions of the device
are clocked, and sometimes, at what speed. The Run
and Idle modes may use any of the three available
clock sources (primary, secondary or internal oscillator
block). The Sleep mode does not use a clock source.
The ULPWU mode, on the RA0 pin, enables a slow falling voltage to generate a wake-up, even from Sleep,
without excess current consumption. (See Section 4.7
“Ultra Low-Power Wake-up”.)
The power-managed modes include several
power-saving features offered on previous PIC®
devices. One is the clock switching feature, offered in
other PIC18 devices. This feature allows the controller
to use the SOSC oscillator instead of the primary one.
Another power-saving feature is Sleep mode, offered
by all PIC devices, where all device clocks are stopped.
4.1
Selecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions:
• Will the CPU be clocked or not
• What will be the clock source
TABLE 4-1:
4.1.1
CLOCK SOURCES
The SCS bits select one of three clock sources
for power-managed modes. Those sources are:
• The primary clock as defined by the FOSC
Configuration bits
• The Secondary Clock (the SOSC oscillator)
• The Internal Oscillator block (for LF-INTOSC
modes)
4.1.2
ENTERING POWER-MANAGED
MODES
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS bits select the clock source and determine
which Run or Idle mode is used. Changing these bits
causes an immediate switch to the new clock source,
assuming that it is running. The switch may also be
subject to clock transition delays. These considerations
are discussed in Section 4.1.3 “Clock Transitions
and Status Indicators” and subsequent sections.
Entering the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current and impending mode, a
change to a power-managed mode does not always
require setting all of the previously discussed bits. Many
transitions can be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured as
desired, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
POWER-MANAGED MODES
OSCCON Bits
Mode
The IDLEN bit (OSCCON) controls CPU clocking,
while the SCS bits (OSCCON) select the
clock source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table 4-1.
Module Clocking
Available Clock and Oscillator Source
IDLEN(1)
SCS
CPU
Peripherals
0
N/A
Off
Off
PRI_RUN
N/A
00
Clocked
Clocked
Primary – XT, LP, HS, EC, RC and PLL modes.
This is the normal, full-power execution mode.
SEC_RUN
N/A
01
Clocked
Clocked
Secondary – SOSC Oscillator
RC_RUN
N/A
1x
Clocked
Clocked
Internal oscillator block(2)
PRI_IDLE
1
00
Off
Clocked
Primary – LP, XT, HS, RC, EC
SEC_IDLE
1
01
Off
Clocked
Secondary – SOSC oscillator
RC_IDLE
1
1x
Off
Clocked
Internal oscillator block(2)
Sleep
Note 1:
2:
None – All clocks are disabled
IDLEN reflects its value when the SLEEP instruction is executed.
Includes INTOSC (HF-INTOSC and MG-INTOSC) and INTOSC postscaler, as well as the LF-INTOSC
source.
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4.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable. The
HF-INTOSC and MF-INTOSC are termed as INTOSC
in this chapter.
Three bits indicate the current clock source and its
status, as shown in Table 4-2. The three bits are:
• OSTS (OSCCON)
• HFIOFS (OSCCON)
• SOSCRUN (OSCCON2)
TABLE 4-2:
HFIOFS or
OSTS
SOSCRUN
MFIOFS
Primary Oscillator
1
0
0
INTOSC (HF-INTOSC
or MF-INTOSC)
0
1
0
Secondary Oscillator
0
0
1
MF-INTOSC or
HF-INTOSC as Primary
Clock Source
1
1
0
LF-INTOSC is
Running or INTOSC is
Not Yet Stable
0
0
0
When the OSTS bit is set, the primary clock is providing
the device clock. When the HFIOFS or MFIOFS bit is
set, the INTOSC output is providing a stable clock
source to a divider that actually drives the device clock.
When the SOSCRUN bit is set, the SOSC oscillator is
providing the clock. If none of these bits are set, either
the LF-INTOSC clock source is clocking the device or
the INTOSC source is not yet stable.
If the internal oscillator block is configured as the
primary clock source by the FOSC Configuration
bits (CONFIG1H). Then, the OSTS and HFIOFS
or MFIOFS bits can be set when in PRI_RUN or PRI_IDLE mode. This indicates that the primary clock
(INTOSC output) is generating a stable output. Entering another INTOSC power-managed mode at the
same frequency would clear the OSTS bit.
Note 1: Caution should be used when modifying
a single IRCF bit. At a lower VDD, it is
possible to select a higher clock speed
than is supportable by that VDD. Improper
device operation may result if the
VDD/FOSC specifications are violated.
2: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
DS30009977G-page 62
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
4.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
SYSTEM CLOCK INDICATOR
Main Clock Source
4.1.4
4.2.1
PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default
mode upon a device Reset, unless Two-Speed Start-up
is enabled. (For details, see Section 28.4 “Two-Speed
Start-up”.) In this mode, the OSTS bit is set. The
HFIOFS or MFIOFS bit may be set if the internal
oscillator block is the primary clock source. (See
Section 3.2 “Control Registers”.)
4.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock-switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the SOSC oscillator. This enables lower
power consumption while retaining a high-accuracy
clock source.
SEC_RUN mode is entered by setting the SCS
bits to ‘01’. The device clock source is switched to the
SOSC oscillator (see Figure 4-1), the primary oscillator
is shut down, the SOSCRUN bit (OSCCON2) is set
and the OSTS bit is cleared.
Note:
The SOSC oscillator can be enabled by
setting the SOSCGO bit (OSCCON2).
If this bit is set, the clock switch to the
SEC_RUN mode can switch immediately
once SCS are set to ‘01’.
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the SOSC oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 4-2). When the clock switch is complete, the
SOSCRUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCSx bits are not affected by the wake-up and the
SOSC oscillator continues to run.
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FIGURE 4-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
1
SOSCI
2
3
n-1
Q3
Q4
Q1
Q2
Q3
n
Clock Transition(1)
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
Note 1: Clock transition typically occurs within 2-4 TOSC.
FIGURE 4-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
SOSC
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
2
n-1 n
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program
Counter
SCS Bits Changed
PC + 2
PC
PC + 4
OSTS Bit Set
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
4.2.3
RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer. In this mode, the primary clock is
shut down. When using the LF-INTOSC source, this
mode provides the best power conservation of all the
Run modes, while still executing code. It works well for
user applications which are not highly timing-sensitive
or do not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
block – either LF-INTOSC or INTOSC (MF-INTOSC or
HF-INTOSC) – there are no distinguishable differences
between the PRI_RUN and RC_RUN modes during
execution. Entering or exiting RC_RUN mode, however, causes a clock switch delay. Therefore, if the
primary clock source is the internal oscillator block,
using RC_RUN mode is not recommended.
2010-2017 Microchip Technology Inc.
This mode is entered by setting the SCS1 bit to ‘1’. To
maintain software compatibility with future devices, it is
recommended that the SCS0 bit also be cleared, even
though the bit is ignored. When the clock source is
switched to the INTOSC multiplexer (see Figure 4-3),
the primary oscillator is shut down and the OSTS bit is
cleared. The IRCFx bits may be modified at any time to
immediately change the clock speed.
Note:
Caution should be used when modifying a
single IRCF bit. At a lower VDD, it is
possible to select a higher clock speed
than is supportable by that VDD. Improper
device operation may result if the
VDD/FOSC specifications are violated.
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If the IRCFx bits and the INTSRC bit are all clear, the
INTOSC output (HF-INTOSC/MF-INTOSC) is not
enabled and the HFIOFS and MFIOFS bits will remain
clear. There will be no indication of the current clock
source. The LF-INTOSC source is providing the device
clocks.
TABLE 4-3:
If the IRCFx bits are changed from all clear (thus,
enabling the INTOSC output) or if INTSRC or
MFIOSEL is set, the HFIOFS or MFIOFS bit is set after
the INTOSC output becomes stable. For details, see
Table 4-3.
INTERNAL OSCILLATOR FREQUENCY STABILITY BITS
IRCF
INTSRC
MFIOSEL
000
0
x
Status of MFIOFS or HFIOFS when INTOSC is Stable
MFIOFS = 0, HFIOFS = 0 and clock source is LF-INTOSC
000
1
0
MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC
000
1
1
MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC
Non-Zero
x
0
MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC
Non-Zero
x
1
MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC
Clocks to the device continue while the INTOSC source
stabilizes after an interval of TIOBST (Parameter 39,
Table 31-11).
If the IRCFx bits were previously at a non-zero value,
or if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the HFIOFS or
MFIOFS bit will remain set.
DS30009977G-page 64
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 4-4). When the clock
switch is complete, the HFIOFS or MFIOFS bit is
cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCSx bits
are not affected by the switch. The LF-INTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor (FSCM) is enabled.
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FIGURE 4-3:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
1
LF-INTOSC
2
3
n-1
Q3
Q4
Q1
Q2
Q3
n
Clock Transition(1)
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
Note 1: Clock transition typically occurs within 2-4 TOSC.
FIGURE 4-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q1
Q2
Q3
Q4
Q2 Q3 Q4 Q1 Q2 Q3
Q1
INTOSC
Multiplexer
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
2
n-1 n
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC
SCS Bits Changed
PC + 4
OSTS Bit Set
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
2010-2017 Microchip Technology Inc.
DS30009977G-page 65
PIC18F66K80 FAMILY
4.3
Sleep Mode
4.4
The power-managed Sleep mode in the PIC18F66K80
family of devices is identical to the legacy Sleep mode
offered in all other PIC devices. It is entered by clearing
the IDLEN bit (the default state on device Reset) and
executing the SLEEP instruction. This shuts down the
selected oscillator (Figure 4-5). All clock source status
bits are cleared.
Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS bits. The CPU,
however, will not be clocked. The clock source status bits
are not affected. This approach is a quick method to
switch from a given Run mode to its corresponding Idle
mode.
Entering Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the LF-INTOSC source will continue
to operate. If the SOSC oscillator is enabled, it will also
continue to run.
If the WDT is selected, the LF-INTOSC source will
continue to operate. If the SOSC oscillator is enabled,
it will also continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS bits
becomes ready (see Figure 4-6). Alternately, the device
will be clocked from the internal oscillator block if either
the Two-Speed Start-up or the Fail-Safe Clock Monitor is
enabled (see Section 28.0 “Special Features of the
CPU”). In either case, the OSTS bit is set when the
primary clock is providing the device clocks. The IDLEN
and SCSx bits are not affected by the wake-up.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(Parameter 38, Table 31-11) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCSx bits are not affected by the wake-up.
While in any Idle mode or Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS bits.
FIGURE 4-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
FIGURE 4-6:
PC + 2
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
OSC1
PLL Clock
Output
TOST(1)
TPLL(1)
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
PC + 2
PC + 4
PC + 6
OSTS Bit Set
Note1:TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS30009977G-page 66
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
4.4.1
PRI_IDLE MODE
4.4.2
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing-sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate, primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN
first, then clear the SCSx bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC Configuration bits. The OSTS bit
remains set (see Figure 4-7).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval, TCSD
(Parameter 39, Table 31-11), is required between the
wake event and the start of code execution. This is
required to allow the CPU to become ready to execute
instructions. After the wake-up, the OSTS bit remains
set. The IDLEN and SCSx bits are not affected by the
wake-up (see Figure 4-8).
FIGURE 4-7:
SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the SOSC
oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS bits to ‘01’ and execute
SLEEP. When the clock source is switched to the SOSC
oscillator, the primary oscillator is shut down, the OSTS
bit is cleared and the SOSCRUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the SOSC oscillator. After an interval
of TCSD following the wake event, the CPU begins
executing code that is being clocked by the SOSC
oscillator. The IDLEN and SCSx bits are not affected by
the wake-up and the SOSC oscillator continues to run
(see Figure 4-8).
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q1
Q4
Q3
Q2
Q1
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
PC
FIGURE 4-8:
PC + 2
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Q2
Q3
Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
2010-2017 Microchip Technology Inc.
DS30009977G-page 67
PIC18F66K80 FAMILY
4.4.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode
provides controllable power conservation during Idle
periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. To maintain software
compatibility with future devices, it is recommended
that SCS0 also be cleared, though its value is ignored.
The INTOSC multiplexer may be used to select a
higher clock frequency by modifying the IRCFx bits
before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer, the
primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCFx bits are set to any non-zero value, or the
INTSRC/MFIOSEL bit is set, the INTOSC output is
enabled. The HFIOFS/MFIOFS bits become set, after
the INTOSC output becomes stable, after an interval of
TIOBST (Parameter 38, Table 31-11). For information on
the HFIOFS/MFIOFS bits, see Table 4-3.
Clocks to the peripherals continue while the INTOSC
source stabilizes. The HFIOFS/MFIOFS bits will
remain set if the IRCFx bits were previously at a
non-zero value or if INTSRC was set before the SLEEP
instruction was executed and the INTOSC source was
already stable. If the IRCFx bits and INTSRC are all
clear, the INTOSC output will not be enabled, the
HFIOFS/MFIOFS bits will remain clear and there will be
no indication of the current clock source.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a delay
of TCSD (Parameter 38, Table 31-11) following the wake
event, the CPU begins executing code clocked by the
INTOSC multiplexer. The IDLEN and SCSx bits are not
affected by the wake-up. The INTOSC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
DS30009977G-page 68
4.5
Selective Peripheral Module
Control
Idle mode allows users to substantially reduce power
consumption by stopping the CPU clock. Even so,
peripheral modules still remain clocked, and thus, consume power. There may be cases where the application
needs what this mode does not provide: the allocation of
power resources to the CPU processing with minimal
power consumption from the peripherals.
PIC18F66K80 family devices address this requirement
by allowing peripheral modules to be selectively
disabled, reducing or eliminating their power
consumption. This can be done with two control bits:
• Peripheral Enable bit, generically named XXXEN –
Located in the respective module’s main control
register
• Peripheral Module Disable (PMD) bit, generically
named, XXXMD – Located in one of the PMDx
Control registers (PMD0, PMD1 or PMD2)
Disabling a module by clearing its XXXEN bit disables
the module’s functionality, but leaves its registers
available to be read and written to. This reduces power
consumption, but not by as much as the second
approach.
Most peripheral modules have an enable bit.
In contrast, setting the PMD bit for a module disables
all clock sources to that module, reducing its power
consumption to an absolute minimum. In this state, the
control and status registers associated with the peripheral are also disabled, so writes to those registers have
no effect and read values are invalid. Many peripheral
modules have a corresponding PMD bit.
There are three PMD registers in PIC18F66K80 family
devices: PMD0, PMD1 and PMD2. These registers
have bits associated with each module for disabling or
enabling a particular peripheral.
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
REGISTER 4-1:
PMD2: PERIPHERAL MODULE DISABLE REGISTER 2
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
MODMD(1)
ECANMD
CMP2MD
CMP1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
Unimplemented: Read as ‘0’
bit 3
MODMD: Modulator Output Module Disable bit(1)
1 = The modulator output module is disabled; all Modulator Output registers are held in Reset and are
not writable
0 = The modulator output module is enabled
bit 2
ECANMD: Enhanced CAN Module Disable bit
1 = The Enhanced CAN module is disabled; all Enhanced CAN registers are held in Reset and are
not writable
0 = The Enhanced CAN module is enabled
bit 1
CMP2MD: Comparator 2 Module Disable bit
1 = The Comparator 2 module is disabled; all Comparator 2 registers are held in Reset and are not
writable
0 = The Comparator 2 module is enabled
bit 0
CMP1MD: Comparator 1 Module Disable bit
1 = The Comparator 1 module is disabled; all Comparator 1 registers are held in Reset and are not
writable
0 = The Comparator 1 module is enabled
Note 1:
This bit is only implemented on devices with 64 pins (PIC18F6XK80, PIC18LF6XK80).
2010-2017 Microchip Technology Inc.
DS30009977G-page 69
PIC18F66K80 FAMILY
REGISTER 4-2:
PMD1: PERIPHERAL MODULE DISABLE REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PSPMD(1)
CTMUMD
ADCMD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
TMR0MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PSPMD: Peripheral Module Disable bit(1)
1 = The PSP module is disabled; all PSP registers are held in Reset and are not writable
0 = The PSP module is enabled
bit 6
CTMUMD: PMD CTMU Disable bit
1 = The CTMU module is disabled; all CTMU registers are held in Reset and are not writable
0 = The CTMU module is enabled
bit 5
ADCMD: A/D Module Disable bit
1 = The A/D module is disabled; all A/D registers are held in Reset and are not writable
0 = The A/D module is enabled
bit 4
TMR4MD: TMR4MD Disable bit
1 = The Timer4 module is disabled; all Timer4 registers are held in Reset and are not writable
0 = The Timer4 module is enabled
bit 3
TMR3MD: TMR3MD Disable bit
1 = The Timer3 module is disabled; all Timer3 registers are held in Reset and are not writable
0 = The Timer3 module is enabled
bit 2
TMR2MD: TMR2MD Disable bit
1 = The Timer2 module is disabled; all Timer2 registers are held in Reset and are not writable
0 = The Timer2 module is enabled
bit 1
TMR1MD: TMR1MD Disable bit
1 = The Timer1 module is disabled; all Timer1 registers are held in Reset and are not writable
0 = The Timer1 module is enabled
bit 0
TMR0MD: Timer0 Module Disable bit
1 = The Timer0 module is disabled; all Timer0 registers are held in Reset and are not writable
0 = The Timer0 module is enabled
Note 1:
This bit is unimplemented on 28-pin devices (PIC18F2XK80, PIC18LF2XK80).
DS30009977G-page 70
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
REGISTER 4-3:
PMD0: PERIPHERAL MODULE DISABLE REGISTER 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCP5MD
CCP4MD
CCP3MD
CCP2MD
CCP1MD
UART2MD
UART1MD
SSPMD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
CCP5MD: CCP5 Module Disable bit
1 = The CCP5 module is disabled; all CCP5 registers are held in Reset and are not writable
0 = The CCP5 module is enabled
bit 6
CCP4MD: CCP4 Module Disable bit
1 = The CCP4 module is disabled; all CCP4 registers are held in Reset and are not writable
0 = The CCP4 module is enabled
bit 5
CCP3MD: CCP3 Module Disable bit
1 = The CCP3 module is disabled; all CCP3 registers are held in Reset and are not writable
0 = The CCP3 module is enabled
bit 4
CCP2MD: CCP2 Module Disable bit
1 = The CCP2 module is disabled; all CCP2 registers are held in Reset and are not writable
0 = The CCP2 module is enabled
bit 3
CCP1MD: ECCP1 Module Disable bit
1 = The ECCP1 module is disabled; all ECCP1 registers are held in Reset and are not writable
0 = The ECCP1 module is enabled
bit 2
UART2MD: EUSART2 Module Disable bit
1 = The USART2 module is disabled; all USART2 registers are held in Reset and are not writable
0 = The USART2 module is enabled
bit 1
UART1MD: EUSART1 Module Disable bit
1 = The USART1 module is disabled; all USART1 registers are held in Reset and are not writable
0 = The USART1 module is enabled
bit 0
SSPMD: MSSP Module Disable bit
1 = The MSSP module is disabled; all SSP registers are held in Reset and are not writable
0 = The MSSP module is enabled
2010-2017 Microchip Technology Inc.
DS30009977G-page 71
PIC18F66K80 FAMILY
4.6
Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 4.2 “Run Modes”, Section 4.3
“Sleep Mode” and Section 4.4 “Idle Modes”).
4.6.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode or Sleep mode to a
Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCONx or PIEx registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON) is set. Otherwise, code
execution continues or resumes without branching
(see Section 10.0 “Interrupts”).
4.6.2
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 4.2 “Run
Modes” and Section 4.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 28.2 “Watchdog
Timer (WDT)”).
Executing a SLEEP or CLRWDT instruction clears the
WDT timer and postscaler, loses the currently selected
clock source (if the Fail-Safe Clock Monitor is enabled)
and modifies the IRCFx bits in the OSCCON register (if
the internal oscillator block is the device clock source).
DS30009977G-page 72
4.6.3
EXIT BY RESET
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins executing code. If the internal oscillator block is
the new clock source, the HFIOFS/MFIOFS bits are set
instead.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up, and the type of oscillator, if the
new clock source is the primary clock. Exit delays are
summarized in Table 4-4.
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 28.4 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 28.5 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution
as soon as the Reset source has cleared. Execution is
clocked by the INTOSC multiplexer driven by the internal oscillator block. Execution is clocked by the internal
oscillator block until either the primary clock becomes
ready or a power-managed mode is entered before the
primary clock becomes ready; the primary clock is then
shut down.
4.6.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. The two cases are:
• When in PRI_IDLE mode, where the primary
clock source is not stopped
• When the primary clock source is not any of the
LP, XT, HS or HSPLL modes
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally, does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval,
TCSD, following the wake event is still required when
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
4.7
Ultra Low-Power Wake-up
The Ultra Low-Power Wake-up (ULPWU) on pin, RA0,
allows a slow falling voltage to generate an interrupt
without excess current consumption.
To use this feature:
1.
2.
3.
4.
5.
A series resistor, between RA0 and the external
capacitor, provides overcurrent protection for the
RA0/CVREF/AN0/ULPWU pin and enables software
calibration of the time-out (see Figure 4-9).
FIGURE 4-9:
Charge the capacitor on RA0 by configuring the
RA0 pin to an output and setting it to ‘1’.
Stop charging the capacitor by configuring RA0
as an input.
Discharge the capacitor by setting the ULPEN
and ULPSINK bits in the WDTCON register.
Configure Sleep mode.
Enter Sleep mode.
ULTRA LOW-POWER
WAKE-UP INITIALIZATION
RA0/CVREF/AN0/ULPWU
When the voltage on RA0 drops below VIL, the device
wakes up and executes the next instruction.
This feature provides a low-power technique for
periodically waking up the device from Sleep mode.
The time-out is dependent on the discharge time of the
RC circuit on RA0.
When the ULPWU module wakes the device from
Sleep mode, the ULPLVL bit (WDTCON) is set.
Software can check this bit upon wake-up to determine
the wake-up source.
See Example 4-1 for initializing the ULPWU module.
EXAMPLE 4-1:
ULTRA LOW-POWER
WAKE-UP INITIALIZATION
//***************************
//Charge the capacitor on RA0
//***************************
TRISAbits.TRISA0 = 0;
PORTAbits.RA0 = 1;
for(i = 0; i < 10000; i++) Nop();
//*****************************
//Stop Charging the capacitor
//on RA0
//*****************************
TRISAbits.TRISA0 = 1;
//*****************************
//Enable the Ultra Low Power
//Wakeup module and allow
//capacitor discharge
//*****************************
WDTCONbits.ULPEN = 1;
WDTCONbits.ULPSINK = 1;
//For Sleep
OSCCONbits.IDLEN = 0;
//Enter Sleep Mode
//
Sleep();
//for sleep, execution will
//resume here
2010-2017 Microchip Technology Inc.
A timer can be used to measure the charge time and
discharge time of the capacitor. The charge time can
then be adjusted to provide the desired delay in Sleep.
This technique compensates for the affects of
temperature, voltage and component accuracy. The
peripheral can also be configured as a simple
programmable Low-Voltage Detect (LVD) or temperature
sensor.
Note:
For more information, see AN879, “Using
the Microchip Ultra Low-Power Wake-up
Module” (DS00879).
DS30009977G-page 73
PIC18F66K80 FAMILY
TABLE 4-4:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Power-Managed
Mode
Clock Source(5)
Exit Delay
Clock Ready
Status Bits
LP, XT, HS
HSPLL
PRI_IDLE mode
EC, RC
HF-INTOSC(2)
OSTS
TCSD(1)
HFIOFS
MF-INTOSC(2)
MFIOFS
LF-INTOSC
SEC_IDLE mode
SOSC
None
TCSD(1)
SOSCRUN
TCSD(1)
MFIOFS
HF-INTOSC(2)
RC_IDLE mode
MF-INTOSC(2)
HFIOFS
LF-INTOSC
Sleep mode
TOST(3)
HSPLL
TOST + trc(3)
EC, RC
TCSD(1)
HF-INTOSC(2)
MF-INTOSC(2)
LF-INTOSC
Note 1:
2:
3:
4:
5:
None
LP, XT, HS
OSTS
HFIOFS
TIOBST(4)
MFIOFS
None
TCSD (Parameter 38, Table 31-11) is a required delay when waking from Sleep and all Idle modes, and
runs concurrently with any other required delays (see Section 4.4 “Idle Modes”).
Includes postscaler derived frequencies. On Reset, INTOSC defaults to HF-INTOSC at 8 MHz.
TOST is the Oscillator Start-up Timer (Parameter 32, Table 31-11). TRC is the PLL Lock-out Timer
(Parameter F12, Table 31-7); it is also designated as TPLL.
Execution continues during TIOBST (Parameter 39, Table 31-11), the INTOSC stabilization period.
The clock source is dependent upon the settings of the SCSx (OSCCON), IRCFx (OSCCON)
and FOSCx (CONFIG1H) bits.
DS30009977G-page 74
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
5.0
RESET
The PIC18F66K80 family devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
i)
Power-on Reset (POR)
MCLR Reset during Normal Operation
MCLR Reset during Power-Managed modes
Watchdog Timer (WDT) Reset (during
execution)
Configuration Mismatch (CM) Reset
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.3.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 28.2 “Watchdog
Timer (WDT)”.
FIGURE 5-1:
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
5.1
RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the register indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the event
and must be set by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 5.7 “Reset State
of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 10.0 “Interrupts”. BOR is covered in
Section 5.4 “Brown-out Reset (BOR)”.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
POR Pulse
VDD Rise
Detect
VDD
Brown-out
Reset
BOREN
S
OST/PWRT
OST
1024 Cycles
10-Bit Ripple Counter
OSC1
32 s
INTOSC(1)
PWRT
Chip_Reset
R
Q
65.5 ms
11-Bit Ripple Counter
Enable PWRT
Enable OST(2)
Note 1:
2:
This is the INTOSC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
See Table 5-2 for time-out situations.
2010-2017 Microchip Technology Inc.
DS30009977G-page 75
PIC18F66K80 FAMILY
REGISTER 5-1:
RCON: RESET CONTROL REGISTER
R/W-0
R/W-1(1)
R/W-1
R/W-1
R-1
R-1
R/W-0(2)
R/W-0
IPEN
SBOREN
CM
RI
TO
PD
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enables priority levels on interrupts
0 = Disables priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
SBOREN: BOR Software Enable bit(1)
If BOREN = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN = 00, 10 or 11:
Bit is disabled and reads as ‘0’.
bit 5
CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has not occurred.
0 = A Configuration Mismatch Reset has occurred (must be set in software once the Reset occurs)
bit 4
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3
TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out has occurred
bit 2
PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1
POR: Power-on Reset Status bit(2)
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset has occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset has occurred (must be set in software after a Brown-out Reset occurs)
Note 1:
2:
If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and Section 5.7 “Reset State of Registers” for additional information.
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).
DS30009977G-page 76
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
5.2
Master Clear Reset (MCLR)
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR Reset path which detects and ignores small
pulses.
FIGURE 5-2:
In PIC18F66K80 family devices, the MCLR input can
be disabled with the MCLRE Configuration bit. When
MCLR is disabled, the pin becomes a digital input. See
Section 11.6 “PORTE, TRISE and LATE Registers”
for more information.
5.3
D
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k to 10 k) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (Parameter D004). For a slow rise
time, see Figure 5-2.
R
R1
MCLR
C
PIC18FXX80
Note 1:
External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode, D, helps discharge the capacitor
quickly when VDD powers down.
2:
R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3:
R1 1 k will limit any current flowing into
MCLR from external capacitor, C, in the event
of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
VDD
VDD
The MCLR pin is not driven low by any internal Resets,
including the WDT.
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON).
The state of the bit is set to ‘0’ whenever a Power-on
Reset occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘1’ in software following any Power-on Reset.
2010-2017 Microchip Technology Inc.
DS30009977G-page 77
PIC18F66K80 FAMILY
5.4
Brown-out Reset (BOR)
The PIC18F66K80 family has four BOR Power modes:
•
•
•
•
High-Power BOR
Medium Power BOR
Low-Power BOR
Zero-Power BOR
Each power mode is selected by the BORPWR
setting (CONFIG2L). For low, medium and
high-power BOR, the module monitors the VDD depending on the BORV setting (CONFIG1L). The
typical current draw (IBOR) for zero, low and medium
power BOR is 200 nA, 750 nA and 3 A, respectively. A
BOR event re-arms the Power-on Reset. It also causes
a Reset, depending on which of the trip levels has been
set: 1.8V, 2V, 2.7V or 3V.
BOR is enabled by BOREN (CONFIG2L)
and the SBOREN bit (RCON). The four BOR
configurations are summarized in Table 5-1.
In Zero-Power BOR (ZPBORMV), the module monitors
the VDD voltage and re-arms the POR at about 2V.
ZPBORMV does not cause a Reset, but re-arms the
POR.
The BOR accuracy varies with its power level. The lower
the power setting, the less accurate the BOR trip levels
are. Therefore, the high-power BOR has the highest
accuracy and the low-power BOR has the lowest accuracy. The trip levels (BVDD, Parameter D005), current
consumption (Section 31.2 “DC Characteristics:
Power-Down and Supply Current PIC18F66K80
Family (Industrial/Extended)”) and time required
below BVDD (TBOR, Parameter 35) can all be found in
Section 31.0 “Electrical Characteristics”.
5.4.1
SOFTWARE ENABLED BOR
When BOREN = 01, the BOR can be enabled or
disabled by the user in software. This is done with the
control bit, SBOREN (RCON). Setting SBOREN
enables the BOR to function as previously described.
Clearing SBOREN disables the BOR entirely. The
SBOREN bit operates only in this mode; otherwise it is
read as ‘0’.
TABLE 5-1:
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change BOR configuration. It also allows the user to
tailor device power consumption in software by eliminating the incremental current that the BOR consumes.
While the BOR current is typically very small, it may
have some impact in low-power applications.
Note:
5.4.2
Even when BOR is under software control, the Brown-out Reset voltage level is
still set by the BORV Configuration
bits; it cannot be changed in software.
DETECTING BOR
When Brown-out Reset is enabled, the BOR bit always
resets to ‘0’ on any Brown-out Reset or Power-on
Reset event. This makes it difficult to determine if a
Brown-out Reset event has occurred just by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This assumes that the POR bit is reset to ‘1’ in software
immediately after any Power-on Reset event. IF BOR
is ‘0’ while POR is ‘1’, it can be reliably assumed that a
Brown-out Reset event has occurred.
5.4.3
DISABLING BOR IN SLEEP MODE
When BOREN = 10, the BOR remains under
hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
BOR CONFIGURATIONS
BOR Configuration
BOREN1
BOREN0
Status of
SBOREN
(RCON)
0
0
Unavailable
0
1
Available
1
0
Unavailable
BOR is enabled in hardware, in Run and Idle modes; disabled during
Sleep mode.
1
1
Unavailable
BOR is enabled in hardware; must be disabled by reprogramming the
Configuration bits.
DS30009977G-page 78
BOR Operation
BOR is disabled; must be enabled by reprogramming the Configuration
bits.
BOR is enabled in software; operation is controlled by SBOREN.
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
5.5
Configuration Mismatch (CM)
The Configuration Mismatch (CM) Reset is designed to
detect, and attempt to recover from, random memory
corrupting events. These include Electrostatic
Discharge (ESD) events, which can cause widespread,
single bit changes throughout the device and result in
catastrophic failure.
In PIC18FXXKXX Flash devices, the device Configuration registers (located in the configuration memory
space) are continuously monitored during operation by
comparing their values to complimentary Shadow registers. If a mismatch is detected between the two sets
of registers, a CM Reset automatically occurs. These
events are captured by the CM bit (RCON) being
set to ‘0’.
This bit does not change for any other Reset event. A
CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT time-out or Stack Event
Resets. As with all hard and power Reset events, the
device Configuration Words are reloaded from the
Flash Configuration Words in program memory as the
device restarts.
5.6
Device Reset Timers
PIC18F66K80 family devices incorporate three separate on-chip timers that help regulate the Power-on
Reset process. Their main function is to ensure that the
device clock is stable before code is executed. These
timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
5.6.1
POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of the PIC18F66K80
family devices is an 11-bit counter which uses the
INTOSC source as the clock input. This yields an
approximate time interval of 2048 x 32 s = 65.6 ms.
While the PWRT is counting, the device is held in
Reset.
The power-up time delay depends on the INTOSC
clock and will vary from chip-to-chip due to temperature
and process variation. See DC Parameter 33 for
details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
2010-2017 Microchip Technology Inc.
DS30009977G-page 79
PIC18F66K80 FAMILY
5.6.2
OSCILLATOR START-UP TIMER
(OST)
5.6.4
On power-up, the time-out sequence is as follows:
The Oscillator Start-up Timer (OST) provides a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (Parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset or on exit
from most power-managed modes.
5.6.3
PLL LOCK TIME-OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer is
used to provide a fixed time-out that is sufficient for the
PLL to lock to the main oscillator frequency. This PLL
lock time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
TABLE 5-2:
TIME-OUT SEQUENCE
1.
2.
After the POR pulse has cleared, PWRT
time-out is invoked (if enabled).
Then, the OST is activated.
The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 5-3,
Figure 5-4, Figure 5-5, Figure 5-6 and Figure 5-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 5-3 through 5-6 also apply
to devices operating in XT or LP modes. For devices in
RC mode and with the PWRT disabled, on the other
hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately
(Figure 5-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
TIME-OUT IN VARIOUS SITUATIONS
Power-up and Brown-out
Oscillator
Configuration
HSPLL
HS, XT, LP
PWRTEN = 0
PWRTEN = 1
Exit from
Power-Managed Mode
66 ms(1) + 1024 TOSC + 2 ms(2)
1024 TOSC + 2 ms(2)
1024 TOSC + 2 ms(2)
66
ms(1)
1024 TOSC
1024 TOSC
EC, ECIO
66
ms(1)
—
—
RC, RCIO
66 ms(1)
—
—
ms(1)
—
—
INTIO1, INTIO2
Note 1:
2:
+ 1024 TOSC
66
66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2 ms is the nominal time required for the PLL to lock.
FIGURE 5-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30009977G-page 80
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
FIGURE 5-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 5-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 5-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
VDD
1V
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
2010-2017 Microchip Technology Inc.
DS30009977G-page 81
PIC18F66K80 FAMILY
FIGURE 5-7:
TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
Note:
TOST = 1024 clock cycles.
TPLL 2 ms max. First three stages of the PWRT timer.
DS30009977G-page 82
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
5.7
different Reset situations, as indicated in Table 5-3.
These bits are used in software to determine the nature
of the Reset.
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on a Power-on Reset and unchanged by all
other Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Table 5-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD,
CM, POR and BOR, are set or cleared differently in
TABLE 5-3:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program
Counter(1) SBOREN
Power-on Reset
RCON Register
CM
RI
TO
PD
STKPTR Register
POR BOR STKFUL STKUNF
0000h
1
1
1
1
1
0
0
0
0
RESET Instruction
0000h
u
(2)
u
0
u
u
u
u
u
u
Brown-out Reset
0000h
u(2)
1
1
1
1
u
0
u
u
MCLR Reset during
Power-Managed Run modes
0000h
u(2)
u
u
1
u
u
u
u
u
MCLR Reset during
Power-Managed Idle modes and
Sleep mode
0000h
u(2)
u
u
1
0
u
u
u
u
WDT Time-out during Full Power
or Power-Managed Run modes
0000h
u(2)
u
u
0
u
u
u
u
u
MCLR Reset during Full-Power
execution
0000h
u(2)
u
u
u
u
u
u
u
u
Stack Full Reset (STVREN = 1)
0000h
u(2)
u
u
u
u
u
u
1
u
Stack Underflow Reset
(STVREN = 1)
0000h
u(2)
u
u
u
u
u
u
u
1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
u(2)
u
u
u
u
u
u
u
1
WDT Time-out during
Power-Managed Idle or Sleep
modes
PC + 2
u(2)
u
u
0
0
u
u
u
u
Interrupt Exit from
Power-Managed modes
PC + 2
u(2)
u
u
u
0
u
u
u
u
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN, Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.
2010-2017 Microchip Technology Inc.
DS30009977G-page 83
PIC18F66K80 FAMILY
TABLE 5-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
TOSU
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---0 0000
---0 0000
---0 uuuu(3)
TOSH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu(3)
TOSL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu(3)
STKPTR
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
00-0 0000
uu-0 0000
uu-u uuuu(3)
PCLATU
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---0 0000
---0 0000
---u uuuu
PCLATH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
PCL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
PC + 2(2)
TBLPTRU
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
--00 0000
--00 0000
--uu uuuu
TBLPTRH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
TABLAT
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
PRODH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 000x
0000 000u
uuuu uuuu(1)
INTCON2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1111 1111
1111 -1-1
uuuu -u-u(1)
INTCON3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1100 0000
11x0 0x00
uuuu uuuu(1)
INDF0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
N/A
N/A
N/A
POSTINC0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
N/A
N/A
N/A
POSTDEC0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
N/A
N/A
N/A
PREINC0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
N/A
N/A
N/A
PLUSW0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
N/A
N/A
FSR0H
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---- xxxx
---- uuuu
---- uuuu
FSR0L
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
N/A
N/A
N/A
N/A
POSTINC1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
N/A
N/A
N/A
POSTDEC1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
N/A
N/A
N/A
PREINC1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
N/A
N/A
N/A
PLUSW1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
N/A
N/A
FSR1H
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---- xxxx
---- uuuu
---- uuuu
FSR1L
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---- 0000
---- 0000
---- uuuu
INDF2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
N/A
N/A
Legend:
Note 1:
2:
3:
4:
5:
N/A
N/A
u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
See Table 5-3 for Reset value for specific conditions.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as ‘0’.
DS30009977G-page 84
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 5-4:
Register
POSTINC2
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
N/A
N/A
N/A
POSTDEC2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
N/A
N/A
N/A
PREINC2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
N/A
N/A
N/A
PLUSW2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
N/A
N/A
N/A
FSR2H
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---- xxxx
---- uuuu
---- uuuu
FSR2L
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---x xxxx
---u uuuu
---u uuuu
TMR0H
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
uuuu uuuu
uuuu uuuu
TMR0L
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1111 1111
1111 1111
uuuu uuuu
OSCCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0110 q000
0100 00q0
uuuu uuqu
OSCCON2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-0-1 0-x0
-0-0 0-01
-u-u u-uu
WDTCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0-x0 -xx0
0-x0 -xx0
u-u0 -uu0
RCON(4)
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0111 11q0
0111 qquu
uuuu qquu
TMR1H
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
u0uu uuuu
uuuu uuuu
TMR2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
PR2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1111 1111
1111 1111
uuuu uuuu
T2CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-000 0000
-000 0000
-uuu uuuu
SSPBUF
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
SSPCON1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
SSPCON2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
ADRESH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-000 0000
-000 0000
-uuu uuuu
ADCON1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 xxxx
0000 0qqq
uuuu uuuu
ADCON2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0-00 0000
0-00 0000
u-uu uuuu
ECCP1AS
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
xxxx xxxx
CCPR1H
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
TXSTA2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0010
0000 0010
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
See Table 5-3 for Reset value for specific conditions.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as ‘0’.
2010-2017 Microchip Technology Inc.
DS30009977G-page 85
PIC18F66K80 FAMILY
TABLE 5-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
BAUDCON2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
01x0 0-00
01x0 0-00
uuuu u-uu
IPR4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1111 -111
1111 -111
uuuu -uuu
PIR4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 -000
0000 -000
uuuu -uuu
PIE4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 -000
0000 -000
uuuu -uuu
CVRCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
CMSTAT
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xx-- ----
xx-- ----
uu-- ----
TMR3H
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
T3GCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0x00
0000 0x00
uuuu u-uu
SPBRG1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
RCREG1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
TXREG1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
TXSTA1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0010
0000 0010
uuuu uuuu
RCSTA1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 000x
0000 000x
uuuu uuuu
T1GCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0x00
0000 0x00
uuuu u-uu
PR4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1111 1111
1111 1111
uuuu uuuu
HLVDCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
BAUDCON1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
01x0 0-00
01x0 0-00
uuuu u-uu
RCSTA2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 000x
0000 000x
uuuu uuuu
IPR3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
--11 111-
--11 111-
--uu uuu-
PIR3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
--00 000-
--x0 xxx-
--uu uuu-
PIE3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
--00 000-
0000 0000
uuuu uuuu
IPR2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1--- 1111
1--- 111x
u--- uuuu
PIR2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0--- 0000
0--- 000x
u--- uuuu(1)
u--- uuuu
PIE2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0--- 0000
0--- 0000
IPR1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1111 1111
1111 1111
uuuu uuuu
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-111 1111
-111 1111
-uuu uuuu
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu(1)
PIR1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-000 0000
-000 0000
-uuu uuuu
PIE1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-000 0000
-000 0000
-uuu uuuu
PSTR1CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
00-0 0001
xx-x xxxx
OSCTUNE
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
REFOCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0-00 0000
0-00 0000
u-uu uuuu
Legend:
Note 1:
2:
3:
4:
5:
—
u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
See Table 5-3 for Reset value for specific conditions.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as ‘0’.
DS30009977G-page 86
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
CCPTMRS
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---0 0000
---x xxxx
---u uuuu
TRISG
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---1 1111
---1 1111
---u uuuu
TRISF
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1111 1111
1111 1111
uuuu uuuu
TRISE
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1111 -111
1111 -111
uuuu -uuu
TRISD
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1111 1111
1111 1111
uuuu uuuu
TRISC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1111 1111
1111 1111
uuuu uuuu
TRISB
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1111 1111
1111 1111
(5)
uuuu uuuu
(5)
TRISA
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
111- 1111
ODCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
SLRCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-000 0000
-111 1111
-111 1111
LATG
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---x xxxx
---x xxxx
---u uuuu
LATF
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx -xxx
uuuu -uuu
111- 1111
(5)
uuu- uuuu(5)
LATE
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx -xxx
xxxx xxxx
uuuu uuuu
LATD
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
LATC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
LATB
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
LATA(5)
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- xxxx(5)
xxx- xxxx(5)
uuu- uuuu(5)
T4CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-000 0000
-000 0000
-uuu uuuu
TMR4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
PORTG
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---x xxxx
---x xxxx
---u uuuu
PORTF
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTE
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTD
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTB
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
PORTA
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- xxxx
EECON1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xx-0 x000
uu-0 u000
uu-u uuuu
EECON2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
SPBRGH1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
SPBRGH2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
SPBRG2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
RCREG2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
TXREG2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
IPR5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1111 1111
1111 1111
uuuu uuuu
PIR5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
(5)
uuuu uuuu
(5)
xxx- xxxx
(5)
uuu- uuuu(5)
u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
See Table 5-3 for Reset value for specific conditions.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as ‘0’.
2010-2017 Microchip Technology Inc.
DS30009977G-page 87
PIC18F66K80 FAMILY
TABLE 5-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
PIE5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
EEADRH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---- --00
---- --00
---- --00
EEADR
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
EEDATA
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
ECANCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0001 0000
0001 0000
uuuu uuuu
COMSTAT
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
CIOCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 ---0
0000 ---0
uuuu ---u
CANCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
CANSTAT
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
RXB0D7
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D6
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0DLC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx x-xx
uuuu u-uu
uuuu u-uu
RXB0SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
CM1CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0001 1111
0001 1111
uuuu uuuu
CM2CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0001 1111
0001 1111
uuuu uuuu
ANCON0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1111 1111
1111 1111
uuuu uuuu
ANCON1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-111 1111
-111 1111
-uuu uuuu
WPUB
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
1111 1111
uuuu uuuu
IOCB
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 ----
0000 ----
uuuu ----
PMD0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
See Table 5-3 for Reset value for specific conditions.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as ‘0’.
DS30009977G-page 88
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
0000 0000
0000 0000
uuuu uuuu
PMD1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
PMD2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---- 0000
---- 0000
---- uuuu
PADCFG1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 ---0
0000 ---0
uuuu ---u
CTMUCONH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0-00 0000
0-00 0000
u-uu uuuu
CTMUCONL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
CTMUICON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
CCPR2H
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCPR2L
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCP2CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
--00 0000
--00 0000
--uu uuuu
CCPR3H
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCPR3L
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCP3CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
--00 0000
--00 0000
--uu uuuu
CCPR4H
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCPR4L
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCP4CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
--00 0000
--00 0000
--uu uuuu
CCPR5H
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCPR5L
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCP5CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
--00 0000
--00 0000
--uu uuuu
PSPCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 ----
0000 ----
uuuu ----
MDCON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0010 0--0
0010 0--0
uuuu u--u
MDSRC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0--- xxxx
0--- xxxx
u--- uuuu
MDCARH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0xx- xxxx
0xx- xxxx
uuu- uuuu
MDCARL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0xx- xxxx
0xx- xxxx
uuu- uuuu
CANCON_RO0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
CANSTAT_RO0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
RXB1D7
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1D6
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1D5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1D4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1D3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1D2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1D1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1D0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
xxxx xxxx
RXB1DLC
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
See Table 5-3 for Reset value for specific conditions.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as ‘0’.
2010-2017 Microchip Technology Inc.
DS30009977G-page 89
PIC18F66K80 FAMILY
TABLE 5-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
RXB1EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx x-xx
uuuu u-uu
uuuu u-uu
RXB1SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
CANCON_RO1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
CANSTAT_RO1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
TXB0D7
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D6
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0DLC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
TXB0EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
TXB0EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
TXB0SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
xxx- x-xx
uuu- u-uu
TXB0SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
xxxx xxxx
uuuu uuuu
TXB0CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0-00
0000 0-00
uuuu u-uu
CANCON_RO2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
CANSTAT_RO2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
TXB1D7
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D6
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1DLC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
See Table 5-3 for Reset value for specific conditions.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as ‘0’.
DS30009977G-page 90
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
TXB1SIDH
PIC18F2XK80
TXB1CON
CANCON_RO3
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0-00
0000 0-00
uuuu u-uu
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
CANSTAT_RO3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
TXB2D7
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2D6
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2D5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2D4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2D3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2D2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2D1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2D0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2DLC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
TXB2SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0-00
0000 0-00
uuuu u-uu
RXM1EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXM1EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXM1SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- 0-xx
uuu- u-uu
uuu- u-uu
RXM1SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXM0EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXM0EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXM0SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- 0-xx
uuu- u-uu
uuu- u-uu
RXM0SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF5EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF5EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF5SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF5SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF4EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF4EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF4SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF4SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF3EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
See Table 5-3 for Reset value for specific conditions.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as ‘0’.
2010-2017 Microchip Technology Inc.
DS30009977G-page 91
PIC18F66K80 FAMILY
TABLE 5-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
RXF3EIDH
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
Applicable Devices
PIC18F2XK80
PIC18F4XK80
RXF3SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF3SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF2EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF2EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF2SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF2SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF1EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF1EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF1SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF1SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF0EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF0EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF0SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF0SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
CANCON_RO4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
CANSTAT_RO4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
B5D7
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B5D6
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B5D5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B5D4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B5D3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B5D2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B5D1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B5D0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B5DLC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-xxx xxxx
-uuu uuuu
uuuu uuuu
B5EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B5EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B5SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx x-xx
uuuu u-uu
uuuu u-uu
B5SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B5CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
CANCON_RO5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
CANSTAT_RO5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
B4D7
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B4D6
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
See Table 5-3 for Reset value for specific conditions.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as ‘0’.
DS30009977G-page 92
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
B4D5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B4D4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B4D3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B4D2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B4D1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B4D0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B4DLC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-xxx xxxx
-uuu uuuu
-uuu uuuu
B4EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B4EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B4SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx x-xx
uuuu u-uu
uuuu u-uu
B4SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B4CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
CANCON_RO6
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
CANSTAT_RO6
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
B3D7
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B3D6
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B3D5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B3D4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B3D3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B3D2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B3D1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B3D0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B3DLC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-xxx xxxx
-uuu uuuu
-uuu uuuu
B3EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B3EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B3SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx x-xx
uuuu u-uu
uuuu u-uu
B3SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B3CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
CANCON_RO7
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
B2D7
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B2D6
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B2D5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B2D4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B2D3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B2D2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
See Table 5-3 for Reset value for specific conditions.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as ‘0’.
2010-2017 Microchip Technology Inc.
DS30009977G-page 93
PIC18F66K80 FAMILY
TABLE 5-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
B2D1
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
Applicable Devices
PIC18F2XK80
PIC18F4XK80
B2D0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B2DLC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-xxx xxxx
-uuu uuuu
-uuu uuuu
B2EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B2EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B2SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx x-xx
uuuu u-uu
uuuu u-uu
B2SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B2CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
CANCON_RO8
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
B1D7
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B1D6
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B1D5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B1D4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B1D3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B1D2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B1D1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B1D0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B1DLC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-xxx xxxx
-uuu uuuu
-uuu uuuu
B1EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B1EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B1SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx x-xx
uuuu u-uu
uuuu u-uu
B1SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B1CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
CANCON_RO9
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
CANSTAT_RO
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
1000 0000
1000 0000
uuuu uuuu
B0D7
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B0D6
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B0D5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B0D4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B0D3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B0D2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B0D1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B0D0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B0DLC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
-xxx xxxx
-uuu uuuu
-uuu uuuu
B0EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
See Table 5-3 for Reset value for specific conditions.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as ‘0’.
DS30009977G-page 94
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
B0EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B0SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx x-xx
uuuu u-uu
uuuu u-uu
B0SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
B0CON
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
TXBIE
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---0 00--
---u uu--
---u uu--
BIE0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
BSEL0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 00--
0000 00--
uuuu uu--
MSEL3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
MSEL2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
MSEL1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0101
0000 0101
uuuu uuuu
MSEL0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0101 0000
0101 0000
uuuu uuuu
RXFBCON7
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
RXFBCON6
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
RXFBCON5
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
RXFBCON4
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
RXFBCON3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
RXFBCON2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0001 0001
0001 0001
uuuu uuuu
RXFBCON1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0001 0001
0001 0001
uuuu uuuu
RXFBCON0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
SDFLC
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
---0 0000
---0 0000
---u uuuu
RXF15EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF15EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF15SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF15SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF14EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF14EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF14SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF14SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF13EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF13EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF13SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF13SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF12EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF12EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF12SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
See Table 5-3 for Reset value for specific conditions.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as ‘0’.
2010-2017 Microchip Technology Inc.
DS30009977G-page 95
PIC18F66K80 FAMILY
TABLE 5-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on
Reset,
Brown-out
Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT
or Interrupt
RXF12SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF11EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF11EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF11SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF11SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF10EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF10EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF10SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF10SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF9EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF9EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF9SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF9SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF8EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF8EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF8SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF8SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF7EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF7EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF7SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF7SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF6EIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF6EIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF6SIDL
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF6SIDH
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXFCON0
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
RXFCON1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
BRGCON3
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
00-- -000
00-- -000
uu-- -uuu
BRGCON2
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
BRGCON1
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
TXERRCNT
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
RXERRCNT
PIC18F2XK80
PIC18F4XK80
PIC18F6XK80
0000 0000
0000 0000
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
See Table 5-3 for Reset value for specific conditions.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read as ‘0’.
DS30009977G-page 96
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
6.0
MEMORY ORGANIZATION
PIC18F66K80 family devices have these types of
memory:
• Program Memory
• Data RAM
• Data EEPROM
As Harvard architecture devices, the data and program
memories use separate busses. This enables
concurrent access of the two memory spaces.
FIGURE 6-1:
The data EEPROM, for practical purposes, can be
regarded as a peripheral device because it is
addressed and accessed through a set of control
registers.
Additional detailed information on the operation of the
Flash program memory is provided in Section 7.0
“Flash Program Memory”. The data EEPROM is
discussed separately in Section 8.0 “Data EEPROM
Memory”.
MEMORY MAPS FOR PIC18F66K80 FAMILY DEVICES
PC
CALL, CALLW, RCALL,
RETURN, RETFIE, RETLW,
ADDULNK, SUBULNK
21
Stack Level 1
Stack Level 31
PIC18FX5K80
On-Chip
Memory
PIC18FX6K80
On-Chip
Memory
000000h
007FFFh
User Memory Space
00FFFFh
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
1FFFFFh
Note:
Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.
2010-2017 Microchip Technology Inc.
DS30009977G-page 97
PIC18F66K80 FAMILY
6.1
Program Memory Organization
PIC18 microcontrollers implement a 21-bit Program
Counter (PC) that is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOP instruction).
The entire PIC18F66K80 family offers a range of
on-chip Flash program memory sizes, from 32 Kbytes
(16,384 single-word instructions) to 64 Kbytes
(32,768 single-word instructions).
• PIC18F25K80, PIC18F45K80 and PIC18F65K80 –
32 Kbytes of Flash memory, storing up to
16,384 single-word instructions
• PIC18F26K80, PIC18F46K80 and PIC18F66K80 –
64 Kbytes of Flash memory, storing up to
32,768 single-word instructions
The program memory maps for individual family
members are shown in Figure 6-1.
6.1.1
FIGURE 6-2:
HARD VECTOR FOR
PIC18F66K80 FAMILY
DEVICES
Reset Vector
0000h
High-Priority Interrupt Vector
0008h
Low-Priority Interrupt Vector
0018h
On-Chip
Program Memory
HARD MEMORY VECTORS
All PIC18 devices have a total of three hard-coded
return vectors in their program memory space. The
Reset vector address is the default value to which the
Program Counter returns on all device Resets. It is
located at 0000h.
PIC18 devices also have two interrupt vector
addresses for handling high-priority and low-priority
interrupts. The high-priority interrupt vector is located at
0008h and the low-priority interrupt vector is at 0018h.
The locations of these vectors are shown, in relation to
the program memory map, in Figure 6-2.
DS30009977G-page 98
Read ‘0’
1FFFFFh
Legend:
(Top of Memory) represents upper boundary
of on-chip program memory space (see
Figure 6-1 for device-specific values).
Shaded area represents unimplemented
memory. Areas are not shown to scale.
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
6.1.2
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and contained in three separate 8-bit registers.
The low byte, known as the PCL register, is both
readable and writable. The high byte, or PCH register,
contains the PC bits and is not directly readable
or writable. Updates to the PCH register are performed
through the PCLATH register. The upper byte is called
PCU. This register contains the PC bits; it is also
not directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred to
the Program Counter by any operation that writes PCL.
Similarly, the upper two bytes of the Program Counter
are transferred to PCLATH and PCLATU by an operation
that reads PCL. This is useful for computed offsets to the
PC (see Section 6.1.5.1 “Computed GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit (LSb) of PCL is
fixed to a value of ‘0’. The PC increments by two to
address sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the Program Counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the Program Counter.
6.1.3
RETURN ADDRESS STACK
The return address stack enables execution of any
combination of up to 31 program calls and interrupts.
The PC is pushed onto the stack when a CALL or
RCALL instruction is executed or an interrupt is
Acknowledged. The PC value is pulled off the stack on
a RETURN, RETLW or a RETFIE instruction. The value
is also pulled off the stack on ADDULNK and SUBULNK
instructions if the extended instruction set is enabled.
PCLATU and PCLATH are not affected by any of the
RETURN or CALL instructions.
FIGURE 6-3:
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
Top-of-Stack (TOS) Special Function Registers. Data
can also be pushed to, or popped from the stack, using
these registers.
A CALL type instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
6.1.3.1
Top-of-Stack Access
Only the top of the return address stack is readable and
writable. A set of three registers, TOSU:TOSH:TOSL,
holds the contents of the stack location pointed to by
the STKPTR register (Figure 6-3). This allows users to
implement a software stack, if necessary. After a CALL,
RCALL or interrupt (or ADDULNK and SUBULNK instructions, if the extended instruction set is enabled), the
software can read the pushed value by reading the
TOSU:TOSH:TOSL registers. These values can be
placed on a user-defined software stack. At return time,
the software can return these values to
TOSU:TOSH:TOSL and do a return.
While accessing the stack, users must disable the
Global Interrupt Enable bits to prevent inadvertent
stack corruption.
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
Stack Pointer
Top-of-Stack Registers
TOSU
00h
TOSH
1Ah
11111
11110
11101
TOSL
34h
Top-of-Stack
2010-2017 Microchip Technology Inc.
001A34h
000D58h
STKPTR
00010
00011
00010
00001
00000
DS30009977G-page 99
PIC18F66K80 FAMILY
6.1.3.2
Return Stack Pointer (STKPTR)
The STKPTR register (Register 6-1) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and the
STKUNF (Stack Underflow) status bits. The value of the
Stack Pointer can be 0 through 31. The Stack Pointer
increments before values are pushed onto the stack and
decrements after values are popped off of the stack. On
Reset, the Stack Pointer value will be zero.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and set the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
Note:
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
What happens when the stack becomes full depends
on the state of the STVREN (Stack Overflow Reset
Enable) Configuration bit. (For a description of the
device Configuration bits, see Section 28.1 “Configuration Bits”.) If STVREN is set (default), the 31st push
will push the (PC + 2) value onto the stack, set the
STKFUL bit and reset the device. The STKFUL bit will
remain set and the Stack Pointer will be set to zero.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.
REGISTER 6-1:
R/C-0
(1)
STKFUL
6.1.3.3
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
of the stack, without disturbing normal program execution, is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
STKPTR: STACK POINTER REGISTER
R/C-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STKUNF(1)
—
SP4
SP3
SP2
SP1
SP0
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
STKFUL: Stack Full Flag bit(1)
1 = Stack has become full or overflowed
0 = Stack has not become full or overflowed
bit 6
STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow has occurred
0 = Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP: Stack Pointer Location bits
Note 1:
x = Bit is unknown
Bit 7 and bit 6 are cleared by user software or by a POR.
DS30009977G-page 100
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
6.1.3.4
Stack Full and Underflow Resets
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit
(CONFIG4L). When STVREN is set, a full or underflow condition will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
6.1.4
FAST REGISTER STACK
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers to provide a “fast return”
option for interrupts. This stack is only one level deep
and is neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push values into the Stack registers. The values in
the registers are then loaded back into the working
registers if the RETFIE, FAST instruction is used to
return from the interrupt.
If both low and high-priority interrupts are enabled, the
Stack registers cannot be used reliably to return from
low-priority interrupts. If a high-priority interrupt occurs
while servicing a low-priority interrupt, the Stack
register values stored by the low-priority interrupt will
be overwritten. In these cases, users must save the key
registers in software during a low-priority interrupt.
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FAST instruction is then executed to restore
these registers from the Fast Register Stack.
Example 6-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
EXAMPLE 6-1:
CALL SUB1, FAST
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
RETURN FAST
SUB1
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
2010-2017 Microchip Technology Inc.
6.1.5
LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
6.1.5.1
Computed GOTO
A computed GOTO is accomplished by adding an offset
to the Program Counter. An example is shown in
Example 6-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value, ‘nn’, to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the Program Counter should advance and
should be multiples of two (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 6-2:
ORG
TABLE
6.1.5.2
MOVF
CALL
nn00h
ADDWF
RETLW
RETLW
RETLW
.
.
.
COMPUTED GOTO USING
AN OFFSET VALUE
OFFSET, W
TABLE
PCL
nnh
nnh
nnh
Table Reads
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per
program word while programming. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from the
program memory. Data is transferred from program
memory one byte at a time.
The table read operation is discussed further in
Section 7.1 “Table Reads and Table Writes”.
DS30009977G-page 101
PIC18F66K80 FAMILY
6.2
6.2.2
PIC18 Instruction Cycle
6.2.1
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction
cycle, while the decode and execute take another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction (such as GOTO) causes the Program
Counter to change, two cycles are required to complete
the instruction. (See Example 6-3.)
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the Program Counter
is incremented on every Q1, with the instruction
fetched from the program memory and latched into the
Instruction Register (IR) during Q4.
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
The instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow are shown in Figure 6-4.
FIGURE 6-4:
INSTRUCTION FLOW/PIPELINING
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle, Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
PC
PC + 2
PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC)
EXAMPLE 6-3:
1. MOVLW 55h
4. BSF
Execute INST (PC + 2)
Fetch INST (PC + 4)
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
Fetch 1
Execute 1
2. MOVWF PORTB
3. BRA
Execute INST (PC)
Fetch INST (PC + 2)
SUB_1
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
Fetch 2
TCY2
TCY3
TCY4
TCY5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush (NOP)
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30009977G-page 102
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
6.2.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instructions are stored as two or four bytes in program
memory. The Least Significant Byte (LSB) of an
instruction word is always stored in a program memory
location with an even address (LSB = 0). To maintain
alignment with instruction boundaries, the PC increments in steps of two and the LSB will always read ‘0’
(see Section 6.1.2 “Program Counter”).
Figure 6-5 shows an example of how instruction words
are stored in the program memory.
FIGURE 6-5:
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruction. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC
which accesses the desired byte address in program
memory. Instruction #2 in Figure 6-5 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. For more details on the instruction set, see
Section 29.0 “Instruction Set Summary”.
INSTRUCTIONS IN PROGRAM MEMORY
LSB = 1
LSB = 0
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Program Memory
Byte Locations
6.2.4
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
Instruction 3:
MOVFF
123h, 456h
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four, two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all cases,
the second word of the instructions always has ‘1111’ as
its four Most Significant bits (MSbs). The other 12 bits
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence, immediately after the
first word, the data in the second word is accessed and
EXAMPLE 6-4:
Word Address
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
used by the instruction sequence. If the first word is
skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 6-4 shows how this works.
Note:
For information on two-word instructions
in the extended instruction set, see
Section 6.5 “Program Memory and the
Extended Instruction Set”.
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
1100 0001 0010 0011
MOVFF
REG1, REG2 ; No, skip this word
ADDWF
REG3
; continue code
; is RAM location 0?
1111 0100 0101 0110
0010 0100 0000 0000
; is RAM location 0?
; Execute this word as a NOP
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
1100 0001 0010 0011
MOVFF
REG1, REG2 ; Yes, execute this word
ADDWF
REG3
1111 0100 0101 0110
0010 0100 0000 0000
; 2nd word of instruction
2010-2017 Microchip Technology Inc.
; continue code
DS30009977G-page 103
PIC18F66K80 FAMILY
6.3
Note:
Data Memory Organization
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 6.6 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4,096 bytes of data
memory. The memory space is divided into 16 banks
that contain 256 bytes each.
Figure 6-6 and Figure 6-7 show the data memory
organization for the devices.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
section.
To ensure that commonly used registers (select SFRs
and select GPRs) can be accessed in a single cycle,
PIC18 devices implement an Access Bank. This is a
256-byte memory space that provides fast access to
select SFRs and the lower portion of GPR Bank 0 without using the Bank Select Register. For details on the
Access RAM, see Section 6.3.2 “Access Bank”.
6.3.1
BANK SELECT REGISTER
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an
eight-bit, low-order address and a four-bit Bank Pointer.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the four Most Significant bits of
a location’s address. The instruction itself includes the
eight Least Significant bits. Only the four lower bits of
the BSR are implemented (BSR). The upper four
bits are unused and always read as ‘0’, and cannot be
written to. The BSR can be loaded directly by using the
MOVLB instruction.
The value of the BSR indicates the bank in data
memory. The eight bits in the instruction show the location in the bank and can be thought of as an offset from
the bank’s lower boundary. The relationship between
the BSR’s value and the bank division in data memory
is shown in Figure 6-7.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an eight-bit address of F9h while the
BSR is 0Fh, will end up resetting the Program Counter.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 6-6 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. When this instruction
executes, it ignores the BSR completely. All other
instructions include only the low-order address as an
operand and must use either the BSR or the Access
Bank to locate their target registers.
DS30009977G-page 104
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
FIGURE 6-6:
DATA MEMORY MAP FOR PIC18FX5K80 AND PIC18FX6K80 DEVICES
BSR
Data Memory Map
00h
= 0000
= 0001
= 0010
= 0011
= 0100
= 0101
= 0110
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
= 1111
Note 1:
Bank 0
FFh
00h
Bank 1
Access RAM
GPR
GPR
1FFh
200h
FFh
00h
Bank 2
GPR
FFh
00h
Bank 3
2FFh
300h
GPR
FFh
00h
Bank 4
6FFh
700h
GPR
Bank 7
FFh
00h
7FFh
800h
GPR
FFh
00h
Bank 9
8FFh
900h
The BSR specifies the bank
used by the instruction.
Access Bank
Access RAM Low
00h
5Fh
Access RAM High 60h
(SFRs)
FFh
GPR
9FFh
A00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
Bank 14
Bank 15
When a = 1:
3FFh
400h
5FFh
600h
FFh
00h
Bank 13
The second 160 bytes are
Special Function Registers
(from Bank 15).
GPR
Bank 6
Bank 12
The first 96 bytes are general
purpose RAM (from Bank 0).
4FFh
500h
FFh
00h
Bank 11
The BSR is ignored and the
Access Bank is used.
GPR
Bank 5
Bank 10
When a = 0:
GPR
FFh
00h
Bank 8
000h
05Fh
060h
0FFh
100h
GPR
GPR
GPR
AFFh
B00h
BFFh
C00h
CFFh
D00h
GPR
DFFh
E00h
GPR(1)
FFh
00h
GPR(1)
FFh
SFR
EFFh
F00h
F5Fh
F60h
FFFh
Addresses, E41h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
Users must always use the complete address, or load the proper BSR value, to access these
registers.
2010-2017 Microchip Technology Inc.
DS30009977G-page 105
PIC18F66K80 FAMILY
FIGURE 6-7:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
BSR(1)
7
0
0
0
0
0
0
0
Bank Select(2)
1
0
000h
Data Memory
Bank 0
100h
Bank 1
200h
300h
Bank 2
00h
7
FFh
00h
1
From Opcode(2)
1
11
1
11
1
0
11
11
FFh
00h
FFh
00h
Bank 3
through
Bank 13
E00h
Bank 14
F00h
FFFh
Note 1:
2:
6.3.2
Bank 15
FFh
00h
FFh
00h
FFh
The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR)
to the registers of the Access Bank.
The MOVFF instruction embeds the entire 12-bit address in the instruction.
ACCESS BANK
While the use of the BSR, with an embedded 8-bit
address, allows users to address the entire range of data
memory, it also means that the user must ensure that the
correct bank is selected. If not, data may be read from,
or written to, the wrong location. This can be disastrous
if a GPR is the intended target of an operation, but an
SFR is written to instead. Verifying and/or changing the
BSR for each read or write to data memory can become
very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Bank 15. The lower half is known
as the “Access RAM” and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an eight-bit address (Figure 6-6).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map. In that case, the current value of
the BSR is ignored entirely.
DS30009977G-page 106
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables.
Access RAM also allows for faster and more code
efficient context saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 6.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
6.3.3
GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
6.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
all of Bank 15 (F00h to FFFh) and the top part of
Bank 14 (EF4h to EFFh).
A list of these registers is given in Table 6-1 and
Table 6-2.
TABLE 6-1:
FFFh
Addr.
TOSU
FFEh
TOSL
FFCh
STKPTR
Name
Name
Addr.
Name
Addr.
Name
Addr.
Name
FBFh
ECCP1AS
F9Fh
IPR1
F7Fh
EECON1
F5Fh CM1CON(5)
FDEh
POSTINC2
FBEh
ECCP1DEL
F9Eh
PIR1
F7Eh
EECON2
F5Eh CM2CON(5)
FDDh
POSTDEC2(1)
FBDh
CCPR1H
F9Dh
PIE1
F7Dh SPBRGH1
F5Dh
ANCON0(5)
FBCh
CCPR1L
F9Ch
PSTR1CON
F7Ch SPBRGH2
F5Ch
ANCON1(5)
WPUB(5)
FDCh
INDF2
(1)
Addr.
(1)
FDFh
TOSH
FFDh
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
SPECIAL FUNCTION REGISTER MAP FOR PIC18F66K80 FAMILY
Name
Addr.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
(1)
PREINC2
(1)
FFBh
PCLATU
FDBh
PLUSW2
FBBh
CCP1CON
F9Bh
OSCTUNE
F7Bh
SPBRG2
F5Bh
FFAh
PCLATH
FDAh
FSR2H
FBAh
TXSTA2
F9Ah
REFOCON
F7Ah
RCREG2
F5Ah
IOCB(5)
FF9h
PCL
FD9h
FSR2L
FB9h
BAUDCON2
F99h
CCPTMRS
F79h
TXREG2
F59h
PMD0(5)
FF8h
TBLPTRU
FD8h
STATUS
FB8h
IPR4
F98h
TRISG(3)
F78h
IPR5
F58h
PMD1(5)
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
PIR4
F97h
TRISF(3)
F77h
PIR5
F57h
PMD2(5)
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
PIE4
F96h
TRISE(4)
F76h
PIE5
F56h PADCFG1(5)
(4)
F75h
EEADRH
F55h CTMUCONH(5)
FF5h
TABLAT
FD5h
T0CON
FB5h
CVRCON
F95h
TRISD
FB4h
CMSTAT
F94h
TRISC
F74h
EEADR
F54h CTMUCONL(5)
EEDATA
F53h CTMUICONH(5)
FF4h
PRODH
FD4h
—(2)
FF3h
PRODL
FD3h
OSCCON
FB3h
TMR3H
F93h
TRISB
F73h
FF2h
INTCON
FD2h
OSCCON2
FB2h
TMR3L
F92h
TRISA
F72h ECANCON
F52h
CCPR2H(5)
FF1h
INTCON2
FD1h
WDTCON
FB1h
T3CON
F91h
ODCON
F71h COMSTAT
F51h
CCPR2L(5)
FF0h
INTCON3
FD0h
RCON
FB0h
T3GCON
F90h
SLRCON
F70h
F50h CCP2CON(4,5)
CIOCON
FEFh
INDF0(1)
FCFh
TMR1H
FAFh
SPBRG1
F8Fh
LATG(3)
F6Fh
CANCON
F4Fh CCPR3H(4,5)
FEEh
POSTINC0(1)
FCEh
TMR1L
FAEh
RCREG1
F8Eh
LATF(3)
F6Eh
CANSTAT
F4Eh CCPR3L(4,5)
FEDh
POSTDEC0(1)
FCDh
T1CON
FADh
TXREG1
F8Dh
LATE(4)
F6Dh
RXB0D7
F4Dh CCP3CON(5)
(4)
F6Ch
RXB0D6
F4Ch
CCPR4H(5)
CCPR4L(5)
FECh
PREINC0
(1)
FCCh
TMR2
FACh
TXSTA1
F8Ch
FEBh
PLUSW0(1)
FCBh
PR2
FABh
RCSTA1
F8Bh
LATC
F6Bh
RXB0D5
F4Bh
FEAh
FSR0H
FCAh
T2CON
FAAh
T1GCON
F8Ah
LATB
F6Ah
RXB0D4
F4Ah CCP4CON(5)
FE9h
FSR0L
FC9h
SSPBUF
FA9h
PR4
F89h
LATA
F69h
RXB0D3
F49h
CCPR5H(5)
FE8h
WREG
FC8h
SSPADD
FA8h
HLVDCON
F88h
T4CON
F68h
RXB0D2
F48h
CCPR5L(5)
FC8h
SSPMSK
FA7h
BAUDCON1
F87h
TMR4
F67h
RXB0D1
F47h CCP5CON(5)
FE6h
POSTINC1(1)
FC7h
SSPSTAT
FA6h
RCSTA2
F86h
PORTG(3)
F66h
RXB0D0
F46h PSPCON(4,5)
FE5h
POSTDEC1(1)
FC6h
SSPCON1
FA5h
IPR3
F85h
PORTF(3)
F65h
RXB0DLC
F45h MDCON(3,5)
FE4h
PREINC1(1)
FC5h
SSPCON2
FA4h
PIR3
F84h
PORTE
F64h RXB0EIDL
F44h MDSRC(3,5)
FE3h
PLUSW1(1)
FC4h
ADRESH
FA3h
PIE3
F83h
PORTD(4)
F63h RXB0EIDH
F43h MDCARH(3,5)
FE2h
FSR1H
FC3h
ADRESL
FA2h
IPR2
F82h
PORTC
F62h RXB0SIDL
F42h MDCARL(3,5)
FE1h
FSR1L
FC2h
ADCON0
FA1h
PIR2
F81h
PORTB
F61h RXB0SIDH
F41h
—(2)
FE0h
BSR
FC1h
ADCON1
FA0h
PIE2
F80h
PORTA
F60h RXB0CON
F40h
—(2)
FC0h
ADCON2
FE7h
Note
INDF1
1:
2:
3:
4:
5:
(1)
LATD
This is not a physical register.
Unimplemented registers are read as ‘0’.
This register is only available on devices with 64 pins.
This register is not available on devices with 28 pins.
Addresses, E41h through F5Fh, are also used by the SFRs, but are not part of the Access RAM. To access these registers, users must
always load the proper BSR value.
2010-2017 Microchip Technology Inc.
DS30009977G-page 107
PIC18F66K80 FAMILY
TABLE 6-1:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F66K80 FAMILY (CONTINUED)
Name
Addr.
Addr.
F3Fh CANCON_RO0(5)
F3Eh CANSTAT_RO0(5)
Name
Addr.
Name
F0Fh CANCON_RO3(5) EDFh CANCON_RO4(5)
Name
Addr.
EAFh CANCON_RO7(5)
Name
Addr.
TXBIE(5)
Name
E4Fh RXF7EIDL(5)
E7Eh
BIE0(5)
E4Eh RXF7EIDH(5)
RXB1D7(5)
F0Dh
TXB2D7(5)
EDDh
B5D7(5)
EADh
B2D7(5)
E7Dh
BSEL0(5)
E4Dh RXF7SIDL(5)
F3Ch
RXB1D6(5)
F0Ch
TXB2D6(5)
EDCh
B5D6(5)
EACh
B2D6(5)
E7Ch
MSEL3(5)
E4Ch RXF7SIDH(5)
F3Bh
(5)
RXB1D5
F0Bh
TXB2D5
(5)
EDBh
(5)
B5D5
EABh
(5)
B2D5
E7Bh
(5)
MSEL2
E4Bh RXF6EIDL(5)
F3Ah
RXB1D4(5)
F0Ah
TXB2D4(5)
EDAh
B5D4(5)
EAAh
B2D4(5)
E7Ah
MSEL1(5)
E4Ah RXF6EIDH(5)
F39h
(5)
F09h
TXB2D3
(5)
ED9h
(5)
EA9h
(5)
E79h
(5)
F08h
TXB2D2
(5)
F07h
TXB2D1(5)
F06h
(5)
(5)
F38h
RXB1D2
F37h
RXB1D1(5)
F36h
(5)
B5D3
(5)
ED8h
B5D2
ED7h
B5D1(5)
ED6h
(5)
EAEh CANSTAT_RO7(5)
E7Fh
F3Dh
RXB1D3
F0Eh CANSTAT_RO3(5) EDEh CANSTAT_RO4(5)
Addr.
B2D3
(5)
EA8h
B2D2
EA7h
B2D1(5)
EA6h
(5)
E49h RXF6SIDL(5)
MSEL0
(5)
E48h RXF6SIDH(5)
RXFBCON6(5)
E47h RXFCON1(5)
(5)
E78h RXFBCON7
E77h
E76h RXFBCON5
E46h RXFCON0(5)
F35h
RXB1DLC(5)
F05h
TXB2DLC(5)
ED5h
B5DLC(5)
EA5h
B2DLC(5)
E75h RXFBCON4(5)
E45h BRGCON3(5)
F34h
RXB1EIDL(5)
F04h
TXB2EIDL(5)
ED4h
B5EIDL(5)
EA4h
B2EIDL(5)
E74h RXFBCON3(5)
E44h BRGCON2(5)
F33h
RXB1EIDH(5)
F03h
TXB2EIDH(5)
ED3h
B5EIDH(5)
EA3h
B2EIDH(5)
E73h RXFBCON2(5)
E43h BRGCON1(5)
F32h
RXB1SIDL(5)
F02h
TXB2SIDL(5)
ED2h
B5SIDL(5)
EA2h
B2SIDL(5)
E72h RXFBCON1(5)
E42h TXERRCNT(5)
F31h
RXB1SIDH(5)
F01h
TXB2SIDH(5)
ED1h
B5SIDH(5)
EA1h
B2SIDH(5)
RXFBCON0(5)
E41h RXERRCNT(5)
F30h
RXB1CON
(5)
F00h
TXB2CON
(5)
ED0h
(5)
EA0h
(5)
F30h
RXB1CON(5)
EFFh
RXM1EIDL(5)
ECFh CANCON_RO5(5)
E9Fh CANCON_RO8(5)
E6Fh RXF15EIDL(5)
EFEh
RXM1EIDH(5)
ECEh CANSTAT_RO5(5)
E9Eh CANSTAT_RO8(5)
E6Eh RXF15EIDH(5)
EFDh
(5)
RXB1D0
F2Fh CANCON_RO1(5)
(5)
F2Eh CANSTAT_RO1
F2Dh
TXB0D7
(5)
F2Ch
TXB0D6(5)
F2Bh
TXB2D0
RXM1SIDL
EFCh
RXM1SIDH
(5)
EFBh
RXM0EIDL(5)
TXB0D5(5)
EFAh
F2Ah
TXB0D4(5)
F29h
TXB0D3(5)
F28h
TXB0D2
(5)
F27h
TXB0D1
(5)
F26h
TXB0D0(5)
F25h
TXB0DLC
(5)
(5)
ECDh
B5D0
B5CON
(5)
B4D7
E9Dh
B2D0
E71h
B2CON
E70h
(5)
SDFLC
(5)
E6Dh RXF15SIDL(5)
(5)
B1D7
ECCh
(5)
B4D6
E9Ch
B1D6
E6Ch RXF15SIDH(5)
ECBh
B4D5(5)
E9Bh
B1D5(5)
E6Bh RXF14EIDL(5)
RXM0EIDH(5)
ECAh
B4D4(5)
E9Ah
B1D4(5)
E6Ah RXF14EIDH(5)
EF9h
RXM0SIDL(5)
EC9h
B4D3(5)
E99h
B1D3(5)
E69h RXF14SIDL(5)
EF8h
RXM0SIDH(5)
EC8h
B4D2(5)
E98h
B1D2(5)
E68h RXF14SIDH(5)
EF7h
(5)
EC7h
(5)
E97h
(5)
E67h RXF13EIDL(5)
(5)
E66h RXF13EIDH(5)
RXF5EIDL
(5)
EF6h
RXF5EIDH
EF5h
RXF5SIDL(5)
EF4h
(5)
RXF5SIDH
(5)
B4D0
EC5h
B4DLC(5)
EC4h
(5)
B4EIDL
B1D0
E95h
B1DLC(5)
E65h RXF13SIDL(5)
E94h
(5)
E64h RXF13SIDH(5)
(5)
B1EIDL
TXB0EIDL
EF3h
RXF4EIDL
EC3h
B4EIDH
E93h
B1EIDH
E63h RXF12EIDL(5)
F23h
TXB0EIDH(5)
EF2h
RXF4EIDH(5)
EC2h
B4SIDL(5)
E92h
B1SIDL(5)
E62h RXF12EIDH(5)
F22h
TXB0SIDL(5)
EF1h
RXF4SIDL(5)
EC1h
B4SIDH(5)
E91h
B1SIDH(5)
E61h RXF12SIDL(5)
F21h
TXB0SIDH(5)
EF0h
RXF4SIDH(5)
EC0h
B4CON(5)
E90h
B1CON(5)
E60h RXF12SIDH(5)
F20h
TXB0CON(5)
EEFh
RXF3EIDL(5)
EBFh CANCON_RO6(5)
E90h
B1CON(5)
E5Fh RXF11EIDL(5)
F1Fh CANCON_RO2(5) EEEh
RXF3EIDH(5)
EBEh CANSTAT_RO6(5)
E8Fh CANCON_RO9(5)
E5Eh RXF11EIDH(5)
(5)
E5Dh RXF11SIDL(5)
F1Eh CANSTAT_RO2
TXB1D7
(5)
F1Ch
TXB1D6
(5)
F1Bh
TXB1D5(5)
F1Ah
TXB1D4
(5)
F19h
TXB1D3
(5)
F18h
TXB1D2(5)
F17h
F1Dh
EEDh
EECh
RXF3SIDL
(5)
RXF3SIDH
(5)
(5)
EEBh
RXF2EIDL
EEAh
RXF2EIDH(5)
EE9h
(5)
RXF2SIDL
EE8h
RXF2SIDH
(5)
EE7h
RXF1EIDL(5)
TXB1D1(5)
EE6h
F16h
TXB1D0(5)
F15h
TXB1DLC(5)
F14h
(5)
TXB1EIDL
(5)
F13h
TXB1EIDH
F12h
TXB1SIDL(5)
F11h
(5)
TXB1SIDH
F10h
Note
TXB1CON
1:
2:
3:
4:
5:
EBDh
EBCh
(5)
E96h
B1D1
F24h
(5)
(5)
EC6h
B4D1
(5)
B3D7
(5)
B3D6
(5)
EBBh
B3D5
EBAh
B3D4(5)
EB9h
(5)
B3D3
E8Eh CANSTAT_RO9
(5)
E5Ch RXF11SIDH(5)
E8Ch
(5)
B0D6
E5Bh RXF10EIDL(5)
E8Bh
B0D5(5)
E5Ah RXF10EIDH(5)
E8Ah
(5)
E59h RXF10SIDL(5)
(5)
E8Dh
B0D7
B0D4
EB8h
(5)
B3D2
E89h
B0D3
E58h RXF10SIDH(5)
EB7h
B3D1(5)
E88h
B0D2(5)
E57h RXF9EIDL(5)
RXF1EIDH(5)
EB6h
B3D0(5)
E87h
B0D1(5)
E56h RXF9EIDH(5)
EE5h
RXF1SIDL(5)
EB5h
B3DLC(5)
E86h
B0D0(5)
E55h RXF9SIDL(5)
EE4h
RXF1SIDH(5)
EB4h
B3EIDL(5)
E85h
B0DLC(5)
E54h RXF9SIDH(5)
EE3h
(5)
EB3h
(5)
E84h
(5)
E53h RXF8EIDL(5)
E83h
(5)
B0EIDH
E52h RXF8EIDH(5)
E82h
B0SIDL(5)
E51h RXF8SIDL(5)
E81h
(5)
E50h RXF8SIDH(5)
RXF0EIDL
(5)
EE2h
RXF0EIDH
EE1h
RXF0SIDL(5)
EE0h
(5)
(5)
RXF0SIDH
B3EIDH
(5)
EB2h
B3SIDL
EB1h
B3SIDH(5)
EB0h
(5)
B3CON
E80h
B0EIDL
B0SIDH
(5)
B0CON
This is not a physical register.
Unimplemented registers are read as ‘0’.
This register is only available on devices with 64 pins.
This register is not available on devices with 28 pins.
Addresses, E41h through F5Fh, are also used by the SFRs, but are not part of the Access RAM. To access these registers, users must
always load the proper BSR value.
DS30009977G-page 108
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 6-2:
Addr.
PIC18F66K80 FAMILY REGISTER FILE SUMMARY
File Name
Bit 7
Bit 6
Bit 5
—
—
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
on page
FFFh
TOSU
FFEh
TOSH
Top-of-Stack High Byte (TOS)
FFDh
TOSL
Top-of-Stack Low Byte (TOS)
FFCh
STKPTR
STKFUL
STKUNF
—
FFBh
PCLATU
—
—
Bit 21
FFAh
PCLATH
Holding Register for PC
FF9h
PCL
PC Low Byte (PC)
FF8h
TBLPTRU
FF7h
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR)
84
FF6h
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR)
84
FF5h
TABLAT
Program Memory Table Latch
84
FF4h
PRODH
Product Register High Byte
84
FF3h
PRODL
Product Register Low Byte
FF2h
INTCON
—
—
Top-of-Stack Upper Byte (TOS)
84
84
84
SP4
SP3
SP2
SP1
SP0
Holding Register for PC
84
84
84
84
Bit 21
Program Memory Table Pointer Upper Byte (TBLPTR)
84
84
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
84
FF1h
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
84
FF0h
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
84
FEFh
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
84
FEEh
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
84
FEDh
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
84
FECh
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
84
FEBh
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
84
FEAh
FSR0H
FE9h
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
84
FE8h
WREG
Working Register
84
FE7h
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
84
FE6h
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
84
FE5h
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
84
FE4h
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
84
FE3h
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
84
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
84
FE2h
FSR1H
FE1h
FSR1L
FE0h
BSR
FDFh
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
84
FDEh
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
85
FDDh
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
85
FDCh
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
85
FDBh
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
85
FDAh
FSR2H
FD9h
FSR2L
FD8h
STATUS
FD7h
TMR0H
Timer0 Register High Byte
FD6h
TMR0L
Timer0 Register Low Byte
FD5h
T0CON
FD4h
Unimplemented
FD3h
OSCCON
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
—
—
—
—
—
84
Bank Select Register
84
Indirect Data Memory Address Pointer 2 High Byte
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
84
85
85
OV
Z
DC
C
85
85
85
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
85
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
HFIOFS
SCS1
SCS0
85
—
FD2h
OSCCON2
—
SOSCRUN
—
SOSCDRV
SOSCGO
—
MFIOFS
MFIOSEL
85
FD1h
WDTCON
REGSLP
—
ULPLVL
SRETEN
—
ULPEN
ULPSINK
SWDTEN
85
FD0h
RCON
IPEN
SBOREN
CM
RI
TO
PD
POR
BOR
85
2010-2017 Microchip Technology Inc.
DS30009977G-page 109
PIC18F66K80 FAMILY
TABLE 6-2:
Addr.
PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
on page
FCFh
TMR1H
Timer1 Register High Byte
85
FCEh
TMR1L
Timer1 Register Low Bytes
85
FCDh
T1CON
FCCh
TMR2
Timer2 Register
TMR1CS1
FCBh
PR2
Timer2 Period Register
FCAh
T2CON
FC9h
SSPBUF
MSSP Receive Buffer/Transmit Register
85
FC8h
SSPADD
MSSP Address Register (I2C™ Slave Mode), MSSP Baud Rate Reload Register (I2C Master Mode)
85
—
TMR1CS0
T1CKPS1
T1CKPS0
SOSCEN
T1SYNC
RD16
TMR1ON
85
85
85
T2OUTPS3
T2OUTPS2
T2OUTPS1
T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
85
FC8h
SSPMSK
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
85
FC7h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
85
FC6h
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
85
FC5h
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
85
FC4h
ADRESH
A/D Result Register High Byte
FC3h
ADRESL
A/D Result Register Low Byte
FC2h
ADCON0
—
CHS4
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
FC1h
ADCON1
TRIGSEL1
TRIGSEL0
VCFG1
VCFG0
VNCFG
CHSN2
CHSN1
CHSN0
85
FC0h
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
85
ECCP1AS1
ECCP1AS0
PSS1AC1
PSS1AC0
PSS1BD1
PSS1BD0
85
P1DC5
P1DC4
P1DC3
P1DC2
P1DC1
P1DC0
85
ECCP1ASE ECCP1AS2
85
85
85
FBFh
ECCP1AS
FBEh
ECCP1DEL
FBDh
CCPR1H
Capture/Compare/PWM Register 1 High Byte
FBCh
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
FBBh
CCP1CON
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
85
FBAh
TXSTA2
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
85
FB9h
BAUDCON2
ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
85
FB8h
IPR4
TMR4IP
EEIP
CMP2IP
CMP1IP
—
CCP5IP
CCP4IP
CCP3IP
85
FB7h
PIR4
TMR4IF
EEIF
CMP2IF
CMP1IF
—
CCP5IF
CCP4IF
CCP3IF
85
FB6h
PIE4
TMR4IE
EEIE
CMP2IE
CMP1IE
—
CCP5IE
CCP4IE
CCP3IE
85
FB5h
CVRCON
CVREN
CVROE
CVRSS
CVR4
CVR3
CVR2
CVR1
CVR0
85
CMP2OUT
CMP1OUT
—
—
—
—
—
—
P1RSEN
P1DC6
85
85
FB4h
CMSTAT
FB3h
TMR3H
Timer3 Register High Byte
FB2h
TMR3L
Timer3 Register Low Bytes
FB1h
T3CON
TMR3CS1
TMR3CS0
T3CKPS1
T3CKPS0
SOSCEN
T3SYNC
RD16
TMR3ON
85
FB0h
T3GCON
TMR3GE
T3GPOL
T3GTM
T3GSPM
T3GGO/
T3DONE
T3GVAL
T3GSS1
T3GSS0
85
85
85
85
FAFh
SPBRG1
EUSART1 Baud Rate Generator Register Low Byte
85
FAEh
RCREG1
EUSART1 Receive Register
85
FADh
TXREG1
EUSART1 Transmit Register
FACh
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
85
FABh
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
85
FAAh
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
T1DONE
T1GVAL
T1GSS1
T1GSS0
85
FA9h
PR4
FA8h
HLVDCON
VDIRMAG
BGVST
IRVST
HLVDEN
HLVDL3
HLVDL2
HLVDL1
HLVDL0
85
FA7h
BAUDCON1
ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
85
FA6h
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
85
FA5h
IPR3
—
—
RC2IP
TX2IP
CTMUIP
CCP2IP
CCP1IP
—
85
FA4h
PIR3
—
—
RC2IF
TX2IF
CTMUIF
CCP2IF
CCP1IF
—
85
FA3h
PIE3
—
—
RC2IE
TX2IE
CTMUIE
CCP2IE
CCP1IE
—
85
FA2h
IPR2
OSCFIP
—
—
—
BCLIP
HLVDIP
TMR3IP
TMR3GIP
85
85
Timer4 Period Register
85
FA1h
PIR2
OSCFIF
—
—
—
BCLIF
HLVDIF
TMR3IF
TMR3GIF
85
FA0h
PIE2
OSCFIE
—
—
—
BCLIE
HLVDIE
TMR3IE
TMR3GIE
85
DS30009977G-page 110
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 6-2:
Addr.
File Name
PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
on page
F9Fh
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
TMR1GIP
TMR2IP
TMR1IP
86
F9Eh
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
TMR1GIF
TMR2IF
TMR1IF
85
F9Dh
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
TMR1GIE
TMR2IE
TMR1IE
85
F9Ch
PSTR1CON
CMPL1
CMPL0
—
STRSYNC
STRD
STRC
STRB
STRA
85
F9Bh
OSCTUNE
INTSRC
PLLEN
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
86
F9Ah
REFOCON
ROON
—
ROSSLP
ROSEL
RODIV3
RODIV2
RODIV1
RODIV0
86
F99h
CCPTMRS
—
—
—
C5TSEL
C4TSEL
C3TSEL
C2TSEL
C1TSEL
86
86
F98h
TRISG
—
—
—
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
F97h
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
86
F96h
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
—
TRISE2
TRISE1
TRISE0
86
F95h
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
86
F94h
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
86
F93h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
86
F92h
TRISA
TRISA7
TRISA6
TRISA5
—
TRISA3
TRISA2
TRISA1
TRISA0
86
F91h
ODCON
SSPOD
CCP5OD
CCP4OD
CCP3OD
CCP2OD
CCP1OD
U2OD
U1OD
86
F90h
SLRCON
—
SLRG
SLRF
SLRE
SLRD
SLRC
SLRB
SLRA
86
F8Fh
LATG
—
—
—
LATG4
LATG3
LATG2
LATG1
LATG0
86
F8Eh
LATF
LATF7
LATF6
LATF5
LATF4
—
LATF2
LATF1
LATF0
86
F8Dh
LATE
LATE7
LATE6
LATE5
LATE4
—
LATE2
LATE1
LATE0
86
F8Ch
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
86
F8Bh
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
86
F8Ah
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
86
F89h
LATA
LATA7
LATA6
LATA5
—
LATA3
LATA2
LATA1
LATA0
86
F88h
T4CON
—
T4OUTPS3
T4OUTPS2
T4OUTPS1
T4OUTPS0
TMR4ON
T4CKPS1
T4CKPS0
86
F87h
TMR4
F86h
PORTG
—
RG4
RG3
RG2
RG1
RG0
86
F85h
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
86
F84h
PORTE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
86
F83h
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
86
F82h
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
86
F81h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
86
F80h
PORTA
RA7
RA6
RA5
—
RA3
RA2
RA1
RA0
86
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
86
Timer4 Register
86
—
—
F7Fh
EECON1
F7Eh
EECON2
Flash Self-Program Control Register (not a physical register)
86
F7Dh
SPBRGH1
EUSART1 Baud Rate Generator Register High Byte
86
F7Ch
SPBRGH2
EUSART2 Baud Rate Generator Register High Byte
86
F7Bh
SPBRG2
EUSART2 Baud Rate Generator Register Low Byte
86
F7Ah
RCREG2
EUSART2 Receive Register
86
F79h
TXREG2
EUSART2 Transmit Register
F78h
IPR5
IRXIP
WAKIP
ERRIP
TX2BIP
TXB1IP
TXB0IP
RXB1IP
RXB0IP
87
F77h
PIR5
IRXIF
WAKIF
ERRIF
TXB2IF
TXB1IF
TXB0IF
RXB1IF
RXB0IF
87
F76H
PIE5
IRXIE
WAKIE
ERRIE
TX2BIE
TXB1IE
TXB0IE
RXB1IE
RXB0IE
87
F75h
EEADRH
Data EE Address Register High Byte
87
F74h
EEADR
Data EE Address Register Low Byte
87
F73h
EEDATA
Data EE Data Register
F72h
ECANCON
F71h
COMSTAT
F70h
CIOCON
TX2SRC
F6Fh
CANCON
F6Eh
CANSTAT
MDSEL1
MDSEL0
87
87
FIFOWM
EWIN4
EWIN3
EWIN2
EWIN1
EWIN0
87
TXBO
TXBP
RXBP
TXWARN
RXWARN
EWARN
87
TX2EN
ENDRHI
CANCAP
—
—
—
CLKSEL
87
REQOP2
REQOP1
REQOP0
ABAT
WIN2/FP3
WIN1/FP2
WIN0/FP1
FP0
87
OPMODE2
OPMODE1
OPMODE0
—/
EICOD4
ICODE2/
EICODE3
ICODE1/
EICODE2
ICODE0/
EICODE1
—/
EICODE0
87
RXB0OVFL RXB1OVFL
2010-2017 Microchip Technology Inc.
DS30009977G-page 111
PIC18F66K80 FAMILY
TABLE 6-2:
Addr.
PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
on page
F6Dh
RXB0D7
RXB0D77
RXB0D76
RXB0D75
RXB0D74
RXB0D73
RXB0D72
RXB0D71
RXB0D70
87
F6Ch
RXB0D6
RXB0D67
RXB0D66
RXB0D65
RXB0D64
RXB0D63
RXB0D62
RXB0D61
RXB0D60
87
F6Bh
RXB0D5
RXB0D57
RXB0D56
RXB0D55
RXB0D54
RXB0D53
RXB0D52
RXB0D51
RXB0D50
87
F6Ah
RXB0D4
RXB0D47
RXB0D46
RXB0D45
RXB0D44
RXB0D43
RXB0D42
RXB0D41
RXB0D40
87
F69h
RXB0D3
RXB0D37
RXB0D36
RXB0D35
RXB0D34
RXB0D33
RXB0D32
RXB0D31
RXB0D30
87
F68h
RXB0D2
RXB0D27
RXB0D26
RXB0D25
RXB0D24
RXB0D23
RXB0D22
RXB0D21
RXB0D20
87
F67h
RXB0D1
RXB0D17
RXB0D16
RXB0D15
RXB0D14
RXB0D13
RXB0D12
RXB0D11
RXB0D10
87
F66h
RXB0D0
RXB0D07
RXB0D06
RXB0D05
RXB0D04
RXB0D03
RXB0D02
RXB0D01
RXB0D00
87
F65h
RXB0DLC
—
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
87
F64h
RXB0EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
87
F63h
RXB0EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
87
F62h
RXB0SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
87
F61h
RXB0SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
87
F60h
RXB0CON
RXFUL
RXM1
RXM0
—
RXRTRRO
RXB0DBEN
JTOFF
FILHIT0
87
F60h
RXB0CON
RXFUL
RXM1
RTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
87
F5Fh
CM1CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
87
F5Eh
CM2CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
87
F5Dh
ANCON0
ANSEL7
ANSEL6
ANSEL5
ANSEL4
ANSEL3
ANSEL2
ANSEL1
ANSEL0
87
F5Ch
ANCON1
—
ANSEL14
ANSEL13
ANSEL12
ANSEL11
ANSEL10
ANSEL9
ANSEL8
87
F5Bh
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
87
F5Ah
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
—
—
—
—
87
F59h
PMD0
CCP5MD
CCP4MD
CCP3MD
CCP2MD
CCP1MD
UART2MD
UART1MD
SSPMD
87
F58h
PMD1
PSPMD
CTMUMD
ADCMD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
TMR0MD
89
F57h
PMD2
—
—
—
—
MODMD
ECANMD
CMP2MD
CMP1MD
89
F56h
PADCFG1
RDPU
REPU
RFPU
RGPU
—
—
—
CTMUDS
89
F55h
CTMUCONH
CTMUEN
—
CTMUSIDL
TGEN
EDGEN
EDGSEQEN
IDISSEN
CTTRIG
89
F54h
CTMUCONL
EDG2POL
EDG2SEL1
EDG2SEL0
EDG1POL
EDG1SEL1
EDG1SEL0
EDG2STAT
EDG1STAT
89
F53h
CTMUICON
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
IRNG1
IRNG0
89
F52h
CCPR2H
Capture/Compare/PWM Register 2 High Byte
F51h
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
F50h
CCP2CON
—
—
DC2B1
89
89
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
89
F4Fh
CCPR3H
Capture/Compare/PWM Register 3 High Byte
F4Eh
CCPR3L
Capture/Compare/PWM Register 3 Low Byte
F4Dh
CCP3CON
F4Ch
CCPR4H
Capture/Compare/PWM Register 4 High Byte
F4Bh
CCPR4L
Capture/Compare/PWM Register 4 Low Byte
F4Ah
CCP4CON
F49H
CCPR5H
Capture/Compare/PWM Register 5 High Byte
F48h
CCPR5L
Capture/Compare/PWM Register 5 Low Byte
F47h
CCP5CON
—
—
DC5B1
DC5B0
CCP5M3
CCP5M2
CCP5M1
CCP5M0
89
F46h
PSPCON
IBF
OBF
IBOV
PSPMODE
—
—
—
—
89
—
—
—
—
89
89
DC3B1
D32B0
DC4B1
CCP3M3
CCP3M2
CCP3M1
CCP3M0
89
89
89
DC4B0
CCP4M3
CCP4M2
CCP4M1
CCP4M0
89
89
89
F45h
MDCON
MDEN
MDOE
MDSLR
MDOPOL
MDO
—
—
MDBIT
89
F44h
MDSRC
MDSODIS
—
—
—
MDSRC3
MDSRC2
MDSRC1
MDSRC0
89
F43h
MDCARH
MDCHODIS MDCHPOL
MDCHSYNC
—
MDCH3
MDCH2
MDCH1
MDCH0
89
F42h
MDCARL
MDCLODIS
MDCLSYNC
—
MDCL3
MDCL2
MDCL1
MDCL0
89
F41h
Unimplemented
F40h
Unimplemented
F3Fh
CANCON_RO0
CANCON_RO0
F3Eh
CANSTAT_RO0
CANSTAT_RO0
F3Dh
RXB1D7
RXB1D77
RXB1D76
RXB1D75
RXB1D74
RXB1D73
RXB1D72
RXB1D71
RXB1D70
89
F3Ch
RXB1D6
RXB1D67
RXB1D66
RXB1D65
RXB1D64
RXB1D63
RXB1D62
RXB1D61
RXB1D60
89
MDCLPOL
—
—
DS30009977G-page 112
89
89
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 6-2:
Addr.
PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
on page
F3Bh
RXB1D5
RXB1D57
RXB1D56
RXB1D55
RXB1D54
RXB1D53
RXB1D52
RXB1D51
RXB1D50
89
F3Ah
RXB1D4
RXB1D47
RXB1D46
RXB1D45
RXB1D44
RXB1D43
RXB1D42
RXB1D41
RXB1D40
89
F39h
RXB1D3
RXB1D37
RXB1D36
RXB1D35
RXB1D34
RXB1D33
RXB1D32
RXB1D31
RXB1D30
89
F38h
RXB1D2
RXB1D27
RXB1D26
RXB1D25
RXB1D24
RXB1D23
RXB1D22
RXB1D21
RXB1D20
89
F37h
RXB1D1
RXB1D17
RXB1D16
RXB1D15
RXB1D14
RXB1D13
RXB1D12
RXB1D11
RXB1D10
89
F36h
RXB1D0
RXB1D07
RXB1D06
RXB1D05
RXB1D04
RXB1D03
RXB1D02
RXB1D01
RXB1D00
89
F35h
RXB1DLC
—
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
89
F34h
RXB1EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
90
F33h
RXB1EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
90
F32h
RXB1SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
90
F31h
RXB1SIDH
SID10
SID9
SID8
SID7
SID6
SID5
F30h
RXB1CON
RXFUL
RXM1
RXM0
—
F30h
RXB1CON
RXFUL
RXM1
RTRRO
FILHIT4
F2Fh
CANCON_RO1
CANCON_RO1
F2Eh
CANSTAT_RO1
CANSTAT_RO1
F2Dh
TXB0D7
TXB0D77
TXB0D76
TXB0D75
TXB0D74
TXB0D73
TXB0D72
TXB0D71
TXB0D70
90
F2Ch
TXB0D6
TXB0D67
TXB0D66
TXB0D65
TXB0D64
TXB0D63
TXB0D62
TXB0D61
TXB0D60
90
F2Bh
TXB0D5
TXB0D57
TXB0D56
TXB0D55
TXB0D54
TXB0D53
TXB0D52
TXB0D51
TXB0D50
90
F2Ah
TXB0D4
TXB0D47
TXB0D46
TXB0D45
TXB0D44
TXB0D43
TXB0D42
TXB0D41
TXB0D40
90
F29h
TXB0D3
TXB0D37
TXB0D36
TXB0D35
TXB0D34
TXB0D33
TXB0D32
TXB0D31
TXB0D30
90
F28h
TXB0D2
TXB0D27
TXB0D26
TXB0D25
TXB0D24
TXB0D23
TXB0D22
TXB0D21
TXB0D20
90
F27h
TXB0D1
TXB0D17
TXB0D16
TXB0D15
TXB0D14
TXB0D13
TXB0D12
TXB0D11
TXB0D10
90
F26h
TXB0D0
TXB0D07
TXB0D06
TXB0D05
TXB0D04
TXB0D03
TXB0D02
TXB0D01
TXB0D00
90
F25h
TXB0DLC
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
90
F24h
TXB0EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
90
F23h
TXB0EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
90
F22h
TXB0SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
90
F21h
TXB0SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
90
F20h
TXB0CON
TXBIF
TXABT
TXLARB
TXERR
TXREQ
—
TXPRI1
TXPRI0
90
F1Fh
CANCON_RO2
CANCON_RO2
F1Eh
CANSTAT_RO2
CANSTAT_RO2
F1Dh
TXB1D7
TXB1D77
TXB1D76
TXB1D75
TXB1D74
TXB1D73
TXB1D72
TXB1D71
TXB1D70
90
F1Ch
TXB1D6
TXB1D67
TXB1D66
TXB1D65
TXB1D64
TXB1D63
TXB1D62
TXB1D61
TXB1D60
90
F1Bh
TXB1D5
TXB1D57
TXB1D56
TXB1D55
TXB1D54
TXB1D53
TXB1D52
TXB1D51
TXB1D50
90
F1Ah
TXB1D4
TXB1D47
TXB1D46
TXB1D45
TXB1D44
TXB1D43
TXB1D42
TXB1D41
TXB1D40
90
F19h
TXB1D3
TXB1D37
TXB1D36
TXB1D35
TXB1D34
TXB1D33
TXB1D32
TXB1D31
TXB1D30
90
F18h
TXB1D2
TXB1D27
TXB1D26
TXB1D25
TXB1D24
TXB1D23
TXB1D22
TXB1D21
TXB1D20
90
F17h
TXB1D1
TXB1D17
TXB1D16
TXB1D15
TXB1D14
TXB1D13
TXB1D12
TXB1D11
TXB1D10
90
F16h
TXB1D0
TXB1D07
TXB1D06
TXB1D05
TXB1D04
TXB1D03
TXB1D02
TXB1D01
TXB1D00
90
F15h
TXB1DLC
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
90
F14h
TXB1EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
90
F13h
TXB1EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
90
F12h
TXB1SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
90
F11h
TXB1SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
90
F10h
TXB1CON
TXBIF
TXABT
TXLARB
TXERR
TXREQ
—
TXPRI1
TXPRI0
90
F0Fh
CANCON_RO3
CANCON_RO3
F0Eh
CANSTAT_RO3
CANSTAT_RO3
F0Dh
TXB2D7
TXB2D77
TXB2D76
TXB2D75
TXB2D74
TXB2D73
TXB2D72
TXB2D71
TXB2D70
90
F0Ch
TXB2D6
TXB2D67
TXB2D66
TXB2D65
TXB2D64
TXB2D63
TXB2D62
TXB2D61
TXB2D60
91
F0Bh
TXB2D5
TXB2D57
TXB2D56
TXB2D55
TXB2D54
TXB2D53
TXB2D52
TXB2D51
TXB2D50
91
F0Ah
TXB2D4
TXB2D47
TXB2D46
TXB2D45
TXB2D44
TXB2D43
TXB2D42
TXB2D41
TXB2D40
—
RXRTRRO RXBODBEN
FILHIT3
FILHIT2
SID4
SID3
90
JTOFF
FILHIT0
90
FILHIT1
FILHIT0
90
90
90
90
90
2010-2017 Microchip Technology Inc.
90
90
DS30009977G-page 113
PIC18F66K80 FAMILY
TABLE 6-2:
Addr.
PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
on page
F09h
TXB2D3
TXB2D37
TXB2D36
TXB2D35
TXB2D34
TXB2D33
TXB2D32
TXB2D31
TXB2D30
91
F08h
TXB2D2
TXB2D27
TXB2D26
TXB2D25
TXB2D24
TXB2D23
TXB2D22
TXB2D21
TXB2D20
91
F07h
TXB2D1
TXB2D17
TXB2D16
TXB2D15
TXB2D14
TXB2D13
TXB2D12
TXB2D11
TXB2D10
91
F06h
TXB2D0
TXB2D07
TXB2D06
TXB2D05
TXB2D04
TXB2D03
TXB2D02
TXB2D01
TXB2D00
91
F05h
TXB2DLC
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
91
F04h
TXB2EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
91
F03h
TXB2EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
91
F02h
TXB2SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
91
F01h
TXB2SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
91
F00h
TXB2CON
TXBIF
TXABT
TXLARB
TXERR
TXREQ
—
TXPRI1
TXPRI0
91
EFFh
RXM1EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
91
EFEh
RXM1EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
91
EFDh
RXM1SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
91
EFCh
RXM1SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
91
EFBh
RXM0EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
91
EFAh
RXM0EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
91
EF9h
RXM0SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
91
EF8h
RXM0SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
91
EF7h
RXF5EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
91
EF6h
RXF5EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
91
EF5h
RXF5SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
91
EF4h
RXF5SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
91
EF3h
RXF4EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
91
EF2h
RXF4EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
91
EF1h
RXF4SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
91
EF0h
RXF4SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
91
EEFh
RXF3EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
91
EEEh
RXF3EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
91
EEDh
RXF3SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
91
EECh
RXF3SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
91
EEBh
RXF2EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
91
EEAh
RXF2EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
91
EE9h
RXF2SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
91
EE8h
RXF2SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
91
EE7h
RXF1EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
91
EE6h
RXF1EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
91
EE5h
RXF1SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
91
EE4h
RXF1SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
91
EE3h
RXF0EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
91
EE2h
RXF0EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
91
EE1h
RXF0SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
91
EE0h
RXF0SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
91
EDFh
CANCON_RO4
CANCON_RO4
EDEh
CANSTAT_RO4
CANSTAT_RO4
EDDh
B5D7
B5D77
B5D76
B5D75
B5D74
B5D73
B5D72
B5D71
B5D70
91
EDCh
B5D6
B5D67
B5D66
B5D65
B5D64
B5D63
B5D62
B5D61
B5D60
91
EDBh
B5D5
B5D57
B5D56
B5D55
B5D54
B5D53
B5D52
B5D51
B5D50
91
EDAh
B5D4
B5D47
B5D46
B5D45
B5D44
B5D43
B5D42
B5D41
B5D40
91
ED9h
B5D3
B5D37
B5D36
B5D35
B5D34
B5D33
B5D32
B5D31
B5D30
91
ED8h
B5D2
B5D27
B5D26
B5D25
B5D24
B5D23
B5D22
B5D21
B5D20
91
ED7h
B5D1
B5D17
B5D16
B5D15
B5D14
B5D13
B5D12
B5D11
B5D10
91
DS30009977G-page 114
91
91
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 6-2:
Addr.
PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
on page
ED6h
B5D0
B5D07
B5D06
B5D05
B5D04
B5D03
B5D02
B5D01
B5D00
91
ED5h
B5DLC
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
91
ED4h
B5EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
91
ED3h
B5EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
91
ED2h
B5SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
91
ED1h
B5SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
91
ED0h
B5CON
TXBIF
TXABT
TXLARB
TXERR
TXREQ
—
TXPRI1
TXPRI0
91
ECFh
CANCON_RO5
CANCON_RO5
ECEh
CANSTAT_RO5
CANSTAT_RO5
ECDh
B4D7
B4D77
B4D76
B4D75
B4D74
B4D73
B4D72
B4D71
B4D70
92
ECCh
B4D6
B4D67
B4D66
B4D65
B4D64
B4D63
B4D62
B4D61
B4D60
92
ECBh
B4D5
B4D57
B4D56
B4D55
B4D54
B4D53
B4D52
B4D51
B4D50
92
ECAh
B4D4
B4D47
B4D46
B4D45
B4D44
B4D43
B4D42
B4D41
B4D40
92
EC9h
B4D3
B4D37
B4D36
B4D35
B4D34
B4D33
B4D32
B4D31
B4D30
92
EC8h
B4D2
B4D27
B4D26
B4D25
B4D24
B4D23
B4D22
B4D21
B4D20
92
EC7h
B4D1
B4D17
B4D16
B4D15
B4D14
B4D13
B4D12
B4D11
B4D10
92
EC6h
B4D0
B4D07
B4D06
B4D05
B4D04
B4D03
B4D02
B4D01
B4D00
92
EC5h
B4DLC
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
92
EC4h
B4EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
92
EC3h
B4EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
92
EC2h
B4SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
92
91
92
EC1h
B4SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
92
EC0h
B4CON
TXBIF
TXABT
TXLARB
TXERR
TXREQ
—
TXPRI1
TXPRI0
92
EBFh
CANCON_RO6
CANCON_RO6
EBEh
CANSTAT_RO6
CANSTAT_RO6
EBDh
B3D7
B3D77
B3D76
B3D75
B3D73
B3D73
B3D72
B3D71
B3D70
92
EBCh
B3D6
B3D67
B3D66
B3D65
B3D63
B3D63
B3D62
B3D61
B3D60
92
EBBh
B3D5
B3D57
B3D56
B3D55
B3D53
B3D53
B3D52
B3D51
B3D50
92
EBAh
B3D4
B3D47
B3D46
B3D45
B3D43
B3D43
B3D42
B3D41
B3D40
92
EB9h
B3D3
B3D37
B3D36
B3D35
B3D33
B3D33
B3D32
B3D31
B3D30
92
EB8h
B3D2
B3D27
B3D26
B3D25
B3D23
B3D23
B3D22
B3D21
B3D20
92
EB7h
B3D1
B3D17
B3D16
B3D15
B3D13
B3D13
B3D12
B3D11
B3D10
92
EB6h
B3D0
B3D07
B3D06
B3D05
B3D03
B3D03
B3D02
B3D01
B3D00
92
EB5h
B3DLC
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
92
EB4h
B3EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
92
EB3h
B3EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
92
EB2h
B3SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
92
EB1h
B3SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
92
EB0h
B3CON
TXBIF
TXABT
TXLARB
TXERR
TXREQ
—
TXPRI1
TXPRI0
92
EAFh
CANCON_RO7
CANCON_RO7
EAEh
CANSTAT_RO7
CANSTAT_RO7
EADh
B2D7
B2D77
B2D76
B2D75
B2D72
B2D73
B2D72
B2D71
B2D70
92
EACh
B2D6
B2D67
B2D66
B2D65
B2D62
B2D63
B2D62
B2D61
B2D60
92
EABh
B2D5
B2D57
B2D56
B2D55
B2D52
B2D53
B2D52
B2D51
B2D50
93
EAAh
B2D4
B2D47
B2D46
B2D45
B2D42
B2D43
B2D42
B2D41
B2D40
93
EA9h
B2D3
B2D37
B2D36
B2D35
B2D32
B2D33
B2D32
B2D31
B2D30
93
EA8h
B2D2
B2D27
B2D26
B2D25
B2D22
B2D23
B2D22
B2D21
B2D20
93
EA7h
B2D1
B2D17
B2D16
B2D15
B2D12
B2D13
B2D12
B2D11
B2D10
93
EA6h
B2D0
B2D07
B2D06
B2D05
B2D02
B2D03
B2D02
B2D01
B2D00
93
EA5h
B2DLC
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
93
EA4h
B2EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
93
92
92
92
92
2010-2017 Microchip Technology Inc.
DS30009977G-page 115
PIC18F66K80 FAMILY
TABLE 6-2:
Addr.
PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
on page
EA3h
B2EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
93
EA2h
B2SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
93
EA1h
B2SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
93
EA0h
B2CON
TXBIF
TXABT
TXLARB
TXERR
TXREQ
—
TXPRI1
TXPRI0
93
E9Fh
CANCON_RO8
CANCON_RO8
E9Eh
CANSTAT_RO8
CANSTAT_RO8
E9Dh
B1D7
B1D77
B1D76
B1D75
B1D71
B1D73
B1D72
B1D71
B1D70
93
E9Ch
B1D6
B1D67
B1D66
B1D65
B1D61
B1D63
B1D62
B1D61
B1D60
93
E9Bh
B1D5
B1D57
B1D56
B1D55
B1D51
B1D53
B1D52
B1D51
B1D50
93
E9Ah
B1D4
B1D47
B1D46
B1D45
B1D41
B1D43
B1D42
B1D41
B1D40
93
E99h
B1D3
B1D37
B1D36
B1D35
B1D31
B1D33
B1D32
B1D31
B1D30
93
E98h
B1D2
B1D27
B1D26
B1D25
B1D21
B1D23
B1D22
B1D21
B1D20
93
E97h
B1D1
B1D17
B1D16
B1D15
B1D11
B1D13
B1D12
B1D11
B1D10
93
E96h
B1D0
B1D07
B1D06
B1D05
B1D01
B1D03
B1D02
B1D01
B1D00
93
E95h
B1DLC
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
93
93
93
E94h
B1EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
93
E93h
B1EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
93
E92h
B1SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
93
E91h
B1SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
93
E90h
B1CON
TXBIF
TXABT
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
93
E90h
B1CON
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
93
E8Fh
CANCON_RO9
CANCON_RO9
E8Eh
CANSTAT_RO9
CANSTAT_RO9
E8Dh
B0D7
B0D77
B0D76
B0D75
B0D70
B0D73
B0D72
B0D71
B0D70
93
E8Ch
B0D6
B0D67
B0D66
B0D65
B0D60
B0D63
B0D62
B0D61
B0D60
93
E8Bh
B0D5
B0D57
B0D56
B0D55
B0D50
B0D53
B0D52
B0D51
B0D50
93
E8Ah
B0D4
B0D47
B0D46
B0D45
B0D40
B0D43
B0D42
B0D41
B0D40
93
E89h
B0D3
B0D37
B0D36
B0D35
B0D30
B0D33
B0D32
B0D31
B0D30
93
E88h
B0D2
B0D27
B0D26
B0D25
B0D20
B0D23
B0D22
B0D21
B0D20
94
E87h
B0D1
B0D17
B0D16
B0D15
B0D10
B0D13
B0D12
B0D11
B0D10
94
E86h
B0D0
B0D07
B0D06
B0D05
B0D00
B0D03
B0D02
B0D01
B0D00
94
E85h
B0DLC
—
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
94
93
93
E84h
B0EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
94
E83h
B0EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
94
E82h
B0SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
94
E81h
B0SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
94
E80h
B0CON
TXBIF
TXABT
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
94
E80h
B0CON
RTXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
94
E7Fh
TXBIE
—
—
—
—
—
94
E7Eh
BIE0
CAN Buffer Interrupt Enable
E7Dh
BSEL0
Mode Select Register 0
—
—
E7Ch
MSEL3
CAN Mask Select Register 3
94
E7Bh
MSEL2
CAN Mask Select Register 2
94
E7Ah
MSEL1
CAN Mask Select Register 1
94
E79h
MSEL0
CAN Mask Select Register 0
94
E78h
RXFBCON7
CAN Buffer 15/14 Pointer Register
94
E77h
RXFBCON6
CAN Buffer 13/12 Pointer Register
94
E76h
RXFBCON5
CAN Buffer 11/10 Pointer Register
94
E75h
RXFBCON4
CAN Buffer 9/8 Pointer Register
94
E74h
RXFBCON3
CAN Buffer 7/6 Pointer Register
94
E73h
RXFBCON2
CAN Buffer 5/4 Pointer Register
94
DS30009977G-page 116
CAN TX Buffer Interrupt Enable
94
94
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 6-2:
Addr.
File Name
PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
E72h
RXFBCON1
CAN Buffer 3/2 Pointer Register
E71h
RXFBCON0
CAN Buffer 1/0 Pointer Register
E70h
SDFLC
E6Fh
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
on page
94
94
—
—
—
CAN Device Net Count Register
RXF15EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
94
E6Eh
RXF15EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
94
E6Dh
RXF15SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
94
E6Ch
RXF15SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
94
E6Bh
RXF14EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
94
E6Ah
RXF14EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
94
E69h
RXF14SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
94
E68h
RXF14SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
94
94
E67h
RXF13EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
94
E66h
RXF13EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
95
E65h
RXF13SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
95
E64h
RXF13SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
95
E63h
RXF12EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
95
E62h
RXF12EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
95
E61h
RXF12SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
95
E60h
RXF12SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
95
E5Fh
RXF11EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
95
E5Eh
RXF11EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
95
E5Dh
RXF11SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
95
E5Ch
RXF11SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
95
E5Bh
RXF10EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
95
E5Ah
RXF10EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
95
E59h
RXF10SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
95
E58h
RXF10SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
95
E57h
RXF9EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
95
E56h
RXF9EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
95
E55h
RXF9SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
95
E54h
RXF9SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
95
E53h
RXF8EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
95
E52h
RXF8EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
95
E51h
RXF8SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
95
E50h
RXF8SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
95
E4Fh
RXF7EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
95
E4Eh
RXF7EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
95
E4Dh
RXF7SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
95
E4Ch
RXF7SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
95
E4Bh
RXF6EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
95
E4Ah
RXF6EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
95
E49h
RXF6SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
95
E48h
RXF6SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
95
E47h
RXFCON1
CAN Receive Filter Control Register 1
E46h
RXFCON0
CAN Receive Filter Control Register 0
E45h
BRGCON3
WAKDIS
WAKFIL
—
—
—
SEG2PH2
SEG2PH1
SEG2PH0
95
E44h
BRGCON2
SEG2PHTS
SAM
SEG1PH2
SEG1PH1
SEG1PH0
PRSEG2
PRSEG1
PRSEG0
96
E43h
BRGCON1
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
96
E42h
TXERRCNT
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
96
E41h
RXERRCNT
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
96
2010-2017 Microchip Technology Inc.
95
95
DS30009977G-page 117
PIC18F66K80 FAMILY
6.3.5
STATUS REGISTER
The STATUS register, shown in Register 6-2, contains
the arithmetic status of the ALU. The STATUS register
can be the operand for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
the write to these five bits is disabled.
These bits are set or cleared according to the device
logic. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended. For example, CLRF STATUS will set the Z bit
but leave the other bits unchanged. The STATUS
register then reads back as ‘000u u1uu’.
REGISTER 6-2:
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions be used to alter
the STATUS register because these instructions do not
affect the Z, C, DC, OV or N bits in the STATUS
register.
For other instructions not affecting any Status bits, see
the instruction set summaries in Table 29-2 and
Table 29-3.
Note:
The C and DC bits operate, in subtraction,
as borrow and digit borrow bits, respectively.
STATUS REGISTER
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
N
OV
Z
DC(1)
C(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative
(ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the seven-bit
magnitude which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit(1)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result occurred
bit 0
C: Carry/Borrow bit(2)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand.
For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand.
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6.4
Data Addressing Modes
Note:
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. For more information, see
Section 6.6 “Data Memory and the
Extended Instruction Set”.
While the program memory can be addressed in only
one way, through the Program Counter, information in
the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
•
•
•
•
Inherent
Literal
Direct
Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). For details on
this mode’s operation, see Section 6.6.1 “Indexed
Addressing with Literal Offset”.
6.4.1
INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all. They either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as Inherent
Addressing. Examples of this mode include SLEEP,
RESET and DAW.
Other instructions work in a similar way, but require an
additional explicit argument in the opcode. This method
is known as the Literal Addressing mode because the
instructions require some literal value as an argument.
Examples of this include ADDLW and MOVLW, which
respectively, add or move a literal value to the W
register. Other examples include CALL and GOTO,
which include a 20-bit program memory address.
6.4.2
DIRECT ADDRESSING
Direct Addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies the instruction’s data
source as either a register address in one of the banks
2010-2017 Microchip Technology Inc.
of data RAM (see Section 6.3.3 “General Purpose
Register File”) or a location in the Access Bank (see
Section 6.3.2 “Access Bank”).
The Access RAM bit, ‘a’, determines how the address
is interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 6.3.1 “Bank Select Register”) are used with
the address to determine the complete 12-bit address
of the register. When ‘a’ is ‘0’, the address is interpreted
as being a register in the Access Bank. Addressing that
uses the Access RAM is sometimes also known as
Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction,
either the target register being operated on or the W
register.
6.4.3
INDIRECT ADDRESSING
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures such as
tables and arrays in data memory.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code using
loops, such as the example of clearing an entire RAM
bank in Example 6-5. It also enables users to perform
Indexed Addressing and other Stack Pointer
operations for program memory in data memory.
EXAMPLE 6-5:
NEXT
LFSR
CLRF
BTFSS
BRA
CONTINUE
HOW TO CLEAR RAM
(BANK 1) USING INDIRECT
ADDRESSING
FSR0, 100h ;
POSTINC0
; Clear INDF
; register then
; inc pointer
FSR0H, 1
; All done with
; Bank1?
NEXT
; NO, clear next
; YES, continue
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6.4.3.1
FSR Registers and the
INDF Operand
mapped in the SFR space, but are not physically implemented. Reading or writing to a particular INDF register
actually accesses its corresponding FSR register pair.
A read from INDF1, for example, reads the data at the
address indicated by FSR1H:FSR1L.
At the core of Indirect Addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers: FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Instructions that use the INDF registers as operands
actually use the contents of their corresponding FSR as
a pointer to the instruction’s target. The INDF operand
is just a convenient way of using the pointer.
Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
Indirect Addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can
be thought of as “virtual” registers. The operands are
FIGURE 6-8:
INDIRECT ADDRESSING
000h
Using an instruction with one of the
Indirect Addressing registers as the
operand....
Bank 0
ADDWF, INDF1, 1
100h
Bank 1
200h
...uses the 12-bit address stored in
the FSR pair associated with that
register....
300h
FSR1H:FSR1L
7
0
x x x x 1 1 1 1
7
Bank 2
0
1 1 0 0 1 1 0 0
Bank 3
through
Bank 13
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
FCCh. This means the contents of
location FCCh will be added to that
of the W register and stored back in
FCCh.
E00h
Bank 14
F00h
FFFh
Bank 15
Data Memory
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6.4.3.2
FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on its stored value.
These operands are:
• POSTDEC – Accesses the FSR value, then
automatically decrements it by ‘1’ afterwards
• POSTINC – Accesses the FSR value, then
automatically increments it by ‘1’ afterwards
• PREINC – Increments the FSR value by ‘1’, then
uses it in the operation
• PLUSW – Adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the new value in the operation
In this context, accessing an INDF register uses the
value in the FSR registers without changing them.
Similarly, accessing a PLUSW register gives the FSR
value, offset by the value in the W register, with neither
value actually changed in the operation. Accessing the
other virtual registers changes the value of the FSR
registers.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair. Rollovers of
the FSRnL register, from FFh to 00h, carry over to the
FSRnH register. On the other hand, results of these
operations do not change the value of any flags in the
STATUS register (for example, Z, N and OV bits).
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
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6.4.3.3
Operations by FSRs on FSRs
Indirect Addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations.
As a specific case, assume that the FSR0H:FSR0L
registers contain FE7h, the address of INDF1.
Attempts to read the value of the INDF1, using INDF0
as an operand, will return 00h. Attempts to write to
INDF1, using INDF0 as the operand, will result in a
NOP.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair, but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, however, particularly if their
code uses Indirect Addressing.
Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise
the appropriate caution, so that they do not inadvertently
change settings that might affect the operation of the
device.
6.5
Program Memory and the
Extended Instruction Set
The operation of program memory is unaffected by the
use of the extended instruction set.
Enabling the extended instruction set adds five
additional two-word commands to the existing PIC18
instruction set: ADDFSR, CALLW, MOVSF, MOVSS and
SUBFSR. These instructions are executed as described
in Section 6.2.4 “Two-Word Instructions”.
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6.6
Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Using the
Access Bank for many of the core PIC18 instructions
introduces a new addressing mode for the data memory
space. This mode also alters the behavior of Indirect
Addressing using FSR2 and its associated operands.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in Direct Addressing) or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer
specified by FSR2. The offset and the contents of FSR2
are added to obtain the target address of the operation.
6.6.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode. Inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing
modes are unaffected.
6.6.1
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit = 1), or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the different possible addressing modes when the extended
instruction set is enabled is shown in Figure 6-9.
INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented
instructions – can invoke a form of Indexed Addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset or the Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 29.2.1
“Extended Instruction Syntax”.
• Use of the Access Bank (‘a’ = 0)
• A file address argument that is less than or equal
to 5Fh
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FIGURE 6-9:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED
INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When a = 0 and f 60h:
The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and FFFh. This is the same as
locations, F60h to FFFh,
(Bank 15) of data memory.
Locations below 060h are not
available in this addressing
mode.
000h
060h
Bank 0
100h
00h
Bank 1
through
Bank 14
60h
Valid Range
for ‘f’
FFh
F00h
Access RAM
Bank 15
F40h
SFRs
FFFh
Data Memory
When a = 0 and f5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
000h
Bank 0
060h
100h
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
Bank 15
F40h
SFRs
FFFh
Data Memory
When a = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
BSR
00000000
000h
Bank 0
060h
100h
Bank 1
through
Bank 14
001001da ffffffff
F00h
Bank 15
F40h
SFRs
FFFh
Data Memory
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6.6.3
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower part of Access RAM
(00h to 5Fh) is mapped. Rather than containing just the
contents of the bottom part of Bank 0, this mode maps
the contents from Bank 0 and a user-defined “window”
that can be located anywhere in the data memory
space.
The value of FSR2 establishes the lower boundary of
the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described. (See Section 6.3.2 “Access
Bank”.) An example of Access Bank remapping in this
addressing mode is shown in Figure 6-10.
FIGURE 6-10:
Remapping the Access Bank applies only to operations
using the Indexed Literal Offset mode. Operations that
use the BSR (Access RAM bit = 1) will continue to use
Direct Addressing as before. Any Indirect or Indexed
Addressing operation that explicitly uses any of the
indirect file operands (including FSR2) will continue to
operate as standard Indirect Addressing. Any instruction that uses the Access Bank, but includes a register
address of greater than 05Fh, will use Direct
Addressing and the normal Access Bank map.
6.6.4
BSR IN INDEXED LITERAL
OFFSET MODE
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL
OFFSET ADDRESSING
Example Situation:
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
000h
05Fh
Bank 0
100h
120h
17Fh
200h
Window
Bank 1
00h
Bank 1 “Window”
5Fh
60h
Special Function Registers
at F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
Not Accessible
Bank 2
through
Bank 14
SFRs
FFh
Access Bank
F00h
Bank 15
F60h
FFFh
SFRs
Data Memory
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7.0
FLASH PROGRAM MEMORY
7.1
Table Reads and Table Writes
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 64 bytes at a time. Program memory is
erased in blocks of 64 bytes at a time. A bulk erase
operation may not be issued from user code.
• Table Read (TBLRD)
• Table Write (TBLWT)
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 7-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 7.5 “Writing
to Flash Program Memory”. Figure 7-2 shows the
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.
FIGURE 7-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1: The Table Pointer register points to a byte in program memory.
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FIGURE 7-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1: The Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL. The process for physically writing data to the program memory array is discussed in
Section 7.5 “Writing to Flash Program Memory”.
7.2
Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
•
•
•
•
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
7.2.1
EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 7-1) is the control
register for memory accesses. The EECON2 register,
not a physical register, is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access is a
program or data EEPROM memory access. When
clear, any subsequent operations operate on the data
EEPROM memory. When set, any subsequent
operations operate on the program memory.
The CFGS control bit determines if the access is to the
Configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
operate on Configuration registers regardless of
EEPGD (see Section 28.0 “Special Features of the
CPU”). When clear, memory selection access is
determined by EEPGD.
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The FREE bit, when set, allows a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, allows a write operation. On
power-up, the WREN bit is clear. The WRERR bit is set
in hardware when the WR bit is set and cleared when
the internal programming timer expires and the write
operation is complete.
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the write operation.
Note:
The EEIF interrupt flag bit (PIR4) is
set when the write is complete. It must be
cleared in software.
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REGISTER 7-1:
EECON1: EEPROM CONTROL REGISTER 1
R/W-x
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
—
FREE
WRERR(1)
WREN
WR
RD
bit 7
bit 0
S = Settable bit
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Accesses Flash program memory
0 = Accesses data EEPROM memory
bit 6
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Accesses Configuration registers
0 = Accesses Flash program or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1 = Erases the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Performs write-only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation or an improper write attempt)
0 = The write operation completed
bit 2
WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or, a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once the write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Note 1:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
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7.2.2
TABLAT – TABLE LATCH REGISTER
7.2.4
The Table Latch (TABLAT) is an eight-bit register
mapped into the SFR space. The Table Latch register
is used to hold 8-bit data during data transfers between
program memory and data RAM.
7.2.3
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
TBLPTR – TABLE POINTER
REGISTER
When a TBLWT is executed, the six LSbs of the Table
Pointer register (TBLPTR) determine which of
the 64 program memory holding registers is written to.
When the timed write to program memory begins (via
the WR bit), the 16 MSbs of the TBLPTR
(TBLPTR) determine which program memory
block of 64 bytes is written to. For more detail, see
Section 7.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the Device ID, the User ID and the Configuration bits.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR) are ignored.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways, based on the
table operation. These operations are shown in
Table 7-1 and only affect the low-order 21 bits.
TABLE 7-1:
TABLE POINTER BOUNDARIES
Figure 7-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
FIGURE 7-3:
21
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU
16
15
TBLPTRH
8
TABLE ERASE/WRITE
TBLPTR
7
TBLPTRL
0
TABLE WRITE
TBLPTR
TABLE READ – TBLPTR
DS30009977G-page 128
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7.3
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
FIGURE 7-4:
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 7-4
shows the interface between the internal program
memory and the TABLAT.
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx0
TBLPTR = xxxxx1
Instruction Register
(IR)
EXAMPLE 7-1:
FETCH
TBLRD
TABLAT
Read Register
READING A FLASH PROGRAM MEMORY WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVF
MOVF
TABLAT, W
WORD_EVEN
TABLAT, W
WORD_ODD
2010-2017 Microchip Technology Inc.
; read into TABLAT and increment
; get data
; read into TABLAT and increment
; get data
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7.4
Erasing Flash Program Memory
The erase blocks are 32 words or 64 bytes.
Word erase in the Flash array is not supported.
When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR point to the block being erased. The
TBLPTR bits are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash
program memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
For protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 7-2:
7.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1.
2.
3.
4.
5.
6.
7.
Load the Table Pointer register with the address
of row to be erased.
Set the EECON1 register for the erase operation:
• Set the EEPGD bit to point to program memory
• Clear the CFGS bit to access program memory
• Set the WREN bit to enable writes
• Set the FREE bit to enable the erase
Disable the interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit.
This begins the row erase cycle.
The CPU will stall for the duration of the erase
for TIW. (See Parameter D133A.)
Re-enable interrupts.
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
EECON1,
EECON1,
EECON1,
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
;
;
;
;
;
ERASE_ROW
Required
Sequence
DS30009977G-page 130
EEPGD
CFGS
WREN
FREE
GIE
point to Flash program memory
access Flash program memory
enable write to memory
enable Row Erase operation
disable interrupts
; write 55h
WR
GIE
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
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7.5
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
Writing to Flash Program Memory
The programming blocks are 32 words or 64 bytes.
Word or byte programming is not supported.
Table writes are used internally to load the holding registers needed to program the Flash memory. There are
64 holding registers for programming by the table writes.
Note:
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT instruction may need to be executed 64 times for
each programming operation. All of the table write operations will essentially be short writes because only the
holding registers are written. At the end of updating the
64 or 128 holding registers, the EECON1 register must
be written to in order to start the programming operation
with a long write.
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may
be modified, provided that the change does
not attempt to change any bit from a ‘0’ to a
‘1’. When modifying individual bytes, it is
not necessary to load all 64 holding
registers before executing a write
operation.
The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long
write cycle. The long write is terminated by the internal
programming timer.
FIGURE 7-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
TBLPTR = xxxxx0
8
TBLPTR = xxxxx1
Holding Register
TBLPTR = xxxx3F
TBLPTR = xxxxx2
Holding Register
8
Holding Register
Holding Register
Program Memory
7.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
8.
Read the 64 bytes into RAM.
Update the data values in RAM as necessary.
Load the Table Pointer register with the address
being erased.
Execute the row erase procedure.
Load the Table Pointer register with the address
of the first byte being written.
Write the 64 bytes into the holding registers with
auto-increment.
Set the EECON1 register for the write operation:
• Set the EEPGD bit to point to program memory
• Clear the CFGS bit to access program memory
• Set the WREN to enable byte writes
Disable the interrupts.
2010-2017 Microchip Technology Inc.
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
The CPU will stall for the duration of the write for
TIW (see Parameter D133A).
12. Re-enable the interrupts.
13. Verify the memory (table read).
An example of the required code is shown in
Example 7-3 on the following page.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
DS30009977G-page 131
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EXAMPLE 7-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
SIZE_OF_BLOCK
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; number of bytes in erase block
TBLRD*+
MOVF
MOVWF
DECFSZ
BRA
TABLAT, W
POSTINC0
COUNTER
READ_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
; point to buffer
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
; load TBLPTR with the base
; address of the memory block
; point to buffer
; Load TBLPTR with the base
; address of the memory block
READ_BLOCK
;
;
;
;
;
read into TABLAT, and inc
get data
store data
done?
repeat
MODIFY_WORD
; update buffer word
ERASE_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
Required
MOVWF
Sequence
MOVLW
MOVWF
BSF
BSF
TBLRD*MOVLW
MOVWF
MOVLW
MOVWF
WRITE_BUFFER_BACK
MOVLW
MOVWF
WRITE_BYTE_TO_HREGS
MOVFF
MOVWF
TBLWT+*
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
point to Flash program memory
access Flash program memory
enable write to memory
enable Row Erase operation
disable interrupts
; write 55h
;
;
;
;
;
write 0AAh
start erase (CPU stall)
re-enable interrupts
dummy read decrement
point to buffer
SIZE_OF_BLOCK
COUNTER
; number of bytes in holding register
POSTINC0, WREG
TABLAT
;
;
;
;
;
DECFSZ COUNTER
BRA
WRITE_BYTE_TO_HREGS
DS30009977G-page 132
;
;
;
;
;
get low byte of buffer data
present data to table latch
write data, perform a short write
to internal TBLWT holding register.
loop until buffers are full
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EXAMPLE 7-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
Required
Sequence
7.5.2
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
EECON1,
EECON1,
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
EECON1,
EEPGD
CFGS
WREN
GIE
;
;
;
;
point to Flash program memory
access Flash program memory
enable write to memory
disable interrupts
; write 55h
;
;
;
;
WR
GIE
WREN
write 0AAh
start program (CPU stall)
re-enable interrupts
disable write to memory
WRITE VERIFY
7.5.4
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.3
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 28.0 “Special Features of the
CPU” for more detail.
UNEXPECTED TERMINATION OF
WRITE OPERATION
7.6
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 7-2:
Name
TBLPTRU
PROTECTION AGAINST
SPURIOUS WRITES
Flash Program Operation During
Code Protection
See Section 28.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Bit 7
—
Bit 6
—
Bit 5
bit
21(1)
Bit 4
Bit 3
Program Memory Table Pointer High Byte (TBLPTR)
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR)
TABLAT
Program Memory Table Latch
EECON2
GIE/GIEH
PEIE/GIEL TMR0IE
Bit 1
Bit 0
Program Memory Table Pointer Upper Byte (TBLPTR)
TBPLTRH
INTCON
Bit 2
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
EEPROM Control Register 2 (not a physical register)
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
IPR4
TMR4IP
EEIP
CMP2IP
CMP1IP
—
CCP5IP
CCP4IP
CCP3IP
PIR4
TMR4IF
EEIF
CMP2IF
CMP1IF
—
CCP5IF
CCP4IF
CCP3IF
PIE4
TMR4IE
EEIE
CMP2IE
CMP1IE
—
CCP5IE
CCP4IE
CCP3IE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
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8.0
DATA EEPROM MEMORY
The data EEPROM is a nonvolatile memory array,
separate from the data RAM and program memory, that
is used for long-term storage of program data. It is not
directly mapped in either the register file or program
memory space, but is indirectly addressed through the
Special Function Registers (SFRs). The EEPROM is
readable and writable during normal operation over the
entire VDD range.
Five SFRs are used to read and write to the data
EEPROM, as well as the program memory. They are:
•
•
•
•
•
EECON1
EECON2
EEDATA
EEADR
EEADRH
The data EEPROM allows byte read and write. When
interfacing to the data memory block, EEDATA holds
the 8-bit data for read/write and the EEADRH:EEADR
register pair holds the address of the EEPROM location
being accessed.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write).
The write time is controlled by an on-chip timer; it will
vary with voltage and temperature, as well as from chipto-chip. Please refer to Parameter D122 (Table 31-1 in
Section 31.0 “Electrical Characteristics”) for exact
limits.
8.1
EEADR and EEADRH Registers
The EEADRH:EEADR register pair is used to address
the data EEPROM for read and write operations.
EEADRH holds the two MSbs of the address; the upper
6 bits are ignored. The 10-bit range of the pair can
address a memory range of 1024 bytes (00h to 3FFh).
8.2
EECON1 and EECON2 Registers
Access to the data EEPROM is controlled by two
registers: EECON1 and EECON2. These are the same
registers which control access to the program memory
and are used in a similar manner for the data
EEPROM.
The EECON1 register (Register 8-1) is the control
register for data and program memory access. Control
bit, EEPGD, determines if the access will be to program
memory or data EEPROM memory. When clear,
operations will access the data EEPROM memory.
When set, program memory is accessed.
Control bit, CFGS, determines if the access will be to
the Configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access Configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WREN bit is set and cleared,
when the internal programming timer expires and the
write operation is complete.
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
Note:
The EEIF interrupt flag bit (PIR4) is
set when the write is complete. It must be
cleared in software.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 7.1 “Table Reads
and Table Writes” regarding table reads.
The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all ‘0’s.
DS30009977G-page 134
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REGISTER 8-1:
EECON1: DATA EEPROM CONTROL REGISTER 1
R/W-x
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
—
FREE
WRERR(1)
WREN
WR
RD
bit 7
bit 0
Legend:
S = Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Accesses Flash program memory
0 = Accesses data EEPROM memory
bit 6
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Accesses Configuration registers
0 = Accesses Flash program or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1 = Erases the program memory row addressed by TBLPTR on the next WR command (cleared by
completion of erase operation)
0 = Performs write only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation or an improper write attempt)
0 = The write operation completed
bit 2
WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle, or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once the write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Note 1:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
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8.3
Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADRH:EEADR register pair, clear the
EEPGD control bit (EECON1) and then set control
bit, RD (EECON1). The data is available after one
instruction cycle, in the EEDATA register. It can be read
after one NOP instruction. EEDATA will hold this value
until another read operation or until it is written to by the
user (during a write operation).
After a write sequence has been initiated, EECON1,
EEADRH:EEADR and EEDATA cannot be modified.
The WR bit will be inhibited from being set unless the
WREN bit is set. The WREN bit must be set on a
previous instruction. Both WR and WREN cannot be
set with the same instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt
or poll this bit; EEIF must be cleared by software.
The basic process is shown in Example 8-1.
8.5
8.4
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADRH:EEADR register pair
and the data written to the EEDATA register. The
sequence in Example 8-2 must be followed to initiate
the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Note:
Write Verify
Self-write execution to Flash and
EEPROM memory cannot be done while
running in LP Oscillator (low-power)
mode. Executing a self-write will put the
device into High-Power mode.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware.
DS30009977G-page 136
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EXAMPLE 8-1:
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
NOP
MOVF
EXAMPLE 8-2:
Required
Sequence
DATA EEPROM READ
DATA_EE_ADDRH
EEADRH
DATA_EE_ADDR
EEADR
EECON1, EEPGD
EECON1, CFGS
EECON1, RD
;
;
;
;
;
;
;
EEDATA, W
; W = EEDATA
Upper bits of Data Memory Address to read
Lower bits of Data Memory Address to read
Point to DATA memory
Access EEPROM
EEPROM Read
DATA EEPROM WRITE
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
DATA_EE_ADDRH
EEADRH
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDATA
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
;
;
;
;
;
;
;
;
;
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BSF
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
EECON1,
INTCON,
;
;
;
;
;
;
;
;
BCF
EECON1, WREN
2010-2017 Microchip Technology Inc.
GIE
WR
WR
GIE
Upper bits of Data Memory Address to write
Lower bits of Data Memory Address to write
Data Memory Value to write
Point to DATA memory
Access EEPROM
Enable writes
Disable Interrupts
Write 55h
Write 0AAh
Set WR bit to begin write
Wait for write to complete GOTO $-2
Enable Interrupts
; User code execution
; Disable writes on write complete (EEIF set)
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8.6
Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
Configuration Words. External read and write
operations are disabled if code protection is enabled.
The microcontroller itself can both read and write to the
internal data EEPROM regardless of the state of the
code-protect Configuration bit. Refer to Section 28.0
“Special Features of the CPU” for additional
information.
8.7
Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during the Power-up Timer period (TPWRT,
Parameter 33).
8.8
Using the Data EEPROM
The
data
EEPROM is a
high-endurance,
byte-addressable array that has been optimized for the
storage of frequently changing information (e.g., program variables or other data that are updated often).
Frequently changing values will typically be updated
more often than Parameter D124. If this is not the case,
an array refresh must be performed. For this reason,
variables that change infrequently (such as constants,
IDs, calibration, etc.) should be stored in Flash program
memory.
A simple data EEPROM refresh routine is shown in
Example 8-3.
Note:
If data EEPROM is only used to store
constants and/or data that changes often,
an array refresh is likely not required. See
Parameter D124.
The write initiate sequence, and the WREN bit
together, help prevent an accidental write during
brown-out, power glitch or software malfunction.
EXAMPLE 8-3:
DATA EEPROM REFRESH ROUTINE
CLRF
CLRF
BCF
BCF
BCF
BSF
EEADR
EEADRH
EECON1,
EECON1,
INTCON,
EECON1,
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
INCFSZ
BRA
EECON1, RD
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
$-2
EEADR, F
LOOP
EEADRH, F
LOOP
BCF
BSF
EECON1, WREN
INTCON, GIE
CFGS
EEPGD
GIE
WREN
LOOP
DS30009977G-page 138
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Start at address 0
Set for memory
Set for Data EEPROM
Disable interrupts
Enable writes
Loop to refresh array
Read current address
Write 55h
Write 0AAh
Set WR bit to begin write
Wait for write to complete
Increment
Not zero,
Increment
Not zero,
address
do it again
the high address
do it again
; Disable writes
; Enable interrupts
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 8-1:
Name
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
EEADRH
EEPROM Address Register High Byte
EEADR
EEPROM Address Register Low Byte
EEDATA
EEPROM Data Register
EECON2
EEPROM Control Register 2 (not a physical register)
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
CCP3IP
IPR4
TMR4IP
EEIP
CMP2IP
CMP1IP
—
CCP5IP
CCP4IP
PIR4
TMR4IF
EEIF
CMP2IF
CMP1IF
—
CCP5IF
CCP4IF
CCP3IF
PIE4
TMR4IE
EEIE
CMP2IE
CMP1IE
—
CCP5IE
CCP4IE
CCP3IE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
2010-2017 Microchip Technology Inc.
DS30009977G-page 139
PIC18F66K80 FAMILY
9.0
8 x 8 HARDWARE MULTIPLIER
9.1
Introduction
EXAMPLE 9-1:
MOVF
MULWF
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
EXAMPLE 9-2:
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows PIC18 devices to be used in many applications
previously reserved for digital-signal processors. A
comparison of various hardware and software multiply
operations, along with the savings in memory and
execution time, is shown in Table 9-1.
9.2
8 x 8 UNSIGNED MULTIPLY
ROUTINE
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
ARG1, W
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH, F
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
;
;
;
;
;
ARG1 * ARG2 ->
PRODH:PRODL
Test Sign Bit
PRODH = PRODH
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
Operation
Example 9-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 9-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
TABLE 9-1:
Routine
8 x 8 unsigned
8 x 8 signed
16 x 16
unsigned
16 x 16 signed
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Multiply Method
Without hardware multiply
Program
Cycles
Memory
(Max)
(Words)
13
Time
@ 64 MHz
@ 48 MHz
@ 10 MHz
@ 4 MHz
69
4.3 s
5.7 s
27.6 s
69 s
Hardware multiply
1
1
62.5 ns
83.3 ns
400 ns
1 s
Without hardware multiply
33
91
5.6 s
7.5 s
36.4 s
91 s
Hardware multiply
6
6
375 ns
500 ns
2.4 s
6 s
Without hardware multiply
21
242
15.1 s
20.1 s
96.8 s
242 s
Hardware multiply
28
28
1.7 s
2.3 s
11.2 s
28 s
Without hardware multiply
52
254
15.8 s
21.2 s
101.6 s
254 s
Hardware multiply
35
40
2.5 s
3.3 s
16.0 s
40 s
DS30009977G-page 140
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
Example 9-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 9-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 9-1:
RES3:RES0
=
=
EXAMPLE 9-3:
EQUATION 9-2:
RES3:RES0=
=
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L)
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L * ARG2H->
PRODH:PRODL
Add cross
products
ARG1H * ARG2L->
PRODH:PRODL
Add cross
products
Example 9-4 shows the sequence to do a 16 x 16
signed multiply. Equation 9-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
2010-2017 Microchip Technology Inc.
MOVFF
MOVFF
; ARG1L * ARG2L ->
; PRODH:PRODL
PRODH, RES1 ;
PRODL, RES0 ;
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
; ARG1H * ARG2H ->
; PRODH:PRODL
PRODH, RES3 ;
PRODL, RES2 ;
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
;
;
;
;
;
;
;
;
ARG1L * ARG2H ->
PRODH:PRODL
Add cross
products
;
;
;
;
;
;
;
;
;
;
;
ARG1L, W
ARG2L
;
;
;
;
;
;
;
;
;
;
16 x 16 SIGNED MULTIPLY
ROUTINE
;
;
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L) +
(-1 ARG2H ARG1H:ARG1L 216) +
(-1 ARG1H ARG2H:ARG2L 216)
EXAMPLE 9-4:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
;
;
;
;
;
;
;
;
;
ARG1H * ARG2L ->
PRODH:PRODL
Add cross
products
;
BTFSS
ARG2H, 7
BRA SIGN_ARG1
MOVF
ARG1L, W
SUBWF
RES2
MOVF
ARG1H, W
SUBWFB RES3
SIGN_ARG1
BTFSS
ARG1H, 7
BRA
CONT_CODE
MOVF
ARG2L, W
SUBWF
RES2
MOVF
ARG2H, W
SUBWFB RES3
;
CONT_CODE
:
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
;
; ARG1H:ARG1L neg?
; no, done
;
;
;
DS30009977G-page 141
PIC18F66K80 FAMILY
10.0
INTERRUPTS
Members of the PIC18F66K80 family of devices have
multiple interrupt sources and an interrupt priority
feature that allows most interrupt sources to be
assigned a high-priority level or a low-priority level. The
high-priority interrupt vector is at 0008h and the
low-priority interrupt vector is at 0018h. High-priority
interrupt events will interrupt any low-priority interrupts
that may be in progress.
The registers for controlling interrupt operation are:
•
•
•
•
•
•
•
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2, PIR3, PIR4 and PIR5
PIE1, PIE2, PIE3, PIE4 and PIE5
IPR1, IPR2, IPR3, IPR4 and IPR5
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic
bit names in these registers. This allows the
assembler/compiler to automatically take care of the
placement of these bits within the specified register.
In general, interrupt sources have three bits to control
their operation. They are:
• Flag bit – Indicating that an interrupt event
occurred
• Enable bit – Enabling program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit – Specifying high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON). When interrupt priority is
enabled, there are two bits that enable interrupts
globally. Setting the GIEH bit (INTCON) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
Global Interrupt Enable bit are set, the interrupt will
vector immediately to address 0008h or 0018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
DS30009977G-page 142
When the IPEN bit is cleared (default state), the interrupt
priority feature is disabled and interrupts are compatible
with PIC® mid-range devices. In Compatibility mode, the
interrupt priority bits for each source have no effect. INTCON is the PEIE bit that enables/disables all peripheral interrupt sources. INTCON is the GIE bit that
enables/disables all interrupt sources. All interrupts
branch to address 0008h in Compatibility mode.
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High-priority interrupt sources can interrupt a
low-priority interrupt. Low-priority interrupts are not
processed while high-priority interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine (ISR),
the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) that re-enables interrupts.
For external interrupt events, such as the INTx pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
Note:
Do not use the MOVFF instruction to modify
any of the Interrupt Control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
FIGURE 10-1:
PIC18F66K80 FAMILY INTERRUPT LOGIC
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
PIR4
PIE4
IPR4
PIR5
PIE5
IPR5
Wake-up if in
Idle or Sleep modes
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Interrupt to CPU
Vector to Location
0008h
GIE/GIEH
IPEN
IPEN
PEIE/GIEL
IPEN
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
PIR4
PIE4
IPR4
PIR5
PIE5
IPR5
2010-2017 Microchip Technology Inc.
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
Interrupt to CPU
Vector to Location
0018h
IPEN
GIE/GIEH
PEIE/GIEL
DS30009977G-page 143
PIC18F66K80 FAMILY
10.1
INTCON Registers
Note:
The INTCON registers are readable and writable
registers that contain various enable, priority and flag
bits.
REGISTER 10-1:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE(2)
TMR0IF
INT0IF
RBIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high-priority interrupts
0 = Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low-priority peripheral interrupts
0 = Disables all low-priority peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit(2)
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register has not overflowed
bit 1
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB pins changed state (must be cleared in software)
0 = None of the RB pins have changed state
Note 1:
2:
A mismatch condition will continue to set this bit. To end the mismatch condition and allow the bit to be
cleared, read PORTB and wait one additional instruction cycle.
Each pin on PORTB for interrupt-on-change is individually enabled and disabled in the IOCB register. By
default, all pins are disabled.
DS30009977G-page 144
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
REGISTER 10-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port TRIS values
bit 6
INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5
INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4
INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3
INTEDG3: External Interrupt 3 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 2
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
INT3IP: INT3 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
2010-2017 Microchip Technology Inc.
DS30009977G-page 145
PIC18F66K80 FAMILY
REGISTER 10-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
INT3IE: INT3 External Interrupt Enable bit
1 = Enables the INT3 external interrupt
0 = Disables the INT3 external interrupt
bit 4
INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2
INT3IF: INT3 External Interrupt Flag bit
1 = The INT3 external interrupt occurred (must be cleared in software)
0 = The INT3 external interrupt did not occur
bit 1
INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
DS30009977G-page 146
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
10.2
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are six Peripheral Interrupt
Request (Flag) registers (PIR1 through PIR5).
Note 1: Interrupt flag bits are set when an
interrupt condition occurs regardless of
the state of its corresponding enable bit or
the Global Interrupt Enable bit, GIE
(INTCON).
2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 10-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
TMR1GIF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or write operation has taken place (must be cleared in software)
0 = No read or write operation has occurred
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5
RC1IF: EUSARTx Receive Interrupt Flag bit
1 = The EUSARTx receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0 = The EUSARTx receive buffer is empty
bit 4
TX1IF: EUSARTx Transmit Interrupt Flag bit
1 = The EUSARTx transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0 = The EUSARTx transmit buffer is full
bit 3
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2
TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = Timer gate interrupt occurred (must be cleared in software)
0 = No timer gate interrupt occurred
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
2010-2017 Microchip Technology Inc.
DS30009977G-page 147
PIC18F66K80 FAMILY
REGISTER 10-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
OSCFIF
—
—
—
BCLIF
HLVDIF
TMR3IF
TMR3GIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OSCFIF: Oscillator Fail Interrupt Flag bit
1 = Device oscillator failed, clock input has changed to INTOSC (bit must be cleared in software)
0 = Device clock is operating
bit 6-4
Unimplemented: Read as ‘0’
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred (bit must be cleared in software)
0 = No bus collision occurred
bit 2
HLVDIF: High/Low-Voltage Detect Interrupt Flag bit
1 = A low-voltage condition occurred (bit must be cleared in software)
0 = The device voltage is above the regulator’s low-voltage trip point
bit 1
TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (bit must be cleared in software)
0 = TMR3 register did not overflow
bit 0
TMR3GIF: TMR3 Gate Interrupt Flag bit
1 = Timer gate interrupt occurred (bit must be cleared in software)
0 = No timer gate interrupt occurred
DS30009977G-page 148
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
REGISTER 10-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
U-0
U-0
R-0
R-0
R/W-0
R/W-0
R/W-0
U-0
—
—
RC2IF
TX2IF
CTMUIF
CCP2IF
CCP1IF
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
RC2IF: EUSARTx Receive Interrupt Flag bit
1 = The EUSARTx receive buffer, RCREG2, is full (cleared when RCREG2 is read)
0 = The EUSARTx receive buffer is empty
bit 4
TX2IF: EUSARTx Transmit Interrupt Flag bit
1 = The EUSARTx transmit buffer, TXREG2, is empty (cleared when TXREG2 is written)
0 = The EUSARTx transmit buffer is full
bit 3
CTMUIF: CTMU Interrupt Flag bit
1 = CTMU interrupt occurred (must be cleared in software)
0 = No CTMU interrupt occurred
bit 2
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
CCP1IF: ECCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 0
Unimplemented: Read as ‘0’
2010-2017 Microchip Technology Inc.
DS30009977G-page 149
PIC18F66K80 FAMILY
REGISTER 10-7:
PIR4: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 4
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
TMR4IF
EEIF
CMP2IF
CMP1IF
—
CCP5IF
CCP4IF
CCP3IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR4IF: TMR4 Overflow Interrupt Flag bit
1 = TMR4 register overflowed (must be cleared in software)
0 = TMR4 register did not overflow
bit 6
EEIF: Data EEDATA/Flash Write Operation Interrupt Flag bit
1 = The write operation is complete (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 5
CMP2IF: CMP2 Interrupt Flag bit
1 = CMP2 interrupt occurred (must be cleared in software)
0 = CMP2 interrupt did not occur
bit 4
CMP1IF: CMP1 Interrupt Flag bit
1 = CMP1 interrupt occurred (must be cleared in software)
0 = CMP1 interrupt did not occur
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP5IF: CCP5 Interrupt Flag bit
Capture Mode
1 = A TMR register capture occurred (bit must be cleared in software)
0 = No TMR register capture occurred
Compare Mode
1 = A TMR register compare match occurred (must be cleared in software)
0 = No TMR register compare match occurred
PWM Mode
Not used in PWM mode.
bit 1
CCP4IF: CCP4 Interrupt Flag bit
Capture Mode
1 = A TMR register capture occurred (bit must be cleared in software)
0 = No TMR register capture occurred
Compare Mode
1 = A TMR register compare match occurred (must be cleared in software)
0 = No TMR register compare match occurred
PWM Mode
Not used in PWM mode.
bit 0
CCP3IF: CCP3 Interrupt Flag bit
Capture Mode
1 = A TMR register capture occurred (bit must be cleared in software)
0 = No TMR register capture occurred
Compare Mode
1 = A TMR register compare match occurred (must be cleared in software)
0 = No TMR register compare match occurred
PWM Mode
Not used in PWM mode.
DS30009977G-page 150
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
REGISTER 10-8:
PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRXIF
WAKIF
ERRIF
TXB2IF
TXB1IF
TXB0IF
RXB1IF
RXB0IF/
FIFOFIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IRXIF: Invalid Message Received Interrupt Flag bits
1 = An invalid message occurred on the CAN bus
0 = No invalid message occurred on the CAN bus
bit 6
WAKIF: Bus Wake-up Activity Interrupt Flag bit
1 = Activity on the CAN bus has occurred
0 = No activity on the CAN bus
bit 5
ERRIF: Error Interrupt Flag bit (Multiple sources in COMSTAT register)
1 = An error has occurred in the CAN module (multiple sources)
0 = No CAN module errors have occurred
bit 4
TXB2IF: Transmit Buffer 2 Interrupt Flag bit
1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 2 has not completed transmission of a message
bit 3
TXB1IF: Transmit Buffer 1 Interrupt Flag bit
1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 1 has not completed transmission of a message
bit 2
TXB0IF: Transmit Buffer 0 Interrupt Flag bit
1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 0 has not completed transmission of a message
bit 1
RXB1IF: Receive Buffer 1 Interrupt Flag bit
Mode 0:
1 = CAN Receive Buffer 1 has received a new message
0 = CAN Receive Buffer 1 has not received a new message
Modes 1 and 2:
1 = A CAN Receive Buffer/FIFO has received a new message
0 = A CAN Receive Buffer/FIFO has not received a new message
bit 0
Bit operation is dependent on the selected mode:
Mode 0:
RXB0IF: Receive Buffer 0 Interrupt Flag bit
1 = CAN Receive Buffer 0 has received a new message
0 = CAN Receive Buffer 0 has not received a new message
Mode 1:
Unimplemented: Read as ‘0’
Mode 2:
FIFOFIF: FIFO Full Interrupt Flag bit
1 = FIFO has reached full status as defined by the FIFO_HF bit
0 = FIFO has not reached full status as defined by the FIFO_HF bit
2010-2017 Microchip Technology Inc.
DS30009977G-page 151
PIC18F66K80 FAMILY
10.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are six Peripheral
Interrupt Enable registers (PIE1 through PIE6). When
IPEN (RCON) = 0, the PEIE bit must be set to
enable any of these peripheral interrupts.
REGISTER 10-9:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
TMR1GIE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5
RC1IE: EUSARTx Receive Interrupt Enable bit
1 = Enables the EUSARTx receive interrupt
0 = Disables the EUSARTx receive interrupt
bit 4
TX1IE: EUSARTx Transmit Interrupt Enable bit
1 = Enables the EUSARTx transmit interrupt
0 = Disables the EUSARTx transmit interrupt
bit 3
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2
TMR1GIE: TMR1 Gate Interrupt Enable bit
1 = Enables the gate
0 = Disabled the gate
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
DS30009977G-page 152
x = Bit is unknown
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
REGISTER 10-10: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
OSCFIE
—
—
—
BCLIE
HLVDIE
TMR3IE
TMR3GIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6-4
Unimplemented: Read as ‘0’
bit 3
BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
HLVDIE: High/Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
TMR3GIE: Timer3 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
2010-2017 Microchip Technology Inc.
x = Bit is unknown
DS30009977G-page 153
PIC18F66K80 FAMILY
REGISTER 10-11: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
U-0
R-0
R-0
R/W-0
R/W-0
R/W-0
U-0
—
—
RC2IE
TX2IE
CTMUIE
CCP2IE
CCP1IE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5
RC2IE: EUSARTx Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4
TX2IE: EUSARTx Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3
CTMUIE: CTMU Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
CCP2IE: CCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
CCP1IE: ECCP1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
Unimplemented: Read as ‘0’
DS30009977G-page 154
x = Bit is unknown
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
REGISTER 10-12: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
TMR4IE
EEIE
CMP2IE
CMP1IE
—
CCP5IE
CCP4IE
CCP3IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
TMR4IE: TMR4 Overflow Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 6
EEIE: Data EEDATA/Flash Write Operation Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 5
CMP2IE: CMP2 Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 4
CMP1IE: CMP1 Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP5IE: CCP5 Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 1
CCP4IE: CCP4 Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 0
CCP3IE: CCP3 Interrupt Flag bits
1 = Interrupt is enabled
0 = Interrupt is disabled
2010-2017 Microchip Technology Inc.
x = Bit is unknown
DS30009977G-page 155
PIC18F66K80 FAMILY
REGISTER 10-13: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRXIE
WAKIE
ERRIE
TXB2IE
TXB1IE
TXB0IE
RXB1IE
RXB0IE/
FIFOFIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IRXIE: Invalid Message Received Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 6
WAKIE: Bus Wake-up Activity Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 5
ERRIE: Error Interrupt Flag bit (multiple sources in the COMSTAT register)
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 4
TXB2IE: Transmit Buffer 2 Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 3
TXB1IE: Transmit Buffer 1 Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 2
TXB0IE: Transmit Buffer 0 Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 1
RXB1IE: Receive Buffer 1 Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 0
Bit operation is dependent on the selected mode:
Mode 0:
RXB0IE: Receive Buffer 0 Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
Mode 1:
Unimplemented: Read as ‘0’
Mode 2:
FIFOFIE: FIFO Full Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
DS30009977G-page 156
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
10.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are six Peripheral
Interrupt Priority registers (IPR1 through IPR6). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit (RCON) be set.
REGISTER 10-14: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
TMR1GIP
TMR2IP
TMR1IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RC1IP: EUSARTx Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TX1IP: EUSARTx Transmit Interrupt Priority bit
x = Bit is unknown
1 = High priority
0 = Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
TMR1GIP: Timer1 Gate Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
2010-2017 Microchip Technology Inc.
DS30009977G-page 157
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REGISTER 10-15: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
OSCFIP
—
—
—
BCLIP
HLVDIP
TMR3IP
TMR3GIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6-4
Unimplemented: Read as ‘0’
bit 3
BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
HLVDIP: High/Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR3GIP: TMR3 Gate Interrupt Priority bit
1 = High priority
0 = Low priority
DS30009977G-page 158
x = Bit is unknown
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
REGISTER 10-16: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U-0
—
—
RC2IP
TX2IP
CTMUIP
CCP2IP
CCP1IP
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5
RC2IP: EUSARTx Receive Priority Flag bit
1 = High priority
0 = Low priority
bit 4
TX2IP: EUSARTx Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
CTMUIP: CTMU Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
CCP1IP: ECCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
Unimplemented: Read as ‘0’
2010-2017 Microchip Technology Inc.
x = Bit is unknown
DS30009977G-page 159
PIC18F66K80 FAMILY
REGISTER 10-17: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4
R/W-1
R/W-1
R/W-1
R/W-1
U-0
R/W-1
R/W-1
R/W-1
TMR4IP
EEIP
CMP2IP
CMP1IP
—
CCP5IP
CCP4IP
CCP3IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
TMR4IP: TMR4 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
EEIP: EE Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
CMP2IP: CMP2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
CMP1IP: CMP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP5IP: CCP5 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
CCP4IP: CCP4 Interrupt Priority bit
1 = High priority
0 = Low priority
bit
CCP3IP: CCP3 Interrupt Priority bits
1 = High priority
0 = Low priority
DS30009977G-page 160
x = Bit is unknown
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
REGISTER 10-18: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IRXIP
WAKIP
ERRIP
TXB2IP
TXB1IP
TXB0IP
RXB1IP
RXB0IP/
FIFOFIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
IRXIP: Invalid Message Received Interrupt Priority bits
1 = High priority
0 = Low priority
bit 6
WAKIP: Bus Wake-up Activity Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
ERRIP: CAN Bus Error Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TXB2IP: Transmit Buffer 2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
TXB1IP: Transmit Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
TXB0IP: Transmit Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
RXB1IP: Receive Buffer 1 Interrupt Priority bit
Mode 0:
1 = High priority for Receive Buffer 1
0 = Low priority for Receive Buffer 1
Modes 1 and 2:
1 = High priority for received messages
0 = Low priority for received messages
bit 0
RXB0IP/FIFOFIP: Receive Buffer 0 Interrupt Priority bit
Mode 0:
1 = High priority for Receive Buffer 0
0 = Low priority for Receive Buffer 0
Mode 1:
Unimplemented: Read as ‘0’
Mode 2:
FIFOFIE: FIFO Full Interrupt Flag bit
1 = High priority
0 = Low priority
2010-2017 Microchip Technology Inc.
x = Bit is unknown
DS30009977G-page 161
PIC18F66K80 FAMILY
10.5
RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
modes. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 10-19: RCON: RESET CONTROL REGISTER
R/W-0
R/W-1
R/W-1
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
SBOREN
CM
RI
TO
PD
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enables priority levels on interrupts
0 = Disables priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
SBOREN: Software BOR Enable bit
For details of bit operation, see Register 5-1.
bit 5
CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has not occurred
0 = A Configuration Mismatch Reset has occurred (must be subsequently set in software)
bit 4
RI: RESET Instruction Flag bit
For details of bit operation, see Register 5-1.
bit 3
TO: Watchdog Timer Time-out Flag bit
For details of bit operation, see Register 5-1.
bit 2
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 5-1.
bit 1
POR: Power-on Reset Status bit
For details of bit operation, see Register 5-1.
bit 0
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 5-1.
DS30009977G-page 162
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
10.6
INTx Pin Interrupts
10.7
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge. If
that bit is clear, the trigger is on the falling edge.
When a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Before re-enabling the interrupt, the flag bit
(INTxIF) must be cleared in software in the Interrupt
Service Routine.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake up the processor from the power-managed
modes, if bit, INTxIE, was set prior to going into the
power-managed modes. If the Global Interrupt Enable
bit (GIE) is set, the processor will branch to the interrupt
vector following wake-up.
The interrupt priority for INT1, INT2 and INT3 is
determined by the value contained in the Interrupt
Priority bits, INT1IP (INTCON3), INT2IP
(INTCON3) and INT3IP (INTCON2).
TMR0 Interrupt
In 8-bit mode (the default), an overflow in the TMR0
register (FFh 00h) will set flag bit, TMR0IF. In 16-bit
mode, an overflow in the TMR0H:TMR0L register pair
(FFFFh 0000h) will set TMR0IF.
The interrupt can be enabled/disabled by setting/clearing
enable bit, TMR0IE (INTCON). Interrupt priority for
Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2). For further
details on the Timer0 module, see Section 13.0 “Timer0
Module”.
10.8
PORTB Interrupt-on-Change
An input change on PORTB sets flag bit, RBIF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON), and
each individual pin can be enabled/disabled by its
corresponding bit in the IOCB register.
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2).
There is no priority bit associated with INT0; it is always
a high-priority interrupt source.
REGISTER 10-20: IOCB: INTERRUPT-ON-CHANGE PORTB CONTROL REGISTER
R/W-0
(1)
IOCB7
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
IOCB6(1)
IOCB5(1)
IOCB4(1)
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
IOCB: Interrupt-on-Change PORTB Control bits(1)
1 = Interrupt-on-change is enabled
0 = Interrupt-on-change is disabled
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
Interrupt-on-change also requires that the RBIE bit of the INTCON register be set.
2010-2017 Microchip Technology Inc.
DS30009977G-page 163
PIC18F66K80 FAMILY
10.9
If a fast return from interrupt is not used (see
Section 6.3 “Data Memory Organization”), the user
may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine (ISR).
Depending on the user’s application, other registers
also may need to be saved.
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack.
Example 10-1 saves and restores the WREG, STATUS
and BSR registers during an Interrupt Service Routine.
EXAMPLE 10-1:
MOVWF
MOVFF
MOVFF
;
; USER
;
MOVFF
MOVF
MOVFF
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
ISR CODE
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
TABLE 10-1:
Name
; Restore BSR
; Restore WREG
; Restore STATUS
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
PIR1
PSPIP
ADIF
RC1IF
TX1IF
SSPIF
TMR1GIF
TMR2IF
TMR1IF
PIR2
OSCFIF
—
—
—
BCLIF
HLVDIF
TMR3IF
TMR3GIF
PIR3
—
—
RC2IF
TX2IF
CTMUIF
CCP2IF
CCP1IF
—
PIR4
TMR4IF
EEIF
CMP2IF
CMP1IF
—
CCP5IF
CCP4IF
CCP3IF
PIR5
IRXIF
WAKIF
ERRIF
TXB2IF
TXB1IF
TXB0IF
RXB1IF
RXB0IF
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
TMR1GIE
TMR2IE
TMR1IE
PIE2
OSCFIE
—
—
—
BCLIE
HLVDIE
TMR3IE
TMR3GIE
PIE3
—
—
RC2IE
TX2IE
CTMUIE
CCP2IE
CCP1IE
—
PIE4
TMR4IE
EEIE
CCP2IE
CMP1IE
—
CCP5IE
CCP4IE
CCP3IE
PIE5
IRXIE
WAKIE
ERRIE
TXB2IE
TXB1IE
TXB0IE
RXB1IE
RXB0IE
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
TMR1GIP
TMR2IP
TMR1IP
IPR2
OSCFIP
—
—
—
BCLIP
HLVDIP
TMR3IP
TMR3GIP
IPR3
—
—
RC2IP
TX2IP
CTMUIP
CCP2IP
CCP1IP
—
IPR4
TMR4IP
EEIP
CMP2IP
CMP1IP
—
CCP5IP
CCP4IP
CCP3IP
IPR5
IRXIP
WAKIP
ERRIP
TXB2IP
TXB1IP
TXB0IP
RXB1IP
RXB0IP
RCON
IPEN
SBOREN
CM
RI
TO
PD
POR
BOR
Legend: Shaded cells are not used by the interrupts.
DS30009977G-page 164
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
11.0
I/O PORTS
11.1
Depending on the device selected and features
enabled, there are up to seven ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three memory mapped registers for its
operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Output Latch register)
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register, writes
to the Output Latch (LAT) register.
Setting a TRIS bit (= 1) makes the corresponding port
pin an input (putting the corresponding output driver in
a High-Impedance mode). Clearing a TRIS bit (= 0)
makes the corresponding port pin an output (i.e., put
the contents of the corresponding LAT bit on the
selected pin).
The Output Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
the PORT register.
I/O Port Pin Capabilities
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than VDD input levels.
All of the digital ports are 5.5V input tolerant. The
analog ports have the same tolerance, having clamping
diodes implemented internally.
11.1.1
When used as digital I/O, the output pin drive strengths
vary, according to the pins’ grouping to meet the needs
for a variety of applications. In general, there are two
classes of output pins, in terms of drive capability:
• Outputs that are designed to drive higher current
loads, such as LEDs:
- PORTA
– PORTB
- PORTC
• Outputs with lower drive levels, but capable of
driving normal digital circuit loads with a high input
impedance. Able to drive LEDs, but only those
with smaller current requirements:
– PORTE(1)
- PORTD(1)
(2)
- PORTF
– PORTG(2)
Note 1: These ports are not available on 28-pin
devices.
2: These ports are not available on 28-pin
or 40/44-pin devices
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 11-1.
FIGURE 11-1:
GENERIC I/O PORT
OPERATION
RD LAT
Data
Bus
WR LAT
or PORT
D
Q
I/O Pin(1)
WR TRIS
For more details, see “Absolute Maximum Ratings” in
Section 31.0 “Electrical Characteristics”.
11.1.2
PULL-UP CONFIGURATION
Five of the I/O ports (PORTB, PORTD, PORTE,
PORTF and PORTG) implement configurable weak
pull-ups on all pins. These are internal pull-ups that
allow floating digital input signals to be pulled to a
consistent level without the use of external resistors.
The pull-ups are enabled with a single bit for each of the
ports: RBPU (INTCON2) for PORTB, and RDPU,
REPU, RFPU and RGPU (PADCFG1) for the
other ports.
CKx
Data Latch
D
PIN OUTPUT DRIVE
Q
CKx
TRIS Latch
Input
Buffer
Additionally, the PORTB pull-up resistors can be
enabled individually using the WPUB register. Each bit
in the register corresponds to a bit on PORTB.
RD TRIS
Q
D
ENEN
RD PORT
Note 1:
I/O pins have diode protection to VDD and VSS.
2010-2017 Microchip Technology Inc.
DS30009977G-page 165
PIC18F66K80 FAMILY
REGISTER 11-1:
R/W-0
RDPU
PADCFG1: PAD CONFIGURATION REGISTER
R/W-0
(1)
(1)
REPU
R/W-0
RFPU
(2)
R/W-0
(2)
RGPU
U-0
U-0
U-0
R/W-0
—
—
—
CTMUDS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RDPU: PORTD Pull-up Enable bit(1)
1 = PORTD pull-up resistors are enabled by individual port latch values
0 = All PORTD pull-up resistors are disabled
bit 6
REPU: PORTE Pull-up Enable bit(1)
1 = PORTE pull-up resistors are enabled by individual port latch values
0 = All PORTE pull-up resistors are disabled
bit 5
RFPU: PORTF Pull-up Enable bit(2)
1 = PORTF pull-up resistors are enabled by individual port latch values
0 = All PORTF pull-up resistors are disabled
bit 4
RGPU: PORTG Pull-up Enable bit(2)
1 = PORTG pull-up resistors are enabled by individual port latch values
0 = All PORTG pull-up resistors are disabled
bit 3-1
Unimplemented: Read as ‘0’
bit 0
CTMUDS: CTMU Comparator Data Select bit
1 = External comparator (with output on pin CTDIN) is used for CTMU compares
0 = Internal comparator (CMP2) is used for CTMU compares
Note 1:
2:
These bits are unimplemented on 28-pin devices.
These bits are unimplemented on 40-pin devices.
REGISTER 11-2:
WPUB: WEAK PULL-UP PORTB ENABLE REGISTER
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
WPUB: Weak Pull-Up Enable Register bits
1 = Pull-up is enabled on corresponding PORTB pin when RBPU = 0 and the pin is an input
0 = Pull-up is disabled on corresponding PORTB pin
DS30009977G-page 166
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
11.1.3
OPEN-DRAIN OUTPUTS
FIGURE 11-2:
The output pins for several peripherals are also
equipped with a configurable, open-drain output option.
This allows the peripherals to communicate with
external pull-up voltage.
USING THE OPEN-DRAIN
OUTPUT (USARTx SHOWN
AS EXAMPLE)
5.5V
+5.5V
PIC18F66K80
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the USARTs, the MSSP module (in SPI mode) and
the CCP modules. This option is selectively enabled by
setting the open-drain control bits in the ODCON
register.
VDD
5V
TXX
(at logic ‘1’)
5.5V
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor
provided by the user.
REGISTER 11-3:
ODCON: PERIPHERAL OPEN-DRAIN CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSPOD
CCP5OD
CCP4OD
CCP3OD
CCP2OD
CCP1OD
U2OD
U1OD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SSPOD: SPI Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 6
CCP5OD: CCP5 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 5
CCP4OD: CCP4 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 4
CCP3OD: CCP3 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 3
CCP2OD: CCP2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 2
CCP1OD: CCP1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 1
U2OD: UART2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
bit 0
U1OD: UART1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
2010-2017 Microchip Technology Inc.
x = Bit is unknown
DS30009977G-page 167
PIC18F66K80 FAMILY
11.1.4
ANALOG AND DIGITAL PORTS
11.1.5
Many of the ports multiplex analog and digital functionality, providing a lot of flexibility for hardware designers.
PIC18F66K80 family devices can make any analog pin
analog or digital, depending on an application’s needs.
The ports’ analog/digital functionality is controlled by
the registers: ANCON0 and ANCON1.
PORT SLEW RATE
The output slew rate of each port is programmable to
select either the standard transition rate, or a reduced
transition rate of ten percent of the standard transition
time, to minimize EMI. The reduced transition time is
the default slew rate for all ports.
Setting these registers makes the corresponding pins
analog and clearing the registers makes the ports digital. For details on these registers, see Section 23.0
“12-Bit Analog-to-Digital Converter (A/D) Module”
REGISTER 11-4:
SLRCON: SLEW RATE CONTROL REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SLRG(1)
SLRF(1)
SLRE(2)
SLRD(2)
SLRC(2)
SLRB
SLRA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6
SLRG: PORTG Slew Rate Control bit(1)
1 = All output pins on PORTG slew at 0.1 the standard rate
0 = All output pins on PORTG slew at standard rate
bit 5
SLRF: PORTF Slew Rate Control bit(1)
1 = All output pins on PORTF slew at 0.1 the standard rate
0 = RAll output pins on PORTF slew at standard rate
bit 4
SLRE: PORTE Slew Rate Control bit(2)
1 = All output pins on PORTE slew at 0.1 the standard rate
0 = All output pins on PORTE slew at standard rate
bit 3
SLRD: PORTD Slew Rate Control bit(2)
1 = All output pins on PORTD slew at 0.1 the standard rate
0 = All output pins on PORTD slew at standard rate
bit 2
SLRC: PORTC Slew Rate Control bit(2)
1 = All output pins on PORTC slew at 0.1 the standard rate
0 = All output pins on PORTC slew at standard rate
bit 1
SLRB: PORTB Slew Rate Control bit
1 = All output pins on PORTB slew at 0.1 the standard rate
0 = All output pins on PORTB slew at standard rate
bit 0
SLRA: PORTA Slew Rate Control bit
1 = All output pins on PORTA slew at 0.1 the standard rate
0 = All output pins on PORTA slew at standard rate
Note 1:
2:
x = Bit is unknown
These bits are unimplemented and read back as ‘0’ on 28-pin and 40/44-pin devices.
These bits are unimplemented and read back as ‘0’ on 28-pin devices.
DS30009977G-page 168
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
11.2
PORTA, TRISA and
LATA Registers
PORTA is a seven-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers
are TRISA and LATA.
RA5 and RA are multiplexed with analog inputs
for the A/D Converter.
The operation of the analog inputs as A/D Converter
inputs is selected by clearing or setting the ANSELx
control bits in the ANCON1 register. The corresponding
TRISA bits control the direction of these pins, even
when they are being used as analog inputs. The user
must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Note:
RA5 and RA are configured as
analog inputs on any Reset and are read
as ‘0’.
OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally
serve as the external circuit connections for the external (primary) oscillator circuit (HS Oscillator modes) or
the external clock input and output (EC Oscillator
modes). In these cases, RA6 and RA7 are not available
as digital I/O and their corresponding TRIS and LAT
bits are read as ‘0’. When the device is configured to
use HF-INTOSC, MF-INTOSC or LF-INTOSC as the
default oscillator mode, RA6 and RA7 are automatically
configured as digital I/O; the oscillator and clock
in/clock out functions are disabled.
RA5 has additional functionality for Timer1 and Timer3.
It can be configured as the Timer1 clock input or the
Timer3 external clock gate input.
EXAMPLE 11-1:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
2010-2017 Microchip Technology Inc.
PORTA
;
;
LATA
;
;
00h
;
ANCON1 ;
0BFh
;
;
TRISA
;
;
INITIALIZING PORTA
Initialize PORTA by
clearing output latches
Alternate method to
clear output data latches
Configure A/D
for digital inputs
Value used to initialize
data direction
Set RA as inputs,
RA as output
DS30009977G-page 169
PIC18F66K80 FAMILY
TABLE 11-1:
PORTA FUNCTIONS
Pin Name
RA0/CVREF/AN0/
ULPWU
RA1/AN1/C1INC
Function
TRIS
Setting
I/O
I/O
Type
RA0
0
O
DIG
LATA data output; not affected by analog input.
1
I
ST
PORTA data input; disabled when analog input is enabled.
CVREF
x
O
ANA Comparator voltage reference output. Enabling this feature disables digital I/O.
AN0
1
I
ANA A/D Input Channel 0. Default input configuration on POR; does not affect
digital output.
ULPWU
1
O
DIG
RA1
0
O
DIG
LATA data output; not affected by analog input.
1
I
ST
PORTA data input; disabled when analog input is enabled.
1
I
ANA A/D Input Channel 1. Default input configuration on POR; does not affect
digital output.
AN1
RA2/VREF-/AN2/
C2INC
RA3/VREF+/AN3
RA5/AN4/C2INB/
HLVDIN/T1CKI/
SS/CTMUI
RA6/OSC2/
CLKOUT
RA7/OSC1/CLKIN
Legend:
Note 1:
2:
Ultra Low-Power Wake-up input.
C1INC(1)
x
I
ANA Comparator 1 Input C.
RA2
0
O
DIG
LATA data output; not affected by analog input.
1
I
ST
PORTA data input; disabled when analog functions are enabled.
VREF-
1
I
ANA A/D and comparator low reference voltage input.
AN2
1
I
ANA A/D Input Channel 2. Default input configuration on POR.
C2INC(1)
x
I
ANA Comparator 2 Input C.
RA3
0
O
DIG
LATA data output; not affected by analog input.
1
I
ST
PORTA data input; disabled when analog input is enabled.
VREF+
1
I
ANA A/D Input Channel 3. Default input configuration on POR.
AN3
1
I
ANA A/D and comparator high reference voltage input.
RA5
0
O
DIG
LATA data output; not affected by analog input.
1
I
ST
PORTA data input; disabled when analog input is enabled.
AN4
1
I
ANA A/D Input Channel 4. Default configuration on POR.
C2INB(2)
1
I
ANA Comparator 2 Input B.
HLVDIN
1
I
ANA High/Low-Voltage Detect external trip point input.
T1CKI
x
I
ST
Timer1 clock input.
SS
1
I
ST
Slave select input for MSSP module.
CTMUI(2)
x
O
—
CTMU pulse generator charger for the C2INB comparator input.
RA6
0
O
DIG
LATA data output; disabled when FOSC2 Configuration bit is set.
1
I
ST
PORTA data input; disabled when FOSC2 Configuration bit is set.
OSC2
x
O
ANA Main oscillator feedback output connection (HS, XT and LP modes).
CLKOUT
x
O
DIG
RA7
0
O
DIG
LATA data output; disabled when FOSC2 Configuration bit is set.
1
I
ST
PORTA data input; disabled when FOSC2 Configuration bit is set.
OSC1
x
I
ANA Main oscillator input connection (HS, XT, and LP modes).
CLKIN
x
I
ANA Main external clock source input (EC modes).
System cycle clock output (FOSC/4) (EC and INTOSC modes).
O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
This pin assignment is unavailable for 28-pin devices (PIC18F2XK80).
This pin assignment is only available for 28-pin devices (PIC18F2XK80).
TABLE 11-2:
Name
Description
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA7(1)
RA6(1)
RA5
—
RA3
RA2
RA1
RA0
LATA
LATA7(1)
LATA6(1)
LATA5
—
LATA3
LATA2
LATA1
LATA0
TRISA
TRISA7(1)
TRISA6(1)
TRISA5
—
TRISA3
TRISA2
TRISA1
TRISA0
ANSEL7
ANSEL6
ANSEL5
ANSEL4
ANSEL3
ANSEL2
ANSEL1
ANSEL0
PORTA
ANCON0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins,
they are disabled and read as ‘x’.
DS30009977G-page 170
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
11.3
PORTB, TRISB and
LATB Registers
PORTB is an eight-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISB and LATB. All pins on PORTB are digital only.
EXAMPLE 11-2:
CLRF
PORTB
CLRF
LATB
MOVLW
0CFh
MOVWF
TRISB
INITIALIZING PORTB
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RB as inputs
RB as outputs
RB as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur. Any RB
pins that are configured as outputs are excluded from
the interrupt-on-change comparison.
Comparisons with the input pins (of RB) are
made with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB are ORed
together to generate the RB Port Change Interrupt with
Flag bit, RBIF (INTCON).
This interrupt can wake the device from
power-managed modes. To clear the interrupt in the
Interrupt Service Routine:
1.
2.
Perform any read or write of PORTB (except
with the MOVFF (ANY), PORTB instruction).
Wait one instruction cycle (such as executing a
NOP instruction).
This ends the mismatch condition.
3.
Clear flag bit, RBIF.
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after a one TCY delay.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
The RB pins are multiplexed as CTMU edge
inputs. RB5 has an additional function for Timer3 and
Timer1. It can be configured for Timer3 clock input or
Timer1 external clock gate input.
2010-2017 Microchip Technology Inc.
DS30009977G-page 171
PIC18F66K80 FAMILY
TABLE 11-3:
Pin Name
PORTB FUNCTIONS
Function
TRIS
Setting
I/O
I/O Type
RB0
0
O
DIG
LATB data output.
1
I
ST
PORTB data input; weak pull-up when RBPU bit is cleared.
AN10
1
I
ANA
A/D Input Channel 10 and Comparator C1+ input. Default input
configuration on POR.
C1INA(1)
1
I
ANA
FLT0
x
I
ST
Enhanced PWM Fault input for ECCPx.
INT0
1
I
ST
External Interrupt 0 input.
RB1
0
O
DIG
LATB data output.
1
I
ST
PORTB data input; weak pull-up when RBPU bit is cleared.
AN8
1
I
ANA
C1INB(1)
1
I
ANA
Comparator 1 Input B.
P1B(1)
0
O
DIG
ECCP1 PWM Output B. May be configured for tri-state during
Enhanced PWM shutdown events.
CTDIN
1
I
ST
CTMU pulse delay input.
INT1
1
I
ST
External Interrupt 1 input.
RB2
0
O
DIG
LATB data output.
1
I
ST
PORTB data input; weak pull-up when RBPU bit is cleared.
CANTX(2)
0
O
DIG
CAN bus TX.
C1OUT(1)
0
O
DIG
Comparator 1 output; takes priority over port data.
P1C(1)
0
O
DIG
ECCP1 PWM Output C. May be configured for tri-state during
Enhanced PWM.
CTED1
x
I
ST
CTMU Edge 1 input.
INT2
1
I
ST
External Interrupt 2.
RB3
0
O
DIG
LATB data output.
1
I
ST
PORTB data input; weak pull-up when RBPU bit is cleared.
CANRX(2)
1
I
ST
CAN bus RX.
C2OUT(1)
x
I
ST
CTMU Edge 2 input.
(1)
P1D
0
O
DIG
ECCP1 PWM Output D. May be configured for tri-state during
Enhanced PWM.
CTED2
x
I
ST
CTMU Edge 2 input.
INT3
1
I
ST
External Interrupt 3 input.
RB0/AN10/C1INA
FLT0/INT0
RB1/AN8/C1INB/
P1B/CTDIN/INT1
RB2/CANTX/C1OUT/
P1C/CTED1/INT2
RB3/CANRX/
C2OUT/P1D/
CTED2/INT3
Legend:
Note 1:
2:
3:
4:
Description
Comparator 1 Input A.
A/D Input Channel 8 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
This pin assignment is only available for 28-pin devices (PIC18F2XK80).
This is the default pin assignment for CANRX and CANTX when the CANMX Configuration bit is set.
This is the default pin assignment for T0CKI when the T0CKMX Configuration bit is set.
This is the default pin assignment for T3CKI for 28, 40 and 44-pin devices. This is the alternate pin assignment for
T3CKI for 64-pin devices when T3CKMX is cleared.
DS30009977G-page 172
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 11-3:
PORTB FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O Type
RB4/AN9/C2INA/
ECCP1/P1A/CTPLS/
KBI0
RB4
0
O
DIG
LATB data output.
1
I
ST
PORTB data input; weak pull-up when RBPU bit is cleared.
AN9
1
I
ANA
C2INA(1)
2
I
ANA
Comparator 2 Input A.
ECCP1(1)
0
O
DIG
ECCP1 compare output and ECCP1 PWM output. Takes priority
over port data.
1
I
ST
ECCP1 capture input.
P1A(1)
0
O
DIG
ECCP1 Enhanced PWM output, Channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority
over port data.
CTPLS
x
O
DIG
CTMU pulse generator output.
KBI0
1
I
ST
Interrupt-on-pin change.
RB5
0
O
DIG
LATB data output.
1
I
ST
PORTB data input; weak pull-up when RBPU bit is cleared.
T0CKI(3)
x
I
ST
Timer0 clock input.
(4)
x
I
ST
Timer3 clock input.
0
O
DIG
CCP5 compare/PWM output. Takes priority over port data.
1
I
ST
CCP5 capture input.
KBI1
1
I
ST
Interrupt-on-pin change.
RB6
0
O
DIG
LATB data output.
1
I
ST
PORTB data input; weak pull-up when RBPU bit is cleared.
RB5/T0CKI/T3CKI/
CCP5/KBI1
T3CKI
CCP5
RB6/PGC/TX2/CK2/
KBI2
RB7/PGD/T3G/RX2/
DT2/KBI3
PGC
x
I
ST
Serial execution (ICSP™) clock input for ICSP and ICD operation.
0
O
DIG
Asynchronous serial data output (EUSARTx module); takes priority
over port data.
CK2(1)
0
O
DIG
Synchronous serial clock output (EUSARTx module); user must
configure as an input.
1
I
ST
Synchronous serial clock input (EUSARTx module); user must
configure as an input.
Interrupt-on-pin change.
KBI2
1
I
ST
RB7
0
O
DIG
LATB data output.
1
I
ST
PORTB data input; weak pull-up when RBPU bit is cleared.
x
O
DIG
Serial execution data output for ICSP and ICD operation.
x
I
ST
Serial execution data input for ICSP and ICD operation.
T3G
x
I
ST
Timer3 external clock gate input.
RX2(1)
1
I
ST
Asynchronous serial receive data input (EUSARTx module).
DT2(1)
1
O
DIG
Synchronous serial data output (AUSART module); takes priority
over port data.
1
I
ST
Synchronous serial data input (AUSART module); user must
configure as an input.
1
I
ST
Interrupt-on-pin change.
KBI3
Note 1:
2:
3:
4:
A/D Input Channel 9 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
TX2(1)
PGD
Legend:
Description
O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
This pin assignment is only available for 28-pin devices (PIC18F2XK80).
This is the default pin assignment for CANRX and CANTX when the CANMX Configuration bit is set.
This is the default pin assignment for T0CKI when the T0CKMX Configuration bit is set.
This is the default pin assignment for T3CKI for 28, 40 and 44-pin devices. This is the alternate pin assignment for
T3CKI for 64-pin devices when T3CKMX is cleared.
2010-2017 Microchip Technology Inc.
DS30009977G-page 173
PIC18F66K80 FAMILY
TABLE 11-4:
Name
PORTB
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
ODCON
SSPOD
CCP5OD
CCP4OD
CCP3OD
CCP2OD
CCP1OD
U2OD
U1OD
ANCON1
—
ANSEL14
ANSEL13
ANSEL12
ANSEL11
ANSEL10
ANSEL9
ANSEL8
INTCON
Legend: Shaded cells are not used by PORTB.
DS30009977G-page 174
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
11.4
PORTC, TRISC and
LATC Registers
PORTC is an eight-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISC and LATC. Only PORTC pins, RC2 through
RC7, are digital only pins.
PORTC is multiplexed with CCP, MSSP and EUSARTx
peripheral functions (Table 11-5). The pins have
Schmitt Trigger input buffers. The pins for CCP, SPI
and EUSARTx are also configurable for open-drain
output whenever these functions are active.
Open-drain configuration is selected by setting the
SSPOD, CCPxOD and U1OD control bits in the
ODCON register.
RC1 is configurable for open-drain output when CCP2
is active on this pin. Open-drain configuration is
selected by setting the CCP2OD control bit
(ODCON).
2010-2017 Microchip Technology Inc.
When enabling peripheral functions, use care in defining TRIS bits for each PORTC pin. Some peripherals
can override the TRIS bit to make a pin an output or
input. Consult the corresponding peripheral section for
the correct TRIS bit settings.
Note:
These pins are configured as digital inputs
on any device Reset.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 11-3:
CLRF
PORTC
CLRF
LATC
MOVLW
0CFh
MOVWF
TRISC
INITIALIZING PORTC
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTC by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RC as inputs
RC as outputs
RC as inputs
DS30009977G-page 175
PIC18F66K80 FAMILY
TABLE 11-5:
Pin Name
RC0/SOSCO/
SCLKI
PORTC FUNCTIONS
Function
TRIS
Setting
I/O
I/O
Type
RC0
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
1
I
ST
SOSC oscillator output.
Digital clock input; enabled when SOSC oscillator is disabled.
SOSCO
RC1/SOSCI
RC2/T1G/
CCP2
RC3/REFO/
SCL/SCK
SCLKI
1
I
ST
RC1
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
SOSCI
x
I
ANA SOSC oscillator input.
RC2
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
T1G
x
I
ST
Timer1 external clock gate input.
CCP2
0
O
DIG
CCP2 compare/PWM output; takes priority over port data.
CCP2 capture input.
1
I
ST
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
REFO
x
O
DIG
Reference output clock.
SCL
0
O
DIG
I2C™ clock output (MSSP module); takes priority over port data.
1
I
2
I C
0
O
DIG
SPI clock output (MSSP module); takes priority over port data.
1
I
ST
SPI clock input (MSSP module).
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
1
O
DIG
I2C data output (MSSP module); takes priority over port data.
1
I
I2 C
I2C data input (MSSP module); input type depends on module setting.
SPI data input (MSSP module).
RC3
SCK
RC4/SDA/SDI
RC4
SDA
RC5/SDO
RC6/CANTX/
TX1/CK1/
CCP3
SDI
1
I
ST
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
SDO
0
O
DIG
SPI data output (MSSP module).
RC6
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
CANTX(2)
0
O
DIG
CAN bus TX.
TX1(1)
0
O
DIG
Asynchronous serial data output (EUSARTx module); takes priority over port data.
(1)
CCP3
Note 1:
2:
I2C clock input (MSSP module); input type depends on module setting.
RC5
CK1
Legend:
Description
0
O
DIG
Synchronous serial clock output (EUSARTx module); user must configure as an input.
1
I
ST
Synchronous serial clock input (EUSARTx module); user must configure as an input.
0
O
DIG
CCP3 compare/PWM output. Takes priority over port data.
1
I
ST
CCP3 capture input.
O = Output; I = Input; I2C = I2C/SMBus; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input; x
= Don’t care (TRIS bit does not affect port direction or is overridden for this option)
The pin assignment for 28, 40 and 44-pin devices (PIC18F2XK80 and PIC18F4XK80).
The alternate pin assignment for CANRX and CANTX on 28, 40 and 44-pin devices (PIC18F4XK80) when the CANMX
Configuration bit is set.
DS30009977G-page 176
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 11-5:
Pin Name
RC7/CANRX/
RX1/DT1/
CCP4
PORTC FUNCTIONS (CONTINUED)
Function
TRIS
Setting
I/O
I/O
Type
RC7
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
CANRX(2)
1
I
ST
CAN bus RX.
RX1(1)
1
I
ST
Asynchronous serial receive data input (EUSARTx module).
DT1(1)
1
O
DIG
Synchronous serial data output (EUSARTx module); takes priority over port data.
1
I
ST
Synchronous serial data input (EUSARTx module); user must configure as an
input.
0
O
DIG
CCP4 compare/PWM output; takes priority over port data.
1
I
ST
CCP4 capture input.
CCP4
Legend:
Note 1:
2:
O = Output; I = Input; I2C = I2C/SMBus; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input; x
= Don’t care (TRIS bit does not affect port direction or is overridden for this option)
The pin assignment for 28, 40 and 44-pin devices (PIC18F2XK80 and PIC18F4XK80).
The alternate pin assignment for CANRX and CANTX on 28, 40 and 44-pin devices (PIC18F4XK80) when the CANMX
Configuration bit is set.
TABLE 11-6:
Name
Description
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
LATC
LATC7
LATBC6
LATC5
LATCB4
LATC3
LATC2
LATC1
LATC0
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
ODCON
SSPOD
CCP5OD
CCP4OD
CCP3OD
CCP2OD
CCP1OD
U2OD
U1OD
PORTC
Legend: Shaded cells are not used by PORTC.
2010-2017 Microchip Technology Inc.
DS30009977G-page 177
PIC18F66K80 FAMILY
11.5
PORTD, TRISD and
LATD Registers
PORTD is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISD and LATD.
Note:
RD3 has a CTMU functionality.
PORTD is unavailable on 28-pin devices.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note:
PORTD can also be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control
bit, PSPMODE (PSPCON). In this mode, the input
buffers are ST. For additional information, see
Section 11.9 “Parallel Slave Port”.
These pins are configured as digital inputs
on any device Reset.
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by setting bit, RDPU (PADCFG1). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
DS30009977G-page 178
EXAMPLE 11-4:
CLRF
PORTD
CLRF
LATD
MOVLW
0CFh
MOVWF
TRISD
INITIALIZING PORTD
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTD by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RD as inputs
RD as outputs
RD as inputs
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 11-7:
Pin Name
RD0/C1INA/
PSP0
RD1/C1INB/
PSP1
RD2/C2INA/
PSP2
RD3/C2INB/
CTMUI/PSP3
RD4/ECCP1/
P1A/PSP4
RD5/P1B/PSP5
RD6/TX2/CK2
P1C/PSP6
Legend:
Note 1:
PORTD FUNCTIONS
Function
TRIS
Setting
I/O
I/O Type
RD0
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
Comparator 1 Input A.
Description
C1INA
1
I
ANA
PSP0
x
I/O
ST
(1)
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
Comparator 1 Input B.
RD1
Parallel Slave Port data.
C1INB(1)
1
I
ANA
PSP1(1)
x
I/O
ST
RD2
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
Comparator 2 Input A.
Parallel Slave Port data.
C2INA
1
I
ANA
PSP2
x
I/O
ST
RD3
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
Parallel Slave Port data.
C2INB
1
I
ANA
CTMUI
x
I
—
Comparator 2 Input B.
PSP3
x
I/O
ST
Parallel Slave Port data.
RD4
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
ECCP1
0
O
DIG
ECCP1 compare output and ECCP1 PWM output; takes priority over
port data.
CTMU pulse generator charger for the C2INB comparator input.
1
I
ST
ECCP1 capture input.
P1A
0
O
DIG
ECCP1 Enhanced PWM output, Channel A. May be configured for
tri-state during Enhanced PWM shutdown events; takes priority over
port data.
PSP4
x
I/O
ST
Parallel Slave Port data.
RD5
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
P1B
0
O
DIG
ECCP1 Enhanced PWM output, Channel B. May be configured for
tri-state during Enhanced PWM shutdown events; takes priority over
port data.
PSP5
x
I/O
ST
Parallel Slave Port data.
RD6
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
TX2(1)
0
O
DIG
Asynchronous serial data output (EUSARTx module); takes priority
over port data.
CK2(1)
0
O
DIG
Synchronous serial clock output (EUSARTx module); user must
configure as an input.
1
I
ST
Synchronous serial clock input (EUSARTx module); user must
configure as an input.
P1C
0
O
DIG
ECCP1 Enhanced PWM output, Channel C. May be configured for
tri-state during Enhanced PWM.
PSP6
x
I/O
ST
Parallel Slave Port data.
O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
This is the pin assignment for 40 and 44-pin devices (PIC18F4XK80).
2010-2017 Microchip Technology Inc.
DS30009977G-page 179
PIC18F66K80 FAMILY
TABLE 11-7:
Pin Name
RD7/RX2/DT2/
P1D/PSP7
Legend:
Note 1:
PORTD
LATD
Function
TRIS
Setting
I/O
I/O Type
RD7
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
Description
RX2(1)
1
I
ST
Asynchronous serial receive data input (EUSARTx module).
DT2(1)
1
O
DIG
Synchronous serial data output (EUSARTx module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSARTx module); user must
configure as an input.
P1D
0
O
DIG
ECCP1 Enhanced PWM output, Channel D. May be configured for
tri-state during Enhanced PWM.
PSP7
x
I/O
ST
Parallel Slave Port data.
O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
This is the pin assignment for 40 and 44-pin devices (PIC18F4XK80).
TABLE 11-8:
Name
PORTD FUNCTIONS (CONTINUED)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
PADCFG1
RDPU(1)
REPU(1)
RFPU(2)
RGPU(2)
—
—
—
CTMUDS
ODCON
SSPOD
CCP5OD
CCP4OD
CCP3OD
CCP2OD
CCP1OD
U2OD
U1OD
ANCON1
—
ANSEL14
ANSEL13
ANSEL12
ANSEL11
ANSEL10
ANSEL9
ANSEL8
Legend: Shaded cells are not used by PORTD.
Note 1: These bits are unimplemented on 28-pin devices, read as ‘0’.
2: These bits are unimplemented on 28/40/44-pin devices, read as ‘0’.
DS30009977G-page 180
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
11.6
PORTE, TRISE and
LATE Registers
PORTE is a seven-bit-wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISE and LATE.
Note:
These pins are configured as digital inputs
on any device Reset.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, REPU (PADCFG1). The
TABLE 11-9:
Pin Name
RE0/AN5/RD
RE4/CANRX
CLRF
LATE
MOVLW
03h
MOVWF
TRISE
I/O
I/O Type
RE0
0
O
DIG
LATE data output.
INITIALIZING PORTE
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTE by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RE as inputs
RE as outputs
PORTE data input.
Description
1
I
ST
AN5
1
I
ANA
A/D Input Channel 5. Default input configuration on POR; does not
affect digital output.
RD
x
O
DIG
Parallel Slave Port read strobe pin.
x
I
ST
Parallel Slave Port read pin.
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
1
I
ANA
A/D Input Channel 5. Default input configuration on POR; does not
affect digital output.
C1OUT
0
O
DIG
Comparator 1 output; takes priority over port data.
WR
x
O
DIG
Parallel Slave Port write strobe pin.
x
I
ST
Parallel Slave Port write pin.
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
AN7
1
I
ANA
A/D Input Channel 7. Default input configuration on POR; does not
affect digital output.
C2OUT
0
O
DIG
Comparator 2 output; takes priority over port data.
CS
x
I
ST
Parallel Slave Port chip select.
RE3
1
I
ST
PORT data input.
RE4(1)
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
1
I
ST
CAN bus RX.
CANRX
Note 1:
2:
PORTE
TRIS
Setting
RE2
RE3
CLRF
Function
AN6
RE2/AN7/
C2OUT/CS
EXAMPLE 11-5:
PORTE FUNCTIONS
RE1
RE1/AN6/
C1OUT/WR
Legend:
PORTE is also multiplexed with the Parallel Slave Port
address lines. RE1 and RE0 are multiplexed with the
Parallel Slave Port (PSP) control signals, WR and RD.
PORTE is unavailable on 28-pin devices.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note:
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
(1,2)
O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
These bits are unavailable for 40 and 44-pin devices (PIC18F4XK0).
This is the alternate pin assignment for CANRX and CANTX on 64-pin devices (PIC18F6XK80) when the CANMX
Configuration bit is cleared.
2010-2017 Microchip Technology Inc.
DS30009977G-page 181
PIC18F66K80 FAMILY
TABLE 11-9:
Pin Name
RE5/CANTX
RE6/RX2/DT2
RE7/TX2/CK2
Legend:
Note 1:
2:
PORTE FUNCTIONS (CONTINUED)
Function
TRIS
Setting
I/O
I/O Type
RE5(1)
0
O
DIG
1
I
ST
PORTE data input.
CANTX(1,2)
0
O
DIG
CAN bus TX.
RE6(1)
0
O
DIG
LATE data output.
Description
LATE data output.
1
I
ST
PORTE data input.
RX2(1)
1
I
ST
Asynchronous serial receive data input (EUSARTx module).
DT2(1)
1
O
DIG
Synchronous serial data output (EUSARTx module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSARTx module); user must
configure as an input.
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
TX2(1)
0
O
DIG
Asynchronous serial data output (EUSARTx module); takes priority
over port data.
CK2(1)
0
O
DIG
Synchronous serial clock output (EUSARTx module); user must
configure as an input.
1
I
ST
Synchronous serial clock input (EUSARTx module); user must configure as an input.
RE7(1)
O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
These bits are unavailable for 40 and 44-pin devices (PIC18F4XK0).
This is the alternate pin assignment for CANRX and CANTX on 64-pin devices (PIC18F6XK80) when the CANMX
Configuration bit is cleared.
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
PORTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RE7(1)
RE6(1)
RE5(1)
RE4(1)
RE3
RE2
RE1
RE0
LATE
LATE7
LATE6
LATE5
LATE4
—
LATE2
LATE1
LATE0
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
—
TRISE2
TRISE1
TRISE0
PADCFG1
RDPU
REPU
RFPU(1)
RGPU(1)
—
—
—
CTMUDS
ANCON0
ANSEL7
ANSEL6
ANSEL5
ANSEL4
ANSEL3
ANSEL2
ANSEL1
ANSEL0
Legend: Shaded cells are not used by PORTE.
Note 1: These bits are unimplemented on 44-pin devices, read as ‘0’.
DS30009977G-page 182
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
11.7
PORTF, LATF and TRISF Registers
PORTF is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers are TRISF and LATF. All pins on PORTF are
implemented with Schmitt Trigger input buffers. Each pin
is individually configurable as an input or output.
EXAMPLE 11-6:
Each of the PORTF pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
done by clearing bit, RFPU (PADCFG1). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on
any device Reset.
TABLE 11-11:
Pin Name
RF0/MDMIN
RF1
RF2/MDCIN1
RF3
RF4/MDCIN2
RF5
RF6/MDOUT
Legend:
CLRF
PORTF
CLRF
LATF
MOVLW
0CEh
MOVWF
TRISF
INITIALIZING PORTF
;
;
;
;
;
;
;
;
;
;
;
;
PORTF is only available on 64-pin devices.
Note:
RF7
On device Resets, pins, RF, are
configured as analog inputs and are read
as ‘0’.
Note:
Initialize PORTF by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RF3:RF1 as inputs
RF5:RF4 as outputs
RF7:RF6 as inputs
PORTF FUNCTIONS
Function
TRIS
Setting
I/O
I/O Type
RF0
0
O
DIG
LATF data output.
1
I
ST
PORTF data input.
MDMIN
1
I
ST
Modulator source input.
RF1
0
O
DIG
LATF data output.
1
I
ST
PORTF data input.
0
O
DIG
LATF data output.
1
I
ST
PORTF data input.
Modulator Carrier Input 1.
RF2
Description
MDCIN1
1
I
ST
RF3
0
O
DIG
LATF data output.
1
I
ST
PORTF data input.
0
O
DIG
LATF data output.
1
I
ST
PORTF data input.
Modulator Carrier Input 2.
RF4
MDCIN2
1
I
ST
RF5
0
O
DIG
LATF data output.
1
I
ST
PORTF data input.
RF6
0
O
DIG
LATF data output.
1
I
ST
PORTF data input.
MDOUT
0
O
DIG
Modulator output.
RF7
0
O
DIG
LATF data output.
1
I
ST
PORTF data input.
O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Name
PORTF
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
RDPU
REPU
RFPU(1)
RGPU(1)
—
—
—
CTMUDS
PADCFG1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.
Note 1: These bits are unimplemented on 28-pin devices, read as ‘0’.
2010-2017 Microchip Technology Inc.
DS30009977G-page 183
PIC18F66K80 FAMILY
11.8
PORTG, TRISG and
LATG Registers
PORTG is a 5-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISG and LATG.
Note:
PORTG is only available on 64-pin
devices.
PORTG is multiplexed with EUSARTx and CCP, ECCP,
Analog, Comparator and Timer input functions
(Table 11-13). When operating as I/O, all PORTG pins
have Schmitt Trigger input buffers. The open-drain
functionality for the EUARTx can be configured using
ODCON.
Each of the PORTG pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is performed by clearing bit, RGPU (PADCFG1). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
put, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
EXAMPLE 11-7:
CLRF
PORTG
CLRF
LATG
MOVLW
04h
MOVWF
TRISG
INITIALIZING PORTG
;
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTG by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RG1:RG0 as
outputs
RG2 as input
RG4:RG3 as inputs
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an out-
TABLE 11-13: PORTG FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
RG0/RX1/DT1
RG0
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
RX1
1
I
ST
Asynchronous serial receive data input (EUSARTx module).
DT1
0
O
DIG
Synchronous serial data output (EUSARTx module); takes priority over port data.
1
I
ST
Synchronous serial data input (EUSARTx module); user must configure
as an input.
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
CANTX
0
O
DIG
CAN bus TX.
RG2
0
O
DIG
LATG data output.
PORTG data input.
RG1/CANTX
RG2/T3CKI
RG3/TX1/CK1
RG4/T0CKI
RG1
1
I
ST
T3CKI(2)
x
I
ST
Timer3 clock input.
RG3
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
TX1
0
O
DIG
Asynchronous serial data output (EUSARTx module); takes priority over port data.
CK1
0
O
DIG
Synchronous serial clock output (EUSARTx module); user must
configure as an input.
1
I
ST
Synchronous serial clock input (EUSARTx module); user must configure
as an input.
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
x
I
ST
Timer0 clock input.
RG4
T0CKI(1)
Legend:
Note 1:
2:
Description
O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
This is the alternate pin assignment for T0CKI on 64-pin devices when the T0CKMX Configuration bit is cleared.
This is the default pin assignment for T3CKI on 64-pin devices when the T3CKMX Configuration bit is set.
DS30009977G-page 184
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Name
PORTG
TRISG
PADCFG1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
RG4
RG3
RG2
RG1
RG0
—
—
—
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
RDPU
REPU
RFPU(1)
RGPU(1)
—
—
—
CTMUDS
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: These bits are unimplemented on 28-pin devices; read as ‘0’.
2010-2017 Microchip Technology Inc.
DS30009977G-page 185
PIC18F66K80 FAMILY
11.9
Parallel Slave Port
PORTD can function as an 8-bit-wide Parallel Slave
Port (PSP), or microprocessor port, when control bit,
PSPMODE (PSPCON), is set. The port is asynchronously readable and writable by the external world
through the RD control input pin (RE0/AN5/RD) and
WR control input pin (RE1/AN6/C1OUT/WR).
Note:
The Parallel Slave Port is available only on
40/44-pin and 64-pin devices.
The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can
read or write the PORTD latch as an eight-bit latch.
Setting bit, PSPMODE, enables port pin,
to
be
the
RD
input,
RE0/AN5/RD,
RE1/AN6/C1OUT/WR to be the WR input and
RE2/AN7/C2OUT/CS to be the CS (Chip Select)
input. For this functionality, the corresponding data
direction bits of the TRISE register (TRISE)
must be configured as inputs (= 111).
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits (PIR1
and PSPCON, respectively) are set when the write
ends.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit (PSPCON) is set. If the user
writes new data to PORTD to set OBF, the data is
immediately read out, but the OBF bit is not set.
When either the CS or RD line is detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP. When this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
FIGURE 11-3:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Data Bus
WR LATD
or
PORTD
D
Q
RDx
Pin
CK
Data Latch
Q
RD PORTD
ST
D
ENEN
TRIS Latch
RD LATD
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1)
Read
ST
RD
Chip Select
Write
ST
CS
ST
WR
Note: The I/O pin has protection diodes to VDD and VSS.
The timing for the control signals in Write and Read
modes is shown in Figure 11-4 and Figure 11-5,
respectively.
DS30009977G-page 186
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
REGISTER 11-5:
PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER
R-0
R-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
IBF
OBF
IBOV
PSPMODE
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5
IBOV: Input Buffer Overflow Detect bit
1 = A write occurred when a previously input word had not been read (must be cleared in software)
0 = No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel Slave Port mode
0 = General Purpose I/O mode
bit 3-0
Unimplemented: Read as ‘0’
FIGURE 11-4:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
2010-2017 Microchip Technology Inc.
DS30009977G-page 187
PIC18F66K80 FAMILY
FIGURE 11-5:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
TABLE 11-15: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name
PORTD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
PORTE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
LATE
LATE7
LATE6
LATE5
LATE4
—
LATE2
LATE1
LATE0
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
—
TRISE2
TRISE1
TRISE0
PSPCON
IBF
OBF
IBOV
PSPMODE
—
—
—
—
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
TMR1GIF
TMR2IF
TMR1IF
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
TMR1GIE
TMR2IE
TMR1IE
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
TMR1GIP
TMR2IP
TMR1IP
PMD1
PSPMD
CTMUMD
ADCMD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
TMR0MD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
DS30009977G-page 188
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
12.0
Note:
DATA SIGNAL MODULATOR
The Data Signal Modulator is only available
on 64-pin devices (PIC18F6XK80).
The Data Signal Modulator (DSM) is a peripheral which
allows the user to mix a data stream, also known as a
modulator signal, with a carrier signal to produce a
modulated output.
Both the carrier and the modulator signals are supplied
to the DSM module, either internally from the output of
a peripheral, or externally through an input pin.
The modulated output signal is generated by performing a logical “AND” operation of both the carrier and
modulator signals and then it is provided to the MDOUT
pin.
The carrier signal is comprised of two distinct and separate signals: a carrier high (CARH) signal and a carrier
low (CARL) signal. During the time in which the modulator (MOD) signal is in a logic high state, the DSM mixes
the carrier high signal with the modulator signal. When
the modulator signal is in a logic low state, the DSM
mixes the carrier low signal with the modulator signal.
2010-2017 Microchip Technology Inc.
Using this method, the DSM can generate the following
types of key modulation schemes:
• Frequency-Shift Keying (FSK)
• Phase-Shift Keying (PSK)
• On-Off Keying (OOK)
Additionally, the following features are provided within
the DSM module:
•
•
•
•
•
•
•
Carrier Synchronization
Carrier Source Polarity Select
Carrier Source Pin Disable
Programmable Modulator Data
Modulator Source Pin Disable
Modulated Output Polarity Select
Slew Rate Control
Figure 12-1 shows a simplified block diagram of the
Data Signal Modulator peripheral.
DS30009977G-page 189
PIC18F66K80 FAMILY
FIGURE 12-1:
SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR
MDCH
VSS
MDCIN1
MDCIN2
REFO Clock
ECCP1
CCP2
CCP3
CCP4
CCP5
Reserved
No Channel Selected
MDEN
0000
0001
0010
0011
0100
0101 CARH
0110
0111
1000
1001
**
1111
EN
Data Signal
Modulator
MDCHPOL
D
SYNC
MDMS
MDBIT
MDMIN
MSSP (SDO)
EUSART1 (TX)
EUSART2 (TX)
ECCP1
CCP2
CCP3
CCP4
CCP5
Reserved
No Channel
Selected
Q
0000
0001
0010
0011
0100
0101
0110 MOD
0111
1000
1001
1
0
MDCHSYNC
MDOUT
MDOPOL
1010
MDOE
*
*
1111
D
SYNC
MDCL
VSS
MDCIN1
MDCIN2
REFO Clock
ECCP1
CCP2
CCP3
CCP4
CCP5
Reserved
No Channel Selected
DS30009977G-page 190
Q
0000
0001
0010
0011
0100
0101 CARL
0110
0111
1000
1001
**
1111
1
0
MDCLSYNC
MDCLPOL
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
12.1
DSM Operation
The DSM module can be enabled by setting the MDEN
bit in the MDCON register. Clearing the MDEN bit in the
MDCON register, disables the DSM module by automatically switching the carrier high and carrier low
signals to the VSS signal source. The modulator signal
source is also switched to the MDBIT in the MDCON
register. This not only assures that the DSM module is
inactive, but that it is also consuming the least amount
of current.
The values used to select the carrier high, carrier low
and modulator sources held by the Modulation Source,
Modulation High Carrier and Modulation Low Carrier
Control registers are not affected when the MDEN bit is
cleared, and the DSM module is disabled. The values
inside these registers remain unchanged while the
DSM is inactive. The sources for the carrier high,
carrier low and modulator signals will once again be
selected when the MDEN bit is set and the DSM
module is again enabled and active.
The modulated output signal can be disabled without
shutting down the DSM module. The DSM module will
remain active and continue to mix signals, but the output value will not be sent to the MDOUT pin. During the
time that the output is disabled, the MDOUT pin will
remain low. The modulated output can be disabled by
clearing the MDOE bit in the MDCON register.
12.2
Modulator Signal Sources
The modulator signal can be supplied from the following
sources:
•
•
•
•
•
•
•
•
•
•
ECCP1 Signal
CCP2 Signal
CCP3 Signal
CCP4 Signal
CCP5 Signal
MSSP SDO Signal (SPI mode only)
EUSART1 TX1 Signal
EUSART2 TX2 Signal
External Signal on MDMIN Pin (RF0/MDMIN)
MDBIT bit in the MDCON Register
12.3
Carrier Signal Sources
The carrier high signal and carrier low signal can be
supplied from the following sources:
•
•
•
•
•
•
•
•
CCP1 Signal
CCP2 Signal
CCP3 Signal
CCP4 Signal
Reference Clock Module Signal
External Signal on MDCIN1 Pin (RF2/MDCIN1)
External Signal on MDCIN2 Pin (RF4/MDCIN2)
VSS
The carrier high signal is selected by configuring the
MDCH bits in the MDCARH register. The carrier
low signal is selected by configuring the MDCL
bits in the MDCARL register.
12.4
Carrier Synchronization
During the time when the DSM switches between carrier high and carrier low signal sources, the carrier data
in the modulated output signal can become truncated.
To prevent this, the carrier signal can be synchronized
to the modulator signal. When synchronization is
enabled, the carrier pulse that is being mixed at the
time of the transition is allowed to transition low before
the DSM switches over to the next carrier source.
Synchronization is enabled separately for the carrier
high and carrier low signal sources. Synchronization for
the carrier high signal can be enabled by setting the
MDCHSYNC bit in the MDCARH register. Synchronization for the carrier low signal can be enabled by setting
the MDCLSYNC bit in the MDCARL register.
Figure 12-1 through Figure 12-5 show timing diagrams
of using various synchronization methods.
The modulator signal is selected by configuring the
MDSRC bits in the MDSRC register.
2010-2017 Microchip Technology Inc.
DS30009977G-page 191
PIC18F66K80 FAMILY
FIGURE 12-2:
ON/OFF KEYING (OOK) SYNCHRONIZATION
Carrier Low (CARL)
Carrier High (CARH)
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
MDCHSYNC = 1
MDCLSYNC = 1
MDCHSYNC = 0
MDCLSYNC = 0
MDCHSYNC = 0
MDCLSYNC = 1
EXAMPLE 12-1:
NO SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 0)
Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
MDCHSYNC = 0
MDCLSYNC = 0
Active Carrier
State
FIGURE 12-3:
CARH
CARL
CARH
CARL
CARRIER HIGH SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 0)
Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
Active Carrier
State
DS30009977G-page 192
CARH
both
CARL
CARH
both
CARL
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
FIGURE 12-4:
CARRIER LOW SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 1)
Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
MDCHSYNC = 0
MDCLSYNC = 1
Active Carrier
State
FIGURE 12-5:
CARH
CARL
CARH
CARL
FULL SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 1)
Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
Falling Edges
Used to Sync
MDCHSYNC = 1
MDCLSYNC = 1
Active Carrier
State
CARH
2010-2017 Microchip Technology Inc.
CARL
CARH
CARL
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12.5
Carrier Source Polarity Select
The signal provided from any selected input source for
the carrier high and carrier low signals can be inverted.
Inverting the signal for the carrier high source is
enabled by setting the MDCHPOL bit of the MDCARH
register. Inverting the signal for the carrier low source is
enabled by setting the MDCLPOL bit of the MDCARL
register.
12.6
Carrier Source Pin Disable
Some peripherals assert control over their corresponding output pin when they are enabled. For example,
when the CCP1 module is enabled, the output of CCP1
is connected to the CCP1 pin.
This default connection to a pin can be disabled by
setting the MDCHODIS bit in the MDCARH register for
the carrier high source and the MDCLODIS bit in the
MDCARL register for the carrier low source.
12.7
Programmable Modulator Data
The MDBIT of the MDCON register can be selected as
the source for the modulator signal. This gives the user
the ability to program the value used for modulation.
12.8
Modulator Source Pin Disable
The modulator source default connection to a pin can
be disabled by setting the MDSODIS bit in the MDSRC
register.
12.9
Modulated Output Polarity
The modulated output signal provided on the MDOUT
pin can also be inverted. Inverting the modulated output signal is enabled by setting the MDOPOL bit of the
MDCON register.
12.10 Slew Rate Control
When modulated data streams of 20 MHz or greater
are required, the slew rate limitation on the output port
pin can be disabled. The slew rate limitation can be
removed by clearing the MDSLR bit in the MDCON
register.
12.11 Operation In Sleep Mode
The DSM module is not affected by Sleep mode. The
DSM can still operate during Sleep if the Carrier and
Modulator input sources are also still operable during
Sleep.
12.12 Effects of a Reset
Upon any device Reset, the Data Signal Modulator
module is disabled. The user’s firmware is responsible
for initializing the module before enabling the output.
The registers are reset to their default values.
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REGISTER 12-1:
MDCON: MODULATION CONTROL REGISTER
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
U-0
U-0
R/W-0
MDEN
MDOE
MDSLR
MDOPOL
MDO
—
—
MDBIT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
MDEN: Modulator Module Enable bit
1 = Modulator module is enabled and mixing input signals
0 = Modulator module is disabled and has no output
bit 6
MDOE: Modulator Module Pin Output Enable bit
1 = Modulator pin output is enabled
0 = Modulator pin output is disabled
bit 5
MDSLR: MDOUT Pin Slew Rate Limiting bit
1 = MDOUT pin slew rate limiting is enabled
0 = MDOUT pin slew rate limiting is disabled
bit 4
MDOPOL: Modulator Output Polarity Select bit
1 = Modulator output signal is inverted
0 = Modulator output signal is not inverted
bit 3
MDO: Modulator Output bit
Displays the current output value of the modulator module.(2)
bit 2-1
Unimplemented: Read as ‘0’
bit 0
MDBIT: Modulator Source Input bit
Allows software to manually set modulation source input to module.(1)
Note 1:
2:
x = Bit is unknown
The MDBIT must be selected as the modulation source in the MDSRC register for this operation.
The modulated output frequency can be greater and asynchronous from the clock that updates this
register bit. The bit value may not be valid for higher speed modulator or carrier signals.
2010-2017 Microchip Technology Inc.
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REGISTER 12-2:
MDSRC: MODULATION SOURCE CONTROL REGISTER
R/W-0
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
MDSODIS
—
—
—
MDSRC3
MDSRC2
MDSRC1
MDSRC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
MDSODIS: Modulation Source Output Disable bit
1 = Output signal driving the peripheral output pin (selected by MDMS) is disabled
0 = Output signal driving the peripheral output pin (selected by MDMS) is enabled
bit 6-4
Unimplemented: Read as ‘0’
bit 3-0
MDSRC Modulation Source Selection bits
1111-1010 = Reserved; no channel connected
1001 = CCP5 output (PWM Output mode only)
1000 = CCP4 output (PWM Output mode only)
0111 = CCP3 output (PWM Output mode only)
0110 = CCP2 output (PWM Output mode only)
0101 = ECCP1 output (PWM Output mode only)
0100 = EUSART2 TX output
0011 = EUSART1 TX output
0010 = MSSP SDO output
0001 = MDMIN port pin
0000 = MDBIT bit of the MDCON register is the modulation source
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REGISTER 12-3:
MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER
R/W-0
R/W-x
R/W-x
U-0
R/W-x
R/W-x
R/W-x
R/W-x
MDCHODIS
MDCHPOL
MDCHSYNC
—
MDCH3(1)
MDCH2(1)
MDCH1(1)
MDCH0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
MDCHODIS: Modulator High Carrier Output Disable bit
1 = Output signal driving the peripheral output pin (selected by MDCH) is disabled
0 = Output signal driving the peripheral output pin (selected by MDCH) is enabled
bit 6
MDCHPOL: Modulator High Carrier Polarity Select bit
1 = Selected high carrier signal is inverted
0 = Selected high carrier signal is not inverted
bit 5
MDCHSYNC: Modulator High Carrier Synchronization Enable bit
1 = Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the
low time carrier
0 = Modulator output is not synchronized to the high time carrier signal(1)
bit 4
Unimplemented: Read as ‘0’
bit 3-0
MDCH Modulator Data High Carrier Selection bits(1)
1111-1001 = Reserved
1000 = CCP5 output (PWM Output mode only)
0111 = CCP4 output (PWM Output mode only)
0110 = CCP3 output (PWM Output mode only)
0101 = CCP2 output (PWM Output mode only)
0100 = ECCP1 output (PWM Output mode only)
0011 = Reference clock module signal
0010 = MDCIN2 port pin
0001 = MDCIN1 port pin
0000 = VSS
Note 1:
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
2010-2017 Microchip Technology Inc.
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REGISTER 12-4:
MDCARL: MODULATION LOW CARRIER CONTROL REGISTER
R/W-0
R/W-x
R/W-x
U-0
R/W-x
R/W-x
R/W-x
R/W-x
MDCLODIS
MDCLPOL
MDCLSYNC
—
MDCL3(1)
MDCL2(1)
MDCL1(1)
MDCL0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
MDCLODIS: Modulator Low Carrier Output Disable bit
1 = Output signal driving the peripheral output pin (selected by MDCL of the MDCARL register)
is disabled
0 = Output signal driving the peripheral output pin (selected by MDCL of the MDCARL register)
is enabled
bit 6
MDCLPOL: Modulator Low Carrier Polarity Select bit
1 = Selected low carrier signal is inverted
0 = Selected low carrier signal is not inverted
bit 5
MDCLSYNC: Modulator Low Carrier Synchronization Enable bit
1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high
time carrier
0 = Modulator output is not synchronized to the low time carrier signal(1)
bit 4
Unimplemented: Read as ‘0’
bit 3-0
MDCL Modulator Data High Carrier Selection bits(1)
1111-1001 = Reserved
1000 = CCP5 output (PWM Output mode only)
0111 = CCP4 output (PWM Output mode only)
0110 = CCP3 output (PWM Output mode only)
0101 = CCP2 output (PWM Output mode only)
0100 = ECCP1 output (PWM Output mode only)
0011 = Reference clock module signal
0010 = MDCIN2 port pin
0001 = MDCIN1 port pin
0000 = VSS
Note 1:
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
TABLE 12-1:
SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MDCARH
MDCHODIS
MDCHPOL
MDCHSYNC
—
MDCH3
MDCH2
MDCH1
MDCH0
MDCARL
MDCLODIS
MDCLPOL
MDCLSYNC
—
MDCL3
MDCL2
MDCL1
MDCL0
MDCON
MDEN
MDOE
MDSLR
MDOPOL
MDO
—
—
MDBIT
MDSRC
MDSODIS
—
—
—
MDSRC3
MDSRC2
MDSRC1
MDSRC0
—
—
—
—
MODMD
ECANMD
CMP2MD
CMP1MD
PMD2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode.
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PIC18F66K80 FAMILY
13.0
TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or
counter in both 8-bit or 16-bit modes
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow
REGISTER 13-1:
The T0CON register (Register 13-1) controls all
aspects of the module’s operation, including the
prescale selection. It is both readable and writable.
Figure 13-1 provides a simplified block diagram of the
Timer0 module in 8-bit mode. Figure 13-2 provides a
simplified block diagram of the Timer0 module in 16-bit
mode.
T0CON: TIMER0 CONTROL REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6
T08BIT: Timer0 8-Bit/16-Bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transitions on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increments on high-to-low transition on T0CKI pin
0 = Increments on low-to-high transition on T0CKI pin
bit 3
PSA: Timer0 Prescaler Assignment bit
1 = Timer0 prescaler is not assigned; Timer0 clock input bypasses prescaler
0 = Timer0 prescaler is assigned; Timer0 clock input comes from prescaler output
bit 2-0
T0PS: Timer0 Prescaler Select bits
111 = 1:256 Prescale value
110 = 1:128 Prescale value
101 = 1:64 Prescale value
100 = 1:32 Prescale value
011 = 1:16 Prescale value
010 = 1:8 Prescale value
001 = 1:4 Prescale value
000 = 1:2 Prescale value
2010-2017 Microchip Technology Inc.
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13.1
Timer0 Operation
Timer0 can operate as either a timer or a counter. The
mode is selected with the T0CS bit (T0CON). In
Timer mode (T0CS = 0), the module increments on
every clock by default unless a different prescaler value
is selected (see Section 13.3 “Prescaler”). If the
TMR0 register is written to, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising edge or falling edge of the T0CKI pin. The
incrementing edge is determined by the Timer0 Source
Edge Select bit, T0SE (T0CON); clearing this bit
selects the rising edge. Restrictions on the external
clock input are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 13-1:
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
13.2
Timer0 Reads and Writes in 16-Bit
Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0, which is not directly readable nor
writable. (See Figure 13-2.) TMR0H is updated with the
contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4
0
1
1
Programmable
Prescaler
T0CKI Pin
T0SE
T0CS
0
Sync with
Internal
Clocks
Set
TMR0IF
on Overflow
TMR0L
(2 TCY Delay)
8
3
T0PS
8
PSA
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 13-2:
FOSC/4
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
0
1
1
T0CKI Pin
T0SE
T0CS
T0PS
Programmable
Prescaler
0
Sync with
Internal
Clocks
TMR0
High Byte
TMR0L
8
Set
TMR0IF
on Overflow
(2 TCY Delay)
3
Read TMR0L
Write TMR0L
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS30009977G-page 200
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PIC18F66K80 FAMILY
13.3
13.3.1
Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable.
Its value is set by the PSA and T0PS bits
(T0CON), which determine the prescaler
assignment and prescale ratio.
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
13.4
Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from
1:2 through 1:256, in power-of-two increments, are
selectable.
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
TABLE 13-1:
Name
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON). Before
re-enabling the interrupt, the TMR0IF bit must be
cleared in software by the Interrupt Service Routine
(ISR).
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (for example, CLRF TMR0,
MOVWF TMR0, BSF TMR0) clear the prescaler count.
Note:
SWITCHING PRESCALER
ASSIGNMENT
Since Timer0 is shutdown in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
TMR0L
Timer0 Register Low Byte
TMR0H
Timer0 Register High Byte
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
PSPMD
CTMUMD
ADCMD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
TMR0MD
PMD1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.
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14.0
TIMER1 MODULE
The Timer1 timer/counter module incorporates these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
• Selectable clock source (internal or external) with
device clock or SOSC oscillator internal options
• Interrupt-on-overflow
• Reset on ECCP Special Event Trigger
• Timer with gated control
Figure 14-1 displays a simplified block diagram of the
Timer1 module.
REGISTER 14-1:
The module derives its clocking source from either the
secondary oscillator or from an external digital source.
If using the secondary oscillator, there are the additional options for low-power, high-power and external
digital clock source.
Timer1 is controlled through the T1CON Control
register (Register 14-1). It also contains the Timer1
Oscillator Enable bit (SOSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON).
The FOSC clock source should not be used with the
ECCP capture/compare features. If the timer will be
used with the capture or compare features, always
select one of the other timer clocking options.
T1CON: TIMER1 CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
SOSCEN
T1SYNC
RD16
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
TMR1CS: Timer1 Clock Source Select bits
10 = Timer1 clock source is either from pin or oscillator, depending on the SOSCEN bit:
SOSCEN = 0:
External clock is from the T1CKI pin (on the rising edge).
SOSCEN = 1:
Depending on the SOSCSELx Configuration bit, the clock source is either a crystal oscillator on
SOSCI/SOSCO or an internal digital clock from the SCLKI pin.
01 = Timer1 clock source is the system clock (FOSC)(1)
00 = Timer1 clock source is the instruction clock (FOSC/4)
bit 5-4
T1CKPS: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
SOSCEN: SOSC Oscillator Enable bit
1 = SOSC is enabled and available for Timer1
0 = SOSC is disabled for Timer1
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Select bit
TMR1CS = 10:
1 = Do not synchronize external clock input
0 = Synchronizes external clock input
TMR1CS = 0x:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 1x.
Note 1:
The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare
features.
DS30009977G-page 202
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REGISTER 14-1:
T1CON: TIMER1 CONTROL REGISTER (CONTINUED)
bit 1
RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1:
The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare
features.
2010-2017 Microchip Technology Inc.
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14.1
Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON),
displayed in Register 14-2, is used to control the Timer1 gate.
REGISTER 14-2:
T1GCON: TIMER1 GATE CONTROL REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-x
R/W-0
R/W-0
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/T1DONE
T1GVAL
T1GSS1
T1GSS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored.
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6
T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5
T1GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
T1GSPM: Timer1 Gate Single Pulse Mode bit
1 = Timer1 Gate Single Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 Gate Single Pulse mode is disabled
bit 3
T1GGO/T1DONE: Timer1 Gate Single Pulse Acquisition Status bit
1 = Timer1 gate single pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single pulse acquisition has completed or has not been started
This bit is automatically cleared when T1GSPM is cleared.
bit 2
T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L; unaffected by
Timer1 Gate Enable (TMR1GE) bit.
bit 1-0
T1GSS: Timer1 Gate Source Select bits
11 = Comparator 2 output
10 = Comparator 1 output
01 = TMR2 to match PR2 output
00 = Timer1 gate pin
Note 1:
Programming the T1GCON prior to T1CON is recommended.
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14.2
14.3.2
Timer1 Operation
The Timer1 module is an 8 or 16-bit incrementing
counter that is accessed through the TMR1H:TMR1L
register pair.
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter. It increments
on every selected edge of the external source.
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively.
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input, T1CKI. Either of
these external clock sources can be synchronized to the
microcontroller system clock or they can run
asynchronously.
When used as a timer with a clock oscillator, an
external, 32.768 kHz crystal can be used in conjunction
with the dedicated internal oscillator circuit.
Note:
When SOSC is selected as Crystal mode (by the
SOSCSELx
bits),
the
RC1/SOSCI
and
RC0/SOSCO/SCLKI pins become inputs. This means
the values of TRISC are ignored and the pins are
read as ‘0’.
14.3
Clock Source Selection
The TMR1CS and SOSCEN bits of the T1CON
register are used to select the clock source for Timer1.
Table 14-1 displays the clock source selections.
14.3.1
EXTERNAL CLOCK SOURCE
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• Timer1 is enabled after POR Reset
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
When T1CKI is high, Timer1 is enabled
(TMR1ON = 1) when T1CKI is low.
INTERNAL CLOCK SOURCE
When the internal clock source is selected, the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
TABLE 14-1:
TIMER1 CLOCK SOURCE SELECTION
TMR1CS1
TMR1CS0
SOSCEN
0
1
x
Clock Source (FOSC)
0
0
x
Instruction Clock (FOSC/4)
1
0
0
External Clock on T1CKI Pin
1
0
1
Oscillator Circuit on SOSCI/SOSCO Pins
2010-2017 Microchip Technology Inc.
Clock Source
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FIGURE 14-1:
TIMER1 BLOCK DIAGRAM
T1GSS
T1G
T1GSPM
00
From TMR2
Match PR2
01
From Comparator 1
Output
10
0
T1G_IN
T1GVAL
0
From Comparator 2
Output
Single Pulse
D
Q
CK
R
Q
11
TMR1ON
T1GPOL
1
Acq. Control
1
D
Q1
Q
EN
Interrupt
T1GGO/T1DONE
det
Data Bus
RD
T1GCON
Set
TMR1GIF
T1GTM
TMR1GE
Set Flag bit,
TMR1IF, on
Overflow
TMR1ON
TMR1(2)
TMR1H
EN
TMR1L
Q
D
T1CLK
Synchronized
Clock Input
0
1
TMR1CS
SOSCO/SCLKI
SOSC
SOSCI
T1SYNC
OUT(4)
10
1
EN
0
T1CON.SOSCEN
T3CON.SOSCEN
SOSCGO
SCS = 01
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
Synchronize(3)
Prescaler
1, 2, 4, 8
det
2
T1CKPS
FOSC/2
Internal
Clock
Sleep Input
(1)
T1CKI
Note 1:
2:
3:
4:
ST Buffer is high-speed type when using T1CKI.
Timer1 register increments on rising edge.
Synchronize does not operate while in Sleep.
The output of SOSC is determined by the SOSCSEL Configuration bits.
DS30009977G-page 206
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
14.4
Timer1 16-Bit Read/Write Mode
FIGURE 14-2:
Timer1 can be configured for 16-bit reads and writes.
When the RD16 control bit (T1CON) is set, the
address for TMR1H is mapped to a buffer register for
the high byte of Timer1. A read from TMR1L loads the
contents of the high byte of Timer1 into the Timer1 High
Byte Buffer register. This provides the user with the
ability to accurately read all 16 bits of Timer1 without
having to determine whether a read of the high byte,
followed by a read of the low byte, has become invalid
due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits at once to both the high and low bytes of Timer1.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
14.5
SOSC Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins, SOSCI (input) and SOSCO (amplifier
output). It can be enabled one of these ways:
• Setting the SOSCEN bit in either the T1CON or
T3CON register (TxCON)
• Setting the SOSCGO bit in the OSCCON2 register
(OSCCON2)
• Setting the SCSx bits to secondary clock source in
the OSCCON register (OSCCON = 01)
The SOSCGO bit is used to warm up the SOSC so that
it is ready before any peripheral requests it.
The oscillator is a low-power circuit rated for 32 kHz
crystals. It will continue to run during all
power-managed modes. The circuit for a typical
low-power oscillator is depicted in Figure 14-2.
Table 14-2 provides the capacitor selection for the
SOSC oscillator.
The user must provide a software time delay to ensure
proper start-up of the SOSC oscillator.
EXTERNAL COMPONENTS
FOR THE SOSC
OSCILLATOR
C1
12 pF
PIC18F66K80
SOSCI
XTAL
32.768 kHz
SOSCO
C2
12 pF
See the Notes with Table 14-2 for additional
information about capacitor selection.
Note:
TABLE 14-2:
CAPACITOR SELECTION FOR
THE TIMER
OSCILLATOR(2,3,4,5)
Oscillator
Type
Freq.
C1
C2
LP
32 kHz
12 pF(1)
12 pF(1)
Note 1:
Microchip suggests these values as a starting
point in validating the oscillator circuit.
2:
Higher capacitance increases the stability of
the oscillator, but also increases the start-up
time.
3:
Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate
values of external components.
4:
Capacitor values are for design guidance only.
Values listed would be typical of a CL = 10 pF
rated crystal, when SOSCSEL = 11.
5:
Incorrect capacitance value may result in a frequency not meeting the crystal manufacturer’s
tolerance specification.
The SOSC crystal oscillator drive level is determined
based on the SOSCSELx (CONFIG1L) Configuration bits. The Higher Drive Level mode,
SOSCSEL = 11, is intended to drive a wide
variety of 32.768 kHz crystals with a variety of Load
Capacitance (CL) ratings.
The Lower Drive Level mode is highly optimized for
extremely low-power consumption. It is not intended to
drive all types of 32.768 kHz crystals. In the Low Drive
Level mode, the crystal oscillator circuit may not work
correctly if excessively large discrete capacitors are
placed on the SOSCO and SOSCI pins. This mode is
designed to work only with discrete capacitances of
approximately 3 pF-10 pF on each pin.
Crystal manufacturers usually specify a CL (Load
Capacitance) rating for their crystals. This value is
related to, but not necessarily the same as, the values
that should be used for C1 and C2 in Figure 14-2.
2010-2017 Microchip Technology Inc.
DS30009977G-page 207
PIC18F66K80 FAMILY
For more details on selecting the optimum C1 and C2
for a given crystal, see the crystal manufacture’s applications information. The optimum value depends in
part on the amount of parasitic capacitance in the
circuit, which is often unknown. For that reason, it is
highly recommended that thorough testing and validation of the oscillator be performed after values have
been selected.
14.5.1
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
VDD
VSS
OSC1
USING SOSC AS A
CLOCK SOURCE
The SOSC oscillator is also available as a clock source
in power-managed modes. By setting the clock select
bits, SCS (OSCCON), to ‘01’, the device
switches to SEC_RUN mode and both the CPU and
peripherals are clocked from the SOSC oscillator. If the
IDLEN bit (OSCCON) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 4.0
“Power-Managed Modes”.
Whenever the SOSC oscillator is providing the clock
source, the SOSC System Clock Status flag,
SOSCRUN (OSCCON2), is set. This can be used
to determine the controller’s current clocking mode. It
can also indicate the clock source currently being used
by the Fail-Safe Clock Monitor.
If the Clock Monitor is enabled and the SOSC oscillator
fails while providing the clock, polling the SOCSRUN
bit will indicate whether the clock is being provided by
the SOSC oscillator or another source.
14.5.2
FIGURE 14-3:
SOSC OSCILLATOR LAYOUT
CONSIDERATIONS
The SOSC oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity. This is especially true when
the oscillator is configured for extremely Low-Power
mode, SOSCSEL (CONFIG1L) = 01.
The oscillator circuit, displayed in Figure 14-2, should
be located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the oscillator,
it may help to have a grounded guard ring around the
oscillator circuit. The guard, as displayed in Figure 14-3,
could be used on a single-sided PCB or in addition to a
ground plane. (Examples of a high-speed circuit include
the ECCP1 pin, in Output Compare or PWM mode, or
the primary oscillator, using the OSC2 pin.)
DS30009977G-page 208
OSC2
RC0
RC1
RC2
Note: Not drawn to scale.
In the Low Drive Level mode, SOSCSEL = 01, it is
critical that RC2 I/O pin signals be kept away from the
oscillator circuit. Configuring RC2 as a digital output, and
toggling it, can potentially disturb the oscillator circuit,
even with a relatively good PCB layout. If possible, either
leave RC2 unused or use it as an input pin with a slew
rate limited signal source. If RC2 must be used as a
digital output, it may be necessary to use the Higher
Drive Level Oscillator mode (SOSCSEL = 11) with
many PCB layouts.
Even in the Higher Drive Level mode, careful layout
procedures should still be followed when designing the
oscillator circuit.
In addition to dV/dt induced noise considerations, it is
important to ensure that the circuit board is clean. Even
a very small amount of conductive, soldering flux
residue can cause PCB leakage currents that can
overwhelm the oscillator circuit.
14.6
Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which
is latched in interrupt flag bit, TMR1IF (PIR1). This
interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1).
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14.7
Resetting Timer1 Using the ECCP
Special Event Trigger
If ECCP modules are configured to use Timer1 and to
generate a Special Event Trigger in Compare mode
(CCP1M = 1011), this signal will reset Timer1. The
trigger from ECCP will also start an A/D conversion if the
A/D module is enabled. (For more information, see
Section 20.3.4 “Special Event Trigger”.)
14.8
Timer1 Gate
Timer1 can be configured to count freely or the count can
be enabled and disabled using the Timer1 gate circuitry.
This is also referred to as Timer1 gate count enable.
Timer1 gate can also be driven by multiple selectable
sources.
14.8.1
TIMER1 GATE COUNT ENABLE
To take advantage of this feature, the module must be
configured as either a timer or a synchronous counter.
When used this way, the CCPR1H:CCPR1L register
pair effectively becomes a Period register for Timer1.
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit (T1GCON).
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 14-4 for timing details.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
Note:
The Special Event Trigger from the ECCP
module will only clear the TMR1 register’s
content, but not set the TMR1IF interrupt
flag bit (PIR1).
TABLE 14-3:
T1CLK(†)
TIMER1 GATE ENABLE
SELECTIONS
T1GPOL
T1G Pin
(T1GCON)
Timer1
Operation
0
0
Counts
0
1
Holds Count
1
0
Holds Count
1
1
Counts
† The clock on which TMR1 is running. For more
information, see Figure 14-1.
Note:
2010-2017 Microchip Technology Inc.
The CCP and ECCP modules use Timers,
1 through 4, for some modes. The assignment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRS register. For
more details, see Register 20-2 and
Register 19-2.
DS30009977G-page 209
PIC18F66K80 FAMILY
FIGURE 14-4:
TIMER1 GATE COUNT ENABLE MODE
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
Timer1
14.8.2
N
TIMER1 GATE SOURCE
SELECTION
The Timer1 gate source can be selected from one of
four sources. Source selection is controlled by the
T1GSSx (T1GCON) bits (see Table 14-4).
TABLE 14-4:
TIMER1 GATE SOURCES
T1GSS
Timer1 Gate Pin
01
TMR2 to Match PR2
(TMR2 increments to match PR2)
10
Comparator 1 Output
(comparator logic high output)
11
Comparator 2 Output
(comparator logic high output)
The polarity for each available source is also selectable,
controlled by the T1GPOL bit (T1GCON).
T1G Pin Gate Operation
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
14.8.2.2
N+2
N+3
N+4
Depending on T1GPOL, Timer1 increments differently
when TMR2 matches PR2. When T1GPOL = 1, Timer1
increments for a single instruction cycle following a
TMR2 match with PR2. When T1GPOL = 0, Timer1
increments continuously except for the cycle following
the match when the gate signal goes from low-to-high.
14.8.2.3
Timer1 Gate Source
00
14.8.2.1
N+1
Comparator 1 Output Gate
Operation
The output of Comparator 1 can be internally supplied
to the Timer1 gate circuitry. After setting up
Comparator 1 with the CM1CON register, Timer1 will
increment depending on the transitions of the
CMP1OUT (CMSTAT) bit.
14.8.2.4
Comparator 2 Output Gate
Operation
The output of Comparator 2 can be internally supplied
to the Timer1 gate circuitry. After setting up
Comparator 2 with the CM2CON register, Timer1 will
increment depending on the transitions of the
CMP2OUT (CMSTAT) bit.
Timer2 Match Gate Operation
The TMR2 register will increment until it matches the
value in the PR2 register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry.
The pulse will remain high for one instruction cycle and
will return back to a low state until the next match.
DS30009977G-page 210
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14.8.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full cycle length of a Timer1
gate signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. (For timing details, see Figure 14-5.)
FIGURE 14-5:
The T1GVAL bit (T1GCON) indicates when the
Toggled mode is active and the timer is counting.
The Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit (T1GCON). When T1GTM is cleared,
the flip-flop is cleared and held clear. This is necessary
in order to control which edge is measured.
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
Timer1
N
2010-2017 Microchip Technology Inc.
N+1 N+2 N+3
N+4
N+5 N+6 N+7
N+8
DS30009977G-page 211
PIC18F66K80 FAMILY
14.8.4
TIMER1 GATE SINGLE PULSE
MODE
When Timer1 Gate Single Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single Pulse mode is enabled by setting the
T1GSPM bit (T1GCON) and the T1GGO/T1DONE
bit (T1GCON). The Timer1 will be fully enabled on
the next incrementing edge.
On the next trailing edge of the pulse, the
T1GGO/T1DONE bit will automatically be cleared. No
other gate events will be allowed to increment Timer1
until the T1GGO/T1DONE bit is once again set in
software.
FIGURE 14-6:
Clearing the T1GSPM bit of the T1GCON register will
also clear the T1GGO/T1DONE bit. (For timing details,
see Figure 14-6.)
Simultaneously enabling the Toggle and Single Pulse
modes will permit both sections to work together. This
allows the cycle times on the Timer1 gate source to be
measured. (For timing details, see Figure 14-7.)
14.8.5
TIMER1 GATE VALUE STATUS
When the Timer1 gate value status is utilized, it is
possible to read the most current level of the gate
control value. The value is stored in the T1GVAL bit
(T1GCON). This bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
TIMER1 GATE SINGLE PULSE MODE
TMR1GE
T1GPOL
T1GSPM
T1GGO/
Cleared by Hardware on
Falling Edge of T1GVAL
Set by Software
T1DONE
Counting Enabled on
Rising Edge of T1G
T1G_IN
T1CKI
T1GVAL
Timer1
DS30009977G-page 212
N
N+1
N+2
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PIC18F66K80 FAMILY
FIGURE 14-7:
TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
Cleared by Hardware on
Falling Edge of T1GVAL
Set by Software
T1DONE
Counting Enabled on
Rising Edge of T1G
T1G_IN
T1CKI
T1GVAL
Timer1
TABLE 14-5:
Name
INTCON
N+1
N
N+2
N+4
N+3
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
TMR1GIF
TMR2IF
TMR1IF
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
TMR1GIE
TMR2IE
TMR1IE
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
TMR1GIP
TMR2IP
TMR1IP
T1CKPS0
SOSCEN
T1SYNC
RD16
TMR1ON
T1GTM
T1GSPM
T1GGO/
T1DONE
T1GVAL
T1GSS1
T1GSS0
TMR1L
Timer1 Register Low Byte
TMR1H
Timer1 Register High Byte
T1CON
TMR1CS1
T1GCON
TMR1GE
T1GPOL
—
SOSCRUN
—
SOSCDRV
SOSCGO
—
MFIOFS
MFIOSEL
PSPMD
CTMUMD
ADCMD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
TMR0MD
OSCCON2
PMD1
TMR1CS0 T1CKPS1
Legend: Shaded cells are not used by the Timer1 module.
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DS30009977G-page 213
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15.0
TIMER2 MODULE
The Timer2 module incorporates the following features:
• Eight-bit Timer and Period registers (TMR2 and
PR2, respectively)
• Both registers are readable and writable
• Software programmable prescaler
(1:1, 1:4 and 1:16)
• Software programmable postscaler
(1:1 through 1:16)
• Interrupt on TMR2 to PR2 match
• Optional use as the shift clock for the
MSSP module
The module is controlled through the T2CON register
(Register 15-1) that enables or disables the timer, and
configures the prescaler and postscaler. Timer2 can be
shut off by clearing control bit, TMR2ON (T2CON),
to minimize power consumption.
A simplified block diagram of the module is shown in
Figure 15-1.
15.1
The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values
match, the comparator generates a match signal as the
timer output. This signal also resets the value of TMR2
to 00h on the next cycle and drives the output
counter/postscaler. (See Section 15.2 “Timer2 Interrupt”.)
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset – Power-on Reset (POR),
MCLR Reset, Watchdog Timer Reset (WDTR) or
Brown-out Reset (BOR)
TMR2 is not cleared when T2CON is written.
Note:
Timer2 Operation
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A four-bit counter/prescaler on the
clock input gives the prescale options of direct input,
divide-by-4 or divide-by-16. These are selected by the
prescaler control bits, T2CKPS (T2CON).
REGISTER 15-1:
The CCP and ECCP modules use Timers,
1 through 4, for some modes. The assignment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRS register. For
more details, see Register 20-2 and
Register 19-2.
T2CON: TIMER2 CONTROL REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
T2OUTPS3
T2OUTPS2
T2OUTPS1
T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
DS30009977G-page 214
x = Bit is unknown
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REGISTER 15-1:
bit 1-0
T2CON: TIMER2 CONTROL REGISTER (CONTINUED)
T2CKPS: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
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DS30009977G-page 215
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15.2
Timer2 Interrupt
15.3
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) provides
the input for the four-bit output counter/postscaler. This
counter generates the TMR2 match interrupt flag, which
is latched in TMR2IF (PIR1). The interrupt is enabled
by setting the TMR2 Match Interrupt Enable bit, TMR2IE
(PIE1).
Timer2 Output
The unscaled output of TMR2 is available primarily to
the ECCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can optionally be used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 21.0
“Master Synchronous Serial Port (MSSP) Module”.
A range of 16 postscaler options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS (T2CON).
FIGURE 15-1:
TIMER2 BLOCK DIAGRAM
4
T2OUTPS
1:1 to 1:16
Postscaler
Set TMR2IF
2
T2CKPS
Reset
1:1, 1:4, 1:16
Prescaler
FOSC/4
TMR2 Output
(to PWM or MSSP)
TMR2/PR2
Match
Comparator
TMR2
8
PR2
8
8
Internal Data Bus
TABLE 15-1:
Name
INTCON
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
TMR1GIF
TMR2IF
TMR1IF
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
TMR1GIE
TMR2IE
TMR1IE
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
TMR1GIP
TMR2IP
TMR1IP
T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
TMR3MD
TMR2MD
TMR1MD
TMR0MD
TMR2
T2CON
PR2
PMD1
Timer2 Register
—
T2OUTPS3 T2OUTPS2 T2OUTPS1
Timer2 Period Register
PSPMD
CTMUMD
ADCMD
TMR4MD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
DS30009977G-page 216
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16.0
TIMER3 MODULE
The Timer3 timer/counter modules incorporate these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable eight-bit registers (TMR3H
and TMR3L)
• Selectable clock source (internal or external) with
device clock or SOSC oscillator internal options
• Interrupt-on-overflow
• Module Reset on ECCP Special Event Trigger
REGISTER 16-1:
A simplified block diagram of the Timer3 module is
shown in Figure 16-1.
The Timer3 module is controlled through the T3CON
register (Register 16-1). It also selects the clock source
options for the ECCP modules. (For more information,
see Section 20.1.1 “ECCP Module and Timer
Resources”.)
The FOSC clock source should not be used with the
ECCP capture/compare features. If the timer will be
used with the capture or compare features, always
select one of the other timer clocking options.
T3CON: TIMER3 CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TMR3CS1
bit 7
TMR3CS0
T3CKPS1
T3CKPS0
SOSCEN
T3SYNC
RD16
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Note 1:
W = Writable bit
‘1’ = Bit is set
R/W-0
TMR3ON
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
TMR3CS: Timer3 Clock Source Select bits
10 = Timer3 clock source is either from pin or oscillator, depending on the SOSCEN bit:
SOSCEN = 0:
External clock is from T3CKI pin (on the rising edge).
SOSCEN = 1:
Depending on the SOSCSELx Configuration bit, the clock source is either a crystal oscillator on
SOSCI/SOSCO or an internal digital clock from the SCLKI pin.
01 = Timerx clock source is system clock (FOSC)(1)
00 = Timerx clock source is instruction clock (FOSC/4)
T3CKPS: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
SOSCEN: SOSC Oscillator Enable bit
1 = SOSC is enabled and available for Timer3
0 = SOSC is disabled and available for Timer3
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 10:
1 = Does not synchronize external clock input
0 = Synchronizes external clock input
When TMR3CS = 0x:
This bit is ignored; Timer3 uses the internal clock.
RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two eight-bit operations
TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features.
2010-2017 Microchip Technology Inc.
DS30009977G-page 217
PIC18F66K80 FAMILY
16.1
Timer3 Gate Control Register
The Timer3 Gate Control register (T3GCON), provided
in Register 14-2, is used to control the Timer3 gate.
REGISTER 16-2:
T3GCON: TIMER3 GATE CONTROL REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-x
R/W-0
R/W-0
TMR3GE
T3GPOL
T3GTM
T3GSPM
T3GGO/T3DONE
T3GVAL
T3GSS1
T3GSS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR3GE: Timer3 Gate Enable bit
If TMR3ON = 0:
This bit is ignored.
If TMR3ON = 1:
1 = Timer3 counting is controlled by the Timer3 gate function
0 = Timer3 counts regardless of Timer3 gate function
bit 6
T3GPOL: Timer3 Gate Polarity bit
1 = Timer3 gate is active-high (Timer3 counts when gate is high)
0 = Timer3 gate is active-low (Timer3 counts when gate is low)
bit 5
T3GTM: Timer3 Gate Toggle Mode bit
1 = Timer3 Gate Toggle mode is enabled.
0 = Timer3 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer3 gate flip-flop toggles on every rising edge.
bit 4
T3GSPM: Timerx Gate Single Pulse Mode bit
1 = Timer3 Gate Single Pulse mode is enabled and is controlling Timer3 gate
0 = Timer3 Gate Single Pulse mode is disabled
bit 3
T3GGO/T3DONE: Timer3 Gate Single Pulse Acquisition Status bit
1 = Timer3 Gate Single Pulse mode acquisition is ready, waiting for an edge
0 = Timer3 Gate Single Pulse mode acquisition has completed or has not been started
This bit is automatically cleared when T3GSPM is cleared.
bit 2
T3GVAL: Timer3 Gate Current State bit
Indicates the current state of the Timerx gate that could be provided to TMR3H:TMR3L. Unaffected by
Timerx Gate Enable (TMR3GE) bit.
bit 1-0
T3GSS: Timer3 Gate Source Select bits
11 = Comparator 2 output
10 = Comparator 1 output
01 = TMR4 to match PR4 output
00 = Timer3 gate pin
Watchdog Timer oscillator is turned on if TMR3GE = 1, regardless of the state of TMR3ON.
Note 1:
Programming the T3GCON prior to T3CON is recommended.
DS30009977G-page 218
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
REGISTER 16-3:
OSCCON2: OSCILLATOR CONTROL REGISTER 2
U-0
R-0
U-0
RW-1
R/W-0
U-0
R-x
R/W-0
—
SOSCRUN
—
SOSCDRV(1)
SOSCGO
—
MFIOFS
MFIOSEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
SOSCRUN: SOSC Run Status bit
1 = System clock comes from a secondary SOSC
0 = System clock comes from an oscillator other than SOSC
bit 5
Unimplemented: Read as ‘0’
bit 4
SOSCDRV: Secondary Oscillator Drive Control bit(1)
1 = High-power SOSC circuit selected
0 = Low/high-power select is done via the SOSCSEL Configuration bits
bit 3
SOSCGO: Oscillator Start Control bit
1 = Oscillator is running even if no other sources are requesting it
0 = Oscillator is shut off if no other sources are requesting it (When the SOSC is selected to run from
a digital clock input, rather than an external crystal, this bit has no effect.)
bit 2
Unimplemented: Read as ‘0’
bit 1
MFIOFS: MF-INTOSC Frequency Stable bit
1 = MF-INTOSC is stable
0 = MF-INTOSC is not stable
bit 0
MFIOSEL: MF-INTOSC Select bit
1 = MF-INTOSC is used in place of HF-INTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz
0 = MF-INTOSC is not used
Note 1:
When SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no
effect.
2010-2017 Microchip Technology Inc.
DS30009977G-page 219
PIC18F66K80 FAMILY
16.2
The operating mode is determined by the clock select
bits, TMR3CSx (T3CON). When the TMR3CSx bits
are cleared (= 00), Timer3 increments on every internal
instruction cycle (FOSC/4). When TMR3CSx = 01, the
Timer3 clock source is the system clock (FOSC), and
when it is ‘10’, Timer3 works as a counter from the
external clock from the T3CKI pin (on the rising edge
after the first falling edge) or the SOSC oscillator.
Timer3 Operation
Timer3 can operate in these modes:
•
•
•
•
Timer
Synchronous Counter
Asynchronous Counter
Timer with Gated Control
FIGURE 16-1:
TIMER3 BLOCK DIAGRAM
T3GSS
T3G
00
From TMR4
Match PR4
01
From Comparator 1
Output
10
T3GSPM
0
T3G_IN
T3GVAL
0
From Comparator 2
Output
Single Pulse
D
Q
CK
R
Q
11
TMR3ON
T3GPOL
1
Acq. Control
1
D
Q1
Q
RD
T3GCON
EN
Interrupt
T3GGO/T3DONE
Data Bus
det
Set
TMR3GIF
T3GTM
TMR3GE
Set Flag bit,
TMR3IF, on
Overflow
TMR3ON
TMR3(2)
TMR3H
EN
TMR3L
Q
D
T3CLK
Synchronized
Clock Input
0
1
TMR3CS
SOSCO/SCLKI
SOSC
SOSCI
10
EN
T1CON.SOSCEN
T3CON.SOSCEN
SOSCGO
SCS = 01
(1)
Note 1:
2:
3:
4:
Prescaler
1, 2, 4, 8
1
0
T3CKI
T3SYNC
OUT(4)
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
Synchronize(3)
det
2
T3CKPS
FOSC/2
Internal
Clock
Sleep Input
ST Buffer is high-speed type when using T3CKI.
Timer3 registers increment on rising edge.
Synchronization does not operate while in Sleep.
The output of SOSC is determined by the SOSCSEL Configuration bits.
DS30009977G-page 220
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
16.3
Timer3 16-Bit Read/Write Mode
Timer3 can be configured for 16-bit reads and writes
(see Figure 16.3). When the RD16 control bit
(T3CON) is set, the address for TMR3H is mapped
to a buffer register for the high byte of Timer3. A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 High Byte Buffer register. This
provides users with the ability to accurately read all
16 bits of Timer3 without having to determine whether a
read of the high byte, followed by a read of the low byte,
has become invalid due to a rollover between reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows users to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
2010-2017 Microchip Technology Inc.
16.4
Using the SOSC Oscillator as the
Timer3 Clock Source
The SOSC internal oscillator may be used as the clock
source for Timer3. It can be enabled in one of these
ways:
• Setting the SOSCEN bit in either the T1CON or
T3CON register (TxCON)
• Setting the SOSCGO bit in the OSCCON2 register
(OSCCON2)
• Setting the SCSx bits to secondary clock source in
the OSCCON register (OSCCON = 01)
The SOSCGO bit is used to warm up the SOSC so that
it is ready before any peripheral requests it.
To use it as the Timer3 clock source, the TMR3CSx bits
must also be set. As previously noted, this also configures Timer3 to increment on every rising edge of the
oscillator source.
The SOSC oscillator is described in Section 14.5
“SOSC Oscillator”.
DS30009977G-page 221
PIC18F66K80 FAMILY
16.5
Timer3 Gates
TABLE 16-1:
TIMER3 GATE ENABLE
SELECTIONS
Timer3 can be configured to count freely or the count
can be enabled and disabled using the Timer3 gate
circuitry. This is also referred to as the Timer3 gate
count enable.
T3CLK(†)
0
0
The Timer3 gate can also be driven by multiple
selectable sources.
Counts
0
1
Holds Count
1
0
Holds Count
1
1
Counts
16.5.1
TIMER3 GATE COUNT ENABLE
T3GPOL
T3G Pin
(T3GCON)
Timer3
Operation
† The clock on which TMR3 is running. For more
information, see T3CLK in Figure 16-1.
The Timer3 Gate Enable mode is enabled by setting
the TMR3GE bit (TxGCON). The polarity of the
Timer3 Gate Enable mode is configured using the
T3GPOL bit (T3GCON).
When Timer3 Gate Enable mode is enabled, Timer3 will
increment on the rising edge of the Timer3 clock source.
When Timer3 Gate Enable mode is disabled, no incrementing will occur and Timer3 will hold the current count.
See Figure 16-2 for timing details.
FIGURE 16-2:
TIMER3 GATE COUNT ENABLE MODE
TMR3GE
T3GPOL
T3G_IN
T3CKI
T3GVAL
Timer3
DS30009977G-page 222
N
N+1
N+2
N+3
N+4
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
16.5.2
TIMER3 GATE SOURCE
SELECTION
The Timer3 gate source can be selected from one of
four different sources. Source selection is controlled by
the T3GSS bits (T3GCON). The polarity for
each available source is also selectable and is
controlled by the T3GPOL bit (T3GCON).
TABLE 16-2:
TIMER3 GATE SOURCES
T3GSS
Timer3 Gate Source
00
Timerx Gate Pin
01
TMR4 to Match PR4
(TMR4 increments to match PR4)
10
Comparator 1 Output
(comparator logic high output)
11
Comparator 2 Output
(comparator logic high output)
16.5.2.1
T3G Pin Gate Operation
The T3G pin is one source for Timer3 gate control. It can
be used to supply an external source to the Timerx gate
circuitry.
16.5.2.2
Timer4 Match Gate Operation
The TMR4 register will increment until it matches the
value in the PR4 register. On the very next increment
cycle, TMR4 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be generated and internally supplied to the Timerx gate circuitry.
The pulse will remain high for one instruction cycle and
will return back to a low state until the next match.
Depending on T3GPOL, Timerx increments differently
when TMR4 matches PR4. When T3GPOL = 1, Timer3
increments for a single instruction cycle following a
FIGURE 16-3:
TMR4 match with PR4. When T3GPOL = 0, Timer3
increments continuously, except for the cycle following
the match, when the gate signal goes from low-to-high.
16.5.2.3
Comparator 1 Output Gate
Operation
The output of Comparator 1 can be internally supplied
to the Timer3 gate circuitry. After setting up
Comparator 1 with the CM1CON register, Timer3 will
increment depending on the transitions of the
CMP1OUT (CMSTAT) bit.
16.5.2.4
Comparator 2 Output Gate
Operation
The output of Comparator 2 can be internally supplied
to the Timer3 gate circuitry. After setting up
Comparator 2 with the CM2CON register, Timer3 will
increment depending on the transitions of the
CMP2OUT (CMSTAT) bit.
16.5.3
TIMER3 GATE TOGGLE MODE
When Timer3 Gate Toggle mode is enabled, it is
possible to measure the full cycle length of a Timer3
gate signal, as opposed to the duration of a single level
pulse.
The Timer3 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. (For timing details, see Figure 16-3.)
The T3GVAL bit will indicate when the Toggled mode is
active and the timer is counting.
Timer3 Gate Toggle mode is enabled by setting the
T3GTM bit (T3GCON). When the T3GTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.
TIMER3 GATE TOGGLE MODE
TMR3GE
T3GPOL
T3GTM
T3G_IN
T3CKI
T3GVAL
Timer3
N
2010-2017 Microchip Technology Inc.
N+1 N+2 N+3
N+4
N+5 N+6 N+7
N+8
DS30009977G-page 223
PIC18F66K80 FAMILY
16.5.4
TIMER3 GATE SINGLE PULSE
MODE
other gate events will be allowed to increment Timer3
until the T3GGO/T3DONE bit is once again set in
software.
When Timer3 Gate Single Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer3
Gate Single Pulse mode is first enabled by setting the
T3GSPM
bit
(T3GCON).
Next,
the
T3GGO/T3DONE bit (T3GCON) must be set.
Clearing the T3GSPM bit will also clear the
T3GGO/T3DONE bit. (For timing details, see
Figure 16-4.)
Simultaneously enabling the Toggle mode and the
Single Pulse mode will permit both sections to work
together. This allows the cycle times on the Timer3 gate
source to be measured. (For timing details, see
Figure 16-5.)
The Timer3 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the
T3GGO/T3DONE bit will automatically be cleared. No
FIGURE 16-4:
TIMER3 GATE SINGLE PULSE MODE
TMR3GE
T3GPOL
T3GSPM
Cleared by Hardware on
Falling Edge of T3GVAL
Set by Software
T3GGO/
T3DONE
Counting Enabled on
Rising Edge of T3G
T3G_IN
T3CKI
T3GVAL
Timer3
TMR3GIF
DS30009977G-page 224
N
Cleared by Software
N+1
N+2
Set by Hardware on
Falling Edge of T3GVAL
Cleared by
Software
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
FIGURE 16-5:
TIMER3 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
TMR3GE
T3GPOL
T3GSPM
T3GTM
Cleared by Hardware on
Falling Edge of T3GVAL
Set by Software
T3GGO/
T3DONE
Counting Enabled on
Rising Edge of T3G
T3G_IN
T3CKI
T3GVAL
Timer3
TMR3GIF
16.5.5
N
N+1
Cleared by Software
TIMER3 GATE VALUE STATUS
When Timer3 gate value status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T3GVAL bit (T3GCON).
The T3GVAL bit is valid even when the Timer3 gate is
not enabled (TMR3GE bit is cleared).
N+2
N+3
Set by Hardware on
Falling Edge of T3GVAL
16.5.6
N+4
Cleared by
Software
TIMER3 GATE EVENT INTERRUPT
When the Timer3 gate event interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of T3GVAL
occurs, the TMR3GIF flag bit in the PIR2 register will be
set. If the TMR3GIE bit in the PIE2 register is set, then
an interrupt will be recognized.
The TMR3GIF flag bit operates even when the Timer3
gate is not enabled (TMR3GE bit is cleared).
2010-2017 Microchip Technology Inc.
DS30009977G-page 225
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16.6
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPR3H:CCPR3L register
pair effectively becomes a Period register for Timer3.
Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in the interrupt flag bit, TMR3IF.
Table 16-3 gives each module’s flag bit.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from an ECCP module, the write
will take precedence.
This interrupt can be enabled or disabled by setting or
clearing the TMR3IE bit. Table 16-3 displays each
module’s enable bit.
16.7
Note:
The Special Event Triggers from the
ECCPx module will only clear the TMR3
register’s content, but not set the TMR3IF
interrupt flag bit (PIR2).
Note:
The CCP and ECCP modules use Timers,
1 through 4, for some modes. The assignment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRS register. For
more details, see Register 20-2 and
Register 19-2.
Resetting Timer3 Using the ECCP
Special Event Trigger
If the ECCP modules are configured to use Timer3 and
to generate a Special Event Trigger in Compare mode
(CCP3M = 1011), this signal will reset Timer3.
The trigger from ECCP will also start an A/D conversion
if the A/D module is enabled (For more information, see
Section 20.3.4 “Special Event Trigger”.)
TABLE 16-3:
Name
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
IRXIF
WAKIF
ERRIF
TXB2IF
TXB1IF
TXB0IF
RXB1IF
RXB0IF
PIE5
IRXIE
WAKIE
ERRIE
TX2BIE
TXB1IE
TXB0IE
RXB1IE
RXB0IE
PIR2
OSCFIF
—
—
—
BCLIF
HLVDIF
TMR3IF
TMR3GIF
OSCFIE
—
—
—
BCLIE
HLVDIE
TMR3IE
TMR3GIE
T3GSS1
T3GSS0
INTCON
PIR5
PIE2
TMR3H
Timer3 Register High Byte
TMR3L
Timer3 Register Low Byte
T3GCON
TMR3GE
T3GPOL
T3GTM
T3GSPM
T3GGO/
T3DONE
T3GVAL
T3CON
TMR3CS1
TMR3CS0
T3CKPS1
T3CKPS0
SOSCEN
T3SYNC
RD16
TMR3ON
—
SOSCRUN
—
SOSCDRV
SOSCGO
—
MFIOFS
MFIOSEL
PSPMD
CTMUMD
ADCMD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
TMR0MD
OSCCON2
PMD1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
DS30009977G-page 226
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
17.0
TIMER4 MODULES
The Timer4 timer modules have the following features:
•
•
•
•
•
•
Eight-bit Timer register (TMR4)
Eight-bit Period register (PR4)
Readable and writable (all registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Interrupt on TMR4 match of PR4
The Timer4 modules have a control register shown in
Register 17-1. Timer4 can be shut off by clearing
control bit, TMR4ON (T4CON), to minimize power
consumption. The prescaler and postscaler selection of
Timer4 also are controlled by this register. Figure 17-1
is a simplified block diagram of the Timer4 modules.
17.1
TMR4 goes through a four-bit postscaler (that gives a
1:1 to 1:16 inclusive scaling) to generate a TMR4
interrupt, latched in the flag bit, TMR4IF. Table 17-1
gives each module’s flag bit.
The interrupt can be enabled or disabled by setting or
clearing the Timer4 Interrupt Enable bit (TMR4IE),
shown in Table 17-1.
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR4 register
• A write to the T4CON register
• Any device Reset – Power-on Reset (POR),
MCLR Reset, Watchdog Timer Reset (WDTR) or
Brown-out Reset (BOR)
A TMR4 is not cleared when a T4CON is written.
Note:
Timer4 Operation
Timer4 can be used as the PWM time base for the
PWM mode of the ECCP modules. The TMR4 registers
are readable and writable, and are cleared on any
device Reset. The input clock (FOSC/4) has a prescale
option of 1:1, 1:4 or 1:16, selected by control bits,
T4CKPS (T4CON). The match output of
REGISTER 17-1:
The CCP and ECCP modules use Timers,
1 through 4, for some modes. The assignment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRS register. For
more details, see Register 20-2 and
Register 19-2.
T4CON: TIMER4 CONTROL REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
T4OUTPS3
T4OUTPS2
T4OUTPS1
T4OUTPS0
TMR4ON
T4CKPS1
T4CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T4OUTPS: Timer4 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR4ON: Timer4 On bit
1 = Timer4 is on
0 = Timer4 is off
bit 1-0
T4CKPS: Timer4 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
2010-2017 Microchip Technology Inc.
x = Bit is unknown
DS30009977G-page 227
PIC18F66K80 FAMILY
17.2
Timer4 Interrupt
17.3
The Timer4 module has an eight-bit Period register,
PR4, that is both readable and writable. Timer4 increment from 00h until it matches PR4 and then resets to
00h on the next increment cycle. The PR4 register is
initialized to FFh upon Reset.
FIGURE 17-1:
Output of TMR4
The outputs of TMR4 (before the postscaler) are used
only as a PWM time base for the ECCP modules. They
are not used as baud rate clocks for the MSSP module
as is the Timer2 output.
TIMER4 BLOCK DIAGRAM
4
T4OUTPS
1:1 to 1:16
Postscaler
Set TMR4IF
2
T4CKPS
TMR4 Output
(to PWM)
Reset
1:1, 1:4, 1:16
Prescaler
FOSC/4
TMRx/PRx
Match
Comparator
TMR4
8
PR4
8
8
Internal Data Bus
TABLE 17-1:
Name
INTCON
IPR4
REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER
Bit 7
Bit 6
GIE/GIEH
PEIE/GIEL
TMR4IP
EEIP
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
CMP2IP
CMP1IP
—
CCP5IP
CCP4IP
CCP3IP
PIR4
TMR4IF
EEIF
CMP2IF
CMP1IF
—
CCP5IF
CCP4IF
CCP3IF
PIE4
TMR4IE
EEIE
CMP2IE
CMP1IE
—
CCP5IE
CCP4IE
CCP3IE
TMR4ON
T4CKPS1
T4CKPS0
TMR2MD
TMR1MD
TMR0MD
TMR4
T4CON
PR4
PMD1
Timer4 Register
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0
Timer4 Period Register
PSPMD
CTMUMD
ADCMD
TMR4MD
TMR3MD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module.
DS30009977G-page 228
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
18.0
•
•
•
•
•
Control of edge sequence
Control of response to edges
Time measurement resolution of 1 nanosecond
High-precision time measurement
Time delay of external or internal signal
asynchronous to system clock
• Accurate current source suitable for capacitive
measurement
CHARGE TIME
MEASUREMENT UNIT (CTMU)
The Charge Time Measurement Unit (CTMU) is a
flexible analog module that provides accurate differential time measurement between pulse sources, as well
as asynchronous pulse generation. By working with
other on-chip analog modules, the CTMU can precisely
measure time, capacitance and relative changes in
capacitance or generate output pulses with a specific
time delay. The CTMU is ideal for interfacing with
capacitive-based sensors.
The CTMU works in conjunction with the A/D Converter
to provide up to 11 channels for time or charge
measurement, depending on the specific device and
the number of A/D channels available. When configured for time delay, the CTMU is connected to one of
the analog comparators. The level-sensitive input edge
sources can be selected from four sources: two
external inputs or the ECCP1/CCP2 Special Event
Triggers.
The module includes these key features:
• Up to 11 channels available for capacitive or time
measurement input
• Low-cost temperature measurement using on-chip
diode channel
• On-chip precision current source
• Four-edge input trigger sources
• Polarity control for each edge source
FIGURE 18-1:
The CTMU special event can trigger the Analog-to-Digital
Converter module.
Figure 18-1 provides a block diagram of the CTMU.
CTMU BLOCK DIAGRAM
CTMUCONH:CTMUCONL
EDGEN
EDGSEQEN
EDG1SEL
EDG1POL
EDG2SEL
EDG2POL
CTED1
CTED2
CTMUICON
ITRIM
IRNG
EDG1STAT
EDG2STAT
Edge
Control
Logic
Current Source
Current
Control
CCP2
TGEN
IDISSEN
CTTRIG
CTMU
Control
Logic
Pulse
Generator
ECCP1
A/D Converter
A/D Trigger
CTPLS
Comparator 2
Input
Comparator 2 Output
2010-2017 Microchip Technology Inc.
DS30009977G-page 229
PIC18F66K80 FAMILY
18.1
The CTMUCONH and CTMUCONL registers
(Register 18-1 and Register 18-2) contain control bits
for configuring the CTMU module edge source selection, edge source polarity selection, edge sequencing,
A/D trigger, analog circuit capacitor discharge and
enables. The CTMUICON register (Register 18-3) has
bits for selecting the current source range and current
source trim.
CTMU Registers
The control registers for the CTMU are:
• CTMUCONH
• CTMUCONL
• CTMUICON
REGISTER 18-1:
CTMUCONH: CTMU CONTROL HIGH REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMUEN
—
CTMUSIDL
TGEN
EDGEN
EDGSEQEN
IDISSEN
CTTRIG
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CTMUEN: CTMU Enable bit
1 = Module is enabled
0 = Module is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
CTMUSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 4
TGEN: Time Generation Enable bit
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 3
EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
bit 2
ESGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
bit 1
IDISSEN: Analog Current Source Control bit
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 0
CTTRIG: CTMU Special Event Trigger bit
1 = CTMU Special Event Trigger is enabled
0 = CTMU Special Event Trigger is disabled
DS30009977G-page 230
x = Bit is unknown
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
REGISTER 18-2:
CTMUCONL: CTMU CONTROL LOW REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EDG2POL
EDG2SEL1
EDG2SEL0
EDG1POL
EDG1SEL1
EDG1SEL0
EDG2STAT
EDG1STAT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 is programmed for a positive edge response
0 = Edge 2 is programmed for a negative edge response
bit 6-5
EDG2SEL: Edge 2 Source Select bits
11 = CTED1 pin
10 = CTED2 pin
01 = ECCP1 Special Event Trigger
00 = CCP2 Special Event Trigger
bit 4
EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 is programmed for a positive edge response
0 = Edge 1 is programmed for a negative edge response
bit 3-2
EDG1SEL: Edge 1 Source Select bits
11 = CTED1 pin
10 = CTED2 pin
01 = ECCP1 Special Event Trigger
00 = CCP2 Special Event Trigger
bit 1
EDG2STAT: Edge 2 Status bit
1 = Edge 2 event has occurred
0 = Edge 2 event has not occurred
bit 0
EDG1STAT: Edge 1 Status bit
1 = Edge 1 event has occurred
0 = Edge 1 event has not occurred
2010-2017 Microchip Technology Inc.
x = Bit is unknown
DS30009977G-page 231
PIC18F66K80 FAMILY
REGISTER 18-3:
CTMUICON: CTMU CURRENT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
IRNG1
IRNG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
ITRIM: Current Source Trim bits
011111 = Maximum positive change (+62% typ.) from nominal current
011110
.
.
.
000001 = Minimum positive change (+2% typ.) from nominal current
000000 = Nominal current output specified by IRNG
111111 = Minimum negative change (-2% typ.) from nominal current
.
.
.
100010
100001 = Maximum negative change (-62% typ.) from nominal current
bit 1-0
IRNG: Current Source Range Select bits
11 = 100 x Base Current
10 = 10 x Base Current
01 = Base Current level (0.55 A nominal)
00 = Current source is disabled
DS30009977G-page 232
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
18.2
CTMU Operation
The CTMU works by using a fixed current source to
charge a circuit. The type of circuit depends on the type
of measurement being made.
In the case of charge measurement, the current is fixed
and the amount of time the current is applied to the circuit is fixed. The amount of voltage read by the A/D
becomes a measurement of the circuit’s capacitance.
In the case of time measurement, the current, as well
as the capacitance of the circuit, is fixed. In this case,
the voltage read by the A/D is representative of the
amount of time elapsed from the time the current
source starts and stops charging the circuit.
If the CTMU is being used as a time delay, both capacitance and current source are fixed, as well as the voltage
supplied to the comparator circuit. The delay of a signal
is determined by the amount of time it takes the voltage
to charge to the comparator threshold voltage.
18.2.1
THEORY OF OPERATION
The operation of the CTMU is based on the equation
for charge:
I=C•
dV
dT
More simply, the amount of charge measured in
coulombs in a circuit is defined as current in amperes
(I) multiplied by the amount of time in seconds that the
current flows (t). Charge is also defined as the capacitance in farads (C) multiplied by the voltage of the
circuit (V). It follows that:
I•t=C•V
The CTMU module provides a constant, known current
source. The A/D Converter is used to measure (V) in
the equation, leaving two unknowns: capacitance (C)
and time (t). The above equation can be used to calculate capacitance or time, by either the relationship
using the known fixed capacitance of the circuit:
t = (C • V)/I
or by:
C = (I • t)/V
using a fixed time that the current source is applied to
the circuit.
18.2.2
CURRENT SOURCE
At the heart of the CTMU is a precision current source,
designed to provide a constant reference for measurements. The level of current is user-selectable across
three ranges, or a total of two orders of magnitude, with
the ability to trim the output in ±2% increments
(nominal). The current range is selected by the
IRNG bits (CTMUICON), with a value of
‘01’ representing the lowest range.
2010-2017 Microchip Technology Inc.
Current trim is provided by the ITRIM bits
(CTMUICON). These six bits allow trimming of
the current source in steps of approximately 2% per
step. Half of the range adjusts the current source positively and the other half reduces the current source. A
value of ‘000000’ is the neutral position (no change). A
value of ‘100001’ is the maximum negative adjustment
(approximately -62%) and ‘011111’ is the maximum
positive adjustment (approximately +62%).
18.2.3
EDGE SELECTION AND CONTROL
CTMU measurements are controlled by edge events
occurring on the module’s two input channels. Each
channel, referred to as Edge 1 and Edge 2, can be configured to receive input pulses from one of the edge
input pins (CTED1 and CTED2) or CCPx Special Event
Triggers (ECCP1 and CCP2). The input channels are
level-sensitive, responding to the instantaneous level
on the channel rather than a transition between levels.
The inputs are selected using the EDG1SEL and
EDG2SEL bit pairs (CTMUCONL, 6:5>).
In addition to source, each channel can be configured for
event polarity using the EDGE2POL and EDGE1POL
bits (CTMUCONL). The input channels can also
be filtered for an edge event sequence (Edge 1 occurring before Edge 2) by setting the EDGSEQEN bit
(CTMUCONH).
18.2.4
EDGE STATUS
The CTMUCONL register also contains two status bits,
EDG2STAT and EDG1STAT (CTMUCONL).
Their primary function is to show if an edge response
has occurred on the corresponding channel. The
CTMU automatically sets a particular bit when an edge
response is detected on its channel. The level-sensitive
nature of the input channels also means that the status
bits become set immediately if the channel’s configuration is changed and matches the channel’s current
state.
The module uses the edge status bits to control the current source output to external analog modules (such as
the A/D Converter). Current is only supplied to external
modules when only one (not both) of the status bits is
set. Current is shut off when both bits are either set or
cleared. This allows the CTMU to measure current only
during the interval between edges. After both status
bits are set, it is necessary to clear them before another
measurement is taken. Both bits should be cleared
simultaneously, if possible, to avoid re-enabling the
CTMU current source.
In addition to being set by the CTMU hardware, the
edge status bits can also be set by software. This permits a user application to manually enable or disable
the current source. Setting either (but not both) of the
bits enables the current source. Setting or clearing both
bits at once disables the source.
DS30009977G-page 233
PIC18F66K80 FAMILY
18.2.5
INTERRUPTS
The CTMU sets its interrupt flag (PIR3) whenever
the current source is enabled, then disabled. An interrupt is generated only if the corresponding interrupt
enable bit (PIE3) is also set. If edge sequencing is
not enabled (i.e., Edge 1 must occur before Edge 2), it
is necessary to monitor the edge status bits and
determine which edge occurred last and caused the
interrupt.
18.3
CTMU Module Initialization
The following sequence is a general guideline used to
initialize the CTMU module:
1.
2.
3.
4.
Select the current source range using the
IRNGx bits (CTMUICON).
Adjust the current source trim using the ITRIMx
bits (CTMUICON).
Configure the edge input sources for Edge 1 and
Edge 2 by setting the EDG1SEL and EDG2SEL
bits (CTMUCONL and , respectively).
Configure the input polarities for the edge inputs
using the EDG1POL and EDG2POL bits
(CTMUCONL).
The default configuration is for negative edge
polarity (high-to-low transitions).
5.
Enable edge sequencing using the EDGSEQEN
bit (CTMUCONH).
By default, edge sequencing is disabled.
6.
Select the operating mode (Measurement or Time
Delay) with the TGEN bit (CTMUCONH).
The default mode
Measurement.
7.
is
Time/Capacitance
Configure the module to automatically trigger
an A/D conversion when the second edge
event has occurred using the CTTRIG bit
(CTMUCONH).
The conversion trigger is disabled by default.
8.
Discharge the connected circuit by setting the
IDISSEN bit (CTMUCONH).
9. After waiting a sufficient time for the circuit to
discharge, clear the IDISSEN bit.
10. Disable the module by clearing the CTMUEN bit
(CTMUCONH).
11. Clear the Edge Status bits, EDG2STAT and
EDG1STAT (CTMUCONL).
Both bits should be cleared simultaneously, if
possible, to avoid re-enabling the CTMU current
source.
12. Enable both edge inputs by setting the EDGEN
bit (CTMUCONH).
13. Enable the module by setting the CTMUEN bit.
DS30009977G-page 234
Depending on the type of measurement or pulse
generation being performed, one or more additional
modules may also need to be initialized and configured
with the CTMU module:
• Edge Source Generation: In addition to the
external edge input pins, ECCP1/CCP2 Special
Event Triggers can be used as edge sources for
the CTMU.
• Capacitance or Time Measurement: The CTMU
module uses the A/D Converter to measure the
voltage across a capacitor that is connected to one
of the analog input channels.
• Pulse Generation: When generating system clock
independent, output pulses, the CTMU module
uses Comparator 2 and the associated
comparator voltage reference.
18.4
Calibrating the CTMU Module
The CTMU requires calibration for precise measurements of capacitance and time, as well as for accurate
time delay. If the application only requires measurement
of a relative change in capacitance or time, calibration is
usually not necessary. An example of a less precise
application is a capacitive touch switch, in which the
touch circuit has a baseline capacitance and the added
capacitance of the human body changes the overall
capacitance of a circuit.
If actual capacitance or time measurement is required,
two hardware calibrations must take place:
• The current source needs calibration to set it to a
precise current.
• The circuit being measured needs calibration to
measure or nullify any capacitance other than that
to be measured.
18.4.1
CURRENT SOURCE CALIBRATION
The current source on board the CTMU module has a
range of ±62% nominal for each of three current
ranges. For precise measurements, it is possible to
measure and adjust this current source by placing a
high-precision resistor, RCAL, onto an unused analog
channel. An example circuit is shown in Figure 18-2.
To measure the current source:
1.
2.
3.
4.
5.
6.
Initialize the A/D Converter.
Initialize the CTMU.
Enable the current source by setting EDG1STAT
(CTMUCONL).
Issue time delay for voltage across RCAL to
stabilize and A/D sample/hold capacitor to charge.
Perform the A/D conversion.
Calculate the current source current using
I = V / RCAL, where RCAL is a high-precision
resistance and V is measured by performing an
A/D conversion.
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
The CTMU current source may be trimmed with the
trim bits in CTMUICON, using an iterative process to
get the exact current desired. Alternatively, the nominal
value without adjustment may be used. That value may
be stored by software, for use in all subsequent
capacitive or time measurements.
To calculate the optimal value for RCAL, the nominal
current must be chosen.
For example, if the A/D Converter reference voltage is
3.3V, use 70% of full scale (or 2.31V) as the desired
approximate voltage to be read by the A/D Converter. If
the range of the CTMU current source is selected to be
0.55 A, the resistor value needed is calculated as
RCAL = 2.31V/0.55 A, for a value of 4.2 MΩ. Similarly,
if the current source is chosen to be 5.5 A, RCAL would
be 420,000Ω, and 42,000Ω if the current source is set
to 55 A.
FIGURE 18-2:
CTMU CURRENT SOURCE
CALIBRATION CIRCUIT
PIC18F66K80
Current Source
CTMU
A value of 70% of full-scale voltage is chosen to make
sure that the A/D Converter is in a range that is well
above the noise floor. If an exact current is chosen to
incorporate the trimming bits from CTMUICON, the
resistor value of RCAL may need to be adjusted accordingly. RCAL also may be adjusted to allow for available
resistor values. RCAL should be of the highest precision
available, in light of the precision needed for the circuit
that the CTMU will be measuring. A recommended
minimum would be 0.1% tolerance.
The following examples show a typical method for
performing a CTMU current calibration.
• Example 18-1 demonstrates how to initialize the
A/D Converter and the CTMU.
This routine is typical for applications using both
modules.
• Example 18-2 demonstrates one method for the
actual calibration routine.
This method manually triggers the A/D Converter to
demonstrate the entire step-wise process. It is also
possible to automatically trigger the conversion by
setting the CTMU’s CTTRIG bit (CTMUCONH).
A/D
Trigger
A/D Converter
ANx
RCAL
A/D
MUX
2010-2017 Microchip Technology Inc.
DS30009977G-page 235
PIC18F66K80 FAMILY
EXAMPLE 18-1:
SETUP FOR CTMU CALIBRATION ROUTINES
#include "p18cxxx.h"
/**************************************************************************/
/*Setup CTMU *****************************************************************/
/**************************************************************************/
void setup(void)
{ //CTMUCON - CTMU Control register
CTMUCONH = 0x00;
//make sure CTMU is disabled
CTMUCONL = 0x90;
//CTMU continues to run when emulator is stopped,CTMU continues
//to run in idle mode,Time Generation mode disabled, Edges are blocked
//No edge sequence order, Analog current source not grounded, trigger
//output disabled, Edge2 polarity = positive level, Edge2 source =
//source 0, Edge1 polarity = positive level, Edge1 source = source 0,
// Set Edge status bits to zero
//CTMUICON - CTMU Current Control Register
CTMUICON = 0x01;
//0.55uA, Nominal - No Adjustment
/**************************************************************************/
//Setup AD converter;
/**************************************************************************/
TRISA=0x04;
//set channel 2 as an input
// Configured AN2 as an analog channel
// ANCON1
ANCON1 = 0x04;
// ADCON1
ADCON2bits.ADFM=1;
ADCON2bits.ACQT=1;
ADCON2bits.ADCS=2;
// Result format 1= Right justified
// Acquisition time 7 = 20TAD 2 = 4TAD 1=2TAD
// Clock conversion bits 6= FOSC/64 2=FOSC/32
// ADCON1
ADCON1bits.VCFG0 =0;
ADCON1bits.VCFG1 =0;
ADCON1bits.VNCFG = 0;
ADCON1bits.CHS=2;
//
//
//
//
ADCON0bits.ADON=1;
// Turn on ADC
Vref+ = AVdd
Vref+ = AVdd
Vref- = AVss
Select ADC channel
}
DS30009977G-page 236
2010-2017 Microchip Technology Inc.
PIC18F66K80 FAMILY
EXAMPLE 18-2:
CURRENT CALIBRATION ROUTINE
#include "p18cxxx.h"
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