PIC18F26Q10-E/STX

PIC18F26/45/46Q10 28/40-Pin, Low-Power, High-Performance Microcontrollers Description PIC18F26/45/46Q10 microcontrollers feature analog, core independent, and communication peripherals for a wide range of general purpose and low-power applications. These 28/40/44-pin devices are equipped with a 10-bit ADC with Computation (ADC2) automating Capacitive Voltage Divider (CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and performing automatic threshold comparisons. They also offer a set of core independent peripherals such as Complementary Waveform Generator (CWG), Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/ Memory Scan, Zero-Cross Detect (ZCD), Configurable Logic Cell (CLC), and Peripheral Pin Select (PPS), providing increased design flexibility and lower system cost. Core Features • C Compiler Optimized RISC Architecture • Operating Speed: – DC – 64 MHz clock input over the full VDD range – 62.5 ns minimum instruction cycle • Programmable 2-Level Interrupt Priority • 31-Level Deep Hardware Stack • Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT) • Four 16-Bit Timers (TMR0/1/3/5) • Low-Current Power-on Reset (POR) • Power-up Timer (PWRT) • Brown-out Reset (BOR) • Low-Power BOR (LPBOR) Option • Windowed Watchdog Timer (WWDT): – Watchdog Reset on too long or too short interval between watchdog clear events – Variable prescaler selection – Variable window size selection – All sources configurable in hardware or software Memory • • • • Up to 64K Bytes Program Flash Memory Up to 3615 Bytes Data SRAM Memory Up to 1024 Bytes Data EEPROM Programmable Code Protection © 2019 Microchip Technology Inc. Preliminary Datasheet DS40001996C-page 1 PIC18F26/45/46Q10 • Direct, Indirect and Relative Addressing modes Operating Characteristics • Operating Voltage Range: – 1.8V to 5.5V • Temperature Range: – Industrial: -40°C to 85°C – Extended: -40°C to 125°C Power-Saving Operation Modes • • • • Doze: CPU and Peripherals Running at Different Cycle Rates (typically CPU is lower) Idle: CPU Halted While Peripherals Operate Sleep: Lowest Power Consumption Peripheral Module Disable (PMD): – Ability to selectively disable hardware module to minimize active power consumption of unused peripherals • Extreme Low-Power mode (XLP) – Sleep: 500 nA typical @ 1.8V – Sleep and Watchdog Timer: 900 nA typical @ 1.8V Digital Peripherals • Configurable Logic Cell (CLC): – Integrated combinational and sequential logic • Complementary Waveform Generator (CWG): – Rising and falling edge dead-band control – Full-bridge, half-bridge, 1-channel drive – Multiple signal sources • Capture/Compare/PWM (CCP) modules: – Two CCPs – 16-bit resolution for Capture/Compare modes – 10-bit resolution for PWM mode • 10-Bit Pulse-Width Modulators (PWM): – Two 10-bit PWMs • Serial Communications: – Two Enhanced USART (EUSART) with Auto-Baud Detect, Auto-wake-up on Start. RS-232, RS-485, LIN compatible – SPI – I2C, SMBus and PMBus™ compatible • Up to 35 I/O Pins and One Input Pin: – Individually programmable pull-ups – Slew rate control © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 2 PIC18F26/45/46Q10 • • • • – Interrupt-on-change on all pins – Input level selection control Programmable CRC with Memory Scan: – Reliable data/program memory monitoring for Fail-Safe operation (e.g., Class B) – Calculate CRC over any portion of Flash or EEPROM – High-speed or background operation Hardware Limit Timer (TMR2/4/6+HLT): – Hardware monitoring and Fault detection Peripheral Pin Select (PPS): – Enables pin mapping of digital I/O Data Signal Modulator (DSM) Analog Peripherals • 10-Bit Analog-to-Digital Converter with Computation (ADC2): – 35 external channels – Conversion available during Sleep – Four internal analog channels – Internal and external trigger options – Automated math functions on input signals: • Averaging, filter calculations, oversampling and threshold comparison – 8-bit hardware acquisition timer • Hardware Capacitive Voltage Divider (CVD) Support: – 8-bit precharge timer – Adjustable Sample-and-Hold capacitor array – Guard ring digital output drive • Zero-Cross Detect (ZCD): – Detect when AC signal on pin crosses ground • 5-Bit Digital-to-Analog Converter (DAC): – Output available externally – Programmable 5-bit voltage (% of VDD,[VREF+ - VREF-], FVR) – Internal connections to comparators and ADC • Two Comparators (CMP): – Four external inputs – External output via PPS • Fixed Voltage Reference (FVR) Module: – 1.024V, 2.048V and 4.096V output levels – Two buffered outputs: One for DAC/CMP and one for ADC Clocking Structure • High-Precision Internal Oscillator Block (HFINTOSC): – Selectable frequencies up to 64 MHz – ±1% at calibration © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 3 PIC18F26/45/46Q10 • 32 kHz Low-Power Internal Oscillator (LFINTOSC) • External 32 kHz Crystal Oscillator (SOSC) • External High-frequency Oscillator Block: – Three crystal/resonator modes – Digital Clock Input mode – 4x PLL with external sources • Fail-Safe Clock Monitor: – Allows for safe shutdown if external clock stops • Oscillator Start-up Timer (OST) Programming/Debug Features • In-Circuit Serial Programming™ (ICSP™) via Two Pins • In-Circuit Debug (ICD) with Three Breakpoints via Two Pins • Debug Integrated On-Chip PIC18F26/45/46Q10 Family Types CLC Low Voltage Detect (LVD) 8-bit TMR with HLT CRC with Memory Scan EUSART I2C/SPI PPS Peripheral Module Disable Temperature Indicator Debug(1) 24 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I PIC18F45Q10 32k 2304 256 36 4 2 35 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I PIC18F46Q10 64k 3615 1024 36 4 2 35 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I Timer CWG 2 Windowed Watchdog Zero-Cross Detect 4 CCP/10-bit PWM 5-bit DAC 25 Computation (ch) Comparators 1024 10-bit ADC2 with 16-bit Timers 3615 Data EEPROM (bytes) 64k Device Data SRAM (bytes)(2) PIC18F26Q10 Program Memory Flash (bytes) I/O Pins Table 1.  Devices included in this data sheet Note:  1. Debugging Methods: (I) – Integrated on-chip. 2. SRAM includes 256 bytes of SECTOR space which is not included in the data size displayed by MPLAB X. CWG CLC Low Voltage Detect (LVD) 8-bit TMR with HLT CRC with Memory Scan EUSART I2C/SPI PPS Peripheral Module Disable Temperature Indicator Debug(1) 2 24 1 1 2/2 1 0 1 3 Y Y 1 1 Y Y Y I PIC18F25Q10 32k 2304 256 25 4 2 24 1 1 2/2 1 0 1 3 Y Y 1 1 Y Y Y I PIC18F27Q10 128k 3615 1024 25 4 2 24 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I © 2019 Microchip Technology Inc. Datasheet Preliminary Timer Zero-Cross Detect 4 Windowed Watchdog 5-bit DAC 25 CCP/10-bit PWM Comparators 256 Computation (ch) 16-bit Timers 1280 10-bit ADC2 with I/O Pins 16k Device Data SRAM (bytes)(2) PIC18F24Q10 Program Memory Flash (bytes) Data EEPROM (bytes) Table 2. Devices not included in this data sheet DS40001996C-page 4 PIC18F26/45/46Q10 PPS Peripheral Module Disable Temperature Indicator Debug(1) Y I2C/SPI 3 EUSART 1 CRC with Memory Scan 8-bit TMR with HLT 8 Timer Low Voltage Detect (LVD) 1 2/2 Windowed Watchdog CLC 1 CCP/10-bit PWM 1 CWG 35 Zero-Cross Detect 2 Computation (ch) 4 10-bit ADC2 with 36 5-bit DAC 1024 Comparators 3615 16-bit Timers 128k I/O Pins PIC18F47Q10 Data EEPROM (bytes) Device Data SRAM (bytes)(2) Program Memory Flash (bytes) ...........continued Y 2 2 Y Y Y I Note:  1. Debugging Methods: (I) – Integrated on-chip. 2. SRAM includes 256 bytes of SECTOR space which is not included in the data size displayed by MPLAB X. Data Sheet Index: 1. 2. DS40001945 Data Sheet, 28-Pin, 8-bit Flash Microcontrollers DS40002043 Data Sheet, 28/40-Pin, 8-bit Flash Microcontrollers Packages Important:  For other small form-factor package availability and marking information, visit http://www.microchip.com/packaging or contact your local Microchip sales office. TQFP (PT) PDIP (P) QFN (MP) (5x5x0.9) PIC18F45Q10 ● ● ● PIC18F46Q10 ● ● ● Packages PIC18F26Q10 SPDIP (SP) SOIC (SO) SSOP (SS) QFN (ML) (6x6x0.9) VQFN (STX) (4x4x1) ● ● ● ● ● Important:  Pin details are subject to change. © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 5 Filename: Title: Last Edit: First Used: Notes: PIC18F26/45/46Q10 00-000028A.vsd 28-pin DIP 10/3/2018 N/A Generic 28-pin dual in-line diagram Pin Diagrams Figure 1. 28-pin SPDIP, SSOP, SOIC Rev. 00-000028A 10/3/2018 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 VSS RA7 RA6 RC0 RC1 RC2 RC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RC7 RC6 RC5 RC4 RA1 RA0 RE3/MCLR/VPP RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 Figure 2. 28-pin QFN VQFN Rev. 00-000028B 6/23/2017 28 27 26 25 24 23 22 RA2 1 RA3 RA4 RA5 VSS RA7 RA6 21 RB3 20 RB2 2 3 19 RB1 18 RB0 4 5 17 VDD 16 VSS 6 7 15 RC7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 8 9 10 11 12 13 14 Note:  It is recommended that the exposed bottom pad be connected to VSS, however it must not be the only VSS connection to the device. © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 6 Filename: Title: Last Edit: First Used: Notes: 00-000040A.vsd 40-pin DIP 10/3/2018 N/A Generic 40-pin dual in-line diagram PIC18F26/45/46Q10 Figure 3. 40-pin PDIP Rev. 00-000040A 10/3/2018 Filename: Title: Last Edit: First Used: Notes: MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 RE0 RE1 RE2 VDD VSS RA7 RA6 RC0 RC1 00-000040B.vsd RC2 40-pin QFN RC3 11/6/2017 N/A RD0 Generic 40-pin QFN diagram RD1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 26 25 24 23 22 21 RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4 RD3 RD2 Figure 4. 40-pin QFN RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 Rev. 00-000040B 11/6/2017 40 39 38 37 36 35 34 33 32 31 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 RB3 RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 11 12 13 14 15 16 17 18 19 20 Note:  It is recommended that the exposed bottom pad be connected to VSS, however it must not be the only VSS connection to the device. © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 7 Filename: Title: Last Edit: First Used: Notes: 00-000044A.vsd 44-pin TQFP 11/6/2017 N/A Generic 44-pin TQFP diagram PIC18F26/45/46Q10 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 NC Figure 5. 44-pin TQFP Rev. 00-000044A 11/6/2017 44 43 42 41 40 39 38 37 36 35 34 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 1 2 3 4 5 6 7 8 9 10 11 NC RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 33 32 31 30 29 28 27 26 25 24 23 NC NC RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 12 13 14 15 16 17 18 19 20 21 22 Pin Allocation Tables Table 3. 28-Pin Allocation Table I/O(2) RA0 28-Pin SPDIP, SOIC, SSOP 28-Pin (V)QFN A/D Reference 2 27 ANA0 — Comparator Timers DSM MSSP Pullup Basic — — — Y — IOCA1 — — — Y — — IOCA2 — — — Y — — — IOCA3 — MDCARL(1) — Y — CCP CWG — — — — IOCA0 — — — — — — — C1IN1+ — — C1IN0- ZCD Interrupt EUSART C2IN0RA1 3 28 ANA1 — C1IN1C2IN1- RA2 4 1 ANA2 DAC1OUT1 C1IN0+ VREF- (DAC) C2IN0+ VREF- (ADC) RA3 5 2 ANA3 VREF+ (DAC) VREF+ (ADC) RA4 6 3 ANA4 — — T0CKI(1) — — — IOCA4 — MDCARH(1) — Y — RA5 7 4 ANA5 — — — — — — IOCA5 — MDSRC(1) SS1(1) Y — RA6 10 7 ANA6 — — — — — — IOCA6 — — — Y CLKOUT OSC2 RA7 9 6 ANA7 — — — — — — IOCA7 — — — Y OSC1 CLKIN RB0 21 18 ANB0 — C2IN1+ — — CWG1(1) ZCDIN IOCB0 — — SS2(1) Y — — — SCK2(1) Y — INT0(1) RB1 22 19 ANB1 — © 2019 Microchip Technology Inc. C1IN3C2IN3- — — — — IOCB1 INT1(1) Datasheet Preliminary SCL2(3,4) DS40001996C-page 8 PIC18F26/45/46Q10 ...........continued I/O(2) RB2 28-Pin SPDIP, SOIC, SSOP 28-Pin (V)QFN A/D Reference 23 20 ANB2 — Comparator Timers — — CCP CWG — — ZCD Interrupt EUSART — IOCB2 INT2(1) — DSM MSSP Pullup Basic — SDI2(1) Y — SDA2(3,4) RB3 24 21 ANB3 — C1IN2C2IN2- — — — — IOCB3 — — — Y — RB4 25 22 ANB4 — — — — — IOCB4 — — — Y — RB5 26 23 ANB5 — — T5G(1) T1G(1) — — — IOCB5 — — — Y — RB6 27 24 ANB6 — — — — — — IOCB6 — — — Y ICSPCLK RB7 28 25 ANB7 DAC1OUT2 — T6IN(1) — — — IOCB7 — — — Y ICSPDAT — T1CKI(1) T3CKI(1) — — — IOCC0 — — — Y SOSCO CCP2(1) — — IOCC1 — — — Y SOSCIN SOSCI T5CKI(1) CCP1(1) T2IN(1) — — — IOCC2 — — — Y — — — IOCC3 — — SCK1(1) SCL1(3,4) Y — — — SDI1(1) SDA1(3,4) Y — RC0 11 8 ANC0 — T3G(1) RC1 12 9 ANC1 — — — RC2 13 10 ANC2 — — RC3 14 11 ANC3 — — RC4 15 12 ANC4 — — — — — — IOCC4 RC5 16 13 ANC5 — — T4IN(1) — — — IOCC5 — — — Y — RC6 17 14 ANC6 — — — — — — IOCC6 CK1(1,3) — — Y — RC7 18 15 ANC7 — — — — — — IOCC7 RX1/ DT1(1,3) — — Y — RE3 1 26 — — — — — — — IOCE3 — — — Y Vpp/MCLR VSS 19 16 — — — — — — — — — — — — VDD(5) 20 17 — — — — — — — — — — — — VSS VDD VSS 8 5 — — — — — — — — — — — — VSS OUT(2) — — ADGRDA ADGRDB — C1OUT C2OUT TMR0 CCP1 CCP2 CWG1A CWG1B — — DSM SDO1 SCK1 — — PWM3 CWG1C TX1/ CK1(3) DT1(3) PWM4 CWG1D Note:  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which port pins may be used for this signal. 2. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table. 3. 4. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. 5. A 0.1 uF bypass capacitor to VSS is required on the VDD pin. Table 4.  40/44-Pin Allocation Table I/O(2) 40-Pin PDIP 4044-Pin Pin TQFP QFN A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pullup Basic RA0 2 17 19 ANA0 — C1INOC2IN0- — — — — IOCA0 — — — Y — RA1 3 18 20 ANA1 — C1IN1- — — — — IOCA1 — — — Y — C2IN1- © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 9 PIC18F26/45/46Q10 ...........continued I/O(2) RA2 40-Pin PDIP 4 4044-Pin Pin TQFP QFN 19 21 A/D ANA2 Reference Comparator Timers DSM MSSP Pullup Basic — — — Y — IOCA3 — MDCARL(1) — Y — IOCA4 — MDCARH(1) — Y — SS1(1) CCP CWG — — — — IOCA2 C1IN1+ — — — — — T0CKI(1) — — — DAC1OUT1 C1IN0+ VREF(DAC5) C2IN0+ ZCD Interrupt EUSART VREF(ADC) RA3 5 20 22 ANA3 VREF+ (DAC5) VREF+ (ADC) RA4 6 21 23 ANA4 — RA5 7 22 24 ANA5 — — — — — — IOCA5 — MDSRC(1) Y — RA6 14 29 31 ANA6 — — — — — — IOCA6 — — — Y CLKOUT RA7 13 28 30 ANA7 — — — — — — IOCA7 — — — Y RB0 33 8 8 ANB0 — C2IN1+ — — CWG1(1) ZCDIN IOCB0 — — SS2(1) Y — — — SCK2(1) Y — Y — OSC2 OSC1 CLKIN INT0(1) RB1 34 9 9 ANB1 — C1IN3- — — — — INT1(1) C2IN3RB2 35 10 10 ANB2 — — IOCB1 — — — — IOCB2 SCL2(3,4) — — INT2(1) RB3 36 11 11 ANB3 — RB4 37 12 14 ANB4 — RB5 38 13 15 ANB5 — C1IN2- SDI2(1) SDA2(3,4) — — — — IOCB3 — — — Y — — T5G(1) — — — IOCB4 — — — Y — — T1G(1) — — — IOCB5 — — — Y — — — Y ICSPCLK C2IN2- RB6 39 14 16 ANB6 — — — — — — IOCB6 CK2(1,3) — — — IOCB7 RX2/ DT2(1,3) — — Y ICSPDAT — — — IOCC0 — — — Y SOSCO CCP2(1) — — IOCC1 — — — Y SOSCIN RB7 40 15 17 ANB7 DAC1OUT2 — T6IN(1) RC0 15 30 32 ANC0 — — T1CKI(1) T3CKI(1) T3G(1) RC1 16 31 35 ANC1 — — — SOSCI RC2 RC3 17 18 32 33 36 37 ANC2 ANC3 — — — — T5CKI(1) CCP1(1) T2IN(1) — — — — — IOCC2 IOCC3 — — — — Y — — SCK1(1) Y — — — SCL1(3,4) RC4 23 38 42 ANC4 — — — — — — IOCC4 — — SDI1(1) SDA1(3,4) RC5 24 39 43 ANC5 — — T4IN(1) — — — IOCC5 — — — Y — RC6 25 40 44 ANC6 — — — — — — IOCC6 CK1(1,3) — — Y — RC7 26 1 1 ANC7 — — — — — — IOCC7 RX1/ DT1(1,3) — — Y — RD0 19 34 38 AND0 — — — — — — — — — — Y — RD1 20 35 39 AND1 — — — — — — — — — — Y — © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 10 PIC18F26/45/46Q10 ...........continued 4044-Pin Pin TQFP QFN I/O(2) 40-Pin PDIP DSM MSSP Pullup Basic RD2 21 36 40 AND2 — — — — — Y — RD3 22 37 41 AND3 — — — — — Y — RD4 27 2 2 AND4 RD5 28 3 3 AND5 — — — — — Y — — — — — — Y — RD6 29 4 4 — — — — — — Y — RD7 30 5 — — — — — — — Y — RE0 8 RE1 9 — — — — — — — — Y — — — — — — — — — Y — RE2 — — — — — — — — — Y — — — — — — — IOCE3 — — — Y Vpp/MCLR — — — — — — — — — — — VSS — — — — — — — — — — — — VDD 28 — — — — — — — — — — — — VSS 29 — — — — — — — — — — — — VSS — ADGRDA — C1OUT TMR0 CCP1 CCP2 CWG1A — — TX1/ CK1(3) DSM SDO1 SCK1 — — A/D Reference Comparator Timers CCP CWG — — — — — — — — — — — — — — — — — — — — AND6 — — — — 5 AND7 — — — 23 25 ANE0 — — 24 26 ANE1 — — 10 25 27 ANE2 — RE3 1 16 18 — VSS 12 6 6 — VDD(5) 11 7 7 VDD(5) 32 26 VSS 31 27 OUT(2) — — ADGRDB C2OUT PWM3 PWM4 ZCD Interrupt EUSART CWG1B CWG1C CWG1D DT1(3) SDO2 TX2/ CK2(3) SCK2 DT2(3) Note:  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which port pins may be used for this signal. 2. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table. 3. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. 4. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. 5. A 0.1 uF bypass capacitor to VSS is required on all VDD pins. © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 11 PIC18F26/45/46Q10 Table of Contents Description.......................................................................................................................1 Core Features..................................................................................................................1 Memory............................................................................................................................1 Operating Characteristics................................................................................................ 2 Power-Saving Operation Modes......................................................................................2 Digital Peripherals........................................................................................................... 2 Analog Peripherals.......................................................................................................... 3 Clocking Structure........................................................................................................... 3 Programming/Debug Features........................................................................................ 4 PIC18F26/45/46Q10 Family Types................................................................................. 4 Packages.........................................................................................................................5 Pin Diagrams................................................................................................................... 6 Pin Allocation Tables....................................................................................................... 8 1. Device Overview......................................................................................................15 2. Guidelines for Getting Started with PIC18F26/45/46Q10 Microcontrollers............. 23 3. Device Configuration............................................................................................... 28 4. Oscillator Module (with Fail-Safe Clock Monitor).....................................................44 5. Reference Clock Output Module............................................................................. 66 6. Power-Saving Operation Modes..............................................................................72 7. (PMD) Peripheral Module Disable........................................................................... 81 8. Resets..................................................................................................................... 90 9. (WWDT) Windowed Watchdog Timer....................................................................104 10. Memory Organization............................................................................................ 116 11. (NVM) Nonvolatile Memory Control.......................................................................151 © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 12 PIC18F26/45/46Q10 12. 8x8 Hardware Multiplier.........................................................................................180 13. (CRC) Cyclic Redundancy Check Module with Memory Scanner.........................185 14. Interrupts............................................................................................................... 206 15. I/O Ports................................................................................................................ 237 16. Interrupt-on-Change.............................................................................................. 285 17. (PPS) Peripheral Pin Select Module......................................................................301 18. Timer0 Module.......................................................................................................312 19. Timer1 Module with Gate Control.......................................................................... 321 20. Timer2 Module.......................................................................................................341 21. Capture/Compare/PWM Module........................................................................... 368 22. (PWM) Pulse-Width Modulation............................................................................ 384 23. (ZCD) Zero-Cross Detection Module.....................................................................393 24. (CWG) Complementary Waveform Generator Module..........................................401 25. (CLC) Configurable Logic Cell...............................................................................431 26. (DSM) Data Signal Modulator Module...................................................................454 27. (MSSP) Master Synchronous Serial Port Module................................................. 469 28. (EUSART) Enhanced Universal Synchronous Asynchronous Receiver Transmitter ...............................................................................................................................533 29. (FVR) Fixed Voltage Reference.............................................................................568 30. Temperature Indicator Module...............................................................................573 31. (DAC) 5-Bit Digital-to-Analog Converter Module................................................... 576 32. (ADC2) Analog-to-Digital Converter with Computation Module............................. 582 33. (CMP) Comparator Module................................................................................... 630 34. (HLVD) High/Low-Voltage Detect.......................................................................... 643 35. Register Summary.................................................................................................651 36. In-Circuit Serial Programming™ (ICSP™) .............................................................662 37. Instruction Set Summary....................................................................................... 665 © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 13 PIC18F26/45/46Q10 38. Development Support............................................................................................764 39. Electrical Specifications.........................................................................................769 40. DC and AC Characteristics Graphs and Tables.................................................... 801 41. Packaging Information...........................................................................................802 42. Revision History.....................................................................................................824 The Microchip Web Site.............................................................................................. 825 Customer Change Notification Service........................................................................825 Customer Support....................................................................................................... 825 Product Identification System...................................................................................... 826 Microchip Devices Code Protection Feature............................................................... 826 Legal Notice.................................................................................................................827 Trademarks................................................................................................................. 827 Quality Management System Certified by DNV...........................................................828 Worldwide Sales and Service......................................................................................829 © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 14 PIC18F26/45/46Q10 Device Overview 1. Device Overview This document contains device specific information for the following devices: • PIC18F26Q10 • PIC18F45Q10 • PIC18F46Q10 This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance Program Flash Memory. In addition to these features, the PIC18F26/45/46Q10 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications. 1.1 New Core Features 1.1.1 Low-Power Technology All of the devices in the PIC18F26/45/46Q10 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • Alternate Run modes: By clocking the microcontroller from the secondary oscillator or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. • Multiple Idle modes: The controller can also run with its CPU core disabled but the peripherals are still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. • On-the-fly mode switching: The Power-Managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design. • Peripheral Module Disable: Modules that are not being used in the code can be selectively disabled using the PMD module. This further reduces the power consumption. 1.1.2 Multiple Oscillator Options and Features All of the devices in the PIC18F26/45/46Q10family offer several different oscillator options. The PIC18F26/45/46Q10 family can be clocked from several different sources: • HFINTOSC – 1-64 MHz precision digitally controlled internal oscillator • LFINTOSC – 31 kHz internal oscillator • EXTOSC – External clock (EC) – Low-power oscillator (LP) – Medium power oscillator (XT) – High power oscillator (HS) • SOSC – Secondary oscillator circuit optimized for 31 kHz clock crystals • A Phase Lock Loop (PLL) frequency multiplier (4x) is available to the External Oscillator modes enabling clock speeds of up to 64 MHz © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 15 PIC18F26/45/46Q10 Device Overview • Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the LFINTOSC. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued operation or a safe application shutdown. 1.2 Other Special Features • Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 10K for program memory and 100K for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. • Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a boot loader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. • Extended Instruction Set: The PIC18F26/45/46Q10 family includes an optional extension to the PIC18 instruction set, which adds eight new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize reentrant application code originally developed in high-level languages, such as C. • Enhanced Peripheral Pin Select: The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital signals are included in the selections. All analog inputs and outputs remain fixed to their assigned pins. • Enhanced Addressable EUSART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). • 10-bit A/D Converter with Computation: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. It has a new module called ADC2 with computation features, which provides a digital filter and threshold interrupt functions. • Windowed Watchdog Timer (WWDT): – Timer monitoring of overflow and underflow events – Variable prescaler selection – Variable window size selection – All sources configurable in hardware or software 1.3 Details on Individual Family Members Devices in the PIC18F26/45/46Q10 family are available in 28-pin and 40/44-pin packages. The block diagram for this device is shown in Figure 1-1. The devices have the following differences: 1. 2. 3. 4. 5. 6. Program Flash Memory Data Memory SRAM Data Memory EEPROM A/D channels I/O ports Enhanced USART © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 16 PIC18F26/45/46Q10 Device Overview 7. Input Voltage Range/Power Consumption All other features for devices in this family are identical. These are summarized in the following Device Features table. The pinouts for all devices are listed in the pin summary tables. Table 1-1. Device Features Features PIC18F26Q10 PIC18F45Q10 PIC18F46Q10 Program Memory (Bytes) 65536 32768 65536 Program Memory (Instructions) 32768 16384 32768 Data Memory (Bytes) 3615 2048 3615 Data EEPROM Memory (Bytes) 1024 256 1024 A,B,C,E(1) A,B,C,D,E A,B,C,D,E Capture/Compare/PWM Modules (CCP) 2 2 2 10-Bit Pulse-Width Modulator (PWM) 2 2 2 4 internal 24 external 4 internal 35 external 4 internal 35 external 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin VQFN 28-pin QFN 40-pin PDIP 40-pin QFN 44-pin TQFP 40-pin PDIP 40-pin QFN 44-pin TQFP 4/3 4/3 4/3 2 MSSP, 2 EUSART 2 MSSP, 2 EUSART 2 MSSP, 2 EUSART Enhanced Complementary Waveform Generator (ECWG) 1 1 1 Zero-Cross Detect (ZCD) 1 1 1 Data Signal Modulator (DSM) 1 1 1 Configurable Logic Cell (CLC) 8 8 8 Yes Yes Yes I/O Ports 10-Bit Analog-to-Digital Module (ADC2) with Computation Accelerator Packages Timers (16-/8-bit) Serial Communications Peripheral Pin Select (PPS) © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 17 PIC18F26/45/46Q10 Device Overview ...........continued Features PIC18F26Q10 PIC18F45Q10 PIC18F46Q10 Peripheral Module Disable (PMD) Yes Yes Yes 16-bit CRC with NVMSCAN Yes Yes Yes Programmable High/LowVoltage Detect (HLVD) Yes Yes Yes Programmable Brown-out Reset (BOR) Yes Yes Yes POR, BOR, RESET Instruction, POR, BOR, RESET Instruction, POR, BOR, RESET Instruction, Stack Overflow, Stack Overflow, Stack Overflow, Stack Underflow Stack Underflow Stack Underflow (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR, WDT MCLR, WDT MCLR, WDT 75 Instructions; 83 with Extended Instruction Set enabled 75 Instructions; 83 with Extended Instruction Set enabled 75 Instructions; 83 with Extended Instruction Set enabled DC – 64 MHz DC – 64 MHz DC – 64 MHz Resets (and Delays) Instruction Set Operating Frequency Note 1: PORTE contains the single RE3 read-only bit. © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 18 PIC18F26/45/46Q10 Device Overview Figure 1-1. PIC18F26/45/46Q10 Family Block Diagram Rev. 30-000131B 6/14/2017 Data Bus Table Pointer Data Latch 8 8 inc/dec logic Data Memory PCLATU PCLATH 21 PORTA Address Latch 20 PCU PCH PCL Program Counter RA 12 Data Address 31-Level Stack 4 BSR Address Latch Program Memory (8/16/32/64 Kbytes) STKPTR 12 Data Latch 8 PORTB 12 RB inc/dec logic Table Latch Instruction Bus 4 Access Bank FSR0 FSR1 FSR2 Address Decode ROM Latch PORTC RC IR 8 State machine control signals Instruction Decode and Control PRODH PRODL 3 8 W BITOP 8 Internal Oscillator Block Power-up Timer SOSCI LFINTOSC Oscillator SOSCO 64 MHz Oscillator Oscillator Start-up Timer Power-on Reset OSC1(2) OSC2(2) Single-Supply Programming In-Circuit Debugger MCLR(1) BOR HLVD FVR DAC Note Comparators C1/C2 Brown-out Reset Fail-Safe Clock Monitor NVM Timer0 Controller CCP1 CCP2 PWM3 PWM4 Timer1 Timer3 Timer5 8 Timer2 Timer4 Timer6 RE3 is only available when MCLR functionality is disabled. 2: 3: PORTD and PORTE not implemented on 28-pin devices. PORTE RE(3) RE3(1) 8 Precision Band Gap Reference MSSP1 EUSART1 ECWG MSSP2 EUSART2 1: 8 ALU ZCD RD 8 8 Watchdog Timer PORTD(3) 8x8 Multiply FVR CRC-Scan DSM DAC PMD ADC 10-bit FVR FVR OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes. © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 19 PIC18F26/45/46Q10 Device Overview 1.4 Register and Bit Naming Conventions 1.4.1 Register Names When there are multiple instances of the same peripheral in a device, the Peripheral Control registers will be depicted as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The control registers section will show just one instance of all the register names with an ‘x’ in the place of the peripheral instance number. This naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device to maintain compatibility with other devices in the family that contain more than one. 1.4.2 Bit Names There are two variants for bit names: • Short name: Bit function abbreviation • Long name: Peripheral abbreviation + short name 1.4.2.1 Short Bit Names Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit. The bit names shown in the registers are the short name variant. Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short name is RegisterNamebits.ShortName. For example, the enable bit, EN, in the CM1CON0 register can be set in C programs with the instruction CM1CON0bits.EN = 1. Short names are generally not useful in assembly programs because the same name may be used by different peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short bit name are appended with an underscore plus the name of the register in which the bit resides to avoid naming contentions. 1.4.2.2 Long Bit Names Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to the peripheral, thereby making every long bit name unique. The long bit name for the COG1 enable bit is the COG1 prefix, G1, appended with the enable bit short name, EN, resulting in the unique bit name G1EN. Important:  The COG1 peripheral is used as an example. Not all devices have the COG peripheral. Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit can be set with the G1EN = 1 instruction. In assembly, this bit can be set with the BSF COG1CON0,G1EN instruction. 1.4.2.3 Bit Fields Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention. For example, the three Least Significant bits of the COG1CON0 register contain the Mode Control bits. The short name for this field is MD. There is no long bit name variant. Bit field access is only possible in C programs. The following example demonstrates a C program instruction for setting the COG1 to the Push-Pull mode: COG1CON0bits.MD = 0x5; © 2019 Microchip Technology Inc. Datasheet Preliminary DS40001996C-page 20 PIC18F26/45/46Q10 Device Overview Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name MD2 and the long bit name is G1MD2. The following two examples demonstrate assembly program sequences for setting the COG1 to Push-Pull mode: Example 1: MOVLW ANDWF MOVLW IORWF ~(1