PIC18FXXQ83/84
PIC18FXXQ83/84 Family Programming Specification
Introduction
This programming specification describes a SPI-based programming method for the PIC18FXXQ83/84 family of
microcontrollers. Programming Algorithms describes the programming commands, programming algorithms and
electrical specifications used in that particular programming method. APPENDIX B contains individual part numbers,
device identification and checksum values, pinout and packaging information, and Configuration Words.
Important:
• This is a SPI-compliant programming method with 8-bit commands.
• The low-voltage entry code is now 32 clocks and MSb first, unlike earlier PIC18 devices, which had
33 clocks and LSb first.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 1
PIC18FXXQ83/84
Table of Contents
Introduction.....................................................................................................................................................1
1.
Overview................................................................................................................................................. 4
1.1.
1.2.
1.3.
1.4.
2.
Memory Map........................................................................................................................................... 6
2.1.
2.2.
2.3.
2.4.
2.5.
2.6.
3.
Programming Data Flow...............................................................................................................4
Pin Utilization................................................................................................................................4
Hardware Requirements.............................................................................................................. 4
Write and/or Erase Section.......................................................................................................... 5
User ID Location...........................................................................................................................7
Device/Revision ID....................................................................................................................... 7
Device Configuration Information (DCI)....................................................................................... 7
Configuration Bytes...................................................................................................................... 7
DEVICE ID .................................................................................................................................. 9
REVISION ID .............................................................................................................................10
Programming Algorithms....................................................................................................................... 11
3.1.
3.2.
3.3.
3.4.
3.5.
Program/Verify Mode..................................................................................................................11
Programming Algorithms............................................................................................................18
Code Protection..........................................................................................................................23
Hex File Usage...........................................................................................................................23
CRC Checksum Computation.................................................................................................... 24
4.
Electrical Specifications........................................................................................................................ 25
5.
APPENDIX A: Revision History.............................................................................................................27
6.
APPENDIX B.........................................................................................................................................28
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
6.11.
6.12.
6.13.
6.14.
6.15.
6.16.
6.17.
CONFIG1 .................................................................................................................................. 29
CONFIG2 .................................................................................................................................. 30
CONFIG3................................................................................................................................... 31
CONFIG4................................................................................................................................... 32
CONFIG5................................................................................................................................... 33
CONFIG6................................................................................................................................... 34
CONFIG7................................................................................................................................... 35
CONFIG8................................................................................................................................... 36
CONFIG9................................................................................................................................... 37
CONFIG10................................................................................................................................. 38
CONFIG11..................................................................................................................................39
CRC Boot Polynomial.................................................................................................................41
CRC Boot Seed..........................................................................................................................42
CRC Boot Expected Value......................................................................................................... 43
CRC Polynomial......................................................................................................................... 44
CRC Seed.................................................................................................................................. 45
CRC Expected Value..................................................................................................................46
The Microchip Website.................................................................................................................................47
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 2
PIC18FXXQ83/84
Product Change Notification Service............................................................................................................47
Customer Support........................................................................................................................................ 47
Microchip Devices Code Protection Feature................................................................................................ 47
Legal Notice................................................................................................................................................. 47
Trademarks.................................................................................................................................................. 48
Quality Management System....................................................................................................................... 48
Worldwide Sales and Service.......................................................................................................................49
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 3
PIC18FXXQ83/84
Overview
1.
Overview
1.1
Programming Data Flow
Nonvolatile Memory (NVM) programming data can be supplied by either the high-voltage In-Circuit Serial
Programming™ (ICSP™) interface or the low-voltage In-Circuit Serial Programming (ICSP) interface. Data can be
programmed into the Program Flash Memory (PFM), Data EEPROM Memory, dedicated “User ID” locations and the
Configuration Bytes.
1.2
Pin Utilization
Five pins are needed for ICSP programming. The pins are listed in the table below. For pin locations and packaging
information, refer to Pin Utilization Table .
Table 1-1. PIN DESCRIPTIONS DURING PROGRAMMING
Pin Name
During Programming
Function
Pin Type
Pin Description
ISCPCLK
ICSPCLK
I
ISCPDAT
ICSPDAT
I/O
Data Input/Output - Schmitt
Trigger Input
MCLR/VPP
Program/Verify mode
I(1)
Program Mode Select
VDD
VDD
P
Power Supply
VSS
VSS
P
Ground
Clock Input - Schmitt
Trigger Input
Legend: I = Input, O = Output, P = Power
Note:
1. The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage
needs to be applied to the MCLR input. Since the MCLR is used for a level source, MCLR does not draw any
significant current.
1.3
Hardware Requirements
1.3.1
High-Voltage ICSP Programming
In High-Voltage ICSP mode, the device requires two programmable power supplies: one for VDD and one for the
MCLR/VPP pin.
1.3.2
Low-Voltage ICSP Programming
In Low-Voltage ICSP mode, the device can be programmed using a single VDD source in the device operating range.
The MCLR/VPP pin does not have to be brought to programming voltage, but can instead be left at the normal
operating voltage.
1.3.2.1
Single-Supply ICSP Programming
The device’s LVP Configuration bit enables single-supply (low-voltage) ICSP programming. The LVP bit defaults to a
‘1’ (enabled). The LVP bit may only be programmed to ‘0’ by entering the High-Voltage ICSP mode, where the
MCLR/VPP pin is raised to VIHH. Once the LVP bit is programmed to a ‘0’, only the High-Voltage ICSP mode is
available and can be used to program the device.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 4
PIC18FXXQ83/84
Overview
Important:
• The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying
VIHH to the MCLR/VPP pin.
• While in Low-Voltage ICSP mode, MCLR is always enabled, regardless of the MCLRE bit. Also, the
MCLR pin can no longer be used as a general purpose input.
1.4
Write and/or Erase Section
Erasing or writing is selected according to the command used to begin operation (see Table 3-1). The terminologies
used in this document, related to erasing/writing to the program memory, are defined in the table below.
Table 1-2. PROGRAMMING TERMS
1.4.1
Term
Definition
Programmed Cell
A memory cell at logic ‘0’
Erased Cell
A memory cell at logic ‘1’
Erase
Change memory cell from a ‘0’ to a ‘1’
Write
Change memory cell from a ‘1’ to a ‘0’
Program
Generic erase and/or write
Erasing Memory
Memory is erased by 128-word pages or in bulk, where ‘bulk’ includes many subsets of the total memory space. The
duration of the data memory erase is determined by the size of data memory. All Bulk ICSP Erase commands have
minimum VDD requirements, which are higher than the Page Erase and Write requirements.
Page erasing pertains to PFM and User ID memory only. Configuration and data memory should be erased by the
Bulk Erase command. For self-write operations, each byte write to data memory includes an automatic erase cycle
for the location about to be programmed.
1.4.2
Writing Memory
Memory is written one word at a time. The duration of the write is determined internally.
Note: The size of the word is 16 bits for the Program Flash Memory and is 8 bits for the EEPROM, but the same 24bit payload is used for both memory regions.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 5
PIC18FXXQ83/84
Memory Map
2.
Memory Map
This section provides details about how the program memory and EEPROM is organized for this device.
Figure 2-1. Program and Data EEPROM Memory Map
Rev. 40-000101F
4/20/2017
Address
Device
PIC18Fx6Q83/84
PIC18Fx7Q83/84
00 0000h
to
00 3FFFh
00 4000h
to
00 7FFFh
Program Flash
Memory
(32 KW)(1)
Program Flash
Memory
(64 KW)(1)
00 8000h
to
00 FFFFh
01 0000h
to
01 FFFFh
02 0000h
to
1F FFFFh
20 0000h
to
20 001Fh
20 0020h
to
2B FFFFh
2C 0000h
to
2C 00FFh
2C 0100h
to
2F FFFFh
30 0000h
to
30 0022h
30 0023h
to
37 FFFFh
38 0000h
to
38 03FFh
38 0400h
to
3B FFFFh
3C 0000h
to
3C 000Ah
3C 000Bh
to
3F FFFBh
3F FFFCh
to
3F FFFDh
3F FFFEh
to
3F FFFFh
Note 1:
Not
Present(2)
Not
Present(2)
User IDs (32 Words)(3)
Reserved
Device Information Area (DIA)(3)(5)
Reserved
Configuration Words (3)
Reserved
Data EEPROM (1024 Bytes)
Reserved
Device Configuration Information(3)(4)(5)
Reserved
Revision ID (1 Word)(3)(4)(5)
Device ID (1 Word)(3)(4)(5)
Storage Area Flash is implemented as the last 128 Words of User Flash, if enabled.
2:
The addresses do not roll over. The region is read as ‘0’.
3:
Not code-protected.
4:
Hard-coded in silicon.
5:
This region cannot be written by the user and it’s not affected by a Bulk Erase.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 6
PIC18FXXQ83/84
Memory Map
2.1
User ID Location
A user may store identification information (User ID) in 32 designated locations. The User ID locations are mapped to
20 0000h-20 001Fh. Each location is 16 bits in length. Code protection has no effect on these memory locations.
Each location may be read with code protection enabled or disabled.
2.2
Device/Revision ID
The 16-bit Device ID Word is located at 3F FFFEh and the 16-bit Revision ID is located at 3F FFFCh. These
locations are read-only and cannot be erased or modified. See 2.5 DEVICE ID and 2.6 REVISION ID for more
details.
2.3
Device Configuration Information (DCI)
The Device Configuration Information (DCI) is a dedicated region in the memory that holds information about the
device which is useful for programming and bootloader applications. The data stored in this region is read-only and
cannot be modified/erased. Refer to the table below for complete DCI table addresses and description.
Table 2-1. DEVICE CONFIGURATION INFORMATION
Address
Name
Description
Value
PIC18F26/46/56Q83/84
3C0000h ERSIZ
PIC18F27/47/57Q83/84
128
Words
3C0002h WLSIZ Number of write latches per row
0
Words
3C0004h URSIZ Number of user-erasable pages
256
3C0006h EESIZ
Data EEPROM memory size
1024
Pin Count
28/40(1)/48
3C0008h PCNT
Erase Page Size
Units
512
Pages
Bytes
28/40(1)/48
Pins
Note:
1. Pin Count value of 40 is used for 44-pin parts as well.
2.4
Configuration Bytes
The devices have thirty-five Configuration Bytes, starting at address, 30 0000h. Configuration bits enable or disable
specific features, placing these controls outside the normal software process, and they establish configured values
prior to the execution of any software.
In terms of programming, these important Configuration bits should be considered:
1. LVP: Low-Voltage Programming Enable bit
– 1 = ON: Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration
bit is ignored.
– 0 = OFF: High voltage on MCLR/VPP must be used for programming.
2.
It is important to note that the LVP bit cannot be written (to ‘0’) while operating from the LVP programming
interface. The purpose of this rule is to prevent the user from dropping out of LVP mode while programming
from LVP mode, or accidentally eliminating LVP mode from the Configuration state. For more information, see
3.1.2 Low-Voltage Programming (LVP) Mode.
MCLRE: Master Clear (MCLR) Enable bit
– If LVP = 1: RE3 pin function is MCLR
– If LVP = 0
•
1 = MCLR pin is MCLR
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 7
PIC18FXXQ83/84
Memory Map
•
3.
0 = MCLR pin function is a port-defined function
CP: User NVM Program Memory Code Protection bit
– 1 = OFF: User NVM code protection is disabled
– 0 = ON: User NVM code protection is enabled
For more information on code protection, see 3.3 Code Protection.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 8
PIC18FXXQ83/84
Memory Map
2.5
DEVICE ID
Name:
Offset:
DEVICE ID
3FFFFEh
Device ID Register
Bit
15
14
13
12
11
10
9
8
R
q
R
q
R
q
R
q
3
2
1
0
R
q
R
q
R
q
R
q
DEV[15:8]
Access
Reset
R
q
R
q
R
q
R
q
Bit
7
6
5
4
DEV[7:0]
Access
Reset
R
q
R
q
R
q
R
q
Bits 15:0 – DEV[15:0] Device ID
Device
Device ID
PIC18F26Q83
9906h
PIC18F26Q84
9900h
PIC18F27Q83
9909h
PIC18F27Q84
9903h
PIC18F46Q83
9907h
PIC18F46Q84
9901h
PIC18F47Q83
990Ah
PIC18F47Q84
9904h
PIC18F56Q83
9908h
PIC18F56Q84
9902h
PIC18F57Q83
990Bh
PIC18F57Q84
9905h
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 9
PIC18FXXQ83/84
Memory Map
2.6
REVISION ID
Name:
Offset:
REVISION ID
3FFFFCh
Revision ID Register
Bit
15
14
13
12
11
R
1
R
0
RO
q
5
4
3
RO
q
RO
q
1010[3:0]
Access
Reset
R
1
Bit
7
Access
Reset
R
0
6
MJRREV[1:0]
RO
RO
q
q
10
9
MJRREV[5:2]
RO
RO
q
q
2
MNRREV[5:0]
RO
RO
q
q
8
RO
q
1
0
RO
q
RO
q
Bits 15:12 – 1010[3:0] Read as 'b1010
These bits are fixed with value 'b1010 for all devices in this family.
Bits 11:6 – MJRREV[5:0] Major Revision ID
These bits are used to identify a major revision. (A0, B0, C0, etc.).
Revision A = 'b00 0000
Bits 5:0 – MNRREV[5:0] Minor Revision ID
These bits are used to identify a minor revision.
Revision A0 = 'b00 0000
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 10
PIC18FXXQ83/84
Programming Algorithms
3.
Programming Algorithms
3.1
Program/Verify Mode
In Program/Verify mode, the program memory and the configuration memory can be accessed and programmed in
serial fashion. ICSPDAT and ICSPCLK are used for the data and the clock, respectively. All commands and data
words are transmitted MSb first. Data changes on the rising edge of the ICSPCLK and is latched on the falling edge.
In Program/Verify mode, both the ICSPDAT and ICSPCLK pins are Schmitt Trigger inputs. The sequence that enters
the device into Program/Verify mode places all other logic into the Reset state, all I/Os are automatically configured
as high-impedance inputs and the Program Counter (PC) is cleared.
3.1.1
High-Voltage Program/Verify Mode Entry and Exit
There are two different modes of entering Program/Verify mode via high voltage:
•
•
3.1.1.1
VPP-First Entry mode
VDD-First Entry mode
VPP-First Entry Mode
To enter Program/Verify mode via the VPP-First Entry mode, the following sequence must be followed:
1.
2.
3.
Hold ICSPCLK and ICSPDAT low.
Raise the voltage on MCLR from 0V to VIHH.
Raise the voltage on VDD from 0V to the desired operating voltage.
The VPP-First Entry mode prevents the device from executing code prior to entering Program/Verify mode. For
example, when the Configuration Byte has already been programmed to have MCLR disabled (MCLRE = 0), the
Power-up Timer disabled (PWRTE = 0) and the internal oscillator selected, the device will execute code immediately.
VPP-First Entry mode is strongly recommended as it prevents user code from executing. See the timing diagram in
Figure 3-1.
Figure 3-1. PROGRAMMING ENTRY AND EXIT MODES – VPP-First and Last
PROGRAMMING MODE ENTRY – ENTRY
PROGRAMMING MODE ENTRY – EXIT
VPP-First
VPP-Last
TENTS
TENTH
TEXIT
VDD
VIHH
VPP
VIL
ICSPDAT
ICSPCLK
3.1.1.2
VDD- First Entry Mode
To enter Program/Verify mode via the VDD-First Entry mode, the following sequence must be followed:
1.
Hold ICSPCLK and ICSPDAT low.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 11
PIC18FXXQ83/84
Programming Algorithms
2.
3.
Raise the voltage on VDD from 0V to the desired operating voltage.
Raise the voltage on MCLR from VDD or below to VIHH.
The VDD-First Entry mode is useful for programming the device when VDD is already applied, for it is not necessary to
disconnect VDD to enter Program/Verify mode. See the timing diagram in Figure 3-2.
Figure 3-2. PROGRAMMING ENTRY AND EXIT MODES – VDD-First and Last
PROGRAMMING MODE ENTRY – ENTRY
PROGRAMMING MODE ENTRY – EXIT
VDD-First
VDD-Last
TENTS
TENTH
TEXIT
VDD
VIHH
VPP
VIL
ICSPDAT
ICSPCLK
3.1.1.3
Program/Verify Mode Exit
To exit Program/Verify mode, lower MCLR from VIHH to VIL. VPP-First Entry mode should use VPP-Last Exit mode (see
Figure 3-1). VDD-First Entry mode should use VDD-Last Exit mode (see Figure 3-2).
3.1.2
Low-Voltage Programming (LVP) Mode
The Low-Voltage Programming mode allows the devices to be programmed using VDD only, without high voltage.
When the LVP bit in the Configuration Byte register is set to ‘1’, the Low-Voltage ICSP Programming entry is enabled.
To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. This can only be done while in the
High-Voltage Entry mode.
Entry into the Low-Voltage ICSP Program/Verify mode requires the following steps:
1. MCLR is brought to VIL.
2. A 32-bit key sequence is presented on ICSPDAT, clocked by ICSPCLK. The LSb of the pattern is a “don’t
care X”. The Program/Verify mode entry pattern detect hardware verifies only the first 31 bits of the sequence
DS40001874D-page 8
2017-2018 Microchip Technology Inc.
and the last clock is required before the pattern detect goes active.
The key sequence is a specific 32-bit pattern, ‘32’h4d434850’ (more easily remembered as MCHP in ASCII). The
device will enter Program/Verify mode only if the sequence is valid. The Most Significant bit of the Most Significant
Byte must be shifted in first. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/
Verify mode is to be maintained. For Low-Voltage Programming timing, see Figure 3-3 and Figure 3-4.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 12
PIC18FXXQ83/84
Programming Algorithms
Figure 3-3. LVP Entry (Powering Up)
VDD
MCLR
TENTS
TENTH
TENTH
32 Clocks
TCKH
TCKL
ICSPCLK
MSb of Pattern
31
ICSPDAT
TDH
TDS
LSb of Pattern
30
29
...
1
Figure 3-4. LVP Entry (Powered)
VDD
MCLR
TENTH
TENTH
32 Clocks
TCKH
TCKL
ICSPCLK
TDS
MSb of Pattern
ICSPDAT
31
30
TDH
LSb of Pattern
29
...
1
Exiting Program/Verify mode is done by raising MCLR from below VIL to VIH level (or higher, up to VDD).
Important:
To enter LVP mode, the MSb of the Most Significant nibble must be shifted in first. This differs from
entering the key sequence on some other device families.
3.1.3
Program/Verify Commands
Once a device has entered ICSP Program/Verify mode (using either high-voltage or LVP entry), the programming
host device may issue six commands to the microcontroller, each eight bits in length. The commands are
summarized in Table 3-1. The commands are used to erase or program the device based on the location of the
Program Counter (PC).
Some of the 8-bit commands also have an associated data payload (such as Load PC Address and Read Data from
NVM).
If the host device issues an 8-bit command byte that has an associated data payload, the host device is responsible
for sending an additional 24 clock pulses (for example, three 8-bit bytes) in order to send or receive the payload data
associated with the command.
The payload field size is used so as to be compatible with many 8-bit SPI-based systems. Within each 24-bit payload
field, the first bit transmitted is always a Start bit, followed by a variable number of Pad bits, followed by the useful
data payload bits and ending with one Stop bit. The useful data payload bits are always transmitted, Most Significant
bit (MSb) first.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 13
PIC18FXXQ83/84
Programming Algorithms
When the programming device issues a command that involves a host to microcontroller payload (for example, Load
PC Address), the Start, Stop and Pad bits should all be driven by the programmer to ‘0’. When the programming host
device issues a command that involves microcontroller to host payload data (for example, Read Data from NVM), the
Start, Stop and Pad bits should be treated as “don't care” bits and the values should be ignored by the host.
When the programming host device issues an 8-bit command byte to the microcontroller, the host should wait a
specified minimum amount of delay (which is command-specific) prior to sending any additional clock pulses
(associated with either a 24-bit data payload field or the next command byte).
Table 3-1. ICSP™ COMMAND SET SUMMARY(1)
Command Name
Command Value
Payload
Expected
Delay after
Command
Data/Note
Binary (MSb …
LSb)
Hex
Load PC Address
1000 0000
80
Yes
TDLY
Payload Value =
PC
Bulk Erase
0001 1000
18
Yes
TERAB
The payload
carries the
information of the
regions that need
to be bulk
erased.
Page Erase
Program Memory
1111 0000
F0
No
TERAS
The page
addressed by the
MSbs of the PC
is erased; LSbs
are ignored
Read Data from
NVM
1111 11J0
FC/FE
Yes
TDLY
Data output ‘0’ if
code-protect is
enabled: J = 0:
PC is unchanged
J = 1: PC = PC +
n(2) after reading
Increment
Address
1111 1000
F8
No
TDLY
PC = PC + n(2)
Program Data
11J0 0000
C0/E0
Yes
TPROG
Payload value =
Data Word J = 0:
PC is unchanged
J = 1: PC = PC +
n after writing
Important:
1. All clock pulses for both the 8-bit commands and the 24-bit payload fields are generated by the host
programming device. The microcontroller does not drive the ICSPCLK line. The ICSPDAT signal is
a bidirectional data line. For all commands and payload fields, except the Read Data from NVM
payload, the host programming device continuously drives the ICSPDAT line. Both the host
programmer device and the microcontroller should latch received ICSPDAT values on the falling
edge of the ICSPCLK line. When the microcontroller receives ICSPDAT line values from the host
programmer, the ICSPDAT values must be valid a minimum of TDS before the falling edges of
ICSPCLK and should remain valid for a minimum of TDH after the falling edge of ICSPDAT. See
Figure 3-5.
2. PC is incremented by n = 1 for data memory, Configuration Bytes and n = 2 for all other regions.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 14
PIC18FXXQ83/84
Programming Algorithms
Figure 3-5. Clock and Data Timing
TCKH
TCKL
ICSPCLK
TDS TDH
ICSPDAT
as
Input
TCO
ICSPDAT
as
Output
TLZD
ICSPDAT
from Input
to Output
THZD
ICSPDAT
from Output
to Input
3.1.3.1
Program Data
The Program Data command is used to program one NVM word (for example, one 16-bit instruction word for program
memory/User ID memory or one 8-bit data for a Data EEPROM Memory address). The payload data is written into
program or EEPROM memory immediately after the Programming Data command is issued (see 3.2 Programming
Algorithms). Depending on the value of bit 5 of the command, the PC may or may not be incremented (see Table
3-1).
Figure 3-6. PROGRAM DATA (Program Memory and User IDs)
7
6
5
4
3
2
1
0
23
22
17
16
1
0
TPINT
TDLY
ICSPCLK
1
ICSPDAT
1
J
0
0
0
0
0
0
0
0
MSb
LSb
Start Bit
0
Stop Bit
8-Bit Command
24-Bit Payload Field
Figure 3-7. PROGRAM DATA (DATA EEPROM and Configuration Bytes)
7
6
5
4
3
2
1
0
22
9
8
1
0
TPDFM
TDLY
ICSPCLK
ICSPDAT
23
1
1
J
0
0
0
0
0
0
0
0
MSb
LSb
Start Bit
8-Bit Command
© 2019 Microchip Technology Inc.
0
Stop Bit
24-Bit Payload Field
Programming Specification
DS40002137B-page 15
PIC18FXXQ83/84
Programming Algorithms
3.1.3.2
Read Data from NVM
The Read Data from the NVM command will transmit data bits out of the current PC address. The ICSPDAT pin will
go into Output mode on the first falling edge of the ICSP data payload clock and it will revert to Input mode (highimpedance) after the 24th falling edge of the ICSP data payload clock. The Start and Stop bits are only one-half of a
bit time wide; therefore, they should be ignored by the host programmer device, since the latched value may be
indeterminate. Additionally, the host programmer device should only consider the MSb to LSb payload bits as valid
and should ignore the values of the Pad bits. If the memory region is code-protected (CP or DP), the data will be read
as zeros (see Figure 3-8 and Figure 3-9). Depending on the value of bit 1 of the command, the PC may or may not
be incremented (see Table 3-1). The Read Data from the NVM command can be used to read data for Program Flash
Memory (see Figure 3-8) or the Data EEPROM Memory (see Figure 3-9).
Figure 3-8. READ DATA FROM NVM (PFM and User IDs)
7
6
5
4
3
2
1
0
23
22
17
16
1
0
TDLY
TDLY
ICSPCLK
ICSPDAT (from
1
programmer)
1
1
1
1
J
1
High-Z
0
High-Z
0
ICSPDAT
(from device)
0
0
MSb Data
LSb
0
Stop
Start
Input
Output
Input
Figure 3-9. READ DATA FROM NVM (DATA EEPROM and Configuration Bytes)
7
6
5
4
3
2
1
0
23
9
8
1
0
TDLY
TDLY
ICSPCLK
ICSPDAT (from
Programmer) 1
22
1
1
1
1
1
J
High-Z
0
High-Z
0
ICSPDAT
(from device)
0
MSb Data
Start
Input
3.1.3.3
0
LSb
0
Stop
Output
Input
Increment Address
The address is incremented when this command is received. Depending on the current value of the Program
Counter, the increment varies. If the PC points to PFM, then the PC is incremented by 2; if the PC points to the data
EEPROM or Configuration Space, then it is incremented by 1. It is not possible to decrement the address. To reset
the Program Counter, the user must use the Load PC Address command.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 16
PIC18FXXQ83/84
Programming Algorithms
Figure 3-10. INCREMENT ADDRESS
Next Command
7
6
5
4
3
2
1
0
7
6
TDLY
ICSPCLK
ICSPDAT
1
1
1
1
1
0
0
0
x
Address
3.1.3.4
5
x
x
Address + 1
Load PC Address
The PC value is set using the supplied data. The address indicates the memory location (PFM or Data EEPROM
Memory or Configuration memory) to be accessed (see Figure 3-11).
Figure 3-11. LOAD PC ADDRESS
7
6
5
4
3
2
1
0
1
0
1
0
0
0
0
0
0
0
TDLY
0
Start
3.1.3.5
22
TDLY
ICSPCLK
ICSPDAT
23
MSb
Address
LSb
0
Stop
Bulk Erase
The Bulk Erase command is used to completely erase different memory regions. The area selection is a bit field in
the payload.
By setting the following bits of the payload, the corresponding memory regions can be bulk erased. Setting multiple
bits is valid.
1.
2.
3.
4.
Bit 1: Data EEPROM
Bit 2: Flash memory
Bit 3: User ID memory
Bit 4: Configuration memory
Important: If the device is code-protected and a Bulk Erase command for the configuration memory is
issued, all other regions are also bulk erased.
After receiving the Bulk Erase command, the erase will complete after the time interval TERAB. See Figure 3-12 for
Bulk Erase command structure.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 17
PIC18FXXQ83/84
Programming Algorithms
Figure 3-12. BULK ERASE MEMORY
TERAB
3.1.3.6
Page Erase Program Memory
The Page Erase Program Memory command will erase an individual page based on the current address of the
Program Counter. If the program memory is code-protected, the Page Erase Memory command will be ignored. The
Bulk Erase command must be used to erase code-protected memory.
The Flash memory page defined by the current PC will be erased. The user must wait TERAS for erasing to be
complete (see Figure 3-13). Page Erase may be used for program memory and User ID regions only. Configuration
and data regions must be erased with the Bulk Erase method.
Figure 3-13. PAGE ERASE MEMORY
Next Command
7
6
5
4
3
2
1
0
3.2
6
5
TERAS
ICSPCLK
ICSPDAT
7
1
1
1
1
0
0
0
0
x
x
x
Programming Algorithms
The Program Flash Memory and User ID are programmed one word at a time. The EEPROM memory and
Configuration regions are programmed one byte at a time.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 18
PIC18FXXQ83/84
Programming Algorithms
Figure 3-14. DEVICE PROGRAM/VERIFY FLOWCHART
START
Enter Programming
Mode
Bulk Erase Device
Write Program Memory(1)
Verify Program Memory
Write Data
EEPROM
Verify Data
EEPROM
Write User IDs
Verify User IDs
Write Configuration
Bytes
Exit Programming
Mode
Done
Note:
1. See Figure 3-15.
2. See Figure 3-17.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 19
PIC18FXXQ83/84
Programming Algorithms
Figure 3-15. PROGRAM MEMORY FLOWCHART
Start
Bulk Erase Program
Memory(1)
Load PC Address
(00 0000h)
One-Word Program Cycle(2)
(Program Data)
Read from NVM
Command
Data
Correct?
No
Report Programming
Failure
No
Yes
Increment PC Address
All Locations
Done?
Yes
Done
Note:
1. This step is optional if the device has already been erased or has not been previously programmed.
2. If the device is code-protected or must be completely erased, then Bulk Erase the device per Figure 3-18.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 20
PIC18FXXQ83/84
Programming Algorithms
Figure 3-16. ONE-WORD PROGRAM CYCLE
Program Cycle
(For programming Data, EEPROM, User ID and Configuration Bytes)
Load PC with Address
Program Data Command
Wait TPINT
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 21
PIC18FXXQ83/84
Programming Algorithms
Figure 3-17. USER ID AND CONFIGURATION MEMORY PROGRAM FLOWCHART
Start
Load PC Address
(select Bulk Erase
regions)
Bulk Erase
Program Memory(1)
Load PC Address
(First Address of User ID
Space)
One-Word Program
Cycle(2)
(User ID)
Read from NVM
Command
Data
Correct?
No
Report Programming
Failure
No
Yes
Increment PC
Address
Address =
Last address of
User ID space?
Yes
Load PC Address
(First Address of
Configuration Space)
One-Word Program
Cycle(2)
(Config. Byte)
Read from NVM
Command
Data
Correct?
Report Programming
Failure
No
No
Yes
Increment PC
Address
Address =
Last address of
Configuration
Space?
Yes
Done
Note:
1. This step is optional if the device has already been erased or has not been previously programmed.
2. See Figure 3-16.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 22
PIC18FXXQ83/84
Programming Algorithms
Figure 3-18. BULK ERASE FLOWCHART
Start
Bulk Erase Command with
payload containing area
selections for bulk erase
Wait TERAB for Operation
to complete
Done
3.3
Code Protection
Code protection is controlled using the CP bit. When code protection is enabled, all program memory and Data
EEPROM locations read as ‘0’. Further programming is disabled for the program memory and Data EEPROM until a
Bulk Erase operation is performed on the configuration memory region. Program memory and Data EEPROM can
still be programmed and read during program execution.
The User ID locations and Configuration Bytes can be programmed and read out regardless of the code protection
settings.
The only way to disable code protection is to use the Bulk Erase Program Memory command with bit 4 of the payload
set to ‘1’. This will clear the disable code protection and also erase all the memory locations.
3.4
Hex File Usage
3.4.1
Embedding Configuration Information in the HEX File
To allow portability of code, a programmer is required to read the Configuration Byte locations from the Hex file. If
Configuration Byte information is not present in the Hex file, then a simple warning message should be issued.
Similarly, when saving a Hex file, all Configuration Byte information should be included. An option to not include the
Configuration Byte information may be provided. When embedding Configuration Byte information in the Hex file, it
should start at address 30 0000h.
Important:
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
3.4.2
Embedding Data EEPROM Information in the HEX File
To allow portability of code, a programmer is required to read the data EEPROM information from the Hex file. If data
EEPROM information is not present, a simple warning message should be issued. Similarly, when saving a Hex file,
all data EEPROM information must be included. An option to not include the data EEPROM information may be
provided. When embedding data EEPROM information in the Hex file, it should start at address 38 0000h.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 23
PIC18FXXQ83/84
Programming Algorithms
Important:
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
3.5
CRC Checksum Computation
®
Unlike older PIC devices, the Microchip toolchain runs a 32-bit CRC calculation on the entire hex file to calculate its
checksum. The checksum uses the standard CRC-32 algorithm with the polynomial 0x4C11DB7
�32 + �26 + �23 + �22 + �16 + �12 + �11 + �10 + �8 + �7 + �5 + �4 + �2 + � + 1 .
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 24
PIC18FXXQ83/84
Electrical Specifications
4.
Electrical Specifications
Refer to the device-specific data sheet for absolute maximum ratings.
Table 4-1. AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
Standard Operating Conditions Production tested at
+25°C
AC/DC CHARACTERISTICS
Sym.
Characteristics
Min.
Typ.
Max.
Units
Conditions/
Comments
Programming Supply Voltages and Currents
VDD
Supply Voltage (VDDMIN, VDDMAX)
1.80
—
5.50
V
VPEW Read/Write and Page Erase Operations
VDDMIN
—
VDDMAX
V
VBORMAX
—
VDDMAX
V
VBE
Bulk Erase Operations
IDDI
Current on VDD, Idle
—
—
1.0
mA
IDDP
Current on VDD, Programming
—
—
10
mA
IPP
VIHH
TVHHR
(Note 1)
(Note 2)
VPP
Current on MCLR/VPP
—
—
600
µA
High Voltage on MCLR/VPP for Program/Verify
Mode Entry
7.9
—
9.0
V
MCLR Rise Time (VIL to VIHH) for Program/
Verify Mode Entry
—
—
1.0
µs
I/O Pins
VIH
(ICSPCLK, ICSPDAT, MCLR/VPP) Input High
Level
0.8 VDD
—
VDD
V
VIL
(ICSPCLK, ICSPDAT, MCLR/VPP) Input Low
Level
VSS
—
0.2 VDD
V
VOH
ICSPDAT Output High Level
VDD-0.7
—
—
V
IOH = 3 mA, VDD = 3.0V
VOL
ICSPDAT Output Low Level
—
—
VSS + 0.6
V
IOL = 6 mA, VDD = 3.0V
Programming Mode Entry and Exit
Programing Mode Entry Setup Time:
TENTS ICSPCLK, ICSPDAT Setup Time before VDD or
MCLR↑
TENTH
Programing Mode Entry Hold Time: ICSPCLK,
ICSPDAT Hold Time before VDD or MCLR↑
100
—
—
ns
1
—
—
ms
Serial Program/Verify
TCKL
Clock Low Pulse Width
100
—
—
ns
TCKH Clock High Pulse Width
100
—
—
ns
TDS
Data in Setup Time before Clock↓
100
—
—
ns
TDH
Data in Hold Time after Clock↓
100
—
—
ns
TCO
Clock↑ to Data Out Valid (during a Read Data
command)
0
—
80
ns
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 25
PIC18FXXQ83/84
Electrical Specifications
...........continued
Standard Operating Conditions Production tested at
+25°C
AC/DC CHARACTERISTICS
Characteristics
Min.
Typ.
Max.
Units
TLZD
Clock↓ to Data Low-Impedance (during a Read
Data from NVM command)
0
—
80
ns
THZD
Clock↓ to Data High-Impedance (during a
Read Data from NVM command)
0
—
80
ns
Data Input not Driven to Next Clock Input
(delay required between command/data or
command/command)
1.0
—
—
µs
TDLY
TERAB Bulk Erase Cycle Time
—
—
11
ms
TERAS Page Erase Cycle Time
—
—
11
ms
Sym.
Conditions/
Comments
Program, Config and ID
TPDFM
Internally Timed DFM (EEPROM)
Programming Operation Time
—
—
11
ms
EEPROM memory and
Configuration Words
TPINT
Internally Timed Programming Operation Time
—
—
75
µs
Program Memory and
Configuration Words
TEXIT
Time Delay when Exiting Program/Verify Mode
1
—
—
µs
Note:
1. Bulk erased devices default to Brown-out Reset enabled with BORV = 11 (low trip point). VDDMIN is the VBOR
threshold (with BORV = 1) when performing Low-Voltage Programming on a bulk erased device to ensure that
the device is not held in Brown-out Reset.
2. The hardware requires VDD to be above the BOR threshold, at the ~2.85V nominal setting, in order to perform
Bulk Erase operations. This threshold does not depend on the BORV Configuration bit settings. Refer to the
microcontroller device data sheet specifications for min./typ./max. limits of the VBOR level.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 26
PIC18FXXQ83/84
APPENDIX A: Revision History
5.
APPENDIX A: Revision History
Doc Rev.
Date
Comments
B
10/2019
Updated Table 4-1 - TPINT from 50 µs
to 75 µs.
A
07/2019
Initial Document Release
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 27
PIC18FXXQ83/84
APPENDIX B
6.
APPENDIX B
This section provides information about the Device IDs and Pinout Descriptions
Table 6-1. Programming Pin Locations By Package Type
Package
Package
Code
VDD
VSS
PIN
PIN
PIN
PORT
PIN
PORT
PIN
PORT
28-Pin
SPDIP
(SP)
20
19, 8
1
RE3
27
RB6
28
RB7
28-Pin
SOIC
(SO)
20
19, 8
1
RE3
27
RB6
28
RB7
28-Pin
SSOP
(SS)
20
19, 8
1
RE3
27
RB6
28
RB7
28-Pin
VQFN
(5N)
17
16, 5
26
RE3
24
RB6
25
RB7
PIC18F
46Q83
PIC18F
46Q84
PIC18F
47Q83
PIC18F
47Q84
40-Pin
PDIP
(P)
32, 11
31, 12
1
RE3
39
RB6
40
RB7
40-Pin
VQFN
(NHX)
26, 7
27, 6
16
RE3
14
RB6
15
RB7
44-Pin
TQFP
(PT)
28, 7
29, 6
18
RE3
16
RB6
17
RB7
PIC18F
56Q83
PIC18F
56Q84
PIC18F
57Q83
PIC18F
57Q84
48-Pin
TQFP
(PT)
30, 7
31 , 6
20
RE3
18
RB6
19
RB7
48-Pin
VQFN
(6MX)
30, 7
31, 6
20
RE3
18
RB6
19
RB7
Device
PIC18F
26Q83
PIC18F
26Q84
PIC18F
27Q83
PIC18F
27Q84
MCLR
ICSPCLK
ICSPDAT
Note:
The most current package drawings are located in the Microchip Packaging Specification, DS00000049 (http://
www.microchip.com/packaging). The drawing numbers listed above do not include the current revision designator,
which is added at the end of the number.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 28
PIC18FXXQ83/84
APPENDIX B
6.1
CONFIG1
Name:
Offset:
CONFIG1
30 0000h
Configuration Byte 1
Bit
Access
Reset
7
6
R/W
1
5
RSTOSC[2:0]
R/W
1
4
3
R/W
1
2
R/W
1
1
FEXTOSC[2:0]
R/W
1
0
R/W
1
Bits 6:4 – RSTOSC[2:0] Power-up Default Value for COSC
This value is the Reset default value for COSC and selects the oscillator first used by user software. Refer to COSC
operation.
Value
Description
111
EXTOSC operating per FEXTOSC bits
110
HFINTOSC with HFFRQ = 4 MHz and CDIV = 4:1. Resets COSC/NOSC to b'110'.
101
LFINTOSC
100
SOSC
011
Reserved
010
EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits
001
Reserved
000
HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1. Resets COSC/NOSC to b'110'.
Bits 2:0 – FEXTOSC[2:0] External Oscillator Mode Selection
Value
Description
111
ECH (external clock) above 8 MHz
110
ECM (external clock) for 500 kHz to 8 MHz
101
ECL (external clock) below 500 kHz
100
Oscillator not enabled
011
Reserved (do not use)
010
HS (crystal oscillator) above 4 MHz
001
XT (crystal oscillator) above 500 kHz, below 4 MHz
000
LP (crystal oscillator) optimized for 32.768 kHz
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 29
PIC18FXXQ83/84
APPENDIX B
6.2
CONFIG2
Name:
Offset:
CONFIG2
30 0001h
Configuration Byte 2
Bit
Access
Reset
7
FCMENS
R/W
1
6
FCMENP
R/W
1
5
FCMEN
R/W
1
4
FJTAGEN
R/W
1
3
CSWEN
R/W
1
2
1
PR1WAY
R/W
1
0
CLKOUTEN
R/W
1
Bit 7 – FCMENS Fail-Safe Clock Monitor Enable for Secondary Crystal Oscillator Enable
Value
Description
1
Fail-Safe Clock Monitor enabled for Secondary Crystal, Fail-Safe timer will set FSCMS bit and trigger
OSFIF interrupt on secondary crystal failure
0
Fail-Safe Clock Monitor disabled for Secondary Crystal
Bit 6 – FCMENP Fail-Safe Clock Monitor Enable for Primary Crystal Oscillator
Value
Description
1
Fail-Safe Clock Monitor enabled for Primary Crystal Oscillator, Fail-Safe timer will set FSCMP bit and
trigger OSFIF interrupt on primary crystal failure
0
Fail-Safe Clock Monitor disabled for Primary Crystal Oscillator
Bit 5 – FCMEN Fail-Safe Clock Monitor Enable for FOSC
Value
Description
1
Fail-Safe Clock Monitor enabled, Fail-Safe timer will initiate a clock switch and trigger OSFIF interrupt
on FOSC failure
0
Fail-Safe Clock Monitor disabled
Bit 4 – FJTAGEN JTAG Boundary Scan Enable
Value
Description
1
Enable JTAG Boundary Scan mode and pins
0
Disable JTAG Boundary Scan mode, JTAG pins revert to user functions
Bit 3 – CSWEN Clock Switch Enable
Value
Description
1
Writing to NOSC and NDIV is allowed
0
The NOSC and NDIV bits cannot be changed by user software
Bit 1 – PR1WAY PRLOCKED One-Way Set Enable
Value
Description
1
PRLOCKED bit can be cleared and set only once; Priority registers remain locked after one clear/set
cycle
0
PRLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)
Bit 0 – CLKOUTEN Clock Out Enable
If FEXTOSC = HS, XT, LP, then this bit is ignored.
Otherwise:
Value
Description
1
CLKOUT function is disabled; I/O function on OSC2
0
CLKOUT function is enabled; FOSC/4 clock appears at OSC2
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 30
PIC18FXXQ83/84
APPENDIX B
6.3
CONFIG3
Name:
Offset:
CONFIG3
30 0002h
Configuration Byte 3
Bit
Access
Reset
7
6
BOREN[1:0]
R/W
R/W
0
1
5
LPBOREN
R/W
1
4
IVT1WAY
R/W
1
3
MVECEN
R/W
1
2
1
PWRTS[1:0]
R/W
R/W
1
1
0
MCLRE
R/W
1
Bits 7:6 – BOREN[1:0] Brown-out Reset Enable
When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit
Value
Description
11
Brown-out Reset enabled, SBOREN bit is ignored
10
Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored
01
Brown-out Reset enabled according to SBOREN
00
Brown-out Reset disabled
Bit 5 – LPBOREN Low-Power BOR Enable
Value
Description
1
Low-Power Brown-out Reset is disabled
0
Low-Power Brown-out Reset is enabled
Bit 4 – IVT1WAY IVTLOCK One-Way Set Enable
Value
Description
1
IVTLOCK bit can be cleared and set only once; IVT registers remain locked after one clear/set cycle
0
IVTLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)
Bit 3 – MVECEN Multivector Enable
Value
Description
1
Multivector is enabled; vector table used for interrupts
0
Legacy interrupt behavior
Bits 2:1 – PWRTS[1:0] Power-up Timer Selection
Value
Description
11
PWRT is disabled
10
PWRT is set at 64 ms
01
PWRT is set at 16 ms
00
PWRT is set at 1 ms
Bit 0 – MCLRE Master Clear (MCLR) Enable
Value
Condition
Description
x
If LVP = 1
RE3 pin function is MCLR
1
If LVP = 0
MCLR pin is MCLR
0
If LVP = 0
MCLR pin function is port defined function
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 31
PIC18FXXQ83/84
APPENDIX B
6.4
CONFIG4
Name:
Offset:
CONFIG4
30 0003h
Configuration Byte 4
Bit
Access
Reset
7
XINST
R/W
1
6
5
LVP
R/W
1
4
STVREN
R/W
1
3
PPS1WAY
R/W
1
2
ZCD
R/W
1
1
0
BORV[1:0]
R/W
1
R/W
1
Bit 7 – XINST Extended Instruction Set Enable
Value
Description
1
Extended Instruction Set and Indexed Addressing mode disabled (Legacy mode)
0
Extended Instruction Set and Indexed Addressing mode enabled
Bit 5 – LVP Low-Voltage Programming Enable
The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of this rule
is to prevent the user from dropping out of LVP mode while programming from LVP mode, or accidentally eliminating
LVP mode from the Configuration state.
Value
Description
1
Low-voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is
ignored.
0
HV on MCLR/VPP must be used for programming
Bit 4 – STVREN Stack Overflow/Underflow Reset Enable
Value
Description
1
Stack Overflow or Underflow will cause a Reset
0
Stack Overflow or Underflow will not cause a Reset
Bit 3 – PPS1WAY PPSLOCKED One-Way Set Enable
Value
Description
1
The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once PPSLOCK
is set, all future changes to PPS registers are prevented
0
The PPSLOCKED bit can be set and cleared as needed (unlocking sequence is required)
Bit 2 – ZCD ZCD Disable
Value
Description
1
ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
0
ZCD always enabled, PMDx[ZCDMD] bit is ignored
Bits 1:0 – BORV[1:0] Brown-out Reset Voltage Selection(1)
Value
Description
11
Brown-out Reset Voltage (VBOR) set to 1.90 V
10
Brown-out Reset Voltage (VBOR) set to 2.45 V
01
Brown-out Reset Voltage (VBOR) set to 2.7 V
00
Brown-out Reset Voltage (VBOR) set to 2.85 V
Note:
1. The higher voltage setting is recommended for operation at or above 16 MHz.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 32
PIC18FXXQ83/84
APPENDIX B
6.5
CONFIG5
Name:
Offset:
CONFIG5
30 0004h
Configuration Byte 5
Bit
7
6
5
4
3
R/W
1
R/W
1
R/W
1
WDTE[1:0]
Access
Reset
R/W
1
2
WDTCPS[4:0]
R/W
1
1
0
R/W
1
R/W
1
Bits 6:5 – WDTE[1:0] WDT Operating Mode
Value
Description
11
WDT enabled regardless of Sleep; SEN bit in WDTCON0 is ignored
10
WDT enabled while Sleep = 0, suspended when Sleep = 1; SEN bit in WDTCON0 is ignored
01
WDT enabled/disabled by SEN bit in WDTCON0
00
WDT disabled, SEN bit in WDTCON0 is ignored
Bits 4:0 – WDTCPS[4:0] WDT Period Select
WDTCON0[WDTPS] at POR
Typical Time Out
Value
Divider Ratio
(FIN = 31 kHz)
WDTCPS
11111
11110 to 10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
01011
11110 to 10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
© 2019 Microchip Technology Inc.
1:65536
1:32
1:8388608
1:4194304
1:2097152
1:1048576
1:524288
1:262144
1:131072
1:65536
1:32768
1:16384
1:8192
1:4096
1:2048
1:1024
1:512
1:256
1:128
1:64
1:32
216
25
223
222
221
220
219
218
217
216
215
214
213
212
211
210
29
28
27
26
25
2s
1 ms
256s
128s
64s
32s
16s
8s
4s
2s
1s
512 ms
256 ms
128 ms
64 ms
32 ms
16 ms
8 ms
4 ms
2 ms
1 ms
Programming Specification
Software Control of WDTPS?
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
DS40002137B-page 33
PIC18FXXQ83/84
APPENDIX B
6.6
CONFIG6
Name:
Offset:
CONFIG6
30 0005h
Configuration Byte 6
Bit
7
6
5
Access
Reset
R/W
1
4
WDTCCS[2:0]
R/W
1
3
2
R/W
1
R/W
1
1
WDTCWS[2:0]
R/W
1
0
R/W
1
Bits 5:3 – WDTCCS[2:0] WDT Input Clock Selector
Value
Condition
Description
x
WDTE = 00
These bits have no effect
111
WDTE ≠ 00
Software Control
110 to
WDTE ≠ 00
Reserved
011
010
WDTE ≠ 00
WDT reference clock is the SOSC
001
WDTE ≠ 00
WDT reference clock is the 31.25 kHz MFINTOSC
000
WDTE ≠ 00
WDT reference clock is the 31.0 kHz LFINTOSC
Bits 2:0 – WDTCWS[2:0] WDT Window Select
WDTCON1[WINDOW] at POR
WDTCWS
Value
Window delay
Percent of time
Window opening
Percent of time
111
111
n/a
100
110
110
n/a
100
101
101
25
75
100
100
37.5
62.5
011
011
50
50
010
010
62.5
37.5
001
001
75
25
000
000
87.5
12.5
© 2019 Microchip Technology Inc.
Software control of
WINDOW
Keyed access
required?
Yes
No
No
Yes
Programming Specification
DS40002137B-page 34
PIC18FXXQ83/84
APPENDIX B
6.7
CONFIG7
Name:
Offset:
CONFIG7
30 0006h
Configuration Byte 7
Bit
7
6
5
DEBUG
R/W
1
Access
Reset
4
SAFEN
R/W
1
3
BBEN
R/W
1
2
1
BBSIZE[2:0]
R/W
1
R/W
1
0
R/W
1
Bit 5 – DEBUG Debugger Enable
Value
Description
1
Background debugger disabled
0
Background debugger enabled
Bit 4 – SAFEN Storage Area Flash (SAF) Enable(1)
Value
Description
1
SAF is disabled
0
SAF is enabled
Bit 3 – BBEN Boot Block Enable(1)
Value
Description
1
Boot Block is disabled
0
Boot Block is enabled
Bits 2:0 – BBSIZE[2:0] Boot Block Size Selection(2)
Table 6-2. Boot Block Size
Boot Block Size (words)
BBEN
BBSIZE
End Address of
Boot Block
1
xxx
–
–
0
111
00 03FFh
512
0
110
00 07FFh
1024
0
101
00 0FFFh
2048
0
100
00 1FFFh
4096
0
011
00 3FFFh
8192
0
010
00 7FFFh
0
001
00 FFFFh
0
000
00 FFFFh
PIC18Fx5Q43
PIC18Fx6Q43
–
PIC18Fx7Q43
16384
–
32768
–
Note:
1. Once protection is enabled through ICSP™ or a self-write, it can only be reset through a Bulk Erase.
2. BBSIZE[2:0] bits can only be changed when BBEN = 1. Once BBEN = 0, BBSIZE[2:0] can only be changed
through a Bulk Erase.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 35
PIC18FXXQ83/84
APPENDIX B
6.8
CONFIG8
Name:
Offset:
CONFIG8
30 0007h
Configuration Byte 8
Bit
Access
Reset
7
WRTAPP
R/W
1
6
5
4
3
WRTSAF
R/W
1
2
WRTD
R/W
1
1
WRTC
R/W
1
0
WRTB
R/W
1
Bit 7 – WRTAPP Application Block Write Protection(1)
Value
Description
1
Application Block is NOT write-protected
0
Application Block is write-protected
Bit 3 – WRTSAF Storage Area Flash (SAF) Write Protection(1,2)
Value
Description
1
SAF is NOT write-protected
0
SAF is write-protected
Bit 2 – WRTD Data EEPROM Write Protection(1)
Value
Description
1
Data EEPROM is NOT write-protected
0
Data EEPROM is write-protected
Bit 1 – WRTC Configuration Register Write Protection(1)
Value
Description
1
Configuration registers are NOT write-protected
0
Configuration registers are write-protected
Bit 0 – WRTB Boot Block Write Protection(1,3)
Value
Description
1
Boot Block is NOT write-protected
0
Boot Block is write-protected
Note:
1. Once protection is enabled through ICSP™ or a self-write, it can only be reset through a Bulk Erase.
2. Applicable only if SAFEN = 0.
3.
Applicable only if BBEN = 0.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 36
PIC18FXXQ83/84
APPENDIX B
6.9
CONFIG9
Name:
Offset:
CONFIG9
30 0008h
Configuration Byte 9
Bit
7
6
Access
Reset
5
ODCON
R/W
1
4
BPEN
R/W
1
3
2
1
0
BOOTPINSEL[1:0]
R/W
R/W
1
1
Bit 5 – ODCON CRC-on-Boot Pin Open-Drain Configuration
Value
Description
1
CRC-on-boot output drives both high-going and low-going signals (source and sink current)
0
CRC-on-boot output drives only low-going signals (sink current only)
Bit 4 – BPEN CRC-on-Boot Output Pin Enable
Value
Description
1
CRC-on-boot output pin disabled
0
CRC-on-boot output pin determined by BOOTPINSEL[1:0]
Bits 1:0 – BOOTPINSEL[1:0] CRC-on-Boot Pin Select
Value
Description
11
CRC-on-boot output pin is RC5
10
CRC-on-boot output pin is RC4
01
CRC-on-boot output pin is RA2
00
CRC-on-boot output pin is RA4
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 37
PIC18FXXQ83/84
APPENDIX B
6.10
CONFIG10
Name:
Offset:
CONFIG10
30 0009h
Configuration Byte 10
Bit
7
6
5
4
3
2
Access
Reset
1
0
CP
R/W
1
Bit 0 – CP User Program Flash Memory and Data EEPROM Code Protection(1)
Value
Description
1
User Program Flash Memory and Data EEPROM code protection are disabled
0
User Program Flash Memory and Data EEPROM code protection are enabled
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 38
PIC18FXXQ83/84
APPENDIX B
6.11
CONFIG11
Name:
Offset:
CONFIG11
30 000Ah
Configuration Byte 11
Bit
Access
Reset
7
BOOTPOR
R/W
1
6
COE
R/W
1
5
CFGSCEN
R/W
1
4
DATSCEN
R/W
1
3
SAFSCEN
R/W
1
2
APPSCEN
R/W
1
1
BOOTCOE
R/W
1
0
BOOTSCEN
R/W
1
Bit 7 – BOOTPOR CRC-on-Boot Enable
Value
Description
1
CRC-on-boot disabled, device will immediately execute user code upon device Reset
0
CRC-on-boot enabled, device will perform CRC check of configured memory before executing user
code upon device Reset
Bit 6 – COE Continue on Error for Non-Boot Block Areas Enable
Value
Description
1
Device will halt if a mismatch is found between expected and calculated CRC values for the non-boot
block areas of memory
0
Device will continue execution even if a mismatch is found between expected and calculated CRC
values for the non-boot block areas of memory
Bit 5 – CFGSCEN Non-Boot Block Area CRC Configuration Fuse Scan Enable
Value
Description
1
Non-boot block area CRC scan/calculation will not include Configuration Fuse values in its calculation
0
Non-boot block area CRC scan/calculation will include all Configuration Fuse values except
CONFIG14H-CONFIG16L in its calculation
Bit 4 – DATSCEN Non-Boot Block Area CRC Data EEPROM Scan Enable
Value
Description
1
Non-boot block area CRC scan/calculation will not include Data EEPROM values in its calculation
0
Non-boot block area CRC scan/calculation will include Data EEPROM values in its calculation
Bit 3 – SAFSCEN Non-Boot Block Area CRC SAF Area Scan Enable
Value
Description
1
Non-boot block area CRC scan/calculation will not include SAF area of Flash memory in its calculation
if SAF area is enabled
0
Non-boot block area CRC scan/calculation will include SAF area of Flash memory in its calculation if
SAF area is enabled
Bit 2 – APPSCEN Non-Boot Block Area CRC Application Code Area Scan Enable
Value
Description
1
Non-boot block area CRC scan/calculation will not include main application code area of Flash memory
in its calculations
0
Non-boot block area CRC scan/calculation will include main application code area of Flash memory in
its calculations
Bit 1 – BOOTCOE Continue on Error for Boot Block Areas Enable
Value
Description
1
Device will halt if a mismatch is found between expected and calculated CRC values for the boot block
areas of memory
0
Device will continue execution even if a mismatch is found between expected and calculated CRC
values for the boot block areas of memory
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 39
PIC18FXXQ83/84
APPENDIX B
Bit 0 – BOOTSCEN Boot Block Area CRC Scan Enable
Value
Description
1
CRC Scan/calculation on boot block area will not be run
0
CRC Scan/calculation on boot block area will be run
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 40
PIC18FXXQ83/84
APPENDIX B
6.12
CRC Boot Polynomial
Name:
Offset:
CRC Boot Polynomial
30 000Bh
The Polynomial for the CRC of the boot block segment of memory.
Note: The CRC-on-boot module uses a 32-bit polynomial, as such the polynomial configuration spans from
CONFIG12 to CONFIG15, with the MSB of CONFIG12 being the XOR of polynomial term X31and the LSB of
CONFIG15 being the XOR of polynomial term X0
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
28
27
BCRCPOL[31:24]
R/W
R/W
1
1
20
19
BCRCPOL[23:16]
R/W
R/W
1
1
12
11
BCRCPOL[15:8]
R/W
R/W
1
1
4
3
BCRCPOL[7:0]
R/W
R/W
1
1
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 31:0 – BCRCPOL[31:0] XOR of Polynomial Term Xn Enable bits
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 41
PIC18FXXQ83/84
APPENDIX B
6.13
CRC Boot Seed
Name:
Offset:
CRC Boot Seed
30 000Fh
The Seed for the CRC of the boot block segment of memory
Note: The CRC-on-boot module uses a 32-bit polynomial, as such the boot block seed spans from CONFIG16 to
CONFIG19, with the MSB of CONFIG16 being the MSB of the seed and the LSB of CONFIG19 being the LSB of the
seed.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
28
27
BCRCSEED[31:24]
R/W
R/W
1
1
20
19
BCRCSEED[23:16]
R/W
R/W
1
1
12
11
BCRCSEED[15:8]
R/W
R/W
1
1
4
3
BCRCSEED[7:0]
R/W
R/W
1
1
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 31:0 – BCRCSEED[31:0] Boot Block CRC Seed Field
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 42
PIC18FXXQ83/84
APPENDIX B
6.14
CRC Boot Expected Value
Name:
Offset:
CRC Boot Expected Value
30 0013h
The Expected Value for the CRC of the boot block segment of memory
Note: The CRC-on-boot module uses a 32-bit polynomial, as such the expected value spans from CONFIG20 to
CONFIG23, with the MSB of CONFIG20 being the MSB of the expected value, and the LSB of CONFIG23 being the
LSB of the expected value.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
28
27
BCRCERES[31:24]
R/W
R/W
1
1
20
19
BCRCERES[23:16]
R/W
R/W
1
1
12
11
BCRCERES[15:8]
R/W
R/W
1
1
4
3
BCRCERES[7:0]
R/W
R/W
1
1
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 31:0 – BCRCERES[31:0] Boot Block Area CRC Expected Result
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 43
PIC18FXXQ83/84
APPENDIX B
6.15
CRC Polynomial
Name:
Offset:
CRC Polynomial
30 0017h
The Polynomial for the CRC of the non-boot block segments of memory
Note: The CRC-on-boot module uses a 32-bit polynomial, as such the polynomial configuration spans from
CONFIG24 to CONFIG27, with the MSB of CONFIG24 being the XOR of polynomial term X31and the LSB of
CONFIG27 being the XOR of polynomial term X0
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
28
27
CRCPOL[31:24]
R/W
R/W
1
1
20
19
CRCPOL[23:16]
R/W
R/W
1
1
12
11
CRCPOL[15:8]
R/W
R/W
1
1
4
3
CRCPOL[7:0]
R/W
R/W
1
1
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 31:0 – CRCPOL[31:0] XOR of Polynomial Term Xn Enable bits
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 44
PIC18FXXQ83/84
APPENDIX B
6.16
CRC Seed
Name:
Offset:
CRC Seed
30 001B
The Seed for the CRC of the non-boot block segments of memory
Note: The CRC-on-boot module uses a 32-bit polynomial, as such the seed spans from CONFIG28 to CONFIG31,
with the MSB of CONFIG28 being the MSB of the seed and the LSB of CONFIG31 being the LSB of the seed.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
28
27
CRCSEED[31:24]
R/W
R/W
1
1
20
19
CRCSEED[23:16]
R/W
R/W
1
1
12
11
CRCSEED[15:8]
R/W
R/W
1
1
4
3
CRCSEED[7:0]
R/W
R/W
1
1
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 31:0 – CRCSEED[31:0] Non-Boot Block Area CRC Seed Field
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 45
PIC18FXXQ83/84
APPENDIX B
6.17
CRC Expected Value
Name:
Offset:
CRC Expected Value
30 001F
The Expected Value for the CRC of the non-boot block segments of memory
Note: The CRC-on-boot module uses a 32-bit polynomial, as such the expected value spans from CONFIG32 to
CONFIG35, with the MSB of CONFIG32 being the MSB of the expected value, and the LSB of CONFIG35 being the
LSB of the expected value.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
28
27
CRCERES[31:24]
R/W
R/W
1
1
20
19
CRCERES[23:16]
R/W
R/W
1
1
12
11
CRCERES[15:8]
R/W
R/W
1
1
4
3
CRCERES[7:0]
R/W
R/W
1
1
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 31:0 – CRCERES[31:0] Non-Boot Block Area CRC Expected Result
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 46
PIC18FXXQ83/84
The Microchip Website
Microchip provides online support via our website at http://www.microchip.com/. This website is used to make files
and information easily available to customers. Some of the content available includes:
•
•
•
Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online
discussion groups, Microchip design partner program member listing
Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of
seminars and events, listings of Microchip sales offices, distributors and factory representatives
Product Change Notification Service
Microchip’s product change notification service helps keep customers current on Microchip products. Subscribers will
receive email notification whenever there are changes, updates, revisions or errata related to a specified product
family or development tool of interest.
To register, go to http://www.microchip.com/pcn and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Embedded Solutions Engineer (ESE)
Technical Support
Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to
help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the website at: http://www.microchip.com/support
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
•
•
•
•
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these
methods, to our knowledge, require using the Microchip products in a manner outside the operating
specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of
intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code
protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection
features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital
Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you
may have a right to sue for relief under that Act.
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for your
convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 47
PIC18FXXQ83/84
your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER
EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,
indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such
use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless
otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,
BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,
KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST,
MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer,
QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control,
HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus,
ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider,
Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom,
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP,
INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM,
PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad
I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
©
2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-5126-6
Quality Management System
For information regarding Microchip’s Quality Management Systems, please visit http://www.microchip.com/quality.
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 48
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/support
Web Address:
http://www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Austin, TX
Tel: 512-257-3370
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Raleigh, NC
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
Australia - Sydney
Tel: 61-2-9868-6733
China - Beijing
Tel: 86-10-8569-7000
China - Chengdu
Tel: 86-28-8665-5511
China - Chongqing
Tel: 86-23-8980-9588
China - Dongguan
Tel: 86-769-8702-9880
China - Guangzhou
Tel: 86-20-8755-8029
China - Hangzhou
Tel: 86-571-8792-8115
China - Hong Kong SAR
Tel: 852-2943-5100
China - Nanjing
Tel: 86-25-8473-2460
China - Qingdao
Tel: 86-532-8502-7355
China - Shanghai
Tel: 86-21-3326-8000
China - Shenyang
Tel: 86-24-2334-2829
China - Shenzhen
Tel: 86-755-8864-2200
China - Suzhou
Tel: 86-186-6233-1526
China - Wuhan
Tel: 86-27-5980-5300
China - Xian
Tel: 86-29-8833-7252
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
India - Bangalore
Tel: 91-80-3090-4444
India - New Delhi
Tel: 91-11-4160-8631
India - Pune
Tel: 91-20-4121-0141
Japan - Osaka
Tel: 81-6-6152-7160
Japan - Tokyo
Tel: 81-3-6880- 3770
Korea - Daegu
Tel: 82-53-744-4301
Korea - Seoul
Tel: 82-2-554-7200
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Malaysia - Penang
Tel: 60-4-227-8870
Philippines - Manila
Tel: 63-2-634-9065
Singapore
Tel: 65-6334-8870
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Thailand - Bangkok
Tel: 66-2-694-1351
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Finland - Espoo
Tel: 358-9-4520-820
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-72400
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-72884388
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
© 2019 Microchip Technology Inc.
Programming Specification
DS40002137B-page 49
工商网监
湘ICP备2023018690号
