PIC18F46K22T-E/PT

PIC18(L)F2X/4XK22 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology High-Performance RISC CPU: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operation • 16-bit Wide Instructions, 8-bit Wide Data Path • Priority Levels for Interrupts • 31-Level, Software Accessible Hardware Stack • 8 x 8 Single-Cycle Hardware Multiplier screens and capacitive switches eXtreme Low-Power Features (XLP) (PIC18(L)F2X/4XK22): • • • • Special Microcontroller Features: • • • • Flexible Oscillator Structure: • Precision 16 MHz Internal Oscillator Block: - Factory-calibrated to ± 1% - Selectable frequencies, 31 kHz to 16 MHz - 64 MHz performance available using PLL – no external components required • Four Crystal modes up to 64 MHz • Two External Clock modes up to 64 MHz • 4x Phase Lock Loop (PLL) • Secondary Oscillator using Timer1 @ 32 kHz • Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops - Two-Speed Oscillator Start-up Analog Features: • Analog-to-Digital Converter (ADC) module: - 10-bit resolution, up to 30 external channels - Auto-acquisition capability - Conversion available during Sleep - Fixed Voltage Reference (FVR) channel - Independent input multiplexing • Analog Comparator module: - Two rail-to-rail analog comparators - Independent input multiplexing • Digital-to-Analog Converter (DAC) module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection • Charge Time Measurement Unit (CTMU) module: - Supports capacitive touch sensing for touch  2010-2021 Microchip Technology Inc. Sleep mode: 20 nA, typical Watchdog Timer: 300 nA, typical Timer1 Oscillator: 800 nA @ 32 kHz Peripheral Module Disable • • • • 2.3V to 5.5V Operation – PIC18FXXK22 devices 1.8V to 3.6V Operation – PIC18LFXXK22 devices Self-Programmable under Software Control High/Low-Voltage Detection (HLVD) module: - Programmable 16-Level - Interrupt on High/Low-Voltage Detection Programmable Brown-out Reset (BOR): - With software enable option - Configurable shutdown in Sleep Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s In-Circuit Serial Programming™ (ICSP™): - Single-Supply 3V In-Circuit Debug (ICD) Peripheral Highlights: • Up to 35 I/O Pins plus One Input-Only Pin: - High-Current Sink/Source 25 mA/25 mA - Three programmable external interrupts - Four programmable interrupt-on-change - Nine programmable weak pull-ups - Programmable slew rate • SR Latch: - Multiple Set/Reset input options • Two Capture/Compare/PWM (CCP) modules • Three Enhanced CCP (ECCP) modules: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-Shutdown and Auto-Restart - PWM steering • Two Host Synchronous Serial Port (MSSP) modules: - 3-wire SPI (supports all four modes) - I2C Host and Client modes with address mask DS40001412H-page 1 PIC18(L)F2X/4XK22 • Two Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) modules: - Supports RS-485, RS-232 and LIN - RS-232 operation using internal oscillator - Auto-Wake-up on Break - Auto-Baud Detect TABLE 1: PIC18(L)F2X/4XK22 FAMILY TYPES SRAM (Bytes) EEPROM (Bytes) I/O(1) 10-bit A/D Channels(2) CCP ECCP (Full-Bridge) ECCP (Half-Bridge) SPI I2C EUSART Comparator CTMU BOR/LVD SR Latch 8-bit Timer 16-bit Timer MSSP # Single-Word Instructions Data Memory Flash (Bytes) Program Memory PIC18(L)F23K22 8K 4096 512 256 25 19 2 1 2 2 2 2 2 Y Y Y 3 4 PIC18(L)F24K22 16K 8192 768 256 25 19 2 1 2 2 2 2 2 Y Y Y 3 4 PIC18(L)F25K22 32K 16384 1536 256 25 19 2 1 2 2 2 2 2 Y Y Y 3 4 PIC18(L)F26K22 64k 32768 3896 1024 25 19 2 1 2 2 2 2 2 Y Y Y 3 4 PIC18(L)F43K22 8K 4096 512 256 36 30 2 2 1 2 2 2 2 Y Y Y 3 4 PIC18(L)F44K22 16K 8192 768 256 36 30 2 2 1 2 2 2 2 Y Y Y 3 4 PIC18(L)F45K22 32K 16384 1536 256 36 30 2 2 1 2 2 2 2 Y Y Y 3 4 PIC18(L)F46K22 64k 32768 3896 1024 36 30 2 2 1 2 2 2 2 Y Y Y 3 4 Device Note 1: 2: One pin is input only. Channel count includes internal FVR and DAC channels. DS40001412H-page 2  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 28-PIN PDIP, SOIC, SSOP DIAGRAM MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 VSS RA7 RA6 RC0 RC1 RC2 RC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC18(L)F2XK22 FIGURE 1: 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RC7 RC6 RC5 RC4 28-PIN QFN, UQFN(1) DIAGRAM RA1 RA0 MCLR/VPP/RE3 RB7/PGD RB6/PGC RB5 RB4 FIGURE 2: 28 27 26 25 24 23 22 1 2 3 4 PIC18(L)F2XK22 5 6 7 8 9 10 11 12 13 14 21 20 19 18 17 16 15 RB3 RB2 RB1 RB0 VDD VSS RC7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RA2 RA3 RA4 RA5/ VSS RA7 RA6 Note 1: The 28-pin UQFN package is available only for PIC18(L)F23K22 and PIC18(L)F24K22.  2010-2021 Microchip Technology Inc. DS40001412H-page 3 PIC18(L)F2X/4XK22 40-PIN PDIP DIAGRAM MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 RE0 RE1 RE2 VDD VSS RA7 RA6 RC0 RC1 RC2 RC3 RD0 RD1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/PGD RB6/PGC RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4 RD3 RD2 40-PIN UQFN DIAGRAM 40 39 38 37 36 35 34 33 32 31 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 FIGURE 4: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIC18(L)F4XK22 FIGURE 3: 1 2 3 4 5 PIC18(L)F4XK22 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 RB3 RB4 RB5 PGC/RB6 PGD/RB7 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 11 12 13 14 15 16 17 18 19 20 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 DS40001412H-page 4  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 44-PIN TQFP DIAGRAM 1 2 3 4 5 6 PIC18(L)F4XK22 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 NC RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 NC NC RB4 RB5 PGC/RB6 PGD/RB7 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 22 21 20 19 18 17 16 15 14 13 12 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 44 43 42 41 40 39 38 37 36 35 34 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 NC FIGURE 5: 44-PIN QFN DIAGRAM 1 2 3 4 5 6 PIC18(L)F4XK22 7 8 9 10 11 33 RA6 32 RA7 31 VSS 30 VSS 29 VDD 28 VDD 27 RE2 26 RE1 25 RE0 24 RA5 23 RA4 RB3 NC RB4 RB5 PGC/RB6 PGD/RB7 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 22 21 20 19 18 17 16 15 14 13 12 RC7 RD4 RD5 RD6 RD7 VSS VDD VDD RB0 RB1 RB2 44 43 42 41 40 39 38 37 36 35 34 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 RC0 FIGURE 6:  2010-2021 Microchip Technology Inc. DS40001412H-page 5 PIC18(L)F2X/4XK22 C2IN+ AN3 Basic AN2 Pull-up RA2 Interrupts 1 Timers C12IN1- 4 MSSP C12IN0- AN1 EUSART AN0 RA1 (E)CCP Comparator RA0 28 Reference Analog 27 3 SR Latch I/O 2 CTMU 28-QFN, UQFN PIC18(L)F2XK22 PIN SUMMARY 28-SSOP, SOIC 28-SPDIP TABLE 2: VREFDACOUT 5 2 RA3 6 3 RA4 7 4 RA5 10 7 RA6 OSC2 CLKO 9 6 RA7 OSC1 CLKI 21 18 RB0 AN12 22 19 RB1 AN10 23 20 RB2 AN8 24 21 RB3 AN9 25 22 RB4 AN11 P1D T5G IOC Y 26 23 RB5 AN13 CCP3 P3A(4) P2B(3) T1G T3CKI(2) IOC Y AN4 C1IN+ VREF+ C1OUT SRQ C2OUT SRNQ SRI T0CKI SS1 CCP4 FLT0 SS2 INT0 Y P1C SCK2 SCL2 INT1 Y CTED1 P1B SDI2 SDA2 INT2 Y CTED2 CCP2 P2A(1) SDO2 C12IN3- C12IN2- CCP5 HLVDIN Y 27 24 RB6 TX2/CK2 IOC Y PGC 28 25 RB7 RX2/DT2 IOC Y PGD 11 8 RC0 P2B(3) SOSCO T1CKI T3CKI(2) T3G 12 9 RC1 CCP2 P2A(1) SOSCI 13 10 RC2 AN14 CCP1 P1A T5CKI 14 11 RC3 AN15 SCK1 SCL1 15 12 RC4 AN16 SDI1 SDA1 CTPLS 16 13 RC5 AN17 17 14 RC6 AN18 CCP3 P3A(4) TX1/CK1 18 15 RC7 AN19 P3B RX1/DT1 1 26 RE3 MCLR VPP VSS VSS VDD VDD 8, 19 5, 16 19 16 20 17 Note 1: 2: 3: 4: SDO1 CCP2/P2A multiplexed in fuses. T3CKI multiplexed in fuses. P2B multiplexed in fuses. CCP3/P3A multiplexed in fuses. DS40001412H-page 6  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 Basic Pull-up Interrupts Timers MSSP EUSART (E)CCP Reference SR Latch CTMU Comparator Analog I/O 44-QFN PIC18(L)F4XK22 PIN SUMMARY 44-TQFP 40-UQFN 40-PDIP TABLE 3: 2 17 19 19 RA0 AN0 C12IN0- 3 18 20 20 RA1 AN1 C12IN1- 4 19 21 21 RA2 AN2 C2IN+ 5 20 22 22 RA3 AN3 6 21 23 23 RA4 7 22 24 24 RA5 14 29 31 33 RA6 OSC2 CLKO 13 28 30 32 RA7 OSC1 CLKI 33 8 8 9 RB0 AN12 34 9 9 10 RB1 AN10 35 10 10 11 RB2 AN8 36 11 11 12 RB3 AN9 AN4 37 12 14 14 RB4 AN11 38 13 15 15 RB5 AN13 VREFDACOU T C1IN+ VREF+ C1OUT SRQ C2OUT SRNQ SRI T0CKI HLVDIN SS1 FLT0 C12IN3CTED1 C12IN2- CTED2 INT0 Y INT1 Y INT2 Y CCP2 P2A(1) Y CCP3 P3A(3) T5G IOC Y T1G T3CKI(2) IOC Y 39 14 16 16 RB6 IOC Y PGC 40 15 17 17 RB7 IOC Y PGD 15 30 32 34 RC0 P2B(4) SOSCO T1CKI T3CKI(2) T3G 16 31 35 35 RC1 CCP2(1) P2A SOSCI 17 32 36 36 RC2 AN14 CCP1 P1A T5CKI 18 33 37 37 RC3 AN15 SCK1 SCL1 23 38 42 42 RC4 AN16 SDI1 SDA1 CTPLS 24 39 43 43 RC5 AN17 25 40 44 44 RC6 AN18 TX1 CK1 26 1 1 1 RC7 AN19 RX1 DT1 19 34 38 38 RD0 AN20 20 35 39 39 RD1 AN21 CCP4 21 36 40 40 RD2 AN22 P2B(4) 22 37 41 41 RD3 AN23 P2C SS2 27 2 2 2 RD4 AN24 P2D SD02 28 3 3 3 RD5 AN25 P1B 29 4 4 4 RD6 AN26 P1C TX2 CK2 30 5 5 5 RD7 AN27 P1D RX2 DT2 8 23 25 25 RE0 AN5 CCP3 P3A(3) Note 1: 2: 3: 4: SDO1 SCK2 SCL2 SDI2 SDA2 CCP2 multiplexed in fuses. T3CKI multiplexed in fuses. CCP3/P3A multiplexed in fuses. P2B multiplexed in fuses.  2010-2021 Microchip Technology Inc. DS40001412H-page 7 PIC18(L)F2X/4XK22 CCP5 Interrupts Timers Basic AN7 Pull-up P3B MSSP AN6 EUSART RE1 (E)CCP Analog 26 Reference I/O 26 SR Latch 44-QFN 24 CTMU 44-TQFP 9 Comparator 40-UQFN PIC18(L)F4XK22 PIN SUMMARY (CONTINUED) 40-PDIP TABLE 3: Y MCLR VPP 10 25 27 27 RE2 1 16 18 18 RE3 11, 32 7, 26 7, 28 7,8 28, 29 VDD VDD 12, 31 6, 27 6, 29 6, 30, 31 VSS VSS — — 12, 13 33, 34 13 NC Note 1: 2: 3: 4: CCP2 multiplexed in fuses. T3CKI multiplexed in fuses. CCP3/P3A multiplexed in fuses. P2B multiplexed in fuses. DS40001412H-page 8  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Oscillator Module (With Fail-Safe Clock Monitor)) .................................................................................................................... 25 3.0 Power-Managed Modes ............................................................................................................................................................ 44 4.0 Reset ......................................................................................................................................................................................... 55 5.0 Memory Organization ................................................................................................................................................................ 64 6.0 Flash Program Memory............................................................................................................................................................. 90 7.0 Data EEPROM Memory ............................................................................................................................................................ 99 8.0 8 x 8 Hardware Multiplier......................................................................................................................................................... 104 9.0 Interrupts ................................................................................................................................................................................. 106 10.0 I/O Ports .................................................................................................................................................................................. 127 11.0 Timer0 Module ........................................................................................................................................................................ 154 12.0 Timer1/3/5 Module with Gate Control...................................................................................................................................... 157 13.0 Timer2/4/6 Module .................................................................................................................................................................. 169 14.0 Capture/Compare/PWM Modules ........................................................................................................................................... 173 15.0 Host Synchronous Serial Port (MSSP1 and MSSP2) Module................................................................................................. 204 16.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .............................................................. 259 17.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................. 288 18.0 Comparator Module................................................................................................................................................................. 302 19.0 Charge Time Measurement Unit (CTMU)................................................................................................................................. 311 20.0 SR LATCH ................................................................................................................................................................................. 326 21.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 331 22.0 Digital-to-Analog Converter (DAC) Module ............................................................................................................................. 333 23.0 High/Low-Voltage Detect (HLVD) ............................................................................................................................................ 337 24.0 Special Features of the CPU................................................................................................................................................... 343 25.0 Instruction Set Summary ......................................................................................................................................................... 360 26.0 Development Support.............................................................................................................................................................. 410 27.0 Electrical Specifications........................................................................................................................................................... 414 28.0 DC and AC Characteristics Graphs and Tables ...................................................................................................................... 453 29.0 Packaging Information............................................................................................................................................................. 509 Appendix A: Revision History............................................................................................................................................................ 534 Appendix B: Device Differences........................................................................................................................................................ 535 The Microchip Web Site .................................................................................................................................................................... 536 Customer Change Notification Service ............................................................................................................................................. 536 Customer Support ............................................................................................................................................................................. 536 Product Identification System ........................................................................................................................................................... 537  2010-2021 Microchip Technology Inc. DS40001412H-page 9 PIC18(L)F2X/4XK22 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Website; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products. DS40001412H-page 10  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F23K22 • PIC18LF23K22 • PIC18F24K22 • PIC18LF24K22 • PIC18F25K22 • PIC18LF25K22 • PIC18F26K22 • PIC18LF26K22 • PIC18F43K22 • PIC18LF43K22 • PIC18F44K22 • PIC18LF44K22 • PIC18F45K22 • PIC18LF45K22 • PIC18F46K22 • PIC18LF46K22 This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance, Flash program memory. On top of these features, the PIC18(L)F2X/4XK22 family introduces design enhancements that make these microcontrollers a logical choice for many highperformance, power sensitive applications. 1.1 1.1.1 New Core Features XLP TECHNOLOGY All of the devices in the PIC18(L)F2X/4XK22 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. • Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. • On-the-fly Mode Switching: The powermanaged modes are invoked by user code during operation, allowing the user to incorporate powersaving ideas into their application’s software design. • Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 27.0 “Electrical Specifications” for values.  2010-2021 Microchip Technology Inc. 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18(L)F2X/4XK22 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators • Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O) • Two External RC Oscillator modes with the same pin options as the External Clock modes • An internal oscillator block which contains a 16 MHz HFINTOSC oscillator and a 31 kHz LFINTOSC oscillator, which together provide eight user selectable clock frequencies, from 31 kHz to 16 MHz. This option frees the two oscillator pins for use as additional general purpose I/O. • A Phase Lock Loop (PLL) frequency multiplier, available to both external and internal oscillator modes, which allows clock speeds of up to 64 MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 kHz to 64 MHz – all without using an external crystal or clock circuit. Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: • Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the LFINTOSC. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued operation or a safe application shutdown. • Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or Wake-up from Sleep mode, until the primary clock source is available. DS40001412H-page 11 PIC18(L)F2X/4XK22 1.2 Other Special Features • Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 10K for program memory and 100K for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. • Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. • Extended Instruction Set: The PIC18(L)F2X/ 4XK22 family introduces an optional extension to the PIC18 instruction set, which adds eight new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C. • Enhanced CCP module: In PWM mode, this module provides one, two or four modulated outputs for controlling half-bridge and full-bridge drivers. Other features include: - Auto-Shutdown, for disabling PWM outputs on interrupt or other select conditions - Auto-Restart, to reactivate outputs once the condition has cleared - Output steering to selectively enable one or more of four outputs to provide the PWM signal. • Enhanced Addressable EUSART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). • 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit postscaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 27.0 “Electrical Specifications” for time-out periods. • Charge Time Measurement Unit (CTMU) • SR Latch Output: DS40001412H-page 12 1.3 Details on Individual Family Members Devices in the PIC18(L)F2X/4XK22 family are available in 28-pin and 40/44-pin packages. The block diagram for the device family is shown in Figure 1-1. The devices have the following differences: 1. 2. 3. 4. 5. 6. 7. Flash program memory Data Memory SRAM Data Memory EEPROM A/D channels I/O ports ECCP modules (Full/Half Bridge) Input Voltage Range/Power Consumption All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in the pin summary tables: Table 2 and Table 3, and I/O description tables: Table 1-2 and Table 1-3.  2010-2021 Microchip Technology Inc.  2010-2021 Microchip Technology Inc. TABLE 1-1: DEVICE FEATURES PIC18F23K22 PIC18LF23K22 PIC18F24K22 PIC18LF24K22 PIC18F25K22 PIC18(L)F25K22 PIC18F26K22 PIC18LF26K22 PIC18F43K22 PIC18LF43K22 PIC18F44K22 PIC18LF44K22 PIC18F45K22 PIC18LF45K22 PIC18F46K22 PIC18LF46K22 Program Memory (Bytes) 8192 16384 32768 65536 8192 16384 32768 65536 Program Memory (Instructions) 4096 8192 16384 32768 4096 8192 16384 32768 Features Data Memory (Bytes) 512 768 1536 3896 512 768 1536 3896 Data EEPROM Memory (Bytes) 256 256 256 1024 256 256 256 1024 A, B, C, E(1) A, B, C, E(1) A, B, C, E(1) A, B, C, E(1) A, B, C, D, E A, B, C, D, E A, B, C, D, E A, B, C, D, E Capture/Compare/PWM Modules (CCP) 2 2 2 2 2 2 2 2 Enhanced CCP Modules (ECCP) Half Bridge 2 2 2 2 1 1 1 1 Enhanced CCP Modules (ECCP) Full Bridge 1 1 1 1 2 2 2 2 2 internal 17 input 2 internal 17 input 2 internal 17 input 2 internal 17 input 2 internal 28 input 2 internal 28 input 2 internal 28 input 2 internal 28 input 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin QFN 28-pin UQFN 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin QFN 28-pin UQFN 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin QFN 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin QFN 40-pin PDIP 40-pin UQFN 44-pin QFN 44-pin TQFP 40-pin PDIP 40-pin UQFN 44-pin QFN 44-pin TQFP 40-pin PDIP 40-pin UQFN 44-pin QFN 44-pin TQFP 40-pin PDIP 40-pin UQFN 44-pin QFN 44-pin TQFP I/O Ports 10-bit Analog-to-Digital Module (ADC) Packages Interrupt Sources Timers (16-bit) 33 4 2 MSSP, 2 EUSART SR Latch Yes Charge Time Measurement Unit Module (CTMU) Yes Programmable High/Low-Voltage Detect (HLVD) Yes Programmable Brown-out Reset (BOR) Yes Resets (and Delays) DS40001412H-page 13 Instruction Set 75 Instructions; 83 with Extended Instruction Set enabled Operating Frequency Note 1: POR, BOR, RESET Instruction, Stack Overflow, Stack Underflow (PWRT, OST), MCLR, WDT PORTE contains the single RE3 read-only bit. DC - 64 MHz PIC18(L)F2X/4XK22 Serial Communications PIC18(L)F2X/4XK22 FIGURE 1-1: PIC18(L)F2X/4XK22 FAMILY BLOCK DIAGRAM Data Bus Table Pointer Data Latch 8 8 inc/dec logic Data Memory PCLATU PCLATH 21 PORTA Address Latch 20 PCU PCH PCL Program Counter RA0:RA7 12 Data Address 31-Level Stack 4 BSR Address Latch Program Memory (8/16/32/64 Kbytes) STKPTR 12 FSR0 FSR1 FSR2 Data Latch 8 PORTB 12 RB0:RB7 inc/dec logic Table Latch Instruction Bus 4 Access Bank Address Decode ROM Latch PORTC RC0:RC7 IR Instruction Decode and Control 8 State machine control signals PRODH PRODL PORTD 8 x 8 Multiply 3 8 W BITOP 8 Internal Oscillator Block OSC1(2) (2) OSC2 LFINTOSC Oscillator SOSCI 16 MHz Oscillator SOSCO Single-Supply Programming In-Circuit Debugger MCLR(1) BOR HLVD FVR DAC Note Comparators C1/C2 Data EEPROM ECCP1 ECCP2(3) ECCP3 Power-up Timer 8 8 8 8 Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor PORTE ALU RE0:RE2 RE3(1) 8 Precision Band Gap Reference RD0:RD7 FVR Timer0 Timer1 Timer3 Timer5 Timer2 Timer4 Timer6 CTMU DAC CCP4 CCP5 MSSP1 MSSP2 EUSART1 EUSART2 SR Latch ADC 10-bit FVR 1: RE3 is only available when MCLR functionality is disabled. 2: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional information. 3: Full-Bridge operation for PIC18(L)F4XK22, half-bridge operation for PIC18(L)F2XK22. DS40001412H-page 14  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS Pin Number PDIP, SOIC QFN, UQFN 2 27 3 28 4 1 5 2 6 3 7 4 10 7 Legend: Note 1: 2: Pin Name Pin Type Buffer Type Description RA0/C12IN0-/AN0 RA0 I/O TTL C12IN0- I Analog Comparators C1 and C2 inverting input. Digital I/O. AN0 I Analog Analog input 0. RA1/C12IN1-/AN1 RA1 I/O TTL C12IN1- I Analog Comparators C1 and C2 inverting input. Digital I/O. AN1 I Analog Analog input 1. RA2/C2IN+/AN2/DACOUT/VREFRA2 I/O TTL C2IN+ I Analog Digital I/O. Comparator C2 noninverting input. AN2 I Analog Analog input 2. DACOUT O Analog DAC Reference output. VREF- I Analog A/D reference voltage (low) input. RA3/C1IN+/AN3/VREF+ RA3 I/O TTL C1IN+ I Analog Digital I/O. Comparator C1 noninverting input. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/CCP5/C1OUT/SRQ/T0CKI RA4 I/O ST Digital I/O. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM 5 output. C1OUT O CMOS SRQ O TTL SR latch Q output. T0CKI I ST Timer0 external clock input. RA5 I/O TTL Digital I/O. C2OUT O CMOS SRNQ O TTL SR latch Q output. Comparator C1 output. RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4 Comparator C2 output. SS1 I TTL SPI client select input (MSSP). HLVDIN I Analog High/Low-Voltage Detect input. AN4 I Analog Analog input 4. TTL RA6/CLKO/OSC2 RA6 I/O CLKO O Digital I/O. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. OSC2 O Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010-2021 Microchip Technology Inc. DS40001412H-page 15 PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP, SOIC QFN, UQFN 9 6 21 18 22 19 23 20 24 21 Legend: Note 1: 2: Pin Name Pin Type Buffer Type Description RA7/CLKI/OSC1 RA7 I/O TTL CLKI I CMOS External clock source input. Always associated with pin function OSC1. Digital I/O. OSC1 I ST Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise. RB0/INT0/CCP4/FLT0/SRI/SS2/AN12 RB0 I/O TTL Digital I/O. INT0 I ST External interrupt 0. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM 4 output. FLT0 I ST PWM Fault input for ECCP Auto-Shutdown. SRI I ST SR latch input. SS2 I TTL SPI client select input (MSSP). AN12 I Analog Analog input 12. RB1/INT1/P1C/SCK2/SCL2/C12IN3-/AN10 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. P1C O CMOS SCK2 I/O ST Synchronous serial clock input/output for SPI mode (MSSP). SCL2 I/O ST Synchronous serial clock input/output for I2C mode (MSSP). C12IN3- I Analog Comparators C1 and C2 inverting input. AN10 I Analog Analog input 10. Enhanced CCP1 PWM output. RB2/INT2/CTED1/P1B/SDI2/SDA2/AN8 RB2 I/O TTL Digital I/O. INT2 I ST External interrupt 2. CTED1 I ST CTMU Edge 1 input. P1B O CMOS SDI2 I ST SPI data in (MSSP). Enhanced CCP1 PWM output. SDA2 I/O ST I2C data I/O (MSSP). AN8 I Analog Analog input 8. RB3/CTED2/P2A/CCP2/SDO2/C12IN2-/AN9 RB3 I/O TTL CTED2 I ST Digital I/O. P2A O CMOS CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. SDO2 O — SPI data out (MSSP). C12IN2- I Analog Comparators C1 and C2 inverting input. AN9 I Analog Analog input 9. CTMU Edge 2 input. Enhanced CCP2 PWM output. TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. DS40001412H-page 16  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP, SOIC QFN, UQFN 25 22 26 23 Pin Name 24 28 25 11 8 12 9 Note 1: 2: Description RB4 I/O TTL Digital I/O. IOC0 I TTL Interrupt-on-change pin. P1D O CMOS T5G I ST AN11 I Analog Enhanced CCP1 PWM output. Timer5 external clock gate input. Analog input 11. RB5/IOC1/P2B/P3A/CCP3/T3CKI/T1G/AN13 I/O TTL Digital I/O. Interrupt-on-change pin. IOC1 I TTL P2B(1) O CMOS P3A(1) O CMOS CCP3(1) I/O ST Capture 3 input/Compare 3 output/PWM 3 output. T3CKI(2) I ST Timer3 clock input. T1G I ST AN13 I Analog Enhanced CCP2 PWM output. Enhanced CCP3 PWM output. Timer1 external clock gate input. Analog input 13. RB6/IOC2/TX2/CK2/PGC RB6 I/O TTL Digital I/O. IOC2 I TTL Interrupt-on-change pin. TX2 O — EUSART asynchronous transmit. CK2 I/O ST EUSART synchronous clock (see related RXx/DTx). PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/IOC3/RX2/DT2/PGD RB7 I/O TTL Digital I/O. IOC3 I TTL Interrupt-on-change pin. RX2 I ST EUSART asynchronous receive. DT2 I/O ST EUSART synchronous data (see related TXx/CKx). PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin. Digital I/O. RC0/P2B/T3CKI/T3G/T1CKI/SOSCO RC0 I/O ST P2B(2) O CMOS T3CKI(1) I ST Timer3 clock input. T3G I ST Timer3 external clock gate input. T1CKI I ST Timer1 clock input. SOSCO O — Secondary oscillator output. I/O ST Digital I/O. Enhanced CCP1 PWM output. RC1/P2A/CCP2/SOSCI RC1 Legend: Buffer Type RB4/IOC0/P1D/T5G/AN11 RB5 27 Pin Type P2A O CMOS CCP2(1) I/O ST SOSCI I Analog Enhanced CCP2 PWM output. Capture 2 input/Compare 2 output/PWM 2 output. Secondary oscillator input. TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010-2021 Microchip Technology Inc. DS40001412H-page 17 PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP, SOIC QFN, UQFN Pin Name 13 10 RC2/CTPLS/P1A/CCP1/T5CKI/AN14 14 11 15 12 16 13 17 14 15 1 26 Legend: Note 1: 2: Buffer Type Description RC2 I/O ST CTPLS O — CTMU pulse generator output. P1A O CMOS Enhanced CCP1 PWM output. Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM 1 output. T5CKI I ST Timer5 clock input. AN14 I Analog Analog input 14. RC3/SCK1/SCL1/AN15 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode (MSSP). SCL1 I/O ST Synchronous serial clock input/output for I2C mode (MSSP). AN15 I Analog Analog input 15. RC4/SDI1/SDA1/AN16 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in (MSSP). SDA1 I/O ST I2C data I/O (MSSP). AN16 I Analog Analog input 16. RC5/SDO1/AN17 RC5 I/O ST Digital I/O. SDO1 O — SPI data out (MSSP). AN17 I Analog Analog input 17. RC6/P3A/CCP3/TX1/CK1/AN18 RC6 I/O ST P3A(2) O CMOS CCP3 18 Pin Type (2) Digital I/O. Enhanced CCP3 PWM output. I/O ST Capture 3 input/Compare 3 output/PWM 3 output. TX1 O — EUSART asynchronous transmit. CK1 I/O ST EUSART synchronous clock (see related RXx/DTx). AN18 I Analog Analog input 18. RC7/P3B/RX1/DT1/AN19 RC7 I/O ST P3B O CMOS Digital I/O. RX1 I ST EUSART asynchronous receive. DT1 I/O ST EUSART synchronous data (see related TXx/CKx). AN19 I Analog RE3 I ST VPP P MCLR I Enhanced CCP3 PWM output. Analog input 19. RE3/VPP/MCLR Digital input. Programming voltage input. ST Active-Low Master Clear (device Reset) input. TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. DS40001412H-page 18  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number QFN, UQFN Pin Name Pin Type Buffer Type 20 17 VDD P — Positive supply for logic and I/O pins. 8, 19 5, 16 VSS P — Ground reference for logic and I/O pins. PDIP, SOIC Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. Note 1: 2: TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS Pin Number PDIP TQFP QFN UQFN 2 19 19 17 3 4 5 6 20 21 22 23 Legend: Note Description 20 21 22 23 18 19 20 21 Pin Name Pin Type Buffer Type Description RA0/C12IN0-/AN0 RA0 I/O C12IN0- I Analog Comparators C1 and C2 inverting input. TTL Digital I/O. AN0 I Analog Analog input 0. RA1/C12IN1-/AN1 RA1 I/O C12IN1- I Analog Comparators C1 and C2 inverting input. TTL Digital I/O. AN1 I Analog Analog input 1. RA2/C2IN+/AN2/DACOUT/VREFRA2 I/O C2IN+ I TTL Digital I/O. Analog Comparator C2 noninverting input. AN2 I Analog Analog input 2. DACOUT O Analog DAC Reference output. VREF- I Analog A/D reference voltage (low) input. RA3/C1IN+/AN3/VREF+ RA3 I/O C1IN+ I TTL Digital I/O. Analog Comparator C1 noninverting input. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/C1OUT/SRQ/T0CKI RA4 I/O C1OUT O ST Digital I/O. SRQ O TTL SR latch Q output. T0CKI I ST Timer0 external clock input. CMOS Comparator C1 output. TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010-2021 Microchip Technology Inc. DS40001412H-page 19 PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP TQFP QFN UQFN 7 24 24 22 14 13 33 34 35 36 31 30 8 Note 32 9 9 10 10 11 Legend: 33 11 12 29 28 8 9 10 11 Pin Name Pin Type Buffer Type Description RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4 RA5 I/O TTL Digital I/O. C2OUT O SRNQ O TTL SR latch Q output. SS1 I TTL SPI client select input (MSSP1). HLVDIN I Analog High/Low-Voltage Detect input. AN4 I Analog Analog input 4. CMOS Comparator C2 output. RA6/CLKO/OSC2 RA6 I/O TTL CLKO O — In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Digital I/O. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. RA7/CLKI/OSC1 RA7 I/O CLKI I TTL OSC1 I ST Digital I/O. CMOS External clock source input. Always associated with pin function OSC1. Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise. RB0/INT0/FLT0/SRI/AN12 RB0 I/O TTL Digital I/O. INT0 I ST External interrupt 0. FLT0 I ST PWM Fault input for ECCP Auto-Shutdown. SRI I ST SR latch input. AN12 I Analog Analog input 12. RB1/INT1/C12IN3-/AN10 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. C12IN3- I Analog Comparators C1 and C2 inverting input. AN10 I Analog Analog input 10. RB2/INT2/CTED1/AN8 RB2 I/O TTL Digital I/O. INT2 I ST External interrupt 2. CTED1 I ST CTMU Edge 1 input. AN8 I Analog Analog input 8. RB3/CTED2/P2A/CCP2/C12IN2-/AN9 RB3 I/O TTL Digital I/O. CTED2 I ST CTMU Edge 2 input. P2A(2) O CCP2(2) I/O C12IN2- I Analog Comparators C1 and C2 inverting input. AN9 I Analog Analog input 9. CMOS Enhanced CCP2 PWM output. ST Capture 2 input/Compare 2 output/PWM 2 output. TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. DS40001412H-page 20  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP TQFP QFN UQFN 37 14 14 12 38 15 15 13 Pin Type Buffer Type RB4 I/O TTL Digital I/O. IOC0 I TTL Interrupt-on-change pin. T5G I ST Timer5 external clock gate input. AN11 I Pin Name RB4/IOC0/T5G/AN11 40 15 16 16 17 32 35 16 17 34 35 14 15 30 31 RB5 I/O TTL Digital I/O. IOC1 I TTL Interrupt-on-change pin. P3A(1) O CCP3(1) I/O ST Capture 3 input/Compare 3 output/PWM 3 output. (2) 36 Legend: Note 36 32 CMOS Enhanced CCP3 PWM output. I ST Timer3 clock input. T1G I ST Timer1 external clock gate input. AN13 I Analog Analog input 13. RB6/IOC2/PGC RB6 I/O TTL Digital I/O. IOC2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/IOC3/PGD RB7 I/O TTL Digital I/O. IOC3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin. ST Digital I/O. RC0/P2B/T3CKI/T3G/T1CKI/SOSCO RC0 I/O P2B(2) O T3CKI(1) I ST Timer3 clock input. T3G I ST Timer3 external clock gate input. T1CKI I ST Timer1 clock input. SOSCO O — Secondary oscillator output. I/O ST Digital I/O. CMOS Enhanced CCP1 PWM output. RC1/P2A/CCP2/SOSCI RC1 17 Analog Analog input 11. RB5/IOC1/P3A/CCP3/T3CKI/T1G/AN13 T3CKI 39 Description P2A(1) O CCP2(1) I/O SOSCI I CMOS Enhanced CCP2 PWM output. ST Capture 2 input/Compare 2 output/PWM 2 output. Analog Secondary oscillator input. RC2/CTPLS/P1A/CCP1/T5CKI/AN14 RC2 I/O ST Digital I/O. CTPLS O — CTMU pulse generator output. P1A O CCP1 I/O T5CKI I AN14 I CMOS Enhanced CCP1 PWM output. ST Capture 1 input/Compare 1 output/PWM 1 output. ST Timer5 clock input. Analog Analog input 14. TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010-2021 Microchip Technology Inc. DS40001412H-page 21 PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP TQFP QFN UQFN 18 37 37 33 23 24 25 26 19 20 42 43 44 1 Note 43 44 1 38 39 Legend: 42 38 39 38 39 40 1 34 35 Pin Type Buffer Type RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode (MSSP). SCL1 I/O ST Synchronous serial clock input/output for I2C mode (MSSP). AN15 I Pin Name Description RC3/SCK1/SCL1/AN15 Analog Analog input 15. RC4/SDI1/SDA1/AN16 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in (MSSP). SDA1 I/O ST I2C data I/O (MSSP). AN16 I Analog Analog input 16. RC5/SDO1/AN17 RC5 I/O ST Digital I/O. SDO1 O — SPI data out (MSSP). AN17 I Analog Analog input 17. RC6/TX1/CK1/AN18 RC6 I/O ST Digital I/O. TX1 O — EUSART asynchronous transmit. CK1 I/O ST EUSART synchronous clock (see related RXx/ DTx). AN18 I Analog Analog input 18. RC7/RX1/DT1/AN19 RC7 I/O ST Digital I/O. RX1 I ST EUSART asynchronous receive. DT1 I/O ST EUSART synchronous data (see related TXx/ CKx). AN19 I Analog Analog input 19. RD0/SCK2/SCL2/AN20 RD0 I/O ST Digital I/O. SCK2 I/O ST Synchronous serial clock input/output for SPI mode (MSSP). SCL2 I/O ST Synchronous serial clock input/output for I2C mode (MSSP). AN20 I Analog Analog input 20. RD1/CCP4/SDI2/SDA2/AN21 RD1 I/O ST Digital I/O. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM 4 output. SDI2 I ST SPI data in (MSSP). SDA2 I/O ST I2C data I/O (MSSP). AN21 I Analog Analog input 21. TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. DS40001412H-page 22  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP TQFP QFN UQFN 21 40 40 36 22 27 28 29 30 8 9 41 2 Note 2 3 3 4 4 5 5 25 26 Legend: 41 25 26 37 2 3 4 5 23 24 Pin Type Buffer Type RD2 I/O ST P2B(1) O CMOS Enhanced CCP2 PWM output. AN22 I Analog Analog input 22. Pin Name Description RD2/P2B/AN22 Digital I/O RD3/P2C/SS2/AN23 RD3 I/O P2C O SS2 I AN23 I ST Digital I/O. CMOS Enhanced CCP2 PWM output. TTL SPI client select input (MSSP). Analog Analog input 23. RD4/P2D/SDO2/AN24 RD4 I/O P2D O SDO2 O AN24 I ST Digital I/O. CMOS Enhanced CCP2 PWM output. — SPI data out (MSSP). Analog Analog input 24. RD5/P1B/AN25 RD5 I/O P1B O CMOS Enhanced CCP1 PWM output. ST Digital I/O. AN25 I Analog Analog input 25. RD6/P1C/TX2/CK2/AN26 RD6 I/O P1C O ST Digital I/O. TX2 O — EUSART asynchronous transmit. CK2 I/O ST EUSART synchronous clock (see related RXx/ DTx). AN26 I CMOS Enhanced CCP1 PWM output. Analog Analog input 26. RD7/P1D/RX2/DT2/AN27 RD7 I/O P1D O ST Digital I/O. RX2 I ST EUSART asynchronous receive. DT2 I/O ST EUSART synchronous data (see related TXx/ CKx). AN27 I CMOS Enhanced CCP1 PWM output. Analog Analog input 27. RE0/P3A/CCP3/AN5 RE0 I/O P3A(2) O CCP3(2) I/O AN5 I ST Digital I/O. CMOS Enhanced CCP3 PWM output. ST Capture 3 input/Compare 3 output/PWM 3 output. Analog Analog input 5. RE1/P3B/AN6 RE1 I/O P3B O CMOS Enhanced CCP3 PWM output. ST Digital I/O. AN6 I Analog Analog input 6. TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear.  2010-2021 Microchip Technology Inc. DS40001412H-page 23 PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP TQFP QFN UQFN 10 27 27 25 1 18 18 16 Pin Type Buffer Type RE2 I/O ST Digital I/O. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM 5 output AN7 I Pin Name Description RE2/CCP5/AN7 Analog Analog input 7. RE3/VPP/MCLR RE3 I ST Digital input. VPP P MCLR I ST Active-low Master Clear (device Reset) input. Programming voltage input. 11,32 7, 28 7, 8, 28, 29 7, 26 VDD P — Positive supply for logic and I/O pins. 12,31 6, 29 6,30, 31 6, 27 VSS P — Ground reference for logic and I/O pins. 12,13, 33,34 13 Legend: Note NC TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. 2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. DS40001412H-page 24  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 2.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 2.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 2-1 illustrates a block diagram of the oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of three internal oscillators, with a choice of speeds selectable via software. Additional clock features include: • Selectable system clock source between external or internal sources via software. • Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. • Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources.  2010-2021 Microchip Technology Inc. The primary clock module can be configured to provide one of six clock sources as the primary clock. 1. 2. 3. 4. 5. 6. RC LP XT INTOSC HS EC External Resistor/Capacitor Low-Power Crystal Crystal/Resonator Internal Oscillator High-Speed Crystal/Resonator External Clock The HS and EC oscillator circuits can be optimized for power consumption and oscillator speed using settings in FOSC. Additional FOSC selections enable RA6 to be used as I/O or CLKO (FOSC/4) for RC, EC and INTOSC Oscillator modes. Primary Clock modes are selectable by the FOSC bits of the CONFIG1H Configuration register. The primary clock operation is further defined by these Configuration and register bits: 1. 2. 3. 4. 5. 6. 7. 8. PRICLKEN (CONFIG1H) PRISD (OSCCON2) PLLCFG (CONFIG1H) PLLEN (OSCTUNE) HFOFST (CONFIG3H) IRCF (OSCCON) MFIOSEL (OSCCON2) INTSRC (OSCTUNE) The HFINTOSC, MFINTOSC and LFINTOSC are factory calibrated high, medium and low-frequency oscillators, respectively, which are used as the internal clock sources. DS40001412H-page 25 PIC18(L)F2X/4XK22 FIGURE 2-1: SIMPLIFIED OSCILLATOR SYSTEM BLOCK DIAGRAM Secondary Oscillator(1) SOSCO Secondary Oscillator (SOSC) SOSCI Low-Power Mode Event Switch (SCS) SOSCOUT 2 Primary Clock Module Secondary Oscillator PRICLKEN PRISD PLL_Select(3) (4) OSC2 OSC1 FOSC(5) Primary Oscillator(2) ( OSC) Primary Oscillator INTOSC 0 4xPLL 0 Primary Clock 00 1 1 INTOSC Clock Switch MUX EN 01 1x Internal Oscillator IRCF MFIOSEL INTSRC 3 3 INTOSC Divide Circuit HF-16 MHZ HF-8 MHZ HF-4 MHZ HF-2 MHZ HF-1 MHZ HF-500 kHZ HF-250 kHZ HF-31.25 kHZ MFINTOSC (500 kHz) MF-500 kHZ MF-250 kHZ MF-31.25 kHZ LFINTOSC Internal Oscillator MUX(3) HFINTOSC (16 MHz) INTOSC LF-31.25 kHz (31.25 kHz) Note 1: Details in Figure 2-4. 2: Details in Figure 2-2. 3: Details in Figure 2-3. 4: Details in Table 2-1. 5: The Primary Oscillator MUX uses the INTOSC branch when FOSC = 100x. DS40001412H-page 26  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 2.2 Oscillator Control The OSCCON, OSCCON2 and OSCTUNE registers (Register 2-1 to Register 2-3) control several aspects of the device clock’s operation, both in full-power operation and in power-managed modes. • • • • • • Main System Clock Selection (SCS) Primary Oscillator Circuit Shutdown (PRISD) Secondary Oscillator Enable (SOSCGO) Primary Clock Frequency 4x multiplier (PLLEN) Internal Frequency selection bits (IRCF, INTSRC) Clock Status bits (OSTS, HFIOFS, MFIOFS, LFIOFS. SOSCRUN, PLLRDY) • Power management selection (IDLEN) 2.2.1 MAIN SYSTEM CLOCK SELECTION The System Clock Select bits, SCS, select the main clock source. The available clock sources are • Primary clock defined by the FOSC bits of CONFIG1H. The primary clock can be the primary oscillator, an external clock, or the internal oscillator block. • Secondary clock (secondary oscillator) • Internal oscillator block (HFINTOSC, MFINTOSC and LFINTOSC). 2.2.3 LOW FREQUENCY SELECTION When a nominal output frequency of 31.25 kHz is selected (IRCF = 000), users may choose which internal oscillator acts as the source. This is done with the INTSRC bit of the OSCTUNE register and MFIOSEL bit of the OSCCON2 register. See Figure 2-2 and Register 2-1 for specific 31.25 kHz selection. This option allows users to select a 31.25 kHz clock (MFINTOSC or HFINTOSC) that can be tuned using the TUN bits in OSCTUNE register, while maintaining power savings with a very low clock speed. LFINTOSC always remains the clock source for features such as the Watchdog Timer and the Fail-Safe Clock Monitor, regardless of the setting of INTSRC and MFIOSEL bits This option allows users to select the tunable and more precise HFINTOSC as a clock source, while maintaining power savings with a very low clock speed. 2.2.4 POWER MANAGEMENT The IDLEN bit of the OSCCON register determines whether the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed. The clock source changes immediately after one or more of the bits is written to, following a brief clock transition interval. The SCS bits are cleared to select the primary clock on all forms of Reset. 2.2.2 INTERNAL FREQUENCY SELECTION The Internal Oscillator Frequency Select bits (IRCF) select the frequency output of the internal oscillator block. The choices are the LFINTOSC source (31.25 kHz), the MFINTOSC source (31.25 kHz, 250 kHz or 500 kHz) and the HFINTOSC source (16 MHz) or one of the frequencies derived from the HFINTOSC postscaler (31.25 kHz to 8 MHz). If the internal oscillator block is supplying the main clock, changing the states of these bits will have an immediate change on the internal oscillator’s output. On device Resets, the output frequency of the internal oscillator is set to the default frequency of 1 MHz.  2010-2021 Microchip Technology Inc. DS40001412H-page 27 PIC18(L)F2X/4XK22 FIGURE 2-2: INTERNAL OSCILLATOR MUX BLOCK DIAGRAM FIGURE 2-3: FOSC = 100x PLLCFG IRCF MFIOSEL INTSRC 3 HF-16 MHZ HF-8 MHZ HF-4 MHZ HF-2 MHZ HF-1 MHZ PLLEN PLL_Select 111 110 101 100 011 MF-500 KHZ 1 HF-500 KHZ 500 kHZ 010 250 kHZ 001 0 MF-250 KHZ 1 HF-250 KHZ INTOSC 0 HF-31.25 KHZ 11 MF-31.25 KHZ 10 LF-31.25 KHZ 0X TABLE 2-1: PLL_SELECT BLOCK DIAGRAM 31.25 kHZ 000 PLL_SELECT TRUTH TABLE Primary Clock MUX Source FOSC PLLCFG PLLEN PLL_Select FOSC (any source) 0000-1111 0 0 0 OSC1/OSC2 (external source) 0000-0111 1010-1111 1 x 1 0 1 1 1000-1001 x 0 0 x 1 1 INTOSC (internal source) DS40001412H-page 28  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 2-4: SECONDARY OSCILLATOR AND EXTERNAL CLOCK INPUTS SOSCGO T1SOSCEN T3SOSCEN T5SOSCEN SOSCEN To Clock Switch Module SOSCI EN SOSCOUT Secondary Oscillator SOSCO T1CKI T3G T3CKI 1 T1CLK_EXT_SRC SOSCEN 0 T1SOSCEN SOSCEN T3G SOSCEN 1 T3CLK_EXT_SRC 0 0 1 T3CKI T1G T3SOSCEN T3CMX T1G 1 T5CLK_EXT_SRC 0 T5CKI T5SOSCEN T5G  2010-2021 Microchip Technology Inc. T5G DS40001412H-page 29 PIC18(L)F2X/4XK22 2.3 Register Definitions: Oscillator Control REGISTER 2-1: R/W-0 OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 IDLEN R/W-1 R/W-1 R-q R-0 (1) IRCF OSTS HFIOFS R/W-0 R/W-0 SCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF: Internal RC Oscillator Frequency Select bits(2) 111 = HFINTOSC – (16 MHz) 110 = HFINTOSC/2 – (8 MHz) 101 = HFINTOSC/4 – (4 MHz) 100 = HFINTOSC/8 – (2 MHz) 011 = HFINTOSC/16 – (1 MHz)(3) If INTSRC = 0 and MFIOSEL = 0: 010 = HFINTOSC/32 – (500 kHz) 001 = HFINTOSC/64 – (250 kHz) 000 = LFINTOSC – (31.25 kHz) If INTSRC = 1 and MFIOSEL = 0: 010 = HFINTOSC/32 – (500 kHz) 001 = HFINTOSC/64 – (250 kHz) 000 = HFINTOSC/512 – (31.25 kHz) If INTSRC = 0 and MFIOSEL = 1: 010 = MFINTOSC – (500 kHz) 001 = MFINTOSC/2 – (250 kHz) 000 = LFINTOSC – (31.25 kHz) If INTSRC = 1 and MFIOSEL = 1: 010 = MFINTOSC – (500 kHz) 001 = MFINTOSC/2 – (250 kHz) 000 = MFINTOSC/16 – (31.25 kHz) bit 3 OSTS: Oscillator Start-up Time-out Status bit 1 = Device is running from the clock defined by FOSC of the CONFIG1H register 0 = Device is running from the internal oscillator (HFINTOSC, MFINTOSC or LFINTOSC) bit 2 HFIOFS: HFINTOSC Frequency Stable bit 1 = HFINTOSC frequency is stable 0 = HFINTOSC frequency is not stable bit 1-0 SCS: System Clock Select bit 1x = Internal oscillator block 01 = Secondary (SOSC) oscillator 00 = Primary clock (determined by FOSC in CONFIG1H). Note 1: 2: 3: Reset state depends on state of the IESO Configuration bit. INTOSC source may be determined by the INTSRC bit in OSCTUNE and the MFIOSEL bit in OSCCON2. Default output frequency of HFINTOSC on Reset. DS40001412H-page 30  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 2-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2 R-0/0 R-0/q U-0 PLLRDY SOSCRUN — R/W-0/0 MFIOSEL R/W-0/u SOSCGO (1) R/W-1/1 R-x/u R-0/0 PRISD MFIOFS LFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown q = depends on condition -n/n = Value at POR and BOR/Value at all other Resets bit 7 PLLRDY: PLL Run Status bit 1 = System clock comes from 4xPLL 0 = System clock comes from an oscillator, other than 4xPLL bit 6 SOSCRUN: SOSC Run Status bit 1 = System clock comes from secondary SOSC 0 = System clock comes from an oscillator, other than SOSC bit 5 Unimplemented: Read as ‘0’. bit 4 MFIOSEL: MFINTOSC Select bit 1 = MFINTOSC is used in place of HFINTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz 0 = MFINTOSC is not used bit 3 SOSCGO(1): Secondary Oscillator Start Control bit 1 = Secondary oscillator is enabled. 0 = Secondary oscillator is shut off if no other sources are requesting it. bit 2 PRISD: Primary Oscillator Drive Circuit Shutdown bit 1 = Oscillator drive circuit on 0 = Oscillator drive circuit off (zero power) bit 1 MFIOFS: MFINTOSC Frequency Stable bit 1 = MFINTOSC is stable 0 = MFINTOSC is not stable bit 0 LFIOFS: LFINTOSC Frequency Stable bit 1 = LFINTOSC is stable 0 = LFINTOSC is not stable Note 1: The SOSCGO bit is only reset on a POR Reset.  2010-2021 Microchip Technology Inc. DS40001412H-page 31 PIC18(L)F2X/4XK22 2.4 Clock Source Modes Clock Source modes can be classified as external or internal. 2.5 External Clock Modes 2.5.1 OSCILLATOR START-UP TIMER (OST) • External Clock modes rely on external circuitry for the clock source. Examples are: Clock modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and ResistorCapacitor (RC mode) circuits. • Internal clock sources are contained internally within the Oscillator block. The Oscillator block has three internal oscillators: the 16 MHz HighFrequency Internal Oscillator (HFINTOSC), 500 kHz Medium-Frequency Internal Oscillator (MFINTOSC) and the 31.25 kHz Low-Frequency Internal Oscillator (LFINTOSC). When the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 2-2. The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits of the OSCCON register. See Section 2.11 “Clock Switching” for additional information. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 2.12 “Two-Speed Clock Start-up Mode”). TABLE 2-2: OSCILLATOR DELAY EXAMPLES Switch From Switch To Frequency Sleep/POR/BOR LFINTOSC MFINTOSC HFINTOSC 31.25 kHz 31.25 kHz to 500 kHz 31.25 kHz to 16 MHz Sleep/POR/BOR EC, RC DC – 64 MHz LFINTOSC (31.25 kHz) Sleep/POR/BOR Sleep/POR/BOR LFINTOSC (31.25 kHz) 2.5.2 EC, RC DC – 64 MHz LP, XT, HS 32 kHz to 40 MHz 4xPLL 32 MHz to 64 MHz LFINTOSC HFINTOSC 31.25 kHz to 16 MHz EC MODE The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure 2-5 shows the pin connections for EC mode. The External Clock (EC) offers different power modes, Low Power (ECLP), Medium Power (ECMP) and High Power (ECHP), selectable by the FOSC bits. Each mode is best suited for a certain range of frequencies. The ranges are: • ECLP – below 500 kHz • ECMP – between 500 kHz and 16 MHz • ECHP – above 16 MHz The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. DS40001412H-page 32 Oscillator Delay Oscillator Start-up Delay (TIOSC_ST) 2 instruction cycles 1 cycle of each 1024 Clock Cycles (OST) 1024 Clock Cycles (OST) + 2 ms 1 s (approx.) Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. FIGURE 2-5: EXTERNAL CLOCK (EC) MODE OPERATION OSC1/CLKIN Clock from Ext. System PIC® MCU I/O Note 1: OSC2/CLKOUT(1) Alternate pin functions are listed in Section 1.0 “Device Overview”.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 2.5.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 2-6). The mode selects a low, medium or high gain setting of the internal inverteramplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user may consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, refer to the following Microchip Application Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode offers a Medium Power (MP) and a High Power (HP) option selectable by the FOSC bits. The MP selections are best suited for oscillator frequencies between 4 MHz and 16 MHz. The HP selection has the highest gain setting of the internal inverter-amplifier and is best suited for frequencies above 16 MHz. HS mode is best suited for resonators that require a high drive setting. FIGURE 2-6: CERAMIC RESONATOR OPERATION (XT OR HS MODE) QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) PIC® MCU C1 PIC® MCU OSC1/CLKIN C1 To Internal Logic RP(3) OSC1/CLKIN RF(2) Sleep To Internal Logic Quartz Crystal C2 FIGURE 2-7: RS(1) RF(2) Sleep OSC2/CLKOUT Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.  2010-2021 Microchip Technology Inc. C2 Ceramic RS(1) Resonator OSC2/CLKOUT Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. DS40001412H-page 33 PIC18(L)F2X/4XK22 2.5.4 2.6 EXTERNAL RC MODES The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. 2.5.4.1 FIGURE 2-8: EXTERNAL RC MODES VDD PIC® MCU REXT OSC1/CLKIN Internal Clock CEXT VSS FOSC/4 or I/O(2) OSC2/CLKOUT(1) Recommended values: 10 k  REXT  100 k CEXT > 20 pF Note 1: 2: 2.5.4.2 The oscillator module has three independent, internal oscillators that can be configured or selected as the system clock source. 1. RC Mode In RC mode, the RC circuit connects to OSC1. OSC2/ CLKOUT outputs the RC oscillator frequency divided by four. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 2-8 shows the external RC mode connections. Alternate pin functions are listed in Section 1.0 “Device Overview”. Output depends upon RC or RCIO clock mode. RCIO Mode In RCIO mode, the RC circuit is connected to OSC1. OSC2 becomes a general purpose I/O pin. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: Internal Clock Modes 2. 3. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 2-3). The MFINTOSC (Medium-Frequency Internal Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 2-3). The LFINTOSC (Low-Frequency Internal Oscillator) is factory calibrated and operates at 31.25 kHz. The LFINTOSC cannot be useradjusted, but is designed to be stable over temperature and voltage. The system clock speed can be selected via software using the Internal Oscillator Frequency select bits IRCF of the OSCCON register. The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bits of the OSCCON register. See Section 2.11 “Clock Switching” for more information. 2.6.1 INTOSC WITH I/O OR CLOCKOUT Two of the clock modes selectable with the FOSC bits of the CONFIG1H Configuration register configure the internal oscillator block as the primary oscillator. Mode selection determines whether the OSC2/ CLKOUT pin will be configured as general purpose I/O or FOSC/4 (CLKOUT). In both modes, the OSC1/CLKIN pin is configured as general purpose I/O. See Section 24.0 “Special Features of the CPU” for more information. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. • input threshold voltage variation • component tolerances • packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used. DS40001412H-page 34  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 2.6.1.1 OSCTUNE Register The OSCTUNE register also implements the INTSRC and PLLEN bits, which control certain features of the internal oscillator block. The HFINTOSC/MFINTOSC oscillator circuits are factory calibrated but can be adjusted in software by writing to the TUN bits of the OSCTUNE register (Register 2-3). The INTSRC bit allows users to select which internal oscillator provides the clock source when the 31.25 kHz frequency option is selected. This is covered in greater detail in Section 2.2.3 “Low Frequency Selection”. The default value of the TUN is ‘000000’. The value is a 6-bit two’s complement number. When the OSCTUNE register is modified, the HFINTOSC/MFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. The PLLEN bit controls the operation of the frequency multiplier, PLL, for all primary external clock sources and internal oscillator modes. However, the PLL is intended for operation with clock sources between 4 MHz and 16 MHz. For more details about the function of the PLLEN bit, see Section 2.8.2 “PLL in HFINTOSC Modes” The TUN bits in OSCTUNE do not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. 2.7 Register Definitions: Oscillator Tuning REGISTER 2-3: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 INTSRC PLLEN R/W-0 (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TUN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25 kHz device clock derived from the MFINTOSC or HFINTOSC source 0 = 31.25 kHz device clock derived directly from LFINTOSC internal oscillator bit 6 PLLEN: Frequency Multiplier 4xPLL for HFINTOSC Enable bit(1) 1 = PLL enabled 0 = PLL disabled bit 5-0 TUN: Frequency Tuning bits – use to adjust MFINTOSC and HFINTOSC frequencies 011111 = Maximum frequency 011110 = ••• 000001 = 000000 = Oscillator module (HFINTOSC and MFINTOSC) are running at the factory calibrated frequency. 111111 = ••• 100000 = Minimum frequency Note 1: The PLLEN bit is active for all the primary clock sources (internal or external) and is designed to operate with clock frequencies between 4 MHz and 16 MHz.  2010-2021 Microchip Technology Inc. DS40001412H-page 35 PIC18(L)F2X/4XK22 2.7.1 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is a 31.25 kHz internal clock source. The LFINTOSC is not tunable, but is designed to be stable across temperature and voltage. See Section 27.0 “Electrical Specifications” for the LFINTOSC accuracy specifications. The output of the LFINTOSC can be a clock source to the primary clock or the INTOSC clock (see Figure 2-1). The LFINTOSC is also the clock source for the Powerup Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). 2.7.2 FREQUENCY SELECT BITS (IRCF) The HFINTOSC (16 MHz) and MFINTOSC (500 MHz) outputs connect to a divide circuit that provides frequencies of 16 MHz to 31.25 kHz. These divide circuit frequencies, along with the 31.25 kHz LFINTOSC output, are multiplexed to provide a single INTOSC clock output (see Figure 2-1). The IRCF bits of the OSCCON register, the MFIOSEL bit of the OSCCON2 register and the INTSRC bit of the OSCTUNE register, select the output frequency of the internal oscillators. One of eight frequencies can be selected via software: • • • • • • • • 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz (default after Reset) 500 kHz (MFINTOSC or HFINTOSC) 250 kHz (MFINTOSC or HFINTOSC) 31 kHz (LFINTOSC, MFINTOSC or HFINTOSC) 2.7.3 INTOSC FREQUENCY DRIFT The factory calibrates the internal oscillator block outputs (HFINTOSC/MFINTOSC) for 16 MHz/500 kHz. However, this frequency may drift as VDD or temperature changes. It is possible to adjust the HFINTOSC/MFINTOSC frequency by modifying the value of the TUN bits in the OSCTUNE register. This has no effect on the LFINTOSC clock source frequency. 2.7.3.1 Compensating with the EUSART An adjustment may be required when the EUSART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high; to adjust for this, decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate, increment OSCTUNE to increase the clock frequency. 2.7.3.2 Compensating with the Timers This technique compares device clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. 2.7.3.3 Compensating with the CCP Module in Capture Mode A CCP module can use free running Timer1, Timer3 or Timer5 clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calculated time, the internal oscillator block is running too fast; to compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow; to compensate, increment the OSCTUNE register. Tuning the HFINTOSC/MFINTOSC source requires knowing when to make the adjustment, in which direction it may be made and, in some cases, how large a change is needed. Three possible compensation techniques are discussed in the following sections. However, other techniques may be used. DS40001412H-page 36  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 2.8 PLL Frequency Multiplier A Phase-Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from the crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from an internal oscillator. 2.8.1 PLL IN EXTERNAL OSCILLATOR MODES The PLL can be enabled for any of the external oscillator modes using the OSC1/OSC2 pins by either setting the PLLCFG bit (CONFIG1H), or setting the PLLEN bit (OSCTUNE). The PLL is designed for input frequencies of 4 MHz up to 16 MHz. The PLL then multiplies the oscillator output frequency by four to produce an internal clock frequency up to 64 MHz. Oscillator frequencies below 4 MHz may not be used with the PLL. 2.8.2 PLL IN HFINTOSC MODES The 4x frequency multiplier can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with the internal oscillator. When enabled, the PLL multiplies the HFINTOSC by four to produce clock rates up to 64 MHz. Unlike external clock modes, when internal clock modes are enabled, the PLL can only be controlled through software. The PLLEN control bit of the OSCTUNE register is used to enable or disable the PLL operation when the HFINTOSC is used. The PLL is designed for input frequencies of 4 MHz up to 16 MHz.  2010-2021 Microchip Technology Inc. DS40001412H-page 37 PIC18(L)F2X/4XK22 2.9 Effects of Power-Managed Modes on the Various Clock Sources For more information about the modes discussed in this section see Section 3.0 “Power-Managed Modes”. A quick reference list is also available in Table 3-1. When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the secondary oscillator (SOSC) is operating and providing the device clock. The secondary oscillator may also run in all powermanaged modes if required to clock Timer1, Timer3 or Timer5. In internal oscillator modes (INTOSC_RUN and INTOSC_IDLE), the internal oscillator block provides the device clock source. The 31.25 kHz LFINTOSC output can be used directly to provide the clock and may be enabled to support various special features, regardless of the power-managed mode (see Section 24.3 “Watchdog Timer (WDT)”, Section 2.12 “Two-Speed Clock Start-up Mode” and Section 2.13 “Fail-Safe Clock Monitor” for more information on WDT, Fail-Safe Clock Monitor and TwoSpeed Start-up). The HFINTOSC and MFINTOSC outputs may be used directly to clock the device or may be divided down by the postscaler. The HFINTOSC and MFINTOSC outputs are disabled when the clock is provided directly from the LFINTOSC output. When the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The LFINTOSC is required to support WDT operation. Other features may be operating that do not require a device clock source (i.e., SSP client, PSP, INTn pins and others). Peripherals that may add significant current consumption are listed in Section 27.8 “DC Characteristics: Input/Output Characteristics, PIC18(L)F2X/4XK22”. DS40001412H-page 38 2.10 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 4.6 “Device Reset Timers”. The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up. It is enabled by clearing (= 0) the PWRTEN Configuration bit. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. When the PLL is enabled with external oscillator modes, the device is kept in Reset for an additional 2 ms, following the OST delay, so the PLL can lock to the incoming clock frequency. There is a delay of interval TCSD, following POR, while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC, RC or INTIOSC modes are used as the primary clock source. When the HFINTOSC is selected as the primary clock, the main system clock can be delayed until the HFINTOSC is stable. This is user selectable by the HFOFST bit of the CONFIG3H Configuration register. When the HFOFST bit is cleared, the main system clock is delayed until the HFINTOSC is stable. When the HFOFST bit is set, the main system clock starts immediately. In either case, the HFIOFS bit of the OSCCON register can be read to determine whether the HFINTOSC is operating and stable.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTOSC with CLKOUT Floating, external resistor may pull high At logic low (clock/4 output) RC with IO Configured as PORTA, bit 6 Floating, external resistor may pull high INTOSC with IO Configured as PORTA, bit 7 Configured as PORTA, bit 6 EC with IO Floating, pulled by external clock Configured as PORTA, bit 6 EC with CLKOUT Floating, pulled by external clock At logic low (clock/4 output) LP, XT, HS Feedback inverter disabled at quiescent voltage level Feedback inverter disabled at quiescent voltage level Note: 2.11 See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. PIC18(L)F2X/4XK22 devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 3.1.2 “Entering Power-Managed Modes”. 2.11.1 SYSTEM CLOCK SELECT (SCS) BITS The System Clock Select (SCS) bits of the OSCCON register select the system clock source that is used for the CPU and peripherals. • When SCS = 00, the system clock source is determined by configuration of the FOSC bits in the CONFIG1H Configuration register. • When SCS = 10, the system clock source is chosen by the internal oscillator frequency selected by the INTSRC bit of the OSCTUNE register, the MFIOSEL bit of the OSCCON2 register and the IRCF bits of the OSCCON register. • When SCS = 01, the system clock source is the 32.768 kHz secondary oscillator shared with Timer1, Timer3 and Timer5.  2010-2021 Microchip Technology Inc. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: 2.11.2 Any automatic clock switch, which may occur from Two-Speed Start-up or FailSafe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the SOSCRUN, MFIOFS and LFIOFS bits of the OSCCON2 register, and the HFIOFS and OSTS bits of the OSCCON register to determine the current system clock source. OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT The Oscillator Start-up Time-out Status (OSTS) bit of the OSCCON register indicates whether the system clock is running from the external clock source, as defined by the FOSC bits in the CONFIG1H Configuration register, or from the internal clock source. In particular, when the primary oscillator is the source of the primary clock, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. DS40001412H-page 39 PIC18(L)F2X/4XK22 2.11.3 CLOCK SWITCH TIMING When switching between one oscillator and another, the new oscillator may not be operating which saves power (see Figure 2-9). If this is the case, there is a delay after the SCS bits of the OSCCON register are modified before the frequency change takes place. The OSTS and IOFS bits of the OSCCON register will reflect the current active status of the external and HFINTOSC oscillators. The timing of a frequency selection is as follows: 1. 2. 3. 4. 5. 6. 7. SCS bits of the OSCCON register are modified. The old clock continues to operate until the new clock is ready. Clock switch circuitry waits for two consecutive rising edges of the old clock after the new clock ready signal goes true. The system clock is held low starting at the next falling edge of the old clock. Clock switch circuitry waits for an additional two rising edges of the new clock. On the next falling edge of the new clock the low hold on the system clock is released and new clock is switched in as the system clock. Clock switch is complete. See Figure 2-1 for more details. If the HFINTOSC is the source of both the old and new frequency, there is no start-up delay before the new frequency is active. This is because the old and new frequencies are derived from the HFINTOSC via the postscaler and multiplexer. Start-up delay specifications are located in Section 27.0 “Electrical Specifications”, under AC Specifications (Oscillator Module). 2.12 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake up from Sleep, perform a few instructions using the HFINTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear. When the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 2.5.1 “Oscillator Start-up Timer (OST)”). The OST will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit of the OSCCON register is set, program execution switches to the external oscillator. 2.12.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is enabled when all of the following settings are configured as noted: • Two-Speed Start-up mode is enabled when the IESO of the CONFIG1H Configuration register is set. • SCS (of the OSCCON register) = 00. • FOSC bits of the CONFIG1H Configuration register are configured for LP, XT or HS mode. Two-Speed Start-up mode becomes active after: • Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or • Wake-up from Sleep. DS40001412H-page 40  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 2.12.2 1. 2. 3. 4. 5. 6. TWO-SPEED START-UP SEQUENCE 2.12.3 Wake-up from Power-on Reset or Sleep. Instructions begin executing by the internal oscillator at the frequency set in the IRCF bits of the OSCCON register. OST enabled to count 1024 external clock cycles. OST timed out. External clock is ready. OSTS is set. Clock switch finishes according to Figure 2-9 FIGURE 2-9: High Speed CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC bits in CONFIG1H Configuration register, or the internal oscillator. OSTS = 0 when the external oscillator is not ready, which indicates that the system is running from the internal oscillator. CLOCK SWITCH TIMING Low Speed Old Clock Start-up Time(1) Clock Sync Running New Clock New Clk Ready IRCF Select Old Select New System Clock Low Speed High Speed Old Clock Start-up Time(1) Clock Sync Running New Clock New Clk Ready IRCF Select Old Select New System Clock Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode.  2010-2021 Microchip Technology Inc. DS40001412H-page 41 PIC18(L)F2X/4XK22 2.13 Fail-Safe Clock Monitor 2.13.3 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating if the external oscillator fails. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the CONFIG1H Configuration register. mayThe FSCM is applicable to all external oscillator modes (LP, XT, HS, EC, RC and RCIO). FIGURE 2-10: FSCM BLOCK DIAGRAM Clock Monitor Latch External Clock S LFINTOSC Oscillator ÷ 64 31 kHz (~32 s) 488 Hz (~2 ms) R 2.13.1 Clock Failure Detected Both of these conditions restart the OST. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device automatically switches over to the external clock source. The Fail-Safe condition need not be cleared before the OSCFIF flag is cleared. RESET OR WAKE-UP FROM SLEEP Note: Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user may check the OSTS bit of the OSCCON register to verify the oscillator start-up and that the system clock switchover has successfully completed. Note: When the device is configured for FailSafe clock monitoring in either HS, XT, or LS Oscillator modes then the IESO configuration bit may also be set so that the clock will automatically switch from the internal clock to the external oscillator when the OST times out. FAIL-SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64 (see Figure 2-10). Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire halfcycle of the sample clock elapses before the primary clock goes low. 2.13.2 • Any Reset • By toggling the SCS1 bit of the OSCCON register The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. Q Sample Clock The Fail-Safe condition is cleared by either one of the following: 2.13.4 Q FAIL-SAFE CONDITION CLEARING FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSCFIF of the PIR2 register. The OSCFIF flag will generate an interrupt if the OSCFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. An automatic transition back to the failed clock source will not occur. The internal clock source chosen by the FSCM is determined by the IRCF bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. DS40001412H-page 42  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 2-11: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: TABLE 2-4: Name INTCON IPR2 OSCCON Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. REGISTERS ASSOCIATED WITH CLOCK SOURCES Bit 7 Bit 6 GIE/GIEH PEIE/GIEL OSCFIP C1IP IDLEN Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 OSTS HFIOFS SCS 30 PRISD MFIOFS LFIOFS 31 IRCF MFIOSEL SOSCGO OSCCON2 PLLRDY SOSCRUN OSCTUNE INTSRC PLLEN PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 — TUN 35 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by clock sources. TABLE 2-5: Name CONFIGURATION REGISTERS ASSOCIATED WITH CLOCK SOURCES Bit 7 Bit 6 Bit 5 CONFIG1H IESO CONFIG2L — — — CONFIG3H MCLRE — P2BMX Bit 4 Bit 3 FCMEN PRICLKEN PLLCFG Bit 1 Bit 0 FOSC BORV T3CMX Bit 2 BOREN Register on Page 345 PWRTEN 346 HFOFST CCP3MX PBADEN CCP2MX 348 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for clock sources.  2010-2021 Microchip Technology Inc. DS40001412H-page 43 PIC18(L)F2X/4XK22 3.0 POWER-MANAGED MODES 3.1.1 The SCS bits allow the selection of one of three clock sources for power-managed modes. They are: PIC18(L)F2X/4XK22 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). • the primary clock, as defined by the FOSC Configuration bits • the secondary clock (the SOSC oscillator) • the internal oscillator block There are three categories of power-managed modes: 3.1.2 • Run modes • Idle modes • Sleep mode ENTERING POWER-MANAGED MODES Switching from one power-managed mode to another begins by loading the OSCCON register. The SCS bits select the clock source and determine which Run or Idle mode is to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. Refer to Section 2.11 “Clock Switching” for more information. These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block). The Sleep mode does not use a clock source. The power-managed modes include several powersaving features offered on previous PIC® microcontroller devices. One of the clock switching features allows the controller to use the secondary oscillator (SOSC) in place of the primary oscillator. Also included is the Sleep mode, offered by all PIC microcontroller devices, where all device clocks are stopped. 3.1 CLOCK SOURCES Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode. Selecting Power-Managed Modes Selecting a power-managed mode requires two decisions: • Whether or not the CPU is to be clocked • The selection of a clock source The IDLEN bit (OSCCON) controls CPU clocking, while the SCS bits (OSCCON) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1. TABLE 3-1: POWER-MANAGED MODES OSCCON Bits Mode (1) IDLEN Module Clocking Available Clock and Oscillator Source SCS CPU Peripherals 0 N/A Off Off PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, RC, EC and Internal Oscillator Block(2). This is the normal full-power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – SOSC Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – SOSC Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Sleep Note 1: 2: None – All clocks are disabled IDLEN reflects its value when the SLEEP instruction is executed. Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source. DS40001412H-page 44  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 3.1.3 MULTIPLE FUNCTIONS OF THE SLEEP COMMAND The power-managed mode that is invoked with the SLEEP instruction is determined by the value of the IDLEN bit at the time the instruction is executed. If IDLEN = 0, when SLEEP is executed, the device enters the Sleep mode and all clocks stop and minimum power is consumed. If IDLEN = 1, when SLEEP is executed, the device enters the IDLE mode and the system clock continues to supply a clock to the peripherals but is disconnected from the CPU. 3.2 Run Modes In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source. 3.2.1 PRI_RUN MODE The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default mode upon a device Reset, unless Two-Speed Start-up is enabled (see Section 2.12 “Two-Speed Clock Start-up Mode” for details). In this mode, the device is operated off the oscillator defined by the FOSC bits of the CONFIG1H Configuration register. 3.2.2 SEC_RUN MODE In SEC_RUN mode, the CPU and peripherals are clocked from the secondary external oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source. SEC_RUN mode is entered by setting the SCS bits to ‘01’. When SEC_RUN mode is active, all of the following are true: • The device clock source is switched to the SOSC oscillator (see Figure 3-1) • The primary oscillator is shut down • The SOSCRUN bit (OSCCON2) is set • The OSTS bit (OSCCON2) is cleared Note: The secondary external oscillator may already be running prior to entering SEC_RUN mode. If the SOSCGO bit or any of the TxSOSCEN bits are not set when the SCS bits are set to ‘01’, entry to SEC_RUN mode will not occur until SOSCGO bit is set and secondary external oscillator is ready. Figure 3-2). When the clock switch is complete, the SOSCRUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up and the SOSC oscillator continues to run. 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer. In this mode, the primary clock is shut down. When using the LFINTOSC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing-sensitive or do not require high-speed clocks at all times. If the primary clock source is the internal oscillator block – either LFINTOSC or INTOSC (MFINTOSC or HFINTOSC) – there are no distinguishable differences between the PRI_RUN and RC_RUN modes during execution. Entering or exiting RC_RUN mode, however, causes a clock switch delay. Therefore, if the primary clock source is the internal oscillator block, using RC_RUN mode is not recommended. This mode is entered by setting the SCS1 bit to ‘1’. To maintain software compatibility with future devices, it is recommended that the SCS0 bit also be cleared, even though the bit is ignored. When the clock source is switched to the INTOSC multiplexer (see Figure 3-1), the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits (OSCCON) may be modified at any time to immediately change the clock speed. When the IRCF bits and the INTSRC bit are all clear, the INTOSC output (HFINTOSC/MFINTOSC) is not enabled and the HFIOFS and MFIOFS bits will remain clear. There will be no indication of the current clock source. The LFINTOSC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, enabling the INTOSC output) or if INTSRC or MFIOSEL is set, then the HFIOFS or MFIOFS bit is set after the INTOSC output becomes stable. For details, see Table 3-2. Clocks to the device continue while the INTOSC source stabilizes after an interval of TIOBST. If the IRCF bits were previously at a non-zero value, or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, then the HFIOFS or MFIOFS bit will remain set. On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the SOSC oscillator, while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see  2010-2021 Microchip Technology Inc. DS40001412H-page 45 PIC18(L)F2X/4XK22 On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-3). When the clock switch is complete, the HFIOFS or MFIOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The LFINTOSC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 SOSCI 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 SOSC OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition(2) CPU Clock Peripheral Clock Program Counter SCS bits Changed PC + 2 PC PC + 4 OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. DS40001412H-page 46  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 3-2: INTERNAL OSCILLATOR FREQUENCY STABILITY BITS IRCF INTSRC MFIOSEL Selected Oscillator Selected Oscillator Stable when: 000 0 x LFINTOSC LFIOFS = 1 000 1 0 HFINTOSC HFIOFS = 1 000 1 1 MFINTOSC MFIOFS = 1 010 or 001 x 0 HFINTOSC HFIOFS = 1 010 or 001 x 1 MFINTOSC MFIOFS = 1 011 – 111 x x HFINTOSC HFIOFS = 1 FIGURE 3-3: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition(2) CPU Clock Peripheral Clock Program Counter PC + 2 PC SCS bits Changed PC + 4 OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC.  2010-2021 Microchip Technology Inc. DS40001412H-page 47 PIC18(L)F2X/4XK22 3.3 Sleep Mode 3.4 The Power-Managed Sleep mode in the PIC18(L)F2X/ 4XK22 devices is identical to the legacy Sleep mode offered in all other PIC microcontroller devices. It is entered by clearing the IDLEN bit of the OSCCON register and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-4) and all clock source Status bits are cleared. Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected by the SCS bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. Entering the Sleep mode from either Run or Idle mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the LFINTOSC source will continue to operate. If the SOSC oscillator is enabled, it will also continue to run. If the WDT is selected, the LFINTOSC source will continue to operate. If the SOSC oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS bits becomes ready (see Figure 3-5), or it will be clocked from the internal oscillator block if either the Two-Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 24.0 “Special Features of the CPU”). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out, or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS bits. FIGURE 3-4: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC DS40001412H-page 48 PC + 2  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 3-5: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 TOST(1) PLL Clock Output TPLL(1) CPU Clock Peripheral Clock Program Counter PC Wake Event PC + 2 PC + 4 PC + 6 OSTS bit set Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 3.4.1 3.4.2 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm-up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then clear the SCS bits and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC Configuration bits. The OSTS bit remains set (see Figure 3-6). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval TCSD is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wakeup, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-7). FIGURE 3-6: SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the SOSC oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS bits to ‘01’ and execute SLEEP. When the clock source is switched to the SOSC oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the SOSCRUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the SOSC oscillator. After an interval of TCSD following the wake event, the CPU begins executing code being clocked by the SOSC oscillator. The IDLEN and SCS bits are not affected by the wake-up; the SOSC oscillator continues to run (see Figure 3-7). Note: The SOSC oscillator may already be running prior to entering SEC_IDLE mode. At least one of the secondary oscillator enable bits (SOSCGO, T1SOSCEN, T3SOSCEN or T5SOSCEN) must be set when the SLEEP instruction is executed. Otherwise, the main system clock will continue to operate in the previously selected mode and the corresponding IDLE mode will be entered (i.e., PRI_IDLE or RC_IDLE). TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q3 Q2 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program Counter PC  2010-2021 Microchip Technology Inc. PC + 2 DS40001412H-page 49 PIC18(L)F2X/4XK22 FIGURE 3-7: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program Counter PC Wake Event 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block from the HFINTOSC multiplexer output. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP. It is recommended that SCS0 also be cleared, although its value is ignored, to maintain software compatibility with future devices. The HFINTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the HFINTOSC multiplexer, the primary oscillator is shut down and the OSTS bit is cleared. Clocks to the peripherals continue while the HFINTOSC source stabilizes. The HFIOFS and MFIOFS bits will remain set if the IRCF bits were previously set at a nonzero value or if INTSRC was set before the SLEEP instruction was executed and the HFINTOSC source was already stable. If the IRCF bits and INTSRC are all clear, the HFINTOSC output will not be enabled, the HFIOFS and MFIOFS bits will remain clear and there will be no indication of the current clock source. When a wake event occurs, the peripherals continue to be clocked from the HFINTOSC multiplexer output. After a delay of TCSD following the wake event, the CPU begins executing code being clocked by the HFINTOSC multiplexer. The IDLEN and SCS bits are not affected by the wake-up. The LFINTOSC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. If the IRCF bits are set to any nonzero value, or either the INTSRC or MFIOSEL bits are set, the HFINTOSC output is enabled. Either the HFIOFS or the MFIOFS bits become set, after the HFINTOSC output stabilizes after an interval of TIOBST. For information on the HFIOFS and MFIOFS bits, see Table 3-2. DS40001412H-page 50  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 3.5 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes is triggered by any one of the following: • an interrupt • a Reset • a Watchdog Time-out This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Section 3.2 “Run Modes”, Section 3.3 “Sleep Mode” and Section 3.4 “Idle Modes”). 3.5.1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit from an Idle mode or the Sleep mode to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. The instruction immediately following the SLEEP instruction is executed on all exits by interrupt from Idle or Sleep modes. Code execution then branches to the interrupt vector if the GIE/GIEH bit of the INTCON register is set, otherwise code execution continues without branching (see Section 9.0 “Interrupts”). A fixed delay of interval TCSD following the wake event is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power-managed mode (see Section 3.2 “Run Modes” and Section 3.3 “Sleep Mode”). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 24.3 “Watchdog Timer (WDT)”). The WDT timer and postscaler are cleared by any one of the following: • executing a SLEEP instruction • executing a CLRWDT instruction • the loss of the currently selected clock source when the Fail-Safe Clock Monitor is enabled • modifying the IRCF bits in the OSCCON register when the internal oscillator block is the device clock source 3.5.3 EXIT BY RESET Exiting Sleep and Idle modes by Reset causes code execution to restart at address ‘0’. See Section 4.0 “Reset” for more details. The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator. 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped and • the primary clock source is not any of the LP, XT, HS or HSPLL modes. In these instances, the primary clock source either does not require an oscillator start-up delay since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC, INTOSC, and INTOSCIO modes). However, a fixed delay of interval TCSD following the wake event is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay.  2010-2021 Microchip Technology Inc. DS40001412H-page 51 PIC18(L)F2X/4XK22 3.6 Selective Peripheral Module Control Idle mode allows users to substantially reduce power consumption by stopping the CPU clock. Even so, peripheral modules still remain clocked, and thus, consume power. There may be cases where the application needs what IDLE mode does not provide: the allocation of power resources to the CPU processing with minimal power consumption from the peripherals. PIC18(L)F2X/4XK22 family devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with control bits in the Peripheral Module Disable (PMD) registers. These bits generically named XXXMD are located in control registers PMD0, PMD1 or PMD2. 3.7 Setting the PMD bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. In this state, power to the control and status registers associated with the peripheral is removed. Writes to these registers have no effect and read values are invalid. Clearing a set PMD bit restores power to the associated control and status registers, thereby setting those registers to their default values. Register Definitions: Peripheral Module Disable REGISTER 3-1: PMD0: PERIPHERAL MODULE DISABLE REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UART2MD: UART2 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 6 UART1MD: UART1 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 5 TMR6MD: Timer6 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 4 TMR5MD: Timer5 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 3 TMR4MD: Timer4 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 2 TMR3MD: Timer3 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 1 TMR2MD: Timer2 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 0 TMR1MD: Timer1 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power DS40001412H-page 52  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 3-2: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 R/W-0 R/W-0 MSSP2MD MSSP1MD U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MSSP2MD: MSSP2 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 6 MSSP1MD: MSSP1 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 5 Unimplemented: Read as ‘0’ bit 4 CCP5MD: CCP5 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 3 CCP4MD: CCP4 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 2 CCP3MD: CCP3 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 1 CCP2MD: CCP2 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 0 CCP1MD: CCP1 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power  2010-2021 Microchip Technology Inc. DS40001412H-page 53 PIC18(L)F2X/4XK22 REGISTER 3-3: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CTMUMD CMP2MD CMP1MD ADCMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 CTMUMD: CTMU Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 2 CMP2MD: Comparator C2 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 1 CMP1MD: Comparator C1 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power bit 0 ADCMD: ADC Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power 0 = Module is enabled, Clock Source is connected, module draws digital power DS40001412H-page 54  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 4.0 RESET The PIC18(L)F2X/4XK22 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section 5.2.0.1 “Stack Full and Underflow Resets”. WDT Resets are covered in Section 24.3 “Watchdog Timer (WDT)”. FIGURE 4-1: A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. 4.1 RCON Register Device Reset events are tracked through the RCON register (Register 4-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 4.7 “Reset State of Registers”. The RCON register also has control bits for setting interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in Section 9.0 “Interrupts”. BOR is covered in Section 4.5 “Brown-out Reset (BOR)”. SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Full/Underflow Reset Stack Pointer External Reset MCLRE MCLR ( )_IDLE Sleep WDT Time-out VDD Detect POR VDD Brown-out Reset BOREN S OST/PWRT OST(2) 1024 Cycles 10-bit Ripple Counter OSC1 32 s LFINTOSC Chip_Reset R Q PWRT(2) 65.5 ms 11-bit Ripple Counter Enable PWRT Enable OST(1) Note 1: 2: See Table 4-2 for time-out situations. PWRT and OST counters are reset by POR and BOR. See Sections 4.4 and 4.5.  2010-2021 Microchip Technology Inc. DS40001412H-page 55 PIC18(L)F2X/4XK22 4.2 Register Definitions: Reset Control REGISTER 4-1: R/W-0/0 IPEN RCON: RESET CONTROL REGISTER R/W-q/u SBOREN (1) U-0 R/W-1/q — RI R-1/q R-1/q TO PD R/W-q/u (2) POR bit 7 R/W-0/q BOR bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets x = Bit is unknown u = unchanged q = depends on condition bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN = 00, 10 or 11: Bit is disabled and read as ‘0’. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware or Power-on Reset) 0 = The RESET instruction was executed causing a device Reset (must be set in firmware after a code-executed Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit(2) 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit(3) 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs) Note 1: 2: 3: When CONFIG2L[2:1] = 01, then the SBOREN Reset state is ‘1’; otherwise, it is ‘0’. The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section 4.7 “Reset State of Registers” for additional information. See Table 4-1. Note 1: Brown-out Reset is indicated when BOR is ‘0’ and POR is ‘1’ (assuming that both POR and BOR were set to ‘1’ by firmware immediately after POR). 2: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. DS40001412H-page 56  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 4.3 Master Clear (MCLR) The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. An internal weak pull-up is enabled when the pin is configured as the MCLR input. FIGURE 4-2: In PIC18(L)F2X/4XK22 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 10.6 “PORTE Registers” for more information. 4.4 D To take advantage of the POR circuitry either leave the pin floating, or tie the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified. For a slow rise time, see Figure 4-2. PIC® MCU R R1 MCLR C Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: 15 k < R < 40 k is recommended to make sure that the voltage drop across R does not violate the device’s electrical specification. 3: R1  1 k will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Power-on Reset (POR) A Power-on Reset pulse is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. VDD VDD The MCLR pin is not driven low by any internal Resets, including the WDT. EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure proper operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit of the RCON register. The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user must manually set the bit to ‘1’ by software following any POR.  2010-2021 Microchip Technology Inc. DS40001412H-page 57 PIC18(L)F2X/4XK22 4.5 Brown-out Reset (BOR) PIC18(L)F2X/4XK22 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV and BOREN bits of the CONFIG2L Configuration register. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV bits. If BOR is enabled (any values of BOREN, except ‘00’), any drop of VDD below VBOR for greater than TBOR will reset the device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay, TPWRT. If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. BOR and the Power-on Timer (PWRT) are independently configured. Enabling BOR Reset does not automatically enable the PWRT. The BOR circuit has an output that feeds into the POR circuit and rearms the POR within the operating range of the BOR. This early rearming of the POR ensures that the device will remain in Reset in the event that VDD falls below the operating range of the BOR circuitry. 4.5.1 DETECTING BOR When BOR is enabled, the BOR bit always resets to ‘0’ on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR and BOR bits are reset to ‘1’ by software immediately after any POR event. If BOR is ‘0’ while POR is ‘1’, it can be reliably assumed that a BOR event has occurred. DS40001412H-page 58 4.5.2 SOFTWARE ENABLED BOR When BOREN = 01, the BOR can be enabled or disabled by the user in software. This is done with the SBOREN control bit of the RCON register. Setting SBOREN enables the BOR to function as previously described. Clearing SBOREN disables the BOR entirely. The SBOREN bit operates only in this mode; otherwise it is read as ‘0’. Placing the BOR under software control gives the user the additional flexibility of tailoring the application to the environment without having to reprogram the device to change BOR configuration. It also allows the user to tailor device power consumption in software by eliminating the incremental current that the BOR consumes. While the BOR current is typically very small, it may have some impact in low-power applications. Note: 4.5.3 Even when BOR is under software control, the BOR Reset voltage level is still set by the BORV Configuration bits. It cannot be changed by software. DISABLING BOR IN SLEEP MODE When BOREN = 10, the BOR remains under hardware control and operates as previously described. Whenever the device enters Sleep mode, however, the BOR is automatically disabled. When the device returns to any other operating mode, BOR is automatically re-enabled. This mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current. 4.5.4 MINIMUM BOR ENABLE TIME Enabling the BOR also enables the Fixed Voltage Reference (FVR) when no other peripheral requiring the FVR is active. The BOR becomes active only after the FVR stabilizes. Therefore, to ensure BOR protection, the FVR settling time must be considered when enabling the BOR in software or when the BOR is automatically enabled after waking from Sleep. If the BOR is disabled, in software or by reentering Sleep before the FVR stabilizes, the BOR circuit will not sense a BOR condition. The FVRST bit of the VREFCON0 register can be used to determine FVR stability.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 4-1: BOR CONFIGURATIONS BOR Configuration BOREN1 BOREN0 Status of SBOREN (RCON) 0 0 Unavailable 0 1 Available BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled by software; operation controlled by SBOREN. 1 0 Unavailable BOR enabled by hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled by hardware; must be disabled by reprogramming the Configuration bits. 4.6 Device Reset Timers PIC18(L)F2X/4XK22 devices incorporate three separate on-chip timers that help regulate the Poweron Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.6.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of PIC18(L)F2X/4XK22 devices is an 11-bit counter which uses the LFINTOSC source as the clock input. This yields an approximate time interval of 2048 x 32 s = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the LFINTOSC clock and will vary from chip-to-chip due to temperature and process variation. The PWRT is enabled by clearing the PWRTEN Configuration bit. 4.6.2 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. 4.6.3 PLL LOCK TIME-OUT With the PLL enabled, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer is used to provide a fixed timeout that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out. 4.6.4 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: 1. 2. After the POR pulse has cleared, PWRT time-out is invoked (if enabled). Then, the OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all depict time-out sequences on power-up, with the Power-up Timer enabled and the device operating in HS Oscillator mode. Figures 4-3 through 4-6 also apply to devices operating in XT or LP modes. For devices in RC mode and with the PWRT disabled, on the other hand, there will be no time-out at all. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire, after which, bringing MCLR high will allow program execution to begin immediately (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC® MCU device operating in parallel. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset, or on exit from all power-managed modes that stop the external oscillator.  2010-2021 Microchip Technology Inc. DS40001412H-page 59 PIC18(L)F2X/4XK22 TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Configuration HSPLL PWRTEN = 1 Exit from Power-Managed Mode 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) PWRTEN = 0 66 ms (1) (2) + 1024 TOSC + 2 ms 66 ms(1) + 1024 TOSC HS, XT, LP 1024 TOSC 1024 TOSC (1) — — RC, RCIO 66 ms(1) — — INTIO1, INTIO2 66 ms(1) — — EC, ECIO 66 ms Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the PLL to lock. FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS40001412H-page 60  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL  2 ms max. First three stages of the PWRT timer.  2010-2021 Microchip Technology Inc. DS40001412H-page 61 PIC18(L)F2X/4XK22 4.7 Reset State of Registers Table 5-2 describes the Reset states for all of the Special Function Registers. The table identifies differences between Power-On Reset (POR)/Brown-Out Reset (BOR) and all other Resets, (i.e., Master Clear, WDT Resets, STKFUL, STKUNF, etc.). Additionally, the table identifies register bits that are changed when the device receives a wake-up from WDT or other interrupts. Some registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. All other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 4-3. These bits are used by software to determine the nature of the Reset. TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program Counter Condition RCON Register SBOREN RI TO PD STKPTR Register POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET Instruction 0000h u(2) 0 u u u u u u 0000h u(2) 1 1 1 u 0 u u MCLR during Power-Managed Run Modes 0000h u(2) u 1 u u u u u MCLR during Power-Managed Idle Modes and Sleep Mode 0000h u(2) u 1 0 u u u u WDT Time-out during Full Power or Power-Managed Run Mode 0000h u(2) u 0 u u u u u MCLR during Full Power Execution 0000h u(2) u u u u u u u Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u Stack Underflow Reset (STVREN = 1) 0000h (2) u u u u u u u 1 Stack Underflow Error (not an actual Reset, STVREN = 0) 0000h u(2) u u u u u u 1 WDT Time-out during PowerManaged Idle or Sleep Modes PC + 2 u(2) u 0 0 u u u u PC + 2(1) u(2) u u 0 u u u u Brown-out Reset Interrupt Exit from PowerManaged Modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is ‘1’ for SBOREN and unchanged for all other Resets when software BOR is enabled (BOREN Configuration bits = 01). Otherwise, the Reset state is ‘0’. TABLE 4-4: Name RCON STKPTR REGISTERS ASSOCIATED WITH RESETS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page IPEN SBOREN — RI TO PD POR BOR 56 STKFUL STKUNF — STKPTR 67 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets. DS40001412H-page 62  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 4-5: CONFIGURATION REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 CONFIG2L — — — CONFIG2H — — Bit 4 Bit 3 BORV Bit 2 BOREN WDPS CONFIG3H MCLRE — P2BMX T3CMX CONFIG4L DEBUG XINST — — Bit 0 Register on Page PWRTEN 346 WDTEN HFOFST CCP3MX — Bit 1 LVP 347 PBADEN CCP2MX 348 — STRVEN 349 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets.  2010-2021 Microchip Technology Inc. DS40001412H-page 63 PIC18(L)F2X/4XK22 5.0 MEMORY ORGANIZATION There are three types of memory in PIC18 Enhanced microcontroller devices: • Program Memory • Data RAM • Data EEPROM As Harvard architecture devices, the data and program memories use separate buses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers. Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 “Flash Program Memory”. Data EEPROM is discussed separately in Section 7.0 “Data EEPROM Memory”. 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). This family of devices contain the following: • PIC18(L)F23K22, PIC18(L)F43K22: 8 Kbytes of Flash Memory, up to 4,096 single-word instructions • PIC18(L)F24K22, PIC18(L)F44K22: 16 Kbytes of Flash Memory, up to 8,192 single-word instructions • PIC18(L)F25K22, PIC18(L)F45K22: 32 Kbytes of Flash Memory, up to 16,384 single-word instructions • PIC18(L)F26K22, PIC18(L)F46K22: 64 Kbytes of Flash Memory, up to 37,768 single-word instructions PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory map for PIC18(L)F2X/4XK22 devices is shown in Figure 5-1. Memory block details are shown in Figure 20-2. DS40001412H-page 64  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18(L)F2X/4XK22 DEVICES PC 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1    Stack Level 31 2000h 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On-Chip Program Memory 3FFFh 4000h PIC18(L)F23K22 PIC18(L)F43K22 On-Chip Program Memory User Memory Space On-Chip Program Memory 1FFFh Reset Vector On-Chip Program Memory PIC18(L)F24K22 PIC18(L)F44K22 7FFFh 8000h PIC18(L)F25K22 PIC18(L)F45K22 Read ‘0’ Read ‘0’ Read ‘0’ FFFFh 10000h PIC18(L)F26K22 PIC18(L)F46K22 Read ‘0’ 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 5.2.2.1 “Computed GOTO”). 1FFFFFh 200000h The PC increments by two to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. 5.1.2 RETURN ADDRESS STACK The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of ‘0’.  2010-2021 Microchip Technology Inc. DS40001412H-page 65 PIC18(L)F2X/4XK22 The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack (TOS) Special File Registers. Data can also be pushed to, or popped from the stack, using these registers. A CALL type instruction causes a push onto the stack; the Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack; the contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to ‘00000’ after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is full or has overflowed or has underflowed. FIGURE 5-2: 5.1.2.1 Top-of-Stack Access Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 5-2). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the Global Interrupt Enable (GIE) bits while accessing the stack to prevent inadvertent stack corruption. RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 Top-of-Stack Registers TOSU 00h TOSH 1Ah 5.1.2.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 5-1) contains the Stack Pointer value, the STKFUL (stack full) Status bit and the STKUNF (Stack Underflow) Status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to Section 24.1 “Configuration Bits” for a description of the device Configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value DS40001412H-page 66 STKPTR 00010 TOSL 34h Top-of-Stack Stack Pointer 001A34h 000D58h 00011 00010 00001 00000 onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 5.1.2.3 PUSH and POP Instructions The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. 5.2 The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. Register Definitions: Stack Pointer REGISTER 5-1: R/C-0 STKPTR: STACK POINTER REGISTER R/C-0 STKFUL(1) STKUNF U-0 (1) R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 STKPTR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack Underflow occurred 0 = Stack Underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 STKPTR: Stack Pointer Location bits Note 1: 5.2.0.1 Bit 7 and bit 6 are cleared by user software or by a POR. Stack Full and Underflow Resets Device Resets on Stack Overflow and Stack Underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 5.2.1 FAST REGISTER STACK A fast register stack is provided for the Status, WREG and BSR registers, to provide a “fast return” option for interrupts. The stack for each register is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the stack registers. The values in the registers are then loaded back into their associated registers if the RETFIE,FAST instruction is used to return from the interrupt.  2010-2021 Microchip Technology Inc. If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. In these cases, users must save the key registers by software during a low priority interrupt. If interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. If no interrupts are used, the fast register stack can be used to restore the Status, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a CALL label, FAST instruction must be executed to save the Status, WREG and BSR registers to the fast register stack. A RETURN, FAST instruction is then executed to restore these registers from the fast register stack. Example 5-1 shows a source code example that uses the fast register stack during a subroutine call and return. DS40001412H-page 67 PIC18(L)F2X/4XK22 EXAMPLE 5-1: CALL SUB1, FAST     RETURN, FAST FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK EXAMPLE 5-2: ORG TABLE SUB1 5.2.2 ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • Computed GOTO • Table Reads 5.2.2.1 Computed GOTO A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 5-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value ‘nn’ to the calling function. 5.2.2.2 MOVF CALL nn00h ADDWF RETLW RETLW RETLW . . . COMPUTED GOTO USING AN OFFSET VALUE OFFSET, W TABLE PCL nnh nnh nnh Table Reads and Table Writes A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. The offset value (in WREG) specifies the number of bytes that the program counter may advance and may be multiples of two (LSb = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. DS40001412H-page 68  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 5.3 PIC18 Instruction Cycle 5.3.1 5.3.2 An “Instruction Cycle” consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 5-3). CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four nonoverlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the instruction register during Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 5-3. FIGURE 5-3: INSTRUCTION FLOW/PIPELINING A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Clock Q3 Q4 PC PC PC + 2 PC + 4 OSC2/CLKOUT (RC mode) Execute INST (PC – 2) Fetch INST (PC) EXAMPLE 5-3: 1. MOVLW 55h 4. BSF TCY0 TCY1 Fetch 1 Execute 1 Fetch 2 SUB_1 PORTA, BIT3 (Forced NOP) 5. Instruction @ address SUB_1 Note: Execute INST (PC + 2) Fetch INST (PC + 4) INSTRUCTION PIPELINE FLOW 2. MOVWF PORTB 3. BRA Execute INST (PC) Fetch INST (PC + 2) TCY2 TCY3 TCY4 TCY5 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.  2010-2021 Microchip Technology Inc. DS40001412H-page 69 PIC18(L)F2X/4XK22 5.3.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as either two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of two and the LSb will always read ‘0’ (see Section 5.1.1 “Program Counter”). Figure 5-4 shows an example of how instruction words are stored in the program memory. FIGURE 5-4: The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC, which accesses the desired byte address in program memory. Instruction #2 in Figure 5-4 shows how the instruction GOTO 0006h is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 25.0 “Instruction Set Summary” provides further details of the instruction set. INSTRUCTIONS IN PROGRAM MEMORY LSB = 1 LSB = 0 0Fh EFh F0h C1h F4h 55h 03h 00h 23h 56h Program Memory Byte Locations  5.3.4 Instruction 1: Instruction 2: MOVLW GOTO 055h 0006h Instruction 3: MOVFF 123h, 456h TWO-WORD INSTRUCTIONS The standard PIC18 instruction set has four two-word instructions: CALL, MOVFF, GOTO and LSFR. In all cases, the second word of the instruction always has ‘1111’ as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. The use of ‘1111’ in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence – immediately after the first word – the data in the second word is accessed and used by the instruction sequence. EXAMPLE 5-4: Word Address  000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 5-4 shows how this works. Note: See Section 5.8 “PIC18 Instruction Execution and the Extended Instruction Set” for information on two-word instructions in the extended instruction set. TWO-WORD INSTRUCTIONS CASE 1: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000 0000 0011 0110 0000 Source Code TSTFSZ REG1 ; is RAM location 0? MOVFF REG1, REG2 ; No, skip this word ; Execute this word as a NOP ADDWF REG3 ; continue code 0000 0011 0110 0000 Source Code TSTFSZ REG1 ; is RAM location 0? MOVFF REG1, REG2 ; Yes, execute this word ; 2nd word of instruction ADDWF REG3 ; continue code CASE 2: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000 DS40001412H-page 70  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 5.4 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 5.7 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each. Figures 5-5 through 5-7 show the data memory organization for the PIC18(L)F2X/4XK22 devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’s application. Any read of an unimplemented location will read as ‘0’s. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the Bank Select Register (BSR). Section 5.4.2 “Access Bank” provides a detailed description of the Access RAM. 5.4.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer. Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (BSR). This SFR holds the 4 Most Significant bits of a location’s address; the instruction itself includes the 8 Least Significant bits. Only the four lower bits of the BSR are implemented (BSR). The upper four bits are unused; they will always read ‘0’ and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory; the eight bits in the instruction show the location in the bank and can be thought of as an offset from the bank’s lower boundary. The relationship between the BSR’s value and the bank division in data memory is shown in Figures 5-5 through 5-7. Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what may be program data to an 8-bit address of F9h while the BSR is 0Fh will end up resetting the program counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory maps in Figures 5-5 through 5-7 indicate which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers.  2010-2021 Microchip Technology Inc. DS40001412H-page 71 PIC18(L)F2X/4XK22 FIGURE 5-5: DATA MEMORY MAP FOR PIC18(L)F23K22 AND PIC18(L)F43K22 DEVICES BSR = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 When ‘a’ = 0: Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 FFh 00h 1FFh 200h FFh 00h 2FFh 300h FFh 00h 3FFh 400h FFh 00h 4FFh 500h FFh 00h 5FFh 600h FFh 00h 6FFh 700h FFh 00h Unused Read 00h FFh 00h AFFh B00h FFh 00h BFFh C00h FFh Bank 13 00h CFFh D00h FFh 00h DFFh E00h Bank 12 Bank 14 FFh 00h Bank 15 Unused SFR(1) EFFh F00h F37h F38h F5Fh F60h SFR FFh DS40001412H-page 72 When ‘a’ = 1: The BSR specifies the Bank used by the instruction. Access Bank Access RAM Low 00h 5Fh Access RAM High 60h (SFRs) FFh 8FFh 900h 9FFh A00h Bank 11 The second 160 bytes are Special Function Registers (from Bank 15). 7FFh 800h FFh 00h FFh 00h Bank 10 The first 96 bytes are general purpose RAM (from Bank 0). GPR Bank 1 Bank 2 The BSR is ignored and the Access Bank is used. 000h 05Fh 060h 0FFh 100h FFFh Note 1: Addresses F38h through F5Fh are also used by SFRs, but are not part of the Access RAM. Users must always use the complete address or load the proper BSR value to access these registers.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 5-6: DATA MEMORY MAP FOR PIC18(L)F24K22 AND PIC18(L)F44K22 DEVICES BSR = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 When ‘a’ = 0: Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 GPR FFh 00h 2FFh 300h FFh 00h 3FFh 400h FFh 00h 4FFh 500h FFh 00h 5FFh 600h FFh 00h 6FFh 700h FFh 00h Unused Read 00h AFFh B00h FFh 00h BFFh C00h FFh Bank 13 00h CFFh D00h FFh 00h DFFh E00h Bank 14 FFh 00h Bank 15 Unused SFR(1) EFFh F00h F37h F38h F5Fh F60h SFR FFh  2010-2021 Microchip Technology Inc. The BSR specifies the Bank used by the instruction. Access Bank Access RAM Low 00h 5Fh Access RAM High 60h (SFRs) FFh 8FFh 900h FFh 00h Bank 12 When ‘a’ = 1: 7FFh 800h FFh 00h 9FFh A00h Bank 11 The second 160 bytes are Special Function Registers (from Bank 15). 1FFh 200h FFh 00h FFh 00h Bank 10 The first 96 bytes are general purpose RAM (from Bank 0). GPR Bank 1 Bank 2 The BSR is ignored and the Access Bank is used. 000h 05Fh 060h 0FFh 100h FFFh Note 1: Addresses F38h through F5Fh are also used by SFRs, but are not part of the Access RAM. Users must always use the complete address or load the proper BSR value to access these registers. DS40001412H-page 73 PIC18(L)F2X/4XK22 FIGURE 5-7: DATA MEMORY MAP FOR PIC18(L)F25K22 AND PIC18(L)F45K22 DEVICES BSR = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 When ‘a’ = 0: Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 Bank 10 GPR FFh 00h 2FFh 300h GPR 4FFh 500h FFh 00h GPR FFh 00h 5FFh 600h FFh 00h 6FFh 700h FFh 00h 7FFh 800h FFh 00h 8FFh 900h FFh 00h Unused Read 00h BFFh C00h FFh Bank 13 00h CFFh D00h FFh 00h DFFh E00h FFh 00h Bank 15 Unused SFR(1) FFh Access Bank Access RAM Low 00h 5Fh Access RAM High 60h (SFRs) FFh 9FFh A00h EFFh F00h F37h F38h F5Fh F60h SFR DS40001412H-page 74 The BSR specifies the Bank used by the instruction. 3FFh 400h FFh 00h FFh 00h Bank 14 When ‘a’ = 1: GPR AFFh B00h Bank 12 The second 160 bytes are Special Function Registers (from Bank 15). 1FFh 200h FFh 00h FFh 00h Bank 11 The first 96 bytes are general purpose RAM (from Bank 0). GPR Bank 1 Bank 2 The BSR is ignored and the Access Bank is used. 000h 05Fh 060h 0FFh 100h FFFh Note 1: Addresses F38h through F5Fh are also used by SFRs, but are not part of the Access RAM. Users must always use the complete address or load the proper BSR value to access these registers.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 5-8: DATA MEMORY MAP FOR PIC18(L)F26K22 AND PIC18(L)F46K22 DEVICES BSR = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 When ‘a’ = 0: Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 The second 160 bytes are Special Function Registers (from Bank 15). 1FFh 200h FFh 00h GPR FFh 00h 2FFh 300h When ‘a’ = 1: The BSR specifies the Bank used by the instruction. GPR 3FFh 400h FFh 00h GPR 4FFh 500h FFh 00h GPR 5FFh 600h FFh 00h GPR FFh 00h Access Bank 6FFh 700h Access RAM Low GPR GPR FFh 00h 00h 5Fh Access RAM High 60h (SFRs) FFh 7FFh 800h FFh 00h 8FFh 900h GPR 9FFh A00h FFh 00h GPR FFh 00h FFh 00h FFh Bank 13 00h Bank 14 The first 96 bytes are general purpose RAM (from Bank 0). GPR Bank 1 Bank 2 The BSR is ignored and the Access Bank is used. 000h 05Fh 060h 0FFh 100h FFh 00h FFh 00h Bank 15 AFFh B00h GPR BFFh C00h GPR CFFh D00h GPR DFFh E00h GPR GPR SFR(1) F00h F37h F38h F5Fh F60h SFR FFh  2010-2021 Microchip Technology Inc. FFFh Note 1: Addresses F38h through F5Fh are also used by SFRs, but are not part of the Access RAM. Users must always use the complete address or load the proper BSR value to access these registers. DS40001412H-page 75 PIC18(L)F2X/4XK22 FIGURE 5-9: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 Bank Select(2) 0 0 0 1 1 000h Data Memory 00h Bank 0 100h Bank 1 200h 300h Bank 2 FFh 00h From Opcode(2) 7 1 1 1 1 1 1 0 1 1 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR) to the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction. DS40001412H-page 76  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 5.4.2 ACCESS BANK While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of memory (60h-FFh) in Block 15. The lower half is known as the “Access RAM” and is composed of GPRs. This upper half is also where the device’s SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figures 5-5 through 5-7). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. 5.4.3 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area. This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. 5.4.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top portion of Bank 15 (F38h to FFFh). A list of these registers is given in Table 5-1 and Table 5-2. The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and interrupt registers are described in their respective chapters, while the ALU’s STATUS register is described later in this section. Registers related to the operation of a peripheral feature are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as ‘0’s. Using this “forced” addressing allows the instruction to operate on a data address in a single cycle, without updating the BSR first. For 8-bit addresses of 60h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 5.7.3 “Mapping the Access Bank in Indexed Literal Offset Mode”.  2010-2021 Microchip Technology Inc. DS40001412H-page 77 PIC18(L)F2X/4XK22 TABLE 5-1: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F2X/4XK22 DEVICES Name Address Name Address Name Address Name Address Name FFFh TOSU FD7h TMR0H FAFh SPBRG1 F87h —(2) F5Fh CCPR3H FFEh TOSH FD6h TMR0L FAEh RCREG1 F86h —(2) F5Eh CCPR3L (2) F5Dh CCP3CON F5Ch PWM3CON — FFDh TOSL FD5h T0CON FADh TXREG1 F85h FFCh STKPTR FD4h —(2) FACh TXSTA1 F84h PORTE FFBh PCLATU FD3h OSCCON FABh RCSTA1 F83h PORTD(3) F5Bh ECCP3AS FFAh PCLATH FD2h OSCCON2 FAAh EEADRH(4) F82h PORTC F5Ah PSTR3CON FF9h PCL FD1h WDTCON FA9h EEADR F81h PORTB F59h CCPR4H FF8h TBLPTRU FD0h RCON FA8h EEDATA F80h PORTA F58h CCPR4L FF7h TBLPTRH FCFh TMR1H FA7h EECON2(1) F7Fh IPR5 F57h CCP4CON FF6h TBLPTRL FCEh TMR1L FA6h EECON1 F7Eh PIR5 F56h CCPR5H FF5h TABLAT FCDh T1CON FA5h IPR3 F7Dh PIE5 F55h CCPR5L FF4h PRODH FCCh T1GCON FA4h PIR3 F7Ch IPR4 F54h CCP5CON FF3h PRODL FCBh SSP1CON3 FA3h PIE3 F7Bh PIR4 F53h TMR4 FF2h INTCON FCAh SSP1MSK FA2h IPR2 F7Ah PIE4 F52h PR4 FF1h INTCON2 FC9h SSP1BUF FA1h PIR2 F79h CM1CON0 F51h T4CON FF0h INTCON3 FC8h SSP1ADD FA0h PIE2 F78h CM2CON0 F50h TMR5H FEFh INDF0(1) FC7h SSP1STAT F9Fh IPR1 F77h CM2CON1 F4Fh TMR5L FEEh POSTINC0(1) FC6h SSP1CON1 F9Eh PIR1 F76h SPBRGH2 F4Eh T5CON FEDh POSTDEC0(1) FC5h SSP1CON2 F9Dh PIE1 F75h SPBRG2 F4Dh T5GCON FECh PREINC0(1) FC4h ADRESH F9Ch HLVDCON F74h RCREG2 F4Ch TMR6 FEBh PLUSW0(1) FC3h ADRESL F9Bh OSCTUNE F73h TXREG2 F4Bh PR6 FEAh FSR0H FC2h ADCON0 F9Ah —(2) F72h TXSTA2 F4Ah T6CON FE9h FSR0L FC1h ADCON1 F99h —(2) F71h RCSTA2 F49h CCPTMRS0 FE8h WREG FC0h ADCON2 F98h —(2) F70h BAUDCON2 F48h CCPTMRS1 FE7h INDF1(1) FBFh CCPR1H F97h —(2) F6Fh SSP2BUF F47h SRCON0 FE6h POSTINC1(1) FBEh CCPR1L F96h TRISE F6Eh SSP2ADD F46h SRCON1 FE5h POSTDEC1(1) FBDh CCP1CON F95h TRISD(3) F6Dh SSP2STAT F45h CTMUCONH FE4h PREINC1(1) FBCh TMR2 F94h TRISC F6Ch SSP2CON1 F44h CTMUCONL FE3h PLUSW1(1) FBBh PR2 F93h TRISB F6Bh SSP2CON2 F43h CTMUICON FE2h FSR1H FBAh T2CON F92h TRISA F6Ah SSP2MSK F42h VREFCON0 FE1h FSR1L FB9h PSTR1CON F91h —(2) F69h SSP2CON3 F41h VREFCON1 FE0h BSR FB8h BAUDCON1 F90h —(2) F68h CCPR2H F40h VREFCON2 FDFh INDF2(1) FB7h PWM1CON F8Fh —(2) F67h CCPR2L F3Fh PMD0 FB6h F8Eh —(2) F66h CCP2CON F3Eh PMD1 F8Dh (3) LATE F65h PWM2CON F3Dh PMD2 F8Ch LATD(3) F64h ECCP2AS F3Ch ANSELE FDEh POSTINC2(1) FDDh POSTDEC2 (1) FDCh PREINC2(1) FDBh FDAh FB5h ECCP1AS — (2) FB4h T3GCON PLUSW2(1) FB3h TMR3H F8Bh LATC F63h PSTR2CON F3Bh ANSELD FSR2H FB2h TMR3L F8Ah LATB F62h IOCB F3Ah ANSELC FD9h FSR2L FB1h T3CON F89h LATA F61h WPUB F39h ANSELB FD8h STATUS FB0h SPBRGH1 F88h —(2) F60h SLRCON F38h ANSELA Note 1: 2: 3: 4: This is not a physical register. Unimplemented registers are read as ‘0’. PIC18(L)F4XK22 devices only. PIC18(L)F26K22 and PIC18(L)F46K22 devices only. DS40001412H-page 78  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 5-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES Name Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FFFh TOSU FFEh TOSH Top-of-Stack, High Byte (TOS) 0000 0000 FFDh TOSL Top-of-Stack, Low Byte (TOS) 0000 0000 FFCh STKPTR STKFUL STKUNF — STKPTR 00-0 0000 FFBh PCLATU — — — Holding Register for PC ---0 0000 FFAh PCLATH Holding Register for PC FF9h PCL Holding Register for PC FF8h TBLPTRU FF7h TBLPTRH Program Memory Table Pointer High Byte(TBLPTR) 0000 0000 FF6h TBLPTRL Program Memory Table Pointer Low Byte(TBLPTR) 0000 0000 FF5h TABLAT Program Memory Table Latch 0000 0000 FF4h PRODH Product Register, High Byte xxxx xxxx FF3h PRODL Product Register, Low Byte FF2h INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF FF1h INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 FF0h INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 FEFh INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) ---- ---- FEEh POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) ---- ---- FEDh POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) ---- ---- FECh PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) ---- ---- FEBh PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value of FSR0 offset by W ---- ---- — Top-of-Stack, Upper Byte (TOS) Value on POR, BOR — ---0 0000 0000 0000 0000 0000 Program Memory Table Pointer Upper Byte(TBLPTR) --00 0000 xxxx xxxx 0000 000x FEAh FSR0H FE9h FSR0L FE8h WREG FE7h INDF1 FE6h POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) ---- ---- FE5h POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) ---- ---- FE4h PREINC1 FE3h PLUSW1 FE2h FSR1H FE1h FSR1L FE0h BSR — FDFh INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) FDEh POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) ---- ---- FDDh POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) ---- ---- FDCh PREINC2 FDBh PLUSW2 FDAh FSR2H FD9h FSR2L FD8h STATUS FD7h TMR0H Timer0 Register, High Byte FD6h TMR0L Timer0 Register, Low Byte FD5h T0CON FD3h OSCCON IDLEN FD2h OSCCON2 PLLRDY Legend: Note 1: 2: 3: 4: — — — — Indirect Data Memory Address Pointer 0, High Byte Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx Working Register xxxx xxxx Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value of FSR1 offset by W — — — — Indirect Data Memory Address Pointer 1, High Byte Indirect Data Memory Address Pointer 1, Low Byte — — ---- 0000 — ---- ---- ---- ------- ------- 0000 xxxx xxxx Bank Select Register ---- 0000 ---- ---- Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) ---- ---Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of FSR2 offset by W — — — — Indirect Data Memory Address Pointer 2, High Byte Indirect Data Memory Address Pointer 2, Low Byte — TMR0ON — T08BIT — T0CS N T0SE IRCF SOSCRUN — MFIOSEL OV Z ---- ------- 0000 xxxx xxxx DC C ---x xxxx 0000 0000 xxxx xxxx PSA T0PS OSTS HFIOFS SOSCGO PRISD 1111 1111 SCS MFIOFS LFIOFS 0011 q000 00-0 01x0 x = unknown, u = unchanged, — = unimplemented, q = value depends on condition PIC18(L)F4XK22 devices only. PIC18(L)F2XK22 devices only. PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only. PIC18(L)F26K22 and PIC18(L)F46K22 devices only.  2010-2021 Microchip Technology Inc. DS40001412H-page 79 PIC18(L)F2X/4XK22 TABLE 5-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — — — — — IPEN SBOREN — RI TO Bit 2 Bit 0 — — SWDTEN ---- ---0 PD POR BOR 01-1 1100 FD1h WDTCON FD0h RCON FCFh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register FCEh TMR1L Least Significant Byte of the 16-bit TMR1 Register FCDh T1CON FCCh T1GCON TMR1GE T1GPOL T1GTM FCBh SSP1CON3 ACKTIM PCIE SCIE FCAh SSP1MSK SSP1 MASK Register bits FC9h SSP1BUF SSP1 Receive Buffer/Transmit Register FC8h SSP1ADD FC7h SSP1STAT SMP CKE D/A P FC6h SSP1CON1 WCOL SSPOV SSPEN CKP FC5h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN FC4h ADRESH A/D Result, High Byte FC3h ADRESL A/D Result, Low Byte FC2h ADCON0 — FC1h ADCON1 TRIGSEL — FC0h ADCON2 ADFM — TMR1CS T1CKPS T1SOSCEN T1SYNC T1GSPM T1GGO/ DONE T1GVAL BOEN SDAHT SBCDE xxxx xxxx xxxx xxxx T1RD16 TMR1ON T1GSS AHEN DHEN xxxx xxxx R/W PEN UA BF RSEN SEN 0000 0000 0000 0000 xxxx xxxx GO/DONE — 0000 0000 xxxx xxxx CHS — 0000 0000 0000 0000 SSPM RCEN 0000 0000 0000 xx00 1111 1111 SSP1 Address Register in I2C Client Mode. SSP1 Baud Rate Reload Register in I2C Host Mode S Value on POR, BOR Bit 1 PVCFG ADON NVCFG ACQT ADCS --00 0000 0--- 0000 0-00 0000 FBFh CCPR1H Capture/Compare/PWM Register 1, High Byte xxxx xxxx FBEh CCPR1L Capture/Compare/PWM Register 1, Low Byte xxxx xxxx FBDh CCP1CON FBCh TMR2 FBBh PR2 FBAh T2CON — FB9h PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 FB8h BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 0100 0-00 P1M DC1B CCP1M 0000 0000 Timer2 Register 0000 0000 Timer2 Period Register T2OUTPS 1111 1111 TMR2ON T2CKPS FB7h PWM1CON P1RSEN FB6h ECCP1AS CCP1ASE FB4h T3GCON TMR3GE FB3h TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register FB2h TMR3L Least Significant Byte of the 16-bit TMR3 Register FB1h T3CON FB0h SPBRGH1 EUSART1 Baud Rate Generator, High Byte 0000 0000 FAFh SPBRG1 EUSART1 Baud Rate Generator, Low Byte 0000 0000 FAEh RCREG1 EUSART1 Receive Register 0000 0000 FADh TXREG1 EUSART1 Transmit Register FACh TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D FABh RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D FAAh EEADRH(5) — — — — — — FA9h EEADR FA8h EEDATA EEPROM Data Register FA7h EECON2 EEPROM Control Register 2 (not a physical register) FA6h EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 FA5h IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 0000 0000 FA4h PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 0000 0000 FA3h PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 0000 0000 Legend: Note 1: 2: 3: 4: P1DC -000 0000 CCP1AS T3GPOL TMR3CS T3GTM 0000 0000 PSS1AC T3GSPM T3CKPS T3GGO/ DONE T3SOSCEN PSS1BD 0000 0000 T3GSS 0000 0x00 T3GVAL T3SYNC xxxx xxxx xxxx xxxx T3RD16 TMR3ON 0000 0000 0000 0000 EEADR EEADR 0000 0010 0000 000x ---- --00 0000 0000 0000 0000 ---- --00 x = unknown, u = unchanged, — = unimplemented, q = value depends on condition PIC18(L)F4XK22 devices only. PIC18(L)F2XK22 devices only. PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only. PIC18(L)F26K22 and PIC18(L)F46K22 devices only. DS40001412H-page 80  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 5-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR FA2h IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 1111 1111 FA1h PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 0000 0000 FA0h PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 0000 0000 F9Fh IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP -111 1111 F9Eh PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF -000 0000 F9Dh PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE -000 0000 F9Ch HLVDCON VDIRMAG BGVST IRVST HLVDEN F9Bh OSCTUNE INTSRC PLLEN F96h TRISE WPUE3 — F95h TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 F94h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 F93h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 F92h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 HLVDL 0000 0000 TUN — — — 00xx xxxx TRISE2(1) TRISE1(1) TRISE0(1) 1--- -111 TRISD1 TRISD0 1111 1111 TRISC1 TRISC0 1111 1111 F8Dh LATE(1) — — — — — LATE2 LATE1 LATE0 ---- -xxx F8Ch LATD(1) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx F8Bh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx F8Ah LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx F89h LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx PORTE(2) — — — — RE3 — — — ---- x--- PORTE(1) — — — — RE3 RE2 RE1 RE0 ---- x000 F84h F83h PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000 F82h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 0000 00xx F81h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxx0 0000 F80h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 F7Fh IPR5 — — — — — TMR6IP TMR5IP TMR4IP ---- -111 F7Eh PIR5 — — — — — TMR6IF TMR5IF TMR4IF ---- -111 F7Dh PIE5 — — — — — TMR6IE TMR5IE TMR4IE ---- -000 F7Ch IPR4 — — — — — CCP5IP CCP4IP CCP3IP ---- -000 F7Bh PIR4 — — — — — CCP5IF CCP4IF CCP3IF ---- -000 F7Ah PIE4 — — — — — CCP5IE CCP4IE CCP3IE ---- -000 F79h CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH 0000 1000 F78h CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH 0000 1000 F77h CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS F76h SPBRGH2 EUSART2 Baud Rate Generator, High Byte 0000 0000 F75h SPBRG2 EUSART2 Baud Rate Generator, Low Byte 0000 0000 F74h RCREG2 EUSART2 Receive Register 0000 0000 F73h TXREG2 EUSART2 Transmit Register F72h TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 F71h RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x F70h BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 01x0 0-00 F6Fh SSP2BUF F6Eh SSP2ADD SSP2 Address Register in I2C Client Mode. SSP2 Baud Rate Reload Register in I 2C Host Mode F6Dh SSP2STAT SMP CKE D/A P F6Ch SSP2CON1 WCOL SSPOV SSPEN CKP F6Bh SSP2CON2 GCEN ACKSTAT ACKDT ACKEN F6Ah SSP2MSK F69h SSP2CON3 Legend: Note 1: 2: 3: 4: C1SYNC C2SYNC 0000 0000 SSP2 Receive Buffer/Transmit Register S xxxx xxxx R/W 0000 0000 UA BF PEN RSEN SEN SBCDE AHEN DHEN SSPM RCEN PCIE SCIE BOEN SDAHT 0000 0000 0000 0000 SSP1 MASK Register bits ACKTIM 0000 0000 0000 0000 1111 1111 0000 0000 x = unknown, u = unchanged, — = unimplemented, q = value depends on condition PIC18(L)F4XK22 devices only. PIC18(L)F2XK22 devices only. PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only. PIC18(L)F26K22 and PIC18(L)F46K22 devices only.  2010-2021 Microchip Technology Inc. DS40001412H-page 81 PIC18(L)F2X/4XK22 TABLE 5-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 F68h CCPR2H Capture/Compare/PWM Register 2, High Byte F67h CCPR2L Capture/Compare/PWM Register 2, Low Byte F66h CCP2CON F65h PWM2CON P2RSEN F64h ECCP2AS CCP2ASE F63h PSTR2CON F62h F61h P2M DC2B Bit 1 Bit 0 xxxx xxxx xxxx xxxx CCP2M 0000 0000 P2DC CCP2AS Value on POR, BOR 0000 0000 PSS2AC PSS2BD 0000 0000 — — — STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 1111 ---- WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 F60h SLRCON(2) — — — — — SLRC SLRB SLRA ---- -111 SLRCON(1) — — — SLRE SLRD SLRC SLRB SLRA F5Fh CCPR3H F5Eh CCPR3L F5Dh CCP3CON F5Ch PWM3CON P3RSEN F5Bh ECCP3AS CCP3ASE F5Ah PSTR3CON F59h CCPR4H F58h CCPR4L F57h CCP4CON xxxx xxxx Capture/Compare/PWM Register 3, Low Byte xxxx xxxx P3M — DC3B CCP3M 0000 0000 P3DC CCP3AS — — 0000 0000 PSS3AC STR3SYNC STR3D PSS3BD STR3C STR3B STR3A Capture/Compare/PWM Register 4, High Byte — DC4B 0000 0000 ---0 0001 xxxx xxxx Capture/Compare/PWM Register 4, Low Byte — ---1 1111 Capture/Compare/PWM Register 3, High Byte xxxx xxxx CCP4M --00 0000 F56h CCPR5H Capture/Compare/PWM Register 5, High Byte xxxx xxxx F55h CCPR5L Capture/Compare/PWM Register 5, Low Byte xxxx xxxx F54h CCP5CON F53h TMR4 F52h PR4 F51h T4CON F50h TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register F4Fh TMR5L Least Significant Byte of the 16-bit TMR5 Register F4Eh T5CON F4Dh T5GCON F4Ch TMR6 Timer6 Register F4Bh PR6 Timer6 Period Register F4Ah T6CON F49h CCPTMRS0 — — DC5B CCP5M --00 0000 Timer4 Register 0000 0000 Timer4 Period Register — TMR5CS TMR5GE T5GPOL — T5CKPS T5GTM TMR4ON T5SOSCEN T5SYNC T5GGO/ DONE T5GVAL T5GSPM — CCPTMRS1 F47h SRCON0 SRLEN F46h SRCON1 SRSPE SRSCKE SRSC2E F45h CTMUCONH CTMUEN — CTMUSIDL F44h CTMUCONL EDG2POL EDG2SEL F43h CTMUICON F42h VREFCON0 FVREN FVRST F41h VREFCON1 DACEN DACLPS F40h VREFCON2 — — — F3Fh PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD F3Eh PMD1 MSSP2MD MSSP1MD — CCP5MD F3Dh PMD2 — — — — — — SRCLK 0000 0000 0000 0000 T5RD16 TMR5ON T5GSS 0000 0000 0000 0x00 TMR6ON T6CKPS -000 0000 — C1TSEL 00-0 0-00 C4TSEL ---- 0000 C5TSEL SRQEN SRNQEN SRPS SRPR SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 0000 0000 EDG1POL EDG1SEL FVRS — — — 0000 0000 EDG2STAT EDG1STAT 0000 0000 IRNG 0000 0000 ITRIM DACOE -000 0000 1111 1111 C2TSEL F48h — T4CKPS 0000 0000 T6OUTPS C3TSEL — 1111 1111 T4OUTPS — — 0001 ---- — DACNSS 000- 00-0 TMR3MD TMR2MD TMR1MD CCP4MD CCP3MD CCP2MD CCP1MD 00-0 0000 CTMUMD CMP2MD CMP1MD ADCMD ---- 0000 DACPSS DACR ---0 0000 0000 0000 F3Ch ANSELE(1) — — — — — ANSE2 ANSE1 ANSE0 ---- -111 F3Bh ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition PIC18(L)F4XK22 devices only. PIC18(L)F2XK22 devices only. PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only. PIC18(L)F26K22 and PIC18(L)F46K22 devices only. DS40001412H-page 82  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 5-2: Address Name REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR F3Ah ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 1111 11-- F39h ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 F38h ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111 Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition PIC18(L)F4XK22 devices only. PIC18(L)F2XK22 devices only. PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only. PIC18(L)F26K22 and PIC18(L)F46K22 devices only.  2010-2021 Microchip Technology Inc. DS40001412H-page 83 PIC18(L)F2X/4XK22 5.4.5 STATUS REGISTER The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed. Therefore, the result of an instruction with the STATUS register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’). 5.5 It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions that do not affect Status bits, see the instruction set summaries in Section 25.2 “Extended Instruction Set” and Table 25-3. Note: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. Register Definitions: Status REGISTER 5-2: U-0 STATUS: STATUS REGISTER U-0 — — U-0 — R/W-x N R/W-x OV R/W-x R/W-x R/W-x (1) Z DC bit 7 C(1) bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (two’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. DS40001412H-page 84  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 5.6 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.7 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: • • • • Inherent Literal Direct Indirect An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section 5.7.1 “Indexed Addressing with Literal Offset”. 5.6.1 INHERENT AND LITERAL ADDRESSING Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address. 5.6.2 Purpose Register File”) or a location in the Access Bank (Section 5.4.2 “Access Bank”) as the data source for the instruction. The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.4.1 “Bank Select Register (BSR)”) are used with the address to determine the complete 12-bit address of the register. When ‘a’ is ‘0’, the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely. The destination of the operation’s results is determined by the destination bit ‘d’. When ‘d’ is ‘1’, the results are stored back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results are stored in the W register. Instructions without the ‘d’ argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register. 5.6.3 INDIRECT ADDRESSING Indirect addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations which are to be read or written. Since the FSRs are themselves located in RAM as Special File Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. The registers for indirect addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using loops, such as the example of clearing an entire RAM bank in Example 5-5. EXAMPLE 5-5: DIRECT ADDRESSING LFSR CLRF Direct addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. NEXT In the core PIC18 instruction set, bit-oriented and byteoriented instructions use some version of direct addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.4.3 “General BRA CONTINUE  2010-2021 Microchip Technology Inc. BTFSS HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING FSR0, 100h ; POSTINC0 ; Clear INDF ; register then ; inc pointer FSR0H, 1 ; All done with ; Bank1? NEXT ; NO, clear next ; YES, continue DS40001412H-page 85 PIC18(L)F2X/4XK22 5.6.3.1 FSR Registers and the INDF Operand 5.6.3.2 At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. Each FSR pair holds a 12-bit value, therefore, the four upper bits of the FSRnH register are not used. The 12-bit FSR value can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers which cannot be directly read or written. Accessing these registers actually accesses the location to which the associated FSR register pair points, and also performs a specific action on the FSR value. They are: • POSTDEC: accesses the location to which the FSR points, then automatically decrements the FSR by 1 afterwards • POSTINC: accesses the location to which the FSR points, then automatically increments the FSR by 1 afterwards • PREINC: automatically increments the FSR by one, then uses the location to which the FSR points in the operation • PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the location to which the result points in the operation. Indirect addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can be thought of as “virtual” registers: they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target. The INDF operand is just a convenient way of using the pointer. Because indirect addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. FIGURE 5-10: FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In this context, accessing an INDF register uses the value in the associated FSR register without changing it. Similarly, accessing a PLUSW register gives the FSR value an offset by that in the W register; however, neither W nor the FSR is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR register. INDIRECT ADDRESSING 000h Using an instruction with one of the indirect addressing registers as the operand.... Bank 0 ADDWF, INDF1, 1 100h Bank 1 200h ...uses the 12-bit address stored in the FSR pair associated with that register.... 300h FSR1H:FSR1L 7 0 x x x x 1 1 1 0 7 0 Bank 2 Bank 3 through Bank 13 1 1 0 0 1 1 0 0 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. E00h Bank 14 F00h FFFh Bank 15 Data Memory DS40001412H-page 86  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of indexed addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 5.6.3.3 Operations by FSRs on FSRs Indirect addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to either the INDF2 or POSTDEC2 register will write the same value to the FSR2H:FSR2L. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users may proceed cautiously when working on these registers, particularly if their code uses indirect addressing. Similarly, operations by indirect addressing are generally permitted on all other SFRs. Users may exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 5.7 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different; this is due to the introduction of a new addressing mode for the data memory space. 5.7.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of indirect addressing using the FSR2 register pair within Access RAM. Under the proper conditions, instructions that use the Access Bank – that is, most bit-oriented and byte-oriented instructions – can invoke a form of indexed addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. When using the extended instruction set, this addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0) and • The file address argument is less than or equal to 5Fh. Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in direct addressing), or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer, specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. 5.7.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructions that can use direct addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the Access Bank (Access RAM bit is ‘1’), or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible addressing modes when the extended instruction set is enabled is shown in Figure 5-11. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode may note the changes to assembler syntax for this mode. This is described in more detail in Section 25.2.1 “Extended Instruction Syntax”. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged.  2010-2021 Microchip Technology Inc. DS40001412H-page 87 PIC18(L)F2X/4XK22 FIGURE 5-11: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When ‘a’ = 0 and f  60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 60h are not available in this addressing mode. 000h 060h Bank 0 100h 00h Bank 1 through Bank 14 60h Valid range for ‘f’ Access RAM F00h FFh Bank 15 F60h SFRs FFFh When ‘a’ = 0 and f5Fh: The instruction executes in Indexed Literal Offset mode. ‘f’ is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. Note that in this mode, the correct syntax is now: ADDWF [k], d where ‘k’ is the same as ‘f’. When ‘a’ = 1 (all values of f): The instruction executes in Direct mode (also known as Direct Long mode). ‘f’ is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. Data Memory 000h 060h Bank 0 100h 001001da ffffffff Bank 1 through Bank 14 FSR2H FSR2L F00h Bank 15 F60h SFRs FFFh Data Memory BSR 00000000 000h 060h Bank 0 100h Bank 1 through Bank 14 001001da ffffffff F00h Bank 15 F60h SFRs FFFh DS40001412H-page 88 Data Memory  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 5.7.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom section of Bank 0, this mode maps the contents from a user defined “window” that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section 5.4.2 “Access Bank”). An example of Access Bank remapping in this addressing mode is shown in Figure 5-12. FIGURE 5-12: Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before. 5.8 PIC18 Instruction Execution and the Extended Instruction Set Enabling the extended instruction set adds eight additional commands to the existing PIC18 instruction set. These instructions are executed as described in Section 25.2 “Extended Instruction Set”. REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: ADDWF f, d, a FSR2H:FSR2L = 120h Locations in the region from the FSR2 pointer (120h) to the pointer plus 05Fh (17Fh) are mapped to the bottom of the Access RAM (000h-05Fh). 000h Bank 0 100h 120h 17Fh 200h Bank 1 Window Bank 1 00h Bank 1 “Window” 5Fh 60h Special File Registers at F60h through FFFh are mapped to 60h through FFh, as usual. Bank 2 through Bank 14 Bank 0 addresses below 5Fh can still be addressed by using the BSR. SFRs FFh Access Bank F00h Bank 15 F60h FFFh SFRs Data Memory  2010-2021 Microchip Technology Inc. DS40001412H-page 89 PIC18(L)F2X/4XK22 6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation cannot be issued from user code. • Table Read (TBLRD) • Table Write (TBLWT) Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). The table read operation retrieves one byte of data directly from program memory and places it into the TABLAT register. Figure 6-1 shows the operation of a table read. The table write operation stores one byte of data from the TABLAT register into a write block holding register. The procedure to write the contents of the holding registers into program memory is detailed in Section 6.6 “Writing to Flash Program Memory”. Figure 6-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. Tables containing data, rather than program instructions, are not required to be word aligned. Therefore, a table can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned. FIGURE 6-1: TABLE READ OPERATION Instruction: TBLRD* Program Memory Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. DS40001412H-page 90  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Table Pointer(1) TBLPTRU TBLPTRH Holding Registers Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL actually point to an address within the write block holding registers. The MSBs of the Table Pointer determine where the write block will eventually be written. The process for writing the holding registers to the program memory array is discussed in Section 6.6 “Writing to Flash Program Memory”. 6.2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: • • • • EECON1 register EECON2 register TABLAT register TBLPTR registers 6.2.1 EECON1 AND EECON2 REGISTERS The EECON1 register (Register 6-1) is the control register for memory accesses. The EECON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s. The EEPGD control bit determines if the access will be a program or data EEPROM memory access. When EEPGD is clear, any subsequent operations will operate on the data EEPROM memory. When EEPGD is set, any subsequent operations will operate on the program memory. The CFGS control bit determines if the access will be to the Configuration/Calibration registers or to program memory/data EEPROM memory. When CFGS is set, subsequent operations will operate on Configuration registers regardless of EEPGD (see Section 24.0 “Special Features of the CPU”). When CFGS is clear, memory selection access is determined by EEPGD.  2010-2021 Microchip Technology Inc. The FREE bit allows the program memory erase operation. When FREE is set, an erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit, when set, will allow a write operation. The WREN bit is clear on power-up. The WRERR bit is set by hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete. Note: During normal operation, the WRERR is read as ‘1’. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. The WR control bit initiates write operations. The WR bit cannot be cleared, only set, by firmware. Then WR bit is cleared by hardware at the completion of the write operation. Note: The EEIF interrupt flag bit of the PIR2 register is set when the write is complete. The EEIF flag stays set until cleared by firmware. DS40001412H-page 91 PIC18(L)F2X/4XK22 6.3 Register Definitions: Memory Control REGISTER 6-1: R/W-x EEPGD EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row (Block) Erase Enable bit 1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) by software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS40001412H-page 92  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 6.3.1 TABLAT – TABLE LATCH REGISTER When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory directly into the TABLAT register. The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.3.2 When a TBLWT is executed the byte in the TABLAT register is written, not to Flash memory but, to a holding register in preparation for a program memory write. The holding registers constitute a write block which varies depending on the device (see Table 6-1).The 3, 4, or 5 LSbs of the TBLPTRL register determine which specific address within the holding register block is written to. The MSBs of the Table Pointer have no effect during TBLWT operations. TBLPTR – TABLE POINTER REGISTER The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the device ID, the user ID and the Configuration bits. When a program memory write is executed the entire holding register block is written to the Flash memory at the address determined by the MSbs of the TBLPTR. The 3, 4, or 5 LSBs are ignored during Flash memory writes. For more details, see Section 6.6 “Writing to Flash Program Memory”. When an erase of program memory is executed, the 16 MSbs of the Table Pointer register (TBLPTR) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR) are ignored. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations on the TBLPTR affect only the low-order 21 bits. 6.3.3 Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. TABLE POINTER BOUNDARIES TBLPTR is used in reads, writes and erases of the Flash program memory. TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLWT* TBLPTR is not modified TBLRD*+ TBLWT*+ TBLPTR is incremented after the read/write TBLRD*TBLWT*- TBLPTR is decremented after the read/write TBLRD+* TBLWT+* TBLPTR is incremented before the read/write FIGURE 6-3: 21 TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU 16 15 TBLPTRH 8 TABLE ERASE/WRITE TBLPTR(1) 7 TBLPTRL 0 TABLE WRITE TBLPTR(1) TABLE READ – TBLPTR Note 1: n = 6 for block sizes of 64 bytes.  2010-2021 Microchip Technology Inc. DS40001412H-page 93 PIC18(L)F2X/4XK22 6.4 Reading the Flash Program Memory The TBLRD instruction retrieves data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 Instruction Register (IR) EXAMPLE 6-1: FETCH TBLPTR = xxxxx0 TABLAT Read Register TBLRD READING A FLASH PROGRAM MEMORY WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word READ_WORD TBLRD*+ MOVF MOVWF TBLRD*+ MOVFW MOVF DS40001412H-page 94 TABLAT, W WORD_EVEN TABLAT, W WORD_ODD ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 6.5 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP™ control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR point to the block being erased. The TBLPTR bits are ignored. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. The write initiate sequence for EECON2, shown as steps 4 through 6 in Section 6.5.1 “Flash Program Memory Erase Sequence”, is used to guard against accidental writes. This is sometimes referred to as a long write. 6.5.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory is: 1. 2. 3. 4. 5. 6. 7. 8. Load Table Pointer register with address of block being erased. Set the EECON1 register for the erase operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN bit to enable writes; • set FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the block erase cycle. The CPU will stall for duration of the erase (about 2 ms using internal timer). Re-enable interrupts. A long write is necessary for erasing the internal Flash. Instruction execution is halted during the long write cycle. The long write is terminated by the internal programming timer. EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; load TBLPTR with the base ; address of the memory block BSF BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF EECON1, EECON1, EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, ; ; ; ; ; ERASE_BLOCK Required Sequence  2010-2021 Microchip Technology Inc. EEPGD CFGS WREN FREE GIE point to Flash program memory access Flash program memory enable write to memory enable block Erase operation disable interrupts ; write 55h WR GIE ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts DS40001412H-page 95 PIC18(L)F2X/4XK22 6.6 Writing to Flash Program Memory The programming block size is 64 bytes. Word or byte programming is not supported. The long write is necessary for programming the internal Flash. Instruction execution is halted during a long write cycle. The long write will be terminated by the internal programming timer. Table writes are used internally to load the holding registers needed to program the Flash memory. There are only as many holding registers as there are bytes in a write block (64 bytes). The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction needs to be executed 64 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written. After all the holding registers have been written, the programming operation of that block of memory is started by configuring the EECON1 register for a program memory write and performing the long write sequence. FIGURE 6-5: Note: The default value of the holding registers on device Resets and after write operations is FFh. A write of FFh to a holding register does not modify that byte. This means that individual bytes of program memory may be modified, provided that the change does not attempt to change any bit from a ‘0’ to a ‘1’. When modifying individual bytes, it is not necessary to load all holding registers before executing a long write operation. TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 TBLPTR = xxxx00 TBLPTR = xxxx01 Holding Register 8 TBLPTR = xxxxYY(1) TBLPTR = xxxx02 Holding Register 8 Holding Register Holding Register Program Memory Note 1: YY = 3F for 64 byte write blocks. 6.6.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location may be: 1. 2. 3. 4. 5. 6. 7. Read 64 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer register with address being erased. Execute the block erase procedure. Load Table Pointer register with address of first byte being written. Write the 64-byte block into the holding registers with auto-increment. Set the EECON1 register for the write operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. DS40001412H-page 96 8. 9. 10. 11. 12. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the write cycle. The CPU will stall for duration of the write (about 2 ms using internal timer). 13. Re-enable interrupts. 14. Verify the memory (table read). This procedure will require about 6 ms to update each write block of memory. An example of the required code is given in Example 6-3. Note: Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the bytes in the holding registers.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64’ COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; point to buffer MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BSF BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF TBLRD*MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, EEPGD EECON1, CFGS EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE ; load TBLPTR with the base ; address of the memory block MOVLW MOVWF MOVLW MOVWF BlockSize COUNTER D’64’/BlockSize COUNTER2 MOVF MOVWF TBLWT+* POSTINC0, W TABLAT ; point to buffer ; Load TBLPTR with the base ; address of the memory block READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data done? repeat MODIFY_WORD ; update buffer word ERASE_BLOCK Required Sequence BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L ; ; ; ; ; point to Flash program memory access Flash program memory enable write to memory enable Erase operation disable interrupts ; write 55h ; ; ; ; ; write 0AAh start erase (CPU stall) re-enable interrupts dummy read decrement point to buffer WRITE_BUFFER_BACK ; number of bytes in holding register ; number of write blocks in 64 bytes WRITE_BYTE_TO_HREGS  2010-2021 Microchip Technology Inc. ; ; ; ; get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. DS40001412H-page 97 PIC18(L)F2X/4XK22 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) DECFSZ BRA COUNTER WRITE_WORD_TO_HREGS ; loop until holding registers are full BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF DCFSZ BRA BSF BCF EECON1, EEPGD EECON1, CFGS EECON1, WREN INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR COUNTER2 WRITE_BYTE_TO_HREGS INTCON, GIE EECON1, WREN ; ; ; ; PROGRAM_MEMORY Required Sequence 6.6.2 WRITE VERIFY UNEXPECTED TERMINATION OF WRITE OPERATION If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed may be verified and reprogrammed if needed. If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the WRERR bit will be set which the user can check to decide whether a rewrite of the location(s) is needed. TABLE 6-2: Name TBLPTRU ; write 55h ; ; ; ; ; ; write 0AAh start program (CPU stall) repeat for remaining write blocks re-enable interrupts disable write to memory 6.6.4 Depending on the application, good programming practice may dictate that the value written to the memory may be verified against the original value. This may be used in applications where excessive writes can stress bits near the specification limit. 6.6.3 point to Flash program memory access Flash program memory enable write to memory disable interrupts PROTECTION AGAINST SPURIOUS WRITES To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 24.0 “Special Features of the CPU” for more details. 6.7 Flash Program Operation During Code Protection See Section 24.5 “Program Verification and Code Protection” for details on code protection of Flash program memory. REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Bit 7 — Bit 6 — Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Program Memory Table Pointer Upper Byte (TBLPTR) Reset Values on page — TBLPTRH Program Memory Table Pointer High Byte (TBLPTR) — TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR) — TABLAT INTCON Program Memory Table Latch GIE/GIEH PEIE/GIEL EECON1 EEPGD CFGS — FREE WRERR EECON2 TMR0IE INT0IE RBIE — TMR0IF INT0IF RBIF 109 WREN WR RD 92 122 EEPROM Control Register 2 (not a physical register) — IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during Flash/EEPROM access. DS40001412H-page 98  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 7.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, which is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire VDD range. Four SFRs are used to read and write to the data EEPROM as well as the program memory. They are: • • • • • EECON1 EECON2 EEDATA EEADR EEADRH The data EEPROM allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and the EEADR:EEADRH register pair hold the address of the EEPROM location being accessed. The EEPROM data memory is rated for high erase/write cycle endurance. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer; it will vary with voltage and temperature as well as from chipto-chip. Please refer to the Data EEPROM Memory parameters in Section 27.0 “Electrical Specifications” for limits. 7.1 EEADR and EEADRH Registers The EEADR register is used to address the data EEPROM for read and write operations. The 8-bit range of the register can address a memory range of 256 bytes (00h to FFh). The EEADRH register expands the range to 1024 bytes by adding an additional two address bits. 7.2 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers: EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory. When the EEPGD bit is clear, operations will access the data EEPROM memory. When the EEPGD bit is set, program memory is accessed. Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data EEPROM memory. When the CFGS bit is set, subsequent operations access Configuration registers. When the CFGS bit is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set by hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete. Note: During normal operation, the WRERR may read as ‘1’. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. The WR control bit initiates write operations. The bit can be set but not cleared by software. It is cleared only by hardware at the completion of the write operation. Note: The EEIF interrupt flag bit of the PIR2 register is set when the write is complete. It must be cleared by software. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.1 “Table Reads and Table Writes” regarding table reads. The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s.  2010-2021 Microchip Technology Inc. DS40001412H-page 99 PIC18(L)F2X/4XK22 REGISTER 7-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row (Block) Erase Enable bit 1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) by software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS40001412H-page 100  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit of the EECON1 register and then set control bit, RD. The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation). The basic process is shown in Example 7-1. 7.4 Writing to the Data EEPROM Memory To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. The sequence in Example 7-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write 0AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. EXAMPLE 7-1: MOVLW MOVWF BCF BCF BSF MOVF After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared by hardware and the EEPROM Interrupt Flag bit, EEIF, is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by software. 7.5 Write Verify Depending on the application, good programming practice may dictate that the value written to the memory may be verified against the original value. This may be used in applications where excessive writes can stress bits near the specification limit. DATA EEPROM READ DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, CFGS EECON1, RD EEDATA, W EXAMPLE 7-2: Required Sequence Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit may be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. ; ; ; ; ; ; Data Memory Address to read Point to DATA memory Access EEPROM EEPROM Read W = EEDATA DATA EEPROM WRITE MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BCF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF DATA_EE_ADDR_LOW EEADR DATA_EE_ADDR_HI EEADRH DATA_EE_DATA EEDATA EECON1, EEPGD EECON1, CFGS EECON1, WREN INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; BCF EECON1, WREN ; User code execution ; Disable writes on write complete (EEIF set)  2010-2021 Microchip Technology Inc. Data Memory Address to write Data Memory Value to write Point to DATA memory Access EEPROM Enable writes Disable Interrupts Write 55h Write 0AAh Set WR bit to begin write Enable Interrupts DS40001412H-page 101 PIC18(L)F2X/4XK22 7.6 Operation During Code-Protect 7.8 Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 24.0 “Special Features of the CPU” for additional information. 7.7 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been implemented. On power-up, the WREN bit is cleared. In addition, writes to the EEPROM are blocked during the Power-up Timer period (TPWRT).The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. EXAMPLE 7-3: Using the Data EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM without exceeding the total number of write cycles to a single byte. Refer to the Data EEPROM Memory parameters in Section 27.0 “Electrical Specifications” for write cycle limits. If this is the case, then an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) may be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example 7-3. Note: If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification. DATA EEPROM REFRESH ROUTINE CLRF CLRF BCF BCF BCF BSF EEADR EEADRH EECON1, EECON1, INTCON, EECON1, BSF MOVLW MOVWF MOVLW MOVWF BSF BTFSC BRA INCFSZ BRA INCFSZ BRA EECON1, RD 55h EECON2 0AAh EECON2 EECON1, WR EECON1, WR $-2 EEADR, F LOOP EEADRH, F LOOP BCF BSF EECON1, WREN INTCON, GIE CFGS EEPGD GIE WREN Loop DS40001412H-page 102 ; ; ; ; ; ; ; ; ; ; ; ; ; ; Start at address 0 if > 256 bytes EEPROM Set for memory Set for Data EEPROM Disable interrupts Enable writes Loop to refresh array Read current address ; ; ; ; Increment address Not zero, do it again if > 256 bytes, Increment address if > 256 bytes, Not zero, do it again Write 55h Write 0AAh Set WR bit to begin write Wait for write to complete ; Disable writes ; Enable interrupts  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 7-1: Name REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL EEADR EEADR7 EEADR6 — — (1) EEADRH Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 — EEDATA — — — EEADR9 EEADR8 EEPROM Data Register EECON2 — — — EEPROM Control Register 2 (not a physical register) — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 100 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during EEPROM access. Note 1: PIC18(L)F26K22 and PIC18(L)F46K22 only.  2010-2021 Microchip Technology Inc. DS40001412H-page 103 PIC18(L)F2X/4XK22 8.0 8 x 8 HARDWARE MULTIPLIER 8.1 Introduction All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register. Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 8-1. 8.2 EXAMPLE 8-1: MOVF MULWF 8 x 8 UNSIGNED MULTIPLY ROUTINE ARG1, W ARG2 ; ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY ROUTINE MOVF MULWF ARG1, W ARG2 BTFSC SUBWF ARG2, SB PRODH, F MOVF BTFSC SUBWF ARG2, W ARG1, SB PRODH, F ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 ; Test Sign Bit ; PRODH = PRODH ; - ARG2 Operation Example 8-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 8-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Multiply Method Program Memory (Words) Without hardware multiply 13 Routine 8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed Time Cycles (Max) @ 64 MHz @ 40 MHz @ 10 MHz @ 4 MHz 69 4.3 s 6.9 s 27.6 s 69 s Hardware multiply 1 1 62.5 ns 100 ns 400 ns 1 s Without hardware multiply 33 91 5.7 s 9.1 s 36.4 s 91 s Hardware multiply 6 6 375 ns 600 ns 2.4 s 6 s Without hardware multiply 21 242 15.1 s 24.2 s 96.8 s 242 s Hardware multiply 28 28 1.8 s 2.8 s 11.2 s 28 s Without hardware multiply 52 254 15.9 s 25.4 s 102.6 s 254 s Hardware multiply 35 40 2.5 s 4.0 s 16.0 s 40 s DS40001412H-page 104  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 Example 8-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES). EQUATION 8-1: RES3:RES0 = = EXAMPLE 8-3: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L  ARG2H:ARG2L (ARG1H  ARG2H  216) + (ARG1H  ARG2L  28) + (ARG1L  ARG2H  28) + (ARG1L  ARG2L) EQUATION 8-2: RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L = (ARG1H  ARG2H  216) + (ARG1H  ARG2L  28) + (ARG1L  ARG2H  28) + (ARG1L  ARG2L) + (-1  ARG2H  ARG1H:ARG1L  216) + (-1  ARG1H  ARG2H:ARG2L  216) EXAMPLE 8-4: 16 x 16 UNSIGNED MULTIPLY ROUTINE MOVF MULWF ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1L * ARG2L-> ; PRODH:PRODL ; ; ARG1L * ARG2H-> PRODH:PRODL Add cross products ARG1H * ARG2L-> PRODH:PRODL Add cross products Example 8-4 shows the sequence to do a 16 x 16 signed multiply. Equation 8-2 shows the algorithm used. The 32-bit result is stored in four registers (RES). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done.  2010-2021 Microchip Technology Inc. ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F BTFSS BRA MOVF SUBWF MOVF SUBWFB ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ; ; ; ; ; ; ; ; ; ; ; MOVF MULWF ; ; ; ; ; ; ; ; ; ; 16 x 16 SIGNED MULTIPLY ROUTINE ; ; ; ARG1H * ARG2H-> ; PRODH:PRODL ; ; 16 x 16 SIGNED MULTIPLICATION ALGORITHM ; ; ; ; ; ; ; ; ; ARG1H * ARG2L -> PRODH:PRODL Add cross products ; ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE : DS40001412H-page 105 PIC18(L)F2X/4XK22 9.0 INTERRUPTS The PIC18(L)F2X/4XK22 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high or low priority level (INT0 does not have a priority bit, it is always a high priority). The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. A high priority interrupt event will interrupt a low priority interrupt that may be in progress. There are 19 registers used to control interrupt operation. These registers are: • • • • • INTCON, INTCON2, INTCON3 PIR1, PIR2, PIR3, PIR4, PIR5 PIE1, PIE2, PIE3, PIE4, PIE5 IPR1, IPR2, IPR3, IPR4, IPR5 RCON It is recommended that the Microchip header files supplied with MPLAB® IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. In general, interrupt sources have three bits to control their operation. They are: • Flag bit to indicate that an interrupt event occurred • Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set • Priority bit to select high priority or low priority 9.1 Mid-Range Compatibility When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC® microcontroller mid-range devices. In Compatibility mode, the interrupt priority bits of the IPRx registers have no effect. The PEIE/GIEL bit of the INTCON register is the global interrupt enable for the peripherals. The PEIE/GIEL bit disables only the peripheral interrupt sources and enables the peripheral interrupt sources when the GIE/GIEH bit is also set. The GIE/GIEH bit of the INTCON register is the global interrupt enable which enables all nonperipheral interrupt sources and disables all interrupt sources, including the peripherals. All interrupts branch to address 0008h in Compatibility mode. DS40001412H-page 106 9.2 Interrupt Priority The interrupt priority feature is enabled by setting the IPEN bit of the RCON register. When interrupt priority is enabled the GIE/GIEH and PEIE/GIEL global interrupt enable bits of Compatibility mode are replaced by the GIEH high priority, and GIEL low priority, global interrupt enables. When set, the GIEH bit of the INTCON register enables all interrupts that have their associated IPRx register or INTCONx register priority bit set (high priority). When clear, the GIEH bit disables all interrupt sources including those selected as low priority. When clear, the GIEL bit of the INTCON register disables only the interrupts that have their associated priority bit cleared (low priority). When set, the GIEL bit enables the low priority sources when the GIEH bit is also set. When the interrupt flag, enable bit and appropriate Global Interrupt Enable (GIE) bit are all set, the interrupt will vector immediately to address 0008h for high priority, or 0018h for low priority, depending on level of the interrupting source’s priority bit. Individual interrupts can be disabled through their corresponding interrupt enable bits. 9.3 Interrupt Response When an interrupt is responded to, the Global Interrupt Enable bit is cleared to disable further interrupts. The GIE/GIEH bit is the Global Interrupt Enable when the IPEN bit is cleared. When the IPEN bit is set, enabling interrupt priority levels, the GIEH bit is the high priority global interrupt enable and the GIEL bit is the low priority Global Interrupt Enable. High priority interrupt sources can interrupt a low priority interrupt. Low priority interrupts are not processed while high priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (0008h or 0018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits in the INTCONx and PIRx registers. The interrupt flag bits must be cleared by software before re-enabling interrupts to avoid repeating the same interrupt. The “return from interrupt” instruction, RETFIE, exits the interrupt routine and sets the GIE/GIEH bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB interrupt-on-change, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one-cycle or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bits or the Global Interrupt Enable bit.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. FIGURE 9-1: PIC18 INTERRUPT LOGIC Wake-up if in Idle or Sleep modes INT0IF INT0IE PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 PIR3 PIE3 IPR3 TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP (1) Interrupt to CPU Vector to Location 0008h GIEH/GIE IPEN PIR4 PIE4 IPR4 PIR5 PIE5 IPR5 IPEN GIEL/PEIE IPEN High Priority Interrupt Generation Low Priority Interrupt Generation PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 PIR3 PIE3 IPR3 PIR4 PIE4 IPR4 PIR5 PIE5 IPR5 Interrupt to CPU Vector to Location 0018h TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP (1) GIEH/GIE GIEL/PEIE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Note 1: The RBIF interrupt also requires the individual pin IOCB enables.  2010-2021 Microchip Technology Inc. DS40001412H-page 107 PIC18(L)F2X/4XK22 9.4 INTCON Registers The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. 9.5 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are five Peripheral Interrupt Request Flag registers (PIR1, PIR2, PIR3, PIR4 and PIR5). 9.6 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are five Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3, PIE4 and PIE5). When IPEN = 0, the PEIE/GIEL bit must be set to enable any of these peripheral interrupts. 9.7 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are five Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3, IPR4 and IPR5). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. DS40001412H-page 108  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 9.8 Register Definitions: Interrupt Control REGISTER 9-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts including peripherals When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts including low priority bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority interrupts 0 = Disables all low priority interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: Port B Interrupt-On-Change (IOCx) Interrupt Enable bit(2) 1 = Enables the IOCx port change interrupt 0 = Disables the IOCx port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared by software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared by software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: Port B Interrupt-On-Change (IOCx) Interrupt Flag bit(1) 1 = At least one of the IOC (RB) pins changed state (must be cleared by software) 0 = None of the IOC (RB) pins have changed state Note 1: 2: Note: A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. RB port change interrupts also require the individual pin IOCB enables. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software may ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2010-2021 Microchip Technology Inc. DS40001412H-page 109 PIC18(L)F2X/4XK22 REGISTER 9-2: INTCON2: INTERRUPT CONTROL 2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled provided that the pin is an input and the corresponding WPUB bit is set. bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as ‘0’ bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software may ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS40001412H-page 110  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 9-3: INTCON3: INTERRUPT CONTROL 3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared by software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared by software) 0 = The INT1 external interrupt did not occur Note: x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software may ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2010-2021 Microchip Technology Inc. DS40001412H-page 111 PIC18(L)F2X/4XK22 REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’. bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared by software) 0 = The A/D conversion is not complete or has not been started bit 5 RC1IF: EUSART1 Receive Interrupt Flag bit 1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART1 receive buffer is empty bit 4 TX1IF: EUSART1 Transmit Interrupt Flag bit 1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART1 transmit buffer is full bit 3 SSP1IF: Host Synchronous Serial Port 1 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared by software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR register capture occurred (must be cleared by software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared by software) 0 = No TMR register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared by software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared by software) 0 = TMR1 register did not overflow Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE/ GIEH of the INTCON register. Note: User software may ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. DS40001412H-page 112  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software) 0 = Device clock operating bit 6 C1IF: Comparator C1 Interrupt Flag bit 1 = Comparator C1 output has changed (must be cleared by software) 0 = Comparator C1 output has not changed bit 5 C2IF: Comparator C2 Interrupt Flag bit 1 = Comparator C2 output has changed (must be cleared by software) 0 = Comparator C2 output has not changed bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared by software) 0 = The write operation is not complete or has not been started bit 3 BCL1IF: MSSP1 Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared by software) 0 = No bus collision occurred bit 2 HLVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (direction determined by the VDIRMAG bit of the HLVDCON register) 0 = A low-voltage condition has not occurred bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared by software) 0 = TMR3 register did not overflow bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR register capture occurred (must be cleared by software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared by software) 0 = No TMR register compare match occurred PWM mode: Unused in this mode.  2010-2021 Microchip Technology Inc. DS40001412H-page 113 PIC18(L)F2X/4XK22 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 6 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit 1 = A bus collision has occurred while the SSP2 module configured in I2C host was transmitting (must be cleared in software) 0 = No bus collision occurred bit 5 RC2IF: EUSART2 Receive Interrupt Flag bit 1 = The EUSART2 receive buffer, RCREG2, is full (cleared by reading RCREG2) 0 = The EUSART2 receive buffer is empty bit 4 TX2IF: EUSART2 Transmit Interrupt Flag bit 1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared by writing TXREG2) 0 = The EUSART2 transmit buffer is full bit 3 CTMUIF: CTMU Interrupt Flag bit 1 = CTMU interrupt occurred (must be cleared in software) 0 = No CTMU interrupt occurred bit 2 TMR5GIF: TMR5 Gate Interrupt Flag bits 1 = TMR gate interrupt occurred (must be cleared in software) 0 = No TMR gate occurred bit 1 TMR3GIF: TMR3 Gate Interrupt Flag bits 1 = TMR gate interrupt occurred (must be cleared in software) 0 = No TMR gate occurred bit 0 TMR1GIF: TMR1 Gate Interrupt Flag bits 1 = TMR gate interrupt occurred (must be cleared in software) 0 = No TMR gate occurred DS40001412H-page 114  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 9-7: PIR4: PERIPHERAL INTERRUPT (FLAG) REGISTER 4 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2 CCP5IF: CCP5 Interrupt Flag bits Capture mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM mode: Unused in PWM mode. bit 1 CCP4IF: CCP4 Interrupt Flag bits Capture mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM mode: Unused in PWM mode. bit 0 CCP3IF: ECCP3 Interrupt Flag bits Capture mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM mode: Unused in PWM mode.  2010-2021 Microchip Technology Inc. DS40001412H-page 115 PIC18(L)F2X/4XK22 REGISTER 9-8: PIR5: PERIPHERAL INTERRUPT (FLAG) REGISTER 5 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — TMR6IF TMR5IF TMR4IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit 1 = TMR6 to PR6 match occurred (must be cleared in software) 0 = No TMR6 to PR6 match occurred bit 1 TMR5IF: TMR5 Overflow Interrupt Flag bit 1 = TMR5 register overflowed (must be cleared in software) 0 = TMR5 register did not overflow bit 0 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred DS40001412H-page 116 x = Bit is unknown  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 9-9: PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’. bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RC1IE: EUSART1 Receive Interrupt Enable bit 1 = Enables the EUSART1 receive interrupt 0 = Disables the EUSART1 receive interrupt bit 4 TX1IE: EUSART1 Transmit Interrupt Enable bit 1 = Enables the EUSART1 transmit interrupt 0 = Disables the EUSART1 transmit interrupt bit 3 SSP1IE: Host Synchronous Serial Port 1 Interrupt Enable bit 1 = Enables the MSSP1 interrupt 0 = Disables the MSSP1 interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt  2010-2021 Microchip Technology Inc. x = Bit is unknown DS40001412H-page 117 PIC18(L)F2X/4XK22 REGISTER 9-10: PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 C1IE: Comparator C1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 C2IE: Comparator C2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCL1IE: MSSP1 Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS40001412H-page 118 x = Bit is unknown  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 9-11: PIE3: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SSP2IE: Host Synchronous Serial Port 2 Interrupt Enable bit 1 = Enables the MSSP2 interrupt 0 = Disables the MSSP2 interrupt bit 6 BCL2IE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 RC2IE: EUSART2 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX2IE: EUSART2 Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 CTMUIE: CTMU Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 TMR5GIE: TMR5 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3GIE: TMR3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR1GIE: TMR1 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled  2010-2021 Microchip Technology Inc. x = Bit is unknown DS40001412H-page 119 PIC18(L)F2X/4XK22 REGISTER 9-12: PIE4: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 4 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 CCP5IE: CCP5 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: CCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled REGISTER 9-13: x = Bit is unknown PIE5: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 5 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — TMR6IE TMR5IE TMR4IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit 1 = Enables the TMR6 to PR6 match interrupt 0 = Disables the TMR6 to PR6 match interrupt bit 1 TMR5IE: TMR5 Overflow Interrupt Enable bit 1 = Enables the TMR5 overflow interrupt 0 = Disables the TMR5 overflow interrupt bit 0 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 match interrupt 0 = Disables the TMR4 to PR4 match interrupt DS40001412H-page 120 x = Bit is unknown  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 9-14: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: EUSART1 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: EUSART1 Transmit Interrupt Priority bit x = Bit is unknown 1 = High priority 0 = Low priority bit 3 SSP1IP: Host Synchronous Serial Port 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority  2010-2021 Microchip Technology Inc. DS40001412H-page 121 PIC18(L)F2X/4XK22 REGISTER 9-15: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 C1IP: Comparator C1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 C2IP: Comparator C2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCL1IP: MSSP1 Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority DS40001412H-page 122 x = Bit is unknown  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 9-16: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SSP2IP: Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: EUSART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 CTMUIP: CTMU Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 TMR5GIP: TMR5 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3GIP: TMR3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1GIP: TMR1 Gate Interrupt Priority bit 1 = High priority 0 = Low priority  2010-2021 Microchip Technology Inc. x = Bit is unknown DS40001412H-page 123 PIC18(L)F2X/4XK22 REGISTER 9-17: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 CCP5IP: CCP5 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 CCP4IP: CCP4 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP3IP: CCP3 Interrupt Priority bit 1 = High priority 0 = Low priority REGISTER 9-18: x = Bit is unknown IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — TMR6IP TMR5IP TMR4IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 TMR6IP: TMR6 to PR6 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR5IP: TMR5 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit 1 = High priority 0 = Low priority DS40001412H-page 124 x = Bit is unknown  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 9.9 INTn Pin Interrupts 9.10 External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE. Flag bit, INTxF, must be cleared by software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wakeup the processor from Idle or Sleep modes if bit INTxE was set prior to going into those modes. If the Global Interrupt Enable bit, GIE/GIEH, is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits, INT1IP and INT2IP of the INTCON3 register. There is no priority bit associated with INT0. It is always a high priority interrupt source. TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh  00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE of the INTCON register. Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP of the INTCON2 register. See Section 11.0 “Timer0 Module” for further details on the Timer0 module. 9.11 PORTB Interrupt-on-Change An input change on PORTB sets flag bit, RBIF of the INTCON register. The interrupt can be enabled/ disabled by setting/clearing enable bit, RBIE of the INTCON register. Pins must also be individually enabled with the IOCB register. Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP of the INTCON2 register. 9.12 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section 5.2.1 “Fast Register Stack”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP MOVFF STATUS, STATUS_TEMP MOVFF BSR, BSR_TEMP ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS  2010-2021 Microchip Technology Inc. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS DS40001412H-page 125 PIC18(L)F2X/4XK22 TABLE 9-1: Name ANSELB INTCON REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 150 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 — TMR0IP — RBIP 110 GIE/GIEH PEIE/GIEL INTCON2 RBPU INTEDG0 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 111 IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 153 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP IPR4 — — — — IPR5 — — — PIE1 — ADIE RC1IE PIE2 OSCFIE C1IE C2IE PIE3 SSP2IE BCL2IE RC2IE PIE4 — — — — — CCP5IE CCP4IE CCP3IE 120 PIE5 — — — — — TMR6IE TMR5IE TMR4IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF PIR4 — — — — PIR5 PORTB RCON Legend: INTEDG1 INTEDG2 123 — CCP5IP CCP4IP CCP3IP 124 — — TMR6IP TMR5IP TMR4IP 124 TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 TMR1GIF 114 — CCP5IF CCP4IF CCP3IF 115 — — — — — TMR6IF TMR5IF TMR4IF 116 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 148 IPEN SBOREN — RI TO PD POR BOR 56 Register on Page — = unimplemented locations, read as ‘0’. Shaded bits are not used for Interrupts. TABLE 9-2: Name CONFIGURATION REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 CONFIG4L DEBUG XINST — — — LVP — STRVEN 349 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Interrupts. DS40001412H-page 126  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 10.0 I/O PORTS 10.1 Depending on the device selected and features enabled, there are up to five ports available. All pins of the I/O ports are multiplexed with one or more alternate functions from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has five registers for its operation. These registers are: • TRIS register (data direction register) • PORT register (reads the levels on the pins of the device) • LAT register (output latch) • ANSEL register (analog input control) • SLRCON register (port slew rate control) The Data Latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are driving. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 10-1. FIGURE 10-1: GENERIC I/O PORT OPERATION WR LAT or Port D Q (1) I/O pin CK WR TRIS Q The Data Latch (LATA) register is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. The RA4 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to become the RA4/T0CKI/C1OUT pin. Pins RA6 and RA7 are multiplexed with the main oscillator pins; they are enabled as oscillator or I/O pins by the selection of the main oscillator in the Configuration register (see Section 24.1 “Configuration Bits” for details). When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as ‘0’. Pins RA0 through RA5 may also be used as comparator inputs or outputs by setting the appropriate bits in the CM1CON0 and CM2CON0 registers. TRISx ANSELx CK TRIS Latch Input Buffer RD TRIS Q D ENEN RD Port Note 1: Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the PORT latch. Note: Data Latch D PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs, and the comparator voltage reference output. The operation of pins RA and RA5 as analog is selected by setting the ANSELA bits in the ANSELA register which is the default setting after a Power-on Reset. RD LAT Data Bus On a Power-on Reset, RA5 and RA are configured as analog inputs and read as ‘0’. RA4 is configured as a digital input. The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input. All other PORTA pins have TTL input levels and full CMOS output drivers. The TRISA register controls the drivers of the PORTA pins, even when they are being used as analog inputs. The user may ensure the bits in the TRISA register are maintained set when using them as analog inputs. EXAMPLE 10-1: MOVLB CLRF I/O pins have diode protection to VDD and VSS. CLRF MOVLW MOVWF MOVLW MOVWF  2010-2021 Microchip Technology Inc. PORTA Registers 0xF PORTA ; ; ; ; LATA ; ; ; E0h ; ANSELA ; 0CFh ; ; ; TRISA ; ; INITIALIZING PORTA Set BSR for banked SFRs Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure I/O for digital inputs Value used to initialize data direction Set RA as inputs RA as outputs DS40001412H-page 127 PIC18(L)F2X/4XK22 TABLE 10-1: Pin Name PORTA I/O SUMMARY Function TRIS Setting ANSEL Setting Pin Type RA0 0 0 O DIG 1 0 I TTL PORTA data input; disabled when analog input enabled. C12IN0- 1 1 I AN Comparators C1 and C2 inverting input. AN0 1 1 I AN Analog input 0. RA1 0 0 O DIG LATA data output; not affected by analog input. 1 0 I TTL PORTA data input; disabled when analog input enabled. 1 1 I AN Comparators C1 and C2 inverting input. RA0/C12IN0-/AN0 RA1/C12IN1-/AN1 C12IN1- Description LATA data output; not affected by analog input. AN1 1 1 I AN Analog input 1. RA2 0 0 O DIG LATA data output; not affected by analog input; disabled when DACOUT enabled. 1 0 I TTL PORTA data input; disabled when analog input enabled; disabled when DACOUT enabled. C2IN+ 1 1 I AN Comparator C2 noninverting input. AN2 1 1 I AN Analog output 2. DACOUT x 1 O AN DAC Reference output. VREF- 1 1 I AN A/D reference voltage (low) input. RA3 0 LATA data output; not affected by analog input. RA2/C2IN+/AN2/ DACOUT/VREF- RA3/C1IN+/AN3/ VREF+ C1IN+ O DIG 1 0 I TTL PORTA data input; disabled when analog input enabled. 1 1 I AN Comparator C1 noninverting input. AN3 1 1 I AN Analog input 3. VREF+ 1 1 I AN A/D reference voltage (high) input. RA4 0 — O DIG LATA data output. 1 — I ST PORTA data input; default configuration on POR. 0 — O DIG CCP5 Compare output/PWM output, takes priority over RA4 output. RA4/CCP5/C1OUT/ SRQ/T0CKI CCP5 1 — I ST Capture 5 input/Compare 5 output/ PWM 5 output. C1OUT 0 — O DIG Comparator C1 output. SR latch Q output; take priority over CCP 5 output. SRQ 0 — O DIG T0CKI 1 — I ST Timer0 external clock input. RA5 0 0 O DIG LATA data output; not affected by analog input. PORTA data input; disabled when analog input enabled. RA5/C2OUT/SRNQ/ SS1/ HLVDIN/AN4 1 0 I TTL C2OUT 0 0 O DIG Comparator C2 output. SRNQ 0 0 O DIG SR latch Q output. SS1 1 0 I TTL SPI client select input (MSSP1). HLVDIN 1 1 I AN High/Low-Voltage Detect input. AN4 1 1 I AN A/D input 4. RA6 0 — O DIG LATA data output; enabled in INTOSC modes when CLKO is not enabled. 1 — I TTL PORTA data input; enabled in INTOSC modes when CLKO is not enabled. CLKO x — O DIG In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. OSC2 x — O XTAL RA7 0 — O DIG LATA data output; disabled in external oscillator modes. 1 — I TTL PORTA data input; disabled in external oscillator modes. CLKI x — I AN External clock source input; always associated with pin function OSC1. OSC1 x — I XTAL RA6/CLKO/OSC2 RA7/CLKI/OSC1 Legend: Buffer Type Oscillator crystal output; connects to crystal or resonator in Crystal Oscillator mode. Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. DS40001412H-page 128  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 10-2: REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 149 C1ON C1OUT C1OE C1POL C1SP C1R CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 VREFCON1 DACEN DACLPS DACOE — VREFCON2 — — — VDIRMAG BGVST IRVST HLVDEN RA7 RA6 RA5 RA4 SLRCON — — — SLRE SRCON0 SRLEN Name ANSELA CM1CON0 HLVDCON PORTA SSP1CON1 C1CH 308 C2CH 308 LATA1 LATA0 — DACNSS DACPSS DACR SRCLK RA2 335 336 HLVDL RA3 152 RA1 337 RA0 148 SLRD SLRC SLRB SLRA 153 SRQEN SRNQEN SRPS SRPR 329 WCOL SSPOV SSPEN CKP T0CON TMR0ON T08BIT T0CS T0SE PSA SSPM TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 253 T0PS TRISA2 TRISA1 154 TRISA0 151 Bit 0 Register on Page Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTA. TABLE 10-3: CONFIGURATION REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 CONFIG1H IESO FCMEN Bit 5 Bit 4 PRICLKEN PLLCFG Bit 3 Bit 2 Bit 1 FOSC 345 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTA.  2010-2021 Microchip Technology Inc. DS40001412H-page 129 PIC18(L)F2X/4XK22 10.1.1 PORTA OUTPUT PRIORITY Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. Table 10-4 lists the PORTA pin functions from the highest to the lowest priority. Analog input functions, such as ADC and comparator, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below. TABLE 10-4: PORT PIN FUNCTION PRIORITY Port bit 0 1 Port Function Priority by Port Pin PORTA PORTB PORTC PORTD(2) PORTE(2) RA0 CCP4(1) SOSCO SCL2 CCP3(8) RB0 P2B(6) SCK2 P3A(8) RC0 RD0 RE0 RA1 2 RA2 SCL2(1) SOSCI SDA2 P3B SCK2(1) CCP2(3) CCP4 RE1 P1C(1) P2A(3) RD1 RB1 RC1 SDA2(1) CCP1 P2B CCP5 P1B(1) P1A RD2(4) RE2 RB2 CTPLS RC2 3 RA3 (1) SCL1 P2C MCLR CCP2(6) SCK1 RD3 VPP SDO2 (6) P2A RC3 RE3 RB3 4 SRQ P1D(1) SDA1 SDO2 C1OUT RB4 RC4 P2D (1) CCP5 RD4 RA4 Note 1: 2: 3: 4: 5: 6: 7: 8: PIC18(L)F2XK22 devices. PIC18(L)F4XK22 devices. Function default pin. Function default pin (28-pin devices). Function default pin (40/44-pin devices). Function alternate pin. Function alternate pin (28-pin devices). Function alternate pin (40/44-pin devices) DS40001412H-page 130  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 10-4: Port bit 5 PORT PIN FUNCTION PRIORITY (CONTINUED) Port Function Priority by Port Pin PORTD(2) PORTA PORTB PORTC SRNQ CCP3(3) SDO1 P1B C2OUT P3A(3) RC5 RD5 RA5 P2B(1)(4) PORTE(2) RB5 6 OSC2 PGC TX1/CK1 TX2/CK2 CLKO TX2/CK2(1) CCP3(1)(7) P1C RB6 P3A(1)(7) RD6 ICDCK RC6 RA6 7 RA7 OSC1 RA7 PGD RX2/DT2 RB7 RX1/DT1 (1) RX2/DT2 P3B(1) P1D RC7 RD7 ICDDT Note 1: 2: 3: 4: 5: 6: 7: 8: PIC18(L)F2XK22 devices. PIC18(L)F4XK22 devices. Function default pin. Function default pin (28-pin devices). Function default pin (40/44-pin devices). Function alternate pin. Function alternate pin (28-pin devices). Function alternate pin (40/44-pin devices)  2010-2021 Microchip Technology Inc. DS40001412H-page 131 PIC18(L)F2X/4XK22 10.2 PORTB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., disable the output driver). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB. EXAMPLE 10-2: MOVLB CLRF CLRF MOVLW MOVWF MOVLW MOVWF 10.2.1 0xF PORTB ; ; ; ; LATB ; ; ; 0F0h ; ANSELB ; ; ; ; 0CFh ; ; ; TRISB ; ; ; INITIALIZING PORTB Set BSR for banked SFRs Initialize PORTB by clearing output data latches Alternate method to clear output data latches Value for init Enable RB for digital input pins (not required if config bit PBADEN is clear) Value used to initialize data direction Set RB as inputs RB as outputs RB as inputs PORTB OUTPUT PRIORITY Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. Table 10-4 lists the PORTB pin functions from the highest to the lowest priority. Analog input functions, such as ADC, comparator and SR latch inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below. 10.3 PORTB pins RB have an interrupt-on-change option. All PORTB pins have a weak pull-up option. 10.3.1 WEAK PULL-UPS Each of the PORTB pins has an individually controlled weak internal pull-up. When set, each bit of the WPUB register enables the corresponding pin pull-up. When cleared, the RBPU bit of the INTCON2 register enables pull-ups on all pins which also have their corresponding WPUB bit set. When set, the RBPU bit disables all weak pull-ups. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Note: On a Power-on Reset, RB are configured as analog inputs by default and read as ‘0’; RB are configured as digital inputs. When the PBADEN Configuration bit is set to ‘1’, RB will alternatively be configured as digital inputs on POR. 10.3.2 INTERRUPT-ON-CHANGE Four of the PORTB pins (RB) are individually configurable as interrupt-on-change pins. Control bits in the IOCB register enable (when set) or disable (when clear) the interrupt function for each pin. When set, the RBIE bit of the INTCON register enables interrupts on all pins which also have their corresponding IOCB bit set. When clear, the RBIE bit disables all interrupt-on-changes. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB pin configured as an output is excluded from the interrupt-on-change comparison). For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTB. The ‘mismatch’ outputs of the last read are OR’d together to set the PORTB Change Interrupt flag bit (RBIF) in the INTCON register. This interrupt can wake the device from the Sleep mode, or any of the Idle modes. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) DS40001412H-page 132 Additional PORTB Pin Functions Any read or write of PORTB to clear the mismatch condition (except when PORTB is the source or destination of a MOVFF instruction). Execute at least one instruction after reading or writing PORTB, then clear the flag bit, RBIF.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 10.3.3 A mismatch condition will continue to set the RBIF flag bit. Reading or writing PORTB will end the mismatch condition and allow the RBIF bit to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After either one of these Resets, the RBIF flag will continue to be set if a mismatch is present. Note: ALTERNATE FUNCTIONS PORTB is multiplexed with several peripheral functions (Table 10-5). The pins have TTL input buffers. Some of these pin functions can be relocated to alternate pins using the Control fuse bits in CONFIG3H. RB5 is the default pin for P2B (28-pin devices). Clearing the P2BMX bit moves the pin function to RC0. RB5 is also the default pin for the CCP3/P3A peripheral pin. Clearing the CCP3MX bit moves the pin function to the RC6 pin (28-pin devices) or RE0 (40/44-pin devices). If a change on the I/O pin may occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set. Furthermore, since a read or write on a port affects all bits of that port, care must be taken when using multiple pins in Interrupt-on-change mode. Changes on one pin may not be seen while servicing changes on another pin. Two other pin functions, T3CKI and CCP2/P2A, can be relocated from their default pins to PORTB pins by clearing the control fuses in CONFIG3H. Clearing T3CMX and CCP2MX moves the pin functions to RB5 and RB3, respectively. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. TABLE 10-5: Pin PORTB I/O SUMMARY Function RB0/INT0/CCP4/ FLT0/SRI/SS2/ AN12 RB1/INT1/P1C/ SCK2/SCL2/ C12IN3-/AN10 RB0 Note 1: 2: 3: Pin Type Buffer Type Description 0 0 O DIG LATB data output; not affected by analog input. 1 0 I TTL PORTB data input; disabled when analog input enabled. INT0 1 0 I ST External interrupt 0. CCP4(3) 0 0 O DIG Compare 4 output/PWM 4 output. 1 0 I ST Capture 4 input. FLT0 1 0 I ST PWM Fault input for ECCP auto-shutdown. SRI 1 0 I ST SR latch input. SS2(3) 1 0 I TTL SPI client select input (MSSP2). AN12 1 1 I AN Analog input 12. RB1 0 0 O DIG LATB data output; not affected by analog input. 1 0 I TTL PORTB data input; disabled when analog input enabled. INT1 1 0 I ST External Interrupt 1. P1C(3) 0 0 O DIG Enhanced CCP1 PWM output 3. SCK2(3) 0 0 O DIG MSSP2 SPI Clock output. 1 0 I ST MSSP2 SPI Clock input. 0 0 O DIG MSSP2 I2C Clock output. 1 0 I I2C MSSP2 I2C Clock input. C12IN3- 1 1 I AN Comparators C1 and C2 inverting input. AN10 1 1 I AN Analog input 10. SCL2(3) Legend: TRIS ANSEL Setting Setting AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. Function on PORTD and PORTE for PIC18(L)F4XK22 devices.  2010-2021 Microchip Technology Inc. DS40001412H-page 133 PIC18(L)F2X/4XK22 TABLE 10-5: PORTB I/O SUMMARY (CONTINUED) Pin Function RB2/INT2/CTED1/ P1B/SDI2/SDA2/ AN8 RB2 TRIS ANSEL Setting Setting 0 O DIG LATB data output; not affected by analog input. 1 0 I TTL PORTB data input; disabled when analog input enabled. INT2 1 0 I ST External interrupt 2. 1 0 I ST CTMU Edge 1 input. P1B(3) 0 0 O DIG Enhanced CCP1 PWM output 2. SDI2(3) 1 0 I ST MSSP2 SPI data input. (3) 0 0 O DIG MSSP2 I2C data output. I I2C MSSP2 I2C data input. AN8 1 1 I AN Analog input 8. 0 0 O DIG LATB data output; not affected by analog input. 1 0 I TTL PORTB data input; disabled when analog input enabled. CTED2 1 0 I ST CTMU Edge 2 input. P2A 0 0 O DIG Enhanced CCP1 PWM output 1. CCP2(2) 0 0 O DIG Compare 2 output/PWM 2 output. 1 0 I ST Capture 2 input. SDO2(2) 0 0 O DIG MSSP2 SPI data output. C12IN2- 1 1 I AN Comparators C1 and C2 inverting input. AN9 1 1 I AN Analog input 9. RB4 0 0 O DIG LATB data output; not affected by analog input. 1 0 I TTL PORTB data input; disabled when analog input enabled. IOC0 1 0 I TTL Interrupt-on-change pin. P1D 0 0 O DIG Enhanced CCP1 PWM output 4. T5G 1 0 I ST Timer5 external clock gate input. AN11 1 1 I AN Analog input 11. RB5 0 0 O DIG LATB data output; not affected by analog input. 1 0 I TTL PORTB data input; disabled when analog input enabled. RB4/IOC0/P1D/ T5G/AN11 RB5/IOC1/P2B/ P3A/CCP3/T3CKI/ T1G/AN13 3: 0 RB3 RB3/CTED2/P2A/ CCP2/SDO2/ C12IN2-/AN9 2: Description 0 1 Note 1: Buffer Type CTED1 SDA2 Legend: Pin Type IOC1 1 0 I TTL Interrupt-on-change pin 1. P2B(1)(3) 0 0 O DIG Enhanced CCP2 PWM output 2. P3A(1) 0 0 O DIG Enhanced CCP3 PWM output 1. CCP3(1) 0 0 O DIG Compare 3 output/PWM 3 output. 1 0 I ST Capture 3 input. T3CKI(2) 1 0 I ST Timer3 clock input. T1G 1 0 I ST Timer1 external clock gate input. AN13 1 1 I AN Analog input 13. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. Function on PORTD and PORTE for PIC18(L)F4XK22 devices. DS40001412H-page 134  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 10-5: Pin PORTB I/O SUMMARY (CONTINUED) Function RB6/KBI2/PGC RB6 TRIS ANSEL Setting Setting 0 1 IOC2 1 TX2(3) 1 CK2(3) 1 1 PGC RB7/KBI3/PGD RB7 x 0 1 IOC3 1 RX2(2), (3) 1 DT2(2), (3) 1 1 PGD x x Legend: Note 1: 2: 3: — — — — — — — — — — — — — — — Pin Type Buffer Type O DIG LATB data output; not affected by analog input. I TTL PORTB data input; disabled when analog input enabled. Description I TTL Interrupt-on-change pin. O DIG EUSART asynchronous transmit data output. O DIG EUSART synchronous serial clock output. I ST EUSART synchronous serial clock input. I ST In-Circuit Debugger and ICSPTM programming clock input. O DIG LATB data output; not affected by analog input. I TTL PORTB data input; disabled when analog input enabled. I TTL Interrupt-on-change pin. I ST EUSART asynchronous receive data input. O DIG EUSART synchronous serial data output. I ST EUSART synchronous serial data input. O DIG In-Circuit Debugger and ICSPTM programming data output. I ST In-Circuit Debugger and ICSPTM programming data input. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. Function on PORTD and PORTE for PIC18(L)F4XK22 devices.  2010-2021 Microchip Technology Inc. DS40001412H-page 135 PIC18(L)F2X/4XK22 TABLE 10-6: Name ANSELB REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 — — CCP2ASE ECCP2AS CCP2CON CCP3ASE CCP3CON Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 150 PSS2AC DC2B CCP3AS P3M INTCON Bit 4 CCP2AS P2M ECCP3AS Bit 5 GIE/GIEH PEIE/GIEL PSS2BD CCP2M PSS3AC DC3B 202 198 PSS3BD CCP3M 202 198 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 110 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 111 IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 153 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 152 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 148 SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 153 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T3SOSCEN T3SYNC PORTB T3CON TMR3CS T5GCON T1GSS T3RD16 TMR3ON 166 T5GPOL T5GTM T5GSPM T5GGO/DONE T5GVAL TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 152 WPUB T5GSS 167 TMR5GE TRISB Legend: Note 1: T3CKPS 167 — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB. Available on PIC18(L)F4XK22 devices. TABLE 10-7: Name CONFIGURATION REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 CONFIG4L DEBUG XINST — — — LVP(1) — STRVEN 349 Legend: Note 1: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB. Can only be changed when in high voltage programming mode. DS40001412H-page 136  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 10.4 PORTC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., disable the output driver). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (Table 10-8). The pins have Schmitt Trigger input buffers. Some of these pin functions can be relocated to alternate pins using the Control fuse bits in CONFIG3H. RC0 is the default pin for T3CKI. Clearing the T3CMX bit moves the pin function to RB5. RC1 is the default pin for the CCP2 peripheral pin. Clearing the CCP2MX bit moves the pin function to the RB3 pin. Two other pin functions, P2B and CCP3, can be relocated from their default pins to PORTC pins by clearing the control fuses in CONFIG3H. Clearing P2BMX and CCP3MX moves the pin functions to RC0 and RC6(1)/RE0(2), respectively. When enabling peripheral functions, care may be taken in defining TRIS bits for each PORTC pin. The EUSART and MSSP peripherals override the TRIS bit to make a pin an output or an input, depending on the peripheral configuration. Refer to the corresponding peripheral section for additional information. Note: On a Power-on Reset, these pins are configured as analog inputs. EXAMPLE 10-3: MOVLB CLRF CLRF MOVLW MOVWF MOVLW MOVWF 10.4.1 0xF PORTC ; ; ; ; LATC ; ; ; 0CFh ; ; ; TRISC ; ; ; 30h ; ; ANSELC ; ; ; INITIALIZING PORTC Set BSR for banked SFRs Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RC as inputs RC as outputs RC as inputs Value used to enable digital inputs RC dig input enable No ANSEL bits for RC RC dig input enable PORTC OUTPUT PRIORITY Each PORTC pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. Table 10-4 lists the PORTC pin functions from the highest to the lowest priority. Analog input functions, such as ADC, comparator and SR latch inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins.  2010-2021 Microchip Technology Inc. DS40001412H-page 137 PIC18(L)F2X/4XK22 TABLE 10-8: PORTC I/O SUMMARY Pin Name RC0/P2B/T3CKI/T3G/ T1CKI/SOSCO RC1/P2A/CCP2/SOSCI Function TRIS Setting ANSEL setting Pin Type Buffer Type RC0 0 — — O DIG LATC data output; not affected by analog input. I ST PORTC data input; disabled when analog input enabled. — — — — — — — O DIG Enhanced CCP2 PWM output 2. I ST Timer3 clock input. I ST Timer3 external clock gate input. I ST Timer1 clock input. O XTAL O DIG LATC data output; not affected by analog input. I ST PORTC data input; disabled when analog input enabled. O DIG Enhanced CCP2 PWM output 1. O DIG Compare 2 output/PWM 2 output. I ST Capture 2 input. 1 P2B(2) 0 T3CKI(1) 1 T3G 1 T1CKI 1 SOSCO x RC1 0 1 RC3/SCK1/SCL1/AN15 SOSCI x I XTAL RC2 0 0 O DIG LATC data output; not affected by analog input. 1 0 I ST PORTC data input; disabled when analog input enabled. 0 0 0 0 O DIG CTMU pulse generator output. P1A 0 0 O DIG Enhanced CCP1 PWM output 1. CCP1 0 0 O DIG Compare 1 output/PWM 1 output. 1 0 I ST Capture 1 input. T5CKI 1 0 I ST Timer5 clock input. AN14 1 1 I AN Analog input 14. RC3 0 0 O DIG LATC data output; not affected by analog input. 1 0 I ST PORTC data input; disabled when analog input enabled. 0 0 O DIG MSSP1 SPI Clock output. 1 0 I ST MSSP1 SPI Clock input. 0 0 O DIG MSSP1 I2C Clock output. 2 SCL1 1 0 I I C MSSP1 I2C Clock input. AN15 1 1 I AN Analog input 15. RC4 0 0 O DIG LATC data output; not affected by analog input. 1 0 I ST PORTC data input; disabled when analog input enabled. SDI1 1 0 I ST MSSP1 SPI data input. SDA1 0 0 O DIG MSSP1 I2C data output. 1 0 I I2C MSSP1 I2C data input. 1 1 I AN Analog input 16. AN16 Legend: Note 1: 2: 3: Secondary oscillator input. CTPLS SCK1 RC4/SDI1/SDA1/AN16 Secondary oscillator output. — — — — P2A CCP2(1) 1 RC2/CTPLS/P1A/ CCP1/T5CKI/AN14 Description AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. Function on PORTD and PORTE for PIC18(L)F4XK22 devices. DS40001412H-page 138  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 10-8: PORTC I/O SUMMARY (CONTINUED) Pin Name RC5/SDO1/AN17 RC6/P3A/CCP3/TX1/ CK1/AN18 RC7/P3B/RX1/DT1/ AN19 Function TRIS Setting ANSEL setting Pin Type Buffer Type Description RC5 0 0 O DIG LATC data output; not affected by analog input. 1 0 I ST PORTC data input; disabled when analog input enabled. SDO1 0 0 O DIG MSSP1 SPI data output. AN17 1 1 I AN Analog input 17. RC6 0 0 O DIG LATC data output; not affected by analog input. 1 0 I ST PORTC data input; disabled when analog input enabled. P3A(2), (3) 0 0 O CCP3(2), (3) 0 0 O DIG Compare 3 output/PWM 3 output. 1 0 I ST Capture 3 input. TX1 1 0 O DIG EUSART asynchronous transmit data output. CK1 1 0 O DIG EUSART synchronous serial clock output. 1 0 I ST EUSART synchronous serial clock input. AN18 1 1 I AN Analog input 18. RC7 0 0 O DIG LATC data output; not affected by analog input. 1 0 I ST PORTC data input; disabled when analog input enabled. P3B 0 0 O RX1 1 0 I ST EUSART asynchronous receive data in. DT1 1 0 O DIG EUSART synchronous serial data output. 1 0 I ST EUSART synchronous serial data input. 1 1 I AN Analog input 19. AN19 Legend: Note 1: 2: 3: CMOS Enhanced CCP3 PWM output 1. CMOS Enhanced CCP3 PWM output 2. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. Function on PORTD and PORTE for PIC18FXXK22 devices.  2010-2021 Microchip Technology Inc. DS40001412H-page 139 PIC18(L)F2X/4XK22 TABLE 10-9: Name ANSELC REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 ANSC7 ANSC6 CCP1ASE ECCP1AS CCP1CON Bit 3 Bit 2 ANSC5 ANSC4 ANSC3 ANSC2 PSS1AC DC1B CCP2ASE CCP2CON Bit 4 CCP1AS P1M ECCP2AS Bit 5 CCP2AS P2M Bit 1 Bit 0 Register on Page — — 150 PSS1BD CCP1M PSS2AC DC2B 202 198 PSS2BD CCP2M 202 198 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 323 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 152 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 148 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA WCOL SSPOV SSPEN CKP CTMUCONH LATC SSP1CON1 T1CON T3CON T3GCON T5CON TRISC TXSTA1 Legend: Note 1: TMR1CS TMR3CS TMR3GE T3GPOL SSPM T1CKPS T1SOSCEN T1SYNC T1RD16 TMR1ON T3CKPS T3SOSCEN T3SYNC T3RD16 TMR3ON T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS 166 166 167 T5SOSCEN T5SYNC T5RD16 TMR5ON 166 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 TMR5CS T5CKPS 153 253 — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC. Available on PIC18(L)F4XK22 devices. TABLE 10-10: CONFIGURATION REGISTERS ASSOCIATED WITH PORTC Name CONFIG3H Legend: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC. DS40001412H-page 140  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 10.5 Note: PORTD Registers PORTD is only available on 40-pin and 44-pin devices. PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., disable the output driver). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register read and write the latched output value for PORTD. 10.5.1 PORTD OUTPUT PRIORITY Each PORTD pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. Table 10-4 lists the PORTD pin functions from the highest to the lowest priority. Analog input functions, such as ADC, comparator and SR latch inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. All of the PORTD pins are multiplexed with analog and digital peripheral modules. See Table 10-11. Note: On a Power-on Reset, these pins are configured as analog inputs. EXAMPLE 10-4: MOVLB CLRF CLRF MOVLW MOVWF MOVLW MOVWF 0xF PORTD ; ; ; ; LATD ; ; ; 0CFh ; ; ; TRISD ; ; ; 30h ; ; ANSELD ; ; INITIALIZING PORTD Set BSR for banked SFRs Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD as inputs RD as outputs RD as inputs Value used to enable digital inputs RD dig input enable RC dig input enable  2010-2021 Microchip Technology Inc. DS40001412H-page 141 PIC18(L)F2X/4XK22 TABLE 10-11: PORTD I/O SUMMARY Pin Name Function RD0/SCK2/SCL2/AN20 RD0 SCK2 SCL2 RD1/CCP4/SDI2/SDA2/ AN21 RD3/P2C/SS2/AN23 RD5/P1B/AN25 Legend: Note 1: 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. 0 0 O DIG MSSP2 SPI Clock output. 1 0 I ST MSSP2 SPI Clock input. 0 0 O DIG MSSP2 I2C Clock output. I I2C MSSP2 I2C Clock input. 0 AN20 1 1 I AN Analog input 20. RD1 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. 0 0 O DIG Compare 4 output/PWM 4 output. 1 0 I ST Capture 4 input. SDI2 1 0 I ST MSSP2 SPI data input. SDA2 0 0 O DIG MSSP2 I2C data output. 1 0 I I2C MSSP2 I2C data input. AN21 1 1 I AN Analog input 21. RD2 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. P2B(1) 0 0 O DIG Enhanced CCP2 PWM output 2. AN22 1 1 I AN Analog input 22. RD3 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. 0 0 O DIG Enhanced CCP2 PWM output 4. P2C RD4/P2D/SDO2/AN24 Description 1 CCP4 RD2/P2B/AN22 TRIS ANSEL Pin Buffer Setting setting Type Type SS2 1 0 I TTL MSSP2 SPI client select input. AN23 1 1 I AN Analog input 23. RD4 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. P2D 0 0 O DIG Enhanced CCP2 PWM output 3. SDO2 0 0 O DIG MSSP2 SPI data output. AN24 1 1 I AN Analog input 24. RD5 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. P1B 0 0 O DIG Enhanced CCP1 PWM output 2. AN25 1 1 I AN Analog input 25. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. DS40001412H-page 142  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 10-11: PORTD I/O SUMMARY (CONTINUED) Pin Name RD6/P1C/TX2/CK2/ AN26 RD7/P1D/RX2/DT2/ AN27 Function RD6 Note 1: Description 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. P1C 0 0 O DIG Enhanced CCP1 PWM output 3. TX2 1 0 O DIG EUSART asynchronous transmit data output. CK2 1 0 O DIG EUSART synchronous serial clock output. 1 0 I ST EUSART synchronous serial clock input. AN26 1 1 I AN Analog input 26. RD7 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. P1D 0 0 O DIG Enhanced CCP1 PWM output 4. RX2 1 0 I ST EUSART asynchronous receive data in. DT2 1 0 O DIG EUSART synchronous serial data output. 1 0 I ST EUSART synchronous serial data input. 1 1 I AN Analog input 27. AN27 Legend: TRIS ANSEL Pin Buffer Setting setting Type Type AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set.  2010-2021 Microchip Technology Inc. DS40001412H-page 143 PIC18(L)F2X/4XK22 TABLE 10-12: REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 150 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 Name CCP1CON CCP2CON CCP4CON (1) P1M DC1B CCP1M 198 P2M DC2B CCP2M 198 DC4B CCP4M 198 — — LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 152 PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 148 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 — — — SLRE SLRD SLRC SLRB SLRA 153 SSPEN TRISD3 TRISD2 TRISD0 151 LATD SLRCON(1) SSP2CON1 WCOL SSPOV TRISD(1) TRISD7 TRISD6 TRISD5 CKP TRISD4 SSPM TRISD1 253 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTD. Note 1: Available on PIC18(L)F4XK22 devices. TABLE 10-13: CONFIGURATION REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CONFIG3H MCLRE — P2BMX T3CMX HFOFST Bit 2 Bit 1 Bit 0 CCP3MX PBADEN CCP2MX Register on Page 348 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTD. DS40001412H-page 144  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 10.6 PORTE Registers Depending on the particular PIC18(L)F2X/4XK22 device selected, PORTE is implemented in two different ways. 10.6.1 The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., disable the output driver). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). TRISE controls the direction of the REx pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. On a Power-on Reset, RE are configured as analog inputs. The fourth pin of PORTE (MCLR/VPP/RE3) is an input only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin; as such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device’s Master Clear input. In either configuration, RE3 also functions as the programming voltage input during programming. Note: CLRF CLRF PORTE ON 40/44-PIN DEVICES For PIC18(L)F2X/4XK22 devices, PORTE is a 4-bit wide port. Three pins (RE0/P3A/CCP3/AN5, RE1/P3B/ AN6 and RE2/CCP5/AN7) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘0’s. Note: EXAMPLE 10-5: On a Power-on Reset, RE3 is enabled as a digital input only if Master Clear functionality is disabled. CLRF MOVLW MOVWF 10.6.2 PORTE ; ; ; LATE ; ; ; ANSELE ; ; 05h ; ; ; TRISE ; ; ; INITIALIZING PORTE Initialize PORTE by clearing output data latches Alternate method to clear output data latches Configure analog pins for digital only Value used to initialize data direction Set RE as input RE as output RE as input PORTE ON 28-PIN DEVICES For PIC18F2XK22 devices, PORTE is only available when Master Clear functionality is disabled (MCLR = 0). In these cases, PORTE is a single bit, input only port comprised of RE3 only. The pin operates as previously described. 10.6.3 RE3 WEAK PULL-UP The port RE3 pin has an individually controlled weak internal pull-up. When set, the WPUE3 (TRISE) bit enables the RE3 pin pull-up. The RBPU bit of the INTCON2 register controls pull-ups on both PORTB and PORTE. When RBPU = 0, the weak pull-ups become active on all pins which have the WPUE3 or WPUBx bits set. When set, the RBPU bit disables all weak pullups. The pull-ups are disabled on a Power-on Reset. When the RE3 port pin is configured as MCLR, (CONFIG3H, MCLRE=1 and CONFIG4L, LVP=0), or configured for Low Voltage Programming, (MCLRE=x and LVP=1), the pull-up is always enabled and the WPUE3 bit has no effect. 10.6.4 PORTE OUTPUT PRIORITY Each PORTE pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. Table 10-4 lists the PORTE pin functions from the highest to the lowest priority. Analog input functions, such as ADC, comparator and SR latch inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below.  2010-2021 Microchip Technology Inc. DS40001412H-page 145 PIC18(L)F2X/4XK22 TABLE 10-14: PORTE I/O SUMMARY Pin Function RE0/P3A/CCP3/AN5 RE0 P3A(1) CCP3(1) RE1/P3B/AN6 RE2/CCP5/AN7 Legend: Note 1: Buffer Type Description 0 0 O DIG LATE data output; not affected by analog input. 1 0 I ST PORTE data input; disabled when analog input enabled. 0 0 O DIG Enhanced CCP3 PWM output. 0 0 O DIG Compare 3 output/PWM 3 output. 1 0 I ST Capture 3 input. AN5 1 1 I AN Analog input 5. RE1 0 0 O DIG LATE data output; not affected by analog input. 1 0 I ST PORTE data input; disabled when analog input enabled. P3B 0 0 O DIG Enhanced CCP3 PWM output. AN6 1 1 I AN Analog input 6. RE2 0 0 O DIG LATE data output; not affected by analog input. 1 0 I ST PORTE data input; disabled when analog input enabled. 0 0 O DIG Compare 5 output/PWM 5 output. CCP5 RE3/VPP/MCLR TRIS ANSEL Pin Setting Setting Type 1 0 I ST Capture 5 input. AN7 1 1 I AN Analog input 7. RE3 — — I ST PORTE data input; enabled when Configuration bit MCLRE = 0. VPP — — P AN Programming voltage input; always available MCLR — — I ST Active-low Master Clear (device Reset) input; enabled when configuration bit MCLRE = 1. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Alternate pin assignment for P3A/CCP3 when Configuration bit CCP3MX is clear. DS40001412H-page 146  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 10-15: REGISTERS ASSOCIATED WITH PORTE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page ANSELE(1) — — — — — ANSE2 ANSE1 ANSE0 151 INTCON2 RBPU INTEDG2 — TMR0IP — RBIP 110 LATE(1) — — — — — LATE2 LATE1 LATE0 152 PORTE — — — — RE3 RE2(1) RE1(1) RE0(1) 149 SLRC SLRB SLRA SLRCON TRISE INTEDG0 INTEDG1 — — — WPUE3 — — (1) SLRE — SLRD (1) — TRISE2(1) TRISE1(1) TRISE0(1) 153 151 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTE. Note 1: Available on PIC18(L)F4XK22 devices. TABLE 10-16: CONFIGURATION REGISTERS ASSOCIATED WITH PORTE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CONFIG3H MCLRE — P2BMX T3CMX HFOFST CONFIG4L DEBUG XINST — — — Bit 2 Bit 1 Bit 0 CCP3MX PBADEN CCP2MX LVP(1) — STRVEN Reset Values on page 348 349 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Interrupts. Note 1: Can only be changed when in high voltage programming mode.  2010-2021 Microchip Technology Inc. DS40001412H-page 147 PIC18(L)F2X/4XK22 10.7 Port Analog Control 10.8 Most port pins are multiplexed with analog functions such as the Analog-to-Digital Converter and comparators. When these I/O pins are to be used as analog inputs it is necessary to disable the digital input buffer to avoid excessive current caused by improper biasing of the digital input. Individual control of the digital input buffers on pins which share analog functions is provided by the ANSELA, ANSELB, ANSELC, ANSELD and ANSELE registers. Setting an ANSx bit high will disable the associated digital input buffer and cause all reads of that pin to return ‘0’ while allowing analog functions of that pin to operate correctly. Port Slew Rate Control The output slew rate of each port is programmable to select either the standard transition rate or a reduced transition rate of approximately 0.1 times the standard to minimize EMI. The reduced transition time is the default slew rate for all ports. The state of the ANSx bits has no affect on digital output functions. A pin with the associated TRISx bit clear and ANSx bit set will still operate as a digital output but the input mode will be analog. This can cause unexpected behavior when performing readmodify-write operations on the affected port. All ANSEL register bits default to ‘1’ upon POR and BOR, disabling digital inputs for their associated port pins. All TRIS register bits default to ‘1’ upon POR or BOR, disabling digital outputs for their associated port pins. As a result, all port pins that have an ANSEL register will default to analog inputs upon POR or BOR. 10.9 Register Definitions – Port Control PORTX(1): PORTx REGISTER REGISTER 10-1: R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x Rx7 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 Note 1: 2: Rx: PORTx I/O bit values(2) Register Description for PORTA, PORTB, PORTC and PORTD. Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O pin values. DS40001412H-page 148  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 10-2: U-0 PORTE: PORTE REGISTER U-0 — U-0 — — U-0 — R/W-u/x RE3 (1) R/W-u/x RE2 (2), (3) R/W-u/x (2), (3) RE1 R/W-u/x RE0(2), (3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-4 Unimplemented: Read as ‘0’ bit 3 RE3: PORTE Input bit value(1) bit 2-0 RE: PORTE I/O bit values(2), (3) Note 1: 2: 3: Port is available as input only when MCLRE = 0. Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O pin values. Available on PIC18(L)F4XK22 devices. REGISTER 10-3: ANSELA – PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 ANSA5: RA5 Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled bit 4 Unimplemented: Read as ‘0’ bit 3-0 ANSA: RA Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled  2010-2021 Microchip Technology Inc. x = Bit is unknown DS40001412H-page 149 PIC18(L)F2X/4XK22 REGISTER 10-4: ANSELB – PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB: RB Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled REGISTER 10-5: x = Bit is unknown ANSELC – PORTC ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 ANSC: RC Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled bit 1-0 Unimplemented: Read as ‘0’ REGISTER 10-6: x = Bit is unknown ANSELD – PORTD ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ANSD: RD Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled DS40001412H-page 150  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 10-7: U-0 ANSELE – PORTE ANALOG SELECT REGISTER U-0 — U-0 — — U-0 U-0 — — R/W-1 ANSE2 (1) R/W-1 ANSE1 (1) R/W-1 ANSE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ANSE: RE Analog Select bit(1) 1 = Digital input buffer disabled 0 = Digital input buffer enabled Note 1: x = Bit is unknown Available on PIC18(L)F4XK22 devices only. REGISTER 10-8: TRISx: PORTx TRI-STATE REGISTER(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISx7 TRISx6 TRISx5 TRISx4 TRISx3 TRISx2 TRISx1 TRISx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown TRISx: PORTx Tri-State Control bit 1 = PORTx pin configured as an input (tri-stated) 0 = PORTx pin configured as an output Register description for TRISA, TRISB, TRISC and TRISD. REGISTER 10-9: R/W-1 TRISE: PORTE TRI-STATE REGISTER U-0 WPUE3 U-0 — — U-0 — U-0 — R/W-1 TRISE2 (1) R/W-1 (1) TRISE1 R/W-1 TRISE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUE3: Weak Pull-up Register bits 1 = Pull-up enabled on PORT pin 0 = Pull-up disabled on PORT pin bit 6-3 Unimplemented: Read as ‘0’ bit 2-0 TRISE: PORTE Tri-State Control bit(1) 1 = PORTE pin configured as an input (tri-stated) 0 = PORTE pin configured as an output Note 1: x = Bit is unknown Available on PIC18(L)F4XK22 devices only.  2010-2021 Microchip Technology Inc. DS40001412H-page 151 PIC18(L)F2X/4XK22 REGISTER 10-10: LATx: PORTx OUTPUT LATCH REGISTER(1) R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATx7 LATx6 LATx5 LATx4 LATx3 LATx2 LATx1 LATx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared LATx: PORTx Output Latch bit value(2) bit 7-0 Note 1: 2: x = Bit is unknown Register Description for LATA, LATB, LATC and LATD. Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O pin values. REGISTER 10-11: LATE: PORTE OUTPUT LATCH REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u — — — — — LATE2 LATE1 LATE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LATE: PORTE Output Latch bit value(2) Note 1: 2: x = Bit is unknown Available on PIC18(L)F4XK22 devices only. Writes to PORTE are written to corresponding LATE register. Reads from PORTE register is return of I/O pin values. REGISTER 10-12: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown WPUB: Weak Pull-up Register bits 1 = Pull-up enabled on PORT pin 0 = Pull-up disabled on PORT pin DS40001412H-page 152  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 10-13: IOCB: INTERRUPT-ON-CHANGE PORTB CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 IOCB7 IOCB6 IOCB5 IOCB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Note 1: x = Bit is unknown IOCB: Interrupt-on-Change PORTB control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled Interrupt-on-change requires that the RBIE bit (INTCON) is set. REGISTER 10-14: SLRCON: SLEW RATE CONTROL REGISTER U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SLRE(1) SLRD(1) SLRC SLRB SLRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 SLRE: PORTE Slew Rate Control bit(1) 1 = All outputs on PORTE slew at a limited rate 0 = All outputs on PORTE slew at the standard rate bit 3 SLRD: PORTD Slew Rate Control bit(1) 1 = All outputs on PORTD slew at a limited rate 0 = All outputs on PORTD slew at the standard rate bit 2 SLRC: PORTC Slew Rate Control bit 1 = All outputs on PORTC slew at a limited rate 0 = All outputs on PORTC slew at the standard rate bit 1 SLRB: PORTB Slew Rate Control bit 1 = All outputs on PORTB slew at a limited rate 0 = All outputs on PORTB slew at the standard rate bit 0 SLRA: PORTA Slew Rate Control bit 1 = All outputs on PORTA slew at a limited rate(2) 0 = All outputs on PORTA slew at the standard rate Note 1: 2: x = Bit is unknown These bits are available on PIC18(L)F4XK22 devices. The slew rate of RA6 defaults to standard rate when the pin is used as CLKOUT.  2010-2021 Microchip Technology Inc. DS40001412H-page 153 PIC18(L)F2X/4XK22 11.0 TIMER0 MODULE The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection. It is both readable and writable. The Timer0 module incorporates the following features: • Software selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit, software programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow 11.1 A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1. Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. Register Definitions: Timer0 Control REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA R/W-1 R/W-1 R/W-1 TOPS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value DS40001412H-page 154  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 11.2 Timer0 Operation 11.3 Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit of the T0CON register. In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 11.4 “Prescaler”). Timer0 incrementing is inhibited for two instruction cycles following a TMR0 register write. The user can work around this by adjusting the value written to the TMR0 register to compensate for the anticipated missing increments. The Counter mode is selected by setting the T0CS bit (= 1). In this mode, Timer0 increments either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE of the T0CON register; clearing this bit selects the rising edge. Restrictions on the external clock input are discussed below. Timer0 Reads and Writes in 16-Bit Mode TMR0H is not the actual high byte of Timer0 in 16-bit mode; it is actually a buffered version of the real high byte of Timer0 which is neither directly readable nor writable (refer to Figure 11-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without the need to verify that the read of the high and low byte were valid. Invalid reads could otherwise occur due to a rollover between successive reads of the high and low byte. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. Writing to TMR0H does not directly affect Timer0. Instead, the high byte of Timer0 is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. An external clock source can be used to drive Timer0; however, it must meet certain requirements (see Table 27-12) to ensure that the external clock can be synchronized with the internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter. FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 1 T0CKI pin T0SE T0CS T0PS PSA Note: Programmable Prescaler 0 Sync with Internal Clocks TMR0L Set TMR0IF on Overflow (2 TCY Delay) 8 3 8 Internal Data Bus Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.  2010-2021 Microchip Technology Inc. DS40001412H-page 155 PIC18(L)F2X/4XK22 FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 Sync with Internal Clocks 1 Programmable Prescaler T0CKI pin T0SE T0CS 0 TMR0 High Byte TMR0L 8 Set TMR0IF on Overflow (2 TCY Delay) 3 Read TMR0L T0PS Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: 11.4 Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. Prescaler 11.4.1 An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; its value is set by the PSA and T0PS bits of the T0CON register which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When the prescaler is assigned, prescale values from 1:2 through 1:256 in integer power-of-2 increments are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, etc.) clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment. TABLE 11-1: Name INTCON INTCON2 T0CON SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution. 11.5 Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or from FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF flag bit. The interrupt can be masked by clearing the TMR0IE bit of the INTCON register. Before re-enabling the interrupt, the TMR0IF bit must be cleared by software in the Interrupt Service Routine. Since Timer0 is shut down in Sleep mode, the TMR0 interrupt cannot awaken the processor from Sleep. REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL RBPU TMR0ON Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 — TMR0IP — RBIP INTEDG0 INTEDG1 INTEDG2 T08BIT T0CS T0SE PSA T0PS 110 154 TMR0H Timer0 Register, High Byte — TMR0L Timer0 Register, Low Byte — TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by Timer0. DS40001412H-page 156  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 12.0 TIMER1/3/5 MODULE WITH GATE CONTROL • • • • • • The Timer1/3/5 module is a 16-bit timer/counter with the following features: • • • • • • • • 16-bit timer/counter register pair (TMRxH:TMRxL) Programmable internal or external clock source 2-bit prescaler Dedicated Secondary 32 kHz oscillator circuit Optionally synchronized comparator out Multiple Timer1/3/5 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) • 16-Bit Read/Write Operation • Time base for the Capture/Compare function FIGURE 12-1: Special Event Trigger (with CCP/ECCP) Selectable Gate Source Polarity Gate Toggle mode Gate Single-pulse mode Gate Value Status Gate Event Interrupt Figure 12-1 is a block diagram of the Timer1/3/5 module. TIMER1/3/5 BLOCK DIAGRAM TxGSS TxGSPM 00 TxG Timer2/4/6 Match PR2/4/6 01 sync_C1OUT(7) 0 TxG_IN Single Pulse 10 sync_C2OUT(7) D Q CK R Q 11 TMRxON TxGVAL 0 1 Acq. Control 1 Q1 Data Bus D Q RD TXGCON EN Interrupt TxGGO/DONE Set TMRxGIF det TxGTM TxGPOL TMRxGE Set flag bit TMRxIF on Overflow TMRxON To Comparator Module TMRx(2),(4) TMRxH EN TMRxL Q D TxCLK Synchronized clock input 0 1 Secondary Oscillator Module See Figure 2-4 TMRxCS Reserved 1 (5) ,(6) TxSOSCEN TxCLK_EXT_SRC (1) 0 TxCKI Note TxSYNC SOSCOUT 11 10 FOSC Internal Clock 01 FOSC/4 Internal Clock 00 Synchronize(3),(7) Prescaler 1, 2, 4, 8 det 2 TxCKPS FOSC/2 Internal Clock Sleep input 1: 2: 3: 4: 5: 6: ST Buffer is high speed type when using TxCKI. Timer1/3/5 register increments on rising edge. Synchronize does not operate while in Sleep. See Figure 12-2 for 16-Bit Read/Write Mode Block Diagram. T1CKI is not available when the secondary oscillator is enabled. (SOSCGO = 1 or TXSOSCEN = 1) T3CKI is not available when the secondary oscillator is enabled, unless T3CMX = 1. 7: Synchronized comparator output may not be used in conjunction with synchronized TxCKI.  2010-2021 Microchip Technology Inc. DS40001412H-page 157 PIC18(L)F2X/4XK22 12.1 Timer1/3/5 Operation 12.2.1 When the internal clock source is selected the TMRxH:TMRxL register pair will increment on multiples of FOSC as determined by the Timer1/3/5 prescaler. The Timer1/3/5 module is a 16-bit incrementing counter which is accessed through the TMRxH:TMRxL register pair. Writes to TMRxH or TMRxL directly update the counter. When the FOSC internal clock source is selected, the Timer1/3/5 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1/3/5 value. To utilize the full resolution of Timer1/3/5, an asynchronous input signal must be used to gate the Timer1/3/5 clock input. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. The following asynchronous sources may be used: Timer1/3/5 is enabled by configuring the TMRxON and TMRxGE bits in the TxCON and TxGCON registers, respectively. Table 12-1 displays the Timer1/3/5 enable selections. TABLE 12-1: 12.2.2 0 0 Off 0 1 Off 1 0 Always On 1 1 Count Enabled When enabled to count, Timer1/3/5 is incremented on the rising edge of the external clock input of the TxCKI pin. This external clock source can be synchronized to the microcontroller system clock or it can run asynchronously. When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated secondary internal oscillator circuit. Clock Source Selection The TMRxCS and TxSOSCEN bits of the TxCON register are used to select the clock source for Timer1/3/5. The dedicated Secondary Oscillator circuit can be used as the clock source for Timer1, Timer3 and Timer5, simultaneously. Any of the TxSOSCEN bits will enable the Secondary Oscillator circuit and select it as the clock source for that particular timer. Table 12-2 displays the clock source selections. TABLE 12-2: TMRxCS1 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1/3/5 module may work as a timer or a counter. Timer1/3/5 Operation TMRxGE 12.2 • Asynchronous event on the TxG pin to Timer1/3/5 Gate • C1 or C2 comparator input to Timer1/3/5 Gate TIMER1/3/5 ENABLE SELECTIONS TMRxON INTERNAL CLOCK SOURCE Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • • • • Timer1/3/5 enabled after POR Write to TMRxH or TMRxL Timer1/3/5 is disabled Timer1/3/5 is disabled (TMRxON = 0) when TxCKI is high then Timer1/3/5 is enabled (TMRxON=1) when TxCKI is low. CLOCK SOURCE SELECTIONS TMRxCS0 TxSOSCEN Clock Source 0 1 x System Clock (FOSC) 0 0 x Instruction Clock (FOSC/4) 1 0 0 External Clocking on TxCKI Pin 1 0 1 Osc.Circuit On SOSCI/SOSCO Pins DS40001412H-page 158  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 12.3 Timer1/3/5 Prescaler Timer1/3/5 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The TxCKPS bits of the TxCON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMRxH or TMRxL. 12.4 Secondary Oscillator A dedicated secondary low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. The oscillator circuit is enabled by setting the TxSOSCEN bit of the TxCON register, the SOSCGO bit of the OSCCON2 register or by selecting the secondary oscillator as the system clock by setting SCS = 01 in the OSCCON register. The oscillator will continue to run during Sleep. Note: 12.5 The oscillator requires a start-up and stabilization time before use. Thus, TxSOSCEN may be set and a suitable delay observed prior to enabling Timer1/3/5. Timer1/3/5 Operation in Asynchronous Counter Mode If control bit TxSYNC of the TxCON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake up the processor. However, special precautions in software are needed to read/write the timer (see Section 12.5.1 “Reading and Writing Timer1/3/5 in Asynchronous Counter Mode”). Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment.  2010-2021 Microchip Technology Inc. 12.5.1 READING AND WRITING TIMER1/3/5 IN ASYNCHRONOUS COUNTER MODE Reading TMRxH or TMRxL while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user may keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMRxH:TMRxL register pair. 12.6 Timer1/3/5 16-Bit Read/Write Mode Timer1/3/5 can be configured to read and write all 16 bits of data, to and from, the 8-bit TMRxL and TMRxH registers, simultaneously. The 16-bit read and write operations are enabled by setting the RD16 bit of the TxCON register. To accomplish this function, the TMRxH register value is mapped to a buffer register called the TMRxH buffer register. While in 16-Bit mode, the TMRxH register is not directly readable or writable and all read and write operations take place through the use of this TMRxH buffer register. When a read from the TMRxL register is requested, the value of the TMRxH register is simultaneously loaded into the TMRxH buffer register. When a read from the TMRxH register is requested, the value is provided from the TMRxH buffer register instead. This provides the user with the ability to accurately read all 16 bits of the Timer1/3/5 value from a single instance in time. In contrast, when not in 16-Bit mode, the user must read each register separately and determine if the values have become invalid due to a rollover that may have occurred between the read operations. When a write request of the TMRxL register is requested, the TMRxH buffer register is simultaneously updated with the contents of the TMRxH register. The value of TMRxH must be preloaded into the TMRxH buffer register prior to the write request for the TMRxL register. This provides the user with the ability to write all 16 bits to the TMRxL:TMRxH register pair at the same time. Any requests to write to the TMRxH directly does not clear the Timer1/3/5 prescaler value. The prescaler value is only cleared through write requests to the TMRxL register. DS40001412H-page 159 PIC18(L)F2X/4XK22 FIGURE 12-2: TIMER1/3/5 16-BIT READ/WRITE MODE BLOCK DIAGRAM From Timer1 Circuitry TMR1 High Byte TMR1L 8 Set TMR1IF on Overflow Read TMR1L Write TMR1L 8 8 TMR1H 8 8 12.7.2 The Timer1/3/5 Gate source can be selected from one of four different sources. Source selection is controlled by the TxGSS bits of the TxGCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the TxGPOL bit of the TxGCON register. TABLE 12-4: TxGSS 12.7 Timer1/3/5 Gate can also be driven by multiple selectable sources. 12.7.1 TIMER1/3/5 GATE ENABLE The Timer1/3/5 Gate Enable mode is enabled by setting the TMRxGE bit of the TxGCON register. The polarity of the Timer1/3/5 Gate Enable mode is configured using the TxGPOL bit of the TxGCON register. When Timer1/3/5 Gate Enable mode is enabled, Timer1/3/5 will increment on the rising edge of the Timer1/3/5 clock source. When Timer1/3/5 Gate Enable mode is disabled, no incrementing will occur and Timer1/3/5 will hold the current count. See Figure 12-4 for timing details. TABLE 12-3: TIMER1/3/5 GATE ENABLE SELECTIONS Timer1/3/5 Operation TxCLK TxGPOL TxG  0 0 Counts  0 1 Holds Count  1 0 Holds Count  1 1 Counts DS40001412H-page 160 Timer1/3/5 Gate Source Timer1/3/5 Gate Pin 01 Timer2/4/6 Match to PR2/4/6 (TMR2/4/6 increments to match PR2/4/6) 10 Comparator 1 Output sync_C1OUT (optionally Timer1/3/5 synchronized output) 11 Comparator 2 Output sync_C2OUT (optionally Timer1/3/5 synchronized output) Timer1/3/5 Gate Timer1/3/5 can be configured to count freely or the count can be enabled and disabled using Timer1/3/5 Gate circuitry. This is also referred to as Timer1/3/5 Gate Enable. TIMER1/3/5 GATE SOURCES 00 Internal Data Bus Block Diagram of Timer1 Example of TIMER1/3/5 TIMER1/3/5 GATE SOURCE SELECTION The Gate resource, Timer2 Match to PR2, changes between Timer2, Timer4 and Timer6 depending on which of the three 16-bit Timers, Timer1, Timer3 or Timer5, is selected. See Table 12-5 to determine which Timer2/4/6 Match to PR2/4/6 combination is available for the 16-bit timer being used. TABLE 12-5: GATE RESOURCES FOR TIMER2/4/6 MATCH TO PR2/4/6 Timer1/3/5 Resource Timer1/3/5 Gate Match Selection Timer1 TMR2 Match to PR2 Timer3 TMR4 Match to PR4 Timer5 TMR6 Match to PR6 12.7.2.1 TxG Pin Gate Operation The TxG pin is one source for Timer1/3/5 Gate Control. It can be used to supply an external source to the Timer1/3/5 Gate circuitry. 12.7.2.2 Timer2/4/6 Match Gate Operation The TMR2/4/6 register will increment until it matches the value in the PR2/4/6 register. On the very next increment cycle, TMR2/4/6 will be reset to 00h. When this Reset occurs, a low-to-high pulse will automatically be generated and internally supplied to the Timer1/3/5 Gate circuitry. When both TMR2/4/6 and Timer 1/3/5 use FOSC/4 as the clock source then Timer 1/3/5 will increment once during the TMR2/4/6 overflow pulse. This concatenation creates a 24-bit timer. When used in conjunction with the CCP special event trigger very long periodic interrupts can be generated.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 12.7.2.3 Comparator C1 Gate Operation The output resulting from a Comparator 1 operation can be selected as a source for Timer1/3/5 Gate Control. The Comparator 1 output (sync_C1OUT) can be synchronized to the Timer1/3/5 clock or left asynchronous. For more information see Section 18.8.4 “Synchronizing Comparator Output to Timer1”. 12.7.2.4 Comparator C2 Gate Operation The output resulting from a Comparator 2 operation can be selected as a source for Timer1/3/5 Gate Control. The Comparator 2 output (sync_C2OUT) can be synchronized to the Timer1/3/5 clock or left asynchronous. For more information see Section 18.8.4 “Synchronizing Comparator Output to Timer1”. 12.7.3 TIMER1/3/5 GATE TOGGLE MODE When Timer1/3/5 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1/3/5 gate signal, as opposed to the duration of a single level pulse. The Timer1/3/5 Gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 12-5 for timing details. Timer1/3/5 Gate Toggle mode is enabled by setting the TxGTM bit of the TxGCON register. When the TxGTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. 12.7.4 TIMER1/3/5 GATE SINGLE-PULSE MODE When Timer1/3/5 Gate Single-Pulse mode is enabled, it is possible to capture a single-pulse gate event. Timer1/3/5 Gate Single-Pulse mode is first enabled by setting the TxGSPM bit in the TxGCON register. Next, the TxGGO/DONE bit in the TxGCON register must be set. The Timer1/3/5 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the TxGGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1/3/5 until the TxGGO/DONE bit is once again set in software. Clearing the TxGSPM bit of the TxGCON register will also clear the TxGGO/DONE bit. See Figure 12-6 for timing details. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1/3/5 Gate source to be measured. See Figure 12-7 for timing details. 12.7.5 TIMER1/3/5 GATE VALUE STATUS When Timer1/3/5 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the TxGVAL bit in the TxGCON register. The TxGVAL bit is valid even when the Timer1/3/5 Gate is not enabled (TMRxGE bit is cleared). 12.7.6 TIMER1/3/5 GATE EVENT INTERRUPT When Timer1/3/5 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of TxGVAL occurs, the TMRxGIF flag bit in the PIR3 register will be set. If the TMRxGIE bit in the PIE3 register is set, then an interrupt will be recognized. The TMRxGIF flag bit operates even when the Timer1/3/5 Gate is not enabled (TMRxGE bit is cleared). For more information on selecting high or low priority status for the Timer1/3/5 Gate Event Interrupt see Section 9.0 “Interrupts”.  2010-2021 Microchip Technology Inc. DS40001412H-page 161 PIC18(L)F2X/4XK22 12.8 Timer1/3/5 Interrupt The Timer1/3/5 register pair (TMRxH:TMRxL) increments to FFFFh and rolls over to 0000h. When Timer1/3/5 rolls over, the Timer1/3/5 interrupt flag bit of the PIR1/2/5 register is set. To enable the interrupt on rollover, the user must set these bits: • • • • TMRxON bit of the TxCON register TMRxIE bits of the PIE1, PIE2 or PIE5 registers PEIE/GIEL bit of the INTCON register GIE/GIEH bit of the INTCON register The interrupt is cleared by clearing the TMRxIF bit in the Interrupt Service Routine. For more information on selecting high or low priority status for the Timer1/3/5 Overflow Interrupt, see Section 9.0 “Interrupts”. Note: 12.9 The TMRxH:TMRxL register pair and the TMRxIF bit may be cleared before enabling interrupts. Timer1/3/5 Operation During Sleep Timer1/3/5 can only operate during Sleep when set up in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: • • • • • TMRxON bit of the TxCON register must be set TMRxIE bit of the PIE1/2/5 register must be set PEIE/GIEL bit of the INTCON register must be set TxSYNC bit of the TxCON register must be set TMRxCS bits of the TxCON register must be configured • TxSOSCEN bit of the TxCON register must be configured 12.10 ECCP/CCP Capture/Compare Time Base The CCP modules use the TMRxH:TMRxL register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMRxH:TMRxL register pair is copied into the CCPRxH:CCPRxL register pair on a configured event. In Compare mode, an event is triggered when the value CCPRxH:CCPRxL register pair matches the value in the TMRxH:TMRxL register pair. This event can be a Special Event Trigger. For more information, see “Capture/Compare/PWM Modules”. Section 14.0 12.11 ECCP/CCP Special Event Trigger When any of the CCP’s are configured to trigger a special event, the trigger will clear the TMRxH:TMRxL register pair. This special event does not cause a Timer1/3/5 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPRxH:CCPRxL register pair becomes the period register for Timer1/3/5. Timer1/3/5 may be synchronized and FOSC/4 may be selected as the clock source in order to utilize the Special Event Trigger. Asynchronous operation of Timer1/3/5 can cause a Special Event Trigger to be missed. In the event that a write to TMRxH or TMRxL coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section 17.2.8 “Special Event Trigger”. The device will wake up on an overflow and execute the next instruction. If the GIE/GIEH bit of the INTCON register is set, the device will call the Interrupt Service Routine. The secondary oscillator will continue to operate in Sleep regardless of the TxSYNC bit setting. DS40001412H-page 162  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 12-3: TIMER1/3/5 INCREMENTING EDGE TXCKI = 1 when TMRx Enabled TXCKI = 0 when TMRX Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. FIGURE 12-4: TIMER1/3/5 GATE ENABLE MODE TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3/5 N  2010-2021 Microchip Technology Inc. N+1 N+2 N+3 N+4 DS40001412H-page 163 PIC18(L)F2X/4XK22 FIGURE 12-5: TIMER1/3/5 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM TxTxG_IN TxCKI TxGVAL TIMER1/3/5 N FIGURE 12-6: N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 TIMER1/3/5 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3/5 TMRxGIF DS40001412H-page 164 N Cleared by software N+1 N+2 Set by hardware on falling edge of TxGVAL Cleared by software  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 12-7: TIMER1/3/5 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3/5 TMRxGIF N N+1 Cleared by software N+2 N+3 Set by hardware on falling edge of TxGVAL N+4 Cleared by software 12.12 Peripheral Module Disable When a peripheral module is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power consumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module’s clock source. The Module Disable bits for Timer1 (TMR1MD), Timer3 (TMR3MD) and Timer5 (TMR5MD) are in the PMD0 Register. See Section 3.0 “Power-Managed Modes” for more information.  2010-2021 Microchip Technology Inc. DS40001412H-page 165 PIC18(L)F2X/4XK22 12.13 Register Definitions: Timer1/3/5 Control REGISTER 12-1: R/W-0/u TXCON: TIMER1/3/5 CONTROL REGISTER R/W-0/u TMRxCS R/W-0/u R/W-0/u TxCKPS R/W-0/u R/W-0/u R/W-0/0 R/W-0/u TxSOSCEN TxSYNC TxRD16 TMRxON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMRxCS: Timer1/3/5 Clock Source Select bits 11 = Reserved. Do not use. 10 = Timer1/3/5 clock source is pin or oscillator: If TxSOSCEN = 0: External clock from TxCKI pin (on the rising edge) If TxSOSCEN = 1: Crystal oscillator on SOSCI/SOSCO pins 01 = Timer1/3/5 clock source is system clock (FOSC) 00 = Timer1/3/5 clock source is instruction clock (FOSC/4) bit 5-4 TxCKPS: Timer1/3/5 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 TxSOSCEN: Secondary Oscillator Enable Control bit 1 = Dedicated Secondary oscillator circuit enabled 0 = Dedicated Secondary oscillator circuit disabled bit 2 TxSYNC: Timer1/3/5 External Clock Input Synchronization Control bit TMRxCS = 1x 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMRxCS = 0X This bit is ignored. Timer1/3/5 uses the internal clock when TMRxCS = 1X. bit 1 TxRD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1/3/5 in one 16-bit operation 0 = Enables register read/write of Timer1/3/5 in two 8-bit operation bit 0 TMRxON: Timer1/3/5 On bit 1 = Enables Timer1/3/5 0 = Stops Timer1/3/5 Clears Timer1/3/5 Gate flip-flop DS40001412H-page 166  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 12-2: TXGCON: TIMER1/3/5 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMRxGE TxGPOL TxGTM TxGSPM TxGGO/DONE TxGVAL R/W-0/u R/W-0/u TxGSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMRxGE: Timer1/3/5 Gate Enable bit If TMRxON = 0: This bit is ignored If TMRxON = 1: 1 = Timer1/3/5 counting is controlled by the Timer1/3/5 gate function 0 = Timer1/3/5 counts regardless of Timer1/3/5 gate function bit 6 TxGPOL: Timer1/3/5 Gate Polarity bit 1 = Timer1/3/5 gate is active-high (Timer1/3/5 counts when gate is high) 0 = Timer1/3/5 gate is active-low (Timer1/3/5 counts when gate is low) bit 5 TxGTM: Timer1/3/5 Gate Toggle Mode bit 1 = Timer1/3/5 Gate Toggle mode is enabled 0 = Timer1/3/5 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1/3/5 gate flip-flop toggles on every rising edge. bit 4 TxGSPM: Timer1/3/5 Gate Single-Pulse Mode bit 1 = Timer1/3/5 gate Single-Pulse mode is enabled and is controlling Timer1/3/5 gate 0 = Timer1/3/5 gate Single-Pulse mode is disabled bit 3 TxGGO/DONE: Timer1/3/5 Gate Single-Pulse Acquisition Status bit 1 = Timer1/3/5 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1/3/5 gate single-pulse acquisition has completed or has not been started This bit is automatically cleared when TxGSPM is cleared. bit 2 TxGVAL: Timer1/3/5 Gate Current State bit Indicates the current state of the Timer1/3/5 gate that could be provided to TMRxH:TMRxL. Unaffected by Timer1/3/5 Gate Enable (TMRxGE). bit 1-0 TxGSS: Timer1/3/5 Gate Source Select bits 00 = Timer1/3/5 Gate pin 01 = Timer2/4/6 Match PR2/4/6 output (See Table 12-5 for proper timer match selection) 10 = Comparator 1 optionally synchronized output (sync_C1OUT) 11 = Comparator 2 optionally synchronized output (sync_C2OUT)  2010-2021 Microchip Technology Inc. DS40001412H-page 167 PIC18(L)F2X/4XK22 TABLE 12-6: Name ANSELB REGISTERS ASSOCIATED WITH TIMER1/3/5 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 150 150 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 IPR5 — — — — — TMR6IP TMR5IP TMR4IP 124 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIE5 — — — — — TMR6IE TMR5IE TMR4IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PIR5 — — — — — TMR6IF TMR5IF TMR4IF 116 PMD0 UART2MD TMR4MD TMR3MD TMR2MD TMR1MD 52 T1SOSCEN T1SYNC T1RD16 TMR1ON 166 T1CON T1GCON TMR1GE T3CON T3GCON T1GPOL TMR3CS TMR3GE T5CON T5GCON UART1MD TMR6MD TMR1CS T3GPOL TMR5CS TMR5GE T5GPOL TMR5MD T1CKPS T1GTM T1GSPM T3CKPS T3GTM T3GSPM T5CKPS T5GTM T5GSPM T1GGO/DONE T1GVAL T3SOSCEN T3SYNC T3GGO/DONE T3GVAL T5SOSCEN T5SYNC T5GGO/DONE T5GVAL T1GSS T3RD16 TMR3ON T3GSS T5RD16 TMR5ON T5GSS 167 166 167 166 167 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — TMR1L Least Significant Byte of the 16-bit TMR1 Register — TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register — TMR3L Least Significant Byte of the 16-bit TMR3 Register — TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register — TMR5L Least Significant Byte of the 16-bit TMR5 Register — TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TABLE 12-7: CONFIGURATION REGISTERS ASSOCIATED WITH TIMER1/3/5 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 DS40001412H-page 168  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 13.0 TIMER2/4/6 MODULE There are three identical 8-bit Timer2-type modules available. To maintain pre-existing naming conventions, the Timers are called Timer2, Timer4 and Timer6 (also Timer2/4/6). Note: The ‘x’ variable used in this section is used to designate Timer2, Timer4, or Timer6. For example, TxCON references T2CON, T4CON, or T6CON. PRx references PR2, PR4, or PR6. The Timer2/4/6 module incorporates the following features: • 8-bit Timer and Period registers (TMRx and PRx, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMRx match with PRx, respectively • Optional use as the shift clock for the MSSPx modules (Timer2 only) See Figure 13-1 for a block diagram of Timer2/4/6. FIGURE 13-1: TIMER2/4/6 BLOCK DIAGRAM TMRx Output FOSC/4 Prescaler 1:1, 1:4, 1:16 2 TMRx Comparator Sets Flag bit TMRxIF Reset EQ Postscaler 1:1 to 1:16 TxCKPS PRx 4 TxOUTPS  2010-2021 Microchip Technology Inc. DS40001412H-page 169 PIC18(L)F2X/4XK22 13.1 Timer2/4/6 Operation The clock input to the Timer2/4/6 module is the system instruction clock (FOSC/4). TMRx increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, TxCKPS of the TxCON register. The value of TMRx is compared to that of the Period register, PRx, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMRx to 00h on the next cycle and drives the output counter/postscaler (see Section 13.2 “Timer2/4/6 Interrupt”). The TMRx and PRx registers are both directly readable and writable. The TMRx register is cleared on any device Reset, whereas the PRx register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: • • • • • • • • • a write to the TMRx register a write to the TxCON register Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset Watchdog Timer (WDT) Reset Stack Overflow Reset Stack Underflow Reset RESET Instruction Note: TMRx is not cleared when TxCON is written. 13.2 Timer2/4/6 Interrupt Timer2/4/6 can also generate an optional device interrupt. The Timer2/4/6 output signal (TMRx-to-PRx match) provides the input for the 4-bit counter/postscaler. This counter generates the TMRx match interrupt flag which is latched in TMRxIF of the PIR1/PIR5 registers. The interrupt is enabled by setting the TMRx Match Interrupt Enable bit, TMRxIE of the PIE1/PIE5 registers. Interrupt Priority is selected with the TMRxIP bit in the IPR1/IPR5 registers. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, TxOUTPS, of the TxCON register. 13.3 Timer2/4/6 Output The unscaled output of TMRx is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. The timer to be used with a specific CCP module is selected using the CxTSEL bits in the CCPTMRS0 and CCPTMRS1 registers. Timer2 can be optionally used as the shift clock source for the MSSPx modules operating in SPI mode by setting SSPM = 0011 in the SSPxCON1 register. Additional information is provided in Section 15.0 “Host Synchronous Serial Port (MSSP1 and MSSP2) Module”. 13.4 Timer2/4/6 Operation During Sleep The Timer2/4/6 timers cannot be operated while the processor is in Sleep mode. The contents of the TMRx and PRx registers will remain unchanged while the processor is in Sleep mode. 13.5 Peripheral Module Disable When a peripheral module is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power consumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module’s clock source. The Module Disable bits for Timer2 (TMR2MD), Timer4 (TMR4MD) and Timer6 (TMR6MD) are in the PMD0 Register. See Section 3.0 “Power-Managed Modes” for more information. DS40001412H-page 170  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 13.6 Register Definitions: Timer2/4/6 Control REGISTER 13-1: U-0 TxCON: TIMER2/TIMER4/TIMER6 CONTROL REGISTER R/W-0 R/W-0 — R/W-0 R/W-0 TxOUTPS R/W-0 R/W-0 TMRxON bit 7 R/W-0 TxCKPS bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TxOUTPS: TimerX Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler bit 2 TMRxON: TimerX On bit 1 = TimerX is on 0 = TimerX is off bit 1-0 TxCKPS: Timer2-type Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16  2010-2021 Microchip Technology Inc. DS40001412H-page 171 PIC18(L)F2X/4XK22 TABLE 13-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CCPTMRS0 C3TSEL — C2TSEL CCPTMRS1 — — — — Bit 2 Bit 1 Bit 0 Register on Page — C1TSEL 201 C5TSEL C4TSEL 201 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR5 — — — — — TMR6IP TMR5IP TMR4IP 124 INTCON 109 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE5 — — — — — TMR6IE TMR5IE TMR4IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR5 — — — — — TMR6IF TMR5IF TMR4IF 116 TMR1MD 52 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD PR2 Timer2 Period Register — PR4 Timer4 Period Register — PR6 Timer6 Period Register — T2CON — T2OUTPS TMR2ON T2CKPS 166 T4CON — T4OUTPS TMR4ON T4CKPS 166 T6CON — T6OUTPS TMR6ON T6CKPS 166 TMR2 Timer2 Register — TMR4 Timer4 Register — Timer6 Register — TMR6 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by Timer2/4/6. DS40001412H-page 172  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 14.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. Note 1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2: Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to ECCP1, ECCP2, ECCP3, CCP4 and CCP5. Register names, module signals, I/O pins, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module, when required. This family of devices contains three Enhanced Capture/Compare/PWM modules (ECCP1, ECCP2, and ECCP3) and two standard Capture/Compare/PWM modules (CCP4 and CCP5). The Capture and Compare functions are identical for all CCP/ECCP modules. The difference between CCP and ECCP modules are in the Pulse-Width Modulation (PWM) function. In CCP modules, the standard PWM function is identical. In ECCP modules, the Enhanced PWM function has either full-bridge or half-bridge PWM output. Full-bridge ECCP modules have four available I/O pins while half-bridge ECCP modules only have two available I/O pins. ECCP PWM modules are backward compatible with CCP PWM modules and can be configured as standard PWM modules. See Table 14-1 to determine the CCP/ECCP functionality available on each device in this family. TABLE 14-1: Device Name PWM RESOURCES ECCP1 ECCP2 PIC18(L)F23K22 PIC18(L)F24K22 PIC18(L)F25K22 PIC18(L)F26K22 Enhanced PWM Full-Bridge Enhanced PWM Half-Bridge Enhanced PWM Standard PWM Standard PWM Half-Bridge (Special Event Trigger) PIC18(L)F43K22 PIC18(L)F44K22 PIC18(L)F45K22 PIC18(L)F46K22 Enhanced PWM Full-Bridge Enhanced PWM Full-Bridge Enhanced PWM Standard PWM Standard PWM Half-Bridge (Special Event Trigger)  2010-2021 Microchip Technology Inc. ECCP3 CCP4 CCP5 DS40001412H-page 173 PIC18(L)F2X/4XK22 14.1 Capture Mode The Capture mode function described in this section is identical for all CCP and ECCP modules available on this device family. Capture mode makes use of the 16-bit Timer resources, Timer1, Timer3 and Timer5. The timer resources for each CCP capture function are independent and are selected using the CCPTMRS0 and CCPTMRS1 registers. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMRxH:TMRxL register pair, respectively. An event is defined as one of the following and is configured by the CCPxM bits of the CCPxCON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Figure 14-1 shows a simplified diagram of the Capture operation. FIGURE 14-1: Prescaler  1, 4, 16 CCPRxH and Edge Detect CCPRxL Capture Enable TMR1/3/5H TMR1/3/5L CCPxM System Clock (FOSC) CCP PIN CONFIGURATION In Capture mode, the CCPx pin may be configured as an input by setting the associated TRIS control bit. Some CCPx outputs are multiplexed on a couple of pins. Table 14-2 shows the CCP output pin multiplexing. Selection of the output pin is determined by the CCPxMX bits in Configuration register 3H (CONFIG3H). Refer to Register 24-4 for more details. Note: TABLE 14-2: Set Flag bit CCPxIF (PIR1/2/4 register) CCPx pin 14.1.1 When a capture is made, the corresponding Interrupt Request Flag bit CCPxIF of the PIR1, PIR2 or PIR4 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH:CCPRxL register pair is read, the old captured value is overwritten by the new captured value. CAPTURE MODE OPERATION BLOCK DIAGRAM If the CCPx pin is configured as an output, a write to the port can cause a capture condition. CCP PIN MULTIPLEXING CCP OUTPUT CONFIG 3H Control Bit CCP2 CCP2MX CCP3 CCP3MX Bit Value PIC18(L)F2XK22 I/O pin PIC18(L)F4XK22 I/O pin 0 RB3 RB3 1(*) RC1 RC1 0(*) RC6 RE0 1 RB5 RB5 Legend: * = Default 14.1.2 TIMER1 MODE RESOURCE The 16-bit Timer resource must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. See Section 12.0 “Timer1/3/5 Module with Gate Control” for more information on configuring the 16-bit Timers. 14.1.3 Note: DS40001412H-page 174 SOFTWARE INTERRUPT MODE When the Capture mode is changed, a false capture interrupt may be generated. The user may keep the CCPxIE interrupt enable bit of the PIE1, PIE2 or PIE4 register clear to avoid false interrupts. Additionally, the user may clear the CCPxIF interrupt flag bit of the PIR1, PIR2 or PIR4 register following any change in Operating mode. Clocking the 16-bit Timer resource from the system clock (FOSC) may not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, the Timer resource must be clocked from the instruction clock (FOSC/ 4) or from an external clock source.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 14.1.4 CCP PRESCALER 14.1.5 There are four prescaler settings specified by the CCPxM bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Capture mode requires a 16-bit TimerX module for use as a time base. There are four options for driving the 16-bit TimerX module in Capture mode. It can be driven by the system clock (FOSC), the instruction clock (FOSC/ 4), or by the external clock sources, the Secondary Oscillator (SOSC), or the TxCKI clock input. When the 16-bit TimerX resource is clocked by FOSC or FOSC/4, TimerX will not increment during Sleep. When the device wakes from Sleep, TimerX will continue from its previous state. Capture mode will operate during Sleep when the 16-bit TimerX resource is clocked by one of the external clock sources (SOSC or the TxCKI pin). Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler. Example 14-1 demonstrates the code to perform this function. EXAMPLE 14-1: CHANGING BETWEEN CAPTURE PRESCALERS #define NEW_CAPT_PS 0x06 //Capture // Prescale 4th // rising edge // Turn the CCP // Module Off // Turn CCP module // on with new // prescale value ... CCPxCON = 0; CCPxCON = NEW_CAPT_PS; TABLE 14-3: Name CAPTURE DURING SLEEP REGISTERS ASSOCIATED WITH CAPTURE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CCP1CON P1M DC1B CCP1M 198 CCP2CON P2M DC2B CCP2M 198 CCP3CON DC3B CCP3M 198 CCP4CON — P3M — DC4B CCP4M 198 CCP5CON — — DC5B CCP5M 198 CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) — CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) — CCPR2H Capture/Compare/PWM Register 2 High Byte (MSB) — CCPR2L Capture/Compare/PWM Register 2 Low Byte (LSB) — CCPR3H Capture/Compare/PWM Register 3 High Byte (MSB) — CCPR3L Capture/Compare/PWM Register 3 Low Byte (LSB) — CCPR4H Capture/Compare/PWM Register 4 High Byte (MSB) — CCPR4L Capture/Compare/PWM Register 4 Low Byte (LSB) — CCPR5H Capture/Compare/PWM Register 5 High Byte (MSB) — CCPR5L Capture/Compare/PWM Register 5 Low Byte (LSB) CCPTMRS0 CCPTMRS1 C3TSEL — C2TSEL — 201 C4TSEL 201 — — — — GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 IPR4 — — — — — CCP5IP CCP4IP CCP3IP 124 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 INTCON C5TSEL — C1TSEL Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. Note 1: These registers/bits are available on PIC18(L)F4XK22 devices.  2010-2021 Microchip Technology Inc. DS40001412H-page 175 PIC18(L)F2X/4XK22 TABLE 14-3: Name REGISTERS ASSOCIATED WITH CAPTURE (CONTINUED) Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIE4 — — — — — CCP5IE CCP4IE CCP3IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIR4 — — — — — CCP5IF CCP4IF CCP3IF 115 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 PMD1 MSSP2MD MSSP1MD — CCP5MD T1CON TMR1CS T1GCON TMR1GE T3CON T1GPOL T1CKPS T1GTM TMR3CS T3GCON TMR3GE T5CON T3GPOL T3CKPS T3GTM TMR5CS T5GCON TMR5GE T5GPOL TMR1H T1GSPM T3GSPM T5CKPS T5GTM T5GSPM CCP4MD CCP3MD CCP2MD CCP1MD 53 T1SOSCEN T1SYNC T1RD16 TMR1ON 166 T1GGO/DONE T1GVAL T3SOSCEN T3SYNC T3GGO/DONE T3GVAL T5SOSCEN T5SYNC T5GGO/DONE T5GVAL T1GSS T3RD16 TMR3ON T3GSS T5RD16 TMR5ON T5GSS 167 166 167 166 167 Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — TMR1L Least Significant Byte of the 16-bit TMR1 Register — TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register — TMR3L Least Significant Byte of the 16-bit TMR3 Register — TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register — TMR5L Least Significant Byte of the 16-bit TMR5 Register — TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 151 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. Note 1: These registers/bits are available on PIC18(L)F4XK22 devices. TABLE 14-4: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. DS40001412H-page 176  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 14.2 Compare Mode 14.2.1 The Compare mode function described in this section is identical for all CCP and ECCP modules available on this device family. Compare mode makes use of the 16-bit TimerX resources, Timer1, Timer3 and Timer5. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMRxH:TMRxL register pair. When a match occurs, one of the following events can occur: • • • • • Some CCPx outputs are multiplexed on a couple of pins. Table 14-2 shows the CCP output pin Multiplexing. Selection of the output pin is determined by the CCPxMX bits in Configuration register 3H (CONFIG3H). Refer to Register 24-4 for more details. 14.2.2 The action on the pin is based on the value of the CCPxM control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set. All Compare modes can generate an interrupt. Figure 14-2 shows a simplified diagram of the Compare operation. FIGURE 14-2: The user must configure the CCPx pin as an output by clearing the associated TRIS bit. Note: Toggle the CCPx output Set the CCPx output Clear the CCPx output Generate a Special Event Trigger Generate a Software Interrupt COMPARE MODE OPERATION BLOCK DIAGRAM S R Output Logic Match TRIS Output Enable Comparator TMRxH Special Event Trigger TMRxL TimerX MODE RESOURCE See Section 12.0 “Timer1/3/5 Module with Gate Control” for more information on configuring the 16-bit TimerX resources. Note: Set CCPxIF Interrupt Flag (PIR1/2/4) 4 CCPRxH CCPRxL Q Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. In Compare mode, 16-bit TimerX resource must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. CCPxM Mode Select CCPx Pin CCP PIN CONFIGURATION 14.2.3 Clocking TimerX from the system clock (FOSC) may not be used in Compare mode. In order for Compare mode to recognize the trigger event on the CCPx pin, TimerX must be clocked from the instruction clock (FOSC/4) or from an external clock source. SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen (CCPxM = 1010), the CCPx module does not assert control of the CCPx pin (see the CCPxCON register). Special Event Trigger function on • ECCP1, ECCP2, ECCP3, CCP4 and CCP5 will: - Reset TimerX – TMRxH:TMRxL = 0x0000 - TimerX Interrupt Flag, (TMRxIF) is not set Additional Function on • CCP5 will - Set ADCON0, GO/DONE bit to start an ADC Conversion if ADCON, ADON = 1.  2010-2021 Microchip Technology Inc. DS40001412H-page 177 PIC18(L)F2X/4XK22 14.2.4 SPECIAL EVENT TRIGGER 14.2.5 When Special Event Trigger mode is selected (CCPxM = 1011), and a match of the TMRxH:TMRxL and the CCPRxH:CCPRxL registers occurs, all CCPx and ECCPx modules will immediately: COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. • Set the CCP interrupt flag bit – CCPxIF • CCP5 will start an ADC conversion, if the ADC is enabled On the next TimerX rising clock edge: • A Reset of TimerX register pair occurs – TMRxH:TMRxL = 0x0000, This Special Event Trigger mode does not: • Assert control over the CCPx or ECCPx pins. • Set the TMRxIF interrupt bit when the TMRxH:TMRxL register pair is reset. (TMRxIF gets set on a TimerX overflow.) If the value of the CCPRxH:CCPRxL registers are modified when a match occurs, the user may be aware that the automatic reset of TimerX occurs on the next rising edge of the clock. Therefore, modifying the CCPRxH:CCPRxL registers before this reset occurs will allow the TimerX to continue without being reset, inadvertently resulting in the next event being advanced or delayed. The Special Event Trigger mode allows the CCPRxH:CCPRxL register pair to effectively provide a 16-bit programmable period register for TimerX. TABLE 14-5: Name REGISTERS ASSOCIATED WITH COMPARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CCP1CON P1M DC1B CCP1M 198 CCP2CON P2M DC2B CCP2M 198 CCP3CON P3M DC3B CCP3M 198 CCP4CON — — DC4B CCP4M 198 CCP5CON — — DC5B CCP5M 198 CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) — CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) — CCPR2H Capture/Compare/PWM Register 2 High Byte (MSB) — CCPR2L Capture/Compare/PWM Register 2 Low Byte (LSB) — CCPR3H Capture/Compare/PWM Register 3 High Byte (MSB) — CCPR3L Capture/Compare/PWM Register 3 Low Byte (LSB) — CCPR4H Capture/Compare/PWM Register 4 High Byte (MSB) — CCPR4L Capture/Compare/PWM Register 4 Low Byte (LSB) — CCPR5H Capture/Compare/PWM Register 5 High Byte (MSB) — CCPR5L Capture/Compare/PWM Register 5 Low Byte (LSB) CCPTMRS0 CCPTMRS1 INTCON IPR1 C3TSEL — C2TSEL — — C1TSEL C5TSEL C4TSEL 201 — — — — GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 201 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Compare mode. Note 1: These registers/bits are available on PIC18(L)F4XK22 devices. DS40001412H-page 178  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 14-5: REGISTERS ASSOCIATED WITH COMPARE (CONTINUED) Bit 2 Bit 1 Bit 0 Register on Page BCL1IP HLVDIP TMR3IP CCP2IP 122 — CCP5IP CCP4IP CCP3IP 124 TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 — — — — CCP5IE CCP4IE CCP3IE 120 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIR4 — — — — — CCP5IF CCP4IF CCP3IF 115 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 53 T1RD16 TMR1ON 166 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 IPR2 OSCFIP C1IP C2IP EEIP IPR4 — — — — PIE1 — ADIE RC1IE PIE2 OSCFIE C1IE PIE4 — PIR1 T1CON TMR1CS T1GCON TMR1GE T3CON T1GPOL T1CKPS T1GTM TMR3CS T3GCON TMR3GE T5CON T3GPOL T3CKPS T3GTM TMR5CS T5GCON TMR5GE T5GPOL T1GSPM T3GSPM T5CKPS T5GTM T5GSPM T1SOSCEN T1SYNC T1GGO/DONE T1GVAL T3SOSCEN T3SYNC T3GGO/DONE T3GVAL T5SOSCEN T5SYNC T5GGO/DONE T5GVAL T1GSS T3RD16 TMR3ON T3GSS T5RD16 TMR5ON T5GSS 167 166 167 166 167 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — TMR1L Least Significant Byte of the 16-bit TMR1 Register — TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register — TMR3L Least Significant Byte of the 16-bit TMR3 Register — TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register — TMR5L Least Significant Byte of the 16-bit TMR5 Register — TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 151 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Compare mode. Note 1: These registers/bits are available on PIC18(L)F4XK22 devices. TABLE 14-6: CONFIGURATION REGISTERS ASSOCIATED WITH COMPARE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Compare mode.  2010-2021 Microchip Technology Inc. DS40001412H-page 179 PIC18(L)F2X/4XK22 14.3 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. FIGURE 14-3: Period Pulse Width TMRx = 0 FIGURE 14-4: CCPRxH(2) (Client) CCPx TMRx Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 2: Clearing the CCPxCON register will relinquish control of the CCPx pin. Comparator PRx Note 1: 2: 14.3.2 S Clear Timer, toggle CCPx pin and latch duty cycle The 8-bit timer TMRx register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPRxH is a read-only register. SETUP FOR PWM OPERATION The following steps may be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. DS40001412H-page 180 (1) Q TRIS The standard PWM mode generates a Pulse-Width modulation (PWM) signal on the CCPx pin with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: Figure 14-4 shows a simplified block diagram of PWM operation. R Comparator STANDARD PWM OPERATION PRx registers TxCON registers CCPRxL registers CCPxCON registers CCPxCON CCPRxL Figure 14-3 shows a typical waveform of the PWM signal. • • • • SIMPLIFIED PWM BLOCK DIAGRAM Duty Cycle Registers The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. The standard PWM function described in this section is available and identical for CCP and ECCP modules. TMRx = PRx TMRx = CCPRxH:CCPxCON PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. 14.3.1 CCP PWM OUTPUT SIGNAL Disable the CCPx pin output driver by setting the associated TRIS bit. Select the 8-bit TimerX resource, (Timer2, Timer4 or Timer6) to be used for PWM generation by setting the CxTSEL bits in the CCPTMRSx register.(1) Load the PRx register for the selected TimerX with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register and the DCxB bits of the CCPxCON register, with the PWM duty cycle value.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 6. 7. Configure and start the 8-bit TimerX resource: • Clear the TMRxIF interrupt flag bit of the PIR2 or PIR4 register. See Note 1 below. • Configure the TxCKPS bits of the TxCON register with the Timer prescale value. • Enable the Timer by setting the TMRxON bit of the TxCON register. Enable PWM output pin: • Wait until the Timer overflows and the TMRxIF bit of the PIR2 or PIR4 register is set. See Note 1 below. • Enable the CCPx pin output driver by clearing the associated TRIS bit. Note 1: In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. 14.3.3 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB bits of the CCPxCON register contain the two LSbs. CCPRxL and DCxB bits of the CCPxCON register can be written to at any time. The duty cycle value is not latched into CCPRxH until after the period completes (i.e., a match between PRx and TMRx registers occurs). While using the PWM, the CCPRxH register is read-only. Equation 14-2 is used to calculate the PWM pulse width. Equation 14-3 is used to calculate the PWM duty cycle ratio. EQUATION 14-2: PULSE WIDTH Pulse W idth =  CCPRxL:CCPxCO N   TO SC  (TM Rx Prescale Value) PWM TIMER RESOURCE The PWM standard mode makes use of one of the 8-bit Timer2/4/6 timer resources to specify the PWM period. Configuring the CxTSEL bits in the CCPTMRS0 or CCPTMRS1 register selects which Timer2/4/6 timer is used. 14.3.4 14.3.5 PWM PERIOD The PWM period is specified by the PRx register of 8-bit TimerX. The PWM period can be calculated using the formula of Equation 14-1. EQUATION 14-1: PWM PERIOD PW M Period =   PRx + 1  4  TO SC  (TM Rx Prescale Value) Note 1: TOSC = 1/FOSC EQUATION 14-3: DUTY CYCLE RATIO  CCPRxL:CCPxCO N  D uty Cycle Ratio = ---------------------------------------------------------------------4 PRx + 1 The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMRx register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the TimerX prescaler is set to 1:1. When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure 14-4). When TMRx is equal to PRx, the following three events occur on the next increment cycle: • TMRx is cleared • The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is latched from CCPRxL into CCPRxH. Note: The Timer postscaler (see Section 13.0 “Timer2/4/6 Module”) is not used in the determination of the PWM frequency.  2010-2021 Microchip Technology Inc. DS40001412H-page 181 PIC18(L)F2X/4XK22 14.3.6 PWM RESOLUTION EQUATION 14-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PRx is 255. The resolution is a function of the PRx register value as shown by Equation 14-4. TABLE 14-7: Timer Prescale (1, 4, 16) PRx Value Maximum Resolution (bits) Timer Prescale (1, 4, 16) PRx Value Maximum Resolution (bits) Timer Prescale (1, 4, 16) PRx Value Maximum Resolution (bits) 1.95 kHz 7.81 kHz 31.25 kHz 125 kHz 250 kHz 333.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 OPERATION IN SLEEP MODE In Sleep mode, the TMRx register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMRx will continue from its previous state. 14.3.8 If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 14.3.7 Note: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency TABLE 14-9: log 4 PRx + 1  Resolution = ----------------------------------------- bits log 2 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz) PWM Frequency TABLE 14-8: PWM RESOLUTION 14.3.9 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details. DS40001412H-page 182  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 14-10: REGISTERS ASSOCIATED WITH STANDARD PWM Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CCP1CON P1M DC1B CCP1M 198 CCP2CON P2M DC2B CCP2M 198 DC3B CCP3M 198 CCP4CON — P3M — DC4B CCP4M 198 CCP5CON — — DC5B CCP5M CCP3CON CCPTMRS0 C3TSEL — C2TSEL — 201 C4TSEL 201 — — — — GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 IPR4 — — — — — CCP5IP CCP4IP CCP3IP 124 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIE4 — — — — — CCP5IE CCP4IE CCP3IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 115 CCPTMRS1 INTCON C5TSEL 198 C1TSEL 109 PIR4 — — — — — CCP5IF CCP4IF CCP3IF PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 53 PR2 Timer2 Period Register — PR4 Timer4 Period Register — PR6 Timer6 Period Register — T2CON — T2OUTPS TMR2ON T2CKPS 166 T4CON — T4OUTPS TMR4ON T4CKPS 166 T6CON — T6OUTPS TMR6ON T6CKPS 166 TMR2 Timer2 Register — TMR4 Timer4 Register — TMR6 Timer6 Register — TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD0 151 TRISE WPUE3 — — — — TRISE0(1) 151 TRISD2 TRISD1 TRISE2(1) TRISE1(1) Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Standard PWM mode. Note 1: These registers/bits are available on PIC18(L)F4XK22 devices. TABLE 14-11: CONFIGURATION REGISTERS ASSOCIATED WITH STANDARD PWM Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Standard PWM mode.  2010-2021 Microchip Technology Inc. DS40001412H-page 183 PIC18(L)F2X/4XK22 14.4 PWM (Enhanced Mode) To select an Enhanced PWM Output mode, the PxM bits of the CCPxCON register must be configured appropriately. The enhanced PWM function described in this section is available for CCP modules ECCP1, ECCP2 and ECCP3, with any differences between modules noted. The PWM outputs are multiplexed with I/O pins and are designated PxA, PxB, PxC and PxD. The polarity of the PWM pins is configurable and is selected by setting the CCPxM bits in the CCPxCON register appropriately. The enhanced PWM mode generates a Pulse-Width Modulation (PWM) signal on up to four different output pins with up to ten bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • • • • Figure 14-5 shows an example of a simplified block diagram of the Enhanced PWM module. Table 14-12 shows the pin assignments for various Enhanced PWM modes. PRx registers TxCON registers CCPRxL registers CCPxCON registers Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. The ECCP modules have the following additional PWM registers which control Auto-shutdown, Auto-restart, Dead-band Delay and PWM Steering modes: 2: Clearing the CCPxCON register will relinquish control of the CCPx pin. • ECCPxAS registers • PSTRxCON registers • PWMxCON registers 3: Any pin not used in the enhanced PWM mode is available for alternate pin functions, if applicable. The enhanced PWM module can generate the following five PWM Output modes: • • • • • 4: To prevent the generation of an incomplete waveform when the PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal. Single PWM Half-Bridge PWM Full-Bridge PWM, Forward mode Full-Bridge PWM, Reverse mode Single PWM with PWM Steering mode FIGURE 14-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE Duty Cycle Registers DCxB CCPxM 4 PxM 2 CCPRxL CCPx/PxA CCPx/PxA TRISx CCPRxH (Client) PxB Comparator R Q Output Controller PxB TRISx PxC(2) PxC TMRx (1) Comparator PRx Note TRISx S PxD Clear Timer, toggle PWM pin and latch duty cycle PxD(2) TRISx PWMxCON 1: The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. 2: PxC and PxD are not available on half-bridge ECCP modules. DS40001412H-page 184  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 14-12: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM CCPx/PxA Yes PxC (1) Yes PxD (1) Yes(1) Single 00 Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Yes PxB (1) PWM Steering enables outputs in Single mode. FIGURE 14-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) PxM Signal PRX+1 Pulse Width 0 Period 00 (Single Output) PxA Modulated Delay(1) Delay(1) PxA Modulated 10 (Half-Bridge) PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL:CCPxCON) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON) Note 1: Dead-band delay is programmed using the PWMxCON register (Section 14.4.5 “Programmable Dead-Band Delay Mode”).  2010-2021 Microchip Technology Inc. DS40001412H-page 185 PIC18(L)F2X/4XK22 FIGURE 14-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal PxM PRx+1 Pulse Width 0 Period 00 (Single Output) PxA Modulated PxA Modulated 10 (Half-Bridge) Delay(1) Delay(1) PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL:CCPxCON) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON) Note 1: Dead-band delay is programmed using the PWMxCON register (Section 14.4.5 “Programmable Dead-Band Delay Mode”). DS40001412H-page 186  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 14.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCPx/PxA pin, while the complementary PWM output signal is output on the PxB pin (see Figure 14-9). This mode can be used for half-bridge applications, as shown in Figure 14-9, or for full-bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in halfbridge power devices. The value of the PDC bits of the PWMxCON register sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 14.4.5 “Programmable Dead-Band Delay Mode” for more details of the dead-band delay operations. Since the PxA and PxB outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure PxA and PxB as outputs. FIGURE 14-8: Period Period Pulse Width PxA(2) td td PxB(2) (1) (1) (1) td = Dead-Band Delay Note 1: 2: FIGURE 14-9: EXAMPLE OF HALFBRIDGE PWM OUTPUT At this time, the TMRx register is equal to the PRx register. Output signals are shown as active-high. EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + PxA Load FET Driver + PxB - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET Driver FET Driver PxA FET Driver Load FET Driver PxB  2010-2021 Microchip Technology Inc. DS40001412H-page 187 PIC18(L)F2X/4XK22 14.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of full-bridge application is shown in Figure 14-10. In the Forward mode, pin CCPx/PxA is driven to its active state, pin PxD is modulated, while PxB and PxC will be driven to their inactive state as shown in Figure 14-11. In the Reverse mode, PxC is driven to its active state, pin PxB is modulated, while PxA and PxD will be driven to their inactive state as shown Figure 14-11. PxA, PxB, PxC and PxD outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the PxA, PxB, PxC and PxD pins as outputs. FIGURE 14-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET Driver QC QA FET Driver PxA Load PxB FET Driver PxC FET Driver QD QB VPxD DS40001412H-page 188  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 14-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA (2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) Note 1: 2: (1) At this time, the TMRx register is equal to the PRx register. Output signal is shown as active-high.  2010-2021 Microchip Technology Inc. DS40001412H-page 189 PIC18(L)F2X/4XK22 14.4.2.1 Direction Change in Full-Bridge Mode This situation occurs when both of the following conditions are true: In the Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. 1. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register. The following sequence occurs four Timer cycles prior to the end of the current PWM period: Figure 14-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty cycle. In this example, at time t1, the output PxA and PxD become inactive, while output PxC becomes active. Since the turn off time of the power devices is longer than the turn on time, a shoot-through current will flow through power devices QC and QD (see Figure 14-10) for the duration of ‘t’. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward. • The modulated outputs (PxB and PxD) are placed in their inactive state. • The associated unmodulated outputs (PxA and PxC) are switched to drive in the opposite direction. • PWM modulation resumes at the beginning of the next period. See Figure 14-12 for an illustration of this sequence. The Full-Bridge mode does not provide dead-band delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation where dead-band delay is required. 2. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn off time of the power switch, including the power device and driver circuit, is greater than the turn on time. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. 2. Reduce PWM duty cycle for one PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 14-12: EXAMPLE OF PWM DIRECTION CHANGE Period(1) Signal Period PxA (Active-High) PxB (Active-High) Pulse Width PxC (Active-High) (2) PxD (Active-High) Pulse Width Note 1: 2: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle. When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The modulated PxB and PxD signals are inactive at this time. The length of this time is (TimerX Prescale)/FOSC, where TimerX is Timer2, Timer4 or Timer6. DS40001412H-page 190  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 14-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: 14.4.3 T = TOFF – TON All signals are shown as active-high. 2: TON is the turn-on delay of power switch QC and its driver. 3: TOFF is the turn-off delay of power switch QD and its driver. ENHANCED PWM AUTOSHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the CCPxAS bits of the ECCPxAS register. A shutdown event may be generated by: • A logic ‘0’ on the INT pin • Comparator Cx (async_CxOUT) • Setting the CCPxASE bit in firmware A shutdown condition is indicated by the CCPxASE (Auto-Shutdown Event Status) bit of the ECCPxAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state. When a shutdown event occurs, two things happen: The state of each pin pair is determined by the PSSxAC and PSSxBD bits of the ECCPxAS register. Each pin pair may be placed into one of three states: • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) Note 1: The auto-shutdown condition is a levelbased signal, not an edge-based signal. As long as the level is present, the autoshutdown will persist. 2: Writing to the CCPxASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart), the PWM signal will always restart at the beginning of the next PWM period. The CCPxASE bit is set to ‘1’. The CCPxASE will remain set until cleared in firmware or an auto-restart occurs (see Section 14.4.4 “Auto-Restart Mode”). The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [PxA/PxC] and [PxB/PxD].  2010-2021 Microchip Technology Inc. DS40001412H-page 191 PIC18(L)F2X/4XK22 FIGURE 14-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0) Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow Missing Pulse (CCPxASE not clear) Timer Overflow Timer Overflow Timer Overflow PWM Period PWM Activity Start of PWM Period Shutdown Event CCPxASE bit Shutdown Event Occurs 14.4.4 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the autoshutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit in the PWMxCON register. FIGURE 14-15: Shutdown Event Clears PWM Resumes CCPxASE Cleared by Firmware If auto-restart is enabled, the CCPxASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the CCPxASE bit will be cleared via hardware and normal operation will resume. PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1) Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow Missing Pulse (CCPxASE not clear) Timer Overflow Timer Overflow Timer Overflow PWM Period PWM Activity Start of PWM Period Shutdown Event CCPxASE bit PWM Resumes Shutdown Event Occurs Shutdown Event Clears DS40001412H-page 192 CCPxASE Cleared by Hardware  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 14.4.5 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 14-16: In half-bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shoot-through current) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shootthrough current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. Period Period Pulse Width PxA(2) td td PxB(2) (1) (1) (1) td = Dead-Band Delay Note 1: In Half-Bridge mode, a digitally programmable deadband delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the nonactive state to the active state. See Figure 14-16 for illustration. The lower seven bits of the associated PWMxCON register (Register 14-6) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 14-17: EXAMPLE OF HALFBRIDGE PWM OUTPUT 2: At this time, the TMRx register is equal to the PRx register. Output signals are shown as active-high. EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + V - PxA Load FET Driver + V - PxB V-  2010-2021 Microchip Technology Inc. DS40001412H-page 193 PIC18(L)F2X/4XK22 14.4.6 PWM STEERING MODE In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCPxM = 11 and PxM = 00 of the CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate Steering Enable bits (STRxA, STRxB, STRxC and/or STRxD) of the PSTRxCON register, as shown in Table 14-13. FIGURE 14-18: STRxA PxA Signal CCPxM1 PORT Data CCPxM0 The associated TRIS bits must be set to output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. PORT Data While the PWM Steering mode is active, CCPxM bits of the CCPxCON register select the PWM output polarity for the PxD, PxC, PxB and PxA pins. The PWM auto-shutdown operation also applies to PWM Steering mode as described in Section 14.4.3 “Enhanced PWM Auto-shutdown Mode”. An autoshutdown event will only affect pins that have PWM outputs enabled. 0 0 PORT Data PxB pin TRIS PxC pin 1 0 TRIS STRxD CCPxM0 TRIS 1 STRxC CCPxM1 PxA pin 1 STRxB PORT Data Note: SIMPLIFIED STEERING BLOCK DIAGRAM PxD pin 1 0 TRIS Note 1: Port outputs are configured as shown when the CCPxCON register bits PxM = 00 and CCPxM = 11. 2: Single PWM output requires setting at least one of the STRx bits. 14.4.6.1 Steering Synchronization The STRxSYNC bit of the PSTRxCON register gives the user two selections of when the steering event will happen. When the STRxSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case, the output signal at the PxA, PxB, PxC and PxD pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin. When the STRxSYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM period. In this case, steering on/off the PWM output will always produce a complete PWM waveform. Figures 14-19 and 14-20 illustrate the timing diagrams of the PWM steering depending on the STRxSYNC setting. DS40001412H-page 194  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 14.4.7 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. The CCPxM bits of the CCPxCON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (PxA/PxC and PxB/PxD). The PWM output polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enable is not recommended since it may result in damage to the application circuits. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMRxIF bit of the PIR1, PIR2 or PIR5 register being set as the second PWM period begins. Note: The PxA, PxB, PxC and PxD output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. FIGURE 14-19: When the microcontroller is released from Reset, all of the I/O pins are in the highimpedance state. The external circuits must keep the power switch devices in the Off state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0) PWM Period PWM STRx P1 PORT Data PORT Data P1n = PWM FIGURE 14-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRxSYNC = 1) PWM STRx P1 PORT Data PORT Data P1n = PWM  2010-2021 Microchip Technology Inc. DS40001412H-page 195 PIC18(L)F2X/4XK22 14.4.8 SETUP FOR ECCP PWM OPERATION USING ECCP1 AND TIMER2 The following steps may be taken when configuring the ECCP1 module for PWM operation using Timer2: 1. 2. 3. 4. 5. 6. 7. 8. 9. Configure the PWM pins to be used (P1A, P1B, P1C, and P1D): • Configure PWM outputs to be used as inputs by setting the corresponding TRIS bits. This prevents spurious outputs during setup. • Set the PSTR1CON bits for each PWM output to be used. Select Timer2 as the period timer by configuring CCPTMR0 register bits C1TSEL = ‘00’. Set the PWM period by loading the PR2 register. Configure auto-shutdown as OFF or select the source with the CCP1AS bits of the ECCP1AS register. Configure the auto-shutdown sources as needed: • Configure each comparator used. • Configure the comparator inputs as analog. • Configure the FLT0 input pin and clear ANSB0. Force a shutdown condition (OFF included): • Configure safe starting output levels by setting the default shutdown drive states with the PSS1AC and PSS1BD bits of the ECCP1AS register. • Clear the P1RSEN bit of the PWM1CON register. • Set the CCP1AS bit of the ECCP1AS register. Configure the ECCP1 module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values: • Select one of the available output configurations and direction with the P1M bits. • Select the polarities of the PWM output signals with the CCP1M bits. Set the 10-bit PWM duty cycle: • Load the eight MSbs into the CCPR1L register. • Load the two LSbs into the DC bits of the CCP1CON register. For Half-Bridge Output mode, set the deadband delay by loading P1DC bits of the PWM1CON register with the appropriate value. DS40001412H-page 196 10. Configure and start TMR2: • Set the TMR2 prescale value by loading the T2CKPS bits of the T2CON register. • Start Timer2 by setting the TMR2ON bit. 11. Enable the ECCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. 12. Start the PWM: • If shutdown auto-restart is used, then set the P1RSEN bit of the PWM1CON register. • If shutdown auto-restart is not used, then clear the CCP1ASE bit of the ECCP1AS register.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 14-13: REGISTERS ASSOCIATED WITH ENHANCED PWM Name Bit 7 ECCP1AS Bit 6 CCP1ASE CCP1CON Bit 5 CCP3CON CCPTMRS0 CCP2M C2TSEL — 202 202 198 PSS3BD 202 C1TSEL 201 CCP3M — Register on Page 198 PSS2BD PSS3AC DC3B C3TSEL PSS1BD PSS2AC CCP3AS P3M Bit 0 CCP1M DC2B CCP3ASE Bit 1 PSS1AC CCP2AS P2M ECCP3AS Bit 2 DC1B CCP2ASE CCP2CON Bit 3 CCP1AS P1M ECCP2AS Bit 4 198 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 124 INTCON 109 IPR4 — — — — — CCP5IP CCP4IP CCP3IP PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIE4 — — — — — CCP5IE CCP4IE CCP3IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PIR4 — — — — — CCP5IF CCP4IF CCP3IF 115 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 53 PR2 Timer2 Period Register — PR4 Timer4 Period Register — PR6 Timer6 Period Register — PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A 203 PSTR2CON — — — STR2SYNC STR2D STR2C STR2B STR2A 203 PSTR3CON — — — STR3SYNC STR3D STR3C STR3B STR3A 203 PWM1CON P1RSEN P1DC 203 PWM2CON P2RSEN P2DC 203 PWM3CON P3RSEN P3DC 203 T2CON — T2OUTPS TMR2ON T2CKPS 166 T4CON — T4OUTPS TMR4ON T4CKPS 166 T6CON — T6OUTPS TMR6ON T6CKPS 166 TMR2 Timer2 Register — TMR4 Timer4 Register — TMR6 Timer6 Register TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 — TRISA2 TRISA1 TRISA0 151 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 151 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Enhanced PWM mode. Note 1: These registers/bits are available on PIC18(L)F4XK22 devices. TABLE 14-14: CONFIGURATION REGISTERS ASSOCIATED WITH ENHANCED PWM Name CONFIG3H Legend: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348 — = Unimplemented location, read as ‘0’. Shaded bits are not used by Enhanced PWM mode.  2010-2021 Microchip Technology Inc. DS40001412H-page 197 PIC18(L)F2X/4XK22 14.5 Register Definitions: ECCP Control REGISTER 14-1: CCPxCON: STANDARD CCPx CONTROL REGISTER U-0 U-0 — — R/W-0 R/W-0 R/W-0 DCxB R/W-0 R/W-0 R/W-0 CCPxM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unused bit 5-4 DCxB: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets the module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Reserved 0100 = 0101 = 0110 = 0111 = Capture mode: every falling edge Capture mode: every rising edge Capture mode: every 4th rising edge Capture mode: every 16th rising edge 1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set) 1001 = Compare mode: clear output on compare match (CCPx pin is cleared, CCPxIF is set) 1010 = Compare mode: generate software interrupt on compare match (CCPx pin is unaffected, CCPxIF is set) 1011 = Compare mode: Special Event Trigger (CCPx pin is unaffected, CCPxIF is set) TimerX (selected by CxTSEL bits) is reset ADON is set, starting A/D conversion if A/D module is enabled(1) 11xx =: PWM mode Note 1: This feature is available on CCP5 only. DS40001412H-page 198  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 14-2: R/x-0 CCPxCON: ENHANCED CCPx CONTROL REGISTER R/W-0 R/W-0 PxM R/W-0 DCxB R/W-0 R/W-0 R/W-0 R/W-0 CCPxM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PxM: Enhanced PWM Output Configuration bits If CCPxM = 00, 01, 10: (Capture/Compare modes) xx = PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins Half-Bridge ECCP Modules(1): If CCPxM = 11: (PWM modes) 0x = Single output; PxA modulated; PxB assigned as port pin 1x = Half-Bridge output; PxA, PxB modulated with dead-band control Full-Bridge ECCP Modules(1): If CCPxM = 11: (PWM modes) 00 = Single output; PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-Bridge output forward; PxD modulated; PxA active; PxB, PxC inactive 10 = Half-Bridge output; PxA, PxB modulated with dead-band control; PxC, PxD assigned as port pins 11 = Full-Bridge output reverse; PxB modulated; PxC active; PxA, PxD inactive bit 5-4 Note 1: DCxB: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. See Table 14-1 to determine full-bridge and half-bridge ECCPs for the device being used.  2010-2021 Microchip Technology Inc. DS40001412H-page 199 PIC18(L)F2X/4XK22 REGISTER 14-2: bit 3-0 CCPxCON: ENHANCED CCPx CONTROL REGISTER (CONTINUED) CCPxM: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets the module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Reserved 0100 = 0101 = 0110 = 0111 = Capture mode: every falling edge Capture mode: every rising edge Capture mode: every 4th rising edge Capture mode: every 16th rising edge 1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set) 1001 = Compare mode: clear output on compare match (CCPx pin is cleared, CCPxIF is set) 1010 = Compare mode: generate software interrupt on compare match (CCPx pin is unaffected, CCPxIF is set) 1011 = Compare mode: Special Event Trigger (CCPx pin is unaffected, CCPxIF is set) TimerX is reset Half-Bridge ECCP Modules(1): 1100 = PWM mode: PxA active-high; PxB active-high 1101 = PWM mode: PxA active-high; PxB active-low 1110 = PWM mode: PxA active-low; PxB active-high 1111 = PWM mode: PxA active-low; PxB active-low Full-Bridge ECCP Modules(1): 1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high 1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low Note 1: See Table 14-1 to determine full-bridge and half-bridge ECCPs for the device being used. DS40001412H-page 200  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 14-3: R/W-0 CCPTMRS0: PWM TIMER SELECTION CONTROL REGISTER 0 R/W-0 U-0 C3TSEL R/W-0 — R/W-0 C2TSEL U-0 R/W-0 — R/W-0 C1TSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C3TSEL: CCP3 Timer Selection bits 00 = CCP3 – Capture/Compare modes use Timer1, PWM modes use Timer2 01 = CCP3 – Capture/Compare modes use Timer3, PWM modes use Timer4 10 = CCP3 – Capture/Compare modes use Timer5, PWM modes use Timer6 11 = Reserved bit 5 Unused bit 4-3 C2TSEL: CCP2 Timer Selection bits 00 = CCP2 – Capture/Compare modes use Timer1, PWM modes use Timer2 01 = CCP2 – Capture/Compare modes use Timer3, PWM modes use Timer4 10 = CCP2 – Capture/Compare modes use Timer5, PWM modes use Timer6 11 = Reserved bit 2 Unused bit 1-0 C1TSEL: CCP1 Timer Selection bits 00 = CCP1 – Capture/Compare modes use Timer1, PWM modes use Timer2 01 = CCP1 – Capture/Compare modes use Timer3, PWM modes use Timer4 10 = CCP1 – Capture/Compare modes use Timer5, PWM modes use Timer6 11 = Reserved REGISTER 14-4: CCPTMRS1: PWM TIMER SELECTION CONTROL REGISTER 1 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 C5TSEL bit 7 R/W-0 C4TSEL bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 C5TSEL: CCP5 Timer Selection bits 00 = CCP5 – Capture/Compare modes use Timer1, PWM modes use Timer2 01 = CCP5 – Capture/Compare modes use Timer3, PWM modes use Timer4 10 = CCP5 – Capture/Compare modes use Timer5, PWM modes use Timer6 11 = Reserved bit 1-0 C4TSEL: CCP4 Timer Selection bits 00 = CCP4 – Capture/Compare modes use Timer1, PWM modes use Timer2 01 = CCP4 – Capture/Compare modes use Timer3, PWM modes use Timer4 10 = CCP4 – Capture/Compare modes use Timer5, PWM modes use Timer6 11 = Reserved  2010-2021 Microchip Technology Inc. DS40001412H-page 201 PIC18(L)F2X/4XK22 REGISTER 14-5: R/W-0 ECCPxAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER R/W-0 CCPxASE R/W-0 R/W-0 CCPxAS R/W-0 R/W-0 R/W-0 PSSxAC R/W-0 PSSxBD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCPxASE: CCPx Auto-shutdown Event Status bit if PxRSEN = 1; 1 = An Auto-shutdown event occurred; CCPxASE bit will automatically clear when event goes away; CCPx outputs in shutdown state 0 = CCPx outputs are operating if PxRSEN = 0; 1 = An Auto-shutdown event occurred; bit must be cleared in software to restart PWM; CCPx outputs in shutdown state 0 = CCPx outputs are operating bit 6-4 CCPxAS: CCPx Auto-Shutdown Source Select bits (1) 000 = Auto-shutdown is disabled 001 = Comparator C1 (async_C1OUT) – output high will cause shutdown event 010 = Comparator C2 (async_C2OUT) – output high will cause shutdown event 011 = Either Comparator C1 or C2 – output high will cause shutdown event 100 = FLT0 pin – low level will cause shutdown event 101 = FLT0 pin – low level or Comparator C1 (async_C1OUT) – high level will cause shutdown event 110 = FLT0 pin – low level or Comparator C2 (async_C2OUT) – high level will cause shutdown event 111 = FLT0 pin – low level or Comparators C1 or C2 – high level will cause shutdown event bit 3-2 PSSxAC: Pins PxA and PxC Shutdown State Control bits 00 = Drive pins PxA and PxC to ‘0’ 01 = Drive pins PxA and PxC to ‘1’ 1x = Pins PxA and PxC tri-state bit 1-0 PSSxBD: Pins PxB and PxD Shutdown State Control bits 00 = Drive pins PxB and PxD to ‘0’ 01 = Drive pins PxB and PxD to ‘1’ 1x = Pins PxB and PxD tri-state Note 1: If C1SYNC or C2SYNC bits in the CM2CON1 register are enabled, the shutdown will be delayed by Timer1. DS40001412H-page 202  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 14-6: R/W-0 PWMxCON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 PxRSEN R/W-0 R/W-0 R/W-0 R/W-0 PxDC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM bit 6-0 PxDC: PWM Delay Count bits PxDCx = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal may transition active and the actual time it transitions active PSTRxCON: PWM STEERING CONTROL REGISTER(1) REGISTER 14-7: U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — — STRxSYNC STRxD STRxC STRxB STRxA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 STRxSYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STRxD: Steering Enable bit D 1 = PxD pin has the PWM waveform with polarity control from CCPxM 0 = PxD pin is assigned to port pin bit 2 STRxC: Steering Enable bit C 1 = PxC pin has the PWM waveform with polarity control from CCPxM 0 = PxC pin is assigned to port pin bit 1 STRxB: Steering Enable bit B 1 = PxB pin has the PWM waveform with polarity control from CCPxM 0 = PxB pin is assigned to port pin bit 0 STRxA: Steering Enable bit A 1 = PxA pin has the PWM waveform with polarity control from CCPxM 0 = PxA pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM = 11 and PxM = 00.  2010-2021 Microchip Technology Inc. DS40001412H-page 203 PIC18(L)F2X/4XK22 15.0 15.1 HOST SYNCHRONOUS SERIAL PORT (MSSP1 AND MSSP2) MODULE The SPI interface supports the following modes and features: • • • • • Host SSPx (MSSPx) Module Overview The Host Synchronous Serial Port (MSSPx) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSPx module can operate in one of two modes: Host mode Client mode Clock Parity Client Select Synchronization (Client mode only) Daisy chain connection of client devices Figure 15-1 is a block diagram of the SPI interface module. • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) FIGURE 15-1: MSSPx BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPxBUF Reg SDIx SSPxSR Reg SDOx bit 0 SSx SSx Control Enable Shift Clock 2 (CKP, CKE) Clock Select Edge Select SSPxM 4 SCKx Edge Select TRIS bit DS40001412H-page 204 ( TMR22Output ) Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSPxADD)  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 The I2C interface supports the following modes and features: Host mode Client mode Byte NACKing (Client mode) Limited Multi-host support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDAx hold times Note 1: In devices with more than one MSSP module, it is very important to pay close attention to SSPxCONx register names. SSP1CON1 and SSP1CON2 registers control different operational aspects of the same module, while SSP1CON1 and SSP2CON1 control the same features for two different modules. 2: Throughout this section, generic references to an MSSP module in any of its operating modes may be interpreted as being equally applicable to MSSP1 or MSSP2. Register names, module I/O signals, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module when required. Figure 15-2 is a block diagram of the I2C interface module in Host mode. Figure 15-3 is a diagram of the I2C interface module in Client mode. MSSPx BLOCK DIAGRAM (I2C HOST MODE) Internal Data Bus Read [SSPxM 3:0] Write SSPxBUF Baud Rate Generator (SSPxADD) Shift Clock SDAx SDAx in Receive Enable (RCEN) SCLx SCLx in Bus Collision  2010-2021 Microchip Technology Inc. LSb Start bit, Stop bit, Acknowledge Generate (SSPxCON2) Start bit Detect, Stop bit Detect Write Collision Detect Clock Arbitration State Counter for end of XMIT/RCV Address Match Detect Clock Cntl SSPxSR MSb (Hold off clock source) FIGURE 15-2: Clock Arbitrate/BCOL Detect • • • • • • • • • • • • • The PIC18(L)F2X/4XK22 has two MSSP modules, MSSP1 and MSSP2, each module operating independently from the other. Set/Reset: S, P, SSPxSTAT, WCOL, SSPxOV Reset SEN, PEN (SSPxCON2) Set SSPxIF, BCLxIF DS40001412H-page 205 PIC18(L)F2X/4XK22 FIGURE 15-3: MSSPx BLOCK DIAGRAM (I2C CLIENT MODE) Internal Data Bus Read Write SSPxBUF Reg SCLx Shift Clock SSPxSR Reg SDAx MSb LSb SSPxMSK Reg Match Detect Addr Match SSPxADD Reg Start and Stop bit Detect DS40001412H-page 206 Set, Reset S, P bits (SSPxSTAT Reg)  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 15.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a host/client environment where the host device initiates the communication. A client device is controlled through a chip select known as Client Select. The SPI bus specifies four signal connections: • • • • Serial Clock (SCKx) Serial Data Out (SDOx) Serial Data In (SDIx) Client Select (SSx) Figure 15-1 shows the block diagram of the MSSPx module when operating in SPI Mode. The SPI bus operates with a single host device and one or more client devices. When multiple client devices are used, an independent Client Select connection is required from the host device to each client device. Figure 15-4 shows a typical connection between a host device and multiple client devices. The host selects only one client at a time. Most client devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. Transmissions involve two shift registers, eight bits in size, one in the host and one in the client. With either the host or the client device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. During each SPI clock cycle, a full-duplex data transmission occurs. This means that at the same time, the client device is sending out the MSb from its shift register and the host device is reading this bit from that same line and saving it as the LSb of its shift register. After 8 bits have been shifted out, the host and client have exchanged register values. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: • Host sends useful data and client sends dummy data. • Host sends useful data and client sends useful data. • Host sends dummy data and client sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the host stops sending the clock signal and it deselects the client. Every client device connected to the bus that has not been selected through its client select line must disregard the clock and transmission signals and must not transmit out any data of its own. Figure 15-5 shows a typical connection between two processors configured as host and client devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The host device transmits information out on its SDOx output pin which is connected to, and received by, the client’s SDIx input pin. The client device transmits information out on its SDOx output pin, which is connected to, and received by, the host’s SDIx input pin. To begin communication, the host device first sends out the clock signal. Both the host and the client devices may be configured for the same clock polarity. The host device starts a transmission by sending out the MSb from its shift register. The client device reads this bit from that same line and saves it into the LSb position of its shift register.  2010-2021 Microchip Technology Inc. DS40001412H-page 207 PIC18(L)F2X/4XK22 FIGURE 15-4: SPI HOST AND MULTIPLE CLIENT CONNECTION SPI Host SCLK SCLK SDOx SDIx SDIx SDOx General I/O General I/O SSx General I/O SCLK SDIx SDOx SPI Client #1 SPI Client #2 SSx SCLK SDIx SDOx SPI Client #3 SSx 15.2.1 SPI MODE REGISTERS 15.2.2 SPI MODE OPERATION The MSSPx module has five registers for SPI mode operation. These are: When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1 and SSPxSTAT). These control bits allow the following to be specified: • • • • • • MSSPx STATUS register (SSPxSTAT) MSSPx Control register 1 (SSPxCON1) MSSPx Control register 3 (SSPxCON3) MSSPx Data Buffer register (SSPxBUF) MSSPx Address register (SSPxADD) MSSPx Shift register (SSPxSR) (Not directly accessible) SSPxCON1 and SSPxSTAT are the control and STATUS registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. In one SPI Host mode, SSPxADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 15.7 “Baud Rate Generator”. SSPxSR is the shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPxSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPxSR and SSPxBUF together create a buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. DS40001412H-page 208 • • • • Host mode (SCKx is the clock output) Client mode (SCKx is the clock input) Clock Polarity (Idle state of SCKx) Data Input Sample Phase (middle or end of data output time) • Clock Edge (output data on rising/falling edge of SCKx) • Clock Rate (Host mode only) • Client Select mode (Client mode only) To enable the serial port, SSPx Enable bit, SSPxEN of the SSPxCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPxEN bit, re-initialize the SSPxCONx registers and then set the SSPxEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: • SDIx must have corresponding TRIS bit set • SDOx must have corresponding TRIS bit cleared • SCKx (Host mode) must have corresponding TRIS bit cleared • SCKx (Client mode) must have corresponding TRIS bit set • SSx must have corresponding TRIS bit set  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. The MSSPx consists of a transmit/receive shift register (SSPxSR) and a buffer register (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPxSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full Detect bit, BF of the SSPxSTAT register, and the interrupt flag bit, SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission/ reception of data will be ignored and the write collision detect bit, WCOL of the SSPxCON1 register, will be When the application software is expecting to receive valid data, the SSPxBUF may be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF of the SSPxSTAT register, indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSPx interrupt is used to determine when the transmission/ reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. FIGURE 15-5: The SSPxSR is not directly readable or writable and SPI HOST/CLIENT CONNECTION SPI Host SSPxM = 00xx = 1010 SPI Client SSPxM = 010x SDOx SDIx Serial Input Buffer (BUF) SDIx Shift Register (SSPxSR) MSb Serial Input Buffer (SSPxBUF) LSb SCKx General I/O Processor 1  2010-2021 Microchip Technology Inc. SDOx Serial Clock Client Select (optional) Shift Register (SSPxSR) MSb LSb SCKx SSx Processor 2 DS40001412H-page 209 PIC18(L)F2X/4XK22 15.2.3 SPI HOST MODE The host can initiate the data transfer at any time because it controls the SCKx line. The host determines when the client (Processor 2, Figure 15-5) is to broadcast data by the software protocol. In Host mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input). The SSPxSR register will continue to shift in the signal present on the SDIx pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register and the CKE bit of the SSPxSTAT register. FIGURE 15-6: This then, would give waveforms for SPI communication as shown in Figure 15-6, Figure 15-8, Figure 15-9 and Figure 15-10, where the MSB is transmitted first. In Host mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • • • • • FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 FOSC/(4 * (SSPxADD + 1)) Figure 15-6 shows the waveforms for Host mode. When the CKE bit is set, the SDOx data is valid before there is a clock edge on SCKx. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. SPI MODE WAVEFORM (HOST MODE) Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) 4 Clock Modes SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDOx (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDIx (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPxIF SSPxSR to SSPxBUF DS40001412H-page 210  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 15.2.4 SPI CLIENT MODE In Client mode, the data is transmitted and received as external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Client mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin. The Idle state is determined by the CKP bit of the SSPxCON1 register. While in Client mode, the external clock is supplied by the external clock source on the SCKx pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the client can transmit/receive data. The shift register is clocked from the SCKx pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake up from Sleep. 15.2.4.1 Daisy-Chain Configuration The SPI bus can sometimes be connected in a daisychain configuration. The first client output is connected to the second client input, the second client output is connected to the third client input, and so on. The final client output is connected to the host input. Each client sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Client Select line from the host device. Figure 15-7 shows the block diagram of a typical daisy-chain connection when operating in SPI Mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the client. Setting the BOEN bit of the SSPxCON3 register will enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. 15.2.5 CLIENT SELECT SYNCHRONIZATION The Client Select can also be used to synchronize communication. The Client Select line is held high until the host device is ready to communicate. When the Client Select line is pulled low, the client knows that a new transmission is starting. If the client fails to receive the communication properly, it will be reset at the end of the transmission, when the Client Select line returns to a high state. The client is then ready to receive a new transmission when the Client Select line is pulled low again. If the Client Select line is not used, there is a risk that the client will eventually become out of sync with the host. If the client misses a bit, it will always be one bit off in future transmissions. Use of the Client Select line allows the client and host to align themselves at the beginning of each transmission (Figure 15-8). The SSx pin allows a Synchronous Client mode. The SPI must be in Client mode with SSx pin control enabled (SSPxCON1 = 0100). When the SSx pin is low, transmission and reception are enabled and the SDOx pin is driven. When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Client mode with SSx pin control enabled (SSPxCON1 = 0100), the SPI module will reset if the SSx pin is set to VDD. 2: When the SPI is used in Client mode with CKE set; the user must enable SSx pin control. 3: While operated in SPI Client mode the SMP bit of the SSPxSTAT register must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SSx pin to a high level or clearing the SSPxEN bit.  2010-2021 Microchip Technology Inc. DS40001412H-page 211 PIC18(L)F2X/4XK22 FIGURE 15-7: SPI DAISY-CHAIN CONNECTION SPI Host SCLK SCLK SDOx SDIx SDIx SDOx General I/O SPI Client #1 SSx SCLK SDIx SDOx SPI Client #2 SSx SCLK SDIx SDOx SPI Client #3 SSx FIGURE 15-8: CLIENT SELECT SYNCHRONOUS WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPxSR and bit count are reset SSPxBUF to SSPxSR SDOx bit 7 bit 6 bit 7 SDIx bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF DS40001412H-page 212  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 15-9: SPI MODE WAVEFORM (CLIENT MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 15-10: SPI MODE WAVEFORM (CLIENT MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 7 bit 0 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active  2010-2021 Microchip Technology Inc. DS40001412H-page 213 PIC18(L)F2X/4XK22 15.2.6 SPI OPERATION IN SLEEP MODE In SPI Host mode, when the Sleep mode is selected, all module clocks are halted and the transmission/ reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Host mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSPx clock is much faster than the system clock. In SPI Client mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSPx interrupt flag bit will be set and if enabled, will wake the device. In Client mode, when MSSPx interrupts are enabled, after the host completes sending data, an MSSPx interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSPx interrupts may be disabled. TABLE 15-1: Name ANSELA REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 149 ANSB4 ANSB3(1) ANSB2(1) ANSB1(1) ANSB0(1) 150 ANSELB — — ANSB5 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 150 ANSELD ANSD7 ANSD6 ANSD5 ANSD4(2) ANSD3(2) ANSD2 ANSD1(2) ANSD0(2) 150 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 53 PIR3 PMD1 MSSP2MD MSSP1MD SSP1BUF SSP1 Receive Buffer/Transmit Register — SSP1CON1 WCOL SSPOV SSPEN CKP SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 256 SSP1STAT SMP CKE D/A P S R/W UA BF 252 SSP2BUF SSPM 253 SSP2 Receive Buffer/Transmit Register — SSP2CON1 WCOL SSPOV SSPEN CKP SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 256 SSP2STAT SMP CKE D/A P S R/W UA BF 252 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3(1) TRISB2(1) TRISB1(1) TRISB0(1) 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD5 TRISD4(2) TRISD3(2) TRISD2 TRISD1(2) TRISD0(2) 151 TRISD Legend: Note 1: 2: TRISD7 TRISD6 SSPM 253 Shaded bits are not used by the MSSPx in SPI mode. PIC18(L)F2XK22 devices. PIC18(L)F4XK22 devices. DS40001412H-page 214  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 15.3 I2C Mode Overview FIGURE 15-11: The Inter-Integrated Circuit Bus (I2C) is a multi-host serial data communication bus. Devices communicate in a host/client environment where the host devices initiate the communication. A client device is controlled through addressing. VDD SCLK The I2C bus specifies two signal connections: • Serial Clock (SCLx) • Serial Data (SDAx) Figure 15-2 shows the block diagram of the MSSPx module when operating in I2C mode. Both the SCLx and SDAx connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. Figure 15-11 shows a typical connection between two processors configured as host and client devices. The I2C bus can operate with one or more host devices and one or more client devices. There are four potential modes of operation for a given device: • Host Transmit mode (host is transmitting data to a client) • Host Receive mode (host is receiving data from a client) • Client Transmit mode (client is transmitting data to a host) • Client Receive mode (client is receiving data from the host) To begin communication, a host device starts out in Host Transmit mode. The host device sends out a Start bit followed by the address byte of the client it intends to communicate with. This is followed by a single Read/ Write bit, which determines whether the host intends to transmit to or receive data from the client device. If the requested client exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The host then continues in either Transmit mode or Receive mode and the client continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDAx line while the SCLx line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the host intends to read data from the client, and is sent out as a logical zero when it intends to write data to the client.  2010-2021 Microchip Technology Inc. I2C HOST/ CLIENT CONNECTION SCLK VDD Host Client SDIx SDOx The Acknowledge bit (ACK) is an active-low signal, which holds the SDAx line low to indicate to the transmitter that the client device has received the transmitted data and is ready to receive more. The transition of data bits is always performed while the SCLx line is held low. Transitions that occur while the SCLx line is held high are used to indicate Start and Stop bits. If the host intends to write to the client, then it repeatedly sends out a byte of data, with the client responding after each byte with an ACK bit. In this example, the host device is in Host Transmit mode and the client is in Client Receive mode. If the host intends to read from the client, then it repeatedly receives a byte of data from the client, and responds after each byte with an ACK bit. In this example, the host device is in Host Receive mode and the client is Client Transmit mode. On the last byte of data communicated, the host device may end the transmission by sending a Stop bit. If the host device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDAx line while the SCLx line is held high. In some cases, the host may want to maintain control of the bus and re-initiate another transmission. If so, the host device may send another Start bit in place of the Stop bit or last ACK bit when it is in receive mode. The I2C bus specifies three message protocols; • Single message where a host writes data to a client. • Single message where a host reads data from a client. • Combined message where a host initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more clients. DS40001412H-page 215 PIC18(L)F2X/4XK22 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCLx line, is called clock stretching. Clock stretching give client devices a mechanism to control the flow of data. When this detection is used on the SDAx line, it is called arbitration. Arbitration ensures that there is only one host device communicating at any single time. 15.3.1 CLOCK STRETCHING When a client device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. An addressed client device may hold the SCLx clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The host that is communicating with the client will attempt to raise the SCLx line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCLx connection is opendrain, the client has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 15.3.2 ARBITRATION Each host device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two host devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDAx data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels don’t match, loses arbitration, and must stop transmitting on the SDAx line. For example, if one transmitter holds the SDAx line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDAx line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDAx line. If this transmitter is also a host device, it also must stop driving the SCLx line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDAx line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Client Transmit mode can also be arbitrated, when a host addresses multiple clients, but this is less common. If two host devices are sending a message to two different client devices at the address stage, the host sending the lower client address always wins arbitration. When two host devices send messages to the same client address, and addresses can sometimes refer to multiple clients, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-host support. DS40001412H-page 216  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 15.4 I2C Mode Operation All MSSPx I2C communication is byte oriented and shifted out MSb first. Six SFR registers and 2 interrupt flags interface the module with the PIC microcontroller and user software. Two pins, SDAx and SCLx, are exercised by the module to communicate with other external I2C devices. 15.4.1 BYTE FORMAT TABLE 15-1: TERM Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Host The device that initiates a transfer, generates clock signals and terminates a transfer. Client The device addressed by the host. Multi-host A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one host at a time controls the bus. Winning arbitration ensures that the message is not corrupted. 2 All communication in I C is done in 9-bit segments. A byte is sent from a host to a client or vice-versa, followed by an Acknowledge bit sent back. After the 8th falling edge of the SCLx line, the device outputting data on the SDAx changes that pin to an input and reads in an acknowledge value on the next clock pulse. I2C BUS TERMS The clock signal, SCLx, is provided by the host. Data is valid to change while the SCLx signal is low, and sampled on the rising edge of the clock. Changes on the SDAx line while the SCLx line is high define special conditions on the bus, explained below. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. 15.4.2 DEFINITION OF I2C TERMINOLOGY Idle No host is controlling the bus, and both SDAx and SCLx lines are high. Active Any time one or more host devices are controlling the bus. Addressed Client Client device that has received a matching address and is actively being clocked by a host. Matching Address Address byte that is clocked into a client that matches the value stored in SSPxADD. Write Request Client receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Host sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Client. This data is the next and all following bytes until a Restart or Stop. There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Phillips I2C specification. 15.4.3 SDAx AND SCLx PINS I2C Selection of any mode with the SSPxEN bit set, forces the SCLx and SDAx pins to be open-drain. These pins may be set by the user to inputs by setting the appropriate TRIS bits. Note: Data is tied to output zero when an I2C mode is enabled. 15.4.4 SDAx HOLD TIME The hold time of the SDAx pin is selected by the SDAHT bit of the SSPxCON3 register. Hold time is the time SDAx is held valid after the falling edge of SCLx. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance.  2010-2021 Microchip Technology Inc. Clock Stretching When a device on the bus holds SCLx low to stall communication. Bus Collision Any time the SDAx line is sampled low by the module while it is outputting and expected high state. DS40001412H-page 217 PIC18(L)F2X/4XK22 15.4.5 START CONDITION 15.4.7 RESTART CONDITION The I2C specification defines a Start condition as a transition of SDAx from a high-to -low state while SCLx line is high. A Start condition is always generated by the host and signifies the transition of the bus from an Idle to an Active state. Figure 15-12 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid. A host can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the client that a Start would, resetting all client logic and preparing it to clock in an address. The host may want to address the same or another client. Figure 15-13 shows the wave form for a Restart condition. A bus collision can occur on a Start condition if the module samples the SDAx line low before asserting it low. This does not conform to the I2C specification that states no bus collision can occur on a Start. In 10-bit Addressing Client mode a Restart is required for the host to clock data out of the addressed client. Once a client has been fully addressed, matching both high and low address bytes, the host can issue a Restart and the high address byte with the R/W bit set. The client logic will then hold the clock and prepare to clock out data. 15.4.6 STOP CONDITION A Stop condition is a transition of the SDAx line from a low-to-high state while the SCLx line is high. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained. Until a Stop condition, a high address with R/W clear, or high address match fails. Note: At least one SCLx low time must appear before a Stop is valid, therefore, if the SDAx line goes low then high again while the SCLx line stays high, only the Start condition is detected. 15.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Client modes that do not typically support this function. Client modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. I2C START AND STOP CONDITIONS FIGURE 15-12: SDAx SCLx S Start P Change of Change of Data Allowed Data Allowed Condition FIGURE 15-13: Stop Condition I2C RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition DS40001412H-page 218  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 I2C Client Mode Operation 15.4.9 ACKNOWLEDGE SEQUENCE 15.5 The 9th SCLx pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDAx line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDAx line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. The MSSPx Client mode operates in one of four modes selected in the SSPxM bits of SSPxCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. The result of an ACK is placed in the ACKSTAT bit of the SSPxCON2 register. Client software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSPxCON2 register is set/cleared to determine the response. Client hardware will generate an ACK response if the AHEN and DHEN bits of the SSPxCON3 register are clear. There are certain conditions where an ACK will not be sent by the client. If the BF bit of the SSPxSTAT register or the SSPxOV bit of the SSPxCON1 register are set when a byte is received. When the module is addressed, after the 8th falling edge of SCLx on the bus, the ACKTIM bit of the SSPxCON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled. Modes with Start and Stop bit interrupts operated the same as the other modes with SSPxIF additionally getting set upon detection of a Start, Restart, or Stop condition. 15.5.1 CLIENT MODE ADDRESSES The SSPxADD register (Register 15-7) contains the Client mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes Idle and no indication is given to the software that anything happened. The SSPx Mask register (Register 15-6) affects the address matching process. See Section 15.5.9 “SSPx Mask Register” for more information. 15.5.1.1 I2C Client 7-bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 15.5.1.2 I2C Client 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. After the acknowledge of the high byte the UA bit is set and SCLx is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCLx is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the client is addressed, and clocking in the high address with the R/W bit set. The client hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a client after it has received a complete high and low address byte match.  2010-2021 Microchip Technology Inc. DS40001412H-page 219 PIC18(L)F2X/4XK22 15.5.2 CLIENT RECEPTION 15.5.2.2 7-bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. Client device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of SCLx. These additional interrupts allow the client software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBus™ that was not present on previous versions of this module. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPxOV of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modifies this operation. For more information see Register 15-5. An MSSPx interrupt is generated for each transferred data byte. Flag bit, SSPxIF, must be cleared by software. When the SEN bit of the SSPxCON2 register is set, SCLx will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPxCON1 register, except sometimes in 10-bit mode. See Section 15.2.3 “SPI Host Mode” for more detail. 15.5.2.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSPx module configured as an I2C client in 7-bit Addressing mode. All decisions made by hardware or software and their effect on reception. Figure 15-14 and Figure 15-5 are used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The client pulls SDAx low sending an ACK to the host, and sets SSPxIF bit. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. If SEN = 1; Client software sets CKP bit to release the SCLx line. The host clocks out a data byte. Client drives SDAx low sending an ACK to the host, and sets SSPxIF bit. Software clears SSPxIF. Software reads the received byte from SSPxBUF clearing BF. Steps 8-12 are repeated for all received bytes from the host. Host sends Stop condition, setting P bit of SSPxSTAT, and the bus goes Idle. DS40001412H-page 220 This list describes the steps that need to be taken by client software to use these options for I2C communication. Figure 15-16 displays a module using both address and data holding. Figure 15-17 includes the operation with the SEN bit of the SSPxCON2 register set. 1. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the 8th falling edge of SCLx. 3. Client clears the SSPxIF. 4. Client can look at the ACKTIM bit of the SSPxCON3 register to determine if the SSPxIF was after or before the ACK. 5. Client reads the address value from SSPxBUF, clearing the BF flag. 6. Client sets ACK value clocked out to the host by setting ACKDT. 7. Client releases the clock by setting CKP. 8. SSPxIF is set after an ACK, not after a NACK. 9. If SEN = 1 the client hardware will stretch the clock after the ACK. 10. Client clears SSPxIF. Note: SSPxIF is still set after the 9th falling edge of SCLx even if there is no clock stretching and BF has been cleared. Only if NACK is sent to host is SSPxIF not set. 11. SSPxIF set and CKP cleared after 8th falling edge of SCLx for a received data byte. 12. Client looks at ACKTIM bit of SSPxCON3 to determine the source of the interrupt. 13. Client reads the received data from SSPxBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the client sending an ACK = 1, or the host sending a Stop condition. If a Stop is sent and Interrupt on Stop detect is disabled, the client will only know by polling the P bit of the SSTSTAT register.  2010-2021 Microchip Technology Inc. I2C CLIENT, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0) Bus Host sends Stop condition From Client to Host Receiving Address SDAx SCLx S Receiving Data A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 ACK 8 9 Receiving Data D7 D6 D5 D4 D3 D2 D1 1 2 3 4 5 6 7 D0 ACK D7 8 9 1 ACK = 1 D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P SSPxIF Cleared by software Cleared by software BF SSPxBUF is read First byte of data is available in SSPxBUF SSPxOV SSPxOV set because SSPxBUF is still full. ACK is not sent. SSPxIF set on 9th falling edge of SCLx PIC18(L)F2X/4XK22 DS40001412H-page 221 FIGURE 15-14:  2010-2021 Microchip Technology Inc.  2010-2021 Microchip Technology Inc. I2C CLIENT, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 15-15: Bus Host sends Stop condition Receive Address SDAx SCLx S Receive Data A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 R/W=0 ACK 8 9 SEN Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 SEN ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P Clock is held low until CKP is set to ‘1’ SSPxIF Cleared by software BF SSPxBUF is read Cleared by software SSPxIF set on 9th falling edge of SCLx SSPxOV SSPxOV set because SSPxBUF is still full. ACK is not sent. CKP CKP is written to ‘1’ in software, releasing SCLx CKP is written to 1 in software, releasing SCLx SCLx is not held low because ACK= 1 DS40001412H-page 222 PIC18(L)F2X/4XK22 First byte of data is available in SSPxBUF I2C CLIENT, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) Host sends Stop condition Host Releases SDAx to client for ACK sequence Receiving Address SDAx Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 Received Data ACK ACK=1 D7 D6 D5 D4 D3 D2 D1 D0 SCLx S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPxIF If AHEN = 1: SSPxIF is set BF ACKDT SSPxIF is set on 9th falling edge of SCLx, after ACK Address is read from SSBUF Data is read from SSPxBUF Client software clears ACKDT to CKP Client software sets ACKDT to not ACK ACK the received byte When AHEN=1: CKP is cleared by hardware and SCLx is stretched No interrupt after not ACK from Client Cleared by software When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCLx CKP set by software, SCLx is released ACKTIM  2010-2021 Microchip Technology Inc. ACKTIM set by hardware on 8th falling edge of SCLx S P ACKTIM cleared by hardware in 9th rising edge of SCLx ACKTIM set by hardware on 8th falling edge of SCLx PIC18(L)F2X/4XK22 DS40001412H-page 223 FIGURE 15-16:  2010-2021 Microchip Technology Inc. I2C CLIENT, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) FIGURE 15-17: R/W = 0 Receiving Address SDAx ACK A7 A6 A5 A4 A3 A2 A1 SCLx S 1 2 3 4 5 6 7 Host sends Stop condition Host releases SDAx to client for ACK sequence 8 9 Receive Data 1 2 3 4 5 6 7 ACK Receive Data D7 D6 D5 D4 D3 D2 D1 D0 8 ACK 9 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P SSPxIF No interrupt after if not ACK from Client Cleared by software BF Received address is loaded into SSPxBUF Received data is available on SSPxBUF ACKDT Client software clears ACKDT to ACK the received byte SSPxBUF can be read any time before next byte is loaded Client sends not ACK CKP When DHEN = 1; on the 8th falling edge of SCLx of a received data byte, CKP is cleared ACKTIM ACKTIM is set by hardware on 8th falling edge of SCLx S DS40001412H-page 224 P ACKTIM is cleared by hardware on 9th rising edge of SCLx Set by software, release SCLx CKP is not cleared if not ACK PIC18(L)F2X/4XK22 When AHEN = 1; on the 8th falling edge of SCLx of an address byte, CKP is cleared PIC18(L)F2X/4XK22 15.5.3 CLIENT TRANSMISSION When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the client on the ninth bit. Following the ACK, client hardware clears the CKP bit and the SCLx pin is held low (see Section 15.5.6 “Clock Stretching” for more details). By stretching the clock, the host will be unable to assert another clock pulse until the client is done preparing the transmit data. The transmit data must be loaded into the SSPxBUF register which also loads the SSPxSR register. Then the SCLx pin may be released by setting the CKP bit of the SSPxCON1 register. The eight data bits are shifted out on the falling edge of the SCLx input. This ensures that the SDAx signal is valid during the SCLx high time. The ACK pulse from the host-receiver is latched on the rising edge of the ninth SCLx input pulse. This ACK value is copied to the ACKSTAT bit of the SSPxCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the client, the client goes Idle and waits for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCLx pin must be released by setting bit CKP. An MSSPx interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. 15.5.3.1 Client Mode Bus Collision A client receives a Read request and begins shifting data out on the SDAx line. If a bus collision is detected and the SBCDE bit of the SSPxCON3 register is set, the BCLxIF bit of the PIRx register is set. Once a bus collision is detected, the client goes Idle and waits to be addressed again. User software can use the BCLxIF bit to handle a client bus collision. 15.5.3.2 1. Host sends a Start condition on SDAx and SCLx. 2. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the client setting SSPxIF bit. 4. Client hardware generates an ACK and sets SSPxIF. 5. SSPxIF bit is cleared by user. 6. Software reads the received address from SSPxBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The client software loads the transmit data into SSPxBUF. 9. CKP bit is set releasing SCLx, allowing the host to clock the data out of the client. 10. SSPxIF is set after the ACK response from the host is loaded into the ACKSTAT register. 11. SSPxIF bit is cleared. 12. The client software checks the ACKSTAT bit to see if the host wants to clock out more data. Note 1: If the host ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCLx (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the host sends a not ACK; the clock is not held, but SSPxIF is still set. 15. The host sends a Restart condition or a Stop. 16. The client is no longer addressed. 7-bit Transmission A host device can transmit a read request to a client, and then clock data out of the client. The list below outlines what software for a client will need to do to accomplish a standard transmission. Figure 15-18 can be used as a reference to this list.  2010-2021 Microchip Technology Inc. DS40001412H-page 225  2010-2021 Microchip Technology Inc. FIGURE 15-18: I2C CLIENT, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) Host sends Stop condition Receiving Address SDAx SCLx S D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 2 3 4 5 6 7 8 9 Transmitting Data 2 3 4 5 6 Automatic ACK R/W = 1 Automatic A7 A6 A5 A4 A3 A2 A1 ACK 7 8 9 Transmitting Data 2 3 4 5 6 7 8 9 P SSPxIF Cleared by software BF Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF BF is automatically cleared after 8th falling edge of SCLx CKP When R/W is set SCLx is always held low after 9th SCLx falling edge Set by software CKP is not held for not ACK ACKSTAT R/W R/W is copied from the matching address byte D/A Indicates an address has been received DS40001412H-page 226 S P PIC18(L)F2X/4XK22 Host not ACK is copied to ACKSTAT PIC18(L)F2X/4XK22 15.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 15-19 displays a standard waveform of a 7-bit Address Client Transmission with AHEN enabled. 1. 2. Bus starts Idle. Host sends Start condition; the S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Host sends matching address with R/W bit set. After the 8th falling edge of the SCLx line the CKP bit is cleared and SSPxIF interrupt is generated. 4. Client software clears SSPxIF. 5. Client software reads ACKTIM bit of SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt. 6. Client reads the address value from the SSPxBUF register clearing the BF bit. 7. Client software decides from this information if it wishes to ACK or not ACK and sets ACKDT bit of the SSPxCON2 register accordingly. 8. Client sets the CKP bit releasing SCLx. 9. Host clocks in the ACK value from the client. 10. Client hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set. 11. Client software clears SSPxIF. 12. Client loads value to transmit to the host into SSPxBUF setting the BF bit. Note: SSPxBUF cannot be loaded until after the ACK. 13. Client sets CKP bit releasing the clock. 14. Host clocks out the data from the client and sends an ACK value on the 9th SCLx pulse. 15. Client hardware copies the ACK value into the ACKSTAT bit of the SSPxCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the host from the client. 17. If the host sends a not ACK the client releases the bus allowing the host to send a Stop and end the communication. Note: Host must send a not ACK on the last byte to ensure that the client releases the SCLx line to receive a Stop.  2010-2021 Microchip Technology Inc. DS40001412H-page 227  2010-2021 Microchip Technology Inc. I2C CLIENT, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) FIGURE 15-19: Host sends Stop condition Host releases SDAx to client for ACK sequence Receiving Address SDAx SCLx S 1 2 3 4 5 6 Automatic R/W = 1 ACK A7 A6 A5 A4 A3 A2 A1 7 8 9 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 1 2 3 4 5 6 7 8 9 Transmitting Data 2 3 4 5 6 7 ACK 8 9 P SSPxIF Cleared by software BF Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF BF is automatically cleared after 8th falling edge of SCLx ACKDT Client clears ACKDT to ACK address ACKSTAT CKP When AHEN = 1; CKP is cleared by hardware after receiving matching address. ACKTIM DS40001412H-page 228 R/W D/A ACKTIM is set on 8th falling edge of SCLx When R/W = 1; CKP is always cleared after ACK Set by software, releases SCLx ACKTIM is cleared on 9th rising edge of SCLx CKP not cleared after not ACK PIC18(L)F2X/4XK22 Host’s ACK response is copied to SSPxSTAT PIC18(L)F2X/4XK22 15.5.4 CLIENT MODE 10-BIT ADDRESS RECEPTION 15.5.5 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD This section describes a standard sequence of events for the MSSPx module configured as an I2C client in 10-bit Addressing mode (Figure 15-20) and is used as a visual reference for this description. Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCLx line is held low are the same. Figure 15-21 can be used as a reference of a client in 10-bit addressing with AHEN set. This is a step by step process of what must be done by client software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Host sends Start condition; S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Host sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set. Client sends ACK and SSPxIF is set. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. Client loads low address into SSPxADD, releasing SCLx. Host sends matching low address byte to the client; UA bit is set. Figure 15-22 shows a standard waveform for a client transmitter in 10-bit Addressing mode. Note: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Client sends ACK and SSPxIF is set. Note: If the low address does not match, SSPxIF and UA are still set so that the client software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Client clears SSPxIF. 11. Client reads the received matching address from SSPxBUF clearing BF. 12. Client loads high address into SSPxADD. 13. Host clocks a data byte to the client and clocks out the clients ACK on the 9th SCLx pulse; SSPxIF is set. 14. If SEN bit of SSPxCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Client clears SSPxIF. 16. Client reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the client sets CKP to release the SCLx. 18. Steps 13-17 repeat for each received byte. 19. Host sends Stop to end the transmission.  2010-2021 Microchip Technology Inc. DS40001412H-page 229  2010-2021 Microchip Technology Inc. I2C CLIENT, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 15-20: Host sends Stop condition Receive Second Address Byte Receive First Address Byte SDAx SCLx S 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 ACK 8 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 Receive Data Receive Data 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 P SCLx is held low while CKP = 0 SSPxIF Set by hardware on 9th falling edge Cleared by software BF Receive address is read from SSPxBUF If address matches SSPxADD it is loaded into SSPxBUF Data is read from SSPxBUF When UA = 1; SCLx is held low Software updates SSPxADD and releases SCLx CKP Set by software, When SEN = 1; releasing SCLx CKP is cleared after 9th falling edge of received byte DS40001412H-page 230 PIC18(L)F2X/4XK22 UA Receive First Address Byte SDAx SCLx S Receive Second Address Byte R/W = 0 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 ACK 8 9 UA Receive Data A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 9 UA Receive Data D7 D6 D5 D4 D3 D2 D1 1 2 3 4 5 6 7 D0 ACK D7 8 9 1 D6 D5 2 SSPxIF Set by hardware on 9th falling edge Cleared by software Cleared by software BF SSPxBUF can be read anytime before the next received byte Received data is read from SSPxBUF ACKDT Client software clears ACKDT to ACK the received byte UA  2010-2021 Microchip Technology Inc. Update to SSPxADD is not allowed until 9th falling edge of SCLx CKP If when AHEN = 1; on the 8th falling edge of SCLx of an address byte, CKP is cleared ACKTIM ACKTIM is set by hardware on 8th falling edge of SCLx Update of SSPxADD, clears UA and releases SCLx Set CKP with software releases SCLx PIC18(L)F2X/4XK22 DS40001412H-page 231 I2C CLIENT, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 15-21:  2010-2021 Microchip Technology Inc. FIGURE 15-22: I2C CLIENT, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) Host sends Restart event Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK SDAx SCLx S 1 2 3 4 5 6 7 8 9 Receiving Second Address Byte Receive First Address Byte A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 8 1 9 Host sends Stop condition Host sends not ACK 2 3 4 5 6 7 8 Transmitting Data Byte ACK 9 ACK = 1 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P Sr SSPxIF Set by hardware Cleared by software Set by hardware BF SSPxBUF loaded with received address Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF UA UA indicates SSPxADD must be updated High address is loaded back into SSPxADD When R/W = 1; CKP is cleared on 9th falling edge of SCLx ACKSTAT Set by software releases SCLx Host not ACK is copied R/W R/W is copied from the matching address byte D/A DS40001412H-page 232 Indicates an address has been received PIC18(L)F2X/4XK22 CKP After SSPxADD is updated, UA is cleared and SCLx is released PIC18(L)F2X/4XK22 15.5.6 CLOCK STRETCHING 15.5.6.2 10-bit Addressing Mode Clock stretching occurs when a device on the bus holds the SCLx line low effectively pausing communication. The client may stretch the clock to allow more time to handle data or prepare a response for the host device. A host device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a client is invisible to the host software and handled by the hardware that generates SCLx. In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the SCLx is stretched without CKP being cleared. SCLx is released immediately after a write to SSPxADD. The CKP bit of the SSPxCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCLx line to go low and then hold it. Setting CKP will release SCLx and allow more communication. 15.5.6.3 Byte NACKing 15.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit of SSPxSTAT is set, a read request, the client hardware will clear CKP. This allows the client time to update SSPxBUF with data to transfer to the host. If the SEN bit of SSPxCON2 is set, the client hardware will always stretch the clock after the ACK sequence. Once the client is ready; CKP is set by software and communication resumes. Note 1: The BF bit has no effect on whether the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPxBUF was read before the 9th falling edge of SCLx. 2: Previous versions of the module did not stretch the clock for a transmission if SSPxBUF was loaded before the 9th falling edge of SCLx. It is now always cleared for read requests. FIGURE 15-23: Note: Previous versions of the module did not stretch the clock if the second address byte did not match. When the AHEN bit of SSPxCON3 is set; CKP is cleared by hardware after the 8th falling edge of SCLx for a received matching address byte. When the DHEN bit of SSPxCON3 is set; CKP is cleared after the 8th falling edge of SCLx for received data. Stretching after the 8th falling edge of SCLx allows the client to look at the received address or data and decide if it wants to ACK the received data. 15.5.7 CLOCK SYNCHRONIZATION AND THE CKP BIT Any time the CKP bit is cleared, the module will wait for the SCLx line to go low and then hold it. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C host device has already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCLx. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCLx (see Figure 15-23). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX ‚ – 1 DX SCLx CKP Host device asserts clock Host device releases clock WR SSPxCON1  2010-2021 Microchip Technology Inc. DS40001412H-page 233 PIC18(L)F2X/4XK22 15.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The client will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the client addressed by the host device. The exception is the general call address which can address all devices. When this address is used, all devices may, in theory, respond with an acknowledge. If the AHEN bit of the SSPxCON3 register is set, just as with any other address reception, the client hardware will stretch the clock after the 8th falling edge of SCLx. The client must then set its ACKDT value and release the clock with communication progressing as it would normally. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPxCON2 register is set, the client module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the client clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and client software can read SSPxBUF and respond. Figure 15-24 shows a general call reception sequence. FIGURE 15-24: CLIENT MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDAx SCLx S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPxIF BF (SSPxSTAT) Cleared by software GCEN (SSPxCON2) SSPxBUF is read ’1’ 15.5.9 SSPx MASK REGISTER An SSPx Mask (SSPxMSK) register (Register 15-6) is available in I2C Client mode as a mask for the value held in the SSPxSR register during an address comparison operation. A zero (‘0’) bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSPx operation until written with a mask value. The SSPx Mask register is active during: • 7-bit Address mode: address compare of A. • 10-bit Address mode: address compare of A only. The SSPx mask has no effect during the reception of the first (high) byte of the address. DS40001412H-page 234  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 15.6 I2C Host Mode Host mode is enabled by setting and clearing the appropriate SSPxM bits in the SSPxCON1 register and by setting the SSPxEN bit. In Host mode, the SCLx and SDAx lines are set as inputs and are manipulated by the MSSPx hardware. Host mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSPx module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Firmware Controlled Host mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDAx and SCLx lines. The following events will cause the SSPx Interrupt Flag bit, SSPxIF, to be set (SSPx interrupt, if enabled): • • • • • Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1: The MSSPx module, when configured in I2C Host mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur 15.6.1 I2C HOST MODE OPERATION The host device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Host Transmitter mode, serial data is output through SDAx, while SCLx outputs the serial clock. The first byte transmitted contains the client address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Host Receive mode, the first byte transmitted contains the client address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit client address followed by a ‘1’ to indicate the receive bit. Serial data is received via SDAx, while SCLx outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCLx. See Section 15.7 “Baud Rate Generator” for more detail. 2: When in Host mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete.  2010-2021 Microchip Technology Inc. DS40001412H-page 235 PIC18(L)F2X/4XK22 15.6.2 CLOCK ARBITRATION Clock arbitration occurs when the host, during any receive, transmit or Repeated Start/Stop condition, releases the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 15-25). FIGURE 15-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDAx DX ‚ – 1 DX SCLx deasserted but client holds SCLx low (clock arbitration) SCLx allowed to transition high SCLx BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCLx is sampled high, reload takes place and BRG starts its count BRG Reload 15.6.3 WCOL STATUS FLAG If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not Idle. Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPxCON2 is disabled until the Start condition is complete. DS40001412H-page 236  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 15.6.4 I2C HOST MODE START CONDITION TIMING To initiate a Start condition (Figure 15-26), the user sets the Start Enable bit, SEN, of the SSPxCON2 register. If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD and starts its count. If SCLx and SDAx are both sampled high when the Baud Rate Generator times out (TBRG), the SDAx pin is driven low. The action of the SDAx being driven low while SCLx is high is the Start condition and causes the S bit of the SSPxSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPxCON2 register will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDAx line held low and the Start condition is complete. Note 1: If at the beginning of the Start condition, the SDAx and SCLx pins are already sampled low, or if during the Start condition, the SCLx line is sampled low before the SDAx line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLxIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2: The Philips I2C Specification states that a bus collision cannot occur on a Start. FIGURE 15-26: FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPxSTAT) At completion of Start bit, hardware clears SEN bit and sets SSPxIF bit SDAx = 1, SCLx = 1 TBRG TBRG Write to SSPxBUF occurs here SDAx 1st bit 2nd bit TBRG SCLx S  2010-2021 Microchip Technology Inc. TBRG DS40001412H-page 237 PIC18(L)F2X/4XK22 15.6.5 I2C HOST MODE REPEATED START CONDITION TIMING Following this, the RSEN bit of the SSPxCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the S bit of the SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out. A Repeated Start condition (Figure 15-27) occurs when the RSEN bit of the SSPxCON2 register is programmed high and the host state machine is no longer active. When the RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDAx pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDAx is sampled high, the SCLx pin will be deasserted (brought high). When SCLx is sampled high, the Baud Rate Generator is reloaded and begins counting. SDAx and SCLx must be sampled high for one TBRG. This action is then followed by assertion of the SDAx pin (SDAx = 0) for one TBRG while SCLx is high. SCLx is asserted low. FIGURE 15-27: Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDAx is sampled low when SCLx goes from low-to-high. • SCLx goes low before SDAx is asserted low. This may indicate that another host is attempting to transmit a data ‘1’. REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPxCON2 occurs here SDAx = 1, SCLx (no change) At completion of Start bit, hardware clears RSEN bit and sets SSPxIF SDAx = 1, SCLx = 1 TBRG TBRG TBRG 1st bit SDAx Write to SSPxBUF occurs here TBRG SCLx Sr TBRG Repeated Start DS40001412H-page 238  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 15.6.6 I2C HOST MODE TRANSMISSION 15.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted. SCLx is held low for one Baud Rate Generator rollover count (TBRG). Data may be valid before SCLx is released high. When the SCLx pin is released high, it is held that way for TBRG. The data on the SDAx pin must remain stable for that duration and some hold time after the next falling edge of SCLx. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the host releases SDAx. This allows the client device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the host receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPxIF bit is set and the host clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCLx low and SDAx unchanged (Figure 15-28). In Transmit mode, the ACKSTAT bit of the SSPxCON2 register is cleared when the client has sent an Acknowledge (ACK = 0) and is set when the client does not Acknowledge (ACK = 1). A client sends an Acknowledge when it has recognized its address (including a general call), or when the client has properly received its data. After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCLx until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the host will release the SDAx pin, allowing the client to respond with an Acknowledge. On the falling edge of the ninth clock, the host will sample the SDAx pin to see if the address was recognized by a client. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPxCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCLx low and allowing SDAx to float. 15.6.6.1 BF Status Flag ACKSTAT Status Flag 15.6.6.4 Typical Transmit Sequence: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. The MSSPx module will wait the required start time before any other operation takes place. The user loads the SSPxBUF with the client address to transmit. Address is shifted out the SDAx pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSPx module shifts in the ACK bit from the client device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSPx module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. The user loads the SSPxBUF with eight bits of data. Data is shifted out the SDAx pin until all eight bits are transmitted. The MSSPx module shifts in the ACK bit from the client device and writes its value into the ACKSTAT bit of the SSPxCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPxCON2 register. Interrupt is generated once the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all 8 bits are shifted out. 15.6.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission.  2010-2021 Microchip Technology Inc. DS40001412H-page 239  2010-2021 Microchip Technology Inc. FIGURE 15-28: I2C HOST MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) Write SSPxCON2 SEN = 1 Start condition begins From client, clear ACKSTAT bit SSPxCON2 SEN = 0 Transmit Address to Client A7 SDAx A6 A5 A4 ACKSTAT in SSPxCON2 = 1 A3 A2 Transmitting Data or Second Half of 10-bit Address R/W = 0 A1 ACK = 0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 SCLx held low while CPU responds to SSPxIF 2 3 4 5 6 7 8 SSPxBUF written with 7-bit address and R/W start transmit SCLx S 1 2 3 4 5 6 7 8 9 9 P SSPxIF Cleared by software Cleared by software service routine from SSPx interrupt Cleared by software BF (SSPxSTAT) SSPxBUF written SSPxBUF is written by software SEN After Start condition, SEN cleared by hardware R/W DS40001412H-page 240 PIC18(L)F2X/4XK22 PEN PIC18(L)F2X/4XK22 15.6.7 I2C HOST MODE RECEPTION Host mode reception (Figure 15-29) is enabled by programming the Receive Enable bit, RCEN, of the SSPxCON2 register. Note: The MSSPx module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCLx pin changes (high-to-low/ low-to-high) and data is shifted into the SSPxSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPxSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPxIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCLx low. The MSSPx is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable bit, ACKEN, of the SSPxCON2 register. 15.6.7.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPxSR. It is cleared when the SSPxBUF register is read. 15.6.7.2 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. SSPxOV Status Flag In receive operation, the SSPxOV bit is set when eight bits are received into the SSPxSR and the BF flag bit is already set from a previous reception. 15.6.7.3 15.6.7.4 Typical Receive Sequence: WCOL Status Flag 13. 14. 15. The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. User writes SSPxBUF with the client address to transmit and the R/W bit set. Address is shifted out the SDAx pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSPx module shifts in the ACK bit from the client device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSPx module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. User sets the RCEN bit of the SSPxCON2 register and the Host clocks in a byte from the client. After the 8th falling edge of SCLx, SSPxIF and BF are set. Host clears SSPxIF and reads the received byte from SSPxUF, clears BF. Host sets ACK value sent to client in ACKDT bit of the SSPxCON2 register and initiates the ACK by setting the ACKEN bit. Host ACK is clocked out to the client and SSPxIF is set. User clears SSPxIF. Steps 8-13 are repeated for each received byte from the client. Host sends a not ACK or Stop to end communication. If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).  2010-2021 Microchip Technology Inc. DS40001412H-page 241  2010-2021 Microchip Technology Inc. I2C HOST MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) FIGURE 15-29: Write to SSPxCON2 to start Acknowledge sequence SDAx = ACKDT (SSPxCON2) = 0 Write to SSPxCON2(SEN = 1), begin Start condition SEN = 0 Write to SSPxBUF occurs here, ACK from Client start XMIT A6 A5 A4 A3 A2 RCEN = 1, start next receive RCEN cleared automatically Transmit Address to Client A7 SDAx ACK PEN bit = 1 written here RCEN cleared automatically Receiving Data from Client Receiving Data from Client A1 R/W Set ACKEN, start Acknowledge sequence SDAx = ACKDT = 1 ACK from Host SDAx = ACKDT = 0 Host configured as a receiver by programming SSPxCON2 (RCEN = 1) D7 D6 D5 D4 D3 D2 D1 ACK D0 D7 D6 D5 D4 D3 D2 D1 D0 ACK Bus host terminates transfer ACK is not sent SCLx S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 Data shifted in on falling edge of CLK Set SSPxIF interrupt at end of receive Cleared by software Cleared by software Cleared by software BF (SSPxSTAT) P Set SSPxIF at end of receive Set SSPxIF interrupt at end of Acknowledge sequence SSPxIF SDAx = 0, SCLx = 1 while CPU responds to SSPxIF 9 8 Cleared by software Cleared in software SSPxOV SSPxOV is set because SSPxBUF is still full ACKEN DS40001412H-page 242 RCEN Host configured as a receiver by programming SSPxCON2 (RCEN = 1) RCEN cleared automatically ACK from Host SDAx = ACKDT = 0 RCEN cleared automatically Set P bit (SSPxSTAT) and SSPxIF PIC18(L)F2X/4XK22 Last bit is shifted into SSPxSR and contents are unloaded into SSPxBUF Set SSPxIF interrupt at end of Acknowledge sequence PIC18(L)F2X/4XK22 15.6.8 ACKNOWLEDGE SEQUENCE TIMING 15.6.9 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN, of the SSPxCON2 register. At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the host will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’. When the Baud Rate Generator times out, the SCLx pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDAx pin will be deasserted. When the SDAx pin is sampled high while SCLx is high, the P bit of the SSPxSTAT register is set. A TBRG later, the PEN bit is cleared and the SSPxIF bit is set (Figure 15-31). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN, of the SSPxCON2 register. When this bit is set, the SCLx pin is pulled low and the contents of the Acknowledge data bit are presented on the SDAx pin. If the user wishes to generate an Acknowledge, then the ACKDT bit may be cleared. If not, the user may set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCLx pin is deasserted (pulled high). When the SCLx pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCLx pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSPx module then goes into Idle mode (Figure 1530). 15.6.8.1 15.6.9.1 WCOL Status Flag If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL Status Flag If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 15-30: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPxCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDAx D0 SCLx ACK 8 9 SSPxIF SSPxIF set at the end of receive Cleared in software Cleared in software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period.  2010-2021 Microchip Technology Inc. DS40001412H-page 243 PIC18(L)F2X/4XK22 FIGURE 15-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG after SDAx sampled high. P bit (SSPxSTAT) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCLx ACK SDAx P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to set up Stop condition Note: TBRG = one Baud Rate Generator period. 15.6.10 SLEEP OPERATION the I2C client While in Sleep mode, module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSPx interrupt is enabled). 15.6.11 EFFECTS OF A RESET A Reset disables the MSSPx module and terminates the current transfer. 15.6.12 MULTI-HOST MODE In Multi-Host mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSPx module is disabled. Control of the I 2C bus may be taken when the P bit of the SSPxSTAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSPx interrupt will generate the interrupt when the Stop condition occurs. In multi-host operation, the SDAx line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLxIF bit. The states where arbitration can be lost are: • • • • • DS40001412H-page 244 Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 15.6.13 MULTI -HOST COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Host mode support is achieved by bus arbitration. When the host outputs address/data bits onto the SDAx pin, arbitration takes place when the host outputs a ‘1’ on SDAx, by letting SDAx float high and another host asserts a ‘0’. When the SCLx pin floats high, data may be stable. If the expected data on SDAx is a ‘1’ and the data sampled on the SDAx pin is ‘0’, then a bus collision has taken place. The host will set the Bus Collision Interrupt Flag, BCLxIF, and reset the I2C port to its Idle state (Figure 15-32). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDAx and SCLx lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. FIGURE 15-32: If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDAx and SCLx lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The host will continue to monitor the SDAx and SCLx pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Host mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCLx = 0 SDAx line pulled low by another source SDAx released by host Sample SDAx. While SCLx is high, data does not match what is driven by the host. Bus collision has occurred. SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF  2010-2021 Microchip Technology Inc. DS40001412H-page 245 PIC18(L)F2X/4XK22 15.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx are sampled low at the beginning of the Start condition (Figure 15-33). SCLx is sampled low before SDAx is asserted low (Figure 15-34). During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is already low, or the SCLx pin is already low, then all of the following occur: • the Start condition is aborted, • the BCLxIF flag is set and • the MSSPx module is reset to its Idle state (Figure 15-33). If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 15-35). If, however, a ‘1’ is sampled on the SDAx pin, the SDAx pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCLx pin is sampled as ‘0’ during this time, a bus collision does not occur. At the end of the BRG count, the SCLx pin is asserted low. Note: The Start condition begins with the SDAx and SCLx pins deasserted. When the SDAx pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCLx pin is sampled low while SDAx is high, a bus collision occurs because it is assumed that another host is attempting to drive a data ‘1’ during the Start condition. FIGURE 15-33: The reason that bus collision is not a factor during a Start condition is that no two bus hosts can assert a Start condition at the exact same time. Therefore, one host will always assert SDAx before the other. This condition does not cause a bus collision because the two hosts must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDAx ONLY) SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1. SDAx SCLx Set SEN, enable Start condition if SDAx = 1, SCLx = 1 SEN cleared automatically because of bus collision. SSPx module reset into Idle state. SEN BCLxIF SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared by software S SSPxIF SSPxIF and BCLxIF are cleared by software DS40001412H-page 246  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 15-34: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared by software S ’0’ ’0’ SSPxIF ’0’ ’0’ FIGURE 15-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Less than TBRG SDAx Set SSPxIF TBRG SDAx pulled low by other host. Reset BRG and assert SDAx. SCLx S SCLx pulled low after BRG time-out SEN BCLxIF Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 ’0’ S SSPxIF SDAx = 0, SCLx = 1, set SSPxIF  2010-2021 Microchip Technology Inc. Interrupts cleared by software DS40001412H-page 247 PIC18(L)F2X/4XK22 15.6.13.2 Bus Collision During a Repeated Start Condition If SDAx is low, a bus collision has occurred (i.e., another host is attempting to transmit a data ‘0’, Figure 15-36). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two hosts can assert SDAx at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDAx when SCLx goes from low level to high level (Case 1). SCLx goes low before SDAx is asserted low, indicating that another host is attempting to transmit a data ‘1’ (Case 2). If SCLx goes from high-to-low before the BRG times out and SDAx has not already been asserted, a bus collision occurs. In this case, another host is attempting to transmit a data ‘1’ during the Repeated Start condition, see Figure 15-37. When the user releases SDAx and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero. The SCLx pin is then deasserted and when sampled high, the SDAx pin is sampled. FIGURE 15-36: If, at the end of the BRG time-out, both SCLx and SDAx are still high, the SDAx pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDAx SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN BCLxIF Cleared by software S ’0’ SSPxIF ’0’ FIGURE 15-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx BCLxIF SCLx goes low before SDAx, set BCLxIF. Release SDAx and SCLx. Interrupt cleared by software RSEN S ’0’ SSPxIF DS40001412H-page 248  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 15.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to zero. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another host attempting to drive a data ‘0’ (Figure 15-38). If the SCLx pin is sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another host attempting to drive a data ‘0’ (Figure 15-39). Bus collision occurs during a Stop condition if: a) b) After the SDAx pin has been deasserted and allowed to float high, SDAx is sampled low after the BRG has timed out (Case 1). After the SCLx pin is deasserted, SCLx is sampled low before SDAx goes high (Case 2). FIGURE 15-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDAx SDAx sampled low after TBRG, set BCLxIF SDAx asserted low SCLx PEN BCLxIF P ’0’ SSPxIF ’0’ FIGURE 15-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx Assert SDAx SCLx SCLx goes low before SDAx goes high, set BCLxIF PEN BCLxIF P ’0’ SSPxIF ’0’  2010-2021 Microchip Technology Inc. DS40001412H-page 249 PIC18(L)F2X/4XK22 TABLE 15-2: Name ANSELA REGISTERS ASSOCIATED WITH I2C OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 Register on Page Bit 0 (1) ANSA0 ANSB0 (1) 149 150 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 150 ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1(2) ANSD0(2) 150 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 53 I2C Host mode. 258 PIR3 SSP2IF BCL2IF RC2IF PMD1 MSSP2MD MSSP1MD — 2C SSP1ADD SSP1 Address Register in I SSP1BUF Client mode. SSP1 Baud Rate Reload Register in SSP1 Receive Buffer/Transmit Register — SSP1CON1 WCOL SSPOV SSPEN CKP SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 255 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 256 SMP CKE D/A R/W UA BF SSP1MSK SSPM 253 SSP1 MASK Register bits SSP1STAT P S 257 SSP2 Address Register in I2C Client mode. SSP2 Baud Rate Reload Register in I2C Host mode. SSP2ADD SSP2BUF SSP2 Receive Buffer/Transmit Register SSP2CON1 252 258 — WCOL SSPOV SSPEN CKP SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 255 SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 256 SSP2MSK SSPM 253 SSP1 MASK Register bits 257 SMP CKE D/A P S R/W UA BF 252 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1(1) TRISB0(1) 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD2 TRISD1(2) TRISD0(2) 151 SSP2STAT TRISD Legend: Note 1: 2: TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 Shaded bits are not used by the MSSPx in I2C mode. PIC18(L)F2XK22 devices. PIC18(L)F4XK22 devices. DS40001412H-page 250  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 15.7 Baud Rate Generator The MSSPx module has a Baud Rate Generator available for clock generation in both I2C and SPI Host modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 15-7). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSPx is being operated in. Table 15-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. EQUATION 15-1: FO SC FCLO CK = ------------------------------------------------ SSPxAD D + 1  4 An internal signal “Reload” in Figure 15-40 triggers the value from SSPxADD to be loaded into the BRG counter. FIGURE 15-40: FCLOCK FORMULA BAUD RATE GENERATOR BLOCK DIAGRAM SSPxM SSPxM Reload SSPxADD Reload Control SCLx SSPxCLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 15-3: Note 1: MSSPx CLOCK RATE W/BRG FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz(1) 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz(1) 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application.  2010-2021 Microchip Technology Inc. DS40001412H-page 251 PIC18(L)F2X/4XK22 15.8 Register Definitions: MSSP Control REGISTER 15-2: SSPxSTAT: SSPx STATUS REGISTER R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Host mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Client mode: SMP must be cleared when SPI is used in Client mode In I2 C Host or Client mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Host or Client mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I2 C mode only: 1 = Enable input logic so that thresholds are compliant with SMbus specification 0 = Disable SMbus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Client mode: 1 = Read 0 = Write In I2 C Host mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty DS40001412H-page 252  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 15-3: SSPxCON1: SSPx CONTROL REGISTER 1 R/C/HS-0 R/C/HS-0 R/W-0 R/W-0 WCOL SSPxOV SSPxEN CKP R/W-0 R/W-0 R/W-0 R/W-0 SSPxM bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Host mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Client mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPxOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Client mode. In Client mode, the user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow. In Host mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register (must be cleared in software). 0 = No overflow In I2 C mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPxOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPxEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2 C mode: 1 = Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2 C Client mode: SCLx release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2 C Host mode: Unused in this mode  2010-2021 Microchip Technology Inc. DS40001412H-page 253 PIC18(L)F2X/4XK22 REGISTER 15-3: bit 3-0 SSPxCON1: SSPx CONTROL REGISTER 1 (CONTINUED) SSPxM: Synchronous Serial Port Mode Select bits 0000 = SPI Host mode, clock = FOSC/4 0001 = SPI Host mode, clock = FOSC/16 0010 = SPI Host mode, clock = FOSC/64 0011 = SPI Host mode, clock = TMR2 output/2 0100 = SPI Client mode, clock = SCKx pin, SSx pin control enabled 0101 = SPI Client mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0110 = I2C Client mode, 7-bit address 0111 = I2C Client mode, 10-bit address 1000 = I2C Host mode, clock = FOSC / (4 * (SSPxADD+1))(4) 1001 = Reserved 1010 = SPI Host mode, clock = FOSC/(4 * (SSPxADD+1)) 1011 = I2C firmware controlled Host mode (client Idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Client mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Client mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: 2: 3: 4: In Host mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When enabled, these pins must be properly configured as input or output. When enabled, the SDAx and SCLx pins must be configured as inputs. SSPxADD values of 0, 1 or 2 are not supported for I2C mode. DS40001412H-page 254  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 15-4: R/W-0 SSPxCON2: SSPx CONTROL REGISTER 2 R-0 GCEN ACKSTAT R/W-0 R/S/HC-0 R/S/HC-0 ACKDT ACKEN(1) (1) RCEN R/S/HC-0 (1) PEN R/S/HC-0 R/W/HC-0 (1) RSEN SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Client mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN(1): Acknowledge Sequence Enable bit (in I2C Host mode only) In Host Receive mode: 1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN(1): Receive Enable bit (in I2C Host mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN(1): Stop Condition Enable bit (in I2C Host mode only) SCKx Release Control: 1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN(1): Repeated Start Condition Enabled bit (in I2C Host mode only) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN(1): Start Condition Enabled bit (in I2C Host mode only) In Host mode: 1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition Idle In Client mode: 1 = Clock stretching is enabled for both client transmit and client receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).  2010-2021 Microchip Technology Inc. DS40001412H-page 255 PIC18(L)F2X/4XK22 REGISTER 15-5: SSPxCON3: SSPx CONTROL REGISTER 3 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCLx clock 0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCLx clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Client mode:(1) 1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPxOV bit of the SSPxCON1 register is set, and the buffer is not updated In I2C Host mode: This bit is ignored. In I2C Client mode: 1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPxOV bit only if the BF bit = 0. 0 = SSPxBUF is only updated when SSPxOV is clear bit 3 SDAHT: SDAx Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx 0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx bit 2 SBCDE: Client Mode Bus Collision Detect Enable bit (I2C Client mode only) If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the BCLxIF bit of the PIR2 register is set, and bus goes Idle 1 = Enable client bus collision interrupts 0 = Client bus collision interrupts are disabled AHEN: Address Hold Enable bit (I2C Client mode only) 1 = Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the SSPxCON1 register will be cleared and the SCLx will be held low. 0 = Address holding is disabled bit 1 Note 1: 2: 3: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF. This bit has no effect in Client modes for which Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set. DS40001412H-page 256  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 15-5: SSPxCON3: SSPx CONTROL REGISTER 3 (CONTINUED) DHEN: Data Hold Enable bit (I2C Client mode only) 1 = Following the 8th falling edge of SCLx for a received data byte; client hardware clears the CKP bit of the SSPxCON1 register and SCLx is held low. 0 = Data holding is disabled bit 0 Note 1: 2: 3: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF. This bit has no effect in Client modes for which Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set. REGISTER 15-6: SSPxMSK: SSPx MASK REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK: Mask bits 1 = The received address bit n is compared to SSPxADD to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK: Mask bit for I2C Client mode, 10-bit Address I2C Client mode, 10-bit address (SSPxM = 0111 or 1111): 1 = The received address bit 0 is compared to SSPxADD to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Client mode, 7-bit address, the bit is ignored  2010-2021 Microchip Technology Inc. DS40001412H-page 257 PIC18(L)F2X/4XK22 SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE) REGISTER 15-7: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Host mode: bit 7-0 ADD: Baud Rate Clock Divider bits SCLx pin clock period = ((ADD + 1) *4)/FOSC 10-Bit Client mode — Most Significant Address byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pattern sent by host is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Client mode — Least Significant Address byte: bit 7-0 ADD: Eight Least Significant bits of 10-bit address 7-Bit Client mode: bit 7-1 ADD: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. DS40001412H-page 258  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 16.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The EUSART module includes the following capabilities: • • • • • • • • • • The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a host synchronous device. FIGURE 16-1: Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous host Half-duplex synchronous client Programmable clock and data polarity The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: • Automatic detection and calibration of the baud rate • Wake-up on Break reception • 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 16-1 and Figure 16-2. EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXxIE Interrupt TXxIF TXREGx Register 8 MSb LSb (8) 0 • • • TXx/CKx pin Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT Baud Rate Generator FOSC ÷n +1 SPBRGHx TX9 n BRG16 SPBRGx Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0  2010-2021 Microchip Technology Inc. TX9D DS40001412H-page 259 PIC18(L)F2X/4XK22 FIGURE 16-2: EUSART RECEIVE BLOCK DIAGRAM CREN RXx/DTx pin Baud Rate Generator Data Recovery FOSC BRG16 SPBRGHx SPBRGx Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREGx Register 8 FIFO Data Bus RCxIF RCxIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTAx) • Receive Status and Control (RCSTAx) • Baud Rate Control (BAUDCONx) These registers are detailed in Register 16-1, Register 16-2 and Register 16-3, respectively. For all modes of EUSART operation, the TRIS control bits corresponding to the RXx/DTx and TXx/CKx pins may be set to ‘1’. The EUSART control will automatically reconfigure the pin from input to output, as needed. When the receiver or transmitter section is not enabled then the corresponding RXx/DTx or TXx/CKx pin may be used for general purpose input and output. DS40001412H-page 260  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 16.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH Mark state which represents a ‘1’ data bit, and a VOL Space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is eight bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 16-5 for examples of baud rate configurations. 16.1.1.2 Transmitting Data A transmission is initiated by writing a character to the TXREGx register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREGx is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREGx until the Stop bit of the previous character has been transmitted. The pending character in the TXREGx is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXREGx. 16.1.1.3 Transmit Data Polarity The EUSART transmits and receives the LSb first. The EUSART’s transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. The polarity of the transmit data can be controlled with the CKTXP bit of the BAUDCONx register. The default state of this bit is ‘0’ which selects high true transmit idle and data bits. Setting the CKTXP bit to ‘1’ will invert the transmit data resulting in low true idle and data bits. The CKTXP bit controls transmit data polarity only in Asynchronous mode. In Synchronous mode the CKTXP bit has a different function. 16.1.1 16.1.1.4 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 16-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXREGx register. 16.1.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: • TXEN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTAx register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTAx register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTAx register enables the EUSART and automatically configures the TXx/CKx I/O pin as an output. If the TXx/CKx pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: Transmit Interrupt Flag The TXxIF interrupt flag bit of the PIR1/PIR3 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXREGx. In other words, the TXxIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREGx. The TXxIF flag bit is not cleared immediately upon writing TXREGx. TXxIF becomes valid in the second instruction cycle following the write execution. Polling TXxIF immediately following the TXREGx write will return invalid results. The TXxIF bit is read-only, it cannot be set or cleared by software. The TXxIF interrupt can be enabled by setting the TXxIE interrupt enable bit of the PIE1/PIE3 register. However, the TXxIF flag bit will be set whenever the TXREGx is empty, regardless of the state of TXxIE enable bit. To use interrupts when transmitting data, set the TXxIE bit only when there is more data to send. Clear the TXxIE interrupt enable bit upon writing the last character of the transmission to the TXREGx. The TXxIF transmitter interrupt flag is set when the TXEN enable bit is set.  2010-2021 Microchip Technology Inc. DS40001412H-page 261 PIC18(L)F2X/4XK22 16.1.1.5 TSR Status 16.1.1.7 The TRMT bit of the TXSTAx register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREGx. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user needs to poll this bit to determine the TSR status. 1. 2. 3. 4. Note: 16.1.1.6 The TSR register is not mapped in data memory, so it is not available to the user. 5. Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTAx register is set the EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXSTAx register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the eight Least Significant bits into the TXREGx. All nine bits of data will be transferred to the TSR shift register immediately after the TXREGx is written. A special 9-bit Address mode is available for use with multiple receivers. See Section 16.1.2.8 “Address Detection” for more information on the Address mode. FIGURE 16-3: Write to TXREGx BRG Output (Shift Clock) TXx/CKx pin TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) DS40001412H-page 262 6. 7. 8. 9. Asynchronous Transmission Setup: Initialize the SPBRGHx:SPBRGx register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 16.4 “EUSART Baud Rate Generator (BRG)”). Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight Least Significant data bits are an address when the receiver is set for address detection. Set the CKTXP control bit if inverted transmit data polarity is desired. Enable the transmission by setting the TXEN control bit. This will cause the TXxIF interrupt bit to be set. If interrupts are desired, set the TXxIE interrupt enable bit. An interrupt will occur immediately provided that the GIE/GIEH and PEIE/GIEL bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit may be loaded into the TX9D data bit. Load 8-bit data into the TXREGx register. This will start the transmission. ASYNCHRONOUS TRANSMISSION Word 1 Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 1 TCY Word 1 Transmit Shift Reg  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREGx TXx/CKx pin Start bit bit 0 bit 1 Word 1 1 TCY TXxIF bit (Interrupt Reg. Flag) bit 7/8 Start bit Stop bit bit 0 Word 2 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 2 Word 1 BRG Output (Shift Clock) Word 1 Transmit Shift Reg Word 2 Transmit Shift Reg This timing diagram shows two consecutive transmissions. TABLE 16-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 TMR2IP TMR1IP IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF SSP2IF BCL2IF RC2IF PIR3 PMD0 SPEN RX9 RCSTA2 SPEN RX9 TMR2IE TMR1IE TMR3GIE TMR1GIE TMR2IF 121 123 117 119 TMR1IF 112 114 TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 SREN CREN ADDEN FERR OERR RX9D 270 SREN CREN ADDEN FERR OERR RX9D 270 UART2MD UART1MD TMR6MD RCSTA1 TMR3GIP TMR1GIP SPBRG1 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 EUSART2 Baud Rate Generator, High Byte — TXREG1 TXSTA1 EUSART1 Transmit Register CSRC TX9 TXEN TXREG2 TXSTA2 Legend: SYNC SENDB — BRGH TRMT TX9D EUSART2 Transmit Register CSRC TX9 TXEN SYNC SENDB 269 — BRGH TRMT TX9D 269 — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous transmission.  2010-2021 Microchip Technology Inc. DS40001412H-page 263 PIC18(L)F2X/4XK22 16.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 16-2. The data is received on the RXx/DTx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREGx register. 16.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: • CREN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCSTAx register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXSTAx register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTAx register enables the EUSART. The RXx/DTx I/O pin must be configured as an input by setting the corresponding TRIS control bit. If the RXx/DTx pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. DS40001412H-page 264 16.1.2.2 Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 16.1.2.5 “Receive Framing Error” for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCxIF interrupt flag bit of the PIR1/PIR3 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCREGx register. Note: 16.1.2.3 If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 16.1.2.6 “Receive Overrun Error” for more information on overrun errors. Receive Data Polarity The polarity of the receive data can be controlled with the DTRXP bit of the BAUDCONx register. The default state of this bit is ‘0’ which selects high true receive idle and data bits. Setting the DTRXP bit to ‘1’ will invert the receive data resulting in low true idle and data bits. The DTRXP bit controls receive data polarity only in Asynchronous mode. In Synchronous mode the DTRXP bit has a different function.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 16.1.2.4 Receive Interrupts The RCxIF interrupt flag bit of the PIR1/PIR3 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCxIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCxIF interrupts are enabled by setting the following bits: • RCxIE interrupt enable bit of the PIE1/PIE3 register • PEIE/GIEL peripheral interrupt enable bit of the INTCON register • GIE/GIEH global interrupt enable bit of the INTCON register The RCxIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. 16.1.2.5 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTAx register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.x The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTAx register which resets the EUSART. Clearing the CREN bit of the RCSTAx register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: 16.1.2.6 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTAx register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTAx register or by resetting the EUSART by clearing the SPEN bit of the RCSTAx register. 16.1.2.7 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTAx register is set, the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTAx register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREGx. 16.1.2.8 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTAx register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCxIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREGx will not clear the FERR bit.  2010-2021 Microchip Technology Inc. DS40001412H-page 265 PIC18(L)F2X/4XK22 16.1.2.9 Asynchronous Reception Setup: 1. Initialize the SPBRGHx:SPBRGx register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 16.4 “EUSART Baud Rate Generator (BRG)”). 2. Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. 3. Enable the serial port by setting the SPEN bit and the RXx/DTx pin TRIS bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCxIE interrupt enable bit and set the GIE/GIEH and PEIE/GIEL bits of the INTCON register. 5. If 9-bit reception is desired, set the RX9 bit. 6. Set the DTRXP if inverted receive polarity is desired. 7. Enable reception by setting the CREN bit. 8. The RCxIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCxIE interrupt enable bit was also set. 9. Read the RCSTAx register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCREGx register. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 16.1.2.10 This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. DS40001412H-page 266 9-bit Address Detection Mode Setup Initialize the SPBRGHx, SPBRGx register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 16.4 “EUSART Baud Rate Generator (BRG)”). Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCxIE interrupt enable bit and set the GIE/GIEH and PEIE/GIEL bits of the INTCON register. Enable 9-bit reception by setting the RX9 bit. Enable address detection by setting the ADDEN bit. Set the DTRXP if inverted receive polarity is desired. Enable reception by setting the CREN bit. The RCxIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCxIE interrupt enable bit was also set. Read the RCSTAx register to get the error flags. The ninth data bit will always be set. Get the received eight Least Significant data bits from the receive buffer by reading the RCREGx register. Software determines if this is the device’s address. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 16-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RXx/DTx pin bit 1 bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg Start bit bit 7/8 Stop bit bit 0 bit 7/8 Stop bit Word 2 RCREGx Word 1 RCREGx RCIDL Start bit Read Rcv Buffer Reg RCREGx RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx/DTx input. The RCREGx (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. TABLE 16-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 INTCON 109 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 OERR RX9D 270 RCREG1 RCSTA1 EUSART1 Receive Register SPEN RX9 RCREG2 RCSTA2 SREN CREN ADDEN — FERR EUSART2 Receive Register SPEN RX9 SREN CREN ADDEN — FERR OERR RX9D 270 SPBRG1 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 EUSART2 Baud Rate Generator, High Byte — TRISB (2) TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 150 ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 150 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 Legend: Note — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception. 1: PIC18(L)F4XK22 devices. 2: PIC18(L)F2XK22 devices.  2010-2021 Microchip Technology Inc. DS40001412H-page 267 PIC18(L)F2X/4XK22 16.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (HFINTOSC). However, the HFINTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the HFINTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 2.6 “Internal Clock Modes” for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 16.4.1 “AutoBaud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. DS40001412H-page 268  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 16.3 Register Definitions: EUSART Control REGISTER 16-1: TxSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Host mode (clock generated internally from BRG) 0 = Client mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode.  2010-2021 Microchip Technology Inc. DS40001412H-page 269 PIC18(L)F2X/4XK22 REGISTER 16-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Host: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Client Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREGx register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. DS40001412H-page 270  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 16-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been detected and the receiver is active Synchronous mode: Don’t care bit 5 DTRXP: Data/Receive Polarity Select bit Asynchronous mode: 1 = Receive data (RXx) is inverted (active-low) 0 = Receive data (RXx) is not inverted (active-high) Synchronous mode: 1 = Data (DTx) is inverted (active-low) 0 = Data (DTx) is not inverted (active-high) bit 4 CKTXP: Clock/Transmit Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TXx) is low 0 = Idle state for transmit (TXx) is high Synchronous mode: 1 = Data changes on the falling edge of the clock and is sampled on the rising edge of the clock 0 = Data changes on the rising edge of the clock and is sampled on the falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used (SPBRGHx:SPBRGx) 0 = 8-bit Baud Rate Generator is used (SPBRGx) bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received but RCxIF will be set on the falling edge. WUE will automatically clear on the rising edge. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care  2010-2021 Microchip Technology Inc. DS40001412H-page 271 PIC18(L)F2X/4XK22 16.4 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCONx register selects 16-bit mode. The SPBRGHx:SPBRGx register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXSTAx register and the BRG16 bit of the BAUDCONx register. In Synchronous mode, the BRGH bit is ignored. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock. EXAMPLE 16-1: For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: F O SC D esired Baud Rate = ------------------------------------------------------------------------64 [SPBRG H x:SPBRG x] + 1 Solving for SPBRGHx:SPBRGx: F O SC --------------------------------------------D esired Baud Rate X = ---------------------------------------------– 1 64 Table 16-3 contains the formulas for determining the baud rate. Example 16-1 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various Asynchronous modes have been computed for the user’s convenience and are shown in Table 16-5. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. 16000000 ----------------------9600 = ----------------------- – 1 64 =  25.042 = 25 16000000 C alculated Baud Rate = -------------------------64 25 + 1 Writing a new value to the SPBRGHx, SPBRGx register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. TABLE 16-3: Calc.Baud Rate – D esired Baud Rate Error = -------------------------------------------------------------------------------------------D esired Baud Rate  9615 – 9600 = ---------------------------------- = 0.16% 9600 BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 1 0 16-bit/Asynchronous SYNC BRG16 BRGH 0 0 0 0 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous 1 = 9615 BAUD RATE FORMULAS Configuration Bits Legend: CALCULATING BAUD RATE ERROR FOSC/[16 (n+1)] FOSC/[4 (n+1)] x = Don’t care, n = value of SPBRGHx, SPBRGx register pair. DS40001412H-page 272  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 16-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 UART2MD UART1MD TMR6MD TMR5MD TMR4MD RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 PMD0 TMR3MD TMR2MD TMR1MD 52 SPBRG1 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 EUSART2 Baud Rate Generator, High Byte PIR1 — ADIF RC1IF PIR3 SSP2IF BCL2IF CSRC TX9 CSRC TX9 TXSTA1 TXSTA2 Legend: — TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 RC2IF TX2IF CTMUIF TXEN SYNC SENDB BRGH TRMT TX9D 269 TXEN SYNC SENDB BRGH TRMT TX9D 269 TMR5GIF TMR3GIF TMR1GIF 114 — = unimplemented, read as ‘0’. Shaded bits are not used by the BRG. TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE 300 FOSC = 64.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRxG value (decimal) — — — — — — — — — — — — — 1200 0.00 239 1202 0.16 207 1200 0.00 143 Actual Rate % Error SPBRGx value (decimal) Actual Rate % Error SPBRGx value (decimal) Actual Rate % Error SPBRGx value (decimal) 1200 — — 2400 — — — 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9615 0.16 103 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 95 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.23k 0.16 51 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k 58.82k 2.12 16 57.60k 0.00 7 — — — 57.60k 0.00 2 115.2k 111.11k -3.55 8 — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRGx value (decimal) FOSC = 4.000 MHz Actual Rate FOSC = 3.6864 MHz % Error SPBRGx value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRGx value (decimal) Actual Rate % Error SPBRGx value (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — —  2010-2021 Microchip Technology Inc. DS40001412H-page 273 PIC18(L)F2X/4XK22 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 64.000 MHz Actual Rate % Error SPBRGx value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRGx value (decimal) FOSC = 16.000 MHz Actual Rate % Error FOSC = 11.0592 MHz SPBRGx value (decimal) Actual Rate % Error SPBRGx value (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 — — — 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 — — — 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 207 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 57.97k 0.64 68 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 114.29k -0.79 34 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5 SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error FOSC = 4.000 MHz SPBRGx value (decimal) Actual Rate % Error FOSC = 3.6864 MHz SPBRGx value (decimal) Actual Rate % Error FOSC = 1.000 MHz SxBRGx value (decimal) Actual Rate % Error SPBRGx value (decimal) 207 300 — — — — — — — — — 300 0.16 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 — 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 64.000 MHz Actual Rate FOSC = 18.432 MHz % Error SPBRGHx: SPBRGx (decimal) Actual Rate % Error SPBRGHx: SPBRGx (decimal) FOSC = 16.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRGHx :SPBRGx (decimal) Actual Rate % Error SPBRGHx: SPBRGx (decimal) 300 300.0 0.00 13332 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303 1200 1200.1 0.01 3332 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2399 -0.02 1666 2400 0.00 479 2398 -0.08 416 2400 0.00 287 9600 9592 -0.08 416 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 383 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 207 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 57.97k 0.64 68 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 114.29k -0.79 34 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5 DS40001412H-page 274  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz FOSC = 4.000 MHz Actual Rate % Error SPBRGHx: SPBRGx (decimal) Actual Rate % Error FOSC = 3.6864 MHz SPBRGHx: SPBRGx (decimal) Actual Rate % Error FOSC = 1.000 MHz SPBRGHx :SPBRGx (decimal) Actual Rate % Error SPBRGHx: SPBRGx (decimal) 207 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 — 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 64.000 MHz Actual Rate % Error FOSC = 18.432 MHz SPBRGHx: SPBRGx (decimal) Actual Rate % Error SPBRGHx: SPBRGx (decimal) FOSC = 16.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRGHx :SPBRGx (decimal) Actual Rate % Error SPBRGHx: SPBRGx (decimal) 300 300 0.00 53332 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215 1200 1200 0.00 13332 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303 2400 2400 0.00 6666 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9598.1 -0.02 1666 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 1535 10425 0.08 441 10417 0.00 383 10433 0.16 264 143 19.2k 19.21k 0.04 832 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 57.6k 57.55k -0.08 277 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 115.11k -0.08 138 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPBRGHx: SPBRGx (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPBRGHx: SPBRGx (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRGHx :SPBRGx (decimal) Actual Rate % Error SPBRGHx: SPBRGx (decimal) 832 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0.00 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —  2010-2021 Microchip Technology Inc. DS40001412H-page 275 PIC18(L)F2X/4XK22 16.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RXx signal, the RXx signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDCONx register starts the auto-baud calibration sequence (Section 16.4.2 “Auto-baud Overflow”). While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPBRGx begins counting up using the BRG counter clock as shown in Table 16-6. The fifth rising edge will occur on the RXx/ DTx pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPBRGHx:SPBRGx register pair, the ABDEN bit is automatically cleared, and the RCxIF interrupt flag is set. A read operation on the RCREGx needs to be performed to clear the RCxIF interrupt. RCREGx content may be discarded. When calibrating for modes that do not use the SPBRGHx register the user can verify that the SPBRGx register did not overflow by checking for 00h in the SPBRGHx register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 16-6. During ABD, both the SPBRGHx and SPBRGx registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPBRGHx FIGURE 16-6: Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 16.4.3 “Auto-Wake-up on Break”). 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the autobaud counter starts counting at one. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract one from the SPBRGHx:SPBRGx register pair. TABLE 16-6: BRG COUNTER CLOCK RATES BRG16 BRGH BRG Base Clock BRG ABD Clock 0 0 FOSC/64 FOSC/512 0 1 FOSC/16 FOSC/128 1 0 FOSC/16 FOSC/128 1 FOSC/4 FOSC/32 1 Note: During the ABD sequence, SPBRGx and SPBRGHx registers are both used as a 16-bit counter, independent of BRG16 setting. AUTOMATIC BAUD RATE CALIBRATION XXXXh BRG Value and SPBRGx registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. RXx/DTx pin 0000h 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RCxIF bit (Interrupt) Read RCREGx SPBRGx XXh 1Ch SPBRGHx XXh 00h Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. DS40001412H-page 276  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 16.4.2 AUTO-BAUD OVERFLOW During the course of automatic baud detection, the ABDOVF bit of the BAUDCONx register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGHx:SPBRGx register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RXx/DTx pin. Upon detecting the fifth RXx/DTx edge, the hardware will set the RCxIF interrupt flag and clear the ABDEN bit of the BAUDCONx register. The RCxIF flag can be subsequently cleared by reading the RCREGx. The ABDOVF flag can be cleared by software directly. To terminate the auto-baud process before the RCxIF flag is set, clear the ABDEN bit then clear the ABDOVF bit. The ABDOVF bit will remain set if the ABDEN bit is not cleared first. 16.4.3 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake up due to activity on the RXx/DTx line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDCONx register. Once set, the normal receive sequence on RXx/DTx is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wakeup event consists of a high-to-low transition on the RXx/DTx line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCxIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 16-7), and asynchronously if the device is in Sleep mode (Figure 16-8). The interrupt condition is cleared by reading the RCREGx register. 16.4.3.1 Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid nonzero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all ‘0’s. This must be 10 or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Start-up Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared by hardware by a rising edge on RXx/DTx. The interrupt condition is then cleared by software by reading the RCREGx register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. The WUE bit is automatically cleared by the low-to-high transition on the RXx line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character.  2010-2021 Microchip Technology Inc. DS40001412H-page 277 PIC18(L)F2X/4XK22 FIGURE 16-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RXx/DTx Line RCxIF Note 1: Cleared due to User Read of RCREGx The EUSART remains in Idle while the WUE bit is set. FIGURE 16-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RXx/DTx Line Note 1 RCxIF Sleep Command Executed Note 1: 2: Sleep Ends Cleared due to User Read of RCREGx If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence may not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. DS40001412H-page 278  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 16.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTAx register. The Break character transmission is then initiated by a write to the TXREGx. The value of data written to TXREGx will be ignored and all ‘0’s will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXSTAx register indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 16-9 for the timing of the Break character sequence. 16.4.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus host. 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXREGx with a dummy character to initiate transmission (the value is ignored). Write ‘55h’ to TXREGx to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. FIGURE 16-9: Write to TXREGx When the TXREGx becomes empty, as indicated by the TXxIF, the next data byte can be written to TXREGx. 16.4.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCSTAx register and the Received data as indicated by RCREGx. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when; • RCxIF bit is set • FERR bit is set • RCREGx = 00h The second method uses the Auto-Wake-up feature described in Section 16.4.3 “Auto-Wake-up on Break”. By enabling this feature, the EUSART will sample the next two transitions on RXx/DTx, cause an RCxIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDCONx register before placing the EUSART in Sleep mode. SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TXx/CKx (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXxIF bit (Transmit interrupt Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB (send Break control bit)  2010-2021 Microchip Technology Inc. SENDB Sampled Here Auto Cleared DS40001412H-page 279 PIC18(L)F2X/4XK22 16.5 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single host and one or more clients. The host device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Client devices can take advantage of the host clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Clients use the external clock supplied by the host to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that host and client devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a host or client device. Start and Stop bits are not used in synchronous transmissions. 16.5.1 SYNCHRONOUS HOST MODE The following bits are used to configure the EUSART for Synchronous Host operation: • • • • • SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXSTAx register configures the device for synchronous operation. Setting the CSRC bit of the TXSTAx register configures the device as a host. Clearing the SREN and CREN bits of the RCSTAx register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTAx register enables the EUSART. If the RXx/DTx or TXx/CKx pins are shared with an analog peripheral the analog I/O functions must be disabled by clearing the corresponding ANSEL bits. The TRIS bits corresponding to the RXx/DTx and TXx/CKx pins may be set. 16.5.1.1 16.5.1.2 Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the CKTXP bit of the BAUDCONx register. Setting the CKTXP bit sets the clock Idle state as high. When the CKTXP bit is set, the data changes on the falling edge of each clock and is sampled on the rising edge of each clock. Clearing the CKTXP bit sets the Idle state as low. When the CKTXP bit is cleared, the data changes on the rising edge of each clock and is sampled on the falling edge of each clock. 16.5.1.3 Synchronous Host Transmission Data is transferred out of the device on the RXx/DTx pin. The RXx/DTx and TXx/CKx pin output drivers are automatically enabled when the EUSART is configured for synchronous host transmit operation. A transmission is initiated by writing a character to the TXREGx register. If the TSR still contains all or part of a previous character the new character data is held in the TXREGx until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREGx is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXREGx. Each data bit changes on the leading edge of the host clock and remains valid until the subsequent leading clock edge. Note: 16.5.1.4 The TSR register is not mapped in data memory, so it is not available to the user. Data Polarity The polarity of the transmit and receive data can be controlled with the DTRXP bit of the BAUDCONx register. The default state of this bit is ‘0’ which selects high true transmit and receive data. Setting the DTRXP bit to ‘1’ will invert the data resulting in low true transmit and receive data. Host Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a host transmits the clock on the TXx/CKx line. The TXx/CKx pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. DS40001412H-page 280  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 16.5.1.5 1. 2. 3. Synchronous Host Transmission Setup: 4. 5. 6. 7. Initialize the SPBRGHx, SPBRGx register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 16.4 “EUSART Baud Rate Generator (BRG)”). Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. Enable the synchronous host serial port by setting bits SYNC, SPEN and CSRC. Set the TRIS bits corresponding to the RXx/DTx and TXx/CKx I/O pins. FIGURE 16-10: 8. 9. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXxIE, GIE/ GIEH and PEIE/GIEL interrupt enable bits. If 9-bit transmission is selected, the ninth bit may be loaded in the TX9D bit. Start transmission by loading data to the TXREGx register. SYNCHRONOUS TRANSMISSION RXx/DTx pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TXx/CKx pin (SCKP = 0) TXx/CKx pin (SCKP = 1) Write to TXREGx Reg Write Word 1 Write Word 2 TXxIF bit (Interrupt Flag) TRMT bit TXEN bit Note: ‘1’ ‘1’ Sync Host mode, SPBRGx = 0, continuous transmission of two 8-bit words. FIGURE 16-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RXx/DTx pin bit 0 bit 1 bit 2 bit 6 bit 7 TXx/CKx pin Write to TXREGx reg TXxIF bit TRMT bit TXEN bit  2010-2021 Microchip Technology Inc. DS40001412H-page 281 PIC18(L)F2X/4XK22 TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS HOST TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 INTCON 109 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP PIE1 — ADIE RC1IE TX1IE SSP1IE PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIP TMR3GIP TMR1GIP CCP1IE TMR2IE TMR1IE TMR5GIE TMR3GIE TMR1GIE 121 123 117 119 PIR1 — ADIF RC1IF TX1IF SSP1IF PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 52 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 270 SPBRG1 CCP1IF TMR2IF TMR1IF 112 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 EUSART2 Baud Rate Generator, High Byte — TRISB (2) TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 150 ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 150 BRGH TRMT TX9D 269 BRGH TRMT TX9D 269 TXREG1 TXSTA1 EUSART1 Transmit Register CSRC TX9 TXEN CSRC TX9 TXEN TXREG2 TXSTA2 Legend: Note SYNC SENDB — EUSART2 Transmit Register SYNC SENDB — — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous host transmission. 1: PIC18(L)F4XK22 devices. 2: PIC18(L)F2XK22 devices. DS40001412H-page 282  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 16.5.1.6 Synchronous Host Reception Data is received at the RXx/DTx pin. The RXx/DTx pin output driver must be disabled by setting the corresponding TRIS bits when the EUSART is configured for synchronous host receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTAx register) or the Continuous Receive Enable bit (CREN of the RCSTAx register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RXx/DTx pin on the trailing edge of the TXx/CKx clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCxIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCREGx. The RCxIF bit remains set as long as there are un-read characters in the receive FIFO. 16.5.1.7 Client Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a client receives the clock on the TXx/CKx line. The TXx/CKx pin output driver must be disabled by setting the associated TRIS bit when the device is configured for synchronous client transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles may be received as there are data bits. 16.5.1.8 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREGx is read to access the FIFO. When this happens the OERR bit of the RCSTAx register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREGx.  2010-2021 Microchip Technology Inc. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTAx register or by clearing the SPEN bit which resets the EUSART. 16.5.1.9 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTAx register is set the EUSART will shift 9-bits into the RSR for each character received. The RX9D bit of the RCSTAx register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREGx. 16.5.1.10 Synchronous Host Reception Setup: 1. Initialize the SPBRGHx, SPBRGx register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. 3. Enable the synchronous host serial port by setting bits SYNC, SPEN and CSRC. Disable RXx/ DTx and TXx/CKx output drivers by setting the corresponding TRIS bits. 4. Ensure bits CREN and SREN are clear. 5. If using interrupts, set the GIE/GIEH and PEIE/ GIEL bits of the INTCON register and set RCxIE. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCxIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCxIE was set. 9. Read the RCSTAx register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCREGx register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTAx register or by clearing the SPEN bit which resets the EUSART. DS40001412H-page 283 PIC18(L)F2X/4XK22 FIGURE 16-12: SYNCHRONOUS RECEPTION (HOST MODE, SREN) RXx/DTx pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TXx/CKx pin (SCKP = 0) TXx/CKx pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCxIF bit (Interrupt) Read RCREGx Note: Timing diagram demonstrates Sync Host mode with bit SREN = 1 and bit BRGH = 0. TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS HOST RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 TMR4MD TMR3MD TMR2MD TMR1MD 52 PIR3 PMD0 UART2MD UART1MD TMR6MD TMR5MD RCREG1 RCSTA1 TMR1IE TMR3GIE TMR1GIE EUSART1 Receive Register SPEN RX9 SREN RCREG2 RCSTA2 TMR2IE 123 CREN ADDEN RX9 SREN CREN ADDEN 119 — FERR OERR RX9D EUSART2 Receive Register SPEN 117 270 — FERR OERR RX9D 270 SPBRG1 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 EUSART2 Baud Rate Generator, High Byte — TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous host reception. DS40001412H-page 284  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 16.5.2 SYNCHRONOUS CLIENT MODE The following bits are used to configure the EUSART for Synchronous client operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXSTAx register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTAx register configures the device as a client. Clearing the SREN and CREN bits of the RCSTAx register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTAx register enables the EUSART. If the RXx/DTx or TXx/CKx pins are shared with an analog peripheral the analog I/O functions must be disabled by clearing the corresponding ANSEL bits. 16.5.2.1 The operation of the Synchronous Host and Client modes are identical (see Section 16.5.1.3 “Synchronous Host Transmission”), except in the case of the Sleep mode. If two words are written to the TXREGx and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. 4. 5. RXx/DTx and TXx/CKx pin output drivers must be disabled by setting the corresponding TRIS bits. The first character will immediately transfer to the TSR register and transmit. The second word will remain in TXREGx register. The TXxIF bit will not be set. After the first character has been shifted out of TSR, the TXREGx register will transfer the second character to the TSR and the TXxIF bit will now be set. If the PEIE/GIEL and TXxIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE/GIEH bit is also set, the program will call the Interrupt Service Routine. 16.5.2.2 1. 2. 3. 4. 5. 6. 7. 8.  2010-2021 Microchip Technology Inc. EUSART Synchronous Client Transmit Synchronous Client Transmission Setup: Set the SYNC and SPEN bits and clear the CSRC bit. Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. Clear the CREN and SREN bits. If using interrupts, ensure that the GIE/GIEH and PEIE/GIEL bits of the INTCON register are set and set the TXxIE bit. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant eight bits to the TXREGx register. DS40001412H-page 285 PIC18(L)F2X/4XK22 TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS CLIENT TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PMD0 TMR6MD TMR5MD TMR4MD UART2MD UART1MD RCSTA1 SPEN RX9 RCSTA2 SPEN RX9 TMR3MD TMR2MD TMR1MD 52 SREN CREN ADDEN FERR OERR RX9D 270 SREN CREN ADDEN FERR OERR RX9D 270 SPBRG1 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 EUSART2 Baud Rate Generator, High Byte — ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 150 ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 150 TRISB(2) TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 TXREG1 TXSTA1 EUSART1 Transmit Register CSRC TX9 TXREG2 TXSTA2 TXEN SYNC SENDB — BRGH TRMT TX9D 269 EUSART2 Transmit Register CSRC TX9 TXEN SYNC SENDB — BRGH TRMT TX9D 269 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous client transmission. Note 1: PIC18(L)F4XK22 devices. 2: PIC18(L)F2XK22 devices. DS40001412H-page 286  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 16.5.2.3 EUSART Synchronous Client Reception 16.5.2.4 The operation of the Synchronous Host and Client modes is identical (Section 16.5.1.6 “Synchronous Host Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don't care” in Client mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREGx register. If the RCxIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE/GIEH bit is also set, the program will branch to the interrupt vector. 4. 5. 6. 7. 8. 9. Synchronous Client Reception Setup: Set the SYNC and SPEN bits and clear the CSRC bit. Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. If using interrupts, ensure that the GIE/GIEH and PEIE/GIEL bits of the INTCON register are set and set the RCxIE bit. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCxIF bit will be set when reception is complete. An interrupt will be generated if the RCxIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTAx register. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREGx register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTAx register or by clearing the SPEN bit which resets the EUSART. TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS CLIENT RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 271 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 TMR4MD TMR3MD TMR2MD TMR1MD 52 PIR3 PMD0 UART2MD UART1MD TMR6MD TMR5MD RCREG1 RCSTA1 EUSART1 Receive Register SPEN RX9 SREN RCREG2 RCSTA2 CREN ADDEN — FERR OERR RX9D EUSART2 Receive Register SPEN RX9 SREN CREN ADDEN 270 — FERR OERR RX9D 270 SPBRG1 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 TXSTA1 TXSTA2 Legend: EUSART2 Baud Rate Generator, High Byte — CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 269 — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous client reception.  2010-2021 Microchip Technology Inc. DS40001412H-page 287 PIC18(L)F2X/4XK22 17.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC voltage reference is software selectable to either VDD or a voltage applied to the external reference pins. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH). FIGURE 17-1: The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake up the device from Sleep. Figure 17-1 shows the block diagram of the ADC. ADC BLOCK DIAGRAM 5 FVR BUF2 11111 DAC 11110 CTMU 11101 AN28(1) AN27(1) CHS 11100 11011 ADCMD AN5(1) AN4 AN3 AN2 AN1 AN0 ADON 00101 10-Bit ADC 00100 GO/DONE 10 00011 00010 ADFM 00001 0 = Left Justify 1 = Right Justify 00000 10 2 PVCFG ADRESH AVDD VREF+/AN3 01 FVR BUF2 10 Reserved 11 2 AVSS VREF-/AN2 ADRESL 00 NVCFG 00 01 Reserved 10 Reserved 11 Note: Additional ADC channels AN5-AN7 and AN20-AN27 are only available on PIC18(L)F4XK22 devices. DS40001412H-page 288  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 17.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 17.1.1 PORT CONFIGURATION The ANSELx and TRISx registers configure the A/D port pins. Any port pin needed as an analog input may have its corresponding ANSx bit set to disable the digital input buffer and TRISx bit set to disable the digital output driver. If the TRISx bit is cleared, the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the ANSx bits and the TRIS bits. Note 1: When reading the PORT register, all pins with their corresponding ANSx bit set read as cleared (a low level). However, analog conversion of pins configured as digital inputs (ANSx bit cleared and TRISx bit set) will be accurately converted. 2: Analog levels on any pin with the corresponding ANSx bit cleared may cause the digital input buffer to consume current out of the device’s specification limits. 3: The PBADEN bit in Configuration Register 3H configures PORTB pins to reset as analog or digital pins by controlling how the bits in ANSELB are reset. 17.1.2 CHANNEL SELECTION 17.1.3 ADC VOLTAGE REFERENCE The PVCFG and NVCFG bits of the ADCON1 register provide independent control of the positive and negative voltage references. The positive voltage reference can be: • VDD • the fixed voltage reference (FVR BUF2) • an external voltage source (VREF+) The negative voltage reference can be: • VSS • an external voltage source (VREF-) 17.1.4 SELECTING AND CONFIGURING ACQUISITION TIME The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. Acquisition time is set with the ACQT bits of the ADCON2 register. Acquisition delays cover a range of 2 to 20 TAD. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there is no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. Manual acquisition is selected when ACQT = 000. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This option is also the default Reset state of the ACQT bits and is compatible with devices that do not offer programmable acquisition times. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. When an acquisition time is programmed, there is no indication of when the acquisition time ends and the conversion begins. The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 17.2 “ADC Operation” for more information.  2010-2021 Microchip Technology Inc. DS40001412H-page 289 PIC18(L)F2X/4XK22 17.1.5 CONVERSION CLOCK 17.1.6 The source of the conversion clock is software selectable via the ADCS bits of the ADCON2 register. There are seven possible clock options: • • • • • • • The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital Conversion. The ADC interrupt enable is the ADIE bit in the PIE1 register and the interrupt priority is the ADIP bit in the IPR1 register. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADIF bit must be cleared by software. FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator) Note: The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11 TAD periods as shown in Figure 17-3. Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. TABLE 17-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) ADC Clock Source FOSC/2 FOSC/4 ADCS 000 100 Device Frequency (FOSC) 64 MHz 31.25 ns(2) 62.5 ns(2) ns(2) FOSC/8 001 400 FOSC/16 101 250 ns(2) FOSC/32 010 ns(2) FOSC/64 110 FRC Legend: Note 1: 2: 3: 4: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. For correct conversion, the appropriate TAD specification must be met. See A/D conversion requirements in Table 27-22 for more information. Table 17-1 gives examples of appropriate ADC clock selections. Note: INTERRUPTS x11 500 1.0 s (1,4) 1-4 s 16 MHz 4 MHz 125 250 ns(2) 1.0 s 4.0 s(3) 500 ns(2) 2.0 s 8.0 s(3) 1.0 s 4.0 s(3) 16.0 s(3) 2.0 s s(3) 32.0 s(3) 16.0 s(3) 64.0 s(3) (1,4) 1-4 s(1,4) 4.0 s(3) (1,4) 1-4 s 500 8.0 ns(2) 1 MHz ns(2) 1-4 s 2.0 s Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 1.7 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the device in Sleep mode. DS40001412H-page 290  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 17.1.7 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON2 register controls the output format. Figure 17-2 shows the two output formats. FIGURE 17-2: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 10-bit A/D Result bit 0 Unimplemented: Read as ‘0’ MSB (ADFM = 1) bit 7 Unimplemented: Read as ‘0’  2010-2021 Microchip Technology Inc. LSB bit 0 bit 7 bit 0 10-bit A/D Result DS40001412H-page 291 PIC18(L)F2X/4XK22 17.2 ADC Operation 17.2.1 Figure 17-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT bits are cleared. A conversion is started after the following instruction to allow entry into SLEEP mode before the conversion begins. STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will, depending on the ACQT bits of the ADCON2 register, either immediately start the Analog-to-Digital conversion or start an acquisition delay followed by the Analog-toDigital conversion. Figure 17-4 shows the operation of the A/D converter after the GO bit has been set and the ACQT bits are set to ‘010’ which selects a 4 TAD acquisition time before the conversion starts. Note: FIGURE 17-3: The GO/DONE bit may not be set in the same instruction that turns on the ADC. Refer to Section 17.2.10 “A/D Conversion Procedure”. A/D CONVERSION TAD CYCLES (ACQT = 000, TACQ = 0) TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 1 TCY b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Discharge Holding capacitor is disconnected from analog input (0.5 TAD) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 17-4: A/D CONVERSION TAD CYCLES (ACQT = 010, TACQ = 4 TAD) TAD Cycles TACQT Cycles 1 2 3 Automatic Acquisition Time 4 1 3 4 5 6 7 8 9 10 11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts (Holding capacitor is disconnected from analog input) Set GO bit (Holding capacitor continues acquiring input) DS40001412H-page 292 2 1 TCY Discharge On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 17.2.2 COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF flag bit • Update the ADRESH:ADRESL registers with new conversion result 17.2.3 DISCHARGE The discharge phase is used to initialize the value of the capacitor array. The array is discharged after every sample. This feature helps to optimize the unity-gain amplifier, as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous measure values. 17.2.4 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared by software. The ADRESH:ADRESL registers will not be updated with the partially complete Analog-to-Digital conversion sample. Instead, the ADRESH:ADRESL register pair will retain the value of the previous conversion. Note: 17.2.5 A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. DELAY BETWEEN CONVERSIONS After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, the currently selected channel is reconnected to the charge holding capacitor commencing the next acquisition. 17.2.6 ADC OPERATION IN POWERMANAGED MODES The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT and ADCS bits in ADCON2 may be updated in accordance with the clock source to be used in that mode. After entering the mode, an A/D acquisition or conversion may be started. Once started, the device may continue to be clocked by the same clock source until the conversion has been completed. If desired, the device may be placed into the corresponding Idle mode during the conversion. If the device clock frequency is less than 1 MHz, the A/D FRC clock source may be selected.  2010-2021 Microchip Technology Inc. 17.2.7 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 17.2.8 SPECIAL EVENT TRIGGER Two Special Event Triggers are available to start an A/D conversion: CTMU and CCP5. The Special Event Trigger source is selected using the TRIGSEL bit in ADCON1. When TRIGSEL = 0, the CCP5 module is selected as the Special Event Trigger source. To enable the Special Event Trigger in the CCP module, set CCP5M = 1011, in the CCP5CON register. When TRIGSEL = 1, the CTMU module is selected. The CTMU module requires that the CTTRIG bit in CTMUCONH is set to enable the Special Event Trigger. In addition to TRIGSEL bit, the following steps are required to start an A/D conversion: • The A/D module must be enabled (ADON = 1) • The appropriate analog input channel selected • The minimum acquisition period set one of these ways: - Timing provided by the user - Selection made of an appropriate TACQ time With these conditions met, the trigger sets the GO/DONE bit and the A/D acquisition starts. If the A/D module is not enabled (ADON = 0), the module ignores the Special Event Trigger. 17.2.9 PERIPHERAL MODULE DISABLE When a peripheral module is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power consumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module’s clock source. The Module Disable bit for the ADC module is ADCMD in the PMD2 Register. See Section 3.0 “Power-Managed Modes” for more information. DS40001412H-page 293 PIC18(L)F2X/4XK22 17.2.10 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: • Disable pin output driver (See TRIS register) • Configure pin as analog Configure the ADC module: • Select ADC conversion clock • Configure voltage reference • Select ADC input channel • Select result format • Select acquisition delay • Turn on ADC module Configure ADC interrupt (optional): • Clear ADC interrupt flag • Enable ADC interrupt • Enable peripheral interrupt • Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) Read ADC Result Clear the ADC interrupt flag (required if interrupt is enabled). EXAMPLE 17-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd and Vss as reference, Frc clock and AN0 input. ; ;Conversion start & polling for completion ; are included. ; MOVLW B’10101111’ ;right justify, Frc, MOVWF ADCON2 ; & 12 TAD ACQ time MOVLW B’00000000’ ;ADC ref = Vdd,Vss MOVWF ADCON1 ; BSF TRISA,0 ;Set RA0 to input BSF ANSEL,0 ;Set RA0 to analog MOVLW B’00000001’ ;AN0, ADC on MOVWF ADCON0 ; BSF ADCON0,GO ;Start conversion ADCPoll: BTFSC ADCON0,GO ;Is conversion done? BRA ADCPoll ;No, test again ; Result is complete - store 2 MSbits in ; RESULTHI and 8 LSbits in RESULTLO MOVFF ADRESH,RESULTHI MOVFF ADRESL,RESULTLO Note 1: The global interrupt can be disabled if the user is attempting to wake up from Sleep and resume in-line code execution. 2: Software delay required if ACQT bits are set to zero delay. See Section 17.4 “A/D Acquisition Requirements”. DS40001412H-page 294  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 17.3 Register Definitions: ADC Control Note: Analog pin control is determined by the ANSELx registers (see Register 10-2) REGISTER 17-1: U-0 ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 CHS R/W-0 R/W-0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS: Analog Channel Select bits 00000 = AN0 00001 = AN1 00010 = AN2 00011 = AN3 00100 = AN4 00101 = AN5(1) 00110 = AN6(1) 00111 = AN7(1) 01000 = AN8 01001 = AN9 01010 = AN10 01011 = AN11 01100 = AN12 01101 = AN13 01110 = AN14 01111 = AN15 10000 = AN16 10001 = AN17 10010 = AN18 10011 = AN19 10100 = AN20(1) 10101 = AN21(1) 10110 = AN22(1) 10111 = AN23(1) 11000 = AN24(1) 11001 = AN25(1) 11010 = AN26(1) 11011 = AN27(1) 11100 = Reserved 11101 = CTMU 11110 = DAC 11111 = FVR BUF2 (1.024V/2.048V/2.096V Volt Fixed Voltage Reference)(2) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: 2: Available on PIC18(L)F4XK22 devices only. Allow greater than 15 s acquisition time when measuring the Fixed Voltage Reference.  2010-2021 Microchip Technology Inc. DS40001412H-page 295 PIC18(L)F2X/4XK22 REGISTER 17-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 TRIGSEL — — — R/W-0 R/W-0 R/W-0 PVCFG R/W-0 NVCFG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TRIGSEL: Special Trigger Select bit 1 = Selects the special trigger from CTMU 0 = Selects the special trigger from CCP5 bit 6-4 Unimplemented: Read as ‘0’ bit 3-2 PVCFG: Positive Voltage Reference Configuration bits 00 = A/D VREF+ connected to internal signal, AVDD 01 = A/D VREF+ connected to external pin, VREF+ 10 = A/D VREF+ connected to internal signal, FVR BUF2 11 = Reserved (by default, A/D VREF+ connected to internal signal, AVDD) bit 1-0 NVCFG: Negative Voltage Reference Configuration bits 00 = A/D VREF- connected to internal signal, AVSS 01 = A/D VREF- connected to external pin, VREF10 = Reserved (by default, A/D VREF- connected to internal signal, AVSS) 11 = Reserved (by default, A/D VREF- connected to internal signal, AVSS) DS40001412H-page 296  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 17-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 ADFM — R/W-0 R/W-0 R/W-0 ACQT R/W-0 R/W-0 R/W-0 ADCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 x = Bit is unknown ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT: A/D Acquisition time select bits. Acquisition time is the duration that the A/D charge holding capacitor remains connected to A/D channel from the instant the GO/DONE bit is set until conversions begins. 000 = 0(1) 001 = 2 TAD 010 = 4 TAD 011 = 6 TAD 100 = 8 TAD 101 = 12 TAD 110 = 16 TAD 111 = 20 TAD bit 2-0 ADCS: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal) Note 1: When the A/D clock source is selected as FRC then the start of conversion is delayed by one instruction cycle after the GO/DONE bit is set to allow the SLEEP instruction to be executed.  2010-2021 Microchip Technology Inc. DS40001412H-page 297 PIC18(L)F2X/4XK22 REGISTER 17-4: R/W-x ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 17-5: R/W-x ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x ADRES R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. REGISTER 17-6: x = Bit is unknown ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — — — — — R/W-x R/W-x ADRES bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 17-7: R/W-x x = Bit is unknown ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES: ADC Result Register bits Lower eight bits of 10-bit conversion result DS40001412H-page 298  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 17.4 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 17-5. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 17-5. The maximum recommended impedance for analog sources is 3 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D EQUATION 17-1: acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 17-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. ACQUISITION TIME EXAMPLE Tem perature = 50°C and externalim pedance of10k 3.0V V D D Assumptions: TAC Q = Am plifier Settling Tim e + H old Capacitor Charging Tim e + Tem perature Coefficient = TAM P + TC + TC O FF = 5µs + TC +   Tem perature -25°C   0.05µs/°C   The value for TC can be approximated with the following equations: 1 V AP P LIED  1 – ----------- = V C H O LD  2047 ;[1] VCHOLD charged to within 1/2 lsb –TC ---------  RC V AP P LIED  1 – e  = V C H O LD   ;[2] VCHOLD charge response to VAPPLIED –Tc --------  1 RC V A PP LIE D  1 – e  = V A P PLIE D  1 – -----------  2047   ;combining [1] and [2] Solving for TC: TC = –C H O LD  R IC + R SS + R S ln(1/2047) = –13.5pF  1k + 700 + 10k  ln(0.0004885) = 1.20µs Therefore: TAC Q = 5µs + 1.20µs +   50°C-25°C   0.05 s/°C   = 7.45µs Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.  2010-2021 Microchip Technology Inc. DS40001412H-page 299 PIC18(L)F2X/4XK22 FIGURE 17-5: ANALOG INPUT MODEL VDD Rs VA ANx RIC  1k CPIN 5 pF I LEAKAGE(1) Sampling Switch SS Rss CHOLD = 13.5 pF Legend: CPIN = Input Capacitance I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC SS = Sampling Switch CHOLD = Sample/Hold Capacitance Note 1: VDD Discharge Switch VSS/VREF- 3.5V 3.0V 2.5V 2.0V 1.5V .1 1 10 Rss (k) 100 See Section 27.0 “Electrical Specifications”. FIGURE 17-6: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh ADC Output Code 3FDh 3FCh 1/2 LSB ideal 3FBh Full-Scale Transition 004h 003h 002h 001h 000h Analog Input Voltage 1/2 LSB ideal VSS/VREF- DS40001412H-page 300 Zero-Scale Transition VDD/VREF+  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 17-2: Name REGISTERS ASSOCIATED WITH A/D OPERATION Bit 7 Bit 6 Bit 5 — ADCON0 — ADCON1 TRIGSEL — ADCON2 ADFM — Bit 4 Bit 3 Bit 2 CHS — Bit 1 Bit 0 GO/DONE ADON PVCFG NVCFG ACQT ADCS Register on Page 295 296 297 ADRESH A/D Result, High Byte 298 ADRESL A/D Result, Low Byte 298 ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 149 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 150 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 150 ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 150 ANSELE(1) — — — — — ANSE2 ANSE1 ANSE0 151 CCP5CON — — DC5B CCP5M 198 CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 323 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123 IPR4 — — — — — CCP5IP CCP4IP CCP3IP 124 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119 PIE4 — — — — — CCP5IE CCP4IE CCP3IE 120 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114 PIR4 — — — — — CCP5IF CCP4IF CCP3IF 115 PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 53 PMD2 — — — — CTMUMD CMP2MD CMP1MD ADCMD 54 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 151 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 151 Legend: Note 1: — = unimplemented locations, read as ‘0’. Shaded bits are not used by this module. Available on PIC18(L)F4XK22 devices. TABLE 17-3: Name CONFIG3H Legend: CONFIGURATION REGISTERS ASSOCIATED WITH THE ADC MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 MCLRE — P2BMX T3CMX HFOFST Bit 2 CCP3MX Bit 1 Bit 0 Register on Page PBADEN CCP2MX 348 — = unimplemented locations, read as ‘0’. Shaded bits are not used by the ADC module.  2010-2021 Microchip Technology Inc. DS40001412H-page 301 PIC18(L)F2X/4XK22 18.0 COMPARATOR MODULE Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution. The analog comparator module includes the following features: • • • • • • • • • • Independent comparator control Programmable input selection Comparator output is available internally/externally Programmable output polarity Interrupt-on-change Wake-up from Sleep Programmable Speed/Power optimization PWM shutdown Programmable and fixed voltage reference Selectable Hysteresis 18.1 FIGURE 18-1: SINGLE COMPARATOR VIN+ + VIN- – Output VINVIN+ Output Note: The black areas of the output of the comparator represents the uncertainty due to input offsets and response time. Comparator Overview A single comparator is shown in Figure 18-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. DS40001412H-page 302  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 18-2: COMPARATOR C1/C2 SIMPLIFIED BLOCK DIAGRAM CxCH CxON(1) 2 C12IN0- 0 C12IN1- 1 C12IN2- CxSP D CxVIN- 2 C12IN3- CxVIN+ 3 Q1 - (2),(3) EN Cx + D Q3(2) DAC Output Read or Write of CMxCON0 0 0 FVR BUF1 1 1 Q To Interrupts (CxIF) EN CL CxR CxIN+ Q To CMxCON0 (CxOUT) CM2CON1 (MCxOUT) Reset async_CXOUT CxPOL CxSYNC CXVREF to PWM Logic CxOE TRIS bit 0 CXRSEL D Q 1 CxOUT Timer1 Clock sync_CxOUT - to SR Latch - to TxG MUX(4) Note 1: 2: 3: 4: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode. Synchronized comparator output may not be used to gate Timer1 in conjunction with synchronized T1CKI.  2010-2021 Microchip Technology Inc. DS40001412H-page 303 PIC18(L)F2X/4XK22 18.2 Comparator Control Each comparator has a separate control and Configuration register: CM1CON0 for Comparator C1 and CM2CON0 for Comparator C2. In addition, Comparator C2 has a second control register, CM2CON1, for controlling the interaction with Timer1 and simultaneous reading of both comparator outputs. The CM1CON0 and CM2CON0 registers (see Register 18-1) contain the control and status bits for the following: • • • • • • Enable Input selection Reference selection Output selection Output polarity Speed selection 18.2.1 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 18.2.5 COMPARATOR INPUT SELECTION The CxCH bits of the CMxCON0 register direct one of four analog input pins to the comparator inverting input. Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a noninverted output. Table 18-1 shows the output state versus input conditions, including polarity control. TABLE 18-1: 18.2.3 To use CxIN+ and C12INx- pins as analog inputs, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. COMPARATOR REFERENCE SELECTION Setting the CxR bit of the CMxCON0 register directs an internal voltage reference or an analog input pin to the noninverting input of the comparator. See Section 21.0 “Fixed Voltage Reference (FVR)” for more information on the Internal Voltage Reference module. 18.2.4 COMPARATOR OUTPUT SELECTION The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CM2CON1 register. In order to make the output available for an external connection, the following conditions must be true: COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS Input Condition CxPOL CxOUT CxVIN- > CxVIN+ 0 0 CxVIN- < CxVIN+ 0 1 CxVIN- > CxVIN+ 1 1 CxVIN- 1 0 18.2.6 Note: COMPARATOR OUTPUT POLARITY COMPARATOR ENABLE Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current consumption. 18.2.2 Note 1: The CxOE bit overrides the PORT data latch. Setting the CxON has no impact on the port override. < CxVIN+ COMPARATOR SPEED SELECTION The trade-off between speed or power can be optimized during program execution with the CxSP control bit. The default state for this bit is ‘1’ which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to ‘0’. 18.3 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section 27.0 “Electrical Specifications” for more details. • CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set DS40001412H-page 304  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 18.4 Comparator Interrupt Operation The comparator interrupt flag will be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusiveor gate (see Figure 18-2). The first latch is updated with the comparator output value, when the CMxCON0 register is read or written. The value is latched on the third cycle of the system clock, also known as Q3. This first latch retains the comparator value until another read or write of the CMxCON0 register occurs or a Reset takes place. The second latch is updated with the comparator output value on every first cycle of the system clock, also known as Q1. When the output value of the comparator changes, the second latch is updated and the output values of both latches no longer match one another, resulting in a mismatch condition. The latch outputs are fed directly into the inputs of an exclusive-or gate. This mismatch condition is detected by the exclusive-or gate and sent to the interrupt circuitry. The mismatch condition will persist until the first latch value is updated by performing a read of the CMxCON0 register or the comparator output returns to the previous state. Note 1: A write operation to the CMxCON0 register will also clear the mismatch condition because all writes include a read operation at the beginning of the write cycle. 2: Comparator interrupts will operate correctly regardless of the state of CxOE. When the mismatch condition occurs, the comparator interrupt flag is set. The interrupt flag is triggered by the edge of the changing value coming from the exclusiveor gate. This means that the interrupt flag can be reset once it is triggered without the additional step of reading or writing the CMxCON0 register to clear the mismatch latches. When the mismatch registers are cleared, an interrupt will occur upon the comparator’s return to the previous state, otherwise no interrupt will be generated. Software will need to maintain information about the status of the comparator output, as read from the CMxCON0 register, or CM2CON1 register, to determine the actual change that has occurred. See Figures 18-3 and 18-4. The CxIF bit of the PIR2 register is the comparator interrupt flag. This bit must be reset by software by clearing it to ‘0’. Since it is also possible to write a ‘1’ to this register, an interrupt can be generated. In mid-range Compatibility mode the CxIE bit of the PIE2 register and the PEIE/GIEL and GIE/GIEH bits of the INTCON register must all be set to enable comparator interrupts. If any of these bits are cleared, the interrupt is not enabled, although the CxIF bit of the PIR2 register will still be set if an interrupt condition occurs.  2010-2021 Microchip Technology Inc. 18.4.1 PRESETTING THE MISMATCH LATCHES The comparator mismatch latches can be preset to the desired state before the comparators are enabled. When the comparator is off the CxPOL bit controls the CxOUT level. Set the CxPOL bit to the desired CxOUT noninterrupt level while the CxON bit is cleared. Then, configure the desired CxPOL level in the same instruction that the CxON bit is set. Since all register writes are performed as a read-modify-write, the mismatch latches will be cleared during the instruction read phase and the actual configuration of the CxON and CxPOL bits will be occur in the final write phase. FIGURE 18-3: COMPARATOR INTERRUPT TIMING W/O CMxCON0 READ Q1 Q3 CxIN+ TRT CxIN Set CxIF (edge) CxIF Reset by Software FIGURE 18-4: COMPARATOR INTERRUPT TIMING WITH CMxCON0 READ Q1 Q3 CxIN+ TRT CxOUT Set CxIF (edge) CxIF Cleared by CMxCON0 Read Reset by Software Note 1: If a change in the CMxCON0 register (CxOUT) may occur when a read operation is being executed (start of the Q2 cycle), then the CxIF interrupt flag of the PIR2 register may not get set. 2: When either comparator is first enabled, bias circuitry in the comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 s for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts. DS40001412H-page 305 PIC18(L)F2X/4XK22 18.5 Operation During Sleep 18.7 The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in Section 27.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. Each comparator is turned off by clearing the CxON bit of the CMxCON0 register. A change to the comparator output can wake up the device from Sleep. To enable the comparator to wake the device from Sleep, the CxIE bit of the PIE2 register and the PEIE/GIEL bit of the INTCON register must be set. The instruction following the SLEEP instruction always executes following a wake from Sleep. If the GIE/GIEH bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine. 18.6 Effects of a Reset A device Reset forces the CMxCON0 and CM2CON1 registers to their Reset states. This forces both comparators and the voltage references to their Off states.Comparator Control Registers. FIGURE 18-5: Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 18-5. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, may have very little leakage current to minimize inaccuracies introduced. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. ANALOG INPUT MODEL VDD VT  0.6V Rs < 10K RIC To Comparator AIN VA CPIN 5 pF VT  0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC RS = Source Impedance = Analog Voltage VA = Threshold Voltage VT Note 1: See Section 27.0 “Electrical Specifications”. DS40001412H-page 306  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 18.8 Additional Comparator Features There are four additional comparator features: • • • • Simultaneous read of comparator outputs Internal reference selection Hysteresis selection Output Synchronization 18.8.1 SIMULTANEOUS COMPARATOR OUTPUT READ The MC1OUT and MC2OUT bits of the CM2CON1 register are mirror copies of both comparator outputs. The ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers. Note 1: Obtaining the status of C1OUT or C2OUT by reading CM2CON1 does not affect the comparator interrupt mismatch registers. 18.8.2 INTERNAL REFERENCE SELECTION There are two internal voltage references available to the noninverting input of each comparator. One of these is the Fixed Voltage Reference (FVR) and the other is the variable Digital-to-Analog Converter (DAC). The CxRSEL bit of the CM2CON1 register determines which of these references is routed to the Comparator Voltage reference output (CXVREF). Further routing to the comparator is accomplished by the CxR bit of the CMxCON0 register. See Section 21.0 “Fixed Voltage Reference (FVR)” and Figure 18-2 for more details.  2010-2021 Microchip Technology Inc. 18.8.3 COMPARATOR HYSTERESIS Each Comparator has a selectable hysteresis feature. The hysteresis can be enabled by setting the CxHYS bit of the CM2CON1 register. See Section 27.0 “Electrical Specifications” for more details. 18.8.4 SYNCHRONIZING COMPARATOR OUTPUT TO TIMER1 The Comparator Cx output can be synchronized with Timer1 by setting the CxSYNC bit of the CM2CON1 register. When enabled, the Cx output is latched on the falling edge of the Timer1 source clock. To prevent a race condition when gating Timer1 clock with the comparator output, Timer1 increments on the rising edge of its clock source, and the falling edge latches the comparator output. See the Comparator Block Diagram (Figure 18-2) and the Timer1 Block Diagram (Figure 12-1) for more information. Note 1: The comparator synchronized output may not be used to gate the external Timer1 clock when the Timer1 synchronizer is enabled. 2: The Timer1 prescale may be set to 1:1 when synchronizing the comparator output as unexpected results may occur with other prescale values. DS40001412H-page 307 PIC18(L)F2X/4XK22 18.9 Register Definitions: Comparator Control REGISTER 18-1: CMxCON0: COMPARATOR x CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 CxON CxOUT CxOE CxPOL CxSP CxR R/W-0 R/W-0 CxCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxON: Comparator Cx Enable bit 1 = Comparator Cx is enabled 0 = Comparator Cx is disabled bit 6 CxOUT: Comparator Cx Output bit If CxPOL = 1 (inverted polarity): CxOUT = 0 when CxVIN+ > CxVINCxOUT = 1 when CxVIN+ < CxVINIf CxPOL = 0 (noninverted polarity): CxOUT = 1 when CxVIN+ > CxVINCxOUT = 0 when CxVIN+ < CxVIN- bit 5 CxOE: Comparator Cx Output Enable bit 1 = CxOUT is present on the CxOUT pin(1) 0 = CxOUT is internal only bit 4 CxPOL: Comparator Cx Output Polarity Select bit 1 = CxOUT logic is inverted 0 = CxOUT logic is not inverted bit 3 CxSP: Comparator Cx Speed/Power Select bit 1 = Cx operates in Normal-Power, Higher Speed mode 0 = Cx operates in Low-Power, Low-Speed mode bit 2 CxR: Comparator Cx Reference Select bit (noninverting input) 1 = CxVIN+ connects to CXVREF output 0 = CxVIN+ connects to C12IN+ pin bit 1-0 CxCH: Comparator Cx Channel Select bit 00 = C12IN0- pin of Cx connects to CxVIN01 = C12IN1- pin of Cx connects to CXVIN10 = C12IN2- pin of Cx connects to CxVIN11 = C12IN3- pin of Cx connects to CxVIN- Note 1: x = Bit is unknown Comparator output requires the following three conditions: CxOE = 1, CxON = 1 and corresponding port TRIS bit = 0. DS40001412H-page 308  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 REGISTER 18-2: CM2CON1: COMPARATOR 1 AND 2 CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MC1OUT: Mirror Copy of C1OUT bit bit 6 MC2OUT: Mirror Copy of C2OUT bit bit 5 C1RSEL: Comparator C1 Reference Select bit 1 = FVR BUF1 routed to C1VREF input 0 = DAC routed to C1VREF input bit 4 C2RSEL: Comparator C2 Reference Select bit 1 = FVR BUF1 routed to C2VREF input 0 = DAC routed to C2VREF input bit 3 C1HYS: Comparator C1 Hysteresis Enable bit 1 = Comparator C1 hysteresis enabled 0 = Comparator C1 hysteresis disabled bit 2 C2HYS: Comparator C2 Hysteresis Enable bit 1 = Comparator C2 hysteresis enabled 0 = Comparator C2 hysteresis disabled bit 1 C1SYNC: C1 Output Synchronous Mode bit 1 = C1 output is synchronized to rising edge of TMR1 clock (T1CLK) 0 = C1 output is asynchronous bit 0 C2SYNC: C2 Output Synchronous Mode bit 1 = C2 output is synchronized to rising edge of TMR1 clock (T1CLK) 0 = C2 output is asynchronous  2010-2021 Microchip Technology Inc. x = Bit is unknown DS40001412H-page 309 PIC18(L)F2X/4XK22 TABLE 18-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 149 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 150 CM2CON1 MC1OUT MC2OUT C1SYNC C2SYNC 309 CM1CON0 C1ON C1OUT Name C1RSEL C2RSEL C1HYS C2HYS C1OE C1POL C1SP C1R C2SP C2R CM2CON0 C2ON C2OUT C2OE C2POL VREFCON1 DACEN DACLPS DACOE — VREFCON2 — — — VREFCON0 FVREN FVRST INTCON GIE/GIEH 308 C2CH 308 — DACNSS DACR FVRS PEIE/GIEL TMR0IE DACPSS C1CH — — 335 336 — — 332 INT0IE RBIE TMR0IF INT0IF RBIF 109 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113 PMD2 — — — — ADCMD 54 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 151 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151 CTMUMD CMP2MD CMP1MD Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by the comparator module. DS40001412H-page 310  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 19.0 CHARGE TIME MEASUREMENT UNIT (CTMU) The Charge Time Measurement Unit (CTMU) is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. By working with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses with a specific time delay. The CTMU is ideal for interfacing with capacitive-based sensors. The module includes the following key features: • Up to 28(1) channels available for capacitive or time measurement input • On-chip precision current source • Four-edge input trigger sources • Polarity control for each edge source • Control of edge sequence • Control of response to edges FIGURE 19-1: • High precision time measurement • Time delay of external or internal signal asynchronous to system clock • Accurate current source suitable for capacitive measurement The CTMU works in conjunction with the A/D Converter to provide up to 28(1) channels for time or charge measurement, depending on the specific device and the number of A/D channels available. When configured for time delay, the CTMU is connected to the C12IN1- input of Comparator 2. The level-sensitive input edge sources can be selected from four sources: two external input pins (CTED1/CTED2) or the ECCP1/ (E)CCP2 Special Event Triggers. Figure 19-1 provides a block diagram of the CTMU. Note 1: PIC18(L)F2XK22 devices have up to 17 channels available. CTMU BLOCK DIAGRAM CTMUCONH/CTMUCONL EDGEN EDGSEQEN EDG1SELx EDG1POL EDG2SELx EDG2POL CTED1 CTED2 ECCP2 ECCP1 CTMUICON ITRIM IRNG EDG1STAT EDG2STAT Edge Control Logic Current Source Current Control TGEN IDISSEN CTTRIG CTMU Control Logic Pulse Generator CTPLS Comparator 2 Output Comparator C1/C2 Input A/D Converter  2010-2021 Microchip Technology Inc. DS40001412H-page 311 PIC18(L)F2X/4XK22 19.1 CTMU Operation The CTMU works by using a fixed current source to charge a circuit. The type of circuit depends on the type of measurement being made. In the case of charge measurement, the current is fixed, and the amount of time the current is applied to the circuit is fixed. The amount of voltage read by the A/D is then a measurement of the capacitance of the circuit. In the case of time measurement, the current, as well as the capacitance of the circuit, is fixed. In this case, the voltage read by the A/D is then representative of the amount of time elapsed from the time the current source starts and stops charging the circuit. If the CTMU is being used as a time delay, both capacitance and current source are fixed, as well as the voltage supplied to the comparator circuit. The delay of a signal is determined by the amount of time it takes the voltage to charge to the comparator threshold voltage. 19.1.1 THEORY OF OPERATION The operation of the CTMU is based on the equation for charge: dV I = C  -----dT More simply, the amount of charge measured in coulombs in a circuit is defined as current in amperes (I) multiplied by the amount of time in seconds that the current flows (t). Charge is also defined as the capacitance in farads (C) multiplied by the voltage of the circuit (V). It follows that: I t = C  V. The CTMU module provides a constant, known current source. The A/D Converter is used to measure (V) in the equation, leaving two unknowns: capacitance (C) and time (t). The above equation can be used to calculate capacitance or time, by either the relationship using the known fixed capacitance of the circuit: t = C  V  I 19.1.2 CURRENT SOURCE At the heart of the CTMU is a precision current source, designed to provide a constant reference for measurements. The level of current is user-selectable across three ranges, with the ability to trim the output. The current range is selected by the IRNG bits (CTMUICON), with a value of ‘00’ representing the lowest range. Current trim is provided by the ITRIM bits (CTMUICON). Note that half of the range adjusts the current source positively and the other half reduces the current source. A value of ‘000000’ is the neutral position (no change). A value of ‘100000’ is the maximum negative adjustment, and ‘011111’ is the maximum positive adjustment. 19.1.3 EDGE SELECTION AND CONTROL CTMU measurements are controlled by edge events occurring on the module’s two input channels. Each channel, referred to as Edge 1 and Edge 2, can be configured to receive input pulses from one of the edge input pins (CTED1 and CTED2) or ECCPx Special Event Triggers. The input channels are level-sensitive, responding to the instantaneous level on the channel rather than a transition between levels. The inputs are selected using the EDG1SEL and EDG2SEL bit pairs (CTMUCONL). In addition to source, each channel can be configured for event polarity using the EDGE2POL and EDGE1POL bits (CTMUCONL). The input channels can also be filtered for an edge event sequence (Edge 1 occurring before Edge 2) by setting the EDGSEQEN bit (CTMUCONH). 19.1.4 EDGE STATUS The CTMUCONL register also contains two Status bits: EDG2STAT and EDG1STAT (CTMUCONL). Their primary function is to show if an edge response has occurred on the corresponding channel. The CTMU automatically sets a particular bit when an edge response is detected on its channel. The level-sensitive nature of the input channels also means that the Status bits become set immediately if the channel’s configuration is changed and is the same as the channel’s current state. or by: C =  I t  V using a fixed time that the current source is applied to the circuit. DS40001412H-page 312  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 The module uses the edge Status bits to control the current source output to external analog modules (such as the A/D Converter). Current is only supplied to external modules when only one (but not both) of the Status bits is set, and shuts current off when both bits are either set or cleared. This allows the CTMU to measure current only during the interval between edges. After both Status bits are set, it is necessary to clear them before another measurement is taken. Both bits may be cleared simultaneously, if possible, to avoid re-enabling the CTMU current source. In addition to being set by the CTMU hardware, the edge Status bits can also be set by software. This is also the user’s application to manually enable or disable the current source. Setting either one (but not both) of the bits enables the current source. Setting or clearing both bits at once disables the source. 19.1.5 INTERRUPTS The CTMU sets its interrupt flag (PIR3) whenever the current source is enabled, then disabled. An interrupt is generated only if the corresponding interrupt enable bit (PIE3) is also set. If edge sequencing is not enabled (i.e., Edge 1 must occur before Edge 2), it is necessary to monitor the edge Status bits and determine which edge occurred last and caused the interrupt. 19.2 CTMU Module Initialization The following sequence is a general guideline used to initialize the CTMU module: 1. Select the current source range using the IRNG bits (CTMUICON). 2. Adjust the current source trim using the ITRIM bits (CTMUICON). 3. Configure the edge input sources for Edge 1 and Edge 2 by setting the EDG1SEL and EDG2SEL bits (CTMUCONL). 4. Configure the input polarities for the edge inputs using the EDG1POL and EDG2POL bits (CTMUCONL). The default configuration is for negative edge polarity (high-to-low transitions). 5. Enable edge sequencing using the EDGSEQEN bit (CTMUCONH). By default, edge sequencing is disabled. 6. Select the operating mode (Measurement or Time Delay) with the TGEN bit. The default mode is Time/Capacitance Measurement. 7. Discharge the connected circuit by setting the IDISSEN bit (CTMUCONH); after waiting a sufficient time for the circuit to discharge, clear IDISSEN. 8. Disable the module by clearing the CTMUEN bit (CTMUCONH). 9. Enable the module by setting the CTMUEN bit. 10. Clear the Edge Status bits: EDG2STAT and EDG1STAT (CTMUCONL). 11. Enable both edge inputs by setting the EDGEN bit (CTMUCONH). Depending on the type of measurement or pulse generation being performed, one or more additional modules may also need to be initialized and configured with the CTMU module: • Edge Source Generation: In addition to the external edge input pins, both Timer1 and the Output Compare/PWM1 module can be used as edge sources for the CTMU. • Capacitance or Time Measurement: The CTMU module uses the A/D Converter to measure the voltage across a capacitor that is connected to one of the analog input channels. • Pulse Generation: When generating system clock independent output pulses, the CTMU module uses Comparator 2 and the associated comparator voltage reference.  2010-2021 Microchip Technology Inc. DS40001412H-page 313 PIC18(L)F2X/4XK22 19.3 Calibrating the CTMU Module FIGURE 19-2: The CTMU requires calibration for precise measurements of capacitance and time, as well as for accurate time delay. If the application only requires measurement of a relative change in capacitance or time, calibration is usually not necessary. An example of this type of application would include a capacitive touch switch, in which the touch circuit has a baseline capacitance, and the added capacitance of the human body changes the overall capacitance of a circuit. If actual capacitance or time measurement is required, two hardware calibrations must take place: the current source needs calibration to set it to a precise current, and the circuit being measured needs calibration to measure and/or nullify all other capacitance other than that to be measured. 19.3.1 4. 5. 6. PIC18(L)FXXK22 Device CTMU Current Source A/D Converter ANx RCAL A/D MUX CURRENT SOURCE CALIBRATION The current source on the CTMU module is trimable. Therefore, for precise measurements, it is possible to measure and adjust this current source by placing a high precision resistor, RCAL, onto an unused analog channel. An example circuit is shown in Figure 19-2. The current source measurement is performed using the following steps: 1. 2. 3. CTMU CURRENT SOURCE CALIBRATION CIRCUIT Initialize the A/D Converter. Initialize the CTMU. Enable the current source by setting EDG1STAT (CTMUCONL). Issue settling time delay. Perform A/D conversion. Calculate the current source current using I = V/ RCAL, where RCAL is a high precision resistance and V is measured by performing an A/D conversion. A value of 70% of full-scale voltage is chosen to make sure that the A/D Converter was in a range that is well above the noise floor. Keep in mind that if an exact current is chosen, that is to incorporate the trimming bits from CTMUICON, the resistor value of RCAL may need to be adjusted accordingly. RCAL may also be adjusted to allow for available resistor values. RCAL may be of the highest precision available, keeping in mind the amount of precision needed for the circuit that the CTMU will be used to measure. A recommended minimum would be 0.1% tolerance. The following examples show one typical method for performing a CTMU current calibration. Example 19-1 demonstrates how to initialize the A/D Converter and the CTMU; this routine is typical for applications using both modules. Example 19-2 demonstrates one method for the actual calibration routine. The CTMU current source may be trimmed with the trim bits in CTMUICON using an iterative process to get an exact desired current. Alternatively, the nominal value without adjustment may be used; it may be stored by the software for use in all subsequent capacitive or time measurements. To calculate the value for RCAL, the nominal current must be chosen, and then the resistance can be calculated. For example, if the A/D Converter reference voltage is 3.3V, use 70% of full scale, or 2.31V as the desired approximate voltage to be read by the A/D Converter. If the range of the CTMU current source is selected to be 0.55 A, the resistor value needed is calculated as RCAL = 2.31V/0.55 A, for a value of 4.2 MΩ. Similarly, if the current source is chosen to be 5.5 A, RCAL would be 420,000Ω, and 42,000Ω if the current source is set to 55 A. DS40001412H-page 314  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 EXAMPLE 19-1: SETUP FOR CTMU CALIBRATION ROUTINES #include "p18cxxx.h" /**************************************************************************/ /*Set up CTMU *****************************************************************/ /**************************************************************************/ void setup(void) { //CTMUCONH/1 - CTMU Control registers CTMUCONH = 0x00; //make sure CTMU is disabled CTMUCONL = 0x90; //CTMU continues to run when emulator is stopped,CTMU continues //to run in idle mode,Time Generation mode disabled, Edges are blocked //No edge sequence order, Analog current source not grounded, trigger //output disabled, Edge2 polarity = positive level, Edge2 source = //source 0, Edge1 polarity = positive level, Edge1 source = source 0, //CTMUICON - CTMU Current Control Register CTMUICON = 0x01; //0.55uA, Nominal - No Adjustment /**************************************************************************/ //Set up AD converter; /**************************************************************************/ TRISA=0x04; //set channel 2 as an input // Configure AN2 as an analog channel ANSELAbits.ANSA2=1; TRISAbits.TRISA2=1; // ADCON2 ADCON2bits.ADFM=1; ADCON2bits.ACQT=1; ADCON2bits.ADCS=2; // ADCON1 ADCON1bits.PVCFG0 =0; ADCON1bits.NVCFG1 =0; // ADCON0 ADCON0bits.CHS=2; ADCON0bits.ADON=1; // Results format 1= Right justified // Acquition time 7 = 20TAD 2 = 4TAD 1=2TAD // Clock conversion bits 6= FOSC/64 2=FOSC/32 // Vref+ = AVdd // Vref- = AVss // Select ADC channel // Turn on ADC }  2010-2021 Microchip Technology Inc. DS40001412H-page 315 PIC18(L)F2X/4XK22 EXAMPLE 19-2: CURRENT CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 500 #define DELAY for(i=0;i 9] or [DC = 1] then (W) + 6  W; else (W)  W; 0  f  255 d  [0,1] a  [0,1] Operation: (f) – 1  dest Status Affected: C, DC, N, OV, Z If [W + DC > 9] or [C = 1] then (W) + 6 + DC  W; else (W) + DC  W Status Affected: Decrement f Encoding: 0000 0000 0000 0000 0111 Description: DAW adjusts the 8-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Words: 1 Decode Read register W Process Data Write W Cycles: 1 Example1: DAW Before Instruction W = C = DC = After Instruction W C DC Example 2: = = = A5h 0 0 05h 1 0 Before Instruction W = C = DC = After Instruction W C DC = = = ffff ffff Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. C Encoding: 01da Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: DECF Before Instruction CNT = Z = After Instruction CNT = Z = CNT, 1, 0 01h 0 00h 1 CEh 0 0 34h 1 0  2010-2021 Microchip Technology Inc. DS40001412H-page 379 PIC18(L)F2X/4XK22 DECFSZ Decrement f, skip if 0 DCFSNZ Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0  f  255 d  [0,1] a  [0,1] Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (f) – 1  dest, skip if result = 0 Operation: (f) – 1  dest, skip if result  0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a 2-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Decrement f, skip if not 0 Encoding: 0100 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Q1 Q2 Q3 Q4 No operation No operation No operation No operation Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation HERE DECFSZ GOTO Example: CNT, 1, 1 LOOP CONTINUE Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT  PC = DS40001412H-page 380 Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE + 2) ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is not ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a 2-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip: If skip and followed by 2-word instruction: 11da Description: Q Cycle Activity: Q1 f {,d {,a}} If skip: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE ZERO NZERO Before Instruction TEMP After Instruction TEMP If TEMP PC If TEMP PC DCFSNZ : : TEMP, 1, 0 = ? = = =  = TEMP – 1, 0; Address (ZERO) 0; Address (NZERO)  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 GOTO Unconditional Branch INCF Syntax: GOTO k Syntax: INCF Operands: 0  k  1048575 Operands: Operation: k  PC Status Affected: None 0  f  255 d  [0,1] a  [0,1] Operation: (f) + 1  dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k) 2nd word(k) Description: 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch Increment f Encoding: 0010 2 Cycles: 2 Q1 Q2 Q3 Q4 Read literal ‘k’, No operation Read literal ‘k’, Write to PC No operation No operation No operation No operation ffff ffff The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Decode 10da Description: anywhere within entire 2-Mbyte memory range. The 20-bit value ‘k’ is loaded into PC. GOTO is always a 2-cycle instruction. Words: f {,d {,a}} Q Cycle Activity: Example: GOTO THERE After Instruction PC = Address (THERE) Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: INCF Before Instruction CNT = Z = C = DC = After Instruction CNT = Z = C = DC =  2010-2021 Microchip Technology Inc. CNT, 1, 0 FFh 0 ? ? 00h 1 1 1 DS40001412H-page 381 PIC18(L)F2X/4XK22 INCFSZ Increment f, skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0  f  255 d  [0,1] a  [0,1] f {,d {,a}} Increment f, skip if not 0 f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operands: Operation: (f) + 1  dest, skip if result = 0 Operation: (f) + 1  dest, skip if result  0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a 2-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Encoding: 0100 Description: Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Cycles: 1(2) Note: Q Cycle Activity: 10da ffff ffff The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is not ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a 2-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Decode Read register ‘f’ Process Data Write to destination Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT  PC = DS40001412H-page 382 INCFSZ : : Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO) CNT, 1, 0 Example: HERE ZERO NZERO Before Instruction PC = After Instruction REG =  If REG PC = If REG = PC = INFSNZ REG, 1, 0 Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO)  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 IORLW Inclusive OR literal with W IORWF Syntax: IORLW k Syntax: IORWF Operands: 0  k  255 Operands: Operation: (W) .OR. k  W Status Affected: N, Z 0  f  255 d  [0,1] a  [0,1] Operation: (W) .OR. (f)  dest Status Affected: N, Z Encoding: 0000 Description: 1001 kkkk kkkk The contents of W are ORed with the 8-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Inclusive OR W with f Encoding: 0001 Q1 Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W Example: IORLW W = ffff Words: 1 Cycles: 1 35h 9Ah BFh ffff Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Before Instruction W = After Instruction 00da Description: Q Cycle Activity: Decode f {,d {,a}} Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: IORWF Before Instruction RESULT = W = After Instruction RESULT = W =  2010-2021 Microchip Technology Inc. RESULT, 0, 1 13h 91h 13h 93h DS40001412H-page 383 PIC18(L)F2X/4XK22 LFSR Load FSR MOVF Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0  k  4095 Operands: Operation: k  FSRf 0  f  255 d  [0,1] a  [0,1] Status Affected: None Operation: f  dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the File Select Register pointed to by ‘f’. Words: 2 Cycles: 2 Move f Encoding: 0101 Q1 Q2 Q3 Q4 Read literal ‘k’ MSB Process Data Write literal ‘k’ MSB to FSRfH Decode Read literal ‘k’ LSB Process Data Write literal ‘k’ to FSRfL Example: = = 03h ABh ffff ffff The contents of register ‘f’ are moved to a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). Location ‘f’ can be anywhere in the 256-byte bank. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 LFSR 2, 3ABh After Instruction FSR2H FSR2L 00da Description: Q Cycle Activity: Decode f {,d {,a}} Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write W Example: MOVF Before Instruction REG W After Instruction REG W DS40001412H-page 384 REG, 0, 0 = = 22h FFh = = 22h 22h  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 MOVFF Move f to f MOVLB Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0  fs  4095 0  fd  4095 Operands: 0  k  255 Operation: k  BSR Operation: (fs)  fd Status Affected: None Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) Description: 1100 1111 ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’. Location of source ‘fs’ can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination ‘fd’ can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Words: 2 Cycles: 2 (3) Move literal to low nibble in BSR 0000 0001 kkkk kkkk Description: The 8-bit literal ‘k’ is loaded into the Bank Select Register (BSR). The value of BSR always remains ‘0’, regardless of the value of k7:k4. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write literal ‘k’ to BSR MOVLB 5 Example: Before Instruction BSR Register = After Instruction BSR Register = 02h 05h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ (src) Process Data No operation Decode No operation No operation Write register ‘f’ (dest) No dummy read Example: MOVFF Before Instruction REG1 REG2 After Instruction REG1 REG2 REG1, REG2 = = 33h 11h = = 33h 33h  2010-2021 Microchip Technology Inc. DS40001412H-page 385 PIC18(L)F2X/4XK22 MOVLW Move literal to W MOVWF Syntax: MOVLW k Syntax: MOVWF Operands: 0  k  255 Operands: Operation: kW 0  f  255 a  [0,1] Status Affected: None Operation: (W)  f Status Affected: None Encoding: 0000 1110 kkkk kkkk Description: The 8-bit literal ‘k’ is loaded into W. Words: 1 Cycles: 1 Move W to f Encoding: 0110 Q1 Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W Example: MOVLW = ffff ffff Move data from W to register ‘f’. Location ‘f’ can be anywhere in the 256-byte bank. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 5Ah After Instruction W 111a Description: Q Cycle Activity: Decode f {,a} 5Ah Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: MOVWF REG, 0 Before Instruction W = REG = After Instruction W REG DS40001412H-page 386 = = 4Fh FFh 4Fh 4Fh  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 MULLW Multiply literal with W MULWF Syntax: MULLW Syntax: MULWF Operands: 0  k  255 Operands: Operation: (W) x k  PRODH:PRODL 0  f  255 a  [0,1] Status Affected: None Operation: (W) x (f)  PRODH:PRODL Status Affected: None Encoding: 0000 Description: k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. Words: 1 Cycles: 1 Multiply W with f Encoding: 0000 Q1 Q2 Q3 Q4 Read literal ‘k’ Process Data Write registers PRODH: PRODL Example: MULLW W PRODH PRODL After Instruction W PRODH PRODL = = = E2h ? ? = = = E2h ADh 08h ffff ffff An unsigned multiplication is carried out between the contents of W and the register file location ‘f’. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and ‘f’ are unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 0C4h Before Instruction 001a Description: Q Cycle Activity: Decode f {,a} Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write registers PRODH: PRODL Example: MULWF REG, 1 Before Instruction W REG PRODH PRODL After Instruction W REG PRODH PRODL  2010-2021 Microchip Technology Inc. = = = = C4h B5h ? ? = = = = C4h B5h 8Ah 94h DS40001412H-page 387 PIC18(L)F2X/4XK22 NEGF Negate f NOP No Operation Syntax: NEGF Syntax: NOP Operands: 0  f  255 a  [0,1] Operands: None Operation: No operation Operation: (f)+1f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: f {,a} 0110 Description: Encoding: 110a ffff Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 0000 1111 ffff 0000 xxxx Description: No operation. Words: 1 Cycles: 1 0000 xxxx 0000 xxxx Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation Example: None. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: NEGF Before Instruction REG = After Instruction REG = DS40001412H-page 388 REG, 1 0011 1010 [3Ah] 1100 0110 [C6h]  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS)  bit bucket Operation: (PC + 2)  TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. Words: 1 Cycles: 1 Encoding: 0000 0000 0101 The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. Words: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation POP TOS value No operation POP GOTO NEW Example: 0000 Description: Q1 Q2 Q3 Q4 Decode PUSH PC + 2 onto return stack No operation No operation Example: Before Instruction TOS Stack (1 level down) = = 0031A2h 014332h After Instruction TOS PC = = 014332h NEW  2010-2021 Microchip Technology Inc. PUSH Before Instruction TOS PC = = 345Ah 0124h After Instruction PC TOS Stack (1 level down) = = = 0126h 0126h 345Ah DS40001412H-page 389 PIC18(L)F2X/4XK22 RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET Operands: -1024  n  1023 Operands: None Operation: (PC) + 2  TOS, (PC) + 2 + 2n  PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: n 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a 2-cycle instruction. Words: 1 Cycles: 2 Encoding: 0000 Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation 1111 1111 Description: This instruction provides a way to execute a MCLR Reset by software. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Start Reset No operation No operation Example: Q Cycle Activity: 0000 RESET After Instruction Registers = Flags* = Reset Value Reset Value PUSH PC to stack No operation Example: No operation HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2) DS40001412H-page 390  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 RETFIE Return from Interrupt RETLW Return literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s  [0,1] Operands: 0  k  255 Operation: (TOS)  PC, 1  GIE/GIEH or PEIE/GIEL, if s = 1 (WS)  W, (STATUSS)  Status, (BSRS)  BSR, PCLATU, PCLATH are unchanged. Operation: k  W, (TOS)  PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 0000 0001 1 Cycles: 2 Q Cycle Activity: kkkk kkkk Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data POP PC from stack, Write to W No operation No operation No operation No operation Example: Q1 Q2 Q3 Q4 Decode No operation No operation POP PC from stack Set GIEH or GIEL Example: 1100 W is loaded with the 8-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. 000s Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If ‘s’ = 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, STATUS and BSR. If ‘s’ = 0, no update of these registers occurs (default). Words: No operation 0000 Description: GIE/GIEH, PEIE/GIEL. Encoding: Description: Encoding: No operation RETFIE After Interrupt PC W BSR Status GIE/GIEH, PEIE/GIEL No operation No operation 1 = = = = =  2010-2021 Microchip Technology Inc. TOS WS BSRS STATUSS 1 CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; Before Instruction W = After Instruction W = W contains table offset value W now has table value W = offset Begin table End of table 07h value of kn DS40001412H-page 391 PIC18(L)F2X/4XK22 RETURN Return from Subroutine RLCF Syntax: RETURN {s} Syntax: RLCF Operands: s  [0,1] Operands: Operation: (TOS)  PC, if s = 1 (WS)  W, (STATUSS)  Status, (BSRS)  BSR, PCLATU, PCLATH are unchanged 0  f  255 d  [0,1] a  [0,1] Operation: (f)  dest, (f)  C, (C)  dest Status Affected: C, N, Z Status Affected: None Encoding: 0000 Rotate Left f through Carry Encoding: 0000 0001 001s Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If ‘s’= 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, STATUS and BSR. If ‘s’ = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 0011 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data POP PC from stack No operation No operation No operation No operation f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left through the CARRY flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. register f C Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN After Instruction: PC = TOS Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: RLCF Before Instruction REG = C = After Instruction REG = W = C = DS40001412H-page 392 REG, 0, 0 1110 0110 0 1110 0110 1100 1100 1  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 RLNCF Rotate Left f (No Carry) RRCF Syntax: RLNCF Syntax: RRCF Operands: 0  f  255 d  [0,1] a  [0,1] Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (f)  dest, (f)  dest Operation: Status Affected: N, Z (f)  dest, (f)  C, (C)  dest Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Rotate Right f through Carry Encoding: 0011 Description: register f Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Before Instruction REG = After Instruction REG = 00da RLNCF Words: 1 Cycles: 1 0101 0111  2010-2021 Microchip Technology Inc. ffff register f Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination RRCF REG, 0, 0 REG, 1, 0 1010 1011 ffff The contents of register ‘f’ are rotated one bit to the right through the CARRY flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. C Q Cycle Activity: Example: f {,d {,a}} Example: Before Instruction REG = C = After Instruction REG = W = C = 1110 0110 0 1110 0110 0111 0011 0 DS40001412H-page 393 PIC18(L)F2X/4XK22 RRNCF Rotate Right f (No Carry) SETF Syntax: RRNCF Syntax: SETF Operands: 0  f  255 d  [0,1] a  [0,1] Operands: 0  f  255 a [0,1] Operation: FFh  f Operation: (f)  dest, (f)  dest Status Affected: None Status Affected: f {,d {,a}} Encoding: N, Z Encoding: 0100 Description: 00da ffff ffff The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected (default), overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. register f Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination RRNCF Before Instruction REG = After Instruction REG = Example 2: f {,a} 0110 100a ffff ffff Description: The contents of the specified register are set to FFh. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: Q Cycle Activity: Example 1: Set f SETF Before Instruction REG After Instruction REG REG, 1 = 5Ah = FFh REG, 1, 0 1101 0111 1110 1011 RRNCF REG, 0, 0 Before Instruction W = REG = After Instruction ? 1101 0111 = = 1110 1011 1101 0111 W REG DS40001412H-page 394  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 SLEEP Enter Sleep mode SUBFWB Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h  WDT, 0  WDT postscaler, 1  TO, 0  PD 0 f 255 d  [0,1] a  [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-down Status bit (PD) is cleared. The Time-out Status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Words: 1 Cycles: 1 0101 Q1 Q2 Q3 Q4 Decode No operation Process Data Go to Sleep SLEEP Before Instruction TO = ? PD = ? After Instruction 1† TO = 0 PD = † If WDT causes wake-up, this bit is cleared.  2010-2021 Microchip Technology Inc. f {,d {,a}} 01da ffff ffff Description: Subtract register ‘f’ and CARRY flag (borrow) from W (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Example: Subtract f from W with borrow Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination SUBFWB REG, 1, 0 Example 1: Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative SUBFWB REG, 0, 0 Example 2: Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive SUBFWB REG, 1, 0 Example 3: Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS40001412H-page 395 PIC18(L)F2X/4XK22 SUBLW Subtract W from literal SUBWF Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k – (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d  [0,1] a  [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 Description 1000 kkkk kkkk W is subtracted from the 8-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Subtract W from f Encoding: 0101 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example 1: SUBLW Before Instruction W = C = After Instruction W = C = Z = N = Example 2: Before Instruction W = C = After Instruction W = C = Z = N = Example 3: 02h 1 Cycles: 1 Q Cycle Activity: 02h ? 00h 1 ; result is zero 1 0 SUBLW Before Instruction W = C = After Instruction W = C = Z = N = 02h 03h ? FFh ; (2’s complement) 0 ; result is negative 0 1 Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination SUBWF REG, 1, 0 Example 1: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: 3 2 ? 1 2 1 0 0 ; result is positive SUBWF REG, 0, 0 2 2 ? 2 0 1 1 0 SUBWF Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = DS40001412H-page 396 ffff Words: 01h ? SUBLW ffff Subtract W from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. 02h 01h 1 ; result is positive 0 0 11da Description: Q Cycle Activity: Q1 f {,d {,a}} ; result is zero REG, 1, 0 1 2 ? FFh ;(2’s complement) 2 0 ; result is negative 0 1  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 SUBWFB Subtract W from f with Borrow SWAPF Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f)  dest, (f)  dest Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the CARRY flag (borrow) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Read register ‘f’ Q3 Process Data SUBWFB REG, 1, 0 Example 1: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: 19h 0Dh 1 (0001 1001) (0000 1101) 0Ch 0Dh 1 0 0 (0000 1100) (0000 1101) Encoding: 0011 10da ffff ffff Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: SWAPF Before Instruction REG = After Instruction REG = REG, 1, 0 53h 35h ; result is positive SUBWFB REG, 0, 0 Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: 1Bh 1Ah 0 (0001 1011) (0001 1010) 1Bh 00h 1 1 0 (0001 1011) SUBWFB Before Instruction REG = W = C = After Instruction REG = W C Z N Q4 Write to destination Swap f = = = = ; result is zero REG, 1, 0 03h 0Eh 1 (0000 0011) (0000 1110) F5h (1111 0101) ; [2’s comp] (0000 1110) 0Eh 0 0 1 ; result is negative  2010-2021 Microchip Technology Inc. DS40001412H-page 397 PIC18(L)F2X/4XK22 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR))  TABLAT; TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR))  TABLAT; (TBLPTR) + 1  TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR))  TABLAT; (TBLPTR) – 1  TBLPTR; if TBLRD +*, (TBLPTR) + 1  TBLPTR; (Prog Mem (TBLPTR))  TABLAT; Example2: Status Affected: None Encoding: 0000 0000 0000 *+ ; Before Instruction TABLAT TBLPTR MEMORY (00A356h) After Instruction TABLAT TBLPTR 10nn nn=0 * =1 *+ =2 *=3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 TBLRD = = = 55h 00A356h 34h = = 34h 00A357h +* ; Before Instruction TABLAT TBLPTR MEMORY (01A357h) MEMORY (01A358h) After Instruction TABLAT TBLPTR = = = = AAh 01A357h 12h 34h = = 34h 01A358h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read Program Memory) No operation No operation (Write TABLAT) DS40001412H-page 398  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT)  Holding Register; TBLPTR – No Change; if TBLWT*+, (TABLAT)  Holding Register; (TBLPTR) + 1  TBLPTR; if TBLWT*-, (TABLAT)  Holding Register; (TBLPTR) – 1  TBLPTR; if TBLWT+*, (TBLPTR) + 1  TBLPTR; (TABLAT)  Holding Register; Status Affected: Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion) TABLAT = 55h TBLPTR = 00A357h HOLDING REGISTER (00A356h) = 55h Example 2: None Encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +* Description: This instruction uses the three LSBs of TBLPTR to determine which of the eight holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 6.0 “Flash Program Memory” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MByte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 TBLWT +*; Before Instruction TABLAT = 34h TBLPTR = 01389Ah HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = FFh After Instruction (table write completion) TABLAT = 34h TBLPTR = 01389Bh HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = 34h Q Cycle Activity: Q1 Decode Q2 Q3 Q4 No No No operation operation operation No No No No operation operation operation operation (Read (Write to TABLAT) Holding Register )  2010-2021 Microchip Technology Inc. DS40001412H-page 399 PIC18(L)F2X/4XK22 TSTFSZ Test f, skip if 0 XORLW Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0  f  255 a  [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: Encoding: 0110 Description: Exclusive OR literal with W 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a 2-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. 0000 1010 kkkk kkkk Description: The contents of W are XORed with the 8-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: XORLW 0AFh Before Instruction W = After Instruction W = B5h 1Ah Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO Before Instruction PC After Instruction If CNT PC If CNT PC DS40001412H-page 400 TSTFSZ : : CNT, 1 = Address (HERE) = =  = 00h, Address (ZERO) 00h, Address (NZERO)  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 XORWF Exclusive OR W with f Syntax: XORWF Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 f {,d {,a}} 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: XORWF Before Instruction REG = W = After Instruction REG = W = REG, 1, 0 AFh B5h 1Ah B5h  2010-2021 Microchip Technology Inc. DS40001412H-page 401 PIC18(L)F2X/4XK22 25.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 25-3. Detailed descriptions are provided in Section 25.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 25-1 apply to both the standard and extended PIC18 instruction sets. In addition to the standard 75 instructions of the PIC18 instruction set, PIC18(L)F2X/4XK22 devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions. Note: The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler. The additional features of the extended instruction set are disabled by default. To enable them, users must set the XINST Configuration bit. The instructions in the extended set can all be classified as literal operations, which either manipulate the File Select Registers, or use them for indexed addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. 25.2.1 EXTENDED INSTRUCTION SYNTAX Most of the extended instructions use indexed arguments, using one of the File Select Registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of indexed addressing, it is enclosed in square brackets (“[ ]”). This is done to indicate that the argument is used as an index or offset. MPASM™ Assembler will flag an error if it determines that an index or offset value is not bracketed. The extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include: • dynamic allocation and deallocation of software stack space when entering and leaving subroutines • function pointer invocation • software Stack Pointer manipulation • manipulation of variables located in a software stack When the extended instruction set is enabled, brackets are also used to indicate index arguments in byteoriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see Section 25.2.3.1 “Extended Instruction Syntax with Standard PIC18 Commands”. Note: TABLE 25-3: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces (“{ }”). EXTENSIONS TO THE PIC18 INSTRUCTION SET Mnemonic, Operands ADDFSR ADDULNK CALLW MOVSF f, k k MOVSS zs, zd PUSHL k SUBFSR SUBULNK f, k k zs, fd Description Add literal to FSR Add literal to FSR2 and return Call subroutine using WREG 1st word Move zs (source) to 2nd word fd (destination) Move zs (source) to 1st word 2nd word zd (destination) Store literal at FSR2, decrement FSR2 Subtract literal from FSR Subtract literal from FSR2 and return DS40001412H-page 402 Cycles 1 2 2 2 16-Bit Instruction Word MSb LSb Status Affected 1000 1000 0000 1011 ffff 1011 xxxx 1010 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk None None None None 1 1110 1110 0000 1110 1111 1110 1111 1110 1 2 1110 1110 1001 1001 ffkk 11kk kkkk kkkk None None 2 None None  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 25.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0  k  63 f  [ 0, 1, 2 ] Operands: 0  k  63 Operation: FSR(f) + k  FSR(f) Status Affected: None Encoding: 1110 Add Literal to FSR2 and Return FSR2 + k  FSR2, Operation: (TOS) PC Status Affected: 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. Words: 1 Cycles: 1 None Encoding: 1110 Q1 Q2 Q3 Q4 Read literal ‘k’ Process Data Write to FSR Example: ADDFSR 2, 23h Before Instruction FSR2 = 03FFh After Instruction FSR2 = 0422h kkkk Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to FSR No Operation No Operation No Operation No Operation Example: Note: 11kk The 6-bit literal ‘k’ is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Q Cycle Activity: Decode 1000 Description: ADDULNK 23h Before Instruction FSR2 = PC = 03FFh 0100h After Instruction FSR2 = PC = 0422h (TOS) All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).  2010-2021 Microchip Technology Inc. DS40001412H-page 403 PIC18(L)F2X/4XK22 CALLW Subroutine Call Using WREG MOVSF Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2)  TOS, (W)  PCL, (PCLATH)  PCH, (PCLATU)  PCU 0  zs  127 0  fd  4095 Operation: ((FSR2) + zs)  fd Status Affected: None Status Affected: None Encoding: 0000 0000 0001 0100 Description First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched into PCH and PCU, respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Unlike CALL, there is no option to update W, Status or BSR. Words: 1 Cycles: 2 Move Indexed to f Encoding: 1st word (source) 2nd word (destin.) Q1 Q2 Q3 Q4 Read WREG PUSH PC to stack No operation No operation No operation No operation No operation HERE Before Instruction PC = PCLATH = PCLATU = W = After Instruction PC = TOS = PCLATH = PCLATU = W = DS40001412H-page 404 zzzzs ffffd Words: 2 Cycles: 2 Q Cycle Activity: Q1 CALLW Decode address (HERE) 10h 00h 06h 001006h address (HERE + 2) 10h 00h 06h 0zzz ffff The contents of the source register are moved to destination register ‘fd’. The actual address of the source register is determined by adding the 7-bit literal offset ‘zs’ in the first word to the value of FSR2. The address of the destination register is specified by the 12-bit literal ‘fd’ in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh). The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. Decode Example: 1011 ffff Description: Q Cycle Activity: Decode 1110 1111 Q2 Q3 Determine Determine source addr source addr No operation No operation No dummy read Example: MOVSF Before Instruction FSR2 Contents of 85h REG2 After Instruction FSR2 Contents of 85h REG2 Q4 Read source reg Write register ‘f’ (dest) [05h], REG2 = 80h = = 33h 11h = 80h = = 33h 33h  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 MOVSS Move Indexed to Indexed PUSHL Syntax: Syntax: PUSHL k Operands: MOVSS [zs], [zd] 0  zs  127 0  zd  127 Operands: 0k  255 Operation: ((FSR2) + zs)  ((FSR2) + zd) Operation: k  (FSR2), FSR2 – 1  FSR2 Status Affected: None Status Affected: None Encoding: 1st word (source) 2nd word (dest.) Description 1110 1111 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets ‘zs’ or ‘zd’, respectively, to the value of FSR2. Both registers can be located anywhere in the 4096-byte data memory space (000h to FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the resultant destination address points to an indirect addressing register, the instruction will execute as a NOP. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Decode Decode Example: Q2 Q3 Determine Determine source addr source addr Determine dest addr Determine dest addr Store Literal at FSR2, Decrement FSR2 Encoding: 1111 1010 kkkk kkkk Description: The 8-bit literal ‘k’ is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process data Write to destination Example: PUSHL 08h Before Instruction FSR2H:FSR2L Memory (01ECh) = = 01ECh 00h After Instruction FSR2H:FSR2L Memory (01ECh) = = 01EBh 08h Q4 Read source reg Write to dest reg MOVSS [05h], [06h] Before Instruction FSR2 Contents of 85h Contents of 86h After Instruction FSR2 Contents of 85h Contents of 86h = 80h = 33h = 11h = 80h = 33h = 33h  2010-2021 Microchip Technology Inc. DS40001412H-page 405 PIC18(L)F2X/4XK22 SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: Operation: FSR(f) – k  FSRf Status Affected: None Encoding: 1110 FSR2 – k  FSR2 (TOS) PC Status Affected: None 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’. Words: 1 Cycles: 1 Encoding: 1110 Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination SUBFSR 2, 23h 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Words: 1 Cycles: 2 Q Cycle Activity: Example: Subtract Literal from FSR2 and Return Q Cycle Activity: Before Instruction FSR2 = Q1 Q2 Q3 Q4 03FFh Decode After Instruction FSR2 = Read register ‘f’ Process Data Write to destination 03DCh No Operation No Operation No Operation No Operation Example: DS40001412H-page 406 SUBULNK 23h Before Instruction FSR2 = PC = 03FFh 0100h After Instruction FSR2 = PC = 03DCh (TOS)  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 25.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 5.7.1 “Indexed Addressing with Literal Offset”). This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted. When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (‘a’ = 0), or in a GPR bank designated by the BSR (‘a’ = 1). When the extended instruction set is enabled and ‘a’ = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument – that is, all byte-oriented and bitoriented instructions, or almost half of the core PIC18 instructions – may behave differently when the extended instruction set is enabled. When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see Section 25.2.3.1 “Extended Instruction Syntax with Standard PIC18 Commands”). Although the Indexed Literal Offset Addressing mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset Addressing mode are provided on the following page to show how execution is affected. The operand conditions shown in the examples are applicable to all instructions of these types.  2010-2021 Microchip Technology Inc. 25.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands When the extended instruction set is enabled, the file register argument, ‘f’, in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value, ‘k’. As already noted, this occurs only when ‘f’ is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets (“[ ]”). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within brackets, will generate an error in the MPASM assembler. If the index argument is properly bracketed for Indexed Literal Offset Addressing, the Access RAM argument is never specified; it will automatically be assumed to be ‘0’. This is in contrast to standard operation (extended instruction set disabled) when ‘a’ is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM assembler. The destination argument, ‘d’, functions as before. In the latest versions of the MPASM™ assembler, language support for the extended instruction set must be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the source listing. 25.2.4 CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. When porting an application to the PIC18(L)F2X/ 4XK22, it is very important to consider the type of code. A large, re-entrant application that is written in ‘C’ and would benefit from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS40001412H-page 407 PIC18(L)F2X/4XK22 ADDWF ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0  k  95 d  [0,1] Operands: 0  f  95 0b7 Operation: (W) + ((FSR2) + k)  dest Operation: 1  ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value ‘k’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). Encoding: 1000 bbb0 kkkk kkkk Description: Bit ‘b’ of the register indicated by FSR2, offset by the value ‘k’, is set. Words: 1 Cycles: 1 Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read register ‘f’ Process Data Write to destination Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Data Write to destination Example: ADDWF [OFST] , 0 Before Instruction W OFST FSR2 Contents of 0A2Ch After Instruction W Contents of 0A2Ch = = = 17h 2Ch 0A00h = 20h = 37h = 20h Example: BSF Before Instruction FLAG_OFST FSR2 Contents of 0A0Ah After Instruction Contents of 0A0Ah [FLAG_OFST], 7 = = 0Ah 0A00h = 55h = D5h Set Indexed (Indexed Literal Offset mode) SETF Syntax: SETF [k] Operands: 0  k  95 Operation: FFh  ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Data Write register Example: SETF Before Instruction OFST FSR2 Contents of 0A2Ch After Instruction Contents of 0A2Ch DS40001412H-page 408 [OFST] = = 2Ch 0A00h = 00h = FFh  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 25.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18(L)F2X/4XK22 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is ‘0’, disabling the extended instruction set and Indexed Literal Offset Addressing mode. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: • A menu option, or dialog box within the environment, that allows the user to configure the language tool and its settings for the project • A command line option • A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information.  2010-2021 Microchip Technology Inc. DS40001412H-page 409 PIC18(L)F2X/4XK22 26.0 DEVELOPMENT SUPPORT The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® X IDE Software • Compilers/Assemblers/Linkers - MPLAB XC Compiler - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB X SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers/Programmers - MPLAB ICD 3 - PICkit™ 3 • Device Programmers - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits • Third-party development tools 26.1 MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: • Color syntax highlighting • Smart code completion makes suggestions and provides hints as you type • Automatic code formatting based on user-defined rules • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • • • • Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker DS40001412H-page 410  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 26.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility 26.3 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: 26.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 26.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process  2010-2021 Microchip Technology Inc. DS40001412H-page 411 PIC18(L)F2X/4XK22 26.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 26.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. DS40001412H-page 412 26.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 26.9 PICkit 3 In-Circuit Debugger/ Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial Programming™ (ICSP™). 26.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 26.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. 26.12 Third-Party Development Tools Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. • Device Programmers and Gang Programmers from companies, such as SoftLog and CCS • Software Tools from companies, such as Gimpel and Trace Systems • Protocol Analyzers from companies, such as Saleae and Total Phase • Demonstration Boards from companies, such as MikroElektronika, Digilent® and Olimex • Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2010-2021 Microchip Technology Inc. DS40001412H-page 413 PIC18(L)F2X/4XK22 27.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (†) Ambient temperature under bias .............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, and MCLR)................................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS PIC18LF24K22 ......................................................................................................... -0.3V to +4.5V PIC18(L)F26K22 ....................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to VSS (Note 2) ........................................................................................... 0V to +11.0V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin (-40°C to +85°C)............................................................................................... 300 mA Maximum current out of VSS pin (+85°C to +125°C)............................................................................................ 125 mA Maximum current into VDD pin (-40°C to +85°C)...................................................................................................200 mA Maximum current into VDD pin (+85°C to +125°C) .................................................................................................85 mA Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin.....................................................................................................25 mA Maximum current sunk byall ports (-40°C to +85°C) ........................................................................................... 200 mA Maximum current sunk byall ports (+85°C to +125°C) ......................................................................................... 110 mA Maximum current sourced by all ports (-40°C to +85°C).......................................................................................185 mA Maximum current sourced by all ports (+85°C to +125°C)......................................................................................70 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 may be used when applying a “low” level to the MCLR/VPP/RE3 pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DS40001412H-page 414  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 27-1: PIC18LF2X/4XK22 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL TEMPERATURE) 5.5V Voltage 5.0V 4.0V 3.6V 3.0V 2.7V 2.3V 1.8V 10 16 20 30 40 48 60 64 Frequency (MHz) Note 1: Maximum Frequency 20 MHz, 1.8V to 2.7V, -40°C to +85°C 2: Maximum Frequency 64 MHz, 2.7V to 3.6V, -40°C to +85°C FIGURE 27-2: PIC18LF2X/4XK22 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED TEMPERATURE) 5.5V Voltage 5.0V 4.0V 3.6V 3.0V 2.7V 2.3V 1.8V 10 16 20 30 40 48 60 64 Frequency (MHz) Note 1: Maximum Frequency 16 MHz, 1.8V to 2.7V, +85°C to +125°C 2: Maximum Frequency 48 MHz, 2.7V to 3.6V, +85°C to +125°C  2010-2021 Microchip Technology Inc. DS40001412H-page 415 PIC18(L)F2X/4XK22 FIGURE 27-3: PIC18F2X/4XK22 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL TEMPERATURE) 5.5V Voltage 5.0V 4.0V 3.6V 3.0V 2.7V 2.3V 1.8V 10 16 20 30 40 48 60 64 Frequency (MHz) Note 1: Maximum Frequency 20 MHz, 2.3V to 2.7V, -40°C to +85°C 2: Maximum Frequency 64 MHz, 2.7V to 5.5V, -40°C to +85°C FIGURE 27-4: PIC18F2X/4XK22 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED TEMPERATURE) 5.5V Voltage 5.0V 4.0V 3.6V 3.0V 2.7V 2.3V 1.8V 10 16 20 30 40 48 60 64 Frequency (MHz) Note 1: Maximum Frequency 16 MHz, 2.3V to 2.7V, +85°C to +125°C 2: Maximum Frequency 48 MHz, 2.7V to 5.5V, +85°C to +125°C DS40001412H-page 416  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 27.1 DC Characteristics: Supply Voltage, PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C PIC18(L)F2X/4XK22 Param Symbol No. Characteristic D001 VDD Supply Voltage D002 VDR RAM Data Retention Voltage(1) D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal D004 SVDD VDD Rise Rate to ensure internal Power-on Reset signal D005 VBOR Brown-out Reset Voltage Note 1: 2: 3: Min PIC18LF2X/4XK22 1.8 PIC18F2X/4XK22 Typ Max Units — 3.6 2.3 — 5.5 V 1.5 — — V — — 0.7 V 0.05 — — BORV = 11(2) 1.75 1.9 2.05 V BORV = 10 2.05 2.2 2.35 V BORV = 01 2.35 2.5 2.65 V BORV = 00(3) 2.65 2.85 3.05 V Conditions V See section on Power-on Reset for details V/ms See section on Power-on Reset for details This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. On PIC18(L)F2X/4XK22 devices with BOR enabled, operation is supported until a BOR occurs. This is valid although VDD may be below the minimum rated supply voltage. With BOR enabled, full-speed operation (FOSC = 64 MHz or 48 MHz) is supported until a BOR occurs. This is valid although VDD may be below the minimum voltage for this frequency.  2010-2021 Microchip Technology Inc. DS40001412H-page 417 PIC18(L)F2X/4XK22 27.2 DC Characteristics: Power-Down Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. Typ Typ Max Max +25°C +60°C +85°C +125°C Device Characteristics Power-down Base Current (IPD) D006 Units Conditions VDD Notes (1) Sleep mode 2 10 A 1.8V 0.06 2 10 A 3.0V 13 25 35 A 2.3V 13 14 30 40 A 3.0V 13 14 35 50 A 5.0V 0.01 0.04 0.01 12 WDT, BOR, FVR and SOSC disabled, all Peripherals inactive Power-down Module Differential Current (delta IPD) D007 Watchdog Timer D008 Brown-out Reset(2) High/Low Voltage Detect(2) D010 D011 Secondary Oscillator Note 1: 2: 3: 0.3 0.3 2.5 2.5 A 1.8V 0.5 0.5 2.5 2.5 A 3.0V 0.35 0.35 5.0 5.0 A 2.3V 0.5 0.5 5.0 5.0 A 3.0V 0.5 0.5 5.0 5.0 A 5.0V 8 8.5 15 16 A 2.0V 9 9.5 15 16 A 3.0V 3.4 3.4 15 16 A 2.3V 3.8 3.8 15 16 A 3.0V 5.2 5.2 15 16 A 5.0V 6.5 6.7 15 15 A 2.0V 7 7.5 15 15 A 3.0V 2.1 2.1 15 15 A 2.3V 2.4 2.4 15 15 A 3.0V 3.2 3.2 15 15 A 5.0V 0.5 1 3 10 A 1.8V 0.6 1.1 4 10 A 3.0V 0.5 1 3 10 A 2.3V 0.6 1.1 4 10 A 3.0V 0.6 1.1 5 10 A 5.0V 32 kHz on SOSC The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). On PIC18LF2X/4XK22 the BOR, HLVD and FVR enable internal band gap reference. With more than one of these modules enabled, the current consumption will be less than the sum of the specifications. On PIC18F2X/4XK22, the internal band gap reference is always enabled and its current consumption is included in the Power-down Base Current (IPD). A/D converter differential currents apply only in Run mode. In Sleep or Idle mode both the ADC and the FRC turn off as soon as conversion (if any) is complete. DS40001412H-page 418  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 27.2 DC Characteristics: Power-Down Current, PIC18(L)F2X/4XK22 (Continued) PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. Typ Typ Max Max +25°C +60°C +85°C +125°C D015 Device Characteristics Comparators D016 Comparators D017 DAC FVR(2) D018 D013 A/D Note 1: 2: 3: Converter(3) Units Conditions VDD 7 7 18 18 A 1.8V 7 7 18 18 A 3.0V 7 7 18 18 A 2.3V 7 7 18 18 A 3.0V 8 8 20 20 A 5.0V 38 38 95 95 A 1.8V 40 40 105 105 A 3.0V 39 39 95 95 A 2.3V 40 40 105 105 A 3.0V 40 40 105 105 A 5.0V 14 14 25 25 A 2.0V 20 20 35 35 A 3.0V 15 15 30 30 A 2.3V 20 20 35 35 A 3.0V 32 32 60 60 A 5.0V 15 16 25 25 A 1.8V 15 16 25 25 A 3.0V 28 28 45 45 A 2.3V 31 31 55 55 A 3.0V 66 66 100 100 A 5.0V 185 185 370 370 A 1.8V 210 210 400 400 A 3.0V 200 200 380 380 A 2.3V 210 210 400 400 A 3.0V 250 250 450 450 A 5.0V Notes LP mode HP mode A/D on, not converting The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). On PIC18LF2X/4XK22 the BOR, HLVD and FVR enable internal band gap reference. With more than one of these modules enabled, the current consumption will be less than the sum of the specifications. On PIC18F2X/4XK22, the internal band gap reference is always enabled and its current consumption is included in the Power-down Base Current (IPD). A/D converter differential currents apply only in Run mode. In Sleep or Idle mode both the ADC and the FRC turn off as soon as conversion (if any) is complete.  2010-2021 Microchip Technology Inc. DS40001412H-page 419 PIC18(L)F2X/4XK22 27.3 DC Characteristics: RC Run Supply Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. D020 Device Characteristics Typ Max Units Supply Current (IDD)(1),(2) 3.6 23 A -40°C 3.9 25 A +25°C 3.9 — A +60°C 3.9 28 A +85°C D021 Conditions 4.0 30 A 125°C 8.1 26 A -40°C 8.4 30 A +25°C 8.6 — A +60°C VDD = 1.8V VDD = 3.0V 8.7 35 A +85°C 10.7 40 A +125°C 16 35 A -40°C 17 35 A +25°C 18 35 A +85°C 19 50 A +125°C 18 50 A -40°C 20 50 A +25°C 21 50 A +85°C 22 60 A +125°C 19 55 A -40°C 21 55 A +25°C 22 55 A +85°C 23 70 A +125°C D025 0.14 0.25 mA -40°C to +125°C VDD = 1.8V D026 0.17 0.30 mA -40°C to +125°C VDD = 3.0V D027 0.18 0.25 mA -40°C to +125°C VDD = 2.3V D028 0.20 0.30 mA -40°C to +125°C VDD = 3.0V D029 0.25 0.35 mA -40°C to +125°C VDD = 5.0V D022 D023 D024 Note 1: 2: FOSC = 31 kHz (RC_RUN mode, LFINTOSC source) VDD = 2.3V FOSC = 31 kHz (RC_RUN mode, LFINTOSC source) VDD = 3.0V VDD = 5.0V FOSC = 500 kHz (RC_RUN mode, MFINTOSC source) FOSC = 500 kHz (RC_RUN mode, MFINTOSC source) The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). DS40001412H-page 420  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 27.3 DC Characteristics: RC Run Supply Current, PIC18(L)F2X/4XK22 (Continued) PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. Typ Max Units D030 0.35 0.50 mA -40°C to +125°C VDD = 1.8V D031 0.45 0.65 mA -40°C to +125°C VDD = 3.0V D032 0.40 0.60 mA -40°C to +125°C VDD = 2.3V D033 0.50 0.65 mA -40°C to +125°C VDD = 3.0V D034 0.55 0.75 mA -40°C to +125°C VDD = 5.0V D035 1.3 2.0 mA -40°C to +125°C VDD = 1.8V D036 2.2 3.0 mA -40°C to +125°C VDD = 3.0V D037 1.7 2.0 mA -40°C to +125°C VDD = 2.3V D038 2.2 3.0 mA -40°C to +125°C VDD = 3.0V D039 2.5 3.5 mA -40°C to +125°C VDD = 5.0V D041 6.2 8.5 mA -40°C to +125°C VDD = 3.0V FOSC = 64 MHz (RC_RUN mode, HFINTOSC + PLL source) D043 6.2 8.5 mA -40°C to +125°C VDD = 3.0V D044 6.8 9.5 mA -40°C to +125°C VDD = 5.0V FOSC = 64 MHz (RC_RUN mode, HFINTOSC + PLL source) Note 1: 2: Device Characteristics Conditions FOSC = 1 MHz (RC_RUN mode, HFINTOSC source) FOSC = 1 MHz (RC_RUN mode, HFINTOSC source) FOSC = 16 MHz (RC_RUN mode, HFINTOSC source) FOSC = 16 MHz (RC_RUN mode, HFINTOSC source) The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).  2010-2021 Microchip Technology Inc. DS40001412H-page 421 PIC18(L)F2X/4XK22 27.4 DC Characteristics: RC Idle Supply Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. D045 Device Characteristics Typ Supply Current (IDD)(1),(2) 0.5 18 A -40°C 0.6 18 A +25°C D046 D047 D048 D049 Max Units Conditions 0.7 — A +60°C 0.75 20 A +85°C 2.3 22 A +125°C 1.1 20 A -40°C 1.2 20 A +25°C 1.3 — A +60°C 1.4 22 A +85°C 3.2 25 A +125°C 17 30 A -40°C 13 30 A +25°C 14 30 A +85°C 15 45 A +125°C 19 35 A -40°C 15 35 A +25°C 16 35 A +85°C 17 50 A +125°C 21 40 A -40°C 15 40 A +25°C 16 40 A +85°C VDD = 1.8V VDD = 3.0V VDD = 2.3V VDD = 5.0V 18 60 A +125°C 0.11 0.20 mA -40°C to +125°C VDD = 1.8V D051 0.12 0.25 mA -40°C to +125°C VDD = 3.0V D052 0.14 0.21 mA -40°C to +125°C VDD = 2.3V D053 0.15 0.25 mA -40°C to +125°C VDD = 3.0V D054 0.20 0.31 mA -40°C to +125°C VDD = 5.0V 2: FOSC = 31 kHz (RC_IDLE mode, LFINTOSC source) VDD = 3.0V D050 Note 1: FOSC = 31 kHz (RC_IDLE mode, LFINTOSC source) FOSC = 500 kHz (RC_IDLE mode, MFINTOSC source) FOSC = 500 kHz (RC_IDLE mode, MFINTOSC source) The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). DS40001412H-page 422  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 27.4 DC Characteristics: RC Idle Supply Current, PIC18(L)F2X/4XK22 (Continued) PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. Device Characteristics Typ Max Units Conditions D055 0.25 0.40 mA -40°C to +125°C VDD = 1.8V D056 0.35 0.50 mA -40°C to +125°C VDD = 3.0V D057 0.30 0.45 mA -40°C to +125°C VDD = 2.3V D058 0.40 0.50 mA -40°C to +125°C VDD = 3.0V FOSC = 1 MHz (RC_IDLE mode, HFINTOSC source) FOSC = 1 MHz (RC_IDLE mode, HFINTOSC source) D059 0.45 0.60 mA -40°C to +125°C VDD = 5.0V D060 0.50 0.7 mA -40°C to +125°C VDD = 1.8V D061 0.80 1.1 mA -40°C to +125°C VDD = 3.0V D062 0.65 1.0 mA -40°C to +125°C VDD = 2.3V D063 0.80 1.1 mA -40°C to +125°C VDD = 3.0V D064 0.95 1.2 mA -40°C to +125°C VDD = 5.0V D066 2.5 3.5 mA -40°C to +125°C VDD = 3.0V FOSC = 64 MHz (RC_IDLE mode, HFINTOSC + PLL source) D068 2.5 3.5 mA -40°C to +125°C VDD = 3.0V D069 3.0 4.5 mA -40°C to +125°C VDD = 5.0V FOSC = 64 MHz (RC_IDLE mode, HFINTOSC + PLL source) Note 1: 2: FOSC = 16 MHz (RC_IDLE mode, HFINTOSC source) FOSC = 16 MHz (RC_IDLE mode, HFINTOSC source) The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).  2010-2021 Microchip Technology Inc. DS40001412H-page 423 PIC18(L)F2X/4XK22 27.5 DC Characteristics: Primary Run Supply Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. Device Characteristics Typ Max Units Supply Current (IDD)(1),(2) 0.11 0.20 mA -40°C to +125°C VDD = 1.8V D071 0.17 0.25 mA -40°C to +125°C VDD = 3.0V D072 0.15 0.25 mA -40°C to +125°C VDD = 2.3V D073 0.20 0.30 mA -40°C to +125°C VDD = 3.0V D074 0.25 0.35 mA -40°C to +125°C VDD = 5.0V D075 1.45 2.0 mA -40°C to +125°C VDD = 1.8V D076 2.60 3.5 mA -40°C to +125°C VDD = 3.0V D077 1.95 2.5 mA -40°C to +125°C VDD = 2.3V D078 2.65 3.5 mA -40°C to +125°C VDD = 3.0V D079 2.95 4.5 mA -40°C to +125°C VDD = 5.0V D080 7.5 10 mA -40°C to +125°C VDD = 3.0V FOSC = 64 MHz (PRI_RUN, ECH oscillator) D081 7.5 10 mA -40°C to +125°C VDD = 3.0V D082 8.5 11.5 mA -40°C to +125°C VDD = 5.0V FOSC = 64 MHz (PRI_RUN mode, ECH source) D083 1.0 1.5 mA -40°C to +125°C VDD = 1.8V D084 1.8 3.0 mA -40°C to +125°C VDD = 3.0V D085 1.4 2.0 mA -40°C to +125°C VDD = 2.3V D086 1.85 2.5 mA -40°C to +125°C VDD = 3.0V D087 2.1 3.0 mA -40°C to +125°C VDD = 5.0V D088 6.35 9.0 mA -40°C to +125°C VDD = 3.0V FOSC = 16 MHz 64 MHz Internal (PRI_RUN mode, ECH + PLL source) D089 6.35 9.0 mA -40°C to +125°C VDD = 3.0V D090 7.0 10 mA -40°C to +125°C VDD = 5.0V FOSC = 16 MHz 64 MHz Internal (PRI_RUN mode, ECH + PLL source) D070 Note 1: 2: Conditions FOSC = 1 MHz (PRI_RUN mode, ECM source) FOSC = 1 MHz (PRI_RUN mode, ECM source) FOSC = 20 MHz (PRI_RUN mode, ECH source) FOSC = 20 MHz (PRI_RUN mode, ECH source) FOSC = 4 MHz 16 MHz Internal (PRI_RUN mode, ECM + PLL source) FOSC = 4 MHz 16 MHz Internal (PRI_RUN mode, ECM + PLL source) The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). DS40001412H-page 424  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 27.6 DC Characteristics: Primary Idle Supply Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. Device Characteristics Supply Current (IDD)(1),(2) D100 Typ Max Units Conditions 0.030 0.050 mA -40°C to +125°C VDD = 1.8V D101 0.045 0.065 mA -40°C to +125°C VDD = 3.0V D102 0.06 0.12 mA -40°C to +125°C VDD = 2.3V D103 0.08 0.15 mA -40°C to +125°C VDD = 3.0V D104 0.13 0.20 mA -40°C to +125°C VDD = 5.0V Fosc = 1 MHz (PRI_IDLE mode, ECM source) Fosc = 1 MHz (PRI_IDLE mode, ECM source) D105 0.45 0.8 mA -40°C to +125°C VDD = 1.8V D106 0.70 1.0 mA -40°C to +125°C VDD = 3.0V D107 0.55 0.8 mA -40°C to +125°C VDD = 2.3V D108 0.75 1.0 mA -40°C to +125°C VDD = 3.0V D109 0.90 1.2 mA -40°C to +125°C VDD = 5.0V D110 2.25 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 64 MHz (PRI_IDLE mode, ECH source) D111 2.25 3.0 mA -40°C to +125°C VDD = 3.0V D112 2.60 3.5 mA -40°C to +125°C VDD = 5.0V Fosc = 64 MHz (PRI_IDLE mode, ECH source) Fosc = 20 MHz (PRI_IDLE mode, ECH source) Fosc = 20 MHz (PRI_IDLE mode, ECH source) D113 0.35 0.6 mA -40°C to +125°C VDD = 1.8V D114 0.55 0.8 mA -40°C to +125°C VDD = 3.0V D115 0.45 0.6 mA -40°C to +125°C VDD = 2.3V D116 0.60 0.9 mA -40°C to +125°C VDD = 3.0V D117 0.70 1.0 mA -40°C to +125°C VDD = 5.0V D118 2.2 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 16 MHz 64 MHz Internal (PRI_IDLE mode, ECH + PLL source) D119 2.2 3.0 mA -40°C to +125°C VDD = 3.0V D120 2.5 3.5 mA -40°C to +125°C VDD = 5.0V Fosc = 16 MHz 64 MHz Internal (PRI_IDLE mode, ECH + PLL source) Note 1: 2: Fosc = 4 MHz 16 MHz Internal (PRI_IDLE mode, ECM + PLL source) Fosc = 4 MHz 16 MHz Internal (PRI_IDLE mode, ECM + PLL source) The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).  2010-2021 Microchip Technology Inc. DS40001412H-page 425 PIC18(L)F2X/4XK22 . 27.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. D130 Device Characteristics Typ Supply Current (IDD)(1),(2) 3.5 23 A -40°C 3.7 25 A +25°C 3.8 — A +60°C 4.0 28 A +85°C 5.1 30 A +125°C 6.2 26 A -40°C 6.4 30 A +25°C 6.5 — A +60°C 6.8 35 A +85°C 7.8 40 A +125°C 15 35 A -40°C 16 35 A +25°C 17 35 A +85°C 19 50 A +125°C 18 50 A -40°C 19 50 A +25°C 21 50 A +85°C 22 60 A +125°C 19 55 A -40°C 20 55 A +25°C 22 55 A +85°C 23 70 A +125°C D131 D132 D133 D134 Note 1: 2: Max Units Conditions VDD = 1.8V Fosc = 32 kHz (SEC_RUN mode, SOSC source) VDD = 3.0V VDD = 2.3V Fosc = 32 kHz (SEC_RUN mode, SOSC source) VDD = 3.0V VDD = 5.0V The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; SOSCI / SOSCO = complementary external square wave, from rail-to-rail. DS40001412H-page 426  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 27.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. Device Characteristics D135 D136 D137 D138 D139 Note 1: 2: Typ Max Units Conditions 0.9 18 A -40°C 1.0 18 A +25°C 1.1 — A +60°C 1.3 20 A +85°C 2.3 22 A +125°C 1.3 20 A -40°C 1.4 20 A +25°C 1.5 — A +60°C 1.8 22 A +85°C 2.9 25 A +125°C 12 30 A -40°C 13 30 A +25°C 14 30 A +85°C 16 45 A +125°C 13 35 A -40°C 14 35 A +25°C 16 35 A +85°C 18 50 A +125°C 14 40 A -40°C 15 40 A +25°C 16 40 A +85°C 18 60 A +125°C VDD = 1.8V Fosc = 32 kHz (SEC_IDLE mode, SOSC source) VDD = 3.0V VDD = 2.3V Fosc = 32 kHz (SEC_IDLE mode, SOSC source) VDD = 3.0V VDD = 5.0V The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; SOSCI / SOSCO = complementary external square wave, from rail-to-rail.  2010-2021 Microchip Technology Inc. DS40001412H-page 427 PIC18(L)F2X/4XK22 27.8 DC Characteristics: Input/Output Characteristics, PIC18(L)F2X/4XK22 DC CHARACTERISTICS Param Symbol No. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA  +125°C Min Typ† Max Units Conditions — — 0.8 V 4.5V  VDD  5.5V — — 0.15 VDD V 1.8V  VDD  4.5V with Schmitt Trigger buffer — — 0.2 VDD V 2.0V  VDD  5.5V with I2C levels — — 0.3 VDD V with SMBus levels — — 0.8 V Input Low Voltage I/O PORT: D140 with TTL buffer D140A D141 D142 MCLR, OSC1 (RC mode)(1) — — 0.2 VDD V D142A OSC1 (HS mode) — — 0.3 VDD V — — VIH Input High Voltage I/O ports: D147 2.0 — — V 4.5V  VDD 5.5V 0.25 VDD + 0.8 — — V 1.8V  VDD  4.5V with Schmitt Trigger buffer 0.8 VDD — — V 2.0V  VDD  5.5V with I2C levels 0.7 VDD — — V 2.1 — — V with TTL buffer D147A D148 with SMBus levels D149 MCLR 0.8 VDD — — V D150A OSC1 (HS mode) 0.7 VDD — — V D150B OSC1 (RC mode)(1) 0.9 VDD — — V IIL D155 Note 1: 2: 3: 4: IPU Weak Pull-up Current(4) IPURB PORTB weak pull-up current 2.7V  VDD  5.5V VSS VPIN VDD, Pin at high-impedance Input Leakage I/O and MCLR(2),(3) I/O ports and MCLR D158 2.7V  VDD  5.5V — — — — 0.1 0.7 4 35 50 100 200 1000 nA nA nA nA +25°C(4) +60°C +85°C +125°C 25 25 85 130 200 300 A A VDD = 3.3V, VPIN = VSS VDD = 5.0V, VPIN = VSS In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested. DS40001412H-page 428  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 27.8 DC Characteristics: Input/Output Characteristics, PIC18(L)F2X/4XK22 (Continued) DC CHARACTERISTICS Param Symbol No. VOL D159 Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA  +125°C Min Typ† Max Units Conditions — — 0.6 V IOL = 8 mA, VDD = 5V IOL = 6 mA, VDD = 3.3V IOL = 1.8 mA, VDD = 1.8V VDD - 0.7 — — V IOH = 3.5 mA, VDD = 5V IOH = 3 mA, VDD = 3.3V IOH = 1 mA, VDD = 1.8V Output Low Voltage I/O ports VOH D161 Output High Voltage(3) I/O ports Note 1: 2: 3: 4: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested.  2010-2021 Microchip Technology Inc. DS40001412H-page 429 PIC18(L)F2X/4XK22 27.9 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units Conditions Internal Program Memory Programming Specifications(1) D170 VPP Voltage on MCLR/VPP pin 8 — 9 V D171 IDDP Supply Current during Programming — — 10 mA 100K — — E/W VDDMIN — VDDMAX V (Note 3), (Note 4) Data EEPROM Memory D172 ED Byte Endurance D173 VDRW VDD for Read/Write D175 TDEW Erase/Write Cycle Time — 3 4 ms D176 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated D177 TREF 1M 10M — E/W -40°C to +85°C 10K — — E/W -40C to +85C (Note 5) VDDMIN — VDDMAX V Number of Total Erase/Write Cycles before Refresh(2) -40C to +85C Using EECON to read/ write Program Flash Memory D178 EP Cell Endurance D179 VPR VDD for Read D181 VIW VDD for Row Erase or Write D182 VIW D183 TIW D184 TRETD Characteristic Retention Self-timed Write Cycle Time 2.2 — VDDMAX V PIC18LF24K22 VDDMIN — VDDMAX V PIC18(L)F26K22 — 2 — ms — 40 — Year Provided no other specifications are violated † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Refer to Section 7.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. 4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the MPLAB ICD 2 VPP voltage must be placed between the MPLAB ICD 2 and target system when programming or debugging with the MPLAB ICD 2. 5: Self-write and Block Erase. DS40001412H-page 430  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 27.10 Analog Characteristics TABLE 27-1: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated) Param No. CM01 CM02 CM04* CM05* * Note 1: Sym VIOFF Characteristics Input Offset Voltage Input Common-mode Voltage VICM TRESP TMC2OV Response Time (1) Comparator Mode Change to Output Valid Min Typ Max Units Comments — 3 40 mV High-Power mode VREF = VDD/2 — 4 60 mV Low-Power mode VREF = VDD/2 VSS — VDD V — 200 400 ns High-Power mode — 600 3500 ns Low-Power mode — — 10 s These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. TABLE 27-2: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions: 2.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated) Param No. Sym Characteristics Min Typ Max Units CV01* CLSB Step Size(2) — VDD/32 — V CV02* CACC Absolute Accuracy — — 1/2 LSb CV03* CR Unit Resistor Value (R) — 5k —  Time(1) CV04* CST Settling — — 10 s CV05* VSRC+ DAC Positive Reference VSRC- +2 — VDD V CV06* VSRC- DAC Negative Reference VSS — VSRC+ -2 V CV07* VSRC DAC Reference Range (VSRC+ - VSRC-) 2 — VDD V * Note 1: 2: Comments VSRC 2.0V These parameters are characterized but not tested. Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’. See Section 22.0 “Digital-to-Analog Converter (DAC) Module” for more information.  2010-2021 Microchip Technology Inc. DS40001412H-page 431 PIC18(L)F2X/4XK22 TABLE 27-3: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS Operating Conditions: -40°C < TA < +125°C (unless otherwise stated) Param No. VR01 Sym Characteristics VR voltage output to ADC VROUT VR02 VROUT VR04* VR voltage output all other modules TSTABLE * Settling Time Min Typ Max Units Comments 0.973 1.024 1.085 V 1x output, VDD 2.5V 1.946 2.048 2.171 V 2x output, VDD 2.5V 3.891 4.096 4.342 V 4x output, VDD 4.75V (PIC18F2X/4XK22) 0.942 1.024 1.096 V 1x output, VDD 2.5V 1.884 2.048 2.191 V 2x output, VDD 2.5V 3.768 4.096 4.383 V 4x output, VDD 4.75V (PIC18F2X/4XK22) — 25 100 s 0 to 125°C These parameters are characterized but not tested. TABLE 27-4: CHARGE TIME MEASUREMENT UNIT (CTMU) SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated) Param No. Sym Characteristics Min Typ(1) Max Units Comments CT01 IOUT1 CTMU Current Source, Base Range — 0.55 — A IRNG=01 CT02 IOUT2 CTMU Current Source, 10X Range — 5.5 — A IRNG=10 CT03 IOUT3 CTMU Current Source, 100X Range — 55 — A IRNG=11 VDD  3.0V Note 1: Nominal value at center point of current trim range (CTMUICON=000000). DS40001412H-page 432  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 27-5: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD (HLVDIF can be cleared by software) VHLVD (HLVDIF set by hardware) HLVDIF TABLE 27-5: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Symbol No. Characteristic HLVDL Min Typ† Max Units HLVD Voltage on VDD Transition High-to-Low 0000 1.69 1.84 1.99 V 0001 1.92 2.07 2.22 V 0010 2.08 2.28 2.48 V 0011 2.24 2.44 2.64 V 0100 2.34 2.54 2.74 V 0101 2.54 2.74 2.94 V 0110 2.62 2.87 3.12 V 0111 2.76 3.01 3.26 V 1000 3.00 3.30 3.60 V 1001 3.18 3.48 3.78 V 1010 3.44 3.69 3.94 V 1011 3.66 3.91 4.16 V 1100 3.90 4.15 4.40 V 1101 4.11 4.41 4.71 V 1110 4.39 4.74 5.09 V 1111 V(HLVDIN pin) Conditions v † Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.  2010-2021 Microchip Technology Inc. DS40001412H-page 433 PIC18(L)F2X/4XK22 27.11 AC (Timing) Characteristics 27.11.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T13CKI WR Fall High Invalid (High-impedance) Low P R V Z Period Rise Valid High-impedance output access Bus free High Low High Low Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F H I L I2C only AA BUF TCC:ST (I2C specifications only) CC HD Hold SU Setup DAT STA DATA input hold Start condition STO Stop condition ST DS40001412H-page 434  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 27.11.2 TIMING CONDITIONS The temperature and voltages specified in Table 27-6 apply to all timing specifications unless otherwise noted. Figure 27-6 specifies the load conditions for the timing specifications. TABLE 27-6: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS FIGURE 27-6: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA +125°C Operating voltage VDD range as described in Section 27.1 “DC Characteristics: Supply Voltage, PIC18(L)F2X/4XK22” and Section 27.9 “Memory Programming Requirements”. LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL CL Pin VSS  2010-2021 Microchip Technology Inc. CL Pin Legend: RL = 464 CL = 50 pF VSS for all pins except OSC2/CLKOUT and including D and E outputs as ports DS40001412H-page 435 PIC18(L)F2X/4XK22 27.11.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-7: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 27-7: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic External CLKIN Frequency(1) (1) Oscillator Frequency 1 TOSC External CLKIN Period(1) Oscillator Period (1) Min Max Units Conditions DC DC 0.5 16 MHz MHz DC 64 MHz DC 4 MHz RC Oscillator mode 5 200 kHz LP Oscillator mode 0.1 4 MHz XT Oscillator mode 4 4 MHz HS Oscillator mode, VDD < 2.7V 4 16 MHz HS Oscillator mode, VDD 2.7V, Medium-Power mode (HSMP) 4 20 MHz HS Oscillator mode, VDD 2.7V, High-Power mode (HSHP) 2.0 62.5 — — s ns 15.6 — ns EC, ECIO Oscillator mode (low power) EC, ECIO Oscillator mode (medium power) EC, ECIO Oscillator mode (high power) EC, ECIO Oscillator mode (low power) EC, ECIO Oscillator mode (medium power) EC, ECIO Oscillator mode (high power) 250 — ns RC Oscillator mode 5 200 s LP Oscillator mode 0.25 250 10 250 s ns XT Oscillator mode HS Oscillator mode, VDD < 2.7V 62.5 250 ns HS Oscillator mode, VDD 2.7V, Medium-Power mode (HSMP) 50 250 ns HS Oscillator mode, VDD 2.7V, High-Power mode (HSHP) 2 TCY Instruction Cycle Time(1) 62.5 — ns TCY = 4/FOSC 3 TOSL, TOSH External Clock in (OSC1) High or Low Time 2.5 — s LP Oscillator mode 4 Note 1: TOSR, TOSF External Clock in (OSC1) Rise or Fall Time 30 — ns XT Oscillator mode 10 — ns HS Oscillator mode — 50 ns LP Oscillator mode — 20 ns XT Oscillator mode — 7.5 ns HS Oscillator mode Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS40001412H-page 436  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 27-8: PLL CLOCK TIMING SPECIFICATIONS Param. No. Sym F10 FOSC Oscillator Frequency Range F11 F12 FSYS Characteristic On-Chip VCO System Frequency PLL Start-up Time (Lock Time) trc TABLE 27-9: Min Max Units Conditions 4 5 MHz VDD < 2.7V, -40°C to +85°C 4 4 MHz VDD < 2.7V, +85°C to +125°C 4 16 MHz 2.7V  VDD, -40°C to +85°C 4 12 MHz 2.7V  VDD, +85°C to +125°C 16 20 MHz VDD < 2.7V, -40°C to +85°C 16 16 MHz VDD < 2.7V, +85°C to +125°C 16 64 MHz 2.7V  VDD, -40°C to +85°C 16 48 MHz 2.7V  VDD, +85°C to +125°C — 2 ms AC CHARACTERISTICS:INTERNAL OSCILLATORS ACCURACY PIC18(L)F46K22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param. No. OA1 OA2 OA3 Characteristics Internal Calibrated HFINTOSC Frequency(1) Freq. Tolerance Min Typ† Max  2% — 16.0 — Units Conditions MHz 0°C TA +60°C, VDD 2.5V  3% — 16.0 — MHz +60°C TA +85°C, VDD 2.5V  5% — 16.0 — MHz -40°C TA +125°C Internal Calibrated MFINTOSC Frequency(1)  2% — 500 — kHz 0°C TA +60°C, VDD 2.5V  3% — 500 — kHz +60°C TA +85°C, VDD 2.5V  5% — 500 — kHz -40°C TA +125°C Internal Calibrated LFINTOSC Frequency(1)  20% — 31 — kHz -40°C TA +125°C † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended.  2010-2021 Microchip Technology Inc. DS40001412H-page 437 PIC18(L)F2X/4XK22 FIGURE 27-8: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) Note: New Value Old Value 20, 21 Refer to Figure 27-6 for load conditions. TABLE 27-10: CLKOUT AND I/O TIMING REQUIREMENTS Param. No. Symbol Characteristic Min Typ Max Units Conditions 10 TosH2ckL OSC1  to CLKOUT  — 75 200 ns (Note 1) 11 TosH2ckH OSC1  to CLKOUT  — 75 200 ns (Note 1) 12 TckR CLKOUT Rise Time — 35 100 ns (Note 1) 13 TckF CLKOUT Fall Time — 35 100 ns (Note 1) 14 TckL2ioV CLKOUT  to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15 TioV2ckH Port In Valid before CLKOUT  0.25 TCY + 25 — — ns (Note 1) 16 TckH2ioI Port In Hold after CLKOUT  0 — — ns (Note 1) 17 TosH2ioV OSC1  (Q1 cycle) to Port Out Valid 18 TosH2ioI OSC1  (Q2 cycle) to Port Input Invalid (I/O in hold time) 19 TioV2osH 20 TioR 21 — 50 150 ns 100 — — ns Port Input Valid to OSC1 (I/O in setup time) 0 — — ns Port Output Rise Time — — 40 15 72 32 ns ns VDD = 1.8V VDD = 3.3V - 5.0V TioF Port Output Fall Time — — 28 15 55 30 ns ns VDD = 1.8V VDD = 3.3V - 5.0V 22† TINP INTx pin High or Low Time 20 — — ns 23† TRBP RB Change KBIx High or Low Time TCY — — ns † Note 1: These parameters are asynchronous events not related to any internal clock edges. Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC. DS40001412H-page 438  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 27-9: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 27-6 for load conditions. FIGURE 27-10: BROWN-OUT RESET TIMING VDD BVDD 35 VBGAP = 1.2V VIVRST Enable Internal Reference Voltage Internal Reference Voltage Stable  2010-2021 Microchip Technology Inc. 36 DS40001412H-page 439 PIC18(L)F2X/4XK22 TABLE 27-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. No. Symbol Characteristic Min Typ Max Units 2 — — s Conditions 30 TmcL MCLR Pulse Width (low) 31 TWDT Watchdog Timer Time-out Period (no postscaler) 3.5 4.1 4.7 ms 1:1 prescaler 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 54.8 64.4 74.1 ms 34 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset — 2 — s 35 TBOR Brown-out Reset Pulse Width 2001 — — s 36 TIVRST Internal Reference Voltage Stable 37 THLVD High/Low-Voltage Detect Pulse Width — 25 35 s 2001 — — s — 10 s 38 TCSD CPU Start-up Time 5 39 TIOBST Time for HF-INTOSC to Stabilize — 0.25 1 ms 40 TIOSC_ST Time for HF-INTOSC to Start — TBD TBD µs VDD  BVDD (see D005) VDD  VHLVD Note 1: Minimum pulse width that will consistently trigger a reset or interrupt. Shorter pulses may intermittently trigger a response. FIGURE 27-11: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T13CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 27-6 for load conditions. DS40001412H-page 440  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 27-12: TIMER0 AND TIMER1/3/5 EXTERNAL CLOCK REQUIREMENTS Param. No. 40 Symbol Tt0H Characteristic T0CKI High Pulse Width No prescaler Min Max Units 0.5 TCY + 20 — ns 10 — ns 0.5 TCY + 20 — ns 10 — ns With prescaler 41 Tt0L T0CKI Low Pulse Width No prescaler With prescaler 42 Tt0P T0CKI Period With prescaler 45 46 47 48 Tt1H TxCKI High Time Tt1L TxCKI Low Time Tt1P TxCKI Input Period — ns — ns 0.5 TCY + 20 — ns Synchronous, with prescaler 10 — ns Asynchronous 30 — ns Synchronous, no prescaler Synchronous, no prescaler 0.5 TCY + 5 — ns Synchronous, with prescaler 10 — ns Asynchronous 30 — ns Synchronous Greater of: 20 ns or (TCY + 40)/N — ns Asynchronous 60 — ns DC 50 kHz 2 TOSC 7 TOSC — Ft1 TxCKI Clock Input Frequency Range Tcke2tmrI Delay from External TxCKI Clock Edge to Timer Increment FIGURE 27-12: TCY + 10 Greater of: 20 ns or (TCY + 40)/N No prescaler Conditions N = prescale value (1, 2, 4,..., 256) N = prescale value (1, 2, 4, 8) CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 27-6 for load conditions.  2010-2021 Microchip Technology Inc. DS40001412H-page 441 PIC18(L)F2X/4XK22 TABLE 27-13: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param. Symbol No. 50 51 TccL TccH Characteristic Min Max Units CCPx Input Low No prescaler Time With prescaler 0.5 TCY + 20 — ns 10 — ns CCPx Input High Time 0.5 TCY + 20 — ns 10 — ns 3 TCY + 40 N — ns No prescaler With prescaler 52 TccP CCPx Input Period 53 TccR CCPx Output Fall Time — 25 ns 54 TccF CCPx Output Fall Time — 25 ns DS40001412H-page 442 Conditions N = prescale value (1, 4 or 16)  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 27-13: EXAMPLE SPI HOST MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 27-6 for load conditions. FIGURE 27-14: EXAMPLE SPI HOST MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - -1 LSb bit 6 - - - -1 LSb In 75, 76 SDI MSb In 74 Note: Refer to Figure 27-6 for load conditions.  2010-2021 Microchip Technology Inc. DS40001412H-page 443 PIC18(L)F2X/4XK22 FIGURE 27-15: EXAMPLE SPI CLIENT MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb bit 6 - - - - - -1 77 75, 76 MSb In SDI 73 Note: bit 6 - - - -1 LSb In 74 Refer to Figure 27-6 for load conditions. FIGURE 27-16: EXAMPLE SPI CLIENT MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI Note: MSb In 77 bit 6 - - - -1 LSb In 74 Refer to Figure 27-6 for load conditions. DS40001412H-page 444  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 27-14: SPI MODE REQUIREMENTS Param. No. Symbol Characteristic Min Max Units 70 TssL2scH, TssL2scL SS  to SCK  or SCK  Input TCY — ns 71 TscH SCK Input High Time Continuous 25 — ns 72 TscL SCK Input Low Time Continuous 30 — ns 73 TdiV2scH, TdiV2scL Setup Time of SDI Data Input to SCK Edge 25 — ns 74 TscH2diL, TscL2diL Hold Time of SDI Data Input to SCK Edge 25 — ns 75 TdoR SDO Data Output Rise Time — 30 ns 76 TdoF SDO Data Output Fall Time — 20 ns 77 TssH2doZ SS to SDO Output High-Impedance 10 50 ns 78 TscR SCK Output Rise Time (Host mode) — 30 ns 79 TscF SCK Output Fall Time (Host mode) — 20 ns 80 TscH2doV, TscL2doV SDO Data Output Valid after SCK Edge — 20 60 ns ns 81 TdoV2scH, TdoV2scL SDO Data Output Setup to SCK Edge TCY — ns 82 TssL2doV SDO Data Output Valid after SS  Edge — 60 ns 83 TscH2ssH, TscL2ssH SS  after SCK edge 1.5 TCY + 40 — ns Conditions SPI Host Mode SPI Client Mode I2C BUS START/STOP BITS TIMING FIGURE 27-17: SCL 91 90 93 92 SDA Start Condition Note: Stop Condition Refer to Figure 27-6 for load conditions.  2010-2021 Microchip Technology Inc. DS40001412H-page 445 PIC18(L)F2X/4XK22 TABLE 27-15: I2C BUS START/STOP BITS REQUIREMENTS (CLIENT MODE) Param. Symbol No. 90 TSU:STA 91 THD:STA 92 TSU:STO 93 Characteristic Min Max Units Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated Start Condition 100 kHz mode 4700 — Setup Time 400 kHz mode 600 — Start Condition 100 kHz mode 4000 — Hold Time 400 kHz mode 600 — Stop Condition 100 kHz mode 4700 — Setup Time 400 kHz mode 600 — 100 kHz mode 4000 — 400 kHz mode 600 — THD:STO Stop Condition Hold Time FIGURE 27-18: ns ns I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 27-6 for load conditions. DS40001412H-page 446  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 27-16: I2C BUS DATA REQUIREMENTS (CLIENT MODE) Param. Symbol No. Min Max Units Conditions 100 kHz mode 4.0 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Must operate at a minimum of 10 MHz 1.5 TCY — 100 kHz mode 4.7 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Must operate at a minimum of 10 MHz 1.5 TCY — — 1000 ns 20 + 0.1 CB 300 ns 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s Only relevant for Repeated Start condition 91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s 106 THD:DA 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s ns 100 THIGH Characteristic Clock High Time SSP Module 101 TLOW Clock Low Time SSP Module 102 TR 103 TF 90 T SDA and SCL Rise 100 kHz mode Time 400 kHz mode SDA and SCL Fall Time Data Input Hold Time 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s 109 TAA Output Valid from Clock 100 kHz mode — 3500 ns 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s — 400 pF D102 CB Note 1: 2: Bus Capacitive Loading CB is specified to be from 10 to 400 pF After this period, the first clock pulse is generated (Note 2) (Note 1) Time the bus must be free before a new transmission can start As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement, TSU:DAT  250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification), before the SCL line is released.  2010-2021 Microchip Technology Inc. DS40001412H-page 447 PIC18(L)F2X/4XK22 HOST SSP I2C BUS START/STOP BITS TIMING WAVEFORMS FIGURE 27-19: SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 27-6 for load conditions. TABLE 27-17: HOST SSP I2C BUS START/STOP BITS REQUIREMENTS Param. Symbol No. 90 TSU:STA Characteristic ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated 2(TOSC)(BRG + 1) — Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — (1) 2(TOSC)(BRG + 1) — THD:STA Start Condition TSU:STO Stop Condition Setup Time 93 Units 100 kHz mode Hold Time 92 Max Start Condition 1 MHz mode 91 Min THD:STO Stop Condition Hold Time 100 kHz mode 2(TOSC)(BRG + 1) — 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 100 kHz mode 2(TOSC)(BRG + 1) — 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 100 kHz mode 2(TOSC)(BRG + 1) — 400 kHz mode 2(TOSC)(BRG + 1) — (1) 2(TOSC)(BRG + 1) — 1 MHz mode Conditions ns ns Note 1: Maximum pin capacitance = 10 pF for all I2C pins. HOST SSP I2C BUS DATA TIMING FIGURE 27-20: 103 102 100 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: Refer to Figure 27-6 for load conditions. DS40001412H-page 448  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 27-18: HOST SSP I2C BUS DATA REQUIREMENTS Param. Symbol No. 100 THIGH Characteristic Min Max Units Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms 100 kHz mode — 1000 ns 1 MHz mode 101 TLOW 1 MHz mode 102 103 TR TF SDA and SCL Rise Time SDA and SCL Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) — 300 ns 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns (1) — 100 ns 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms 1 MHz mode 90 TSU:STA Start Condition Setup Time 1 MHz mode 91 THD:STA Start Condition Hold Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 0 — ns 106 THD:DAT Data Input Hold Time 100 kHz mode 400 kHz mode 0 0.9 ms 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns 400 kHz mode 100 — ns TSU:STO Stop Condition Setup Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 100 kHz mode — 3500 ns 400 kHz mode ns 92 109 110 D102 Note 1: 2: TAA TBUF CB Output Valid from Clock Bus Free Time — 1000 (1) 1 MHz mode — — ns 100 kHz mode 4.7 — ms 400 kHz mode 1.3 — ms — 400 pF Bus Capacitive Loading Conditions CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated (Note 2) Time the bus must be free before a new transmission can start Maximum pin capacitance = 10 pF for all I2C pins. A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter 107  250 ns must then be met. This will automatically be the case if the device does not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCL line is released.  2010-2021 Microchip Technology Inc. DS40001412H-page 449 PIC18(L)F2X/4XK22 FIGURE 27-21: EUSART SYNCHRONOUS TRANSMISSION (HOST/CLIENT) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 Note: 122 Refer to Figure 27-6 for load conditions. TABLE 27-19: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. No. Min Max Units TckH2dtV SYNC XMIT (HOST & CLIENT) Clock High to Data Out Valid — 40 ns 121 Tckrf Clock Out Rise Time and Fall Time (Host mode) — 20 ns 122 Tdtrf Data Out Rise Time and Fall Time — 20 ns 120 Symbol Characteristic FIGURE 27-22: EUSART SYNCHRONOUS RECEIVE (HOST/CLIENT) TIMING TXx/CKx pin RXx/DTx Conditions 125 pin 126 Note: Refer to Figure 27-6 for load conditions. TABLE 27-20: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. No. Symbol Characteristic Min Max Units 125 TdtV2ckl SYNC RCV (HOST & CLIENT) Data Setup before CK  (DT setup time) 10 — ns 126 TckL2dtl Data Hold after CK  (DT hold time) 15 — ns DS40001412H-page 450 Conditions  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 TABLE 27-21: A/D CONVERTER CHARACTERISTICS:PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature Tested at +25°C PIC18(L)F2X/4XK22 Param. Symbol No. Characteristic Min Typ Max Units Conditions — — 10 bits VREF  3.0V A01 NR Resolution A03 EIL Integral Linearity Error — ±0.5 ±1 LSb VREF = 3.0V A04 EDL Differential Linearity Error — ±0.5 ±1 LSb VREF  3.0V A06 EOFF Offset Error — ±0.7 ±2 LSb VREF  3.0V A07 EGN Gain Error — ±0.7 ±2 LSb VREF  3.0V A08 ETOTL Total Error — ±0.8 ±3 LSb VREF  3.0V A20 VREF Reference Voltage Range (VREFH – VREFL) 2 — VDD V A21 VREFH Reference Voltage High VDD/2 — VDD + 0.3 V A22 VREFL Reference Voltage Low VSS – 0.3V — VDD/2 V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of Analog Voltage Source — — 3 k Note: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. FIGURE 27-23: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 A/D CLK 130 132 A/D DATA ADRES 9 8 7 ... ... OLD_DATA 2 1 0 NEW_DATA ADIF DONE GO SAMPLE SAMPLING STOPPED Note 1: 2: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. This is a minimal RC delay (0.5TAD), which also disconnects the holding capacitor from the analog input.  2010-2021 Microchip Technology Inc. DS40001412H-page 451 PIC18(L)F2X/4XK22 TABLE 27-22: A/D CONVERSION REQUIREMENTS PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature Tested at +25°C Param. Symbol No. 130 TAD Characteristic A/D Clock Period Min Typ Max Units 1 — 25 s -40C to +85C 1 — 4 s +85C to +125C 131 TCNV Conversion Time (not including acquisition time) (Note 1) 11 — 11 TAD 132 TACQ Acquisition Time (Note 2) 1.4 — — s 135 TSWC Switching Time from Convert  Sample — — (Note 3) 136 TDIS Discharge Time 1 — 1 Note 1: 2: 3: Conditions VDD = 3V, Rs = 50 TCY ADRES register may be read on the following TCY cycle. The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50 . On the following cycle of the device clock. DS40001412H-page 452  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 28.0 Note: DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g. outside specified power supply range) and therefore, outside the warranted range.  2010-2021 Microchip Technology Inc. DS40001412H-page 453 PIC18(L)F2X/4XK22 FIGURE 28-1: PIC18LF2X/4XK22 BASE IPD 10 Max. 85°C IPD (µA) 1 0.1 Typ. 60°C Typ. 25°C 0.01 Limited Accuracy 0.001 1.8 2.1 FIGURE 28-2: 2.4 2.7 VDD (V) 3 3.3 3.6 PIC18F2X/4XK22 BASE IPD 40 35 Max. 85°C ΔIPD (µA) 30 25 20 15 Typ. 60°C Typ. 25°C 10 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) DS40001412H-page 454  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-3: PIC18LF2X/4XK22 DELTA IPD WATCHDOG TIMER (WDT) 3.0 Max. 2.5 ΔIPD (µA) 2.0 1.5 1.0 Typ. 0.5 0.0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-4: PIC18F2X/4XK22 DELTA IPD WATCHDOG TIMER (WDT) 6 Max. 5 ΔIPD (µA) 4 3 2 1 Typical 0 2.3 2.7 3.1  2010-2021 Microchip Technology Inc. 3.5 3.9 VDD (V) 4.3 4.7 5.1 5.5 DS40001412H-page 455 PIC18(L)F2X/4XK22 FIGURE 28-5: PIC18LF2X/4XK22 DELTA IPD BROWN-OUT RESET (BOR) 16 15 Max. 85°C 14 13 ΔIPD (µA) 12 11 10 9 Typical 8 7 6 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-6: PIC18F2X/4XK22 DELTA IPD BROWN-OUT RESET (BOR) 17 Max. 85°C 15 ΔIPD (µA) 13 11 9 7 5 Typical 3 2.3 2.7 DS40001412H-page 456 3.1 3.5 3.9 VDD (V) 4.3 4.7 5.1 5.5  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-7: PIC18LF2X/4XK22 DELTA IPD HIGH/LOW-VOLTAGE DETECT (HLVD) 20 18 16 Max. ΔIPD (µA) 14 12 10 8 Typical 6 4 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-8: PIC18F2X/4XK22 DELTA IPD HIGH/LOW-VOLTAGE DETECT (HLVD) 16 Max. 14 12 ΔIPD (µA) 10 8 6 4 Typical 2 0 2.3 2.7 3.1  2010-2021 Microchip Technology Inc. 3.5 3.9 VDD (V) 4.3 4.7 5.1 5.5 DS40001412H-page 457 PIC18(L)F2X/4XK22 FIGURE 28-9: PIC18LF2X/4XK22 DELTA IPD SECONDARY OSCILLATOR 4.5 4.0 Max. 85°C 3.5 ΔIPD (µA) 3.0 2.5 2.0 1.5 Typ. 60°C 1.0 Typ. 25°C 0.5 0.0 1.8 2.1 2.4 2.7 3 3.6 3.3 VDD (V) FIGURE 28-10: PIC18F2X/4XK22 DELTA IPD SECONDARY OSCILLATOR 6 5 Max. 85°C ΔIPD (µA) 4 3 2 1 Typical 0 2.3 2.7 DS40001412H-page 458 3.1 3.5 3.9 VDD (V) 4.3 4.7 5.1 5.5  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-11: PIC18LF2X/4XK22 DELTA IPD COMPARATOR LOW-POWER MODE 20 18 Max. 16 ΔIPD (µA) 14 12 10 8 Typical 6 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-12: PIC18F2X/4XK22 DELTA IPD COMPARATOR LOW-POWER MODE 40 35 30 ΔIPD (µA) 25 20 Max. 15 10 Typical 5 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 459 PIC18(L)F2X/4XK22 FIGURE 28-13: PIC18LF2X/4XK22 DELTA IPD COMPARATOR HIGH-POWER MODE 120 Max. 100 ΔIPD (µA) 80 60 Typ. 40 20 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-14: PIC18F2X/4XK22 DELTA IPD COMPARATOR HIGH-POWER MODE 120 Max. 100 ΔIPD (µA) 80 60 40 Typical 20 0 2.3 DS40001412H-page 460 2.7 3.1 3.5 3.9 VDD (V) 4.3 4.7 5.1 5.5  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-15: PIC18LF2X/4XK22 DELTA IPD DAC 50 45 40 Max. ΔIPD (µA) 35 30 25 20 Typical 15 10 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-16: PIC18F2X/4XK22 DELTA IPD DAC 70 60 Max. 50 ΔIPD (µA) 40 30 Typical 20 10 0 2.3 2.7 3.1  2010-2021 Microchip Technology Inc. 3.5 3.9 VDD (V) 4.3 4.7 5.1 5.5 DS40001412H-page 461 PIC18(L)F2X/4XK22 FIGURE 28-17: PIC18LF2X/4XK22 DELTA IPD FVR 30 28 26 Max. 24 ΔIPD (µA) 22 20 18 Typ. 60°C 16 Typ. 25°C 14 12 10 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-18: PIC18F2X/4XK22 DELTA IPD FVR 120 Max. 100 ΔIPD (µA) 80 Typical 60 40 20 0 2.3 2.7 3.1 3.5 3.9 VDD (V) 4.3 4.7 5.1 5.5 Note 1: On the PIC18F2X/4XK22, enabling the FVR results in significantly more Sleep current when the part enters Voltage Regulation mode at VDD ~ 3.2V. DS40001412H-page 462  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-19: PIC18(L)F2X/4XK22 DELTA IDD A/D CONVERTOR1 500 450 Max. 400 350 ΔIDD (µA) 300 250 Typical 200 150 100 50 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) Note 1: A/D converter differential currents apply only in Run mode. In Sleep or Idle mode, both the ADC and the FRC turn off as soon as conversion (if any) is complete.  2010-2021 Microchip Technology Inc. DS40001412H-page 463 PIC18(L)F2X/4XK22 FIGURE 28-20: PIC18LF2X/4XK22 TYPICAL IDD: RC_RUN LF-INTOSC 31 kHz 14 12 125°C IDD (µA) 10 25°C 8 -40°C 85°C 6 4 2 0 1.8 FIGURE 28-21: 2.1 2.4 2.7 VDD (V) 3 3.3 3.6 PIC18LF2X/4XK22 MAXIMUM IDD: RC_RUN LF-INTOSC 31 kHz 55 45 125°C IDD (µA) 35 85°C 25 25°C -40°C 15 5 1.8 DS40001412H-page 464 2.1 2.4 2.7 VDD (V) 3 3.3 3.6  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-22: PIC18F2X/4XK22 TYPICAL IDD: RC_RUN LF-INTOSC 31 kHz 28 26 24 125°C 22 IDD (µA) 85°C 25°C 20 -40°C 18 16 14 12 10 2.3 FIGURE 28-23: 2.7 3.1 3.5 3.9 VDD (V) 4.3 4.7 5.1 5.5 PIC18F2X/4XK22 MAXIMUM IDD: RC_RUN LF-INTOSC 31 kHz 85 75 125°C 65 -40°C to +85°C IDD (µA) 55 45 35 25 15 5 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 465 PIC18(L)F2X/4XK22 FIGURE 28-24: PIC18LF2X/4XK22 IDD: RC_RUN MF-INTOSC 500 kHz 0.40 0.35 Max 0.30 IDD (mA) 0.25 0.20 Typical 0.15 0.10 0.05 0.00 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-25: PIC18F2X/4XK22 IDD: RC_RUN MF-INTOSC 500 kHz 0.4 0.35 Max. 0.3 IDD (mA) 0.25 Typical 0.2 0.15 0.1 0.05 0 2.3 DS40001412H-page 466 2.7 3.1 3.5 3.9 VDD (V) 4.3 4.7 5.1 5.5  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-26: PIC18LF2X/4XK22 TYPICAL IDD: RC_RUN HF-INTOSC 3.50 3.00 2.50 IDD (mA) 16 MHz 2.00 1.50 8 MHz 1.00 4 MHz 2 MHz 1 MHz 0.50 0.00 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-27: PIC18LF2X/4XK22 MAXIMUM IDD: RC_RUN HF-INTOSC 4.5 4.0 3.5 16 MHz IDD (mA) 3.0 2.5 2.0 8 MHz 1.5 4 MHz 1.0 2 MHz 1 MHz 0.5 0.0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 467 PIC18(L)F2X/4XK22 FIGURE 28-28: PIC18F2X/4XK22 TYPICAL IDD: RC_RUN HF-INTOSC 3 2.5 16 MHz IDD (mA) 2 1.5 8 MHz 1 4 MHz 0.5 2 MHz 1 MHz 0 2.3 2.7 FIGURE 28-29: 3.1 3.5 3.9 VDD (V) 4.3 4.7 5.1 5.5 PIC18F2X/4XK22 MAXIMUM IDD: RC_RUN HF-INTOSC 4 3.5 16 MHz 3 IDD (mA) 2.5 2 8 MHz 1.5 4 MHZ 1 2 MHz 1 MHz 0.5 0 2.3 DS40001412H-page 468 2.7 3.1 3.5 3.9 VDD (V) 4.3 4.7 5.1 5.5  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-30: PIC18LF2X/4XK22 TYPICAL IDD: RC_RUN HF-INTOSC with PLL 9 8 7 64 MHz IDD (mA) 6 5 4 32 MHz 3 16 MHz 2 1 0 1.8 2.1 2.4 2.7 3 3.6 3.3 VDD (V) FIGURE 28-31: PIC18LF2X/4XK22 MAXIMUM IDD: RC_RUN HF-INTOSC with PLL 12 10 64 MHz IDD (mA) 8 6 32 MHz 4 16 MHz 2 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 469 PIC18(L)F2X/4XK22 FIGURE 28-32: PIC18F2X/4XK22 TYPICAL IDD: RC_RUN HF-INTOSC with PLL 8 7 64 MHz 6 IDD (mA) 5 4 32 MHz 3 16 MHz 2 1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-33: PIC18F2X/4XK22 MAXIMUM IDD: RC_RUN HF-INTOSC with PLL 12 10 64 MHz IDD (mA) 8 6 32 MHz 4 16 MHz 2 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) DS40001412H-page 470  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-34: PIC18LF2X/4XK22 TYPICAL IDD: RC_IDLE LF-INTOSC 31 kHz 4 3.5 125°C 3 IDD (µA) 2.5 2 1.5 85°C 25°C -40°C 1 0.5 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD(V) FIGURE 28-35: PIC18LF2X/4XK22 MAXIMUM IDD: RC_IDLE LF-INTOSC 31 kHz 35 30 125°C IDD (µA) 25 20 15 85°C 10 25°C 5 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 471 PIC18(L)F2X/4XK22 FIGURE 28-36: PIC18F2X/4XK22 TYPICAL IDD: RC_IDLE LF-INTOSC 31 kHz 22 21 -40°C 20 19 IDD (µA) 18 17 125°C 16 15 85°C 25°C 14 13 12 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-37: PIC18F2X/4XK22 MAXIMUM IDD: RC_IDLE LF-INTOSC 31 kHz 70 125°C 60 IDD (µA) 50 -40°C to-40C +85°C 40 30 20 10 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) DS40001412H-page 472  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-38: PIC18LF2X/4XK22 IDD: RC_IDLE MF-INTOSC 500 kHz 0.3 Max. 0.25 IDD (mA) 0.2 0.15 Typical 0.1 0.05 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-39: PIC18F2X/4XK22 IDD: RC_IDLE MF-INTOSC 500 kHz 0.35 Max. 0.3 0.25 IDD (mA) 0.2 Typical 0.15 0.1 0.05 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 473 PIC18(L)F2X/4XK22 FIGURE 28-40: PIC18LF2X/4XK22 TYPICAL IDD: RC_IDLE HF-INTOSC 1.2 IDD (mA) 1 0.8 16 MHz 0.6 8 MHz 4 MHz 0.4 2 MHz 1 MHz 0.2 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 28-41: PIC18LF2X/4XK22 MAXIMUM IDD: RC_IDLE HF-INTOSC 1.6 1.4 1.2 16 MHz IDD (mA) 1 0.8 8 MHz 0.6 4 MHz 1 MHz 0.4 0.2 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) DS40001412H-page 474  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-42: PIC18F2X/4XK22 TYPICAL IDD: RC_IDLE HF-INTOSC 1 16 MHz 0.9 IDD (mA) 0.8 0.7 8 MHz 0.6 4 MHz 0.5 2 MHz 1 MHz 0.4 0.3 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-43: PIC18F2X/4XK22 MAXIMUM IDD: RC_IDLE HF-INTOSC 1.4 1.2 16 MHz 1 IDD (mA) 8 MHz 0.8 4 MHz 0.6 1 MHz 0.4 0.2 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 475 PIC18(L)F2X/4XK22 FIGURE 28-44: PIC18LF2X/4XK22 TYPICAL IDD: RC_IDLE HF-INTOSC with PLL 3.5 3 64 MHz 2.5 IDD (mA) 2 1.5 32 MHz 1 16 MHz 0.5 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-45: PIC18LF2X/4XK22 MAXIMUM IDD: RC_IDLE HF-INTOSC with PLL 5 4.5 4 64 MHz IDD(mA) 3.5 3 2.5 2 32 MHz 1.5 16 MHz 1 0.5 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412H-page 476  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-46: PIC18F2X/4XK22 TYPICAL IDD: RC_IDLE HF-INTOSC with PLL 3 64 MHz 2.5 IDD (mA) 2 32 MHz 1.5 1 16 MHz 0.5 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-47: PIC18F2X/4XK22 MAXIMUM IDD: RC_IDLE HF-INTOSC with PLL 5 64 MHz 4.5 4 IDD (mA) 3.5 3 2.5 2 32 MHz 1.5 16 MHz 1 0.5 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 477 PIC18(L)F2X/4XK22 FIGURE 28-48: PIC18LF2X/4XK22 TYPICAL IDD: PRI_RUN EC MEDIUM POWER 3.0 2.5 16 MHz IDD (mA) 2.0 1.5 10 MHz 1.0 4 MHz 0.5 1 MHz 0.0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-49: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_RUN EC MEDIUM POWER 4.0 3.5 3.0 16 MHz IDD (mA) 2.5 2.0 10 MHz 1.5 1.0 4 MHz 0.5 1 MHz 0.0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412H-page 478  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-50: PIC18F2X/4XK22 TYPICAL IDD: PRI_RUN EC MEDIUM POWER 2.5 16 MHz 2 1.5 IDD (mA) 10 MHz 1 4 MHz 0.5 1 MHz 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-51: PIC18F2X/4XK22 MAXIMUM IDD: PRI_RUN EC MEDIUM POWER 3.5 3 16 MHz IDD (mA) 2.5 2 10 MHz 1.5 1 4 MHz 0.5 1 MHz 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 479 PIC18(L)F2X/4XK22 FIGURE 28-52: PIC18LF2X/4XK22 TYPICAL IDD: PRI_RUN EC HIGH POWER 12 10 IDD (mA) 8 64 MHz 6 40 MHz 4 20 MHz 16 MHz 10 MHz 2 4 MHz 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-53: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_RUN EC HIGH POWER 16 14 12 64 MHz IDD (mA) 10 8 40 MHz 6 4 20 MHz 2 16 MHz 10 MHz 4 MHz 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412H-page 480  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-54: PIC18F2X/4XK22 TYPICAL IDD: PRI_RUN EC HIGH POWER 9 64 MHz 8 7 6 IDD (mA) 40 MHz 5 4 3 20 MHz 16 MHz 2 10 MHz 1 4 MHz 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-55: PIC18F2X/4XK22 MAXIMUM IDD: PRI_RUN EC HIGH POWER 14 12 64 MHz IDD (mA) 10 8 40 MHz 6 20 MHz 4 16 MHz 10 MHz 2 4 MHz 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 481 PIC18(L)F2X/4XK22 FIGURE 28-56: PIC18LF2X/4XK22 TYPICAL IDD: PRI_RUN EC with PLL 10 9 8 7 64 MHz IDD (mA) 6 5 4 32 MHz 3 2 16 MHz 1 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-57: PIC18LF2X/4XK22 MAXIMIUM IDD: PRI_RUN EC with PLL 14 12 10 IDD (mA) 64 MHz 8 6 32 MHz 4 16 MHz 2 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412H-page 482  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-58: PIC18F2X/4XK22 TYPICAL IDD: PRI_RUN EC with PLL 8 7 64 MHz 6 IDD (mA) 5 4 32 MHz 3 16 MHz 2 1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-59: PIC18F2X/4XK22 MAXIMUM IDD: PRI_RUN EC with PLL 12 10 64 MHz IDD (mA) 8 6 32 MHz 4 16 MHz 2 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 483 PIC18(L)F2X/4XK22 FIGURE 28-60: PIC18LF2X/4XK22 TYPICAL IDD: PRI_IDLE EC MEDIUM POWER 0.9 0.8 0.7 IDD (mA) 0.6 16 MHz 0.5 0.4 10 MHz 0.3 0.2 4 MHz 0.1 1 MHz 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-61: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_IDLE EC MEDIUM POWER 1.2 1 0.8 IDD (mA) 16 MHz 0.6 10 MHz 0.4 0.2 4 MHz 1 MHz 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412H-page 484  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-62: PIC18F2X/4XK22 TYPICAL IDD: PRI_IDLE EC MEDIUM POWER 0.8 16 MHz 0.7 0.6 IDD (mA) 0.5 10 MHz 0.4 0.3 4 MHz 0.2 1 MHz 0.1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-63: PIC18F2X/4XK22 MAXIMUM IDD: PRI_IDLE EC MEDIUM POWER 1.2 1 16 MHz IDD (mA) 0.8 10 MHz 0.6 0.4 4 MHz 0.2 1 MHz 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 485 PIC18(L)F2X/4XK22 FIGURE 28-64: PIC18LF2X/4XK22 TYPICAL IDD: PRI_IDLE EC HIGH POWER 3.5 3 2.5 IDD (mA) 64 MHz 2 1.5 40 MHz 1 20 MHz 16 MHz 0.5 10 MHz 4 MHz 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-65: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_IDLE EC HIGH POWER 5 4.5 4 IDD (mA) 3.5 64 MHz 3 2.5 2 40 MHz 1.5 1 20 MHz 0.5 16 MHz 10 MHz 4 MHz 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412H-page 486  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-66: PIC18F2X/4XK22 TYPICAL IDD: PRI_IDLE EC HIGH POWER 3 64 MHz 2.5 IDD (mA) 2 40 MHz 1.5 1 20 MHz 16 MHz 0.5 10 MHz 4 MHz 0 2.3 FIGURE 28-67: 2.7 3.1 3.5 3.9 VDD (V) 4.3 4.7 5.1 5.5 PIC18F2X/4XK22 MAXIMUM IDD: PRI_IDLE EC HIGH POWER 4 3.5 64 MHz 3 IDD (mA) 2.5 40 MHz 2 1.5 20 MHz 1 16 MHz 10 MHz 0.5 4 MHz 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 487 PIC18(L)F2X/4XK22 FIGURE 28-68: PIC18LF2X/4XK22 TYPICAL IDD: PRI_IDLE EC with PLL 3.5 3 2.5 IDD (mA) 64 MHz 2 1.5 32 MHz 1 16 MHz 0.5 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-69: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_IDLE EC with PLL 4.5 4 3.5 64 MHz IDD (mA) 3 2.5 2 1.5 32 MHz 1 16 MHz 0.5 0 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412H-page 488  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-70: PIC18F2X/4XK22 TYPICAL IDD: PRI_IDLE EC with PLL 3 2.5 64 MHz IDD (mA) 2 1.5 32 MHz 1 16 MHz 0.5 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.1 5.5 VDD (V) FIGURE 28-71: PIC18F2X/4XK22 MAXIMUM IDD: PRI_IDLE EC with PLL 4 3.5 64 MHz 3 IDD (mA) 2.5 2 1.5 32 MHz 1 16 MHz 0.5 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 489 PIC18(L)F2X/4XK22 FIGURE 28-72: PIC18LF2X/4XK22 TYPICAL IDD: SEC_RUN 32.768 kHz IDD (µA) 9 8 125°C 7 85°C 60°C 25°C -40°C 6 5 4 3 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-73: PIC18LF2X/4XK22 MAXIMUM IDD: SEC_RUN 32.768 kHz 50 45 40 85°C IDD (µA) 35 25°C 30 -40°C 25 20 15 10 5 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) DS40001412H-page 490  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-74: PIC18F2X/4XK22 TYPICAL IDD: SEC_RUN 32.768 kHz 22 21 85°C 20 25°C IDD (µA) 19 -40°C 18 17 16 15 14 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-75: PIC18F2X/4XK22 MAXIMUM IDD: SEC_RUN 32.768 kHz 85 75 125°C 65 -40°C to +85°C IDD (µA) 55 45 35 25 15 5 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 491 PIC18(L)F2X/4XK22 FIGURE 28-76: PIC18LF2X/4XK22 TYPICAL IDD: SEC_IDLE 32.768 kHz 2.3 2.1 1.9 85°C 1.7 IDD (µA) 60°C 1.5 25°C -40°C 1.3 1.1 0.9 0.7 0.5 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) FIGURE 28-77: PIC18LF2X/4XK22 MAXIMUM IDD: SEC_IDLE 32.768 kHz 25 20 85°C 25°C IDD (µA) 15 -40°C 10 5 0 1.8 DS40001412H-page 492 2 2.2 2.4 2.6 2.8 VDD (V) 3 3.2 3.4 3.6  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-78: PIC18F2X/4XK22 TYPICAL IDD: SEC_IDLE 32.768 kHz 18 17 16 85°C IDD (µA) 15 25°C 14 -40°C 13 12 11 10 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) FIGURE 28-79: PIC18F2X/4XK22 MAXIMUM IDD: SEC_IDLE 32.768 kHz 63 125°C 58 53 IDD (µA) 48 43 -40°C to +85°C 38 33 28 23 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 493 PIC18(L)F2X/4XK22 FIGURE 28-80: PIC18(L)F2X/4XK22 TTL BUFFER INPUT LOW VOLTAGE 1.5 1.3 25°C 1.1 VIL (V) -40°C 0.9 85°C 125°C 0.7 Max. 0.5 0.3 0.1 1.8 2.2 FIGURE 28-81: 2.6 3 3.4 3.8 VDD (V) 4.2 4.6 5 5.4 PIC18(L)F2X/4XK22 SCHMITT TRIGGER BUFFER INPUT LOW VOLTAGE 2.0 1.8 1.6 -40°C 25°C 1.4 VIL (V) 1.2 85°C 1.0 125°C Max. 0.8 0.6 0.4 0.2 1.8 DS40001412H-page 494 2.3 2.8 3.3 3.8 VDD (V) 4.3 4.8 5.3  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-82: PIC18(L)F2X/4XK22 TTL BUFFER INPUT HIGH VOLTAGE 2.1 1.9 Min. 1.7 VIH (V) 1.5 -40°C 1.3 25°C 85°C 1.1 125°C 0.9 0.7 0.5 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5 5.4 VDD (V) FIGURE 28-83: PIC18(L)F2X/4XK22 SCHMITT TRIGGER BUFFER INPUT HIGH VOLTAGE 4.5 4.0 3.5 VIH (V) Min. 3.0 2.5 2.0 25°C -40°C 1.5 125°C 85°C 1.0 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5 5.4 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 495 PIC18(L)F2X/4XK22 FIGURE 28-84: PIC18(L)F2X/4XK22 PIN INPUT LEAKAGE 1.00E-05 1.00E-06 Max. Input Leakage (A) 1.00E-07 1.00E-08 Typical 1.00E-09 1.00E-10 1.00E-11 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 Temperature (°C) DS40001412H-page 496  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-85: PIC18(L)F2X/4XK22 OUTPUT LOW VOLTAGE 1.6 1.4 1.2 Max. 2V 1 Typ. 2V Typ. 3V VOL (V) Max. 3V 0.8 Max. 5V Typ. 5V 0.6 0.4 0.2 0 0 5 10 15 20 25 30 IOL (mA) FIGURE 28-86: PIC18(L)F2X/4XK22 OUTPUT HIGH VOLTAGE 5 4 Typ. 5V VOH(V) 3 Min. 5V 2 Min. 3V 1 Typ. 3V Min. 2V Typ. 2V 0 0 5 10 15 20 25 IOH (mA)  2010-2021 Microchip Technology Inc. DS40001412H-page 497 PIC18(L)F2X/4XK22 FIGURE 28-87: PIC18(L)F2X/4XK22 COMPARATOR OFFSET VOLTAGE, NORMAL-POWER MODE; VDD=5.5V 60 50 Abs. Offset (mV) 40 6 sigma 30 20 Typical 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VREF (V) FIGURE 28-88: PIC18(L)F2X/4XK22 COMPARATOR OFFSET VOLTAGE, NORMAL-POWER MODE; VDD=3.0V 45 40 35 Abs. Offset (mV) 30 6 sigma 25 20 15 10 Typical 5 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF (V) DS40001412H-page 498  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-89: PIC18LF2X/4XK22 COMPARATOR OFFSET VOLTAGE, NORMAL-POWER MODE; VDD=1.8V 35 30 25 Abs. Offset (mV) 6 sigma 20 15 10 5 Typical 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VREF (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 499 PIC18(L)F2X/4XK22 FIGURE 28-90: PIC18(L)F2X/4XK22 COMPARATOR OFFSET VOLTAGE, LOW-POWER MODE; VDD=5.5V 90 80 70 Abs. Offset (mV) 60 50 6 sigma 40 30 20 Typical 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VREF (V) FIGURE 28-91: PIC18(L)F2X/4XK22 COMPARATOR OFFSET VOLTAGE, LOW-POWER MODE; VDD=3.0V 80 70 60 Abs. Offset (mV) 50 40 6 sigma 30 20 10 Typical 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF (V) DS40001412H-page 500  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-92: PIC18LF2X/4XK22 COMPARATOR OFFSET VOLTAGE, LOW-POWER MODE; VDD=1.8V 60 50 Abs. Offset (mV) 40 6 sigma 30 20 10 Typical 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VREF (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 501 PIC18(L)F2X/4XK22 FIGURE 28-93: PIC18(L)F2X/4XK22 TYPICAL DAC ABS. ERROR VDD = 2.5V, 3.0V, & 5.5V 1.7 1.6 1.5 1.4 Minimum VREF Limit 1.3 Absolute Error (LSb) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 Max LSb Limit 0.5 0.4 2.5V 0.3 3.0V 0.2 5.5V 0.1 0.0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VREF (V) DS40001412H-page 502  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-94: PIC18(L)F2X/4XK22 TYPICAL FIXED VOLTAGE REFERENCE 1X OUTPUT 1.035 1.030 5.5V FVR x1 (V) 1.025 2.5V 1.020 1.015 1.010 1.005 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 28-95: PIC18(L)F2X/4XK22 TYPICAL FIXED VOLTAGE REFERENCE 1X OUTPUT 1.10 Max. 1.08 FVR x1 (V) 1.06 1.04 - 40°C 25°C 1.02 85°C 125°C 1.00 0.98 Min. 0.96 2.5 3 3.5 4 4.5 5 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 503 PIC18(L)F2X/4XK22 FIGURE 28-96: PIC18(L)F2X/4XK22 TYPICAL FIXED VOLTAGE REFERENCE 2X OUTPUT 2.065 2.055 5.5V FVR x2 (V) 2.045 2.5V 2.035 2.025 2.015 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 28-97: PIC18(L)F2X/4XK22 TYPICAL FIXED VOLTAGE REFERENCE 2X OUTPUT 2.20 Max. 2.15 FVR x2 (V) 2.10 -40°C 2.05 25°C 85°C 125°C 2.00 1.95 Min. 1.90 2.5 3 3.5 4 4.5 5 5.5 VDD (V) DS40001412H-page 504  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-98: PIC18F2X/4XK22 TYPICAL FIXED VOLTAGE REFERENCE 4X OUTPUT 4.13 4.11 FVR x4 (V) 5.5V 4.09 4.5V 4.07 4.05 4.03 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 28-99: PIC18F2X/4XK22 TYPICAL FIXED VOLTAGE REFERENCE 4X OUTPUT 4.40 4.35 Max. 4.30 4.25 FVR x4 (V) 4.20 4.15 - 40°C 4.10 25°C 85°C 4.05 125°C 4.00 3.95 3.90 Min. 3.85 4.5 4.7 4.9 5.1 5.3 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 505 PIC18(L)F2X/4XK22 FIGURE 28-100: PIC18(L)F2X/4XK22 HF-INTOSC FREQUENCY vs. TEMPERATURE at 16 MHZ MIN / MAX: ± 2%, T = 0°C to +70°C +2% / -3%, T = +70°C to +85°C ± 5%, T = -40°C to 0°C and +85°C to +125°C 16.80 16.64 16.48 Max. 16.32 Freq (MHz) 16.16 16.00 15.84 Typical Min. 15.68 15.52 15.36 15.20 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temp (°C) DS40001412H-page 506  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 FIGURE 28-101: PIC18LF2X/4XK22 TYPICAL LF-INTOSC FREQUENCY vs. VDD Min/Max = 31.25 kHz ± 15%, T = -40°C to +85°C 32.5 32.0 25°C 31.5 -40°C Frequency (kHz) 85°C 31.0 30.5 125°C 30.0 29.5 29.0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 28-102: PIC18F2X/4XK22 TYPICAL LF-INTOSC FREQUENCY vs. VDD Min/Max = 31.25 kHz ± 15%, T = -40°C to +85°C 32.5 32.0 Frequency (kHz) 31.5 25°C -40°C 31.0 30.5 85°C 30.0 29.5 125°C 29.0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V)  2010-2021 Microchip Technology Inc. DS40001412H-page 507 PIC18(L)F2X/4XK22 FIGURE 28-103: PIC18LF2X/4XK22 TYPICAL LF-INTOSC FREQUENCY vs. TEMPERATURE Min/Max = 31.25 kHz ± 15%, T = -40°C to +85°C 32.5 1.8V 32.0 31.5 Frequency (kHz) 3V 31.0 3.6V 30.5 30.0 29.5 29.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 28-104: PIC18F2X/4XK22 TYPICAL LF-INTOSC FREQUENCY vs. TEMPERATURE Min/Max = 31.25 kHz ± 15%, T = -40°C to +85°C 32.5 32.0 2.5V Frequency (kHz) 31.5 3.0V 5.5V 31.0 30.5 30.0 29.5 29.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) DS40001412H-page 508  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 28-Lead SPDIP (.300”) Example PIC18F25K22 -E/SP e3 0810017 28-Lead SOIC (7.50 mm) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX Example PIC18F25K22 -E/SO e3 0810017 YYWWNNN 28-Lead SSOP (5.30 mm) Example PIC18F25K22 -E/SS e3 0810017 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information or Microchip part number Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010-2021 Microchip Technology Inc. DS40001412H-page 509 PIC18(L)F2X/4XK22 Package Marking Information (Continued) 28-Lead QFN (6x6 mm) PIN 1 Example PIN 1 18F25K22 -E/ML e3 0610017 XXXXXXXX XXXXXXXX YYWWNNN 28-Lead UQFN (4x4x0.5 mm) PIN 1 Example PIN 1 40-Lead PDIP (600 mil) XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: DS40001412H-page 510 PIC18 F23K22 E/MV e 810017 3 Example PIC18F45K22 -E/P e3 0810017 Customer-specific information or Microchip part number Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 Package Marking Information (Continued) 40-Lead UQFN (5x5x0.5 mm) PIN 1 Example PIN 1 PIC18F 45K22 -I/MV e 0810017 3 44-Lead QFN (8x8x0.9 mm) PIN 1 Example PIN 1 XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 44-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: 1845K22 -E/ML e3 0810017 Example 18F45K22 -E/PT e3 0810017 Customer-specific information or Microchip part number Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010-2021 Microchip Technology Inc. DS40001412H-page 511 PIC18(L)F2X/4XK22 29.2 Package Details The following sections give the technical details of the packages.                ! "# 3 &' !&" &4# *!(!!& 4%&  &#& &&255***'  '54 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6&! '! 9'&! 7"')  %! 7,8. 7 7 7: ; < &  & &  = =   ##4 4!!   -  1!& &   = =  "# &  "# >#& .  - --  ##4>#& .  #& 9 * 9#>#& :   *+ 1, - "#   !"#$%&" '  ()"&'"!&) &#*&&&#   +%&, & !& - '! !#.#  &"#' #%!  & "! ! #%!  & "! !! &$#/ !#  '! #&   .0 1,2 1!'!   &$& "! **& "&&  !       * ,1 DS40001412H-page 512  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2021 Microchip Technology Inc. DS40001412H-page 513 PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001412H-page 514  2010-2021 Microchip Technology Inc. PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2021 Microchip Technology Inc. DS40001412H-page 515 PIC18(L)F2X/4XK22    $%   &    '(    &! "# 3 &' !&" &4# *!(!!& 4%&  &#& &&255***'  '54 D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 6&! '! 9'&! 7"')  %! 99. . 7 7 7: ; < &  :  8&  = ?1, =   ##4 4!!  ?  #& .  #& .  = ?  ##4>#& .