PIC18F47K42-I/PT

PIC18(L)F2X/4X/5XK42 Highly Integrated 8-Bit PIC® Microcontrollers in 28- to 48- Pins Description The PIC18(L)F2X/4X/5XK42 microcontroller family is available in 28/40/44/48-pin devices. This family features a 12-bit ADC with Computation (ADC2) automating Capacitive Voltage Divider (CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and threshold comparison. Additionally, Vectored Interrupt Controller with fixed latency for handling interrupts, System Bus Arbiter, Direct Memory Access capabilities, UART with support for Asynchronous, DMX, DALI and LIN protocols, SPI, I2C, memory features like Memory Access Partition (MAP) to support customers in data protection and bootloader applications, Device Information Area (DIA) which stores factory calibration values to help improve temperature sensor accuracy. Core Features Operating Characteristics • C Compiler Optimized RISC Architecture • Operating Speed: - Up to 64 MHz clock input - 62.5 ns minimum instruction cycle • Two Direct Memory Access (DMA) Controllers: - Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR spaces - User programmable source and destination sizes - Hardware and software triggered data transfers • Vectored Interrupt Capability: - Selectable high/low priority - Fixed Interrupt latency - Programmable vector table base address • 31-Level Deep Hardware Stack • Low-Current Power-on Reset (POR) • Configurable Power-up Timer (PWRTE) • Brown-Out Reset (BOR) • Low-Power BOR (LPBOR) Option • Windowed Watchdog Timer (WWDT): - Variable prescaler selection - Variable window size selection - Configurable in hardware or software • Programmable Code Protection: - Configurable Boot and App region sizes • Operating Voltage Range: - 1.8V to 3.6V (PIC18LF2X/4X/5XK42) - 2.3V to 5.5V (PIC18F2X/4X/5XK42) • Temperature Range: - Industrial: -40°C to 85°C - Extended: -40°C to 125°C Memory • • • • Up to 128 KB Flash Program Memory Up to 8 KB Data SRAM Memory Up to 1 KB Data EEPROM Memory Access Partition (MAP): - Bootloader write-protect - Configurable partition • Device Information Area (DIA) Stores: - Temp sensor factory calibrated data - Fixed Voltage Reference - Device ID  2016 Microchip Technology Inc. Power-Saving Functionality • DOZE mode: Ability to run CPU core slower than the system clock • IDLE mode: Ability to halt CPU core while internal peripherals continue operating • Sleep mode: Lowest power consumption • Peripheral Module Disable (PMD): - Ability to disable peripherals to minimize power consumption eXtreme Low-Power (XLP) Features • • • • Sleep mode: 50 nA @ 1.8V, typical Watchdog Timer: 500 nA @ 1.8V, typical Secondary Oscillator: 500 nA @ 32 kHz Operating Current: - 8 uA @ 32 kHz, 1.8V, typical - 32 uA/MHz @ 1.8V, typical Digital Peripherals • Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT) • Four 16-Bit Timers (TMR0/1/3/5) • Four Configurable Logic Cell (CLC): - Integrated combinational and sequential logic • Three Complementary Waveform Generators (CWGs): - Rising and falling edge dead-band control - Full-bridge, half-bridge, 1-channel drive - Multiple signal sources - Programmable dead band - Fault-shutdown input • Four 16-Bit Capture/Compare/16-Bit PWM (CCP) modules • Four 10-bit Pulse Width Modulators (PWMs) Advance Information DS40001861B-page 1 PIC18(L)F2X/4X/5XK42 Digital Peripherals (Continued) • Numerically Controlled Oscillator (NCO): - Generates true linear frequency control and increased frequency resolution - Input Clock: 0 Hz < fNCO < 64 MHz - Resolution: fNCO/220 • DSM: Data Signal Modulator: - Multiplex two carrier clocks, with glitch prevention feature - Multiple sources for each carrier • Programmable CRC with Memory Scan: - Reliable data/program memory monitoring for fail-safe operation (e.g., Class B) - Calculate CRC over any portion of Flash • Two UART Modules: - Asynchronous UART, RS-232, RS-485 compatible. - One of the UART modules supports LIN master and slave, DMX mode, DALI gear and device protocols - Automatic and user timed BREAK period generation - DMA compatible - Automatic checksums - Programmable 1, 1.5, and 2 Stop bits - Wake-up on BREAK reception • One SPI module: - Configurable length bytes - Arbitrary length data packets - Receive-without-transmit option - Transmit-without-receive option - Transfer byte counter - Separate transmit and receive buffers with 2-byte FIFO and DMA capabilities • Two I2C modules, SMBus, PMBus™ compatible: - Dedicated address, transmit and receive buffers - Bus collision detection with arbitration - Bus time-out detection and handling - I2C, SMBus 2.0 and SMBus 3.0, and 1.8V input level selections - Multi-Master mode, including self-addressing • Device I/O Port Features: - 25 I/O pins (PIC18(L)F24/25/26/27K42) - 36 I/O pins (PIC18(L)F45/46/47K42) - 44 I/O pins (PIC18(L)F55/56/57K42) - One input-only pin - Individually programmable I/O direction, controlled current, open-drain, slew rate, weak pull-up control - Interrupt-on-change - Three external interrupt pins • Peripheral Pin Select (PPS): - Enables pin mapping of digital I/O DS40001861B-page 2 • Signal Measurement Timer (SMT): - 24-bit timer/counter with prescaler Analog Peripherals • Analog-to-Digital Converter with Computation (ADC2): - 12-bit with up to 43 external channels - Automated post-processing - Automates math functions on input signals: averaging, filter calculations, oversampling and threshold comparison - Operates in Sleep - Temperature Sensor - Internal connection to ADC - Can be calibrated for improved accuracy - Hardware Capacitive Voltage Divider (CVD): - Automates touch sampling and reduces software size and CPU usage when touch or proximity sensing is required - Adjustable sample and hold capacitor array - Two guard ring output drives • Two Comparators: - Comparator Hysteresis enable - Invert output polarity - Comparator outputs externally accessible • 5-Bit Digital-to-Analog Converter (DAC): - 5-bit resolution, rail-to-rail - Unbuffered I/O pin output - Internal connections to ADCs and comparators • Voltage Reference: - Fixed Voltage Reference with 1.024V, 2.048V and 4.096V output levels - Connection to ADC, Comp and DAC Flexible Oscillator Structure • High-Precision Internal Oscillator: - Selectable frequency range up to 64 MHz - Safe clock switching while running - ±1% at calibration (nominal) • Low-Power Internal 32 kHz Oscillator (LFINTOSC) • External 32 kHz Crystal Oscillator • External Oscillator Block with: - x4 PLL with external sources - Three crystal/resonator modes up to 20 MHz - Three external clock modes up to 20 MHz • Fail-Safe Clock Monitor - Allows for safe shutdown if peripherals clock stops • Oscillator Start-up Timer (OST) - Ensures stability of crystal oscillator sources Advance Information  2016 Microchip Technology Inc. Data EEPROM (B) Data SRAM (bytes) I/OPins 12-bit ADC2 (ch) 5-bit DAC Comparator 8-bit/16-bit Timer Window Watchdog Timer (WWDT) Signal Measurement Timer (SMT) CCP/10-bit PWM CWG NCO CLC Zero-Cross Detect Direct Memory Access (DMA) (channels) Memory Access Partition Vectored Interrupts UART/UART with LIN, DMX, DALI Protocol Support I2C/SPI Peripheral Pin Select Peripheral Module Disable Debug (1) PIC18(L)F24K42 A 16 256 1024 25 24 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 1/1 2/1 Y Y I PIC18(L)F25K42 A 32 256 2048 25 24 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 1/1 2/1 Y Y I PIC18(L)F26K42 B 64 1024 4096 25 24 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 1/1 2/1 Y Y I PIC18(L)F27K42 C 128 1024 8192 25 24 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 1/1 2/1 Y Y I PIC18(L)F45K42 B 32 256 2048 36 35 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 1/1 2/1 Y Y I Device PIC18(L)F46K42 B 64 1024 4096 36 35 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 1/1 2/1 Y Y I PIC18(L)F47K42 C 128 1024 8192 36 35 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 1/1 2/1 Y Y I PIC18(L)F55K42 B 32 1024 2048 44 43 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 1/1 2/1 Y Y I PIC18(L)F56K42 B 64 1024 4096 44 43 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 1/1 2/1 Y Y I PIC18(L)F57K42 C 128 1024 8192 44 43 1 2 3/4 Y Y 4/4 3 1 4 Y 2 Y Y 1/1 2/1 Y Y I Note 1: I – Debugging integrated on chip. Data Sheet Index: DS40001861B-page 3 Note: A: Future Release PIC18(L)F24/44K42 Data Sheet, 28-Pin B: Future Release PIC18(L)F26/45/55/46/56K42 Data Sheet, 48-Pin C: Future Release PIC18(L)F27/47/57K42 Data Sheet, 48-Pin For other small form-factor package availability and marking information, please visit www.microchip.com/packaging or contact your local sales office. PIC18(L)F2X/4X/5XK42 Advance Information Program Flash Memory (KB) PIC18(L)F2X/4X/5XK42 FAMILY TYPES Data Sheet Index  2016 Microchip Technology Inc. TABLE 1: PIC18(L)F2X/4X/5XK42 TABLE 2: PACKAGES (S)PDIP SOIC SSOP UQFN (4x4) QFN (6x6) TQFP QFN (8x8) UQFN (5x5) UQFN (6x6) PIC18(L)F24K42 X X X X X — — — — PIC18(L)F25K42 X X X X X — — — — PIC18(L)F26K42 X X X X — — — — — PIC18(L)F27K42 X X X — X — — — — PIC18(L)F45K42 X — — — — X X X — PIC18(L)F46K42 X — — — — X X X — PIC18(L)F47K42 X — — — — X X X — PIC18(L)F55K42 X — — — — X X — X PIC18(L)F56K42 X — — — — X X — X PIC18(L)F57K42 X — — — — X X — X Device Note: Pin details are subject to change. DS40001861B-page 4 Advance Information  2016 Microchip Technology Inc. PIC18(L)F2X/4X/5XK42 PIN DIAGRAMS 28-PIN SPDIP, SOIC, SSOP FOR PIC18(L)F2XK42 VPP/MCLR/RE3 1 28 RB7/ICSPDAT RA0 2 27 RB6/ICSPCLK RA1 3 RB5 RA2 RA3 RA4 RA5 VSS RA7 RA6 4 26 25 24 23 22 21 20 19 RC0 RC1 RC2 RC3 Note: 13 16 14 15 RC4 6 7 8 9 10 11 12 18 17 See Table 3 for location of all peripheral functions. 28-PIN UQFN (4X4) FOR PIC18(L)F2XK42 28 27 26 25 24 23 22 RA1 RA0 RE3/MCLR/VPP RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 FIGURE 2: RB4 RB3 RB2 RB1 RB0 VDD VSS RC7 RC6 RC5 5 PIC18(L)F2XK42 FIGURE 1: 21 20 19 PIC18(L)F2XK42 18 17 16 15 8 9 10 11 12 13 14 1 2 3 4 5 6 7 RB3 RB2 RB1 RB0 VDD VSS RC7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RA2 RA3 RA4 RA5 VSS RA7 RA6 Note: See Table 3 or the pin allocation tables.  2016 Microchip Technology Inc. Advance Information DS40001861B-page 5 PIC18(L)F2X/4X/5XK42 28-PIN QFN (6X6X0.9 mm) FOR PIC18(L)F2XK42 28 27 26 25 24 23 22 RA1 RA0 RE3/MCLR/VPP RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 FIGURE 3: RB3 RB2 RB1 RB0 VDD VSS RC7 21 20 19 PIC18(L)F2XK42 18 17 16 15 8 9 10 11 12 13 14 1 2 3 4 5 6 7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RA2 RA3 RA4 RA5 VSS RA7 RA6 FIGURE 4: See Table 3 or the pin allocation tables. 40-PIN PDIP FOR PIC18(L)F4XK42 VPP/MCLR/RE3 1 40 RB7/ICSPDAT RA0 RA1 2 39 3 38 RB6/ICSPCLK RB5 RA2 RA3 RA4 RA5 RE0 4 37 5 6 36 RB4 RB3 35 34 33 32 31 30 29 RB2 RB1 RB0 VDD VSS RD7 RD6 28 RD5 RD4 RA7 7 8 9 10 11 12 13 RA6 14 27 RC0 RC1 RC2 RC3 RD0 RD1 15 26 25 24 23 22 21 RE1 RE2 VDD VSS Note: PIC18(L)F4XK42 Note: 16 17 18 19 20 RC7 RC6 RC5 RC4 RD3 RD2 See Table 4 for location of all peripheral functions. DS40001861B-page 6 Advance Information  2016 Microchip Technology Inc. PIC18(L)F2X/4X/5XK42 40-PIN UQFN (5X5X0.5 mm) FOR PIC18(L)F4XK42 31 32 34 33 35 36 37 38 39 1 2 30 3 29 4 28 27 5 PIC18(L)F4XK42 6 26 7 25 8 24 20 19 18 17 16 15 RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 RB3 RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 14 22 21 13 23 10 11 9 12 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 40 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 FIGURE 5: Note: 44-PIN QFN (8X8X0.9 mm) FOR PIC18(L)F5XK42 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 PIC18(L)F5XK42 7 8 9 10 11 RA6 RA7 NC VSS NC VDD RE2 RE1 RE0 RA5 RA4 RB3 NC RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 RC7 RD4 RD5 RD6 RD7 VSS VDD NC RB0 RB1 RB2 44 43 42 41 40 39 38 37 36 35 34 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 RC0 FIGURE 6: See Table 4 for the pin allocation tables. Note 1: 2: See Table 4 for location of all peripheral functions. It is recommended that the exposed bottom pad be connected to Vss, however it must not be the only Vss connection to the device.  2016 Microchip Technology Inc. Advance Information DS40001861B-page 7 PIC18(L)F2X/4X/5XK42 44-PIN TQFP FOR PIC18(L)F4XK42 44 43 42 41 40 39 38 37 36 35 34 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 NC FIGURE 7: 33 32 31 30 29 28 27 26 25 24 23 PIC18(L)F4XK42 NC RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC NC RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 AN0/RA0 RA1 RA2 RA3 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 Note 1: See Table 4 for location of all peripheral functions. 2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to float may result in degraded electrical performance or non-functionality. 48-PIN TQFP/UQFN FOR PIC18(L)F5XK42 48 47 46 45 44 43 42 41 40 39 38 37 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RF3 RF2 RF1 FIGURE 8: 1 2 3 4 5 6 7 8 9 10 11 12 PIC18(L)F5XK42 36 35 34 33 32 31 30 29 28 27 26 25 RF0 RC1 RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 RF5 RF6 RF7 RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 13 14 15 16 17 18 19 20 21 22 23 24 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 RF4 Note: See Table 5 for location of all peripheral functions. DS40001861B-page 8 Advance Information  2016 Microchip Technology Inc. Voltage Reference DAC Zero Cross Detect I2C SPI UART DSM Timers/SMT CCP and PWM CWG CLC NCO Clock Reference (CLKR) Interrupt-on-Change Basic 2 27 ANA0 — — C1IN0C2IN0- — — — — — — — — CLCIN0(1) — — IOCA0 — RA1 3 28 ANA1 — — C1IN1C2IN1- — — — — — — — — CLCIN1(1) — — IOCA1 — RA2 4 1 ANA2 VREF- DAC1OUT1 C1IN0+ C2IN0+ — — — — — — — — — — — IOCA2 — RA3 5 2 ANA3 VREF+ — C1IN1+ — — — — MDCARL(1) — — — — — — IOCA3 — RA4 6 3 ANA4 — — — — — — — MDCARH(1) T0CKI(1) — — — — — IOCA4 — RA5 7 4 ANA5 — — — — — SS1(1) — MDSRC(1) — — — — — — IOCA5 — RA6 10 7 ANA6 — — — — — — — — — — — — — — IOCA6 OSC2 CLKOUT RA7 9 6 ANA7 — — — — — — — — — — — — — — IOCA7 OSC1 CLKIN RB0 21 18 ANB0 — — C2IN1+ ZCD — — — — — CCP4(1) CWG1IN(1) — — — INT0(1) IOCB0 — RB1 22 19 ANB1 — — C1IN3C2IN3- — SCL2(3,4) — — — — — CWG2IN(1) — — — INT1(1) IOCB1 — RB2 23 20 ANB2 — — — — SDA2(3,4) — — — — — CWG3IN(1) — — — INT2(1) IOCB2 — RB3 24 21 ANB3 — — C1IN2C2IN2- — — — — — — — — — — — IOCB3 — RB4 25 22 ANB4 ADCACT(1) — — — — — — — — T5G(1) — — — — — IOCB4 — RB5 26 23 ANB5 — — — — — — — — T1G(1) CCP3(1) — — — — IOCB5 — — — — — CLCIN2(1) — — IOCB6 ICSPCLK — T6IN(1) — — CLCIN3(1) — — IOCB7 ICSPDAT Comparators ADC DS40001861B-page 9 RA0 27 24 ANB6 — — — — — — CTS2(1) RB7 28 25 ANB7 — DAC1OUT2 — — — — RX2(1) Note 1: 2: 3: 4: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C and SMBus 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. RB6 PIC18(L)F2X/4X/5XK42 Advance Information 28-Pin (U)QFN 28-PIN ALLOCATION TABLE (PIC18(L)F2XK42) 28-Pin SPDIP/SOIC/SSOP TABLE 3: I/O  2016 Microchip Technology Inc. PIN ALLOCATION TABLES 28-Pin (U)QFN ADC Voltage Reference DAC Comparators Zero Cross Detect I2C SPI UART DSM CCP and PWM CWG CLC NCO Clock Reference (CLKR) Interrupt-on-Change Basic RC0 11 8 ANC0 — — — — — — — — T1CKI(1) T3CKI(1) T3G(1) SMTWIN1(1) — — — — — IOCC0 SOSCO RC1 12 9 ANC1 — — — — — — — — SMTSIG1(1) CCP2(1) — — — — IOCC1 SOSCI CCP1(1) — — — — IOCC2 — IOCC3 — Timers/SMT 28-Pin SPDIP/SOIC/SSOP Advance Information I/O 28-PIN ALLOCATION TABLE (PIC18(L)F2XK42) (CONTINUED) RC2 13 10 ANC2 — — — — — — — — T5CKI(1) RC3 14 11 ANC3 — — — — SCL1(3,4) SCK1(1) — — T2IN(1) — — — — — RC4 15 12 ANC4 — — — — SDA1(3,4) SDI1(1) — — — — — — — — IOCC4 — RC5 16 13 ANC5 — — — — — — — — T4IN(1) — — — — — IOCC5 —  2016 Microchip Technology Inc. RC6 17 14 ANC6 — — — — — — CTS1(1) — — — — — — — IOCC6 — RC7 18 15 ANC7 — — — — — — RX1(1) — — — — — — — IOCC7 — RE3 1 26 — — — — — — — — — — — — — — — IOCE3 MCLR VPP VDD 20 17 — — — — — — — — — — — — — — — — — VSS 8, 19 5, 16 — — — — — — — — — — — — — — — — — OUT(2) — — ADGRDA ADGRDB — — C1OUT C2OUT — SDA1 SCL1 SDA2 SCL2 SS1 SCK1 SDO1 RTS1 TXDE1 TX1 RTS2 TXDE2 TX2 DSM TMR0 CCP1 CCP2 CCP3 CCP4 PWM5OUT PWM6OUT PWM7OUT PWM8OUT CWG1A CWG1B CWG1C CWG1D CWG2A CWG2B CWG2C CWG2D CWG3A CWG3B CWG3C CWG3D CLC1OUT CLC2OUT CLC3OUT CLC4OUT NCO CLKR — — Note 1: 2: 3: 4: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C and SMBus 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. PIC18(L)F2X/4X/5XK42 DS40001861B-page 10 TABLE 3: 40-Pin UQFN 44-Pin QFN ADC Voltage Reference DAC Zero Cross Detect I2C SPI UART DSM Timers/SMT CCP and PWM CWG CLC NCO Clock Reference (CLKR) Interrupt-on-Change Basic 19 17 19 ANA0 — — C1IN0C2IN0- — — — — — — — — CLCIN0(1) — — IOCA0 — RA1 3 20 18 20 ANA1 — — C1IN1C2IN1- — — — — — — — — CLCIN1(1) — — IOCA1 — RA2 4 21 19 21 ANA2 VREF- DAC1OUT1 C1IN0+ C2IN0+ — — — — — — — — — — — IOCA2 — RA3 5 22 20 22 ANA3 VREF+ — C1IN1+ — — — — MDCARL(1) — — — — — — IOCA3 — RA4 6 23 21 23 ANA4 — — — — — — — MDCARH(1) T0CKI(1) — — — — — IOCA4 — RA5 7 24 22 24 ANA5 — — — — — SS1(1) — MDSRC(1) — — — — — — IOCA5 — RA6 14 31 29 33 ANA6 — — — — — — — — — — — — — — IOCA6 OSC2 CLKOUT RA7 13 30 28 32 ANA7 — — — — — — — — — — — — — — IOCA7 OSC1 CLKIN RB0 33 8 8 9 ANB0 — — C2IN1+ ZCD — — — — — CCP4(1) CWG1IN(1) — — — INT0(1) IOCB0 — RB1 34 9 9 10 ANB1 — — C1IN3C2IN3- — SCL2(3,4) — — — — — CWG2IN(1) — — — INT1(1) IOCB1 — RB2 35 10 10 11 ANB2 — — — — SDA2(3,4) — — — — — CWG3IN(1) — — — INT2(1) IOCB2 — RB3 36 11 11 12 ANB3 — — C1IN2C2IN2- — — — — — — — — — — — IOCB3 — RB4 37 14 12 14 ANB4 ADCACT(1) — — — — — — — — T5G(1) — — — — — IOCB4 — RB5 38 15 13 15 ANB5 — — — — — — — — T1G(1) CCP3(1) — — — — IOCB5 — — - — — CLCIN2(1) — — IOCB6 ICSPCLK RB6 39 16 14 16 ANB6 Comparators 44-Pin TQFP 2 — — — — — — CTS2(1) DS40001861B-page 11 RB7 40 17 15 17 ANB7 — DAC1OUT2 — — — — RX2(1) — T6IN(1) — — CLCIN3(1) — — IOCB7 ICSPDAT RC0 15 32 30 34 ANC0 — — — — — — — — T1CKI(1) T3CKI(1) T3G(1) SMTWIN1(1) — — — — — IOCC0 SOSCO RC1 16 35 31 35 ANC1 — — — — — — — — SMTSIG1(1) CCP2(1) — — — — IOCC1 SOSCI Note 1: 2: 3: 4: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C and SMBus 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. PIC18(L)F2X/4X/5XK42 Advance Information 40-Pin PDIP 40/44-PIN ALLOCATION TABLE FOR PIC18(L)F4XK42, PIC18(L)F5XK42 RA0 I/O  2016 Microchip Technology Inc. TABLE 4: Voltage Reference DAC Comparators Zero Cross Detect I2C SPI UART DSM Timers/SMT CCP and PWM ANC2 — — — — — — — — T5CKI(1) CCP1(1) RC3 18 37 33 37 ANC3 — — — — SCL1(3,4) SCK1(1) — Basic ADC 36 Interrupt-on-Change 44-Pin QFN 32 Clock Reference (CLKR) 40-Pin UQFN 36 NCO 44-Pin TQFP 17 CLC 40-Pin PDIP RC2 CWG I/O 40/44-PIN ALLOCATION TABLE FOR PIC18(L)F4XK42, PIC18(L)F5XK42 (CONTINUED) — — — — IOCC2 — — T2IN(1) — — — — — IOCC3 — Advance Information RC4 23 42 38 42 ANC4 — — — — SDA1(3,4) SDI1(1) — — — — — — — — IOCC4 — RC5 24 43 39 43 ANC5 — — — — — — — — T4IN(1) — — — — — IOCC5 — RC6 25 44 40 44 ANC6 — — — — — — CTS1(1) — — — — — — — IOCC6 — RC7 26 1 1 1 ANC7 — — — — — — RX1(1) — — — — — — — IOCC7 — RD0 19 38 34 38 AND0 — — — — —(4) — — — — — — — — — — — RD1 20 39 35 39 AND1 — — — — —(4) — — — — — — — — — — — RD2 21 40 36 40 AND2 — — — — — — — — — — — — — — — — RD3 22 41 37 41 AND3 — — — — — — — — — — — — — — — — RD4 27 2 2 2 AND4 — — — — — — — — — — — — — — — — RD5 28 3 3 3 AND5 — — — — — — — — — — — — — — — — RD6 29 4 4 4 AND6 — — — — — — — — — — — — — — — — RD7 30 5 5 5 AND7 — — — — — — — — — — — — — — — — RE0 8 25 23 25 ANE0 — — — — — — — — — — — — — — — — RE1 9 26 24 26 ANE1 — — — — — — — — — — — — — — — —  2016 Microchip Technology Inc. RE2 10 27 25 27 ANE2 — — — — — — — — — — — — — — — — RE3 1 18 16 18 — — — — — — — — — — — — — — — IOCE3 MCLR VPP VDD 11, 32 7, 28 7, 26 8, 28 — — — — — — — — — — — — — — — — — VSS 12, 31 6, 29 6, 27 6, 31, 30 — — — — — — — — — — — — — — — — — Note 1: 2: 3: 4: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C and SMBus 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. PIC18(L)F2X/4X/5XK42 DS40001861B-page 12 TABLE 4: 1: 2: 3: 4: Interrupt-on-Change Basic CCP1 CCP2 CCP3 CCP4 PWM5OUT PWM6OUT PWM7OUT PWM8OUT Clock Reference (CLKR) TMR0 NCO DSM CLC RTS1 TXDE1 TX1 RTS2 TXDE2 TX2 CWG SS1 SCK1 SDO1 CCP and PWM SDA1 SCL1 SDA2 SCL2 Timers/SMT — DSM C1OUT C2OUT UART — SPI — CWG1A CWG1B CWG1C CWG1D CWG2A CWG2B CWG2C CWG2D CWG3A CWG3B CWG3C CWG3D CLC1OUT CLC2OUT CLC3OUT CLC4OUT NCO CLKR — — This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C and SMBus 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. DS40001861B-page 13 PIC18(L)F2X/4X/5XK42 Advance Information Note ADGRDA ADGRDB I2C — Zero Cross Detect — Comparators 44-Pin QFN — DAC 40-Pin UQFN — Voltage Reference 44-Pin TQFP OUT(2) ADC 40-Pin PDIP 40/44-PIN ALLOCATION TABLE FOR PIC18(L)F4XK42, PIC18(L)F5XK42 (CONTINUED) I/O  2016 Microchip Technology Inc. TABLE 4: DAC Zero Cross Detect I2C SPI UART DSM Timers/SMT CCP and PWM CWG CLC NCO Clock Reference (CLKR) Interrupt-on-Change Basic 21 21 ANA0 — — C1IN0C2IN0- — — — — — — — — CLCIN0(1) — — IOCA0 — RA1 22 22 ANA1 — — C1IN1C2IN1- — — — — — — — — CLCIN1(1) — — IOCA1 — RA2 23 23 ANA2 VREF- DAC1OUT1 C1IN0+ C2IN0+ — — — — — — — — — — — IOCA2 — RA3 24 24 ANA3 VREF+ — C1IN1+ — — — — MDCARL(1) - — — — — — IOCA3 — RA4 25 25 ANA4 — — — — — — — MDCARH(1) T0CKI(1) — — — — — IOCA4 — RA5 26 26 ANA5 — — — — — SS1(1) — MDSRC(1) — — — — — — IOCA5 — RA6 33 33 ANA6 — — — — — — — — — — — — — — IOCA6 OSC2 CLKOUT RA7 32 32 ANA7 — — — — — — — — — — — — — — IOCA7 OSC1 CLKIN RB0 8 8 ANB0 — — C2IN1+ ZCD — — — — — CCP4(1) CWG1IN(1) — — — INT0(1) IOCB0 — RB1 9 9 ANB1 — — C1IN3C2IN3- — SCL2(3,4) — — — — — CWG2IN(1) — — — INT1(1) IOCB1 — RB2 10 10 ANB2 — — — — SDA2(3,4) — — — — — CWG3IN(1) — — — INT2(1) IOCB2 — RB3 11 11 ANB3 — — C1IN2C2IN2- — — — — — — — — — — — IOCB3 — RB4 16 16 ANB4 ADCACT(1) — — — — — — — — T5G(1) — — — — — IOCB4 — RB5 17 17 ANB5 — — — — — — — — T1G(1) CCP3(1) - — — — IOCB5 — RB6 18 18 ANB6 — — — — — — CTS2(1) — — — — CLCIN2(1) — — IOCB6 ICSPCLK RB7 19 19 ANB7 — DAC1OUT2 — — — — RX2(1) — T6IN(1) — — CLCIN3(1) — — IOCB7 ICSPDAT — — — — — IOCC0 SOSCO CCP2(1) — — — — IOCC1 SOSCI RC0 RC1 Note 34 35 1: 2: 3: 4: Comparators Voltage Reference RA0 I/O ADC  2016 Microchip Technology Inc. 48-Pin UQFN Advance Information 48-Pin TQFP 48-PIN ALLOCATION TABLE FOR PIC18(L)F5XK42 34 ANC0 — — — — — — — — T1CKI(1) T3CKI(1) T3G(1) SMTWIN1(1) 35 ANC1 — - — — — — — — SMTSIG1(1) This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C and SMBus 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. PIC18(L)F2X/4X/5XK42 DS40001861B-page 14 TABLE 5: 48-Pin UQFN ADC Voltage Reference DAC Comparators Zero Cross Detect SPI UART DSM Timers/SMT CCP and PWM CWG CLC NCO Clock Reference (CLKR) Interrupt-on-Change Basic 40 40 ANC2 — - — — — — — — T5CKI(1) CCP1(1) — — — — IOCC2 — RC3 41 41 ANC3 — - — — SCL1(3,4) SCK1(1) — — T2IN(1) - — — — — IOCC3 — RC4 46 46 ANC4 — — — — SDA1(3,4) SDI1(1) — — — — — — — — IOCC4 — I2C 48-Pin TQFP 48-PIN ALLOCATION TABLE FOR PIC18(L)F5XK42 (CONTINUED) RC2 I/O  2016 Microchip Technology Inc. TABLE 5: RC5 47 47 ANC5 — — — — — — — — T4IN(1) — — — — — IOCC5 — RC6 48 48 ANC6 — — — — — — CTS1(1) — — — — — — — IOCC6 — 1 1 ANC7 — — — — — — RX1(1) — — — — — — — IOCC7 — 42 42 AND0 — — — — —(4) — — — — — — — — — — — RD1 43 43 AND1 — — — — —(4) — — — — — — — — — — — RD2 44 44 AND2 — — — — — — — — — — — — — — — — RD3 45 45 AND3 — — — — — — — — — — — — — — — — RD4 2 2 AND4 — — — — — — — — — — — — — — — — RD5 3 3 AND5 — — — — — — — — — — — — — — — — RD6 4 4 AND6 — — — — — — — — — — — — — — — — RD7 5 5 AND7 — — — — — — — — — — — — — — — — RE0 27 27 ANE0 — — — — — — — — — — — — — — — — RE1 28 28 ANE1 — — — — — — — — — — — — — — — — RE2 29 29 ANE2 — — — — — — — — — — — — — — — — RE3 20 20 — — — — — — — — — — — — — — — IOCE3 MCLR VPP RF0 36 36 ANF0 — — — — — — — — — — — — — — — — RF1 37 37 ANF1 — — — — — — — — — — — — — — — — RF2 38 38 ANF2 — — — — — — — — — — — — — — — — RF3 39 39 ANF3 — — — — — — — — — — — — — — — — RF4 12 12 ANF4 — — — — — — — — — — — — — — — — DS40001861B-page 15 RF5 13 13 ANF5 — — — — — — — — — — — — — — — — RF6 14 14 ANF6 — — — — — — — — — — — — — — — — RF7 15 15 ANF7 — — — — — — — — — — — — — — — — VDD 7, 30 7, 30 — — — — — — — — — — — — — — — — — Note 1: 2: 3: 4: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C and SMBus 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. PIC18(L)F2X/4X/5XK42 Advance Information RC7 RD0 Advance Information OUT(2) — Note 1: 2: 3: 4: — Voltage Reference DAC Comparators Zero Cross Detect I2C SPI UART DSM Timers/SMT CCP and PWM CWG CLC NCO Clock Reference (CLKR) Interrupt-on-Change Basic 48-Pin UQFN 6, 31 ADC 48-Pin TQFP 6, 31 I/O VSS 48-PIN ALLOCATION TABLE FOR PIC18(L)F5XK42 (CONTINUED) — — — — — — — — — — — — — — — — — ADGRDA ADGRDB — — C1OUT C2OUT — SDA1 SCL1 SDA2 SCL2 SS1 SCK1 SDO1 RTS1 TXDE1 TX1 RTS2 TXDE2 TX2 DSM TMR0 CCP1 CCP2 CCP3 CCP4 PWM5OUT PWM6OUT PWM7OUT PWM8OUT CWG1A CWG1B CWG1C CWG1D CWG2A CWG2B CWG2C CWG2D CWG3A CWG3B CWG3C CWG3D CLC1OUT CLC2OUT CLC3OUT CLC4OUT NCO CLKR — — This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C and SMBus 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. PIC18(L)F2X/4X/5XK42 DS40001861B-page 16 TABLE 5:  2016 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-1158-1 == ISO/TS 16949 ==  2016 Microchip Technology Inc. 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