PIC18FXX80/XX85
Flash Microcontroller Programming Specification
1.0
DEVICE OVERVIEW
2.1
This
document
includes
the
programming
specifications for the following devices:
• PIC18F6585
• PIC18F6680
• PIC18F8585
• PIC18F8680
2.0
2.1.1
Hardware Requirements
HIGH-VOLTAGE ICSP
PROGRAMMING
In High-Voltage ICSP mode, these devices require two
programmable power supplies: one for VDD and one for
MCLR/VPP. Both supplies should have a minimum
resolution of 0.25V. Refer to Section 6.0 “AC/DC
Characteristics Timing Requirements for Program/
Verify Test Mode” for additional hardware parameters.
PROGRAMMING OVERVIEW
PIC18FXX80/XX85 devices can be programmed using
either the high-voltage In-Circuit Serial ProgrammingTM
(ICSPTM) method, or the low-voltage ICSP method.
Both of these programming methods can be done with
the device in the user’s system. The low-voltage ICSP
method is slightly different than the high-voltage
method, and these differences are noted where applicable. This programming specification applies to
PIC18FXX80/XX85 devices in all package types.
2.1.2
LOW-VOLTAGE ICSP
PROGRAMMING
In Low-Voltage ICSP mode, these devices can be programmed using a VDD source in the operating range.
This only means that MCLR/VPP does not have to be
brought to a different voltage but can instead be left at the
normal operating voltage. Refer to Section 6.0 “AC/DC
Characteristics Timing Requirements for Program/
Verify Test Mode” for additional hardware parameters.
2.2
Pin Diagrams
The pin diagrams for the PIC18FXX80/XX85 family are
shown in Figure 2-1, Figure 2-2 and Figure 2-3. The
pin descriptions of these diagrams do not represent the
complete functionality of the device types. Users
should refer to the appropriate device data sheet for
complete pin descriptions.
TABLE 2-1:
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18FXX80/XX85
During Programming
Pin Name
Pin Name
Pin Type
Pin Description
MCLR/VPP/RA5
VPP
P
Programming Enable
VDD(2)
VDD
P
Power Supply
VSS(2)
AVDD(2)
VSS
P
Ground
AVDD
P
Analog Power Supply
AVSS(2)
AVSS
P
Analog Ground
RB5
PGM
I
Low-Voltage ICSP™ Input when LVP Configuration bit equals ‘1’ (1)
RB6
PGC
I
Serial Clock
RB7
PGD
I/O
OSC1
OSC1
I
Serial Data
Oscillator Input (needs to be pulled high during programming.)
Legend: I = Input, O = Output, P = Power
Note 1: See Section 5.3 “Low-Voltage Programming (LVP) Bit” for more detail.
2: All power supplies and ground must be connected.
2010 Microchip Technology Inc.
DS39606E-page 1
PIC18FXX80/XX85
FIGURE 2-1:
64-PIN TQFP PACKAGE DIAGRAM FOR PIC18F6X8X
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RD3/PSP3
RD2/PSP2
RD1/PSP1
VSS
VDD
RD0/PSP0
RE7/CCP2(1)
RE6/P1B
RE5/P1C
RE4
RE3
RE2/CS
TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RE1/WR
RE0/RD
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
RG5/MCLR/VPP
RG4/P1D
VSS
VDD
RF7/SS
RF6/AN11/C1INRF5/AN10/C1IN+/CVREF
RF4/AN9/C2INRF3/AN8/C2IN+
RF2/AN7/C1OUT
1
48
2
3
4
5
6
7
8
9
10
11
12
13
14
47
46
45
44
43
42
41
40
PIC18F6X8X
39
38
37
36
35
34
33
15
16
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A
Note 1:
DS39606E-page 2
RC7/RX/DT
RC6/TX/CK
RC0/T1OSO/T13CKI
RA4/T0CKI
RC1/T1OSI/CCP2(1)
RA5/AN4/LVDIN
VDD
VSS
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
AVSS
RA3/AN3/VREF+
AVDD
RF0/AN5
RF1/AN6/C2OUT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CCP2 pin placement depends on the Processor mode settings.
2010 Microchip Technology Inc.
PIC18FXX80/XX85
FIGURE 2-2:
68-PIN PLCC PACKAGE DIAGRAM FOR PIC18F6X8X
RE2/CS
RE3
RE4
RE5/P1C
RE6/P1B
RE7/CCP2(1)
RD0/PSP0
VDD
N/C
VSS
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
PLCC
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
RE1/WR
RE0/RD
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
RG5/MCLR/VPP
RG4/P1D
N/C
VSS
VDD
RF7/SS
RF6/AN11/C1INRF5/AN10/C1IN+/CVREF
RF4/AN9/C2INRF3/AN8/C2IN+
RF2/AN7/C1OUT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Top View
PIC18F6X8X
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
N/C
OSC2/CLKO/RA6
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A
Note 1:
VDD
RA5/AN4/LVDIN
RA4/T0CKI
RC1/T1OSI/CCP2(1)
RC0/T1OSO/T13CKI
RC6/TX/CK
RC7/RX/DT
RF1/AN6/C2OUT
RF0/AN5
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1
RA0/AN0
N/C
VSS
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
CCP2 pin placement depends on the Processor mode settings.
2010 Microchip Technology Inc.
DS39606E-page 3
PIC18FXX80/XX85
FIGURE 2-3:
80-PIN TQFP PACKAGE DIAGRAM FOR PIC18F8X8X
RJ1/OE
RJ0/ALE
RD7/PSP7(1)/AD7
RD6/PSP6(1)/AD6
RD5/PSP5(1)/AD5
RD4/PSP4(1)/AD4
RD3/PSP3(1)/AD3
RD2/PSP2(1)/AD2
RD1/PSP1(1)/AD1
VSS
VDD
RE7/CCP2(2)/AD15
RD0/PSP0(1)/AD0
RE6/AD14/P1B
RE5/AD13/P1C
RE4/AD12
RE2/CS/AD10
RE3/AD11
RH0/A16
RH1/A17
TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2/A18
RH3/A19
1
2
RE1/WR/AD9
RE0/RD/AD8
3
4
5
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
RG5/MCLR/VPP
RG4/P1D
VSS
VDD
RF7/SS
RF6/AN11/C1INRF5/AN10/C1IN+/CVREF
RF4/AN9/C2INRF3/AN8/C2IN+
RF2/AN7/C1OUT
RH7/AN15/P1B
RH6/AN14/P1C
60
59
58
57
56
55
6
7
8
9
10
11
12
13
14
15
16
54
53
52
51
50
PIC18F8X8X
49
48
47
46
45
44
43
42
17
18
19
20
41
RJ2/WRL
RJ3/WRH
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/CCP2(2)
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A
RJ7/UB
RJ6/LB
RJ5/CE
RJ4/BA0
RC7/RX/DT
RC6/TX/CK
RC0/T1OSO/T13CKI
RA4/T0CKI
RC1/T1OSI/CCP2(2)
RA5/AN4/LVDIN
VDD
VSS
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
AVSS
RA3/AN3/VREF+
AVDD
RF0/AN5
RF1/AN6/C2OUT
RH4/AN12
RH5/AN13
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Note 1: PSP is available only in Microcontroller mode.
2: CCP2 pin placement depends on the Processor mode settings.
DS39606E-page 4
2010 Microchip Technology Inc.
PIC18FXX80/XX85
2.3
Memory Map
The code memory space extends from 0000h to
0FFFFh (64 Kbytes) in four 16-Kbyte blocks. However,
addresses 0000h through 07FFh define a “Boot Block”
region that is treated separately from Block 1. All of
these blocks define code protection boundaries within
the code memory space.
In contrast, code memory panels are defined in 8-Kbyte
boundaries. Panels are discussed in greater detail in
Section 3.2 “Code Memory Programming”.
FIGURE 2-4:
TABLE 2-2:
IMPLEMENTATION OF CODE
MEMORY
Device
PIC18F6585
PIC18F8585
PIC18F6680
PIC18F8680
Code Memory Size
(Bytes)
0000h - 00BFFFh (48K)
0000h -00FFFFh (64K)
MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FXX80/XX85 DEVICES
48 Kbytes
000000h
Code Memory
00FFFFh
Boot Block
Panel 1
Block 1
64 Kbytes
000000h
0007FFh
Boot Block
Block 1
Panel 1
Panel 2
Panel 2
Panel 3
Panel 3
001FFFh
003FFFh
Block 2
Unimplemented
Read as ‘0’
005FFFh
Block 2
Panel 4
Panel 4
Panel 5
Panel 5
007FFFh
Block 3
009FFFh
Block 3
Panel 6
Panel 6
00BFFFh
Panel 7
Unimplemented
Read as ‘0’s
00DFFFh
Block 4
Panel 8
00FFFFh
1FFFFFh
Configuration
and ID
Space
Unimplemented
Read as ‘0’s
Read as ‘0’s
01FFFFh
3FFFFFh
Note:
Unimplemented
Sizes of memory areas are not shown to scale.
2010 Microchip Technology Inc.
DS39606E-page 5
PIC18FXX80/XX85
In addition to the code memory space, there are three
blocks in the configuration and ID space that are accessible to the user through table reads and table writes.
Their locations in the memory map are shown in
Figure 2-5.
Users may store identification information (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations
read out normally even after code protection is applied.
Locations, 300000h through 30000Dh, are reserved for
the Configuration bits. These bits select various device
options and are described in Section 5.0 “Configuration Word”. These Configuration bits read out
normally even after code protection.
Locations, 3FFFFEh and 3FFFFFh, are reserved for
the device ID bits. These bits may be used by the
programmer to identify what device type is being
FIGURE 2-5:
programmed and are described in Section 5.0
“Configuration Word”. These device ID bits read out
normally even after code protection.
2.3.1
MEMORY ADDRESS POINTER
Memory in the address space, 000000h to 3FFFFFh, is
addressed via the Table Pointer which is comprised of
three pointer registers:
• TBLPTRU, at RAM address 0FF8h
• TBLPTRH, at RAM address 0FF7h
• TBLPTRL, at RAM address 0FF6h
TBLPTRU
TBLPTRH
TBLPTRL
Addr[21:16]
Addr[15:8]
Addr[7:0]
The 4-bit command, ‘0000’ (core Instruction), is used
to load the Table Pointer prior to using many read or
write operations.
CONFIGURATION AND ID LOCATIONS FOR PIC18FXX80/XX85 DEVICES
000000h
Code Memory
00FFFFh
or
00BFFFh
Unimplemented
Read as ‘0’
1FFFFFh
Configuration
and ID
Space
2FFFFFh
ID Location 1
200000h
ID Location 2
200001h
ID Location 3
200002h
ID Location 4
200003h
ID Location 5
200004h
ID Location 6
200005h
ID Location 7
200006h
ID Location 8
200007h
CONFIG1L
300000h
CONFIG1H
300001h
CONFIG2L
300002h
CONFIG2H
300003h
CONFIG3L
300004h
CONFIG3H
300005h
CONFIG4L
300006h
CONFIG4H
300007h
CONFIG5L
300008h
CONFIG5H
300009h
CONFIG6L
30000Ah
CONFIG6H
30000Bh
CONFIG7L
30000Ch
CONFIG7H
30000Dh
Device ID1
3FFFFEh
Device ID2
3FFFFFh
3FFFFFh
Note:
Sizes of memory areas are not shown to scale.
DS39606E-page 6
2010 Microchip Technology Inc.
PIC18FXX80/XX85
2.4
High-Level Overview of the
Programming Process
FIGURE 2-7:
Figure 2-7 shows the high-level overview of the
programming process. First, a Bulk Erase is performed.
Next, the code memory, ID locations and data
EEPROM are programmed. These memories are then
verified to ensure that programming was successful. If
no errors are detected, the Configuration bits are then
programmed and verified.
HIGH-LEVEL
PROGRAMMING FLOW
Start
Perform Bulk
Erase
Program Memory
2.5
Entering High-Voltage ICSP
Program/Verify Mode
Program IDs
The High-Voltage ICSP Program/Verify mode is
entered by holding PGC and PGD low and then raising
MCLR/VPP to VIHH (high voltage). Once in this mode,
the code memory, data EEPROM, ID locations and
Configuration bits can be accessed and programmed in
serial fashion.
Program Data
The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.
2.5.1
Verify Program
Verify IDs
ENTERING LOW-VOLTAGE ICSP
PROGRAM/VERIFY MODE
When the LVP Configuration bit is ‘1’ (see Section 5.3
“Low-Voltage Programming (LVP) Bit”), the LowVoltage ICSP mode is enabled. Low-Voltage ICSP
Program/Verify mode is entered by holding PGC and
PGD low, placing a logic high on PGM and then raising
MCLR/VPP to VIH. In this mode, the RB5/PGM pin is
dedicated to the programming function and ceases to
be a general purpose I/O pin.
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.
Done
FIGURE 2-8:
FIGURE 2-6:
ENTERING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
P13
ENTERING LOW-VOLTAGE
PROGRAM/VERIFY MODE
P15
P12
P12
VIH
MCLR/VPP
P1
D110
VDD
MCLR/VPP
VIH
PGM
VDD
PGD
PGD
PGC
PGC
PGD = Input
2010 Microchip Technology Inc.
PGD = Input
DS39606E-page 7
PIC18FXX80/XX85
2.6
TABLE 2-3:
Serial Program/Verify Operation
The PGC pin is used as a clock input pin and the PGD
pin is used for entering command bits and data input/
output during serial operation. Commands and data are
transmitted on the rising edge of PGC, latched on the
falling edge of PGC and are Least Significant bit (LSb)
first.
2.6.1
4-Bit
Command
Description
4-BIT COMMANDS
All instructions are 20 bits, consisting of a leading 4-bit
command followed by a 16-bit operand, which depends
on the type of command being executed. To input a
command, PGC is cycled four times. The commands
needed for programming and verification are shown in
Table 2-3.
Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data or 8 bits of input data
and 8 bits of output data.
Throughout this specification, commands and data are
presented as illustrated in Table 2-4. The 4-bit command is shown Most Significant bit (MSb) first. The
command operand, or “Data Payload”, is shown
. Figure 2-9 demonstrates how to
serially present a 20-bit command/operand to the
device.
2.6.2
COMMANDS FOR
PROGRAMMING
Core Instruction
(shift in16-bit instruction)
0000
Shift out TABLAT register
0010
Table Read
1000
Table Read, Post-Increment
1001
Table Read, Post-Decrement
1010
Table Read, Pre-Increment
1011
Table Write
1100
Table Write, Post-Increment by 2
1101
Table Write, Post-Decrement by 2
1110
Table Write, Start Programming
1111
TABLE 2-4:
SAMPLE COMMAND
SEQUENCE
4-Bit
Data
Command Payload
1101
3C 40
Core Instruction
Table Write,
post-increment by 2
CORE INSTRUCTION
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to set up
registers as appropriate for use with other commands.
FIGURE 2-9:
TABLE WRITE, POST-INCREMENT TIMING (‘1101’)
P2
1
P2A
P2B
2
3
4
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16
2
1
3
4
PGC
P5
P5A
P4
P3
PGD
1
0
1
1
0
0
0
0
4-Bit Command
0
0
0
1
0
0
0
1
4
C
16-Bit Data Payload
1
1
1
0
0
n
n
n
n
3
Fetch Next 4-Bit Command
PGD = Input
DS39606E-page 8
2010 Microchip Technology Inc.
PIC18FXX80/XX85
3.0
DEVICE PROGRAMMING
3.1
High-Voltage ICSP Bulk Erase
TABLE 3-2:
4-Bit
Command
Erasing code or data EEPROM is accomplished by
writing an “Erase Option” to address 3C0004h. Code
memory may be erased portions at a time, or the user
may erase the entire device in one action. “Bulk Erase”
operations will also clear any code-protect settings
associated with the memory block erased. Erase
options are detailed in Table 3-1.
TABLE 3-1:
BULK ERASE OPTIONS
Description
BULK ERASE COMMAND
SEQUENCE
Data
Payload
0000
0000
0000
0000
0000
0000
0000
0000
1100
8E
8C
0E
6E
0E
6E
0E
6E
00
0000
0000
00 00
00 00
A6
A6
3C
F8
00
F7
04
F6
80
BSF
EECON1, EEPGD
BSF
EECON1, CFGS
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 80h TO 3C0004h to
erase entire device.
NOP
Hold PGD low until
erase completes.
Data
Chip Erase
80h
Erase Data EEPROM
81h
Erase Boot Block
83h
Erase Block 1
88h
Erase Block 2
89h
Erase Block 3
8Ah
Erase Block 4
8Bh
FIGURE 3-1:
BULK ERASE FLOW
Start
The actual Bulk Erase function is a self-timed operation. Once the erase has started (falling edge of the 4th
PGC after the “Write” command), serial execution will
cease until the erase completes (parameter P11).
During this time, PGC may continue to toggle but PGD
must be held low.
Load Address
Pointer to
3C0004h
Write 80h
to Erase
Entire Device
The code sequence to erase the entire device is shown
in Table 3-2 and the flowchart is shown in Figure 3-1.
Note:
Core Instruction
A Bulk Erase is the only way to reprogram
code-protect bits from an ON state to an
OFF state.
Delay P11+P10
Time
Non code-protect bits are not returned to
default settings by a Bulk Erase. These
bits should be programmed to ‘1’s, as outlined in Section 3.6 “Configuration Bits
Programming”.
Done
FIGURE 3-2:
BULK ERASE TIMING
P10
1
2
3
4
1
2
15 16
1
2
3
4
1
2
15 16
1
2
3
4
1
2
n
n
PGC
P5A
P5
PGD
0
0
1
1
4-Bit Command
0
0
0
0
16-Bit
Data Payload
P5
0
0
0
0
4-Bit Command
P5A
0
0
0
0
16-Bit
Data Payload
P11
0
0
0
0
4-Bit Command
Erase Time
16-Bit
Data Payload
PGD = Input
2010 Microchip Technology Inc.
DS39606E-page 9
PIC18FXX80/XX85
3.1.1
LOW-VOLTAGE ICSP BULK ERASE
When using low-voltage ICSP, the part must be supplied by the voltage specified in parameter D111 if a
Bulk Erase is to be executed. All other Bulk Erase
details as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the Bulk Erase
limit, refer to the erase methodology described in
Section 3.1.2 “ICSP Multi-Panel Single Row Erase”
and Section 3.2.2 “Modifying Code Memory”.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the Bulk Erase
limit, follow the methodology described in Section 3.3
“Data EEPROM Programming” and write ‘1’s to the
array.
3.1.2
ICSP MULTI-PANEL SINGLE ROW
ERASE
Irrespective of whether high or low-voltage ICSP is
used, it is possible to erase single row (64 bytes of data)
in all panels at once. For example, in the case of a
64-Kbyte device (8 panels), 512 bytes through 64 bytes
in each panel can be erased simultaneously during
each erase sequence. In this case, the offset of the
TABLE 3-3:
erase within each panel is the same (see Figure 3-5).
Multi-panel single row erase is enabled by appropriately
configuring the Programming Control register located at
3C0006h.
The multi-panel single row erase duration is externally
timed and is controlled by PGC. After a “Start Programming” command is issued (4-bit, ‘1111’), a NOP is
issued, where the 4th PGC is held high for the duration
of the programming time, P9.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time specified by parameter P10 to allow high-voltage discharge
of the memory array.
The code sequence to program a PIC18FXX80/XX85
device is shown in Table 3-3. The flowchart shown in
Figure 3-3 depicts the logic necessary to completely
erase a PIC18FXX80/XX85 device. The timing diagram that details the “Start Programming” command
and parameters P9 and P10 is shown in Figure 3-6.
Note:
The TBLPTR register must contain the
same offset value when initiating the programming sequence as it did when the
write buffers were loaded.
ERASE CODE MEMORY CODE SEQUENCE
4-Bit
Command
Data Payload
Core Instruction
Step 1: Direct access to configuration memory.
0000
0000
0000
8E A6
8C A6
86 A6
BSF
BSF
BSF
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
Step 2: Configure device for multi-panel writes.
0000
0000
0000
0000
0000
0000
1100
0E
6E
0E
6E
0E
6E
00
3C
F8
00
F7
06
F6
40
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write
3Ch
TBLPTRU
00h
TBLPTRH
06h
TBLPTRL
40h to 3C0006h to enable multi-panel erase.
Step 3: Direct access to code memory and enable erase.
0000
0000
0000
0000
0000
0000
8E
9C
88
6A
6A
6A
A6
A6
A6
F8
F7
F6
BSF
BCF
BSF
CLRF
CLRF
CLRF
EECON1, EEPGD
EECON1, CFGS
EECON1, FREE
TBLPTRU
TBLPTRH
TBLPTRL
Step 4: Erase single row of all panels at an offset.
1111
0000
00 00
Write 2 dummy bytes and start programming.
NOP - hold PGC high for time P9.
Step 5: Repeat step 4, with Address Pointer incremented by 64 until all panels are erased.
DS39606E-page 10
2010 Microchip Technology Inc.
PIC18FXX80/XX85
FIGURE 3-3:
MULTI-PANEL SINGLE ROW ERASE CODE MEMORY FLOW
Start
Addr = 0
Configure
Device for
Multi-Panel Erase
Start Erase Sequence
and Hold PGC High
until Done
Addr = Addr + 64
Delay P9 + P10
Time for Erase
to Occur
No
All
Panels
Done?
Yes
Done
3.2
Code Memory Programming
Programming code memory is accomplished by first
loading data into the appropriate write buffers and then
initiating a programming sequence. Each panel in the
code memory space (see Figure 2-4) has an 8-byte
deep write buffer that must be loaded prior to initiating
a write sequence. The actual memory write sequence
takes the contents of these buffers and programs the
associated EEPROM code memory.
Typically, all of the program buffers are written in parallel (Multi-Panel Write mode). For example, in the case
of a 64-Kbyte device (8 panels with an 8-byte buffer per
panel), 64 bytes will be simultaneously programmed
during each programming sequence. In this case, the
offset of the write within each panel is the same (see
Figure 3-4). Multi-Panel Write mode is enabled by
appropriately configuring the Programming Control
register located at 3C0006h.
2010 Microchip Technology Inc.
The programming duration is externally timed and is
controlled by PGC. After a “Start Programming” command is issued (4-bit command, ‘1111’), a NOP is
issued, where the 4th PGC is held high for the duration
of the programming time, P9.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time specified by parameter P10 to allow high-voltage discharge
of the memory array.
The code sequence to program a PIC18FXX80/XX85
device is shown in Table 3-4. The flowchart shown in
Figure 3-5 depicts the logic necessary to completely
write a PIC18FXX80/XX85 device. The timing diagram
that details the “Start Programming” command and
parameters P9 and P10 is shown in Figure 3-6.
Note:
The TBLPTR register must contain the
same offset value when initiating the programming sequence as it did when the
write buffers were loaded.
DS39606E-page 11
PIC18FXX80/XX85
FIGURE 3-4:
ERASE AND WRITE BOUNDARIES
Panel n
8-Byte Write Buffer
TBLPTR = (n – 1)
TBLPTR = 7
TBLPTR = 6
TBLPTR = 5
TBLPTR = 4
TBLPTR = 3
TBLPTR = 2
TBLPTR = 1
TBLPTR = 0
Erase Region
(64 bytes)
Offset = TBLPTR
Offset = TBLPTR
Panel 3
8-Byte Write Buffer
TBLPTR = 2
TBLPTR = 7
TBLPTR = 6
TBLPTR = 5
TBLPTR = 4
TBLPTR = 3
TBLPTR = 2
TBLPTR = 1
TBLPTR = 0
Erase Region
(64 bytes)
Offset = TBLPTR
Offset = TBLPTR
Panel 2
8-Byte Write Buffer
TBLPTR = 1
TBLPTR = 7
TBLPTR = 6
TBLPTR = 5
TBLPTR = 4
TBLPTR = 3
TBLPTR = 2
TBLPTR = 1
TBLPTR = 0
Erase Region
(64 bytes)
Offset = TBLPTR
Offset = TBLPTR
Panel 1
8-Byte Write Buffer
TBLPTR = 0
TBLPTR = 7
TBLPTR = 6
TBLPTR = 5
TBLPTR = 4
TBLPTR = 3
TBLPTR = 2
TBLPTR = 1
TBLPTR = 0
Erase Region
(64 bytes)
Offset = TBLPTR
Offset = TBLPTR
Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL.
DS39606E-page 12
2010 Microchip Technology Inc.
PIC18FXX80/XX85
TABLE 3-4:
WRITE CODE MEMORY CODE SEQUENCE
4-Bit
Command
Data Payload
Core Instruction
Step 1: Direct access to configuration memory.
0000
0000
0000
8E A6
8C A6
86 A6
BSF
BSF
BSF
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
Step 2: Configure device for multi-panel writes.
0000
0000
0000
0000
0000
0000
1100
0E
6E
0E
6E
0E
6E
00
3C
F8
00
F7
06
F6
40
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write
3Ch
TBLPTRU
00h
TBLPTRH
06h
TBLPTRL
40h to 3C0006h to enable multi-panel writes.
BSF
BCF
EECON1, EEPGD
EECON1, CFGS
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write
Write
Write
Write
TBLPTRU
TBLPTRH
TBLPTRL
2 bytes and post-increment address by 2
2 bytes and post-increment address by 2
2 bytes and post-increment address by 2
2 bytes
Step 3: Direct access to code memory.
0000
0000
8E A6
9C A6
Step 4: Load write buffer for Panel 1.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1100
0E
6E F8
0E
6E F7
0E
6E F6
Step 5: Repeat for Panel 2.
Step 6: Repeat for all but the last panel (N – 1).
Step 7: Load write buffer for last panel.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E
6E F8
0E
6E F7
0E
6E F6
00 00
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write
Write
Write
Write
NOP -
TBLPTRU
TBLPTRH
TBLPTRL
2 bytes and post-increment address by 2
2 bytes and post-increment address by 2
2 bytes and post-increment address by 2
2 bytes and start programming
hold PGC high for time P9
To continue writing data, repeat steps 2 through 5, where the Address Pointer is incremented by 8 in each panel at each iteration of
the loop.
2010 Microchip Technology Inc.
DS39606E-page 13
PIC18FXX80/XX85
FIGURE 3-5:
PROGRAM CODE MEMORY FLOW
Start
N=1
LoopCount = 0
Configure
Device for
Multi-Panel Writes
Panel Base Address =
(N – 1) x 2000h
Addr = Panel Base Address
+ (8 x LoopCount)
Load 8 Bytes
to Panel N Write
Buffer at
N=N+1
All
Panel Buffers
Written?
No
Yes
N=1
LoopCount =
LoopCount + 1
Start Write Sequence
and Hold PGC
High until Done
Delay P9 + P10 Time
for Write to Occur
All
Locations
Done?
No
Yes
Done
FIGURE 3-6:
TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (‘1111’)
P10
1
2
3
4
1
2
3
4
5
6
15 16
1
2
3
4
PGC
P5
PGD
1
2
3
P9
1
1
1
1
4-Bit Command
P5A
n
n
n
n
n
n
n
16-Bit Data Payload
n
0
0
0
0
0
4-Bit Command Programming Time
0
0
16-Bit
Data Payload
PGD = Input
DS39606E-page 14
2010 Microchip Technology Inc.
PIC18FXX80/XX85
3.2.1
SINGLE PANEL PROGRAMMING
The programming example presented in Section 3.2
“Code Memory Programming” utilizes multi-panel
programming. This technique greatly decreases the
total amount of time necessary to completely program
a device and is the recommended method of
completely programming a device.
There may be situations, however, where it is advantageous to limit writes to a single panel. In such cases,
the user only needs to disable the multi-panel write
feature of the device by appropriately configuring the
Programming Control register located at 3C0006h.
The single panel that will be written will automatically
be enabled based on the value of the Table Pointer.
Note:
3.2.2
Even though multi-panel writes are disabled, the user must still fill the 8-byte
write buffer for the given panel.
MODIFYING CODE MEMORY
All of the programming examples up to this point have
assumed that the device has been Bulk Erased prior to
programming (see Section 3.1 “High-Voltage ICSP
Bulk Erase”). However, it may be the case that the
user wishes to modify only a section of an already
programmed device.
The minimum amount of code memory that may be
erased at a given time is 64 bytes. Again, the device
must be placed in Single Panel Write mode. The
EECON1 register must then be used to erase the
64-byte target space prior to writing the data.
When using the EECON1 register to act on code memory, the EEPGD bit must be set (EECON1 = 1) and
the CFGS bit must be cleared (EECON1 = 0). The
WREN bit must be set (EECON1 = 1) to enable
writes of any sort (e.g., erases) and this must be done
prior to initiating a write sequence. The FREE bit must
be set (EECON1 = 1) in order to erase the program
space being pointed to by the Table Pointer. The erase
sequence is initiated by setting the WR bit
(EECON1 = 1). It is strongly recommended that the
WREN bit be set only when absolutely necessary.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
and then AAh, immediately prior to asserting the WR bit
in order for the write to occur.
The erase will begin on the falling edge of the 4th PGC
after the WR bit is set. After the erase sequence terminates, PGC must still be held low for the time specified
by parameter P10 to allow high-voltage discharge of
the memory array.
The minimum amount of data that can be written to the
device is 8 bytes. This is accomplished by placing the
device in Single Panel Write mode (see Section 3.2.1
“Single Panel Programming”), loading the 8-byte
write buffer for the panel and then initiating a write
sequence. In this case, it is assumed that the address
space to be written already has data in it (i.e., it is not
blank).
2010 Microchip Technology Inc.
DS39606E-page 15
PIC18FXX80/XX85
TABLE 3-5:
MODIFYING CODE MEMORY
4-Bit
Command
Data Payload
Core Instruction
Step 1: Direct access to configuration memory.
0000
0000
8E A6
8C A6
BSF
BSF
EECON1, EEPGD
EECON1, CFGS
Step 2: Configure device for single panel writes.
0000
0000
0000
0000
0000
0000
1100
0E
6E
0E
6E
0E
6E
00
3C
F8
00
F7
06
F6
00
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write
3Ch
TBLPTRU
00h
TBLPTRH
06h
TBLPTRL
00h to 3C0006h to enable single-panel writes.
BSF
BCF
EECON1, EEPGD
EECON1, CFGS
Step 3: Direct access to code memory.
0000
0000
8E A6
9C A6
Step 4: Set the Table Pointer for the block to be erased.
0000
0000
0000
0000
0000
0000
0E
6E
0E
6E
0E
6E
F8
F7
F6
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
TBLPTRU
TBLPTRH
TBLPTRL
Step 5: Enable memory writes and set up an erase.
0000
0000
84 A6
88 A6
BSF
BSF
EECON1, WREN
EECON1, FREE
MOVLW
MOVWF
MOVLW
MOVWF
55h
EECON2
0AAh
EECON2
BSF
NOP
EECON1, WR
Step 6: Perform required sequence.
0000
0000
0000
0000
0E
6E
0E
6E
55
A7
AA
A7
Step 7: Initiate erase.
0000
0000
82 A6
00 00
Step 8: Wait for P11 + P10 and then disable writes.
0000
94 A6
BCF
EECON1, WREN
Step 9: Load write buffer for panel. The correct panel will be selected based on the Table Pointer.
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E
6E F7
0E
6E F6
00 00
MOVLW
MOVWF
MOVLW
MOVWF
Write
Write
Write
Write
NOP -
TBLPTRH
TBLPTRL
2 bytes and post-increment address by 2
2 bytes and post-increment address by 2
2 bytes and post-increment address by 2
2 bytes and start programming
hold PGC high for time P9
To continue writing data, repeat step 8, where the Address Pointer is incremented by 8 at each iteration of the loop.
DS39606E-page 16
2010 Microchip Technology Inc.
PIC18FXX80/XX85
3.3
FIGURE 3-7:
Data EEPROM Programming
PROGRAM DATA FLOW
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair, EEADR:EEADRH) and
a data latch (EEDATA). Data EEPROM is written by
loading EEADR:EEADRH with the desired memory
location, EEDATA with the data to be written and initiating a memory write by appropriately configuring the
EECON1 and EECON2 registers. A byte write automatically erases the location and writes the new data
(erase-before-write).
Start
Set Address
Set Data
Enable Write
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1 = 00). The WREN bit must
be set (EECON1 = 1) to enable writes of any sort,
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1 = 1). It is strongly recommended
that the WREN bit be set only when absolutely
necessary.
Unlock Sequence
55h – EECON2
AAh – EECON2
Start Write
Sequence
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
and then AAh immediately prior to asserting the WR bit
in order for the write to occur.
Yes
No
Done
?
The write begins on the falling edge of the 4th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
Yes
Done
After the programming sequence terminates, PGC must
still be held low for the time specified by parameter P10
to allow high-voltage discharge of the memory array.
FIGURE 3-8:
No
WR bit
Clear?
DATA EEPROM WRITE TIMING
P10
1
2
3
4
2
1
1
15 16
2
PGC
P5A
P5
PGD
0
0
0
n
0
4-Bit Command BSF EECON1, WR
n
16-Bit Data
Payload
Poll WR Bit, Repeat Until Clear
(see below)
PGD = Input
1
2
3
4
1
2
15 16
1
2
3
4
1
2
15 16
PGC
P5
P5A
P5
P5A
Poll WR Bit
PGD
0
0
0
0
0
4-Bit Command MOVF EECON1, W, 0
0
0
4-Bit Command
PGD = Input
2010 Microchip Technology Inc.
0
MOVWF TABLAT
Shift Out Data
(see Figure 4-4)
PGD = Output
DS39606E-page 17
PIC18FXX80/XX85
TABLE 3-6:
PROGRAMMING DATA MEMORY
4-Bit
Command
Data Payload
Core Instruction
Step 1: Direct access to data EEPROM.
0000
0000
9E A6
9C A6
BCF
BCF
EECON1, EEPGD
EECON1, CFGS
Step 2: Set the data EEPROM Address Pointer.
0000
0000
0000
0000
0E
6E
OE
6E
A9
AA
MOVLW
MOVWF
MOVLW
MOVWF
EEADR
EEADRH
Step 3: Load the data to be written.
0000
0000
0E
6E A8
MOVLW
MOVWF EEDATA
Step 4: Enable memory writes.
0000
84 A6
BSF
EECON1, WREN
MOVLW
MOVWF
MOVLW
MOVWF
55h
EECON2
0AAh
EECON2
BSF
EECON1, WR
Step 5: Perform required sequence.
0000
0000
0000
0000
0E
6E
0E
6E
55
A7
AA
A7
Step 6: Initiate write.
0000
82 A6
Step 7: Poll WR bit, repeat until the bit is clear.
0000
0000
0010
50 A6
6E F5
MOVF EECON1, W, 0
MOVWF TABLAT
Shift out data(1)
Step 8: Disable writes.
0000
94 A6
BCF
EECON1, WREN
Repeat steps 2 through 8 to write more data.
Note 1:
See Figure 4-4 for details on shift out data timing.
DS39606E-page 18
2010 Microchip Technology Inc.
PIC18FXX80/XX85
3.4
ID Location Programming
Note:
The ID locations are programmed much like the code
memory except that multi-panel writes must be disabled. The single panel that will be written will automatically be enabled based on the value of the Table
Pointer. The ID registers are mapped in addresses,
200000h through 200007h. These locations read out
normally even after code protection.
TABLE 3-7:
Even though multi-panel writes are disabled, the user must still fill the 8-byte data
buffer for the panel.
Table 3-7 demonstrates the code sequence required to
write the ID locations.
WRITE ID SEQUENCE
4-Bit
Command
Data Payload
Core Instruction
Step 1: Direct access to configuration memory.
0000
0000
8E A6
8C A6
BSF
BSF
EECON1, EEPGD
EECON1, CFGS
Step 2: Configure device for single panel writes.
0000
0000
0000
0000
0000
0000
1100
0E
6E
0E
6E
0E
6E
00
3C
F8
00
F7
06
F6
00
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write
3Ch
TBLPTRU
00h
TBLPTRH
06h
TBLPTRL
00h to 3C0006h to enable single panel writes.
BSF
BCF
EECON1, EEPGD
EECON1, CFGS
Step 3: Direct access to code memory.
0000
0000
8E A6
9C A6
Step 4: Load write buffer. Panel will be automatically determined by address.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E 20
6E F8
0E 00
6E F7
0E 00
6E F6
00 00
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write
Write
Write
Write
NOP -
20h
TBLPTRU
00h
TBLPTRH
00h
TBLPTRL
2 bytes and post-increment address by 2
2 bytes and post-increment address by 2
2 bytes and post-increment address by 2
2 bytes and start programming
hold PGC high for time P9
In order to modify the ID locations, refer to the methodology described in Section 3.2.2 “Modifying Code
Memory”. As with code memory, the ID locations must
be erased before modified.
2010 Microchip Technology Inc.
DS39606E-page 19
PIC18FXX80/XX85
3.5
Boot Block Programming
3.6
The Boot Block segment is programmed in exactly the
same manner as the ID locations (see Section 3.4 “ID
Location Programming”). Multi-panel writes must be
disabled so that only addresses in the range, 0000h to
07FFh, will be written.
The code sequence detailed in Table 3-7 should be
used, except that the address data used in “Step 2” will
be in the range, 000000h to 0007FFh.
Unlike code memory, the Configuration bits are
programmed a byte at a time. The “Table Write, Begin
Programming” 4-bit command (‘1111’) is used, but only
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses
and the MSB will be written to odd addresses. The
code sequence to program two consecutive
configuration locations is shown in Table 3-8.
Note:
TABLE 3-8:
Configuration Bits Programming
Execute four NOPs between
configuration byte programming.
every
SET ADDRESS POINTER TO CONFIGURATION LOCATION
4-Bit
Command
Data Payload
Core Instruction
Step 1: Direct access to configuration memory.
0000
0000
8E A6
8C A6
BSF
BSF
EECON1, EEPGD
EECON1, CFGS
GOTO
100000h
Step 2: Position the program counter.(1)
0000
0000
EF 00
F8 00
Step 3: Set Table Pointer for configuration byte to be written. Write even/odd addresses.(2)
0000
0000
0000
0000
0000
0000
1111
0000
0000
1111
0000
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
00 00
2A F6
00 00
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming
NOP - hold PGC high for time P9
INCF TBLPTRL
Load 2 bytes and start programming
NOP - hold PGC high for time P9
Step 4: Execute four NOPs.
0000
0000
0000
0000
Note 1:
2:
00
00
00
00
00
00
00
00
If the code protection bits are programmed while the program counter resides in the same block, then the interaction of
code protection logic may prevent further table write. To avoid this situation, move the program counter outside the
code protection area (e.g., GOTO 100000h).
Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of Configuration
bits. Always write all the Configuration bits before enabling the write protection for Configuration bits.
DS39606E-page 20
2010 Microchip Technology Inc.
PIC18FXX80/XX85
FIGURE 3-9:
CONFIGURATION PROGRAMMING FLOW
Start
Start
Load Even
Configuration
Address
Load Odd
Configuration
Address
Program
LSB
Program
MSB
Delay P9 Time
for Write
Delay P9 Time
for Write
Execute
Four NOPs
Execute
Four NOPs
Done
Done
2010 Microchip Technology Inc.
DS39606E-page 21
PIC18FXX80/XX85
4.0
READING THE DEVICE
4.1
Read Code Memory, ID Locations
and Configuration Bits
The 4-bit command is shifted in LSb first. The read is
executed during the next 8 clocks, then shifted out on
PGD during the last 8 clocks, LSb to MSb. A delay of
P6 must be introduced after the falling edge of the 8th
PGC of the operand to allow PGD to transition from an
input to an output. During this time, PGC must be held
low (see Figure 4-1). This operation also increments
the Table Pointer by one, pointing to the next byte in
code memory for the next read.
Code memory is accessed one byte at a time via the
4-bit command, ‘1001’ (table read, post-increment).
The contents of memory pointed to by the Table Pointer
(TBLPTRU:TBLPTRH:TBLPTRL) are loaded into the
table latch and then serially output on PGD.
TABLE 4-1:
This technique will work to read any memory in the
000000h to 3FFFFFh address space, so it also applies
to the reading of the ID and Configuration registers.
READ CODE MEMORY SEQUENCE
4-Bit
Command
Data Payload
Core Instruction
Step 1: Set Table Pointer.
0000
0000
0000
0000
0000
0000
0E
6E
0E
6E
0E
6E
F8
F7
F6
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Addr[21:16]
TBLPTRU
TBLPTRH
TBLPTRL
Step 2: Read memory into table latch and then shift out on PGD, LSb to MSb.
1001
00 00
FIGURE 4-1:
TBLRD *+
TABLE READ POST-INCREMENT INSTRUCTION TIMING (‘1001’)
1
2
3
4
1
2
3
4
5
6
7
9
8
10 11
1
12 13 14 15 16
2
3
4
PGC
P5
P6
P5A
P14
PGD
1
0
0
LSb 1
1
2
3
4
5
Shift Data Out
PGD = Input
DS39606E-page 22
PGD = Output
6
MSb
n
n
n
n
Fetch Next
4-Bit Command
PGD = Input
2010 Microchip Technology Inc.
PIC18FXX80/XX85
4.2
Verify Code Memory and ID
Locations
The verify step involves reading back the code memory
space and comparing against the copy held in the programmer’s buffer. Memory reads occur a single byte at
a time, so two bytes must be read to compare against
the word in the programmer’s buffer. Refer to
Section 4.1 “Read Code Memory, ID Locations and
Configuration Bits” for implementation details of
reading code memory.
FIGURE 4-2:
The Table Pointer must be manually set to 200000h
(base address of the ID locations) once the code memory has been verified. The post-increment feature of
the table read 4-bit command may not be used to
increment the Table Pointer beyond the code memory
space. In a 48-Kbyte device, for example, a postincrement read of address 0BFFFh will wrap the Table
Pointer back to 0000h, rather than point to
unimplemented address, 0C000h.
VERIFY CODE MEMORY FLOW
Start
Set Pointer = 0
Set Pointer = 200000h
Read Low Byte
Read Low Byte
Read High Byte
Read High Byte
Does
Word = Expect
Data?
No
Does
Word = Expect
Data?
Failure,
Report
Error
Yes
No
All
Code Memory
Verified?
Yes
No
Failure,
Report
Error
Yes
No
All
ID Locations
Verified?
Yes
Done
2010 Microchip Technology Inc.
DS39606E-page 23
PIC18FXX80/XX85
4.3
FIGURE 4-3:
Verify Configuration Bits
READ DATA EEPROM
FLOW
A configuration address may be read and output on
PGD via the 4-bit command, ‘1001’. Configuration data
is read and written in a byte-wise fashion, so it is not
necessary to merge two bytes into a word prior to a
compare. The result may then be immediately
compared to the appropriate configuration data in the
programmer’s memory for verification. Refer to
Section 4.1 “Read Code Memory, ID Locations and
Configuration Bits” for implementation details of
reading configuration data.
4.4
Start
Set
Address
Read
Byte
Read Data EEPROM Memory
Move to TABLAT
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair, EEADR:EEADRH) and
a data latch (EEDATA). Data EEPROM is read by loading EEADR:EEADRH with the desired memory location
and initiating a memory read by appropriately configuring the EECON1 register. The data will be loaded into
EEDATA, where it may be serially output on PGD via
the 4-bit command, ‘0010’ (Shift Out Data Holding
register). A delay of P6 must be introduced after the
falling edge of the 8th PGC of the operand to allow
PGD to transition from an input to an output. During this
time, PGC must be held low (see Figure 4-4).
Shift Out Data
No
Done
?
Yes
Done
The command sequence to read a single byte of data
is shown in Table 4-2.
TABLE 4-2:
READ DATA EEPROM MEMORY
4-Bit
Command
Data Payload
Core Instruction
Step 1: Direct access to data EEPROM.
0000
0000
9E A6
9C A6
BCF
BCF
EECON1, EEPGD
EECON1, CFGS
Step 2: Set the data EEPROM Address Pointer.
0000
0000
0000
0000
0E
6E
OE
6E
A9
AA
MOVLW
MOVWF
MOVLW
MOVWF
EEADR
EEADRH
BSF
EECON1, RD
Step 3: Initiate a memory read.
0000
80 A6
Step 4: Load data into the Serial Data Holding register.
0000
0000
0010
Note 1:
50 A8
6E F5
MOVF EEDATA, W, 0
MOVWF TABLAT
Shift Out Data(1)
The is undefined. The is the data.
DS39606E-page 24
2010 Microchip Technology Inc.
PIC18FXX80/XX85
FIGURE 4-4:
1
SHIFT OUT DATA HOLDING REGISTER TIMING (‘0010’)
2
3
4
1
2
3
4
5
6
7
9
8
10 11
12 13
14 15 16
1
2
3
4
PGC
P5
P6
P5A
P14
PGD
0
1
0
LSb 1
0
PGD = Input
4.5
Verify Data EEPROM
A data EEPROM address may be read via a sequence of
core instructions (4-bit command, ‘0000’) and then output on PGD via the 4-bit command, ‘0010’ (Shift Out
Data Holding register). The result may then be immediately compared to the appropriate data in the programmer’s memory for verification. Refer to Section 4.4
“Read Data EEPROM Memory” for implementation
details of reading data EEPROM.
4.6
Blank Check
The term “Blank Check” means to verify that the device
has no programmed memory cells. All memories must
be verified: code memory, data EEPROM, ID locations
and Configuration bits. The Device ID registers
(3FFFFEh:3FFFFFh) should be ignored.
A “blank” or “erased” memory cell will read as a ‘1’. So,
“Blank Checking” a device merely means to verify that
all bytes read as FFh, except the Configuration bits.
Unused (reserved) Configuration bits will read ‘0’ (programmed). Refer to Table 5-2 for blank configuration
expect data for the various PIC18FXX80/XX85
devices.
2010 Microchip Technology Inc.
2
3
4
5
6
MSb
n
n
n
n
Shift Data Out
Fetch Next
4-Bit Command
PGD = Output
PGD = Input
Given that “Blank Checking” is merely code and data
EEPROM verification with FFh expect data, refer to
Section 4.2 “Verify Code Memory and ID Locations”
and Section 4.4 “Read Data EEPROM Memory” for
implementation details.
FIGURE 4-5:
BLANK CHECK FLOW
Start
Blank Check Device
Is
Device
Blank?
Yes
Continue
No
Abort
DS39606E-page 25
PIC18FXX80/XX85
5.0
CONFIGURATION WORD
5.3
The PIC18FXX80/XX85 devices have several Configuration Words. These bits can be set or cleared to select
various device configurations. All other memory areas
should be programmed and verified prior to setting
Configuration Words. These bits may be read out
normally even after read or code-protected.
5.1
The LVP bit in Configuration register, CONFIG4L,
enables low-voltage ICSP programming. The LVP bit
defaults to a ‘1’ from the factory.
If Low-Voltage Programming mode is not used, the LVP
bit can be programmed to a ‘0’ and RB5/PGM becomes
a digital I/O pin. However, the LVP bit may only be programmed by entering the High-Voltage ICSP mode,
where MCLR/VPP is raised to VIHH. Once the LVP bit is
programmed to a ‘0’, only the High-Voltage ICSP mode
is available and only the High-Voltage ICSP mode can
be used to program the device.
ID Locations
A user may store identification information (ID) in eight
ID locations, mapped in 200000h:200007h. It is recommended that the Most Significant nibble of each ID be
0Fh. In doing so, if the user code inadvertently tries to
execute from the ID space, the ID data will execute as
a NOP.
5.2
Note 1: The normal ICSP mode is always available, regardless of the state of the LVP
bit, by applying VIHH to the MCLR/VPP
pin.
Device ID Word
2: While in Low-Voltage ICSP mode, the
RB5 pin can no longer be used as a
general purpose I/O.
The Device ID Word for the PIC18FXX80/XX85
devices is located at 3FFFFEh:3FFFFFh. These bits
may be used by the programmer to identify what device
type is being programmed and read out normally even
after code or read-protected.
TABLE 5-1:
Low-Voltage Programming
(LVP) Bit
DEVICE ID VALUES
Device ID Value
Device
DEVID2
DEVID1
PIC18F6585
0Ah
011x xxxx
PIC18F6680
0Ah
001x xxxx
PIC18F8585
0Ah
010x xxxx
PIC18F8680
0Ah
000x xxxx
DS39606E-page 26
2010 Microchip Technology Inc.
PIC18FXX80/XX85
TABLE 5-2:
PIC18FXX80/XX85 CONFIGURATION BITS AND DEVICE IDS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
CONFIG1H
—
—
OSCSEN
—
FOSC3
FOSC2
FOSC1
FOSC0
--1- 1111
300002h
CONFIG2L
—
—
—
—
BORV1
BORV0
---- 1111
300003h
CONFIG2H
—
—
—
WAIT
—
—
—
—
—
File Name
300001h
300004h(1) CONFIG3L
WDTPS3 WDTPS2 WDTPS1
BODEN
PWRTEN
WDTPS0
WDTEN
---1 1111
PM1
PM0
1--- --11
ECCPMX(3) CCP2MX
300005h
CONFIG3H MCLRE
—
—
—
—
—
300006h
CONFIG4L
—
—
—
—
LVP
—
STVREN
1--- -1-1
300008h
CONFIG5L
—
—
—
—
CP3(2)
CP2
CP1
CP0
---- 1111
300009h
CONFIG5H
CPD
CPB
—
—
—
—
—
—
11-- ----
30000Ah
CONFIG6L
—
—
—
—
WRT3(2)
WRT2
WRT1
WRT0
---- 1111
30000Bh
CONFIG6H
WRTD
WRTB
WRTC
—
—
—
—
—
111- ----
DEBUG
(2)
1--- --11
30000Ch
CONFIG7L
—
—
—
—
EBTR2
EBTR1
EBTR0
---- 1111
30000Dh
CONFIG7H
—
EBTRB
—
—
—
—
—
—
-1-- ----
3FFFFEh
DEVID1
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
Table 5-1
3FFFFFh
DEVID2
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
Table 5-1
Legend:
Note 1:
2:
3:
- = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Unimplemented in PIC18F6X8X devices; maintain this bit set.
Unimplemented in PIC18FX585 devices; maintain this bit set.
Reserved in PIC18F6X8X devices; maintain this bit set.
2010 Microchip Technology Inc.
EBTR3
DS39606E-page 27
PIC18FXX80/XX85
TABLE 5-3:
PIC18FXX80/XX85 CONFIGURATION BIT DESCRIPTIONS
Bit Name
Configuration
Bytes
Description
OSCEN
Low Power System Clock Option (Timer1) Enable bit
1 = Disabled
0 = Timer1 oscillator system clock option enabled
FOSC3:FOSC0
Oscillator Selection bits
1111 = RC oscillator w/OSC2 configured as RA6
1110 = HS oscillator w/software controlled PLL
1101 = EC oscillator with OSC2 configured as RA6 w/SW controlled PLL
1100 = EC oscillator with OSC2 configured as RA6 w/PLL enabled
1011 = Reserved; do not use
1010 = Reserved; do not use
1001 = Reserved; do not use
1000 = Reserved; do not use
0111 = RC oscillator w/OSC2 configured as RA6
0110 = HS oscillator w/PLL enabled
0101 = EC oscillator w/OSC2 configured as RA6
0100 = EC oscillator w/OSC2 configured as “divide by 4 clock output”
0011 = RC oscillator
0010 = HS oscillator
0001 = XT oscillator
0000 = LP oscillator
CONFIG1H
BORV1:BORV0
BOREN
Brown-out Reset Voltage bits
11 =VBOR set to 2.0V
10 =VBOR set to 2.7V
01 =VBOR set to 4.2V
00 =VBOR set to 4.5V
CONFIG2L
Brown-out Reset Enable bit
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
PWRTEN
Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTPS3:WDTPS0
Watchdog Timer Postscaler Select bits
1111 = 1:32768
1110 = 1:16384
1101 = 1:8192
1100 = 1:4096
1011 = 1:2048
1010 = 1:1024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
CONFIG2H
WDTEN
Note 1:
2:
3:
Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
Unimplemented in PIC18F6X8X (64-pin) devices; maintain this bit set.
Unimplemented in PIC18FX585 devices; maintain this bit set.
Reserved for PIC18F6X8X devices; maintain this bit set.
DS39606E-page 28
2010 Microchip Technology Inc.
PIC18FXX80/XX85
TABLE 5-3:
Bit Name
PIC18FXX80/XX85 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Configuration
Bytes
WAIT(1)
Description
External Bus Data Wait Enable bit
1 = Wait selections unavailable
0 = Wait selections determined by WAIT1:WAIT0 bits of MEMCOM register
PM1:PM0(1)
CONFIG3L
Processor Mode Select bits
11 = Microcontroller mode
10 = Microprocessor mode
01 = Microprocessor with Boot Block mode
00 = Extended Microcontroller mode
MCLRE
MCLR Enable bit
1 = MCLR pin enabled, RG5 disabled
0 = MCLR pin disabled, RG5 enabled
ECCPMX
CCP1 PWM Outputs P1B, P1C MUX bit (PIC18F8X8X devices only)(3)
1 = P1B, P1C are multiplexed with RE6, RE5
0 = P1B, P1C are multiplexed with RH7, RH6
CCP2MX
CONFIG3H
DEBUG
In Microcontroller mode:
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RE7
In Microprocessor, Microprocessor with Boot Block and Extended
Microcontroller modes (PIC18F8X8X devices only):
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
Background Debugger Enable bit
1 = Background debugger disabled (RB6, RB7 are I/O pins)
0 = Background debugger enabled (RB6, RB7 are ISCP™ pins)
LVP
CONFIG4L
Low-Voltage Programming Enable bit
1 = Low-voltage programming enabled
0 = Low-voltage programming disabled
STVREN
Stack Overflow/Underflow Reset Enable bit
1 = Stack overflow/underflow will cause Reset
0 = Stack overflow/underflow will not cause Reset
CP0
Code Protection bits (code memory area 0800h-3FFFh)
1 = Code memory not code-protected
0 = Code memory code-protected
CP1
Code Protection bits (code memory area 4000h-7FFFh)
1 = Code memory not code-protected
0 = Code memory code-protected
CP2
CONFIG5L
Code Protection bits (code memory area 8000h-0BFFFh)
1 = Code memory not code-protected
0 = Code memory code-protected
CP3(2)
Code Protection bits (code memory area 0C000h-0FFFFh)
1 = Code memory not code-protected
0 = Code memory code-protected
CPD
Code Protection bits (data EEPROM)
1 = Data EEPROM not code-protected
0 = Data EEPROM code-protected
CPB
Note 1:
2:
3:
CONFIG5H
Code Protection bits (boot block, memory area 0000h-07FFh)
1 = Boot block not code-protected
0 = Boot block code-protected
Unimplemented in PIC18F6X8X (64-pin) devices; maintain this bit set.
Unimplemented in PIC18FX585 devices; maintain this bit set.
Reserved for PIC18F6X8X devices; maintain this bit set.
2010 Microchip Technology Inc.
DS39606E-page 29
PIC18FXX80/XX85
TABLE 5-3:
Bit Name
PIC18FXX80/XX85 CONFIGURATION BIT DESCRIPTIONS (CONTINUED)
Configuration
Bytes
Description
WRT0
Table Write Protection bit (code memory area 0800h-3FFFh)
1 = Code memory not write-protected
0 = Code memory write-protected
WRT1
Table Write Protection bit (code memory area 4000h-7FFFh)
1 = Code memory not write-protected
0 = Code memory write-protected
CONFIG6L
WRT2
Table Write Protection bit (code memory area 8000h-0BFFFh)
1 = Code memory not write-protected
0 = Code memory write-protected
WRT3(2)
Table Write Protection bit (code memory area 0C000h-0FFFFh)
1 = Code memory not write-protected
0 = Code memory write-protected
WRTD
Table Write Protection bit (data EEPROM)
1 = Data EEPROM not write-protected
0 = Data EEPROM write-protected
WRTB
CONFIG6H
Table Write Protection bit (Boot Block, memory area 0000h-07FFh)
1 = Boot block not write-protected
0 = Boot block write-protected
WRTC
Table Write Protection bit (Configuration registers)
1 = Configuration registers not write-protected
0 = Configuration registers write-protected
EBTR0
Table Read Protection bit (code memory area 0800h-3FFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
EBTR1
Table Read Protection bit (code memory area 4000h-7FFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
CONFIG7L
EBTR2
EBTR3(2)
Table Read Protection bit (code memory area 8000h-0BFFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
Table Read Protection bit (code memory area 0C000h-0FFFFh)
1 = Code memory not protected from table reads executed in other blocks
0 = Code memory protected from table reads executed in other blocks
EBTRB
CONFIG7H
Table Read Protection bit (Boot Block, memory area 0000h-07FFh)
1 = Boot block not protected from table reads executed in other blocks
0 = Boot block protected from table reads executed in other blocks
DEV10:DEV3
DEVID2
Device ID bits
These bits are used with the DEV2:DEV0 bits in the DEVID1 register to
identify part number.
DEV2:DEV0
DEVID1
Device ID bits
These bits are used with the DEV10:DEV3 bits in the DEVID2 register to
identify part number.
REV4:REV0
Note 1:
2:
3:
These bits are used to indicate the revision of the device.
Unimplemented in PIC18F6X8X (64-pin) devices; maintain this bit set.
Unimplemented in PIC18FX585 devices; maintain this bit set.
Reserved for PIC18F6X8X devices; maintain this bit set.
DS39606E-page 30
2010 Microchip Technology Inc.
PIC18FXX80/XX85
5.4
Embedding Configuration Word
Information in the HEX File
To allow portability of code, a PIC18FXX80/XX85
programmer is required to read the Configuration Word
locations from the HEX file. If Configuration Word information is not present in the HEX file, then a simple
warning message should be issued. Similarly, while
saving a HEX file, all Configuration Word information
must be included. An option to not include the Configuration Word information may be provided. When
embedding Configuration Word information in the HEX
file, it should start at address 300000h.
Microchip Technology Inc. feels strongly that this
feature is important for the benefit of the end customer.
2010 Microchip Technology Inc.
5.5
Checksum Computation
The checksum is calculated by summing the following:
• The contents of all code memory locations
• The Configuration Word, appropriately masked
• ID locations
The Least Significant 16 bits of this sum are the
checksum.
Table 5-4 (pages 32 through 35) describes how to
calculate the checksum for each device.
Note:
The checksum calculation differs depending on the code-protect setting. Since the
code memory locations read out differently
depending on the code-protect setting, the
table describes how to manipulate the
actual code memory values to simulate
the values that would be read from a
protected device. When calculating a
checksum by reading a device, the entire
code memory can simply be read and
summed. The Configuration Word and ID
locations can always be read.
DS39606E-page 31
PIC18FXX80/XX85
TABLE 5-4:
Device
CHECKSUM COMPUTATION
Code-Protect
None
Boot Block
PIC18F6585
Legend:
0AAh at 0
and Max
Address
SUM(0000:07FFh) + SUM(0800:3FFFh) + SUM(4000:7FFFh) +
SUM(8000:0BFFFh) + (CFGW1L & 00h) + (CFGW1H & 2Fh) +
(CFGW2L & 0Fh) + (CFGW2H & 1Fh) + (CFGW3L & 00h) +
(CFGW3H & 80h) + (CFGW4L & 85h) + (CFGW4H & 00h) +
(CFGW5L & 07h) + (CFGW5H & 0C0h) + (CFGW6L & 07h) +
(CFGW6H & 0E0h) + (CFGW7L & 07h) + (CFGW7H & 40h)
0C357h
0C2ADh
SUM(0800:3FFFh) + SUM(4000:7FFFh) + SUM(8000:0BFFFh) +
(CFGW1L & 00h) + (CFGW1H & 2Fh) + (CFGW2L & 0Fh) +
(CFGW2H & 1Fh) + (CFGW3L & 00h) + (CFGW3H & 80h) +
(CFGW4L & 85h) + (CFGW4H & 00h) + (CFGW5L & 07h) +
(CFGW5H & 80h) + (CFGW6L & 07h) + (CFGW6H & 0E0h) +
(CFGW7L & 07h) + (CFGW7H & 40h) + SUM(IDs)
0BB32h
0BAE7h
Boot/
Block 0/
Block 1
SUM(8000:0BFFFh) + (CFGW1L & 00h) + (CFGW1H & 2Fh) +
(CFGW2L & 0Fh) + (CFGW2H & 1Fh) + (CFGW3L & 00h) +
(CFGW3H & 80h) + (CFGW4L & 85h) + (CFGW4H & 00h) +
(CFGW5L & 04h) + (CFGW5H & 80h) + (CFGW6L & 07h) +
(CFGW6H & 0E0h) + (CFGW7L & 07h) + (CFGW7H & 40h) +
SUM(IDs)
432Fh
42E4h
All
(CFGW1L & 00h) + (CFGW1H & 2Fh) + (CFGW2L & 0Fh) +
(CFGW2H & 1Fh) + (CFGW3L & 00h) + (CFGW3H & 80h) +
(CFGW4L & 85h) + (CFGW4H & 00h) + (CFGW5L & 00h) +
(CFGW5H & 00h) + (CFGW6L & 07h) + (CFGW6H & 0E0h) +
(CFGW7L & 07h) + (CFGW7H & 40h) + SUM(IDs)
02A6h
02B5h
Item
CFGW
SUM[a:b]
SUM_ID
+
&
DS39606E-page 32
Blank
Value
Checksum
Description
= Configuration Word
= Sum of locations, a to b inclusive
= Byte-wise sum of lower four bits of all customer ID locations
= Addition
= Bit-wise AND
2010 Microchip Technology Inc.
PIC18FXX80/XX85
TABLE 5-4:
Device
CHECKSUM COMPUTATION (CONTINUED)
0AAh at 0
and Max
Address
036Fh
02C5h
0FB47h
0FAEDh
SUM(8000:0BFFFh) + SUM(0C000:0FFFFh) + (CFGW1L & 00h) +
(CFGW1H & 2Fh) + (CFGW2L & 0Fh) + (CFGW2H & 1Fh) +
(CFGW3L & 00h) + (CFGW3H & 80h) + (CFGW4L & 85h) +
(CFGW4H & 00h) + (CFGW5L & 0Ch) + (CFGW5H & 80h) +
(CFGW6L & 0Fh) + (CFGW6H & 0E0h) + (CFGW7L & 0Fh) +
(CFGW7H & 40h) + SUM(IDs)
8344h
82EAh
(CFGW1L & 00h) + (CFGW1H & 2Fh) + (CFGW2L & 0Fh) +
(CFGW2H & 1Fh) + (CFGW3L & 00h) + (CFGW3H & 80h) +
(CFGW4L & 85h) + (CFGW4H & 00h) + (CFGW5L & 00h) +
(CFGW5H & 00h) + (CFGW6L & 0Fh) + (CFGW6H & 0E0h) +
(CFGW7L & 0Fh) + (CFGW7H & 40h) + SUM(IDs)
02B8h
02B3h
Checksum
None
SUM(0000:07FFh) + SUM(0800:3FFFh) + SUM(4000:7FFFh) +
SUM(8000:0BFFFh) + SUM(0C000:0FFFFh) + (CFGW1L & 00h) +
(CFGW1H & 2Fh) + (CFGW2L & 0Fh ) + (CFGW2H & 1Fh) +
(CFGW3L & 00h) + (CFGW3H & 80h) + (CFGW4L & 85h) +
(CFGW4H & 00h) + (CFGW5L & 0Fh) + (CFGW5H & 0C0h) +
(CFGW6L & 0Fh) + (CFGW6H & 0E0h) + (CFGW7L & 0Fh) +
(CFGW7H & 40h)
Boot Block
PIC18F6680
Boot/
Block1/
Block2
All
Legend:
Blank
Value
Code-Protect
Item
CFGW
SUM[a:b]
SUM_ID
+
&
SUM(0800:3FFFh) + SUM(4000:7FFFh) + SUM(8000:0BFFFh) +
SUM(0C000:0FFFFh) + (CFGW1L & 00h) + (CFGW1H & 2Fh) +
(CFGW2L & 0Fh) + (CFGW2H & 1Fh) + (CFGW3L & 00h) +
(CFGW3H & 80h) + (CFGW4L & 85h) + (CFGW4H & 00h) +
(CFGW5L & 0Fh) + (CFGW5H & 80h) + (CFGW6L & 0Fh) +
(CFGW6H & 0E0h) + (CFGW7L & 0Fh) + (CFGW7H & 40h) +
SUM(IDs)
Description
= Configuration Word
= Sum of locations, a to b inclusive
= Byte-wise sum of lower four bits of all customer ID locations
= Addition
= Bit-wise AND
2010 Microchip Technology Inc.
DS39606E-page 33
PIC18FXX80/XX85
TABLE 5-4:
Device
CHECKSUM COMPUTATION (CONTINUED)
Code-Protect
None
Boot Block
PIC18F8585
Legend:
0AAh at 0
and Max
Address
SUM(0000:07FFh) + SUM(0800:3FFFh) + SUM(4000:7FFFh) +
SUM(8000:0BFFFh) + (CFGW1L & 00h) + (CFGW1H & 2Fh) +
(CFGW2L & 0Fh) + (CFGW2H & 1Fh) + (CFGW3L & 83h) +
(CFGW3H & 80h) + (CFGW4L & 85h) + (CFGW4H & 00h) +
(CFGW5L & 07h) + (CFGW5H & 0C0h) + (CFGW6L & 07h) +
(CFGW6H & 0E0h) + (CFGW7L & 07h) + (CFGW7H & 40h)
0C3DAh
0C330h
SUM(0800:3FFFh) + SUM(4000:7FFFh) + SUM(8000:0BFFFh) +
(CFGW1L & 00h) + (CFGW1H & 2Fh) + (CFGW2L & 0Fh) +
(CFGW2H & 1Fh) + (CFGW3L & 83h) + (CFGW3H & 80h) +
(CFGW4L & 85h) + (CFGW4H & 00h) + (CFGW5L & 07h) +
(CFGW5H & 80h) + (CFGW6L & 07h) + (CFGW6H & 0E0h) +
(CFGW7L & 07h) + (CFGW7H & 40h) + SUM(IDs)
0BBC0h
0BB57h
Boot/
Block1/
Block2
SUM(8000:0BFFFh) + (CFGW1L & 00h) + (CFGW1H & 2Fh) +
(CFGW2L & 0Fh) + (CFGW2H & 1Fh) + (CFGW3L & 83h) +
(CFGW3H & 80h) + (CFGW4L & 85h) + (CFGW4H & 00h) +
(CFGW5L & 04h) + (CFGW5H & 80h) + (CFGW6L & 07h) +
(CFGW6H & 0E0h) + (CFGW7L & 07h) + (CFGW7H & 40h) +
SUM(IDs)
43BDh
4354h
All
(CFGW1L & 00h) + (CFGW1H & 2Fh) + (CFGW2L & 0Fh) +
(CFGW2H & 1Fh) + (CFGW3L & 83h) + (CFGW3H & 80h) +
(CFGW4L & 85h) + (CFGW4H & 00h) + (CFGW5L & 00h) +
(CFGW5H & 00h) + (CFGW6L & 07h) + (CFGW6H & 0E0h) +
(CFGW7L & 07h) + (CFGW7H & 40h) + SUM(IDs)
0339h
0325h
Item
CFGW
SUM[a:b]
SUM_ID
+
&
DS39606E-page 34
Blank
Value
Checksum
Description
= Configuration Word
= Sum of locations, a to b inclusive
= Byte-wise sum of lower four bits of all customer ID locations
= Addition
= Bit-wise AND
2010 Microchip Technology Inc.
PIC18FXX80/XX85
TABLE 5-4:
Device
CHECKSUM COMPUTATION (CONTINUED)
None
SUM(0000:07FFh) + SUM(0800:3FFFh) + SUM(4000:7FFFh) +
SUM(8000:0BFFFh) + SUM(0C000:0FFFFh) + (CFGW1L & 00h) +
(CFGW1H & 2Fh) + (CFGW2L & 0Fh) + (CFGW2H & 1Fh) +
(CFGW3L & 83h) + (CFGW3H & 80h) + (CFGW4L & 85h) +
(CFGW4H & 00h) + (CFGW5L & 0Fh) + (CFGW5H & 0C0h) +
(CFGW6L & 0Fh) + (CFGW6H & 0E0h) + (CFGW7L & 0Fh) +
(CFGW7H & 40h)
03F2h
0348h
SUM(0800:3FFFh) + SUM(4000:7FFFh) + SUM(8000:0BFFFh) +
SUM(0C000:0FFFFh) + (CFGW1L & 00h) + (CFGW1H & 2Fh) +
(CFGW2L & 0Fh) + (CFGW2H & 1Fh) + (CFGW3L & 83h) +
(CFGW3H & 80h) + (CFGW4L & 85h) + (CFGW4H & 00h) +
(CFGW5L & 0Fh) + (CFGW5H & 80h) + (CFGW6L & 0Fh) +
(CFGW6H & 0E0h) + (CFGW7L & 0Fh) + (CFGW7H & 40h) +
SUM(IDs)
0FBC6h
0FB6Ch
SUM(8000:0BFFFh) + SUM(0C000:0FFFFh) + (CFGW1L & 00h) +
(CFGW1H & 2Fh) + (CFGW2L & 0Fh) + (CFGW2H & 1Fh) +
(CFGW3L & 83h) + (CFGW3H & 80h) + (CFGW4L & 85h) +
(CFGW4H & 00h) + (CFGW5L & 0Ch) + (CFGW5H & 80h) +
(CFGW6L & 0Fh) + (CFGW6H & 0E0h) + (CFGW7L & 0Fh) +
(CFGW7H & 40h) + SUM(IDs)
83C3h
8369h
(CFGW1L & 00h) + (CFGW1H & 2Fh) + (CFGW2L & 0Fh) +
(CFGW2H & 1Fh) + (CFGW3L & 83h) + (CFGW3H & 80h) +
(CFGW4L & 85h) + (CFGW4H & 00h) + (CFGW5L & 00h) +
(CFGW5H & 00h) + (CFGW6L & 0Fh) + (CFGW6H & 0E0h) +
(CFGW7L & 0Fh) + (CFGW7H & 40h) + SUM(IDs)
0337h
0332h
PIC18F8680
Boot/
Block1/
Block2
All
5.6
0AAh at 0
and Max
Address
Checksum
Boot Block
Legend:
Blank
Value
Code-Protect
Item
CFGW
SUM[a:b]
SUM_ID
+
&
Description
= Configuration Word
= Sum of locations, a to b inclusive
= Byte-wise sum of lower four bits of all customer ID locations
= Addition
= Bit-wise AND
Embedding Data EEPROM
Information in the HEX File
To allow portability of code, a PIC18FXX80/XX85
programmer is required to read the data EEPROM
information from the HEX file. If data EEPROM information is not present, a simple warning message
2010 Microchip Technology Inc.
should be issued. Similarly, when saving a HEX file, all
data EEPROM information must be included. An option
to not include the data EEPROM information may be
provided. When embedding data EEPROM information
in the HEX file, it should start at address F00000h.
Microchip Technology Inc. believes that this feature is
important for the benefit of the end customer.
DS39606E-page 35
PIC18FXX80/XX85
6.0
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR
PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: 25C is recommended
Param
No.
Sym
Characteristic
Min
Max
Units
Conditions
D110
VIHH
High-Voltage Programming Voltage on
MCLR/VPP
9.00
13.25
V
D110A
VIHL
Low-Voltage Programming Voltage on
MCLR/VPP
2.00
5.50
V
D111
VDD
Supply Voltage During Programming
2.00
5.50
V
Normal programming
4.50
5.50
V
Bulk Erase operations
—
—
300
10
A
mA
V
D112
IPP
Programming Current on MCLR/VPP
D113
IDDP
Supply Current During Programming
D031
VIL
Input Low Voltage
VSS
0.2 VDD
D041
VIH
Input High Voltage
0.8 VDD
VDD
V
0.6
V
D080
VOL
Output Low Voltage
—
D090
VOH
Output High Voltage
VDD – 0.7
—
V
IOH = -3.0 mA @ 4.5V
D012
CIO
Capacitive Loading on I/O pin (PGD)
—
50
pF
To meet AC specifications
P1
Tr
MCLR/VPP Rise Time to Enter
Program/Verify mode
—
1.0
s
(Note 1)
P2
Tsclk
Serial Clock (PGC) Period
100
—
ns
P2A
TsclkL
Serial Clock (PGC) Low Time
40
—
ns
P2B
TsclkH
Serial Clock (PGC) High Time
40
—
ns
P3
Tset1
Input Data Setup Time to Serial Clock
15
—
ns
P4
Thld1
Input Data Hold Time from PGC
P5
Tdly1
Delay Between 4-Bit Command and
Command Operand
15
40
—
—
ns
ns
P5A
Tdly1a
Delay Between 4-Bit Command
Operand and Next 4-Bit Command
40
—
ns
P6
Tdly2
Delay Between Last PGC of
Command Byte to First PGC of Read
of Data Word
20
—
ns
P9
Tdly5
PGC High Time
(minimum programming time)
1
—
ms
P10
Tdly6
PGC Low Time After Programming
(high-voltage discharge time)
5
—
s
P11
Tdly7
Delay to Allow Self-Timed Data Write or
Bulk Erase to Occur
10
—
ms
P11A
Tdrwt
Data Write Polling Time
4
—
ms
IOL = 8.5 mA @ 4.5V
P12
Thld2
Input Data Hold Time from MCLR/VPP
2
—
s
P13
Tset2
VDD Setup Time to MCLR/VPP
100
—
ns
P14
Tvalid
Data Out Valid from PGC
10
—
ns
P15
Tset3
PGM Setup Time to MCLR/VPP
2
—
s
Note 1:
Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program
executions to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only)
+ 2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only)
where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the oscillator period.
For specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device.
DS39606E-page 36
2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2010 Microchip Technology Inc.
DS39606E-page 37
WORLDWIDE SALES AND SERVICE
AMERICAS
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Web Address:
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01/05/10
DS39606E-page 38
2010 Microchip Technology Inc.
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