PIC18F6520/8520/6620/
8620/6720/8720
64/80-Pin High-Performance, 256 Kbit to 1 Mbit
Enhanced Flash Microcontrollers with A/D
High-Performance RISC CPU:
Analog Features:
• C compiler optimized architecture/instruction set:
- Source code compatible with the PIC16 and
PIC17 instruction sets
• Linear program memory addressing to 128 Kbytes
• Linear data memory addressing to 3840 bytes
• 1 Kbyte of data EEPROM
• Up to 10 MIPs operation:
- DC – 40 MHz osc./clock input
- 4 MHz – 10 MHz osc./clock input with PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 31-level, software accessible hardware stack
• 8 x 8 Single Cycle Hardware Multiplier
• 10-bit, up to 16-channel Analog-to-Digital
Converter (A/D):
- Conversion available during Sleep
• Programmable 16-level Low-Voltage Detection
(LVD) module:
- Supports interrupt on Low-Voltage Detection
• Programmable Brown-out Reset (PBOR)
• Dual analog comparators:
- Programmable input/output configuration
Special Microcontroller Features:
• 100,000 erase/write cycle Enhanced Flash
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• 1 second programming time
• Flash/Data EEPROM Retention: > 40 years
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own On-Chip
RC Oscillator for reliable operation
• Programmable code protection
• Power saving Sleep mode
• Selectable oscillator options including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
• In-Circuit Serial Programming™ (ICSP™) via
two pins
• MPLAB® In-Circuit Debug (ICD) via two pins
External Memory Interface
(PIC18F8X20 Devices Only):
• Address capability of up to 2 Mbytes
• 16-bit interface
Peripheral Features:
•
•
•
•
•
•
•
•
•
High current sink/source 25 mA/25 mA
Four external interrupt pins
Timer0 module: 8-bit/16-bit timer/counter
Timer1 module: 16-bit timer/counter
Timer2 module: 8-bit timer/counter
Timer3 module: 16-bit timer/counter
Timer4 module: 8-bit timer/counter
Secondary oscillator clock option – Timer1/Timer3
Five Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution 100 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bit
• Master Synchronous Serial Port (MSSP) module
with two modes of operation:
- 3-wire SPI (supports all 4 SPI modes)
- I2C™ Master and Slave mode
• Two Addressable USART modules:
- Supports RS-485 and RS-232
• Parallel Slave Port (PSP) module
Program Memory
Device
CMOS Technology:
•
•
•
•
Data Memory
# Single-Word SRAM EEPROM I/O
Bytes
Instructions (bytes) (bytes)
Low-power, high-speed Flash technology
Fully static design
Wide operating voltage range (2.0V to 5.5V)
Industrial and Extended temperature ranges
10-bit
CCP
A/D
(PWM)
(ch)
MSSP
Max
Timers
Ext
OSC
USART
F
Master
8-bit/16-bit Bus
SPI
(MHz)
I2C
PIC18F6520
32K
16384
2048
1024
52
12
5
Y
Y
2
2/3
N
PIC18F6620
64K
32768
3840
1024
52
12
5
Y
Y
2
2/3
N
25
PIC18F6720 128K
65536
3840
1024
52
12
5
Y
Y
2
2/3
N
25
PIC18F8520
32K
16384
2048
1024
68
16
5
Y
Y
2
2/3
Y
40
PIC18F8620
64K
32768
3840
1024
68
16
5
Y
Y
2
2/3
Y
25
PIC18F8720 128K
65536
3840
1024
68
16
5
Y
Y
2
2/3
Y
25
2003-2013 Microchip Technology Inc.
40
DS39609C-page 1
PIC18F6520/8520/6620/8620/6720/8720
Pin Diagrams
Note 1:
RE5
RE6
RE7/CCP2(1)
RD0/PSP0
VDD
VSS
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
61
60
58
56
55
54
53
52
51
50
49
RD6/PSP6
RD7/PSP7
RE4
57
RE3
62
59
RE2/CS
64
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PIC18F6520
PIC18F6620
PIC18F6720
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
32
RA5/AN4/LVDIN
31
27
28
VDD
30
26
VSS
RB0/INT0
RB1/INT1
RC0/T1OSO/T13CKI
RC6/TX1/CK1
RC7/RX1/DT1
25
RA0/AN0
29
24
RA4/T0CKI
RC1/T1OSI/CCP2(1)
23
RA2/AN2/VREF-
RA1/AN1
20
AVSS
RA3/AN3/VREF+
21
22
19
AVDD
15
16
RF1/AN6/C2OUT
VSS
VDD
RF7/SS
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
48
2
3
4
5
6
7
8
9
10
11
12
13
14
17
18
RG2/RX2/DT2
RG3/CCP4
MCLR/VPP
RG4/CCP5
1
RF0/AN5
RE1/WR
RE0/RD
RG0/CCP3
RG1/TX2/CK2
63
64-Pin TQFP
CCP2 is multiplexed with RC1 when CCP2MX is set.
DS39609C-page 2
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
Pin Diagrams (Continued)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RH1/A17
RH0/A16
RE2/CS/AD10(3)
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/CCP2/AD15(2)
RD0/PSP0/AD0(3)
VDD
VSS
RD1/PSP1/AD1(3)
RD2/PSP2/AD2(3)
RD3/PSP3/AD3(3)
RD4/PSP4/AD4(3)
RD5/PSP5/AD5(3)
RD6/PSP6/AD6(3)
RD7/PSP7/AD7(3)
RJ0/ALE
RJ1/OE
80-Pin TQFP
RH2/A18
RH3/A19
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC18F8520
PIC18F8620
PIC18F8720
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RJ2/WRL
RJ3/WRH
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/CCP2(1)
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RJ7/UB
RJ6/LB
RH5/AN13
RH4/AN12
RF1/AN6/C2OUT
RF0/AN5
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1
RA0/AN0
VSS
VDD
RA5/AN4/LVDIN
RA4/T0CKI
RC1/T1OSI/CCP2(1)
RC0/T1OSO/T13CKI
RC6/TX1/CK1
RC7/RX1/DT1
RJ4/BA0
RJ5/CE
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RE1/WR/AD9(3)
RE0/RD/AD8(3)
RG0/CCP3
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4
MCLR/VPP
RG4/CCP5
VSS
VDD
RF7/SS
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RH7/AN15
RH6/AN14
1
2
Note 1:
2:
3:
CCP2 is multiplexed with RC1 when CCP2MX is set.
CCP2 is multiplexed by default with RE7 when the device is configured in Microcontroller mode.
PSP is available only in Microcontroller mode.
2003-2013 Microchip Technology Inc.
DS39609C-page 3
PIC18F6520/8520/6620/8620/6720/8720
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 21
3.0 Reset .......................................................................................................................................................................................... 29
4.0 Memory Organization ................................................................................................................................................................. 39
5.0 Flash Program Memory .............................................................................................................................................................. 61
6.0 External Memory Interface ......................................................................................................................................................... 71
7.0 Data EEPROM Memory ............................................................................................................................................................. 79
8.0 8 X 8 Hardware Multiplier ........................................................................................................................................................... 85
9.0 Interrupts .................................................................................................................................................................................... 87
10.0 I/O Ports ................................................................................................................................................................................... 103
11.0 Timer0 Module ......................................................................................................................................................................... 131
12.0 Timer1 Module ......................................................................................................................................................................... 135
13.0 Timer2 Module ......................................................................................................................................................................... 141
14.0 Timer3 Module ......................................................................................................................................................................... 143
15.0 Timer4 Module ......................................................................................................................................................................... 147
16.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 149
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 157
18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 197
19.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 213
20.0 Comparator Module.................................................................................................................................................................. 223
21.0 Comparator Voltage Reference Module ................................................................................................................................... 229
22.0 Low-Voltage Detect .................................................................................................................................................................. 233
23.0 Special Features of the CPU .................................................................................................................................................... 239
24.0 Instruction Set Summary .......................................................................................................................................................... 259
25.0 Development Support............................................................................................................................................................... 301
26.0 Electrical Characteristics .......................................................................................................................................................... 305
27.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 341
28.0 Packaging Information.............................................................................................................................................................. 355
Appendix A: Revision History............................................................................................................................................................. 361
Appendix B: Device Differences......................................................................................................................................................... 361
Appendix C: Conversion Considerations ........................................................................................................................................... 362
Appendix D: Migration from Mid-range to Enhanced Devices ........................................................................................................... 362
Appendix E: Migration from High-end to Enhanced Devices ............................................................................................................. 363
The Microchip Web Site ..................................................................................................................................................................... 375
Customer Change Notification Service .............................................................................................................................................. 375
Customer Support .............................................................................................................................................................................. 375
Reader Response .............................................................................................................................................................................. 376
PIC18F6520/8520/6620/8620/6720/8720 Product Identification System .......................................................................................... 377
DS39609C-page 4
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2003-2013 Microchip Technology Inc.
DS39609C-page 5
PIC18F6520/8520/6620/8620/6720/8720
NOTES:
DS39609C-page 6
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
1.0
DEVICE OVERVIEW
This document contains device specific information for
the following devices:
• PIC18F6520
• PIC18F8520
• PIC18F6620
• PIC18F8620
• PIC18F6720
• PIC18F8720
This family offers the same advantages of all PIC18
microcontrollers – namely, high computational
performance at an economical price – with the addition of
high endurance Enhanced Flash program memory. The
PIC18FXX20 family also provides an enhanced range of
program memory options and versatile analog features
that make it ideal for complex, high-performance
applications.
1.1
1.1.1
Key Features
EXPANDED MEMORY
The PIC18FXX20 family introduces the widest range of
on-chip, Enhanced Flash program memory available
on PIC® microcontrollers – up to 128 Kbyte (or 65,536
words), the largest ever offered by Microchip. For users
with more modest code requirements, the family also
includes members with 32 Kbyte or 64 Kbyte.
Other memory features are:
• Data RAM and Data EEPROM: The
PIC18FXX20 family also provides plenty of room
for application data. Depending on the device,
either 2048 or 3840 bytes of data RAM are
available. All devices have 1024 bytes of data
EEPROM for long-term retention of nonvolatile
data.
• Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.
1.1.2
EXTERNAL MEMORY INTERFACE
In the event that 128 Kbytes of program memory is
inadequate for an application, the PIC18F8X20
members of the family also implement an External
Memory Interface. This allows the controller’s internal
program counter to address a memory space of up to
2 Mbytes, permitting a level of data access that few
8-bit devices can claim.
2003-2013 Microchip Technology Inc.
With the addition of new operating modes, the External
Memory Interface offers many new options, including:
• Operating the microcontroller entirely from external
memory
• Using combinations of on-chip and external
memory, up to the 2-Mbyte limit
• Using external Flash memory for reprogrammable
application code, or large data tables
• Using external RAM devices for storing large
amounts of variable data
1.1.3
EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members, or even
jumping from 64-pin to 80-pin devices.
1.1.4
OTHER SPECIAL FEATURES
• Communications: The PIC18FXX20 family
incorporates a range of serial communications
peripherals, including 2 independent USARTs and
a Master SSP module, capable of both SPI and
I2C (Master and Slave) modes of operation. For
PIC18F8X20 devices, one of the general purpose
I/O ports can be reconfigured as an 8-bit Parallel
Slave Port for direct processor-to-processor
communications.
• CCP Modules: All devices in the family
incorporate five Capture/Compare/PWM modules
to maximize flexibility in control applications. Up
to four different time bases may be used to
perform several different operations at once.
• Analog Features: All devices in the family
feature 10-bit A/D converters, with up to 16 input
channels, as well as the ability to perform
conversions during Sleep mode. Also included
are dual analog comparators with programmable
input and output configuration, a programmable
Low-Voltage Detect module and a programmable
Brown-out Reset module.
• Self-programmability: These devices can write
to their own program memory spaces under internal software control. By using a bootloader routine
located in the protected Boot Block at the top of
program memory, it becomes possible to create
an application that can update itself in the field.
DS39609C-page 7
PIC18F6520/8520/6620/8620/6720/8720
1.2
Details on Individual Family
Members
3.
4.
The PIC18FXX20 devices are available in 64-pin and
80-pin packages. They are differentiated from each
other in five ways:
1.
2.
5.
Flash program memory (32 Kbytes for
PIC18FX520
devices,
64 Kbytes
for
PIC18FX620 devices and 128 Kbytes for
PIC18FX720 devices)
Data RAM (2048 bytes for PIC18FX520
devices, 3840 bytes for PIC18FX620 and
PIC18FX720 devices)
TABLE 1-1:
A/D channels (12 for PIC18F6X20 devices,
16 for PIC18F8X20)
I/O pins (52 on PIC18F6X20 devices, 68 on
PIC18F8X20)
External program memory interface (present
only on PIC18F8X20 devices)
All other features for devices in the PIC18FXX20 family
are identical. These are summarized in Table 1-1.
Block diagrams of the PIC18F6X20 and PIC18F8X20
devices are provided in Figure 1-1 and Figure 1-2,
respectively. The pinouts for these device families are
listed in Table 1-2.
PIC18FXX20 DEVICE FEATURES
Features
Operating Frequency
PIC18F6520
PIC18F6620
PIC18F6720
PIC18F8520
PIC18F8620
PIC18F8720
DC – 40 MHz
DC – 25 MHz
DC – 25 MHz
DC – 40 MHz
DC – 25 MHz
DC – 25 MHz
Program Memory
(Bytes)
32K
64K
128K
32K
64K
128K
Program Memory
(Instructions)
16384
32768
65536
16384
32768
65536
Data Memory
(Bytes)
2048
3840
3840
2048
3840
3840
Data EEPROM
Memory (Bytes)
1024
1024
1024
1024
1024
1024
External Memory
Interface
No
No
No
Yes
Yes
Yes
17
17
Interrupt Sources
I/O Ports
17
Ports A, B, C,
D, E, F, G
Ports A, B, C, D, Ports A, B, C, D,
E, F, G
E, F, G
18
18
18
Ports A, B, C,
D, E, F, G, H, J
Ports A, B, C,
D, E, F, G, H, J
Ports A, B, C,
D, E, F, G, H, J
Timers
5
5
5
5
5
5
Capture/Compare/
PWM Modules
5
5
5
5
5
5
MSSP,
Addressable
USART (2)
MSSP,
Addressable
USART (2)
MSSP,
Addressable
USART (2)
MSSP,
Addressable
USART (2)
MSSP,
Addressable
USART (2)
MSSP,
Addressable
USART (2)
Serial Communications
Parallel Communications
10-bit Analog-to-Digital
Module
Resets (and Delays)
PSP
PSP
PSP
PSP
PSP
PSP
12 input
channels
12 input
channels
12 input
channels
16 input
channels
16 input
channels
16 input
channels
POR, BOR,
POR, BOR,
RESET
RESET
Instruction,
Instruction,
Stack Full,
Stack Full,
Stack Underflow Stack Underflow
(PWRT, OST)
(PWRT, OST)
POR, BOR,
POR, BOR,
POR, BOR,
POR, BOR,
RESET
RESET
RESET
RESET
Instruction,
Instruction,
Instruction,
Instruction,
Stack Full,
Stack Full,
Stack Full,
Stack Full,
Stack Underflow Stack Underflow Stack Underflow Stack Underflow
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
Programmable
Low-Voltage Detect
Yes
Yes
Yes
Yes
Yes
Yes
Programmable
Brown-out Reset
Yes
Yes
Yes
Yes
Yes
Yes
77 Instructions
77 Instructions
77 Instructions
77 Instructions
77 Instructions
77 Instructions
64-pin TQFP
64-pin TQFP
64-pin TQFP
80-pin TQFP
80-pin TQFP
80-pin TQFP
Instruction Set
Package
DS39609C-page 8
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 1-1:
PIC18F6X20 BLOCK DIAGRAM
Data Bus
21
Table Pointer
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/LVDIN
RA6
Data Latch
8
21
PORTA
8
Data RAM
inc/dec logic
Address Latch
21
PCLATU PCLATH
PCU PCH PCL
Program Counter
12
4
4
Bank0, F
FSR0
FSR1
FSR2
31 Level Stack
Program Memory
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
Address
BSR
Address Latch
PORTB
12
12
Data Latch
inc/dec
logic
Decode
Table Latch
PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
8
16
ROM Latch
IR
8
PORTD
PRODH PRODL
Instruction
Decode &
Control
OSC2/CLKO
OSC1/CLKI
RD7/PSP7:RD0/PSP0
8 x 8 Multiply
8
3
WREG
8
BITOP
8
Power-up
Timer
Timing
Generation
Oscillator
Start-up Timer
Precision
Band Gap
Reference
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
PORTE
8
8
ALU
8
RE0/RD
RE1/WR
RE2/CS
RE3
RE4
RE5
RE6
RE7/CCP2
PORTF
RF0/AN5
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CVREF
RF6/AN11
RF7/SS
MCLR/VPP VDD, VSS
PORTG
Synchronous
Serial Port
USART2
USART1
BOR
LVD
Timer0
Timer1
Timer2
Timer3
Timer4
Comparator
CCP1
CCP2
CCP3
CCP4
CCP5
2003-2013 Microchip Technology Inc.
RG0/CCP3
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4
RG4/CCP5
Data
EEPROM
10-bit
A/D
DS39609C-page 9
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 1-2:
PIC18F8X20 BLOCK DIAGRAM
Data Bus
21
Table Pointer
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/LVDIN
RA6
Data Latch
8
21
PORTA
8
Data RAM
inc/dec logic
System Bus Interface
Address Latch
21
PCLATU PCLATH
PCU PCH PCL
Program Counter
12
4
4
Bank0, F
FSR0
FSR1
FSR2
31 Level Stack
Program Memory
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/CCP2
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
Address
BSR
Address Latch
PORTB
12
12
PORTC
Data Latch
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
inc/dec
logic
Decode
Table Latch
8
16
ROM Latch
IR
AD15:AD0, A19:A16(1)
PORTD
RD7/PSP7/AD7:
RD0/PSP0/AD0
8
PORTE
PRODH PRODL
Instruction
Decode &
Control
OSC2/CLKO
OSC1/CLKI
RE0/RD/AD8
RE1/WR/AD9
RE2/CS/AD10
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/CCP2/AD15
8 x 8 Multiply
8
3
WREG
8
BITOP
8
Power-up
Timer
Timing
Generation
Oscillator
Start-up Timer
Precision
Band Gap
Reference
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
8
8
PORTF
RF0/AN5
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CVREF
RF6/AN11
RF7/SS
ALU
8
PORTG
RG0/CCP3
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4
RG4/CCP5
MCLR/VPP VDD, VSS
PORTH
Synchronous
Serial Port
USART2
USART1
RH3/AD19:RH0/AD16
Data
EEPROM
RH7/AN15:RH4/AN12
PORTJ
BOR
LVD
Timer0
Timer1
Timer2
Timer3
Timer4
Comparator
CCP1
CCP2
CCP3
CCP4
CCP5
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
10-bit
A/D
Note 1: External memory interface pins are physically multiplexed with PORTD (AD7:AD0), PORTE (AD15:AD8) and PORTH (A19:A16).
DS39609C-page 10
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
PIC18FXX20 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
MCLR/VPP
Pin
PIC18F6X20 PIC18F8X20 Type
7
9
I
MCLR
ST
P
VPP
OSC1/CLKI
OSC1
Buffer
Type
39
49
I
CMOS/ST
I
CMOS
O
—
CLKO
O
—
RA6
I/O
TTL
CLKI
OSC2/CLKO/RA6
OSC2
40
50
Description
Master Clear (input) or programming
voltage (output).
Master Clear (Reset) input. This pin is
an active-low Reset to the device.
Programming voltage input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock
source input. ST buffer when configured
in RC mode; otherwise CMOS.
External clock source input. Always
associated with pin function OSC1
(see OSC1/CLKI, OSC2/CLKO pins).
Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or resonator in
Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO,
which has 1/4 the frequency of OSC1
and denotes the instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
2003-2013 Microchip Technology Inc.
DS39609C-page 11
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin
Type
PIC18F6X20 PIC18F8X20
Buffer
Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
24
RA1/AN1
RA1
AN1
23
RA2/AN2/VREFRA2
AN2
VREF-
22
RA3/AN3/VREF+
RA3
AN3
VREF+
21
RA4/T0CKI
RA4
28
30
RA6
27
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
I/O
ST/OD
I
ST
Digital I/O – Open-drain when
configured as output.
Timer0 external clock input.
I/O
I
I
TTL
Analog
Analog
29
28
27
34
T0CKI
RA5/AN4/LVDIN
RA5
AN4
LVDIN
I/O
I
33
Digital I/O.
Analog input 4.
Low-Voltage Detect input.
See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
DS39609C-page 12
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin
Type
PIC18F6X20 PIC18F8X20
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB
can be software programmed for internal
weak pull-ups on all inputs.
RB0/INT0
RB0
INT0
48
RB1/INT1
RB1
INT1
47
RB2/INT2
RB2
INT2
46
RB3/INT3/CCP2
RB3
INT3
CCP2(1)
45
RB4/KBI0
RB4
KBI0
44
RB5/KBI1/PGM
RB5
KBI1
PGM
43
RB6/KBI2/PGC
RB6
KBI2
PGC
42
RB7/KBI3/PGD
RB7
KBI3
PGD
37
58
I/O
I
TTL
ST
Digital I/O.
External interrupt 0.
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
I/O
I/O
I/O
TTL
ST
ST
Digital I/O.
External interrupt 3.
Capture2 input, Compare2 output,
PWM2 output.
I/O
I
TTL
ST
Digital I/O.
Interrupt-on-change pin.
I/O
I
I/O
TTL
ST
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP Programming enable
pin.
I/O
I
I/O
TTL
ST
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and
ICSP programming clock.
I/O
I/O
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and
ICSP programming data.
57
56
55
54
53
52
47
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
2003-2013 Microchip Technology Inc.
DS39609C-page 13
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin
Type
PIC18F6X20 PIC18F8X20
Buffer
Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
30
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(2)
29
RC2/CCP1
RC2
CCP1
33
RC3/SCK/SCL
RC3
SCK
34
36
35
RC5/SDO
RC5
SDO
36
RC6/TX1/CK1
RC6
TX1
CK1
31
RC7/RX1/DT1
RC7
RX1
DT1
32
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture2 input/Compare2 output/
PWM2 output.
I/O
I/O
ST
ST
Digital I/O.
Capture1 input/Compare1 output/
PWM1 output.
I/O
I/O
ST
ST
I/O
ST
Digital I/O.
Synchronous serial clock input/output
for SPI mode.
Synchronous serial clock input/output
for I2C mode.
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
ST
—
Digital I/O.
SPI data out.
I/O
O
I/O
ST
—
ST
Digital I/O.
USART 1 asynchronous transmit.
USART 1 synchronous clock
(see RX1/DT1).
I/O
I
I/O
ST
ST
ST
Digital I/O.
USART 1 asynchronous receive.
USART 1 synchronous data
(see TX1/CK1).
35
43
44
SCL
RC4/SDI/SDA
RC4
SDI
SDA
I/O
O
I
45
46
37
38
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
DS39609C-page 14
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin
Type
PIC18F6X20 PIC18F8X20
Buffer
Type
Description
PORTD is a bidirectional I/O port. These
pins have TTL input buffers when external
memory is enabled.
RD0/PSP0/AD0
RD0
PSP0
AD0(3)
58
RD1/PSP1/AD1
RD1
PSP1
AD1(3)
55
RD2/PSP2/AD2
RD2
PSP2
AD2(3)
54
RD3/PSP3/AD3
RD3
PSP3
AD3(3)
53
RD4/PSP4/AD4
RD4
PSP4
AD4(3)
52
RD5/PSP5/AD5
RD5
PSP5
AD5(3)
51
RD6/PSP6/AD6
RD6
PSP6
AD6(3)
50
RD7/PSP7/AD7
RD7
PSP7
AD7(3)
49
72
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 0.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 1.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 2.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 3.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 4.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 5.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 6.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 7.
69
68
67
66
65
64
63
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
2003-2013 Microchip Technology Inc.
DS39609C-page 15
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin
Type
PIC18F6X20 PIC18F8X20
Buffer
Type
Description
PORTE is a bidirectional I/O port.
RE0/RD/AD8
RE0
RD
2
4
AD8(3)
RE1/WR/AD9
RE1
WR
1
64
RE3/AD11
RE3
AD11(3)
RE4/AD12
RE4
AD12
62
RE5/AD13
RE5
AD13(3)
61
RE6/AD14
RE6
AD14(3)
60
RE7/CCP2/AD15
RE7
CCP2(1,4)
59
AD15(3)
Digital I/O.
Read control for Parallel Slave Port
(see WR and CS pins).
External memory address/data 8.
I/O
TTL
I/O
I
ST
TTL
I/O
TTL
I/O
I
ST
TTL
I/O
TTL
Digital I/O.
Chip select control for Parallel Slave
Port (see RD and WR).
External memory address/data 10.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 11.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 12.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 13.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 14.
I/O
I/O
ST
ST
I/O
TTL
Digital I/O.
Capture2 input/Compare2 output/
PWM2 output.
External memory address/data 15.
Digital I/O.
Write control for Parallel Slave Port
(see CS and RD pins).
External memory address/data 9.
78
AD10(3)
63
ST
TTL
3
AD9(3)
RE2/CS/AD10
RE2
CS
I/O
I
77
76
75
74
73
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
DS39609C-page 16
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin
Type
PIC18F6X20 PIC18F8X20
Buffer
Type
Description
PORTF is a bidirectional I/O port.
RF0/AN5
RF0
AN5
18
RF1/AN6/C2OUT
RF1
AN6
C2OUT
17
RF2/AN7/C1OUT
RF2
AN7
C1OUT
16
RF3/AN8
RF1
AN8
15
RF4/AN9
RF1
AN9
14
RF5/AN10/CVREF
RF1
AN10
CVREF
13
RF6/AN11
RF6
AN11
12
RF7/SS
RF7
SS
11
24
I/O
I
ST
Analog
Digital I/O.
Analog input 5.
I/O
I
O
ST
Analog
ST
Digital I/O.
Analog input 6.
Comparator 2 output.
I/O
I
O
ST
Analog
ST
Digital I/O.
Analog input 7.
Comparator 1 output.
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 10.
Comparator VREF output.
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
I/O
I
ST
TTL
23
18
17
16
15
14
13
Digital I/O.
SPI slave select input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
2003-2013 Microchip Technology Inc.
DS39609C-page 17
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin
Type
PIC18F6X20 PIC18F8X20
Buffer
Type
Description
PORTG is a bidirectional I/O port.
RG0/CCP3
RG0
CCP3
3
RG1/TX2/CK2
RG1
TX2
CK2
4
RG2/RX2/DT2
RG2
RX2
DT2
5
RG3/CCP4
RG3
CCP4
6
RG4/CCP5
RG4
CCP5
8
5
I/O
I/O
ST
ST
Digital I/O.
Capture3 input/Compare3 output/
PWM3 output.
I/O
O
I/O
ST
—
ST
Digital I/O.
USART 2 asynchronous transmit.
USART 2 synchronous clock
(see RX2/DT2).
I/O
I
I/O
ST
ST
ST
Digital I/O.
USART 2 asynchronous receive.
USART 2 synchronous data
(see TX2/CK2).
I/O
I/O
ST
ST
Digital I/O.
Capture4 input/Compare4 output/
PWM4 output.
I/O
I/O
ST
ST
Digital I/O.
Capture5 input/Compare5 output/
PWM5 output.
6
7
8
10
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
DS39609C-page 18
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin
Type
PIC18F6X20 PIC18F8X20
Buffer
Type
Description
PORTH is a bidirectional I/O port(5).
RH0/A16
RH0
A16
—
RH1/A17
RH1
A17
—
RH2/A18
RH2
A18
—
RH3/A19
RH3
A19
—
RH4/AN12
RH4
AN12
—
RH5/AN13
RH5
AN13
—
RH6/AN14
RH6
AN14
—
RH7/AN15
RH7
AN15
—
79
I/O
O
ST
TTL
Digital I/O.
External memory address 16.
I/O
O
ST
TTL
Digital I/O.
External memory address 17.
I/O
O
ST
TTL
Digital I/O.
External memory address 18.
I/O
O
ST
TTL
Digital I/O.
External memory address 19.
I/O
I
ST
Analog
Digital I/O.
Analog input 12.
I/O
I
ST
Analog
Digital I/O.
Analog input 13.
I/O
I
ST
Analog
Digital I/O.
Analog input 14.
I/O
I
ST
Analog
Digital I/O.
Analog input 15.
80
1
2
22
21
20
19
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
2003-2013 Microchip Technology Inc.
DS39609C-page 19
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin
Type
PIC18F6X20 PIC18F8X20
Buffer
Type
Description
PORTJ is a bidirectional I/O port(5).
RJ0/ALE
RJ0
ALE
—
RJ1/OE
RJ1
OE
—
RJ2/WRL
RJ2
WRL
—
RJ3/WRH
RJ3
WRH
—
RJ4/BA0
RJ4
BA0
—
RJ5/CE
RJ5
CE
—
RJ6/LB
RJ6
LB
—
RJ7/UB
RJ7
UB
—
62
I/O
O
ST
TTL
Digital I/O.
External memory address latch enable.
I/O
O
ST
TTL
Digital I/O.
External memory output enable.
I/O
O
ST
TTL
Digital I/O.
External memory write low control.
I/O
O
ST
TTL
Digital I/O.
External memory write high control.
I/O
O
ST
TTL
Digital I/O.
External memory Byte Address 0 control.
I/O
O
ST
TTL
Digital I/O.
External memory chip enable control.
I/O
O
ST
TTL
Digital I/O.
External memory low byte select.
I/O
O
ST
TTL
Digital I/O.
External memory high byte select.
61
60
59
39
40
41
42
VSS
9, 25,
41, 56
11, 31,
51, 70
P
—
Ground reference for logic and I/O pins.
VDD
10, 26,
38, 57
12, 32,
48, 71
P
—
Positive supply for logic and I/O pins.
AVSS(6)
20
26
P
—
Ground reference for analog modules.
AVDD(6)
19
25
P
—
Positive supply for analog modules.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
DS39609C-page 20
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
2.0
OSCILLATOR
CONFIGURATIONS
2.1
Oscillator Types
TABLE 2-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Ranges Tested:
Mode
The PIC18FXX20 devices can be operated in eight
different oscillator modes. The user can program three
configuration bits (FOSC2, FOSC1 and FOSC0) to
select one of these eight modes:
1.
2.
3.
4.
LP
XT
HS
HS+PLL
5.
6.
RC
RCIO
7.
8.
EC
ECIO
2.2
Low-Power Crystal
Crystal/Resonator
High-Speed Crystal/Resonator
High-Speed Crystal/Resonator
with PLL enabled
External Resistor/Capacitor
External Resistor/Capacitor with
I/O pin enabled
External Clock
External Clock with I/O pin
enabled
In XT, LP, HS or HS+PLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
The PIC18FXX20 oscillator design requires the use of
a parallel cut crystal.
Use of a series cut crystal may give a frequency out of the crystal manufacturer’s
specifications.
FIGURE 2-1:
C1(1)
C2
XT
455 kHz
68-100 pF
68-100 pF
2.0 MHz
15-68 pF
15-68 pF
4.0 MHz
15-68 pF
15-68 pF
HS
8.0 MHz
10-68 pF
10-68 pF
16.0 MHz
10-22 pF
10-22 pF
These values are for design guidance only.
See notes following this table.
Resonators Used:
2.0 MHz Murata Erie CSA2.00MG
0.5%
4.0 MHz Murata Erie CSA4.00MG
0.5%
8.0 MHz Murata Erie CSA8.00MT
0.5%
16.0 MHz Murata Erie CSA16.00MX
0.5%
All resonators used did not have built-in capacitors.
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use high
gain HS mode, try a lower frequency
resonator, or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components,
or
verify
oscillator
performance.
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
CONFIGURATION)
OSC1
XTAL
OSC2
To
Internal
Logic
RF(3)
Sleep
RS(2)
C2(1)
C1
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
Crystal Oscillator/Ceramic
Resonators
Note:
Freq
PIC18FXX20
Note 1:
See Table 2-1 and Table 2-2 for recommended
values of C1 and C2.
2:
A series resistor (RS) may be required for AT
strip cut crystals.
3:
RF varies with the oscillator mode chosen.
2003-2013 Microchip Technology Inc.
DS39609C-page 21
PIC18F6520/8520/6620/8620/6720/8720
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
FIGURE 2-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC CONFIGURATION)
Ranges Tested:
Mode
Freq
LP
32 kHz
200 kHz
XT
1 MHz
4 MHz
HS
C1
C2
15-22 pF
15-22 pF
15-22 pF
15-22 pF
8 MHz
15-22 pF
15-22 pF
PIC18FXX20
OSC2
Open
2.3
4 MHz
OSC1
Clock from
Ext. System
RC Oscillator
See the notes following this table for additional
information.
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit, due
to normal process parameter variation. Furthermore,
the difference in lead frame capacitance between package types will also affect the oscillation frequency,
especially for low CEXT values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 2-3 shows how the
R/C combination is connected.
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
20 MHz
Capacitor values are for design guidance only.
These capacitors were tested with the above crystal
frequencies for basic start-up and operation. These
values are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
3: Since each resonator/crystal has its
own characteristics, the user should
consult the resonator/crystal manufacturer for appropriate values of external
components,
or
verify
oscillator
performance.
4: RS may be required to avoid overdriving
crystals with low drive level specification.
5: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
An external clock source may also be connected to the
OSC1 pin in the HS, XT and LP modes, as shown in
Figure 2-2.
DS39609C-page 22
FIGURE 2-3:
RC OSCILLATOR MODE
VDD
REXT
OSC1
Internal
Clock
CEXT
PIC18FXX20
VSS
FOSC/4
Recommended values:
OSC2/CLKO
3 k REXT 100 k
CEXT > 20 pF
The RCIO Oscillator mode functions like the RC mode,
except that the OSC2 pin becomes an additional
general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
2.4
FIGURE 2-5:
External Clock Input
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is a maximum
1.5 s start-up required after a Power-on Reset, or
wake-up from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)
OSC1
Clock from
Ext. System
PIC18FXX20
OSC2
FOSC/4
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.
EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
OSC1
Clock from
Ext. System
PIC18FXX20
RA6
2.5
I/O (OSC2)
HS/PLL
A Phase Locked Loop circuit (PLL) is provided as a
programmable option for users that want to multiply the
frequency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high-frequency crystals.
The PLL is one of the modes of the FOSC configuration bits. The oscillator mode is specified during
device programming.
The PLL can only be enabled when the oscillator configuration bits are programmed for HS mode. If they are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1. Also, PLL operation cannot be changed “onthe-fly”. To enable or disable it, the controller must
either cycle through a Power-on Reset, or switch the
clock source from the main oscillator to the Timer1
oscillator and back again. See Section 2.6 “Oscillator
Switching Feature” for details on oscillator switching.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called TPLL.
FIGURE 2-6:
PLL BLOCK DIAGRAM
(from Configuration
bit Register)
HS Osc
PLL Enable
Phase
Comparator
OSC2
Crystal
Osc
FIN
FOUT
Loop
Filter
VCO
OSC1
2003-2013 Microchip Technology Inc.
Divide by 4
MUX
SYSCLK
DS39609C-page 23
PIC18F6520/8520/6620/8620/6720/8720
2.6
Oscillator Switching Feature
execution mode. Figure 2-7 shows a block diagram of
the system clock sources. The clock switching feature
is enabled by programming the Oscillator Switching
Enable (OSCSEN) bit in Configuration Register 1H to a
‘0’. Clock switching is disabled in an erased device.
See Section 12.0 “Timer1 Module” for further details
of the Timer1 oscillator. See Section 23.0 “Special
Features of the CPU” for Configuration register
details.
The PIC18FXX20 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low-frequency clock source.
For the PIC18FXX20 devices, this alternate clock
source is the Timer1 oscillator. If a low-frequency
crystal (32 kHz, for example) has been attached to the
Timer1 oscillator pins and the Timer1 oscillator has
been enabled, the device can switch to a low-power
FIGURE 2-7:
DEVICE CLOCK SOURCES
PIC18FXX20
Main Oscillator
OSC2
4 x PLL
Sleep
Timer1 Oscillator
TSCLK
TT1P
T1OSO
T1OSI
MUX
TOSC
OSC1
TOSC/4
T1OSCEN
Enable
Oscillator
Clock
Source
Clock Source Option
for other Modules
DS39609C-page 24
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
2.6.1
SYSTEM CLOCK SWITCH BIT
Note:
The system clock source switching is performed under
software control. The system clock switch bit, SCS
(OSCCON), controls the clock switching. When the
SCS bit is ‘0’, the system clock source comes from the
main oscillator that is selected by the FOSC configuration bits in Configuration Register 1H. When the SCS
bit is set, the system clock source will come from the
Timer1 oscillator. The SCS bit is cleared on all forms of
Reset.
REGISTER 2-1:
The Timer1 oscillator must be enabled
and operating to switch the system clock
source. The Timer1 oscillator is enabled
by setting the T1OSCEN bit in the Timer1
Control register (T1CON). If the Timer1
oscillator is not enabled, then any write to
the SCS bit will be ignored (SCS bit forced
cleared) and the main oscillator will
continue to be the system clock source.
OSCCON REGISTER
U-0
—
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
SCS
bit 0
bit 7-1 Unimplemented: Read as ‘0’
bit 0
SCS: System Clock Switch bit
When OSCSEN Configuration bit = 0 and T1OSCEN bit is set:
1 = Switch to Timer1 oscillator/clock pin
0 = Use primary oscillator/clock input pin
When OSCSEN and T1OSCEN are in other states:
Bit is forced clear.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 25
PIC18F6520/8520/6620/8620/6720/8720
2.6.2
OSCILLATOR TRANSITIONS
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in Figure 2-8.
The Timer1 oscillator is assumed to be running all the
time. After the SCS bit is set, the processor is frozen at
the next occurring Q1 cycle. After eight synchronization
cycles are counted from the Timer1 oscillator, operation
resumes. No additional delays are required after the
synchronization cycles.
PIC18FXX20 devices contain circuitry to prevent
“glitches” when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to. This
ensures that the new clock source is stable and that its
pulse width will not be less than the shortest pulse
width of the two clock sources.
FIGURE 2-8:
TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1 Q2
Q3 Q4
Q1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
TT1P
1
T1OSI
2
3
4
5
6
7
8
TSCS
OSC1
Internal
System
Clock
TOSC
TDLY
SCS
(OSCCON)
Program
Counter
PC
PC + 2
PC + 4
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
FIGURE 2-9:
If the main oscillator is configured for an external
crystal (HS, XT, LP), then the transition will take place
after an oscillator start-up time (TOST) has occurred. A
timing diagram, indicating the transition from the
Timer1 oscillator to the main oscillator for HS, XT and
LP modes, is shown in Figure 2-9.
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q3
Q4
Q1
Q1
TT1P
Q2 Q3
Q4
Q1
Q2
Q3
T1OSI
OSC1
1
TOST
2
3
4
5
6
7
8
TSCS
OSC2
TOSC
Internal
System Clock
SCS
(OSCCON)
Program
Counter
PC
PC + 2
PC + 6
Note 1: TOST = 1024 TOSC (drawing not to scale).
DS39609C-page 26
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
frequency. A timing diagram, indicating the transition
from the Timer1 oscillator to the main oscillator for
HS-PLL mode, is shown in Figure 2-10.
If the main oscillator is configured for HS-PLL mode, an
oscillator start-up time (TOST), plus an additional PLL
time-out (TPLL), will occur. The PLL time-out is typically
2 ms and allows the PLL to lock to the main oscillator
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
Q4
Q1 Q2 Q3 Q4
TT1P
Q1
Q1 Q2 Q3 Q4
T1OSI
OSC1
TOST
TPLL
OSC2
TSCS
TOSC
PLL Clock
Input
1
2
3
4
5
6
7
8
Internal System
Clock
SCS
(OSCCON)
Program Counter
PC
PC + 2
PC + 4
Note 1: TOST = 1024 TOSC (drawing not to scale).
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram,
FIGURE 2-11:
indicating the transition from the Timer1 oscillator to the
main oscillator for RC, RCIO, EC and ECIO modes, is
shown in Figure 2-11.
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3
Q4
T1OSI
Q1
Q1 Q2 Q3
TT1P
Q4 Q1 Q2
Q3 Q4
TOSC
OSC1
1
2
3
4
5
6
7
8
OSC2
Internal System
Clock
SCS
(OSCCON)
TSCS
Program
Counter
PC
PC + 2
PC + 4
Note 1: RC Oscillator mode assumed.
2003-2013 Microchip Technology Inc.
DS39609C-page 27
PIC18F6520/8520/6620/8620/6720/8720
2.7
Effects of Sleep Mode on the
On-Chip Oscillator
When the device executes a SLEEP instruction, the onchip clocks and oscillator are turned off and the device
is held at the beginning of an instruction cycle (Q1
state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, Sleep mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during Sleep will increase the current
consumed during Sleep. The user can wake from
Sleep through external Reset, Watchdog Timer Reset
or through an interrupt.
TABLE 2-3:
OSC Mode
2.8
Power-up Delays
Power up delays are controlled by two timers so that no
external Reset circuitry is required for most
applications. The delays ensure that the device is kept
in Reset until the device power supply and clock are
stable. For additional information on Reset operation,
see Section 3.0 “Reset”.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer (OST), intended to keep
the chip in Reset until the crystal oscillator is stable.
With the PLL enabled (HS/PLL Oscillator mode), the
time-out sequence following a Power-on Reset is different from other oscillator modes. The time-out sequence
is as follows: First, the PWRT time-out is invoked after
a POR time delay has expired. Then, the Oscillator
Start-up Timer (OST) is invoked. However, this is still
not a sufficient amount of time to allow the PLL to lock
at high frequencies. The PWRT timer is used to provide
an additional fixed 2 ms (nominal) time-out to allow the
PLL ample time to lock to the incoming clock frequency.
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin
OSC2 Pin
RC
Floating, external resistor should pull high
At logic low
RCIO
Floating, external resistor should pull high
Configured as PORTA, bit 6
ECIO
Floating
Configured as PORTA, bit 6
EC
Floating
At logic low
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
LP, XT and HS
Note:
See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR Reset.
DS39609C-page 28
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
3.0
RESET
The PIC18FXX20 devices
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
differentiate
between
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (PBOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 3-2.
These bits are used in software to determine the nature
of the Reset. See Table 3-3 for a full description of the
Reset states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses. The MCLR pin is not driven low by
any internal Resets, including the WDT.
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” on Power-on Reset, MCLR, WDT Reset, Brownout Reset, MCLR Reset during Sleep and by the
RESET instruction.
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET Instruction
Stack
Pointer
Stack Full/Underflow Reset
External Reset
WDT
Time-out
Reset
MCLR
WDT
Module
Sleep
VDD Rise Power-on Reset
Detect
VDD
Brown-out
Reset
BOREN
S
OST/PWRT
OST
10-bit Ripple Counter
Chip_Reset
R
Q
OSC1
PWRT
On-chip
RC OSC(1)
10-bit Ripple Counter
Enable PWRT
Enable OST(2)
Note 1:
2:
This is a separate oscillator from the RC oscillator of the CLKI pin.
See Table 3-1 for time-out situations.
2003-2013 Microchip Technology Inc.
DS39609C-page 29
PIC18F6520/8520/6620/8620/6720/8720
3.1
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR
circuitry, tie the MCLR pin through a 1 k to 10 k
resistor to VDD. This will eliminate external RC
components usually needed to create a Power-on
Reset delay. A minimum rise rate for VDD is specified
(parameter D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
FIGURE 3-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
R
R1
MCLR
C
PIC18FXX20
Note 1:
External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2:
R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3:
R1 = 1 k to 10 k will limit any current flowing into MCLR from external capacitor C, in
the event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
3.2
Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in Reset as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/
disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC
parameter #33 for details.
DS39609C-page 30
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
Sleep.
3.4
PLL Lock Time-out
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to
provide a fixed time-out that is sufficient for the PLL to
lock to the main oscillator frequency. This PLL lock
time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
3.5
VDD
D
3.3
Brown-out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A Reset may not occur if VDD falls below
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. If the Power-up Timer is enabled, it will be
invoked after VDD rises above BVDD; it then will keep
the chip in Reset for an additional time delay (parameter #33). If VDD drops below BVDD while the Power-up
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
VDD rises above BVDD, the Power-up Timer will
execute the additional time delay.
3.6
Time-out Sequence
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figures 3-3 through 3-7 depict time-out sequences on
power-up.
Since the time-outs occur from the POR pulse, the
time-outs will expire if MCLR is kept low long enough.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXX20 device
operating in parallel.
Table 3-2 shows the Reset conditions for some Special
Function Registers, while Table 3-3 shows the Reset
conditions for all of the registers.
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2)
Oscillator
Configuration
Brown-out
Wake-up from
Sleep or
Oscillator Switch
PWRTE = 0
PWRTE = 1
HS with PLL enabled(1)
72 ms + 1024 TOSC
+ 2ms
1024 TOSC
+ 2 ms
72 ms(2) + 1024 TOSC
+ 2 ms
1024 TOSC + 2 ms
HS, XT, LP
72 ms + 1024 TOSC
1024 TOSC
72 ms(2) + 1024 TOSC
1024 TOSC
72 ms
1.5 s
EC
External RC
Note 1:
2:
3:
72 ms
—
72 ms
(2)
1.5 s(3)
72 ms
(2)
—
2 ms is the nominal time required for the 4xPLL to lock.
72 ms is the nominal power-up timer delay, if implemented.
1.5 s is the recovery time from Sleep. There is no recovery time from oscillator switch.
REGISTER 3-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IPEN
—
—
RI
TO
PD
POR
BOR
bit 7
bit 0
Note 1: Refer to Section 4.14 “RCON Register” for bit definitions.
TABLE 3-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Register
RI
TO
PD
POR
BOR
STKFUL
STKUNF
Power-on Reset
0000h
0--1 1100
1
1
1
0
0
u
u
MCLR Reset during normal
operation
0000h
0--u uuuu
u
u
u
u
u
u
u
Software Reset during normal
operation
0000h
0--0 uuuu
0
u
u
u
u
u
u
Stack Full Reset during normal
operation
0000h
0--u uu11
u
u
u
u
u
u
1
Stack Underflow Reset during
normal operation
0000h
0--u uu11
u
u
u
u
u
1
u
MCLR Reset during Sleep
0000h
0--u 10uu
u
1
0
u
u
u
u
WDT Reset
0000h
0--u 01uu
1
0
1
u
u
u
u
WDT Wake-up
PC + 2
u--u 00uu
u
0
0
u
u
u
u
Brown-out Reset
0000h
0--1 11u0
1
1
1
1
0
u
u
u--u 00uu
u
1
0
u
u
u
u
Condition
Interrupt wake-up from Sleep
PC + 2
(1)
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
2003-2013 Microchip Technology Inc.
DS39609C-page 31
PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
---0 0000
---0 uuuu(3)
TOSH
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu(3)
TOSL
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu(3)
STKPTR
PIC18F6X20 PIC18F8X20
00-0 0000
uu-0 0000
uu-u uuuu(3)
PCLATU
PIC18F6X20 PIC18F8X20
---0 0000
---0 0000
---u uuuu
PCLATH
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
PCL
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
PC + 2(2)
TBLPTRU
PIC18F6X20 PIC18F8X20
--00 0000
--00 0000
--uu uuuu
TBLPTRH
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TABLAT
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
PRODH
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
PIC18F6X20 PIC18F8X20
0000 000x
0000 000u
uuuu uuuu(1)
INTCON2
PIC18F6X20 PIC18F8X20
1111 1111
1111 1111
uuuu uuuu(1)
INTCON3
PIC18F6X20 PIC18F8X20
1100 0000
1100 0000
uuuu uuuu(1)
INDF0
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
POSTINC0 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
POSTDEC0 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
PREINC0
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
PLUSW0
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
FSR0H
PIC18F6X20 PIC18F8X20
---- xxxx
---- uuuu
---- uuuu
FSR0L
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
POSTINC1 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
POSTDEC1 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
PREINC1
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
PLUSW1
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
TOSU
PIC18F6X20 PIC18F8X20
DS39609C-page 32
---0 0000
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
FSR1H
PIC18F6X20 PIC18F8X20
---- xxxx
---- uuuu
---- uuuu
FSR1L
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
PIC18F6X20 PIC18F8X20
---- 0000
---- 0000
---- uuuu
INDF2
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
POSTINC2 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
POSTDEC2 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
PREINC2
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
PLUSW2
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
FSR2H
PIC18F6X20 PIC18F8X20
---- xxxx
---- uuuu
---- uuuu
FSR2L
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
PIC18F6X20 PIC18F8X20
---x xxxx
---u uuuu
---u uuuu
TMR0H
PIC18F6X20 PIC18F8X20
0000 0000
uuuu uuuu
uuuu uuuu
TMR0L
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
PIC18F6X20 PIC18F8X20
1111 1111
1111 1111
uuuu uuuu
OSCCON
PIC18F6X20 PIC18F8X20
---- ---0
---- ---0
---- ---u
LVDCON
PIC18F6X20 PIC18F8X20
--00 0101
--00 0101
--uu uuuu
WDTCON
PIC18F6X20 PIC18F8X20
---- ---0
---- ---0
---- ---u
RCON(4)
PIC18F6X20 PIC18F8X20
0--q 11qq
0--q qquu
u--u qquu
TMR1H
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
PIC18F6X20 PIC18F8X20
0-00 0000
u-uu uuuu
u-uu uuuu
TMR2
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
PR2
PIC18F6X20 PIC18F8X20
1111 1111
1111 1111
1111 1111
T2CON
PIC18F6X20 PIC18F8X20
-000 0000
-000 0000
-uuu uuuu
SSPBUF
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
SSPCON1
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
SSPCON2
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
2003-2013 Microchip Technology Inc.
DS39609C-page 33
PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
ADRESH
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
PIC18F6X20 PIC18F8X20
--00 0000
--00 0000
--uu uuuu
ADCON1
PIC18F6X20 PIC18F8X20
--00 0000
--00 0000
--uu uuuu
ADCON2
PIC18F6X20 PIC18F8X20
0--- -000
0--- -000
u--- -uuu
CCPR1H
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON PIC18F6X20 PIC18F8X20
--00 0000
--00 0000
--uu uuuu
CCPR2H
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON PIC18F6X20 PIC18F8X20
--00 0000
--00 0000
--uu uuuu
CCPR3H
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR3L
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP3CON PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
CVRCON
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
CMCON
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TMR3H
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
PIC18F6X20 PIC18F8X20
0000 0000
uuuu uuuu
uuuu uuuu
PSPCON
PIC18F6X20 PIC18F8X20
0000 ---0000 ---uuuu ---SPBRG1
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
RCREG1
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TXREG1
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TXSTA1
PIC18F6X20 PIC18F8X20
0000 -010
0000 -010
uuuu -uuu
RCSTA1
PIC18F6X20 PIC18F8X20
0000 000x
0000 000x
uuuu uuuu
EEADRH
PIC18F6X20 PIC18F8X20
---- --00
---- --00
---- --uu
EEADR
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
EEDATA
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
EECON2
PIC18F6X20 PIC18F8X20
---- ------- ------- ---EECON1
PIC18F6X20 PIC18F8X20
xx-0 x000
uu-0 u000
uu-0 u000
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
DS39609C-page 34
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
IPR3
PIC18F6X20 PIC18F8X20
--11 1111
--11 1111
--uu uuuu
PIR3
PIC18F6X20 PIC18F8X20
--00 0000
--00 0000
--uu uuuu
PIE3
PIC18F6X20 PIC18F8X20
--00 0000
--00 0000
--uu uuuu
IPR2
PIC18F6X20 PIC18F8X20
-1-1 1111
-1-1 1111
-u-u uuuu
PIR2
PIC18F6X20 PIC18F8X20
-0-0 0000
-0-0 0000
-u-u uuuu(1)
PIE2
PIC18F6X20 PIC18F8X20
-0-0 0000
-0-0 0000
-u-u uuuu
IPR1
PIC18F6X20 PIC18F8X20
0111 1111
0111 1111
uuuu uuuu
PIR1
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu(1)
PIE1
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
MEMCON
PIC18F6X20 PIC18F8X20
0-00 --00
0-00 --00
u-uu --uu
TRISJ
PIC18F6X20 PIC18F8X20
1111 1111
1111 1111
uuuu uuuu
TRISH
PIC18F6X20 PIC18F8X20
1111 1111
1111 1111
uuuu uuuu
TRISG
PIC18F6X20 PIC18F8X20
---1 1111
---1 1111
---u uuuu
TRISF
PIC18F6X20 PIC18F8X20
1111 1111
1111 1111
uuuu uuuu
TRISE
PIC18F6X20 PIC18F8X20
1111 1111
1111 1111
uuuu uuuu
TRISD
PIC18F6X20 PIC18F8X20
1111 1111
1111 1111
uuuu uuuu
TRISC
PIC18F6X20 PIC18F8X20
1111 1111
1111 1111
uuuu uuuu
TRISB
PIC18F6X20 PIC18F8X20
1111 1111
1111 1111
uuuu uuuu
(5,6)
(5)
(5)
TRISA
PIC18F6X20 PIC18F8X20
-111 1111
-111 1111
-uuu uuuu(5)
LATJ
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATH
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATG
PIC18F6X20 PIC18F8X20
---x xxxx
---u uuuu
---u uuuu
LATF
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATE
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATD
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATA(5,6)
PIC18F6X20 PIC18F8X20
-xxx xxxx(5)
-uuu uuuu(5)
-uuu uuuu(5)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
2003-2013 Microchip Technology Inc.
DS39609C-page 35
PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
PORTJ
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTH
PIC18F6X20 PIC18F8X20
0000 xxxx
0000 uuuu
uuuu uuuu
PORTG
PIC18F6X20 PIC18F8X20
---x xxxx
uuuu uuuu
---u uuuu
PORTF
PIC18F6X20 PIC18F8X20
x000 0000
u000 0000
u000 0000
PORTE
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTD
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA(5,6) PIC18F6X20 PIC18F8X20
-x0x 0000(5)
-u0u 0000(5)
-uuu uuuu(5)
TMR4
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
PR4
PIC18F6X20 PIC18F8X20
1111 1111
1111 1111
uuuu uuuu
T4CON
PIC18F6X20 PIC18F8X20
-000 0000
-000 0000
-uuu uuuu
CCPR4H
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR4L
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP4CON PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
CCPR5H
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR5L
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP5CON PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
SPBRG2
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
RCREG2
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TXREG2
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TXSTA2
PIC18F6X20 PIC18F8X20
0000 -010
0000 -010
uuuu -uuu
RCSTA2
PIC18F6X20 PIC18F8X20
0000 000x
0000 000x
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
DS39609C-page 36
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 3-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA 1 k RESISTOR)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 3-4:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 3-5:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
2003-2013 Microchip Technology Inc.
DS39609C-page 37
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 3-6:
SLOW RISE TIME (MCLR TIED TO VDD VIA 1 kRESISTOR)
5V
VDD
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-7:
TIME-OUT SEQUENCE ON POR W/PLL ENABLED
(MCLR TIED TO VDD VIA 1 kRESISTOR)
VDD
MCLR
IINTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
Note:
DS39609C-page 38
TOST = 1024 clock cycles.
TPLL 2 ms max. First three stages of the PWRT timer.
2003-2013 Microchip Technology Inc.
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4.0
MEMORY ORGANIZATION
There are three memory blocks in PIC18FXX20
devices. They are:
• Program Memory
• Data RAM
• Data EEPROM
Data and program memory use separate busses,
which allows for concurrent access of these blocks.
Additional detailed information for Flash program
memory and data EEPROM is provided in Section 5.0
“Flash Program Memory” and Section 7.0 “Data
EEPROM Memory”, respectively.
In addition to on-chip Flash, the PIC18F8X20 devices
are also capable of accessing external program memory through an external memory bus. Depending on the
selected operating mode (discussed in Section 4.1.1
“PIC18F8X20 Program Memory Modes”), the controllers may access either internal or external program
memory exclusively, or both internal and external memory in selected blocks. Additional information on the
External Memory Interface is provided in Section 6.0
“External Memory Interface”.
4.1
Program Memory Organization
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all ‘0’s (a NOP
instruction).
Devices in the PIC18FXX20 family can be divided into
three groups, based on program memory size. The
PIC18FX520 devices (PIC18F6520 and PIC18F8520)
have 32 Kbytes of on-chip Flash memory, equivalent to
16,384 single-word instructions. The PIC18FX620
devices (PIC18F6620 and PIC18F8620) have
64 Kbytes of on-chip Flash memory, equivalent to
32,768
single-word
instructions.
Finally,
the
PIC18FX720 devices (PIC18F6720 and PIC18F8720)
have 128 Kbytes of on-chip Flash memory, equivalent
to 65,536 single-word instructions.
For all devices, the Reset vector address is at 0000h
and the interrupt vector addresses are at 0008h and
0018h.
The program memory maps for all of the PIC18FXX20
devices are compared in Figure 4-1.
4.1.1
PIC18F8X20 PROGRAM MEMORY
MODES
PIC18F8X20 devices differ significantly from their
PIC18 predecessors in their utilization of program
memory. In addition to available on-chip Flash program
memory, these controllers can also address up to
2 Mbytes of external program memory through the
External Memory Interface. There are four distinct
operating modes available to the controllers:
•
•
•
•
Microprocessor (MP)
Microprocessor with Boot Block (MPBB)
Extended Microcontroller (EMC)
Microcontroller (MC)
The Program Memory mode is determined by setting
the two Least Significant bits of the CONFIG3L configuration byte, as shown in Register 4-1. (See also
Section 23.1 “Configuration Bits” for additional
details on the device configuration bits.)
The Program Memory modes operate as follows:
• The Microprocessor Mode permits access only
to external program memory; the contents of the
on-chip Flash memory are ignored. The 21-bit
program counter permits access to a 2-Mbyte
linear program memory space.
• The Microprocessor with Boot Block Mode
accesses on-chip Flash memory from addresses
000000h to 0007FFh for PIC18F8520 devices
and from 000000h to 0001FFh for PIC18F8620
and PIC18F8720 devices. Above this, external
program memory is accessed all the way up to
the 2-Mbyte limit. Program execution automatically switches between the two memories, as
required.
• The Microcontroller Mode accesses only onchip Flash memory. Attempts to read above the
physical limit of the on-chip Flash (7FFFh for the
PIC18F8520, 0FFFFh for the PIC18F8620,
1FFFFh for the PIC18F8720) causes a read of all
‘0’s (a NOP instruction). The Microcontroller mode
is also the only operating mode available to
PIC18F6X20 devices.
• The Extended Microcontroller Mode allows
access to both internal and external program
memories as a single block. The device can
access its entire on-chip Flash memory; above
this, the device accesses external program
memory up to the 2-Mbyte program space limit.
As with Boot Block mode, execution automatically
switches between the two memories, as required.
In all modes, the microcontroller has complete access
to data RAM and EEPROM.
Figure 4-2 compares the memory maps of the different
Program Memory modes. The differences between onchip and external memory access limitations are more
fully explained in Table 4-1.
2003-2013 Microchip Technology Inc.
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PIC18F6520/8520/6620/8620/6720/8720
FIGURE 4-1:
INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18FXX20 DEVICES
PC
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
21
Stack Level 31
000000h
000000h
000000h
Reset Vector
000008h
000008h
000008h
High Priority
Interrupt Vector
000018h
000018h
000018h
Low Priority
Interrupt Vector
On-Chip Flash
Program Memory
On-Chip Flash
Program Memory
00FFFFh
010000h
On-Chip Flash
Program Memory
User Memory Space
007FFFh
008000h
01FFFFh
020000h
Read ‘0’
1FFFFFh
200000h
1FFFFFh
200000h
1FFFFFh
200000h
PIC18FX520
(32 Kbyte)
Note:
Read ‘0’
Read ‘0’
PIC18FX620
(64 Kbyte)
PIC18FX720
(128 Kbyte)
Size of memory regions not to scale.
TABLE 4-1:
MEMORY ACCESS FOR PIC18F8X20 PROGRAM MEMORY MODES
Internal Program Memory
Operating Mode
External Program Memory
Execution
From
Table Read
From
Table Write To
Microprocessor
No Access
No Access
No Access
Microprocessor
with Boot Block
Yes
Yes
Yes
Microcontroller
Yes
Yes
Yes
Extended
Microcontroller
Yes
Yes
Yes
DS39609C-page 40
Execution
From
Table Read
From
Table Write To
Yes
Yes
Yes
Yes
Yes
Yes
No Access
No Access
No Access
Yes
Yes
Yes
2003-2013 Microchip Technology Inc.
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REGISTER 4-1:
CONFIG3L CONFIGURATION BYTE
R/P-1
U-0
U-0
U-0
U-0
U-0
R/P-1
R/P-1
WAIT
—
—
—
—
—
PM1
PM0
bit 7
bit 0
bit 7
WAIT: External Bus Data Wait Enable bit
1 = Wait selections unavailable, device will not wait
0 = Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM)
bit 6-2
Unimplemented: Read as ‘0’
bit 1-0
PM1:PM0: Processor Data Memory Mode Select bits
11 = Microcontroller mode
10 = Microprocessor mode
01 = Microcontroller with Boot Block mode
00 = Extended Microcontroller mode
Legend:
FIGURE 4-2:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value after erase
‘1’ = Bit is set
x = Bit is unknown
MEMORY MAPS FOR PIC18F8X20 PROGRAM MEMORY MODES
Microprocessor
with Boot Block
Mode (MPBB)
Microprocessor
Mode (MP)
000000h
On-Chip
Program
Memory
(No
access)
Program Space Execution
‘0’ = Bit is cleared
000000h
Boot
Boot+1
On-Chip
Flash
Boundary
Boundary+1
Boundary
Boundary+1
Reads
‘0’s
1FFFFFh
External
Memory
1FFFFFh
External
Memory
On-Chip
Program
Memory
On-Chip
Program
Memory
External
Program
Memory
1FFFFFh
000000h
000000h
On-Chip
Program
Memory
External
Program
Memory
Extended
Microcontroller
Mode (EMC)
Microcontroller
Mode (MC)
External
Program
Memory
1FFFFFh
External
Memory
On-Chip
Flash
On-Chip
Flash
On-Chip
Flash
Boundary Values for Microprocessor with Boot Block, Microcontroller and Extended Microcontroller modes(1)
Device
Boot
Boot+1
Boundary
Boundary+1
Available
Memory Mode(s)
PIC18F6520
0007FFh
000800h
007FFFh
008000h
MC
PIC18F6620
0001FFh
000200h
00FFFFh
010000h
MC
PIC18F6720
0001FFh
000200h
01FFFFh
020000h
MC
PIC18F8520
0007FFh
000800h
007FFFh
008000h
MP, MPBB, MC, EMC
PIC18F8620
0001FFh
000200h
00FFFFh
010000h
MP, MPBB, MC, EMC
PIC18F8720
0001FFh
000200h
01FFFFh
020000h
MP, MPBB, MC, EMC
Note 1:
PIC18F6X20 devices are included here for completeness, to show the boundaries of their Boot Blocks and program memory spaces.
2003-2013 Microchip Technology Inc.
DS39609C-page 41
PIC18F6520/8520/6620/8620/6720/8720
4.2
Return Address Stack
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALL or RCALL instruction is executed, or an interrupt
is Acknowledged. The PC value is pulled off the stack
on a RETURN, RETLW or a RETFIE instruction. PCLATU
and PCLATH are not affected by any of the RETURN or
CALL instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the stack pointer initialized to
00000b after all Resets. There is no RAM associated
with stack pointer 00000b. This is only a Reset value.
During a CALL type instruction, causing a push onto the
stack, the stack pointer is first incremented and the
RAM location pointed to by the stack pointer is written
with the contents of the PC. During a RETURN type
instruction, causing a pop from the stack, the contents
of the RAM location pointed to by the STKPTR are
transferred to the PC and then the stack pointer is
decremented.
The stack space is not part of either program or data
space. The stack pointer is readable and writable and
the address on the top of the stack is readable and writable through SFR registers. Data can also be pushed
to, or popped from the stack using the top-of-stack
SFRs. Status bits indicate if the stack pointer is at, or
beyond the 31 levels provided.
4.2.1
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL, hold the
contents of the stack location pointed to by the
STKPTR register. This allows users to implement a
software stack if necessary. After a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
The user must disable the global interrupt enable bits
during this time to prevent inadvertent stack
operations.
DS39609C-page 42
4.2.2
RETURN STACK POINTER
(STKPTR)
The STKPTR register contains the stack pointer value,
the STKFUL (Stack Full) status bit and the STKUNF
(Stack Underflow) status bits. Register 4-2 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when values are pushed onto the stack and decrements when
values are popped off the stack. At Reset, the stack
pointer value will be ‘0’. The user may read and write
the stack pointer value. This feature can be used by a
Real-Time Operating System for return stack
maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR.
The action that takes place when the stack becomes
full, depends on the state of the STVREN (Stack Overflow Reset Enable) configuration bit. Refer to
Section 24.0 “Instruction Set Summary” for a
description of the device configuration bits. If STVREN
is set (default), the 31st push will push the (PC + 2)
value onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the stack
pointer will be set to ‘0’.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at ‘0’. The STKUNF bit will remain set
until cleared in software or a POR occurs.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken.
2003-2013 Microchip Technology Inc.
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REGISTER 4-2:
STKPTR REGISTER
R/C-0
R/C-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SP4
SP3
SP2
SP1
SP0
STKFUL(1) STKUNF(1)
bit 7
bit 0
bit 7
STKFUL: Stack Full Flag bit
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6
STKUNF: Stack Underflow Flag bit
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.
Legend:
FIGURE 4-3:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
11111
11110
11101
TOSU
0x00
TOSH
0x1A
STKPTR
00010
TOSL
0x34
00011
Top-of-Stack 0x001A34 00010
0x000D58 00001
00000
4.2.3
PUSH AND POP INSTRUCTIONS
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program
execution, is a desirable option. To push the current PC
value onto the stack, a PUSH instruction can be
executed. This will increment the stack pointer and load
the current PC value onto the stack. TOSU, TOSH and
TOSL can then be modified to place a return address
on the stack.
4.2.4
STACK FULL/UNDERFLOW RESETS
These Resets are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disabled, a full or underflow condition will set the
appropriate STKFUL or STKUNF bit, but not cause a
device Reset. When the STVREN bit is enabled, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. The
STKFUL or STKUNF bits are only cleared by the user
software or a POR Reset.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP instruction. The POP
instruction discards the current TOS by decrementing
the stack pointer. The previous value pushed onto the
stack then becomes the TOS value.
2003-2013 Microchip Technology Inc.
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PIC18F6520/8520/6620/8620/6720/8720
4.3
Fast Register Stack
4.4
A “fast interrupt return” option is available for interrupts.
A Fast Register Stack is provided for the Status, WREG
and BSR registers and is only one in depth. The stack
is not readable or writable and is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. The values in the
registers are then loaded back into the working registers, if the FAST RETURN instruction is used to return
from the interrupt.
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits
wide. The low byte is called the PCL register; this register is readable and writable. The high byte is called
the PCH register. This register contains the PC
bits and is not directly readable or writable; updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC bits and is not directly
readable or writable; updates to the PCU register may
be performed through the PCLATU register.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority
interrupt will be overwritten.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of the PCL is fixed to a value of
‘0’. The PC increments by 2 to address sequential
instructions in the program memory.
If high priority interrupts are not disabled during low
priority interrupts, users must save the key registers in
software during a low priority interrupt.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
If no interrupts are used, the fast register stack can be
used to restore the Status, WREG and BSR registers at
the end of a subroutine call. To use the fast register
stack for a subroutine call, a FAST CALL instruction
must be executed.
The contents of PCLATH and PCLATU will be transferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the
program counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1
“Computed GOTO”).
Example 4-1 shows a source code example that uses
the fast register stack.
EXAMPLE 4-1:
FAST REGISTER STACK
CODE EXAMPLE
CALL SUB1, FAST
4.5
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
FIGURE 4-4:
Clocking Scheme/Instruction
Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-4.
RETURN FAST
PCL, PCLATH and PCLATU
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
OSC2/CLKO
(RC mode)
DS39609C-page 44
PC
Execute INST (PC-2)
Fetch INST (PC)
PC+2
Execute INST (PC)
Fetch INST (PC+2)
PC+4
Execute INST (PC+2)
Fetch INST (PC+4)
2003-2013 Microchip Technology Inc.
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4.6
Instruction Flow/Pipelining
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined, such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 4-2).
EXAMPLE 4-2:
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
TCY0
TCY1
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. BRA
4. BSF
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
TCY2
TCY4
TCY5
Execute 2
Fetch 3
SUB_1
TCY3
Execute 3
Fetch 4
PORTA, BIT3 (Forced NOP)
Flush (NOP)
Fetch SUB_1 Execute SUB_1
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed”
from the pipeline, while the new instruction is being fetched and then executed.
4.7
Instructions in Program Memory
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). Figure 4-5 shows an
example of how instruction words are stored in the program memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ‘0’ (see Section 4.4 “PCL,
PCLATH and PCLATU”).
word boundaries, the data contained in the instruction
is a word address. The word address is written to
PC, which accesses the desired byte address in
program memory. Instruction #2 in Figure 4-5 shows
how the instruction “GOTO 000006h” is encoded in the
program memory. Program branch instructions, which
encode a relative address offset, operate in the same
manner. The offset value stored in a branch instruction
represents the number of single-word instructions that
the PC will be offset by. Section 24.0 “Instruction Set
Summary” provides further details of the instruction
set.
The CALL and GOTO instructions have an absolute
program memory address embedded into the
instruction. Since instructions are always stored on
FIGURE 4-5:
INSTRUCTIONS IN PROGRAM MEMORY
LSB = 1
LSB = 0
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Program Memory
Byte Locations
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
000006h
Instruction 3:
MOVFF
123h, 456h
2003-2013 Microchip Technology Inc.
Word Address
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
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4.7.1
TWO-WORD INSTRUCTIONS
The PIC18FXX20 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second word
of these instructions has the 4 MSBs set to ‘1’s and is
a special kind of NOP instruction. The lower 12 bits of
the second word contain data to be used by the instruction. If the first word of the instruction is executed, the
data in the second word is accessed. If the second
EXAMPLE 4-3:
word of the instruction is executed by itself (first word
was skipped), it will execute as a NOP. This action is
necessary when the two-word instruction is preceded
by a conditional instruction that changes the PC. A program example that demonstrates this concept is shown
in Example 4-3. Refer to Section 24.0 “Instruction
Set Summary” for further details of the instruction set.
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
1100 0001 0010 0011
MOVFF
REG1, REG2 ; No, execute 2-word instruction
1111 0100 0101 0110
0010 0100 0000 0000
; is RAM location 0?
; 2nd operand holds address of REG2
ADDWF
REG3
; continue code
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
1100 0001 0010 0011
MOVFF
REG1, REG2 ; Yes
ADDWF
REG3
1111 0100 0101 0110
0010 0100 0000 0000
4.8
; 2nd operand becomes NOP
Look-up Tables
Look-up tables are implemented two ways. These are:
• Computed GOTO
• Table Reads
4.8.1
; is RAM location 0?
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL).
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions, that returns the value 0xnn to the calling
function.
; continue code
4.8.2
TABLE READS/TABLE WRITES
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Look-up table data may be stored 2 bytes per program
word by using table reads and writes. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from, or
written to program memory. Data is transferred to/from
program memory, one byte at a time.
A description of the table read/table write operation is
shown in Section 5.0 “Flash Program Memory”.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
DS39609C-page 46
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PIC18F6520/8520/6620/8620/6720/8720
4.9
Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. The data
memory map is in turn divided into 16 banks of
256 bytes each. The lower 4 bits of the Bank Select
Register (BSR) select which bank will be
accessed. The upper 4 bits of the BSR are not
implemented.
The data memory space contains both Special Function Registers (SFR) and General Purpose Registers
(GPR). The SFRs are used for control and status of the
controller and peripheral functions, while GPRs are
used for data storage and scratch pad operations in the
user’s application. The SFRs start at the last location of
Bank 15 (0FFFh) and extend downwards. Any remaining space beyond the SFRs in the Bank may be implemented as GPRs. GPRs start at the first location of
Bank 0 and grow upwards. Any read of an
unimplemented location will read as ‘0’s.
PIC18FX520 devices have 2048 bytes of data RAM,
extending from Bank 0 to Bank 7 (000h through 7FFh).
PIC18FX620 and PIC18FX720 devices have
3840 bytes of data RAM, extending from Bank 0 to
Bank 14 (000h through EFFh). The organization of the
data memory space for these devices is shown in
Figure 4-6 and Figure 4-7.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and a corresponding Indirect File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the data memory map without banking.
4.9.1
GENERAL PURPOSE
REGISTER FILE
The register file can be accessed either directly or indirectly. Indirect addressing operates using a File Select
Register and corresponding Indirect File Operand. The
operation of indirect addressing is shown in
Section 4.12 “Indirect Addressing, INDF and FSR
Registers”.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
Data RAM is available for use as General Purpose
Registers by all instructions. The top section of Bank 15
(F60h to FFFh) contains SFRs. All other banks of data
memory contain GPR registers, starting with Bank 0.
4.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 4-2 and Table 4-3.
The SFRs can be classified into two sets: those associated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature. The
SFRs are typically distributed among the peripherals
whose functions they control.
The unused SFR locations are unimplemented and
read as ‘0’s. The addresses for the SFRs are listed in
Table 4-2.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing, or by the use of the MOVFF instruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 4.10
“Access Bank” provides a detailed description of the
Access RAM.
2003-2013 Microchip Technology Inc.
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FIGURE 4-6:
DATA MEMORY MAP FOR PIC18FX520 DEVICES
BSR
= 0000
= 0001
= 0010
Data Memory Map
= 0110
= 0111
Access RAM
FFh
00h
GPRs
000h
05Fh
060h
0FFh
100h
GPRs
Bank 1
FFh
00h
Bank 2
1FFh
200h
GPRs
2FFh
300h
FFh
00h
= 0011
00h
Bank 0
Bank 3
to
Bank 6
GPRs
Access Bank
FFh
00h
Bank 7
6FFh
700h
GPRs
FFh
7FFh
800h
00h
5Fh
Access RAM High 60h
(SFRs)
FFh
Access RAM Low
= 1000
Unused,
Read as ‘0’
Bank 8
to
Bank 14
= 1110
= 1111
00h
Unused
FFh
SFRs
Bank 15
EFFh
F00h
F5Fh
F60h
FFFh
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 96 bytes are General
Purpose RAM (from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
the BSR is used to specify the
RAM location that the instruction
uses.
DS39609C-page 48
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PIC18F6520/8520/6620/8620/6720/8720
FIGURE 4-7:
DATA MEMORY MAP FOR PIC18FX620 AND PIC18FX720 DEVICES
BSR
= 0000
= 0001
= 0010
= 0011
Data Memory Map
00h
Access RAM
FFh
00h
GPRs
Bank 0
GPRs
Bank 1
FFh
00h
Bank 2
1FFh
200h
GPRs
2FFh
300h
FFh
00h
Bank 3
GPRs
FFh
= 0100
Bank 4
3FFh
400h
GPRs
Access Bank
4FFh
500h
= 0101
000h
05Fh
060h
0FFh
100h
Bank 5
to
Bank 13
GPRs
= 1101
= 1110
= 1111
00h
5Fh
Access RAM High 60h
(SFRs)
FFh
Access RAM Low
DFFh
E00h
00h
Bank 14
GPRs
FFh
00h
Unused
FFh
SFRs
Bank 15
EFFh
F00h
F5Fh
F60h
FFFh
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 96 bytes are General
Purpose RAM (from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
the BSR is used to specify the
RAM location that the instruction
uses.
2003-2013 Microchip Technology Inc.
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PIC18F6520/8520/6620/8620/6720/8720
TABLE 4-2:
SPECIAL FUNCTION REGISTER MAP
Address
Name
FFFh
Address
TOSU
FFEh
FDFh
TOSH
FDEh
Name
Address
(3)
Name
Address
Name
FBFh
CCPR1H
F9Fh
IPR1
POSTINC2(3)
FBEh
CCPR1L
F9Eh
PIR1
(3)
F9Dh
PIE1
INDF2
FFDh
TOSL
FBDh
CCP1CON
FFCh
STKPTR
FDCh
FDDh POSTDEC2
PREINC2(3)
FBCh
CCPR2H
F9Ch MEMCON(2)
FFBh
PCLATU
FDBh
PLUSW2(3)
FBBh
CCPR2L
F9Bh
—(1)
FFAh
PCLATH
FDAh
FSR2H
FBAh
CCP2CON
F9Ah
TRISJ
FF9h
PCL
FD9h
FSR2L
FB9h
CCPR3H
F99h
TRISH
FF8h
TBLPTRU
FD8h
STATUS
FB8h
CCPR3L
F98h
TRISG
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
CCP3CON
F97h
TRISF
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
—(1)
F96h
TRISE
FF5h
TABLAT
FD5h
T0CON
FB5h
CVRCON
F95h
TRISD
FF4h
PRODH
FD4h
—(1)
FB4h
CMCON
F94h
TRISC
FF3h
PRODL
FD3h
OSCCON
FB3h
TMR3H
F93h
TRISB
FF2h
INTCON
FD2h
LVDCON
FB2h
TMR3L
F92h
TRISA
FF1h
INTCON2
FD1h
WDTCON
FB1h
T3CON
F91h
LATJ
FF0h
INTCON3
FD0h
RCON
FB0h
PSPCON
F90h
LATH
FEFh
INDF0(3)
LATG
FCFh
TMR1H
FAFh
SPBRG1
F8Fh
FEEh POSTINC0(3)
FCEh
TMR1L
FAEh
RCREG1
F8Eh
LATF
(3)
FCDh
T1CON
FADh
TXREG1
F8Dh
LATE
FCCh
TMR2
FACh
TXSTA1
F8Ch
LATD
FEDh POSTDEC0
FECh
PREINC0(3)
FEBh
PLUSW0(3)
FCBh
PR2
FABh
RCSTA1
F8Bh
LATC
FEAh
FSR0H
FCAh
T2CON
FAAh
EEADRH
F8Ah
LATB
FE9h
FSR0L
FC9h
SSPBUF
FA9h
EEADR
F89h
LATA
FE8h
WREG
FC8h
SSPADD
FA8h
EEDATA
F88h
PORTJ
FE7h
INDF1(3)
FC7h
SSPSTAT
FA7h
EECON2
F87h
PORTH
FE6h
POSTINC1(3)
FC6h
SSPCON1
FA6h
EECON1
F86h
PORTG
FE5h
POSTDEC1(3)
FC5h
SSPCON2
FA5h
IPR3
F85h
PORTF
FE4h
PREINC1(3)
FC4h
ADRESH
FA4h
PIR3
F84h
PORTE
FE3h
PLUSW1(3)
FC3h
ADRESL
FA3h
PIE3
F83h
PORTD
FE2h
FSR1H
FC2h
ADCON0
FA2h
IPR2
F82h
PORTC
FE1h
FSR1L
FC1h
ADCON1
FA1h
PIR2
F81h
PORTB
FE0h
BSR
FC0h
ADCON2
FA0h
PIE2
F80h
PORTA
Note 1:
2:
3:
Unimplemented registers are read as ‘0’.
This register is unused on PIC18F6X20 devices. Always maintain this register clear.
This is not a physical register.
DS39609C-page 50
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PIC18F6520/8520/6620/8620/6720/8720
TABLE 4-2:
Address
SPECIAL FUNCTION REGISTER MAP (CONTINUED)
Name
Address
Name
—(1)
Name
Address
Name
—
F7Eh
—
(1)
F5Eh
—
F7Dh
—(1)
F5Dh
—(1)
F3Dh
—(1)
F1Dh
—(1)
F7Ch
—
(1)
F5Ch
—
(1)
F3Ch
—
(1)
F1Ch
—(1)
F7Bh
—(1)
F5Bh
—(1)
F3Bh
—(1)
F1Bh
—(1)
F7Ah
—
(1)
F5Ah
—
(1)
F3Ah
—
(1)
F1Ah
—(1)
F79h
—(1)
F59h
—(1)
F39h
—(1)
F19h
—(1)
(1)
F38h
—
(1)
F18h
—(1)
F7Fh
F5Fh
Address
(1)
F3Fh
—(1)
F1Fh
—(1)
(1)
F3Eh
—
(1)
F1Eh
—(1)
F78h
TMR4
F58h
—
F77h
PR4
F57h
—(1)
F37h
—(1)
F17h
—(1)
(1)
F36h
—
(1)
F16h
—(1)
F76h
T4CON
F56h
—
F75h
CCPR4H
F55h
—(1)
F35h
—(1)
F15h
—(1)
F34h
—(1)
F14h
—(1)
F74h
CCPR4L
F54h
—(1)
F73h
CCP4CON
F53h
—(1)
F33h
—(1)
F13h
—(1)
F32h
—(1)
F12h
—(1)
F72h
CCPR5H
F52h
—(1)
F71h
CCPR5L
F51h
—(1)
F31h
—(1)
F11h
—(1)
F30h
—(1)
F10h
—(1)
F70h
CCP5CON
F50h
—(1)
F6Fh
SPBRG2
F4Fh
—(1)
F2Fh
—(1)
F0Fh
—(1)
F2Eh
—(1)
F0Eh
—(1)
F6Eh
RCREG2
F4Eh
—(1)
F6Dh
TXREG2
F4Dh
—(1)
F2Dh
—(1)
F0Dh
—(1)
F2Ch
—(1)
F0Ch
—(1)
F6Ch
TXSTA2
F4Ch
—(1)
F6Bh
RCSTA2
F4Bh
—(1)
F2Bh
—(1)
F0Bh
—(1)
F6Ah
—(1)
F4Ah
—(1)
F2Ah
—(1)
F0Ah
—(1)
F69h
—(1)
F49h
—(1)
F29h
—(1)
F09h
—(1)
F68h
—(1)
F48h
—(1)
F28h
—(1)
F08h
—(1)
F67h
—(1)
F47h
—(1)
F27h
—(1)
F07h
—(1)
F66h
—(1)
F46h
—(1)
F26h
—(1)
F06h
—(1)
F65h
—(1)
F45h
—(1)
F25h
—(1)
F05h
—(1)
F64h
—(1)
F44h
—(1)
F24h
—(1)
F04h
—(1)
F63h
—(1)
F43h
—(1)
F23h
—(1)
F03h
—(1)
F62h
—
(1)
F42h
—
(1)
F22h
—
(1)
F02h
—(1)
F61h
—(1)
F41h
—(1)
F21h
—(1)
F01h
—(1)
F60h
—(1)
F40h
—(1)
F20h
—(1)
F00h
—(1)
Note 1:
2:
3:
Unimplemented registers are read as ‘0’.
This register is not available on PIC18F6X20 devices.
This is not a physical register.
2003-2013 Microchip Technology Inc.
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PIC18F6520/8520/6620/8620/6720/8720
TABLE 4-3:
File Name
TOSU
REGISTER FILE SUMMARY
Bit 7
Bit 6
Bit 5
—
—
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Top-of-Stack Upper Byte (TOS)
Value on
Details
POR, BOR on page:
---0 0000
32, 42
TOSH
Top-of-Stack High Byte (TOS)
0000 0000
32, 42
TOSL
Top-of-Stack Low Byte (TOS)
0000 0000
32, 42
Return Stack Pointer
00-0 0000
32, 43
Holding Register for PC
--10 0000
32, 44
STKPTR
STKFUL
STKUNF
—
PCLATU
—
—
bit 21
PCLATH
Holding Register for PC
0000 0000
32, 44
PCL
PC Low Byte (PC)
0000 0000
32, 44
TBLPTRU
TBLPTRH
—
—
bit 21(2)
Program Memory Table Pointer Upper Byte (TBLPTR)
Program Memory Table Pointer High Byte (TBLPTR)
--00 0000
32, 64
0000 0000
32, 64
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR)
0000 0000
32, 64
TABLAT
Program Memory Table Latch
0000 0000
32, 64
PRODH
Product Register High Byte
xxxx xxxx
32, 85
PRODL
Product Register Low Byte
xxxx xxxx
32, 85
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
32, 89
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
1111 1111
32, 90
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
1100 0000
32, 91
INTCON3
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
n/a
57
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented
(not a physical register)
n/a
57
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented
(not a physical register)
n/a
57
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
n/a
57
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented
(not a physical register) – value of FSR0 offset by value in WREG
n/a
57
FSR0H
---- 0000
32, 57
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
xxxx xxxx
32, 57
WREG
Working Register
xxxx xxxx
32
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
n/a
57
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented
(not a physical register)
n/a
57
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented
(not a physical register)
n/a
57
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented
(not a physical register)
n/a
57
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented
(not a physical register) – value of FSR1 offset by value in WREG
n/a
57
---- 0000
33, 57
xxxx xxxx
33, 57
---- 0000
33, 56
FSR1H
FSR1L
BSR
—
—
INDF2
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
Bank Select Register
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
n/a
57
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented
(not a physical register)
n/a
57
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented
(not a physical register)
n/a
57
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator
modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X20 devices; always maintain these clear.
DS39609C-page 52
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TABLE 4-3:
File Name
REGISTER FILE SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Details
POR, BOR on page:
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented
(not a physical register)
n/a
57
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented
(not a physical register) – value of FSR2 offset by value in WREG
n/a
57
---- 0000
33, 57
FSR2H
FSR2L
STATUS
—
—
—
—
TMR0H
Timer0 Register High Byte
TMR0L
Timer0 Register Low Byte
T0CON
—
—
Indirect Data Memory Address Pointer 2 High Byte
Indirect Data Memory Address Pointer 2 Low Byte
—
N
OV
Z
DC
C
xxxx xxxx
33, 57
---x xxxx
33, 59
0000 0000 33, 133
xxxx xxxx 33, 133
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
OSCCON
—
—
—
—
—
—
—
SCS
LVDCON
—
—
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
--00 0101 33, 235
—
—
—
—
—
—
—
SWDTE
---- ---0 33, 250
IPEN
—
—
RI
TO
PD
POR
BOR
WDTCON
RCON
TMR1H
Timer1 Register High Byte
TMR1L
Timer1 Register Low Byte
T1CON
—
RD16
TMR2
Timer2 Register
PR2
Timer2 Period Register
T2CON
—
1111 1111 33, 131
---- ---0
0--1 11qq
25, 33
33, 60,
101
xxxx xxxx 33, 135
xxxx xxxx 33, 135
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON 0-00 0000 33, 135
0000 0000 33, 141
1111 1111 33, 142
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0 -000 0000 33, 141
SSPBUF
SSP Receive Buffer/Transmit Register
xxxx xxxx 33, 157
SSPADD
SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode.
0000 0000 33, 166
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 33, 158
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000 33, 168
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000 33, 169
ADRESH
A/D Result Register High Byte
xxxx xxxx 34, 215
ADRESL
A/D Result Register Low Byte
xxxx xxxx 34, 215
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
--00 0000 34, 213
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
--00 0000 34, 214
ADCON2
ADFM
—
—
—
—
ADCS2
ADCS1
ADCS0
0--- -000 34, 215
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx 34, 151,
152
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx 34, 151,
152
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000 34, 149
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx 34, 151,
152
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 34, 151,
152
CCP2CON
Legend:
Note 1:
2:
3:
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000 34, 149
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator
modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X20 devices; always maintain these clear.
2003-2013 Microchip Technology Inc.
DS39609C-page 53
PIC18F6520/8520/6620/8620/6720/8720
TABLE 4-3:
File Name
REGISTER FILE SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Details
POR, BOR on page:
CCPR3H
Capture/Compare/PWM Register 3 High Byte
xxxx xxxx 34, 151,
152
CCPR3L
Capture/Compare/PWM Register 3 Low Byte
xxxx xxxx 34, 151,
152
CCP3CON
—
—
DC3B1
DC3B0
CCP3M3
CCP3M2
CCP3M1
CCP3M0
--00 0000 34, 149
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
0000 0000 34, 229
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000 34, 223
CMCON
TMR3H
Timer3 Register High Byte
TMR3L
Timer3 Register Low Byte
T3CON
PSPCON
xxxx xxxx 34, 143
xxxx xxxx 34, 143
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
IBF
OBF
IBOV
PSPMODE
—
—
—
TMR3ON 0000 0000 34, 143
—
0000 ---- 34, 129
SPBRG1
USART1 Baud Rate Generator
0000 0000 34, 205
RCREG1
USART1 Receive Register
0000 0000 34, 206
TXREG1
USART1 Transmit Register
0000 0000 34, 204
TXSTA1
CSRC
TX9
TXEN
SYNC
—
BRGH
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
EEADRH
—
—
—
—
—
—
TRMT
TX9D
0000 -010 34, 198
OERR
RX9D
0000 000x 34, 199
---- --00
34, 79
EEADR
Data EEPROM Address Register
0000 0000
34, 79
EEDATA
Data EEPROM Data Register
0000 0000
34, 79
EECON2
Data EEPROM Control Register 2 (not a physical register)
---- ----
34, 79
xx-0 x000
34, 80
EECON1
EE Adr Register High
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
IPR3
—
—
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
--11 1111 35, 100
PIR3
—
—
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
--00 0000
PIE3
—
—
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
--00 0000
35, 97
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
-1-1 1111
35, 99
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
-0-0 0000
35, 93
PIE2
—
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
-0-0 0000
35, 96
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0111 1111
35, 98
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
35, 92
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
35, 95
MEMCON(3)
EBDIS
—
WAIT1
WAIT0
—
—
WM1
WM0
0-00 --00
35, 71
TRISJ(3)
Data Direction Control Register for PORTJ
TRISH(3)
Data Direction Control Register for PORTH
TRISG
—
—
—
Data Direction Control Register for PORTG
35, 94
1111 1111 35, 125
1111 1111 35, 122
---1 1111 35, 120
TRISF
Data Direction Control Register for PORTF
1111 1111
35, 117
TRISE
Data Direction Control Register for PORTE
1111 1111
35, 114
TRISD
Data Direction Control Register for PORTD
1111 1111
35, 111
TRISC
Data Direction Control Register for PORTC
1111 1111 35, 109
TRISB
Data Direction Control Register for PORTB
1111 1111 35, 106
TRISA
Legend:
Note 1:
2:
3:
—
TRISA6(1)
Data Direction Control Register for PORTA
-111 1111 35, 103
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator
modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X20 devices; always maintain these clear.
DS39609C-page 54
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 4-3:
File Name
REGISTER FILE SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
LATJ(3)
Read PORTJ Data Latch, Write PORTJ Data Latch
LATH(3)
Read PORTH Data Latch, Write PORTH Data Latch
LATG
—
—
—
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Details
POR, BOR on page:
xxxx xxxx 35, 125
xxxx xxxx 35, 122
Read PORTG Data Latch, Write PORTG Data Latch
---x xxxx 35, 120
LATF
Read PORTF Data Latch, Write PORTF Data Latch
xxxx xxxx
35, 117
LATE
Read PORTE Data Latch, Write PORTE Data Latch
xxxx xxxx
35, 114
LATD
Read PORTD Data Latch, Write PORTD Data Latch
xxxx xxxx
35, 111
LATC
Read PORTC Data Latch, Write PORTC Data Latch
xxxx xxxx 35, 109
LATB
Read PORTB Data Latch, Write PORTB Data Latch
xxxx xxxx 35, 106
LATA
—
LATA6(1)
Read PORTA Data Latch, Write PORTA Data Latch(1)
PORTJ(3)
Read PORTJ pins, Write PORTJ Data Latch
PORTH(3)
Read PORTH pins, Write PORTH Data Latch
PORTG
—
—
—
-xxx xxxx 35, 103
xxxx xxxx 36, 125
xxxx xxxx 36, 122
Read PORTG pins, Write PORTG Data Latch
---x xxxx 36, 120
PORTF
Read PORTF pins, Write PORTF Data Latch
xxxx xxxx
36, 117
PORTE
Read PORTE pins, Write PORTE Data Latch
xxxx xxxx
36, 114
PORTD
Read PORTD pins, Write PORTD Data Latch
xxxx xxxx
36, 111
PORTC
Read PORTC pins, Write PORTC Data Latch
xxxx xxxx 36, 109
PORTB
Read PORTB pins, Write PORTB Data Latch
xxxx xxxx 36, 106
PORTA
RA6(1)
—
TMR4
Timer4 Register
PR4
Timer4 Period Register
T4CON
—
Read PORTA pins, Write PORTA Data Latch(1)
-x0x 0000 36, 103
0000 0000 36, 148
1111 1111 36, 148
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0
TMR4ON
T4CKPS1
T4CKPS0 -000 0000 36, 147
CCPR4H
Capture/Compare/PWM Register 4 High Byte
xxxx xxxx 36, 151,
152
CCPR4L
Capture/Compare/PWM Register 4 Low Byte
xxxx xxxx 36, 151,
152
CCP4CON
—
—
DC4B1
DC4B0
CCP4M3
CCP4M2
CCP4M1
CCP4M0
0000 0000 36, 149
CCPR5H
Capture/Compare/PWM Register 5 High Byte
xxxx xxxx 36, 151,
152
CCPR5L
Capture/Compare/PWM Register 5 Low Byte
xxxx xxxx 36, 151,
152
CCP5CON
—
—
DC5B1
DC5B0
CCP5M3
CCP5M2
CCP5M1
CCP5M0
0000 0000 36, 149
SPBRG2
USART2 Baud Rate Generator
0000 0000 36, 205
RCREG2
USART2 Receive Register
0000 0000 36, 206
TXREG2
USART2 Transmit Register
0000 0000 36, 204
TXSTA2
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 36, 198
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x 36, 199
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator
modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X20 devices; always maintain these clear.
2003-2013 Microchip Technology Inc.
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4.10
Access Bank
4.11
The Access Bank is an architectural enhancement,
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
This data memory region can be used for:
•
•
•
•
•
BSR holds the upper 4 bits of the 12-bit RAM
address. The BSR bits will always read ‘0’s and
writes will have no effect.
Intermediate computational values
Local variables of subroutines
Faster context saving/switching of variables
Common variables
Faster evaluation/control of SFRs (no banking)
A MOVLB instruction has been provided in the
instruction set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all ‘0’s and all writes are ignored. The
Status register bits will be set/cleared as appropriate for
the instruction performed.
The Access Bank is comprised of the upper 160 bytes
in Bank 15 (SFRs) and the lower 96 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-7
indicates the Access RAM areas.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted by the ‘a’ bit (for
access bit).
A MOVFF instruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 “Indirect Addressing, INDF and FSR
Registers” provides a description of indirect addressing, which allows linear addressing of the entire RAM
space.
When forced in the Access Bank (a = 0), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function Registers, so that these registers
can be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
FIGURE 4-8:
Bank Select Register (BSR)
DIRECT ADDRESSING
Direct Addressing
BSR
Bank Select(2)
7
From Opcode(3)
0
Location Select(3)
00h
01h
0Eh
0Fh
000h
100h
E00h
F00h
0FFh
1FFh
EFFh
FFFh
Bank 14
Bank 15
Data
Memory(1)
Bank 0
Note 1:
Bank 1
For register file map detail, see Table 4-2.
2:
The access bit of the instruction can be used to force an override of the selected bank (BSR) to the
registers of the Access Bank.
3:
The MOVFF instruction embeds the entire 12-bit address in the instruction.
DS39609C-page 56
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4.12
Indirect Addressing, INDF and
FSR Registers
Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-9
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address,
specified by the value of the FSR register.
Indirect addressing is possible by using one of the
INDF registers. Any instruction using the INDF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = 0), will read 00h. Writing to the INDF
register indirectly, results in a no operation. The FSR
register contains a 12-bit address, which is shown in
Figure 4-10.
The INDFn register is not a physical register. Addressing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addressing.
Example 4-4 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 4-4:
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
FSR0 ,0x100 ;
POSTINC0
; Clear INDF
; register and
; inc pointer
BTFSS FSR0H, 1
; All done with
; Bank 1?
GOTO NEXT
; NO, clear next
CONTINUE
; YES, continue
NEXT
LFSR
CLRF
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12 bits wide. To store the 12 bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
1.
2.
3.
FSR0: composed of FSR0H:FSR0L
FSR1: composed of FSR1H:FSR1L
FSR2: composed of FSR2H:FSR2L
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect addressing, with the value in the corresponding FSR register
being the address of the data. If an instruction writes a
value to INDF0, the value will be written to the address
pointed to by FSR0H:FSR0L. A read from INDF1 reads
2003-2013 Microchip Technology Inc.
the data from the address pointed to by
FSR1H:FSR1L. INDFn can be used in code anywhere
an operand can be used.
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all ‘0’s are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOP instruction and the
Status bits are not affected.
4.12.1
INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Performing an operation on one of these five registers
determines how the FSR will be modified during
indirect addressing.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
• Do nothing to FSRn after an indirect access
(no change) – INDFn.
• Auto-decrement FSRn after an indirect access
(post-decrement) – POSTDECn.
• Auto-increment FSRn after an indirect access
(post-increment) – POSTINCn.
• Auto-increment FSRn before an indirect access
(pre-increment) – PREINCn.
• Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access
(no change) – PLUSWn.
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
Status register. For example, if the indirect address
causes the FSR to equal ‘0’, the Z bit will not be set.
Incrementing or decrementing an FSR affects all 12
bits. That is, when FSRnL overflows from an increment,
FSRnH will be incremented automatically.
Adding these features allows the FSRn to be used as a
stack pointer, in addition to its uses for table operations
in data memory.
Each FSR has an address associated with it that
performs an indexed indirect access. When a data
access to this INDFn location (PLUSWn) occurs, the
FSRn is configured to add the signed value in the
WREG register and the value in FSR to form the
address before an indirect access. The FSR value is
not changed.
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(Status bits are not affected).
If an indirect addressing operation is done where the target address is an FSRnH or FSRnL register, the write
operation will dominate over the pre- or post-increment/
decrement functions.
DS39609C-page 57
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 4-9:
INDIRECT ADDRESSING OPERATION
RAM
0h
Instruction
Executed
Opcode
Address
FFFh
12
File Address = Access of an Indirect Addressing Register
BSR
Instruction
Fetched
4
Opcode
FIGURE 4-10:
12
12
8
FSR
File
INDIRECT ADDRESSING
Indirect Addressing
11
FSR Register
0
Location Select
0000h
Data
Memory(1)
0FFFh
Note 1:
DS39609C-page 58
For register file map detail, see Table 4-2.
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4.13
Status Register
The Status register, shown in Register 4-3, contains the
arithmetic status of the ALU. The Status register can be
the destination for any instruction, as with any other register. If the Status register is the destination for an
instruction that affects the Z, DC, C, OV or N bits, then
the write to these five bits is disabled. These bits are set
or cleared according to the device logic. Therefore, the
result of an instruction with the Status register as
destination may be different than intended.
REGISTER 4-3:
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the Status register as
000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to alter
the Status register, because these instructions do not
affect the Z, C, DC, OV or N bits from the Status register. For other instructions not affecting any status bits,
see Table 24-1.
Note:
The C and DC bits operate as a borrow
and digit borrow bit respectively, in
subtraction.
STATUS REGISTER
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
N
OV
Z
DC
C
bit 7
bit 0
bit 7-5
Unimplemented: Read as ‘0’
bit 4
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude, which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
Note:
bit 0
For borrow, the polarity is reversed. A subtraction is executed by adding the
2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit
is loaded with either bit 4 or bit 3 of the source register.
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the
2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit
is loaded with either the high or low-order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 59
PIC18F6520/8520/6620/8620/6720/8720
4.14
RCON Register
Note 1: If the BOREN configuration bit is set
(Brown-out Reset enabled), the BOR bit
is ‘1’ on a Power-on Reset. After a Brownout Reset has occurred, the BOR bit will
be cleared and must be set by firmware to
indicate the occurrence of the next
Brown-out Reset.
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device Reset. These flags include the TO, PD, POR,
BOR and RI bits. This register is readable and writable.
2: It is recommended that the POR bit be set
after a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
REGISTER 4-4:
RCON REGISTER
R/W-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
IPEN
—
—
RI
TO
PD
POR
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5
Unimplemented: Read as ‘0’
bit 4
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed
0 = The RESET instruction was executed causing a device Reset
(must be set in software after a Brown-out Reset occurs)
bit 3
TO: Watchdog Time-out Flag bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 2
PD: Power-down Detection Flag bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 1
POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
DS39609C-page 60
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
5.0
FLASH PROGRAM MEMORY
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
The Flash program memory is readable, writable and
erasable, during normal operation over the entire VDD
range.
Table read operations retrieve data from program memory and place it into the data RAM space. Figure 5-1
shows the operation of a table read with program
memory and data RAM.
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 8 bytes at a time. Program memory is erased
in blocks of 64 bytes at a time. A bulk erase operation
may not be issued from user code.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 5.5
“Writing to Flash Program Memory”. Figure 5-2
shows the operation of a table write with program
memory and data RAM.
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word aligned. Therefore, a table block
can start and end at any byte address. If a table write is
being used to write executable code into program
memory, program instructions will need to be word
aligned.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
5.1
Table Reads and Table Writes
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data
RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
FIGURE 5-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1:
Table Pointer points to a byte in program memory.
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FIGURE 5-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1:
5.2
Table Pointer actually points to one of eight holding registers, the address of which is determined by
TBLPTRL. The process for physically writing data to the Program Memory Array is discussed in
Section 5.5 “Writing to Flash Program Memory”.
Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
•
•
•
•
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
5.2.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit EEPGD determines if the access will be a
program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
Control bit CFGS determines if the access will be to the
configuration/calibration registers, or to program
memory/data EEPROM memory. When set, subsequent operations will operate on configuration registers, regardless of EEPGD (see Section 23.0 “Special
Features of the CPU”). When clear, memory selection
access is determined by EEPGD.
DS39609C-page 62
The FREE bit, when set, will allow a program memory
erase operation. When the FREE bit is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal operation. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR), due to Reset values of zero.
The WR control bit, initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation. The
inability to clear the WR bit in software prevents the
accidental or premature termination of a write
operation.
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when the write is complete. It must
be cleared in software.
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REGISTER 5-1:
EECON1 REGISTER (ADDRESS FA6h)
R/W-x
EEPGD
bit 7
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
WRERR
R/W-0
WREN
R/S-0
WR
R/S-0
RD
bit 0
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access configuration registers
0 = Access Flash program or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any Reset during self-timed programming in normal operation)
0 = The write operation completed
Note:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
bit 2
WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write
cycle. (The operation is self-timed and the bit is cleared by hardware once write is
complete. The WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit
can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
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5.2.2
TABLAT – TABLE LATCH REGISTER
5.2.4
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data RAM.
5.2.3
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the Table
Pointer determine which byte is read from program
memory into TABLAT.
TBLPTR – TABLE POINTER
REGISTER
When a TBLWT is executed, the three LSbs of the Table
Pointer (TBLPTR) determine which of the eight
program memory holding registers is written to. When
the timed write to program memory (long write) begins,
the 19 MSbs of the Table Pointer, TBLPTR
(TBLPTR), will determine which program memory block of 8 bytes is written to. For more detail, see
Section 5.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21
bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the Device ID, the User ID and the configuration bits.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer (TBLPTR) point to
the 64-byte block that will be erased. The Least
Significant bits (TBLPTR) are ignored.
The Table Pointer, TBLPTR, is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways, based on the table operation. These operations are shown in Table 5-1. These
operations on the TBLPTR only affect the low-order
21 bits.
TABLE 5-1:
TABLE POINTER BOUNDARIES
Figure 5-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
FIGURE 5-3:
21
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU
16
15
TBLPTRH
8
7
TBLPTRL
0
ERASE – TBLPTR
WRITE – TBLPTR
READ – TBLPTR
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5.3
Reading the Flash Program
Memory
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
FIGURE 5-4:
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 5-4
shows the interface between the internal program
memory and the TABLAT.
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
Instruction Register
(IR)
EXAMPLE 5-1:
FETCH
TBLRD
TBLPTR = xxxxx0
TABLAT
Read Register
READING A FLASH PROGRAM MEMORY WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVFW
MOVWF
TABLAT, W
WORD_EVEN
TABLAT, W
WORD_ODD
2003-2013 Microchip Technology Inc.
; read into TABLAT and increment
; get data
; read into TABLAT and increment
; get data
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5.4
5.4.1
Erasing Flash Program Memory
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
bulk erased. Word erase in the Flash array is not
supported.
The sequence of events for erasing a block of internal
program memory location is:
1.
When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR point to the block being erased.
TBLPTR are ignored.
2.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash program memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
3.
4.
5.
6.
For protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 5-2:
FLASH PROGRAM MEMORY
ERASE SEQUENCE
7.
8.
9.
Load Table Pointer with address of row being
erased.
Set the EECON1 register for the erase
operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program
memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
Disable interrupts.
Write 55h to EECON2.
Write AAh to EECON2.
Set the WR bit. This will begin the row erase
cycle.
The CPU will stall for duration of the erase
(about 2 ms using internal timer).
Execute a NOP.
Re-enable interrupts.
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
EECON1,
EECON1,
EECON1,
EECON1,
INTCON,
55h
EECON2
AAh
EECON2
EECON1,
;
;
;
;
;
ERASE_ROW
Required
Sequence
DS39609C-page 66
EEPGD
CFGS
WREN
FREE
GIE
point to Flash program memory
access Flash program memory
enable write to memory
enable Row Erase operation
disable interrupts
; write 55H
WR
INTCON, GIE
; write AAH
; start erase (CPU stall)
; re-enable interrupts
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5.5
Writing to Flash Program Memory
The minimum programming block is 4 words or 8 bytes.
Word or byte programming is not supported.
Table writes are used internally to load the holding registers needed to program the Flash memory. There are
8 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction has to be executed 8 times for
each programming operation. All of the table write
operations will essentially be short writes, because only
FIGURE 5-5:
the holding registers are written. At the end of updating
8 registers, the EECON1 register must be written to, to
start the programming operation with a long write.
The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device for byte or word operations.
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
TBLPTR = xxxxx0
8
TBLPTR = xxxxx1
Holding Register
TBLPTR = xxxxx2
Holding Register
8
TBLPTR = xxxxx7
Holding Register
Holding Register
Program Memory
5.5.1
FLASH PROGRAM MEMORY
WRITE SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
8.
Read 64 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer with address being erased.
Do the row erase procedure.
Load Table Pointer with address of first byte
being written.
Write the first 8 bytes into the holding registers
with auto-increment.
Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory
• clear the CFGS bit to access program
memory
• set WREN to enable byte writes
Disable interrupts.
2003-2013 Microchip Technology Inc.
9.
10.
11.
12.
13.
14.
15.
16.
Write 55h to EECON2.
Write AAh to EECON2.
Set the WR bit. This will begin the write cycle.
The CPU will stall for duration of the write (about
2 ms using internal timer).
Execute a NOP.
Re-enable interrupts.
Repeat steps 6-14 seven times, to write
64 bytes.
Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 5-3.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the eight bytes
in the holding register.
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EXAMPLE 5-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D’64
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
TBLRD*+
MOVF
MOVWF
DECFSZ
BRA
TABLAT, W
POSTINC0
COUNTER
READ_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
; number of bytes in erase block
; point to buffer
; Load TBLPTR with the base
; address of the memory block
READ_BLOCK
;
;
;
;
;
read into TABLAT, and inc
get data
store data
done?
repeat
MODIFY_WORD
; point to buffer
; update buffer word
ERASE_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
Required
MOVLW
Sequence
MOVWF
BSF
NOP
BSF
TBLRD*WRITE_BUFFER_BACK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
PROGRAM_LOOP
MOVLW
MOVWF
WRITE_WORD_TO_HREGS
MOVFF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
;
;
;
;
;
point to Flash program memory
access Flash program memory
enable write to memory
enable Row Erase operation
disable interrupts
; write 55H
; write AAH
; start erase (CPU stall)
INTCON, GIE
; re-enable interrupts
; dummy read decrement
8
COUNTER_HI
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
; number of write buffer groups of 8 bytes
8
COUNTER
; number of bytes in holding register
POSTINC0, WREG
;
;
;
;
;
TBLWT+*
DECFSZ COUNTER
BRA
WRITE_WORD_TO_HREGS
DS39609C-page 68
; load TBLPTR with the base
; address of the memory block
; point to buffer
get low byte of buffer data
present data to table latch
write data, perform a short write
to internal TBLWT holding register.
loop until buffers are full
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EXAMPLE 5-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
DECFSZ
BRA
BCF
Required
Sequence
5.5.2
EECON1,
EECON1,
EECON1,
INTCON,
55h
EECON2
AAh
EECON2
EECON1,
EEPGD
CFGS
WREN
GIE
;
;
;
;
point to Flash program memory
access Flash program memory
enable write to memory
disable interrupts
; write 55H
; write AAH
; start program (CPU stall)
WR
INTCON, GIE
COUNTER_HI
PROGRAM_LOOP
EECON1, WREN
; re-enable interrupts
; loop until done
; disable write to memory
WRITE VERIFY
5.5.4
Depending on the application, good programming
practice may dictate that the value written to the memory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
5.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
TABLE 5-2:
Name
TBLPTRU
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 23.0 “Special Features of the
CPU” for more detail.
5.6
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and reprogrammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset, or a
WDT Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
PROTECTION AGAINST
SPURIOUS WRITES
Flash Program Operation During
Code Protection
See Section 23.0 “Special Features of the CPU” for
details on code protection of Flash program memory.
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Bit 7
Bit 6
Bit 5
—
—
bit 21
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Program Memory Table Pointer Upper Byte
(TBLPTR)
Value on
POR, BOR
Value on
all other
Resets
--00 0000
--00 0000
TBPLTRH
Program Memory Table Pointer High Byte (TBLPTR)
0000 0000
0000 0000
TBLPTRL
Program Memory Table Pointer High Byte (TBLPTR)
0000 0000
0000 0000
TABLAT
Program Memory Table Latch
0000 0000
0000 0000
0000 0000
0000 0000
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
EECON2
EEPROM Control Register 2 (not a physical register)
INTE
RBIE
TMR0IF
INTF
RBIF
—
—
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000
uu-0 u000
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
---1 1111
---1 1111
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
---0 0000
---0 0000
PIE2
—
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
---0 0000
---0 0000
EECON1
Legend:
x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
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NOTES:
DS39609C-page 70
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6.0
Note:
EXTERNAL MEMORY
INTERFACE
6.1
The External Memory Interface is not
implemented on PIC18F6X20 (64-pin)
devices.
The External Memory Interface is a feature of the
PIC18F8X20 devices that allows the controller to
access external memory devices (such as Flash,
EPROM, SRAM, etc.) as program or data memory.
The physical implementation of the interface uses 27
pins. These pins are reserved for external address/data
bus functions; they are multiplexed with I/O port pins on
four ports. Three I/O ports are multiplexed with the
address/data bus, while the fourth port is multiplexed
with the bus control signals. The I/O port functions are
enabled when the EBDIS bit in the MEMCON register
is set (see Register 6-1). A list of the multiplexed pins
and their functions is provided in Table 6-1.
As implemented in the PIC18F8X20 devices, the
interface operates in a similar manner to the external
memory interface introduced on PIC18C601/801
microcontrollers. The most notable difference is that
the interface on PIC18F8X20 devices only operates in
16-bit modes. The 8-bit mode is not supported.
As previously noted, PIC18F8X20 controllers are
capable of operating in any one of four program
memory modes, using combinations of on-chip and
external program memory. The functions of the multiplexed port pins depend on the program memory
mode selected, as well as the setting of the EBDIS bit.
In Microprocessor Mode, the external bus is always
active and the port pins have only the external bus
function.
In Microcontroller Mode, the bus is not active and
the pins have their port functions only. Writes to the
MEMCOM register are not permitted.
In Microprocessor with Boot Block or Extended
Microcontroller Mode, the external program memory
bus shares I/O port functions on the pins. When the
device is fetching or doing table read/table write
operations on the external program memory space, the
pins will have the external bus function. If the device is
fetching and accessing internal program memory locations only, the EBDIS control bit will change the pins
from external memory to I/O port functions. When
EBDIS = 0, the pins function as the external bus.
When EBDIS = 1, the pins function as I/O ports.
For a more complete discussion of the operating modes
that use the external memory interface, refer to
Section 4.1.1 “PIC18F8X20 Program Memory
Modes”.
REGISTER 6-1:
Program Memory Modes and the
External Memory Interface
Note:
Maximum FOSC for the PIC18FX520 is
limited to 25 MHz when using the external
memory interface.
MEMCON REGISTER
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
EBDIS
—
WAIT1
WAIT0
—
—
WM1
WM0
bit7
bit0
bit 7
EBDIS: External Bus Disable bit
1 = External system bus disabled, all external bus drivers are mapped as I/O ports
0 = External system bus enabled and I/O ports are disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
WAIT: Table Reads and Writes Bus Cycle Wait Count bits
11 = Table reads and writes will wait 0 TCY
10 = Table reads and writes will wait 1 TCY
01 = Table reads and writes will wait 2 TCY
00 = Table reads and writes will wait 3 TCY
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
WM: TBLWRT Operation with 16-bit Bus bits
1x = Word Write mode: TABLAT and TABLAT word output, WRH active when
TABLAT written
01 = Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB)
will activate
00 = Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
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x = Bit is unknown
DS39609C-page 71
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If the device fetches or accesses external memory
while EBDIS = 1, the pins will switch to external bus. If
the EBDIS bit is set by a program executing from
external memory, the action of setting the bit will be
delayed until the program branches into the internal
memory. At that time, the pins will change from
external bus to I/O ports.
TABLE 6-1:
When the device is executing out of internal memory
(EBDIS = 0) in Microprocessor with Boot Block mode,
or Extended Microcontroller mode, the control signals
will NOT be active. They will go to a state where the
AD and A are tri-state; the CE, OE,
WRH, WRL, UB and LB signals are ‘1’ and ALE and
BA0 are ‘0’.
PIC18F8X20 EXTERNAL BUS – I/O PORT FUNCTIONS
Name
Port
Bit
Function
RD0/AD0
PORTD
bit 0
Input/Output or System Bus Address bit 0 or Data bit 0.
RD1/AD1
PORTD
bit 1
Input/Output or System Bus Address bit 1 or Data bit 1.
RD2/AD2
PORTD
bit 2
Input/Output or System Bus Address bit 2 or Data bit 2.
RD3/AD3
PORTD
bit 3
Input/Output or System Bus Address bit 3 or Data bit 3.
RD4/AD4
PORTD
bit 4
Input/Output or System Bus Address bit 4 or Data bit 4.
RD5/AD5
PORTD
bit 5
Input/Output or System Bus Address bit 5 or Data bit 5.
RD6/AD6
PORTD
bit 6
Input/Output or System Bus Address bit 6 or Data bit 6.
RD7/AD7
PORTD
bit 7
Input/Output or System Bus Address bit 7 or Data bit 7.
RE0/AD8
PORTE
bit 0
Input/Output or System Bus Address bit 8 or Data bit 8.
RE1/AD9
PORTE
bit 1
Input/Output or System Bus Address bit 9 or Data bit 9.
RE2/AD10
PORTE
bit 2
Input/Output or System Bus Address bit 10 or Data bit 10.
RE3/AD11
PORTE
bit 3
Input/Output or System Bus Address bit 11 or Data bit 11.
RE4/AD12
PORTE
bit 4
Input/Output or System Bus Address bit 12 or Data bit 12.
RE5/AD13
PORTE
bit 5
Input/Output or System Bus Address bit 13 or Data bit 13.
RE6/AD14
PORTE
bit 6
Input/Output or System Bus Address bit 14 or Data bit 14.
RE7/AD15
PORTE
bit 7
Input/Output or System Bus Address bit 15 or Data bit 15.
RH0/A16
PORTH
bit 0
Input/Output or System Bus Address bit 16.
RH1/A17
PORTH
bit 1
Input/Output or System Bus Address bit 17.
RH2/A18
PORTH
bit 2
Input/Output or System Bus Address bit 18.
RH3/A19
PORTH
bit 3
Input/Output or System Bus Address bit 19.
RJ0/ALE
PORTJ
bit 0
Input/Output or System Bus Address Latch Enable (ALE) Control pin.
RJ1/OE
PORTJ
bit 1
Input/Output or System Bus Output Enable (OE) Control pin.
RJ2/WRL
PORTJ
bit 2
Input/Output or System Bus Write Low (WRL) Control pin.
RJ3/WRH
PORTJ
bit 3
Input/Output or System Bus Write High (WRH) Control pin.
RJ4/BA0
PORTJ
bit 4
Input/Output or System Bus Byte Address bit 0.
RJ5/CE
PORTJ
bit 5
Input/Output or System Bus Chip Enable (CE) Control pin.
RJ6/LB
PORTJ
bit 6
Input/Output or System Bus Lower Byte Enable (LB) Control pin.
RJ7/UB
PORTJ
bit 7
Input/Output or System Bus Upper Byte Enable (UB) Control pin.
DS39609C-page 72
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
6.2
16-bit Mode
The External Memory Interface implemented in
PIC18F8X20 devices operates only in 16-bit mode.
The mode selection is not software configurable, but is
programmed via the configuration bits.
The WM bits in the MEMCON register determine
three types of connections in 16-bit mode. They are
referred to as:
• 16-bit Byte Write
• 16-bit Word Write
• 16-bit Byte Select
These three different configurations allow the designer
maximum flexibility in using 8-bit and 16-bit memory
devices.
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits A are
available on the External Memory Interface bus.
Following the address latch, the Output Enable signal
(OE) will enable both bytes of program memory at once
to form a 16-bit instruction word. The Chip Enable
signal (CE) is active at any time that the microcontroller
accesses external memory, whether reading or writing;
it is inactive (asserted high) whenever the device is in
Sleep mode.
FIGURE 6-1:
In Byte Select mode, JEDEC standard Flash memories
will require BA0 for the byte address line and one I/O
line to select between Byte and Word mode. The other
16-bit modes do not need BA0. JEDEC standard static
RAM memories will use the UB or LB signals for byte
selection.
6.2.1
16-BIT BYTE WRITE MODE
Figure 6-1 shows an example of 16-bit Byte Write
mode for PIC18F8X20 devices. This mode is used for
two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash
devices. It allows table writes to byte-wide external
memories.
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
16-BIT BYTE WRITE MODE EXAMPLE
D
PIC18F8X20
AD
(MSB)
373
(LSB)
A
A
A
D
D
D
CE
AD
373
OE
D
CE
WR(1)
OE
WR(1)
ALE
A
CE
OE
WRH
WRL
Address Bus
Data Bus
Control Lines
Note 1:
This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
2003-2013 Microchip Technology Inc.
DS39609C-page 73
PIC18F6520/8520/6620/8620/6720/8720
6.2.2
16-BIT WORD WRITE MODE
Figure 6-2 shows an example of 16-bit Word Write
mode for PIC18F8X20 devices. This mode is used for
word-wide memories, which includes some of the
EPROM and Flash type memories. This mode allows
opcode fetches and table reads from all forms of 16-bit
memory and table writes to any type of word-wide
external memories. This method makes a distinction
between TBLWT cycles to even or odd addresses.
During a TBLWT cycle to an even address
(TBLPTR = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is
tri-stated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 6-2:
During a TBLWT cycle to an odd address
(TBLPTR = 1), the TABLAT data is presented on
the upper byte of the AD15:AD0 bus. The contents of
the holding latch are presented on the lower byte of the
AD15:AD0 bus.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSb of TBLPTR, but it is left unconnected. Instead,
the UB and LB signals are active to select both bytes.
The obvious limitation to this method is that the table
write must be done in pairs on a specific word boundary
to correctly write a word location.
16-BIT WORD WRITE MODE EXAMPLE
PIC18F8X20
AD
373
A
D
A
D
CE
AD
JEDEC Word
EPROM Memory
OE
WR(1)
373
ALE
A
CE
OE
WRH
Address Bus
Data Bus
Control Lines
Note 1:
DS39609C-page 74
This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
6.2.3
16-BIT BYTE SELECT MODE
Figure 6-3 shows an example of 16-bit Byte Select
mode for PIC18F8X20 devices. This mode allows table
write operations to word-wide external memories with
byte selection capability. This generally includes both
word-wide Flash and SRAM devices.
During a TBLWT cycle, the TABLAT data is presented
on the upper and lower byte of the AD15:AD0 bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written, based on the Least
Significant bit of the TBLPTR register.
FIGURE 6-3:
Flash and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
16-BIT BYTE SELECT MODE EXAMPLE
PIC18F8X20
AD
373
A
A
JEDEC Word
Flash Memory
D
D
138
AD
373
CE
A0
ALE
BYTE/WORD
OE WR(1)
A
OE
WRH
WRL
A
A
BA0
JEDEC Word
SRAM Memory
I/O
D
D
CE
LB
LB
UB
UB
OE
WR(1)
Address Bus
Data Bus
Control Lines
Note 1:
This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
2003-2013 Microchip Technology Inc.
DS39609C-page 75
PIC18F6520/8520/6620/8620/6720/8720
6.2.4
16-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 6-4 through Figure 6-6.
FIGURE 6-4:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE)
Q1
Q1
Apparent Q
Actual Q
Q2
Q2
Q3
Q3
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
00h
A
3AABh
AD
Q4
Q1
Q4
Q2
Q4
Q3
Q4
Q4
0Ch
0E55h
9256h
CF33h
BA0
ALE
OE
WRH
‘1’
‘1’
WRL
‘1’
‘1’
CE
‘0’
‘0’
1 TCY Wait
Memory
Cycle
Instruction
Execution
FIGURE 6-5:
Opcode Fetch
MOVLW 55h
from 007556h
Table Read
of 92h
from 199E67h
TBLRD Cycle 1
TBLRD Cycle 2
EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED
MICROCONTROLLER MODE)
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
0Ch
A
CF33h
AD
9256h
CE
ALE
OE
Memory
Cycle
Opcode Fetch
TBLRD *
from 000100h
Opcode Fetch
MOVLW 55h
from 000102h
TBLRD 92h
from 199E67h
Instruction
Execution
INST(PC-2)
TBLRD Cycle 1
TBLRD Cycle 2
DS39609C-page 76
Opcode Fetch
ADDLW 55h
from 000104h
MOVLW
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 6-6:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE)
Q1
Q2
Q4
Q1
Q2
3AAAh
Q3
Q4
Q1
00h
00h
A
AD
Q3
0003h
3AABh
0E55h
CE
ALE
OE
Memory
Cycle
Instruction
Execution
Opcode Fetch
SLEEP
from 007554h
Opcode Fetch
MOVLW 55h
from 007556h
INST(PC-2)
SLEEP
2003-2013 Microchip Technology Inc.
Sleep Mode, Bus Inactive
DS39609C-page 77
PIC18F6520/8520/6620/8620/6720/8720
NOTES:
DS39609C-page 78
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
7.0
DATA EEPROM MEMORY
The data EEPROM is readable and writable during
normal operation over the entire VDD range. The data
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).
There are five SFRs used to read and write the
program and data EEPROM memory. These registers
are:
•
•
•
•
•
EECON1
EECON2
EEDATA
EEADRH
EEADR
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write. EEADR and
EEADRH hold the address of the EEPROM location
being accessed. These devices have 1024 bytes of
data EEPROM with an address range from 00h to
3FFh.
The EEPROM data memory is rated for high erase/
write cycles. A byte write automatically erases the location and writes the new data (erase-before-write). The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature, as well as
from chip to chip. Please refer to parameter D122 (see
Section 26.0 “Electrical Characteristics”) for exact
limits.
7.1
The address register pair can address up to a maximum of 1024 bytes of data EEPROM. The two Most
Significant bits of the address are stored in EEADRH,
while the remaining eight Least Significant bits are
stored in EEADR. The six Most Significant bits of
EEADRH are unused and are read as ‘0’.
7.2
EECON1 and EECON2 Registers
EECON1 is the control register for EEPROM memory
accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the EEPROM write sequence.
Control bits, RD and WR, initiate read and write operations, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal operation. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR) due to the Reset condition forcing the
contents of the registers to zero.
Note:
2003-2013 Microchip Technology Inc.
EEADR and EEADRH
Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.
DS39609C-page 79
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 7-1:
EECON1 REGISTER (ADDRESS FA6h)
R/W-x
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
EEPGD: Flash Program/Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access configuration or calibration registers
0 = Access Flash program or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR or any WDT Reset during self-timed programming in normal operation)
0 = The write operation completed
Note:
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
bit 2
WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle, or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bit
can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
0 = Does not initiate an EEPROM read
Legend:
DS39609C-page 80
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
7.3
Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADRH:EEADR register pair, clear the
EEPGD control bit (EECON1), clear the CFGS
EXAMPLE 7-1:
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
MOVF
7.4
control bit (EECON1) and then set the RD control
bit (EECON1). The data is available for the very
next instruction cycle; therefore, the EEDATA register
can be read by the next instruction. EEDATA will hold
this value until another read operation, or until it is
written to by the user (during a write operation).
DATA EEPROM READ
DATA_EE_ADDRH
EEADRH
DATA_EE_ADDR
EEADR
EECON1, EEPGD
EECON1, CFGS
EECON1, RD
EEDATA, W
;
;
;
;
;
;
;
;
Upper bits of Data Memory Address to read
Lower bits of Data Memory Address to read
Point to DATA memory
Access EEPROM
EEPROM Read
W = EEDATA
Writing to the Data EEPROM
Memory
should be kept clear at all times, except when updating
the EEPROM. The WREN bit is not cleared
by hardware
To write an EEPROM data location, the address must
first be written to the EEADRH:EEADR register pair
and the data written to the EEDATA register. Then the
sequence in Example 7-2 must be followed to initiate
the write cycle.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
After a write sequence has been initiated, EECON1,
EEADRH, EEADR and EEDATA cannot be modified.
The WR bit will be inhibited from being set unless the
WREN bit is set. Both WR and WREN cannot be set
with the same instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. The user may either
enable this interrupt, or poll this bit. EEIF must be
cleared by software.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
EXAMPLE 7-2:
Required
Sequence
DATA EEPROM WRITE
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
DATA_EE_ADDRH
EEADRH
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDATA
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
;
;
;
;
;
;
;
;
;
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
;
;
;
;
;
;
;
BCF
EECON1, WREN
; User code execution
; Disable writes on write complete (EEIF set)
2003-2013 Microchip Technology Inc.
Upper bits of Data Memory Address to write
Lower bits of Data Memory Address to write
Data Memory Value to write
Point to DATA memory
Access EEPROM
Enable writes
Disable Interrupts
Write 55h
Write AAh
Set WR bit to begin write
Enable Interrupts
DS39609C-page 81
PIC18F6520/8520/6620/8620/6720/8720
7.5
Write Verify
7.8
Depending on the application, good programming
practice may dictate that the value written to the memory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
7.6
Protection Against Spurious Write
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
Using the Data EEPROM
The data EEPROM is a high endurance, byte addressable array that has been optimized for the storage of
frequently changing information (e.g., program variables or other data that are updated often). Frequently
changing values will typically be updated more often
than specification D124. If this is not the case, an array
refresh must be performed. For this reason, variables
that change infrequently (such as constants, IDs,
calibration, etc.) should be stored in Flash program
memory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
Note:
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
7.7
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124.
Operation During Code-Protect
Data EEPROM memory has its own code-protect
mechanism. External read and write operations are
disabled if either of these mechanisms are enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect configuration bit. Refer to Section 23.0
“Special Features of the CPU” for additional
information.
EXAMPLE 7-3:
DATA EEPROM REFRESH ROUTINE
CLRF
CLRF
BCF
BCF
BCF
BSF
EEADR
EEADRH
EECON1,
EECON1,
INTCON,
EECON1,
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
INCFSZ
BRA
EECON1, RD
55h
EECON2
AAh
EECON2
EECON1, WR
EECON1, WR
$-2
EEADR, F
Loop
EEADRH, F
Loop
BCF
BSF
EECON1, WREN
INTCON, GIE
CFGS
EEPGD
GIE
WREN
Loop
DS39609C-page 82
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Start at address 0
Set for memory
Set for Data EEPROM
Disable interrupts
Enable writes
Loop to refresh array
Read current address
Write 55h
Write AAh
Set WR bit to begin write
Wait for write to complete
Increment
Not zero,
Increment
Not zero,
address
do it again
the high address
do it again
; Disable writes
; Enable interrupts
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 7-1:
Name
INTCON
EEADRH
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Bit 7
Bit 6
Bit 5
Bit 4
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
—
—
—
—
Bit 3
Bit 2
RBIE
TMR0IF
—
—
Bit 1
Bit 0
INT0IF
RBIF
EE Addr Register High
Value on
POR, BOR
Value on
all other
Resets
0000 0000
0000 0000
---- --00
---- --00
EEADR
EEPROM Address Register
0000 0000
0000 0000
EEDATA
EEPROM Data Register
0000 0000
0000 0000
EECON2
EEPROM Control Register 2 (not a physical register)
---- ----
---- ----
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000
uu-0 u000
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
---1 1111
---1 1111
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
---0 0000
---0 0000
PIE2
—
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
---0 0000
---0 0000
EECON1
Legend:
x = unknown, u = unchanged, r = reserved, – = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
2003-2013 Microchip Technology Inc.
DS39609C-page 83
PIC18F6520/8520/6620/8620/6720/8720
NOTES:
DS39609C-page 84
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
8.0
8 X 8 HARDWARE MULTIPLIER
8.1
Introduction
8.2
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX20 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored in the 16-bit product register
pair (PRODH:PRODL). The multiplier does not affect
any flags in the ALUSTA register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-1:
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
MOVF
MULWF
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
ARG1, W
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH, F
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
;
;
;
;
;
;
;
;
;
;
ARG1 * ARG2 ->
PRODH:PRODL
Test Sign Bit
PRODH = PRODH
- ARG1
Test Sign Bit
PRODH = PRODH
- ARG2
PERFORMANCE COMPARISON
Routine
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 8-2:
Table 8-1 shows a performance comparison between
enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
TABLE 8-1:
Operation
Multiply Method
Without hardware multiply
Time
Program
Memory
(Words)
Cycles
(Max)
@ 40 MHz
@ 10 MHz
@ 4 MHz
13
69
6.9 s
27.6 s
69 s
Hardware multiply
1
1
100 ns
400 ns
1 s
Without hardware multiply
33
91
9.1 s
36.4 s
91 s
Hardware multiply
6
6
600 ns
2.4 s
6 s
Without hardware multiply
21
242
24.2 s
96.8 s
242 s
Hardware multiply
28
28
2.8 s
11.2 s
28 s
Without hardware multiply
52
254
25.4 s
102.6 s
254 s
Hardware multiply
35
40
4.0 s
16.0 s
40 s
2003-2013 Microchip Technology Inc.
DS39609C-page 85
PIC18F6520/8520/6620/8620/6720/8720
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 8-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 8-1:
RES3:RES0
=
=
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L)
EQUATION 8-2:
RES3:RES0
=
ARG1H:ARG1L ARG2H:ARG2L
=
(ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L) +
(-1 ARG2H ARG1H:ARG1L 216) +
(-1 ARG1H ARG2H:ARG2L 216)
EXAMPLE 8-4:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
16 x 16 SIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
ARG1L * ARG2H ->
PRODH:PRODL
Add cross
products
ARG1H * ARG2L ->
PRODH:PRODL
Add cross
products
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the arguments, each argument pairs’ Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
DS39609C-page 86
;
;
;
;
;
;
;
;
ARG1L * ARG2H ->
PRODH:PRODL
Add cross
products
;
;
;
;
;
;
;
;
;
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
;
;
;
;
;
;
;
;
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
;
;
;
;
;
;
;
;
;
ARG1H * ARG2L ->
PRODH:PRODL
Add cross
products
;
;
SIGN_ARG1
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
;
CONT_CODE
:
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
9.0
INTERRUPTS
The PIC18FXX20 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high or a low
priority level. The high priority interrupt vector is at
000008h, while the low priority interrupt vector is at
000018h. High priority interrupt events will override any
low priority interrupts that may be in progress.
There are thirteen registers which are used to control
interrupt operation. They are:
•
•
•
•
•
•
•
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2, PIR3
PIE1, PIE2, PIE3
IPR1, IPR2, IPR3
It is recommended that the Microchip header files,
supplied with MPLAB® IDE, be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
Each interrupt source has three bits to control its
operation. The functions of these bits are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC® mid-range devices. In Compatibility mode, the interrupt priority bits for each source
have no effect. INTCON is the PEIE bit, which
enables/disables all peripheral interrupt sources.
INTCON is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
The interrupt priority feature is enabled by setting the
IPEN bit (RCON). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON) enables all
interrupts that have the priority bit set. Setting the GIEL
bit (INTCON) enables all interrupts that have the
priority bit cleared. When the interrupt flag, enable bit
and appropriate global interrupt enable bit are set, the
interrupt will vector immediately to address 000008h or
000018h, depending on the priority level. Individual
interrupts can be disabled through their corresponding
enable bits.
2003-2013 Microchip Technology Inc.
DS39609C-page 87
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 9-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Wake-up if in Sleep mode
Interrupt to CPU
Vector to Location
0008h
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
GIEH/GIE
TMR1IF
TMR1IE
TMR1IP
IPEN
IPEN
XXXXIF
XXXXIE
XXXXIP
GIEL/PEIE
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR1IF
TMR1IE
TMR1IP
RBIF
RBIE
RBIP
XXXXIF
XXXXIE
XXXXIP
Additional Peripheral Interrupts
DS39609C-page 88
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
GIEL/PEIE
GIE/GEIH
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
9.1
INTCON Registers
Note:
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 9-1:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
INTCON REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
bit 7
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN (RCON) = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN (RCON) = 1:
1 = Enables all high priority interrupts
0 = Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN (RCON) = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN (RCON) = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note:
A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 89
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 9-2:
INTCON2 REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5
INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4
INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3
INTEDG3: External Interrupt 3 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 2
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
INT3IP: INT3 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Note:
DS39609C-page 90
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 9-3:
INTCON3 REGISTER
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
bit 7
bit 0
bit 7
INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
INT3IE: INT3 External Interrupt Enable bit
1 = Enables the INT3 external interrupt
0 = Disables the INT3 external interrupt
bit 4
INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2
INT3IF: INT3 External Interrupt Flag bit
1 = The INT3 external interrupt occurred (must be cleared in software)
0 = The INT3 external interrupt did not occur
bit 1
INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
2003-2013 Microchip Technology Inc.
DS39609C-page 91
PIC18F6520/8520/6620/8620/6720/8720
9.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON).
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Flag Registers (PIR1, PIR2 and PIR3).
REGISTER 9-4:
2: User software should ensure the appropriate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
PSPIF
(1)
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIF
RC1IF
TX1IF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5
RC1IF: USART1 Receive Interrupt Flag bit
1 = The USART1 receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The USART1 receive buffer is empty
bit 4
TX1IF: USART Transmit Interrupt Flag bit
1 = The USART1 transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The USART1 transmit buffer is full
bit 3
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.
Legend:
DS39609C-page 92
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 9-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
CMIF: Comparator Interrupt Flag bit
1 = The comparator input has changed (must be cleared in software)
0 = The comparator input has not changed
bit 5
Unimplemented: Read as ‘0’
bit 4
EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1 = The write operation is complete (must be cleared in software)
0 = The write operation is not complete, or has not been started
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred while the SSP module (configured in I2C Master mode)
was transmitting (must be cleared in software)
0 = No bus collision occurred
bit 2
LVDIF: Low-Voltage Detect Interrupt Flag bit
1 = A low-voltage condition occurred (must be cleared in software)
0 = The device voltage is above the Low-Voltage Detect trip point
bit 1
TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 0
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 or TMR3 register capture occurred (must be cleared in software)
0 = No TMR1 or TMR3 register capture occurred
Compare mode:
1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1 or TMR3 register compare match occurred
PWM mode:
Unused in this mode.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 93
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 9-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
U-0
U-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
bit 7
bit 0
bit 7- 6
Unimplemented: Read as ‘0’
bit 5
RC2IF: USART2 Receive Interrupt Flag bit
1 = The USART2 receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The USART2 receive buffer is empty
bit 4
TX2IF: USART2 Transmit Interrupt Flag bit
1 = The USART2 transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The USART2 transmit buffer is full
bit 3
TMR4IF: TMR3 Overflow Interrupt Flag bit
1 = TMR4 register overflowed (must be cleared in software)
0 = TMR4 register did not overflow
bit 2-0
CCPxIF: CCPx Interrupt Flag bit (CCP Modules 3, 4 and 5)
Capture mode:
1 = A TMR1 or TMR3 register capture occurred (must be cleared in software)
0 = No TMR1 or TMR3 register capture occurred
Compare mode:
1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1 or TMR3 register compare match occurred
PWM mode:
Unused in this mode.
Legend:
DS39609C-page 94
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2 and PIE3).
When the IPEN bit (RCON) is ‘0’, the PEIE bit must
be set to enable any of these peripheral interrupts.
REGISTER 9-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PSPIE(1)
ADIE
RC1IE
TX1IE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5
RC1IE: USART1 Receive Interrupt Enable bit
1 = Enables the USART1 receive interrupt
0 = Disables the USART1 receive interrupt
bit 4
TX1IE: USART1 Transmit Interrupt Enable bit
1 = Enables the USART1 transmit interrupt
0 = Disables the USART1 transmit interrupt
bit 3
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 95
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 9-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
bit 5
Unimplemented: Read as ‘0’
bit 4
EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1 = Enables the write operation interrupt
0 = Disables the write operation interrupt
bit 3
BCLIE: Bus Collision Interrupt Enable bit
1 = Enables the bus collision interrupt
0 = Disables the bus collision interrupt
bit 2
LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = Enables the Low-Voltage Detect interrupt
0 = Disables the Low-Voltage Detect interrupt
bit 1
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enables the TMR3 overflow interrupt
0 = Disables the TMR3 overflow interrupt
bit 0
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
DS39609C-page 96
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 9-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5
RC2IE: USART2 Receive Interrupt Enable bit
1 = Enables the USART2 receive interrupt
0 = Disables the USART2 receive interrupt
bit 4
TX2IE: USART2 Transmit Interrupt Enable bit
1 = Enables the USART2 transmit interrupt
0 = Disables the USART2 transmit interrupt
bit 3
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enables the TMR4 to PR4 match interrupt
0 = Disables the TMR4 to PR4 match interrupt
bit 2-0
CCPxIE: CCPx Interrupt Enable bit (CCP Modules 3, 4 and 5)
1 = Enables the CCPx interrupt
0 = Disables the CCPx interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 97
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9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority Registers (IPR1, IPR2 and IPR3). The
operation of the priority bits requires that the Interrupt
Priority Enable (IPEN) bit be set.
REGISTER 9-10:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PSPIP(1)
ADIP
RC1IP
TX1IP
SSPIP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)
1 = High priority
0 = Low priority
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RC1IP: USART1 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TX1IP: USART1 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.
Legend:
DS39609C-page 98
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2003-2013 Microchip Technology Inc.
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REGISTER 9-11:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
U-0
R/W-1
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
CMIP: Comparator Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
Unimplemented: Read as ‘0’
bit 4
EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
LVDIP: Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 99
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 9-12:
IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5
RC2IP: USART2 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TX2IP: USART2 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
TMR4IP: TMR4 to PR4 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2-0
CCPxIP: CCPx Interrupt Priority bit (CCP Modules 3, 4 and 5)
1 = High priority
0 = Low priority
Legend:
DS39609C-page 100
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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9.5
RCON Register
The RCON register contains the IPEN bit, which is
used to enable prioritized interrupts. The functions of
the other bits in this register are discussed in more
detail in Section 4.14 “RCON Register”.
REGISTER 9-13:
RCON REGISTER
R/W-0
U-0
U-0
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
—
—
RI
TO
PD
POR
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16 Compatibility mode)
bit 6-5
Unimplemented: Read as ‘0’
bit 4
RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-4.
bit 3
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-4.
bit 2
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 4-4.
bit 1
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-4.
bit 0
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-4.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 101
PIC18F6520/8520/6620/8620/6720/8720
9.6
INT0 Interrupt
9.7
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered:
either rising, if the corresponding INTEDGx bit is set in
the INTCON2 register, or falling, if the INTEDGx bit is
clear. When a valid edge appears on the RBx/INTx pin,
the corresponding flag bit, INTxF, is set. This interrupt
can be disabled by clearing the corresponding enable
bit, INTxE. Flag bit, INTxF, must be cleared in software
in the Interrupt Service Routine before re-enabling the
interrupt. All external interrupts (INT0, INT1, INT2 and
INT3) can wake-up the processor from Sleep if bit
INTxIE was set prior to going into Sleep. If the Global
Interrupt Enable bit, GIE, is set, the processor will
branch to the interrupt vector following wake-up.
The interrupt priority for INT, INT2 and INT3 is determined by the value contained in the interrupt priority
bits: INT1IP (INTCON3), INT2IP (INTCON3)
and INT3IP (INTCON2). There is no priority bit
associated with INT0; it is always a high priority
interrupt source.
TMR0 Interrupt
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh 00h) will set flag bit TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L registers (FFFFh 0000h) will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit, TMR0IE (INTCON). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP (INTCON2). See
Section 11.0 “Timer0 Module” for further details on
the Timer0 module.
9.8
PORTB Interrupt-on-Change
An input change on PORTB sets flag bit, RBIF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2).
9.9
Context Saving During Interrupts
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, Status and BSR registers
are saved on the fast return stack. If a fast return from
interrupt is not used (see Section 4.3 “Fast Register
Stack”), the user may need to save the WREG, Status
and BSR registers in software. Depending on the user’s
application, other registers may also need to be saved.
Example 9-1 saves and restores the WREG, Status and
BSR registers during an Interrupt Service Routine.
EXAMPLE 9-1:
MOVWF
MOVFF
MOVFF
;
; USER
;
MOVFF
MOVF
MOVFF
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR located anywhere
ISR CODE
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
DS39609C-page 102
; Restore BSR
; Restore WREG
; Restore STATUS
2003-2013 Microchip Technology Inc.
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10.0
I/O PORTS
10.1
Depending on the device selected, there are either
seven or nine I/O ports available on PIC18FXX20
devices. Some of their pins are multiplexed with one or
more alternate functions from the other peripheral features on the device. In general, when a peripheral is
enabled, that pin may not be used as a general
purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The Data Latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are
driving.
A simplified version of a generic I/O port and its
operation is shown in Figure 10-1.
FIGURE 10-1:
SIMPLIFIED BLOCK
DIAGRAM OF PORT/LAT/
TRIS OPERATION
RD LAT
TRIS
PORTA is a 7-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register, read and write the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA4/
T0CKI pin is a Schmitt Trigger input and an open-drain
output. All other RA port pins have TTL input levels and
full CMOS output drivers.
The RA6 pin is only enabled as a general I/O pin in
ECIO and RCIO Oscillator modes.
The other PORTA pins are multiplexed with analog
inputs and the analog VREF+ and VREF- inputs. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register 1).
Note:
D
WR LAT +
WR Port
Q
CK
Data Latch
Data Bus
RD Port
I/O pin
PORTA, TRISA and LATA
Registers
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA6 and RA4 are configured as
digital inputs.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 10-1:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
2003-2013 Microchip Technology Inc.
PORTA
;
;
;
LATA
;
;
;
0x0F
;
ADCON1 ;
0xCF
;
;
;
TRISA ;
;
INITIALIZING PORTA
Initialize PORTA by
clearing output
data latches
Alternate method
to clear output
data latches
Configure A/D
for digital inputs
Value used to
initialize data
direction
Set RA as inputs
RA as outputs
DS39609C-page 103
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-2:
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 10-3:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
RD LATA
RD LATA
Data
Bus
D
WR LATA
or
PORTA
Data
Bus
WR LATA
or
PORTA
Q
VDD
CK
Q
P
WR TRISA
N
Q
I/O
pin(1)
WR TRISA
CK
Q
CK
Q
N
Data Latch
Data Latch
D
D
VSS
Analog
Input
Mode
Q
TRIS Latch
D
Q
CK
Q
I/O pin(1)
VSS
Schmitt
Trigger
Input
Buffer
TRIS Latch
RD TRISA
RD TRISA
Q
D
TTL
Input
Buffer
Q
D
ENEN
EN
RD PORTA
RD PORTA
TMR0 Clock Input
To A/D Converter and LVD Modules
Note 1:
Note 1:
I/O pins have protection diodes to VDD and VSS.
FIGURE 10-4:
I/O pins have protection diodes to VDD and VSS.
BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O)
ECRA6 or RCRA6 Enable
Data Bus
RD LATA
WR LATA or PORTA
D
Q
CK
Q
VDD
P
Data Latch
WR TRISA
D
Q
CK
Q
N
I/O pin(1)
VSS
TRIS Latch
TTL
Input
Buffer
RD TRISA
ECRA6 or RCRA6 Enable
Q
D
EN
RD PORTA
Note 1:
I/O pins have protection diodes to VDD and VSS.
DS39609C-page 104
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TABLE 10-1:
PORTA FUNCTIONS
Name
RA0/AN0
Bit#
Buffer
bit 0
TTL
Function
Input/output or analog input.
RA1/AN1
bit 1
TTL
Input/output or analog input.
RA2/AN2/VREF-
bit 2
TTL
Input/output or analog input or VREF-.
RA3/AN3/VREF+
bit 3
TTL
Input/output or analog input or VREF+.
RA4/T0CKI
bit 4
ST
Input/output or external clock input for Timer0.
Output is open-drain type.
RA5/AN4/LVDIN
bit 5
TTL
Input/output or slave select input for synchronous serial port or analog
input, or Low-Voltage Detect input.
OSC2/CLKO/RA6
bit 6
TTL
OSC2 or clock output, or I/O pin.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 10-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Value on
all other
Resets
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
RA6
RA5
RA4
RA3
RA2
RA1
RA0
-x0x 0000 -u0u 0000
PORTA
—
LATA
—
LATA Data Output Register
TRISA
—
PORTA Data Direction Register
ADCON1
—
—
VCFG1 VCFG0 PCFG3
-xxx xxxx -uuu uuuu
-111 1111 -111 1111
PCFG2
PCFG1
PCFG0
--00 0000 --00 0000
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’.
Shaded cells are not used by PORTA.
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DS39609C-page 105
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10.2
PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register, read and write the latched output value for
PORTB.
EXAMPLE 10-2:
CLRF
PORTB
CLRF
LATB
MOVLW
0xCF
MOVWF
TRISB
INITIALIZING PORTB
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RB as inputs
RB as outputs
RB as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Note:
The other four PORTB pins (RB7:RB4) have an interrupt-on-change feature. Only pins configured as inputs
can cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
b)
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB3 can be configured by the configuration bit
CCP2MX, as the alternate peripheral pin for the CCP2
module. This is only available when the device is
configured in Microprocessor, Microprocessor with
Boot Block, or Extended Microcontroller operating
modes.
The RB5 pin is used as the LVP programming pin.
When the LVP configuration bit is programmed, this pin
loses the I/O function and become a programming test
function.
Note:
When LVP is enabled, the weak pull-up on
RB5 is disabled.
FIGURE 10-5:
BLOCK DIAGRAM OF
RB7:RB4 PINS
VDD
RBPU(2)
Weak
P Pull-up
Data Bus
WR LATB
or PORTB
Data Latch
D
Q
I/O pin(1)
CK
TRIS Latch
D
WR TRISB
On a Power-on Reset, these pins are
configured as digital inputs.
Four of the PORTB pins (RB3:RB0) are the external
interrupt pins, INT3 through INT0. In order to use these
pins as external interrupts, the corresponding TRISB
bit must be set to ‘1’.
a)
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
Q
TTL
Input
Buffer
CK
ST
Buffer
RD TRISB
RD LATB
Latch
Q
D
RD PORTB
EN
Q1
Set RBIF
Q
D
RD PORTB
From other
RB7:RB4 pins
EN
Q3
RB7:RB5 in Serial Programming Mode
Note 1:
2:
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2).
Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
Clear flag bit RBIF.
DS39609C-page 106
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FIGURE 10-6:
BLOCK DIAGRAM OF RB2:RB0 PINS
VDD
RBPU(2)
Weak
P Pull-up
Data Latch
D
Q
Data Bus
I/O pin(1)
WR Port
CK
TRIS Latch
D
WR TRIS
Q
TTL
Input
Buffer
CK
RD TRIS
Q
D
RD Port
EN
INTx
RD Port
Schmitt Trigger
Buffer
Note
FIGURE 10-7:
1:
2:
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG).
BLOCK DIAGRAM OF RB3 PIN
VDD
RBPU(2)
CCP2MX
Weak
P Pull-up
CCP Output(3)
1
VDD
P
Enable(3)
CCP Output
0
Data Latch
Data Bus
D
WR LATB or
WR PORTB
I/O pin(1)
Q
N
CK
TRIS Latch
D
WR TRISB
CK
VSS
TTL
Input
Buffer
Q
RD TRISB
RD LATB
Q
D
RD PORTB
EN
RD PORTB
CCP2 or INT3
Schmitt Trigger
Buffer
Note
CCP2MX = 0
1:
I/O pin has diode protection to VDD and VSS.
2:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2).
3:
The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device
is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.
2003-2013 Microchip Technology Inc.
DS39609C-page 107
PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
RB0/INT0
bit 0
TTL/ST(1)
Input/output pin or external interrupt input 0.
Internal software programmable weak pull-up.
RB1/INT1
bit 1
TTL/ST(1)
Input/output pin or external interrupt input 1.
Internal software programmable weak pull-up.
RB2/INT2
bit 2
TTL/ST(1)
Input/output pin or external interrupt input 2.
Internal software programmable weak pull-up.
RB3/INT3/CCP2(3)
bit 3
TTL/ST(4)
Input/output pin or external interrupt input 3. Capture2 input/Compare2
output/PWM output (when CCP2MX configuration bit is enabled, all
PIC18F8X20 operating modes except Microcontroller mode).
Internal software programmable weak pull-up.
RB4/KBI0
bit 4
TTL
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB5/KBI1/PGM
bit 5
TTL/ST(2)
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Low-voltage ICSP enable pin.
RB6/KBI2/PGC
bit 6
TTL/ST(2)
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming clock.
RB7/KBI3/PGD
bit 7
TTL/ST(2)
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming data.
Legend:
Note 1:
2:
3:
4:
TTL = TTL input, ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
RC1 is the alternate assignment for CCP2 when CCP2MX is not set (all operating modes except
Microcontroller mode).
This buffer is a Schmitt Trigger input when configured as the CCP2 input.
TABLE 10-4:
Name
PORTB
Function
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
LATB
LATB Data Output Register
xxxx xxxx
uuuu uuuu
TRISB
PORTB Data Direction Register
1111 1111
1111 1111
RBIF
0000 0000
0000 0000
INTCON
GIE/
GIEH
INTCON2
RBPU
INTCON3
INT2IP
Legend:
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
INTEDG0 INTEDG1 INTEDG2 INTEDG3
INT1IP
INT3IE
INT2IE
INT1IE
TMR0IF
INT0IF
TMR0IP
INT3IP
RBIP
1111 1111
1111 1111
INT3IF
INT2IF
INT1IF
1100 0000
1100 0000
x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS39609C-page 108
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
10.3
PORTC, TRISC and LATC
Registers
The pin override value is not loaded into the TRIS
register. This allows read-modify-write of the TRIS
register, without concern due to peripheral overrides.
PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
RC1 is normally configured by configuration bit,
CCP2MX, as the default peripheral pin of the CCP2
module (default/erased state, CCP2MX = 1).
EXAMPLE 10-3:
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register, read and write the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 10-5). PORTC pins have Schmitt Trigger input
buffers.
CLRF
PORTC
CLRF
LATC
MOVLW
0xCF
MOVWF
TRISC
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings.
Note:
INITIALIZING PORTC
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTC by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RC as inputs
RC as outputs
RC as inputs
On a Power-on Reset, these pins are
configured as digital inputs.
FIGURE 10-8:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
PORTC/Peripheral Out Select
Peripheral Data Out
VDD
0
P
1
RD LATC
Data Bus
WR LATC or
WR PORTC
D
Q
CK
Q
I/O pin(1)
Data Latch
D
WR TRISC
CK
Q
TRIS Latch
TRIS OVERRIDE
N
Q
VSS
TRIS
Override
Logic
Pin
Override
Peripheral
RC0
Yes
Timer1 Osc for
Timer1/Timer3
RC1
Yes
Timer1 Osc for
Timer1/Timer3,
CCP2 I/O
RC2
Yes
CCP1 I/O
RC3
Yes
SPI/I2C
Master Clock
RC4
Yes
I2C Data Out
RD TRISC
Schmitt
Trigger
Peripheral Output
Enable(2)
Q
D
EN
RD PORTC
Peripheral Data In
Note 1:
2:
I/O pins have diode protection to VDD and VSS.
Peripheral Output Enable is only active if Peripheral Select is active.
2003-2013 Microchip Technology Inc.
RC5
Yes
SPI Data Out
RC6
Yes
USART1 Async
Xmit, Sync Clock
RC7
Yes
USART1 Sync
Data Out
DS39609C-page 109
PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-5:
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0/T1OSO/T13CKI
bit 0
ST
Input/output port pin, Timer1 oscillator output or Timer1/Timer3
clock input.
RC1/T1OSI/CCP2(1)
bit 1
ST
Input/output port pin, Timer1 oscillator input or Capture2 input/
Compare2 output/PWM output (when CCP2MX configuration bit is
disabled).
RC2/CCP1
bit 2
ST
Input/output port pin or Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
bit 3
ST
RC3 can also be the synchronous serial clock for both SPI and I2C
modes.
RC4/SDI/SDA
bit 4
ST
RC4 can also be the SPI data in (SPI mode) or data I/O (I2C mode).
RC5/SDO
bit 5
ST
Input/output port pin or synchronous serial port data output.
RC6/TX1/CK1
bit 6
ST
Input/output port pin, addressable USART1 asynchronous transmit or
addressable USART1 synchronous clock.
RC7/RX1/DT1
bit 7
ST
Input/output port pin, addressable USART1 asynchronous receive or
addressable USART1 synchronous data.
Legend: ST = Schmitt Trigger input
Note 1: RB3 is the alternate assignment for CCP2 when CCP2MX is set.
TABLE 10-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
LATC
LATC Data Output Register
xxxx xxxx
uuuu uuuu
TRISC
PORTC Data Direction Register
1111 1111
1111 1111
Legend: x = unknown, u = unchanged
DS39609C-page 110
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
10.4
PORTD, TRISD and LATD
Registers
PORTD can also be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control
bit PSPMODE (TRISE). In this mode, the input
buffers are TTL. See Section 10.10 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
EXAMPLE 10-4:
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register, read and write the latched output value for
PORTD.
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or
output.
Note:
CLRF
PORTD
CLRF
LATD
MOVLW
0xCF
MOVWF
TRISD
On a Power-on Reset, these pins are
configured as digital inputs.
INITIALIZING PORTD
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTD by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RD as inputs
RD as outputs
RD as inputs
PORTD is multiplexed with the system bus as the
external memory interface; I/O port functions are only
available when the system bus is disabled, by setting
the EBDIS bit in the MEMCOM register
(MEMCON). When operating as the external memory interface, PORTD is the low-order byte of the
multiplexed address/data bus (AD7:AD0).
FIGURE 10-9:
PORTD BLOCK DIAGRAM IN I/O PORT MODE
PORTD/CCP1 Select
PSPMODE
RD LATD
Data Bus
WR LATD
or PORTD
D
Q
CK
Q
VDD
P
Data Latch
WR TRISD
D
Q
CK
Q
I/O pin(1)
0
N
1
VSS
TRIS Latch
PSP Write
TTL Buffer
RD TRISD
1
Q
D
0
RD PORTD
PSP Read
Note 1:
0
ENEN
Schmitt Trigger
Input Buffer
1
I/O pins have diode protection to VDD and VSS.
2003-2013 Microchip Technology Inc.
DS39609C-page 111
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-10:
PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
EN
RD PORTD
RD LATD
Data Bus
D
WR LATD
or PORTD
CK
Q
Port
Data
I/O pin(1)
0
1
Data Latch
D
WR TRISD
Q
CK
TRIS Latch
TTL
Input
Buffer
RD TRISD
Bus Enable
System Bus Data/TRIS Out
Control
Drive Bus
Instruction Register
Instruction Read
Note 1: I/O pins have protection diodes to VDD and VSS.
DS39609C-page 112
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-7:
PORTD FUNCTIONS
Name
Bit#
Buffer Type
Function
RD0/PSP0/AD0
bit 0
ST/TTL(1)
Input/output port pin, Parallel Slave Port bit 0 or address/data bus bit 0.
bit 1
ST/TTL
(1)
Input/output port pin, Parallel Slave Port bit 1 or address/data bus bit 1.
ST/TTL
(1)
Input/output port pin, Parallel Slave Port bit 2 or address/data bus bit 2.
ST/TTL
(1)
Input/output port pin, Parallel Slave Port bit 3 or address/data bus bit 3.
ST/TTL
(1)
Input/output port pin, Parallel Slave Port bit 4 or address/data bus bit 4.
ST/TTL
(1)
Input/output port pin, Parallel Slave Port bit 5 or address/data bus bit 5.
ST/TTL
(1)
Input/output port pin, Parallel Slave Port bit 6 or address/data bus bit 6.
ST/TTL
(1)
Input/output port pin, Parallel Slave Port bit 7 or address/data bus bit 7.
RD1/PSP1/AD1
RD2/PSP2/AD2
bit 2
RD3/PSP3/AD3
bit 3
RD4/PSP4/AD4
bit 4
RD5/PSP5/AD5
bit 5
RD6/PSP6/AD6
bit 6
RD7/PSP7/AD7
bit 7
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel
Slave Port mode.
TABLE 10-8:
Name
PORTD
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
LATD
LATD Data Output Register
TRISD
PORTD Data Direction Register
1111 1111
1111 1111
PSPCON
IBF
OBF
IBOV
PSPMODE
—
—
—
—
0000 ----
0000 ----
MEMCON
EBDIS
—
WAIT1
WAIT0
—
—
WM1
WM0
0-00 --00
0-00 --00
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
2003-2013 Microchip Technology Inc.
DS39609C-page 113
PIC18F6520/8520/6620/8620/6720/8720
10.5
PORTE, TRISE and LATE
Registers
PORTE is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output (i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATE register,
read and write the latched output value for PORTE.
PORTE is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or
output. PORTE is multiplexed with the CCP module
(Table 10-9).
On PIC18F8X20 devices, PORTE is also multiplexed
with the system bus as the external memory interface;
the I/O bus is available only when the system bus is
disabled, by setting the EBDIS bit in the MEMCON
register (MEMCON). If the device is configured in
Microprocessor or Extended Microcontroller mode,
then the PORTE becomes the high byte of the
address/data bus for the external program memory
interface. In Microcontroller mode, the PORTE
pins become the control inputs for the Parallel Slave
Port when bit PSPMODE (PSPCON) is set. (Refer
to Section 4.1.1 “PIC18F8X20 Program Memory
Modes” for more information on program memory
modes.)
DS39609C-page 114
When the Parallel Slave Port is active, three PORTE
pins (RE0/RD/AD8, RE1/WR/AD9 and RE2/CS/AD10)
function as its control inputs. This automatically occurs
when the PSPMODE bit (PSPCON) is set. Users
must also make certain that bits TRISE are set to
configure the pins as digital inputs and the ADCON1
register is configured for digital I/O. The PORTE PSP
control functions are summarized in Table 10-9.
Pin RE7 can be configured as the alternate peripheral
pin for CCP module 2 when the device is operating in
Microcontroller mode. This is done by clearing the
configuration bit, CCP2MX, in configuration register,
CONFIG3H (CONFIG3H).
Note:
For PIC18F8X20 (80-pin) devices operating in Extended Microcontroller mode,
PORTE defaults to the system bus on
Power-on Reset.
EXAMPLE 10-5:
CLRF
PORTE
CLRF
LATE
MOVLW
0x03
MOVWF
TRISE
INITIALIZING PORTE
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTE by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RE1:RE0 as inputs
RE7:RE2 as outputs
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-11:
PORTE BLOCK DIAGRAM IN I/O MODE
Peripheral Out Select
Peripheral Data Out
VDD
0
P
RD LATE
1
Data Bus
WR LATE
or WR PORTE
D
Q
CK
Q
Data Latch
WR TRISE
D
Q
CK
Q
I/O pin(1)
N
TRIS OVERRIDE
VSS
TRIS
Override
TRIS Latch
RD TRISE
Schmitt
Trigger
Peripheral Enable
Q
D
EN
RD PORTE
Peripheral Data In
Pin
Override
Peripheral
RE0
Yes
External Bus
RE1
Yes
External Bus
RE2
Yes
External Bus
RE3
Yes
External Bus
RE4
Yes
External Bus
RE5
Yes
External Bus
RE6
Yes
External Bus
RE7
Yes
External Bus
Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 10-12:
PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
EN
RD PORTE
RD LATE
Data Bus
D
WR LATE
or PORTE
CK
Q
Port 0
Data
1
I/O pin(1)
Data Latch
D
WR TRISE
Q
CK
TRIS Latch
TTL
Input
Buffer
RD TRISE
Bus Enable
System Bus Data/TRIS Out
Control
Drive Bus
Instruction Register
Instruction Read
Note 1: I/O pins have protection diodes to VDD and VSS.
2003-2013 Microchip Technology Inc.
DS39609C-page 115
PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-9:
PORTE FUNCTIONS
Name
Bit#
Buffer Type
RE0/RD/AD8
bit 0
ST/TTL(1)
Input/output port pin, read control for Parallel Slave Port or
address/data bit 8
For RD (PSP Control mode):
1 = Not a read operation
0 = Read operation, reads PORTD register (if chip selected)
RE1/WR/AD9
bit 1
ST/TTL(1)
Input/output port pin, write control for Parallel Slave Port or
address/data bit 9
For WR (PSP Control mode):
1 = Not a write operation
0 = Write operation, writes PORTD register (if chip selected)
RE2/CS/AD10
bit 2
ST/TTL(1)
Input/output port pin, chip select control for Parallel Slave Port or
address/data bit 10
For CS (PSP Control mode):
1 = Device is not selected
0 = Device is selected
RE3/AD11
bit 3
ST/TTL(1)
Input/output port pin or address/data bit 11.
RE4/AD12
bit 4
ST/TTL(1)
Input/output port pin or address/data bit 12.
bit 5
(1)
ST/TTL
Input/output port pin or address/data bit 13.
bit 6
ST/TTL(1)
Input/output port pin or address/data bit 14.
bit 7
ST/TTL(1)
Input/output port pin, Capture2 input/Compare2 output/PWM output
(PIC18F8X20 devices in Microcontroller mode only) or
address/data bit 15.
RE5/AD13
RE6/AD14
RE7/CCP2/AD15
Function
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O or CCP mode and TTL buffers when in System Bus or PSP
Control mode.
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on
POR, BOR
Value on
all other
Resets
PORTE Data Direction Control Register
1111 1111
1111 1111
PORTE
Read PORTE pin/Write PORTE Data Latch
xxxx xxxx
uuuu uuuu
LATE
Read PORTE Data Latch/Write PORTE Data Latch
xxxx xxxx
uuuu uuuu
MEMCON
EBDIS
—
WAIT1
WAIT0
—
—
WM1
WM0
0-00 --00
0000 --00
PSPCON
IBF
OBF
IBOV
PSPMODE
—
—
—
—
0000 ----
0000 ----
Name
TRISE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTE.
DS39609C-page 116
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
10.6
EXAMPLE 10-6:
PORTF, LATF and TRISF Registers
PORTF is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISF. Setting a
TRISF bit (= 1) will make the corresponding PORTF pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISF bit (= 0) will
make the corresponding PORTF pin an output (i.e., put
the contents of the output latch on the selected pin).
Read-modify-write operations on the LATF register,
read and write the latched output value for PORTF.
PORTF is multiplexed with several analog peripheral
functions, including the A/D converter inputs and
comparator inputs, outputs and voltage reference.
CLRF
PORTF
CLRF
LATF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
0x07
CMCON
0x0F
ADCON1
0xCF
MOVWF
TRISF
Note 1: On a Power-on Reset, the RF6:RF0 pins
are configured as inputs and read as ‘0’.
INITIALIZING PORTF
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTF by
clearing output
data latches
Alternate method
to clear output
data latches
Turn off comparators
Set PORTF as digital I/O
Value used to
initialize data
direction
Set RF3:RF0 as inputs
RF5:RF4 as outputs
RF7:RF6 as inputs
2: To configure PORTF as digital I/O, turn off
comparators and set ADCON1 value.
FIGURE 10-13:
PORTF RF1/AN6/C2OUT, RF2/AN7/C1OUT PINS BLOCK DIAGRAM
Port/Comparator Select
Comparator Data Out
VDD
0
P
RD LATF
Data Bus
WR LATF
or
WR PORTF
D
CK
Q
I/O pin
Q
Data Latch
D
WR TRISF
1
CK
N
Q
VSS
Q
TRIS Latch
Analog
Input
Mode
RD TRISF
Schmitt
Trigger
Q
D
EN
RD PORTF
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
2003-2013 Microchip Technology Inc.
DS39609C-page 117
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-14:
RF6:RF3 AND RF0 PINS
BLOCK DIAGRAM
D
WR LATF
or
WR PORTF
D
WR LATF or
WR PORTF
CK
Q
VDD
CK
Data
Bus
Q
P
D
VSS
Analog
Input
Mode
Q
TRIS Latch
Q
Schmitt
Trigger
Input
Buffer
I/O pin
WR TRISF
CK
I/O pin
D
N
Q
Q
Data Latch
Data Latch
WR TRISF
RF7 PIN BLOCK
DIAGRAM
RD LATF
RD LATF
Data
Bus
FIGURE 10-15:
CK
TRIS Latch
TTL
Input
Buffer
RD TRISF
RD TRISF
ST
Input
Buffer
Q
Q
D
D
ENEN
EN
RD PORTF
RD PORTF
SS Input
To A/D Converter or Comparator Input
Note
1:
I/O pins have diode protection to VDD and VSS.
DS39609C-page 118
Note:
I/O pins have diode protection to VDD and VSS.
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-11: PORTF FUNCTIONS
Name
Bit#
Buffer Type
Function
RF0/AN5
bit 0
ST
Input/output port pin or analog input.
RF1/AN6/C2OUT
bit 1
ST
Input/output port pin, analog input or comparator 2 output.
RF2/AN7/C1OUT
bit 2
ST
Input/output port pin, analog input or comparator 1 output.
RF3/AN8
bit 3
ST
Input/output port pin or analog input/comparator input.
RF4/AN9
bit 4
ST
Input/output port pin or analog input/comparator input.
RF5/AN10/CVREF
bit 5
ST
Input/output port pin, analog input/comparator input or
comparator reference output.
RF6/AN11
bit 6
ST
Input/output port pin or analog input/comparator input.
RF7/SS
bit 7
ST/TTL
Input/output port pin or slave select pin for synchronous serial port.
Legend: ST = Schmitt Trigger input, TTL = TTL input
TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
TRISF
PORTF Data Direction Control Register
1111 1111
1111 1111
PORTF
Read PORTF pin/Write PORTF Data Latch
xxxx xxxx
uuuu uuuu
LATF
Read PORTF Data Latch/Write PORTF Data Latch
ADCON1
CMCON
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
C2OUT C1OUT C2INV
C1INV
CVRCON CVREN CVROE CVRR CVRSS
0000 0000
uuuu uuuu
--00 0000
--00 0000
CIS
CM2
CM1
CM0
0000 0000
0000 0000
CVR3
CVR2
CVR1
CVR0
0000 0000
0000 0000
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTF.
2003-2013 Microchip Technology Inc.
DS39609C-page 119
PIC18F6520/8520/6620/8620/6720/8720
10.7
PORTG, TRISG and LATG
Registers
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings.
PORTG is a 5-bit wide, bidirectional port. The corresponding data direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
Note:
The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
EXAMPLE 10-7:
The Data Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register, read and write the latched output value for
PORTG.
PORTG is multiplexed with both CCP and USART
functions (Table 10-13). PORTG pins have Schmitt
Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
FIGURE 10-16:
On a Power-on Reset, these pins are
configured as digital inputs.
CLRF
PORTG
CLRF
LATG
MOVLW
0x04
MOVWF
TRISG
INITIALIZING PORTG
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTG by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RG1:RG0 as outputs
RG2 as input
RG4:RG3 as inputs
PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
PORTG/Peripheral Out Select
Peripheral Data Out
VDD
0
P
1
RD LATG
Data Bus
WR LATG or
WR PORTG
D
Q
CK
Q
I/O pin(1)
Data Latch
D
WR TRISG
CK
N
Q
Q
TRIS Latch
VSS
TRIS
Override
Logic
RD TRISG
Schmitt
Trigger
Peripheral Output
Enable(2)
Q
D
EN
RD PORTG
Peripheral Data In
Note 1:
I/O pins have diode protection to VDD and VSS.
2: Peripheral Output Enable is only active if Peripheral Select is active.
DS39609C-page 120
TRIS OVERRIDE
Pin
Override
Peripheral
RG0
Yes
CCP3 I/O
RG1
Yes
USART1 Async
Xmit, Sync Clock
RG2
Yes
USART1 Async
Rcv, Sync Data
Out
RG3
Yes
CCP4 I/O
RG4
Yes
CCP5 I/O
2003-2013 Microchip Technology Inc.
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TABLE 10-13: PORTG FUNCTIONS
Name
Bit#
Buffer Type
Function
RG0/CCP3
bit 0
ST
Input/output port pin or Capture3 input/Compare3 output/PWM3 output.
RG1/TX2/CK2
bit 1
ST
Input/output port pin, addressable USART2 asynchronous transmit or
addressable USART2 synchronous clock.
RG2/RX2/DT2
bit 2
ST
Input/output port pin, addressable USART2 asynchronous receive or
addressable USART2 synchronous data.
RG3/CCP4
bit 3
ST
Input/output port pin or Capture4 input/Compare4 output/PWM4 output.
RG4/CCP5
bit 4
ST
Input/output port pin or Capture5 input/Compare5 output/PWM5 output.
Legend: ST = Schmitt Trigger input
TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Name
Bit 7
Bit 6
Bit 5
PORTG
—
—
—
LATG
—
—
—
TRISG
—
—
—
Value on
POR, BOR
Value on
all other
Resets
Read PORTF pin/Write PORTF Data Latch
---x xxxx
---u uuuu
LATG Data Output Register
---x xxxx
---u uuuu
Data Direction Control Register for PORTG
---1 1111
---1 1111
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Legend: x = unknown, u = unchanged
2003-2013 Microchip Technology Inc.
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PIC18F6520/8520/6620/8620/6720/8720
10.8
Note:
PORTH, LATH and TRISH
Registers
PORTH is available only on PIC18F8X20
devices.
FIGURE 10-17:
RD LATH
PORTH is an 8-bit wide, bidirectional I/O port. The corresponding data direction register is TRISH. Setting a
TRISH bit (= 1) will make the corresponding PORTH
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISH bit (= 0)
will make the corresponding PORTH pin an output (i.e.,
put the contents of the output latch on the selected pin).
Data
Bus
Read-modify-write operations on the LATH register,
read and write the latched output value for PORTH.
WR TRISH
Pins RH7:RH4 are multiplexed with analog inputs
AN15:AN12. Pins RH3:RH0 are multiplexed with the
system bus as the external memory interface; they are
the high-order address bits, A19:A16. By default, pins
RH7:RH4 are enabled as A/D inputs and pins
RH3:RH0 are enabled as the system address bus.
Register ADCON1 configures RH7:RH4 as I/O or A/D
inputs. Register MEMCON configures RH3:RH0 as I/O
or system bus pins.
Note 1: On Power-on Reset, PORTH pins
RH7:RH4 default to A/D inputs and read
as ‘0’.
2: On Power-on Reset, PORTH pins
RH3:RH0 default to system bus signals.
EXAMPLE 10-8:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
PORTH
LATH
0Fh
ADCON1
0CFh
TRISH
INITIALIZING PORTH
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTH by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RH3:RH0 as inputs
RH5:RH4 as outputs
RH7:RH6 as inputs
RH3:RH0 PINS BLOCK
DIAGRAM IN I/O MODE
WR LATH
or
PORTH
D
Q
I/O pin(1)
CK
Data Latch
D
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
RD TRISH
Q
D
ENEN
RD PORTH
Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 10-18:
RH7:RH4 PINS BLOCK
DIAGRAM IN I/O MODE
RD LATH
Data
Bus
WR LATH
or
PORTH
D
I/O pin(1)
CK
Data Latch
D
WR TRISH
Q
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
RD TRISH
Q
D
EN
EN
RD PORTH
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
DS39609C-page 122
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-19:
RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
EN
RD PORTH
RD LATD
Data Bus
WR LATH
or
PORTH
D
Q
Port
I/O pin(1)
0
Data 1
CK
Data Latch
D
WR TRISH
Q
CK
TRIS Latch
TTL
Input
Buffer
RD TRISH
External Enable
System Bus
Control
Address Out
Drive System
To Instruction Register
Instruction Read
Note 1: I/O pins have diode protection to VDD and VSS.
2003-2013 Microchip Technology Inc.
DS39609C-page 123
PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-15: PORTH FUNCTIONS
Name
Bit#
Buffer Type
bit 0
ST/TTL(1)
Input/output port pin or address bit 16 for external memory interface.
bit 1
ST/TTL(1)
Input/output port pin or address bit 17 for external memory interface.
RH2/A18
bit 2
ST/TTL
(1)
Input/output port pin or address bit 18 for external memory interface.
RH3/A19
bit 3
ST/TTL(1)
Input/output port pin or address bit 19 for external memory interface.
RH4/AN12
bit 4
ST
Input/output port pin or analog input channel 12.
RH5/AN13
bit 5
ST
Input/output port pin or analog input channel 13.
RH6/AN14
bit 6
ST
Input/output port pin or analog input channel 14.
RH7/AN15
bit 7
ST
Input/output port pin or analog input channel 15.
RH0/A16
RH1/A17
Function
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel
Slave Port mode.
TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Value on
POR, BOR
Value on
all other
Resets
PORTH Data Direction Control Register
1111 1111
1111 1111
PORTH
Read PORTH pin/Write PORTH Data Latch
xxxx xxxx
uuuu uuuu
LATH
Read PORTH Data Latch/Write PORTH Data Latch
xxxx xxxx
uuuu uuuu
Name
TRISH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000
--00 0000
MEMCON
EBDIS
—
WAIT1
0-00 --00
WAIT0
—
—
WM1
WM0
0-00 --00
Legend: x = unknown, u = unchanged, – = unimplemented. Shaded cells are not used by PORTH.
DS39609C-page 124
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
10.9
Note:
PORTJ, TRISJ and LATJ
Registers
PORTJ is available only on PIC18F8X20
devices.
FIGURE 10-20:
RD LATJ
PORTJ is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISJ. Setting a
TRISJ bit (= 1) will make the corresponding PORTJ pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISJ bit (= 0) will
make the corresponding PORTJ pin an output (i.e., put
the contents of the output latch on the selected pin).
Data
Bus
The Data Latch register (LATJ) is also memory
mapped. Read-modify-write operations on the LATJ
register, read and write the latched output value for
PORTJ.
WR TRISJ
PORTJ is multiplexed with the system bus as the external memory interface; I/O port functions are only available when the system bus is disabled. When operating
as the external memory interface, PORTJ provides the
control signal to external memory devices. The RJ5 pin
is not multiplexed with any system bus functions.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTJ pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit
settings.
Note:
PORTJ BLOCK DIAGRAM
IN I/O MODE
WR LATJ
or
PORTJ
D
Q
I/O pin(1)
CK
Data Latch
D
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
RD TRISJ
Q
D
ENEN
RD PORTJ
Note 1: I/O pins have diode protection to VDD and VSS.
On a Power-on Reset, these pins are
configured as digital inputs.
The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
EXAMPLE 10-9:
CLRF
PORTJ
CLRF
LATJ
MOVLW
0xCF
MOVWF
TRISJ
INITIALIZING PORTJ
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTG by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RJ3:RJ0 as inputs
RJ5:RJ4 as output
RJ7:RJ6 as inputs
2003-2013 Microchip Technology Inc.
DS39609C-page 125
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-21:
RJ4:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
ENEN
RD PORTJ
RD LATJ
Data Bus
D
Data
WR LATJ
or
PORTJ
I/O pin(1)
Port 0
Q
1
CK
Data Latch
D
WR TRISJ
Q
CK
TRIS Latch
RD TRISJ
Control Out
System Bus
Control
External Enable
Drive System
Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 10-22:
RJ7:RJ6 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
ENEN
RD PORTJ
RD LATJ
Data Bus
WR LATJ
or
PORTJ
D
Port
I/O pin(1)
0
Data 1
CK
Data Latch
D
WR TRISJ
Q
Q
CK
TRIS Latch
RD TRISJ
UB/LB Out
System Bus
Control
Note 1:
DS39609C-page 126
WM = 01
Drive System
I/O pins have diode protection to VDD and VSS.
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 10-17: PORTJ FUNCTIONS
Name
Bit#
Buffer Type
Function
RJ0/ALE
bit 0
ST
Input/output port pin or address latch enable control for external memory
interface.
RJ1/OE
bit 1
ST
Input/output port pin or output enable control for external memory interface.
RJ2/WRL
bit 2
ST
Input/output port pin or write low byte control for external memory interface.
RJ3/WRH
bit 3
ST
Input/output port pin or write high byte control for external memory interface.
RJ4/BA0
bit 4
ST
Input/output port pin or byte address 0 control for external memory interface.
RJ5/CE
bit 5
ST
Input/output port pin or chip enable control for external memory interface.
RJ6/LB
bit 6
ST
Input/output port pin or lower byte select control for external memory
interface.
RJ7/UB
bit 7
ST
Input/output port pin or upper byte select control for external memory
interface.
Legend: ST = Schmitt Trigger input
TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
PORTJ
Read PORTJ pin/Write PORTJ Data Latch
xxxx xxxx
uuuu uuuu
LATJ
LATJ Data Output Register
xxxx xxxx
uuuu uuuu
TRISJ
Data Direction Control Register for PORTJ
1111 1111
1111 1111
Legend: x = unknown, u = unchanged
2003-2013 Microchip Technology Inc.
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10.10 Parallel Slave Port
PORTD also operates as an 8-bit wide Parallel Slave
Port, or microprocessor port, when control bit
PSPMODE (PSPCON) is set. It is asynchronously
readable and writable by the external world through the
RD control input pin, RE0/RD/AD8 and the WR control
input pin, RE1/WR/AD9.
Note:
For PIC18F8X20 devices, the Parallel
Slave Port is available only in
Microcontroller mode.
The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit PSPMODE enables port pin RE0/RD/AD8 to be the
RD input, RE1/WR/AD9 to be the WR input and RE2/
CS/AD10 to be the CS (Chip Select) input. For this
functionality, the corresponding data direction bits of
the TRISE register (TRISE) must be configured
as inputs (set). The A/D port configuration bits,
PCFG2:PCFG0 (ADCON1), must be set which
will configure pins RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The PORTE I/O pins become control inputs for the
microprocessor
port
when
bit
PSPMODE
(PSPCON) is set. In this mode, the user must make
sure that the TRISE bits are set (pins are configured as digital inputs) and the ADCON1 is configured
for digital I/O. In this mode, the input buffers are TTL.
FIGURE 10-23:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Data Bus
D
WR LATD
or
PORTD
Q
RDx
pin
CK
TTL
Data Latch
Q
RD PORTD
D
ENEN
TRIS Latch
RD LATD
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1)
Read
TTL
RD
Chip Select
TTL
CS
Write
TTL
WR
Note: I/O pin has protection diodes to VDD and VSS.
DS39609C-page 128
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 10-1:
PSPCON REGISTER
R-0
R-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
IBF
OBF
IBOV
PSPMODE
—
—
—
—
bit 7
bit 0
bit 7
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5
IBOV: Input Buffer Overflow Detect bit
1 = A write occurred when a previously input word has not been read
(must be cleared in software)
0 = No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel Slave Port mode
0 = General Purpose I/O mode
bit 3-0
Unimplemented: Read as ‘0’
Legend:
FIGURE 10-24:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
2003-2013 Microchip Technology Inc.
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PIC18F6520/8520/6620/8620/6720/8720
FIGURE 10-25:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
PORTD
Port Data Latch when written; Port pins when read
xxxx xxxx
uuuu uuuu
LATD
LATD Data Output bits
xxxx xxxx
uuuu uuuu
TRISD
PORTD Data Direction bits
1111 1111
1111 1111
PORTE
—
—
—
—
—
Read PORTE pin/
Write PORTE Data Latch
0000 0000
0000 0000
LATE
—
—
—
—
—
LATE Data Output bits
xxxx xxxx
uuuu uuuu
PORTE Data Direction bits
TRISE
—
—
—
—
—
1111 1111
1111 1111
PSPCON
IBF
OBF
IBOV
PSPMODE
—
—
—
—
0000 ----
0000 ----
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IF
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
0000 0000
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0111 1111
0111 1111
Legend:
Note 1:
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Enabled only in Microcontroller mode for PIC18F8X20 devices.
DS39609C-page 130
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PIC18F6520/8520/6620/8620/6720/8720
11.0
TIMER0 MODULE
The Timer0 module has the following features:
• Software selectable as an 8-bit or
16-bit timer/counter
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt-on-overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
• Edge select for external clock
REGISTER 11-1:
Figure 11-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
The T0CON register (Register 11-1) is a readable and
writable register that controls all the aspects of Timer0,
including the prescale selection.
T0CON: TIMER0 CONTROL REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
bit 7
bit 0
bit 7
TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6
T08BIT: Timer0 8-bit/16-bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0
T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 prescale value
110 = 1:128 prescale value
101 = 1:64 prescale value
100 = 1:32 prescale value
011 = 1:16 prescale value
010 = 1:8 prescale value
001 = 1:4 prescale value
000 = 1:2 prescale value
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 131
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 11-1:
TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus
FOSC/4
0
8
0
1
RA4/T0CKI pin
Programmable
Prescaler
1
Sync with
Internal
Clocks
TMR0
(2 TCY delay)
T0SE
3
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
T0PS2, T0PS1, T0PS0
T0CS
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 11-2:
FOSC/4
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
0
0
1
RA4/T0CKI
pin
Programmable
Prescaler
1
Sync with
Internal
Clocks
TMR0L
TMR0
High Byte
8
(2 TCY delay)
T0SE
3
Set Interrupt
Flag bit TMR0IF
on Overflow
Read TMR0L
PSA
T0PS2, T0PS1, T0PS0
Write TMR0L
T0CS
8
8
TMR0H
8
Data Bus
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39609C-page 132
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
11.1
11.2.1
Timer0 Operation
Timer0 can operate as a timer or as a counter.
The prescaler assignment is fully under software
control, (i.e., it can be changed “on-the-fly” during
program execution).
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
11.3
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
11.4
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not readable or writable.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
A write to the high byte of Timer0 must also take place
through the TMR0H Buffer register. Timer0 high byte is
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16 bits of Timer0 to be
updated at once.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, x, ..., etc.) will clear the prescaler
count.
Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the
prescaler count, but will not change the
prescaler assignment.
TABLE 11-1:
Name
16-Bit Mode Timer Reads
and Writes
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 11-2). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without
having to verify that the read of the high and low byte
were valid, due to a rollover between successive reads
of the high and low byte.
Prescaler
Note:
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF bit. The interrupt can be masked by clearing
the TMR0IE bit. The TMR0IF bit must be cleared in
software by the Timer0 module Interrupt Service
Routine before re-enabling this interrupt. The TMR0
interrupt cannot awaken the processor from Sleep,
since the timer is shut-off during Sleep.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment, either on every
rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge
Select bit (T0SE). Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input are
discussed below.
11.2
SWITCHING PRESCALER
ASSIGNMENT
REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TMR0L
Timer0 Module Low Byte Register
TMR0H
Timer0 Module High Byte Register
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF INT0IF
T0CON
TMR0ON
PSA
T0PS2
TRISA
—
T08BIT
T0CS
Bit 0
Value on
POR, BOR
Value on
all other
Resets
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
T0SE
T0PS1
RBIF
0000 0000 0000 0000
T0PS0 1111 1111 1111 1111
PORTA Data Direction Register
-111 1111 -111 1111
Legend: x = unknown, u = unchanged, – = unimplemented locations, read as ‘0’.
Shaded cells are not used by Timer0.
2003-2013 Microchip Technology Inc.
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NOTES:
DS39609C-page 134
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12.0
TIMER1 MODULE
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter
(two 8-bit registers: TMR1H and TMR1L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module special event trigger
Register 12-1 details the Timer1 Control register. This
register controls the operating mode of the Timer1
module and contains the Timer1 Oscillator Enable bit
(T1OSCEN). Timer1 can be enabled or disabled by
setting or clearing control bit, TMR1ON (T1CON).
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications, with only a minimal
addition of external components and code overhead.
Figure 12-1 is a simplified block diagram of the Timer1
module.
REGISTER 12-1:
T1CON: TIMER1 CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RD16
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 6
Unimplemented: Read as ‘0’
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
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12.1
Timer1 Operation
When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins
become inputs. That is, the TRISC value is
ignored and the pins are read as ‘0’.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON).
Timer1 also has an internal “Reset input”. This
Reset can be generated by the CCP module
(see Section 16.0 “Capture/Compare/PWM (CCP)
Modules”).
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag Bit
TMR1
TMR1H
1
TMR1ON
On/Off
T1OSC
T1OSO/T13CKI
T1OSCEN
Enable
Oscillator(1)
T1OSI
Synchronized
Clock Input
0
CLR
TMR1L
T1SYNC
1
FOSC/4
Internal
Clock
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
T1CKPS1:T1CKPS0
Sleep Input
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus
8
TMR1H
8
8
Write TMR1L
CCP Special Event Trigger
Read TMR1L
TMR1IF
Overflow
Interrupt
Flag bit
TMR1
8
Timer 1
High Byte
CLR
TMR1L
1
TMR1ON
On/Off
T1OSC
T1OSO/T13CKI
T1OSI
Synchronized
Clock Input
0
T1SYNC
1
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
Sleep Input
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
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12.2
12.2.1
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit, T1OSCEN (T1CON). The oscillator is a low-power oscillator, rated up to 200 kHz. It
will continue to run during Sleep. It is primarily intended
for a 32 kHz crystal. The circuit for a typical LP oscillator is shown in Figure 12-3. Table 12-1 shows the
capacitor selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator
FIGURE 12-3:
EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
C1
33 pF
PIC18FXX20
T1OSI
XTAL
32.768 kHz
LOW-POWER TIMER1 OPTION
(PIC18FX520 DEVICES ONLY)
The Timer1 oscillator for PIC18LFX520 devices incorporates a low-power feature, which allows the oscillator
to automatically reduce its power consumption when
the microcontroller is in Sleep mode.
As high noise environments may cause excessive
oscillator instability in Sleep mode, this option is best
suited for low noise applications where power
conservation is an important design consideration. Due
to the low-power nature of the oscillator, it may also be
sensitive to rapidly changing signals in close proximity.
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the oscillator (such as the CCP1 pin in output compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
T1OSO
C2
33 pF
Note:
FIGURE 12-4:
See the Notes with Table 12-1 for additional
information about capacitor selection.
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
VDD
TABLE 12-1:
CAPACITOR SELECTION
FOR THE ALTERNATE
OSCILLATOR
OSC1
Osc Type
Freq
C1
C2
OSC2
LP
32 kHz
TBD(1)
TBD(1)
VSS
Crystal to be Tested:
32.768 kHz Epson C-001R32.768K-A
RC0
20 PPM
RC1
Note 1: Microchip suggests 33 pF as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
RC2
Note:
Note:
Not drawn to scale.
PIC18FX620/X720 devices have the
standard Timer1 oscillator permanently
selected. PIC18LFX620/X720 devices
have the low-power Timer1 oscillator
permanently selected.
4: Capacitor values are for design guidance
only.
2003-2013 Microchip Technology Inc.
DS39609C-page 137
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12.3
Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR1IF
(PIR1). This interrupt can be enabled/disabled by
setting/clearing TMR1 Interrupt Enable bit, TMR1IE
(PIE1).
12.4
Resetting Timer1 Using a CCP
Trigger Output
If the CCP module is configured in Compare mode
to
generate
a
“special
event
trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1).
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L
register pair effectively becomes the period register for
Timer1.
12.5
Timer1 16-Bit Read/Write Mode
12.6
Using Timer1 as a
Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.2 “Timer1 Oscillator”)
gives users the option to include RTC functionality to
their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base
and several lines of application code to calculate the
time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow, triggers the interrupt and calls
the routine, which increments the seconds counter by
one; additional counters for minutes and hours are
incremented as the previous counter overflow.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to
preload it; the simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1 = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, is
valid, due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place
through the Timer1 High Byte Buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.
DS39609C-page 138
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EXAMPLE 12-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
MOVLW
MOVWF
CLRF
CLRF
MOVLW
MOVWF
BSF
RETURN
0x80
TMR1H
TMR1L
b’00001111’
T1OSC
secs
mins
.12
hours
PIE1, TMR1IE
BSF
BCF
INCF
MOVLW
CPFSGT
RETURN
CLRF
INCF
MOVLW
CPFSGT
RETURN
CLRF
INCF
MOVLW
CPFSGT
RETURN
MOVLW
MOVWF
RETURN
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
secs
; Preload TMR1 register pair
; for 1 second overflow
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
; Enable Timer1 interrupt
RTCisr
TABLE 12-2:
Name
INTCON
Bit 7
secs
mins, F
.59
mins
mins
hours, F
.23
hours
;
;
;
;
Preload for 1 sec overflow
Clear interrupt flag
Increment seconds
60 seconds elapsed?
;
;
;
;
No, done
Clear seconds
Increment minutes
60 minutes elapsed?
;
;
;
;
No, done
clear minutes
Increment hours
24 hours elapsed?
; No, done
; Reset hours to 1
.01
hours
; Done
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0111 1111 0111 1111
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
T1CON
Legend:
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
2003-2013 Microchip Technology Inc.
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NOTES:
DS39609C-page 140
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
13.0
TIMER2 MODULE
13.1
Timer2 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable and is cleared on any device
Reset. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits,
T2CKPS1:T2CKPS0 (T2CON). The match output of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit, TMR2IF (PIR1)).
The Timer2 module timer has the following features:
•
•
•
•
•
•
•
8-bit timer (TMR2 register)
8-bit period register (PR2)
Readable and writable (both registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Interrupt on TMR2 match of PR2
SSP module optional use of TMR2 output to
generate clock shift
Timer2 has a control register shown in Register 13-1.
Timer2 can be shut-off by clearing control bit, TMR2ON
(T2CON), to minimize power consumption.
Figure 13-1 is a simplified block diagram of the Timer2
module. Register 13-1 shows the Timer2 Control register. The prescaler and postscaler selection of Timer2
are controlled by this register.
REGISTER 13-1:
Timer2 Operation
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
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13.2
Timer2 Interrupt
13.3
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
FIGURE 13-1:
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
synchronous serial port module, which optionally uses
it to generate the shift clock.
TIMER2 BLOCK DIAGRAM
Sets Flag
bit TMR2IF
TMR2
Output(1)
Prescaler
1:1, 1:4, 1:16
FOSC/4
TMR2
2
Reset
Comparator
EQ
Postscaler
1:1 to 1:16
T2CKPS1:T2CKPS0
4
PR2
T2OUTPS3:T2OUTPS0
Note 1:
TABLE 13-1:
Name
TMR2 register output can be software selected by the SSP module as a baud clock.
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7
Bit 6
INTCON GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Value on
all other
Resets
Bit 0
Value on
POR, BOR
RBIF
0000 0000 0000 0000
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP 0111 1111 0111 1111
TMR2
T2CON
PR2
Legend:
Timer2 Module Register
—
0000 0000 0000 0000
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register
1111 1111 1111 1111
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
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14.0
TIMER3 MODULE
Figure 14-1 is a simplified block diagram of the Timer3
module.
The Timer3 module timer/counter has the following
features:
• 16-bit timer/counter
(two 8-bit registers; TMR3H and TMR3L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module trigger
REGISTER 14-1:
Register 14-1 shows the Timer3 Control register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
Register 12-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 Oscillator
Enable bit (T1OSCEN), which can be a clock source for
Timer3.
T3CON: TIMER3 CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
bit 7
bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
bit 6, 3
T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
11 = Timer3 and Timer4 are the clock sources for CCP1 through CCP5
10 = Timer3 and Timer4 are the clock sources for CCP3 through CCP5;
Timer1 and Timer2 are the clock sources for CCP1 and CCP2
01 = Timer3 and Timer4 are the clock sources for CCP2 through CCP5;
Timer1 and Timer2 are the clock sources for CCP1
00 = Timer1 and Timer2 are the clock sources for CCP1 through CCP5
bit 5-4
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 2
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the
first falling edge)
0 = Internal clock (FOSC/4)
bit 0
TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 143
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14.1
Timer3 Operation
When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins
become inputs. That is, the TRISC value is
ignored and the pins are read as ‘0’.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON).
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see Section 14.0
“Timer3 Module”).
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
CCP Special Trigger
T3CCPx
TMR3IF
Overflow
Interrupt
Flag bit
TMR3H
Synchronized
Clock Input
0
CLR
TMR3L
1
TMR3ON
On/Off
T1OSC
T1OSO/
T13CKI
T3SYNC
(3)
1
Prescaler
1, 2, 4, 8
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
T1OSI
Synchronize
det
0
2
Sleep Input
TMR3CS
T3CKPS1:T3CKPS0
Note 1:
When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus
8
TMR3H
8
8
Write TMR3L
Read TMR3L
Set TMR3IF Flag bit
on Overflow
8
CCP Special Trigger
T3CCPx
0
TMR3
Timer3
High Byte
TMR3L
CLR
Synchronized
Clock Input
1
To Timer1 Clock Input
T1OSC
T1OSO/
T13CKI
T3SYNC
1
T1OSCEN
Enable
Oscillator(1)
T1OSI
Note 1:
TMR3ON
On/Off
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
T3CKPS1:T3CKPS0
TMR3CS
Sleep Input
When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39609C-page 144
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14.2
Timer1 Oscillator
14.4
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON) bit. The oscillator is a lowpower oscillator rated up to 200 kHz. See Section 12.0
“Timer1 Module” for further details.
14.3
If the CCP module is configured in Compare mode
to
generate
a
“special
event
trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer3.
Note:
Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR3IF
(PIR2). This interrupt can be enabled/disabled by
setting/clearing TMR3 Interrupt Enable bit, TMR3IE
(PIE2).
TABLE 14-1:
Name
INTCON
Bit 7
Resetting Timer3 Using a CCP
Trigger Output
The special event triggers from the CCP
module will not set interrupt flag bit,
TMR3IF (PIR1).
Timer3 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this Reset operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from CCP1, the write will take precedence. In this mode
of operation, the CCPR1H:CCPR1L register pair
effectively becomes the period register for Timer3.
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
0000 0000
PIR2
—
—
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
---0 0000
---0 0000
PIE2
—
—
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
---0 0000
---0 0000
IPR2
—
—
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
---1 1111
---1 1111
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
xxxx xxxx
uuuu uuuu
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx
uuuu uuuu
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000
u-uu uuuu
T3CKPS1 T3CKPS0
uuuu uuuu
T1CON
T3CON
Legend:
RD16
—
RD16
T3CCP2
T3CCP1
T3SYNC TMR3CS TMR3ON 0000 0000
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
2003-2013 Microchip Technology Inc.
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NOTES:
DS39609C-page 146
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
15.0
TIMER4 MODULE
15.1
The Timer4 module timer has the following features:
•
•
•
•
•
•
8-bit timer (TMR4 register)
8-bit period register (PR4)
Readable and writable (both registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Interrupt on TMR4 match of PR4
Timer4 has a control register shown in Register 15-1.
Timer4 can be shut-off by clearing control bit, TMR4ON
(T4CON), to minimize power consumption. The
prescaler and postscaler selection of Timer4 are also
controlled by this register. Figure 15-1 is a simplified
block diagram of the Timer4 module.
Timer4 Operation
Timer4 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR4 register is
readable and writable and is cleared on any device
Reset. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits
T4CKPS1:T4CKPS0 (T4CON). The match output of TMR4 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR4 interrupt, latched in flag bit, TMR4IF (PIR3).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR4 register
• a write to the T4CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR4 is not cleared when T4CON is written.
REGISTER 15-1:
T4CON: TIMER4 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1
R/W-0
T4CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T4OUTPS3:T4OUTPS0: Timer4 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR4ON: Timer4 On bit
1 = Timer4 is on
0 = Timer4 is off
bit 1-0
T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 147
PIC18F6520/8520/6620/8620/6720/8720
15.2
Timer4 Interrupt
15.3
The Timer4 module has an 8-bit period register, PR4,
which is both readable and writable. Timer4 increments
from 00h until it matches PR4 and then resets to 00h on
the next increment cycle. The PR4 register is initialized
to FFh upon Reset.
FIGURE 15-1:
Output of TMR4
The output of TMR4 (before the postscaler) is used
only as a PWM time base for the CCP modules. It is not
used as a baud rate clock for the MSSP, as is the
Timer2 output.
TIMER4 BLOCK DIAGRAM
Sets Flag
bit TMR4IF
TMR4
Output(1)
Prescaler
1:1, 1:4, 1:16
FOSC/4
TMR4
2
Reset
Comparator
EQ
Postscaler
1:1 to 1:16
T4CKPS1:T4CKPS0
4
PR4
T4OUTPS3:T4OUTPS0
TABLE 15-1:
Name
REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER
Bit 7
Bit 6
INTCON GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
TMR0IE
RC2IP
Bit 1
INT0IE
RBIE
TMR0IF
INT0IF
TX2IP
TMR4IP
CCP5IP
CCP4IP
Value on
all other
Resets
Bit 0
Value on
POR, BOR
RBIF
0000 0000 0000 0000
IPR3
—
—
PIR3
—
—
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF --00 0000 --00 0000
PIE3
—
—
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE --00 0000 --00 0000
TMR4
T4CON
PR4
Legend:
Timer4 Module Register
—
CCP3IP --11 1111 --00 0000
0000 0000 0000 0000
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000
Timer4 Period Register
1111 1111 1111 1111
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module.
DS39609C-page 148
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16.0
CAPTURE/COMPARE/PWM
(CCP) MODULES
The PIC18FXX20 devices all have five CCP (Capture/
Compare/PWM) modules. Each module contains a
16-bit register, which can operate as a 16-bit Capture
register, a 16-bit Compare register or a Pulse Width
Modulation (PWM) Master/Slave Duty Cycle register.
Table 16-1 shows the timer resources of the CCP
module modes.
For the sake of clarity, CCP module operation in the
following sections is described with respect to CCP1.
The descriptions can be applied (with the exception of
the special event triggers) to any of the modules.
Note:
The operation of all CCP modules are identical, with
the exception of the special event trigger present on
CCP1 and CCP2.
REGISTER 16-1:
Throughout this section, references to
register and bit names that may be associated with a specific CCP module are
referred to generically by the use of ‘x’ or
‘y’ in place of the specific module number.
Thus, “CCPxCON” might refer to the
control register for CCP1, CCP2, CCP3,
CCP4 or CCP5.
CCPxCON REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DCxB1
DCxB0
CCPxM3
CCPxM2
R/W-0
R/W-0
CCPxM1 CCPxM0
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The
eight Most Significant bits (DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCP Module x Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, Initialize CCP pin Low; on compare match, force CCP pin High
(CCPIF bit is set)
1001 = Compare mode, Initialize CCP pin High; on compare match, force CCP pin Low
(CCPIF bit is set)
1010 = Compare mode, Generate software interrupt on compare match (CCPIF bit is set,
(CCP pin is unaffected)
1011 = Compare mode, trigger special event (CCPIF bit is set):
For CCP1 and CCP2:
Timer1 or Timer3 is reset on event.
For all other modules:
CCPx pin is unaffected and is configured as an I/O port
(same as CCPxM = 1010, above).
11xx = PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 149
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16.1
TABLE 16-1:
CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
16.1.1
CCP MODULES AND TIMER
RESOURCES
The CCP modules utilize Timers 1, 2, 3 or 4, depending
on the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare modes, while
Timer2 and Timer4 are available for modules in PWM
mode.
FIGURE 16-1:
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2 or Timer4
The assignment of a particular timer to a module is
determined by the Timer-to-CCP Enable bits in the
T3CON register (Register 14-1). Depending on the
configuration selected, up to four timers may be active
at once, with modules in the same configuration
(Capture/Compare or PWM) sharing timer resources.
The possible configurations are shown in Figure 16-1.
CCP AND TIMER INTERCONNECT CONFIGURATIONS
T3CCP = 00
TMR1
CCP MODE – TIMER
RESOURCE
TMR3
CCP1
T3CCP = 01
TMR1
TMR3
CCP1
T3CCP = 10
TMR1
TMR3
T3CCP = 11
TMR1
TMR3
CCP1
CCP1
CCP2
CCP2
CCP2
CCP2
CCP3
CCP3
CCP3
CCP3
CCP4
CCP4
CCP4
CCP4
CCP5
CCP5
CCP5
CCP5
TMR2
TMR4
Timer1 is used for all Capture
and Compare operations for
all CCP modules. Timer2 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
Timer3 and Timer4 are not
available.
DS39609C-page 150
TMR2
TMR4
Timer1 and Timer2 are used
for Capture and Compare or
PWM operations for CCP1
only (depending on selected
mode).
All other modules use either
Timer3 or Timer4. Modules
may share either timer
resource as a common time
base, if they are in Capture/
Compare or PWM modes.
TMR2
TMR4
Timer1 and Timer2 are used
for Capture and Compare or
PWM operations for CCP1
and CCP2 only (depending on
the mode selected for each
module). Both modules may
use a timer as a common time
base if they are both in
Capture/Compare or PWM
modes.
TMR2
TMR4
Timer3 is used for all Capture
and Compare operations for
all CCP modules. Timer4 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
Timer1 and Timer2 are not
available.
The other modules use either
Timer3 or Timer4. Modules
may share either timer
resource as a common time
base if they are in Capture/
Compare or PWM modes.
2003-2013 Microchip Technology Inc.
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16.2
16.2.3
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the 16-bit
value of the TMR1 or TMR3 registers when an event
occurs on pin RC2/CCP1. An event is defined as one of
the following:
•
•
•
•
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
16.2.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC bit.
Note:
16.2.2
If the RC2/CCP1 is configured as an output, a write to the port can cause a capture
condition.
TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode,
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work. The
timer to be used with each CCP module is selected in the
T3CON register (see Section 16.1.1 “CCP Modules
and Timer Resources”).
FIGURE 16-2:
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.
16.2.4
The event is selected by control bits, CCP1M3:CCP1M0
(CCP1CON). When a capture is made, the interrupt request flag bit, CCP1IF (PIR1), is set; it must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by the new captured value.
SOFTWARE INTERRUPT
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 16-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 16-1:
CLRF
MOVLW
MOVWF
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON, F ; Turn CCP module off
NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
CCP1CON
; Load CCP1CON with
; this value
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3L
Set Flag bit CCP1IF
T3CCP2
Prescaler
1, 4, 16
CCP1 pin
TMR3
Enable
CCPR1H
and
Edge Detect
T3CCP2
CCPR1L
TMR1
Enable
TMR1H
TMR1L
CCP1CON
Q’s
2003-2013 Microchip Technology Inc.
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16.3
16.3.2
Compare Mode
TIMER1/TIMER3 MODE SELECTION
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 register
pair value or the TMR3 register pair value. When a
match occurs, the CCP1 pin:
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
•
•
•
•
16.3.3
is driven High
is driven Low
toggles output (high-to-low or low-to-high)
remains unchanged
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0. At the same time, interrupt
flag bit CCP1IF (CCP2IF) is set.
16.3.1
16.3.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
CCP PIN CONFIGURATION
The special event trigger output of either CCP1 or
CCP2, resets the TMR1 or TMR3 register pair, depending on which timer resource is currently selected. This
allows the CCPR1 register to effectively be a 16-bit
programmable period register for Timer1 or Timer3.
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
Note:
SOFTWARE INTERRUPT MODE
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
The CCP2 Special Event Trigger will also start an A/D
conversion if the A/D module is enabled.
Note:
FIGURE 16-3:
The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
COMPARE MODE OPERATION BLOCK DIAGRAM
For CCP1 and CCP2 only, the Special Event Trigger will:
Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bit
and set bit GO/DONE (ADCON0),
which starts an A/D conversion (CCP2 only)
Special Event Trigger
Set Flag bit CCP1IF
CCPR1H CCPR1L
Q
RC2/CCP1 pin
TRISC
Output Enable
S
R
Output
Logic
CCP1CON
Mode Select
Comparator
Match
T3CCP2
TMR1H
DS39609C-page 152
TMR1L
0
1
TMR3H
TMR3L
2003-2013 Microchip Technology Inc.
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TABLE 16-2:
Name
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Bit 7
INTCON
Bit 6
GIE/GIEH PEIE/GIEL
RCON
IPEN
Value on
POR, BOR
Value on
all other
Resets
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
—
RI
TO
PD
POR
BOR
0--1 11qq 0--q qquu
—
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP 0111 1111 0111 1111
PIR2
—
CMIE
—
EEIE
BCLIF
LVDIF
TMR3IF
CCP2IF
-0-0 0000 ---0 0000
PIE2
—
CMIF
—
EEIF
BCLIE
LVDIE
TMR3IE
CCP2IE
-0-0 0000 ---0 0000
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
-1-1 1111 ---1 1111
PIR3
—
—
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF --00 0000 --00 0000
PIE3
—
—
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE --00 0000 --00 0000
—
—
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP --11 1111 --11 1111
IPR3
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
T1CON
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
TMR3H
Timer3 Register High Byte
xxxx xxxx uuuu uuuu
TMR3L
Timer3 Register Low Byte
xxxx xxxx uuuu uuuu
T3CON
RD16
T3CCP2
T3CKPS1 T3CKPS0
T3CCP1
T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
CCPRxL(1)
Capture/Compare/PWM Register x (LSB)
xxxx xxxx uuuu uuuu
CCPRxH(1)
Capture/Compare/PWM Register x (MSB)
xxxx xxxx uuuu uuuu
CCPxCON(1)
Legend:
Note 1:
—
—
DCxB1
DCxB0
CCPxM3
CCPxM2 CCPxM1 CCPxM0 --00 0000 --00 0000
x = unknown, u = unchanged, – = unimplemented, read as ‘0’.
Shaded cells are not used by Capture and Compare, Timer1 or Timer3.
Generic term for all of the identical registers of this name for all CCP modules, where ‘x’ identifies the individual module
(CCP1 through CCP5). Bit assignments and Reset values for all registers of the same generic name are identical.
2003-2013 Microchip Technology Inc.
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PIC18F6520/8520/6620/8620/6720/8720
16.4
16.4.1
PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
EQUATION 16-1:
PWM Period = (PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
Figure 16-4 shows a simplified block diagram of the
CCP module in PWM mode.
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 16.4.3
“Setup for PWM Operation”.
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
FIGURE 16-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note:
CCP1CON
Duty Cycle Registers
CCPR1L
CCPR1H (Slave)
16.4.2
R
Comparator
Q
RC2/CCP1
(Note 1)
TMR2
S
TRISC
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
Note
1:
8-bit timer is concatenated with 2-bit internal Q
clock or 2 bits of the prescaler to create 10-bit
time base.
The Timer2 and Timer4 postscalers (see
Section 13.0 “Timer2 Module”) are not
used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON. The following equation is
used to calculate the PWM duty cycle in time:
EQUATION 16-2:
PWM Duty Cycle = (CCPR1L:CCP1CON) •
TOSC • (TMR2 Prescale Value)
A PWM output (Figure 16-5) has a time base (period)
and a time that the output stays high (duty cycle).
The frequency of the PWM is the inverse of the period
(1/period).
CCPR1L and CCP1CON can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
FIGURE 16-5:
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
doublebuffering is essential for glitchless PWM
operation.
PWM OUTPUT
Period
When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
DS39609C-page 154
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16.4.3
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
The following steps should be taken when configuring
the CCP module for PWM operation:
EQUATION 16-3:
1.
F OSC
log ---------------
F PWM
PWM Resolution (max) = -----------------------------bits
log 2
2.
3.
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TABLE 16-3:
9.77 kHz
39.06 kHz
156.25 kHz
312.50 kHz
416.67 kHz
16
4
1
1
1
1
FFh
FFh
FFh
3Fh
1Fh
17h
14 10
12 10
10
8
7
6.58
PR2 Value
Maximum Resolution (bits)
REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4
Bit 7
INTCON
Bit 6
GIE/GIEH PEIE/GIEL
RCON
5.
2.44 kHz
Timer Prescaler (1, 4, 16)
Name
4.
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON bits.
Make the CCP1 pin an output by clearing the
TRISC bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
TABLE 16-4:
SETUP FOR PWM OPERATION
IPEN
Value on
POR, BOR
Value on
all other
Resets
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
—
RI
TO
PD
POR
BOR
0--1 11qq 0--q qquu
0000 0000 0000 0000
—
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP 0111 1111 0111 1111
PIR2
—
CMIE
—
EEIE
BCLIF
LVDIF
TMR3IF
CCP2IF
-0-0 0000 ---0 0000
PIE2
—
CMIF
—
EEIF
BCLIE
LVDIE
TMR3IE
CCP2IE
-0-0 0000 ---0 0000
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
-1-1 1111 ---1 1111
PIR3
—
—
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
--00 0000 --00 0000
PIE3
—
—
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
--00 0000 --00 0000
—
—
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
--11 1111 --11 1111
IPR3
TMR2
Timer2 Module Register
0000 0000 0000 0000
PR2
Timer2 Module Period Register
1111 1111 1111 1111
—
T2CON
T3CON
RD16
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
TMR4
Timer4 Register
0000 0000 uuuu uuuu
PR4
Timer4 Period Register
1111 1111 uuuu uuuu
—
T4CON
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 uuuu uuuu
CCPRxL(1)
Capture/Compare/PWM Register x (LSB)
CCPRxH(1)
Capture/Compare/PWM Register x (MSB)
CCPxCON(1)
Legend:
Note 1:
—
—
DCxB1
DCxB0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCPxM3
CCPxM2 CCPxM1
CCPxM0 --00 0000 --00 0000
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2, or Timer4.
Generic term for all of the identical registers of this name for all CCP modules, where ‘x’ identifies the individual module
(CCP1 through CCP5). Bit assignments and Reset values for all registers of the same generic name are identical.
2003-2013 Microchip Technology Inc.
DS39609C-page 155
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NOTES:
DS39609C-page 156
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17.0
17.1
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mode
- Slave mode (with general address call)
17.3
SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four modes
of SPI are supported. To accomplish communication,
typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RF7/SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
The I2C interface supports the following modes in
hardware:
Internal
Data Bus
Read
• Master mode
• Multi-Master mode
• Slave mode
17.2
Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual configuration bits
differ significantly, depending on whether the MSSP
module is operated in SPI or I2C mode.
Additional details are provided under the individual
sections.
Write
SSPBUF reg
RC4/SDI/SDA
SSPSR reg
Shift
Clock
RC5/SDO
bit0
RF7/SS
SS Control
Enable
Edge
Select
2
Clock Select
RC3/SCK/
SCL
SSPM3:SSPM0
SMP:CKE 4
TMR2 Output
2
2
(
Edge
Select
)
Prescaler TOSC
4, 16, 64
Data to TX/RX in SSPSR
TRIS bit
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17.3.1
REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
•
•
•
•
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
MSSP Control Register 1 (SSPCON1)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
MSSP Shift Register (SSPSR) – Not directly
accessible
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 17-1:
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE: SPI Clock Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
Note:
Polarity of clock state is set by the CKP bit (SSPCON1).
bit 5
D/A: Data/Address bit
Used in I2C mode only.
bit 4
P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled,
SSPEN is cleared.
bit 3
S: Start bit
Used in I2C mode only.
bit 2
R/W: Read/Write bit information
Used in I2C mode only.
bit 1
UA: Update Address bit
Used in I2C mode only.
bit 0
BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Legend:
DS39609C-page 158
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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REGISTER 17-2:
SSPCON1: MSSP CONTROL REGISTER1 (SPI MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow
(must be cleared in software).
0 = No overflow
Note:
bit 5
In Master mode, the overflow bit is not set, since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note:
When enabled, these pins must be properly configured as input or output.
bit 4
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note:
Bit combinations not specifically listed here are either reserved, or implemented in
I2C mode only.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
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17.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1 and SSPSTAT).
These control bits allow the following to be specified:
•
•
•
•
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data input sample phase (middle or end of data
output time)
• Clock edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a Transmit/Receive Shift Register (SSPSR) and a Buffer register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR until the received data is ready. Once the 8 bits
of data have been received, that byte is moved to the
SSPBUF register. Then, the Buffer Full detect bit, BF
(SSPSTAT) and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
EQUATION 17-1:
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the Write Collision detect bit, WCOL
(SSPCON1), will be set. User software must clear
the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed
successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
Full bit, BF (SSPSTAT), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally, the MSSP interrupt is used to
determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 17-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.
LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF
BRA
LOOP
MOVF SSPBUF, W
;Has data been received (transmit complete)?
;No
;WREG reg = contents of SSPBUF
MOVWF RXDATA
;Save in user RAM, if data is meaningful
MOVF TXDATA, W
MOVWF SSPBUF
;W reg = contents of TXDATA
;New data to transmit
DS39609C-page 160
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17.3.3
ENABLING SPI I/O
17.3.4
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON1), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC bit cleared
• SCK (Master mode) must have TRISC bit
cleared
• SCK (Slave mode) must have TRISC bit set
• SS must have TRISF bit set
TYPICAL CONNECTION
Figure 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data–Slave sends dummy data
• Master sends data–Slave sends data
• Master sends dummy data–Slave sends data
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 17-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
SDI
Shift Register
(SSPSR)
MSb
Serial Input Buffer
(SSPBUF)
LSb
2003-2013 Microchip Technology Inc.
Shift Register
(SSPSR)
MSb
SCK
PROCESSOR 1
SDO
Serial Clock
LSb
SCK
PROCESSOR 2
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17.3.5
MASTER MODE
Figure 17-3, Figure 17-5 and Figure 17-6, where the
MSB is transmitted first. In Master mode, the SPI clock
rate (bit rate) is user-programmable to be one of the
following:
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 17-2) is to
broadcast data by the software protocol.
•
•
•
•
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 17-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
The clock polarity is selected by appropriately programming the CKP bit (SSPCON1). This then, would
give waveforms for SPI communication, as shown in
FIGURE 17-3:
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
Timer2 output/2
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 7
bit 0
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
DS39609C-page 162
Next Q4 cycle
after Q2
2003-2013 Microchip Technology Inc.
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17.3.6
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
longer driven, even if in the middle of a transmitted
byte and becomes a floating output. External pull-up/
pull-down resistors may be desirable, depending on the
application.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON = 0100),
the SPI module will reset if the SS pin is set
to VDD.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
17.3.7
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1 = 04h). The pin must not be driven
low for the SS pin to function as an input. The Data
Latch must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is
driven. When the SS pin goes high, the SDO pin is no
FIGURE 17-4:
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function),
since it cannot create a bus conflict.
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 6
bit 7
bit 0
bit 0
bit 7
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
2003-2013 Microchip Technology Inc.
Next Q4 cycle
after Q2
DS39609C-page 163
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FIGURE 17-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
FIGURE 17-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDO
bit 7
SDI
(SMP = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
DS39609C-page 164
Next Q4 cycle
after Q2
2003-2013 Microchip Technology Inc.
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17.3.8
SLEEP OPERATION
17.3.10
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1:
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
17.3.9
EFFECTS OF A RESET
Name
INTCON
SPI BUS MODES
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0
1
0, 1
0
0
1, 0
1
1
1, 1
1
0
There is also an SMP bit, which controls when the data
is sampled.
A Reset disables the MSSP module and terminates the
current transfer.
TABLE 17-2:
BUS MODE COMPATIBILITY
REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
all other
Resets
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP 0111 1111 0111 1111
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0 1111 1111 uuuu uuuu
TRISC
TRISF
SSPBUF
RBIF
Value on
POR, BOR
PORTC Data Direction Register
TRISF7
TRISF6
TRISF5
0000 0000 0000 0000
1111 1111 1111 1111
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000 0000 0000
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 0000 0000
Legend:
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
2003-2013 Microchip Technology Inc.
DS39609C-page 165
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17.4
I2C Mode
17.4.1
The MSSP module in I 2C mode fully implements all
master and slave functions (including general call support) and provides interrupts on Start and Stop bits in
hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs or outputs
through the TRISC bits.
FIGURE 17-7:
MSSP BLOCK DIAGRAM
(I2C MODE)
Internal
Data Bus
Read
Write
Shift
Clock
LSb
MSb
Match Detect
Addr Match
SSPADD reg
Start and
Stop bit Detect
DS39609C-page 166
•
•
•
•
•
MSSP Control Register 1 (SSPCON1)
MSSP Control Register 2 (SSPCON2)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
SSPCON, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON and SSPCON2 registers are readable and
writable. The lower six bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together,
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
SSPSR reg
RC4/
SDI/
SDA
The MSSP module has six registers for I2C operation.
These are:
SSPADD register holds the slave device address
when the SSP is configured in I2C Slave mode. When
the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the Baud Rate
Generator reload value.
SSPBUF reg
RC3/SCK/SCL
REGISTERS
During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
Set, Reset
S, P bits
(SSPSTAT reg)
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REGISTER 17-3:
SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high-speed mode (400 kHz)
bit 6
CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Note:
bit 3
S: Start bit
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
Note:
bit 2
This bit is cleared on Reset and when SSPEN is cleared.
This bit is cleared on Reset and when SSPEN is cleared.
R/W: Read/Write bit Information (I2C mode only)
In Slave mode:
1 = Read
0 = Write
Note:
This bit holds the R/W bit information following the last address match. This bit is only
valid from the address match to the next Start bit, Stop bit, or not ACK bit.
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
Note:
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is
in active mode.
bit 1
UA: Update Address bit (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
In Transmit mode:
1 = SSPBUF is full
0 = SSPBUF is empty
In Receive mode:
1 = SSPBUF is full (does not include the ACK and Stop bits)
0 = SSPBUF is empty (does not include the ACK and Stop bits)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 167
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REGISTER 17-4:
SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be
cleared in software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note:
When enabled, the SDA and SCL pins must be properly configured as input or output.
bit 4
CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (Slave Idle)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Note:
Bit combinations not specifically listed here are either reserved or implemented in
SPI mode only.
Legend:
DS39609C-page 168
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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REGISTER 17-5:
SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
Note:
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence Idle
bit 3
RCEN: Receive Enable bit (Master mode only)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2
PEN: Stop Condition Enable bit (Master mode only)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enabled bit (Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
SEN: Start Condition Enabled/Stretch Enabled bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled)
0 = Clock stretching is disabled
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 169
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17.4.2
OPERATION
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON).
The SSPCON1 register allows control of the I 2C operation. Four mode selection bits (SSPCON) allow
one of the following I 2C modes to be selected:
I2C Master mode, clock = (FOSC/4) x (SSPADD + 1)
I 2C Slave mode (7-bit address)
I 2C Slave mode (10-bit address)
I 2C Slave mode (7-bit address), with Start and
Stop bit interrupts enabled
• I 2C Slave mode (10-bit address), with Start and
Stop bit interrupts enabled
• I 2C Firmware Controlled Master mode, slave is
Idle
•
•
•
•
Selection of any I 2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain, provided these pins are programmed to inputs by setting
the appropriate TRISC bits. To ensure proper operation
of the module, pull-up resistors must be provided
externally to the SCL and SDA pins.
17.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I 2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
When an address is matched or the data transfer after
an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
17.4.3.1
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock
(SCL) line. The value of register SSPSR is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1.
2.
3.
4.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
The SSPSR register value is loaded into the
SSPBUF register.
The Buffer Full bit BF is set.
An ACK pulse is generated.
MSSP Interrupt Flag bit, SSPIF (PIR1), is
set (interrupt is generated, if enabled) on the
falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for
10-bit address is as follows, with steps 7 through 9 for
the slave-transmitter:
1.
2.
3.
4.
5.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit BF (SSPSTAT) was set
before the transfer was received.
• The overflow bit SSPOV (SSPCON) was set
before the transfer was received.
Addressing
6.
7.
8.
9.
Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT) are set).
Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive Repeated Start condition.
Receive first (high) byte of address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
DS39609C-page 170
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17.4.3.2
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT) is
set, or bit SSPOV (SSPCON1) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1) must be cleared in software. The SSPSTAT register is used to determine the
status of the byte.
If SEN is enabled (SSPCON1 = 1), RC3/SCK/SCL
will be held low (clock stretch) following each data
transfer. The clock must be released by setting bit
CKP (SSPCON). See Section 17.4.4 “Clock
Stretching” for more detail.
17.4.3.3
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low, regardless of SEN (see Section 17.4.4 “Clock
Stretching”, for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register,
which also loads the SSPSR register. Then pin RC3/
SCK/SCL should be enabled by setting bit CKP
(SSPCON1). The eight data bits are shifted out on
the falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 17-9).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
2003-2013 Microchip Technology Inc.
DS39609C-page 171
DS39609C-page 172
CKP
2
A6
3
4
A4
5
A3
Receiving Address
A5
6
A2
(CKP does not reset to ‘0’ when SEN = 0)
SSPOV (SSPCON)
BF (SSPSTAT)
(PIR1)
SSPIF
1
SCL
S
A7
7
A1
8
9
ACK
R/W = 0
1
D7
3
4
D4
5
D3
Receiving Data
D5
Cleared in software
SSPBUF is read
2
D6
6
D2
7
D1
8
D0
9
ACK
1
D7
2
D6
3
4
D4
5
D3
Receiving Data
D5
6
D2
7
D1
8
D0
Bus master
terminates
transfer
P
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
9
ACK
FIGURE 17-8:
SDA
PIC18F6520/8520/6620/8620/6720/8720
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
2003-2013 Microchip Technology Inc.
2003-2013 Microchip Technology Inc.
1
CKP
2
A6
Data in
sampled
BF (SSPSTAT)
SSPIF (PIR1)
S
A7
3
A5
4
A4
5
A3
6
A2
Receiving Address
7
A1
8
R/W = 1
9
ACK
SCL held low
while CPU
responds to SSPIF
1
D7
3
D5
4
D4
5
D3
6
D2
CKP is set in software
SSPBUF is written in software
Cleared in software
2
D6
Transmitting Data
7
8
D0
9
ACK
From SSPIF ISR
D1
1
D7
4
D4
5
D3
6
D2
CKP is set in software
7
8
D0
9
ACK
From SSPIF ISR
D1
Transmitting Data
Cleared in software
3
D5
SSPBUF is written in software
2
D6
P
FIGURE 17-9:
SCL
SDA
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I2C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
DS39609C-page 173
DS39609C-page 174
2
1
4
1
5
0
7
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
6
A9 A8
8
9
(CKP does not reset to ‘0’ when SEN = 0)
UA (SSPSTAT)
SSPOV (SSPCON)
CKP
3
1
Cleared in software
BF (SSPSTAT)
(PIR1)
SSPIF
1
SCL
S
1
ACK
R/W = 0
A7
2
4
A4
5
A3
6
8
9
A0 ACK
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware
when SSPADD is updated
with low byte of address
7
A2 A1
Cleared in software
3
A5
Dummy read of SSPBUF
to clear BF flag
1
A6
Receive Second Byte of Address
1
D7
4
5
6
Cleared in software
3
7
Cleared by hardware when
SSPADD is updated with high
byte of address
2
8
9
1
2
4
5
6
Cleared in software
3
D3 D2
Receive Data Byte
D3 D2 D1 D0 ACK D7 D6 D5 D4
Receive Data Byte
D6 D5 D4
Clock is held low until
update of SSPADD has
taken place
7
8
D1 D0
9
P
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
ACK
FIGURE 17-10:
SDA
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
PIC18F6520/8520/6620/8620/6720/8720
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
2003-2013 Microchip Technology Inc.
2003-2013 Microchip Technology Inc.
2
CKP (SSPCON)
UA (SSPSTAT)
BF (SSPSTAT)
(PIR1)
SSPIF
1
S
SCL
1
4
1
5
0
6
7
A9 A8
8
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
3
1
Receive First Byte of Address
1
9
ACK
1
3
4
5
Cleared in software
2
7
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with low
byte of address
6
A6 A5 A4 A3 A2 A1
8
A0
Receive Second Byte of Address
Dummy read of SSPBUF
to clear BF flag
A7
9
ACK
2
3
1
4
1
Cleared in software
1
1
5
0
6
8
9
ACK
R/W = 1
1
2
4
5
6
CKP is set in software
9
P
Completion of
data transmission
clears BF flag
8
ACK
Bus master
terminates
transfer
CKP is automatically cleared in hardware, holding SCL low
7
D4 D3 D2 D1 D0
Cleared in software
3
D7 D6 D5
Transmitting Data Byte
Clock is held low until
CKP is set to ‘1’
Write of SSPBUF
BF flag is clear
initiates transmit
at the end of the
third address sequence
7
A9 A8
Cleared by hardware when
SSPADD is updated with high
byte of address
Dummy read of SSPBUF
to clear BF flag
Sr
1
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
FIGURE 17-11:
SDA
R/W = 0
Clock is held low until
update of SSPADD has
taken place
PIC18F6520/8520/6620/8620/6720/8720
I2C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
DS39609C-page 175
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17.4.4
CLOCK STRETCHING
Both 7- and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence.
The SEN bit (SSPCON2) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
17.4.4.1
Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP being cleared to ‘0’ will assert the
SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 17-13).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software,
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence, in order to prevent an overflow
condition.
17.4.4.2
17.4.4.3
Clock Stretching for 7-bit Slave
Transmit Mode
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock, if the BF bit is clear. This occurs,
regardless of the state of the SEN bit.
The user’s ISR must set the CKP bit before transmission is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 17-9).
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software,
regardless of the state of the BF bit.
17.4.4.4
Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence, which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled as in 7-bit
Slave Transmit mode (see Figure 17-11).
Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence, as described in 7-bit mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by reading the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
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17.4.4.5
Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
FIGURE 17-12:
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 17-12).
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX-1
SCL
CKP
Master device
asserts clock
Master device
deasserts clock
WR
SSPCON
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DS39609C-page 177
DS39609C-page 178
CKP
SSPOV (SSPCON)
BF (SSPSTAT)
(PIR1)
SSPIF
1
SCL
S
A7
2
A6
3
4
A4
5
A3
Receiving Address
A5
6
A2
7
A1
8
9
ACK
R/W = 0
3
4
D4
5
D3
Receiving Data
D5
Cleared in software
2
D6
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur
SSPBUF is read
1
D7
6
D2
7
D1
9
ACK
1
D7
BF is set after falling
edge of the 9th clock,
CKP is reset to ‘0’ and
clock stretching occurs
8
D0
CKP
written
to ‘1’ in
software
2
D6
Clock is held low until
CKP is set to ‘1’
3
4
D4
5
D3
Receiving Data
D5
6
D2
7
D1
8
D0
Bus master
terminates
transfer
P
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
9
ACK
Clock is not held low
because ACK = 1
FIGURE 17-13:
SDA
Clock is not held low
because buffer full bit is
clear prior to falling edge
of 9th clock
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I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
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2003-2013 Microchip Technology Inc.
2
1
UA (SSPSTAT)
SSPOV (SSPCON)
CKP
3
1
4
1
5
0
6
7
A9 A8
8
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
Cleared in software
BF (SSPSTAT)
(PIR1)
SSPIF
1
SCL
S
1
9
ACK
R/W = 0
A7
2
4
A4
5
A3
6
8
A0
Note:
An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
of ninth clock
7
A2 A1
Cleared in software
3
A5
Dummy read of SSPBUF
to clear BF flag
1
A6
Receive Second Byte of Address
9
ACK
2
4
5
6
Cleared in software
3
D3 D2
7
D1
8
Note:
An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set
9
ACK
1
4
5
6
Cleared in software
3
CKP written to ‘1’
in software
2
D3 D2
Receive Data Byte
D7 D6 D5 D4
Clock is held low until
CKP is set to ‘1’
D0
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
of ninth clock
Dummy read of SSPBUF
to clear BF flag
1
D7 D6 D5 D4
Receive Data Byte
Clock is held low until
update of SSPADD has
taken place
7
8
9
Bus master
terminates
transfer
P
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D1 D0
ACK
Clock is not held low
because ACK = 1
FIGURE 17-14:
SDA
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
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I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)
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17.4.5
GENERAL CALL ADDRESS
SUPPORT
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually determines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 17-15).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2
set). Following a Start bit detect, 8 bits are shifted into
the SSPSR and the address is compared against the
SSPADD. It is also compared to the general call
address and fixed in hardware.
FIGURE 17-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
Address is compared to General Call Address
after ACK, set interrupt
R/W = 0
ACK D7
General Call Address
SDA
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
SCL
S
1
2
3
4
5
6
7
8
9
1
9
SSPIF
BF (SSPSTAT)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1)
‘0’
GCEN (SSPCON2)
‘1’
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MASTER MODE
Note:
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset, or when the MSSP module is disabled.
Control of the I 2C bus may be taken when the P bit is
set or the bus is Idle, with both the S and P bits clear.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt if enabled):
In Firmware Controlled Master mode, user code
conducts all I 2C bus operations based on Start and
Stop bit conditions.
•
•
•
•
•
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
Assert a Start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and
SCL.
Write to the SSPBUF register initiating
transmission of data/address.
Configure the I2C port to receive data.
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDA and SCL.
FIGURE 17-16:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start condition is complete. In this case, the SSPBUF
will not be written to and the WCOL bit will
be set, indicating that a write to the
SSPBUF did not occur.
Start Condition
Stop Condition
Data Transfer Byte Transmitted/received
Acknowledge Transmit
Repeated Start
MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Internal
Data Bus
Read
SSPM3:SSPM0
SSPADD
Write
SSPBUF
Baud
Rate
Generator
Shift
Clock
SDA
SDA In
SCL In
Bus Collision
2003-2013 Microchip Technology Inc.
LSb
Start bit, Stop bit,
Acknowledge
Generate
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
Clock Cntl
SCL
Receive Enable
SSPSR
MSb
Clock Arbitrate/WCOL Detect
(hold off clock source)
17.4.6
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
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17.4.6.1
I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an Acknowledge bit is transmitted.
Start and Stop conditions indicate the beginning and
end of transmission.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 17.4.7 “Baud Rate Generator”, for more
information.
DS39609C-page 182
A typical transmit sequence would go as follows:
1.
The user generates a Start condition by setting
the Start enable bit, SEN (SSPCON2).
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all 8 bits are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
11. The user generates a Stop condition by setting
the Stop enable bit PEN (SSPCON2).
12. Interrupt is generated once the Stop condition is
complete.
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17.4.7
BAUD RATE GENERATOR
2
In I C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
FIGURE 17-17:
Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 15-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPM3:SSPM0
Reload
SCL
Control
CLKO
Reload
BRG Down Counter
FOSC/4
I2C CLOCK RATE W/BRG
TABLE 17-3:
Note 1:
SSPADD
FCY
FCY*2
BRG VALUE
FSCL
(2 rollovers of BRG)
10 MHz
20 MHz
19h
400 kHz(1)
10 MHz
20 MHz
20h
312.5 kHz
10 MHz
20 MHz
3Fh
100 kHz
4 MHz
8 MHz
0Ah
400 kHz(1)
4 MHz
8 MHz
0Dh
308 kHz
4 MHz
8 MHz
28h
100 kHz
1 MHz
2 MHz
03h
333 kHz(1)
1 MHz
2 MHz
0Ah
100 kHz
1 MHz
2 MHz
00h
1 MHz(1)
I2C
I2C
The
interface does not conform to the 400 kHz
specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
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17.4.7.1
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 17-18:
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count, in the
event that the clock is held low by an external device
(Figure 15-18).
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
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17.4.8
I2C MASTER MODE START
CONDITION TIMING
17.4.8.1
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
To initiate a Start condition, the user sets the Start Condition Enable bit, SEN (SSPCON2). If the SDA and
SCL pins are sampled high, the Baud Rate Generator
is reloaded with the contents of SSPADD and
starts its count. If SCL and SDA are both sampled high
when the Baud Rate Generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the Start condition and
causes the S bit (SSPSTAT) to be set. Following
this, the Baud Rate Generator is reloaded with the contents of SSPADD and resumes its count. When
the Baud Rate Generator times out (TBRG), the SEN bit
(SSPCON2) will be automatically cleared by
hardware, the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
Note:
WCOL Status Flag
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
If at the beginning of the Start condition,
the SDA and SCL pins are already sampled low, or if during the Start condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
FIGURE 17-19:
FIRST START BIT TIMING
Set S bit (SSPSTAT)
Write to SEN bit occurs here
SDA = 1,
SCL = 1
TBRG
At completion of Start bit,
hardware clears SEN bit
and sets SSPIF bit
TBRG
Write to SSPBUF occurs here
1st bit
SDA
2nd bit
TBRG
SCL
TBRG
S
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17.4.9
I2C MASTER MODE REPEATED
START CONDITION TIMING
Immediately following the setting of the SSPIF bit, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
A Repeated Start condition occurs when the RSEN bit
(SSPCON2) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the
contents of SSPADD and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG, while SCL is high. Following
this, the RSEN bit (SSPCON2) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT) will be set. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.
17.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
FIGURE 17-20:
REPEAT START CONDITION WAVEFORM
S bit set by hardware (SSPSTAT)
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change).
SDA = 1,
SCL = 1
TBRG
TBRG
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
TBRG
1st bit
SDA
Write to SSPBUF occurs here
Falling edge of ninth clock
End of Xmit
TBRG
SCL
TBRG
RSEN bit set
DS39609C-page 186
Sr = Repeated Start
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17.4.10
I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address, or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification parameter
#106). SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high (see data setup time specification
parameter #107). When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time, after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received properly. The status of ACK is written into the ACKDT bit on
the falling edge of the ninth clock. If the master receives
an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 17-21).
After the write to the SSPBUF, each address bit will be
shifted out on the falling edge of SCL, until all seven
address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will deassert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2).
Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is
cleared and the Baud Rate Generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
17.4.10.1
BF Status Flag
17.4.10.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2) is
cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
17.4.11
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2).
Note:
The MSSP module must be in an Idle state
before the RCEN bit is set, or the RCEN
bit will be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes (high-to-low/
low-to-high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The
MSSP is now in Idle state, awaiting the next command.
When the buffer is read by the CPU, the BF flag bit is
automatically cleared. The user can then send an
Acknowledge bit at the end of reception by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2).
17.4.11.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
17.4.11.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
17.4.11.3
WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
In Transmit mode, the BF bit (SSPSTAT) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
17.4.10.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
2003-2013 Microchip Technology Inc.
DS39609C-page 187
DS39609C-page 188
S
R/W
PEN
SEN
BF (SSPSTAT)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
3
4
5
Cleared in software
2
6
7
8
9
After Start condition, SEN cleared by hardware
SSPBUF written
1
D7
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
SSPBUF written with 7-bit address and R/W,
start transmit
A7
Transmit Address to Slave
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
SSPBUF is written in software
Cleared in software service routine
from SSP interrupt
2
D6
Transmitting Data or Second Half
of 10-bit Address
From slave, clear ACKSTAT bit SSPCON2
P
Cleared in software
9
ACK
ACKSTAT in
SSPCON2 = 1
FIGURE 17-21:
SEN = 0
Write SSPCON2 SEN = 1,
Start condition begins
PIC18F6520/8520/6620/8620/6720/8720
I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
2003-2013 Microchip Technology Inc.
2003-2013 Microchip Technology Inc.
S
ACKEN
SSPOV
BF
(SSPSTAT)
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
SCL
SDA
1
A7
2
4
5
Cleared in software
3
6
A6 A5 A4 A3 A2
Transmit Address to Slave
7
A1
8
9
R/W = 1
ACK
ACK from Slave
2
3
5
6
7
8
D0
9
ACK
2
3
4
5
6
7
Cleared in software
Set SSPIF interrupt
at end of Acknowledge
sequence
Data shifted in on falling edge of CLK
1
D7 D6 D5 D4 D3 D2 D1
Cleared in
software
Set SSPIF at end
of receive
9
ACK is not sent
ACK
P
Set SSPIF interrupt
at end of Acknowledge sequence
Bus master
terminates
transfer
Set P bit
(SSPSTAT)
and SSPIF
PEN bit = 1
written here
SSPOV is set because
SSPBUF is still full
8
D0
RCEN cleared
automatically
Set ACKEN, start Acknowledge sequence
SDA = ACKDT = 1
Receiving Data from Slave
RCEN = 1
Start next receive
ACK from Master
SDA = ACKDT = 0
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared in software
Set SSPIF interrupt
at end of receive
4
Cleared in software
1
D7 D6 D5 D4 D3 D2 D1
Receiving Data from Slave
RCEN cleared
automatically
Master configured as a receiver
by programming SSPCON2 (RCEN = 1)
FIGURE 17-22:
SEN = 0
Write to SSPBUF occurs here
Start XMIT
Write to SSPCON2 (SEN = 1),
begin Start Condition
Write to SSPCON2
to start Acknowledge sequence
SDA = ACKDT (SSPCON2) = 0
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I 2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
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17.4.12
ACKNOWLEDGE SEQUENCE
TIMING
17.4.13
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and
counts down to ‘0’. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT) is
set. A TBRG later, the PEN bit is cleared and the SSPIF
bit is set (Figure 17-24).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23).
17.4.12.1
17.4.13.1
WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-23:
STOP CONDITION TIMING
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
TBRG
TBRG
SDA
ACK
D0
SCL
8
9
SSPIF
SSPIF set at the end
of receive
Note:
FIGURE 17-24:
Cleared in
software
Cleared in
software
SSPIF set at the end
of Acknowledge sequence
TBRG = one Baud Rate Generator period.
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT) is set.
Write to SSPCON2
Set PEN
PEN bit (SSPCON2) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
DS39609C-page 190
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PIC18F6520/8520/6620/8620/6720/8720
17.4.14
SLEEP OPERATION
17.4.17
2
While in Sleep mode, the I C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
17.4.15
EFFECT OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.4.16
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I 2C bus may
be taken when the P bit (SSPSTAT) is set, or the
bus is idle with both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be monitored for arbitration, to see if the signal level is the
expected output level. This check is performed in
hardware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
•
•
•
•
•
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 17-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop, or Acknowledge condition was in progress when the bus collision occurred,
the condition is aborted, the SDA and SCL lines are
deasserted and the respective control bits in the
SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if
the I2C bus is free, the user can resume communication
by asserting a Start condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can
be taken when the P bit is set in the SSPSTAT register, or
the bus is Idle and the S and P bits are cleared.
FIGURE 17-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0
SDA line pulled low
by another source
SDA released
by master
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
Bus collision has occurred.
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
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17.4.17.1
Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a)
SDA or SCL are sampled low at the beginning of
the Start condition (Figure 17-26).
SCL is sampled low before SDA is asserted low
(Figure 17-27).
b)
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 17-28). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to ‘0’ and during this time, if the SCL pin
is sampled as ‘0’, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
Note:
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its Idle state
(Figure 17-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD
and counts down to ‘0’. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
FIGURE 17-26:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus collision because the two masters must be
allowed to arbitrate the first address following the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module reset into Idle state.
SEN
BCLIF
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software
DS39609C-page 192
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FIGURE 17-27:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SCL = 0 before SDA = 0,
bus collision occurs. Set BCLIF.
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S
‘0’
‘0’
SSPIF
‘0’
‘0’
FIGURE 17-28:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Less than TBRG
SDA
Set SSPIF
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SCL
S
SCL pulled low after BRG
Time-out
SEN
BCLIF
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
‘0’
S
SSPIF
SDA = 0, SCL = 1
Set SSPIF
2003-2013 Microchip Technology Inc.
Interrupts cleared
in software
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17.4.17.2
Bus Collision During a Repeated
Start Condition
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 17-29).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
Figure 17-30.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD and
counts down to ‘0’. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
FIGURE 17-29:
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is complete.
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
S
‘0’
SSPIF
‘0’
FIGURE 17-30:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
BCLIF
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL.
Interrupt cleared
in software
RSEN
S
‘0’
SSPIF
DS39609C-page 194
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17.4.17.3
Bus Collision During a Stop
Condition
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD
and counts down to ‘0’. After the BRG times out, SDA
is sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 17-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 17-32).
Bus collision occurs during a Stop condition if:
a)
b)
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 17-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG
TBRG
SDA sampled
low after TBRG,
set BCLIF
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
‘0’
SSPIF
‘0’
FIGURE 17-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
Assert SDA
SCL goes low before SDA goes high,
set BCLIF
SCL
PEN
BCLIF
P
‘0’
SSPIF
‘0’
2003-2013 Microchip Technology Inc.
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NOTES:
DS39609C-page 196
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PIC18F6520/8520/6620/8620/6720/8720
18.0
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module (also known as a Serial
Communications Interface or SCI) is one of the two
types of serial I/O modules available on PIC18FXX20
devices. Each device has two USARTs, which can be
configured independently of each other. Each can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers, or as a halfduplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
Register 18-1 shows the layout of the Transmit Status
and Control registers (TXSTAx) and Register 18-2
shows the layout of the Receive Status and Control
registers (RCSTAx). USART1 and USART2 each have
their own independent and distinct pairs of transmit and
receive control registers, which are identical to each
other apart from their names. Similarly, each USART
has its own distinct set of transmit, receive and baud
rate registers.
Note:
Throughout this section, references to
register and bit names that may be associated with a specific USART module are
referred to generically by the use of ‘x’ in
place of the specific module number.
Thus, “RCSTAx” might refer to the receive
status register for either USART1 or
USART2.
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The pins of USART1 and USART2 are multiplexed with
the functions of PORTC (RC6/TX1/CK1 and RC7/RX1/
DT1) and PORTG (RG1/TX2/CK2 and RG2/RX2/DT2),
respectively. In order to configure these pins as a
USART:
• For USART1:
- bit SPEN (RCSTA1) must be set (= 1)
- bit TRISC must be set (= 1)
- bit TRISC must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- bit TRISC must be set (= 1) for
Synchronous Slave mode
• For USART2:
- bit SPEN (RCSTA2) must be set (= 1)
- bit TRISG must be set (= 1)
- bit TRISG must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- bit TRISC must be set (= 1) for
Synchronous Slave mode
2003-2013 Microchip Technology Inc.
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REGISTER 18-1:
TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
bit 7
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note:
R/W-0
BRGH
R-1
TRMT
R/W-0
TX9D
bit 0
SREN/CREN overrides TXEN in Sync mode.
bit 4
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
Unimplemented: Read as ‘0’
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
bit 1
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Legend:
DS39609C-page 198
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2003-2013 Microchip Technology Inc.
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REGISTER 18-2:
RCSTAx: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
bit 7
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
ADDEN
R-0
FERR
R-0
OERR
R-x
RX9D
bit 0
bit 7
SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and load of the receive buffer when RSR
is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
bit 2
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 199
PIC18F6520/8520/6620/8620/6720/8720
18.1
USART Baud Rate Generator
(BRG)
Example 18-1 shows the calculation of the baud rate
error for the following conditions:
•
•
•
•
The BRG supports both the Asynchronous and
Synchronous modes of the USARTs. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTAx) also controls
the baud rate. In Synchronous mode, bit BRGH is
ignored. Table 18-1 shows the formula for computation
of the baud rate for different USART modes, which only
apply in Master mode (internal clock).
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the equation in Example 18-1 can reduce the
baud rate error in some cases.
Writing a new value to the SPBRGx register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGx register can be calculated using the formula in Table 18-1. From this, the
error in baud rate can be determined.
18.1.1
SAMPLING
The data on the RXx pin (either RC7/RX1/DT1 or RG2/
RX2/DT2) is sampled three times by a majority detect
circuit to determine if a high or a low level is present at
the pin.
EXAMPLE 18-1:
CALCULATING BAUD RATE ERROR
Desired Baud Rate
= FOSC/(64 (X + 1))
Solving for X:
= ((FOSC/Desired Baud Rate)/64 ) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
X
X
X
Calculated Baud Rate
=
=
16000000/(64 (25 + 1))
9615
Error
=
(Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
(9615 – 9600)/9600
0.16%
=
=
TABLE 18-1:
BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X + 1))
(Synchronous) Baud Rate = FOSC/(4(X + 1))
Baud Rate = FOSC/(16(X + 1))
N/A
Legend: X = value in SPBRGx (0 to 255)
TABLE 18-2:
Name
TXSTAx
RCSTAx
SPBRGx
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
0000 0000
0000 0000
Baud Rate Generator Register
Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules,
where ‘x’ indicates the particular module. Bit names and Reset values are identical between modules.
DS39609C-page 200
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 18-3:
BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 40 MHz
33 MHz
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
NA
-
1.2
NA
-
2.4
NA
9.6
25 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
NA
-
-
-
NA
NA
-
-
19.2
NA
-
-
76.8
76.92
+0.16
96
96.15
+0.16
300
303.03
+1.01
500
500
0
HIGH
10000
LOW
39.06
20 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
NA
-
-
-
NA
NA
-
-
NA
-
-
129
77.10
+0.39
106
77.16
+0.47
80
76.92
+0.16
64
103
95.93
-0.07
85
96.15
+0.16
64
96.15
+0.16
51
32
294.64
-1.79
27
297.62
-0.79
20
294.12
-1.96
16
19
485.30
-2.94
16
480.77
-3.85
12
500
0
9
-
0
8250
-
0
6250
-
0
5000
-
0
-
255
32.23
-
255
24.41
-
255
19.53
-
255
FOSC = 16 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
-
NA
-
-
-
-
NA
-
-
NA
-
-
NA
-
-
NA
-
-
NA
-
-
10 MHz
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
NA
-
1.2
NA
-
2.4
NA
9.6
7.15909 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
NA
-
-
-
NA
NA
-
-
19.2
19.23
+0.16
76.8
76.92
+0.16
96
95.24
300
500
5.0688 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
NA
-
-
-
NA
NA
-
-
207
19.23
+0.16
51
75.76
-1.36
-0.79
41
96.15
307.70
+2.56
12
500
0
7
HIGH
4000
-
LOW
15.63
-
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
-
NA
-
-
-
-
NA
-
-
9.62
+0.23
185
9.60
0
131
129
19.24
+0.23
92
19.20
0
65
32
77.82
+1.32
22
74.54
-2.94
16
+0.16
25
94.20
-1.88
18
97.48
+1.54
12
312.50
+4.17
7
298.35
-0.57
5
316.80
+5.60
3
500
0
4
447.44
-10.51
3
422.40
-15.52
2
0
2500
-
0
1789.80
-
0
1267.20
-
0
255
9.77
-
255
6.99
-
255
4.95
-
255
FOSC = 4 MHz
BAUD
RATE
(Kbps)
3.579545 MHz
SPBRG
value
(decimal)
SPBRG
value
(decimal)
KBAUD
%
ERROR
0.3
NA
-
-
NA
-
-
NA
-
1.2
NA
-
-
NA
-
-
1.20
+0.16
2.4
NA
-
-
NA
-
-
2.40
+0.16
KBAUD
%
ERROR
1 MHz
KBAUD
%
ERROR
32.768 kHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
0.30
+1.14
26
207
1.17
-2.48
6
103
2.73
+13.78
2
9.6
9.62
+0.16
103
9.62
+0.23
92
9.62
+0.16
25
8.20
-14.67
0
19.2
19.23
+0.16
51
19.04
-0.83
46
19.23
+0.16
12
NA
-
-
76.8
76.92
+0.16
12
74.57
-2.90
11
83.33
+8.51
2
NA
-
-
96
1000
+4.17
9
99.43
+3.57
8
83.33
-13.19
2
NA
-
-
300
333.33
+11.11
2
298.30
-0.57
2
250
-16.67
0
NA
-
-
500
500
0
1
447.44
-10.51
1
NA
-
-
NA
-
-
HIGH
1000
-
0
894.89
-
0
250
-
0
8.20
-
0
LOW
3.91
-
255
3.50
-
255
0.98
-
255
0.03
-
255
2003-2013 Microchip Technology Inc.
DS39609C-page 201
PIC18F6520/8520/6620/8620/6720/8720
TABLE 18-4:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 40 MHz
33 MHz
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
NA
-
1.2
NA
-
2.4
NA
-
25 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
NA
-
-
2.40
-0.07
20 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
NA
-
214
2.40
-0.15
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
-
NA
-
-
162
2.40
+0.16
129
9.6
9.62
+0.16
64
9.55
-0.54
53
9.53
-0.76
40
9.47
-1.36
32
19.2
18.94
-1.36
32
19.10
-0.54
26
19.53
+1.73
19
19.53
+1.73
15
76.8
78.13
+1.73
7
73.66
-4.09
6
78.13
+1.73
4
78.13
+1.73
3
96
89.29
-6.99
6
103.13
+7.42
4
97.66
+1.73
3
104.17
+8.51
2
300
312.50
+4.17
1
257.81
-14.06
1
NA
-
-
312.50
+4.17
0
500
625
+25.00
0
NA
-
-
NA
-
-
NA
-
-
HIGH
625
-
0
515.63
-
0
390.63
-
0
312.50
-
0
LOW
2.44
-
255
2.01
-
255
1.53
-
255
1.22
-
255
FOSC = 16 MHz
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
10 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
7.15909 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
5.0688 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
NA
-
-
NA
-
-
NA
-
-
NA
-
-
1.2
1.20
+0.16
207
1.20
+0.16
129
1.20
+0.23
92
1.20
0
65
2.4
2.40
+0.16
103
2.40
+0.16
64
2.38
-0.83
46
2.40
0
32
9.6
9.62
+0.16
25
9.77
+1.73
15
9.32
-2.90
11
9.90
+3.13
7
19.2
19.23
+0.16
12
19.53
+1.73
7
18.64
-2.90
5
19.80
+3.13
3
76.8
83.33
+8.51
2
78.13
+1.73
1
111.86
+45.65
0
79.20
+3.13
0
96
83.33
-13.19
2
78.13
-18.62
1
NA
-
-
NA
-
-
300
250
-16.67
0
156.25
-47.92
0
NA
-
-
NA
-
-
500
NA
-
-
NA
-
-
NA
-
-
NA
-
-
HIGH
250
-
0
156.25
-
0
111.86
-
0
79.20
-
0
LOW
0.98
-
255
0.61
-
255
0.44
-
255
0.31
-
255
FOSC = 4 MHz
BAUD
RATE
(Kbps)
KBAUD
0.3
1.2
3.579545 MHz
%
ERROR
SPBRG
value
(decimal)
0.30
-0.16
1.20
+1.67
2.4
2.40
9.6
1 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
207
0.30
+0.23
51
1.19
-0.83
+1.67
25
2.43
8.93
-6.99
6
19.2
20.83
+8.51
76.8
62.50
96
NA
300
NA
32.768 kHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
185
0.30
+0.16
46
1.20
+0.16
51
0.26
-14.67
1
12
NA
-
+1.32
22
2.23
-
-6.99
6
NA
-
9.32
-2.90
5
-
7.81
-18.62
1
NA
-
2
18.64
-2.90
-
2
15.63
-18.62
0
NA
-
-
-18.62
0
55.93
-
-
NA
-27.17
0
NA
-
-
NA
-
-
-
-
NA
-
-
NA
-
-
-
NA
-
-
-
NA
-
-
NA
-
-
500
NA
-
-
NA
-
-
NA
-
-
NA
-
-
HIGH
62.50
-
0
55.93
-
0
15.63
-
0
0.51
-
0
LOW
0.24
-
255
0.22
-
255
0.06
-
255
0.002
-
255
DS39609C-page 202
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 18-5:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 40 MHz
33 MHz
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
NA
-
1.2
NA
-
2.4
NA
9.6
25 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
NA
-
-
-
NA
NA
-
-
19.2
19.23
+0.16
76.8
75.76
-1.36
96
96.15
+0.16
300
312.50
+4.17
7
500
500
0
4
HIGH
2500
-
0
LOW
9.77
-
255
20 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
NA
-
-
-
NA
9.60
-0.07
214
129
19.28
+0.39
32
76.39
-0.54
25
98.21
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
-
NA
-
-
-
-
NA
-
-
9.59
-0.15
162
9.62
+0.16
129
106
19.30
+0.47
80
19.23
+0.16
64
26
78.13
+1.73
19
78.13
+1.73
15
+2.31
20
97.66
+1.73
15
96.15
+0.16
12
294.64
-1.79
6
312.50
+4.17
4
312.50
+4.17
3
515.63
+3.13
3
520.83
+4.17
2
416.67
-16.67
2
2062.50
-
0
1562.50
-
0
1250
-
0
8,06
-
255
6.10
-
255
4.88
-
255
FOSC = 16 MHz
10 MHz
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
NA
-
1.2
NA
-
2.4
NA
7.15909 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
NA
-
-
-
NA
5.0688 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
NA
-
-
-
2.41
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
NA
-
-
-
NA
-
-
+0.23
185
2.40
0
131
9.6
9.62
+0.16
103
9.62
+0.16
64
9.52
-0.83
46
9.60
0
32
19.2
19.23
+0.16
51
18.94
-1.36
32
19.45
+1.32
22
18.64
-2.94
16
76.8
76.92
+0.16
12
78.13
+1.73
7
74.57
-2.90
5
79.20
+3.13
3
96
100
+4.17
9
89.29
-6.99
6
89.49
-6.78
4
105.60
+10.00
2
300
333.33
+11.11
2
312.50
+4.17
1
447.44
+49.15
0
316.80
+5.60
0
500
500
0
1
625
+25.00
0
447.44
-10.51
0
NA
-
-
HIGH
1000
-
0
625
-
0
447.44
-
0
316.80
-
0
LOW
3.91
-
255
2.44
-
255
1.75
-
255
1.24
-
255
FOSC = 4 MHz
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
3.579545 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
1 MHz
SPBRG
value
(decimal)
KBAUD
32.768 kHz
%
ERROR
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
NA
-
-
NA
-
-
0.30
+0.16
207
0.29
-2.48
6
1.2
1.20
+0.16
207
1.20
+0.23
185
1.20
+0.16
51
1.02
-14.67
1
2.4
2.40
+0.16
103
2.41
+0.23
92
2.40
+0.16
25
2.05
-14.67
0
9.6
9.62
+0.16
25
9.73
+1.32
22
8.93
-6.99
6
NA
-
-
19.2
19.23
+0.16
12
18.64
-2.90
11
20.83
+8.51
2
NA
-
-
76.8
NA
-
-
74.57
-2.90
2
62.50
-18.62
0
NA
-
-
96
NA
-
-
111.86
+16.52
1
NA
-
-
NA
-
-
300
NA
-
-
223.72
-25.43
0
NA
-
-
NA
-
500
NA
-
-
NA
-
-
NA
-
-
NA
-
-
HIGH
250
-
0
55.93
-
0
62.50
-
0
2.05
-
0
LOW
0.98
-
255
0.22
-
255
0.24
-
255
0.008
-
255
2003-2013 Microchip Technology Inc.
DS39609C-page 203
PIC18F6520/8520/6620/8620/6720/8720
18.2
USART Asynchronous Mode
PIR3 for USART2), is set. This interrupt can be
enabled/disabled by setting/clearing enable bit, TXxIE
(PIE1 for USART1, PIE for USART2). Flag bit
TXxIF will be set, regardless of the state of enable bit
TXxIE and cannot be cleared in software. It will reset
only when new data is loaded into the TXREGx register.
While flag bit TXIF indicates the status of the TXREGx
register, another bit, TRMT (TXSTAx), shows the
status of the TSR register. Status bit TRMT is a read-only
bit, which is set when the TSR register is empty. No
interrupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
In this mode, the USARTs use standard Non-Return-toZero (NRZ) format (one Start bit, eight or nine data bits
and one Stop bit). The most common data format is
8 bits. An on-chip dedicated 8-bit Baud Rate Generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent, but use the same data format
and baud rate. The Baud Rate Generator produces a
clock, either 16 or 64 times the bit shift rate, depending
on bit BRGH (TXSTAx). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during Sleep.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.
Asynchronous mode is selected by clearing bit SYNC
(TXSTAx).
To set up an Asynchronous Transmission:
The USART Asynchronous module consists of the
following important elements:
1.
•
•
•
•
2.
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
18.2.1
3.
USART ASYNCHRONOUS
TRANSMITTER
4.
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREGx register (if available).
Once the TXREGx register transfers the data to the
TSR register (occurs in one TCY), the TXREGx register
is empty and flag bit, TXx1IF (PIR1 for USART1,
FIGURE 18-1:
Initialize the SPBRGx register for the appropriate baud rate. If a high-speed baud rate is
desired, set bit BRGH (Section 18.1 “USART
Baud Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXxIE in
the appropriate PIE register.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN,
which will also set bit TXxIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREGx register (starts
transmission).
5.
6.
7.
Note:
TXIF is not cleared immediately upon
loading data into the transmit buffer
TXREG. The flag bit becomes valid in the
second instruction cycle following the load
instruction.
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG Register
TXIE
8
MSb
LSb
(8)
Pin Buffer
and Control
0
TSR Register
TX pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
DS39609C-page 204
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FIGURE 18-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
BRG Output
(Shift Clock)
Word 1
RC6/TX1/CK1 (pin)
Start bit
bit 0
bit 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 18-3:
bit 7/8
Stop bit
Word 1
Word 1
Transmit Shift Reg
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX1/CK1 (pin)
TXIF bit
(Interrupt Reg. Flag)
Start bit
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
bit 1
Word 1
bit 7/8
Stop bit
Start bit
bit 0
Word 2
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
INTCON
bit 0
This timing diagram shows two consecutive transmissions.
TABLE 18-6:
Name
Word 2
GIE/GIEH
Bit 6
Bit 5
PEIE/GIEL TMR0IE
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
0000 0000
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0111 1111
0111 1111
PIR3
—
—
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
--00 0000
--00 0000
PIE3
—
—
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
--00 0000
--00 0000
—
—
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
--11 1111
--11 1111
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
IPR3
RCSTAx(1)
TXREGx(1) USART Transmit Register
TXSTAx(1)
(1)
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
SPBRGx
Baud Rate Generator Register
Legend:
Note 1:
x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
2003-2013 Microchip Technology Inc.
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PIC18F6520/8520/6620/8620/6720/8720
18.2.2
USART ASYNCHRONOUS
RECEIVER
18.2.3
The USART receiver block diagram is shown in
Figure 18-4. The data is received on the pin (RC7/RX1/
DT1 or RG2/RX2/DT2) and drives the data recovery
block. The data recovery block is actually a high-speed
shifter operating at 16 times the baud rate, whereas the
main receive serial shifter operates at the bit rate or at
FOSC. This mode would typically be used in RS-232
systems.
To set up an Asynchronous Reception:
1.
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 18.1 “USART Baud
Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit RCxIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCxIF will be set when reception is complete and an interrupt will be generated if enable
bit RCxIE was set.
7. Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON) are
set.
FIGURE 18-4:
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
Initialize the SPBRGx register for the appropriate baud rate. If a high-speed baud rate is
required, set the BRGH bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
7. The RCxIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCxIE and GIE bits are set.
8. Read the RCSTAx register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
9. Read RCREGx to determine if the device is
being addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
USART RECEIVE BLOCK DIAGRAM
CREN
FERR
OERR
x64 Baud Rate CLK
SPBRG
64
or
16
RSR Register
MSb
Stop
(8)
7
1
LSb
0
Start
Baud Rate Generator
RX9
RX pin
Pin Buffer
and Control
Data
Recovery
RX9D
RCREG Register
FIFO
SPEN
8
Interrupt
RCIF
Data Bus
RCIE
DS39609C-page 206
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FIGURE 18-5:
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX (pin)
bit 1
Start
bit
bit 7/8 Stop
bit
Rcv Shift
Reg
Rcv Buffer Reg
bit 0
Stop
bit
Start
bit
bit 7/8
Stop
bit
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
bit 7/8
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 18-7:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
0000 0000
PIR1
PSPIF
ADIF
RC1IF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE
ADIE
RC1IE
TXIE
SSPIE
CCP1IE TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP
ADIP
RC1IP
TXIP
SSPIP
CCP1IP TMR2IP
TMR1IP
0111 1111
0111 1111
PIR3
—
—
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
--00 0000
--00 0000
PIE3
—
—
RC2IE
TX2IE
TMR4IE CCP5IE
CCP4IE
CCP3IE
--00 0000
--00 0000
IPR3
—
—
RC2IP
TX2IP
TMR4IP CCP5IP
CCP4IP
CCP3IP
--11 1111
--11 1111
SPEN
RX9
SREN
CREN
ADDEN
OERR
RX9D
0000 000x
0000 000x
0000 0000
0000 0000
RCSTAx(1)
FERR
RCREGx(1) USART Receive Register
TXSTAx(1)
CSRC
TX9
TXEN
SPBRGx(1) Baud Rate Generator Register
Legend:
Note 1:
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
2003-2013 Microchip Technology Inc.
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PIC18F6520/8520/6620/8620/6720/8720
18.3
USART Synchronous Master
Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTAx). In
addition, enable bit SPEN (RCSTAx) is set in order
to configure the appropriate I/O pins to CK (clock) and
DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on
the CK line. The Master mode is entered by setting bit
CSRC (TXSTAx).
18.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
To set up a Synchronous Master Transmission:
1.
Initialize the SPBRG register for the appropriate
baud rate (Section 18.1 “USART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
If interrupts are desired, set enable bit TXxIE in
the appropriate PIE register.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREGx register.
2.
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREGx (if available). Once the
TXREGx register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREGx is empty and
interrupt bit TXxIF (PIR1 for USART1, PIR3 for
USART2) is set. The interrupt can be enabled/disabled
by setting/clearing enable bit TXxIE (PIE1 for
USART1, PIE3 for USART2). Flag bit TXxIF will be
TABLE 18-8:
set, regardless of the state of enable bit TXxIE and cannot be cleared in software. It will reset only when new
data is loaded into the TXREGx register. While flag bit
TXxIF indicates the status of the TXREGx register,
another bit TRMT (TXSTAx) shows the status of the
TSR register. TRMT is a read-only bit, which is set
when the TSR is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty. The TSR is not mapped in
data memory, so it is not available to the user.
3.
4.
5.
6.
7.
Note:
TXIF is not cleared immediately upon
loading data into the transmit buffer
TXREG. The flag bit becomes valid in the
second instruction cycle following the load
instruction.
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
0000 0000
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0111 1111
0111 1111
PIR3
—
—
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
--00 0000
--00 0000
PIE3
—
—
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
--00 0000
--00 0000
IPR3
—
—
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
--11 1111
--11 1111
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
0000 0000
0000 0000
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
RCSTAx(1)
TXREGx(1) USART Transmit Register
TXSTAx(1)
(1)
SPBRGx
Legend:
Note 1:
CSRC
TX9
TXEN
Baud Rate Generator Register
x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
DS39609C-page 208
2003-2013 Microchip Technology Inc.
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FIGURE 18-6:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
pin
bit 0
bit 1
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 2
bit 7
Word 1
bit 0
bit 1
Word 2
bit 7
RC6/TX1/CK1
pin
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT
TRMT
bit
TXEN bit
Note:
‘1’
‘1’
Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words.
FIGURE 18-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX1/DT1 pin
bit 0
bit 1
bit 2
bit 6
bit 7
RC6/TX1/CK1 pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
2003-2013 Microchip Technology Inc.
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18.3.2
USART SYNCHRONOUS MASTER
RECEPTION
4.
If interrupts are desired, set enable bit RCxIE in
the appropriate PIE register.
5. If 9-bit reception is desired, set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCxIF will be set when
reception is complete and an interrupt will be
generated if the enable bit RCxIE was set.
8. Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREGx register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON) are
set.
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTAx) or enable bit CREN (RCSTAx). Data
is sampled on the RXx pin (RC7/RX1/DT1 or RG2/RX2/
DT2) on the falling edge of the clock. If enable bit SREN
is set, only a single word is received. If enable bit CREN
is set, the reception is continuous until CREN is cleared.
If both bits are set, then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
3.
Initialize the SPBRGx register for the appropriate baud rate (Section 18.1 “USART Baud
Rate Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Ensure bits CREN and SREN are clear.
TABLE 18-9:
Name
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
0000 0000
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0111 1111
0111 1111
PIR3
—
—
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
--00 0000
--00 0000
PIE3
—
—
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
--00 0000
--00 0000
IPR3
—
—
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
--11 1111
--11 1111
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
INTCON
RCSTAx
GIE/GIEH PEIE/GIEL
(1)
RCREGx(1) USART Receive Register
TXSTAx(1)
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
SPBRGx(1) Baud Rate Generator Register
Legend:
Note 1:
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
FIGURE 18-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1 pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX1/CK1 pin
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
DS39609C-page 210
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18.4
USART Synchronous Slave Mode
To set up a Synchronous Slave Transmission:
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the TXx pin (RC6/TX1/CK1 or RG1/TX2/CK2), instead
of being supplied internally in Master mode. TRISC
must be set for this mode. This allows the device to
transfer or receive data while in Sleep mode. Slave
mode is entered by clearing bit CSRC (TXSTAx).
18.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
1.
2.
3.
4.
5.
6.
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
7.
8.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXxIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON) are
set.
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXxIF will not be set.
When the first word has been shifted out of TSR,
the TXREGx register will transfer the second
word to the TSR and flag bit TXxIF will now be
set.
If enable bit TXxIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
0000 0000
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0111 1111
0111 1111
PIR3
—
—
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
--00 0000
--00 0000
PIE3
—
—
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
--00 0000
--00 0000
IPR3
—
—
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
--11 1111
--11 1111
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
0000 0000
0000 0000
RCSTAx(1)
TXREGx(1) USART Transmit Register
TXSTAx(1)
CSRC
TX9
TXEN
SPBRGx(1) Baud Rate Generator Register
Legend:
Note 1:
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
2003-2013 Microchip Technology Inc.
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PIC18F6520/8520/6620/8620/6720/8720
18.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
To set up a Synchronous Slave Reception:
1.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode and bit SREN, which is a “don’t care” in Slave
mode.
2.
3.
4.
5.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if
enable bit RCxIE bit is set, the interrupt generated will
wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector.
6.
7.
8.
9.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCxIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCxIF will be set when reception is
complete. An interrupt will be generated if
enable bit RCxIE was set.
Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON) are
set.
TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
0000 0000
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0111 1111
0111 1111
PIR3
—
—
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
--00 0000
--00 0000
PIE3
—
—
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
--00 0000
--00 0000
IPR3
—
—
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
--11 1111
--11 1111
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RCSTAx(1)
RCREGx(1) USART Receive Register
TXSTAx(1)
SPBRGx(1)
Legend:
Note 1:
CSRC
TX9
TXEN
Baud Rate Generator Register
SYNC
—
BRGH
TRMT
TX9D
0000 000x
0000 000x
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
DS39609C-page 212
2003-2013 Microchip Technology Inc.
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19.0
10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The module has five registers:
The analog-to-digital (A/D) converter module has 12
inputs for the PIC18F6X20 devices and 16 for the
PIC18F8X20 devices. This module allows conversion
of an analog input signal to a corresponding 10-bit
digital number.
REGISTER 19-1:
•
•
•
•
•
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
A/D Control Register 2 (ADCON2)
The ADCON0 register, shown in Register 19-1, controls the operation of the A/D module. The ADCON1
register, shown in Register 19-2, configures the functions of the port pins. The ADCON2 register, shown in
Register 19-3, configures the A/D clock source and
justification.
ADCON0 REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5-2
CHS3:CHS0: Analog Channel Select bits
0000 = Channel 0 (AN0)
0001 = Channel 1 (AN1)
0010 = Channel 2 (AN2)
0011 = Channel 3 (AN3)
0100 = Channel 4 (AN4)
0101 = Channel 5 (AN5)
0110 = Channel 6 (AN6)
0111 = Channel 7 (AN7)
1000 = Channel 8 (AN8)
1001 = Channel 9 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12)(1)
1101 = Channel 13 (AN13)(1)
1110 = Channel 14 (AN14)(1)
1111 = Channel 15 (AN15)(1)
Note 1: These channels are not available on the PIC18F6X20 (64-pin) devices.
bit 1
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion, which is automatically
cleared by hardware when the A/D conversion is complete)
0 = A/D conversion not in progress
bit 0
ADON: A/D On bit
1 = A/D converter module is enabled
0 = A/D converter module is disabled
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 213
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 19-2:
ADCON1 REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
VCFG1:VCFG0: Voltage Reference Configuration bits:
VCFG1
VCFG0
A/D VREF-
00
AVDD
AVSS
01
External VREF+
AVSS
10
AVDD
External VREF-
11
External VREF+
External VREF-
PCFG3
PCFG0
AN14
AN13
AN12
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PCFG3:PCFG0: A/D Port Configuration Control bits:
AN15
bit 3-0
A/D VREF+
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
A = Analog input
Note:
D = Digital I/O
Shaded cells indicate A/D channels available only on PIC18F8X20 devices.
Legend:
DS39609C-page 214
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 19-3:
ADCON2 REGISTER
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
ADFM
—
—
—
—
ADCS2
ADCS1
ADCS0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6-3
Unimplemented: Read as ‘0’
bit 2-0
ADCS1:ADCS0: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock derived from an RC oscillator = 1 MHz max)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC (clock derived from an RC oscillator = 1 MHz max)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+ pin and RA2/AN2/VREF- pin.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
x = Bit is unknown
Each port pin associated with the A/D converter can be
configured as an analog input (RA3 can also be a
voltage reference), or as a digital I/O. The ADRESH
and ADRESL registers contain the result of the A/D
conversion. When the A/D conversion is complete, the
result is loaded into the ADRESH/ADRESL registers,
the GO/DONE bit (ADCON0 register) is cleared and
A/D interrupt flag bit, ADIF, is set. The block diagram of
the A/D module is shown in Figure 19-1.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion is aborted.
2003-2013 Microchip Technology Inc.
DS39609C-page 215
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FIGURE 19-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1111
AN15(1)
1110
AN14(1)
1101
AN13(1)
1100
AN12(1)
1011
1010
1001
1000
0111
0110
0101
0100
VAIN
0011
(Input Voltage)
10-bit
Converter
A/D
0010
0001
VCFG1:VCFG0
0000
VDD
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
VREF+
Reference
Voltage
VREFVSS
Note 1: Channels AN15 through AN12 are not available on PIC18F6X20 devices.
2: I/O pins have diode protection to VDD and VSS.
DS39609C-page 216
2003-2013 Microchip Technology Inc.
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The value in the ADRESH/ADRESL registers is not
modified for a Power-on Reset. The ADRESH/
ADRESL registers will contain unknown data after a
Power-on Reset.
2.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 19.1
“A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be
started.
3.
4.
The following steps should be followed to do an A/D
conversion:
6.
1.
7.
5.
Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
FIGURE 19-2:
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0 register)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
For the next conversion, go to step 1 or step 2,
as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
Rs
VAIN
RIC 1k
ANx
CPIN
5 pF
VT = 0.6V
SS
RSS
ILEAKAGE
± 500 nA
CHOLD = 120 pF
VSS
Legend: CPIN
= input capacitance
= threshold voltage
VT
ILEAKAGE = leakage current at the pin due to
various junctions
= interconnect resistance
RIC
= sampling switch
SS
= sample/hold capacitance (from DAC)
CHOLD
RSS
= sampling switch resistance
2003-2013 Microchip Technology Inc.
VDD
6V
5V
4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch (k)
DS39609C-page 217
PIC18F6520/8520/6620/8620/6720/8720
19.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 19-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 k. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
Note:
Example 19-1 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
VHOLD
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
To calculate the minimum acquisition time,
Equation 19-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
=
=
=
=
=
120 pF
2.5 k
1/2 LSb
5V Rss = 7 k
50C (system max.)
0V @ time = 0
Note: When using external voltage references with
the A/D converter, the source impedance of
the external voltage references must be less
than 20 to obtain the A/D performance
specified in parameters A01-A06. Higher
reference source impedances will increase
both offset and gain errors. Resistive voltage
dividers will not provide a sufficiently low
source impedance.
To maintain the best possible performance in
A/D conversions, external VREF inputs should
be buffered with an operational amplifier or
other low output impedance circuit.
If deviating from the operating conditions
specified for parameters A03-A06, the effect
of parameter A50 (VREF input current) must
be considered.
EQUATION 19-1:
TACQ
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 19-2:
VHOLD =
or
=
TC
=
A/D MINIMUM CHARGING TIME
(VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS)))
-(120 pF)(1 k + RSS + RS) ln(1/2047)
EXAMPLE 19-1:
TACQ
ACQUISITION TIME
=
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25C.
TACQ
=
2 s + TC + [(Temp – 25C)(0.05 s/C)]
TC
=
-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 k + 7 k + 2.5 k) ln(0.0004885)
-120 pF (10.5 k) ln(0.0004885)
-1.26 s (-7.6241)
9.61 s
TACQ
=
2 s + 9.61 s + [(50C – 25C)(0.05 s/C)]
11.61 s + 1.25 s
12.86 s
DS39609C-page 218
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
19.2
Selecting the A/D
Conversion Clock
19.3
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 12 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
•
•
•
•
•
•
•
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal RC oscillator
The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs will convert as an
analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
2: Analog levels on any pin defined as a digital input may cause the input buffer to
consume current out of the device’s
specification limits.
Table 19-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 19-1:
Configuring Analog Port Pins
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS2:ADCS0
PIC18FXX20
2 TOSC
000
1.25 MHz
666 kHz
TOSC
100
2.50 MHz
1.33 MHz
8 TOSC
001
5.00 MHz
2.67 MHz
16 TOSC
101
10.0 MHz
5.33 MHz
32 TOSC
010
20.0 MHz
10.67 MHz
64 TOSC
110
40.0 MHz
21.33 MHz
RC
x11
—
—
4
2003-2013 Microchip Technology Inc.
PIC18LFXX20
DS39609C-page 219
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19.4
A/D Conversions
19.5
Figure 19-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2 TAD wait
is required before the next acquisition is started. After
this 2 TAD wait, acquisition on the selected channel is
automatically started.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Use of the CCP2 Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON) be programmed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion and
the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a
conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D module,
but will still reset the Timer1 (or Timer3) counter.
FIGURE 19-3:
A/D CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b0
b1
b3
b0
b4
b2
b5
b7
b6
b8
b9
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
DS39609C-page 220
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 19-2:
SUMMARY OF A/D REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
0000 0000
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
0111 1111
0111 1111
PIR2
—
CMIF
—
—
BCLIF
LVDIF
TMR3IF
CCP2IF
-0-- 0000
-0-- 0000
PIE2
—
CMIE
—
—
BCLIE
LVDIE
TMR3IE
CCP2IE
-0-- 0000
-0-- 0000
IPR2
—
CMIP
—
—
BCLIP
LVDIP
TMR3IP
CCP2IP
-0-- 0000
-0-- 0000
ADRESH
A/D Result Register High Byte
xxxx xxxx
uuuu uuuu
ADRESL
A/D Result Register Low Byte
xxxx xxxx
uuuu uuuu
ADCON0
—
—
CHS3
CHS3
CHS1
CHS0
GO/DONE
ADON
--00 0000
--00 0000
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
--00 0000
--00 0000
ADCON2
ADFM
—
—
—
—
ADCS2
ADCS1
ADCS0
0--- -000
0--- -000
RA6
RA5
RA4
RA3
RA2
RA1
RA0
PORTA
—
TRISA
—
PORTF
LATF
TRISF
PORTH(1)
LATH(1)
PORTA Data Direction Register
--0x 0000
--0u 0000
--11 1111
--11 1111
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
x000 0000
u000 0000
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
PORTF Data Direction Control Register
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
0000 xxxx
0000 xxxx
LATH7
LATH6
LATH5
LATH4
LATH3
LATH2
LATH1
LATH0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
TRISH(1)
PORTH Data Direction Control Register
Legend:
Note 1:
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Only available on PIC18F8X20 devices.
2003-2013 Microchip Technology Inc.
DS39609C-page 221
PIC18F6520/8520/6620/8620/6720/8720
NOTES:
DS39609C-page 222
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20.0
COMPARATOR MODULE
The comparator module contains two analog comparators. The inputs to the comparators are multiplexed
with the RF1 through RF6 pins. The on-chip voltage reference (Section 21.0 “Comparator Voltage Reference
Module”) can also be an input to the comparators.
REGISTER 20-1:
The CMCON register, shown as Register 20-1, controls the comparator input and output multiplexers. A
block diagram of the various comparator configurations
is shown in Figure 20-1.
CMCON REGISTER
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
bit 7
bit 0
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1:
1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1:
1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VIN-
bit 5
C2INV: Comparator 2 Output Inversion bit
1 = C2 output inverted
0 = C2 output not inverted
bit 4
C1INV: Comparator 1 Output Inversion bit
1 = C1 output inverted
0 = C1 output not inverted
bit 3
CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1 = C1 VIN- connects to RF5/AN10
C2 VIN- connects to RF3/AN8
0 = C1 VIN- connects to RF6/AN11
C2 VIN- connects to RF4/AN9
bit 2-0
CM2:CM0: Comparator Mode bits
Figure 20-1 shows the Comparator modes and the CM2:CM0 bit settings.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 223
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20.1
Comparator Configuration
There are eight modes of operation for the comparators. The CMCON register is used to select these
modes. Figure 20-1 shows the eight possible modes.
The TRISF register controls the data direction of the
comparator pins for each mode. If the Comparator
mode is changed, the comparator output level may not
FIGURE 20-1:
A
VIN+
A
VIN-
RF3/AN8
A
VIN+
A
VIN-
RF5/AN10 A
VIN+
D
VIN-
RF5/AN10 D
VIN+
D
VIN-
D
VIN+
RF6/AN11
C1
Off (Read as ‘0’)
C2
Off (Read as ‘0’)
RF4/AN9
RF3/AN8
A
VIN-
RF5/AN10 A
VIN+
RF6/AN11
C1
C1
Off (Read as ‘0’)
C2
Off (Read as ‘0’)
Two Independent Comparators with Outputs
CM2:CM0 = 011
Two Independent Comparators
CM2:CM0 = 010
RF6/AN11
Comparator interrupts should be disabled
during a Comparator mode change.
Otherwise, a false interrupt may occur.
Comparators Off
CM2:CM0 = 111
VIN-
RF5/AN10 A
RF4/AN9
Note:
COMPARATOR I/O OPERATING MODES
Comparators Reset (POR Default Value)
CM2:CM0 = 000
RF6/AN11
be valid for the specified mode change delay shown in
the Electrical Specifications (Section 26.0 “Electrical
Characteristics”).
C1OUT
C1
C1OUT
C2
C2OUT
RF2/AN7/C1OUT
RF4/AN9
RF3/AN8
A
VIN-
A
VIN+
C2
RF4/AN9
C2OUT
RF3/AN8
A
VIN-
A
VIN+
RF1/AN6/C2OUT
Two Common Reference Comparators
CM2:CM0 = 100
RF6/AN11
A
RF5/AN10 A
Two Common Reference Comparators with Outputs
CM2:CM0 = 101
VINVIN+
A
VIN-
RF5/AN10 A
VIN+
RF6/AN11
C1
C1OUT
C1
C1OUT
C2
C2OUT
RF2/AN7/C1OUT
RF4/AN9
RF3/AN8
A
VIN-
D
VIN+
C2
C2OUT
RF4/AN9
RF3/AN8
A
VIN-
D
VIN+
RF1/AN6/C2OUT
Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 110
One Independent Comparator with Output
CM2:CM0 = 001
RF6/AN11
RF5/AN10
A
VIN-
A
VIN+
RF6/AN11
C1
C1OUT
RF5/AN10 A
RF2/AN7/C1OUT
RF4/AN9
RF3/AN8
RF4/AN9
D
VIN-
D
VIN+
RF3/AN8
C2
CIS = 0
CIS = 1
VINVIN+
C1
C1OUT
C2
C2OUT
A
A
CIS = 0
CIS = 1
VINVIN+
Off (Read as ‘0’)
A = Analog Input, port reads zeros always
DS39609C-page 224
A
CVREF
D = Digital Input
From VREF Module
CIS (CMCON) is the Comparator Input Switch
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20.2
20.3.2
Comparator Operation
INTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure 20-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 20-2 represent
the uncertainty, due to input offsets and response time.
The comparator module also allows the selection of an
internally generated voltage reference for the comparators. Section 21.0 “Comparator Voltage Reference
Module” contains a detailed description of the comparator voltage reference module that provides this signal.
The internal reference signal is used when comparators
are in mode CM = 110 (Figure 20-1). In this
mode, the internal voltage reference is applied to the
VIN+ pin of both comparators.
20.3
20.4
Comparator Reference
An external or internal reference signal may be used,
depending on the comparator operating mode. The
analog signal present at VIN- is compared to the signal
at VIN+ and the digital output of the comparator is
adjusted accordingly (Figure 20-2).
FIGURE 20-2:
VIN+
VIN-
SINGLE COMPARATOR
+
–
Response time is the minimum time, after selecting a
new reference voltage or input source, before the comparator output has a valid level. If the internal reference
is changed, the maximum delay of the internal voltage
reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the
comparators should be used (Section 26.0 “Electrical
Characteristics”).
20.5
Output
VIN
VIN–
VIN
+
VIN+
Comparator Response Time
Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RF1 and RF2
I/O pins. When enabled, multiplexors in the output path
of the RF1 and RF2 pins will switch and the output of
each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is
related to the input offset voltage and the response time
given in the specifications. Figure 20-3 shows the
comparator output block diagram.
The TRISF bits will still function as an output enable/
disable for the RF1 and RF2 pins while in this mode.
Output
Output
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON).
20.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the comparators operate from the same, or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
2003-2013 Microchip Technology Inc.
Note 1: When reading the port register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input, according to the
Schmitt Trigger input specification.
2: Analog levels on any pin defined as a digital input may cause the input buffer to
consume more current than is specified.
DS39609C-page 225
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FIGURE 20-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port pins
MULTIPLEX
+
CxINV
To RF1 or
RF2 pin
Bus
Data
Q
Read CMCON
Set
CMIF
bit
D
EN
Q
From
Other
Comparator
D
EN
CL
Read CMCON
Reset
20.6
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON, to
determine the actual change that occurred. The CMIF
bit (PIR registers) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing ‘0’. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE registers) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
DS39609C-page 226
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR
registers) interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of CMCON will end the
mismatch condition.
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
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20.7
Comparator Operation
During Sleep
20.9
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional, if enabled. This interrupt will
wake-up the device from Sleep mode, when enabled.
While the comparator is powered up, higher Sleep
currents than shown in the power-down current
specification will occur. Each operational comparator
will consume additional current, as shown in the comparator specifications. To minimize power consumption
while in Sleep mode, turn off the comparators
(CM = 111) before entering Sleep. If the device
wakes up from Sleep, the contents of the CMCON
register are not affected.
20.8
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 20-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 k is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator module to be in the Comparator Reset mode, CM = 000. This ensures
that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at
Reset time. The comparators will be powered down
during the Reset interval.
FIGURE 20-4:
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RS < 10k
RIC
Comparator
Input
AIN
CPIN
5 pF
VA
VT = 0.6V
ILEAKAGE
±500 nA
VSS
Legend:
CPIN
VT
ILEAKAGE
RIC
RS
VA
2003-2013 Microchip Technology Inc.
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the pin due to various junctions
Interconnect Resistance
Source Impedance
Analog Voltage
DS39609C-page 227
PIC18F6520/8520/6620/8620/6720/8720
TABLE 20-1:
Name
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 5
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000 0000 0000
CVRCON CVREN CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
0000 0000 0000 0000
TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
INTCON
Bit 3
Bit 2
Bit 1
Bit 0
Value on
all other
Resets
Bit 6
CMCON
Bit 4
Value on
POR
Bit 7
GIE/
GIEH
PEIE/
GIEL
PIR2
—
CMIF
—
—
BCLIF
LVDIF
TMR3IF CCP2IF -0-- 0000 -0-- 0000
PIE2
—
CMIE
—
—
BCLIE
LVDIE
TMR3IE CCP2IE -0-- 0000 -0-- 0000
IPR2
—
CMIP
—
—
BCLIP
LVDIP
TMR3IP CCP2IP -1-- 1111 -1-- 1111
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
x000 0000 u000 0000
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
xxxx xxxx uuuu uuuu
TRISF
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’.
Shaded cells are unused by the comparator module.
DS39609C-page 228
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21.0
COMPARATOR VOLTAGE
REFERENCE MODULE
21.1
Configuring the Comparator
Voltage Reference
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two
ranges of CVREF values and has a power-down function
to conserve power when the reference is not being used.
The CVRCON register controls the operation of the
reference as shown in Register 21-1. The block diagram
is given in Figure 21-1.
The comparator voltage reference can output 16 distinct
voltage levels for each range. The equations used to
calculate the output of the comparator voltage reference
are as follows:
The comparator reference supply voltage can come
from either VDD or VSS, or the external VREF+ and
VREF- that are multiplexed with RA3 and RA2. The
comparator reference supply voltage is controlled by
the CVRSS bit.
The settling time of the comparator voltage reference
must be considered when changing the CVREF output
(Section 26.0 “Electrical Characteristics”).
If CVRR = 1:
CVREF = (CVR/24) x CVRSRC
If CVRR = 0:
CVREF = (CVRSRC x 1/4) + (CVR/32) x CVRSRC
Note: In order to select external VREF+ and VREFsupply voltages, the Voltage Reference Configuration bits (VCFG1:VCFG0) of the
ADCON1 register must be set appropriately.
REGISTER 21-1:
CVRCON REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down
bit 6
CVROE: Comparator VREF Output Enable bit(1)
1 = CVREF voltage level is also output on the RF5/AN10/CVREF pin
0 = CVREF voltage is disconnected from the RF5/AN10/CVREF pin
bit 5
CVRR: Comparator VREF Range Selection bit
1 = 0.00 CVRSRC to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
bit 4
CVRSS: Comparator VREF Source Selection bit(2)
1 = Comparator reference source CVRSRC = VREF+ – VREF0 = Comparator reference source CVRSRC = VDD – VSS
bit 3-0
CVR3:CVR0: Comparator VREF Value Selection bits (0 VR3:VR0 15)
When CVRR = 1:
CVREF = (CVR/24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (CVR3:CVR0/32) (CVRSRC)
Note 1: If enabled for output, RF5 must also be configured as an input by setting TRISF
to ‘1’.
2: In order to select external VREF+ and VREF- supply voltages, the Voltage
Reference Configuration bits (VCFG1:VCFG0) of the ADCON1 register must be
set appropriately.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 229
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 21-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
VDD VREF+
CVRSS = 0
16 Stages
CVRSS = 1
CVREN
8R
R
R
R
R
CVRR
8R
CVRSS = 0
CVRSS = 1
CVREF
16-1 Analog Mux
VREFCVR3
(From CVRCON)
CVR0
Note: R is defined in Section 26.0 “Electrical Characteristics”.
21.2
Voltage Reference Accuracy/Error
21.4
Effects of a Reset
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 21-1) keep CVREF from approaching the reference source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 26.0 “Electrical Characteristics”.
A device Reset disables the voltage reference by
clearing bit CVREN (CVRCON). This Reset also
disconnects the reference from the RA2 pin by clearing
bit CVROE (CVRCON) and selects the highvoltage range by clearing bit CVRR (CVRCON).
The VRSS value select bits, CVRCON, are also
cleared.
21.3
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
TRISF bit is set and the CVROE bit is set. Enabling
the voltage reference output onto the RF5 pin,
configured as a digital input, will increase current
consumption. Connecting RF5 as a digital output with
VRSS enabled will also increase current consumption.
Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
21.5
Connection Considerations
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage reference output for external connections to VREF.
Figure 21-2 shows an example buffering technique.
DS39609C-page 230
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FIGURE 21-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
R(1)
CVREF
Module
RF5
+
–
CVREF Output
Voltage
Reference
Output
Impedance
Note 1:
TABLE 21-1:
Name
R is dependent upon the Comparator Voltage Reference Configuration bits CVRCON and CVRCON.
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Bit 7
Bit 6
Value on
POR
Value on
all other
Resets
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVRCON CVREN CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
0000 0000 0000 0000
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000 0000 0000
TRISF
TRISF7
TRISF6 TRISF5 TRISF4 TRISF3
TRISF2
TRISF1
TRISF0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’.
Shaded cells are not used with the comparator voltage reference.
2003-2013 Microchip Technology Inc.
DS39609C-page 231
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NOTES:
DS39609C-page 232
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22.0
LOW-VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application software can do “housekeeping tasks” before the device
voltage exits the valid operating range. This can be
done using the Low-Voltage Detect module.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When the voltage of the device becomes lower then the
specified point, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the interrupt vector address and the software can then respond
to that interrupt source.
Figure 22-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage VA,
the LVD logic generates an interrupt. This occurs at
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to shut down the system. Voltage point VB is the
minimum valid operating voltage specification. This
occurs at time TB. The difference TB – TA is the total
time for shutdown.
TYPICAL LOW-VOLTAGE DETECT APPLICATION
Voltage
FIGURE 22-1:
The Low-Voltage Detect circuitry is completely under
software control. This allows the circuitry to be “turned
off” by the software, which minimizes the current
consumption for the device.
VA
VB
Legend:
VA = LVD trip point
VB = Minimum valid device
operating voltage
Time
TA
TB
The block diagram for the LVD module is shown in
Figure 22-2. A comparator uses an internally generated reference voltage as the set point. When the
selected tap output of the device voltage crosses the
set point (is lower than), the LVDIF bit is set.
Each node in the resistor divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate
before the LVD module asserts an interrupt. When the
2003-2013 Microchip Technology Inc.
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array is equal to the 1.2V
internal reference voltage generated by the voltage reference module. The comparator then generates an
interrupt signal, setting the LVDIF bit. This voltage is
software programmable to any one of 16 values (see
Figure 22-2). The trip point is selected by programming
the LVDL3:LVDL0 bits (LVDCON).
DS39609C-page 233
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FIGURE 22-2:
LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM
LVDIN
LVD3:LVD0
LVDCON
Register
16 to 1 MUX
VDD
Internally Generated
Reference Voltage
(Parameter #D423)
LVDEN
The LVD module has an additional feature that allows
the user to supply the trip voltage to the module from
an external source. This mode is enabled when bits
LVDL3:LVDL0 are set to ‘1111’. In this state, the comparator input is multiplexed from the external input pin,
FIGURE 22-3:
LVDIF
LVDIN (Figure 22-3). This gives users flexibility
because it allows them to configure the Low-Voltage
Detect interrupt to occur at any voltage in the valid
operating range.
LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD
VDD
LVDCON
Register
16 to 1 MUX
LVD3:LVD0
LVDIN
Externally Generated
Trip Point
LVDEN
LVD
VxEN
BODEN
EN
BGAP
DS39609C-page 234
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22.1
Control Register
The Low-Voltage Detect Control register controls the
operation of the Low-Voltage Detect circuitry.
REGISTER 22-1:
LVDCON REGISTER
U-0
U-0
R-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
—
—
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5
IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified
voltage range
0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
bit 4
LVDEN: Low-Voltage Detect Power Enable bit
1 = Enables LVD, powers up LVD circuit
0 = Disables LVD, powers down LVD circuit
bit 3-0
LVDL3:LVDL0: Low-Voltage Detection Limit bits(2)
1111 = External analog input is used (input comes from the LVDIN pin)
1110 = 4.64V
1101 = 4.33V
1100 = 4.13V
1011 = 3.92V
1010 = 3.72V
1001 = 3.61V
1000 = 3.41V
0111 = 3.1V
0110 = 2.89V
0101 = 2.78V
0100 = 2.58V
0011 = 2.47V
0010 = 2.27V
0001 = 2.06V
0000 = Reserved
Note 1: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage
of the device are not tested.
2: Typical values shown, see parameter D420 in Table 26-3 for more information.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2003-2013 Microchip Technology Inc.
x = Bit is unknown
DS39609C-page 235
PIC18F6520/8520/6620/8620/6720/8720
22.2
Operation
The following steps are needed to set up the LVD
module:
Depending on the power source for the device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for
short periods, where the voltage is checked. After
doing the check, the LVD module may be disabled.
1.
2.
3.
Each time that the LVD module is enabled, the circuitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
4.
5.
6.
Write the value to the LVDL3:LVDL0 bits
(LVDCON register), which selects the desired
LVD trip point.
Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
Enable the LVD module (set the LVDEN bit in
the LVDCON register).
Wait for the LVD module to stabilize (the IRVST
bit to become set).
Clear the LVD interrupt flag, which may have
falsely become set, until the LVD module has
stabilized (clear the LVDIF bit).
Enable the LVD interrupt (set the LVDIE and the
GIE bits).
Figure 22-4 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 22-4:
LOW-VOLTAGE DETECT WAVEFORMS
CASE 1:
LVDIF may not be set
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
TIVRST
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
TIVRST
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since LVD condition still exists
DS39609C-page 236
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22.2.1
REFERENCE VOLTAGE SET POINT
The internal reference voltage of the LVD module,
specified in electrical specification parameter #D423,
may be used by other internal circuitry (the
Programmable Brown-out Reset). If these circuits are
disabled (lower current consumption), the reference
voltage circuit requires a time to become stable before a
low-voltage condition can be reliably detected. This time
is invariant of system clock speed. This start-up time is
specified in electrical specification parameter #36. The
low-voltage interrupt flag will not be enabled until a stable
reference voltage is reached. Refer to the waveform in
Figure 22-4.
22.2.2
22.3
Operation During Sleep
When enabled, the LVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wakeup from Sleep. Device execution will continue from the
interrupt vector address if interrupts have been globally
enabled.
22.4
Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the LVD module to be turned off.
CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
2003-2013 Microchip Technology Inc.
DS39609C-page 237
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NOTES:
DS39609C-page 238
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23.0
SPECIAL FEATURES OF THE
CPU
There are several features intended to maximize system reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection. These are:
• Oscillator Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming
All PIC18FXX20 devices have a Watchdog Timer,
which is permanently enabled via the configuration bits,
or software controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer
necessary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
Reset until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT), which provides a fixed
delay on power-up only, designed to keep the part in
Reset while the power supply stabilizes. With these two
timers on-chip, most applications need no external
Reset circuitry.
23.1
Configuration Bits
The configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped,
starting at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h through
3FFFFFh), which can only be accessed using table
reads and table writes.
Programming the configuration registers is done in a
manner similar to programming the Flash memory. The
EECON1 register WR bit starts a self-timed write to the
configuration register. In normal operation mode, a
TBLWT instruction with the TBLPTR pointed to the
configuration register sets up the address and the data
for the configuration register write. Setting the WR bit
starts a long write to the configuration register. The
configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell.
Sleep mode is designed to offer a very low current
power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer Wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of configuration
bits is used to select various options.
2003-2013 Microchip Technology Inc.
DS39609C-page 239
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TABLE 23-1:
CONFIGURATION BITS AND DEVICE IDS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
300001h
CONFIG1H
—
—
OSCSEN
—
—
FOSC2
FOSC1
FOSC0
--1- -111
300002h
CONFIG2L
—
—
—
—
BORV1
BORV0
BODEN
PWRTEN
---- 1111
300003h
CONFIG2H
—
—
—
—
WDTPS2
WDTPS1
WDTPS0
WDTEN
---- 1111
WAIT
—
—
—
—
—
PM1
PM0
1--- --11
300004h(1) CONFIG3L
—
—
—
—
—
r(3)
CCP2MX
---- --11
—
—
—
—
LVP
—
STVREN
1--- -1-1
CP7(2)
CP6(2)
CP5(2)
CP4(2)
CP3
CP2
CP1
CP0
1111 1111
CPD
CPB
—
—
—
—
—
—
11-- ----
WRT5(2)
WRT4(2)
WRT3
WRT2
WRT1
WRT0
1111 1111
WRTB
WRTC
—
—
—
—
—
111- ----
CONFIG7L
EBTR7(2)
EBTR6(2)
EBTR5(2)
EBTR4(2)
EBTR3
EBTR2
EBTR1
EBTR0
1111 1111
CONFIG7H
—
EBTRB
—
—
—
—
—
—
-1-- ----
DEVID1
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
(4)
3FFFFFh
DEVID2
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
0000 0110
Legend:
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition, r = reserved.
Shaded cells are unimplemented, read as ‘0’.
Unimplemented in PIC18F6X20 devices; maintain this bit set.
Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set.
Unimplemented in PIC18FX620 and PIC18FX720 devices; maintain this bit set.
See Register 23-13 for DEVID1 values.
300005h
CONFIG3H
300006h
CONFIG4L DEBUG
300008h
CONFIG5L
300009h
CONFIG5H
30000Ah
CONFIG6L WRT7(2) WRT6(2)
30000Bh
CONFIG6H
WRTD
30000Ch
30000Dh
3FFFFEh
Note 1:
2:
3:
4:
REGISTER 23-1:
—
CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
U-0
U-0
R/P-1
U-0
U-0
R/P-1
R/P-1
R/P-1
—
—
OSCSEN
—
—
FOSC2
FOSC1
FOSC0
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5
OSCSEN: Oscillator System Clock Switch Enable bit
1 = Oscillator system clock switch option is disabled (main oscillator is source)
0 = Timer1 Oscillator system clock switch option is enabled (oscillator switching is enabled)
bit 4-3
Unimplemented: Read as ‘0’
bit 2-0
FOSC2:FOSC0: Oscillator Selection bits
111 = RC oscillator w/ OSC2 configured as RA6
110 = HS oscillator with PLL enabled; clock frequency = (4 x FOSC)
101 = EC oscillator w/ OSC2 configured as RA6
100 = EC oscillator w/ OSC2 configured as divide-by-4 clock output
011 = RC oscillator w/ OSC2 configured as divide-by-4 clock output
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
DS39609C-page 240
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
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REGISTER 23-2:
CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
—
—
—
—
BORV1
BORV0
BOREN
PWRTEN
bit 7
bit 0
bit 7-4
Unimplemented: Read as ‘0’
bit 3-2
BORV1:BORV0: Brown-out Reset Voltage bits
11 = VBOR set to 2.5V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR set to 4.5V
bit 1
BOREN: Brown-out Reset Enable bit
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
bit 0
PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
REGISTER 23-3:
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
—
—
—
—
WDTPS2
WDTPS1
WDTPS0
WDTEN
bit 7
bit 0
bit 7-4
Unimplemented: Read as ‘0’
bit 3-1
WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
bit 0
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
2003-2013 Microchip Technology Inc.
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
DS39609C-page 241
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 23-4:
CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1)
R/P-1
U-0
U-0
U-0
U-0
U-0
R/P-1
R/P-1
WAIT
—
—
—
—
—
PM1
PM0
bit 7
bit 0
bit 7
WAIT: External Bus Data Wait Enable bit
1 = Wait selections unavailable for table reads and table writes
0 = Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits
(MEMCOM)
bit 6-2
Unimplemented: Read as ‘0’
bit 1-0
PM1:PM0: Processor Mode Select bits
11 = Microcontroller mode
10 = Microprocessor mode
01 = Microprocessor with Boot Block mode
00 = Extended Microcontroller mode
Note 1: This register is unimplemented in PIC18F6X20 devices; maintain these bits set.
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
REGISTER 23-5:
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
R/P-1
R/P-1
—
r(1)
CCP2MX
bit 7
bit 0
bit 7-2
Unimplemented: Read as ‘0’
bit 1
Reserved: Read as unknown(1)
bit 0
CCP2MX: CCP2 Mux bit
In Microcontroller mode:
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RE7
In Microprocessor, Microprocessor with Boot Block and Extended Microcontroller modes
(PIC18F8X20 devices only):
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
Note 1: Unimplemented in PIC18FX620 and PIC18FX720 devices; read as ‘0’.
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
DS39609C-page 242
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
2003-2013 Microchip Technology Inc.
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REGISTER 23-6:
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1
U-0
U-0
U-0
U-0
R/P-1
U-0
R/P-1
DEBUG
—
—
—
—
LVP
—
STVREN
bit 7
bit 0
bit 7
DEBUG: Background Debugger Enable bit
1 = Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins.
0 = Background debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.
bit 6-3
Unimplemented: Read as ‘0’
bit 2
LVP: Low-Voltage ICSP Enable bit
1 = Low-voltage ICSP enabled
0 = Low-voltage ICSP disabled
bit 1
Unimplemented: Read as ‘0’
bit 0
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
2003-2013 Microchip Technology Inc.
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
DS39609C-page 243
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 23-7:
CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
CP7(1)
CP6(1)
CP5(1)
CP4(1)
CP3
CP2
CP1
CP0
bit 7
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
CP7: Code Protection bit(1)
1 = Block 7 (01C000-01FFFFh) not code-protected
0 = Block 7 (01C000-01FFFFh) code-protected
CP6: Code Protection bit(1)
1 = Block 6 (018000-01BFFFh) not code-protected
0 = Block 6 (018000-01BFFFh) code-protected
CP5: Code Protection bit(1)
1 = Block 5 (014000-017FFFh) not code-protected
0 = Block 5 (014000-017FFFh) code-protected
CP4: Code Protection bit(1)
1 = Block 4 (010000-013FFFh) not code-protected
0 = Block 4 (010000-013FFFh) code-protected
CP3: Code Protection bit
For PIC18FX520 devices:
1 = Block 3 (006000-007FFFh) not code-protected
0 = Block 3 (006000-007FFFh) code-protected
For PIC18FX620 and PIC18FX720 devices:
1 = Block 3 (00C000-00FFFFh) not code-protected
0 = Block 3 (00C000-00FFFFh) code-protected
CP2: Code Protection bit
For PIC18FX520 devices:
1 = Block 2 (004000-005FFFh) not code-protected
0 = Block 2 (004000-005FFFh) code-protected
For PIC18FX620 and PIC18FX720 devices:
1 = Block 2 (008000-00BFFFh) not code-protected
0 = Block 2 (008000-00BFFFh) code-protected
CP1: Code Protection bit
For PIC18FX520 devices:
1 = Block 1 (002000-003FFFh) not code-protected
0 = Block 1 (002000-003FFFh) code-protected
For PIC18FX620 and PIC18FX720 devices:
1 = Block 1 (004000-007FFFh) not code-protected
0 = Block 1 (004000-007FFFh) code-protected
CP0: Code Protection bit
For PIC18FX520 devices:
1 = Block 0 (000800-001FFFh) not code-protected
0 = Block 0 (000800-001FFFh) code-protected
For PIC18FX620 and PIC18FX720 devices:
1 = Block 0 (000200-003FFFh) not code-protected
0 = Block 0 (000200-003FFFh) code-protected
Note 1: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set.
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
DS39609C-page 244
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 23-8:
CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
R/C-1
CPD
bit 7
bit 7
bit 6
bit 5-0
R/C-1
CPB
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 0
CPD: Data EEPROM Code Protection bit
1 = Data EEPROM not code-protected
0 = Data EEPROM code-protected
CPB: Boot Block Code Protection bit
For PIC18FX520 devices:
1 = Boot Block (000000-0007FFh) not code-protected
0 = Boot Block (000000-0007FFh) code-protected
For PIC18FX620 and PIC18FX720 devices:
1 = Boot Block (000000-0001FFh) not code-protected
0 = Boot Block (000000-0001FFh) code-protected
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
C = Clearable bit
- n = Value when device is unprogrammed
2003-2013 Microchip Technology Inc.
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
DS39609C-page 245
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 23-9:
CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WRT7(1)
WRT6(1)
WRT5(1)
WRT4(1)
WRT3
WRT2
WRT1
WRT0
bit 7
bit 0
bit 7
WR7: Write Protection bit(1)
1 = Block 7 (01C000-01FFFFh) not write-protected
0 = Block 7 (01C000-01FFFFh) write-protected
bit 6
WR6: Write Protection bit(1)
1 = Block 6 (018000-01BFFFh) not write-protected
0 = Block 6 (018000-01BFFFh) write-protected
bit 5
WR5: Write Protection bit(1)
1 = Block 5 (014000-017FFFh) not write-protected
0 = Block 5 (014000-017FFFh) write-protected
bit 4
WR4: Write Protection bit(1)
1 = Block 4 (010000-013FFFh) not write-protected
0 = Block 4 (010000-013FFFh) write-protected
bit 3
WR3: Write Protection bit
For PIC18FX520 devices:
1 = Block 3 (006000-007FFFh) not write-protected
0 = Block 3 (006000-007FFFh) write-protected
For PIC18FX620 and PIC18FX720 devices:
1 = Block 3 (00C000-00FFFFh) not write-protected
0 = Block 3 (00C000-00FFFFh) write-protected
bit 2
WR2: Write Protection bit
For PIC18FX520 devices:
1 = Block 2 (004000-005FFFh) not write-protected
0 = Block 2 (004000-005FFFh) write-protected
For PIC18FX620 and PIC18FX720 devices:
1 = Block 2 (008000-00BFFFh) not write-protected
0 = Block 2 (008000-00BFFFh) write-protected
bit 1
WR1: Write Protection bit
For PIC18FX520 devices:
1 = Block 1 (002000-003FFFh) not write-protected
0 = Block 1 (002000-003FFFh) write-protected
For PIC18FX620 and PIC18FX720 devices:
1 = Block 1 (004000-007FFFh) not write-protected
0 = Block 1 (004000-007FFFh) write-protected
bit 0
WR0: Write Protection bit
For PIC18FX520 devices:
1 = Block 0 (000800-001FFFh) not write-protected
0 = Block 0 (000800-001FFFh) write-protected
For PIC18FX620 and PIC18FX720 devices:
1 = Block 0 (000200-003FFFh) not write-protected
0 = Block 0 (000200-003FFFh) write-protected
Note 1: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set.
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
DS39609C-page 246
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 23-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)
R/P-1
R/P-1
R-1
U-0
U-0
U-0
U-0
U-0
WRTD
WRTB
WRTC(1)
—
—
—
—
—
bit 7
bit 0
bit 7
WRTD: Data EEPROM Write Protection bit
1 = Data EEPROM not write-protected
0 = Data EEPROM write-protected
bit 6
WRTB: Boot Block Write Protection bit
For PIC18FX520 devices:
1 = Boot Block (000000-0007FFh) not write-protected
0 = Boot Block (000000-0007FFh) write-protected
For PIC18FX620 and PIC18FX720 devices:
1 = Boot Block (000000-0001FFh) not write-protected
0 = Boot Block (000000-0001FFh) write-protected
bit 5
WRTC: Configuration Register Write Protection bit(1)
1 = Configuration registers (300000-3000FFh) not write-protected
0 = Configuration registers (300000-3000FFh) write-protected
Note 1: This bit is read-only and cannot be changed in user mode.
bit 4-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
2003-2013 Microchip Technology Inc.
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
DS39609C-page 247
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 23-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
EBTR7(1)
EBTR6(1)
EBTR5(1)
EBTR4(1)
EBTR3
EBTR2
EBTR1
EBTR0
bit 7
bit 0
bit 7
EBTR7: Table Read Protection bit(1)
1 = Block 3 (01C000-01FFFFh) not protected from table reads executed in other blocks
0 = Block 3 (01C000-01FFFFh) protected from table reads executed in other blocks
bit 6
EBTR6: Table Read Protection bit(1)
1 = Block 2 (018000-01BFFFh) not protected from table reads executed in other blocks
0 = Block 2 (018000-01BFFFh) protected from table reads executed in other blocks
bit 5
EBTR5: Table Read Protection bit(1)
1 = Block 1 (014000-017FFFh) not protected from table reads executed in other blocks
0 = Block 1 (014000-017FFFh) protected from table reads executed in other blocks
bit 4
EBTR4: Table Read Protection bit(1)
1 = Block 0 (010000-013FFFh) not protected from table reads executed in other blocks
0 = Block 0 (010000-013FFFh) protected from table reads executed in other blocks
bit 3
EBTR3: Table Read Protection bit
For PIC18FX520 devices:
1 = Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
0 = Block 3 (006000-007FFFh) protected from table reads executed in other blocks
For PIC18FX620 and PIC18FX720 devices:
1 = Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
0 = Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
bit 2
EBTR2: Table Read Protection bit
For PIC18FX520 devices:
1 = Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
0 = Block 2 (004000-005FFFh) protected from table reads executed in other blocks
For PIC18FX620 and PIC18FX720 devices:
1 = Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
0 = Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
bit 1
EBTR1: Table Read Protection bit
For PIC18FX520 devices:
1 = Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
0 = Block 1 (002000-003FFFh) protected from table reads executed in other blocks
For PIC18FX620 and PIC18FX720 devices:
1 = Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
0 = Block 1 (004000-007FFFh) protected from table reads executed in other blocks
bit 0
EBTR0: Table Read Protection bit
For PIC18FX520 devices:
1 = Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
0 = Block 0 (000800-001FFFh) protected from table reads executed in other blocks
For PIC18FX620 and PIC18FX720 devices:
1 = Block 0 (000200-003FFFh) not protected from table reads executed in other blocks
0 = Block 0 (000200-003FFFh) protected from table reads executed in other blocks
Note 1: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set.
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
DS39609C-page 248
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
REGISTER 23-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0
R/P-1
U-0
U-0
U-0
U-0
U-0
U-0
—
EBTRB
—
—
—
—
—
—
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
EBTRB: Boot Block Table Read Protection bit
For PIC18FX520 devices:
1 = Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
0 = Boot Block (000000-0007FFh) protected from table reads executed in other blocks
For PIC18FX620 and PIC18FX720 devices:
1 = Boot Block (000000-0001FFh) not protected from table reads executed in other blocks
0 = Boot Block (000000-0001FFh) protected from table reads executed in other blocks
bit 5-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
REGISTER 23-13: DEVICE ID REGISTER 1 FOR PIC18FXX20 DEVICES (ADDRESS 3FFFFEh)
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
bit 7-5
DEV2:DEV0: Device ID bits
000 = PIC18F8720
001 = PIC18F6720
010 = PIC18F8620
011 = PIC18F6620
bit 4-0
REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
REGISTER 23-14: DEVICE ID REGISTER 2 FOR PIC18FXX20 DEVICES (ADDRESS 3FFFFFh)
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 7-0
bit 0
DEV10:DEV3: Device ID bits
These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part
number.
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
2003-2013 Microchip Technology Inc.
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
DS39609C-page 249
PIC18F6520/8520/6620/8620/6720/8720
23.2
Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator, which does not require any external components. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKI pin. That means that the
WDT will run, even if the clock on the OSC1/CLKI and
OSC2/CLKO/RA6 pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
The WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
Values for the WDT postscaler may be assigned using
the configuration bits.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT and prevent it from
timing out and generating a device Reset
condition.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog Timer wake-up). The TO bit in the RCON register
will be cleared upon a WDT time-out.
The Watchdog Timer is enabled/disabled by a device
configuration bit. If the WDT is enabled, software execution may not disable this function. When the WDTEN
configuration bit is cleared, the SWDTEN bit enables/
disables the operation of the WDT.
2: When a CLRWDT instruction is executed
and the postscaler is assigned to the
WDT, the postscaler count will be cleared,
but the postscaler assignment is not
changed.
23.2.1
CONTROL REGISTER
Register 23-15 shows the WDTCON register. This is a
readable and writable register, which contains a control
bit that allows software to override the WDT enable
configuration bit, only when the configuration bit has
disabled the WDT.
REGISTER 23-15: WDTCON REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
SWDTEN
bit 7
bit 0
bit 7-1
Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is turned off if the WDTEN configuration bit in the configuration register = 0
Legend:
DS39609C-page 250
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2003-2013 Microchip Technology Inc.
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23.2.2
WDT POSTSCALER
The WDT has a postscaler that can extend the WDT
Reset period. The postscaler is selected at the time of
the device programming by the value written to the
CONFIG2H Configuration register.
FIGURE 23-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDT Timer
Postscaler
8
WDTPS2:WDTPS0
8-to-1 MUX
WDTEN
Configuration bit
SWDTEN bit
WDT
Time-out
Note:
TABLE 23-2:
Name
CONFIG2H
RCON
WDTCON
WDPS2:WDPS0 are bits in register CONFIG2H.
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
—
WDTPS2
WDTPS2
WDTPS0
WDTEN
IPEN
—
—
RI
TO
PD
POR
BOR
—
—
—
—
—
—
—
SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
2003-2013 Microchip Technology Inc.
DS39609C-page 251
PIC18F6520/8520/6620/8620/6720/8720
23.3
Power-down Mode (Sleep)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared, but
keeps running, the PD bit (RCON) is cleared, the
TO (RCON) bit is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or high-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are high-impedance inputs, high or low externally,
to avoid switching currents caused by floating inputs.
The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
23.3.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
External Reset input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change or a
peripheral interrupt.
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
PSP read or write.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
3. TMR3 interrupt. Timer3 must be operating as an
asynchronous counter.
4. CCP Capture mode interrupt.
5. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
6. MSSP (Start/Stop) bit detect interrupt.
7. MSSP transmit or receive in Slave mode
(SPI/I2C).
8. USART RX or TX (Synchronous Slave mode).
9. A/D conversion (when A/D clock source is RC).
10. EEPROM write operation complete.
11. LVD interrupt.
External MCLR Reset will cause a device Reset. All
other events are considered a continuation of program
execution and will cause a “wake-up”. The TO and PD
bits in the RCON register can be used to determine the
cause of the device Reset. The PD bit, which is set on
power-up, is cleared when Sleep is invoked. The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 2) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
23.3.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If an interrupt condition (interrupt flag bit and
interrupt enable bits are set) occurs before the
execution of a SLEEP instruction, the SLEEP
instruction will complete as a NOP. Therefore, the
WDT and WDT postscaler will not be cleared, the
TO bit will not be set and PD bits will not be
cleared.
• If the interrupt condition occurs during or after
the execution of a SLEEP instruction, the device
will immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction.
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
DS39609C-page 252
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
FIGURE 23-2:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKO(4)
INT pin
INTF flag
(INTCON)
Interrupt Latency(3)
GIEH bit
(INTCON)
Processor in
Sleep
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note
23.4
1:
2:
3:
4:
PC
PC+2
Inst(PC) = Sleep
Inst(PC + 2)
Inst(PC - 1)
PC+4
PC + 4
PC+4
0008h
000Ah
Inst(0008h)
Inst(000Ah)
Dummy Cycle
Inst(0008h)
Inst(PC + 4)
Inst(PC + 2)
Sleep
Dummy Cycle
XT, HS or LP Oscillator mode assumed.
GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Oscillator modes.
CLKO is not available in these oscillator modes, but shown here for timing reference.
Program Verification and
Code Protection
In the PIC18FXX20 family, the block size varies with
the size of the user program memory. For PIC18FX520
devices, program memory is divided into four blocks of
8 Kbytes each. The first block is further divided into a
boot block of 2 Kbytes and a second block (Block 0) of
6 Kbytes, for a total of five blocks. The organization of
the blocks and their associated code protection bits are
shown in Figure 23-3.
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC® devices. The user program memory is divided on
binary boundaries into individual blocks, each of which
has three separate code protection bits associated with
it:
For PIC18FX620 and PIC18FX720 devices, program
memory is divided into blocks of 16 Kbytes. The first
block is further divided into a boot block of 512 bytes
and a second block (Block 0) of 15.5 Kbytes, for a total
of nine blocks. This produces five blocks for 64-Kbyte
devices and nine for 128-Kbyte devices. The organization of the blocks and their associated code protection
bits are shown in Figure 23-4.
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
The code protection bits are located in Configuration
Registers 5L through 7H. Their locations within the
registers are summarized in Table 23-3.
TABLE 23-3:
SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
300008h
CONFIG5L
CP7(1)
300009h
CONFIG5H
CPD
(1)
Bit 6
CP6
(1)
Bit 5
CP5
(1)
Bit 4
CP4
(1)
Bit 3
Bit 2
Bit 1
Bit 0
CP3
CP2
CP1
CP0
CPB
—
—
—
—
—
—
WRT6(1)
WRT5(1)
WRT4(1)
30000Ah
CONFIG6L
WRT3
WRT2
WRT1
WRT0
30000Bh
CONFIG6H
WRTD
WRTB
WRTC
—
—
—
—
—
30000Ch
CONFIG7L
EBTR7(1)
EBTR6(1)
EBTR5(1)
EBTR4(1)
EBTR3
EBTR2
EBTR1
EBTR0
30000Dh
CONFIG7H
—
EBTRB
—
—
—
—
—
—
WRT7
Legend: Shaded cells are unimplemented.
Note 1: Unimplemented in PIC18FX520 and PIC18FX620 devices.
2003-2013 Microchip Technology Inc.
DS39609C-page 253
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 23-3:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18FX520 DEVICES
Address
Range
32 Kbytes
Block Code Protection
Controlled By:
Boot Block
000000h
0007FFh
CPB, WRTB, EBTRB
Block 0
000800h
001FFFh
CP0, WRT0, EBTR0
002000h
Block 1
CP1, WRT1, EBTR1
003FFFh
004000h
Block 2
CP2, WRT2, EBTR2
005FFFh
006000h
Block 3
CP3, WRT3, EBTR3
007FFFh
008000h
Unimplemented
Read ‘0’s
1FFFFFh
FIGURE 23-4:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18FX620/X720 DEVICES
MEMORY SIZE/DEVICE
Address
Range
Block Code Protection
Controlled By:
64 Kbytes
(PIC18FX620)
128 Kbytes
(PIC18FX720)
Boot Block
Boot Block
000000h
0001FFh
CPB, WRTB, EBTRB
Block 0
Block 0
000200h
003FFFh
CP0, WRT0, EBTR0
Block 1
Block 1
004000h
CP1, WRT1, EBTR1
007FFFh
008000h
Block 2
Block 2
CP2, WRT2, EBTR2
00BFFFh
00C000h
Block 3
Block 3
CP3, WRT3, EBTR3
00FFFFh
010000h
Block 4
CP4, WRT4, EBTR4
013FFFh
014000h
Block 5
CP5, WRT5, EBTR5
017FFFh
Unimplemented
Read ‘0’s
018000h
Block 6
CP6, WRT6, EBTR6
01BFFFh
01C000h
Block 7
CP7, WRT7, EBTR7
01FFFFh
DS39609C-page 254
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23.4.1
PROGRAM MEMORY
CODE PROTECTION
The user memory may be read to, or written from, any
location using the table read and table write instructions. The device ID may be read with table reads. The
configuration registers may be read and written with the
table read and table write instructions.
side of that block is not allowed to read and will result
in reading ‘0’s. Figures 23-5 through 23-7 illustrate
table write and table read protection using devices with
a 16-Kbyte block size as the models. The principles
illustrated are identical for devices with an 8-Kbyte
block size.
Note:
In user mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from table writes if the
WRTn configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the
EBTRn bit set to ‘0’, a table read instruction that
executes from within that block is allowed to read. A
table read instruction that executes from a location out-
FIGURE 23-5:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code protection bits are only set to ‘1’ by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.
TABLE WRITE (WRTn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0001FFh
000200h
TBLPTR = 000FFFh
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
PC = 003FFEh
TBLWT *
003FFFh
004000h
WRT1, EBTR1 = 11
007FFFh
008000h
PC = 008FFEh
WRT2, EBTR2 = 11
TBLWT *
00BFFFh
00C000h
WRT3, EBTR3 = 11
00FFFFh
Results: All table writes disabled to Block n whenever WRTn = 0.
2003-2013 Microchip Technology Inc.
DS39609C-page 255
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FIGURE 23-6:
EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0001FFh
000200h
TBLPTR = 000FFFh
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
003FFFh
004000h
PC = 004FFEh
TBLRD *
WRT1, EBTR1 = 11
007FFFh
008000h
WRT2, EBTR2 = 11
00BFFFh
00C000h
WRT3, EBTR3 = 11
00FFFFh
Results: All table reads from external blocks to Block n are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
FIGURE 23-7:
EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0001FFh
000200h
TBLPTR = 000FFFh
PC = 003FFEh
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
TBLRD *
003FFFh
004000h
WRT1, EBTR1 = 11
007FFFh
008000h
WRT2, EBTR2 = 11
00BFFFh
00C000h
WRT3, EBTR3 = 11
00FFFFh
Results: Table reads permitted within Block n, even when EBTRBn = 0.
TABLAT register returns the value of the data at the location TBLPTR.
DS39609C-page 256
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23.4.2
DATA EEPROM
CODE PROTECTION
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits external writes to data EEPROM. The
CPU can continue to read and write data EEPROM,
regardless of the protection bit settings.
23.4.3
CONFIGURATION REGISTER
PROTECTION
The configuration registers can be write-protected. The
WRTC bit controls protection of the configuration registers. In user mode, the WRTC bit is readable only.
WRTC can only be written via ICSP or an external
programmer.
23.5
ID Locations
Eight memory locations (200000h-200007h) are
designated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are accessible during normal execution
through the TBLRD and TBLWT instructions or during
program/verify. The ID locations can be read when the
device is code-protected.
23.6
In-Circuit Serial Programming
PIC18FX520/X620/X720 microcontrollers can be serially programmed while in the end application circuit.
This is simply done with two lines for clock and data
and three other lines for power, ground and the
programming voltage. This allows customers to manufacture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
Note:
23.7
When
performing
In-Circuit
Serial
Programming, verify that power is connected to all VDD and AVDD pins of the
microcontroller and that all VSS and AVSS
pins are grounded.
In-Circuit Debugger
When the DEBUG bit in the CONFIG4L Configuration
register is programmed to a ‘0’, the In-Circuit Debugger
functionality is enabled. This function allows simple
debugging functions when used with MPLAB® IDE.
When the microcontroller has this feature enabled,
some of the resources are not available for general
use. Table 23-4 shows which features are consumed
by the background debugger.
2003-2013 Microchip Technology Inc.
TABLE 23-4:
DEBUGGER RESOURCES
I/O pins
Stack
Program Memory
Data Memory
RB6, RB7
2 levels
Last 576 bytes
Last 10 bytes
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
23.8
Low-Voltage ICSP Programming
The LVP bit in the CONFIG4L Configuration register
enables Low-Voltage ICSP Programming. This mode
allows the microcontroller to be programmed via ICSP
using a VDD source in the operating voltage range. This
only means that VPP does not have to be brought to
VIHH, but can instead be left at the normal operating
voltage. In this mode, the RB5/PGM pin is dedicated to
the programming function and ceases to be a general
purpose I/O pin. During programming, VDD is applied to
the MCLR/VPP pin. To enter Programming mode, VDD
must be applied to the RB5/PGM pin, provided the LVP
bit is set. The LVP bit defaults to a ‘1’ from the factory.
Note 1: The High-Voltage Programming mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR pin.
2: While in Low-Voltage ICSP mode, the
RB5 pin can no longer be used as a
general purpose I/O pin and should be
held low during normal operation.
3: When using Low-Voltage ICSP Programming (LVP) and the pull-ups on PORTB are
enabled, bit 5 in the TRISB register must be
cleared to disable the pull-up on RB5 and
ensure the proper operation of the device.
If Low-Voltage Programming mode is not used, the LVP
bit can be programmed to a ‘0’ and RB5/PGM becomes
a digital I/O pin. However, the LVP bit may only be
programmed when programming is entered with VIHH
on MCLR/VPP.
It should be noted that once the LVP bit is programmed
to ‘0’, only the High-Voltage Programming mode is
available and only High-Voltage Programming mode
can be used to program the device.
When using Low-Voltage ICSP Programming, the part
must be supplied 4.5V to 5.5V if a bulk erase will be
executed. This includes reprogramming of the codeprotect bits from an on state to an off state. For all other
cases of Low-Voltage ICSP, the part may be
programmed at the normal operating voltage. This
means unique user IDs or user code can be
reprogrammed or added.
DS39609C-page 257
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NOTES:
DS39609C-page 258
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24.0
INSTRUCTION SET SUMMARY
The PIC18 instruction set adds many enhancements to
the previous PIC MCU instruction sets, while maintaining an easy migration from these PIC MCU instruction
sets.
Most instructions are a single program memory word
(16 bits), but there are three instructions that require
two program memory locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
•
•
•
•
Byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
The PIC18 instruction set summary in Table 24-1 lists
byte-oriented, bit-oriented, literal and control
operations. Table 24-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.
The file register (specified by ‘f’)
The destination of the result
(specified by ‘d’)
The accessed memory
(specified by ‘a’)
The file register designator ‘f’ specifies which file
register is to be used by the instruction.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If ‘d’ is zero, the
result is placed in the WREG register. If ‘d’ is one, the
result is placed in the file register specified in the
instruction.
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
The control instructions may use some of the following
operands:
• A program memory address (specified by ‘n’)
• The mode of the CALL or RETURN instructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required
(specified by ‘—’)
All instructions are a single word, except for three
double-word instructions. These three instructions
were made double-word instructions so that all the
required information is available in these 32 bits. In the
second word, the 4 MSbs are ‘1’s. If this second word
is executed as an instruction (by itself), it will execute
as a NOP.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruction. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
All bit-oriented instructions have three operands:
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two-word branch instructions (if true) would take 3 s.
1.
2.
Figure 24-1 shows the general formats that the
instructions can have.
3.
The file register (specified by ‘f’)
The bit in the file register
(specified by ‘b’)
The accessed memory
(specified by ‘a’)
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register designator ‘f’ represents the number of the file in which the
bit is located.
2003-2013 Microchip Technology Inc.
All examples use the format ‘nnh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal
digit.
The Instruction Set Summary, shown in Table 24-1,
lists the instructions recognized by the Microchip
Assembler (MPASMTM).
Section 24.1 “Instruction Set” provides a description
of each instruction.
DS39609C-page 259
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TABLE 24-1:
OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
Bit address within an 8-bit file register (0 to 7).
BSR
Bank Select Register. Used to select the current RAM bank.
d
Destination select bit
d = 0: store result in WREG
d = 1: store result in file register f
dest
Destination either the WREG register or the specified register file location.
f
8-bit Register file address (0x00 to 0xFF).
fs
12-bit Register file address (0x000 to 0xFFF). This is the source address.
fd
12-bit Register file address (0x000 to 0xFFF). This is the destination address.
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label
Label name.
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
No Change to register (such as TBLPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
*
*+
*+*
n
The relative address (2’s complement number) for relative branch instructions, or the direct address for Call/
Branch and Return instructions.
PRODH
Product of Multiply High Byte.
PRODL
Product of Multiply Low Byte.
s
Fast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
u
Unused or Unchanged.
WREG
Working register (accumulator).
x
Don’t care (‘0’ or ‘1’).
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.
TBLPTR
21-bit Table Pointer (points to a Program Memory location).
TABLAT
8-bit Table Latch.
TOS
Top-of-Stack.
PC
Program Counter.
PCL
Program Counter Low Byte.
PCH
Program Counter High Byte.
PCLATH
Program Counter High Byte Latch.
PCLATU
Program Counter Upper Byte Latch.
GIE
Global Interrupt Enable bit.
WDT
Watchdog Timer.
TO
Time-out bit.
PD
Power-down bit.
C, DC, Z, OV, N
ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
[
]
Optional.
(
)
Contents.
Assigned to.
< >
Register bit field.
In the set of.
italics
User defined term (font is courier).
DS39609C-page 260
2003-2013 Microchip Technology Inc.
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FIGURE 24-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15
10
9 8 7
OPCODE d
a
Example Instruction
0
f (FILE #)
ADDWF MYREG, W, B
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
OPCODE
15
0
f (Source FILE #)
12 11
MOVFF MYREG1, MYREG2
0
f (Destination FILE #)
1111
f = 12-bit file register address
Bit-oriented file register operations
15
12 11
9 8 7
OPCODE b (BIT #) a
0
f (FILE #)
BSF MYREG, bit, B
b = 3-bit position of bit in file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
OPCODE
0
k (literal)
MOVLW 0x7F
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
OPCODE
15
0
n (literal)
12 11
GOTO Label
0
n (literal)
1111
n = 20-bit immediate value
15
8 7
OPCODE
15
S
0
CALL MYFUNC
n (literal)
12 11
0
n (literal)
S = Fast bit
15
11 10
OPCODE
15
OPCODE
2003-2013 Microchip Technology Inc.
0
BRA MYFUNC
n (literal)
8 7
n (literal)
0
BC MYFUNC
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TABLE 24-1:
PIC18FXXXX INSTRUCTION SET
Mnemonic,
Operands
16-Bit Instruction Word
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
fs, fd
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
SUBWF
SUBWFB
f, d, a
f, d, a
SWAPF
TSTFSZ
XORWF
f, d, a
f, a
f, d, a
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move fs (source) to 1st word
fd (destination) 2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
borrow
Subtract WREG from f
Subtract WREG from f with
borrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR WREG with f
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1
1
1
1
1
1
1
1
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
1
1
0101
0101
11da
10da
ffff
ffff
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N 1, 2
1
1 (2 or 3)
1
0011
0110
0001
10da
011a
10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
4
1, 2
1
1
1 (2 or 3)
1 (2 or 3)
1
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1, 2
1, 2
3, 4
3, 4
1, 2
None
None
C, DC, Z, OV, N 1, 2
C, Z, N
Z, N
1, 2
C, Z, N
Z, N
None
C, DC, Z, OV, N 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
f, b, a
f, b, a
f, b, a
f, d, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
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TABLE 24-1:
PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
n
n
n
n
n
n
n
n
n
n, s
CLRWDT
DAW
GOTO
—
—
n
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
RETLW
RETURN
SLEEP
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
s
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
No Operation
No Operation
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
k
s
—
Return with literal in WREG
Return from Subroutine
Go into Standby mode
1
1
1
1
2
1
2
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
2
2
1
0000
0000
0000
1100
0000
0000
kkkk
0001
0000
1
1
2
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
None
None
None
None
None
None
None
None
None
None
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
kkkk None
001s None
0011 TO, PD
4
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
2003-2013 Microchip Technology Inc.
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TABLE 24-1:
PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
to FSRx
1st word
Move literal to BSR
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with WREG
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
None
None
None
None
C, DC, Z, OV, N
Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD*
TBLRD*+
TBLRD*TBLRD+*
TBLWT*
TBLWT*+
TBLWT*TBLWT+*
Table Read
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2
2 (5)
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39609C-page 264
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PIC18F6520/8520/6620/8620/6720/8720
24.1
Instruction Set
ADDLW
ADD literal to W
Syntax:
[ label ] ADDLW
Operands:
0 k 255
Operation:
(W) + k W
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
Description:
1111
kkkk
kkkk
The contents of W are added to the
8-bit literal ‘k’ and the result is
placed in W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to W
ADDLW
0x15
Before Instruction
W
k
=
0x10
ADDWF
ADD W to f
Syntax:
[ label ] ADDWF
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(W) + (f) dest
Status Affected:
N, OV, C, DC, Z
Encoding:
0010
01da
f [,d [,a] f [,d [,a]
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected. If ‘a’ is ‘1’,
the BSR is used.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
=
0x25
Example:
ADDWF
REG, 0, 0
Before Instruction
W
REG
=
=
0x17
0xC2
After Instruction
W
REG
2003-2013 Microchip Technology Inc.
=
=
0xD9
0xC2
DS39609C-page 265
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ADDWFC
ADD W and Carry bit to f
ANDLW
AND literal with W
Syntax:
[ label ] ADDWFC
Syntax:
[ label ] ANDLW
Operands:
0 f 255
d [0,1]
a [0,1]
f [,d [,a]
Operation:
(W) + (f) + (C) dest
Status Affected:
N, OV, C, DC, Z
Encoding:
0010
Description:
1
Cycles:
1
0 k 255
Operation:
(W) .AND. k W
Status Affected:
N, Z
Encoding:
ffff
ffff
Add W, the Carry flag and data
memory location ‘f’. If ‘d’ is ‘0’, the
result is placed in W. If ‘d’ is ‘1’, the
result is placed in data memory
location ‘f’. If ‘a’ is ‘0’, the Access
Bank will be selected. If ‘a’ is ‘1’, the
BSR will not be overridden.
Words:
0000
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
ADDWFC
kkkk
kkkk
The contents of W are AND’ed with
the 8-bit literal ‘k’. The result is
placed in W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read literal
‘k’
Process
Data
Write to W
ANDLW
0x5F
Before Instruction
W
=
0xA3
After Instruction
W
Example:
1011
Description:
Example:
Q Cycle Activity:
Q1
Decode
00da
Operands:
k
=
0x03
REG, 0, 1
Before Instruction
Carry bit =
REG
=
W
=
1
0x02
0x4D
After Instruction
Carry bit =
REG
=
W
=
DS39609C-page 266
0
0x02
0x50
2003-2013 Microchip Technology Inc.
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ANDWF
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 f 255
d [0,1]
a [0,1]
f [,d [,a]
Operation:
(W) .AND. (f) dest
Status Affected:
N, Z
Encoding:
0001
ffff
ffff
Operands:
-128 n 127
Operation:
if Carry bit is ‘1’
(PC) + 2 + 2n PC
Status Affected:
None
1110
0010
nnnn
nnnn
Words:
1
1
Cycles:
1(2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
ANDWF
REG, 0, 0
Before Instruction
=
=
0x17
0xC2
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Decode
After Instruction
=
=
n
1
Cycles:
W
REG
[ label ] BC
If the Carry bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
W
REG
Syntax:
Description:
The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected. If ‘a’ is ‘1’, the BSR will
not be overridden (default).
Example:
Branch if Carry
Encoding:
01da
Description:
Decode
BC
Q2
Q3
Q4
Read literal
‘n’
Process
Data
No
operation
0x02
0xC2
Example:
HERE
BC
5
Before Instruction
PC
=
address (HERE)
=
=
=
=
1;
address (HERE+12)
0;
address (HERE+2)
After Instruction
If Carry
PC
If Carry
PC
2003-2013 Microchip Technology Inc.
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BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 f 255
0b7
a [0,1]
Operation:
0 f
Status Affected:
None
Encoding:
1001
Description:
Branch if Negative
Syntax:
[ label ] BN
Operands:
-128 n 127
Operation:
if Negative bit is ‘1’
(PC) + 2 + 2n PC
Status Affected:
None
Encoding:
bbba
ffff
ffff
1110
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
BCF
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
FLAG_REG,
n
0110
nnnn
nnnn
Description:
If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Bit ‘b’ in register ‘f’ is cleared. If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
Decode
f,b[,a]
BN
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
7, 0
If No Jump:
Q1
Decode
Q2
Q3
Q4
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BN
Jump
Before Instruction
PC
=
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE+2)
After Instruction
If Negative
PC
If Negative
PC
DS39609C-page 268
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
[ label ] BNC
Syntax:
[ label ] BNN
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if Carry bit is ‘0’
(PC) + 2 + 2n PC
Operation:
if Negative bit is ‘0’
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
n
0011
nnnn
nnnn
Encoding:
1110
n
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Description:
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Read literal
‘n’
Process
Data
No
operation
If No Jump:
Q1
Decode
Example:
HERE
BNC
Jump
Before Instruction
PC
Decode
Q2
Q3
Q4
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNN
Jump
Before Instruction
=
address (HERE)
After Instruction
If Carry
PC
If Carry
PC
If No Jump:
Q1
PC
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE+2)
After Instruction
=
=
=
=
0;
address (Jump)
1;
address (HERE+2)
2003-2013 Microchip Technology Inc.
If Negative
PC
If Negative
PC
DS39609C-page 269
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BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
[ label ] BNOV
Syntax:
[ label ] BNZ
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if Overflow bit is ‘0’
(PC) + 2 + 2n PC
Operation:
if Zero bit is ‘0’
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
n
0101
nnnn
nnnn
Encoding:
1110
n
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Description:
If the Zero bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Read literal
‘n’
Process
Data
No
operation
If No Jump:
Q1
Decode
Example:
HERE
BNOV Jump
Before Instruction
PC
DS39609C-page 270
Decode
Example:
Q2
Q3
Q4
Read literal
‘n’
Process
Data
No
operation
HERE
BNZ
Jump
Before Instruction
=
address (HERE)
After Instruction
If Overflow
PC
If Overflow
PC
If No Jump:
Q1
PC
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE+2)
After Instruction
=
=
=
=
0;
address (Jump)
1;
address (HERE+2)
If Zero
PC
If Zero
PC
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
[ label ] BRA
Syntax:
[ label ] BSF
Operands:
-1024 n 1023
Operands:
Operation:
(PC) + 2 + 2n PC
Status Affected:
None
0 f 255
0b7
a [0,1]
Operation:
1 f
Status Affected:
None
Encoding:
Description:
1101
1
Cycles:
2
Q Cycle Activity:
Q1
No
operation
0nnn
nnnn
nnnn
Add the 2’s complement number
‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a
two-cycle instruction.
Words:
Decode
n
Q2
Q3
Q4
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
Encoding:
HERE
BRA
Jump
PC
=
address (HERE)
=
address (Jump)
After Instruction
PC
2003-2013 Microchip Technology Inc.
ffff
ffff
Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’,
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as
per the BSR value.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
BSF
FLAG_REG, 7, 1
Before Instruction
FLAG_REG
Before Instruction
bbba
Description:
Example:
Example:
1000
f,b[,a]
=
0x0A
=
0x8A
After Instruction
FLAG_REG
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BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSC f,b[,a]
Syntax:
[ label ] BTFSS f,b[,a]
Operands:
0 f 255
0b7
a [0,1]
Operands:
0 f 255
0b (W)
(unsigned comparison)
Operation:
(f) –W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
None
Status Affected:
None
Encoding:
Description:
0110
010a
f [,a]
ffff
ffff
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If the contents of ‘f’ are greater than
the contents of WREG, then the
fetched instruction is discarded and
a NOP is executed instead, making
this a two-cycle instruction. If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
ffff
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If the contents of ‘f’ are less than
the contents of W, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’
is ‘1’, the BSR will not be
overridden (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
NGREATER
GREATER
CPFSGT REG, 0
:
:
Before Instruction
=
=
Address (HERE)
?
=
=
W;
Address (GREATER)
W;
Address (NGREATER)
After Instruction
2003-2013 Microchip Technology Inc.
ffff
No
operation
No
operation
If REG
PC
If REG
PC
000a
No
operation
No
operation
PC
W
0110
Description:
Decode
If skip:
Example:
Encoding:
f [,a]
Example:
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
Before Instruction
PC
W
=
=
Address (HERE)
?
<
=
=
W;
Address (LESS)
W;
Address (NLESS)
After Instruction
If REG
PC
If REG
PC
DS39609C-page 277
PIC18F6520/8520/6620/8620/6720/8720
DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
[ label ] DAW
Syntax:
[ label ] DECF f [,d [,a]
Operands:
None
Operands:
Operation:
If [W >9] or [DC = 1] then
(W) + 6 W;
else
(W) W;
0 f 255
d [0,1]
a [0,1]
Operation:
(f) – 1 dest
Status Affected:
C, DC, N, OV, Z
If [W >9] or [C = 1] then
(W) + 6 W;
else
(W) W;
Status Affected:
Encoding:
0000
0000
0000
1
Cycles:
1
Q Cycle Activity:
Q1
Q3
Q4
Process
Data
Write
W
Example1:
DAW
1
Cycles:
1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example:
DECF
CNT,
1, 0
Before Instruction
CNT
Z
=
=
0x01
0
After Instruction
Before Instruction
=
=
=
ffff
Words:
Decode
Q2
ffff
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in W. If ‘d’ is ‘1’,
the result is stored back in register
‘f’ (default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Q Cycle Activity:
Q1
Read
register W
01da
Description:
0111
DAW adjusts the eight-bit value in
W, resulting from the earlier
addition of two variables (each in
packed BCD format) and produces
a correct packed BCD result.
Words:
W
C
DC
0000
C
Description:
Decode
Encoding:
0xA5
0
0
CNT
Z
=
=
0x00
1
After Instruction
W
C
DC
=
=
=
0x05
1
0
Example 2:
Before Instruction
W
C
DC
=
=
=
0xCE
0
0
After Instruction
W
C
DC
=
=
=
DS39609C-page 278
0x34
1
0
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
DECFSZ
Decrement f, skip if 0
DCFSNZ
Decrement f, skip if not 0
Syntax:
[ label ] DECFSZ f [,d [,a]]
Syntax:
[ label ] DCFSNZ
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) – 1 dest,
skip if result = 0
Operation:
(f) – 1 dest,
skip if result 0
Status Affected:
None
Status Affected:
None
Encoding:
0010
11da
ffff
ffff
Encoding:
0100
11da
f [,d [,a]
ffff
ffff
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is not ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
1
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
If skip:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
If skip:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
DECFSZ
GOTO
CNT, 1, 1
LOOP
Example:
HERE
Example:
CONTINUE
Before Instruction
PC
=
=
=
=
=
DCFSNZ
:
:
TEMP, 1, 0
Before Instruction
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
HERE
ZERO
NZERO
TEMP
=
?
=
=
=
=
TEMP - 1,
0;
Address (ZERO)
0;
Address (NZERO)
After Instruction
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE+2)
2003-2013 Microchip Technology Inc.
TEMP
If TEMP
PC
If TEMP
PC
DS39609C-page 279
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GOTO
Unconditional Branch
INCF
Increment f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 1048575
Operands:
Operation:
k PC
Status Affected:
None
0 f 255
d [0,1]
a [0,1]
Operation:
(f) + 1 dest
Status Affected:
C, DC, N, OV, Z
Encoding:
1st word (k)
2nd word(k)
Description:
1110
1111
GOTO k
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
GOTO allows an unconditional
branch anywhere within the entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC.
GOTO is always a two-cycle
instruction.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
No
operation
Read literal
’k’,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example:
GOTO THERE
After Instruction
PC =
Address (THERE)
Encoding:
0010
INCF
f [,d [,a]
10da
ffff
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example:
INCF
CNT, 1, 0
Before Instruction
CNT
Z
C
DC
=
=
=
=
0xFF
0
?
?
After Instruction
CNT
Z
C
DC
DS39609C-page 280
=
=
=
=
0x00
1
1
1
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
INCFSZ
Increment f, skip if 0
INFSNZ
Increment f, skip if not 0
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) + 1 dest,
skip if result = 0
Operation:
(f) + 1 dest,
skip if result 0
Status Affected:
None
Status Affected:
None
Encoding:
0011
INCFSZ
11da
f [,d [,a]
ffff
ffff
Encoding:
0100
INFSNZ
10da
f [,d [,a]
ffff
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is not ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
1
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
If skip:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
If skip:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
Before Instruction
PC
=
=
=
=
=
Example:
HERE
ZERO
NZERO
INFSNZ
REG, 1, 0
Before Instruction
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
CNT, 1, 0
PC
=
Address (HERE)
After Instruction
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
2003-2013 Microchip Technology Inc.
REG
If REG
PC
If REG
PC
=
=
=
=
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
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IORLW
Inclusive OR literal with W
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(W) .OR. (f) dest
Status Affected:
N, Z
IORLW k
Operands:
0 k 255
Operation:
(W) .OR. k W
Status Affected:
N, Z
Encoding:
0000
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
kkkk
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to W
IORLW
Before Instruction
=
0x9A
After Instruction
W
kkkk
The contents of W are OR’ed with
the eight-bit literal ‘k’. The result is
placed in W.
Words:
W
1001
=
0x35
Encoding:
0001
IORWF
00da
f [,d [,a]
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If
‘d’ is ‘0’, the result is placed in W. If
‘d’ is ‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
0xBF
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example:
IORWF
RESULT, 0, 1
Before Instruction
RESULT =
W
=
0x13
0x91
After Instruction
RESULT =
W
=
DS39609C-page 282
0x13
0x93
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
LFSR
Load FSR
MOVF
Move f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0f2
0 k 4095
Operands:
Operation:
k FSRf
0 f 255
d [0,1]
a [0,1]
Status Affected:
None
Operation:
f dest
Status Affected:
N, Z
Encoding:
LFSR f,k
1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Description:
The 12-bit literal ‘k’ is loaded into
the File Select Register pointed
to by ‘f’.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’ MSB
Process
Data
Write literal
‘k’ MSB to
FSRfH
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example:
LFSR 2, 0x3AB
After Instruction
FSR2H
FSR2L
=
=
0x03
0xAB
Encoding:
MOVF
0101
f [,d [,a]
00da
ffff
ffff
Description:
The contents of register ‘f’ are
moved to a destination dependent
upon the status of ‘d’. If ‘d’ is ‘0’, the
result is placed in W. If ‘d’ is ‘1’, the
result is placed back in register ‘f’
(default). Location ‘f’ can be
anywhere in the 256-byte bank. If
‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write W
MOVF
REG, 0, 0
Before Instruction
REG
W
=
=
0x22
0xFF
=
=
0x22
0x22
After Instruction
REG
W
2003-2013 Microchip Technology Inc.
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MOVFF
Move f to f
MOVLB
Move literal to low nibble in BSR
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 fs 4095
0 fd 4095
Operands:
0 k 255
Operation:
k BSR
None
MOVFF fs,fd
Operation:
(fs) fd
Status Affected:
Status Affected:
None
Encoding:
Encoding:
1st word (source)
2nd word (destin.)
1100
1111
Description:
ffff
ffff
ffff
ffff
ffffs
ffffd
The contents of source register ‘fs’
are moved to destination register
‘fd’. Location of source ‘fs’ can be
anywhere in the 4096-byte data
space (000h to FFFh) and location
of destination ‘fd’ can also be
anywhere from 000h to FFFh.
Either source or destination can be
W (a useful special situation).
MOVFF is particularly useful for
transferring a data memory location
to a peripheral register (such as the
transmit buffer or an I/O port).
The MOVFF instruction cannot use
the PCL, TOSU, TOSH or TOSL as
the destination register.
Words:
2
Cycles:
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation,
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
MOVLB k
0000
0001
kkkk
kkkk
Description:
The 8-bit literal ‘k’ is loaded into
the Bank Select Register (BSR).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read literal
‘k’
Process
Data
Write
literal ‘k’ to
BSR
MOVLB
5
Before Instruction
BSR register
=
0x02
=
0x05
After Instruction
BSR register
REG1, REG2
Before Instruction
REG1
REG2
=
=
0x33
0x11
=
=
0x33,
0x33
After Instruction
REG1
REG2
DS39609C-page 284
2003-2013 Microchip Technology Inc.
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MOVLW
Move literal to W
MOVWF
Move W to f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
Operation:
kW
0 f 255
a [0,1]
Status Affected:
None
Operation:
(W) f
Status Affected:
None
Encoding:
0000
Description:
MOVLW k
1110
kkkk
The eight-bit literal ‘k’ is loaded into
W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to W
MOVLW
0x5A
After Instruction
W
kkkk
=
0x5A
Encoding:
0110
Description:
111a
f [,a]
ffff
ffff
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as
per the BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
MOVWF
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
MOVWF
REG, 0
Before Instruction
W
REG
=
=
0x4F
0xFF
After Instruction
W
REG
2003-2013 Microchip Technology Inc.
=
=
0x4F
0x4F
DS39609C-page 285
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MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 255
a [0,1]
Operation:
(W) x (f) PRODH:PRODL
Status Affected:
None
MULLW
k
Operands:
0 k 255
Operation:
(W) x k PRODH:PRODL
Status Affected:
None
Encoding:
Description:
0000
1
Cycles:
1
Q Cycle Activity:
Q1
Example:
kkkk
kkkk
An unsigned multiplication is
carried out between the contents
of W and the 8-bit literal ‘k’. The
16-bit result is placed in
PRODH:PRODL register pair.
PRODH contains the high byte.
W is unchanged.
None of the status flags are
affected.
Note that neither overflow nor
carry is possible in this
operation. A zero result is
possible but not detected.
Words:
Decode
1101
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
MULLW
0xC4
Before Instruction
W
PRODH
PRODL
=
=
=
0xE2
?
?
=
=
=
0xE2
0xAD
0x08
Encoding:
Description
0000
001a
1
Cycles:
1
Q Cycle Activity:
Q1
Example:
ffff
ffff
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
registers
PRODH:
PRODL
After Instruction
W
PRODH
PRODL
f [,a]
An unsigned multiplication is
carried out between the contents
of W and the register file location
‘f’. The 16-bit result is stored in
the PRODH:PRODL register
pair. PRODH contains the high
byte.
Both W and ‘f’ are unchanged.
None of the status flags are
affected.
Note that neither overflow nor
carry is possible in this
operation. A zero result is
possible but not detected. If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR
value. If ‘a’= 1, then the bank will
be selected as per the BSR
value (default).
Words:
Decode
MULWF
MULWF
REG, 1
Before Instruction
W
REG
PRODH
PRODL
=
=
=
=
0xC4
0xB5
?
?
=
=
=
=
0xC4
0xB5
0x8A
0x94
After Instruction
W
REG
PRODH
PRODL
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NEGF
Negate f
Syntax:
[ label ]
Operands:
0 f 255
a [0,1]
NEGF
Operation:
(f)+1f
Status Affected:
N, OV, C, DC, Z
Encoding:
0110
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Syntax:
[ label ]
NOP
Operands:
None
Operation:
No operation
Status Affected:
None
0000
1111
ffff
Description:
1
Cycles:
1
Decode
0000
xxxx
0000
xxxx
No operation.
Words:
Q Cycle Activity:
Q1
0000
xxxx
Q2
Q3
Q4
No
operation
No
operation
No
operation
Example:
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
No Operation
Encoding:
ffff
Location ‘f’ is negated using two’s
complement. The result is placed in
the data memory location ‘f’. If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value.
Words:
Decode
110a
f [,a]
NOP
NEGF
None.
REG, 1
Before Instruction
REG
=
0011 1010 [0x3A]
After Instruction
REG
=
1100 0110 [0xC6]
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POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
(TOS) bit bucket
Operation:
(PC+2) TOS
Status Affected:
None
Status Affected:
None
Encoding:
0000
Description:
0000
0000
0110
The TOS value is pulled off the
return stack and is discarded. The
TOS value then becomes the
previous value that was pushed
onto the return stack.
This instruction is provided to
enable the user to properly manage
the return stack to incorporate a
software stack.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
POP
Encoding:
Q2
Q3
Q4
POP TOS
value
No
operation
1
Cycles:
1
=
=
DS39609C-page 288
=
=
Q3
Q4
No
operation
No
operation
PUSH
TOS
PC
0031A2h
014332h
After Instruction
TOS
PC
Q2
PUSH PC+2
onto return
stack
Before Instruction
NEW
Before Instruction
TOS
Stack (1 level down)
0101
Words:
Example:
POP
GOTO
0000
The PC+2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows
implementing a software stack by
modifying TOS and then pushing it
onto the return stack.
Q Cycle Activity:
Q1
No
operation
0000
Description:
Decode
Example:
0000
PUSH
014332h
NEW
=
=
00345Ah
000124h
=
=
=
000126h
000126h
00345Ah
After Instruction
PC
TOS
Stack (1 level down)
2003-2013 Microchip Technology Inc.
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RCALL
Relative Call
RESET
Reset
Syntax:
[ label ] RCALL
Syntax:
[ label ]
Operands:
Operation:
-1024 n 1023
Operands:
None
(PC) + 2 TOS,
(PC) + 2 + 2n PC
Operation:
Reset all registers and flags that
are affected by a MCLR Reset.
Status Affected:
None
Status Affected:
All
Encoding:
Description:
1101
nnnn
nnnn
Subroutine call with a jump up to
1K from the current location. First,
return address (PC+2) is pushed
onto the stack. Then, add the 2’s
complement number ‘2n’ to the PC.
Since the PC will have incremented
to fetch the next instruction, the
new address will be PC+2+2n. This
instruction is a two-cycle
instruction.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
1nnn
n
Encoding:
0000
RESET
0000
1111
1111
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Start
Reset
No
operation
No
operation
RESET
After Instruction
Q2
Q3
Q4
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
Registers =
Flags*
=
Reset Value
Reset Value
Push PC to
stack
No
operation
Example:
No
operation
HERE
RCALL Jump
Before Instruction
PC =
Address (HERE)
After Instruction
PC =
TOS =
Address (Jump)
Address (HERE+2)
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RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
RETFIE [s]
RETLW k
Operands:
s [0,1]
Operands:
0 k 255
Operation:
(TOS) PC,
1 GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Operation:
k W,
(TOS) PC,
PCLATU, PCLATH are unchanged
Status Affected:
None
Status Affected:
0000
0000
0000
0001
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Pop PC
from stack,
Write to W
No
operation
No
operation
No
operation
No
operation
1
Example:
Cycles:
2
CALL TABLE ;
;
;
;
:
TABLE
ADDWF PCL ;
RETLW k0
;
RETLW k1
;
:
:
RETLW kn
;
Decode
Q2
Q3
Q4
No
operation
No
operation
Pop PC
from stack
Set GIEH or
GIEL
No
operation
Example:
No
operation
RETFIE
No
operation
No
operation
1
DS39609C-page 290
W contains table
offset value
W now has
table value
W = offset
Begin table
End of table
Before Instruction
After Interrupt
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL
kkkk
Words:
Words:
Q Cycle Activity:
Q1
kkkk
W is loaded with the eight-bit literal
‘k’. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
000s
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers, WS,
STATUSS and BSRS, are loaded
into their corresponding registers,
W, Status and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
1100
Description:
GIE/GIEH, PEIE/GIEL.
Encoding:
Description:
Encoding:
W
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
=
0x07
After Instruction
W
=
value of kn
2003-2013 Microchip Technology Inc.
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RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
RETURN [s]
RLCF
f [,d [,a]
Operands:
s [0,1]
Operands:
Operation:
(TOS) PC,
if s = 1
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
0 f 255
d [0,1]
a [0,1]
Operation:
(f) dest,
(f) C,
(C) dest
Status Affected:
C, N, Z
None
Encoding:
Status Affected:
Encoding:
0000
0000
0001
001s
Description:
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ‘s’ = 1, the contents of
the shadow registers, WS,
STATUSS and BSRS, are loaded
into their corresponding registers,
W, Status and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
No
operation
Q2
Q3
Q4
No
operation
Process
Data
Pop PC
from stack
No
operation
No
operation
No
operation
0011
Description:
ffff
register f
C
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
ffff
The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example:
Example:
01da
RLCF
REG, 0, 0
Before Instruction
RETURN
After Interrupt
PC = TOS
REG
C
1110 0110
0
After Instruction
REG
W
C
2003-2013 Microchip Technology Inc.
=
=
=
=
=
1110 0110
1100 1100
1
DS39609C-page 291
PIC18F6520/8520/6620/8620/6720/8720
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) dest,
(f) dest
Operation:
Status Affected:
N, Z
(f) dest,
(f) C,
(C) dest
Status Affected:
C, N, Z
Encoding:
0100
Description:
RLNCF
01da
f [,d [,a]
ffff
ffff
The contents of register ‘f’ are
rotated one bit to the left. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register
‘f’ (default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
Encoding:
0011
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
RLNCF
REG, 1, 0
ffff
ffff
register f
C
Q2
Example:
00da
f [,d [,a]
The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
register f
Words:
RRCF
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Before Instruction
REG
=
1010 1011
After Instruction
REG
=
Example:
RRCF
REG, 0, 0
Before Instruction
0101 0111
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
DS39609C-page 292
=
=
=
1110 0110
0111 0011
0
2003-2013 Microchip Technology Inc.
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RRNCF
Rotate Right f (no carry)
SETF
Set f
Syntax:
[ label ]
Syntax:
[ label ] SETF
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
(f) dest,
(f) dest
FFh f
Operation:
Status Affected:
None
Status Affected:
N, Z
Encoding:
0100
Description:
RRNCF
00da
f [,d [,a]
Encoding:
ffff
ffff
The contents of register ‘f’ are
rotated one bit to the right. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is
‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
register f
Words:
1
Cycles:
1
100a
ffff
ffff
Description:
The contents of the specified
register are set to FFh. If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
SETF
REG,1
Before Instruction
Q Cycle Activity:
Q1
Decode
0110
f [,a]
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
REG
=
0x5A
=
0xFF
After Instruction
REG
REG, 1, 0
Before Instruction
REG
=
1101 0111
After Instruction
REG
=
Example 2:
1110 1011
RRNCF
REG, 0, 0
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
2003-2013 Microchip Technology Inc.
DS39609C-page 293
PIC18F6520/8520/6620/8620/6720/8720
SLEEP
Enter SLEEP mode
SUBFWB
Subtract f from W with borrow
Syntax:
[ label ] SLEEP
Syntax:
[ label ] SUBFWB
Operands:
None
Operands:
Operation:
00h WDT,
0 WDT postscaler,
1 TO,
0 PD
0 f 255
d [0,1]
a [0,1]
Operation:
(W) – (f) – (C) dest
Status Affected:
N, OV, C, DC, Z
Status Affected:
TO, PD
Encoding:
0000
Description:
Encoding:
0000
0000
0011
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
No
operation
Process
Data
Go to
Sleep
Example:
SLEEP
After Instruction
TO =
PD =
1†
0
† If WDT causes wake-up, this bit is cleared.
ffff
ffff
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored in register ‘f’ (default). If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Before Instruction
?
?
01da
Description:
The Power-down status bit (PD) is
cleared. The Time-out status bit
(TO) is set. Watchdog Timer and
its postscaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
Words:
TO =
PD =
0101
f [,d [,a]
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
SUBFWB
REG, 1, 0
Before Instruction
REG
W
C
=
=
=
3
2
1
After Instruction
REG
W
C
Z
N
=
=
=
=
=
Example 2:
FF
2
0
0
1 ; result is negative
SUBFWB
REG, 0, 0
Before Instruction
REG
W
C
=
=
=
2
5
1
After Instruction
REG
W
C
Z
N
=
=
=
=
=
Example 3:
2
3
1
0
0
; result is positive
SUBFWB
REG, 1, 0
Before Instruction
REG
W
C
=
=
=
1
2
0
After Instruction
REG
W
C
Z
N
DS39609C-page 294
=
=
=
=
=
0
2
1
1
0
; result is zero
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
SUBLW
Subtract W from literal
SUBWF
Subtract W from f
Syntax:
[ label ] SUBLW k
Syntax:
[ label ] SUBWF
Operands:
0 k 255
Operands:
Operation:
k – (W) W
Status Affected:
N, OV, C, DC, Z
0 f 255
d [0,1]
a [0,1]
Operation:
(f) – (W) dest
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1000
kkkk
kkkk
Description:
W is subtracted from the eight-bit
literal ‘k’. The result is placed in
W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to W
Example 1:
SUBLW
0x02
Before Instruction
W
C
=
=
1
?
=
=
=
=
Example 2:
1
1
0
0
SUBLW
; result is positive
0x02
=
=
0
1
1
0
SUBLW
; result is zero
0x02
Before Instruction
W
C
=
=
=
=
=
=
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’,
the result is stored in W. If ‘d’ is
‘1’, the result is stored back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
Words:
1
Cycles:
1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
SUBWF
REG, 1, 0
Example 1:
=
=
=
3
2
?
FF
0
0
1
REG
W
C
Z
N
=
=
=
=
=
Example 2:
1
2
1
0
0
; result is positive
SUBWF
REG, 0, 0
Before Instruction
3
?
REG
W
C
After Instruction
W
C
Z
N
ffff
After Instruction
=
=
=
=
Example 3:
ffff
Description:
REG
W
C
2
?
After Instruction
W
C
Z
N
11da
Before Instruction
Before Instruction
W
C
0101
Q Cycle Activity:
Q1
After Instruction
W
C
Z
N
Encoding:
f [,d [,a]
; (2’s complement)
; result is negative
=
=
=
2
2
?
After Instruction
REG
W
C
Z
N
=
=
=
=
=
Example 3:
2
0
1
1
0
SUBWF
; result is zero
REG, 1, 0
Before Instruction
REG
W
C
=
=
=
1
2
?
After Instruction
REG
W
C
Z
N
2003-2013 Microchip Technology Inc.
=
=
=
=
=
FFh ;(2’s complement)
2
0
; result is negative
0
1
DS39609C-page 295
PIC18F6520/8520/6620/8620/6720/8720
SUBWFB
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
[ label ] SUBWFB
Syntax:
[ label ] SWAPF f [,d [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) – (W) – (C) dest
Operation:
Status Affected:
N, OV, C, DC, Z
(f) dest,
(f) dest
Status Affected:
None
Encoding:
Description:
0101
10da
f [,d [,a]
ffff
ffff
Subtract W and the Carry flag
(borrow) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding the
BSR value. If ‘a’ is ‘1’, then the bank
will be selected as per the BSR
value (default).
Encoding:
0011
Words:
1
Cycles:
1
Cycles:
1
Decode
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
SUBWFB
REG, 1, 0
Before Instruction
REG
W
C
=
=
=
0x19
0x0D
1
(0001 1001)
(0000 1101)
0x0C
0x0D
1
0
0
(0000 1011)
(0000 1101)
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example:
SWAPF
REG, 1, 0
Before Instruction
REG
REG
=
=
=
=
=
Example 2:
Q Cycle Activity:
Q1
=
0x53
After Instruction
After Instruction
REG
W
C
Z
N
ffff
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is
‘1’, the result is placed in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
1
Q2
ffff
Description:
Words:
Q Cycle Activity:
Q1
10da
=
0x35
; result is positive
SUBWFB REG, 0, 0
Before Instruction
REG
W
C
=
=
=
0x1B
0x1A
0
(0001 1011)
(0001 1010)
0x1B
0x00
1
1
0
(0001 1011)
After Instruction
REG
W
C
Z
N
=
=
=
=
=
Example 3:
SUBWFB
; result is zero
REG, 1, 0
Before Instruction
REG
W
C
=
=
=
0x03
0x0E
1
(0000 0011)
(0000 1101)
(1111 0100)
; [2’s comp]
(0000 1101)
After Instruction
REG
=
0xF5
W
C
Z
N
=
=
=
=
0x0E
0
0
1
DS39609C-page 296
; result is negative
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TBLRD
Table Read
TBLRD
Table Read (Continued)
Syntax:
[ label ]
Example 1:
TBLRD
Operands:
None
Operation:
if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) + 1 TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) – 1 TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 TBLPTR;
(Prog Mem (TBLPTR)) TABLAT;
TBLRD ( *; *+; *-; +*)
Before Instruction
Description:
0000
TABLAT
TBLPTR
MEMORY(0x00A356)
=
=
=
0x55
0x00A356
0x34
=
=
0x34
0x00A357
After Instruction
TABLAT
TBLPTR
Example 2:
TBLRD
+* ;
Before Instruction
TABLAT
TBLPTR
MEMORY(0x01A357)
MEMORY(0x01A358)
=
=
=
=
0xAA
0x01A357
0x12
0x34
=
=
0x34
0x01A358
After Instruction
Status Affected:None
Encoding:
*+ ;
0000
0000
10nn
nn=0 *
=1 *+
=2 *=3 +*
TABLAT
TBLPTR
This instruction is used to read the
contents of Program Memory (P.M.). To
address the Program Memory, a pointer
called Table Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2-Mbyte address
range.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLRD instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
operation
No operation
(Read Program
Memory)
No
No operation
operation (Write TABLAT)
2003-2013 Microchip Technology Inc.
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TBLWT
Table Write
TBLWT Table Write (Continued)
Syntax:
[ label ] TBLWT ( *; *+; *-; +*)
Words: 1
Operands:
None
Cycles: 2
Operation:
if TBLWT*,
(TABLAT) Holding Register;
TBLPTR – No Change;
if TBLWT*+,
(TABLAT) Holding Register;
(TBLPTR) + 1 TBLPTR;
if TBLWT*-,
(TABLAT) Holding Register;
(TBLPTR) – 1 TBLPTR;
if TBLWT+*,
(TBLPTR) + 1 TBLPTR;
(TABLAT) Holding Register;
Q Cycle Activity:
Description:
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *=3 +*
This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is
written to. The holding registers are
used to program the contents of
Program Memory (P.M.). (Refer
to Section 5.0 “Flash Program
Memory” for additional details on
programming Flash memory.)
The TBLPTR (a 21-bit pointer) points
to each byte in the Program Memory.
TBLPTR has a 2-Mbyte address
range. The LSb of the TBLPTR
selects which byte of the program
memory location to access.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify
the value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
DS39609C-page 298
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
operation
No
operation
(Read
TABLAT)
No
operation
No
operation
(Write to
Holding
Register )
Example 1:
Status Affected: None
Encoding:
Q1
TBLWT
*+;
Before Instruction
TABLAT
TBLPTR
HOLDING REGISTER
(0x00A356)
=
=
0x55
0x00A356
=
0xFF
After Instructions (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(0x00A356)
Example 2:
TBLWT
=
=
0x55
0x00A357
=
0x55
+*;
Before Instruction
TABLAT
TBLPTR
HOLDING REGISTER
(0x01389A)
HOLDING REGISTER
(0x01389B)
=
=
0x34
0x01389A
=
0xFF
=
0xFF
After Instruction (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(0x01389A)
HOLDING REGISTER
(0x01389B)
=
=
0x34
0x01389B
=
0xFF
=
0x34
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TSTFSZ
Test f, skip if 0
XORLW
Exclusive OR literal with W
Syntax:
[ label ] TSTFSZ f [,a]
Syntax:
[ label ] XORLW k
Operands:
0 f 255
a [0,1]
Operands:
0 k 255
Operation:
(W) .XOR. k W
Operation:
skip if f = 0
Status Affected:
N, Z
Status Affected:
None
Encoding:
Description:
Encoding:
0110
011a
ffff
ffff
If ‘f’ = 0, the next instruction,
fetched during the current
instruction execution is discarded
and a NOP is executed, making this
a two-cycle instruction. If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
No
operation
0000
1010
kkkk
kkkk
Description:
The contents of W are XOR’ed
with the 8-bit literal ‘k’. The result
is placed in W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to W
Example:
XORLW 0xAF
Before Instruction
W
=
0xB5
After Instruction
W
=
0x1A
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
TSTFSZ
:
:
CNT, 1
Before Instruction
PC
=
Address (HERE)
=
=
=
0x00,
Address (ZERO)
0x00,
Address (NZERO)
After Instruction
If CNT
PC
If CNT
PC
2003-2013 Microchip Technology Inc.
DS39609C-page 299
PIC18F6520/8520/6620/8620/6720/8720
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(W) .XOR. (f) dest
Status Affected:
N, Z
Encoding:
0001
10da
f [,d [,a]
ffff
ffff
Description:
Exclusive OR the contents of W
with register ‘f’. If ‘d’ is ‘0’, the result
is stored in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
REG, 1, 0
Before Instruction
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
DS39609C-page 300
0x1A
0xB5
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
25.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
25.1
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2003-2013 Microchip Technology Inc.
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PIC18F6520/8520/6620/8620/6720/8720
25.2
MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
25.3
HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple
platforms.
25.4
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
25.5
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
25.6
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS39609C-page 302
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
25.7
MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
25.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
2003-2013 Microchip Technology Inc.
25.9
MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
25.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
DS39609C-page 303
PIC18F6520/8520/6620/8620/6720/8720
25.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
25.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a breakpoint, the file registers can be examined and modified.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
25.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
DS39609C-page 304
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
26.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk byall ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2003-2013 Microchip Technology Inc.
DS39609C-page 305
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 26-1:
PIC18F6520/8520 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED)
6.0V
5.5V
Voltage
5.0V
PIC18FX520
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
FMAX (Extended)
FMAX
Frequency
FMAX = 40 MHz for PIC18F6520/8520 in Microcontroller mode.
FMAX (Extended) = 25 MHz for PIC18F6520/8520 in modes other than Microcontroller mode.
FIGURE 26-2:
PIC18LF6520/8520 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
Voltage
5.0V
PIC18LFX520
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
FMAX
4 MHz
Frequency
For PIC18F6520/8520 in Microcontroller mode:
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN 4.2V;
FMAX = 40 MHz, if VDDAPPMIN > 4.2V.
For PIC18F8X8X in modes other than Microcontroller mode:
FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN 4.2V;
FMAX = 25 MHz, if VDDAPPMIN > 4.2V.
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
DS39609C-page 306
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 26-3:
PIC18F6620/6720/8620/8720 VOLTAGE-FREQUENCY GRAPH
(INDUSTRIAL, EXTENDED)
6.0V
5.5V
Voltage
5.0V
PIC18FX620/X720
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
FMAX (Extended)
FMAX
Frequency
FMAX = 25 MHz in Microcontroller mode.
FMAX (Extended) = 16 MHz for PIC18F6520/8520 in modes other than Microcontroller mode.
FIGURE 26-4:
PIC18LF6620/6720/8620/8720 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
Voltage
5.0V
4.5V
PIC18LFX620/X720
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
FMAX
4 MHz
Frequency
In Microcontroller mode:
FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN 4.2V;
FMAX = 25 MHz, if VDDAPPMIN > 4.2V.
In modes other than Microcontroller mode:
FMAX = (5.45 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN 4.2V;
FMAX = 16 MHz, if VDDAPPMIN > 4.2V.
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
2003-2013 Microchip Technology Inc.
DS39609C-page 307
PIC18F6520/8520/6620/8620/6720/8720
26.1
DC Characteristics: Supply Voltage
PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended)
PIC18LF6520/8520/6620/8620/6720/8720 (Industrial)
PIC18LF6520/8520/6620/8620/6720/8720
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
PIC18F6520/8520/6620/8620/6720/8720
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
Symbol
No.
D001
VDD
Characteristic
Min
Typ
Max
Units
PIC18LFXX20
2.0
—
5.5
V
PIC18FXX20
4.2
—
5.5
V
Supply Voltage
D001A AVDD
Analog Supply Voltage
VDD – 0.3
—
VDD + 0.3
V
D002
VDR
RAM Data Retention
Voltage(1)
1.5
—
—
V
D003
VPOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
—
0.7
V
D004
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
—
—
D005
VBOR
Brown-out Reset Voltage
BORV1:BORV0 = 11
N/A
—
N/A
V
Legend:
Note 1:
Conditions
HS, XT, RC and LP Oscillator mode
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
BORV1:BORV0 = 10
2.64
—
2.92
V
BORV1:BORV0 = 01
4.11
—
4.55
V
BORV1:BORV0 = 00
4.41
—
4.87
V
Reserved
Shading of rows is to assist in readability of the table.
This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
DS39609C-page 308
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
26.2
DC Characteristics: Power-Down and Supply Current
PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended)
PIC18LF6520/8520/6620/8620/6720/8720 (Industrial)
PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C TA +85°C for industrial
PIC18F6520/8520/6620/8620/6720/8720
(Industrial, Extended)
Param
No.
Device
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Typ
Max
Units
Conditions
0.2
1
A
-40°C
0.2
1
A
+25°C
+85°C
Power-down Current (IPD)(1)
PIC18LFXX20
PIC18LFXX20
All devices
Legend:
Note 1:
2:
3:
1.2
5
A
0.4
1
A
-40°C
0.4
1
A
+25°C
1.8
8
A
+85°C
0.7
2
A
-40°C
0.7
2
A
+25°C
3.0
15
A
+85°C
VDD = 2.0V,
(Sleep mode)
VDD = 3.0V,
(Sleep mode)
VDD = 5.0V,
(Sleep mode)
Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
2003-2013 Microchip Technology Inc.
DS39609C-page 309
PIC18F6520/8520/6620/8620/6720/8720
26.2
DC Characteristics: Power-Down and Supply Current
PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended)
PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued)
PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C TA +85°C for industrial
PIC18F6520/8520/6620/8620/6720/8720
(Industrial, Extended)
Param
No.
Device
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Typ
Max
Units
Conditions
165
350
A
-40°C
165
350
A
+25°C
+85°C
Supply Current (IDD)(2,3)
PIC18LFXX20
PIC18LFXX20
All devices
PIC18LFXX20
2:
3:
350
A
750
A
-40°C
340
750
A
+25°C
300
750
A
+85°C
800
1700
A
-40°C
730
1700
A
+25°C
700
1700
A
+85°C
600
1200
A
-40°C
600
1200
A
+25°C
640
1300
A
+85°C
PIC18LFXX20 1000
2500
A
-40°C
1000
2500
A
+25°C
1000
2500
A
+85°C
2.2
5.0
mA
-40°C
2.1
5.0
mA
+25°C
2.0
5.0
mA
+85°C
All devices
Legend:
Note 1:
170
360
VDD = 2.0V
VDD = 3.0V
FOSC = 1 MHZ,
EC oscillator
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 4 MHz,
EC oscillator
VDD = 5.0V
Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
DS39609C-page 310
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
26.2
DC Characteristics: Power-Down and Supply Current
PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended)
PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued)
PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C TA +85°C for industrial
PIC18F6520/8520/6620/8620/6720/8720
(Industrial, Extended)
Param
No.
Device
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Typ
Max
Units
Conditions
9.3
15
mA
-40°C
9.5
15
mA
+25°C
Supply Current (IDD)(2,3)
PIC18FX620, PIC18FX720
10
15
mA
+85°C
11.8
20
mA
-40°C
12
20
mA
+25°C
12
20
mA
+85°C
16
20
mA
-40°C
16
20
mA
+25°C
16
20
mA
+85°C
19
25
mA
-40°C
19
25
mA
+25°C
19
25
mA
+85°C
PIC18FX620/X720
15
55
A
-40°C to +85°C
VDD = 2.0V
PIC18LF8520
13
18
A
-40°C to +85°C
VDD = 2.0V
20
35
A
-40°C to +85°C
VDD = 3.0V
50
85
A
-40°C to +85°C
VDD = 5.0V
—
200
A
-40°C to +85°C
VDD = 4.2V
—
250
A
-40°C to +125°C
VDD = 4.2V
PIC18FX620, PIC18FX720
PIC18FX520
PIC18FX520
D014
PIC18FXX20
Legend:
Note 1:
2:
3:
VDD = 4.2V
FOSC = 25 MHZ,
EC oscillator
VDD = 5.0V
VDD = 4.2V
FOSC = 40 MHZ,
EC oscillator
VDD = 5.0V
FOSC = 32 kHz,
Timer1 as clock
FOSC = 32 kHz,
Timer1 as clock
FOSC = 32 kHz,
Timer1 as clock
Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
2003-2013 Microchip Technology Inc.
DS39609C-page 311
PIC18F6520/8520/6620/8620/6720/8720
26.2
DC Characteristics: Power-Down and Supply Current
PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended)
PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued)
PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C TA +85°C for industrial
PIC18F6520/8520/6620/8620/6720/8720
(Industrial, Extended)
Param
No.
Device
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Typ
Max
Units
Conditions
Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD)
Watchdog Timer
D022
(IWDT)
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