PIC18F85J11 Family
Data Sheet
64/80-Pin,
High-Performance Microcontrollers
with nanoWatt Technology
2010 Microchip Technology Inc.
DS39774D
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
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The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
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Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
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are trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
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© 2010, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
ISBN: 978-1-60932-015-7
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39774D-page 2
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
64/80-Pin, High-Performance Microcontrollers
with nanoWatt Technology
Low-Power Features:
External Memory Bus (PIC18F8XJ11 only):
Power-Managed modes: Run, Idle, Sleep
Run Current Down to 7 A, Typical
Idle Current Down to 2.5 A, Typical
Sleep Current Down to 100 nA, Typical
Fast INTOSC Start-up from Sleep, 1 s Typical
Two-Speed Oscillator Start-up Reduces Crystal
Stabilization Wait Time
• Address Capability of up to 2 Mbytes
• 8-Bit or 16-Bit Interface
• 12-Bit, 16-Bit and 20-Bit Addressing modes
Flexible Oscillator Structure:
•
•
•
•
Two Crystal modes, 4-25 MHz
Two External Clock modes, up to 40 MHz
4x Phase Lock Loop (PLL)
Internal Oscillator Block:
- 8 user-selectable frequencies from 31.25 kHz
to 8 MHz
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock fails
Peripheral Highlights:
• High-Current Sink/Source 25 mA/25 mA
(PORTB and PORTC)
• Up to Four External Interrupts
• Four 8-Bit/16-Bit Timer/Counter modules
• Real-Time Clock (RTC) Software module:
- Configurable 24-hour clock, calendar,
automatic 100-year or 12800-year day of
week calculator using Timer1
• Two Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution 100 ns (TCY)
- PWM output: PWM resolution is up to 10-bit
• Master Synchronous Serial Port (MSSP) module with
Two Modes of Operation:
- 3-wire/4-wire SPI (supports all 4 SPI modes)
- I2C™ Master and Slave mode
• One Addressable USART module
• One Enhanced Addressable USART module:
- Supports LIN/J2602
- Auto-wake-up on Start bit and Break character
- Auto-Baud Detect (ABD)
• 10-Bit, up to 12-Channel A/D Converter:
- Auto-acquisition
- Conversion available during Sleep
• Two Analog Comparators
• Programmable Reference Voltage for Comparators
Special Microcontroller Features:
CCP
SPI
Master
I2C™
10-Bit
A/D (ch)
External Bus
I/O
BOR/LVD
Device
MSSP
SRAM Data
Flash # Single-Word Memory
(bytes)
(bytes) Instructions
Timers
8/16-Bit
Program Memory
Comparators
• 1,000 Erase/Write Cycle Flash
Program Memory Typical
• Flash Retention 20 Years Minimum
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• In-Circuit Serial Programming™ (ICSP™) via Two Pins
• In-Circuit Debug via two pins
• Operating Voltage Range: 2.0V to 3.6V
• 5.5V Tolerant Input (digital pins only)
• Selectable Open-Drain Configuration for Serial
Communication and CCP pins for Driving Outputs up
to 5V
• On-Chip 2.5V Regulator
EUSART/
AUSART
•
•
•
•
•
•
PSP
PIC18F63J11
8K
4096
1K
52
1/3
2
Y
Y
1/1
12
2
Y
N
Y
PIC18F64J11
16K
8192
1K
52
1/3
2
Y
Y
1/1
12
2
Y
N
Y
PIC18F65J11
32K
16384
2K
52
1/3
2
Y
Y
1/1
12
2
Y
N
Y
PIC18F83J11
8K
4096
1K
68
1/3
2
Y
Y
1/1
12
2
Y
Y
Y
PIC18F84J11
16K
8192
1K
68
1/3
2
Y
Y
1/1
12
2
Y
Y
Y
PIC18F85J11
32K
16384
2K
68
1/3
2
Y
Y
1/1
12
2
Y
Y
Y
2010 Microchip Technology Inc.
DS39774D-page 3
PIC18F85J11 FAMILY
Pin Diagrams
64-Pin TQFP
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RD3/PSP3
RD2/PSP2
RD1/PSP1
VSS
VDD
RD0/PSP0
RE7/CCP2(1)
RE6
RE5
RE4
RE3
RE2/CS
Pins are up to 5.5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RE1/WR
RE0/RD
RG0
RG1/TX2/CK2
1
RF7/AN5/SS
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
2
3
4
5
6
7
8
9
10
11
12
13
14
RF3/AN8
RF2/AN7/C1OUT
15
16
RG2/RX2/DT2
RG3
MCLR
RG4
VSS
VDDCORE/VCAP
48
47
RB0/INT0
RB1/INT1
46
45
RB2/INT2
RB3/INT3
RB4/KBI0
44
43
42
41
40
PIC18F63J11
PIC18F64J11
PIC18F65J11
39
38
37
36
35
34
33
RB5/KBI1
RB6/KBI2/PGC
VSS
RA6/OSC2/CLKO
RA7/OSC1/CLKI
VDD
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
Note 1:
DS39774D-page 4
RC7/RX1/DT1
RC6/TX1/CK1
RC0/T1OSO/T13CKI
RA4/T0CKI
RC1/T1OSI/CCP2(1)
RA5/AN4
VDD
VSS
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
AVSS
RA3/AN2/VREF+
AVDD
ENVREG
RF1/AN6/C2OUT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
The CCP2 pin placement depends on the CCP2MX Configuration bit setting.
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
Pin Diagrams (Continued)
Pins are up to 5.5V tolerant
RJ1/OE
RJ0/ALE
RD7/AD7/PSP7
RD6/AD6/PSP6
RD5/AD5/PSP5
RD4/AD4/PSP4
RD3/AD3/PSP3
RD2/AD2/PSP2
RD1/AD1/PSP1
VSS
VDD
RD0/AD0/PSP0
RE7/AD15/CCP2(1)
RE6/AD14
RE5/AD13
RE4/AD12
RE3/AD11
RE2/AD10/CS
RH0/A16
RH1/A17
80-Pin TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2/A18
RH3/A19
RE1/WR/AD9
RE0/RD/AD8
RG0
RG1/TX2/CK2
RG2/RX2/DT2
RG3
MCLR
RG4
VSS
VDDCORE/VCAP
RF7/AN5/SS
1
58
57
4
5
6
7
8
9
11
12
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
16
RF3/AN8
RF2/AN7/C1OUT
RH7
17
18
56
55
54
53
52
51
PIC18F83J11
PIC18F84J11
PIC18F85J11
10
13
14
15
RH6
60
59
2
3
50
49
48
47
46
45
44
43
42
19
20
41
RJ2/WRL
RJ3/WRH
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/CCP2(1)
RB4/KBI0
RB5/KBI1
RB6/KBI2/PGC
VSS
RA6/OSC2/CLKO
RA7/OSC1/CLKI
VDD
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RJ7/UB
RJ6/LB
Note 1:
RJ5/CE
RJ4/BA0
RC7/RX1/DT1
RC6/TX1/CK1
RC0/T1OSO/T13CKI
RA4/T0CKI
RC1/T1OSI/CCP2(1)
RA5/AN4
VSS
VDD
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
AVSS
RA3/AN3/VREF+
AVDD
ENVREG
RF1/AN6/C2OUT
RH4
RH5
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
The CCP2 pin placement depends on the settings of the CCP2MX and EMB Configuration bits.
2010 Microchip Technology Inc.
DS39774D-page 5
PIC18F85J11 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 31
3.0 Oscillator Configurations ............................................................................................................................................................ 35
4.0 Power-Managed Modes ............................................................................................................................................................. 43
5.0 Reset .......................................................................................................................................................................................... 51
6.0 Memory Organization ................................................................................................................................................................. 63
7.0 Flash Program Memory .............................................................................................................................................................. 89
8.0 External Memory Bus ................................................................................................................................................................. 99
9.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 111
10.0 Interrupts .................................................................................................................................................................................. 113
11.0 I/O Ports ................................................................................................................................................................................... 129
12.0 Timer0 Module ......................................................................................................................................................................... 153
13.0 Timer1 Module ......................................................................................................................................................................... 157
14.0 Timer2 Module ......................................................................................................................................................................... 163
15.0 Timer3 Module ......................................................................................................................................................................... 165
16.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 169
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 179
18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 223
19.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) ........................................................... 245
20.0 10-bit Analog-to-Digital Converter (A/D) Module ...................................................................................................................... 259
21.0 Comparator Module.................................................................................................................................................................. 269
22.0 Comparator Voltage Reference Module ................................................................................................................................... 275
23.0 Special Features of the CPU .................................................................................................................................................... 279
24.0 Development Support............................................................................................................................................................... 295
25.0 Instruction Set Summary .......................................................................................................................................................... 299
26.0 Electrical Characteristics .......................................................................................................................................................... 349
27.0 Packaging Information.............................................................................................................................................................. 387
Appendix A: Revision History............................................................................................................................................................. 393
Appendix B: Migration Between High-End Device Families............................................................................................................... 393
Index .................................................................................................................................................................................................. 395
The Microchip Web Site ..................................................................................................................................................................... 405
Customer Change Notification Service .............................................................................................................................................. 405
Customer Support .............................................................................................................................................................................. 405
Reader Response .............................................................................................................................................................................. 406
Product Identification System............................................................................................................................................................. 407
DS39774D-page 6
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TO OUR VALUED CUSTOMERS
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2010 Microchip Technology Inc.
DS39774D-page 7
PIC18F85J11 FAMILY
NOTES:
DS39774D-page 8
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC18F63J11
• PIC18F64J11
• PIC18F65J11
• PIC18F83J11
• PIC18F84J11
• PIC18F85J11
This family combines the traditional advantages of all
PIC18 microcontrollers – namely, high computational
performance and a rich feature set – while maintaining
an extremely competitive price point. These features
make the PIC18F85J11 family a logical choice for
many high-performance applications where price is a
primary consideration.
1.1
1.1.1
Core Features
nanoWatt TECHNOLOGY
All of the devices in the PIC18F85J11 family incorporate
a range of features that can significantly reduce power
consumption during operation. Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal RC
oscillator, power consumption during code
execution can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• On-the-Fly Mode Switching: The power-managed
modes are invoked by user code during operation,
allowing the user to incorporate power-saving ideas
into their application’s software design.
1.1.2
OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC18F85J11 family offer six
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• Two Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes offering the option of a
divide-by-4 clock output.
• A Phase Lock Loop (PLL) frequency multiplier,
available to the External Oscillator modes, which
allows clock speeds of up to 40 MHz.
• An internal oscillator block which provides an
8 MHz clock (±2% accuracy) and an INTRC source
(approximately 31 kHz, stable over temperature
and VDD), as well as a range of six user-selectable
clock frequencies, between 125 kHz to 4 MHz, for a
total of eight clock frequencies. This option frees the
two oscillator pins for use as additional general
purpose I/O.
2010 Microchip Technology Inc.
The internal oscillator block provides a stable reference
source that gives the family additional features for
robust operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
1.1.3
MEMORY OPTIONS
The PIC18F85J11 family provides a range of program
memory options, from 8 Kbytes to 32 Kbytes of code
space. The Flash cells for program memory are rated
to last up to 1000 erase/write cycles. Data retention
without refresh is conservatively estimated to be
greater than 20 years.
The PIC18F85J11 family also provides plenty of room
for dynamic application data, with up to 2048 bytes of
data RAM.
1.1.4
EXTENDED INSTRUCTION SET
The PIC18F85J11 family implements the optional
extension to the PIC18 instruction set, adding 8 new
instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as ‘C’.
1.1.5
EXTERNAL MEMORY BUS
In the event that 32 Kbytes of memory are inadequate
for an application, the 80-pin members of the
PIC18F85J11 family also implement an external memory bus. This allows the controller’s internal program
counter to address a memory space of up to 2 Mbytes,
permitting a level of data access that few 8-bit devices
can claim. This allows additional memory options,
including:
• Using combinations of on-chip and external
memory up to the 2-Mbyte limit
• Using external Flash memory for reprogrammable
application code or large data tables
• Using external RAM devices for storing large
amounts of variable data
DS39774D-page 9
PIC18F85J11 FAMILY
1.1.6
EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members or even
jumping from 64-pin to 80-pin devices.
The PIC18F85J11 family is also largely pin compatible
with other PIC18 general purpose families, such as the
PIC18F8720 and PIC18F8722. This allows a new
dimension to the evolution of applications, allowing
developers to select different price points within
Microchip’s PIC18 portfolio, while maintaining a similar
feature set.
1.3
Devices in the PIC18F85J11 family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in four
ways:
1.
2.
3.
4.
1.2
Other Special Features
• Communications: The PIC18F85J11 family
incorporates a range of serial communication
peripherals, including an Addressable USART, a
separate Enhanced USART that supports LIN
Specification LIN/J2602, and one Master SSP
(MSSP) module capable of both SPI and I2C™
(Master and Slave) modes of operation.
• CCP Modules: All devices in the family incorporate
two Capture/Compare/PWM (CCP) modules. Up to
four different time bases may be used to perform
several different operations at once.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reducing code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 26.0 “Electrical Characteristics” for
time-out periods.
DS39774D-page 10
Details on Individual Family
Members
Flash program memory (three sizes, ranging
from 8 Kbytes for PIC18FX3J11 devices to
32 Kbytes for PIC18FX5J11 devices).
Data RAM (1024 bytes for PIC18FX3J11 and
PIC18FX4J11 devices, 2048 bytes for
PIC18FX5J11 devices).
I/O ports (7 bidirectional ports on 64-pin devices,
9 bidirectional ports on 80-pin devices).
External Memory Bus (implemented in 80-pin
devices only).
All other features for devices in this family are identical.
These are summarized in Table 1-1 and Table 1-2.
The pinouts for all devices are listed in Table 1-3 and
Table 1-4.
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-1:
DEVICE FEATURES FOR THE PIC18F6XJ11 FAMILY (64-PIN DEVICES)
Features
PIC18F63J11
Operating Frequency
Program Memory (Bytes)
PIC18F64J11
PIC18F65J11
DC – 40 MHz
8K
16K
32K
Program Memory (Instructions)
4096
8192
16384
Data Memory (Bytes)
1024
1024
2048
Interrupt Sources
27
I/O Ports
Ports A, B, C, D, E, F, G
Timers
4
Capture/Compare/PWM Modules
2
Serial Communications
MSSP, Addressable USART, Enhanced USART
Parallel Communications (PSP)
Yes
External Memory Bus
No
10-Bit Analog-to-Digital Module
Resets (and Delays)
Instruction Set
12 Input Channels
POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
75 Instructions, 83 with Extended Instruction Set Enabled
Packages
64-Pin TQFP
TABLE 1-2:
DEVICE FEATURES FOR THE PIC18F8XJ11 FAMILY (80-PIN DEVICES)
Features
PIC18F83J11
Operating Frequency
Program Memory (Bytes)
PIC18F84J11
PIC18F85J11
DC – 40 MHz
8K
16K
32K
Program Memory (Instructions)
4096
8192
16384
Data Memory (Bytes)
1024
1024
2048
Interrupt Sources
I/O Ports
Timers
Capture/Compare/PWM Modules
Serial Communications
Parallel Communications (PSP)
External Memory Bus
10-Bit Analog-to-Digital Module
Resets (and Delays)
Instruction Set
Packages
2010 Microchip Technology Inc.
27
Ports A, B, C, D, E, F, G, H, J
4
2
MSSP, Addressable USART, Enhanced USART
Yes
Yes
12 Input Channels
POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
75 Instructions, 83 with Extended Instruction Set Enabled
80-Pin TQFP
DS39774D-page 11
PIC18F85J11 FAMILY
FIGURE 1-1:
PIC18F6XJ11 (64-PIN) BLOCK DIAGRAM
Data Bus
Table Pointer
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address
31 Level Stack
4
BSR
Address Latch
Program Memory
(96 Kbytes)
STKPTR
12
PORTC
RC0:RC7(1)
inc/dec
logic
Table Latch
Instruction Bus
PORTB
RB0:RB7(1)
4
Access
Bank
12
FSR0
FSR1
FSR2
Data Latch
8
RA0:RA7(1,2)
Data Memory
(3.9 Kbytes)
PCLATU PCLATH
21
PORTA
Data Latch
8
8
inc/dec logic
Address
Decode
ROM Latch
PORTD
RD0:RD7(1)
IR
8
Instruction
Decode and
Control
OSC2/CLKO
OSC1/CLKI
ENVREG
State Machine
Control Signals
PRODH PRODL
3
Timing
Generation
Power-up
Timer
INTRC
Oscillator
8 MHz
Oscillator
Oscillator
Start-up Timer
Precision
Band Gap
Reference
Watchdog
Timer
Voltage
Regulator
BOR and
LVD(3)
8 x 8 Multiply
8
BITOP
W
8
8
8
Power-on
Reset
PORTE
RE0:RE7(1)
8
PORTF
8
RF1:RF7(1)
ALU
8
PORTG
RG0:RG4(1)
VDDCORE/VCAP
Note 1:
VDD,VSS
MCLR
Timer0
Timer1
Timer2
Timer3
ADC
10-Bit
CCP1
CCP2
AUSART
EUSART
MSSP
Comparators
See Table 1-3 for I/O port pin descriptions.
2:
RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 3.0 “Oscillator Configurations” for more
information
3:
Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.
DS39774D-page 12
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 1-2:
PIC18F8XJ11 (80-PIN) BLOCK DIAGRAM
Data Bus
Table Pointer
inc/dec logic
20
Address Latch
PCU PCH PCL
Program Counter
31 Level Stack
System Bus Interface
PORTB
RB0:RB7(1)
12
Data Address
4
Address Latch
4
12
BSR
STKPTR
Program Memory
(128 Kbytes)
RA0:RA7(1,2)
Data Memory
(3.9 Kbytes)
PCLATU PCLATH
21
PORTA
Data Latch
8
8
Data Latch
PORTC
Access
Bank
FSR0
FSR1
FSR2
RC0:RC7(1)
12
inc/dec
logic
8
Table Latch
PORTD
RD0:RD7(1)
Address
Decode
ROM Latch
Instruction Bus
PORTE
IR
RE0:RE7(1)
AD15:AD0, A19:A16
(Multiplexed with PORTD,
PORTE and PORTH)
State Machine
Control Signals
OSC2/CLKO
OSC1/CLKI
ENVREG
8
Timing
Generation
Power-up
Timer
INTRC
Oscillator
8 MHz
Oscillator
Oscillator
Start-up Timer
3
Watchdog
Timer
Voltage
Regulator
BOR and
LVD(3)
RF1:RF7(1)
8 x 8 Multiply
8
W
BITOP
8
8
8
PORTG
RG0:RG4(1)
8
8
ALU
Power-on
Reset
Precision
Band Gap
Reference
PORTF
PRODH PRODL
Instruction
Decode &
Control
PORTH
8
RH0:RH7(1)
PORTJ
RJ0:RJ7(1)
VDDCORE/VCAP
Note 1:
VDD,VSS
MCLR
Timer0
Timer1
Timer2
Timer3
ADC
10-Bit
CCP1
CCP2
AUSART
EUSART
MSSP
Comparators
See Table 1-3 for I/O port pin descriptions.
2:
RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 3.0 “Oscillator Configurations” for more
information
3:
Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.
2010 Microchip Technology Inc.
DS39774D-page 13
PIC18F85J11 FAMILY
TABLE 1-3:
PIC18F6XJ11 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
TQFP
MCLR
7
RA7/OSC1/CLKI
RA7
OSC1
CLKI
39
RA6/OSC2/CLKO
RA6
OSC2
40
CLKO
Pin Buffer
Type Type
I
ST
I/O
I
I
TTL
CMOS
CMOS
I/O
O
TTL
—
O
—
Description
Master Clear (input) or programming voltage (input). This
pin is an active-low Reset to the device.
Oscillator crystal or external clock input.
General purpose I/O pin.
Oscillator crystal input.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
Oscillator crystal or clock output.
General purpose I/O pin.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
24
RA1/AN1
RA1
AN1
23
RA2/AN2/VREFRA2
AN2
VREF-
22
RA3/AN3/VREF+
RA3
AN3
VREF+
21
RA4/T0CKI
RA4
T0CKI
28
RA5/AN4
RA5
AN4
27
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog Input 1.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
I/O
I
ST/OD
ST
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
I/O
I
TTL
Analog
Digital I/O.
Analog Input 4.
RA6
See the OSC2/CLKO/RA6 pin.
RA7
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39774D-page 14
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-3:
PIC18F6XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0
RB0
INT0
48
RB1/INT1
RB1
INT1
47
RB2/INT2
RB2
INT2
46
RB3/INT3
RB3
INT3
45
RB4/KBI0
RB4
KBI0
44
RB5/KBI1
RB5
KBI1
43
RB6/KBI2/PGC
RB6
KBI2
PGC
42
RB7/KBI3/PGD
RB7
KBI3
PGD
37
I/O
I
TTL
ST
Digital I/O.
External Interrupt 0.
I/O
I
TTL
ST
Digital I/O.
External Interrupt 1.
I/O
I
TTL
ST
Digital I/O.
External Interrupt 2.
I/O
I
TTL
ST
Digital I/O.
External Interrupt 3.
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39774D-page 15
PIC18F85J11 FAMILY
TABLE 1-3:
PIC18F6XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
30
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(1)
29
RC2/CCP1
RC2
CCP1
33
RC3/SCK/SCL
RC3
SCK
SCL
34
RC4/SDI/SDA
RC4
SDI
SDA
35
RC5/SDO
RC5
SDO
36
RC6/TX1/CK1
RC6
TX1
CK1
31
RC7/RX1/DT1
RC7
RX1
DT1
32
I/O
O
I
ST
—
ST
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
I/O
I/O
ST
ST
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
I/O
I/O
I/O
ST
ST
I2C
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
I/O
I
I/O
ST
ST
I2C
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
ST
—
Digital I/O.
SPI data out.
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX1/DT1).
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX1/CK1).
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39774D-page 16
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-3:
PIC18F6XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTD is a bidirectional I/O port.
RD0/PSP0
RD0
PSP0
58
RD1/PSP1
RD1
PSP1
55
RD2/PSP2
RD2
PSP2
54
RD3/PSP3
RD3
PSP3
53
RD4/PSP4
RD4
PSP4
52
RD5/PSP5
RD5
PSP5
51
RD6/PSP6
RD6
PSP6
50
RD7/PSP7
RD7
PSP7
49
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39774D-page 17
PIC18F85J11 FAMILY
TABLE 1-3:
PIC18F6XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTE is a bidirectional I/O port.
RE0/RD
RE0
RD
2
RE1/WR
RE1
WR
1
RE2/CS
RE2
CS
64
RE3
I/O
I
ST
TTL
Digital I/O.
Read control for Parallel Slave Port.
I/O
I
ST
TTL
Digital I/O.
Write control for Parallel Slave Port.
I/O
I
ST
TTL
Digital I/O.
Chip select control for Parallel Slave Port.
63
I/O
ST
Digital I/O.
RE4
62
I/O
ST
Digital I/O.
RE5
61
I/O
ST
Digital I/O.
RE6
60
I/O
ST
Digital I/O.
RE7/CCP2
RE7
CCP2(2)
59
I/O
I/O
ST
ST
Digital I/O.
Capture 2 input/Compare 2 output/PWM2 output.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39774D-page 18
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-3:
PIC18F6XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT
RF1
AN6
C2OUT
17
RF2/AN7/C1OUT
RF2
AN7
C1OUT
16
RF3/AN8
RF3
AN8
15
RF4/AN9
RF4
AN9
14
RF5/AN10/CVREF
RF5
AN10
CVREF
13
RF6/AN11
RF6
AN11
12
RF7/AN5/SS
RF7
AN5
SS
11
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 6.
Comparator 2 output.
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 7.
Comparator 1 output.
I/O
I
ST
Analog
Digital I/O.
Analog Input 8.
I/O
I
ST
Analog
Digital I/O.
Analog Input 9.
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog Input 10.
Comparator reference voltage output.
I/O
I
ST
Analog
Digital I/O.
Analog Input 11.
I/O
O
I
ST
Analog
TTL
Digital I/O.
Analog Input 5.
SPI slave select input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39774D-page 19
PIC18F85J11 FAMILY
TABLE 1-3:
PIC18F6XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTG is a bidirectional I/O port.
RG0
3
I/O
ST
Digital I/O.
RG1/TX2/CK2
RG1
TX2
CK2
4
I/O
O
I/O
ST
—
ST
Digital I/O.
AUSART asynchronous transmit.
AUSART synchronous clock (see related RX2/DT2).
RG2/RX2/DT2
RG2
RX2
DT2
5
I/O
I
I/O
ST
ST
ST
Digital I/O.
AUSART asynchronous receive.
AUSART synchronous data (see related TX2/CK2).
RG3
6
I/O
ST
Digital I/O.
RG4
8
I/O
ST
Digital I/O.
VSS
9, 25, 41, 56
P
—
VDD
26, 38, 57
P
—
Positive supply for logic and I/O pins.
AVSS
20
P
—
Ground reference for analog modules.
AVDD
19
P
—
Positive supply for analog modules.
ENVREG
18
I
ST
VDDCORE/VCAP
10
VDDCORE
P
—
VCAP
P
—
Ground reference for logic and I/O pins.
Enable for on-chip voltage regulator.
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39774D-page 20
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
TQFP
MCLR
9
RA7/OSC1/CLKI
RA7
OSC1
CLKI
49
RA6/OSC2/CLKO
RA6
OSC2
50
CLKO
Pin Buffer
Type Type
I
ST
I/O
I
I
TTL
CMOS
CMOS
I/O
O
TTL
—
O
—
Description
Master Clear (input) or programming voltage (input). This
pin is an active-low Reset to the device.
Oscillator crystal or external clock input.
General purpose I/O pin.
Oscillator crystal input.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
Oscillator crystal or clock output.
General purpose I/O pin.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
30
RA1/AN1
RA1
AN1
29
RA2/AN2/VREFRA2
AN2
VREF-
28
RA3/AN3/VREF+
RA3
AN3
VREF+
27
RA4/T0CKI
RA4
T0CKI
34
RA5/AN4
RA5
AN4
33
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog Input 1.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
I/O
I
ST/OD
ST
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
I/O
I
TTL
Analog
Digital I/O.
Analog Input 4.
RA6
See the OSC2/CLKO/RA6 pin.
RA7
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39774D-page 21
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0
RB0
INT0
58
RB1/INT1
RB1
INT1
57
RB2/INT2
RB2
INT2
56
RB3/INT3/CCP2
RB3
INT3
CCP2(1)
55
RB4/KBI0
RB4
KBI0
54
RB5/KBI1
RB5
KBI1
53
RB6/KBI2/PGC
RB6
KBI2
PGC
52
RB7/KBI3/PGD
RB7
KBI3
PGD
47
I/O
I
TTL
ST
Digital I/O.
External Interrupt 0.
I/O
I
TTL
ST
Digital I/O.
External Interrupt 1.
I/O
I
TTL
ST
Digital I/O.
External Interrupt 2.
I/O
I
I/O
TTL
ST
ST
Digital I/O.
External Interrupt 3.
Capture 2 input/Compare 2 output/PWM2 output.
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39774D-page 22
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
36
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(2)
35
RC2/CCP1
RC2
CCP1
43
RC3/SCK/SCL
RC3
SCK
SCL
44
RC4/SDI/SDA
RC4
SDI
SDA
45
RC5/SDO
RC5
SDO
46
RC6/TX1/CK1
RC6
TX1
CK1
37
RC7/RX1/DT1
RC7
RX1
DT1
38
I/O
O
I
ST
—
ST
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
I/O
I/O
ST
ST
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
I/O
I/O
I/O
ST
ST
I2C
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
I/O
I
I/O
ST
ST
I2C
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
ST
—
Digital I/O.
SPI data out.
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX1/DT1).
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX1/CK1).
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39774D-page 23
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTD is a bidirectional I/O port.
RD0/AD0/PSP0
RD0
AD0
PSP0
72
RD1/AD1/PSP1
RD1
AD1
PSP1
69
RD2/AD2/PSP2
RD2
AD2
PSP2
68
RD3/AD3/PSP3
RD3
AD3
PSP3
67
RD4/AD4/PSP4
RD4
AD4
PSP4
66
RD5/AD5/PSP5
RD5
AD5
PSP5
65
RD6/AD6/PSP6
RD6
AD6
PSP6
64
RD7/AD7/PSP7
RD7
AD7
PSP7
63
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 0.
Parallel Slave Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 1.
Parallel Slave Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 2.
Parallel Slave Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 3.
Parallel Slave Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 4.
Parallel Slave Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 5.
Parallel Slave Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 6.
Parallel Slave Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 7.
Parallel Slave Port data.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39774D-page 24
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTE is a bidirectional I/O port.
RE0/RD/AD8
RE0
RD
AD8
4
RE1/WR/AD9
RE1
WR
AD9
3
RE2/AD10/CS
RE2
AD10
CS
78
RE3/AD11
RE3
AD11
77
RE4/AD12
RE4
AD12
76
RE5/AD13
RE5
AD13
75
RE6/AD14
RE6
AD14
74
RE7/AD15/CCP2
RE7
AD15
CCP2(3)
73
I/O
I
I/O
ST
TTL
TTL
Digital I/O.
Read control for Parallel Slave Port.
External memory address/data 8.
I/O
I
I/O
ST
TTL
TTL
Digital I/O.
Write control for Parallel Slave Port.
External memory address/data 9.
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
External memory address/data 10.
Chip select control for Parallel Slave Port.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 11.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 12.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 13.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 14.
I/O
I/O
I/O
ST
TTL
ST
Digital I/O.
External memory address/data 15.
Capture 2 input/Compare 2 output/PWM2 output.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39774D-page 25
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT
RF1
AN6
C2OUT
23
RF2/AN7/C1OUT
RF2
AN7
C1OUT
18
RF3/AN8
RF3
AN8
17
RF4/AN9
RF4
AN9
16
RF5/AN10/CVREF
RF5
AN10
CVREF
15
RF6/AN11
RF6
AN11
14
RF7/AN5/SS
RF7
AN5
SS
13
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 6.
Comparator 2 output.
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 7.
Comparator 1 output.
I/O
I
ST
Analog
Digital I/O.
Analog Input 8.
I/O
I
ST
Analog
Digital I/O.
Analog Input 9.
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog Input 10.
Comparator reference voltage output.
I/O
I
ST
Analog
Digital I/O.
Analog Input 11.
I/O
O
I
ST
Analog
TTL
Digital I/O.
Analog Input 5.
SPI slave select input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39774D-page 26
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTG is a bidirectional I/O port.
RG0
5
I/O
ST
Digital I/O.
RG1/TX2/CK2
RG1
TX2
CK2
6
I/O
O
I/O
ST
—
ST
Digital I/O.
AUSART asynchronous transmit.
AUSART synchronous clock (see related RX2/DT2).
RG2/RX2/DT2
RG2
RX2
DT2
7
I/O
I
I/O
ST
ST
ST
Digital I/O.
AUSART asynchronous receive.
AUSART synchronous data (see related TX2/CK2).
RG3
8
I/O
ST
Digital I/O.
RG4
10
I/O
ST
Digital I/O.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39774D-page 27
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTH is a bidirectional I/O port.
RH0/A16
RH0
A16
79
RH1/A17
RH1
A17
80
RH2/A18
RH2
A18
1
RH3/A19
RH3
A19
2
RH4
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 16.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 17.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 18.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 19.
22
I/O
ST
Digital I/O.
RH5
21
I/O
ST
Digital I/O.
RH6
20
I/O
ST
Digital I/O.
RH7
19
I/O
ST
Digital I/O.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
DS39774D-page 28
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin Buffer
Type Type
Description
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
ALE
62
RJ1/OE
RJ1
OE
61
RJ2/WRL
RJ2
WRL
60
RJ3/WRH
RJ3
WRH
59
RJ4/BA0
RJ4
BA0
39
RJ5/CE
RJ5
CE
40
RJ6/LB
RJ6
LB
41
RJ7/UB
RJ7
UB
42
I/O
O
ST
—
Digital I/O.
External memory address latch enable.
I/O
O
ST
—
Digital I/O.
External memory output enable.
I/O
O
ST
—
Digital I/O.
External memory write low control.
I/O
O
ST
—
Digital I/O.
External memory write high control.
I/O
O
ST
—
Digital I/O.
External memory byte address 0 control.
I/O
O
ST
—
Digital I/O
External memory chip enable control.
I/O
O
ST
—
Digital I/O.
External memory low byte control.
I/O
O
ST
—
Digital I/O.
External memory high byte control.
VSS
11, 31, 51, 70
P
—
Ground reference for logic and I/O pins.
VDD
32, 48, 71
P
—
Positive supply for logic and I/O pins.
AVSS
26
P
—
Ground reference for analog modules.
AVDD
25
P
—
Positive supply for analog modules.
ENVREG
24
I
ST
VDDCORE/VCAP
VDDCORE
12
VCAP
P
—
P
—
Enable for on-chip voltage regulator.
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc.
DS39774D-page 29
PIC18F85J11 FAMILY
NOTES:
DS39774D-page 30
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
• All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”)
• All AVDD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
• ENVREG (if implemented) and VCAP/VDDCORE pins
(see Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)”)
VDD
R2
VCAP/VDDCORE
C1
C6(2)
VSS
VDD
VDD
VSS
C3(2)
C5(2)
C4(2)
Key (all values are recommendations):
• PGC/PGD pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
R1: 10 kΩ
Note:
C7
PIC18FXXJXX
C1 through C6: 0.1 F, 20V ceramic
• VREF+/VREF- pins are used when external voltage
reference for analog modules is implemented
(1) (1)
ENVREG
MCLR
These pins must also be connected if they are being
used in the end application:
Additionally, the following pins may be required:
VSS
R1
VSS
The following pins must always be connected:
C2(2)
VDD
Getting started with the PIC18F85J11 family family of
8-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.
RECOMMENDED
MINIMUM CONNECTIONS
VDD
Basic Connection Requirements
FIGURE 2-1:
AVSS
2.1
GUIDELINES FOR GETTING
STARTED WITH PIC18FJ
MICROCONTROLLERS
AVDD
2.0
C7: 10 F, 6.3V or greater, tantalum or ceramic
R2: 100Ω to 470Ω
Note 1:
2:
See Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)” for
explanation of ENVREG pin connections.
The example shown is for a PIC18F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
The minimum mandatory connections are shown in
Figure 2-1.
2010 Microchip Technology Inc.
DS39774D-page 31
PIC18F85J11 FAMILY
2.2
2.2.1
Power Supply Pins
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2
TANK CAPACITORS
On boards with power traces running longer than
six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
DS39774D-page 32
2.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: Device Reset, and Device Programming
and Debugging. If programming and debugging are
not required in the end application, a direct
connection to VDD may be all that is required. The
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R1
R2
JP
MCLR
PIC18FXXJXX
C1
Note 1:
R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2:
R2 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
2.4
Voltage Regulator Pins (ENVREG
and VCAP/VDDCORE)
The on-chip voltage regulator enable pin, ENVREG,
must always be connected directly to either a supply
voltage or to ground. Tying ENVREG to VDD enables
the regulator, while tying it to ground disables the
regulator. Refer to Section 23.3 “On-Chip Voltage
Regulator” for details on connecting and using the
on-chip regulator.
When the regulator is enabled, a low-ESR (< 5Ω)
capacitor is required on the VCAP/VDDCORE pin to
stabilize the voltage regulator output voltage. The
VCAP/VDDCORE pin must not be connected to VDD and
must use a capacitor of 10 F connected to ground. The
type can be ceramic or tantalum. A suitable example is
the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or
equivalent. Designers may use Figure 2-3 to evaluate
ESR equivalence of candidate devices.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 26.0 “Electrical
Characteristics” for additional information.
When the regulator is disabled, the VCAP/VDDCORE pin
must be tied to a voltage supply at the VDDCORE level.
Refer to Section 26.0 “Electrical Characteristics” for
information on VDD and VDDCORE.
Note that the “LF” versions of some low pin count
PIC18FJ parts (e.g., the PIC18LF45J10) do not have
the ENVREG pin. These devices are provided with the
voltage regulator permanently disabled; they must
always be provided with a supply voltage on the
VDDCORE pin.
FIGURE 2-3:
2.5
ICSP Pins
The PGC and PGD pins are used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes, and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communications to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin input voltage high
(VIH) and input low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGCx/PGDx pins) programmed
into the device matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 24.0 “Development Support”.
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
10
ESR ()
1
0.1
0.01
0.001
0.01
Note:
0.1
1
10
100
Frequency (MHz)
1000 10,000
Data for Murata GRM21BF50J106ZE01 shown.
Measurements at 25°C, 0V DC bias.
2010 Microchip Technology Inc.
DS39774D-page 33
PIC18F85J11 FAMILY
2.6
External Oscillator Pins
FIGURE 2-4:
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency
secondary
oscillator
(refer to
Section 3.0 “Oscillator Configurations” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Single-Sided and In-Line Layouts:
Copper Pour
(tied to ground)
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design”
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
2.7
Unused I/Os
Primary Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
OSC1
C1
`
OSC2
GND
C2
`
T1OSO
T1OS I
Timer1 Oscillator
Crystal
Layout suggestions are shown in Figure 2-4. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
In planning the application’s routing and I/O assignments, ensure that adjacent port pins and other signals
in close proximity to the oscillator are benign (i.e., free
of high frequencies, short rise and fall times, and other
similar noise).
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
`
T1 Oscillator: C1
T1 Oscillator: C2
Fine-Pitch (Dual-Sided) Layouts:
Top Layer Copper Pour
(tied to ground)
Bottom Layer
Copper Pour
(tied to ground)
OSCO
C2
Oscillator
Crystal
GND
C1
OSCI
DEVICE PINS
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
DS39774D-page 34
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
3.0
OSCILLATOR
CONFIGURATIONS
3.1
Oscillator Types
Five of these are selected by the user by programming
the FOSC Configuration bits. The sixth mode
(INTRC) may be invoked under software control; it can
also be configured as the default mode on device
Resets.
The PIC18F85J11 family of devices can be operated in
six different oscillator modes:
1.
2.
3.
4.
5.
6.
HS
High-Speed Crystal/Resonator
HSPLL High-Speed Crystal/Resonator
with Software PLL Control
EC
External Clock with FOSC/4 Output
ECPLL External Clock with Software PLL
Control
INTOSC Internal Fast RC (8 MHz) Oscillator
INTRC Internal 31 kHz Oscillator
FIGURE 3-1:
In addition, PIC18F85J11 family devices can switch
between different clock sources, either under software
control or automatically under certain conditions. This
allows for additional power savings by managing
device clock speed in real time without resetting the
application.
The clock sources for the PIC18F85J11 family of
devices are shown in Figure 3-1.
PIC18F85J11 FAMILY CLOCK DIAGRAM
PIC18F85J11 Family
Primary Oscillator
HS, EC
OSC2
Sleep
4 x PLL
OSC1
Secondary Oscillator
T1OSCEN
Enable
Oscillator
OSCCON
8 MHz
4 MHz
Internal
Oscillator
Block
8 MHz
(INTOSC)
Postscaler
8 MHz
Source
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
1 31 kHz
0
INTRC
Source
2010 Microchip Technology Inc.
31 kHz (INTRC)
Internal Oscillator
CPU
111
110
IDLEN
101
100
011
MUX
OSCCON
Peripherals
MUX
T1OSC
T1OSO
T1OSI
HSPLL, ECPLL
010
001
000
Clock
Control
FOSC
OSCCON
Clock Source Option
for Other Modules
OSCTUNE
WDT, PWRT, FSCM
and Two-Speed Start-up
DS39774D-page 35
PIC18F85J11 FAMILY
3.2
Control Registers
The OSCTUNE register (Register 3-2) controls the
tuning and operation of the internal oscillator block. It
also implements the PLLEN bits which control the
operation of the Phase Locked Loop (PLL) in Internal
Oscillator modes (see Section 3.4.3 “PLL Frequency
Multiplier”).
The OSCCON register (Register 3-1) controls the main
aspects of the device clock’s operation. It selects the
oscillator type to be used, which of the power-managed
modes to invoke and the output frequency of the
INTOSC source. It also provides status on the
oscillators.
REGISTER 3-1:
R/W-0
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-1
IDLEN
IRCF2
(2)
R/W-0
(2)
IRCF1
R(1)
R/W-0
IRCF0
(2)
OSTS
R-0
IOFS
R/W-0
SCS1
(4)
R/W-0
SCS0(4)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IDLEN: Idle Enable bit
1 = Device enters an Idle mode when a SLEEP instruction is executed
0 = Device enters Sleep mode when a SLEEP instruction is executed
bit 6-4
IRCF: INTOSC Source Frequency Select bits(2)
111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz (default)
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC)(3)
bit 3
OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready
bit 2
IOFS: INTOSC Frequency Stable bit
1 = Fast RC oscillator frequency is stable
0 = Fast RC oscillator frequency is not stable
bit 1-0
SCS: System Clock Select bits(4)
11 = Internal oscillator block
10 = Primary oscillator
01 = Timer1 oscillator
When FOSC2 = 1:
00 = Primary oscillator
When FOSC2 = 0:
00 = Internal oscillator
Note 1:
2:
3:
4:
Reset state depends on the state of the IESO Configuration bit.
Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
Source selected by the INTSRC bit (OSCTUNE), see text.
Modifying these bits will cause an immediate clock source switch.
DS39774D-page 36
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 3-2:
R/W-0
INTSRC
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0
PLLEN
(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived from INTRC 31 kHz oscillator
bit 6
PLLEN: Frequency Multiplier PLL Enable bit(1)
1 = PLL is enabled
0 = PLL is disabled
bit 5-0
TUN: Fast RC Oscillator (INTOSC) Frequency Tuning bits
011111 = Maximum frequency
•
•
•
•
000001
000000 = Center frequency. Fast RC oscillator is running at the calibrated frequency.
111111
•
•
•
•
100000 = Minimum frequency
Note 1:
3.3
Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and reads
as ‘0’.
Clock Sources and
Oscillator Switching
Essentially, PIC18F85J11 family devices have three
independent clock sources:
• Primary oscillators
• Secondary oscillators
• Internal oscillator
The primary oscillators can be thought of as the main
device oscillators. These are any external oscillators
connected to the OSC1 and OSC2 pins, and include
the External Crystal and Resonator modes and the
External Clock modes. In some circumstances, the
internal oscillator block may be considered a primary
oscillator. The particular mode is defined by the FOSC
Configuration bits. The details of these modes are
covered in Section 3.4 “External Oscillator Modes”.
The secondary oscillators are external clock sources
that are not connected to the OSC1 or OSC2 pins.
These sources may continue to operate even after the
controller is placed in a power-managed mode.
2010 Microchip Technology Inc.
PIC18F85J11 family devices offer the Timer1 oscillator
as a secondary oscillator source. This oscillator, in all
power-managed modes, is often the time base for
functions such as a Real-Time Clock. The Timer1 oscillator is discussed in greater detail in Section 13.3
“Timer1 Oscillator”
In addition to being a primary clock source in some circumstances, the internal oscillator is available as a
power-managed mode clock source. The INTRC
source is also used as the clock source for several
special features, such as the WDT and Fail-Safe Clock
Monitor. The internal oscillator block is discussed in
more detail in Section 3.5 “Internal Oscillator
Block”.
The PIC18F85J11 family includes features that allow
the device clock source to be switched from the main
oscillator, chosen by device configuration, to one of the
alternate clock sources. When an alternate clock
source is enabled, various power-managed operating
modes are available.
DS39774D-page 37
PIC18F85J11 FAMILY
3.3.1
CLOCK SOURCE SELECTION
The System Clock Select bits, SCS
(OSCCON), select the clock source. The available clock sources are the primary clock, defined by the
FOSC Configuration bits, the secondary clock
(Timer1 oscillator) and the internal oscillator. The clock
source changes after one or more of the bits are written
to, following a brief clock transition interval.
The OSTS (OSCCON) and T1RUN (T1CON)
bits indicate which clock source is currently providing
the device clock. The OSTS bit indicates that the
Oscillator Start-up Timer (OST) has timed out and the
primary clock is providing the device clock in primary
clock modes. The T1RUN bit indicates when the
Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only
one of these bits will be set at any time. If neither of
these bits are set, the INTRC is providing the clock, or
the internal oscillator has just started and is not yet
stable.
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
“Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control register (T1CON). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEP instruction will be ignored.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEP instruction or a very
long delay may occur while the Timer1
oscillator starts.
3.3.1.1
System Clock Selection and the
FOSC2 Configuration Bit
The SCS bits are cleared on all forms of Reset. In the
device’s default configuration, this means the primary
oscillator defined by FOSC (that is, one of the HS
or EC modes) is used as the primary clock source on
device Resets.
The default clock configuration on Reset can be
changed with the FOSC2 Configuration bit. This bit
determines whether the external or internal oscillator
will be the default clock source on subsequent device
Resets. By extension, it also has the effect of determining the clock source selected when SCS are in
their Reset state (= 00). When FOSC2 = 1 (default), the
oscillator source defined by FOSC is selected
whenever SCS = 00. When FOSC2 = 0, the
internal oscillator block is selected whenever
SCS = 00.
In those cases when the internal oscillator block is the
default clock on Reset, the Fast RC oscillator
(INTOSC) will be used as the device clock source. It will
initially start at 1 MHz; the postscaler selection that
corresponds to the Reset value of the IRCF bits
(‘100’).
Regardless of the setting of FOSC2, INTRC will always
be enabled on device power-up. It serves as the clock
source until the device has loaded its configuration
values from memory. It is at this point that the FOSC
Configuration bits are read and the oscillator selection
of the operational mode is made.
Note that either the primary clock or the internal
oscillator will have two bit setting options for the
possible values of SCS, at any given time,
depending on the setting of FOSC2.
3.3.2
OSCILLATOR TRANSITIONS
PIC18F85J11 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 4.1.2 “Entering Power-Managed Modes”.
DS39774D-page 38
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
3.4
External Oscillator Modes
3.4.1
TABLE 3-2:
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS (HS MODES)
In HS or HSPLL Oscillator modes, a crystal or ceramic
resonator is connected to the OSC1 and OSC2 pins to
establish oscillation. Figure 3-2 shows the pin
connections.
The oscillator design requires the use of a parallel
resonant crystal.
Note:
Use of a series resonant crystal may give a
frequency out of the crystal manufacturer’s
specifications.
TABLE 3-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Typical Capacitor Values Used:
Mode
Freq.
OSC1
OSC2
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Capacitor values are for design guidance only.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application. Refer
to the following application notes for oscillator-specific
information:
• AN588, “PIC® Microcontroller Oscillator Design
Guide”
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC® and PIC® Devices”
• AN849, “Basic PIC® Oscillator Design”
• AN943, “Practical PIC® Oscillator Analysis and
Design”
• AN949, “Making Your Oscillator Work”
See the notes following Table 3-2 for additional
information.
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Typical Capacitor Values
Tested:
Crystal
Freq.
Osc Type
HS
C1
C2
4 MHz
27 pF
27 pF
8 MHz
22 pF
22 pF
20 MHz
15 pF
15 pF
Capacitor values are for design guidance only.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
Refer to the Microchip application notes cited in
Table 3-1 for oscillator-specific information. Also see
the notes following this table for additional
information.
Note 1: Higher capacitance increases the
stability of the oscillator but also
increases the start-up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
3: Rs may be required to avoid overdriving
crystals with low drive level specification.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
FIGURE 3-2:
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS OR HSPLL
CONFIGURATION)
C1(1)
OSC1
XTAL
RF(3)
OSC2
C2(1)
2010 Microchip Technology Inc.
To
Internal
Logic
RS(2)
Sleep
PIC18F85J11
Note 1:
See Table 3-1 and Table 3-2 for initial values of
C1 and C2.
2:
A series resistor (RS) may be required for AT
strip cut crystals.
3:
RF varies with the oscillator mode chosen.
DS39774D-page 39
PIC18F85J11 FAMILY
3.4.2
EXTERNAL CLOCK INPUT
(EC MODES)
The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-3:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
OSC1/CLKI
Clock from
Ext. System
3.4.3
PLL FREQUENCY MULTIPLIER
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator. For these
reasons, the HSPLL and ECPLL modes are available.
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external oscillating source to produce frequencies up to 40 MHz. The
PLL is enabled by programming the FOSC
Configuration bits (CONFIG2L) to either ‘110’ (for
ECPLL) or ‘100’ (for HSPLL). In addition, the PLLEN bit
(OSCTUNE) must also be set. Clearing PLLEN
disables the PLL, regardless of the chosen oscillator
configuration. It also allows additional flexibility for
controlling the application’s clock speed in software.
PIC18F85J11
FOSC/4
or RA6
OSC2/CLKO
FIGURE 3-5:
PLL BLOCK DIAGRAM
HSPLL or ECPLL (CONFIG2L)
PLL Enable (OSCTUNE)
FIGURE 3-4:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
OSC1
Clock from
Ext. System
PIC18F85J11
Open
DS39774D-page 40
OSC2
(HS Mode)
OSC2
HS or EC
OSC1 Mode
FIN
FOUT
Phase
Comparator
Loop
Filter
4
VCO
MUX
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-4. In
this configuration, the divide-by-4 output on OSC2 is
not available.
SYSCLK
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
3.5
Internal Oscillator Block
The PIC18F85J11 family of devices includes an internal
oscillator block which generates two different clock
signals; either can be used as the microcontroller’s clock
source. This may eliminate the need for an external
oscillator circuit on the OSC1 and/or OSC2 pins.
The main output is the Fast RC oscillator, or INTOSC,
an 8 MHz clock source which can be used to directly
drive the device clock. It also drives a postscaler which
can provide a range of clock frequencies from 31 kHz
to 4 MHz. INTOSC is enabled when a clock frequency
from 125 kHz to 8 MHz is selected. The INTOSC output can also be enabled when 31 kHz is selected,
depending on the INTSRC bit (OSCTUNE).
The other clock source is the Internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source. It is also enabled automatically when any of the
following are enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 23.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTOSC
with postscaler or INTRC direct) is selected by configuring the IRCF bits of the OSCCON register. The
default frequency on device Resets is 1 MHz.
3.5.1
OSC1 AND OSC2 PIN
CONFIGURATION
Whenever the internal oscillator is configured as the
default clock source (FOSC2 = 0), the OSC1 and OSC2
pins are reconfigured automatically as port pins, RA6
and RA7. In this mode, they function as general digital
I/O. All oscillator functions on the pins are disabled.
3.5.2
INTERNAL OSCILLATOR OUTPUT
FREQUENCY AND TUNING
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8 MHz. It
can be adjusted in the user’s application by writing to
TUN (OSCTUNE) in the OSCTUNE
register (Register 3-2).
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. The
oscillator will stabilize within 1 ms. Code execution
continues during this shift. There is no indication that
the shift has occurred.
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC or vice versa. The frequency of
INTRC is not affected by OSCTUNE.
2010 Microchip Technology Inc.
3.5.3
INTOSC FREQUENCY DRIFT
The INTOSC frequency may drift as VDD or temperature changes, and can affect the controller operation in
a variety of ways. It is possible to adjust the INTOSC
frequency by modifying the value in the OSCTUNE
register. This will have no effect on the INTRC clock
source frequency.
Tuning INTOSC requires knowing when to make the
adjustment, in which direction it should be made, and in
some cases, how large a change is needed. Three
compensation techniques are shown here.
3.5.3.1
Compensating with the EUSART
An adjustment may be required when the EUSART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high. To
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low. To
compensate, increment OSCTUNE to increase the
clock frequency.
3.5.3.2
Compensating with the Timers
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is much greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
3.5.3.3
Compensating with the CCP Module
in Capture Mode
A CCP module can use free-running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast. To compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow. To compensate, increment the OSCTUNE
register.
DS39774D-page 41
PIC18F85J11 FAMILY
3.6
Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In RC_RUN and RC_IDLE modes, the internal oscillator provides the device clock source. The 31 kHz
INTRC output can be used directly to provide the clock
and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 23.2 “Watchdog Timer (WDT)” through
Section 23.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
TABLE 3-3:
Timer1 oscillator may be operating to support a RealTime Clock (RTC). Other features may be operating
that do not require a device clock source (i.e., MSSP
slave, PSP, INTn pins and others). Peripherals that
may add significant current consumption are listed in
Section 26.2 “DC Characteristics: Power-Down and
Supply Current”.
3.7
Power-up Delays
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applications. The delays ensure that the device is kept in
Reset until the device power supply is stable under normal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 5.6 “Power-up Timer (PWRT)”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 26-12). It is always enabled.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS modes). The OST does
this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
There is a delay of interval TCSD (parameter 38,
Table 26-12), following POR, while the controller
becomes ready to execute instructions.
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode
OSC1 Pin
OSC2 Pin
EC, ECPLL
Floating, pulled by external clock
At logic low (clock/4 output)
HS, HSPLL
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
INTOSC
I/O pin, RA6, direction controlled by
TRISA
I/O pin, RA7, direction controlled by
TRISA
Note:
See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.
DS39774D-page 42
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
4.0
POWER-MANAGED MODES
4.1.1
CLOCK SOURCES
The PIC18F85J11 family devices provide the ability to
manage power consumption by simply managing clocking to the CPU and the peripherals. In general, a lower
clock frequency and a reduction in the number of circuits
being clocked constitutes lower consumed power. For
the sake of managing power in an application, there are
three primary modes of operation:
The SCS bits allow the selection of one of three
clock sources for power-managed modes. They are:
• Run mode
• Idle mode
• Sleep mode
4.1.2
These modes define which portions of the device are
clocked and at what speed. The Run and Idle modes
may use any of the three available clock sources
(primary, secondary or internal oscillator block); the
Sleep mode does not use a clock source.
The power-managed modes include several
power-saving features offered on previous PIC®
MCUs. One is the clock switching feature, offered in
other PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC MCUs,
where all device clocks are stopped.
4.1
Selecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions: if the CPU is to be clocked or not and which
clock source is to be used. The IDLEN bit
(OSCCON) controls CPU clocking, while the
SCS bits (OSCCON) select the clock
source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table 4-1.
TABLE 4-1:
ENTERING POWER-MANAGED
MODES
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 4.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
POWER-MANAGED MODES
OSCCON bits
Mode
• the primary clock, as defined by the FOSC
Configuration bits
• the secondary clock (Timer1 oscillator)
• the internal oscillator
(1)
IDLEN
Module Clocking
Available Clock and Oscillator Source
SCS
CPU
Peripherals
0
N/A
Off
Off
PRI_RUN
N/A
10
Clocked
Clocked
Primary – HS, EC, HSPLL, ECPLL;
this is the normal, full-power execution mode
SEC_RUN
N/A
01
Clocked
Clocked
Secondary – Timer1 Oscillator
RC_RUN
N/A
11
Clocked
Clocked
Internal Oscillator
PRI_IDLE
1
10
Off
Clocked
Primary – HS, EC, HSPLL, ECPLL
SEC_IDLE
1
01
Off
Clocked
Secondary – Timer1 Oscillator
RC_IDLE
1
11
Off
Clocked
Internal Oscillator
Sleep
Note 1:
None – All clocks are disabled
IDLEN reflects its value when the SLEEP instruction is executed.
2010 Microchip Technology Inc.
DS39774D-page 43
PIC18F85J11 FAMILY
4.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Two bits indicate the current clock source and its
status:
OSTS
(OSCCON)
and
T1RUN
(T1CON). In general, only one of these bits will be
set while in a given power-managed mode. When the
OSTS bit is set, the primary clock is providing the
device clock. When the T1RUN bit is set, the Timer1
oscillator is providing the clock. If neither of these bits
is set, INTRC is clocking the device.
Note:
4.1.4
Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
DS39774D-page 44
4.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
4.2.1
PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 23.4 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set (see
Section 3.2 “Control Registers”).
4.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.
SEC_RUN mode is entered by setting the SCS
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 4-1), the primary oscillator is shut down, the T1RUN bit (T1CON) is set and
the OSTS bit is cleared.
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
Note:
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 4-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up; the Timer1
oscillator continues to run.
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started. In such situations, initial oscillator operation is far from
stable and unpredictable operation may
result.
FIGURE 4-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
1
T1OSI
2
3
n-1
Q3
Q4
Q1
Q2
Q3
n
Clock Transition
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
FIGURE 4-2:
PC
PC + 2
PC + 4
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
2
n-1 n
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC
SCS bits Changed
PC + 4
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2010 Microchip Technology Inc.
DS39774D-page 45
PIC18F85J11 FAMILY
4.2.3
RC_RUN MODE
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 4-4). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conservation of all the Run modes while still executing code.
It works well for user applications which are not highly
timing-sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting SCS bits to ‘11’. When
the clock source is switched to the INTRC (see
Figure 4-3), the primary oscillator is shut down and the
OSTS bit is cleared.
FIGURE 4-3:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
1
INTRC
2
3
n-1
Q3
Q4
Q1
Q2
Q3
n
Clock Transition
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
FIGURE 4-4:
PC
PC + 2
PC + 4
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q1
Q2
Q3
Q4
Q2 Q3 Q4 Q1 Q2 Q3
Q1
INTRC
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
2
n-1 n
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC
SCS bits Changed
PC + 4
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39774D-page 46
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
4.3
Sleep Mode
4.4
The power-managed Sleep mode is identical to the
legacy Sleep mode offered in all other PIC microcontrollers. It is entered by clearing the IDLEN bit (the
default state on device Reset) and executing the
SLEEP instruction. This shuts down the selected
oscillator (Figure 4-5). All clock source status bits are
cleared.
Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS bits
becomes ready (see Figure 4-6), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor is enabled (see
Section 23.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 26-12) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS bits.
FIGURE 4-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
FIGURE 4-6:
PC + 2
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
OSC1
TOST(1)
PLL Clock
Output
TPLL(1)
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
PC + 2
PC + 4
PC + 6
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2010 Microchip Technology Inc.
DS39774D-page 47
PIC18F85J11 FAMILY
4.4.1
PRI_IDLE MODE
4.4.2
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing-sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN
first, then set the SCS bits to ‘10’ and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC Configuration bits. The OSTS bit
remains set (see Figure 4-7).
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set IDLEN first, then
set SCS to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscillator, the
primary oscillator is shut down, the OSTS bit is cleared
and the T1RUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 4-8).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code execution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 4-8).
FIGURE 4-7:
SEC_IDLE MODE
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q1
Q4
Q3
Q2
Q1
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
FIGURE 4-8:
PC
PC + 2
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Q2
Q3
Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
DS39774D-page 48
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
4.4.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator.
This mode allows for controllable power conservation
during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTRC, the primary oscillator
is shut down and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC. After a delay of TCSD
following the wake event, the CPU begins executing
code being clocked by the INTOSC. The IDLEN and
SCS bits are not affected by the wake-up. The INTOSC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
4.5
Exiting Idle and Sleep Modes
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
mode sections (see Section 4.2 “Run Modes”,
Section 4.3 “Sleep Mode” and Section 4.4 “Idle
Modes”).
4.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON) is set. Otherwise, code
execution continues or resumes without branching
(see Section 10.0 “Interrupts”).
4.5.2
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 4.2 “Run
Modes” and Section 4.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 23.2 “Watchdog
Timer (WDT)”).
The Watchdog Timer and postscaler are cleared by one
of the following events:
• executing a SLEEP or CLRWDT instruction
• the loss of a currently selected clock source (if the
Fail-Safe Clock Monitor is enabled)
4.5.3
EXIT BY RESET
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
4.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped; and
• the primary clock source is either the EC or
ECPLL mode.
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC). However, a
fixed delay of interval TCSD following the wake event is
still required when leaving Sleep and Idle modes to
allow the CPU to prepare for execution. Instruction
execution resumes on the first clock cycle following this
delay.
A fixed delay of interval TCSD following the wake event
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
2010 Microchip Technology Inc.
DS39774D-page 49
PIC18F85J11 FAMILY
NOTES:
DS39774D-page 50
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
5.0
RESET
5.1
The PIC18F85J11 family of devices differentiate
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 5.7 “Reset State of Registers”.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 10.0 “Interrupts”.
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.6.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 23.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 5-1.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
External Reset
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
VDD
POR Pulse
Brown-out
Reset(1)
S
PWRT
32 s
PWRT
INTRC
Note 1:
65.5 ms
11-Bit Ripple Counter
Chip_Reset
R
Q
The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip
voltage regulator when there is insufficient source voltage to maintain regulation.
2010 Microchip Technology Inc.
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PIC18F85J11 FAMILY
REGISTER 5-1:
RCON: RESET CONTROL REGISTER
R/W-0
U-0
R/W-1
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
—
CM
RI
TO
PD
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16XXXX Compatibility mode)
bit 6
Unimplemented: Read as ‘0’
bit 5
CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has not occurred
0 = A Configuration Mismatch Reset has occurred. Must be set in software once the Reset occurs.
bit 4
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3
TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2
PD: Power-Down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1
POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section 5.4.1 “Detecting
BOR” for more information.
3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).
DS39774D-page 52
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
5.2
Master Clear (MCLR)
FIGURE 5-2:
The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR Reset path
which detects and ignores small pulses.
5.3
D
C
Power-on Reset events are captured by the POR bit
(RCON). The state of the bit is set to ‘0’ whenever
a Power-on Reset occurs; it does not change for any
other Reset event. POR is not reset to ‘1’ by any
hardware event. To capture multiple events, the user
manually resets the bit to ‘1’ in software following any
Power-on Reset.
5.4
Brown-out Reset (BOR)
The PIC18F85J11 family of devices incorporates a
simple BOR function when the internal regulator is
enabled (ENVREG pin is tied to VDD). The voltage regulator will trigger a Brown-out Reset when output of the
regulator to the device core approaches the voltage at
which the device is unable to run at full speed. The
BOR circuit also keeps the device in Reset as VDD
rises, until the regulator’s output level is sufficient for
full-speed operation.
MCLR
PIC18F85J11
Note 1:
External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2:
R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3:
R1 1 k will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k to 10 k) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004). For a slow rise
time, see Figure 5-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
R
R1
Power-on Reset (POR)
A Power-on Reset condition is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
VDD
VDD
The MCLR pin is not driven low by any internal Resets,
including the WDT.
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
5.4.1
DETECTING BOR
The BOR bit always resets to ‘0’ on any Brown-out
Reset or Power-on Reset event. This makes it difficult
to determine if a Brown-out Reset event has occurred
just by reading the state of BOR alone. A more reliable
method is to simultaneously check the state of both
POR and BOR. This assumes that the POR bit is reset
to ‘1’ in software immediately after any Power-on Reset
event. If BOR is ‘0’ while POR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
If the voltage regulator is disabled, Brown-out Reset
functionality is disabled. In this case, the BOR bit
cannot be used to determine a Brown-out Reset event.
The BOR bit is still cleared by a Power-on Reset event.
Once a BOR has occurred, the Power-up Timer will
keep the chip in Reset for TPWRT (parameter 33). If
VDD drops below the threshold for full-speed operation
while the Power-up Timer is running, the chip will go
back into a Brown-out Reset and the Power-up Timer
will be initialized. Once VDD rises to the point where
regulator output is sufficient, the Power-up Timer will
execute the additional time delay.
2010 Microchip Technology Inc.
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PIC18F85J11 FAMILY
5.5
Configuration Mismatch (CM)
5.6
The Configuration Mismatch (CM) Reset is designed to
detect and attempt to recover from random, memory
corrupting events. These include Electrostatic Discharge (ESD) events, which can cause widespread,
single bit changes throughout the device and result in
catastrophic failure.
In PIC18FXXJXX Flash devices, the device Configuration registers (located in the configuration memory
space) are continuously monitored during operation by
comparing their values to complimentary Shadow
registers.
If a mismatch is detected between the two sets of registers, a CM Reset automatically occurs. These events
are captured by the CM bit (RCON) being set to ‘0’.
This bit does not change for any other Reset event.
A CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT time-out or Stack Event
Resets. As with all hard and power Reset events, the
device Configuration Words are reloaded from the
Flash Configuration Words in program memory as the
device restarts.
Power-up Timer (PWRT)
PIC18F85J11 family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is always enabled. The
main function is to ensure that the device voltage is
stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F85J11 family devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32 µs = 65.6 ms. While the
PWRT is counting, the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 for details.
5.6.1
TIME-OUT SEQUENCE
If enabled, the PWRT time-out is invoked after the POR
pulse has cleared. The total time-out will vary based on
the status of the PWRT. Figure 5-3, Figure 5-4,
Figure 5-5 and Figure 5-6 all depict time-out
sequences on power-up with the Power-up Timer
enabled.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR high will begin execution immediately
(Figure 5-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXXXX device
operating in parallel.
FIGURE 5-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
DS39774D-page 54
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 5-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 5-5:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 5-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
3.3V
VDD
0V
1V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
2010 Microchip Technology Inc.
DS39774D-page 55
PIC18F85J11 FAMILY
5.7
Reset State of Registers
Table 5-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, CM, RI,
TO, PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 5-1.
These bits are used in software to determine the nature
of the Reset.
TABLE 5-1:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
RCON Register
STKPTR Register
Program
Counter(1)
CM
RI
TO
PD
POR
BOR
Power-on Reset
0000h
1
1
1
1
0
0
0
0
RESET Instruction
0000h
u
0
u
u
u
u
u
u
Brown-out Reset
0000h
1
1
1
1
u
0
u
u
MCLR during power-managed
Run modes
0000h
u
u
1
u
u
u
u
u
MCLR during power-managed
Idle modes and Sleep mode
0000h
u
u
1
0
u
u
u
u
WDT time-out during full power
or power-managed Run modes
0000h
u
u
0
u
u
u
u
u
MCLR during full-power
execution
0000h
u
u
u
u
u
u
u
u
Stack Full Reset (STVREN = 1)
0000h
u
u
u
u
u
u
1
u
Stack Underflow Reset
(STVREN = 1)
0000h
u
u
u
u
u
u
u
1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
u
u
u
u
u
u
u
1
WDT time-out during
power-managed Idle or Sleep
modes
PC + 2
u
u
0
0
u
u
u
u
Interrupt exit from
power-managed modes
PC + 2
u
u
u
0
u
u
u
u
Condition
STKFUL STKUNF
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
DS39774D-page 56
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 5-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
TOSU
PIC18F6XJ11 PIC18F8XJ11
---0 0000
---0 0000
---0 uuuu(1)
TOSH
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu(1)
TOSL
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu(1)
STKPTR
PIC18F6XJ11 PIC18F8XJ11
uu-0 0000
00-0 0000
uu-u uuuu(1)
PCLATU
PIC18F6XJ11 PIC18F8XJ11
---0 0000
---0 0000
---u uuuu
PCLATH
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
PCL
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
PC + 2(2)
TBLPTRU
PIC18F6XJ11 PIC18F8XJ11
--00 0000
--00 0000
--uu uuuu
TBLPTRH
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
TABLAT
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
PRODH
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
PIC18F6XJ11 PIC18F8XJ11
0000 000x
0000 000u
uuuu uuuu(3)
INTCON2
PIC18F6XJ11 PIC18F8XJ11
1111 1111
1111 1111
uuuu uuuu(3)
INTCON3
PIC18F6XJ11 PIC18F8XJ11
1100 0000
1100 0000
uuuu uuuu(3)
INDF0
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
Register
Wake-up via WDT
or Interrupt
POSTINC0
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
POSTDEC0
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
PREINC0
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
PLUSW0
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
FSR0H
PIC18F6XJ11 PIC18F8XJ11
---- xxxx
---- uuuu
---- uuuu
FSR0L
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
POSTINC1
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
POSTDEC1
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
PREINC1
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
PLUSW1
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
2010 Microchip Technology Inc.
DS39774D-page 57
PIC18F85J11 FAMILY
TABLE 5-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
FSR1H
PIC18F6XJ11 PIC18F8XJ11
---- xxxx
---- uuuu
---- uuuu
FSR1L
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
PIC18F6XJ11 PIC18F8XJ11
---- 0000
---- 0000
---- uuuu
INDF2
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
POSTINC2
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
Register
Wake-up via WDT
or Interrupt
POSTDEC2
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
PREINC2
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
PLUSW2
PIC18F6XJ11 PIC18F8XJ11
N/A
N/A
N/A
FSR2H
PIC18F6XJ11 PIC18F8XJ11
---- xxxx
---- uuuu
---- uuuu
FSR2L
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
PIC18F6XJ11 PIC18F8XJ11
---x xxxx
---u uuuu
---u uuuu
TMR0H
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
TMR0L
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
PIC18F6XJ11 PIC18F8XJ11
1111 1111
1111 1111
uuuu uuuu
OSCCON
PIC18F6XJ11 PIC18F8XJ11
0100 q000
0100 q000
uuuu quuu
WDTCON
PIC18F6XJ11 PIC18F8XJ11
0--- ---0
0--- ---0
u--- ---u
RCON(4)
PIC18F6XJ11 PIC18F8XJ11
0-11 11q0
0-uq qquu
u-uu qquu
TMR1H
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
PIC18F6XJ11 PIC18F8XJ11
0000 0000
u0uu uuuu
uuuu uuuu
TMR2
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
PR2
PIC18F6XJ11 PIC18F8XJ11
1111 1111
1111 1111
1111 1111
T2CON
PIC18F6XJ11 PIC18F8XJ11
-000 0000
-000 0000
-uuu uuuu
SSPBUF
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
SSPCON1
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
SSPCON2
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
DS39774D-page 58
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 5-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
PIC18F6XJ11 PIC18F8XJ11
0-00 0000
0-00 0000
u-uu uuuu
ADCON1
PIC18F6XJ11 PIC18F8XJ11
--00 0000
--00 0000
--uu uuuu
ADCON2
PIC18F6XJ11 PIC18F8XJ11
0-00 0000
0-00 0000
u-uu uuuu
CVRCON
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
CMCON
PIC18F6XJ11 PIC18F8XJ11
0000 0111
0000 0111
uuuu uuuu
TMR3H
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
PIC18F6XJ11 PIC18F8XJ11
0000 0000
uuuu uuuu
uuuu uuuu
PSPCON
PIC18F6XJ11 PIC18F8XJ11
0000 ----
0000 ----
uuuu ----
SPBRG1
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
RCREG1
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
TXREG1
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
TXSTA1
PIC18F6XJ11 PIC18F8XJ11
0000 0010
0000 0010
uuuu uuuu
RCSTA1
PIC18F6XJ11 PIC18F8XJ11
0000 000x
0000 000x
uuuu uuuu
EECON2
PIC18F6XJ11 PIC18F8XJ11
---- ----
---- ----
---- ----
EECON1
PIC18F6XJ11 PIC18F8XJ11
---0 x00-
---0 u00-
---0 u00-
IPR3
PIC18F6XJ11 PIC18F8XJ11
--00 -11-
--00 -11-
--uu -uu-
PIR3
PIC18F6XJ11 PIC18F8XJ11
--00 -00-
--00 -00-
--uu -00-(3)
PIE3
PIC18F6XJ11 PIC18F8XJ11
--00 -00-
--00 -00-
--uu -00-
IPR2
PIC18F6XJ11 PIC18F8XJ11
11-- 111-
11-- 111-
uu-- uuu-
PIR2
PIC18F6XJ11 PIC18F8XJ11
00-- 000-
00-- 000-
uu-- uuu-(3)
PIE2
PIC18F6XJ11 PIC18F8XJ11
00-- 000-
00-- 000-
uu-- uuu-
IPR1
PIC18F6XJ11 PIC18F8XJ11
1111 1-11
1111 1-11
uuuu u-uu
PIR1
PIC18F6XJ11 PIC18F8XJ11
0000 0-00
0000 0-00
uuuu u-uu(3)
PIE1
PIC18F6XJ11 PIC18F8XJ11
0000 0-00
0000 0-00
uuuu u-uu
MEMCON
PIC18F6XJ11 PIC18F8XJ11
0-00 --00
0-00 --00
u-uu --uu
OSCTUNE
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
Register
ADRESH
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
2010 Microchip Technology Inc.
DS39774D-page 59
PIC18F85J11 FAMILY
TABLE 5-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
TRISJ
PIC18F6XJ11 PIC18F8XJ11
1111 1111
1111 1111
uuuu uuuu
TRISH
PIC18F6XJ11 PIC18F8XJ11
1111 1111
1111 1111
uuuu uuuu
TRISG
PIC18F6XJ11 PIC18F8XJ11
0001 1111
0001 1111
uuuu uuuu
TRISF
PIC18F6XJ11 PIC18F8XJ11
1111 111-
1111 111-
uuuu uuu-
TRISE
PIC18F6XJ11 PIC18F8XJ11
1111 1-11
1111 1-11
uuuu u-uu
TRISD
PIC18F6XJ11 PIC18F8XJ11
1111 1111
1111 1111
uuuu uuuu
TRISC
PIC18F6XJ11 PIC18F8XJ11
1111 1111
1111 1111
uuuu uuuu
TRISB
PIC18F6XJ11 PIC18F8XJ11
1111 1111
1111 1111
uuuu uuuu
TRISA(5)
PIC18F6XJ11 PIC18F8XJ11
1111 1111(5)
1111 1111(5)
uuuu uuuu(5)
LATJ
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATH
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATG
PIC18F6XJ11 PIC18F8XJ11
00-x xxxx
00-u uuuu
uu-u uuuu
LATF
PIC18F6XJ11 PIC18F8XJ11
xxxx xxx-
uuuu uuu-
uuuu uuu-
LATE
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATD
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
(5)
xxxx(5)
LATA
PIC18F6XJ11 PIC18F8XJ11
xxxx
PORTJ
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTH
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTG
PIC18F6XJ11 PIC18F8XJ11
000x xxxx
000u uuuu
000u uuuu
PORTF
PIC18F6XJ11 PIC18F8XJ11
xxxx xxx-
uuuu uuu-
uuuu uuu-
PORTE
PIC18F6XJ11 PIC18F8XJ11
xxxx x-xx
uuuu u-uu
uuuu u-uu
PORTD
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA(5)
PIC18F6XJ11 PIC18F8XJ11
xx0x 0000(5)
uu0u 0000(5)
uuuu uuuu(5)
SPBRGH1
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
BAUDCON1
PIC18F6XJ11 PIC18F8XJ11
0100 0-00
0100 0-00
uuuu u-uu
CCPR1H
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
PIC18F6XJ11 PIC18F8XJ11
--00 0000
--00 0000
--uu uuuu
uuuu
uuuu(5)
uuuu uuuu(5)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
DS39774D-page 60
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 5-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
CCPR2H
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
PIC18F6XJ11 PIC18F8XJ11
--00 0000
--00 0000
--uu uuuu
SPBRG2
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
RCREG2
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
TXREG2
PIC18F6XJ11 PIC18F8XJ11
0000 0000
0000 0000
uuuu uuuu
TXSTA2
PIC18F6XJ11 PIC18F8XJ11
0000 -010
0000 -010
uuuu -uuu
RCSTA2
PIC18F6XJ11 PIC18F8XJ11
0000 000x
0000 000x
uuuu uuuu
Register
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
2010 Microchip Technology Inc.
DS39774D-page 61
PIC18F85J11 FAMILY
NOTES:
DS39774D-page 62
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
6.0
MEMORY ORGANIZATION
There are two types of memory in PIC18 Flash
microcontroller devices:
• Program Memory
• Data RAM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for
concurrent access of the two memory spaces.
Additional detailed information on the operation of the
Flash program memory is provided in Section 7.0
“Flash Program Memory”.
FIGURE 6-1:
6.1
Program Memory Organization
PIC18 microcontrollers implement a 21-bit program
counter which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOP instruction).
The entire PIC18F85J11 family offers a range of
on-chip Flash program memory sizes, from 8 Kbytes
(up to 4,096 single-word instructions) to 32 Kbytes
(32,768 single-word instructions). The program
memory maps for individual family members are shown
in Figure 6-1.
MEMORY MAPS FOR PIC18F85J11 FAMILY DEVICES
PC
CALL, CALLW, RCALL,
RETURN, RETFIE, RETLW,
ADDULNK, SUBULNK
21
Stack Level 1
Stack Level 31
PIC18FX4J11
On-Chip
Memory
PIC18FX5J11
On-Chip
Memory
Config. Words
000000h
001FFFh
Config. Words
003FFFh
Config. Words
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
007FFFh
User Memory Space
PIC18FX3J11
On-Chip
Memory
1FFFFFh
Note:
Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.
2010 Microchip Technology Inc.
DS39774D-page 63
PIC18F85J11 FAMILY
6.1.1
HARD MEMORY VECTORS
6.1.2
FLASH CONFIGURATION WORDS
All PIC18 devices have a total of three hard-coded
return vectors in their program memory space. The
Reset vector address is the default value to which the
program counter returns on all device Resets; it is
located at 0000h.
Because PIC18F85J11 family devices do not have persistent configuration memory, the top four words of
on-chip program memory are reserved for configuration
information. On Reset, the configuration information is
copied into the Configuration registers.
PIC18 devices also have two interrupt vector
addresses for the handling of high-priority and
low-priority interrupts. The high-priority interrupt vector
is located at 0008h and the low-priority interrupt vector
is at 0018h. Their locations in relation to the program
memory map are shown in Figure 6-2.
The Configuration Words are stored in their program
memory location in numerical order, starting with the
lower byte of CONFIG1 at the lowest address and ending with the upper byte of CONFIG4. For these devices,
only Configuration Words, CONFIG1 through
CONFIG3, are used; CONFIG4 is reserved. The actual
addresses of the Flash Configuration Word for devices
in the PIC18F85J11 family are shown in Table 6-1.
Their location in the memory map is shown with the
other memory vectors in Figure 6-2.
FIGURE 6-2:
HARD VECTOR AND
CONFIGURATION WORD
LOCATIONS FOR
PIC18F85J11 FAMILY
FAMILY DEVICES
Reset Vector
0000h
High-Priority Interrupt Vector
0008h
Low-Priority Interrupt Vector
0018h
Additional details on the device Configuration Words
are provided in Section 23.1 “Configuration Bits”.
TABLE 6-1:
Device
PIC18F63J11
On-Chip
Program Memory
PIC18F83J11
PIC18F64J11
PIC18F84J11
PIC18F65J11
PIC18F85J11
Flash Configuration Words
FLASH CONFIGURATION
WORD FOR PIC18F85J11
FAMILY DEVICES
Program
Memory
(Kbytes)
Configuration
Word
Addresses
8
1FF8h to 1FFFh
16
3FF8h to 3FFFh
32
7FF8h to 7FFFh
(Top of Memory-7)
(Top of Memory)
Read as ‘0’
1FFFFFh
Legend:
(Top of Memory) represents upper boundary
of on-chip program memory space (see
Figure 6-1 for device-specific values).
Shaded area represents unimplemented
memory. Areas are not shown to scale.
DS39774D-page 64
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
6.1.3
PIC18F8XJ11 PROGRAM MEMORY
MODES
The 80-pin devices in this family can address up to a
total of 2 Mbytes of program memory. This is achieved
through the external memory bus. There are two
distinct operating modes available to the controllers:
• Microcontroller (MC)
• Extended Microcontroller (EMC)
The Program Memory mode is determined by setting
the EMB Configuration bits (CONFIG3L), as
shown in Register 6-1. (See also Section 23.1
“Configuration Bits” for additional details on the
device Configuration bits.)
The Program Memory modes operate as follows:
• The Microcontroller Mode accesses only on-chip
Flash memory. Attempts to read above the top of
on-chip memory causes a read of all ‘0’s (a NOP
instruction).
• The Extended Microcontroller Mode allows
access to both internal and external program
memories as a single block. The device can
access its entire on-chip program memory; above
this, the device accesses external program
memory up to the 2-Mbyte program space limit.
Execution automatically switches between the
two memories as required.
The setting of the EMB Configuration bits also controls
the address bus width of the external memory bus. This
is covered in more detail in Section 8.0 “External
Memory Bus”.
In all modes, the microcontroller has complete access
to data RAM.
Figure 6-3 compares the memory maps of the different
Program Memory modes. The differences between
on-chip and external memory access limitations are
more fully explained in Table 6-2.
The Microcontroller mode is also the only operating
mode available to 64-pin devices.
REGISTER 6-1:
CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1)
R/WO-1
R/WO-1
R/WO-1
R/WO-1
R/WO-1
U-0
U-0
U-0
WAIT
BW
EMB1
EMB0
EASHFT
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
-n = Value when device is unprogrammed
bit 7
bit 6
bit 5:4
bit 3
bit 2-0
Note 1:
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
WAIT: External Bus Wait Enable bit
1 = Wait selections from WAIT (MEMCON) are unavailable and the device will not wait
0 = Wait is programmed by WAIT (MEMCON)
BW: Data Bus Width Select bit
1 = 16-Bit External Bus mode
0 = 8-Bit External Bus mode
EMB: External Memory Bus Configuration bits
00 = Extended Microcontroller mode – 20-Bit Address mode
01 = Extended Microcontroller mode – 16-Bit Address mode
10 = Extended Microcontroller mode – 12-Bit Address mode
11 = Microcontroller mode – external bus disabled
EASHFT: External Address Bus Shift Enable bit
1 = Address shifting enabled – external address bus is shifted to start at 000000h
0 = Address shifting disabled – external address bus reflects the PC value
Unimplemented: Read as ‘0’
CONFIG3L and its associated bits are implemented only in 80-pin devices.
2010 Microchip Technology Inc.
DS39774D-page 65
PIC18F85J11 FAMILY
6.1.4
EXTENDED MICROCONTROLLER
MODE AND ADDRESS SHIFTING
To avoid this, the Extended Microcontroller mode
implements an address shifting option to enable automatic address translation. In this mode, addresses
presented on the external bus are shifted down by the
size of the on-chip program memory and are remapped
to start at 0000h. This allows the complete use of the
external memory device’s memory space.
By default, devices in Extended Microcontroller mode
directly present the program counter value on the
external address bus for those addresses in the range
of the external memory space. In practical terms, this
means addresses in the external memory device below
the top of on-chip memory are unavailable.
FIGURE 6-3:
MEMORY MAPS FOR PIC18F85J11 FAMILY PROGRAM MEMORY MODES
Microcontroller Mode(1)
On-Chip
Memory
Space
Extended Microcontroller Mode(2)
External
Memory
Space
(Top of Memory)
(Top of Memory) + 1
External
Memory
(Top of Memory)
(Top of Memory) + 1
External
Memory
Mapped
to
External
Memory 1FFFFFh –
Space (Top of Memory)
Mapped
to
External
Memory
Space
1FFFFFh
1FFFFFh
1FFFFFh
Note 1:
2:
000000h
On-Chip
Program
Memory
On-Chip
Program
Memory
(Top of Memory)
(Top of Memory) + 1
Legend:
On-Chip
Memory
Space
000000h
No
Access
Reads
‘0’s
External
Memory
Space
On-Chip
Memory
Space
000000h
On-Chip
Program
Memory
Extended Microcontroller Mode
with Address Shifting(2)
(Top of Memory) represents upper boundary of on-chip program memory space (see Figure 6-1 for device-specific
values). Shaded areas represent unimplemented, or inaccessible areas, depending on the mode.
This mode is the only available mode on 64-pin devices and the default mode on 80-pin devices.
These modes are only available on 80-pin devices.
TABLE 6-2:
MEMORY ACCESS FOR PIC18F8XJ11 PROGRAM MEMORY MODES
Internal Program Memory
Operating Mode
External Program Memory
Execution
From
Table Read
From
Table Write
To
Execution
From
Table Read
From
Table Write
To
Microcontroller
Yes
Yes
Yes
No Access
No Access
No Access
Extended Microcontroller
Yes
Yes
Yes
Yes
Yes
Yes
DS39774D-page 66
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
6.1.5
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 6.1.8.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
6.1.6
RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW or
a RETFIE instruction (and on ADDULNK and SUBULNK
instructions if the extended instruction set is enabled).
PCLATU and PCLATH are not affected by any of the
RETURN or CALL instructions.
FIGURE 6-4:
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
Top-of-Stack Special Function Registers. Data can also
be pushed to, or popped from the stack, using these
registers.
A CALL type instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
6.1.6.1
Top-of-Stack Access
Only the top of the return address stack (TOS) is
readable and writable. A set of three registers,
TOSU:TOSH:TOSL, holds the contents of the stack
location pointed to by the STKPTR register
(Figure 6-4). This allows users to implement a software
stack if necessary. After a CALL, RCALL or interrupt
(and ADDULNK and SUBULNK instructions if the
extended instruction set is enabled), the software can
read
the
pushed
value
by
reading
the
TOSU:TOSH:TOSL registers. These values can be
placed on a user-defined software stack. At return time,
the software can return these values to
TOSU:TOSH:TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
Top-of-Stack Registers
TOSU
00h
TOSH
1Ah
TOSL
34h
Top-of-Stack
2010 Microchip Technology Inc.
11111
11110
11101
001A34h
000D58h
Stack Pointer
STKPTR
00010
00011
00010
00001
00000
DS39774D-page 67
PIC18F85J11 FAMILY
6.1.6.2
Return Stack Pointer (STKPTR)
The STKPTR register (Register 6-2) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to
Section 23.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.
REGISTER 6-2:
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and set the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
Note:
6.1.6.3
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack, without disturbing normal program execution, is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
STKPTR: STACK POINTER REGISTER
R/C-0
R/C-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STKFUL(1)
STKUNF(1)
—
SP4
SP3
SP2
SP1
SP0
bit 7
bit 0
Legend:
C = Clearable-only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
STKFUL: Stack Full Flag bit(1)
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6
STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP: Stack Pointer Location bits
Note 1:
x = Bit is unknown
Bit 7 and bit 6 are cleared by user software or by a POR.
DS39774D-page 68
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
6.1.6.4
Stack Full and Underflow Resets
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 1L. When STVREN is set, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
6.1.7
FAST REGISTER STACK
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers to provide a “fast return”
option for interrupts. This stack is only one level deep
and is neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push values into the Stack registers. The values in
the registers are then loaded back into the working
registers if the RETFIE, FAST instruction is used to
return from the interrupt.
6.1.8
LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
6.1.8.1
Computed GOTO
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 6-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
If both low and high-priority interrupts are enabled, the
Stack registers cannot be used reliably to return from
low-priority interrupts. If a high-priority interrupt occurs
while servicing a low-priority interrupt, the Stack
register values stored by the low-priority interrupt will
be overwritten. In these cases, users must save the key
registers in software during a low-priority interrupt.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FAST instruction is then executed to restore
these registers from the Fast Register Stack.
EXAMPLE 6-2:
Example 6-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
EXAMPLE 6-1:
CALL SUB1, FAST
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
RETURN FAST
SUB1
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
2010 Microchip Technology Inc.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
ORG
TABLE
6.1.8.2
MOVF
CALL
nn00h
ADDWF
RETLW
RETLW
RETLW
.
.
.
COMPUTED GOTO USING
AN OFFSET VALUE
OFFSET, W
TABLE
PCL
nnh
nnh
nnh
Table Reads
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per
program word while programming. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from the
program memory. Data is transferred from program
memory one byte at a time.
Table read operation is discussed further
Section 7.1 “Table Reads and Table Writes”.
in
DS39774D-page 69
PIC18F85J11 FAMILY
6.2
PIC18 Instruction Cycle
6.2.1
6.2.2
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction
cycle, while the decode and execute take another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to change (e.g.,
GOTO), then two cycles are required to complete the
instruction (Example 6-3).
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the
Instruction Register (IR) during Q4. The instruction is
decoded and executed during the following Q1 through
Q4. The clocks and instruction execution flow are
shown in Figure 6-5.
FIGURE 6-5:
INSTRUCTION FLOW/PIPELINING
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
PC
PC + 2
PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC)
EXAMPLE 6-3:
1. MOVLW 55h
4. BSF
Execute INST (PC + 2)
Fetch INST (PC + 4)
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
Fetch 1
Execute 1
2. MOVWF PORTB
3. BRA
Execute INST (PC)
Fetch INST (PC + 2)
SUB_1
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
Fetch 2
TCY2
TCY3
TCY4
TCY5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush (NOP)
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS39774D-page 70
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
6.2.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). To maintain alignment
with instruction boundaries, the PC increments in steps
of 2 and the LSB will always read ‘0’ (see Section 6.1.5
“Program Counter”).
Figure 6-6 shows an example of how instruction words
are stored in the program memory.
FIGURE 6-6:
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruction. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC
which accesses the desired byte address in program
memory. Instruction #2 in Figure 6-6 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 25.0 “Instruction Set Summary”
provides further details of the instruction set.
INSTRUCTIONS IN PROGRAM MEMORY
LSB = 1
LSB = 0
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Program Memory
Byte Locations
6.2.4
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
Instruction 3:
MOVFF
123h, 456h
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
EXAMPLE 6-4:
Word Address
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 6-4 shows how this works.
Note:
See Section 6.5 “Program Memory and
the Extended Instruction Set” for
information on two-word instructions in the
extended instruction set.
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; No, skip this word
ADDWF
REG3
; continue code
1111 0100 0101 0110
0010 0100 0000 0000
; Execute this word as a NOP
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; Yes, execute this word
ADDWF
REG3
; continue code
1111 0100 0101 0110
0010 0100 0000 0000
2010 Microchip Technology Inc.
; 2nd word of instruction
DS39774D-page 71
PIC18F85J11 FAMILY
6.3
Note:
Data Memory Organization
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 6.6 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. The
PIC18FX3J11/X4J11 devices, with up to 16 Kbytes of
program memory, implement 4 complete banks for a
total of 1024 bytes. PIC18FX5J11 devices, with
32 Kbytes of program memory, implement 8 complete
banks for a total of 2048 bytes. Figure 6-7 and
Figure 6-8 show the data memory organization for the
devices.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
6.3.1
BANK SELECT REGISTER
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR). The upper four bits
are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLB instruction.
The value of the BSR indicates the bank in data
memory. The 8 bits in the instruction show the location
in the bank and can be thought of as an offset from the
bank’s lower boundary. The relationship between the
BSR’s value and the bank division in data memory is
shown in Figure 6-9.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
section.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 0Fh, will end up resetting the program counter.
To ensure that commonly used registers (select SFRs
and select GPRs) can be accessed in a single cycle,
PIC18 devices implement an Access Bank. This is a
256-byte memory space that provides fast access to
select SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 6.3.2 “Access Bank”
provides a detailed description of the Access RAM.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 6-7 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
DS39774D-page 72
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 6-7:
DATA MEMORY MAP FOR PIC18FX3J11/X4J11 DEVICES
When a = 0:
BSR
Data Memory Map
00h
= 0000
= 0001
= 0010
= 0011
Bank 0
FFh
00h
Bank 1
Access RAM
GPR
GPR
1FFh
200h
FFh
00h
Bank 2
GPR
FFh
00h
Bank 3
2FFh
300h
GPR
FFh
00h
= 0100
000h
05Fh
060h
0FFh
100h
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are general
purpose RAM (from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
When a = 1:
The BSR specifies the bank
used by the instruction.
3FFh
400h
Bank 4
Access Bank
Access RAM Low
= 1110
= 1111
5Fh
Access RAM High 60h
(SFRs)
FFh
Unused
Read as ‘0’
to
00h
Bank 14
FFh
00h
Unused
FFh
SFR
Bank 15
2010 Microchip Technology Inc.
EFFh
F00h
F5Fh
F60h
FFFh
DS39774D-page 73
PIC18F85J11 FAMILY
FIGURE 6-8:
DATA MEMORY MAP FOR PIC18FX5J11 DEVICES
When a = 0:
BSR
Data Memory Map
00h
= 0000
= 0001
= 0010
= 0011
= 0100
= 0101
= 0110
= 0111
Bank 0
FFh
00h
Bank 1
Access RAM
GPR
GPR
1FFh
200h
FFh
00h
Bank 2
GPR
FFh
00h
Bank 3
2FFh
300h
GPR
FFh
00h
Bank 4
= 1111
DS39774D-page 74
The second 160 bytes are
Special Function Registers
(from Bank 15).
When a = 1:
The BSR specifies the bank
used by the instruction.
3FFh
400h
4FFh
500h
GPR
Bank 5
FFh
00h
5FFh
600h
GPR
Bank 6
FFh
00h
6FFh
700h
GPR
Bank 7
7FFh
800h
Access Bank
Access RAM Low
00h
5Fh
Access RAM High 60h
(SFRs)
FFh
Bank 8
Unused
Read as ‘0’
to
= 1110
The first 96 bytes are general
purpose RAM (from Bank 0).
GPR
FFh
00h
FFh
00h
= 1000
000h
05Fh
060h
0FFh
100h
The BSR is ignored and the
Access Bank is used.
Bank 14
FFh
00h
Unused
FFh
SFR
Bank 15
EFFh
F00h
F5Fh
F60h
FFFh
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 6-9:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
BSR(1)
7
0
0
0
0
0
0
0
Bank Select(2)
1
0
000h
Data Memory
Bank 0
100h
Bank 1
200h
300h
Bank 2
00h
7
FFh
00h
1
From Opcode(2)
1
11
1
11
1
0
11
11
FFh
00h
FFh
00h
Bank 3
through
Bank 13
E00h
Bank 14
F00h
FFFh
Note 1:
2:
6.3.2
Bank 15
FFh
00h
FFh
00h
FFh
The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR)
to the registers of the Access Bank.
The MOVFF instruction embeds the entire 12-bit address in the instruction.
ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of data
memory, it also means that the user must always ensure
that the correct bank is selected. Otherwise, data may
be read from, or written to, the wrong location. This can
be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or
changing the BSR for each read or write to data memory
can become very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Bank 15. The lower half is known
as the “Access RAM” and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 6-7).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
2010 Microchip Technology Inc.
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 6.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
6.3.3
GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
DS39774D-page 75
PIC18F85J11 FAMILY
6.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
more than the top half of Bank 15 (F60h to FFFh). A list
of these registers is given in Table 6-3 and Table 6-4.
TABLE 6-3:
Address
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
SPECIAL FUNCTION REGISTER MAP FOR PIC18F85J11 FAMILY DEVICES
Name
Address
Name
Address
Name
Address
Name
Address
Name
FFFh
TOSU
FDFh
FBFh
—(2)
F9Fh
IPR1
F7Fh
SPBRGH1
FFEh
TOSH
FDEh POSTINC2(1)
FBEh
—(2)
F9Eh
PIR1
F7Eh
BAUDCON1
FFDh
TOSL
FDDh POSTDEC2(1)
FBDh
—(2)
F9Dh
PIE1
F7Dh
—(2)
FBCh
—(2)
F9Ch
MEMCON(3)
F7Ch
—(2)
FBBh
(2)
—
F9Bh
OSCTUNE
F7Bh
—(2)
FBAh
—(2)
F9Ah
TRISJ(3)
F7Ah
—(2)
FB9h
—(2)
F99h
TRISH(3)
F79h
—(2)
FB8h
(2)
F98h
TRISG
F78h
—(2)
(2)
FFCh
STKPTR
INDF2(1)
FDCh
PREINC2(1)
(1)
FFBh
PCLATU
FDBh
PLUSW2
FFAh
PCLATH
FDAh
FSR2H
FF9h
FF8h
PCL
FD9h
TBLPTRU
FD8h
FSR2L
STATUS
—
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
—
F97h
TRISF
F77h
—(2)
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
—(2)
F96h
TRISE
F76h
—(2)
FF5h
TABLAT
FD5h
T0CON
FB5h
CVRCON
F95h
TRISD
F75h
—(2)
FB4h
CMCON
F94h
TRISC
F74h
—(2)
FF4h
PRODH
FD4h
FF3h
PRODL
FD3h
OSCCON
FB3h
TMR3H
F93h
TRISB
F73h
—(2)
FF2h
INTCON
FD2h
—(2)
FB2h
TMR3L
F92h
TRISA
F72h
—(2)
F91h
LATJ(3)
F71h
—(2)
(3)
F70h
—(2)
FF1h
FF0h
INTCON2
FD1h
WDTCON
FB1h
T3CON
FD0h
RCON
FB0h
PSPCON
F90h
FCFh
TMR1H
FAFh
SPBRG1
F8Fh
LATG
F6Fh
—(2)
FEEh POSTINC0(1)
FCEh
TMR1L
FAEh
RCREG1
F8Eh
LATF
F6Eh
—(2)
(1)
FEFh
INTCON3
—
(2)
INDF0
(1)
LATH
FCDh
T1CON
FADh
TXREG1
F8Dh
LATE
F6Dh
—(2)
FECh
PREINC0
(1)
FCCh
TMR2
FACh
TXSTA1
F8Ch
LATD
F6Ch
—(2)
FEBh
PLUSW0(1)
FCBh
PR2
FABh
RCSTA1
F8Bh
LATC
F6Bh
—(2)
FEAh
FSR0H
FCAh
T2CON
FAAh
—(2)
F8Ah
LATB
F6Ah
CCPR1H
(2)
FEDh POSTDEC0
FE9h
FSR0L
FC9h
SSPBUF
FA9h
—
F89h
LATA
F69h
CCPR1L
FE8h
WREG
FC8h
SSPADD
FA8h
—(2)
F88h
PORTJ(3)
F68h
CCP1CON
FE7h
INDF1(1)
FC7h
SSPSTAT
FA7h
EECON2
F87h
PORTH(3)
F67h
CCPR2H
FE6h POSTINC1(1)
FC6h
SSPCON1
FA6h
EECON1
F86h
PORTG
F66h
CCPR2L
FE5h
POSTDEC1(1)
FC5h
SSPCON2
FA5h
IPR3
F85h
PORTF
F65h
CCP2CON
FE4h
PREINC1(1)
FC4h
ADRESH
FA4h
PIR3
F84h
PORTE
F64h
SPBRG2
FE3h
PLUSW1(1)
FC3h
ADRESL
FA3h
PIE3
F83h
PORTD
F63h
RCREG2
FE2h
FSR1H
FC2h
ADCON0
FA2h
IPR2
F82h
PORTC
F62h
TXREG2
FE1h
FSR1L
FC1h
ADCON1
FA1h
PIR2
F81h
PORTB
F61h
TXSTA2
FE0h
BSR
FC0h
ADCON2
FA0h
PIE2
F80h
PORTA
F60h
RCSTA2
Note 1:
2:
3:
This is not a physical register.
Unimplemented registers are read as ‘0’.
This register is not available on 64-pin devices.
DS39774D-page 76
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 6-4:
File Name
TOSU
PIC18F85J11 FAMILY REGISTER FILE SUMMARY
Bit 7
Bit 6
Bit 5
—
—
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Details
on page
---0 0000
57, 67
TOSH
Top-of-Stack High Byte (TOS)
0000 0000
57, 67
TOSL
Top-of-Stack Low Byte (TOS)
0000 0000
57, 67
Return Stack Pointer
uu-0 0000
57, 68
Holding Register for PC
---0 0000
57, 67
STKPTR
STKFUL
STKUNF
—
PCLATU
—
—
bit 21(1)
Top-of-Stack Upper Byte (TOS)
Value on
POR, BOR
PCLATH
Holding Register for PC
0000 0000
57, 67
PCL
PC Low Byte (PC)
0000 0000
57, 67
--00 0000
57, 92
TBLPTRU
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR)
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR)
0000 0000
57, 92
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR)
0000 0000
57, 92
TABLAT
Program Memory Table Latch
0000 0000
57, 92
PRODH
Product Register High Byte
xxxx xxxx
57, 111
PRODL
Product Register Low Byte
INTCON
xxxx xxxx
57, 111
RBIF
0000 000x
57, 115
INT3IP
RBIP
1111 1111
57, 116
INT2IF
INT1IF
1100 0000
57, 117
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
57, 83
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
57, 84
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
57, 84
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
57, 84
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
57, 84
FSR0H
---- xxxx
57, 83
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
—
xxxx xxxx
57, 83
WREG
Working Register
xxxx xxxx
57
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
57, 83
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
57, 84
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
57, 84
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
57, 84
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
57, 84
---- xxxx
58, 83
xxxx xxxx
58, 83
FSR1H
—
FSR1L
—
—
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
Indirect Data Memory Address Pointer 1 High Byte
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
---- 0000
58, 72
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
58, 83
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
58, 84
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
58, 84
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
58, 84
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
58, 84
---- xxxx
58, 83
xxxx xxxx
58, 83
---x xxxx
58, 81
INDF2
FSR2H
FSR2L
STATUS
Legend:
Note 1:
2:
3:
4:
5:
—
—
—
—
—
—
—
Bank Select Register
Indirect Data Memory Address Pointer 2 High Byte
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
OV
Z
DC
C
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown are
for 80-pin devices.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 17.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL Frequency
Multiplier” for details.
RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
2010 Microchip Technology Inc.
DS39774D-page 77
PIC18F85J11 FAMILY
TABLE 6-4:
File Name
PIC18F85J11 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page
TMR0H
Timer0 Register High Byte
0000 0000
58, 155
TMR0L
Timer0 Register Low Byte
xxxx xxxx
58, 155
58, 153
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0
0100 q000
36, 58
WDTCON
REGSLP
—
—
—
—
—
—
SWDTEN
0--- ---0
58, 287
IPEN
—
CM
RI
TO
PD
POR
BOR
0-11 11q0
52, 58
xxxx xxxx
58, 161
xxxx xxxx
58, 161
0000 0000
58, 157
RCON
TMR1H
Timer1 Register High Byte
TMR1L
Timer1 Register Low Byte
T1CON
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
TMR2
Timer2 Register
0000 0000
58, 164
PR2
Timer2 Period Register
1111 1111
58, 164
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
58, 163
SSPBUF
MSSP Receive Buffer/Transmit Register
xxxx xxxx
58, 187,
222
SSPADD
MSSP Address Register (I2C™ Slave mode). MSSP Baud Rate Reload Register (I2C Master mode).
0000 0000
58, 222
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
58, 180,
189
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
58, 181,
190
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
GCEN
ACKSTAT
ADMSK5(3)
ADMSK4(3)
ADMSK3(3)
ADMSK2(3)
ADMSK1(3)
SEN
58, 191,
192
ADRESH
A/D Result Register High Byte
xxxx xxxx
59, 267
ADRESL
A/D Result Register Low Byte
xxxx xxxx
59, 267
ADCON0
ADCAL
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
0-00 0000
59, 259
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
--00 0000
59, 260
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
0-00 0000
59, 261
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
0000 0000
59, 275
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111
59, 269
TMR3H
Timer3 Register High Byte
xxxx xxxx
59, 167
TMR3L
Timer3 Register Low Byte
xxxx xxxx
59, 167
T3CON
PSPCON
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
0000 0000
59, 165
IBF
OBF
IBOV
PSPMODE
—
—
—
—
0000 ----
59, 165
SPBRG1
EUSART Baud Rate Generator Register
0000 0000
59, 228
RCREG1
EUSART Receive Register
0000 0000
59, 236
TXREG1
EUSART Transmit Register
0000 0000
59, 234
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
59, 224
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
59, 225
---- ----
59, 90
---0 x00-
59, 91
EECON2
EECON1
Legend:
Note 1:
2:
3:
4:
5:
EEPROM Control Register 2 (not a physical register)
—
—
—
FREE
WRERR
WREN
WR
—
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown are
for 80-pin devices.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 17.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL Frequency
Multiplier” for details.
RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
DS39774D-page 78
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 6-4:
PIC18F85J11 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page
IPR3
—
—
RC2IP
TX2IP
—
CCP2IP
CCP1IP
—
--00 -11-
59, 126
PIR3
—
—
RC2IF
TX2IF
—
CCP2IF
CCP1IF
—
--00 -00-
59, 120
PIE3
—
—
RC2IE
TX2IE
—
CCP2IE
CCP1IE
—
--00 -00-
59, 123
IPR2
OSCFIP
CMIP
—
—
BCLIP
LVDIP
TMR3IP
—
11-- 111-
59, 125
PIR2
OSCFIF
CMIF
—
—
BCLIF
LVDIF
TMR3IF
—
00-- 000-
59, 119
PIE2
OSCFIE
CMIE
—
—
BCLIE
LVDIE
TMR3IE
—
00-- 000-
59, 122
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
—
TMR2IP
TMR1IP
1111 1-11
59, 124
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
—
TMR2IF
TMR1IF
0000 0-00
59, 118
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
—
TMR2IE
TMR1IE
0000 0-00
59, 121
59, 100
File Name
MEMCON(2)
EBDIS
—
WAIT1
WAIT0
—
—
WM1
WM0
0-00 --00
OSCTUNE
INTSRC
PLLEN(4)
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
0000 0000
37, 59
TRISJ(2)
TRISJ7
TRISJ6
TRISJ5
TRISJ4
TRISJ3
TRISJ2
TRISJ1
TRISJ0
1111 1111
60, 149
TRISH(2)
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
1111 1111
60, 147
TRISG
SPIOD
CCP2OD
CCP1OD
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
0001 1111
60, 146
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
1111 111-
60, 144
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
—
TRISE1
TRISE0
1111 1-11
60, 142
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
1111 1111
60, 139
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
60, 136
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
60, 133
TRISA
TRISA7(5)
TRISA6(5)
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
60, 131
LATJ(2)
LATJ7
LATJ6
LATJ5
LATJ4
LATJ3
LATJ2
LATJ1
LATJ0
xxxx xxxx
60, 149
LATH(2)
LATH7
LATH6
LATH5
LATH4
LATH3
LATH2
LATH1
LATH0
xxxx xxxx
60, 147
LATG
U2OD
U1OD
—
LATG4
LATG3
LATG2
LATG1
LATG0
00-x xxxx
60, 146
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
—
xxxx xxx-
60, 144
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
xxxx xxxx
60, 142
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx xxxx
60, 139
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
xxxx xxxx
60, 136
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx xxxx
60, 133
LATA
LATA7(5)
LATA6(5)
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx xxxx
60, 131
PORTJ(2)
RJ7
RJ6
RJ5
RJ4
RJ3
RJ2
RJ1
RJ0
xxxx xxxx
60, 149
PORTH(2)
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
xxxx xxxx
60, 147
PORTG
RDPU
REPU
RJPU(2)
RG4
RG3
RG2
RG1
RG0
000x xxxx
60, 146
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
xxxx xxx-
60, 144
PORTE
RE7
RE6
RE5
RE4
RE3
—
RE1
RE0
xxxx x-xx
60, 142
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
60, 139
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
60, 136
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
60, 133
PORTA
RA7(5)
RA6(5)
RA5
RA4
RA3
RA2
RA1
RA0
xx0x 0000
60, 131
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown are
for 80-pin devices.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 17.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL Frequency
Multiplier” for details.
RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
2010 Microchip Technology Inc.
DS39774D-page 79
PIC18F85J11 FAMILY
TABLE 6-4:
File Name
SPBRGH1
PIC18F85J11 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXCKP
BRG16
—
WUE
ABDEN
EUSART Baud Rate Generator High Byte
BAUDCON1
ABDOVF
RCIDL
RXDTP
Value on
POR, BOR
Details
on page
0000 0000
60, 228
01-0 0-00
60, 226
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
60, 170
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
60, 170
--00 0000
60, 169
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx
61, 170
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx
61, 170
--00 0000
61, 169
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
SPBRG2
AUSART Baud Rate Generator Register
0000 0000
61, 248
RCREG2
AUSART Receive Register
0000 0000
61, 253
TXREG2
AUSART Transmit Register
0000 0000
61, 251
TXSTA2
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
61, 246
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
61, 247
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown are
for 80-pin devices.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 17.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL Frequency
Multiplier” for details.
RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
DS39774D-page 80
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
6.3.5
STATUS REGISTER
The STATUS register, shown in Register 6-3, contains
the arithmetic status of the ALU. The STATUS register
can be the operand for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
then the write to these five bits is disabled.
These bits are set or cleared according to the device
logic. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended. For example, CLRF STATUS will set the Z bit
but leave the other bits unchanged. The STATUS
REGISTER 6-3:
U-0
For other instructions not affecting any Status bits, see
the instruction set summaries in Table 25-2 and
Table 25-3.
Note:
The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
STATUS REGISTER
U-0
—
register then reads back as ‘000u u1uu’. It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the STATUS
register because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.
U-0
—
—
R/W-x
N
R/W-x
R/W-x
R/W-x
R/W-x
Z
DC(1)
C(2)
OV
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit(1)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(2)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.
2010 Microchip Technology Inc.
DS39774D-page 81
PIC18F85J11 FAMILY
6.4
Data Addressing Modes
Note:
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 6.6 “Data Memory
and the Extended Instruction Set” for
more information.
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
•
•
•
•
Inherent
Literal
Direct
Indirect
INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device, or they operate implicitly on
one register. This addressing mode is known as Inherent
Addressing. Examples include SLEEP, RESET and DAW.
Other instructions work in a similar way, but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode, because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
6.4.2
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
6.4.3
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 6.6.1 “Indexed
Addressing with Literal Offset”.
6.4.1
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 6.3.1 “Bank Select Register”) are used with
the address to determine the complete 12-bit address
of the register. When ‘a’ is ‘0’, the address is interpreted
as being a register in the Access Bank. Addressing that
uses the Access RAM is sometimes also known as
Direct Forced Addressing mode.
INDIRECT ADDRESSING
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures such as
tables and arrays in data memory.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code using
loops, such as the example of clearing an entire RAM
bank in Example 6-5. It also enables users to perform
Indexed Addressing and other Stack Pointer
operations for program memory in data memory.
EXAMPLE 6-5:
DIRECT ADDRESSING
LFSR
CLRF
Direct Addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
NEXT
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 6.3.3 “General
Purpose Register File”), or a location in the Access
Bank (Section 6.3.2 “Access Bank”) as the data
source for the instruction.
BRA
CONTINUE
DS39774D-page 82
BTFSS
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
FSR0, 100h ;
POSTINC0
; Clear INDF
; register then
; inc pointer
FSR0H, 1
; All done with
; Bank1?
NEXT
; NO, clear next
; YES, continue
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
6.4.3.1
FSR Registers and the
INDF Operand
the SFR space but are not physically implemented.
Reading or writing to a particular INDF register actually
accesses its corresponding FSR register pair. A read
from INDF1, for example, reads the data at the address
indicated by FSR1H:FSR1L. Instructions that use the
INDF registers as operands actually use the contents
of their corresponding FSR as a pointer to the instruction’s target. The INDF operand is just a convenient
way of using the pointer.
At the core of Indirect Addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
Indirect Addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can
be thought of as “virtual” registers: they are mapped in
FIGURE 6-10:
INDIRECT ADDRESSING
000h
Using an instruction with one of the
Indirect Addressing registers as the
operand....
Bank 0
ADDWF, INDF1, 1
100h
Bank 1
200h
...uses the 12-bit address stored in
the FSR pair associated with that
register....
300h
FSR1H:FSR1L
7
0
x x x x 1 1 1 1
7
Bank 2
0
1 1 0 0 1 1 0 0
Bank 3
through
Bank 13
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
FCCh. This means the contents of
location FCCh will be added to that
of the W register and stored back in
FCCh.
E00h
Bank 14
F00h
FFFh
Bank 15
Data Memory
2010 Microchip Technology Inc.
DS39774D-page 83
PIC18F85J11 FAMILY
6.4.3.2
FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on its stored value. They are:
• POSTDEC: accesses the FSR value, then
automatically decrements it by ‘1’ afterwards
• POSTINC: accesses the FSR value, then
automatically increments it by ‘1’ afterwards
• PREINC: increments the FSR value by ‘1’, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the new value in the operation
In this context, accessing an INDF register uses the
value in the FSR registers without changing them.
Similarly, accessing a PLUSW register gives the FSR
value offset by the value in the W register; neither value
is actually changed in the operation. Accessing the
other virtual registers changes the value of the FSR
registers.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
DS39774D-page 84
6.4.3.3
Operations by FSRs on FSRs
Indirect Addressing operations that target other FSRs or
virtual registers represent special cases. For example,
using an FSR to point to one of the virtual registers will
not result in successful operations. As a specific case,
assume that FSR0H:FSR0L contain FE7h, the address
of INDF1. Attempts to read the value of the INDF1, using
INDF0 as an operand, will return 00h. Attempts to write
to INDF1, using INDF0 as the operand, will result in a
NOP.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses Indirect Addressing.
Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
6.5
Program Memory and the
Extended Instruction Set
The operation of program memory is unaffected by the
use of the extended instruction set.
Enabling the extended instruction set adds five
additional two-word commands to the existing PIC18
instruction set: ADDFSR, CALLW, MOVSF, MOVSS and
SUBFSR. These instructions are executed as described
in Section 6.2.4 “Two-Word Instructions”.
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
6.6
Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifically,
the use of the Access Bank for many of the core PIC18
instructions is different; this is due to the introduction of
a new addressing mode for the data memory space.
This mode also alters the behavior of Indirect
Addressing using FSR2 and its associated operands.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.
6.6.1
INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented
instructions – can invoke a form of Indexed Addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset, or Indexed Literal Offset mode.
6.6.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing
modes are unaffected.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’) or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the different possible addressing modes when the extended
instruction set is enabled is shown in Figure 6-11.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 25.2.1
“Extended Instruction Syntax”.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
and
• The file address argument is less than or equal to
5Fh.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in Direct Addressing) or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer
specified by FSR2. The offset and the contents of FSR2
are added to obtain the target address of the operation.
2010 Microchip Technology Inc.
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FIGURE 6-11:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When a = 0 and f 60h:
The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and FFFh. This is the same as
locations F60h to FFFh
(Bank 15) of data memory.
Locations below 060h are not
available in this addressing
mode.
000h
060h
Bank 0
100h
00h
Bank 1
through
Bank 14
F00h
60h
Valid range
for ‘f’
Access RAM
FFh
Bank 15
F40h
SFRs
FFFh
When a = 0 and f5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When a = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
Data Memory
000h
Bank 0
060h
100h
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
Bank 15
F40h
SFRs
FFFh
Data Memory
BSR
00000000
000h
Bank 0
060h
100h
Bank 1
through
Bank 14
001001da ffffffff
F00h
Bank 15
F40h
SFRs
FFFh
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Data Memory
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6.6.3
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower part of Access RAM
(00h to 5Fh) is mapped. Rather than containing just the
contents of the bottom part of Bank 0, this mode maps
the contents from Bank 0 and a user-defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see Section 6.3.2 “Access
Bank”). An example of Access Bank remapping in this
addressing mode is shown in Figure 6-12.
FIGURE 6-12:
Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use Direct Addressing as before. Any Indirect or
Indexed Addressing operation that explicitly uses any
of the indirect file operands (including FSR2) will continue to operate as standard Indirect Addressing. Any
instruction that uses the Access Bank, but includes a
register address of greater than 05Fh, will use Direct
Addressing and the normal Access Bank map.
6.6.4
BSR IN INDEXED LITERAL
OFFSET MODE
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL
OFFSET ADDRESSING
Example Situation:
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
000h
05Fh
Bank 0
100h
120h
17Fh
200h
Window
Bank 1
00h
Bank 1 “Window”
5Fh
60h
Special Function Registers
at F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
Not Accessible
Bank 2
through
Bank 14
SFRs
FFh
Access Bank
F00h
Bank 15
F60h
FFFh
SFRs
Data Memory
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NOTES:
DS39774D-page 88
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7.0
FLASH PROGRAM MEMORY
7.1
Table Reads and Table Writes
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 64 bytes at a time. Program memory is
erased in blocks of 1024 bytes at a time. A bulk erase
operation may not be issued from user code.
• Table Read (TBLRD)
• Table Write (TBLWT)
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 7-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 7.5 “Writing
to Flash Program Memory”. Figure 7-2 shows the
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.
FIGURE 7-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
Table Pointer(1)
TBLPTRU
TBLPTRH
TBLPTRL
Table Latch (8-bit)
TABLAT
Program Memory
(TBLPTR)
Note 1:
The Table Pointer register points to a byte in program memory.
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FIGURE 7-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1:
7.2
The Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL. The process for physically writing data to the program memory array is discussed in
Section 7.5 “Writing to Flash Program Memory”.
Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
•
•
•
•
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
7.2.1
EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 7-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the write operation.
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
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REGISTER 7-1:
EECON1: EEPROM CONTROL REGISTER 1
U-0
U-0
U-0
R/W-0
R/W-x
R/W-0
R/S-0
U-0
—
—
—
FREE
WRERR
WREN
WR
—
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
S = Settable bit (cannot be cleared in software)
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by
completion of an erase operation)
0 = Perform write only
bit 3
WRERR: Flash Program Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0 = The write operation completed
bit 2
WREN: Flash Program Write Enable bit
1 = Allows write cycles to Flash program memory
0 = Inhibits write cycles to Flash program memory
bit 1
WR: Write Control bit
1 = Initiates a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle is complete
bit 0
Unimplemented: Read as ‘0’
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7.2.2
TABLE LATCH REGISTER (TABLAT)
7.2.4
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
7.2.3
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
TABLE POINTER REGISTER
(TBLPTR)
When a TBLWT is executed, the seven LSbs of the
Table Pointer register (TBLPTR) determine which
of the 64 program memory holding registers is written
to. When the timed write to program memory begins
(via the WR bit), the 12 MSbs of the TBLPTR
(TBLPTR) determine which program memory
block of 1024 bytes is written to. For more detail, see
Section 7.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the Configuration bits.
When an erase of program memory is executed, the
12 MSbs of the Table Pointer register point to the
1024-byte block that will be erased. The Least
Significant bits are ignored.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 7-1. These operations on the TBLPTR only affect
the low-order 21 bits.
TABLE 7-1:
TABLE POINTER BOUNDARIES
Figure 7-3 describes the relevant boundaries of the
TBLPTR based on Flash program memory operations.
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
FIGURE 7-3:
21
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU
16
15
TBLPTRH
8
7
TBLPTRL
0
ERASE: TBLPTR
TABLE WRITE: TBLPTR
TABLE READ: TBLPTR
DS39774D-page 92
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7.3
Reading the Flash Program Memory
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 7-4
shows the interface between the internal program
memory and the TABLAT.
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
FIGURE 7-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
Instruction Register
(IR)
EXAMPLE 7-1:
FETCH
TBLRD
TBLPTR = xxxxx0
TABLAT
Read Register
READING A FLASH PROGRAM MEMORY WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVF
MOVF
TABLAT, W
WORD_EVEN
TABLAT, W
WORD_ODD
2010 Microchip Technology Inc.
; read into TABLAT and increment
; get data
; read into TABLAT and increment
; get data
DS39774D-page 93
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7.4
Erasing Flash Program Memory
The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or
through ICSP control, can larger blocks of program
memory be bulk erased. Word erase in the Flash array
is not supported.
When initiating an erase sequence from the microcontroller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 12 bits of the
TBLPTR point to the block being erased;
TBLPTR are ignored.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. For
protection, the write initiate sequence for EECON2
must be used.
7.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1.
2.
3.
4.
5.
6.
7.
8.
Load the Table Pointer register with the address
of the block being erased.
Set the WREN and FREE bits (EECON1)
to enable the erase operation.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit; this will begin the erase cycle.
The CPU will stall for the duration of the erase
for TIE (see parameter D133B).
Re-enable interrupts.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 7-2:
ERASING A FLASH PROGRAM MEMORY BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
EECON1,
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
; enable write to memory
; enable Erase operation
; disable interrupts
ERASE_BLOCK
Required
Sequence
DS39774D-page 94
WREN
FREE
GIE
; write 55h
WR
GIE
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
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7.5
Writing to Flash Program Memory
The on-chip timer controls the write time. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
The minimum programming block is 32 words or
64 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Note 1: Unlike previous PIC® MCUs, members
of the PIC18F85J11 family do not reset
the holding registers after a write occurs.
The holding registers must be cleared or
overwritten before a programming
sequence.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT instruction may need to be executed 64 times for
each programming operation. All of the table write operations will essentially be short writes because only the
holding registers are written. At the end of updating the
64 holding registers, the EECON1 register must be
written to in order to start the programming operation
with a long write.
2: To maintain the endurance of the program
memory cells, each Flash byte should not
be programmed more than one time
between erase operations. Before
attempting to modify the contents of the
target cell a second time, a block erase of
the target block, or a bulk erase of the
entire memory, must be performed.
The long write is necessary for programming the
internal Flash. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.
FIGURE 7-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
TBLPTR = xxxxx0
8
TBLPTR = xxxxx1
Holding Register
TBLPTR = xxxx3F
TBLPTR = xxxxx2
Holding Register
8
Holding Register
Holding Register
Program Memory
7.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
Read 1024 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer register with address being
erased.
Execute the block erase procedure.
Load the Table Pointer register with the address
of the first byte being written, minus 1.
Write the 64 bytes into the holding registers with
auto-increment.
Set the WREN bit (EECON1) to enable byte
writes.
2010 Microchip Technology Inc.
8.
9.
10.
11.
12.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit; this will begin the write cycle.
The CPU will stall for the duration of the write for
TIW (see parameter D133A).
13. Re-enable interrupts.
14. Repeat steps 6 through 13 until all 1024 bytes
are written to program memory.
15. Verify the memory (table read).
An example of the required code is shown in
Example 7-3.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
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EXAMPLE 7-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base address
; of the memory block, minus 1
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
MOVLW
MOVWF
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
D'16'
WRITE_COUNTER
; enable write to memory
; enable Erase operation
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64'
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
ERASE_BLOCK
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
; Need to write 16 blocks of 64 to write
; one erase block of 1024
RESTART_BUFFER
; point to buffer
FILL_BUFFER
...
; read the new data from I2C, SPI,
; PSP, USART, etc.
WRITE_BUFFER
MOVLW
MOVWF
WRITE_BYTE_TO_HREGS
MOVFF
MOVWF
TBLWT+*
D’64
COUNTER
; number of bytes in holding register
POSTINC0, WREG
TABLAT
;
;
;
;
;
DECFSZ COUNTER
BRA
WRITE_BYTE_TO_HREGS
get low byte of buffer data
present data to table latch
write data, perform a short write
to internal TBLWT holding register.
loop until buffers are full
PROGRAM_MEMORY
Required
Sequence
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
EECON1,
WREN
GIE
; write 55h
WR
GIE
WREN
DECFSZ WRITE_COUNTER
BRA
RESTART_BUFFER
DS39774D-page 96
; enable write to memory
; disable interrupts
;
;
;
;
write 0AAh
start program (CPU stall)
re-enable interrupts
disable write to memory
; done with one write cycle
; if not done replacing the erase block
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7.5.2
7.6
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.3
Flash Program Operation During
Code Protection
See Section 23.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 7-2:
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Name
Bit 7
Bit 6
Bit 5
TBLPTRU
—
—
bit 21
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Program Memory Table Pointer Upper Byte (TBLPTR)
Reset
Values on
page
57
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR)
57
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR)
57
TABLAT
57
Program Memory Table Latch
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
EECON2
EEPROM Control Register 2 (not a physical register)
EECON1
—
—
—
INT0IE
FREE
RBIE
WRERR
TMR0IF
INT0IF
RBIF
57
59
WREN
WR
—
59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during program memory access.
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8.0
EXTERNAL MEMORY BUS
Note:
The external memory bus
implemented on 64-pin devices.
is
not
The external memory bus allows the device to access
external memory devices (such as Flash, EPROM,
SRAM, etc.) as program or data memory. It supports
both 8 and 16-Bit Data Width modes, and three
address widths of up to 20 bits.
TABLE 8-1:
The bus is implemented with 28 pins, multiplexed
across four I/O ports. Three ports (PORTD, PORTE
and PORTH) are multiplexed with the address/data bus
for a total of 20 available lines, while PORTJ is
multiplexed with the bus control signals.
A list of the pins and their functions is provided in
Table 8-1.
PIC18F85J11 FAMILY EXTERNAL BUS – I/O PORT FUNCTIONS
Name
Port
Bit
External Memory Bus Function
RD0/AD0
PORTD
0
Address bit 0 or Data bit 0
RD1/AD1
PORTD
1
Address bit 1 or Data bit 1
RD2/AD2
PORTD
2
Address bit 2 or Data bit 2
RD3/AD3
PORTD
3
Address bit 3 or Data bit 3
RD4/AD4
PORTD
4
Address bit 4 or Data bit 4
RD5/AD5
PORTD
5
Address bit 5 or Data bit 5
RD6/AD6
PORTD
6
Address bit 6 or Data bit 6
RD7/AD7
PORTD
7
Address bit 7 or Data bit 7
RE0/AD8
PORTE
0
Address bit 8 or Data bit 8
RE1/AD9
PORTE
1
Address bit 9 or Data bit 9
RE2/AD10
PORTE
2
Address bit 10 or Data bit 10
RE3/AD11
PORTE
3
Address bit 11 or Data bit 11
RE4/AD12
PORTE
4
Address bit 12 or Data bit 12
RE5/AD13
PORTE
5
Address bit 13 or Data bit 13
RE6/AD14
PORTE
6
Address bit 14 or Data bit 14
RE7/AD15
PORTE
7
Address bit 15 or Data bit 15
RH0/A16
PORTH
0
Address bit 16
RH1/A17
PORTH
1
Address bit 17
RH2/A18
PORTH
2
Address bit 18
RH3/A19
PORTH
3
Address bit 19
RJ0/ALE
PORTJ
0
Address Latch Enable (ALE) Control pin
RJ1/OE
PORTJ
1
Output Enable (OE) Control pin
RJ2/WRL
PORTJ
2
Write Low (WRL) Control pin
RJ3/WRH
PORTJ
3
Write High (WRH) Control pin
RJ4/BA0
PORTJ
4
Byte Address bit 0 (BA0)
RJ5/CE
PORTJ
5
Chip Enable (CE) Control pin
RJ6/LB
PORTJ
6
Lower Byte Enable (LB) Control pin
RJ7/UB
PORTJ
7
Upper Byte Enable (UB) Control pin
Note:
For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional
multiplexed features may be available on some pins.
2010 Microchip Technology Inc.
DS39774D-page 99
PIC18F85J11 FAMILY
8.1
External Memory Bus Control
The operation of the interface is controlled by the
MEMCON register (Register 8-1). This register is
available in all Program Memory modes except Microcontroller mode. In this mode, the register is disabled
and cannot be written to.
The EBDIS bit (MEMCON) controls the operation
of the bus and related port functions. Clearing EBDIS
enables the interface and disables the I/O functions of
the ports, as well as any other functions multiplexed to
those pins. Setting the bit enables the I/O ports and
other functions, but allows the interface to override
everything else on the pins when an external memory
operation is required. By default, the external bus is
always enabled and disables all other I/O.
REGISTER 8-1:
The operation of the EBDIS bit is also influenced by the
Program Memory mode being used. This is discussed
in more detail in Section 8.5 “Program Memory
Modes and the External Memory Bus”.
The WAIT bits allow for the addition of Wait states to
external memory operations. The use of these bits is
discussed in Section 8.3 “Wait States”.
The WM bits select the particular operating mode used
when the bus is operating in 16-Bit Data Width mode.
These are discussed in more detail in Section 8.6
“16-Bit Data Width Modes”. These bits have no effect
when an 8-Bit Data Width mode is selected.
MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
EBDIS
—
WAIT1
WAIT0
—
—
WM1
WM0
bit 15
bit 8
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EBDIS: External Bus Disable bit
1 = External bus is enabled when microcontroller accesses external memory; otherwise, all external
bus drivers are mapped as I/O ports
0 = External bus is always enabled, I/O ports are disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
WAIT: Table Reads and Writes Bus Cycle Wait Count bits
11 = Table reads and writes will wait 0 TCY
10 = Table reads and writes will wait 1 TCY
01 = Table reads and writes will wait 2 TCY
00 = Table reads and writes will wait 3 TCY
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
WM: TBLWT Operation with 16-Bit Data Bus Width Select bits
1x = Word Write mode: TABLAT0 and TABLAT1 word output; WRH active when TABLAT1 written
01 = Byte Select mode: TABLAT data copied on both MSB and LSB; WRH and (UB or LB) will activate
00 = Byte Write mode: TABLAT data copied on both MSB and LSB; WRH or WRL will activate
DS39774D-page 100
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
8.2
Address and Data Width
8.2.1
The PIC18F85J11 family of devices can be independently configured for different address and data widths
on the same memory bus. Both address and data width
are set by Configuration bits in the CONFIG3L register.
As Configuration bits, this means that these options
can only be configured by programming the device and
are not controllable in software.
The BW bit selects an 8-bit or 16-bit data bus width.
Setting this bit (default) selects a data width of 16 bits.
The EMB bits determine both the Program Memory mode and the address bus width. The available
options are 20-bit, 16-bit and 12-bit, as well as the
default Microcontroller mode (external bus disabled).
Selecting a 16-bit or 12-bit width makes a corresponding
number of high-order lines available for I/O functions;
these pins are no longer affected by the setting of the
EBDIS bit. For example, selecting a 16-Bit Address
mode (EMB = 01) disables A and allows
PORTH to function without interruptions from the
bus. Using the smaller address widths allows users to
tailor the memory bus to the size of the external memory
space for a particular design while freeing up pins for
dedicated I/O operation.
Because the EMB bits have the effect of disabling pins
for memory bus operations, it is important to always
select an address width at least equal to the data width.
If a 12-bit address width is used with a 16-bit data
width, the upper four bits of data will not be available on
the bus.
All combinations of address and data widths require
multiplexing of address and data information on the
same lines. The address and data multiplexing, as well
as I/O ports made available by the use of smaller
address widths, are summarized in Table 8-2.
TABLE 8-2:
Data Width
By default, the address presented on the external bus
is the value of the PC. In practical terms, this means
that addresses in the external memory device below
the top of on-chip memory are unavailable to the microcontroller. To access these physical locations, the glue
logic between the microcontroller and the external
memory must somehow translate addresses.
To simplify the interface, the external bus offers an
extension of Extended Microcontroller mode that
automatically performs address shifting. This feature is
controlled by the EASHFT Configuration bit. Setting
this bit offsets addresses on the bus by the size of the
microcontroller’s on-chip program memory and sets
the bottom address at 0000h. This allows the device to
use the entire range of physical addresses of the
external memory.
8.2.2
This addressing mode is available in both 8-bit and
certain 16-Bit Data Width modes. Additional details are
provided in Section 8.6.3 “16-Bit Byte Select Mode”
and Section 8.7 “8-Bit Data Width Mode”.
ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS
Address Width
Multiplexed Data and
Address Lines (and
Corresponding Ports)
16-bit
AD
(PORTD)
20-bit
16-bit
16-bit
21-BIT ADDRESSING
As an extension of 20-bit address width operation, the
external memory bus can also fully address a 2-Mbyte
memory space. This is done by using the Bus Address
bit 0 (BA0) control line as the Least Significant bit of the
address. The UB and LB control signals may also be
used with certain memory devices to select the upper
and lower bytes within a 16-bit wide data word.
12-bit
8-bit
ADDRESS SHIFTING ON THE
EXTERNAL BUS
20-bit
2010 Microchip Technology Inc.
AD
(PORTD,
PORTE)
Address-Only
Lines (and
Corresponding Ports)
Ports Available
for I/O
AD
(PORTE)
PORTE,
All of PORTH
AD
(PORTE)
All of PORTH
A, AD
(PORTH,
PORTE)
—
—
All of PORTH
A
(PORTH)
—
DS39774D-page 101
PIC18F85J11 FAMILY
8.3
Wait States
While it may be assumed that external memory devices
will operate at the microcontroller clock rate, this is
often not the case. In fact, many devices require longer
times to write or retrieve data than the time allowed by
the execution of table read or table write operations.
To compensate for this, the external memory bus can
be configured to add a fixed delay to each table operation using the bus. Wait states are enabled by setting
the WAIT Configuration bit. When enabled, the amount
of delay is set by the WAIT bits (MEMCON).
The delay is based on multiples of microcontroller
instruction cycle time and are added following the
instruction cycle when the table operation is executed.
The range is from no delay to 3 TCY (default value).
8.4
Port Pin Weak Pull-ups
With the exception of the upper address lines,
A, the pins associated with the external memory bus are equipped with weak pull-ups. The pull-ups
are controlled by the upper three bits of the PORTG
register. They are named RDPU, REPU and RJPU and
control pull-ups on PORTD, PORTE and PORTJ,
respectively. Setting one of these bits enables the
corresponding pull-ups for that port. All pull-ups are
disabled by default on all device Resets.
8.5
Program Memory Modes and the
External Memory Bus
The PIC18F85J11 family of devices are capable of
operating in one of two Program Memory modes, using
combinations of on-chip and external program memory.
The functions of the multiplexed port pins depend on
the Program Memory mode selected, as well as the
setting of the EBDIS bit.
In Microcontroller Mode, the bus is not active and the
pins have their port functions only. Writes to the
MEMCOM register are not permitted. The Reset value
of EBDIS (‘0’) is ignored and EMB pins behave as I/O
ports.
In Extended Microcontroller Mode, the external
program memory bus shares I/O port functions on the
pins. When the device is fetching or doing table
read/table write operations on the external program
memory space, the pins will have the external bus
function.
If the device is fetching and accessing internal program
memory locations only, the EBDIS control bit will
change the pins from external memory to I/O port
functions. When EBDIS = 0, the pins function as the
external bus. When EBDIS = 1, the pins function as I/O
ports.
external memory, the action of setting the bit will be
delayed until the program branches into the internal
memory. At that time, the pins will change from external
bus to I/O ports.
If the device is executing out of internal memory when
EBDIS = 0, the memory bus address/data and control
pins will not be active. They will go to a state where the
active address/data pins are tri-state; the CE, OE,
WRH, WRL, UB and LB signals are ‘1’ and ALE and
BA0 are ‘0’. Note that only those pins associated with
the current address width are forced to tri-state; the
other pins continue to function as I/O. In the case of
16-bit address width, for example, only AD
(PORTD and PORTE) are affected; A
(PORTH) continue to function as I/O.
In all External Memory modes, the bus takes priority
over any other peripherals that may share pins with it.
This includes the Parallel Slave Port and serial communication modules which would otherwise take priority
over the I/O port.
8.6
16-Bit Data Width Modes
In 16-Bit Data Width mode, the external memory
interface can be connected to external memories in
three different configurations:
• 16-Bit Byte Write
• 16-Bit Word Write
• 16-Bit Byte Select
The configuration to be used is determined by the
WM
bits
in
the
MEMCON
register
(MEMCON). These three different configurations
allow the designer maximum flexibility in using both
8-bit and 16-bit devices with 16-bit data.
For all 16-Bit Data Width modes, the Address Latch
Enable (ALE) pin indicates that the address bits,
AD, are available on the external memory interface bus. Following the address latch, the Output
Enable signal (OE) will enable both bytes of program
memory at once to form a 16-bit instruction word. The
Chip Enable signal (CE) is active at any time that the
microcontroller accesses external memory, whether
reading or writing. It is inactive (asserted high)
whenever the device is in Sleep mode.
In Byte Select mode, JEDEC standard Flash memories
will require BA0 for the byte address line and one I/O
line to select between Byte and Word mode. The other
16-Bit Data Width modes do not need BA0. JEDEC
standard static RAM memories will use the UB or LB
signals for byte selection.
If the device fetches or accesses external memory
while EBDIS = 1, the pins will switch to the external
bus. If the EBDIS bit is set by a program executing from
DS39774D-page 102
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
8.6.1
16-BIT BYTE WRITE MODE
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
Figure 8-1 shows an example of 16-Bit Byte Write
mode for PIC18F85J11 family devices. This mode is
used for two separate 8-bit memories connected for
16-bit operation. This generally includes basic EPROM
and Flash devices. It allows table writes to byte-wide
external memories.
FIGURE 8-1:
16-BIT BYTE WRITE MODE EXAMPLE
D
PIC18F85J11
AD
(MSB)
373
A
D
(LSB)
A
A
D
D
CE
AD
373
OE
D
CE
WR(2)
OE
WR(2)
ALE
A(1)
CE
OE
WRH
WRL
Address Bus
Data Bus
Control Lines
Note 1:
2:
The upper order address lines are used only for 20-bit address widths.
This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
2010 Microchip Technology Inc.
DS39774D-page 103
PIC18F85J11 FAMILY
8.6.2
16-BIT WORD WRITE MODE
Figure 8-2 shows an example of 16-Bit Word Write
mode for PIC18F85J11 family devices. This mode is
used for word-wide memories which include some of
the EPROM and Flash-type memories. This mode
allows opcode fetches and table reads from all forms of
16-bit memory and table writes to any type of
word-wide external memories. This method makes a
distinction between TBLWT cycles to even or odd
addresses.
During a TBLWT cycle to an even address
(TBLPTR = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is
tri-stated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 8-2:
During a TBLWT cycle to an odd address
(TBLPTR = 1), the TABLAT data is presented on
the upper byte of the AD bus. The contents of
the holding latch are presented on the lower byte of the
AD bus.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSb of the TBLPTR, but it is left unconnected.
Instead, the UB and LB signals are active to select both
bytes. The obvious limitation to this method is that the
table write must be done in pairs on a specific word
boundary to correctly write a word location.
16-BIT WORD WRITE MODE EXAMPLE
PIC18F85J11
AD
373
A
A
D
JEDEC Word
EPROM Memory
D
CE
AD
OE
WR(2)
373
ALE
A(1)
CE
OE
WRH
Address Bus
Data Bus
Control Lines
Note 1:
2:
The upper order address lines are used only for 20-bit address widths.
This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
DS39774D-page 104
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
8.6.3
16-BIT BYTE SELECT MODE
Figure 8-3 shows an example of 16-Bit Byte Select
mode. This mode allows table write operations to
word-wide external memories with byte selection
capability. This generally includes both word-wide
Flash and SRAM devices.
During a TBLWT cycle, the TABLAT data is presented
on the upper and lower byte of the AD bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written, based on the Least
Significant bit of the TBLPTR register.
FIGURE 8-3:
Flash and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
16-BIT BYTE SELECT MODE EXAMPLE
PIC18F85J11
AD
373
A
A
JEDEC Word
FLASH Memory
D
138(3)
AD
373
ALE
D
CE
A0
BYTE/WORD
OE WR(1)
(2)
A
OE
WRH
WRL
A
A
BA0
JEDEC Word
SRAM Memory
I/O
D
D
CE
LB
LB
UB
UB
OE
WR(1)
Address Bus
Data Bus
Control Lines
Note 1:
This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
2:
The upper order address lines are used only for 20-bit address width.
3:
Demultiplexing is only required when multiple memory devices are accessed.
2010 Microchip Technology Inc.
DS39774D-page 105
PIC18F85J11 FAMILY
8.6.4
16-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 8-4 and Figure 8-5.
FIGURE 8-4:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED
MICROCONTROLLER MODE)
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
0Ch
A
CF33h
AD
9256h
CE
ALE
OE
Memory
Cycle
Opcode Fetch
TBLRD *
from 000100h
Opcode Fetch
MOVLW 55h
from 000102h
TBLRD 92h
from 199E67h
Opcode Fetch
ADDLW 55h
from 000104h
Instruction
Execution
INST(PC – 2)
TBLRD Cycle 1
TBLRD Cycle 2
MOVLW
FIGURE 8-5:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED
MICROCONTROLLER MODE)
Q1
Q2
Q4
Q1
Q2
3AAAh
Q3
Q4
Q1
00h
00h
A
AD
Q3
0003h
3AABh
0E55h
CE
ALE
OE
Memory
Cycle
Instruction
Execution
DS39774D-page 106
Opcode Fetch
SLEEP
from 007554h
Opcode Fetch
MOVLW 55h
from 007556h
INST(PC – 2)
SLEEP
Sleep Mode, Bus Inactive
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
8.7
8-Bit Data Width Mode
will enable one byte of program memory for a portion of
the instruction cycle, then BA0 will change and the
second byte will be enabled to form the 16-bit instruction word. The Least Significant bit of the address, BA0,
must be connected to the memory devices in this
mode. The Chip Enable signal (CE) is active at any
time that the microcontroller accesses external
memory, whether reading or writing. It is inactive
(asserted high) whenever the device is in Sleep mode.
In 8-Bit Data Width mode, the external memory bus
operates only in Multiplexed mode; that is, data shares
the 8 Least Significant bits of the address bus.
Figure 8-6 shows an example of 8-Bit Multiplexed
mode for 80-pin devices. This mode is used for a single
8-bit memory connected for 16-bit operation. The
instructions will be fetched as two 8-bit bytes on a
shared data/address bus. The two bytes are sequentially fetched within one instruction cycle (TCY).
Therefore, the designer must choose external memory
devices according to timing calculations based on
1/2 TCY (2 times the instruction rate). For proper memory speed selection, glue logic propagation delay times
must be considered, along with setup and hold times.
This generally includes basic EPROM and Flash
devices. It allows table writes to byte-wide external
memories.
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD bus. The appropriate level of the BA0 control
line is strobed on the LSb of the TBLPTR.
The Address Latch Enable (ALE) pin indicates that the
address bits, AD, are available on the external
memory interface bus. The Output Enable signal (OE)
FIGURE 8-6:
8-BIT MULTIPLEXED MODE EXAMPLE
D
PIC18F85J11
AD
ALE
373
A
A
A0
D
D
AD(1)
CE
A(1)
OE
WR(2)
BA0
CE
OE
WRL
Address Bus
Data Bus
Control Lines
Note 1:
2:
The upper order address bits are only used 20-bit address width. The upper AD byte is used for all
address widths except 8-bit.
This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
2010 Microchip Technology Inc.
DS39774D-page 107
PIC18F85J11 FAMILY
8.7.1
8-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 8-7 and Figure 8-8.
FIGURE 8-7:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED
MICROCONTROLLER MODE)
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
A
0Ch
AD
CFh
33h
AD
Q4
Q1
Q2
Q3
Q4
92h
CE
ALE
OE
Memory
Cycle
Instruction
Execution
FIGURE 8-8:
Opcode Fetch
TBLRD *
from 000100h
Opcode Fetch
MOVLW 55h
from 000102h
TBLRD 92h
from 199E67h
Opcode Fetch
ADDLW 55h
from 000104h
INST(PC – 2)
TBLRD Cycle 1
TBLRD Cycle 2
MOVLW
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED
MICROCONTROLLER MODE)
Q1
Q2
Q4
Q1
Q2
AD
00h
Q4
Q1
3Ah
3Ah
AAh
Q3
00h
00h
A
AD
Q3
03h
ABh
0Eh
55h
BA0
CE
ALE
OE
Memory
Cycle
Instruction
Execution
DS39774D-page 108
Opcode Fetch
SLEEP
from 007554h
Opcode Fetch
MOVLW 55h
from 007556h
INST(PC – 2)
SLEEP
Sleep Mode, Bus Inactive
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
8.8
Operation in Power-Managed
Modes
In alternate, power-managed Run modes, the external
bus continues to operate normally. If a clock source
with a lower speed is selected, bus operations will run
at that speed. In these cases, excessive access times
for the external memory may result if Wait states have
been enabled and added to external memory operations. If operations in a lower power Run mode are
anticipated, users should provide in their applications
for adjusting memory access times at the lower clock
speeds.
2010 Microchip Technology Inc.
In Sleep and Idle modes, the microcontroller core does
not need to access data; bus operations are
suspended. The state of the external bus is frozen, with
the address/data pins and most of the control pins holding at the same state they were in when the mode was
invoked. The only potential changes are the CE, LB
and UB pins, which are held at logic high.
DS39774D-page 109
PIC18F85J11 FAMILY
NOTES:
DS39774D-page 110
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
9.0
8 x 8 HARDWARE MULTIPLIER
9.1
Introduction
EXAMPLE 9-1:
MOVF
MULWF
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
Product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
ARG1, W
ARG2
EXAMPLE 9-2:
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applications previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 9-1.
9.2
8 x 8 UNSIGNED
MULTIPLY ROUTINE
;
; ARG1 * ARG2 ->
; PRODH:PRODL
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
ARG1, W
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH, F
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
;
;
;
;
;
ARG1 * ARG2 ->
PRODH:PRODL
Test Sign Bit
PRODH = PRODH
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
Operation
Example 9-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 9-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
TABLE 9-1:
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Routine
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
Multiply Method
Program
Memory
(Words)
Cycles
(Max)
@ 40 MHz
@ 10 MHz
@ 4 MHz
Without hardware multiply
13
69
6.9 s
27.6 s
69 s
Time
Hardware multiply
1
1
100 ns
400 ns
1 s
Without hardware multiply
33
91
9.1 s
36.4 s
91 s
Hardware multiply
6
6
600 ns
2.4 s
6 s
Without hardware multiply
21
242
24.2 s
96.8 s
242 s
Hardware multiply
28
28
2.8 s
11.2 s
28 s
Without hardware multiply
52
254
25.4 s
102.6 s
254 s
Hardware multiply
35
40
4.0 s
16.0 s
40 s
2010 Microchip Technology Inc.
DS39774D-page 111
PIC18F85J11 FAMILY
Example 9-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 9-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 9-1:
RES3:RES0
=
=
EXAMPLE 9-3:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L)
EQUATION 9-2:
RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L) +
(-1 ARG2H ARG1H:ARG1L 216) +
(-1 ARG1H ARG2H:ARG2L 216)
EXAMPLE 9-4:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
ARG1L * ARG2H->
PRODH:PRODL
Add cross
products
ARG1H * ARG2L->
PRODH:PRODL
Add cross
products
Example 9-4 shows the sequence to do a 16 x 16
signed multiply. Equation 9-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
DS39774D-page 112
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
;
;
;
;
;
;
ARG1L * ARG2H ->
PRODH:PRODL
Add cross
products
;
;
;
;
;
;
;
;
;
;
;
MOVF
MULWF
;
;
;
;
;
;
;
;
;
;
16 x 16 SIGNED
MULTIPLY ROUTINE
;
;
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
;
;
;
;
;
;
;
;
;
ARG1H * ARG2L ->
PRODH:PRODL
Add cross
products
;
;
SIGN_ARG1
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
;
CONT_CODE
:
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
10.0
INTERRUPTS
Members of the PIC18F85J11 family of devices have
multiple interrupt sources and an interrupt priority
feature that allows most interrupt sources to be
assigned a high-priority level or a low-priority level. The
high-priority interrupt vector is at 0008h and the
low-priority interrupt vector is at 0018h. High-priority
interrupt events will interrupt any low-priority interrupts
that may be in progress.
There are thirteen registers which are used to control
interrupt operation. These registers are:
•
•
•
•
•
•
•
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2, PIR3
PIE1, PIE2, PIE3
IPR1, IPR2, IPR3
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the
assembler/compiler to automatically take care of the
placement of these bits within the specified register.
In general, interrupt sources have three bits to control
their operation. They are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 0008h or 0018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
2010 Microchip Technology Inc.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC® MCU mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON is the PEIE bit
which enables/disables all peripheral interrupt sources.
INTCON is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
0008h in Compatibility mode.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High-priority interrupt sources can interrupt a
low-priority interrupt. Low-priority interrupts are not
processed while high-priority interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine (ISR),
the source(s) of the interrupt can be determined by
polling the interrupt flag bits. The interrupt flag bits must
be cleared in software before re-enabling interrupts to
avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
For external interrupt events, such as the INTx pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
Note:
Do not use the MOVFF instruction to modify
any of the Interrupt Control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
DS39774D-page 113
PIC18F85J11 FAMILY
FIGURE 10-1:
PIC18F85J11 FAMILY INTERRUPT LOGIC
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
Wake-up if in
Idle or Sleep modes
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
Interrupt to CPU
Vector to Location
0008h
GIE/GIEH
IPEN
PIR3
PIE3
IPR3
IPEN
PEIE/GIEL
IPEN
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
DS39774D-page 114
Interrupt to CPU
Vector to Location
0018h
IPEN
GIE/GIEH
PEIE/GIEL
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
10.1
INTCON Registers
Note:
The INTCON registers are readable and writable
registers which contain various enable, priority and flag
bits.
REGISTER 10-1:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high-priority interrupts
0 = Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low-priority peripheral interrupts
0 = Disables all low-priority peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB pins changed state (must be cleared in software)
0 = None of the RB pins have changed state
Note 1:
A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional
instruction cycle, will end the mismatch condition and allow the bit to be cleared.
2010 Microchip Technology Inc.
DS39774D-page 115
PIC18F85J11 FAMILY
REGISTER 10-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5
INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4
INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3
INTEDG3: External Interrupt 3 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 2
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
INT3IP: INT3 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
DS39774D-page 116
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 10-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
INT3IE: INT3 External Interrupt Enable bit
1 = Enables the INT3 external interrupt
0 = Disables the INT3 external interrupt
bit 4
INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2
INT3IF: INT3 External Interrupt Flag bit
1 = The INT3 external interrupt occurred (must be cleared in software)
0 = The INT3 external interrupt did not occur
bit 1
INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
2010 Microchip Technology Inc.
DS39774D-page 117
PIC18F85J11 FAMILY
10.2
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
REGISTER 10-4:
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON).
2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
R/W-0
R-0
R-0
R/W-0
U-0
R/W-0
R/W-0
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
—
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5
RC1IF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0 = The EUSART receive buffer is empty
bit 4
TX1IF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0 = The EUSART transmit buffer is full
bit 3
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2
Unimplemented: Read as ‘0’
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
DS39774D-page 118
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 10-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
U-0
OSCFIF
CMIF
—
—
BCLIF
LVDIF
TMR3IF
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OSCFIF: Oscillator Fail Interrupt Flag bit
1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = Device clock is operating
bit 6
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 5-4
Unimplemented: Read as ‘0’
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 2
LVDIF: Low-Voltage Detect Interrupt Flag bit
1 = A low-voltage condition occurred (must be cleared in software)
0 = The device voltage is above the regulator’s low-voltage trip point
bit 1
TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 0
Unimplemented: Read as ‘0’
2010 Microchip Technology Inc.
DS39774D-page 119
PIC18F85J11 FAMILY
REGISTER 10-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
U-0
U-0
R-0
R-0
U-0
R/W-0
R/W-0
U-0
—
—
RC2IF
TX2IF
—
CCP2IF
CCP1IF
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
RC2IF: AUSART Receive Interrupt Flag bit
1 = The AUSART receive buffer, RCREG2, is full (cleared when RCREG2 is read)
0 = The AUSART receive buffer is empty
bit 4
TX2IF: AUSART Transmit Interrupt Flag bit
1 = The AUSART transmit buffer, TXREG2, is empty (cleared when TXREG2 is written)
0 = The AUSART transmit buffer is full
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 0
Unimplemented: Read as ‘0’
DS39774D-page 120
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
10.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 10-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
—
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5
RC1IE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4
TX1IE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2
Unimplemented: Read as ‘0’
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
2010 Microchip Technology Inc.
x = Bit is unknown
DS39774D-page 121
PIC18F85J11 FAMILY
REGISTER 10-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
U-0
OSCFIE
CMIE
—
—
BCLIE
LVDIE
TMR3IE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6
CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5-4
Unimplemented: Read as ‘0’
bit 3
BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
Unimplemented: Read as ‘0’
DS39774D-page 122
x = Bit is unknown
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 10-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
U-0
R-0
R-0
U-0
R/W-0
R/W-0
U-0
—
—
RC2IE
TX2IE
—
CCP2IE
CCP1IE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5
RC2IE: AUSART Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4
TX2IE: AUSART Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP2IE: CCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
CCP1IE: CCP1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
Unimplemented: Read as ‘0’
2010 Microchip Technology Inc.
x = Bit is unknown
DS39774D-page 123
PIC18F85J11 FAMILY
10.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 10-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U-0
R/W-1
R/W-1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
—
TMR2IP
TMR1IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RC1IP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TX1IP: EUSART Transmit Interrupt Priority bit
x = Bit is unknown
1 = High priority
0 = Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
Unimplemented: Read as ‘0’
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
DS39774D-page 124
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
R/W-1
U-0
U-0
R/W-1
R/W-1
R/W-1
U-0
OSCFIP
CMIP
—
—
BCLIP
LVDIP
TMR3IP
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
CMIP: Comparator Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5-4
Unimplemented: Read as ‘0’
bit 3
BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
LVDIP: Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
Unimplemented: Read as ‘0’
2010 Microchip Technology Inc.
x = Bit is unknown
DS39774D-page 125
PIC18F85J11 FAMILY
REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0
U-0
R-1
R-1
U-0
R/W-1
R/W-1
U-0
—
—
RC2IP
TX2IP
—
CCP2IP
CCP1IP
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5
RC2IP: AUSART Receive Priority Flag bit
1 = High priority
0 = Low priority
bit 4
TX2IP: AUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
Unimplemented: Read as ‘0’
DS39774D-page 126
x = Bit is unknown
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
10.5
RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
modes. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 10-13: RCON: RESET CONTROL REGISTER
R/W-0
U-0
R/W-1
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
—
CM
RI
TO
PD
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enables priority levels on interrupts
0 = Disables priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
Unimplemented: Read as ‘0’
bit 5
CM: Configuration Mismatch Flag bit
For details of bit operation, see Register 5-1.
bit 4
RI: RESET Instruction Flag bit
For details of bit operation, see Register 5-1.
bit 3
TO: Watchdog Timer Time-out Flag bit
For details of bit operation, see Register 5-1.
bit 2
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 5-1.
bit 1
POR: Power-on Reset Status bit
For details of bit operation, see Register 5-1.
bit 0
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 5-1.
2010 Microchip Technology Inc.
DS39774D-page 127
PIC18F85J11 FAMILY
10.6
INTx Pin Interrupts
10.7
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Flag bit, INTxIF, must be cleared in software in
the Interrupt Service Routine before re-enabling the
interrupt.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from the power-managed
modes if bit INTxIE was set prior to going into the
power-managed modes. If the Global Interrupt Enable
bit, GIE, is set, the processor will branch to the interrupt
vector following wake-up.
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the interrupt priority bits,
INT1IP (INTCON3), INT2IP (INTCON3) and
INT3IP (INTCON2). There is no priority bit
associated with INT0. It is always a high-priority
interrupt source.
EXAMPLE 10-1:
MOVWF
MOVFF
MOVFF
;
; USER
;
MOVFF
MOVF
MOVFF
TMR0 Interrupt
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh 0000h) will set TMR0IF. The interrupt can
be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON). Interrupt priority for Timer0 is
determined by the value contained in the interrupt priority
bit, TMR0IP (INTCON2). See Section 12.0 “Timer0
Module” for further details on the Timer0 module.
10.8
PORTB Interrupt-on-Change
An input change on PORTB sets flag bit, RBIF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2).
10.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack. If a fast
return from interrupt is not used (see Section 6.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 10-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
ISR CODE
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
DS39774D-page 128
; Restore BSR
; Restore WREG
; Restore STATUS
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
11.0
I/O PORTS
11.1
Depending on the device selected and features
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three memory mapped registers for its
operation:
I/O Port Pin Capabilities
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than VDD input levels.
11.1.1
INPUT PINS AND VOLTAGE
CONSIDERATIONS
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Output Latch register)
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Most pins that are
used as digital only inputs are able to handle DC
voltages up to 5.5V, a level typical for digital logic
circuits. The digital pins that cannot exceed VDD are
RE0, RE1, RE2, RG0, RG2 and RG3.
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register writes to
the Output Latch (LAT) register.
In contrast, pins that also have analog input functions of
any kind can only tolerate voltages up to VDD. Voltage
excursions beyond VDD on these pins should be avoided.
Setting a TRIS bit (= 1) makes the corresponding
PORT pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRIS bit
(= 0) makes the corresponding PORT pin an output
(i.e., put the contents of the corresponding LAT bit on
the selected pin).
Table 11-1 summarizes the input voltage capabilities.
Refer to Section 26.0 “Electrical Characteristics” for
more details.
The Output Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
the PORT register.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 11-1.
FIGURE 11-1:
GENERIC I/O PORT
OPERATION
RD LAT
Data
Bus
WR LAT
or PORT
D
Q
I/O pin(1)
CK
Data Latch
D
WR TRIS
TABLE 11-1:
Port or Pin
INPUT VOLTAGE TOLERANCE
Tolerated
Input
Description
Only VDD input levels
PORTA
VDD
tolerated.
PORTA
PORTC
PORTE
PORTF
PORTG
PORTA
5.5V
Tolerates input levels
above VDD, useful for
PORTB
most standard logic.
PORTC
PORTD
PORTE
PORTG
PORTH(1)
PORTJ(1)
Note 1: Not available on 64-pin devices.
Q
11.1.2
CK
TRIS Latch
Input
Buffer
RD TRIS
Q
D
ENEN
RD PORT
2010 Microchip Technology Inc.
PIN OUTPUT DRIVE
When used as digital I/O, the output pin drive strengths
vary for groups of pins intended to meet the needs for
a variety of applications. In general, there are three
classes of output pins in terms of drive capability.
PORTB and PORTC, as well as PORTA, are
designed to drive higher current loads, such as LEDs.
PORTD, PORTE and PORTJ are capable of driving
digital circuits associated with external memory
devices. They can also drive LEDs, but only those with
smaller current requirements. PORTF, PORTG and
PORTH, along with PORTA, have the lowest
drive level, but are capable of driving normal digital
circuit loads with a high input impedance.
DS39774D-page 129
PIC18F85J11 FAMILY
Table 11-2 summarizes the output capabilities of the
ports. Refer to the “Absolute Maximum Ratings” in
Section 26.0 “Electrical Characteristics” for more
details.
TABLE 11-2:
Medium
PORTD
PORTA
PORTF
PORTE
PORTB
PORTJ
(1)
+5V
PIC18F85J11
High
PORTA
USING THE OPEN-DRAIN
OUTPUT (USARTs
SHOWN AS EXAMPLES
3.3V
OUTPUT DRIVE LEVELS FOR
VARIOUS PORTS
Low
PORTG
FIGURE 11-2:
VDD
TXX
(at logic ‘1’)
3.3V
5V
PORTC
PORTH(1)
Note 1:
11.1.3
Not available on 64-pin devices.
PULL-UP CONFIGURATION
Four of the I/O ports (PORTB, PORTD, PORTE and
PORTJ) implement configurable weak pull-ups on all
pins. These are internal pull-ups that allow floating
digital input signals to be pulled to a consistent level
without the use of external resistors.
The pull-ups are enabled with a single bit for each of the
ports: RBPU (INTCON2) for PORTB, and RDPU,
REPU and RJPU (PORTG) for the other ports.
11.1.4
OPEN-DRAIN OUTPUTS
The output pins for several peripherals are also
equipped with a configurable open-drain output option.
This allows the peripherals to communicate with
external digital logic, operating at a higher voltage
level, without the use of level translators.
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the USARTs, the MSSP module (in SPI mode) and
the CCP modules. The option is selectively enabled by
setting the open-drain control bit for the corresponding
module in TRISG and LATG. Their configuration is
discussed in more detail in the sections for PORTC,
PORTE and PORTG.
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor
provided by the user to a higher voltage level, up to 5V
(Figure 11-2). When a digital logic high signal is output,
it is pulled up to the higher voltage level.
11.2
PORTA, TRISA and LATA Registers
PORTA is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are
TRISA and LATA.
RA4/T0CKI is a Schmitt Trigger input. All other PORTA
pins have TTL input levels and full CMOS output drivers.
The RA4 pin is multiplexed with the Timer0 clock input.
RA5 and RA are multiplexed with analog inputs
for the A/D Converter.
The operation of the analog inputs as A/D Converter
inputs is selected by clearing or setting the PCFG
control bits in the ADCON1 register. The corresponding
TRISA bits control the direction of these pins, even
when they are being used as analog inputs. The user
must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Note:
RA5 and RA are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
RA6/OSC2/CLKO and RA7/OSC1/CLKI normally
serve as the external circuit connections for the external (primary) oscillator circuit (HS Oscillator modes), or
the external clock input and output (EC Oscillator
modes). In these cases, RA6 and RA7 are not available
as digital I/O and their corresponding TRIS and LAT
bits are read as ‘0’. When the device is configured to
use INTOSC or INTRC as the default oscillator mode
(FOSC2 Configuration bit is ‘0’), RA6 and RA7 are
automatically configured as digital I/O; the oscillator
and clock in/clock out functions are disabled.
EXAMPLE 11-1:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
DS39774D-page 130
PORTA
;
;
LATA
;
;
07h
;
ADCON1 ;
0BFh
;
;
TRISA
;
;
INITIALIZING PORTA
Initialize PORTA by
clearing output latches
Alternate method to
clear output data latches
Configure A/D
for digital inputs
Value used to initialize
data direction
Set RA as inputs,
RA as output
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 11-3:
Pin Name
PORTA FUNCTIONS
Function
TRIS
Setting
I/O
I/O
Type
RA0
0
O
DIG
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/
VREF+
Description
LATA data output; not affected by analog input.
1
I
TTL
PORTA data input; disabled when analog input enabled.
AN0
1
I
ANA
A/D Input Channel 0. Default input configuration on POR; does not
affect digital output.
RA1
0
O
DIG
LATA data output; not affected by analog input.
1
I
TTL
PORTA data input; disabled when analog input enabled.
AN1
1
I
ANA
A/D Input Channel 1. Default input configuration on POR; does not
affect digital output.
RA2
0
O
DIG
LATA data output; not affected by analog input.
1
I
TTL
PORTA data input. Disabled when analog functions enabled.
AN2
1
I
ANA
A/D Input Channel 2. Default input configuration on POR.
VREF-
1
I
ANA
A/D and comparator low reference voltage input.
RA3
0
O
DIG
LATA data output; not affected by analog input.
1
I
TTL
PORTA data input; disabled when analog input enabled.
AN3
1
I
ANA
A/D Input Channel 3. Default input configuration on POR.
VREF+
1
I
ANA
A/D and comparator high reference voltage input.
RA4
0
O
DIG
LATA data output.
RA4/T0CKI
1
I
ST
PORTA data input; default configuration on POR.
T0CKI
x
I
ST
Timer0 clock input.
RA5
0
O
DIG
LATA data output; not affected by analog input.
1
I
TTL
PORTA data input; disabled when analog input enabled.
RA5/AN4
RA6/OSC2/
CLKO
AN4
1
I
ANA
A/D Input Channel 4. Default configuration on POR.
RA6
0
O
DIG
LATA data output; disabled when FOSC2 Configuration bit is set.
OSC2
1
I
TTL
PORTA data input; disabled when FOSC2 Configuration bit is set.
x
O
ANA
Main oscillator feedback output connection (HS and HSPLL modes).
CLKO
x
O
DIG
System cycle clock output, FOSC/4 (EC and ECPLL modes).
RA7
0
O
DIG
LATA data output; disabled when FOSC2 Configuration bit is set.
RA7/OSC1/
CLKI
1
I
TTL
PORTA data input; disabled when FOSC2 Configuration bit is set.
OSC1
x
I
ANA
Main oscillator input connection (HS and HSPLL modes).
CLKI
x
I
ANA
Main external clock source input (EC and ECPLL modes).
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 11-4:
Name
PORTA
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Bit 6
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
LATA6(1)
LATA5
LATA4
LATA3
LATA2
(1)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 0
Reset
Values
on page
RA1
RA0
60
LATA1
LATA0
60
Bit 1
LATA
LATA7
TRISA
TRISA7(1)
TRISA6(1)
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
60
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
59
ADCON1
Legend: — = Unimplemented, read as ‘0’, x = Don’t care. Shaded cells are not used by PORTA.
Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins,
they are disabled and read as ‘x’.
2010 Microchip Technology Inc.
DS39774D-page 131
PIC18F85J11 FAMILY
11.3
PORTB, TRISB and
LATB Registers
PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are
TRISB and LATB. All pins on PORTB are digital only
and tolerate voltages up to 5.5V.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON).
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after one TCY delay.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
EXAMPLE 11-2:
CLRF
PORTB
CLRF
LATB
MOVLW
0CFh
MOVWF
TRISB
INITIALIZING PORTB
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RB as inputs
RB as outputs
RB as inputs
This interrupt can wake the device from power-managed
modes. The user, in the Interrupt Service Routine, can
clear the interrupt in the following manner:
a)
b)
c)
Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
Wait one instruction cycle (such as executing a
NOP instruction).
Clear flag bit, RBIF.
DS39774D-page 132
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 11-5:
Pin Name
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/
CCP2
PORTB FUNCTIONS
Function
TRIS
Setting
I/O
I/O
Type
RB0
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
INT0
1
I
ST
External Interrupt 0 input.
RB1
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
INT1
1
I
ST
External Interrupt 1 input.
RB2
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
INT2
1
I
ST
External Interrupt 2 input.
RB3
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
1
I
ST
External Interrupt 3 input.
0
O
DIG
CCP2 compare output and CCP2 PWM output; takes priority over port data.
1
I
ST
CCP2 capture input.
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
I
TTL
Interrupt-on-pin change.
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
I
TTL
Interrupt-on-pin change.
O
DIG
LATB data output.
INT3
CCP2
RB4/KBI0
(1)
RB4
KBI0
RB5/KBI1
RB5
KBI1
RB6/KBI2/PGC
RB7/KBI3/PGD
Legend:
Note 1:
2:
PORTB
LATB
TRISB
INTCON
RB6
0
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
KBI2
1
I
TTL
Interrupt-on-pin change.
PGC
x
I
ST
Serial execution (ICSP™) clock input for ICSP and ICD operation.(2)
RB7
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
KBI3
1
I
TTL
Interrupt-on-pin change.
PGD
x
O
DIG
Serial execution data output for ICSP and ICD operation.(2)
x
I
ST
Serial execution data input for ICSP and ICD operation.(2)
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit
does not affect port direction or is overridden for this option).
Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode, 80-pin
devices only). Default assignment is RC1.
All other pin functions are disabled when ICSP™ or ICD is enabled.
TABLE 11-6:
Name
Description
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
60
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
60
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
60
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
57
TMR0IP
INT3IP
RBIP
57
INT3IF
INT2IF
INT1IF
57
GIE/GIEH PEIE/GIEL
INTCON2
RBPU
INTEDG0
INTCON3
INT2IP
INT1IP
INTEDG1 INTEDG2 INTEDG3
INT3IE
INT2IE
INT1IE
Legend: Shaded cells are not used by PORTB.
2010 Microchip Technology Inc.
DS39774D-page 133
PIC18F85J11 FAMILY
11.4
PORTC, TRISC and
LATC Registers
PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are
TRISC and LATC. Only PORTC pins, RC2 through
RC7, are digital only pins and can tolerate input
voltages up to 5.5V.
PORTC is multiplexed with CCP, MSSP and EUSART
peripheral functions (Table 11-7). The pins have
Schmitt Trigger input buffers. The pins for CCP, SPI
and EUSART are also configurable for open-drain output whenever these functions are active. Open-drain
configuration is selected by setting the SPIOD,
CCPxOD and U1OD control bits (TRISG and
LATG, respectively).
RC1 is normally configured as the default peripheral
pin for the CCP2 module. Assignment of CCP2 is
controlled by Configuration bit, CCP2MX (default state,
CCP2MX = 1).
DS39774D-page 134
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
Note:
These pins are configured as digital inputs
on any device Reset.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 11-3:
CLRF
PORTC
CLRF
LATC
MOVLW
0CFh
MOVWF
TRISC
INITIALIZING PORTC
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTC by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RC as inputs
RC as outputs
RC as inputs
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 11-7:
Pin Name
RC0/T1OSO/
T13CKI
RC1/T1OSI/
CCP2
RC2/CCP1
PORTC FUNCTIONS
Function
TRIS
Setting
I/O
I/O
Type
RC0
0
O
DIG
1
I
ST
T1OSO
x
O
ANA
T13CKI
1
I
ST
Timer1/Timer3 counter input.
RC1
0
O
DIG
LATC data output.
I
ST
x
I
ANA
Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables
digital I/O.
CCP2(1)
0
O
DIG
CCP2 compare output and CCP2 PWM output; takes priority over port data.
1
I
ST
CCP2 capture input.
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
0
O
DIG
CCP1 compare output and CCP1 PWM output; takes priority over port data.
1
I
ST
CCP1 capture input.
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
0
O
DIG
SPI clock output (MSSP module); takes priority over port data.
1
I
ST
SPI clock input (MSSP module).
0
O
DIG
I2C™ clock output (MSSP module); takes priority over port data.
1
I
I2C
I2C clock input (MSSP module); input type depends on module setting.
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
SDI
1
I
ST
SPI data input (MSSP module).
SDA
1
O
DIG
I2C data output (MSSP module); takes priority over port data.
1
I
I2C
I2C data input (MSSP module); input type depends on module setting.
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
SDO
0
O
DIG
SPI data output (MSSP module); takes priority over port data.
RC6
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
TX1
1
O
DIG
Synchronous serial data output (EUSART module); takes priority over port data.
CK1
1
O
DIG
Synchronous serial data input (EUSART module). User must configure as
an input.
RC3
SCK
SCL
RC5/SDO
RC7/RX1/DT1
Legend:
Note 1:
RC4
RC5
RC6/TX1/CK1
PORTC data input.
Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables
digital I/O.
1
CCP1
RC4/SDI/SDA
LATC data output.
T1OSI
RC2
RC3/SCK/SCL
Description
PORTC data input.
1
I
ST
Synchronous serial clock input (EUSART module).
RC7
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
RX1
1
I
ST
Asynchronous serial receive data input (EUSART module).
DT1
1
O
DIG
Synchronous serial data output (EUSART module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSART module). User must configure as
an input.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit
does not affect port direction or is overridden for this option).
Default assignment for CCP2 when CCP2MX Configuration bit is set.
2010 Microchip Technology Inc.
DS39774D-page 135
PIC18F85J11 FAMILY
TABLE 11-8:
Name
PORTC
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
60
LATC
LATC7
LATBC6
LATC5
LATCB4
LATC3
LATC2
LATC1
LATC0
60
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
60
LATG
U2OD
U1OD
—
LATG4
LATG3
LATG2
LATG1
LATG0
60
TRISG
SPIOD
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
60
CCP2OD CCP1OD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC.
DS39774D-page 136
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
11.5
PORTD, TRISD and
LATD Registers
PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are
TRISD and LATD. All pins on PORTD are digital only
and tolerate voltages up to 5.5V.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note:
These pins are configured as digital inputs
on any device Reset.
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, RDPU (PORTG). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
On 80-pin devices, PORTD is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled, by setting the EBDIS bit
(MEMCON). When the interface is enabled,
PORTD is the low-order byte of the multiplexed
address/data bus (AD). The TRISD bits are also
overridden.
2010 Microchip Technology Inc.
PORTD can also be configured to function as an 8-bit
wide, parallel microprocessor port by setting the
PSPMODE control bit (PSPCON). In this mode,
parallel port data takes priority over other digital I/O (but
not the external memory interface). When the parallel
port is active, the input buffers are TTL. For more
information, refer to Section 11.11 “Parallel Slave
Port”.
EXAMPLE 11-4:
CLRF
PORTD
CLRF
LATD
MOVLW
0CFh
MOVWF
TRISD
INITIALIZING PORTD
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTD by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RD as inputs
RD as outputs
RD as inputs
DS39774D-page 137
PIC18F85J11 FAMILY
TABLE 11-9:
PORTD FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
RD0/AD0/PSP0
RD0
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
AD0(2)
x
O
DIG
External memory interface, address/data bit 0 output.(1)
x
I
TTL
External memory interface, data bit 0 input.(1)
O
DIG
PSP read output data (LATD); takes priority over port data.
I
TTL
PSP write data input.
O
DIG
LATD data output.
PSP0
RD1/AD1/PSP1
RD1
AD1(2)
PSP1
RD2/AD2/PSP2
RD2
AD2(2)
PSP2
RD3/AD3/PSP3
RD3
AD3(2)
PSP3
RD4/AD4/PSP4
RD4
AD4(2)
PSP4
RD5/AD5/PSP5
RD5
AD5(2)
PSP5
RD6/AD6/PSP6
RD6
AD6(2)
PSP6
Legend:
Note 1:
2:
0
Description
1
I
ST
PORTD data input.
x
O
DIG
External memory interface, address/data bit 1 output.(1)
x
I
TTL
External memory interface, data bit 1 input.(1)
PSP read output data (LATD); takes priority over port data.
x
O
DIG
x
I
TTL
PSP write data input.
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
x
O
DIG
External memory interface, address/data bit 2 output.(1)
x
I
TTL
External memory interface, data bit 2 input.(1)
x
O
DIG
PSP read output data (LATD); takes priority over port data.
x
I
TTL
PSP write data input.
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
x
O
DIG
External memory interface, address/data bit 3 output.(1)
x
I
TTL
External memory interface, data bit 3 input.(1)
PSP read output data (LATD); takes priority over port data.
x
O
DIG
x
I
TTL
PSP write data input.
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
x
O
DIG
External memory interface, address/data bit 4 output.(1)
x
I
TTL
External memory interface, data bit 4 input.(1)
x
O
DIG
PSP read output data (LATD); takes priority over port data.
x
I
TTL
PSP write data input.
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
x
O
DIG
External memory interface, address/data bit 5 output.(1)
x
I
TTL
External memory interface, data bit 5 input.(1)
PSP read output data (LATD); takes priority over port data.
x
O
DIG
x
I
TTL
PSP write data input.
0
O
DIG
LATD data output.
1
I
ST
x
O
DIG-3
PORTD data input.
x
I
TTL
External memory interface, data bit 6 input.(1)
x
O
DIG
PSP read output data (LATD); takes priority over port data.
x
I
TTL
PSP write data input.
External memory interface, address/data bit 6 output.(1)
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit
does not affect port direction or is overridden for this option).
External memory interface I/O takes priority over all other digital and PSP I/O.
Available on 80-pin devices only.
DS39774D-page 138
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 11-9:
PORTD FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
RD7/AD7/PSP7
RD7
0
O
DIG
LATD data output.
AD7(2)
PSP7
Legend:
Note 1:
2:
Description
1
I
ST
PORTD data input.
x
O
DIG
External memory interface, address/data bit 7 output.(1)
x
I
TTL
External memory interface, data bit 7 input.(1)
x
O
DIG
PSP read output data (LATD); takes priority over port data.
x
I
TTL
PSP write data input.
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit
does not affect port direction or is overridden for this option).
External memory interface I/O takes priority over all other digital and PSP I/O.
Available on 80-pin devices only.
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name
PORTD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
60
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
60
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
60
PORTG
RDPU
REPU
RJPU(1)
RG4
RG3
RG2
RG1
RG0
60
Legend: Shaded cells are not used by PORTD.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
2010 Microchip Technology Inc.
DS39774D-page 139
PIC18F85J11 FAMILY
11.6
PORTE, TRISE and
LATE Registers
PORTE is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are
TRISE and LATE. All pins on PORTE are digital only
and tolerate voltages up to 5.5V.
All pins on PORTE are implemented with Schmitt Trigger input buffers. Each pin is individually configurable
as an input or output. The RE7 pin is also configurable
for open-drain output when CCP2 is active on this pin.
Open-drain configuration is selected by setting the
CCP2OD control bit (TRISG)
Note:
These pins are configured as digital inputs
on any device Reset.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, REPU (PORTG). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
On 80-pin devices, PORTE is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON). When the interface is enabled,
PORTE is the high-order byte of the multiplexed
address/data bus (AD). The TRISE bits are also
overridden.
DS39774D-page 140
When the Parallel Slave Port is active on PORTD, three
of the PORTE pins (RE0, RE1 and RE2) are configured
as digital control inputs for the port. The control
functions are summarized in Table 11-11. The reconfiguration occurs automatically when the PSPMODE
control bit (PSPCON) is set. Users must still make
certain the corresponding TRISE bits are set to
configure these pins as digital inputs.
RE7 can also be configured as the alternate peripheral
pin for the CCP2 module. This is done by clearing the
CCP2MX Configuration bit.
EXAMPLE 11-5:
CLRF
PORTE
CLRF
LATE
MOVLW
03h
MOVWF
TRISE
INITIALIZING PORTE
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTE by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RE as inputs
RE as outputs
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 11-11: PORTE FUNCTIONS
Pin Name
RE0/RD/AD8
Function
TRIS
Setting
I/O
I/O
Type
RE0
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
1
I
TTL
Parallel Slave Port read enable control input.
x
O
DIG
External memory interface, address/data bit 8 output.(2)
x
I
TTL
External memory interface, data bit 8 input.(2)
RE1
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
WR
1
I
TTL
Parallel Slave Port write enable control input.
AD9(1)
x
O
DIG
External memory interface, address/data bit 9 output.(2)
x
I
TTL
External memory interface, data bit 9 input.(2)
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External memory interface, address/data bit 10 output.(2)
x
I
TTL
External memory interface, data bit 10 input.(2)
CS
1
I
TTL
Parallel Slave Port chip select control input.
RE3
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External memory interface, address/data bit 11 output.(2)
x
I
TTL
External memory interface, data bit 11 input.(2)
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External memory interface, address/data bit 12 output.(2)
x
I
TTL
External memory interface, data bit 12 input.(2)
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External memory interface, address/data bit 13 output.(2)
x
I
TTL
External memory interface, data bit 13 input.(2)
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External memory interface, address/data bit 14 output.(2)
x
I
TTL
External memory interface, data bit 14 input.(2)
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External memory interface, address/data bit 15 output.(2)
x
I
TTL
External memory interface, data bit 15 input.(2)
0
O
DIG
CCP2 compare output and CCP2 PWM output; takes priority over
port data.
1
I
ST
CCP2 capture input.
RD
(1)
AD8
RE1/WR/AD9
RE2/AD10/CS
RE2
AD10(1)
RE3/AD11
AD11(1)
RE4/AD12
RE4
AD12(1)
RE5/AD13
RE5
AD13(1)
RE6/AD14
RE6
AD14(1)
RE7/AD15/
CCP2
RE7
AD15(1)
(3)
CCP2
Legend:
Note 1:
2:
3:
Description
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit
does not affect port direction or is overridden for this option).
Available on 80-pin devices only.
External memory interface I/O takes priority over all other digital and PSP I/O.
Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
2010 Microchip Technology Inc.
DS39774D-page 141
PIC18F85J11 FAMILY
TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
PORTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
60
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
60
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
60
PORTG
RDPU
REPU
RJPU(1)
RG4
RG3
RG2
RG1
RG0
60
TRISG
SPIOD
CCP2OD
CCP1OD
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
DS39774D-page 142
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
11.7
PORTF, LATF and TRISF Registers
EXAMPLE 11-6:
INITIALIZING PORTF
PORTF is a 7-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are
TRISF and LATF. All pins on PORTF are implemented
with Schmitt Trigger input buffers. Each pin is individually
configurable as an input or output.
CLRF
PORTF
CLRF
LATF
PORTF is multiplexed with analog peripheral functions.
Pins RF1 through RF6 may be used as comparator
inputs or outputs by setting the appropriate bits in the
CMCON register. To use RF as digital inputs, it is
also necessary to turn off the comparators.
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
07h
CMCON
Turn off comparators
0Fh;
ADCON1 ; Set PORTF as digital I/O
0CEh
; Value used to
; initialize data
; direction
TRISF
; Set RF3:RF1 as inputs
; RF5:RF4 as outputs
; RF7:RF6 as inputs
Note 1: On device Resets, pins, RF, are
configured as analog inputs and are read
as ‘0’.
MOVWF
;
;
;
;
;
;
;
;
Initialize PORTF by
clearing output
data latches
Alternate method
to clear output
data latches
2: To configure PORTF as digital I/O, turn off
comparators and set ADCON1 value.
2010 Microchip Technology Inc.
DS39774D-page 143
PIC18F85J11 FAMILY
TABLE 11-13: PORTF FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
RF1
0
O
DIG
LATF data output; not affected by analog input.
1
I
ST
PORTF data input; disabled when analog input enabled.
RF1/AN6/
C2OUT
AN6
1
I
ANA
A/D Input Channel 6. Default configuration on POR.
C2OUT
0
O
DIG
Comparator 2 output; takes priority over port data.
RF2
0
O
DIG
LATF data output; not affected by analog input.
1
I
ST
PORTF data input; disabled when analog input enabled.
RF2/AN7/
C1OUT
AN7
1
I
ANA
A/D Input Channel 7. Default configuration on POR.
C1OUT
0
O
TTL
Comparator 1 output; takes priority over port data.
RF3
0
O
DIG
LATF data output; not affected by analog input.
1
I
ST
PORTF data input; disabled when analog input enabled.
AN8
1
I
ANA
RF4
0
O
DIG
LATF data output; not affected by analog input.
1
I
ST
PORTF data input; disabled when analog input enabled.
AN9
1
I
ANA
A/D Input Channel 9 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
RF5
0
O
DIG
LATF data output; not affected by analog input. Disabled when
CVREF output enabled.
1
I
ST
PORTF data input; disabled when analog input enabled. Disabled
when CVREF output enabled.
AN10
1
I
ANA
A/D Input Channel 10 and Comparator C1+ input. Default input
configuration on POR.
CVREF
x
O
ANA
Comparator voltage reference output. Enabling this feature disables
digital I/O.
RF6
0
O
DIG
LATF data output; not affected by analog input.
1
I
ST
PORTF data input; disabled when analog input enabled.
AN11
1
I
ANA
RF7
0
O
DIG
LATF data output.
1
I
ST
PORTF data input.
AN5
1
I
ANA
A/D Input Channel 5. Default configuration on POR.
SS
1
I
TTL
Slave select input for MSSP module.
RF3/AN8
RF4/AN9
RF5/AN10/
CVREF
RF6/AN11
RF7/AN5/SS
Legend:
Description
A/D Input Channel 8 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
A/D Input Channel 11 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Name
PORTF
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
60
60
60
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
—
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
59
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
59
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.
DS39774D-page 144
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
11.8
PORTG, TRISG and
LATG Registers
PORTG is a 5-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are
TRISG and LATG. All pins on PORTG are digital only
and tolerate voltages up to 5.5V.
When operating as I/O, all PORTG pins have Schmitt
Trigger input buffers. Pins, RG1 and RG2, are multiplexed with the AUSART module. The RG1 pin is also
configurable for open-drain output when the AUSART
is active. Open-drain configuration is selected by
setting the U2OD control bit (LATG).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
2010 Microchip Technology Inc.
Although the port itself is only five bits wide, the
PORTG bits are still implemented to control the
weak pull-ups on the I/O ports associated with PORTD,
PORTE and PORTJ. Clearing these bits enables the
respective port pull-ups. All pull-ups are disabled by
default on all device Resets.
Most of the corresponding TRISG and LATG bits are
implemented as open-drain control bits for CCP1,
CCP2 and SPI (TRISG), and the USARTs
(LATG). Setting these bits configures the output
pin for the corresponding peripheral for open-drain
operation. LATG is not implemented.
EXAMPLE 11-7:
CLRF
PORTG
CLRF
LATG
MOVLW
04h
MOVWF
TRISG
INITIALIZING PORTG
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTG by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RG1:RG0 as outputs
RG2 as input
RG4:RG3 as inputs
DS39774D-page 145
PIC18F85J11 FAMILY
TABLE 11-15: PORTG FUNCTIONS
Pin Name
RG0
RG1/TX2/CK2
RG2/RX2/DT2
RG3
RG4
Legend:
Function
TRIS
Setting
I/O
I/O
Type
RG0
0
O
DIG
1
I
ST
PORTG data input.
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
TX2
1
O
DIG
Synchronous serial data output (AUSART2 module); takes priority over
port data.
CK2
1
O
DIG
Synchronous serial data input (AUSART2 module). User must configure
as an input.
1
I
ST
Synchronous serial clock input (AUSART2 module).
RG2
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
RX2
1
I
ST
Asynchronous serial receive data input (AUSART2 module).
DT2
1
O
DIG
Synchronous serial data output (AUSART2 module); takes priority over
port data.
1
I
ST
Synchronous serial data input (AUSART2 module). User must configure
as an input.
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
R21
RG3
RG4
Description
LATG data output.
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port
direction or is overridden for this option).
TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Name
Bit 3
Bit 2
Reset
Values on
page
RG1
RG0
60
LATG1
LATG0
60
TRISG0
60
Bit 6
Bit 5
PORTG
RDPU
REPU
RJPU(1)
RG4
RG3
RG2
LATG
U2OD
U1OD
—
LATG4
LATG3
LATG2
TRISG
SPIOD
TRISG4
TRISG3
TRISG2
TRISG1
CCP2OD CCP1OD
Bit 4
Bit 0
Bit 7
Bit 1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
DS39774D-page 146
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
11.9
PORTH, LATH and TRISH Registers
Note:
PORTH is available only on 80-pin
devices.
PORTH is an 8-bit wide, bidirectional I/O port. The corresponding Data Direction and Output Latch registers are
TRISH and LATH. All pins are digital only and tolerate
voltages up to 5.5V.
All pins on PORTH are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
EXAMPLE 11-8:
CLRF
PORTH
CLRF
LATH
MOVLW
MOVWF
MOVLW
0Fh
ADCON1
0CFh
MOVWF
TRISH
When the external memory interface is enabled, four of
the PORTH pins function as the high-order address
lines for the interface. The address output from the
interface takes priority over other digital I/O. The
corresponding TRISH bits are also overridden.
INITIALIZING PORTH
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTH by
clearing output
data latches
Alternate method
to clear output
data latches
Configure PORTH as
digital I/O
Value used to
initialize data
direction
Set RH3:RH0 as inputs
RH5:RH4 as outputs
RH7:RH6 as inputs
TABLE 11-17: PORTH FUNCTIONS
Pin Name
RH0/A16
RH1/A17
RH2/A18
RH3/A19
RH4
Function
TRIS
Setting
I/O
I/O
Type
RH0
0
O
DIG
1
I
ST
PORTH data input.
A16
x
O
DIG
External memory interface, Address Line 16. Takes priority over port data.
RH1
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
A17
x
O
DIG
External memory interface, Address Line 17. Takes priority over port data.
RH2
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
A18
x
O
DIG
External memory interface, Address Line 18. Takes priority over port data.
RH3
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
A19
x
O
DIG
External memory interface, Address Line 19. Takes priority over port data.
RH4
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
O
DIG
LATH data output.
Description
LATH data output.
RH5
RH5
0
1
I
ST
PORTH data input.
RH6
RH6
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
RH7
RH7
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
Legend:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port
direction or is overridden for this option).
TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Name
PORTH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
60
LATH
LATH7
LATH6
LATH5
LATH4
LATH3
LATH2
LATH1
LATH0
60
TRISH
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
60
2010 Microchip Technology Inc.
DS39774D-page 147
PIC18F85J11 FAMILY
11.10 PORTJ, TRISJ and LATJ Registers
Note:
PORTJ is available only on 80-pin devices.
PORTJ is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are
TRISJ and LATJ. All pins on PORTJ are digital only and
tolerate voltages up to 5.5V.
All pins on PORTJ are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note:
These pins are configured as digital inputs
on any device Reset.
Each of the PORTJ pins has a weak internal pull-up.
The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit, RJPU (PORTG). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
DS39774D-page 148
When the external memory interface is enabled, all of
the PORTJ pins function as control outputs for the
interface. This occurs automatically when the interface
is enabled by clearing the EBDIS control bit
(MEMCON). The TRISJ bits are also overridden.
EXAMPLE 11-9:
CLRF
PORTJ
CLRF
LATJ
MOVLW
0CFh
MOVWF
TRISJ
INITIALIZING PORTJ
;
;
;
;
;
;
;
;
;
;
Initialize PORTJ by
clearing output latches
Alternate method
to clear output latches
Value used to
initialize data
direction
Set RJ3:RJ0 as inputs
RJ5:RJ4 as output
RJ7:RJ6 as inputs
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 11-19: PORTJ FUNCTIONS
Pin Name
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
Function
TRIS
Setting
I/O
I/O
Type
RJ0
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
ALE
x
O
DIG
External memory interface address latch enable control output; takes
priority over digital I/O.
RJ1
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
OE
x
O
DIG
External memory interface output enable control output; takes priority
over digital I/O.
RJ2
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
WRL
x
O
DIG
External memory bus write low byte control; takes priority over
digital I/O.
RJ3
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
WRH
x
O
DIG
External memory interface write high byte control output; takes priority
over digital I/O.
RJ4
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
BA0
x
O
DIG
External memory interface byte address 0 control output; takes priority
over digital I/O.
RJ5
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
CE
x
O
DIG
External memory interface chip enable control output; takes priority
over digital I/O.
RJ6
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
LB
x
O
DIG
External memory interface lower byte enable control output; takes
priority over digital I/O.
RJ7
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
x
O
DIG
External memory interface upper byte enable control output; takes
priority over digital I/O.
UB
Legend:
Description
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port
direction or is overridden for this option).
TABLE 11-20: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Name
PORTJ
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
RJ7
RJ6
RJ5
RJ4
RJ3
RJ2
RJ1
RJ0
60
LATJ
LATJ7
LATJ6
LATJ5
LATJ4
LATJ3
LATJ2
LATJ1
LATJ0
60
TRISJ
TRISJ7
TRISJ6
TRISJ5
TRISJ4
TRISJ3
TRISJ2
TRISJ1
TRISJ0
60
PORTG
RDPU
REPU
RJPU
RG4
RG3
RG2
RG1
RG0
60
Legend: Shaded cells are not used by PORTJ.
2010 Microchip Technology Inc.
DS39774D-page 149
PIC18F85J11 FAMILY
11.11 Parallel Slave Port
PORTD can also function as an 8-bit wide Parallel
Slave Port, or microprocessor port, when control bit
PSPMODE (PSPCON) is set. It is asynchronously
readable and writable by the external world through RD
control input pin, RE0/RD, and WR control input pin,
RE1/WR.
Note:
For 80-pin devices, the Parallel Slave Port
is available only in Microcontroller mode.
The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit PSPMODE enables port pin, RE0/RD, to be the RD
input, RE1/WR to be the WR input and RE2/CS to be
the CS (Chip Select) input. For this functionality, the
corresponding data direction bits of the TRISE register
(TRISE) must be configured as inputs (set).
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits are both set
when the write ends.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit is set. If the user writes new data
to PORTD to set OBF, the data is immediately read out;
however, the OBF bit is not set.
When either the CS or RD lines are detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP. When this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
The timing for the control signals in Write and Read
modes is shown in Figure 11-4 and Figure 11-5,
respectively.
DS39774D-page 150
FIGURE 11-3:
Data Bus
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
D
WR LATD
or
PORTD
Q
RDx
pin
CK
Data Latch
RD PORTD
TTL
D
Q
ENEN
TRIS Latch
RD LATD
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1)
Read
TTL
RD
Chip Select
TTL
CS
Write
TTL
WR
Note: I/O pin has protection diodes to VDD and VSS.
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 11-1:
PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER
R-0
R-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
IBF
OBF
IBOV
PSPMODE
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5
IBOV: Input Buffer Overflow Detect bit
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel Slave Port mode
0 = General Purpose I/O mode
bit 3-0
Unimplemented: Read as ‘0’
FIGURE 11-4:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
2010 Microchip Technology Inc.
DS39774D-page 151
PIC18F85J11 FAMILY
FIGURE 11-5:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
TABLE 11-21: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name
PORTD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
60
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
60
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
60
PORTE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
60
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
60
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
60
IBF
OBF
IBOV
PSPMODE
—
—
—
—
59
PSPCON
INTCON
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
57
PIR1
GIE/GIEH PEIE/GIEL
PSPIF
ADIF
RC1IF
TX1IF
SSP1IF
—
TMR2IF
TMR1IF
59
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSP1IE
—
TMR2IE
TMR1IE
59
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSP1IP
—
TMR2IP
TMR1IP
59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
DS39774D-page 152
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
12.0
TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or counter in both 8-bit or 16-bit modes
• Readable and writable registers
• Dedicated, 8-bit software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt on overflow
REGISTER 12-1:
The T0CON register (Register 12-1) controls all
aspects of the module’s operation, including the
prescale selection; it is both readable and writable.
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 12-1. Figure 12-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
T0CON: TIMER0 CONTROL REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6
T08BIT: Timer0 8-Bit/16-Bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin input edge
0 = Internal clock (FOSC/4)
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0
T0PS: Timer0 Prescaler Select bits
111 = 1:256 Prescale value
110 = 1:128 Prescale value
101 = 1:64 Prescale value
100 = 1:32 Prescale value
011 = 1:16 Prescale value
010 = 1:8 Prescale value
001 = 1:4 Prescale value
000 = 1:2 Prescale value
2010 Microchip Technology Inc.
DS39774D-page 153
PIC18F85J11 FAMILY
12.1
Timer0 Operation
Timer0 can operate as either a timer or a counter. The
mode is selected with the T0CS bit (T0CON). In
Timer mode (T0CS = 0), the module increments on
every clock by default unless a different prescaler value
is selected (see Section 12.3 “Prescaler”). If the
TMR0 register is written to, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge
Select bit, T0SE (T0CON). Clearing this bit selects
the rising edge. Restrictions on the external clock input
are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 12-1:
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
12.2
Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0 which is not directly readable nor writable (refer to Figure 12-2). TMR0H is updated with the
contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4
0
1
1
Programmable
Prescaler
T0CKI Pin
T0SE
T0CS
0
Sync with
Internal
Clocks
(2 TCY Delay)
8
3
T0PS
8
PSA
Note:
Set
TMR0IF
on Overflow
TMR0L
Internal Data Bus
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 12-2:
FOSC/4
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
0
1
1
T0CKI Pin
T0SE
T0CS
Programmable
Prescaler
0
Sync with
Internal
Clocks
TMR0
High Byte
TMR0L
8
Set
TMR0IF
on Overflow
(2 TCY Delay)
3
Read TMR0L
T0PS
Write TMR0L
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39774D-page 154
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
12.3
Prescaler
12.3.1
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable.
Its value is set by the PSA and T0PS bits
(T0CON) which determine the prescaler
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256, in power-of-2 increments, are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
TABLE 12-1:
Name
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
12.4
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON). Before
re-enabling the interrupt, the TMR0IF bit must be
cleared in software by the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
TMR0L
Timer0 Register Low Byte
TMR0H
Timer0 Register High Byte
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
T0CON
TMR0ON
TRISA
TRISA7(1) TRISA6(1)
T08BIT
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
58
58
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
57
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
58
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.
Note 1: RA and their associated latch and direction bits are configured as port pins only when the internal
oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are
disabled and these bits read as ‘0’.
2010 Microchip Technology Inc.
DS39774D-page 155
PIC18F85J11 FAMILY
NOTES:
DS39774D-page 156
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
13.0
TIMER1 MODULE
The Timer1 timer/counter module incorporates these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt on overflow
• Reset on CCPx Special Event Trigger
• Device clock status flag (T1RUN)
REGISTER 13-1:
A simplified block diagram of the Timer1 module is
shown in Figure 13-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 13-2.
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
Timer1 is controlled through the T1CON Control
register (Register 13-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON).
T1CON: TIMER1 CONTROL REGISTER
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of TImer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 6
T1RUN: Timer1 System Clock Status bit
1 = Device clock is derived from Timer1 oscillator
0 = Device clock is derived from another source
bit 5-4
T1CKPS: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from the RC0/T1OSO/T13CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
2010 Microchip Technology Inc.
DS39774D-page 157
PIC18F85J11 FAMILY
13.1
Timer1 Operation
cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
Timer1 can operate in one of these modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
When Timer1 is enabled, the RC1/T1OSI and
RC0/T1OSO/T13CKI pins become inputs. This means
the values of TRISC are ignored and the pins are
read as ‘0’.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
FIGURE 13-1:
TIMER1 BLOCK DIAGRAM (8-BIT MODE)
Timer1 Oscillator
Timer1 Clock Input
On/Off
T1OSO/T13CKI
1
1
FOSC/4
Internal
Clock
T1OSI
Synchronize
Prescaler
1, 2, 4, 8
0
2
T1OSCEN(1)
0
Detect
Sleep Input
TMR1CS
Timer1
On/Off
T1CKPS
T1SYNC
TMR1ON
Clear TMR1
(CCPx Special Event Trigger)
Set
TMR1IF
on Overflow
TMR1
High Byte
TMR1L
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 13-2:
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
T1OSO/T13CKI
1
FOSC/4
Internal
Clock
T1OSI
Synchronize
Prescaler
1, 2, 4, 8
0
2
T1OSCEN(1)
T1CKPS
T1SYNC
TMR1ON
0
Detect
Sleep Input
TMR1CS
Clear TMR1
(CCPx Special Event Trigger)
Timer1
On/Off
TMR1
High Byte
TMR1L
8
Set
TMR1IF
on Overflow
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39774D-page 158
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
13.2
Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 13-2). When the RD16 control bit
(T1CON) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
TABLE 13-1:
Oscillator
Type
Freq.
C1
C2
LP
32.768 kHz
27 pF(1)
27 pF(1)
Note 1: Microchip suggests these values as a
starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
13.3
Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins, T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON). The oscillator is a
low-power circuit rated for 32 kHz crystals. It will
continue to run during all power-managed modes. The
circuit for a typical LP oscillator is shown in Figure 13-3.
Table 13-1 shows the capacitor selection for the Timer1
oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 13-3:
EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
C1
27 pF
PIC18F85J11
T1OSI
CAPACITOR SELECTION FOR
THE TIMER1
OSCILLATOR(2,3,4)
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
4: Capacitor values are for design guidance
only.
13.3.1
USING TIMER1 AS A
CLOCK SOURCE
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the System
Clock Select bits, SCS (OSCCON), to ‘01’,
the device switches to SEC_RUN mode; both the CPU
and peripherals are clocked from the Timer1 oscillator.
If the IDLEN bit (OSCCON) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 4.0
“Power-Managed Modes”.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN
(T1CON), is set. This can be used to determine the
controller’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
Clock Monitor. If the Fail-Safe Clock Monitor is enabled
and the Timer1 oscillator fails while providing the clock,
polling the T1RUN bit will indicate whether the clock is
being provided by the Timer1 oscillator or another
source.
XTAL
32.768 kHz
T1OSO
C2
27 pF
Note:
See the Notes with Table 13-1 for additional
information about capacitor selection.
2010 Microchip Technology Inc.
DS39774D-page 159
PIC18F85J11 FAMILY
13.3.2
TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 13-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the oscillator (such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 13-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
FIGURE 13-4:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
13.5
Resetting Timer1 Using the CCPx
Special Event Trigger
If CCP1 or CCP2 is configured to use Timer1 and to
generate a Special Event Trigger in Compare mode
(CCPxM = 1011), this signal will reset Timer3.
The trigger from CCP2 will also start an A/D conversion
if the A/D module is enabled (see Section 16.3.4
“Special Event Trigger” for more information).
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a Period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
Note:
The Special Event Triggers from the CCPx
module will not set the TMR1IF interrupt
flag bit (PIR1).
VDD
VSS
OSC1
OSC2
RC0
RC1
RC2
Note: Not drawn to scale.
13.4
Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1).
13.6
Using Timer1 as a Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 13.3 “Timer1 Oscillator”
above) gives users the option to include RTC functionality to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
The application code routine, RTCisr, shown in
Example 13-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine which increments the seconds counter by
one. Additional counters for minutes and hours are
incremented as the previous counter overflows.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to preload it. The simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1 = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
DS39774D-page 160
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
EXAMPLE 13-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
MOVLW
MOVWF
CLRF
CLRF
MOVLW
MOVWF
BSF
RETURN
80h
TMR1H
TMR1L
b’00001111’
T1CON
secs
mins
.12
hours
PIE1, TMR1IE
BSF
BCF
INCF
MOVLW
CPFSGT
RETURN
CLRF
INCF
MOVLW
CPFSGT
RETURN
CLRF
INCF
MOVLW
CPFSGT
RETURN
CLRF
RETURN
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
secs
; Preload TMR1 register pair
; for 1 second overflow
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
; Enable Timer1 interrupt
RTCisr
TABLE 13-2:
Name
INTCON
secs
mins, F
.59
mins
mins
hours, F
.23
hours
;
;
;
;
Preload for 1 sec overflow
Clear interrupt flag
Increment seconds
60 seconds elapsed?
;
;
;
;
No, done
Clear seconds
Increment minutes
60 minutes elapsed?
;
;
;
;
No, done
clear minutes
Increment hours
24 hours elapsed?
; No, done
; Reset hours
; Done
hours
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
57
Bit 6
GIE/GIEH PEIE/GIEL
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
—
TMR2IF
TMR1IF
59
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
—
TMR2IE
TMR1IE
59
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
—
TMR2IP
TMR1IP
59
IPR1
TMR1L
Timer1 Register Low Byte
TMR1H
Timer1 Register High Byte
T1CON
RD16
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
58
58
TMR1CS
TMR1ON
58
Legend: Shaded cells are not used by the Timer1 module.
2010 Microchip Technology Inc.
DS39774D-page 161
PIC18F85J11 FAMILY
NOTES:
DS39774D-page 162
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
14.0
TIMER2 MODULE
14.1
Timer2 Operation
• 8-bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler
(1:1, 1:4 and 1:16)
• Software programmable postscaler
(1:1 through 1:16)
• Interrupt on TMR2 to PR2 match
• Optional use as the shift clock for the
MSSP module
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 4-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and
divide-by-16 prescale options. These are selected by
the
prescaler
control
bits,
T2CKPS
(T2CON). The value of TMR2 is compared to that
of the Period register, PR2, on each clock cycle. When
the two values match, the comparator generates a
match signal as the timer output. This signal also resets
the value of TMR2 to 00h on the next cycle and drives
the output counter/postscaler (see Section 14.2
“Timer2 Interrupt”).
The module is controlled through the T2CON register
(Register 14-1) which enables or disables the timer and
configures the prescaler and postscaler. Timer2 can be
shut off by clearing control bit, TMR2ON (T2CON),
to minimize power consumption.
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
A simplified block diagram of the module is shown in
Figure 14-1.
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
The Timer2 module incorporates the following features:
TMR2 is not cleared when T2CON is written.
REGISTER 14-1:
T2CON: TIMER2 CONTROL REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
T2OUTPS3
T2OUTPS2
T2OUTPS1
T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
2010 Microchip Technology Inc.
x = Bit is unknown
DS39774D-page 163
PIC18F85J11 FAMILY
14.2
Timer2 Interrupt
14.3
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1).
Timer2 Output
The unscaled output of TMR2 is available primarily to
the CCP modules where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 17.0
“Master Synchronous Serial Port (MSSP) Module”.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS (T2CON).
FIGURE 14-1:
TIMER2 BLOCK DIAGRAM
4
T2OUTPS
1:1 to 1:16
Postscaler
2
T2CKPS
TMR2
Comparator
8
PR2
8
8
Internal Data Bus
Name
TMR2 Output
(to PWM or MSSP)
TMR2/PR2
Match
Reset
1:1, 1:4, 1:16
Prescaler
FOSC/4
TABLE 14-1:
Set TMR2IF
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7
Bit 6
INTCON GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
57
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
—
TMR2IF
TMR1IF
59
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
—
TMR2IE
TMR1IE
59
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
—
TMR2IP
TMR1IP
59
TMR2
T2CON
PR2
Timer2 Register
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON
58
T2CKPS1 T2CKPS0
Timer2 Period Register
58
58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
DS39774D-page 164
2010 Microchip Technology Inc.
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15.0
TIMER3 MODULE
The Timer3 timer/counter module incorporates these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt on overflow
• Module Reset on CCPx Special Event Trigger
REGISTER 15-1:
A simplified block diagram of the Timer3 module is
shown in Figure 15-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 15-2.
The Timer3 module is controlled through the T3CON
register (Register 15-1). It also selects the clock source
options for the CCP modules. See Section 16.2.2
“Timer1/Timer3 Mode Selection” for more
information.
T3CON: TIMER3 CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
bit 6,3
T3CCP: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the capture/compare clock source for the CCP modules
01 = Timer3 is the capture/compare clock source for CCP2;
Timer1 is the capture/compare clock source for CCP1
00 = Timer1 is the capture/compare clock source for the CCP modules
bit 5-4
T3CKPS: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 2
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge)
0 = Internal clock (FOSC/4)
bit 0
TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
2010 Microchip Technology Inc.
DS39774D-page 165
PIC18F85J11 FAMILY
15.1
Timer3 Operation
The operating mode is determined by the clock select
bit, TMR3CS (T3CON). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (FOSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
FIGURE 15-1:
As
with
Timer1,
the
RC1/T1OSI
and
RC0/T1OSO/T13CKI pins become inputs when the
Timer1 oscillator is enabled. This means the values of
TRISC are ignored and the pins are read as ‘0’.
TIMER3 BLOCK DIAGRAM (8-BIT MODE)
Timer1 Oscillator
Timer1 Clock Input
1
T1OSO/T13CKI
1
FOSC/4
Internal
Clock
T1OSI
Synchronize
Prescaler
1, 2, 4, 8
0
2
T1OSCEN(1)
0
Detect
Sleep Input
TMR3CS
Timer3
On/Off
T3CKPS
T3SYNC
TMR3ON
CCPx Special Event Trigger
CCPx Select from T3CON
Clear TMR3
Set
TMR3IF
on Overflow
TMR3
High Byte
TMR3L
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 15-2:
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
T1OSO/T13CKI
1
FOSC/4
Internal
Clock
T1OSI
Synchronize
Prescaler
1, 2, 4, 8
2
T1OSCEN(1)
0
Detect
0
Sleep Input
TMR3CS
Timer3
On/Off
T3CKPS
T3SYNC
TMR3ON
CCPx Special Event Trigger
CCPx Select from T3CON
Clear TMR3
Set
TMR3IF
on Overflow
TMR3
High Byte
TMR3L
8
Read TMR3L
Write TMR3L
8
8
TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39774D-page 166
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
15.2
Timer3 16-Bit Read/Write Mode
15.4
Timer3 Interrupt
Timer3 can be configured for 16-bit reads and writes
(see Figure 15-2). When the RD16 control bit
(T3CON) is set, the address for TMR3H is mapped
to a buffer register for the high byte of Timer3. A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2).
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
If CCP1 or CCP2 is configured to use Timer3 and to
generate a Special Event Trigger in Compare mode
(CCPxM = 1011), this signal will reset Timer3.
The trigger from CCP2 will also start an A/D conversion
if the A/D module is enabled (see Section 16.3.4
“Special Event Trigger” for more information).
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
15.3
Using the Timer1 Oscillator as the
Timer3 Clock Source
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON) bit. To use it as the
Timer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increment on every rising edge of the oscillator source.
15.5
Resetting Timer3 Using the CCPx
Special Event Trigger
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a Period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from a CCPx module, the write
will take precedence.
Note:
The Special Event Triggers from the CCPx
module will not set the TMR3IF interrupt
flag bit (PIR2).
The Timer1 oscillator is described in Section 13.0
“Timer1 Module”.
TABLE 15-1:
Name
INTCON
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Bit 7
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
57
PIR2
OSCFIF
CMIF
—
—
BCLIF
LVDIF
TMR3IF
—
59
PIE2
OSCFIE
CMIE
—
—
BCLIE
LVDIE
TMR3IE
—
59
IPR2
OSCFIP
CMIP
—
—
BCLIP
LVDIP
TMR3IP
—
59
TMR3L
Timer3 Register Low Byte
59
TMR3H
Timer3 Register High Byte
59
T1CON
RD16
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS
TMR1ON
58
T3CON
RD16
T3CCP2
T3CKPS1 T3CKPS0
TMR3CS
TMR3ON
59
T3CCP1
T3SYNC
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
2010 Microchip Technology Inc.
DS39774D-page 167
PIC18F85J11 FAMILY
NOTES:
DS39774D-page 168
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
16.0
CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F85J11 family devices have two CCP
(Capture/Compare/PWM) modules, designated CCP1
and CCP2. Both modules implement standard Capture,
Compare and Pulse-Width Modulation (PWM) modes.
REGISTER 16-1:
Each CCP module contains a 16-bit register which can
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP module operation in the
following sections is described with respect to CCP2,
but is equally applicable to CCP1.
CCPxCON: CCPx CONTROL REGISTER (CCP1, CCP2 MODULES)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DCxB: PWM Duty Cycle bit 1 and bit 0 for CCPx Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM: CCPx Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit
is set)
1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit
is set)
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
reflects I/O state)
1011 = Compare mode: Special Event Trigger; reset timer; start A/D conversion on CCPx match
(CCPxIF bit is set)(1)
11xx = PWM mode
Note 1:
CCPxM = 1011 will only reset the timer and not start an A/D conversion on CCPx match.
2010 Microchip Technology Inc.
DS39774D-page 169
PIC18F85J11 FAMILY
16.1
CCP Module Configuration
Depending on the configuration selected, up to four
timers may be active at once, with modules in the same
configuration (Capture/Compare or PWM) sharing
timer resources. The possible configurations are
shown in Figure 16-1.
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
16.1.1
16.1.2
When operating in Output mode (i.e., in Compare or
PWM modes), the drivers for the CCPx pins can be
optionally configured as open-drain outputs. This
feature allows the voltage level on the pin to be pulled
to a higher level through an external pull-up resistor
and allows the output to communicate with external
circuits without the need for additional level shifters.
CCP MODULES AND TIMER
RESOURCES
The CCP modules utilize Timers 1, 2 or 3, depending
on the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare mode, while Timer2
is available for modules in PWM mode.
TABLE 16-1:
The open-drain output option is controlled by the
CCP2OD and CCP1OD bits (TRISG). Setting the
appropriate bit configures the pin for the corresponding
module for open-drain operation.
CCPx MODE – TIMER
RESOURCE
CCPx Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
16.1.3
Changing the pin assignment of CCP2 does not
automatically change any requirements for configuring
the port pin. Users must always verify that the appropriate TRIS register is configured correctly for CCP2
operation, regardless of where it is located.
CCPx AND TIMER INTERCONNECT CONFIGURATIONS
T3CCP = 00
T3CCP = 01
TMR1
TMR1
TMR3
CCP1
TMR3
CCP1
TMR2
Timer1 is used for all Capture
and Compare operations for
all CCP modules. Timer2 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
T3CCP = 1x
TMR1
TMR3
CCP1
CCP2
DS39774D-page 170
CCP2 PIN ASSIGNMENT
The pin assignment for CCP2 (Capture input, Compare
and PWM output) can change, based on device configuration. The CCP2MX Configuration bit determines
which pin CCP2 is multiplexed to. By default, it is
assigned to RC1 (CCP2MX = 1). If the Configuration bit
is cleared, CCP2 is multiplexed with RE7.
The assignment of a particular timer to a module is
determined by the timer to CCPx enable bits in the
T3CON register (Register 15-1). Both modules may be
active at any given time and may share the same timer
resource if they are configured to operate in the same
mode (Capture/Compare or PWM) at the same time.
The interactions between the two modules are
summarized in Table 16-2.
FIGURE 16-1:
OPEN-DRAIN OUTPUT OPTION
CCP2
TMR2
Timer1 is used for Capture
and Compare operations for
CCP1 and Timer 3 is used for
CCP2.
Both the modules use Timer2
as a common time base if they
are in PWM modes.
CCP2
TMR2
Timer3 is used for all Capture
and Compare operations for
all CCP modules. Timer2 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 16-2:
INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES
CCP1 Mode CCP2 Mode
Interaction
Capture
Capture
Each module can use TMR1 or TMR3 as the time base. The time base can be different
for each CCP module.
Capture
Compare
CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Automatic A/D conversions on trigger event
can also be done. Operation of CCP1 could be affected if it is using the same timer as a
time base.
Compare
Capture
CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Operation of CCP2 could be affected if it is
using the same timer as a time base.
Compare
Compare
Either module can be configured for the Special Event Trigger to reset the time base.
Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if
both modules are using the same time base.
Capture
PWM
None
Compare
PWM
None
PWM
Capture
None
PWM
Compare
None
PWM
PWM
Both PWMs will have the same frequency and update rate (TMR2 interrupt).
2010 Microchip Technology Inc.
DS39774D-page 171
PIC18F85J11 FAMILY
16.2
Capture Mode
16.2.3
SOFTWARE INTERRUPT
In Capture mode, the CCPR2H:CCPR2L register pair
captures the 16-bit value of the TMR1 or TMR3 register
when an event occurs on the CCP2 pin (RB3, RC1 or
RE7, depending on device configuration). An event is
defined as one of the following:
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP2IE bit (PIE3) clear to avoid false interrupts
and should clear the flag bit, CCP2IF, following any
such change in operating mode.
•
•
•
•
16.2.4
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
There are four prescaler settings in Capture mode.
They are specified as part of the operating mode
selected by the mode select bits (CCP2M).
Whenever the CCP2 module is turned off, or the CCP2
module is not in Capture mode, the prescaler counter
is cleared. This means that any Reset will clear the
prescaler counter.
The event is selected by the mode select bits,
CCP2M (CCP2CON). When a capture is
made, the interrupt request flag bit, CCP2IF (PIR3),
is set; it must be cleared in software. If another capture
occurs before the value in register CCPR2 is read, the
old captured value is overwritten by the new captured
value.
16.2.1
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 16-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
CCPx PIN CONFIGURATION
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
EXAMPLE 16-1:
Note: If RB3/INT3/CCP2, RC1/T1OSI/CCP2 or
RE7/CCP2 is configured as an output, a write
to the port can cause a capture condition.
16.2.2
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF CCP2CON
; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF CCP2CON
; Load CCP2CON with
; this value
TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer to
be used with each CCP module is selected in the T3CON
register (see Section 16.1.1 “CCP Modules and Timer
Resources”).
FIGURE 16-2:
CCP PRESCALER
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
Set CCP1IF
T3CCP2
CCP1 Pin
Prescaler
1, 4, 16
and
Edge Detect
CCP1CON
Q1:Q4
CCP2CON
4
4
CCPR1L
TMR1
Enable
TMR1H
TMR1L
TMR3H
TMR3L
Set CCP2IF
4
T3CCP1
T3CCP2
CCP2 Pin
Prescaler
1, 4, 16
TMR3
Enable
CCPR1H
T3CCP2
TMR3L
and
Edge Detect
TMR3
Enable
CCPR2H
CCPR2L
TMR1
Enable
T3CCP2
T3CCP1
DS39774D-page 172
TMR1H
TMR1L
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
16.3
Compare Mode
16.3.3
SOFTWARE INTERRUPT MODE
In Compare mode, the 16-bit CCPR2 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP2
pin can be:
When the Generate Software Interrupt mode is chosen
(CCP2M = 1010), the CCP2 pin is not affected.
Only a CCP2 interrupt is generated, if enabled, and the
CCP2IE bit is set.
•
•
•
•
16.3.4
driven high
driven low
toggled (high-to-low or low-to-high)
remains unchanged (that is, reflects the state of
the I/O latch)
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCP2M = 1011).
The action on the pin is based on the value of the mode
select bits (CCP2M). At the same time, the
interrupt flag bit, CCP2IF, is set.
16.3.1
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a Programmable
Period register for either timer.
CCPx PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
Note:
16.3.2
SPECIAL EVENT TRIGGER
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D Converter
must already be enabled.
Clearing the CCP2CON register will force
the RB3, RC1 or RE7 compare output
latch (depending on device configuration)
to the default low level. This is not the
PORTB, PORTC or PORTE I/O data latch.
Note:
TIMER1/TIMER3 MODE SELECTION
The Special Event Trigger of CCP1 only
resets Timer1/Timer3 and cannot start an
A/D conversion even when the A/D
Converter is enabled.
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCPx module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
FIGURE 16-3:
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR1H
Special Event Trigger
(Timer1 Reset)
Set CCP1IF
CCPR1L
CCP1 Pin
Comparator
Output
Logic
Compare
Match
S
Q
R
TRIS
Output Enable
4
CCP1CON
0
TMR1H
TMR1L
0
1
TMR3H
TMR3L
1
T3CCP1
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
T3CCP2
Set CCP2IF
Comparator
CCPR2H
CCPR2L
Compare
Match
CCP2 Pin
Output
Logic
4
S
Q
R
TRIS
Output Enable
CCP2CON
2010 Microchip Technology Inc.
DS39774D-page 173
PIC18F85J11 FAMILY
TABLE 16-3:
Name
INTCON
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Bit 7
Bit 6
Bit 5
GIE/GIEH PEIE/GIEL TMR0IE
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
57
IPEN
—
CM
RI
TO
PD
POR
BOR
58
PIR3
—
—
RC2IF
TX2IF
—
CCP2IF
CCP1IF
—
59
PIE3
—
—
RC2IE
TX2IE
—
CCP2IE
CCP1IE
—
59
IPR3
—
—
RC2IP
TX2IP
—
CCP2IP
CCP1IP
—
59
RCON
PIR2
OSCFIF
CMIF
—
—
BCLIF
LVDIF
TMR3IF
—
59
PIE2
OSCFIE
CMIE
—
—
BCLIE
LVDIE
TMR3IE
—
59
IPR2
OSCFIP
CMIP
—
—
BCLIP
LVDIP
TMR3IP
—
59
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
60
TRISE
TRISE7
TRISE6
TRISE5
TRISG
SPIOD
CCP2OD CCP1OD
TRISE4
TRISE3
—
TRISE1
TRISE0
60
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
60
TMR1L
Timer1 Register Low Byte
58
TMR1H
Timer1 Register High Byte
58
T1CON
RD16
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON
58
TMR3H
Timer3 Register High Byte
59
TMR3L
Timer3 Register Low Byte
59
T3CON
RD16
T3CCP2
T3CKPS1 T3CKPS0
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
CCPR1H
Capture/Compare/PWM Register 1 High Byte
—
CCP1CON
—
DC1B1
DC1B0
T3CCP1
T3SYNC
TMR3CS TMR3ON
59
60
60
CCP1M3
CCP1M2
CCP1M1
CCP1M0
60
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
61
CCPR2H
Capture/Compare/PWM Register 2 High Byte
61
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
61
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
DS39774D-page 174
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
16.4
PWM Mode
In Pulse-Width Modulation (PWM) mode, the CCP2 pin
produces up to a 10-bit resolution PWM output. Since
the CCP2 pin is multiplexed with a PORTB, PORTC or
PORTE data latch, the appropriate TRIS bit must be
cleared to make the CCP2 pin an output.
Note:
A PWM output (Figure 16-5) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 16-5:
PWM OUTPUT
Period
Clearing the CCP2CON register will force
the RB3, RC1 or RE7 output latch
(depending on device configuration) to the
default low level. This is not the PORTB,
PORTC or PORTE I/O data latch.
Duty Cycle
TMR2 = PR2
Figure 16-4 shows a simplified block diagram of the
CCP1 module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 16.4.3
“Setup for PWM Operation”.
FIGURE 16-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty Cycle Registers
TMR2 = Duty Cycle
TMR2 = PR2
16.4.1
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
CCP1CON
EQUATION 16-1:
CCPR1L
PWM Period = (PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
CCPR1H (Slave)
R
Comparator
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
Q
RC2/CCP1
TMR2
Comparator
PR2
Note 1:
(Note 1)
S
TRISC
Clear Timer,
CCP1 pin and
latch D.C.
The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
2010 Microchip Technology Inc.
• TMR2 is cleared
• The CCP2 pin is set (exception: if PWM duty
cycle = 0%, the CCP2 pin will not be set)
• The PWM duty cycle is latched from CCPR2L into
CCPR2H
Note:
The Timer2 postscalers (see Section 14.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
DS39774D-page 175
PIC18F85J11 FAMILY
16.4.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR2L register and to the CCP2CON bits. Up
to 10-bit resolution is available. The CCPR2L contains
the eight MSbs and the CCP2CON contains the
two LSbs. This 10-bit value is represented by
CCPR2L:CCP2CON. The following equation is
used to calculate the PWM duty cycle in time:
EQUATION 16-2:
When the CCPR2H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP2 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 16-3:
PWM Duty Cycle = (CCPR2L:CCP2CON) •
TOSC • (TMR2 Prescale Value)
CCPR2L and CCP2CON can be written to at any
time, but the duty cycle value is not latched into
CCPR2H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR2H is a read-only register.
TABLE 16-4:
The CCPR2H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
F OSC
log ---------------
F PWM
PWM Resolution (max) = -----------------------------bits
log 2
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP2 pin will not be
cleared.
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
DS39774D-page 176
2.44 kHz
9.77 kHz
39.06 kHz
156.25 kHz
312.50 kHz
416.67 kHz
16
4
1
1
1
1
FFh
FFh
FFh
3Fh
1Fh
17h
14
12
10
8
7
6.58
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
16.4.3
SETUP FOR PWM OPERATION
3.
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR2L register and CCP2CON bits.
TABLE 16-5:
Name
INTCON
4.
5.
Make the CCP2 pin an output by clearing the
appropriate TRIS bit.
Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
Configure the CCP2 module for PWM operation.
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
57
CM
RI
TO
PD
POR
BOR
58
RCON
IPEN
—
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
—
TMR2IF
TMR1IF
59
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
—
TMR2IE
TMR1IE
59
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
—
TMR2IP
TMR1IP
59
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
60
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
—
TRISE1
TRISE0
60
TRISG
SPIOD
CCP2OD
CCP1OD
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
60
TMR2
Timer2 Register
PR2
Timer2 Period Register
T2CON
—
58
58
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
58
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
60
CCPR1H
Capture/Compare/PWM Register 1 High Byte
60
CCP1CON
—
—
DC1B1
DC1B0
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
CCPR2H
Capture/Compare/PWM Register 2 High Byte
CCP2CON
—
—
DC2B1
DC2B0
CCP1M3
CCP1M2
CCP1M1 CCP1M0
60
61
61
CCP2M3
CCP2M2
CCP2M1 CCP2M0
61
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
2010 Microchip Technology Inc.
DS39774D-page 177
PIC18F85J11 FAMILY
NOTES:
DS39774D-page 178
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
17.0
17.1
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D Converters, etc. The MSSP
module can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
- Full Master mode
- Slave mode (with general address call)
17.3
SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RF7/AN5/SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
Note:
The I2C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode
17.2
Disabling the MSSP module by clearing
the SSPEN (SSPCON1) bit may not
reset the module. It is recommended to
clear the SSPSTAT, SSPCON1 and
SSPCON2 registers and select the mode
prior to setting the SSPEN bit to enable
the MSSP module.
FIGURE 17-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
Control Registers
Internal
Data Bus
The MSSP module has three associated control
registers. These include a status register (SSPSTAT)
and two control registers (SSPCON1 and SSPCON2).
The use of these registers and their individual bits differ
significantly depending on whether the MSSP module
is operated in SPI or I2C mode.
Additional details are provided under the individual
sections.
Read
Write
SSPBUF reg
SDI
SSPSR reg
SDO
SS
Shift
Clock
bit 0
SS Control
Enable
Edge
Select
2
Clock Select
SSPM
SCK
SMP:CKE 4
2
Edge
Select
(TMR22Output )
Prescaler TOSC
4, 16, 64
Data to TXx/RXx in SSPSR
TRIS bit
2010 Microchip Technology Inc.
DS39774D-page 179
PIC18F85J11 FAMILY
17.3.1
REGISTERS
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
The MSSP module has four registers for SPI mode
operation. These are:
•
•
•
•
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
MSSP Control Register 1 (SSPCON1)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer Register (SSPBUF)
MSSP Shift Register (SSPSR) – Not directly
accessible
During
transmission,
the
SSPBUF
is
not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 17-1:
R/W-0
SMP
SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0
R-0
R-0
R-0
R-0
R0
R-0
(1)
D/A
P
S
R/W
UA
BF
CKE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE: SPI Clock Select bit(1)
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
bit 5
D/A: Data/Address bit
Used in I2C™ mode only.
bit 4
P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled and SSPEN is cleared.
bit 3
S: Start bit
Used in I2C mode only.
bit 2
R/W: Read/Write Information bit
Used in I2C mode only.
bit 1
UA: Update Address bit
Used in I2C mode only.
bit 0
BF: Buffer Full Status bit (Receive mode only)
1 = Receive is complete, SSPBUF is full
0 = Receive is not complete, SSPBUF is empty
Note 1:
The polarity of the clock state is set by the CKP bit (SSPCON1).
DS39774D-page 180
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 17-2:
SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV(1)
SSPEN(2)
CKP
SSPM3(3)
SSPM2(3)
SSPM1(3)
SSPM0(3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting the overflow (must be cleared in software).
0 = No overflow
bit 5
SSPEN: Master Synchronous Serial Port Enable bit(2)
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0
SSPM: Master Synchronous Serial Port Mode Select bits(3)
0101 = SPI Slave mode, clock = SCK pin, SS pin control is disabled, SS can be used as an I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control is enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note 1:
2:
3:
In Master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
When enabled, this pin must be properly configured as an input or output.
Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.
2010 Microchip Technology Inc.
DS39774D-page 181
PIC18F85J11 FAMILY
17.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1 and SSPSTAT).
These control bits allow the following to be specified:
•
•
•
•
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full detect bit, BF
(SSPSTAT), and the MSSP Interrupt Flag bit,
SSPIF, are set. This double-buffering of the received
data (SSPBUF) allows the next byte to start reception
before reading the data that was just received. Any
write to the SSPBUF register during transmission/reception of data will be ignored and the Write
EXAMPLE 17-1:
LOOP
BTFSS
BRA
MOVF
MOVWF
MOVF
MOVWF
DS39774D-page 182
Collision detect bit, WCOL (SSPCON1), will be set.
User software must clear the WCOL bit so that it can be
determined if the following write(s) to the SSPBUF
register completed successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF (SSPSTAT), indicates when
SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF
bit is cleared. This data may be irrelevant if the SPI is
only a transmitter. Generally, the MSSP interrupt is used
to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 17-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the SSPSTAT register indicates the
various status conditions.
Note:
To avoid lost data in Master mode, a
read of the SSPBUF must be performed
to clear the Buffer Full (BF) detect
bit (SSPSTAT) between each
transmission.
LOADING THE SSPBUF (SSPSR) REGISTER
SSPSTAT, BF
LOOP
SSPBUF, W
RXDATA
TXDATA, W
SSPBUF
;Has data been received (transmit complete)?
;No
;WREG reg = contents of SSPBUF
;Save in user RAM, if data is meaningful
;W reg = contents of TXDATA
;New data to xmit
2010 Microchip Technology Inc.
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17.3.3
ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON1), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC bit cleared
• SCK (Master mode) must have TRISC bit
cleared
• SCK (Slave mode) must have TRISC bit set
• SS must have TRISF bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
17.3.4
OPEN-DRAIN OUTPUT OPTION
The drivers for the SDO output and SCK clock pins can
be optionally configured as open-drain outputs. This
feature allows the voltage level on the pin to be pulled
FIGURE 17-2:
to a higher level through an external pull-up resistor,
and allows the output to communicate with external
circuits without the need for additional level shifters.
The open-drain output option is controlled by the
SPIOD bit (TRISG). Setting the bit configures both
pins for open-drain operation.
17.3.5
TYPICAL CONNECTION
Figure 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data–Slave sends dummy data
• Master sends data–Slave sends data
• Master sends dummy data–Slave sends data
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM = 00xx
SPI Slave SSPM = 010x
SDO
SDI
Serial Input Buffer
(SSPBUF)
SDI
Shift Register
(SSPSR)
MSb
Serial Input Buffer
(SSPBUF)
LSb
2010 Microchip Technology Inc.
Shift Register
(SSPSR)
MSb
SCK
PROCESSOR 1
SDO
Serial Clock
LSb
SCK
PROCESSOR 2
DS39774D-page 183
PIC18F85J11 FAMILY
17.3.6
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 17-2) will
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
FIGURE 17-3:
The clock polarity is selected by appropriately
programming the CKP bit (SSPCON1). This, then,
would give waveforms for SPI communication as
shown in Figure 17-3, Figure 17-5 and Figure 17-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user-programmable to be one
of the following:
•
•
•
•
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 17-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 7
bit 0
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
DS39774D-page 184
Next Q4 Cycle
after Q2
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
17.3.7
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCK pin. The Idle
state is determined by the CKP bit (SSPCON1).
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
17.3.8
SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The SPI
must be in Slave mode with SS pin control enabled
(SSPCON1 = 04h). When the SS pin is low, transmission and reception are enabled and the SDO pin is
FIGURE 17-4:
driven. When the SS pin goes high, the SDO pin is no
longer driven, even if in the middle of a transmitted byte
and
becomes
a
floating
output.
External
pull-up/pull-down resistors may be desirable depending
on the application.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON1 = 0100),
the SPI module will reset if the SS pin is set
to VDD.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 6
bit 7
bit 0
bit 0
bit 7
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
2010 Microchip Technology Inc.
Next Q4 Cycle
after Q2
DS39774D-page 185
PIC18F85J11 FAMILY
FIGURE 17-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
FIGURE 17-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
DS39774D-page 186
Next Q4 Cycle
after Q2
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
17.3.9
OPERATION IN POWER-MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in full-power mode; in
the case of Sleep mode, all clocks are halted.
In Idle modes, a clock is provided to the peripherals.
That clock should be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTRC source. See Section 3.3 “Clock Sources
and Oscillator Switching” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the controller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
TABLE 17-2:
Name
INTCON
mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set,
and if enabled, will wake the device.
17.3.10
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.3.11
BUS MODE COMPATIBILITY
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1:
SPI BUS MODES
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0
1
0, 1
0
0
1, 0
1
1
1, 1
1
0
There is also an SMP bit which controls when the data
is sampled.
REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7
Bit 6
Bit 5
GIE/GIEH PEIE/GIEL TMR0IE
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
57
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
—
TMR2IF
TMR1IF
59
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
—
TMR2IE
TMR1IE
59
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
—
TMR2IP
TMR1IP
59
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
60
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
60
TRISG
SPIOD
CCP2OD
CCP1OD
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
60
SSPBUF
MSSP Receive Buffer/Transmit Register
58
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
58
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in SPI mode.
2010 Microchip Technology Inc.
DS39774D-page 187
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17.4
I2C Mode
17.4.1
The MSSP module in I 2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial Clock (SCL) – RC3/SCK/SCL
• Serial Data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs by setting
the TRISC bits.
Note:
Disabling the MSSP module by clearing
the SSPEN (SSPCON1) bit may not
reset the module. It is recommended to
clear the SSPSTAT, SSPCON1 and
SSPCON2 registers and select the mode
prior to setting the SSPEN bit to enable
the MSSP module.
FIGURE 17-7:
MSSP BLOCK DIAGRAM
(I2C™ MODE)
Internal
Data Bus
Read
Write
SSPBUF reg
SCL
SDA
Shift
Clock
SSPSR reg
MSb
LSb
Match Detect
Addr Match
Address Mask
REGISTERS
The MSSP module has six registers for I2C operation.
These are:
•
•
•
•
MSSP Control Register 1 (SSPCON1)
MSSP Control Register 2 (SSPCON2)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
Many of the bits in SSPCON2 assume different
functions, depending on whether the module is operating in Master or Slave mode; SSPCON2 bits also
assume different names in Slave mode. The different
aspects of SSPCON2 are shown in Register 17-5 (for
Master mode) and Register 17-6 (Slave mode).
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address when
the MSSP is configured in I2C Slave mode. When the
MSSP is configured in Master mode, the lower seven
bits of SSPADD act as the Baud Rate Generator reload
value.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During
transmission,
the
SSPBUF
is
not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
SSPADD reg
Start and
Stop bit Detect
DS39774D-page 188
Set, Reset
S, P bits
(SSPSTAT reg)
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REGISTER 17-3:
SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R0
R-0
SMP
CKE
D/A
P(1)
S(1)
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control is enabled for High-Speed mode (400 kHz)
bit 6
CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: Stop bit(1)
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3
S: Start bit(1)
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
bit 2
R/W: Read/Write Information bit (I2C mode only)
In Slave mode:(2)
1 = Read
0 = Write
In Master mode:(3)
1 = Transmit is in progress
0 = Transmit is not in progress
bit 1
UA: Update Address bit (10-Bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
In Transmit mode:
1 = SSPBUF is full
0 = SSPBUF is empty
In Receive mode:
1 = SSPBUF is full (does not include the ACK and Stop bits)
0 = SSPBUF is empty (does not include the ACK and Stop bits)
Note 1:
2:
3:
This bit is cleared on Reset and when SSPEN is cleared.
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.
2010 Microchip Technology Inc.
DS39774D-page 189
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REGISTER 17-4:
R/W-0
WCOL
SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN(1)
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in
software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
SSPEN: Master Synchronous Serial Port Enable bit(1)
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch); used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0
SSPM: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (slave Idle)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
Note 1:
When enabled, the SDA and SCL pins must be configured as inputs.
DS39774D-page 190
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REGISTER 17-5:
SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MASTER MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT(1)
ACKEN(2)
RCEN(2)
PEN(2)
RSEN(2)
SEN(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GCEN: General Call Enable bit
Unused in Master mode.
bit 6
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1 = Not Acknowledge
0 = Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit(2)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit; automatically
cleared by hardware.
0 = Acknowledge sequence Idle
bit 3
RCEN: Receive Enable bit (Master Receive mode only)(2)
1 = Enables Receive mode for I2C
0 = Receive is Idle
bit 2
PEN: Stop Condition Enable bit(2)
1 = Initiate Stop condition on SDA and SCL pins; automatically cleared by hardware.
0 = Stop condition is Idle
bit 1
RSEN: Repeated Start Condition Enable bit(2)
1 = Initiate Repeated Start condition on SDA and SCL pins; automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
SEN: Start Condition Enable bit(2)
1 = Initiate Start condition on SDA and SCL pins; automatically cleared by hardware.
0 = Start condition is Idle
Note 1:
2:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
If the I2C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
2010 Microchip Technology Inc.
DS39774D-page 191
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REGISTER 17-6:
SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ SLAVE MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ADMSK5
ADMSK4
ADMSK3
ADMSK2
ADMSK1
SEN(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GCEN: General Call Enable bit
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit
Unused in Slave mode.
bit 5-2
ADMSK: Slave Address Mask Select bits
1 = Masking of corresponding bits of SSPADD enabled
0 = Masking of corresponding bits of SSPADD disabled
bit 1
ADMSK1: Slave Address Least Significant bit(s) Mask Select bit
In 7-Bit Address mode:
1 = Masking of SSPADD only is enabled
0 = Masking of SSPADD only is disabled
In 10-Bit Address mode:
1 = Masking of SSPADD is enabled
0 = Masking of SSPADD is disabled
bit 0
SEN: Stretch Enable bit(1)
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1:
If the I2C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
DS39774D-page 192
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17.4.2
OPERATION
The MSSP module functions are enabled by setting the
MSSP Enable bit, SSPEN (SSPCON1).
The SSPCON1 register allows control of the I 2C
operation. Four mode selection bits (SSPCON1)
allow one of the following I 2C modes to be selected:
2
• I C Master mode,
clock = (FOSC/4) x (SSPADD + 1)
• I 2C Slave mode (7-bit address)
• I 2C Slave mode (10-bit address)
• I 2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I 2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I 2C Firmware Controlled Master mode,
slave is Idle
Selection of any I 2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCL and SDA pins.
17.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISC set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I 2C Slave mode hardware will always generate an
interrupt on an exact address match. In addition,
address masking will also allow the hardware to generate an interrupt for more than one address (up to 31 in
7-bit addressing and up to 63 in 10-bit addressing).
Through the mode select bits, the user can also choose
to interrupt on Start and Stop bits.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 and
parameter 101.
17.4.3.1
Once the MSSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition, the
8 bits are shifted into the SSPSR register. All incoming
bits are sampled with the rising edge of the clock (SCL)
line. The value of register SSPSR is compared to
the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse.
If the addresses match and the BF and SSPOV bits are
clear, the following events occur:
1.
2.
3.
4.
1.
2.
3.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
5.
• The Buffer Full bit, BF (SSPSTAT), was set
before the transfer was received.
• The MSSP Overflow bit, SSPOV (SSPCON1),
was set before the transfer was received.
6.
2010 Microchip Technology Inc.
The SSPSR register value is loaded into the
SSPBUF register.
The Buffer Full bit, BF, is set.
An ACK pulse is generated.
The MSSP Interrupt Flag bit, SSPIF, is set (and
the interrupt is generated, if enabled) on the
falling edge of the ninth SCL pulse.
In 10-Bit Addressing mode, two address bytes need to
be received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. The R/W bit (SSPSTAT) must specify a
write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the
two MSbs of the address. The sequence of events for
10-bit addressing is as follows, with steps 7 through 9
for the slave-transmitter:
When an address is matched, or the data transfer after
an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse
and load the SSPBUF register with the received value
currently in the SSPSR register.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but the SSPIF bit is set. The BF bit is
cleared by reading the SSPBUF register, while the
SSPOV bit is cleared through software.
Addressing
4.
7.
8.
9.
Receive the first (high) byte of address (bits,
SSPIF, BF and UA (SSPSTAT) are set).
Update the SSPADD register with second (low)
byte of address (clears bit, UA, and releases the
SCL line).
Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
Receive second (low) byte of address (SSPIF,
BF and UA bits are set).
Update the SSPADD register with the first (high)
byte of address. If match releases the SCL line,
this will clear the UA bit.
Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
Receive Repeated Start condition.
Receive first (high) byte of address (SSPIF and
BF bits are set).
Read the SSPBUF register (clears BF bit) and
clear flag bit, SSPIF.
DS39774D-page 193
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17.4.3.2
Address Masking
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-Bit Addressing mode and up to
63 addresses in 10-Bit Addressing mode (see
Example 17-2).
The I2C Slave behaves the same way, whether
address masking is used or not. However, when
address masking is used, the I2C slave can
Acknowledge multiple addresses and cause interrupts.
When this occurs, it is necessary to determine which
address caused the interrupt by checking SSPBUF.
In 7-Bit Addressing mode, Address Mask bits,
ADMSK (SSPCON2), mask the corresponding address bits in the SSPADD register. For any ADMSK
bits that are set (ADMSK = 1), the corresponding
address bit is ignored (SSPADD = x). For the module
EXAMPLE 17-2:
to issue an address Acknowledge, it is sufficient to match
only on addresses that do not have an active address
mask.
In 10-Bit Addressing mode, ADMSK bits mask
the corresponding address bits in the SSPADD register. In addition, ADMSK1 simultaneously masks the two
LSbs of the address (SSPADD). For any ADMSK
bits that are active (ADMSK = 1), the corresponding address bit is ignored (SSPADD = x). Also note
that although in 10-Bit Addressing mode, the upper
address bits reuse part of the SSPADD register bits, the
address mask bits do not interact with those bits. They
only affect the lower address bits.
Note 1: ADMSK1 masks the two Least Significant
bits of the address.
2: The two Most Significant bits of the
address are not affected by address
masking.
ADDRESS MASKING EXAMPLES
7-Bit Addressing:
SSPADD = A0h (1010000) (SSPADD is assumed to be ‘0’)
ADMSK
= 00111
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
10-Bit Addressing:
SSPADD = A0h (10100000) (the two MSbs of the address are ignored in this example, since they are
not affected by masking)
ADMSK
= 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh
DS39774D-page 194
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17.4.3.3
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit, BF (SSPSTAT), is
set or bit, SSPOV (SSPCON1), is set.
An MSSP interrupt is generated for each data transfer
byte. The interrupt flag bit, SSPIF, must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2 = 1), SCK/SCL will
be held low (clock stretch) following each data
transfer. The clock must be released by setting bit,
CKP (SSPCON1). See Section 17.4.4 “Clock
Stretching” for more details.
17.4.3.4
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3 is held low, regardless of SEN (see Section 17.4.4 “Clock Stretching”
for more details). By stretching the clock, the master
will be unable to assert another clock pulse until the
slave is done preparing the transmit data. The transmit
data must be loaded into the SSPBUF register which
also loads the SSPSR register. Then, pin RC3 should
be enabled by setting bit, CKP (SSPCON1). The
eight data bits are shifted out on the falling edge of the
SCL input. This ensures that the SDA signal is valid
during the SCL high time (Figure 17-10).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset and the slave monitors for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPBUF register. Again, pin RC3 must be enabled
by setting bit, CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
2010 Microchip Technology Inc.
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DS39774D-page 196
2
A6
3
4
A4
5
A3
Receiving Address
A5
6
A2
(CKP does not reset to ‘0’ when SEN = 0)
CKP (SSPCON1 25°C. Below 25°C, TCOFF = 0 ms.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048) µs
-(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) µs
1.05 µs
TACQ
=
0.2 µs + 1 µs + 1.2 µs
2.4 µs
DS39774D-page 264
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20.2
Selecting and Configuring
Automatic Acquisition Time
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensuring the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT bits
(ADCON2) remain in their Reset state (‘000’) and
is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQT bits can be set to select a
programmable acquisition time for the A/D module.
When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition
time, then automatically begins a conversion. Since the
acquisition time is programmed, there may be no need
to wait for an acquisition time between selecting a
channel and setting the GO/DONE bit.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
20.3
Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable.
There are seven possible options for TAD:
•
•
•
•
•
•
•
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal RC Oscillator
TABLE 20-1:
TAD vs. DEVICE OPERATING
FREQUENCIES
AD Clock Source (TAD)
Operation
ADCS
Maximum
Device
Frequency
2 TOSC
000
2.86 MHz
TOSC
100
5.71 MHz
8 TOSC
001
11.43 MHz
16 TOSC
101
22.86 MHz
32 TOSC
010
40.0 MHz
64 TOSC
110
40.0 MHz
RC(1)
x11
1.00 MHz(2)
4
Note 1:
2:
20.4
The RC source has a typical TAD time of
4 s.
For device frequencies above 1 MHz, the
device must be in Sleep mode for the
entire conversion or the A/D accuracy may
be out of specification.
Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
The A/D operation is independent of the state of the
CHS bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible but greater than the
minimum TAD (see parameter 130 in Table 26-26 for
more information).
Table 20-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
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20.5
A/D Conversions
20.6
Figure 20-3 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
An A/D conversion can be started by the “Special Event
Trigger” of the CCP2 module. This requires that the
CCP2M bits (CCP2CON) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE bit
will be set, starting the A/D acquisition and conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate TACQ time is selected before
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
Figure 20-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the ACQT
bits have been set to ‘010’ and a 4 TAD acquisition
time has been selected before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means that the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
After the A/D conversion is completed or aborted, a
2 TAD Wait is required before the next acquisition can
be started. After this Wait, acquisition on the selected
channel is automatically started.
Note:
Use of the CCP2 Trigger
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 20-3:
A/D CONVERSION TAD CYCLES (ACQT = 000, TACQ = 0)
TCY – TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b4
b1
b0
b6
b7
b2
b9
b8
b3
b5
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
Next Q4: ADRESH/ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
A/D CONVERSION TAD CYCLES (ACQT = 010, TACQ = 4 TAD)
FIGURE 20-4:
TAD Cycles
TACQT Cycles
1
2
3
Automatic
Acquisition
Time
4
1
3
4
5
6
7
8
9
10
11
b8
b7
b6
b5
b4
b3
b2
b1
b0
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
DS39774D-page 266
2
b9
Next Q4: ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
20.7
A/D Converter Calibration
The A/D Converter in the PIC18F85J11 family of
devices includes a self-calibration feature which compensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON0). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for offset. Thus, subsequent offsets will
be compensated.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
20.8
Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
TABLE 20-2:
Name
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT and
ADCS bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been
completed. If desired, the device may be placed into
the corresponding power-managed Idle mode during
the conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in the Sleep mode requires the A/D RC clock
to be selected. If bits, ACQT, are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCS bits in the OSCCON register must have
already been cleared prior to starting the conversion.
SUMMARY OF A/D REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
57
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
—
TMR2IF
TMR1IF
59
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
—
TMR2IE
TMR1IE
59
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
—
TMR2IP
TMR1IP
59
PIR3
—
—
RC2IF
TX2IF
—
CCP2IF
CCP1IF
—
59
PIE3
—
—
RC2IE
TX2IE
—
CCP2IE
CCP1IE
—
59
—
—
RC2IP
TX2IP
—
CCP2IP
CCP1IP
—
59
INTCON
IPR3
GIE/GIEH PEIE/GIEL
ADRESH
A/D Result Register High Byte
59
ADRESL
A/D Result Register Low Byte
59
ADCON0
ADCAL
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
59
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
59
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
59
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
60
PORTA
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
60
TRISA
TRISA7(1)
TRISA6(1)
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
60
CCP2CON
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
60
TRISF
TRISF5
TRISF4
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal
oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are
disabled and these bits read as ‘0’.
2010 Microchip Technology Inc.
DS39774D-page 267
PIC18F85J11 FAMILY
NOTES:
DS39774D-page 268
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
21.0
COMPARATOR MODULE
The analog comparator module contains two
comparators that can be configured in a variety of
ways. The inputs can be selected from the analog
inputs multiplexed with pins RF1 through RF6, as well
as the on-chip voltage reference (see Section 22.0
“Comparator Voltage Reference Module”). The digital outputs (normal or inverted) are available at the pin
level and can also be read through the control register.
REGISTER 21-1:
The CMCON register (Register 21-1) selects the
comparator input and output configuration. Block
diagrams of the various comparator configurations are
shown in Figure 21-1.
CMCON: COMPARATOR MODULE CONTROL REGISTER
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1:
1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1:
1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VIN-
bit 5
C2INV: Comparator 2 Output Inversion bit
1 = C2 output is inverted
0 = C2 output is not inverted
bit 4
C1INV: Comparator 1 Output Inversion bit
1 = C1 output is inverted
0 = C1 output is not inverted
bit 3
CIS: Comparator Input Switch bit
When CM = 110:
1 = C1 VIN- connects to RF5/AN10/CVREF,
C2 VIN- connects to RF3/AN8
0 = C1 VIN- connects to RF6/AN11,
C2 VIN- connects to RF4/AN9
bit 2-0
CM: Comparator Mode bits
Figure 21-1 shows the Comparator modes and the CM bit settings.
2010 Microchip Technology Inc.
x = Bit is unknown
DS39774D-page 269
PIC18F85J11 FAMILY
21.1
Comparator Configuration
There are eight modes of operation for the comparators, shown in Figure 21-1. Bits, CM of the
CMCON register, are used to select these modes. The
TRISF register controls the data direction of the
comparator pins for each mode. If the Comparator
FIGURE 21-1:
A
VIN-
RF5/AN10/ A
CVREF
VIN+
RF4/AN9
VIN-
RF3/AN8
A
A
Comparator interrupts should be disabled
during a Comparator mode change;
otherwise, a false interrupt may occur.
VIN+
Comparators Off (POR Default Value)
CM = 111
C1
Off (Read as ‘0’)
C2
Off (Read as ‘0’)
Two Independent Comparators
CM = 010
A
VIN-
RF5/AN10/ A
CVREF
VIN+
RF4/AN9
A
VIN-
RF3/AN8
A
VIN+
RF6/AN11
Note:
COMPARATOR I/O OPERATING MODES
Comparator Outputs Disabled
CM = 000
RF6/AN11
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
Section 26.0 “Electrical Characteristics”.
RF6/AN11
D
VIN-
RF5/AN10/
CVREF
D
VIN+
RF4/AN9
D
VIN-
RF3/AN8
D
VIN+
Off (Read as ‘0’)
C2
Off (Read as ‘0’)
Two Independent Comparators with Outputs
CM = 011
A
VIN-
RF5/AN10/ A
CVREF
VIN+
RF6/AN11
C1
C1
C1OUT
C1
C1OUT
C2
C2OUT
RF2/AN7/C1OUT*
C2
C2OUT
RF4/AN9
A
VIN-
RF3/AN8
A
VIN+
RF1/AN6/C2OUT*
Two Common Reference Comparators
CM = 100
A
VIN-
RF5/AN10/ A
CVREF
VIN+
RF4/AN9
A
VIN-
RF3/AN8
D
VIN+
RF6/AN11
Two Common Reference Comparators with Outputs
CM = 101
RF6/AN11
C1
C1OUT
RF5/AN10
CVREF
A
VIN-
A
VIN+
C1
C1OUT
C2
C2OUT
RF2/AN7/C1OUT*
C2
C2OUT
RF4/AN9
A
VIN-
RF3/AN8
D
VIN+
RF1/AN6/C2OUT*
One Independent Comparator with Output
CM = 001
A
VIN-
RF5/AN10/ A
CVREF
VIN+
RF6/AN11
C1
C1OUT
RF2/AN7/C1OUT*
RF4/AN9
D
VIN-
RF3/AN8
D
VIN+
C2
Off (Read as ‘0’)
Four Inputs Multiplexed to Two Comparators
CM = 110
RF6/AN11
A
RF5/AN10/
CVREF
A
RF4/AN9
A
RF3/AN8
A
CIS = 0
CIS = 1
VIN-
CIS = 0
CIS = 1
VIN-
VIN+
VIN+
C1
C1OUT
C2
C2OUT
CVREF
From VREF module
A = Analog Input, port reads zeros always
D = Digital Input
CIS (CMCON) is the Comparator Input Switch
* Setting the TRISF bits will disable the comparator outputs by configuring the pins as inputs.
DS39774D-page 270
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
21.2
Comparator Operation
21.3.2
A single comparator is shown in Figure 21-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 21-2 represent
the uncertainty due to input offsets and response time.
21.3
Comparator Reference
Depending on the comparator operating mode, either
an external or internal voltage reference may be used.
The analog signal present at VIN- is compared to the
signal at VIN+ and the digital output of the comparator
is adjusted accordingly (Figure 21-2).
FIGURE 21-2:
SINGLE COMPARATOR
VIN+
+
VIN-
–
Output
VINVIN+
Output
21.3.1
INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an
internally generated voltage reference from the
comparator voltage reference module. This module is
described in more detail in Section 22.0 “Comparator
Voltage Reference Module”.
The internal reference is only available in the mode
where four inputs are multiplexed to two comparators
(CM = 110). In this mode, the internal voltage
reference is applied to the VIN+ pin of both
comparators.
21.4
Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (see Section 26.0
“Electrical Characteristics”).
21.5
Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RF1 and RF2
I/O pins. When enabled, multiplexors in the output path
of the RF1 and RF2 pins will switch and the output of
each pin will be the unsynchronized output of the
comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 21-3 shows the comparator output block
diagram.
The TRISF bits will still function as output enables/
disables for the RF1 and RF2 pins while in this mode.
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the comparators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
2010 Microchip Technology Inc.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON).
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin defined as a
digital input may cause the input buffer to
consume more current than is specified.
DS39774D-page 271
PIC18F85J11 FAMILY
Port Pins
+
COMPARATOR OUTPUT BLOCK DIAGRAM
MULTIPLEX
FIGURE 21-3:
To RF1 or
RF2 Pin
D
Bus
Data
Q
CxINV
Read CMCON
EN
D
Q
EN
CL
From
Other
Comparator
Reset
21.6
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON, to
determine the actual change that occurred. The CMIF
bit (PIR2) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
Both the CMIE bit (PIE2) and the PEIE bit (INTCON) must be set to enable the interrupt. In addition, the GIE bit (INTCON) must also be set. If any
of these bits are clear, the interrupt is not enabled,
though the CMIF bit will still be set if an interrupt
condition occurs.
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2)
interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
Set
CMIF
bit
21.7
Comparator Operation
During Sleep
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
Each operational comparator will consume additional
current, as shown in the comparator specifications. To
minimize power consumption while in Sleep mode, turn
off the comparators (CM = 111) before entering
Sleep. If the device wakes up from Sleep, the contents
of the CMCON register are not affected.
21.8
Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator modules to be turned off
(CM = 111). However, the input pins (RF3
through RF6) are configured as analog inputs by
default on device Reset. The I/O configuration for these
pins is determined by the setting of the PCFG bits
(ADCON1). Therefore, device current is
minimized when analog inputs are present at Reset
time.
Any read or write of CMCON will end the
mismatch condition.
Clear flag bit, CMIF.
A mismatch condition will continue to set flag bit, CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit, CMIF, to be cleared.
DS39774D-page 272
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
21.9
Analog Input Connection
Considerations
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 k is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
A simplified circuit for an analog input is shown in
Figure 21-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
FIGURE 21-4:
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RS < 10k
RIC
Comparator
Input
AIN
CPIN
5 pF
VA
VT = 0.6V
ILEAKAGE
±500 nA
VSS
Legend:
TABLE 21-1:
Name
INTCON
CPIN
VT
ILEAKAGE
RIC
RS
VA
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the pin due to various junctions
Interconnect Resistance
Source Impedance
Analog Voltage
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
57
PIR2
OSCFIF
CMIF
—
—
BCLIF
LVDIF
TMR3IF
—
59
PIE2
OSCFIE
CMIE
—
—
BCLIE
LVDIE
TMR3IE
—
59
IPR2
OSCFIP
CMIP
—
—
BCLIP
LVDIP
TMR3IP
—
59
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
59
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
59
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
60
PORTF
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
—
60
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
60
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
2010 Microchip Technology Inc.
DS39774D-page 273
PIC18F85J11 FAMILY
NOTES:
DS39774D-page 274
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
22.0
COMPARATOR VOLTAGE
REFERENCE MODULE
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable reference
voltage. Although its primary purpose is to provide a
reference for the analog comparators, it may also be
used independently of them.
A block diagram of the module is shown in Figure 22-1.
The resistor ladder is segmented to provide two ranges
of CVREF values and has a power-down function to
conserve power when the reference is not being used.
The module’s supply reference can be provided from
either device VDD/VSS or an external voltage reference.
22.1
Configuring the Comparator
Voltage Reference
The comparator voltage reference module is controlled
through the CVRCON register (Register 22-1). The
comparator voltage reference provides two ranges of
output voltage, each with 16 distinct levels.
REGISTER 22-1:
The range to be used is selected by the CVRR bit
(CVRCON). The primary difference between the
ranges is the size of the steps selected by the CVREF
Selection bits (CVR), with one range offering finer
resolution. The equations used to calculate the output
of the comparator voltage reference are as follows:
If CVRR = 1:
CVREF = ((CVR)/24) x (CVRSRC)
If CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR)/32) x (CVRSRC)
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit
(CVRCON).
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output (see Table 26-3 in Section 26.0 “Electrical
Characteristics”).
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE(1)
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit is powered on
0 = CVREF circuit is powered down
bit 6
CVROE: Comparator VREF Output Enable bit(1)
1 = CVREF voltage level is also output on the RF5/AN10/CVREF pin
0 = CVREF voltage is disconnected from the RF5/AN10/CVREF pin
bit 5
CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
bit 4
CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator reference source, CVRSRC = VDD – VSS
bit 3-0
CVR: Comparator VREF Value Selection bits (0 (CVR) 15)
When CVRR = 1:
CVREF = ((CVR)/24) (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR)/32) (CVRSRC)
Note 1:
CVROE overrides the TRISF bit setting.
2010 Microchip Technology Inc.
DS39774D-page 275
PIC18F85J11 FAMILY
FIGURE 22-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+
VDD
CVRSS = 1
8R
CVRSS = 0
CVR
R
CVREN
R
R
16-to-1 MUX
R
16 Steps
R
CVREF
R
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
22.2
Comparator Voltage Reference
Accuracy/Error
The full range of comparator voltage reference cannot
be realized due to the construction of the module. The
transistors on the top and bottom of the resistor ladder
network (Figure 22-1) keep CVREF from approaching the
reference source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be found
in Section 26.0 “Electrical Characteristics”.
22.3
Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the comparator
voltage reference should be disabled.
22.4
Effects of a Reset
A device Reset disables the comparator voltage
reference by clearing bit, CVREN (CVRCON). This
Reset also disconnects the reference from the RA2 pin
by clearing bit, CVROE (CVRCON) and selects the
high-voltage range by clearing bit, CVRR
(CVRCON). The CVR value select bits are
also cleared.
22.5
Connection Considerations
The comparator voltage reference module operates
independently of the comparator module. The output of
the reference generator may be connected to the RF5
pin if the CVROE bit is set. Enabling the voltage reference output onto RA2 when it is configured as a digital
input will increase current consumption. Connecting
RF5 as a digital output with CVRSS enabled will also
increase current consumption.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the comparator voltage reference output for external connections to VREF.
Figure 22-2 shows an example buffering technique.
DS39774D-page 276
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 22-2:
COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC18F85J11
R(1)
CVREF
Module
Note 1:
TABLE 22-1:
Name
CVRCON
Voltage
Reference
Output
Impedance
+
–
RF5
CVREF Output
R is dependent upon the Comparator Voltage Reference bits, CVRCON.
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
59
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
59
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.
2010 Microchip Technology Inc.
DS39774D-page 277
PIC18F85J11 FAMILY
NOTES:
DS39774D-page 278
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
23.0
SPECIAL FEATURES OF THE
CPU
PIC18F85J11 family devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These are:
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 3.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F85J11 family of
devices have a configurable Watchdog Timer which is
controlled in software.
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executed
almost immediately on start-up while the primary clock
source completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
23.1
Configuration Bits
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 300000h. A
complete list is shown in Table 23-2. A detailed
explanation of the various bit functions is provided in
Register 23-1 through Register 23-6.
23.1.1
CONSIDERATIONS FOR
CONFIGURING THE PIC18F85J11
FAMILY DEVICES
Unlike some previous PIC18 microcontrollers, devices
of the PIC18F85J11 family do not use persistent
memory registers to store configuration information.
The Configuration registers, CONFIG1L through
CONFIG4H, are implemented as volatile memory.
Immediately after power-up, or after a device Reset,
the microcontroller hardware automatically loads the
CONFIG1L through CONFIG4L registers with configuration data stored in nonvolatile Flash program
memory. The last four words of Flash program memory,
known as the Flash Configuration Words (FCW), are
used to store the configuration data. Table 23-1
provides the Flash program memory, which will be
loaded into the corresponding Configuration register.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
The volatile memory cells used for the Configuration
bits always reset to ‘1’ on Power-on Resets. For all
other types of Reset events, the previously
programmed values are maintained and used without
reloading from program memory.
The four Most Significant bits of CONFIG1H,
CONFIG2H and CONFIG3H in program memory
should also be ‘1111’. This makes these Configuration
Words appear to be NOP instructions in the remote
event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
TABLE 23-1:
Configuration
Byte
CONFIG1L
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG3L
CONFIG3H
2010 Microchip Technology Inc.
MAPPING OF THE FLASH
CONFIGURATION WORDS TO
THE CONFIGURATION
REGISTERS
Code Space
Address
Configuration
Register
Address
XXXF8h
XXXF9h
XXXFAh
XXXFBh
XXXFCh
XXXFDh
300000h
300001h
300002h
300003h
300004h
300005h
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PIC18F85J11 FAMILY
TABLE 23-2:
CONFIGURATION BITS AND DEVICE IDs
File Name
300000h CONFIG1L
Default/
Unprogrammed
Value(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DEBUG
XINST
STVREN
—
—
—
—
WDTEN
111- ---1
---- 01--
(2)
(2)
(2)
(2)
300001h CONFIG1H
—
300002h CONFIG2L
IESO
FCMEN
—
—
300003h CONFIG2H
—(2)
—(2)
—(2)
—(2)
300004h CONFIG3L(4)
WAIT
BW
EMB1
EMB0
(2)
(2)
(2)
(2)
—
CP0
—
—
FOSC2
FOSC1
FOSC0
11-- -111
WDTPS3 WDTPS2 WDTPS1 WDTPS0
---- 1111
EASHFT
—
—
—
1111 1------ ---1
—
—
—
CCP2MX
DEV0
REV4
REV3
REV2
REV1
REV0
xxxx xxxx(5)
3FFFFFh DEVID2
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
0000 10x1(5)
3:
4:
5:
—
—
DEV1
2:
—
—
DEV2
Legend:
Note 1:
—
—
3FFFFEh DEVID1
300005h CONFIG3H
—
—
(3)
x = unknown, — = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset
states, the configuration bytes maintain their previously programmed states.
The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it
is accidentally executed.
This bit should always be maintained as ‘0’.
CONFIG3L is implemented in 80-pin devices only.
See Register 23-7 and Register 23-8 for DEVID values. These registers are read-only and cannot be programmed by
the user.
DS39774D-page 280
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PIC18F85J11 FAMILY
REGISTER 23-1:
CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
R/WO-1
R/WO-1
R/WO-1
U-0
U-0
U-0
U-0
R/WO-1
DEBUG
XINST
STVREN
—
—
—
—
WDTEN
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
DEBUG: Background Debugger Enable bit
1 = Background debugger is disabled; RB6 and RB7 are configured as general purpose I/O pins
0 = Background debugger is enabled; RB6 and RB7 are dedicated to in-circuit debug
bit 6
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode are enabled
0 = Instruction set extension and Indexed Addressing mode are disabled (Legacy mode)
bit 5
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow is enabled
0 = Reset on stack overflow/underflow is disabled
bit 4-1
Unimplemented: Read as ‘0’
bit 0
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
REGISTER 23-2:
CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
U-0
U-0
U-0
U-0
U-0
R/WO-1
U-0
U-0
—(1)
—(1)
—(1)
—(1)
—(2)
CP0
—
—
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
-n = Value when device is unprogrammed
bit 7-4
Unimplemented: Read as ‘1’(1)
bit 3
Unimplemented: Read as ‘0’(2)
bit 2
CP0: Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is code-protected
bit 1-0
Unimplemented: Read as ‘0’
Note 1:
2:
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOP if it is accidentally executed.
This bit should always be maintained as ‘0’.
2010 Microchip Technology Inc.
DS39774D-page 281
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REGISTER 23-3:
R/WO-1
IESO
bit 7
CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
R/WO-1
U-0
U-0
U-0
R/WO-1
R/WO-1
R/WO-1
FCMEN
—
—
—
FOSC2
FOSC1
FOSC0
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit
1 = Two-Speed Start-up is enabled
0 = Two-Speed Start-up is disabled
bit 6
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
Unimplemented: Read as ‘0’
bit 5-3
bit 2-0
FOSC: Oscillator Selection bits
111 = OSC1/OSC2 as primary; EC oscillator with CLKO function and software controlled
PLL (ECPLL)
110 = OSC1/OSC2 as primary; EC oscillator with CLKO function (EC)
101 = OSC1/OSC2 as primary; HS oscillator with software controlled PLL (HSPLL)
100 = OSC1/OSC2 as primary; HS oscillator (HS)
011 = INTOSC with CLKO as primary; port function on RA7; EC oscillator with CLKO function and
software controlled PLL (ECPLL)
010 = INTOSC with CLKO as primary; port function on RA7; EC oscillator with CLKO function
001 = INTOSC as primary with port function on RA; HS oscillator with software controlled
PLL (HSPLL)
000 = INTOSC as primary with port function on RA; HS oscillator (HS)
DS39774D-page 282
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 23-4:
U-0
—(1)
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
—(1)
U-0
—(1)
U-0
—(1)
R/WO-1
WDTPS3
R/WO-1
WDTPS2
R/WO-1
WDTPS1
R/WO-1
WDTPS0
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘1’(1)
bit 3-0
WDTPS: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
Note 1:
The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOP if it is accidentally executed.
2010 Microchip Technology Inc.
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PIC18F85J11 FAMILY
REGISTER 23-5:
R/WO-1
CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1)
R/WO-1
R/WO-1
R/WO-1
R/WO-1
U-0
U-0
U-0
BW
EMB1
EMB0
EASHFT
—
—
—
WAIT
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
WAIT: External Bus Wait Enable bit
1 = Wait selections from the WAIT bits (MEMCON) are unavailable and the device will not wait
0 = Wait programmed by the WAIT bits (MEMCON)
bit 6
BW: Data Bus Width Select bit
1 = 16-Bit External Bus mode
0 = 8-Bit External Bus mode
EMB: External Memory Bus Configuration bits
00 = Extended Microcontroller mode – 20-Bit Addressing mode
01 = Extended Microcontroller mode – 16-Bit Addressing mode
10 = Extended Microcontroller mode – 12-Bit Addressing mode
11 = Microcontroller mode – external bus disabled
EASHFT: External Address Bus Shift Enable bit
1 = Address shifting enabled – external address bus is shifted to start at 000000h
0 = Address shifting disabled – external address bus reflects the PC value
bit 5-4
bit 3
bit 2-0
Note 1:
Unimplemented: Read as ‘0’
CONFIG3L and its associated bits are implemented only in 80-pin devices.
REGISTER 23-6:
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/WO-1
—(1)
—(1)
—(1)
—(1)
—
—
—
CCP2MX
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-1
Unimplemented: Read as ‘1’(1)
bit 0
CCP2MX: CCP2 MUX bit
1 = CCP2 is multiplexed with RC1
0 = CCP2 is multiplexed with RE7 in Microcontroller mode (all devices) or with RB3 in Extended
Microcontroller mode (80-pin devices only)
Note 1:
The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOP if it is accidentally executed.
DS39774D-page 284
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 23-7:
DEVID1: DEVICE ID REGISTER 1 FOR PIC18F85J11 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Read-only bit
bit 7-5
DEV: Device ID bits
111 = PIC18F85J11
101 = PIC18F84J11
100 = PIC18F83J11
011 = PIC18F65J11
001 = PIC18F64J11
000 = PIC18F63J11
bit 4-0
REV: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 23-8:
DEVID2: DEVICE ID REGISTER 2 FOR PIC18F85J11 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV10(1)
DEV9(1)
DEV8(1)
DEV7(1)
DEV6(1)
DEV5(1)
DEV4(1)
DEV3(1)
bit 7
bit 0
Legend:
R = Read-only bit
bit 7-0
Note 1:
DEV: Device ID bits(1)
These bits are used with the DEV bits in the Device ID Register 1 to identify the part number.
0011 1001 = PIC18F6XJ11/8XJ11 devices
The values for DEV may be shared with other device families. The specific device is always
identified by using the entire DEV bit sequence.
2010 Microchip Technology Inc.
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PIC18F85J11 FAMILY
23.2
Watchdog Timer (WDT)
For PIC18F85J11 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period is
4 ms and has the same stability as the INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared whenever a SLEEP or
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
FIGURE 23-1:
SWDTEN
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
23.2.1
CONTROL REGISTER
The WDTCON register (Register 23-9) is a readable
and writable register. The SWDTEN bit enables or disables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
WDT BLOCK DIAGRAM
Enable WDT
INTRC Control
WDT Counter
INTRC Oscillator
Programmable Postscaler
1:1 to 1:32,768
CLRWDT
All Device Resets
WDTPS
Wake-up from
Power-Managed
Modes
128
4
Reset
WDT
Reset
WDT
Sleep
DS39774D-page 286
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 23-9:
R/W-0
(1)
REGSLP
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
SWDTEN(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
REGSLP: Voltage Regulator Low-Power Operation Enable bit
1 = On-chip regulator enters low-power operation when device enters Sleep mode
0 = On-chip regulator continues to operate normally in Sleep mode
bit 6-1
Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1:
2:
The REGSLP bit is automatically cleared when a Low-Voltage Detect condition occurs.
This bit has no effect if the Configuration bit, WDTEN, is enabled.
TABLE 23-3:
Name
RCON
WDTCON
x = Bit is unknown
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 0
Reset Values
on page
POR
BOR
58
—
SWDTEN
58
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IPEN
—
CM
RI
TO
PD
REGSLP
—
—
—
—
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
2010 Microchip Technology Inc.
DS39774D-page 287
PIC18F85J11 FAMILY
23.3
On-Chip Voltage Regulator
All of the PIC18F85J11 family devices power their core
digital logic at a nominal 2.5V. For designs that are
required to operate at a higher typical voltage, such as
3.3V, all devices in the PIC18F85J11 family incorporate
an on-chip regulator that allows the device to run its
core logic from VDD.
The regulator is controlled by the ENVREG pin. Tying
VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When
the regulator is enabled, a low-ESR filter capacitor must
be connected to the VDDCORE/VCAP pin (Figure 23-2).
This helps to maintain the stability of the regulator. The
recommended value for the filter capacitor is provided in
Section 26.3 “DC Characteristics: PIC18F85J11
Family (Industrial)”.
If ENVREG is tied to VSS, the regulator is disabled. In
this case, separate power for the core logic at a nominal
2.5V must be supplied to the device on the
VDDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the VDDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 23-2 for possible
configurations.
23.3.1
VOLTAGE REGULATION AND
LOW-VOLTAGE DETECTION
When it is enabled, the on-chip regulator provides a
constant voltage of 2.5V nominal to the digital core
logic. The regulator can provide this level from a VDD of
about 2.5V, all the way up to the device’s VDDMAX. It
does not have the capability to boost VDD levels below
2.5V.
In order to prevent “brown-out” conditions, the regulator
enters Tracking mode when the voltage drops too low
for the regulator. In Tracking mode, the regulator output
follows VDD, with a typical voltage drop of 100 mV.
The on-chip regulator includes a simple Low-Voltage
Detect (LVD) circuit. If VDD drops too low to maintain
approximately 2.45V on VDDCORE, the circuit sets the
Low-Voltage Detect Interrupt Flag, LVDIF (PIR2),
and clears the REGSLP (WDTCON) bit if it was set.
FIGURE 23-2:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
Regulator Enabled (ENVREG tied to VDD):
3.3V
PIC18F85J11
VDD
ENVREG
VDDCORE/VCAP
CF
VSS
Regulator Disabled (ENVREG tied to ground):
2.5V(1)
3.3V(1)
PIC18F85J11
VDD
ENVREG
VDDCORE/VCAP
VSS
Regulator Disabled (VDD tied to VDDCORE):
2.5V(1)
PIC18F85J11
VDD
ENVREG
VDDCORE/VCAP
VSS
Note 1: These are typical operating voltages. Refer
to Section 26.1 “DC Characteristics:
Supply Voltage” for the full operating
ranges of VDD and VDDCORE.
This can be used to generate an interrupt and put the
application into a low-power operational mode or to
trigger an orderly shutdown. Low-Voltage Detection is
only available when the regulator is enabled.
DS39774D-page 288
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PIC18F85J11 FAMILY
23.3.2
ON-CHIP REGULATOR AND BOR
When the on-chip regulator is enabled, PIC18F85J11
family devices also have a simple Brown-out Reset
capability. If the voltage supplied to the regulator falls to
a level that is inadequate to maintain a regulated output
for full-speed operation, the regulator Reset circuitry
will generate a Brown-out Reset. This event is captured
by the BOR flag bit (RCON).
The operation of the Brown-out Reset is described in
more detail in Section 5.4 “Brown-out Reset (BOR)”
and Section 5.4.1 “Detecting BOR”.
23.3.3
POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE must
never exceed VDD by 0.3 volts.
2010 Microchip Technology Inc.
23.3.4
OPERATION IN SLEEP MODE
When enabled, the on-chip regulator always consumes
a small incremental amount of current over IDD. This
includes when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator can be configured
to automatically disable itself whenever the device
goes into Sleep mode. This feature is controlled by the
REGSLP bit (WDTCON). Setting this bit disables
the regulator in Sleep mode and reduces its current
consumption to a minimum.
Substantial Sleep-mode power savings can be
obtained by setting the REGSLP bit, but this will
increase device wake-up time to ensure the regulator
has enough time to stabilize.
The REGSLP bit is cleared automatically by hardware
when a Low-Voltage Detect condition occurs. The
REGSLP bit can be set again in software, which would
keep the voltage regulator in Low-Power mode. This is
not recommended, however, if any write operations to
the Flash will be performed.
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23.4
Two-Speed Start-up
23.4.1
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execution, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including serial SLEEP instructions (refer to
Section 4.1.4 “Multiple Sleep Commands”). In
practice, this means that user code can change the
SCS bit settings or issue SLEEP instructions
before the OST times out. This would allow an application to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is HS or HSPLL
(Crystal-Based) modes. Since the EC and ECPLL
modes do not require an Oscillator Start-up Timer
delay, Two-Speed Start-up should be disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the internal oscillator block as the clock source, following the
time-out of the Power-up Timer, after a Power-on Reset
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
FIGURE 23-3:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Q1
Q2
Q3
Q4
Q2 Q3 Q4 Q1 Q2 Q3
Q1
INTRC
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
2
n-1 n
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake from Interrupt Event
Note 1:
DS39774D-page 290
PC + 2
PC + 4
PC + 6
OSTS bit Set
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
23.5
Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the
microcontroller to continue operation in the event of an
external oscillator failure by automatically switching the
device clock to the internal oscillator block. The FSCM
function is enabled by setting the FCMEN Configuration
bit.
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provides
a backup clock in the event of a clock failure. Clock
monitoring (shown in Figure 23-4) is accomplished by
creating a sample clock signal which is the INTRC output divided by 64. This allows ample time between
FSCM sample clocks for a peripheral clock edge to
occur. The peripheral device clock and the sample
clock are presented as inputs to the Clock Monitor latch
(CM). The CM is set on the falling edge of the device
clock source but cleared on the rising edge of the
sample clock.
FIGURE 23-4:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch (CM)
(edge-triggered)
Peripheral
Clock
INTRC
Source
(32 s)
÷ 64
S
Q
C
Q
488 Hz
(2.048 ms)
Clock
Failure
Detected
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable
for timing-sensitive applications. In these cases, it may
be desirable to select another clock configuration and
enter an alternate power-managed mode. This can be
done to attempt a partial recovery or execute a
controlled shutdown. See Section 4.1.4 “Multiple
Sleep Commands” and Section 23.4.1 “Special
Considerations for Using Two-Speed Start-up” for
more details.
The FSCM will detect failures of the primary or secondary
clock sources only. If the internal oscillator block fails, no
failure would be detected, nor would any action be
possible.
23.5.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
As already noted, the clock source is switched to the
INTRC clock when a clock failure is detected. This may
mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value,
a decrease in clock speed allows a WDT time-out to
occur and a subsequent device Reset. For this reason,
Fail-Safe Clock Monitor events also reset the WDT and
postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood
of an erroneous time-out.
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTRC source.
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected
(Figure 23-5). This causes the following:
• the FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2);
• the device clock source is switched to the internal
oscillator block (OSCCON is not updated to show
the current clock source – this is the fail-safe
condition); and
• the WDT is reset.
2010 Microchip Technology Inc.
DS39774D-page 291
PIC18F85J11 FAMILY
FIGURE 23-5:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
Device
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
Note:
23.5.2
CM Test
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
EXITING FAIL-SAFE OPERATION
The fail-safe condition is terminated by either a device
Reset or by entering a power-managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 2H (with any
required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The INTRC
oscillator provides the device clock until the primary
clock source becomes ready (similar to a Two-Speed
Start-up). The clock source is then switched to the
primary clock (indicated by the OSTS bit in the
OSCCON register becoming set). The Fail-Safe Clock
Monitor then resumes monitoring the peripheral clock.
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTOSC multiplexor. The OSCCON register will remain
in its Reset state until a power-managed mode is
entered.
23.5.3
CM Test
FSCM INTERRUPTS IN
POWER-MANAGED MODES
By entering a power-managed mode, the clock
multiplexor selects the clock source selected by the
OSCCON register. Fail-Safe Clock Monitoring of the
power-managed clock source resumes in the
power-managed mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTRC multiplexor. An automatic transition back
to the failed clock source will not occur.
DS39774D-page 292
23.5.4
POR OR WAKE-UP FROM SLEEP
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
device clock is either EC or INTRC mode, monitoring
can begin immediately following these events.
For HS or HSPLL modes, the situation is somewhat
different. Since the oscillator may require a start-up
time considerably longer than the FSCM sample clock
time, a false clock failure may be detected. To prevent
this, the internal oscillator block is automatically configured as the device clock and functions until the primary
clock is stable (the OST and PLL timers have timed
out). This is identical to Two-Speed Start-up mode.
Once the primary clock is stable, the INTRC returns to
its role as the FSCM source.
Note:
The same logic that prevents false
oscillator failure interrupts on POR, or
wake from Sleep, will also prevent the
detection of the oscillator’s failure to start
at all following these events. This can be
avoided by monitoring the OSTS bit and
using a timing routine to determine if the
oscillator is taking too long to start. Even
so, no oscillator failure interrupt will be
flagged.
As noted in Section 23.4.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alternate
power-managed mode while waiting for the primary
clock to become stable. When the new power-managed
mode is selected, the primary clock is disabled.
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
23.6
Program Verification and
Code Protection
For all devices in the PIC18F85J11 family of devices,
the on-chip program memory space is treated as a
single block. Code protection for this block is controlled
by one Configuration bit, CP0. This bit inhibits external
reads and writes to the program memory space. It has
no direct effect in normal execution mode.
23.6.1
CONFIGURATION REGISTER
PROTECTION
The Configuration registers are protected against
untoward changes or reads in two ways. The primary
protection is the write-once feature of the Configuration
bits which prevents reconfiguration once the bit has
been programmed during a power cycle. To safeguard
against unpredictable events, Configuration bit
changes resulting from individual cell level disruptions
(such as ESD events) will cause a parity error and
trigger a device Reset.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the CP0 bit is set, the source data for device
configuration is also protected as a consequence.
2010 Microchip Technology Inc.
23.7
In-Circuit Serial Programming
PIC18F85J11 family microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
23.8
In-Circuit Debugger
When the DEBUG Configuration bit is programmed to
‘0’, the in-circuit debugger functionality is enabled. This
function allows simple debugging functions when used
with MPLAB® IDE. When the microcontroller has this
feature enabled, some resources are not available for
general use. Table 23-4 shows which resources are
required by the background debugger.
TABLE 23-4:
DEBUGGER RESOURCES
I/O pins:
RB6, RB7
Stack:
2 levels
Program Memory:
512 bytes
Data Memory:
10 bytes
DS39774D-page 293
PIC18F85J11 FAMILY
NOTES:
DS39774D-page 294
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
24.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
24.1
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2010 Microchip Technology Inc.
DS39774D-page 295
PIC18F85J11 FAMILY
24.2
MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
24.3
HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple
platforms.
24.4
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
24.5
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
24.6
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS39774D-page 296
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
24.7
MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
24.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including
low-cost, full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
2010 Microchip Technology Inc.
24.9
MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
24.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
DS39774D-page 297
PIC18F85J11 FAMILY
24.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
24.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a breakpoint, the file registers can be examined and modified.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
24.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
DS39774D-page 298
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
25.0
INSTRUCTION SET SUMMARY
The PIC18F85J11 family of devices incorporate the
standard set of 75 PIC18 core instructions, as well as
an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software
stack. The extended set is discussed later in this
section.
25.1
Standard Instruction Set
The standard PIC18 instruction set adds many
enhancements to the previous PIC® MCU instruction
sets, while maintaining an easy migration from these
PIC MCU instruction sets. Most instructions are a
single program memory word (16 bits), but there are
four instructions that require two program memory
locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type,
and one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
•
•
•
•
Byte-Oriented operations
Bit-Oriented operations
Literal operations
Control operations
The PIC18 instruction set summary in Table 25-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 25-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.
The File Select Register (specified by ‘f’).
The destination of the result (specified by ‘d’).
The accessed memory (specified by ‘a’).
The File Select Register designator, ‘f’, specifies which
File Select Register is to be used by the instruction.
The destination designator, ‘d’, specifies where the
result of the operation is to be placed. If ‘d’ is zero, the
result is placed in the WREG register. If ‘d’ is one, the
result is placed in the File Select Register specified in
the instruction.
All bit-oriented instructions have three operands:
1.
2.
3.
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a File Select
Register (specified by ‘k’).
• The desired FSR register to load the literal value
into (specified by ‘f’).
• No operand required (specified by ‘—’).
The control instructions may use some of the following
operands:
• A program memory address (specified by ‘n’).
• The mode of the CALL or RETURN instructions
(specified by ‘s’).
• The mode of the table read and table write
instructions (specified by ‘m’).
• No operand required (specified by ‘—’).
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
All single-word instructions are executed in a single
instruction cycle unless a conditional test is true or the
program counter is changed as a result of the instruction. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two-word branch instructions (if true) would take 3 s.
Figure 25-1 shows the general formats that the instructions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The instruction set summary, shown in Table 25-2, lists
the standard instructions recognized by the Microchip
MPASMTM Assembler.
Section 25.1.1 “Standard Instruction Set” provides
a description of each instruction.
The File Select Register (specified by ‘f’).
The bit in the File Select Register (specified by
‘b’).
The accessed memory (specified by ‘a’).
The bit field designator, ‘b’, selects the number of the bit
affected by the operation, while the File Select Register
designator, ‘f’, represents the number of the file in
which the bit is located.
2010 Microchip Technology Inc.
DS39774D-page 299
PIC18F85J11 FAMILY
TABLE 25-1:
OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
Bit address within an 8-bit File Select Register (0 to 7).
BSR
Bank Select Register. Used to select the current RAM bank.
C, DC, Z, OV, N
ALU STATUS bits: Carry, Digit Carry, Zero, Overflow, Negative.
d
Destination select bit:
d = 0: store result in WREG
d = 1: store result in File Select Register f
dest
Destination: either the WREG register or the specified register file location.
f
8-bit register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).
fs
12-bit register file address (000h to FFFh). This is the source address.
fd
12-bit register file address (000h to FFFh). This is the destination address.
GIE
Global Interrupt Enable bit.
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label
Label name.
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No change to register (such as TBLPTR with table reads and writes)
*+
Post-Increment register (such as TBLPTR with table reads and writes)
*-
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
+*
n
The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC
Program Counter.
PCL
Program Counter Low Byte.
PCH
Program Counter High Byte.
PCLATH
Program Counter High Byte Latch.
PCLATU
Program Counter Upper Byte Latch.
PD
Power-Down bit.
PRODH
Product of Multiply High Byte.
PRODL
Product of Multiply Low Byte.
s
Fast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR
21-bit Table Pointer (points to a program memory location).
TABLAT
8-bit Table Latch.
TO
Time-out bit.
TOS
Top-of-Stack.
u
Unused or unchanged.
WDT
Watchdog Timer.
WREG
Working register (accumulator).
x
Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
zs
7-bit offset value for Indirect Addressing of register files (source).
7-bit offset value for Indirect Addressing of register files (destination).
zd
{
}
Optional argument.
[text]
Indicates an Indexed Address.
(text)
The contents of text.
[expr]
Specifies bit n of the register indicated by the pointer, expr.
Assigned to.
< >
Register bit field.
In the set of.
italics
User-defined term (font is Courier New).
DS39774D-page 300
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 25-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-Oriented File Select Register operations
15
10
9
OPCODE
Example Instruction
8 7
d
0
a
f (FILE #)
ADDWF MYREG, W, B
d = 0 for result destination to be WREG register
d = 1 for result destination to be File Select Register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit File Select Register address
Byte to Byte move operations (2-word)
15
12 11
0
OPCODE
15
f (Source FILE #)
12 11
MOVFF MYREG1, MYREG2
0
f (Destination FILE #)
1111
f = 12-bit File Select Register address
Bit-Oriented File Select Register operations
15
12 11
9 8 7
0
OPCODE b (BIT #) a
f (FILE #)
BSF MYREG, bit, B
b = 3-bit position of bit in File Select Register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit File Select Register address
Literal operations
15
8
7
0
OPCODE
k (literal)
MOVLW 7Fh
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
OPCODE
15
n (literal)
12 11
GOTO Label
0
n (literal)
1111
n = 20-bit immediate value
15
8 7
OPCODE
15
S
0
n (literal)
12 11
CALL MYFUNC
0
n (literal)
1111
S = Fast bit
15
11 10
OPCODE
15
0
n (literal)
8 7
OPCODE
2010 Microchip Technology Inc.
BRA MYFUNC
0
n (literal)
BC MYFUNC
DS39774D-page 301
PIC18F85J11 FAMILY
TABLE 25-2:
PIC18F85J11 FAMILY INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
16-bit Instruction Word
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f s, f d
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, d, a
SUBWF
SUBWFB f, d, a
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, Skip =
Compare f with WREG, Skip >
Compare f with WREG, Skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move fs (source) to
1st word
fd (destination) 2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
Borrow
Subtract WREG from f
Subtract WREG from f with
Borrow
Swap Nibbles in f
Test f, Skip if 0
Exclusive OR WREG with f
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1
1
1
1
1
1
1
1
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
1
1
0101 11da
0101 10da
ffff
ffff
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N
1, 2
1
0011 10da
1 (2 or 3) 0110 011a
1
0001 10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
4
1, 2
None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
1, 2
1, 2
1, 2
SWAPF
TSTFSZ
XORWF
f, d, a
f, a
f, d, a
Note 1:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
2:
3:
4:
DS39774D-page 302
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 25-2:
PIC18F85J11 FAMILY INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
Cycles
16-bit Instruction Word
MSb
LSb
Status
Affected
Notes
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
f, b, a
f, b, a
f, b, a
f, b, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1
1
1 (2 or 3)
1 (2 or 3)
1
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call Subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to Address
1st word
2nd word
No Operation
No Operation
Pop Top of Return Stack (TOS)
Push Top of Return Stack (TOS)
Relative Call
Software Device Reset
Return from Interrupt Enable
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
None
None
None
None
None
None
None
None
None
None
1
1
1
1
2
1
2
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
Return with Literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100
0000 0000
0000 0000
kkkk
0001
0000
1, 2
1, 2
3, 4
3, 4
1, 2
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
n
n
n
n
n
n
n
n
n
n, s
CLRWDT —
DAW
—
GOTO
n
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
s
RETLW
k
RETURN s
SLEEP
—
Note 1:
2:
3:
4:
1
1
2
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
kkkk None
001s None
0011 TO, PD
4
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
2010 Microchip Technology Inc.
DS39774D-page 303
PIC18F85J11 FAMILY
TABLE 25-2:
PIC18F85J11 FAMILY INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
Cycles
16-bit Instruction Word
MSb
LSb
Status
Affected
Notes
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Add Literal and WREG
AND Literal with WREG
Inclusive OR Literal with WREG
Move Literal (12-bit) 2nd word
to FSR(f)
1st word
Move Literal to BSR
Move Literal to WREG
Multiply Literal with WREG
Return with Literal in WREG
Subtract WREG from Literal
Exclusive OR Literal with WREG
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
None
None
None
None
C, DC, Z, OV, N
Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD*
TBLRD*+
TBLRD*TBLRD+*
TBLWT*
TBLWT*+
TBLWT*TBLWT+*
Note 1:
2:
3:
4:
Table Read
Table Read with Post-Increment
Table Read with Post-Decrement
Table Read with Pre-Increment
Table Write
Table Write with Post-Increment
Table Write with Post-Decrement
Table Write with Pre-Increment
2
2
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
DS39774D-page 304
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
25.1.1
STANDARD INSTRUCTION SET
ADDLW
ADD Literal to W
ADDWF
ADD W to f
Syntax:
ADDLW k
Syntax:
ADDWF f {,d {,a}}
Operands:
0 k 255
Operands:
Operation:
(W) + k W
Status Affected:
N, OV, C, DC, Z
0 f 255
d [0, 1]
a [0, 1]
Operation:
(W) + (f) dest
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1111
kkkk
kkkk
Description:
The contents of W are added to the
8-bit literal ‘k’ and the result is placed
in W.
Words:
1
Cycles:
1
Encoding:
0010
Description:
Q1
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to
W
Example:
ADDLW
ffff
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
15h
Before Instruction
W
= 10h
After Instruction
W =
25h
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q Cycle Activity:
Decode
01da
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
Note:
REG, 0, 0
17h
0C2h
0D9h
0C2h
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
2010 Microchip Technology Inc.
DS39774D-page 305
PIC18F85J11 FAMILY
ADDWFC
ADD W and Carry bit to f
ANDLW
AND Literal with W
Syntax:
ADDWFC f {,d {,a}}
Syntax:
ANDLW k
Operands:
0 f 255
d [0, 1]
a [0, 1]
Operands:
0 k 255
Operation:
(W) .AND. k W
Status Affected:
N, Z
Operation:
(W) + (f) + (C) dest
Status Affected:
N, OV, C, DC, Z
Encoding:
0010
Description:
00da
Encoding:
ffff
ffff
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
0000
1011
kkkk
kkkk
Description:
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to
W
Example:
ANDLW
Before Instruction
W
=
After Instruction
W
=
05Fh
A3h
03h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWFC
Before Instruction
Carry bit =
REG
=
W
=
After Instruction
Carry bit =
REG
=
W
=
DS39774D-page 306
REG, 0, 1
1
02h
4Dh
0
02h
50h
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
ANDWF
AND W with f
BC
Branch if Carry
Syntax:
ANDWF f {,d {,a}}
Syntax:
BC n
Operands:
0 f 255
d [0, 1]
a [0, 1]
Operands:
-128 n 127
Operation:
if Carry bit is ‘1’,
(PC) + 2 + 2n PC
Status Affected:
None
Operation:
(W) .AND. (f) dest
Status Affected:
N, Z
Encoding:
0001
Description:
Encoding:
01da
ffff
ffff
1110
Description:
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ANDWF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
REG, 0, 0
17h
C2h
02h
C2h
2010 Microchip Technology Inc.
nnnn
nnnn
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
0010
If the Carry bit is ’1’, then the program
will branch.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
After Instruction
If Carry
PC
If Carry
PC
BC
5
=
address (HERE)
=
=
=
=
1;
address (HERE + 12)
0;
address (HERE + 2)
DS39774D-page 307
PIC18F85J11 FAMILY
BCF
Bit Clear f
BN
Branch if Negative
Syntax:
BCF f, b {,a}
Syntax:
BN n
Operands:
0 f 255
0b7
a [0, 1]
Operands:
-128 n 127
Operation:
if Negative bit is ‘1’,
(PC) + 2 + 2n PC
Status Affected:
None
Operation:
0 f
Status Affected:
None
Encoding:
1001
Description:
Encoding:
bbba
ffff
ffff
1110
Description:
Bit ‘b’ in register ‘f’ is cleared.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
BCF
Before Instruction
FLAG_REG = C7h
After Instruction
FLAG_REG = 47h
DS39774D-page 308
FLAG_REG,
7, 0
nnnn
nnnn
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Q Cycle Activity:
Decode
0110
If the Negative bit is ‘1’, then the
program will branch.
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
After Instruction
If Negative
PC
If Negative
PC
BN
Jump
=
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
2010 Microchip Technology Inc.
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BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
BNC n
Syntax:
BNN n
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if Carry bit is ‘0’,
(PC) + 2 + 2n PC
Operation:
if Negative bit is ‘0’,
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
Description:
0011
nnnn
nnnn
If the Carry bit is ‘0’, then the program
will branch.
Encoding:
1110
Description:
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
nnnn
nnnn
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
0111
If the Negative bit is ‘0’, then the
program will branch.
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
If No Jump:
Example:
If No Jump:
HERE
Before Instruction
PC
After Instruction
If Carry
PC
If Carry
PC
BNC
Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
2010 Microchip Technology Inc.
Example:
HERE
Before Instruction
PC
After Instruction
If Negative
PC
If Negative
PC
BNN
Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
DS39774D-page 309
PIC18F85J11 FAMILY
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
BNOV n
Syntax:
BNZ n
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if Overflow bit is ‘0’,
(PC) + 2 + 2n PC
Operation:
if Zero bit is ‘0’,
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
Description:
0101
nnnn
nnnn
If the Overflow bit is ‘0’, then the
program will branch.
Encoding:
1110
Description:
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
nnnn
nnnn
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
0001
If the Zero bit is ‘0’, then the program
will branch.
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
If No Jump:
If No Jump:
Example:
HERE
Before Instruction
PC
After Instruction
If Overflow
PC
If Overflow
PC
DS39774D-page 310
BNOV Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
Example:
HERE
Before Instruction
PC
After Instruction
If Zero
PC
If Zero
PC
BNZ
Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
BRA n
Syntax:
BSF f, b {,a}
Operands:
-1024 n 1023
Operands:
Operation:
(PC) + 2 + 2n PC
Status Affected:
None
0 f 255
0b7
a [0, 1]
Operation:
1 f
Status Affected:
None
Encoding:
1101
Description:
0nnn
nnnn
nnnn
Add the 2’s complement number, ‘2n’,
to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words:
1
Cycles:
2
Encoding:
1000
Description:
Q1
Q2
Q3
Q4
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Example:
ffff
ffff
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Decode
bbba
Words:
1
Cycles:
1
Q Cycle Activity:
HERE
Before Instruction
PC
After Instruction
PC
BRA
Jump
=
address (HERE)
=
address (Jump)
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
BSF
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
2010 Microchip Technology Inc.
FLAG_REG, 7, 1
=
0Ah
=
8Ah
DS39774D-page 311
PIC18F85J11 FAMILY
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
BTFSC f, b {,a}
Syntax:
BTFSS f, b {,a}
Operands:
0 f 255
0b7
a [0, 1]
Operands:
0 f 255
0b (W)
(unsigned comparison)
Operation:
(f) –W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
None
Status Affected:
None
Encoding:
Description:
0110
010a
ffff
ffff
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
Encoding:
0110
Description:
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Note:
Q Cycle Activity:
Q1
Decode
3 cycles if skip and followed
by a 2-word instruction.
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Example:
HERE
NGREATER
GREATER
Before Instruction
PC
W
After Instruction
If REG
PC
If REG
PC
Q4
No
operation
Q4
No
operation
No
operation
CPFSGT REG, 0
:
:
=
=
Address (HERE)
?
=
=
W;
Address (GREATER)
W;
Address (NGREATER)
2010 Microchip Technology Inc.
ffff
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
Q1
Q2
Q3
No
No
No
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
No
No
operation
operation
operation
No
No
No
operation
operation
operation
ffff
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
000a
Example:
HERE
NLESS
LESS
Before Instruction
PC
W
After Instruction
If REG
PC
If REG
PC
CPFSLT REG, 1
:
:
=
=
Address (HERE)
?
<
=
=
W;
Address (LESS)
W;
Address (NLESS)
DS39774D-page 317
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DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
DAW
Syntax:
DECF f {,d {,a}}
Operands:
None
Operands:
Operation:
If [W > 9] or [DC = 1], then
(W) + 6 W;
else
(W) W
0 f 255
d [0, 1]
a [0, 1]
Operation:
(f) – 1 dest
Status Affected:
C, DC, N, OV, Z
Encoding:
If [W > 9] or [C = 1], then
(W) + 6 W;
C =1;
else
(W) W
Status Affected:
0000
Description:
0000
0000
0000
0111
Description:
DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
Example 1:
A5h
0
0
05h
1
0
ffff
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
DAW
Before Instruction
W
=
C
=
DC
=
After Instruction
W
=
C
=
DC
=
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
C
Encoding:
01da
Example:
DECF
Before Instruction
CNT
=
Z
=
After Instruction
CNT
=
Z
=
CNT,
1, 0
01h
0
00h
1
Example 2:
Before Instruction
W
=
C
=
DC
=
After Instruction
W
=
C
=
DC
=
DS39774D-page 318
CEh
0
0
34h
1
0
2010 Microchip Technology Inc.
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DECFSZ
Decrement f, Skip if 0
DCFSNZ
Decrement f, Skip if Not 0
Syntax:
DECFSZ f {,d {,a}}
Syntax:
DCFSNZ f {,d {,a}}
Operands:
0 f 255
d [0, 1]
a [0, 1]
Operands:
0 f 255
d [0, 1]
a [0, 1]
Operation:
(f) – 1 dest,
skip if result = 0
Operation:
(f) – 1 dest,
skip if result 0
Status Affected:
None
Status Affected:
None
Encoding:
0010
Description:
11da
ffff
ffff
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
Encoding:
0100
Description:
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1(2)
Note:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
DECFSZ
GOTO
CNT, 1, 1
LOOP
Example:
HERE
CONTINUE
Before Instruction
PC
=
After Instruction
CNT
=
If CNT
=
PC =
If CNT
PC =
Address (HERE)
CNT – 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
2010 Microchip Technology Inc.
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
If skip and followed by 2-word instruction:
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
ffff
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
11da
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
ZERO
NZERO
Before Instruction
TEMP
After Instruction
TEMP
If TEMP
PC
If TEMP
PC
DCFSNZ
:
:
TEMP, 1, 0
=
?
=
=
=
=
TEMP – 1
0;
Address (ZERO)
0;
Address (NZERO)
DS39774D-page 319
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GOTO
Unconditional Branch
INCF
Increment f
Syntax:
GOTO k
Syntax:
INCF f {,d {,a}}
Operands:
0 k 1048575
Operands:
Operation:
k PC
Status Affected:
None
0 f 255
d [0, 1]
a [0, 1]
Operation:
(f) + 1 dest
Status Affected:
C, DC, N, OV, Z
Encoding:
1st word (k)
2nd word(k)
1110
1111
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description:
GOTO allows an unconditional branch
anywhere within entire 2-Mbyte memory
range. The 20-bit value, ‘k’, is loaded
into PC. GOTO is always a
two-cycle instruction.
Words:
2
Cycles:
2
Encoding:
0010
Description:
Q1
Q2
Q3
Q4
Read literal
‘k’,
No
operation
Read literal
‘k’,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example:
GOTO THERE
After Instruction
PC =
Address (THERE)
ffff
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
INCF
Before Instruction
CNT
=
Z
=
C
=
DC
=
After Instruction
CNT
=
Z
=
C
=
DC
=
DS39774D-page 320
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q Cycle Activity:
Decode
10da
CNT, 1, 0
FFh
0
?
?
00h
1
1
1
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INCFSZ
Increment f, Skip if 0
INFSNZ
Syntax:
INCFSZ f {,d {,a}}
Syntax:
INFSNZ f {,d {,a}}
Operands:
0 f 255
d [0, 1]
a [0, 1]
Operands:
0 f 255
d [0, 1]
a [0, 1]
Operation:
(f) + 1 dest,
skip if result = 0
Operation:
(f) + 1 dest,
skip if result 0
Status Affected:
None
Status Affected:
None
Encoding:
0011
Description:
11da
ffff
ffff
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
Increment f, Skip if Not 0
Encoding:
0100
Description:
10da
ffff
ffff
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Words:
1
Cycles:
1(2)
Note:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
Before Instruction
PC
=
After Instruction
CNT
=
If CNT
=
PC
=
If CNT
PC
=
INCFSZ
:
:
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
2010 Microchip Technology Inc.
CNT, 1, 0
Example:
HERE
ZERO
NZERO
Before Instruction
PC
=
After Instruction
REG
=
If REG
PC
=
If REG
=
PC
=
INFSNZ
REG, 1, 0
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
DS39774D-page 321
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IORLW
Inclusive OR Literal with W
IORWF
Inclusive OR W with f
Syntax:
IORLW k
Syntax:
IORWF f {,d {,a}}
Operands:
0 k 255
Operands:
Operation:
(W) .OR. k W
Status Affected:
N, Z
0 f 255
d [0, 1]
a [0, 1]
Operation:
(W) .OR. (f) dest
Status Affected:
N, Z
Encoding:
0000
1001
kkkk
kkkk
Description:
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed
in W.
Words:
1
Cycles:
1
Encoding:
0001
Description:
Q1
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to
W
Example:
IORLW
Before Instruction
W
=
After Instruction
W
=
ffff
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
35h
9Ah
BFh
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q Cycle Activity:
Decode
00da
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
IORWF
Before Instruction
RESULT =
W
=
After Instruction
RESULT =
W
=
DS39774D-page 322
RESULT, 0, 1
13h
91h
13h
93h
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LFSR
Load FSR
MOVF
Move f
Syntax:
LFSR f, k
Syntax:
MOVF f {,d {,a}}
Operands:
0f2
0 k 4095
Operands:
Operation:
k FSRf
0 f 255
d [0, 1]
a [0, 1]
Status Affected:
None
Operation:
f dest
Status Affected:
N, Z
Encoding:
1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Description:
The 12-bit literal ‘k’ is loaded into the
File Select Register pointed to by ‘f’.
Words:
2
Cycles:
2
Encoding:
0101
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example:
After Instruction
FSR2H
FSR2L
03h
ABh
ffff
ffff
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’. Location ‘f’
can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
LFSR 2, 3ABh
=
=
00da
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
W
Example:
MOVF
Before Instruction
REG
W
After Instruction
REG
W
2010 Microchip Technology Inc.
REG, 0, 0
=
=
22h
FFh
=
=
22h
22h
DS39774D-page 323
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MOVFF
Move f to f
MOVLB
Move Literal to Low Nibble in BSR
Syntax:
MOVFF fs,fd
Syntax:
MOVLW k
Operands:
0 fs 4095
0 fd 4095
Operands:
0 k 255
Operation:
k BSR
Status Affected:
None
Operation:
(fs) fd
Status Affected:
None
Encoding:
1st word (source)
2nd word (destin.)
Encoding:
1100
1111
Description:
ffff
ffff
ffff
ffff
ffffs
ffffd
The contents of source register, ‘fs’, are
moved to destination register, ‘fd’.
Location of source, ‘fs’, can be
anywhere in the 4096-byte data space
(000h to FFFh) and location of
destination, ‘fd’, can also be anywhere
from 000h to FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF is particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register
Words:
2
Cycles:
2
0000
0001
kkkk
kkkk
Description:
The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR always remains ‘0’
regardless of the value of k7:k4.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write literal
‘k’ to BSR
MOVLB
5
Example:
Before Instruction
BSR Register =
After Instruction
BSR Register =
02h
05h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
Before Instruction
REG1
REG2
After Instruction
REG1
REG2
DS39774D-page 324
REG1, REG2
=
=
33h
11h
=
=
33h
33h
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MOVLW
Move Literal to W
MOVWF
Move W to f
Syntax:
MOVLW k
Syntax:
MOVWF f {,a}
Operands:
0 k 255
Operands:
Operation:
kW
0 f 255
a [0, 1]
Status Affected:
None
Encoding:
0000
Description:
1110
kkkk
kkkk
The eight-bit literal ‘k’ is loaded into W.
Words:
1
Cycles:
1
Operation:
(W) f
Status Affected:
None
Encoding:
0110
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
Example:
After Instruction
W
=
MOVLW
111a
ffff
ffff
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
5Ah
5Ah
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
MOVWF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
2010 Microchip Technology Inc.
REG, 0
4Fh
FFh
4Fh
4Fh
DS39774D-page 325
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MULLW
Multiply Literal with W
MULWF
Syntax:
MULLW k
Syntax:
MULWF f {,a}
Operands:
0 k 255
Operands:
Operation:
(W) x k PRODH:PRODL
0 f 255
a [0, 1]
Status Affected:
None
Operation:
(W) x (f) PRODH:PRODL
Status Affected:
None
Encoding:
0000
Description:
1101
kkkk
kkkk
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in the PRODH:PRODL register
pair. PRODH contains the high byte.
Multiply W with f
Encoding:
0000
Description:
W is unchanged.
None of the Status flags are affected.
1
Cycles:
1
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
Before Instruction
W
PRODH
PRODL
After Instruction
W
PRODH
PRODL
MULLW
0C4h
=
=
=
E2h
?
?
=
=
=
E2h
ADh
08h
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
registers
PRODH:
PRODL
Example:
Before Instruction
W
REG
PRODH
PRODL
After Instruction
W
REG
PRODH
PRODL
DS39774D-page 326
ffff
Note that neither Overflow nor Carry is
possible in this operation. A Zero result is
possible but not detected.
Q Cycle Activity:
Example:
ffff
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected.
Words:
001a
An unsigned multiplication is carried out
between the contents of W and the
register file location, ‘f’. The 16-bit result is
stored in the PRODH:PRODL register
pair. PRODH contains the high byte. Both
W and ‘f’ are unchanged.
MULWF
REG, 1
=
=
=
=
C4h
B5h
?
?
=
=
=
=
C4h
B5h
8Ah
94h
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NEGF
Negate f
NOP
No Operation
Syntax:
NEGF f {,a}
Syntax:
NOP
Operands:
0 f 255
a [0, 1]
Operands:
None
Operation:
No operation
Status Affected:
None
Operation:
(f) + 1 f
Status Affected:
N, OV, C, DC, Z
Encoding:
0110
Description:
Encoding:
110a
ffff
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
0000
1111
ffff
0000
xxxx
Description:
No operation.
Words:
1
Cycles:
1
0000
xxxx
0000
xxxx
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
NEGF
Before Instruction
REG
=
After Instruction
REG
=
REG, 1
0011 1010 [3Ah]
1100 0110 [C6h]
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POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
POP
Syntax:
PUSH
Operands:
None
Operands:
None
Operation:
(TOS) bit bucket
Operation:
(PC + 2) TOS
Status Affected:
None
Status Affected:
None
Encoding:
0000
0000
0000
0110
Encoding:
0000
0000
0000
0101
Description:
The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
Description:
The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
POP TOS
value
No
operation
POP
GOTO
NEW
Example:
Q2
Q3
Q4
PUSH
PC + 2 onto
return stack
No
operation
No
operation
Example:
Before Instruction
TOS
Stack (1 level down)
=
=
0031A2h
014332h
After Instruction
TOS
PC
=
=
014332h
NEW
DS39774D-page 328
Q1
Decode
PUSH
Before Instruction
TOS
PC
=
=
345Ah
0124h
After Instruction
PC
TOS
Stack (1 level down)
=
=
=
0126h
0126h
345Ah
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RCALL
Relative Call
RESET
Reset
Syntax:
RCALL n
Syntax:
RESET
Operands:
-1024 n 1023
Operands:
None
Operation:
(PC) + 2 TOS,
(PC) + 2 + 2n PC
Operation:
Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected:
None
Status Affected:
All
Encoding:
1101
Description:
1nnn
nnnn
nnnn
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number, ‘2n’, to the PC. Since the PC
will have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words:
1
Cycles:
2
Encoding:
0000
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
1111
1111
This instruction provides a way to
execute a MCLR Reset in software.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
Reset
No
operation
No
operation
Example:
Q Cycle Activity:
0000
Description:
After Instruction
Registers =
Flags*
=
RESET
Reset Value
Reset Value
PUSH PC
to stack
No
operation
Example:
No
operation
HERE
RCALL Jump
Before Instruction
PC =
Address (HERE)
After Instruction
PC =
Address (Jump)
TOS =
Address (HERE + 2)
2010 Microchip Technology Inc.
DS39774D-page 329
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RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
RETFIE {s}
Syntax:
RETLW k
Operands:
s [0, 1]
Operands:
0 k 255
Operation:
(TOS) PC,
1 GIE/GIEH or PEIE/GIEL;
if s = 1,
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Operation:
k W,
(TOS) PC,
PCLATU, PCLATH are unchanged
Status Affected:
None
Status Affected:
0000
0000
Description:
0000
0001
Words:
1
Cycles:
2
Q Cycle Activity:
kkkk
kkkk
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Words:
1
Cycles:
2
000s
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low-priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers, WS,
STATUSS and BSRS, are loaded into
their corresponding registers, W,
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs.
1100
Description:
GIE/GIEH, PEIE/GIEL.
Encoding:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
POP PC
from stack,
write to W
No
operation
No
operation
No
operation
No
operation
Example:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
POP PC
from stack
Set GIEH or
GIEL
No
operation
Encoding:
No
operation
Example:
RETFIE
After Interrupt
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL
DS39774D-page 330
No
operation
No
operation
1
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
CALL TABLE ;
;
;
;
:
TABLE
ADDWF PCL ;
RETLW k0
;
RETLW k1
;
:
:
RETLW kn
;
Before Instruction
W
=
After Instruction
W
=
W contains table
offset value
W now has
table value
W = offset
Begin table
End of table
07h
value of kn
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RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
RETURN {s}
Syntax:
RLCF f {,d {,a}}
Operands:
s [0, 1]
Operands:
Operation:
(TOS) PC;
if s = 1,
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
0 f 255
d [0, 1]
a [0, 1]
Operation:
(f) dest,
(f) C,
(C) dest
Status Affected:
C, N, Z
Status Affected:
None
Encoding:
0000
Description:
Encoding:
0000
0001
001s
0011
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers, WS, STATUSS and BSRS,
are loaded into their corresponding
registers, W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs.
Words:
1
Cycles:
2
Q1
Q2
Q3
Q4
No
operation
Process
Data
POP PC
from stack
No
operation
No
operation
No
operation
No
operation
ffff
ffff
The contents of register ‘f’ are rotated
one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register
‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Decode
01da
register f
C
Words:
1
Cycles:
1
Q Cycle Activity:
Example:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
RETURN
After Instruction:
PC = TOS
Example:
Before Instruction
REG
=
C
=
After Instruction
REG
=
W
=
C
=
2010 Microchip Technology Inc.
RLCF
REG, 0, 0
1110 0110
0
1110 0110
1100 1100
1
DS39774D-page 331
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RLNCF
Rotate Left f (No Carry)
RRCF
Rotate Right f through Carry
Syntax:
RLNCF f {,d {,a}}
Syntax:
RRCF f {,d {,a}}
Operands:
0 f 255
d [0, 1]
a [0, 1]
Operands:
0 f 255
d [0, 1]
a [0, 1]
Operation:
(f) dest,
(f) dest
Operation:
Status Affected:
N, Z
(f) dest,
(f) C,
(C) dest
Status Affected:
C, N, Z
Encoding:
0100
Description:
01da
ffff
ffff
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Encoding:
0011
Description:
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
1
1
Q1
Decode
Q2
Read
register ‘f’
Example:
Before Instruction
REG
=
After Instruction
REG
=
DS39774D-page 332
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’.
register f
C
Q Cycle Activity:
RLNCF
Q3
Process
Data
Q4
Write to
destination
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
REG, 1, 0
1010 1011
0101 0111
ffff
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
register f
Cycles:
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
00da
Example:
RRCF
Before Instruction
REG
=
C
=
After Instruction
REG
=
W
=
C
=
REG, 0, 0
1110 0110
0
1110 0110
0111 0011
0
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RRNCF
Rotate Right f (No Carry)
SETF
Set f
Syntax:
RRNCF f {,d {,a}}
Syntax:
SETF f {,a}
Operands:
0 f 255
d [0, 1]
a [0, 1]
Operands:
0 f 255
a [0, 1]
Operation:
(f) dest,
(f) dest
Status Affected:
N, Z
Encoding:
0100
Description:
00da
Operation:
FFh f
Status Affected:
None
Encoding:
ffff
ffff
0110
Description:
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
register f
Words:
1
Cycles:
1
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
Before Instruction
REG
=
After Instruction
REG
=
Example 2:
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
SETF
Before Instruction
REG
After Instruction
REG
REG,1
=
5Ah
=
FFh
REG, 1, 0
1101 0111
1110 1011
RRNCF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
ffff
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
Q Cycle Activity:
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If ‘a’
is ‘1’, then the bank will be selected as
per the BSR value.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
100a
The contents of the specified register
are set to FFh.
REG, 0, 0
?
1101 0111
1110 1011
1101 0111
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SLEEP
Enter Sleep Mode
SUBFWB
Subtract f from W with Borrow
Syntax:
SLEEP
Syntax:
SUBFWB f {,d {,a}}
Operands:
None
Operands:
Operation:
00h WDT,
0 WDT postscaler,
1 TO,
0 PD
0 f 255
d [0, 1]
a [0, 1]
Operation:
(W) – (f) – (C) dest
Status Affected:
N, OV, C, DC, Z
Status Affected:
TO, PD
Encoding:
0000
Description:
Encoding:
0000
0000
0011
0101
Description:
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. The Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
Words:
1
Cycles:
1
Q1
Q2
Q3
Q4
No
operation
Process
Data
Go to
Sleep
Example:
SLEEP
Before Instruction
TO =
?
?
PD =
After Instruction
1†
TO =
PD =
0
† If WDT causes wake-up, this bit is cleared.
DS39774D-page 334
ffff
ffff
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored in
W. If ‘d’ is ‘1’, the result is stored in
register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Decode
01da
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
SUBFWB
REG, 1, 0
Example 1:
Before Instruction
REG
=
3
W
=
2
C
=
1
After Instruction
REG
=
FF
W
=
2
C
=
0
Z
=
0
N
=
1
; result is negative
SUBFWB
REG, 0, 0
Example 2:
Before Instruction
REG
=
2
W
=
5
C
=
1
After Instruction
REG
=
2
W
=
3
C
=
1
Z
=
0
N
=
0
; result is positive
SUBFWB
REG, 1, 0
Example 3:
Before Instruction
REG
=
1
W
=
2
C
=
0
After Instruction
REG
=
0
W
=
2
C
=
1
Z
=
1
; result is zero
N
=
0
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
SUBLW
Subtract W from Literal
SUBWF
Subtract W from f
Syntax:
SUBLW k
Syntax:
SUBWF f {,d {,a}}
Operands:
0 k 255
Operands:
Operation:
k – (W) W
Status Affected:
N, OV, C, DC, Z
0 f 255
d [0, 1]
a [0, 1]
Operation:
(f) – (W) dest
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1000
kkkk
kkkk
Description:
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
Words:
1
Cycles:
1
Encoding:
0101
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
Example 1:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
Example 2:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
SUBLW
SUBLW
; result is positive
02h
?
00h
1
1
0
SUBLW
; result is zero
02h
03h
?
FFh
0
0
1
; (2’s complement)
; result is negative
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
SUBWF
REG, 1, 0
Example 1:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
2010 Microchip Technology Inc.
ffff
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
02h
02h
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
01h
?
01h
1
0
0
11da
3
2
?
1
2
1
0
0
; result is positive
SUBWF
REG, 0, 0
2
2
?
2
0
1
1
0
SUBWF
; result is zero
REG, 1, 0
1
2
?
FFh ; (2’s complement)
2
0
; result is negative
0
1
DS39774D-page 335
PIC18F85J11 FAMILY
SUBWFB
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
SUBWFB f {,d {,a}}
Syntax:
SWAPF f {,d {,a}}
Operands:
0 f 255
d [0, 1]
a [0, 1]
Operands:
0 f 255
d [0, 1]
a [0, 1]
Operation:
(f) – (W) – (C) dest
Operation:
Status Affected:
N, OV, C, DC, Z
(f) dest,
(f) dest
Status Affected:
None
Encoding:
0101
Description:
10da
ffff
ffff
Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
Encoding:
0011
Description:
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Read
register ‘f’
Example 1:
SUBWFB
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
Q4
Write to
destination
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
REG, 1, 0
19h
0Dh
1
(0001 1001)
(0000 1101)
0Ch
0Dh
1
0
0
(0000 1011)
(0000 1101)
ffff
Example:
SWAPF
Before Instruction
REG
=
After Instruction
REG
=
REG, 1, 0
53h
35h
; result is positive
SUBWFB REG, 0, 0
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
1Bh
1Ah
0
(0001 1011)
(0001 1010)
1Bh
00h
1
1
0
(0001 1011)
SUBWFB
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
C
Z
N
Q3
Process
Data
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
10da
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
=
=
=
=
DS39774D-page 336
; result is zero
REG, 1, 0
03h
0Eh
1
(0000 0011)
(0000 1101)
F5h
(1111 0100)
; [2’s comp]
(0000 1101)
0Eh
0
0
1
; result is negative
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TBLRD
Table Read
TBLRD
Table Read (Continued)
Syntax:
TBLRD ( *; *+; *-; +*)
Example 1:
TBLRD
Operands:
None
Operation:
if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR – No Change
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) + 1 TBLPTR
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) – 1 TBLPTR
if TBLRD +*,
(TBLPTR) + 1 TBLPTR;
(Prog Mem (TBLPTR)) TABLAT
Status Affected: None
Encoding:
Description:
0000
0000
0000
Before Instruction
TABLAT
TBLPTR
MEMORY(00A356h)
After Instruction
TABLAT
TBLPTR
Example 2:
TBLRD
Before Instruction
TABLAT
TBLPTR
MEMORY(01A357h)
MEMORY(01A358h)
After Instruction
TABLAT
TBLPTR
*+ ;
=
=
=
55h
00A356h
34h
=
=
34h
00A357h
+* ;
=
=
=
=
AAh
01A357h
12h
34h
=
=
34h
01A358h
10nn
nn=0 *
=1 *+
=2 *=3 +*
This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR = 0: Least Significant Byte of
program memory word
TBLPTR = 1: Most Significant Byte of
program memory word
The TBLRD instruction can modify the value
of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
operation
No operation
(Read Program
Memory)
No
operation
No operation
(Write
TABLAT)
2010 Microchip Technology Inc.
DS39774D-page 337
PIC18F85J11 FAMILY
TBLWT
Table Write
TBLWT
Table Write (Continued)
Syntax:
TBLWT ( *; *+; *-; +*)
Example 1:
TBLWT *+;
Operands:
None
Operation:
if TBLWT*,
(TABLAT) Holding Register;
TBLPTR – No Change
if TBLWT*+,
(TABLAT) Holding Register;
(TBLPTR) + 1 TBLPTR
if TBLWT*-,
(TABLAT) Holding Register;
(TBLPTR) – 1 TBLPTR
if TBLWT+*,
(TBLPTR) + 1 TBLPTR;
(TABLAT) Holding Register
Status Affected:
Example 2:
None
Encoding:
Description:
Before Instruction
TABLAT
=
55h
TBLPTR
=
00A356h
HOLDING REGISTER
(00A356h)
=
FFh
After Instructions (table write completion)
TABLAT
=
55h
TBLPTR
=
00A357h
HOLDING REGISTER
(00A356h)
=
55h
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *=3 +*
This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program Memory
(P.M.). (Refer to Section 6.0 “Memory
Organization” for additional details on
programming Flash memory.)
TBLWT +*;
Before Instruction
TABLAT
=
34h
TBLPTR
=
01389Ah
HOLDING REGISTER
(01389Ah)
=
FFh
HOLDING REGISTER
(01389Bh)
=
FFh
After Instruction (table write completion)
TABLAT
=
34h
TBLPTR
=
01389Bh
HOLDING REGISTER
(01389Ah)
=
FFh
HOLDING REGISTER
(01389Bh)
=
34h
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-Mbyte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
TBLPTR = 0: Least Significant Byte
of program memory
word
TBLPTR = 1: Most Significant Byte
of program memory
word
The TBLWT instruction can modify the
value of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
No
No
No
operation operation operation
No
No
No
No
operation operation operation operation
(Read
(Write to
TABLAT)
Holding
Register)
DS39774D-page 338
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TSTFSZ
Test f, Skip if 0
XORLW
Exclusive OR Literal with W
Syntax:
TSTFSZ f {,a}
Syntax:
XORLW k
Operands:
0 f 255
a [0, 1]
Operands:
0 k 255
Operation:
(W) .XOR. k W
Status Affected:
N, Z
Operation:
skip if f = 0
Status Affected:
None
Encoding:
Encoding:
0110
Description:
011a
ffff
ffff
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
0000
1010
kkkk
kkkk
Description:
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
Example:
Before Instruction
W
=
After Instruction
W
=
XORLW
0AFh
B5h
1Ah
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
Before Instruction
PC
After Instruction
If CNT
PC
If CNT
PC
TSTFSZ
:
:
CNT, 1
=
Address (HERE)
=
=
=
00h,
Address (ZERO)
00h,
Address (NZERO)
2010 Microchip Technology Inc.
DS39774D-page 339
PIC18F85J11 FAMILY
XORWF
Exclusive OR W with f
Syntax:
XORWF f {,d {,a}}
Operands:
0 f 255
d [0, 1]
a [0, 1]
Operation:
(W) .XOR. (f) dest
Status Affected:
N, Z
Encoding:
0001
Description:
10da
ffff
ffff
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
Before Instruction
REG
=
W
=
After Instruction
REG
=
W
=
DS39774D-page 340
REG, 1, 0
AFh
B5h
1Ah
B5h
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
25.2
Extended Instruction Set
In addition to the standard 75 instructions of the PIC18
instruction set, the PIC18F85J11 family of devices also
provides an optional extension to the core CPU functionality. The added features include eight additional
instructions that augment Indirect and Indexed
Addressing operations and the implementation of
Indexed Literal Offset Addressing for many of the
standard PIC18 instructions.
A summary of the instructions in the extended instruction set is provided in Table 25-3. Detailed descriptions
are provided in Section 25.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 25-1
(page 300) apply to both the standard and extended
PIC18 instruction sets.
Note:
The additional features of the extended instruction set
are enabled by default on unprogrammed devices.
Users must properly set or clear the XINST Configuration bit during programming to enable or disable these
features.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers, or use them for Indexed
Addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
• Dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• Function Pointer invocation
• Software Stack Pointer manipulation
• Manipulation of variables located in a software
stack
TABLE 25-3:
25.2.1
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C. The user may likely never use
these instructions directly in the assembler. The syntax for these commands is
provided as a reference for users who may
be reviewing code that has been
generated by a compiler.
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed arguments, using one of the File Select Registers and some
offset to specify a source or destination register. When
an argument for an instruction serves as part of
Indexed Addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. The MPASM™ Assembler will
flag an error if it determines that an index or offset value
is not bracketed.
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in
byte-oriented and bit-oriented instructions. This is in
addition to other changes in their syntax. For more
details, see Section 25.2.3.1 “Extended Instruction
Syntax with Standard PIC18 Commands”.
Note:
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text, and going forward, optional arguments
are denoted by braces (“{ }”).
EXTENSIONS TO THE PIC18 INSTRUCTION SET
Mnemonic,
Operands
ADDFSR
ADDULNK
CALLW
MOVSF
f, k
k
MOVSS
zs, zd
PUSHL
SUBFSR
SUBULNK
k
f, k
k
zs, fd
Description
Cycles
Add Literal to FSR
Add Literal to FSR2 and Return
Call Subroutine using WREG
Move zs (source) to 1st word
fd (destination) 2nd word
Move zs (source) to 1st word
zd (destination) 2nd word
Store Literal at FSR2, Decrement FSR2
Subtract Literal from FSR
Subtract Literal from FSR2 and Return
1
2
2
2
2010 Microchip Technology Inc.
2
1
1
2
16-Bit Instruction Word
MSb
1110
1110
0000
1110
1111
1110
1111
1110
1110
1110
LSb
1000
1000
0000
1011
ffff
1011
xxxx
1010
1001
1001
ffkk
11kk
0001
0zzz
ffff
1zzz
xzzz
kkkk
ffkk
11kk
kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk
kkkk
kkkk
Status
Affected
None
None
None
None
None
None
None
None
DS39774D-page 341
PIC18F85J11 FAMILY
25.2.2
EXTENDED INSTRUCTION SET
ADDFSR
Add Literal to FSR
ADDULNK
Syntax:
ADDFSR f, k
Syntax:
ADDULNK k
Operands:
0 k 63
f [ 0, 1, 2 ]
Operands:
0 k 63
Operation:
Operation:
FSR(f) + k FSR(f)
FSR2 + k FSR2,
(TOS) PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
1000
ffkk
kkkk
Description:
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Words:
1
Cycles:
1
Add Literal to FSR2 and Return
Encoding:
1110
Description:
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
Example:
After Instruction
FSR2
=
03FFh
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
No
Operation
No
Operation
No
Operation
No
Operation
0422h
Example:
Note:
kkkk
This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
ADDFSR 2, 23h
Before Instruction
FSR2
=
11kk
The instruction takes two cycles to
execute; a NOP is performed during
the second cycle.
Q Cycle Activity:
Q1
1000
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURN is then
executed by loading the PC with the
TOS.
ADDULNK 23h
Before Instruction
FSR2
=
PC
=
03FFh
0100h
After Instruction
FSR2
=
PC
=
0422h
(TOS)
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
DS39774D-page 342
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
CALLW
Subroutine Call Using WREG
MOVSF
Move Indexed to f
Syntax:
CALLW
Syntax:
MOVSF [zs], fd
Operands:
None
Operands:
Operation:
(PC + 2) TOS,
(W) PCL,
(PCLATH) PCH,
(PCLATU) PCU
0 zs 127
0 fd 4095
Operation:
((FSR2) + zs) fd
Status Affected:
None
Status Affected:
None
Encoding:
0000
Description
0000
0001
0100
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOP instruction while the
new next instruction is fetched.
Encoding:
1st word (source)
2nd word (destin.)
Description:
Unlike CALL, there is no option to
update W, STATUS or BSR.
Words:
1
Cycles:
2
Q1
Q2
Q3
Q4
Read
WREG
Push PC to
stack
No
operation
No
operation
No
operation
No
operation
No
operation
Before Instruction
PC
=
PCLATH =
PCLATU =
W
=
After Instruction
PC
=
TOS
=
PCLATH =
PCLATU =
W
=
Words:
2
Cycles:
2
Q Cycle Activity:
CALLW
Decode
address (HERE)
10h
00h
06h
001006h
address (HERE + 2)
10h
00h
06h
2010 Microchip Technology Inc.
zzzzs
ffffd
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h.
Decode
HERE
0zzz
ffff
The contents of the source register are
moved to destination register, ‘fd’. The
actual address of the source register is
determined by adding the 7-bit literal
offset, ‘zs’, in the first word to the value
of FSR2. The address of the destination
register is specified by the 12-bit literal,
‘fd’, in the second word. Both addresses
can be anywhere in the 4096-byte data
space (000h to FFFh).
Q1
Example:
1011
ffff
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Q Cycle Activity:
Decode
1110
1111
Q2
Q3
Determine
Determine
source addr source addr
No
operation
No
operation
No dummy
read
Example:
MOVSF
Before Instruction
FSR2
Contents
of 85h
REG2
After Instruction
FSR2
Contents
of 85h
REG2
Q4
Read
source reg
Write
register ‘f’
(dest)
[05h], REG2
=
80h
=
=
33h
11h
=
80h
=
=
33h
33h
DS39774D-page 343
PIC18F85J11 FAMILY
MOVSS
Move Indexed to Indexed
PUSHL
Store Literal at FSR2, Decrement FSR2
Syntax:
MOVSS [zs], [zd]
Syntax:
PUSHL k
Operands:
0 zs 127
0 zd 127
Operands:
0k 255
Operation:
k (FSR2),
FSR2 – 1 FSR2
Status Affected:
None
Operation:
((FSR2) + zs) ((FSR2) + zd)
Status Affected:
None
Encoding:
1st word (source)
2nd word (dest.)
1110
1111
Description
1011
xxxx
1zzz
xzzz
zzzzs
zzzzd
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets, ‘zs’ or ‘zd’,
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
The MOVSS instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h. If the
resultant destination address points to
an Indirect Addressing register, the
instruction will execute as a NOP.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Decode
Decode
Q2
Q3
Determine
Determine
source addr source addr
Determine
dest addr
Example:
1111
Description:
1010
kkkk
kkkk
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2.
FSR2 is decremented by 1 after the
operation.
This instruction allows users to push
values onto a software stack.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
data
Write to
destination
Example:
PUSHL 08h
Before Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01ECh
00h
After Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01EBh
08h
Q4
Read
source reg
Write
to dest reg
MOVSS [05h], [06h]
Before Instruction
FSR2
Contents
of 85h
Contents
of 86h
After Instruction
FSR2
Contents
of 85h
Contents
of 86h
DS39774D-page 344
Determine
dest addr
Encoding:
=
80h
=
33h
=
11h
=
80h
=
33h
=
33h
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
SUBFSR
Subtract Literal from FSR
SUBULNK
Syntax:
SUBFSR f, k
Syntax:
SUBULNK k
Operands:
0 k 63
Operands:
0 k 63
f [ 0, 1, 2 ]
Operation:
Operation:
FSRf – k FSRf
FSR2 – k FSR2,
(TOS) PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
1001
ffkk
kkkk
Description:
The 6-bit literal, ‘k’, is subtracted
from the contents of the FSR
specified by ‘f’.
Words:
1
Cycles:
1
Encoding:
1110
Description:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example:
Before Instruction
FSR2
=
After Instruction
FSR2
=
SUBFSR 2, 23h
1001
11kk
kkkk
The 6-bit literal, ‘k’, is subtracted from
the contents of the FSR2. A RETURN is
then executed by loading the PC with
the TOS.
The instruction takes two cycles to
execute; a NOP is performed during the
second cycle.
Q Cycle Activity:
Decode
Subtract Literal from FSR2 and Return
This may be thought of as a special case
of the SUBFSR instruction, where f = 3
(binary ‘11’); it operates only on FSR2.
Words:
1
Cycles:
2
Q Cycle Activity:
03FFh
03DCh
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
No
Operation
No
Operation
No
Operation
No
Operation
Example:
2010 Microchip Technology Inc.
SUBULNK 23h
Before Instruction
FSR2
=
PC
=
03FFh
0100h
After Instruction
FSR2
=
PC
=
03DCh
(TOS)
DS39774D-page 345
PIC18F85J11 FAMILY
25.2.3
Note:
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
Enabling the PIC18 instruction set extension may cause legacy applications to
behave erratically or fail entirely.
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing (Section 6.6.1
“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations:
either as a location in the Access Bank (a = 0) or in a
GPR bank designated by the BSR (a = 1). When the
extended instruction set is enabled and a = 0, however,
a File Select Register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and
not as a literal address. For practical purposes, this
means that all instructions that use the Access RAM bit
as an argument – that is, all byte-oriented and
bit-oriented instructions, or almost half of the core
PIC18 instructions – may behave differently when the
extended instruction set is enabled.
When the content of FSR2 is 00h, the boundaries of
the Access RAM are essentially remapped to their
original values. This may be useful in creating
backward-compatible code. If this technique is used,
it may be necessary to save the value of FSR2 and
restore it when moving back and forth between C and
assembly routines in order to preserve the Stack
Pointer. Users must also keep in mind the syntax
requirements of the extended instruction set (see
Section 25.2.3.1 “Extended Instruction Syntax
with Standard PIC18 Commands”).
Although the Indexed Literal Offset mode can be very
useful for dynamic stack and pointer manipulation, it
can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are
accustomed to the PIC18 programming must keep in
mind that, when the extended instruction set is
enabled, register addresses of 5Fh or less are used for
Indexed Literal Offset Addressing.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
mode are provided on the following page to show how
execution is affected. The operand conditions shown in
the examples are applicable to all instructions of these
types.
DS39774D-page 346
25.2.3.1
Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the File
Select Register argument, ‘f’, in the standard,
byte-oriented and bit-oriented commands is replaced
with the literal offset value, ‘k’. As already noted, this
occurs only when ‘f’ is less than or equal to 5Fh. When
an offset value is used, it must be indicated by square
brackets (“[ ]”). As with the extended instructions, the
use of brackets indicates to the compiler that the value
is to be interpreted as an index or an offset. Omitting
the brackets, or using a value greater than 5Fh within
the brackets, will generate an error in the MPASM
Assembler.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing, the Access RAM argument is
never specified; it will automatically be assumed to be
‘0’. This is in contrast to standard operation (extended
instruction set disabled) when ‘a’ is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
Assembler.
The destination argument, ‘d’, functions as before.
In the latest versions of the MPASM Assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing.
25.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
When porting an application to the PIC18F85J11 family,
it is very important to consider the type of code. A large,
re-entrant application that is written in C and would benefit from efficient compilation will do well when using the
instruction set extensions. Legacy applications that
heavily use the Access Bank will most likely not benefit
from using the extended instruction set.
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
ADD W to Indexed
(Indexed Literal Offset mode)
BSF
Bit Set Indexed
(Indexed Literal Offset mode)
Syntax:
ADDWF [k] {,d}
Syntax:
BSF [k], b
Operands:
0 k 95
d [0, 1]
Operands:
0 f 95
0b7
Operation:
(W) + ((FSR2) + k) dest
Operation:
1 ((FSR2) + k)
Status Affected:
N, OV, C, DC, Z
Status Affected:
None
ADDWF
Encoding:
0010
Description:
01d0
kkkk
kkkk
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value, ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
Words:
1
Cycles:
1
Encoding:
1000
bbb0
kkkk
kkkk
Description:
Bit ‘b’ of the register indicated by FSR2,
offset by the value, ‘k’, is set.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write to
destination
Example:
ADDWF
Before Instruction
W
OFST
FSR2
Contents
of 0A2Ch
After Instruction
W
Contents
of 0A2Ch
[OFST] ,0
=
=
=
17h
2Ch
0A00h
=
20h
=
37h
=
20h
Example:
BSF
Before Instruction
FLAG_OFST
FSR2
Contents
of 0A0Ah
After Instruction
Contents
of 0A0Ah
[FLAG_OFST], 7
=
=
0Ah
0A00h
=
55h
=
D5h
SETF
Set Indexed
(Indexed Literal Offset mode)
Syntax:
SETF [k]
Operands:
0 k 95
Operation:
FFh ((FSR2) + k)
Status Affected:
None
Encoding:
0110
1000
kkkk
kkkk
Description:
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write
register
Example:
SETF
Before Instruction
OFST
FSR2
Contents
of 0A2Ch
After Instruction
Contents
of 0A2Ch
2010 Microchip Technology Inc.
[OFST]
=
=
2Ch
0A00h
=
00h
=
FFh
DS39774D-page 347
PIC18F85J11 FAMILY
25.2.5
SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLS
The latest versions of Microchip’s software tools have
been designed to fully support the extended instruction
set for the PIC18F85J11 family. This includes the
MPLAB C18 C Compiler, MPASM assembly language
and MPLAB Integrated Development Environment
(IDE).
When selecting a target device for software
development, MPLAB IDE will automatically set default
Configuration bits for that device. The default setting for
the XINST Configuration bit is ‘1’, enabling the
extended instruction set and Indexed Literal Offset
Addressing. For proper execution of applications
developed to take advantage of the extended
instruction set, XINST must be set during
programming.
DS39774D-page 348
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
• A menu option or dialog box within the
environment that allows the user to configure the
language tool and its settings for the project
• A command line option
• A directive in the source code
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompanying their development systems for the appropriate
information.
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
26.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +100°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD) ........................................... -0.3V to 5.6V
Voltage on any combined digital and analog pin with respect to VSS (except VDD and MCLR)...... -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.75V
Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 3.6V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Maximum output current sunk by PORTA and any PORTB and PORTC I/O pins.........................................25 mA
Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pins ..........................................................8 mA
Maximum output current sunk by PORTA and any PORTF, PORTG and PORTH I/O pins ............................2 mA
Maximum output current sourced by PORTA and any PORTB and PORTC I/O pins ...................................25 mA
Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins .....................................................8 mA
Maximum output current sourced by PORTA and any PORTF, PORTG and PORTH I/O pins .......................2 mA
Maximum current sunk byall ports combined.......................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2010 Microchip Technology Inc.
DS39774D-page 349
PIC18F85J11 FAMILY
FIGURE 26-1:
PIC18F85J11 FAMILY VOLTAGE-FREQUENCY GRAPH,
REGULATOR ENABLED (INDUSTRIAL)(1)
4.0V
3.6V
3.5V
Voltage (VDD)
3.0V
PIC18F6XJ11/8XJ11
2.5V
2.35V
2.0V
0
Note 1:
8 MHz
Frequency
40 MHz(2)
When the on-chip regulator is enabled, its BOR circuit will automatically trigger a device Reset
before VDD reaches a level at which full-speed operation is not possible.
FMAX = 25 MHz in 8-bit External Memory mode.
2:
FIGURE 26-2:
PIC18F85J11 FAMILY VOLTAGE-FREQUENCY GRAPH,
REGULATOR DISABLED (INDUSTRIAL)(1,3)
3.00V
Voltage (VDDCORE)
2.75V
2.7V
2.50V
PIC18F6XJ11/8XJ11
2.25V
2.00V
8 MHz
Note 1:
2:
3:
2.35V
Frequency
40 MHz(2)
For frequencies between 4 MHz and 40 MHz, FMAX = (51.42 MHz/V) * (VDDCORE – 2V) + 4 MHz.
FMAX = 25 MHz in 8-bit External Memory mode.
When the on-chip voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCORE VDD 3.6V.
DS39774D-page 350
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
26.1
DC Characteristics:
Supply Voltage
PIC18F85J11 Family (Industrial)
PIC18F85J11 Family
(Industrial)
Param
Symbol
No.
D001
VDD
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Characteristic
Supply Voltage
D001B VDDCORE External Supply for
Microcontroller Core
Min
Typ
Max
Units
VDDCORE
2.0
—
—
3.6
3.6
V
V
ENVREG tied to VSS
ENVREG tied to VDD
2.0
—
2.70
V
ENVREG tied to VSS
D001C AVDD
Analog Supply Voltage
VDD – 0.3
—
VDD + 0.3
V
D001D AVSS
Analog Ground Potential VSS – 0.3
—
VSS + 0.3
V
D002
VDR
RAM Data Retention
Voltage(1)
1.5
—
—
V
D003
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
—
—
0.7
V
D004
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05
—
—
D005
VBOR
Brown-out Reset Voltage
—
1.9
—
Note 1:
Conditions
See Section 5.3 “Power-on
Reset (POR)” for details
V/ms See Section 5.3 “Power-on
Reset (POR)” for details
V
This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
2010 Microchip Technology Inc.
DS39774D-page 351
PIC18F85J11 FAMILY
26.2
DC Characteristics:
PIC18F85J11 Family
(Industrial)
Param
No.
Power-Down and Supply Current
PIC18F85J11 Family (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
Typ
Max Units
Conditions
Power-Down Current (IPD)(1)
All devices
All devices
All devices
Note 1:
2:
3:
4:
5:
0.2
0.9
A
-40°C
0.1
0.9
A
+25°C
0.3
3
A
+60°C
2.4
5
A
+85°C
0.5
0.9
A
-40°C
0.1
0.9
A
+25°C
0.4
3
A
+60°C
2.7
5
A
+85°C
2.7
6
A
-40°C
3.5
6
A
+25°C
4.1
8
A
+60°C
6.7
12
A
+85°C
VDD = 2.0V,
VDDCORE = 2.0V
(Sleep mode)(4)
VDD = 2.5V,
VDDCORE = 2.5V
(Sleep mode)(4)
VDD = 3.3V
(Sleep mode)(5)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
Voltage regulator disabled (ENVREG tied to VSS).
Voltage regulator enabled (ENVREG tied to VDD).
DS39774D-page 352
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
26.2
DC Characteristics:
PIC18F85J11 Family
(Industrial)
Param
No.
Power-Down and Supply Current
PIC18F85J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
Typ
Max Units
Conditions
Supply Current (IDD)(2)
All devices
All devices
All devices
2:
3:
4:
5:
16
A
-40°C
7
16
A
+25°C
9.5
20
A
+85°C
10
18
A
-40°C
10.5
18
A
+25°C
12.5
24
A
+85°C
41
100
A
-40°C
52
100
A
+25°C
71
110
A
+85°C
All devices 359
750
A
-40°C
387
750
A
+25°C
407
840
A
+85°C
All devices 438
850
A
-40°C
470
850
A
+25°C
491
910
A
+85°C
All devices 486
900
A
-40°C
526
900
A
+25°C
564
990
A
+85°C
All devices 0.76
1.45
mA
-40°C
0.84
1.45
mA
+25°C
0.9
1.6
mA
+85°C
1.1
1.63
mA
-40°C
1.18
1.63
mA
+25°C
1.24
1.75
mA
+85°C
All devices 1.25
1.86
mA
-40°C
1.29
1.86
mA
+25°C
1.37
1.94
mA
+85°C
All devices
Note 1:
6.5
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 31 kHz
(RC_RUN mode,
internal oscillator
source)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 1 MHz
VDD = 2.5V,
(INTOSC_RUN mode,
internal oscillator
VDDCORE = 2.5V(4)
source)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 4 MHz
VDD = 2.5V,
(INTOSC_RUN mode,
VDDCORE = 2.5V(4)
internal oscillator
source)
VDD = 3.3V(5)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
Voltage regulator disabled (ENVREG tied to VSS).
Voltage regulator enabled (ENVREG tied to VDD).
2010 Microchip Technology Inc.
DS39774D-page 353
PIC18F85J11 FAMILY
26.2
DC Characteristics:
PIC18F85J11 Family
(Industrial)
Param
No.
Power-Down and Supply Current
PIC18F85J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
Typ
Max Units
Conditions
Supply Current (IDD)(2)
All devices
All devices
All devices
Note 1:
2:
3:
4:
5:
2.4
8
A
-40°C
2.5
8
A
+25°C
4.8
12
A
+85°C
3.2
9
A
-40°C
3.2
9
A
+25°C
6
14
A
+85°C
62
82
A
-40°C
42
82
A
+25°C
59
97
A
+85°C
All devices 251
570
A
-40°C
264
570
A
+25°C
272
590
A
+85°C
All devices 284
610
A
-40°C
284
610
A
+25°C
293
650
A
+85°C
All devices 295
710
A
-40°C
323
710
A
+25°C
392
790
A
+85°C
All devices 368
760
A
-40°C
362
760
A
+25°C
370
800
A
+85°C
All devices 400
850
A
-40°C
410
850
A
+25°C
418
900
A
+85°C
All devices 460
950
A
-40°C
462
950
A
+25°C
486
1,000
A
+85°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 31 kHz
(RC_IDLE mode,
internal oscillator
source)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 1 MHz
(INTOSC_IDLE mode,
VDD = 2.5V,
VDDCORE = 2.5V(4)
internal oscillator
source)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 4 MHz
(INTOSC_IDLE mode,
VDD = 2.5V,
internal oscillator
VDDCORE = 2.5V(4)
source)
VDD = 3.3V(5)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
Voltage regulator disabled (ENVREG tied to VSS).
Voltage regulator enabled (ENVREG tied to VDD).
DS39774D-page 354
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
26.2
DC Characteristics:
PIC18F85J11 Family
(Industrial)
Param
No.
Power-Down and Supply Current
PIC18F85J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
Typ
Max Units
Conditions
Supply Current (IDD)(2)
Note 1:
2:
3:
4:
5:
All devices 165
490
A
-40°C
180
490
A
+25°C
200
490
A
+85°C
All devices 256
670
A
-40°C
260
670
A
+25°C
280
670
A
+85°C
All devices 460
850
A
-40°C
456
850
A
+25°C
482
850
A
+85°C
All devices 0.63
2.2
mA
-40°C
0.68
2.2
mA
+25°C
0.74
2.2
mA
+85°C
All devices 0.91
2.5
mA
-40°C
1.04
2.5
mA
+25°C
1.04
2.5
mA
+85°C
All devices 1.32
3.0
mA
-40°C
1.32
3.0
mA
+25°C
1.41
3.0
mA
+85°C
All devices 7.47
14
mA
-40°C
5.81
14
mA
+25°C
6.32
13
mA
+85°C
All devices 8.84
18
mA
-40°C
8.66
18
mA
+25°C
7.97
16
mA
+85°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 1 MHz
(PRI_RUN mode,
EC oscillator)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 4 MHz
(PRI_RUN mode,
EC oscillator)
VDD = 3.3V(5)
VDD = 2.5V,
VDDCORE = 2.5V(4)
VDD = 3.3V(5)
FOSC = 40 MHz
(PRI_RUN mode,
EC oscillator)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
Voltage regulator disabled (ENVREG tied to VSS).
Voltage regulator enabled (ENVREG tied to VDD).
2010 Microchip Technology Inc.
DS39774D-page 355
PIC18F85J11 FAMILY
26.2
DC Characteristics:
PIC18F85J11 Family
(Industrial)
Param
No.
Power-Down and Supply Current
PIC18F85J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
Typ
Max Units
Conditions
Supply Current (IDD)(2)
All devices
All devices
2:
3:
4:
5:
3.8
mA
-40°C
3.8
mA
+25°C
3.01
4.5
mA
+85°C
4.5
5.4
mA
-40°C
4.8
5.6
mA
+25°C
4.54
5.6
mA
+85°C
All devices 5.72
6.7
mA
-40°C
5.55
6.5
mA
+25°C
5.3
6.5
mA
+85°C
7.4
8.5
mA
-40°C
All devices
Note 1:
2.8
3.02
7.23
8.5
mA
+25°C
6.55
7.5
mA
+85°C
All devices 9.74
11.6
mA
-40°C
9.43
11.6
mA
+25°C
8.89
10.5
mA
+85°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 4 MHz,
16 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 4 MHz,
16 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
VDD =
3.3V(5)
VDD = 2.5V,
VDDCORE = 2.5V(4)
VDD =
3.3V(5)
FOSC = 4 MHz,
16 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
FOSC = 10 MHz,
40 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
FOSC = 10 MHz,
40 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
Voltage regulator disabled (ENVREG tied to VSS).
Voltage regulator enabled (ENVREG tied to VDD).
DS39774D-page 356
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
26.2
DC Characteristics:
PIC18F85J11 Family
(Industrial)
Param
No.
Power-Down and Supply Current
PIC18F85J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
Typ
Max Units
Conditions
50
120
A
-40°C
51
120
A
+25°C
Supply Current (IDD)(2)
All devices
Note 1:
2:
3:
4:
5:
54
130
A
+85°C
All devices 223
480
A
-40°C
134
300
A
+25°C
110
270
A
+85°C
All devices 307
550
A
-40°C
254
500
A
+25°C
194
460
A
+85°C
All devices 307
850
A
-40°C
200
850
A
+25°C
202
800
A
+85°C
All devices 483
950
A
-40°C
318
950
A
+25°C
343
900
A
+85°C
All devices 0.52
1.3
mA
-40°C
0.47
1.2
mA
+25°C
0.47
1.2
mA
+85°C
All devices 2.38
8
mA
-40°C
2.04
8
mA
+25°C
2.52
9
mA
+85°C
All devices 3.02
10
mA
-40°C
2.99
10
mA
+25°C
4.23
11
mA
+85°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 3.3V(5)
VDD = 2.5V,
VDDCORE = 2.5V(4)
VDD = 3.3V(5)
FOSC = 40 MHz
(PRI_IDLE mode,
EC oscillator)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
Voltage regulator disabled (ENVREG tied to VSS).
Voltage regulator enabled (ENVREG tied to VDD).
2010 Microchip Technology Inc.
DS39774D-page 357
PIC18F85J11 FAMILY
26.2
DC Characteristics:
PIC18F85J11 Family
(Industrial)
Param
No.
Power-Down and Supply Current
PIC18F85J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
Typ
Max Units
Conditions
Supply Current (IDD)(2)
All devices 10.5
22
A
-10°C
13.4
28
A
+25°C
17.6
40
A
+70°C
All devices 13.2
30
A
-10°C
16.2
35
A
+25°C
20.7
50
A
+70°C
39
120
A
-10°C
58
150
A
+25°C
All devices
All devices
All devices
All devices
Note 1:
2:
3:
4:
5:
75
190
A
+70°C
5.7
15
A
-10°C
8.9
20
A
+25°C
12.8
26
A
+70°C
6.6
17
A
-10°C
9.7
24
A
+25°C
13.7
30
A
+70°C
39
115
A
-10°C
52.8
145
A
+25°C
72.7
185
A
+70°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 32 kHz(3)
(SEC_RUN mode,
Timer1 as clock)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 32 kHz(3)
(SEC_IDLE mode,
Timer1 as clock)
VDD = 3.3V(5)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
Voltage regulator disabled (ENVREG tied to VSS).
Voltage regulator enabled (ENVREG tied to VDD).
DS39774D-page 358
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
26.2
DC Characteristics:
PIC18F85J11 Family
(Industrial)
Param
No.
Device
Power-Down and Supply Current
PIC18F85J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Typ
Max Units
Conditions
Module Differential Currents (IWDT, IOSCB, IAD)
Watchdog Timer 1.6
4
A
-40°C
1.7
4
A
+25°C
1.6
4
A
+85°C
2.5
5
A
-40°C
2.5
5
A
+25°C
2.3
5
A
+85°C
3.8
6
A
-40°C
2.6
6
A
+25°C
2.4
6
A
+85°C
Timer1 Oscillator 6.6
12.5
A
-40°C
D025
(IOSCB)
7.9
12.5
A
+25°C
11.5
18
A
+85°C
7.2
12.5
A
-40°C
8.1
12.5
A
+25°C
11.9 18.5
A
+85°C
7
12.5
A
-40°C
9
12.5
A
+25°C
11
18.5
A
+85°C
A/D Converter
1
1.5
A
-40°C to
D026
+85°C
(IAD)
D022
(IWDT)
Note 1:
2:
3:
4:
5:
1
1.5
A
-40°C to
+85°C
1
1.5
A
-40°C to
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
32 kHz on Timer1(3)
VDD = 2.5V,
VDDCORE = 2.5V(4)
32 kHz on Timer1(3)
VDD = 3.3V(5)
32 kHz on Timer1(3)
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
A/D on, not converting
VDDCORE = 2.5V(4)
VDD = 3.3V(5)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
Voltage regulator disabled (ENVREG tied to VSS).
Voltage regulator enabled (ENVREG tied to VDD).
2010 Microchip Technology Inc.
DS39774D-page 359
PIC18F85J11 FAMILY
26.3
DC Characteristics: PIC18F85J11 Family (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Max
Units
Conditions
with TTL Buffer
VSS
0.15 VDD
V
VDD < 3.3V
—
0.8
V
3.3V VDD 3.6V
with Schmitt Trigger Buffer
VSS
0.2 VDD
V
VSS
0.3 VDD
V
I2C™ enabled
VSS
0.8
V
SMBus enabled
Input Low Voltage
All I/O Ports:
D030
D030A
D031
D031A
RC3 and RC4
D031B
D032
MCLR
VSS
0.2 VDD
V
D033
OSC1
VSS
0.3 VDD
V
HS, HSPLL modes
D033A
OSC1
VSS
0.2 VDD
V
EC, ECPLL modes(1)
T13CKI
VSS
0.3
V
0.25 VDD + 0.8V
VDD
V
VDD < 3.3V
3.3V VDD 3.6V
D034
VIH
Input High Voltage
I/O Ports with non 5.5V Tolerance:(2)
D040
with TTL Buffer
D040A
D041
with Schmitt Trigger Buffer
D041A
RC3 and RC4
D041B
I/O Ports with 5.5V
Dxxx
VDD
V
VDD
V
0.7 VDD
VDD
V
I2C enabled
2.1
VDD
V
SMBus enabled, VDD > 3.3V
0.25 VDD + 0.8V
5.5
V
VDD < 3.3V
3.3V VDD 3.6V
Tolerance:(2)
with TTL Buffer
DxxxA
Dxxx
2.0
0.8 VDD
with Schmitt Trigger Buffer
2.0
5.5
V
0.8 VDD
5.5
V
VDD
V
D042
MCLR
0.8 VDD
D043
OSC1
0.7 VDD
VDD
V
HS, HSPLL modes
D043A
OSC1
0.8 VDD
VDD
V
EC, ECPLL modes
D044
T13CKI
1.6
VDD
V
I/O Ports with non 5.5V tolerance:(2)
—
200
nA
VSS VPIN VDD,
pin at high-impedance
I/O Ports with 5.5V tolerance:(2)
—
200
nA
VSS VPIN 5.5V,
pin at high-impedance
IIL
D060
Input Leakage
Current(1)
D061
MCLR
—
1
A
VSS VPIN VDD
D063
OSC1
—
1
A
VSS VPIN VDD
30
400
A
VDD = 3.3V, VPIN = VSS
D070
Note 1:
2:
IPU
Weak Pull-up Current
IPURB
PORTB Weak Pull-up Current
Negative current is defined as current sourced by the pin.
Refer to Table 11-1 for the pins that have corresponding tolerance limits.
DS39774D-page 360
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
26.3
DC Characteristics: PIC18F85J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
VOL
D080
Characteristic
Min
Max
Units
Conditions
PORTA, PORTF, PORTG,
PORTH
—
0.4
V
IOL = 3.4 mA, VDD = 3.3V,
-40C to +85C
PORTD, PORTE, PORTJ
—
0.4
V
IOL = 3.4 mA, VDD = 3.3V,
-40C to +85C
PORTB, PORTC
—
0.4
V
IOL = 8.5 mA, VDD = 3.3V,
-40C to +85C
OSC2/CLKO
(EC, ECPLL modes)
—
0.4
V
IOL = 1.6 mA, VDD = 3.3V,
-40C to +85C
PORTA, PORTF, PORTG,
PORTH
2.4
—
V
IOH = -2 mA, VDD = 3.3V,
-40C to +85C
PORTD, PORTE, PORTJ
2.4
—
V
IOH = -2 mA, VDD = 3.3V,
-40C to +85C
PORTB, PORTC
2.4
—
V
IOH = -6 mA, VDD = 3.3V,
-40C to +85C
2.4
—
V
IOH = -1 mA, VDD = 3.3V,
-40C to +85C
Output Low Voltage
I/O Ports:
D083
VOH
D090
Output High Voltage(1)
I/O Ports:
D092
OSC2/CLKO
(INTOSC, EC, ECPLL modes)
V
Capacitive Loading Specs
on Output Pins
D100
COSC2 OSC2 Pin
—
15
pF
In HS mode when
external clock is used to
drive OSC1
D101
CIO
All I/O Pins and OSC2
—
50
pF
To meet the AC Timing
Specifications
D102
CB
SCL, SDA
—
400
pF
I2C™ Specification
Note 1:
2:
Negative current is defined as current sourced by the pin.
Refer to Table 11-1 for the pins that have corresponding tolerance limits.
2010 Microchip Technology Inc.
DS39774D-page 361
PIC18F85J11 FAMILY
TABLE 26-1:
MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
Program Flash Memory
D130
EP
Cell Endurance
100
1k
—
E/W -40C to +85C
D131
VPR
VDD for Read
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D132
VPEW
Voltage for Self-Timed Erase or
Write
VDD
2.35
—
3.6
V
ENVREG tied to VDD
VDDCORE
ENVREG tied to VSS
2.25
—
2.7
V
D133A TIW
Self-Timed Write Cycle Time
—
2.8
—
ms
D133B TIE
Self-Timed Block Erase Cycle
Time
—
33
—
ms
D134
TRETD Characteristic Retention
20
—
—
Year Provided no other
specifications are violated
D135
IDDP
Supply Current during
Programming
—
3
7
mA
D1xxx
TWE
Writes per Erase Cycle
—
—
1
Per one physical word
address
† Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS39774D-page 362
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 26-2:
COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V VDD 3.6V, -40°C TA +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
D300
VIOFF
Input Offset Voltage
—
±5.0
±25
mV
D301
VICM
Input Common Mode Voltage
0
—
AVDD – 1.5
V
D302
CMRR
Common Mode Rejection Ratio
55
—
—
dB
D303
TRESP
Response Time(1)
—
150
400
ns
D304
TMC2OV
Comparator Mode Change to
Output Valid
—
—
10
s
D305
VIRV
Internal Reference Voltage
—
1.2
—
V
Note 1:
Comments
Response time measured with one comparator input at (AVDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 26-3:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V VDD 3.6V, -40°C TA +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
D310
VRES
Resolution
VDD/24
—
VDD/32
LSb
D311
VRAA
Absolute Accuracy
—
—
1/2
LSb
D312
VRUR
Unit Resistor Value (R)
—
2k
—
D313
TSET
Settling Time(1)
—
—
10
s
Note 1:
Comments
Settling time measured while CVRR = 1 and CVR bits transition from ‘0000’ to ‘1111’.
TABLE 26-4:
INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C TA +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
VRGOUT Regulator Output Voltage
CEFC
External Filter Capacitor Value
2010 Microchip Technology Inc.
Min
Typ
Max
Units
—
2.5
—
V
4.7
10
—
F
Comments
Capacitor must be low
series resistance
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DS39774D-page 390
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
)
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2010 Microchip Technology Inc.
DS39774D-page 391
PIC18F85J11 FAMILY
NOTES:
DS39774D-page 392
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
APPENDIX A:
REVISION HISTORY
APPENDIX B:
Revision A (October 2006)
Original data sheet for PIC18F85J11 family devices.
MIGRATION
BETWEEN HIGH-END
DEVICE FAMILIES
Devices in the PIC18F85J11 and PIC18F8722 families
are very similar in their functions and feature sets. However, there are some potentially important differences
which should be considered when migrating an application across device families to achieve a new design goal.
These are summarized in Table B-1. The areas of
difference which could have a major impact on migration
are discussed in greater detail later in this section.
Revision B (March 2007)
Updated power-down and supply current electrical
characteristics and package detail drawings.
Revision C (April 2007)
Updated electrical characteristics.
Revision D (February 2010)
Updated electrical characteristics and package detail
illustrations. Minor text edits throughout document.
TABLE B-1:
NOTABLE DIFFERENCES BETWEEN PIC18F85J11 AND PIC18F8722 FAMILIES
Characteristic
Operating Frequency
Supply Voltage
Operating Current
Program Memory Endurance
I/O Sink/Source at 25 mA
Input Voltage Tolerance on I/O pins
I/O
Pull-ups
Oscillator Options
Program Memory Retention
PIC18F85J11 Family
PIC18F8722 Family
40 MHz @ 2.35V
40 MHz @ 4.2V
2.0V-3.6V, dual voltage requirement
2.0V-5.5V
Low
Lower
1,000 write/erase cycles (typical)
100,000 write/erase cycles (typical)
PORTB and PORTC only
All ports
5.5V on digital only pins
VDD on all I/O pins
68 (RF0 is not available)
70
PORTB, PORTD, PORTE
and PORTJ
PORTB
Limited options (EC, HS, PLL,
flexible INTRC)
More options (EC, HS, XT, LP, RC,
PLL, flexible INTRC)
20 years (minimum)
40 years (minimum)
Self-Writes to Program Memory
Available
Available
Programming Time (normalized)
156 µs/byte (10 ms/64-byte block)
15.6 µs/byte (1 ms/64)
Low voltage, key sequence
VPP and LVP
Programming Entry
Code Protection
Configuration Words
Power-up Timer
Data EEPROM
Single block, all or nothing
Multiple code protection blocks
Stored in last 4 words of program
memory space
Stored in configuration space,
starting at 300000h
Always on
Configurable
Use self-programming
Available
BOR
Simple BOR with voltage regulator
Programmable BOR
LVD
Simple LVD with voltage regulator
Available
12
16
A/D Channels
A/D Calibration
Required
Not required
Microprocessor mode (EMB)
Self-calibration feature
Available
External Memory Addressing
Address shifting available
Address shifting not available
Not available
Available
In-Circuit Emulation
2010 Microchip Technology Inc.
DS39774D-page 393
PIC18F85J11 FAMILY
B.1
Power Requirement Differences
B.3
Oscillator Differences
The most significant difference between the
PIC18F85J11 and PIC18F8722 device families is the
power requirements. PIC18F85J11 devices are
designed on a smaller process; this results in lower
maximum voltage and higher leakage current.
PIC18F8722 and PIC18F85J11 family devices share a
similar range of oscillator options. The major difference
is that PIC18F85J11 family devices support a smaller
number of primary (external) oscillator options, namely
HS and EC Oscillator modes.
The operating voltage range for PIC18F85J11 devices is
2.0V to 3.6V. In addition, these devices have split power
requirements: one for the core logic and one for the I/O.
One of the VDD pins is separated for the core logic supply,
VDDCORE. This pin has specific voltage and capacitor
requirements as described in Section 26.0 “Electrical
Characteristics”.
While both device families have an internal PLL that
can be used with the primary oscillators, the PLL for the
PIC18F85J11 family is not enabled as a device
configuration option. Instead, it must be enabled in
software.
The current specifications for PIC18F85J11 devices
are yet to be determined.
B.2
Pin Differences
There are several differences in the pinout between the
PIC18F85J11 and the PIC18F8722 families:
• Input voltage tolerance
• Output current capabilities
• Available I/O
Pins on the PIC18F85J11 that have digital only input
capability will tolerate voltages up to 5.5V and are thus
tolerant to voltages above VDD. Table 11-1 in
Section 11.1 “I/O Port Pin Capabilities” contains the
complete list.
In addition to input differences, there are output differences as well. PIC18F85J11 devices have three
classes of pin output current capability: high, medium
and low. Not all I/O pins can source or sink equal levels
of current. Only PORTB and PORTC support the
25 mA source/sink capability that is supported by all
output pins on the PIC18F8722. Table 11-2 in
Section 11.1 “I/O Port Pin Capabilities” contains the
complete list of output capabilities.
There are additional differences in how some pin functions are implemented on PIC18F85J11 devices. First,
the MCLR pin is dedicated only to MCLR and cannot be
configured as an input (RG5). Finally, RF0 does not
exist on PIC18F85J11 devices.
The clocking differences should be considered when
making a conversion between the PIC18F8722 and
PIC18F85J11 device families.
B.4
Peripherals
Peripherals must also be considered when making a
conversion between the PIC18F85J11 and the
PIC18F8722:
• External Memory Bus: The External Memory
Bus (EMB) on the PIC18F85J11 does not support
Microcontroller mode; however, it does support
external address offset.
• A/D Converter: There are only 12 channels on
PIC18F85J11 devices. The converters for these
devices also require a calibration step prior to
normal operation.
• Data EEPROM: PIC18F85J11 devices do not
have this module.
• BOR: PIC18F85J11 devices do not have a
programmable BOR. Simple Brown-out Reset
capability is provided through the use of the
internal voltage regulator.
• LVD: PIC18F85J11 devices do not have a
separate programmable LVD module. Simple,
Low-Voltage Detection capability with a configurable interrupt is provided through the use of the
internal voltage regulator.
All of these pin differences (including power pin
differences) should be accounted for when making a
conversion between PIC18F8722 and PIC18F85J11
devices.
DS39774D-page 394
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
INDEX
A
A/D ................................................................................... 259
A/D Converter Interrupt, Configuring ....................... 263
Acquisition Requirements ........................................ 264
ADCAL Bit ................................................................ 267
ADCON0 Register .................................................... 259
ADCON1 Register .................................................... 259
ADCON2 Register .................................................... 259
ADRESH Register ............................................ 259, 262
ADRESL Register .................................................... 259
Analog Port Pins, Configuring .................................. 265
Associated Registers ............................................... 267
Automatic Acquisition Time ...................................... 265
Configuring the Module ............................................ 263
Conversion Clock (TAD) ........................................... 265
Conversion Requirements ....................................... 385
Conversion Status (GO/DONE Bit) .......................... 262
Conversions ............................................................. 266
Converter Calibration ............................................... 267
Converter Characteristics ........................................ 384
Operation in Power-Managed Modes ...................... 267
Special Event Trigger (CCP2) .................................. 266
Use of the CCP2 Trigger .......................................... 266
Absolute Maximum Ratings ............................................. 349
AC (Timing) Characteristics ............................................. 364
Load Conditions for Device Timing
Specifications ................................................... 365
Parameter Symbology ............................................. 364
Temperature and Voltage Specifications ................. 365
Timing Conditions .................................................... 365
ACKSTAT ........................................................................ 213
ACKSTAT Status Flag ..................................................... 213
ADCAL Bit ........................................................................ 267
ADCON0 Register ............................................................ 259
GO/DONE Bit ........................................................... 262
ADCON1 Register ............................................................ 259
ADCON2 Register ............................................................ 259
ADDFSR .......................................................................... 342
ADDLW ............................................................................ 305
Addressable Universal Synchronous Asynchronous
Receiver Transmitter (AUSART). See AUSART.
ADDULNK ........................................................................ 342
ADDWF ............................................................................ 305
ADDWFC ......................................................................... 306
ADRESH Register ............................................................ 259
ADRESL Register .................................................... 259, 262
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................ 306
ANDWF ............................................................................ 307
Assembler
MPASM Assembler .................................................. 296
AUSART
Asynchronous Mode ................................................ 250
Associated Registers, Receive ........................ 253
Associated Registers, Transmit ....................... 251
Receiver ........................................................... 252
Reception Setup .............................................. 252
Setting up 9-Bit Mode with Address Detect ..... 252
Reception with Address Detect
Enable Setup ................................... 252
Transmission Setup ......................................... 250
Transmitter ....................................................... 250
2010 Microchip Technology Inc.
Baud Rate Generator (BRG) ................................... 248
Associated Registers ....................................... 248
Baud Rate Error, Calculating ........................... 248
Baud Rates, Asynchronous Modes ................. 249
High Baud Rate Select (BRGH Bit) ................. 248
Operation in Power-Managed Modes .............. 248
Sampling ......................................................... 248
Control Registers ..................................................... 245
Synchronous Master Mode ...................................... 254
Associated Registers, Receive ........................ 256
Associated Registers, Transmit ....................... 255
Reception ........................................................ 256
Reception Setup .............................................. 256
Transmission ................................................... 254
Transmission Setup ......................................... 254
Synchronous Slave Mode ........................................ 257
Associated Registers, Receive ........................ 258
Associated Registers, Transmit ....................... 257
Reception ........................................................ 258
Reception Setup .............................................. 258
Transmission ................................................... 257
Transmission Setup ......................................... 257
Auto-Wake-up on Sync Break Character ......................... 237
B
Baud Rate Generator ...................................................... 209
BC .................................................................................... 307
BCF ................................................................................. 308
BF .................................................................................... 213
BF Status Flag ................................................................. 213
Block Diagrams
16-Bit Byte Select Mode .......................................... 105
16-Bit Byte Write Mode ............................................ 103
16-Bit Word Write Mode .......................................... 104
8-Bit Multiplexed Mode ............................................ 107
A/D ........................................................................... 262
Analog Input Model .................................................. 263
AUSART Receive .................................................... 252
AUSART Transmit ................................................... 250
Baud Rate Generator .............................................. 209
Capture Mode Operation ......................................... 172
Comparator Analog Input Model .............................. 273
Comparator I/O Operating Modes ........................... 270
Comparator Output .................................................. 272
Comparator Voltage Reference ............................... 276
Comparator Voltage Reference Output
Buffer Example ................................................ 277
Compare Mode Operation ....................................... 173
Connections for On-Chip Voltage Regulator ........... 288
Device Clock .............................................................. 35
EUSART Receive .................................................... 235
EUSART Transmit ................................................... 233
External Power-on Reset Circuit
(Slow VDD Power-up) ........................................ 53
Fail-Safe Clock Monitor ........................................... 291
Generic I/O Port Operation ...................................... 129
Interrupt Logic .......................................................... 114
MSSP (I2C Master Mode) ........................................ 207
MSSP (I2C Mode) .................................................... 188
MSSP (SPI Mode) ................................................... 179
On-Chip Reset Circuit ................................................ 51
PIC18F6XJ11 ............................................................ 12
PIC18F8XJ11 ............................................................ 13
DS39774D-page 395
PIC18F85J11 FAMILY
PLL ............................................................................. 40
PORTD and PORTE (Parallel Slave Port) ............... 150
PWM Operation (Simplified) .................................... 175
Reads From Flash Program Memory ......................... 93
Single Comparator ................................................... 271
Table Read Operation ................................................ 89
Table Write Operation ................................................ 90
Table Writes to Flash Program Memory .................... 95
Timer0 in 16-Bit Mode .............................................. 154
Timer0 in 8-Bit Mode ................................................ 154
Timer1 (16-Bit Read/Write Mode) ............................ 158
Timer1 (8-Bit Mode) ................................................. 158
Timer2 ...................................................................... 164
Timer3 (16-Bit Read/Write Mode) ............................ 166
Timer3 (8-Bit Mode) ................................................. 166
Watchdog Timer ....................................................... 286
BN .................................................................................... 308
BNC .................................................................................. 309
BNN .................................................................................. 309
BNOV ............................................................................... 310
BNZ .................................................................................. 310
BOR. See Brown-out Reset.
BOV .................................................................................. 313
BRA .................................................................................. 311
BRG. See Baud Rate Generator.
BRGH Bit
TXSTA1 Register ..................................................... 227
TXSTA2 Register ..................................................... 248
Brown-out Reset (BOR) ..................................................... 53
and On-Chip Voltage Regulator ............................... 289
Detecting .................................................................... 53
BSF .................................................................................. 311
BTFSC ............................................................................. 312
BTFSS .............................................................................. 312
BTG .................................................................................. 313
BZ ..................................................................................... 314
C
C Compilers
MPLAB C18 ............................................................. 296
CALL ................................................................................ 314
CALLW ............................................................................. 343
Capture (CCP Module) ..................................................... 172
Associated Registers ............................................... 174
CCPR2H:CCPR2L Registers ................................... 172
CCPx Pin Configuration ........................................... 172
Software Interrupt .................................................... 172
Timer1/Timer3 Mode Selection ................................ 172
Capture/Compare/PWM (CCP) ........................................ 169
Capture Mode. See Capture.
CCPRxH Register .................................................... 170
CCPRxL Register ..................................................... 170
CCPx Mode and Timer Resources .......................... 170
Compare Mode. See Compare.
Configuration ............................................................ 170
Interaction of CCP1 and CCP2 for
Timer Resources .............................................. 171
Interconnect Configurations ..................................... 170
Clock Sources .................................................................... 37
Default System Clock on Reset ................................. 38
Selection Using OSCCON Register ........................... 38
CLRF ................................................................................ 315
CLRWDT .......................................................................... 315
DS39774D-page 396
Code Examples
16 x 16 Signed Multiply Routine .............................. 112
16 x 16 Unsigned Multiply Routine .......................... 112
8 x 8 Signed Multiply Routine .................................. 111
8 x 8 Unsigned Multiply Routine .............................. 111
Changing Between Capture Prescalers ................... 172
Computed GOTO Using an Offset Value ................... 69
Erasing a Flash Program Memory Block ................... 94
Fast Register Stack ................................................... 69
How to Clear RAM (Bank 1) Using Indirect
Addressing ......................................................... 82
Implementing a Real-Time Clock Using a
Timer1 Interrupt Service ................................. 161
Initializing PORTA .................................................... 130
Initializing PORTB .................................................... 132
Initializing PORTC ................................................... 134
Initializing PORTD ................................................... 137
Initializing PORTE .................................................... 140
Initializing PORTF .................................................... 143
Initializing PORTG ................................................... 145
Initializing PORTH ................................................... 147
Initializing PORTJ .................................................... 148
Loading the SSPBUF (SSPSR) Register ................. 182
Reading a Flash Program Memory Word .................. 93
Saving STATUS, WREG and BSR
Registers in RAM ............................................. 128
Writing to Flash Program Memory ............................. 96
Code Protection ............................................................... 279
COMF .............................................................................. 316
Comparator ...................................................................... 269
Analog Input Connection Considerations ................ 273
Associated Registers ............................................... 273
Configuration ........................................................... 270
Effects of a Reset .................................................... 272
Interrupts ................................................................. 272
Operation ................................................................. 271
Operation During Sleep ........................................... 272
Outputs .................................................................... 271
Reference ................................................................ 271
External Signal ................................................ 271
Internal Signal .................................................. 271
Response Time ........................................................ 271
Comparator Specifications ............................................... 363
Comparator Voltage Reference ....................................... 275
Accuracy and Error .................................................. 276
Associated Registers ............................................... 277
Configuring .............................................................. 275
Connection Considerations ...................................... 276
Effects of a Reset .................................................... 276
Operation During Sleep ........................................... 276
Compare (CCP Module) .................................................. 173
Associated Registers ............................................... 174
CCPR2 Register ...................................................... 173
CCPx Pin Configuration ........................................... 173
Software Interrupt .................................................... 173
Special Event Trigger ...................................... 167, 173
Timer1/Timer3 Mode Selection ................................ 173
Compare (CCP2 Module)
Special Event Trigger .............................................. 266
Computed GOTO ............................................................... 69
Configuration Bits ............................................................ 279
Configuration Bits, Device IDs
Associated Registers ............................................... 280
Configuration Register Protection .................................... 293
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
Core Features
Easy Migration ........................................................... 10
Extended Instruction Set .............................................. 9
External Memory Bus ................................................... 9
Memory Options ........................................................... 9
nanoWatt Technology .................................................. 9
Oscillator Options and Features .................................. 9
CPFSEQ .......................................................................... 316
CPFSGT .......................................................................... 317
CPFSLT ........................................................................... 317
Crystal Oscillator/Ceramic Resonator ................................ 39
Customer Change Notification Service ............................ 405
Customer Notification Service .......................................... 405
Customer Support ............................................................ 405
D
Data Addressing Modes ..................................................... 82
Comparing Addressing Modes with the
Extended Instruction Set Enabled ..................... 86
Direct .......................................................................... 82
Indexed Literal Offset ................................................. 85
BSR ................................................................... 87
Instructions Affected .......................................... 85
Mapping Access Bank ....................................... 87
Indirect ....................................................................... 82
Inherent and Literal .................................................... 82
Data Memory ..................................................................... 72
Access Bank .............................................................. 75
Bank Select Register (BSR) ....................................... 72
Extended Instruction Set ............................................ 85
General Purpose Registers ........................................ 75
Memory Maps
PIC18FX3J11/X4J11 Devices ........................... 73
PIC18FX5J11 Devices ....................................... 74
Special Function Registers ................................ 76
Special Function Registers ........................................ 76
DAW ................................................................................. 318
DC Characteristics
PIC18F85J11 Family ............................................... 360
Power-Down and Supply Current ............................ 352
Supply Voltage ......................................................... 351
DCFSNZ .......................................................................... 319
DECF ............................................................................... 318
DECFSZ ........................................................................... 319
Default System Clock ......................................................... 38
Details on Individual Family Members ............................... 10
Development Support ...................................................... 295
Device Overview .................................................................. 9
Features (64-Pin Devices) ......................................... 11
Features (80-Pin Devices) ......................................... 11
Direct Addressing ............................................................... 83
E
Effect on Standard PIC18 Instructions ............................. 346
Effects of Power-Managed Modes on Various
Clock Sources ............................................................ 42
Electrical Characteristics .................................................. 349
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART). See EUSART.
ENVREG Pin .................................................................... 288
2010 Microchip Technology Inc.
Equations
16 x 16 Signed Multiplication Algorithm ................... 112
16 x 16 Unsigned Multiplication Algorithm ............... 112
A/D Acquisition Time ............................................... 264
A/D Minimum Charging Time .................................. 264
Calculating the Minimum Required
Acquisition Time .............................................. 264
Errata ................................................................................... 7
EUSART
Asynchronous Mode ................................................ 233
Associated Registers, Receive ........................ 236
Associated Registers, Transmit ....................... 234
Auto-Wake-up on Sync Break ......................... 237
Break and Sync Transmit Sequence Setup ..... 238
Break Character Sequence ............................. 238
Receiver .......................................................... 235
Reception Setup .............................................. 235
Setting up 9-Bit Mode with Address Detect ..... 235
Setting up 9-Bit Mode with Address
Detect Setup ............................................ 235
Transmission Setup ......................................... 233
Transmitter ...................................................... 233
Baud Rate Generator (BRG) ................................... 227
Associated Registers ....................................... 228
Auto-Baud Rate Detect .................................... 231
Baud Rate Error, Calculating ........................... 228
Baud Rates, Asynchronous Modes ................. 229
High Baud Rate Select (BRGH Bit) ................. 227
Operation in Power-Managed Modes .............. 227
Sampling ......................................................... 227
Control Registers ..................................................... 223
Synchronous Master Mode ...................................... 239
Associated Registers, Receive ........................ 241
Associated Registers, Transmit ....................... 240
Reception ........................................................ 241
Reception Setup .............................................. 241
Transmission ................................................... 239
Transmission Setup ......................................... 239
Synchronous Slave Mode ........................................ 242
Associated Registers, Receive ........................ 243
Associated Registers, Transmit ....................... 242
Reception ........................................................ 243
Reception Setup .............................................. 243
Transmission ................................................... 242
Transmission Setup ......................................... 242
Extended Instruction Set ................................................. 341
ADDFSR .................................................................. 342
ADDULNK ............................................................... 342
CALLW .................................................................... 343
Considerations when Enabling ................................ 346
MOVSF .................................................................... 343
MOVSS .................................................................... 344
PUSHL ..................................................................... 344
SUBFSR .................................................................. 345
SUBULNK ................................................................ 345
Syntax ...................................................................... 341
Use with MPLAB IDE Tools ..................................... 348
Extended Microcontroller Mode ....................................... 102
DS39774D-page 397
PIC18F85J11 FAMILY
External Memory Bus ......................................................... 99
16-Bit Byte Select Mode .......................................... 105
16-Bit Byte Write Mode ............................................ 103
16-Bit Data Width Modes ......................................... 102
16-Bit Mode Timing .................................................. 106
16-Bit Word Write Mode ........................................... 104
21-Bit Addressing ..................................................... 101
8-Bit Data Width Mode ............................................. 107
8-Bit Mode Timing .................................................... 108
Address and Data Line Usage (table) ...................... 101
Address and Data Width .......................................... 101
Address Shifting ....................................................... 101
and Program Memory Modes .................................. 102
Control ..................................................................... 100
I/O Port Functions ...................................................... 99
Operation in Power-Managed Modes ...................... 109
Wait States ............................................................... 102
Weak Pull-ups on Port Pins ..................................... 102
External Oscillator Modes .................................................. 39
EC Modes .................................................................. 40
HS Modes .................................................................. 39
F
Fail-Safe Clock Monitor ............................................ 279, 291
Exiting Fail-Safe Operation ...................................... 292
Interrupts in Power-Managed Modes ....................... 292
POR or Wake-up From Sleep .................................. 292
WDT During Oscillator Failure ................................. 291
Fast Register Stack ............................................................ 69
Firmware Instructions ....................................................... 299
Flash Configuration Words
Mapping ................................................................... 279
Flash Program Memory ...................................................... 89
Associated Registers ................................................. 97
Control Registers ....................................................... 90
EECON1 and EECON2 ..................................... 90
TABLAT (Table Latch) Register ......................... 92
TBLPTR (Table Pointer) Register ...................... 92
Erase Sequence ........................................................ 94
Erasing ....................................................................... 94
Operation During Code-Protect ................................. 97
Reading ...................................................................... 93
Table Pointer
Boundaries Based on Operation ........................ 92
Table Pointer Boundaries .......................................... 92
Table Reads and Table Writes .................................. 89
Write Sequence ......................................................... 95
Writing ........................................................................ 95
Unexpected Termination .................................... 97
Write Verify ........................................................ 97
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 320
H
Hardware Multiplier .......................................................... 111
Introduction .............................................................. 111
Operation ................................................................. 111
Performance Comparison ........................................ 111
DS39774D-page 398
I
I/O Ports ........................................................................... 129
Input Pins and Voltage Considerations .................... 129
Open-Drain Outputs ................................................. 130
Output Pin Drive ...................................................... 129
Pin Capabilities ........................................................ 129
Pull-up Configuration ............................................... 130
I2C Mode (MSSP) ............................................................ 188
Acknowledge Sequence Timing .............................. 216
Associated Registers ............................................... 222
Baud Rate Generator .............................................. 209
Bus Collision
During a Repeated Start Condition .................. 220
During a Stop Condition .................................. 221
Clock Arbitration ...................................................... 210
Clock Stretching ....................................................... 202
10-Bit Slave Receive Mode (SEN = 1) ............ 202
10-Bit Slave Transmit Mode ............................ 202
7-Bit Slave Receive Mode (SEN = 1) .............. 202
7-Bit Slave Transmit Mode .............................. 202
Clock Synchronization and the CKP Bit ................... 203
Effects of a Reset .................................................... 217
General Call Address Support ................................. 206
I2C Clock Rate w/BRG ............................................. 209
Master Mode ............................................................ 207
Baud Rate Generator ...................................... 209
Operation ......................................................... 208
Reception ........................................................ 213
Repeated Start Condition Timing .................... 212
Start Condition Timing ..................................... 211
Transmission ................................................... 213
Multi-Master Communication, Bus Collision
and Arbitration ................................................. 217
Multi-Master Mode ................................................... 217
Operation ................................................................. 193
Read/Write Bit Information (R/W Bit) ............... 193, 195
Registers ................................................................. 188
Serial Clock (SCK/SCL) ........................................... 195
Slave Mode .............................................................. 193
Addressing ....................................................... 193
Addressing Masking ........................................ 194
Reception ........................................................ 195
Transmission ................................................... 195
Sleep Operation ....................................................... 217
Stop Condition Timing ............................................. 216
INCF ................................................................................ 320
INCFSZ ............................................................................ 321
In-Circuit Debugger .......................................................... 293
In-Circuit Serial Programming (ICSP) ...................... 279, 293
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 346
Indexed Literal Offset Mode ............................................. 346
Indirect Addressing ............................................................ 83
INFSNZ ............................................................................ 321
Initialization Conditions for all Registers ...................... 57–61
Instruction Cycle ................................................................ 70
Clocking Scheme ....................................................... 70
Flow/Pipelining ........................................................... 70
Instruction Set .................................................................. 299
ADDLW .................................................................... 305
ADDWF .................................................................... 305
ADDWF (Indexed Literal Offset Mode) .................... 347
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ADDWFC ................................................................. 306
ANDLW .................................................................... 306
ANDWF .................................................................... 307
BC ............................................................................ 307
BCF .......................................................................... 308
BN ............................................................................ 308
BNC ......................................................................... 309
BNN ......................................................................... 309
BNOV ....................................................................... 310
BNZ .......................................................................... 310
BOV ......................................................................... 313
BRA .......................................................................... 311
BSF .......................................................................... 311
BSF (Indexed Literal Offset Mode) .......................... 347
BTFSC ..................................................................... 312
BTFSS ..................................................................... 312
BTG .......................................................................... 313
BZ ............................................................................ 314
CALL ........................................................................ 314
CLRF ........................................................................ 315
CLRWDT .................................................................. 315
COMF ...................................................................... 316
CPFSEQ .................................................................. 316
CPFSGT .................................................................. 317
CPFSLT ................................................................... 317
DAW ......................................................................... 318
DCFSNZ .................................................................. 319
DECF ....................................................................... 318
DECFSZ ................................................................... 319
General Format ........................................................ 301
GOTO ...................................................................... 320
INCF ......................................................................... 320
INCFSZ .................................................................... 321
INFSNZ .................................................................... 321
IORLW ..................................................................... 322
IORWF ..................................................................... 322
LFSR ........................................................................ 323
MOVF ....................................................................... 323
MOVFF .................................................................... 324
MOVLB .................................................................... 324
MOVLW ................................................................... 325
MOVWF ................................................................... 325
MULLW .................................................................... 326
MULWF .................................................................... 326
NEGF ....................................................................... 327
NOP ......................................................................... 327
Opcode Field Descriptions ....................................... 300
PIC18F85J11 Family (table) .................................... 302
POP ......................................................................... 328
PUSH ....................................................................... 328
RCALL ..................................................................... 329
RESET ..................................................................... 329
RETFIE .................................................................... 330
RETLW .................................................................... 330
RETURN .................................................................. 331
RLCF ........................................................................ 331
RLNCF ..................................................................... 332
RRCF ....................................................................... 332
RRNCF .................................................................... 333
SETF ........................................................................ 333
SETF (Indexed Literal Offset Mode) ........................ 347
SLEEP ..................................................................... 334
Standard Instructions ............................................... 299
SUBFWB .................................................................. 334
SUBLW .................................................................... 335
SUBWF .................................................................... 335
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SUBWFB ................................................................. 336
SWAPF .................................................................... 336
TBLRD ..................................................................... 337
TBLWT .................................................................... 338
TSTFSZ ................................................................... 339
XORLW ................................................................... 339
XORWF ................................................................... 340
INTCON Register
RBIF Bit ................................................................... 132
INTCON Registers ........................................................... 115
Inter-Integrated Circuit. See I2C Mode.
Internal Oscillator Block ..................................................... 41
Adjustment ................................................................. 41
INTOSC Frequency Drift ........................................... 41
INTOSC Output Frequency ....................................... 41
OSC1, OSC2 Pin Configuration ................................ 41
Internal RC Oscillator
Use with WDT .......................................................... 286
Internal Voltage Regulator Specifications ........................ 363
Internet Address .............................................................. 405
Interrupt Sources ............................................................. 279
A/D Conversion Complete ....................................... 263
Capture Complete (CCP) ........................................ 172
Compare Complete (CCP) ...................................... 173
Interrupt-on-Change (RB7:RB4) .............................. 132
TMR1 Overflow ........................................................ 157
TMR2 to PR2 Match (PWM) .................................... 175
TMR3 Overflow ........................................................ 165
Interrupts ......................................................................... 113
During, Context Saving ............................................ 128
INTx Pin ................................................................... 128
PORTB, Interrupt-on-Change .................................. 128
TMR0 ....................................................................... 128
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ..... 132
INTOSC, INTRC. See Internal Oscillator Block.
IORLW ............................................................................. 322
IORWF ............................................................................. 322
IPR Registers ................................................................... 124
L
LFSR ............................................................................... 323
M
Master Clear (MCLR) ......................................................... 53
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Organization ........................................................ 63
Data Memory ............................................................. 72
Program Memory ....................................................... 63
Memory Programming Requirements .............................. 362
Microchip Internet Web Site ............................................. 405
Microcontroller Mode ....................................................... 102
Migration Between High-End Device Families ................. 393
Oscillator Differences .............................................. 394
Peripherals .............................................................. 394
Pin Differences ........................................................ 394
Power Requirement Differences .............................. 394
MOVF .............................................................................. 323
MOVFF ............................................................................ 324
MOVLB ............................................................................ 324
MOVLW ........................................................................... 325
MOVSF ............................................................................ 343
MOVSS ............................................................................ 344
MOVWF ........................................................................... 325
MPLAB ASM30 Assembler, Linker, Librarian .................. 296
DS39774D-page 399
PIC18F85J11 FAMILY
MPLAB Integrated Development Environment
Software ................................................................... 295
MPLAB PM3 Device Programmer .................................... 298
MPLAB REAL ICE In-Circuit Emulator System ................ 297
MPLINK Object Linker/MPLIB Object Librarian ............... 296
MSSP
ACK Pulse ........................................................ 193, 195
Control Registers (general) ...................................... 179
Module Overview ..................................................... 179
SPI Master/Slave Connection .................................. 183
SSPBUF Register .................................................... 184
SSPSR Register ...................................................... 184
MULLW ............................................................................ 326
MULWF ............................................................................ 326
N
NEGF ............................................................................... 327
NOP ................................................................................. 327
O
Oscillator
Switching .................................................................... 37
Timer1 as Secondary Clock ....................................... 37
Transitions ................................................................. 38
Oscillator Configuration ...................................................... 35
EC .............................................................................. 35
ECPLL ........................................................................ 35
HS .............................................................................. 35
HSPLL ........................................................................ 35
Internal Oscillator Block ............................................. 41
INTOSC ..................................................................... 35
INTRC ........................................................................ 35
Oscillator Selection .......................................................... 279
Oscillator Start-up Timer (OST) ......................................... 42
Oscillator, Timer1 ..................................................... 157, 167
Oscillator, Timer3 ............................................................. 165
P
Packaging ........................................................................ 387
Details ...................................................................... 388
Marking .................................................................... 387
Parallel Slave Port (PSP) ................................................. 150
Associated Registers ............................................... 152
RE0/RD Pin .............................................................. 150
RE1/WR Pin ............................................................. 150
RE2/CS Pin .............................................................. 150
PIE Registers ................................................................... 121
Pin Functions
AVDD .................................................................... 29, 20
AVSS .................................................................... 20, 29
ENVREG .............................................................. 20, 29
MCLR ................................................................... 14, 21
RA0/AN0 .............................................................. 14, 21
RA1/AN1 .............................................................. 14, 21
RA2/AN2/VREF- .................................................... 14, 21
RA3/AN3/VREF+ ................................................... 14, 21
RA4/T0CKI ........................................................... 14, 21
RA5/AN4 .............................................................. 14, 21
RA6/OSC2/CLKO ................................................ 14, 21
RA7/OSC1/CLKI .................................................. 14, 21
RB0/INT0 ............................................................. 15, 22
RB1/INT1 ............................................................. 15, 22
RB2/INT2 ............................................................. 15, 22
RB3/INT3 ................................................................... 15
RB3/INT3/CCP2 ......................................................... 22
RB4/KBI0 ............................................................. 15, 22
DS39774D-page 400
RB5/KBI1 ............................................................. 15, 22
RB6/KBI2/PGC .................................................... 15, 22
RB7/KBI3/PGD .................................................... 15, 22
RC0/T1OSO/T13CKI ........................................... 16, 23
RC1/T1OSI/CCP2 ................................................ 16, 23
RC2/CCP1 ........................................................... 16, 23
RC3/SCK/SCL ..................................................... 16, 23
RC4/SDI/SDA ...................................................... 16, 23
RC5/SDO ............................................................. 16, 23
RC6/TX1/CK1 ...................................................... 16, 23
RC7/RX1/DT1 ...................................................... 16, 23
RD0/AD0/PSP0 ......................................................... 24
RD0/PSP0 ................................................................. 17
RD1/AD1/PSP1 ......................................................... 24
RD1/PSP1 ................................................................. 17
RD2/AD2/PSP2 ......................................................... 24
RD2/PSP2 ................................................................. 17
RD3/AD3/PSP3 ......................................................... 24
RD3/PSP3 ................................................................. 17
RD4/AD4/PSP4 ......................................................... 24
RD4/PSP4 ................................................................. 17
RD5/AD5/PSP5 ......................................................... 24
RD5/PSP5 ................................................................. 17
RD6/AD6/PSP6 ......................................................... 24
RD6/PSP6 ................................................................. 17
RD7/AD7/PSP7 ......................................................... 24
RD7/PSP7 ................................................................. 17
RE0/RD ..................................................................... 18
RE0/RD/AD8 .............................................................. 25
RE1/WR ..................................................................... 18
RE1/WR/AD9 ............................................................. 25
RE2/AD10/CS ............................................................ 25
RE2/CS ...................................................................... 18
RE3 ............................................................................ 18
RE3/AD11 .................................................................. 25
RE4 ............................................................................ 18
RE4/AD12 .................................................................. 25
RE5 ............................................................................ 18
RE5/AD13 .................................................................. 25
RE6 ............................................................................ 18
RE6/AD14 .................................................................. 25
RE7/AD15/CCP2 ....................................................... 25
RE7/CCP2 ................................................................. 18
RF1/AN6/C2OUT ................................................. 19, 26
RF2/AN7/C1OUT ................................................. 19, 26
RF3/AN8 .............................................................. 19, 26
RF4/AN9 .............................................................. 19, 26
RF5/AN10/CVREF ................................................ 19, 26
RF6/AN11 ............................................................ 19, 26
RF7/AN5/SS ........................................................ 26, 19
RG0 ..................................................................... 20, 27
RG1/TX2/CK2 ...................................................... 20, 27
RG2/RX2/DT2 ...................................................... 20, 27
RG3 ..................................................................... 20, 27
RG4 ..................................................................... 20, 27
RH0/A16 .................................................................... 28
RH1/A17 .................................................................... 28
RH2/A18 .................................................................... 28
RH3/A19 .................................................................... 28
RH4 ........................................................................... 28
RH5 ........................................................................... 28
RH6 ........................................................................... 28
RH7 ........................................................................... 28
RJ0/ALE .................................................................... 29
RJ1/OE ...................................................................... 29
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RJ2/WRL .................................................................... 29
RJ3/WRH ................................................................... 29
RJ4/BA0 ..................................................................... 29
RJ5/CE ....................................................................... 29
RJ6/LB ....................................................................... 29
RJ7/UB ....................................................................... 29
VDD ...................................................................... 29, 20
VDDCORE/VCAP ..................................................... 29, 20
VSS ....................................................................... 20, 29
Pinout I/O Descriptions
PIC18F6XJ11 ............................................................. 14
PIC18F8XJ11 ............................................................. 21
PIR Registers ................................................................... 118
PLL ..................................................................................... 40
ECPLL Oscillator Mode .............................................. 40
HSPLL Oscillator Mode .............................................. 40
POP ................................................................................. 328
POR. See Power-on Reset.
PORTA
Associated Registers ............................................... 131
LATA Register .......................................................... 130
PORTA Register ...................................................... 130
TRISA Register ........................................................ 130
PORTB
Associated Registers ............................................... 133
LATB Register .......................................................... 132
PORTB Register ...................................................... 132
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........ 132
TRISB Register ........................................................ 132
PORTC
Associated Registers ............................................... 136
LATC Register ......................................................... 134
PORTC Register ...................................................... 134
RC3/SCK/SCL Pin ................................................... 195
TRISC Register ........................................................ 134
PORTD ............................................................................ 150
Associated Registers ............................................... 139
LATD Register ......................................................... 137
PORTD Register ...................................................... 137
TRISD Register ........................................................ 137
PORTE
Associated Registers ............................................... 142
LATE Register .......................................................... 140
PORTE Register ...................................................... 140
RE0/RD Pin .............................................................. 150
RE1/WR Pin ............................................................. 150
RE2/CS Pin .............................................................. 150
TRISE Register ........................................................ 140
PORTF
Associated Registers ............................................... 144
LATF Register .......................................................... 143
PORTF Register ...................................................... 143
TRISF Register ........................................................ 143
PORTG
Associated Registers ............................................... 146
LATG Register ......................................................... 145
PORTG Register ...................................................... 145
TRISG Register ........................................................ 145
PORTH
Associated Registers ............................................... 147
LATH Register ......................................................... 147
PORTH Register ...................................................... 147
TRISH Register ........................................................ 147
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PORTJ
Associated Registers ............................................... 149
LATJ Register .......................................................... 148
PORTJ Register ...................................................... 148
TRISJ Register ........................................................ 148
Power-Managed Modes ..................................................... 43
and SPI Operation ................................................... 187
Clock Sources ........................................................... 43
Clock Transitions and Status Indicators .................... 44
Entering ..................................................................... 43
Exiting Idle and Sleep Modes .................................... 49
By Interrupt ........................................................ 49
By Reset ............................................................ 49
By WDT Time-out .............................................. 49
Without an Oscillator Start-up Delay ................. 49
Idle Modes ................................................................. 47
PRI_IDLE .......................................................... 48
RC_IDLE ........................................................... 49
SEC_IDLE ......................................................... 48
Multiple Sleep Commands ......................................... 44
Run Modes ................................................................ 44
PRI_RUN ........................................................... 44
RC_RUN ............................................................ 46
SEC_RUN ......................................................... 44
Selecting .................................................................... 43
Sleep Mode ............................................................... 47
Summary (table) ........................................................ 43
Power-on Reset (POR) ...................................................... 53
Power-up Delays ............................................................... 42
Power-up Timer (PWRT) ............................................. 42, 54
Time-out Sequence ................................................... 54
Prescaler, Capture ........................................................... 172
Prescaler, Timer0 ............................................................ 155
Prescaler, Timer2 ............................................................ 176
PRI_IDLE Mode ................................................................. 48
PRI_RUN Mode ................................................................. 44
Program Counter ............................................................... 67
PCL, PCH and PCU Registers .................................. 67
PCLATH and PCLATU Registers .............................. 67
Program Memory
Extended Instruction Set ........................................... 84
Flash Configuration Words ........................................ 64
Hard Memory Vectors ................................................ 64
Instructions ................................................................ 71
Two-Word .......................................................... 71
Interrupt Vector .......................................................... 64
Look-up Tables .......................................................... 69
Memory Maps ............................................................ 63
Hard Vectors and Configuration Words ............. 64
Modes ........................................................................ 65
Extended Microcontroller ................................... 65
Extended Microcontroller (Address Shifting) ..... 66
Memory Access (table) ...................................... 66
Microcontroller ................................................... 65
Reset Vector .............................................................. 64
Program Memory Modes
Operation of the External Memory Bus ................... 102
Program Verification and Code Protection ...................... 293
Programming, Device Instructions ................................... 299
PSP.See Parallel Slave Port.
PSPMODE Bit (PSPCON Register) ................................. 150
Pulse-Width Modulation. See PWM (CCP Module).
PUSH ............................................................................... 328
PUSH and POP Instructions .............................................. 68
PUSHL ............................................................................. 344
DS39774D-page 401
PIC18F85J11 FAMILY
PWM (CCP Module)
Associated Registers ............................................... 177
Duty Cycle ................................................................ 176
Example Frequencies/Resolutions .......................... 176
Period ....................................................................... 175
Setup for PWM Operation ........................................ 177
TMR2 to PR2 Match ................................................ 175
Q
Q Clock ............................................................................ 176
R
RAM. See Data Memory.
RC_IDLE Mode .................................................................. 49
RC_RUN Mode .................................................................. 46
RCALL .............................................................................. 329
RCON Register
Bit Status During Initialization .................................... 56
Reader Response ............................................................ 406
Register File ....................................................................... 75
Register File Summary ................................................. 77–80
Registers
ADCON0 (A/D Control 0) ......................................... 259
ADCON1 (A/D Control 1) ......................................... 260
ADCON2 (A/D Control 2) ......................................... 261
BAUDCON1 (Baud Rate Control 1) ......................... 226
CCPxCON (CCPx Control) ...................................... 169
CMCON (Comparator Control) ................................ 269
CONFIG1H (Configuration 1 High) .......................... 281
CONFIG1L (Configuration 1 Low) ............................ 281
CONFIG2H (Configuration 2 High) .......................... 283
CONFIG2L (Configuration 2 Low) ............................ 282
CONFIG3H (Configuration 3 High) .......................... 284
CONFIG3L (Configuration 3 Low) ...................... 65, 284
CVRCON (Comparator Voltage
Reference Control) ........................................... 275
DEVID1 (Device ID Register 1) ................................ 285
DEVID2 (Device ID Register 2) ................................ 285
EECON1 (EEPROM Control 1) .................................. 91
INTCON (Interrupt Control) ...................................... 115
INTCON2 (Interrupt Control 2) ................................. 116
INTCON3 (Interrupt Control 3) ................................. 117
IPR1 (Peripheral Interrupt Priority 1) ........................ 124
IPR2 (Peripheral Interrupt Priority 2) ........................ 125
IPR3 (Peripheral Interrupt Priority 3) ........................ 126
MEMCON (External Memory Bus Control) .............. 100
OSCCON (Oscillator Control) .................................... 36
OSCTUNE (Oscillator Tuning) ................................... 37
PIE1 (Peripheral Interrupt Enable 1) ........................ 121
PIE2 (Peripheral Interrupt Enable 2) ........................ 122
PIE3 (Peripheral Interrupt Enable 3) ........................ 123
PIR1 (Peripheral Interrupt Request (Flag) 1) ........... 118
PIR2 (Peripheral Interrupt Request (Flag) 2) ........... 119
PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 120
PSPCON (Parallel Slave Port Control) .................... 151
RCON (Reset Control) ....................................... 52, 127
RCSTA1 (EUSART Receive Status
and Control) ..................................................... 225
RCSTA2 (AUSART Receive Status
and Control) ..................................................... 247
SSPCON1 (MSSP Control 1, I2C Mode) ................. 190
SSPCON1 (MSSP Control 1, SPI Mode) ................. 181
SSPCON2 (MSSP Control 2, I2C Master Mode) ..... 191
SSPCON2 (MSSP Control 2, I2C Slave Mode) ....... 192
SSPSTAT (MSSP Status, I2C Mode) ....................... 189
SSPSTAT (MSSP Status, SPI Mode) ...................... 180
DS39774D-page 402
STATUS .................................................................... 81
STKPTR (Stack Pointer) ............................................ 68
T0CON (Timer0 Control) ......................................... 153
T1CON (Timer1 Control) ......................................... 157
T2CON (Timer2 Control) ......................................... 163
T3CON (Timer3 Control) ......................................... 165
TXSTA1 (EUSART Transmit Status
and Control) ..................................................... 224
TXSTA2 (AUSART Transmit Status
and Control) ..................................................... 246
WDTCON (Watchdog Timer Control) ...................... 287
RESET ............................................................................. 329
Reset ................................................................................. 51
Brown-out Reset (BOR) ............................................. 51
MCLR Reset, During Power-Managed Modes .......... 51
MCLR Reset, Normal Operation ................................ 51
Power-on Reset (POR) .............................................. 51
RESET Instruction ..................................................... 51
Stack Full Reset ......................................................... 51
Stack Underflow Reset .............................................. 51
Watchdog Timer (WDT) Reset .................................. 51
Resets .............................................................................. 279
Brown-out Reset (BOR) ........................................... 279
Oscillator Start-up Timer (OST) ............................... 279
Power-on Reset (POR) ............................................ 279
Power-up Timer (PWRT) ......................................... 279
RETFIE ............................................................................ 330
RETLW ............................................................................ 330
RETURN .......................................................................... 331
Return Address Stack ........................................................ 67
Return Stack Pointer (STKPTR) ........................................ 68
Revision History ............................................................... 393
RLCF ............................................................................... 331
RLNCF ............................................................................. 332
RRCF ............................................................................... 332
RRNCF ............................................................................ 333
S
SCK ................................................................................. 179
SDI ................................................................................... 179
SDO ................................................................................. 179
SEC_IDLE Mode ............................................................... 48
SEC_RUN Mode ................................................................ 44
Serial Clock, SCK ............................................................ 179
Serial Data In (SDI) .......................................................... 179
Serial Data Out (SDO) ..................................................... 179
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 333
Slave Select (SS) ............................................................. 179
SLEEP ............................................................................. 334
Sleep
OSC1 and OSC2 Pin States ...................................... 42
Software Simulator (MPLAB SIM) ................................... 297
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ........................................... 279
SPI Mode (MSSP)
Associated Registers ............................................... 187
Bus Mode Compatibility ........................................... 187
Effects of a Reset .................................................... 187
Enabling SPI I/O ...................................................... 183
Master Mode ............................................................ 184
Master/Slave Connection ......................................... 183
Operation ................................................................. 182
Operation in Power-Managed Modes ...................... 187
Serial Clock .............................................................. 179
Serial Data In ........................................................... 179
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Serial Data Out ........................................................ 179
Slave Mode .............................................................. 185
Slave Select ............................................................. 179
Slave Select Synchronization .................................. 185
SPI Clock ................................................................. 184
Typical Connection .................................................. 183
SS .................................................................................... 179
SSPOV ............................................................................. 213
SSPOV Status Flag ......................................................... 213
SSPSTAT Register
R/W Bit ............................................................. 193, 195
Stack Full/Underflow Resets .............................................. 69
STATUS Register .............................................................. 81
SUBFSR .......................................................................... 345
SUBFWB .......................................................................... 334
SUBLW ............................................................................ 335
SUBULNK ........................................................................ 345
SUBWF ............................................................................ 335
SUBWFB .......................................................................... 336
SWAPF ............................................................................ 336
T
Table Pointer Operations (table) ........................................ 92
Table Reads/Table Writes ................................................. 69
TBLRD ............................................................................. 337
TBLWT ............................................................................. 338
Timer0 .............................................................................. 153
Associated Registers ............................................... 155
Clock Source Select (T0CS Bit) ............................... 154
Interrupt .................................................................... 155
Operation ................................................................. 154
Prescaler .................................................................. 155
Switching Assignment ...................................... 155
Prescaler Assignment (PSA Bit) .............................. 155
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 155
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 154
Source Edge Select (T0SE Bit) ................................ 154
Timer1 .............................................................................. 157
16-Bit Read/Write Mode ........................................... 159
Associated Registers ............................................... 161
Interrupt .................................................................... 160
Operation ................................................................. 158
Oscillator .......................................................... 157, 159
Layout Considerations ..................................... 160
Overflow Interrupt .................................................... 157
Resetting, Using the CCPx Special
Event Trigger ................................................... 160
TMR1H Register ...................................................... 157
TMR1L Register ....................................................... 157
Use as a Clock Source ............................................ 159
Use as a Real-Time Clock ....................................... 160
Timer2 .............................................................................. 163
Associated Registers ............................................... 164
Interrupt .................................................................... 164
Operation ................................................................. 163
Output ...................................................................... 164
PR2 Register ............................................................ 175
TMR2 to PR2 Match Interrupt .................................. 175
Timer3 .............................................................................. 165
16-Bit Read/Write Mode ........................................... 167
Associated Registers ............................................... 167
Interrupt .................................................................... 167
Operation ................................................................. 166
Oscillator .......................................................... 165, 167
Overflow Interrupt .................................................... 165
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Special Event Trigger (CCP) ................................... 167
TMR3H Register ...................................................... 165
TMR3L Register ...................................................... 165
Timing Diagrams
A/D Conversion ....................................................... 385
Acknowledge Sequence .......................................... 216
Asynchronous Reception ................................. 236, 253
Asynchronous Transmission ........................... 234, 251
Asynchronous Transmission
(Back-to-Back) ......................................... 234, 251
Automatic Baud Rate Calculation ............................ 232
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 237
Auto-Wake-up Bit (WUE) During Sleep ................... 237
Baud Rate Generator with Clock Arbitration ............ 210
BRG Overflow Sequence ........................................ 232
BRG Reset Due to SDA Arbitration During
Start Condition ................................................. 219
Bus Collision During a Repeated Start
Condition (Case 1) ........................................... 220
Bus Collision During a Repeated Start
Condition (Case 2) ........................................... 220
Bus Collision During a Start Condition (SCL = 0) .... 219
Bus Collision During a Stop Condition (Case 1) ...... 221
Bus Collision During a Stop Condition (Case 2) ...... 221
Bus Collision During Start Condition (SDA Only) .... 218
Bus Collision for Transmit and Acknowledge .......... 217
Capture/Compare/PWM (CCP1, CCP2) .................. 374
CLKO and I/O .......................................................... 368
Clock Synchronization ............................................. 203
Clock/Instruction Cycle .............................................. 70
EUSART/AUSART Synchronous
Receive (Master/Slave) ................................... 383
EUSART/AUSART Synchronous
Transmission (Master/Slave) ........................... 383
Example SPI Master Mode (CKE = 0) ..................... 375
Example SPI Master Mode (CKE = 1) ..................... 376
Example SPI Slave Mode (CKE = 0) ....................... 377
Example SPI Slave Mode (CKE = 1) ....................... 378
External Clock (All Modes Except PLL) ................... 366
External Memory Bus for Sleep
(Extended Microcontroller Mode) ............ 106, 108
External Memory Bus for TBLRD
(Extended Microcontroller Mode) ............ 106, 108
Fail-Safe Clock Monitor ........................................... 292
First Start Bit Timing ................................................ 211
I2C Bus Data ............................................................ 380
I2C Bus Start/Stop Bits ............................................ 379
I2C Master Mode (7 or 10-Bit Transmission) ........... 214
I2C Master Mode (7-Bit Reception) ......................... 215
I2C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001) ............................................ 200
I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 199
I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 205
I2C Slave Mode (10-Bit Transmission) .................... 201
I2C Slave Mode (7-Bit Reception, SEN = 0,
ADMSK = 01011) ............................................ 197
I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 196
I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 204
I2C Slave Mode (7-Bit Transmission) ...................... 198
I2C Slave Mode General Call Address
Sequence (7 or 10-Bit Addressing Mode) ....... 206
I2C Stop Condition Receive or Transmit Mode ........ 216
MSSP I2C Bus Data ................................................ 381
MSSP I2C Bus Start/Stop Bits ................................. 381
DS39774D-page 403
PIC18F85J11 FAMILY
Parallel Slave Port (PSP) Read ............................... 152
Parallel Slave Port (PSP) Write ............................... 151
Program Memory Read ............................................ 370
PWM Output ............................................................ 175
Repeated Start Condition ......................................... 212
Reset, Watchdog Timer (WDT), Oscillator
Start-up Timer (OST) and Power-up
Timer (PWRT) .................................................. 372
Send Break Character Sequence ............................ 238
Slave Synchronization ............................................. 185
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 55
SPI Mode (Master Mode) ......................................... 184
SPI Mode (Slave Mode, CKE = 0) ........................... 186
SPI Mode (Slave Mode, CKE = 1) ........................... 186
Synchronous Reception
(Master Mode, SREN) ............................. 241, 256
Synchronous Transmission .............................. 239, 254
Synchronous Transmission
(Through TXEN) ....................................... 240, 255
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ....................... 55
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 ....................... 55
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise < TPWRT) ........... 54
Timer0 and Timer1 External Clock .......................... 373
Transition for Entry to Idle Mode ................................ 48
Transition for Entry to SEC_RUN Mode .................... 45
Transition for Entry to Sleep Mode ............................ 47
Transition for Two-Speed Start-up
(INTRC to HSPLL) ........................................... 290
Transition for Wake From Idle to Run Mode .............. 48
Transition for Wake From Sleep (HSPLL) ................. 47
Transition From RC_RUN Mode to
PRI_RUN Mode ................................................. 46
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 45
Transition to RC_RUN Mode ..................................... 46
Timing Diagrams and Specifications
Capture/Compare/PWM Requirements
(CCP1, CCP2) ................................................. 374
CLKO and I/O Requirements ........................... 368, 370
EUSART/AUSART Synchronous Receive
Requirements .................................................. 383
EUSART/AUSART Synchronous Transmission
Requirements ................................................... 383
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 375
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 376
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 377
Example SPI Slave Mode
Requirements (CKE = 1) ................................. 378
External Clock Requirements .................................. 366
I2C Bus Data Requirements (Slave Mode) .............. 380
I2C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 379
Internal RC Accuracy ............................................... 367
MSSP I2C Bus Data Requirements ......................... 382
MSSP I2C Bus Start/Stop Bits Requirements .......... 381
PLL Clock ................................................................ 367
Program Memory Write Requirements .................... 371
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Requirements .................................................. 372
Timer0 and Timer1 External Clock
Requirements .................................................. 373
Top-of-Stack Access .......................................................... 67
TSTFSZ ........................................................................... 339
Two-Speed Start-up ................................................. 279, 290
Two-Word Instructions
Example Cases .......................................................... 71
V
VDDCORE/VCAP Pin .......................................................... 288
Voltage Reference Specifications .................................... 363
Voltage Regulator (On-Chip) ........................................... 288
Brown-out Reset (BOR) ........................................... 289
Low-Voltage Detection (LVD) .................................. 288
Operation in Sleep Mode ......................................... 289
Power-up Requirements .......................................... 289
W
Watchdog Timer (WDT) ........................................... 279, 286
Associated Registers ............................................... 287
Control Register ....................................................... 286
Programming Considerations .................................. 286
WCOL ...................................................... 211, 212, 213, 216
WCOL Status Flag ................................... 211, 212, 213, 216
WWW Address ................................................................ 405
WWW, On-Line Support ...................................................... 7
X
XORLW ............................................................................ 339
XORWF ........................................................................... 340
DS39774D-page 404
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
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Users of Microchip products can receive assistance
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To register, access the Microchip web site at
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2010 Microchip Technology Inc.
DS39774D-page 405
PIC18F85J11 FAMILY
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
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Device: PIC18F85J11 Family
Literature Number: DS39774D
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39774D-page 406
2010 Microchip Technology Inc.
PIC18F85J11 FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
XXX
Device
Temperature
Range
Package
Pattern
Device
PIC18F63J11/64J11/65J11(1),
PIC18F83J11/84J11/85J11(1),
PIC18F63J11/64J11/65J11T(2),
PIC18F83J11/84J11/85J11T(2)
Temperature Range
I
= -40C to +85C (Industrial)
Package
PT
= TQFP (Thin Quad Flatpack)
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
2010 Microchip Technology Inc.
Examples:
a)
b)
PIC18F85J11-I/PT 301 = Industrial temp.,
TQFP package, QTP pattern #301.
PIC18F63J11T-I/PT = Tape and reel, Industrial
temp., TQFP package.
Note 1: F
2: T
= Standard Voltage Range
= In Tape and Reel
DS39774D-page 407
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01/05/10
DS39774D-page 408
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