PIC18F8723 Family
Data Sheet
64/80-Pin, 1-Mbit,
Enhanced Flash Microcontrollers
with 12-Bit A/D and nanoWatt Technology
© 2009 Microchip Technology Inc.
DS39894B
Note the following details of the code protection feature on Microchip devices:
•
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•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
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•
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•
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The Microchip name and logo, the Microchip logo, dsPIC,
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rfPIC and UNI/O are registered trademarks of Microchip
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Analog-for-the-Digital Age, Application Maestro, CodeGuard,
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ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
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Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39894B-page 2
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
64/80-Pin, 1-Mbit, Enhanced Flash Microcontrollers
with 12-Bit A/D and nanoWatt Technology
Peripheral Highlights:
Power-Managed Modes:
• 12-Bit, Up to 16-Channel Analog-to-Digital
Converter module (A/D):
- Auto-acquisition capability
- Conversion available during Sleep
• Two Master Synchronous Serial Port (MSSP)
modules supporting 2/3/4-Wire SPI (all four
modes) and I2C™ Master and Slave modes
• Two Capture/Compare/PWM (CCP) modules
• Three Enhanced Capture/Compare/PWM (ECCP)
modules:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
• Two Enhanced Addressable USART modules:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-wake-up on Start bit
- Auto-Baud Detect
• Dual Analog Comparators with Input Multiplexing
• High-Current Sink/Source 25 mA/25 mA
• Four Programmable External Interrupts
• Four Input Change Interrupts
•
•
•
•
•
•
•
Run: CPU on, Peripherals on
Idle: CPU off, Peripherals on
Sleep: CPU off, Peripherals off
Idle mode Currents Down to 15 μA Typical
Sleep Current Down to 0.2 μA Typical
Timer1 Oscillator: 1.8 μA, 32 kHz, 2V
Watchdog Timer: 2.1 μA
Special Microcontroller Features:
• C Compiler Optimized Architecture:
- Optional extended instruction set designed to
optimize re-entrant code
• 100,000 Erase/Write Cycle Enhanced Flash
Program Memory Typical
• 1,000,000 Erase/Write Cycle Data EEPROM
Memory Typical
• Flash/Data EEPROM Retention: 100 Years Typical
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™
(ICSP™) via Two Pins
• In-Circuit Debug (ICD) via Two Pins
• Wide Operating Voltage Range: 2.0V to 5.5V
• Fail-Safe Clock Monitor
• Two-Speed Oscillator Start-up
• nanoWatt Technology
Device
Data Memory
Flash # Single-Word SRAM EEPROM
(bytes) Instructions (bytes) (bytes)
I/O
MSSP
CCP/
12-Bit
ECCP
A/D (ch)
(PWM)
SPI
Master
I2C™
External
Bus
Program Memory
This document is supplemented by the
“PIC18F8722
Family
Data
Sheet”
(DS39646). See Section 1.0 “Device
Overview”.
Timers
8/16-Bit
Note:
Comparators
• Address Capability of Up to 2 Mbytes
• 8-Bit or 16-Bit Interface
• 8, 12, 16 and 20-Bit Address modes
EUSART
External Memory Interface:
PIC18F6628
96K
49152
3936
1024
54
12
2/3
2
Y
Y
2
2
2/3
N
PIC18F6723
128K
65536
3936
1024
54
12
2/3
2
Y
Y
2
2
2/3
N
PIC18F8628
96K
49152
3936
1024
70
16
2/3
2
Y
Y
2
2
2/3
Y
PIC18F8723
128K
65536
3936
1024
70
16
2/3
2
Y
Y
2
2
2/3
Y
© 2009 Microchip Technology Inc.
DS39894B-page 3
PIC18F8723
Pin Diagrams
RD7/PSP7/SS2
RD6/PSP6/SCK2/SCL2
RD5/PSP5/SDI2/SDA2
RD4/PSP4/SDO2
RD3/PSP3
RD2/PSP2
RD1/PSP1
VSS
VDD
RD0/PSP0
RE7/ECCP2(1)/P2A(1)
RE6/P1B
RE5/P1C
RE4/P3B
RE2/CS/P2B
RE3/P3C
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RE1/WR/P2C
RE0/RD/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RF4/AN9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RF3/AN8
RF2/AN7/C1OUT
15
16
RG2/RX2/DT2
RG3/CCP4/P3D
RG5/MCLR/VPP
RG4/CCP5/P1D
VSS
VDD
RF7/SS1
RF6/AN11
RF5/AN10/CVREF
48
47
46
45
44
43
42
41
40
PIC18F6628
PIC18F6723
39
38
37
36
35
34
33
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
RB7/KBI3/PGD
RC5/SDO1
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
Note 1:
DS39894B-page 4
RC7/RX1/DT1
RC6/TX1/CK1
RC0/T1OSO/T13CKI
RA4/T0CKI
RC1/T1OSI/ECCP2(1)/P2A(1)
RA5/AN4/HLVDIN
VDD
VSS
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
AVSS
RA3/AN3/VREF+
AVDD
RF0/AN5
RF1/AN6/C2OUT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit.
© 2009 Microchip Technology Inc.
PIC18F8723
Pin Diagrams (Continued)
RH1/A17
RH0/A16
RE2/AD10/CS/P2B
RE3/AD11/P3C(2)
RE4/AD12/P3B(2)
RE5/AD13/P1C(2)
RE6/AD14/P1B(2)
RE7/AD15/ECCP2(1)/P2A(1)
RD0/AD0/PSP0
VDD
VSS
RD1/AD1/PSP1
RD2/AD2/PSP2
RD3/AD3/PSP3
RD4/AD4/PSP4/SDO2
RD5/AD5/PSP5/SDI2/SDA2
RD6/AD6/PSP6/SCK2/SCL2
RD7/AD7/PSP7/SS2
RJ0/ALE
RJ1/OE
80-Pin TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2/A18
RH3/A19
RE1/AD9/WR/P2C
RE0/AD8/RD/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG5/MCLR/VPP
RG4/CCP5/P1D
VSS
VDD
RF7/SS1
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RH7/AN15/P1B(2)
RH6/AN14/P1C(2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
PIC18F8628
PIC18F8723
44
43
42
41
RJ2/WRL
RJ3/WRH
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/ECCP2(1)/P2A(1)
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
RB7/KBI3/PGD
RC5/SDO1
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RJ7/UB
RJ6/LB
Note 1:
2:
RC0/T1OSO/T13CKI
RC6/TX1/CK1
RC7/RX1/DT1
RJ4/BA0
RJ5/CE
RA5/AN4/HLVDIN
RA4/T0CKI
RC1/T1OSI/ECCP2(1)/P2A(1)
RA1/AN1
RA0/AN0
VSS
VDD
RF1/AN6/C2OUT
RF0/AN5
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RH5/AN13/P3B(2)
RH4/AN12/P3C(2)
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit and Processor mode settings.
P1B, P1C, P3B and P3C pin placement is determined by the ECCPMX Configuration bit.
© 2009 Microchip Technology Inc.
DS39894B-page 5
PIC18F8723
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 31
3.0 Special Features of the CPU ...................................................................................................................................................... 41
4.0 Electrical Characteristics ........................................................................................................................................................... 43
5.0 Packaging Information................................................................................................................................................................ 49
Appendix A: Revision History............................................................................................................................................................... 51
Appendix B: Device Differences........................................................................................................................................................... 51
Appendix C: Conversion Considerations ............................................................................................................................................. 52
Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................... 52
Appendix E: Migration From Mid-Range to Enhanced Devices ........................................................................................................... 53
Appendix F: Migration From High-End to Enhanced Devices.............................................................................................................. 53
Index .................................................................................................................................................................................................... 55
The Microchip Web Site ....................................................................................................................................................................... 57
Customer Change Notification Service ................................................................................................................................................ 57
Customer Support ................................................................................................................................................................................ 57
Reader Response ................................................................................................................................................................................ 58
PIC18F8723 family Product Identification System ............................................................................................................................... 59
DS39894B-page 6
© 2009 Microchip Technology Inc.
PIC18F8723
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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© 2009 Microchip Technology Inc.
DS39894B-page 7
PIC18F8723
NOTES:
DS39894B-page 8
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC18F6628
• PIC18LF6628
• PIC18F6723
• PIC18LF6723
• PIC18F8628
• PIC18LF8628
• PIC18F8723
• PIC18LF8723
Note: This data sheet documents only the devices’
features and specifications that are in addition
to the features and specifications of the
PIC18F8722 family devices. For information
on the features and specifications shared by
the PIC18F8723 family and PIC18F8722 family devices, see the “PIC18F8722 Family Data
Sheet” (DS39646).
The PIC18F8723 family of devices offers the
advantages of all PIC18 microcontrollers – namely, high
computational performance at an economical price –
with the addition of high-endurance, Enhanced Flash
program memory. In addition to these features, the
PIC18F8723 introduces design enhancements that
make these microcontrollers a logical choice for many
high-performance, power-sensitive applications.
1.1
Special Features
• 12-Bit A/D Converter: The PIC18F8723 family
implements a 12-bit A/D Converter. A/D Converters
in both families incorporate programmable acquisition time. This allows for a channel to be selected
and a conversion to be initiated, without waiting for
a sampling period and thus, reducing code
overhead.
© 2009 Microchip Technology Inc.
1.2
Details on Individual Family
Members
Devices in the PIC18F8723 family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in the
following ways:
• Flash program memory (96 Kbytes for
PIC18FX628 devices and 128 Kbytes for
PIC18FX723).
• A/D channels (12 for PIC18F6628/6723 devices
and 16 for PIC18F8628/8723 devices).
• I/O ports (seven bidirectional ports on
PIC18F6628/6723 devices and nine bidirectional
ports on PIC18F8628/8723 devices).
• External Memory Bus, configurable for 8 and
16-bit operation
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Like all Microchip PIC18 devices, members of the
PIC18F8723 family are available as both standard and
low-voltage devices. Standard devices with Enhanced
Flash memory, designated with an “F” in the part
number (such as PIC18F6628), accommodate an
operating VDD range of 4.2V to 5.5V. Low-voltage
parts, designated by “LF” (such as PIC18LF6628),
function over an extended VDD range of 2.0V to 5.5V.
DS39894B-page 9
PIC18F8723 FAMILY
TABLE 1-1:
DEVICE FEATURES
Features
PIC18F6628
PIC18F6723
PIC18F8628
PIC18F8723
Operating Frequency
DC – 40 MHz
DC – 40 MHz
DC – 40 MHz
DC – 40 MHz
96K
128K
96K
128K
Program Memory (Instructions)
49152
65536
49152
65536
Data Memory (Bytes)
3936
3936
3936
3936
Data EEPROM Memory (Bytes)
1024
1024
1024
1024
28
28
29
29
Ports A, B, C, D, E, F, G
Ports A, B, C, D, E, F, G
Ports A, B, C, D, E,
F, G, H, J
Ports A, B, C, D, E,
F, G, H, J
Timers
5
5
5
5
Capture/Compare/PWM
Modules
2
2
2
2
Enhanced Capture/Compare/
PWM Modules
3
3
3
3
Program Memory (Bytes)
Interrupt Sources
I/O Ports
Enhanced USART
Serial Communications
2
2
2
2
MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
Parallel Communications (PSP)
Yes
Yes
Yes
Yes
12-Bit Analog-to-Digital Module
12 Input Channels
12 Input Channels
16 Input Channels
16 Input Channels
Resets (and Delays)
POR, BOR,
POR, BOR,
POR, BOR,
POR, BOR,
RESET Instruction,
RESET Instruction,
RESET Instruction,
RESET Instruction,
Stack Full, Stack
Stack Full, Stack
Stack Full, Stack
Stack Full, Stack
Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST),
MCLR (optional), WDT MCLR (optional), WDT MCLR (optional), WDT MCLR (optional), WDT
Programmable
High/Low-Voltage Detect
Yes
Yes
Yes
Yes
Programmable Brown-out
Reset
Yes
Yes
Yes
Yes
75 Instructions;
83 with Extended
Instruction Set Enabled
75 Instructions;
83 with Extended
Instruction Set Enabled
75 Instructions;
83 with Extended
Instruction Set Enabled
75 Instructions;
83 with Extended
Instruction Set Enabled
64-Pin TQFP
64-Pin TQFP
80-Pin TQFP
80-Pin TQFP
Instruction Set
Packages
DS39894B-page 10
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
FIGURE 1-1:
PIC18F6628/6723 (64-PIN) BLOCK DIAGRAM
Data Bus
Table Pointer
20
Address Latch
PCU PCH PCL
Program Counter
12
Data Address
31 Level Stack
4
BSR
Address Latch
Program Memory
(48/64/96/128
Kbytes)
STKPTR
Instruction Bus
PORTB
RB0:RB7(1)
4
Access
Bank
12
FSR0
FSR1
FSR2
12
Data Latch
8
RA0:RA7(1)
Data Memory
(3.9 Kbytes)
PCLATU PCLATH
21
PORTA
Data Latch
8
8
inc/dec logic
PORTC
RC0:RC7(1)
inc/dec
logic
Table Latch
Address
Decode
ROM Latch
PORTD
RD0:RD7(1)
IR
Instruction
Decode and
Control
8
State Machine
Control Signals
PRODH PRODL
8 x 8 Multiply
3
Internal
Oscillator
Block
OSC1(3)
OSC2(3)
T1OSI
INTRC
Oscillator
T1OSO
8 MHz
Oscillator
MCLR(2)
VDD, VSS
Power-up
Timer
Single-Supply
Programming
In-Circuit
Debugger
8
BITOP
W
8
8
8
Oscillator
Start-up Timer
Power-on
Reset
8
PORTF
8
RF0:RF7(1)
ALU
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
Precision
Band Gap
Reference
8
PORTG
RG0:RG5(1,2)
BOR
HLVD
ADC
12-Bit
Timer0
Timer1
Timer2
Timer3
Timer4
ECCP1
ECCP2
ECCP3
CCP4
CCP5
EUSART1
EUSART2
Note
PORTE
RE0:RE7(1)
Comparators
MSSP1
MSSP2
1:
See Table 1-2 for I/O port pin descriptions.
2:
RG5 is only available when MCLR functionality is disabled.
3:
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as
digital I/O. For additional information, refer to Section 2.0 “Oscillator Configurations” of the “PIC18F8722 Family
Data Sheet” (DS39646).
© 2009 Microchip Technology Inc.
DS39894B-page 11
PIC18F8723 FAMILY
FIGURE 1-2:
PIC18F8628/8723 (80-PIN) BLOCK DIAGRAM
Data Bus
Table Pointer
8
inc/dec logic
21
Address Latch
PCU PCH PCL
Program Counter
31 Level Stack
System Bus Interface
PORTB
RB0:RB7(1)
12
Data Address
4
Address Latch
Program Memory
(48/64/96/128
Kbytes)
RA0:RA7(1)
Data Memory
(3.9 Kbytes)
PCLATU PCLATH
20
PORTA
Data Latch
8
12
BSR
STKPTR
4
PORTC
Access
Bank
FSR0
FSR1
FSR2
RC0:RC7(1)
12
Data Latch
inc/dec
logic
8
Table Latch
PORTD
RD0:RD7(1)
Address
Decode
ROM Latch
Instruction Bus
PORTE
IR
RE0:RE7(1)
AD15:AD0, A19:A16
(Multiplexed with PORTD,
PORTE and PORTH)
8
3
Internal
Oscillator
Block
OSC2(3)
T1OSI
INTRC
Oscillator
T1OSO
8 MHz
Oscillator
8
W
8
Oscillator
Start-up Timer
PORTH
8
Watchdog
Timer
RH0:RH7(1)
Precision
Band Gap
Reference
Brown-out
Reset
Fail-Safe
Clock Monitor
ADC
12-bit
Timer0
Timer1
Timer2
Timer3
Timer4
ECCP1
ECCP2
ECCP3
CCP4
CCP5
EUSART1
EUSART2
1:
PORTG
8
BOR
HLVD
Note
8
ALU
Power-on
Reset
In-Circuit
Debugger
VDD, VSS
8
RG0:RG5(1,2)
Power-up
Timer
Single-Supply
Programming
MCLR(2)
RF0:RF7(1)
8 x 8 Multiply
BITOP
8
OSC1(3)
PORTF
PRODH PRODL
Instruction
Decode &
Control
State Machine
Control Signals
PORTJ
RJ0:RJ7(1)
Comparators
MSSP1
MSSP2
See Table 1-3 for I/O port pin descriptions.
2:
RG5 is only available when MCLR functionality is disabled.
3:
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as
digital I/O. For additional information, refer to Section 2.0 “Oscillator Configurations” of the “PIC18F8722 Family Data
Sheet” (DS39646).
DS39894B-page 12
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-2:
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
TQFP
Buffer
Type
I
I
ST
ST
7
RG5/MCLR/VPP
RG5
MCLR
P
VPP
OSC1/CLKI/RA7
OSC1
Pin
Type
39
I
CLKI
I
RA7
I/O
OSC2/CLKO/RA6
OSC2
Description
Master Clear (input) or programming voltage (input).
Digital input.
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS
otherwise.
CMOS
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
TTL
General purpose I/O pin.
ST
40
O
—
CLKO
O
—
RA6
I/O
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
= I2C/SMBus input buffer
P
= Power
I2C™
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39894B-page 13
PIC18F8723 FAMILY
TABLE 1-2:
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
24
RA1/AN1
RA1
AN1
23
RA2/AN2/VREFRA2
AN2
VREF-
22
RA3/AN3/VREF+
RA3
AN3
VREF+
21
RA4/T0CKI
RA4
T0CKI
28
RA5/AN4/HLVDIN
RA5
AN4
HLVDIN
27
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
I/O
I
ST
ST
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Timer0 external clock input.
Digital I/O.
Analog input 4.
High/Low-Voltage Detect input.
RA6
See the OSC2/CLKO/RA6 pin.
RA7
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
= I2C/SMBus input buffer
P
= Power
I2C™
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
DS39894B-page 14
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-2:
Pin Name
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
INT0
FLT0
48
RB1/INT1
RB1
INT1
47
RB2/INT2
RB2
INT2
46
RB3/INT3
RB3
INT3
45
RB4/KBI0
RB4
KBI0
44
RB5/KBI1/PGM
RB5
KBI1
PGM
43
RB6/KBI2/PGC
RB6
KBI2
PGC
42
RB7/KBI3/PGD
RB7
KBI3
PGD
37
I/O
I
I
TTL
ST
ST
Digital I/O.
External interrupt 0.
PWM Fault input for ECCPx.
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
I/O
I
TTL
ST
Digital I/O.
External interrupt 3.
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
= I2C/SMBus input buffer
P
= Power
I2C™
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39894B-page 15
PIC18F8723 FAMILY
TABLE 1-2:
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
30
RC1/T1OSI/ECCP2/
P2A
RC1
T1OSI
ECCP2(1)
29
P2A(1)
RC2/ECCP1/P1A
RC2
ECCP1
I/O
O
I
ST
—
ST
I/O
I
I/O
ST
CMOS
ST
O
—
I/O
I/O
ST
ST
O
—
Digital I/O.
Enhanced Capture 1 input/Compare 1 output/
PWM1 output.
ECCP1 PWM output A.
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
ST
—
Digital I/O.
SPI data out.
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Digital I/O.
Timer1 oscillator input.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2 PWM output A.
33
P1A
RC3/SCK1/SCL1
RC3
SCK1
SCL1
34
RC4/SDI1/SDA1
RC4
SDI1
SDA1
35
RC5/SDO1
RC5
SDO1
36
RC6/TX1/CK1
RC6
TX1
CK1
31
RC7/RX1/DT1
RC7
RX1
DT1
32
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
= I2C/SMBus input buffer
P
= Power
I2C™
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
DS39894B-page 16
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-2:
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTD is a bidirectional I/O port.
RD0/PSP0
RD0
PSP0
58
RD1/PSP1
RD1
PSP1
55
RD2/PSP2
RD2
PSP2
54
RD3/PSP3
RD3
PSP3
53
RD4/PSP4/SDO2
RD4
PSP4
SDO2
52
RD5/PSP5/SDI2/
SDA2
RD5
PSP5
SDI2
SDA2
51
RD6/PSP6/SCK2/
SCL2
RD6
PSP6
SCK2
SCL2
50
RD7/PSP7/SS2
RD7
PSP7
SS2
49
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
SPI data out.
I/O
I/O
I
I/O
ST
TTL
ST
I2C/SMB
Digital I/O.
Parallel Slave Port data.
SPI data in.
I2C™ data I/O.
I/O
I/O
I/O
I/O
ST
TTL
ST
I2C/SMB
Digital I/O.
Parallel Slave Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
SPI slave select input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
= I2C/SMBus input buffer
P
= Power
I2C™
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39894B-page 17
PIC18F8723 FAMILY
TABLE 1-2:
Pin Name
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTE is a bidirectional I/O port.
RE0/RD/P2D
RE0
RD
P2D
2
RE1/WR/P2C
RE1
WR
P2C
1
RE2/CS/P2B
RE2
CS
P2B
64
RE3/P3C
RE3
P3C
63
RE4/P3B
RE4
P3B
62
RE5/P1C
RE5
P1C
61
RE6/P1B
RE6
P1B
60
RE7/ECCP2/P2A
RE7
ECCP2(2)
59
P2A(2)
I/O
I
O
ST
TTL
—
Digital I/O.
Read control for Parallel Slave Port.
ECCP2 PWM output D.
I/O
I
O
ST
TTL
—
Digital I/O.
Write control for Parallel Slave Port.
ECCP2 PWM output C.
I/O
I
O
ST
TTL
—
Digital I/O.
Chip select control for Parallel Slave Port.
ECCP2 PWM output B.
I/O
O
ST
—
Digital I/O.
ECCP3 PWM output C.
I/O
O
ST
—
Digital I/O.
ECCP3 PWM output B.
I/O
O
ST
—
Digital I/O.
ECCP1 PWM output C.
I/O
O
ST
—
Digital I/O.
ECCP1 PWM output B.
I/O
I/O
ST
ST
O
—
Digital I/O.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2 PWM output A.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
= I2C/SMBus input buffer
P
= Power
I2C™
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
DS39894B-page 18
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-2:
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTF is a bidirectional I/O port.
RF0/AN5
RF0
AN5
18
RF1/AN6/C2OUT
RF1
AN6
C2OUT
17
RF2/AN7/C1OUT
RF2
AN7
C1OUT
16
RF3/AN8
RF3
AN8
15
RF4/AN9
RF4
AN9
14
RF5/AN10/CVREF
RF5
AN10
CVREF
13
RF6/AN11
RF6
AN11
12
RF7/SS1
RF7
SS1
11
I/O
I
ST
Analog
Digital I/O.
Analog input 5.
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 6.
Comparator 2 output.
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 7.
Comparator 1 output.
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 10.
Comparator reference voltage output.
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
I/O
I
ST
TTL
Digital I/O.
SPI slave select input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
= I2C/SMBus input buffer
P
= Power
I2C™
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39894B-page 19
PIC18F8723 FAMILY
TABLE 1-2:
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTG is a bidirectional I/O port.
RG0/ECCP3/P3A
RG0
ECCP3
3
P3A
RG1/TX2/CK2
RG1
TX2
CK2
4
RG2/RX2/DT2
RG2
RX2
DT2
5
RG3/CCP4/P3D
RG3
CCP4
P3D
6
RG4/CCP5/P1D
RG4
CCP5
P1D
8
I/O
I/O
ST
ST
O
—
Digital I/O.
Enhanced Capture 3 input/Compare 3 output/
PWM3 output.
ECCP3 PWM output A.
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM output D.
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM output D.
See RG5/MCLR/VPP pin.
RG5
VSS
9, 25, 41, 56
P
—
Ground reference for logic and I/O pins.
VDD
10, 26, 38, 57
P
—
Positive supply for logic and I/O pins.
AVSS
20
P
—
Ground reference for analog modules.
AVDD
19
P
—
Positive supply for analog modules.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
= I2C/SMBus input buffer
P
= Power
I2C™
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
DS39894B-page 20
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-3:
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
TQFP
RG5/MCLR/VPP
RG5
MCLR
I
I
ST
ST
P
49
I
CLKI
I
RA7
OSC2/CLKO/RA6
OSC2
Buffer
Type
9
VPP
OSC1/CLKI/RA7
OSC1
Pin
Type
I/O
Description
Master Clear (input) or programming voltage (input).
Digital input.
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS
otherwise.
CMOS
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
TTL
General purpose I/O pin.
ST
50
O
—
CLKO
O
—
RA6
I/O
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input
CMOS
= CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog
= Analog input
I
= Input
O
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2009 Microchip Technology Inc.
DS39894B-page 21
PIC18F8723 FAMILY
TABLE 1-3:
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
30
RA1/AN1
RA1
AN1
29
RA2/AN2/VREFRA2
AN2
VREF-
28
RA3/AN3/VREF+
RA3
AN3
VREF+
27
RA4/T0CKI
RA4
T0CKI
34
RA5/AN4/HLVDIN
RA5
AN4
HLVDIN
33
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
I/O
I
ST
ST
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Timer0 external clock input.
Digital I/O.
Analog input 4.
High/Low-Voltage Detect input.
RA6
See the OSC2/CLKO/RA6 pin.
RA7
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
CMOS
= CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog
= Analog input
I
= Input
O
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
DS39894B-page 22
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-3:
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
INT0
FLT0
58
RB1/INT1
RB1
INT1
57
RB2/INT2
RB2
INT2
56
RB3/INT3/ECCP2/P2A
RB3
INT3
ECCP2(1)
55
P2A(1)
RB4/KBI0
RB4
KBI0
54
RB5/KBI1/PGM
RB5
KBI1
PGM
53
RB6/KBI2/PGC
RB6
KBI2
PGC
52
RB7/KBI3/PGD
RB7
KBI3
PGD
47
I/O
I
I
TTL
ST
ST
Digital I/O.
External interrupt 0.
PWM Fault input for ECCPx.
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
I/O
I
O
TTL
ST
—
O
—
Digital I/O.
External interrupt 3.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2 PWM output A.
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input
CMOS
= CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog
= Analog input
I
= Input
O
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2009 Microchip Technology Inc.
DS39894B-page 23
PIC18F8723 FAMILY
TABLE 1-3:
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
36
RC1/T1OSI/ECCP2/
P2A
RC1
T1OSI
ECCP2(2)
35
P2A(2)
RC2/ECCP1/P1A
RC2
ECCP1
I/O
O
I
ST
—
ST
I/O
I
I/O
ST
CMOS
ST
O
—
I/O
I/O
ST
ST
O
—
Digital I/O.
Enhanced Capture 1 input/Compare 1 output/
PWM1 output.
ECCP1 PWM output A.
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
ST
—
Digital I/O.
SPI data out.
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Digital I/O.
Timer1 oscillator input.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2 PWM output A.
43
P1A
RC3/SCK1/SCL1
RC3
SCK1
SCL1
44
RC4/SDI1/SDA1
RC4
SDI1
SDA1
45
RC5/SDO1
RC5
SDO1
46
RC6/TX1/CK1
RC6
TX1
CK1
37
RC7/RX1/DT1
RC7
RX1
DT1
38
Legend: TTL = TTL compatible input
CMOS
= CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog
= Analog input
I
= Input
O
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
DS39894B-page 24
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-3:
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTD is a bidirectional I/O port.
RD0/AD0/PSP0
RD0
AD0
PSP0
72
RD1/AD1/PSP1
RD1
AD1
PSP1
69
RD2/AD2/PSP2
RD2
AD2
PSP2
68
RD3/AD3/PSP3
RD3
AD3
PSP3
67
RD4/AD4/PSP4/SDO2
RD4
AD4
PSP4
SDO2
66
RD5/AD5/PSP5/
SDI2/SDA2
RD5
AD5
PSP5
SDI2
SDA2
65
RD6/AD6/PSP6/
SCK2/SCL2
RD6
AD6
PSP6
SCK2
SCL2
64
RD7/AD7/PSP7/SS2
RD7
AD7
PSP7
SS2
63
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 0.
Parallel Slave Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 1.
Parallel Slave Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 2.
Parallel Slave Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 3.
Parallel Slave Port data.
I/O
I/O
I/O
O
ST
TTL
TTL
—
Digital I/O.
External memory address/data 4.
Parallel Slave Port data.
SPI data out.
I/O
I/O
I/O
I
I/O
ST
TTL
TTL
ST
I2C/SMB
Digital I/O.
External memory address/data 5.
Parallel Slave Port data.
SPI data in.
I2C™ data I/O.
I/O
I/O
I/O
I/O
I/O
ST
TTL
TTL
ST
I2C/SMB
Digital I/O.
External memory address/data 6.
Parallel Slave Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
I/O
I/O
I
ST
TTL
TTL
TTL
Digital I/O.
External memory address/data 7.
Parallel Slave Port data.
SPI slave select input.
Legend: TTL = TTL compatible input
CMOS
= CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog
= Analog input
I
= Input
O
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2009 Microchip Technology Inc.
DS39894B-page 25
PIC18F8723 FAMILY
TABLE 1-3:
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTE is a bidirectional I/O port.
RE0/AD8/RD/P2D
RE0
AD8
RD
P2D
4
RE1/AD9/WR/P2C
RE1
AD9
WR
P2C
3
RE2/AD10/CS/P2B
RE2
AD10
CS
P2B
78
RE3/AD11/P3C
RE3
AD11
P3C(4)
77
RE4/AD12/P3B
RE4
AD12
P3B(4)
76
RE5/AD13/P1C
RE5
AD13
P1C(4)
75
RE6/AD14/P1B
RE6
AD14
P1B(4)
74
RE7/AD15/ECCP2/
P2A
RE7
AD15
ECCP2(3)
73
P2A(3)
I/O
I/O
I
O
ST
TTL
TTL
—
Digital I/O.
External memory address/data 8.
Read control for Parallel Slave Port.
ECCP2 PWM output D.
I/O
I/O
I
O
ST
TTL
TTL
—
Digital I/O.
External memory address/data 9.
Write control for Parallel Slave Port.
ECCP2 PWM output C.
I/O
I/O
I
O
ST
TTL
TTL
—
Digital I/O.
External memory address/data 10.
Chip select control for Parallel Slave Port.
ECCP2 PWM output B.
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 11.
ECCP3 PWM output C.
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 12.
ECCP3 PWM output B.
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 13.
ECCP1 PWM output C.
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 14.
ECCP1 PWM output B.
I/O
I/O
I/O
ST
TTL
ST
O
—
Digital I/O.
External memory address/data 15.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2 PWM output A.
Legend: TTL = TTL compatible input
CMOS
= CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog
= Analog input
I
= Input
O
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
DS39894B-page 26
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-3:
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTF is a bidirectional I/O port.
RF0/AN5
RF0
AN5
24
RF1/AN6/C2OUT
RF1
AN6
C2OUT
23
RF2/AN7/C1OUT
RF2
AN7
C1OUT
18
RF3/AN8
RF3
AN8
17
RF4/AN9
RF4
AN9
16
RF5/AN10/CVREF
RF5
AN10
CVREF
15
RF6/AN11
RF6
AN11
14
RF7/SS1
RF7
SS1
13
I/O
I
ST
Analog
Digital I/O.
Analog input 5.
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 6.
Comparator 2 output.
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 7.
Comparator 1 output.
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 10.
Comparator reference voltage output.
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
I/O
I
ST
TTL
Digital I/O.
SPI slave select input.
Legend: TTL = TTL compatible input
CMOS
= CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog
= Analog input
I
= Input
O
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2009 Microchip Technology Inc.
DS39894B-page 27
PIC18F8723 FAMILY
TABLE 1-3:
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTG is a bidirectional I/O port.
RG0/ECCP3/P3A
RG0
ECCP3
5
P3A
RG1/TX2/CK2
RG1
TX2
CK2
6
RG2/RX2/DT2
RG2
RX2
DT2
7
RG3/CCP4/P3D
RG3
CCP4
P3D
8
RG4/CCP5/P1D
RG4
CCP5
P1D
10
RG5
I/O
I/O
ST
ST
O
—
Digital I/O.
Enhanced Capture 3 input/Compare 3 output/
PWM3 output.
ECCP3 PWM output A.
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM output D.
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM output D.
See RG5/MCLR/VPP pin.
Legend: TTL = TTL compatible input
CMOS
= CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog
= Analog input
I
= Input
O
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
DS39894B-page 28
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-3:
Pin Name
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTH is a bidirectional I/O port.
RH0/A16
RH0
A16
79
RH1/A17
RH1
A17
80
RH2/A18
RH2
A18
1
RH3/A19
RH3
A19
2
RH4/AN12/P3C
RH4
AN12
P3C(5)
22
RH5/AN13/P3B
RH5
AN13
P3B(5)
21
RH6/AN14/P1C
RH6
AN14
P1C(5)
20
RH7/AN15/P1B
RH7
AN15
P1B(5)
19
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 16.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 17.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 18.
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 19.
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 12.
ECCP3 PWM output C.
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 13.
ECCP3 PWM output B.
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 14.
ECCP1 PWM output C.
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 15.
ECCP1 PWM output B.
Legend: TTL = TTL compatible input
CMOS
= CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog
= Analog input
I
= Input
O
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2009 Microchip Technology Inc.
DS39894B-page 29
PIC18F8723 FAMILY
TABLE 1-3:
Pin Name
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
ALE
62
RJ1/OE
RJ1
OE
61
RJ2/WRL
RJ2
WRL
60
RJ3/WRH
RJ3
WRH
59
RJ4/BA0
RJ4
BA0
39
RJ5/CE
RJ4
CE
40
RJ6/LB
RJ6
LB
41
RJ7/UB
RJ7
UB
42
I/O
O
ST
—
Digital I/O.
External memory address latch enable.
I/O
O
ST
—
Digital I/O.
External memory output enable.
I/O
O
ST
—
Digital I/O.
External memory write low control.
I/O
O
ST
—
Digital I/O.
External memory write high control.
I/O
O
ST
—
Digital I/O.
External memory byte address 0 control.
I/O
O
ST
—
Digital I/O
External memory chip enable control.
I/O
O
ST
—
Digital I/O.
External memory low byte control.
I/O
O
ST
—
Digital I/O.
External memory high byte control.
VSS
11, 31, 51, 70
P
—
Ground reference for logic and I/O pins.
VDD
12, 32, 48, 71
P
—
Positive supply for logic and I/O pins.
AVSS
26
P
—
Ground reference for analog modules.
AVDD
25
P
—
Positive supply for analog modules.
Legend: TTL = TTL compatible input
CMOS
= CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog
= Analog input
I
= Input
O
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
DS39894B-page 30
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
2.0
12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has
12 inputs for the 64-pin devices (PIC18F6628/6723) and
16 for the 80-pin devices (PIC18F8628/8723). This
module allows conversion of an analog input signal to a
corresponding 12-bit digital number.
The ADCON0 register, shown in Register 2-1, controls
the operation of the A/D module. The ADCON1
register, shown in Register 2-2, configures the
functions of the port pins. The ADCON2 register,
shown in Register 2-3, configures the A/D clock
source, programmed acquisition time and justification.
The module has five registers:
•
•
•
•
•
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
A/D Control Register 2 (ADCON2)
REGISTER 2-1:
ADCON0: A/D CONTROL REGISTER 0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-2
CHS3:CHS0: Analog Channel Select bits
0000 = Channel 0 (AN0)
0001 = Channel 1 (AN1)
0010 = Channel 2 (AN2)
0011 = Channel 3 (AN3)
0100 = Channel 4 (AN4)
0101 = Channel 5 (AN5)
0110 = Channel 6 (AN6)
0111 = Channel 7 (AN7)
1000 = Channel 8 (AN8)
1001 = Channel 9 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12)(1,2)
1101 = Channel 13 (AN13)(1,2)
1110 = Channel 14 (AN14)(1,2)
1111 = Channel 15 (AN15)(1,2)
bit 1
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0
ADON: A/D On bit
1 = A/D Converter module is enabled
0 = A/D Converter module is disabled
Note 1:
2:
x = Bit is unknown
These channels are not implemented on PIC18F6628/6723 devices.
Performing a conversion on unimplemented channels will return a floating input measurement.
© 2009 Microchip Technology Inc.
DS39894B-page 31
PIC18F8723 FAMILY
REGISTER 2-2:
ADCON1: A/D CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
VCFG1:VCFG0: Voltage Reference Configuration bits
A/D VREF-
00
AVDD
AVSS
01
External VREF+
AVSS
10
AVDD
External VREF-
11
External VREF+
External VREF-
PCFG
AN14(1)
AN13(1)
AN12(1)
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PCFG3:PCFG0: A/D Port Configuration Control bits:
AN15(1)
bit 3-0
A/D VREF+
x = Bit is unknown
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
A = Analog input
Note 1:
DS39894B-page 32
D = Digital I/O
AN15 through AN12 are available only on PIC18F8628/8723 devices.
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
REGISTER 2-3:
ADCON2: A/D CONTROL REGISTER 2
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1:
x = Bit is unknown
If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
© 2009 Microchip Technology Inc.
DS39894B-page 33
PIC18F8723 FAMILY
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF-/CVREF pins.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D Converter can be
configured as an analog input or a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0) is cleared
and the A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 2-1.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 2-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1111
AN15(1)
1110
AN14(1)
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
VAIN
0011
(Input Voltage)
12-Bit
A/D
Converter
0010
0001
VCFG1:VCFG0
AVDD(2)
Reference
Voltage
VREF+
VREF-
0000
AN13(1)
AN12(1)
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
X0
X1
1X
0X
AVSS(2)
Note 1:
2:
Channels AN12 through AN15 are not available on PIC18F6628/6723 devices.
I/O pins have diode protection to VDD and VSS.
DS39894B-page 34
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
Wait for A/D conversion to complete by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
6.
7.
FIGURE 2-2:
The following steps should be followed to perform an A/D
conversion:
FIGURE 2-3:
FFEh
003h
002h
001h
4095 LSB
4095.5 LSB
4094 LSB
4094.5 LSB
3 LSB
2 LSB
000h
2.5 LSB
3.
4.
FFFh
0.5 LSB
2.
Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time (if required).
Start conversion:
• Set GO/DONE bit (ADCON0)
Digital Code Output
1.
A/D TRANSFER FUNCTION
1 LSB
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 2.1
“A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
5.
1.5 LSB
The value in the ADRESH:ADRESL registers is
unknown following Power-on and Brown-out Resets and
is not affected by any other Reset.
Analog Input Voltage
ANALOG INPUT MODEL
VDD
Rs
VAIN
Sampling
Switch
VT = 0.6V
ANx
RIC ≤ 1k
CPIN
5 pF
VT = 0.6V
SS
RSS
CHOLD = 25 pF
ILEAKAGE
±100 nA
VSS
Legend: CPIN
= Input Capacitance
VT
= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
various junctions
= Interconnect Resistance
RIC
= Sampling Switch
SS
= Sample/Hold Capacitance (from DAC)
CHOLD
RSS
= Sampling Switch Resistance
© 2009 Microchip Technology Inc.
VDD
6V
5V
4V
3V
2V
1
2 3
4
Sampling Switch (kΩ)
DS39894B-page 35
PIC18F8723 FAMILY
2.1
A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 2-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor, CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum
recommended impedance for analog sources is
2.5 kΩ. After the analog input channel is selected
(changed), the channel must be sampled for at least
the minimum acquisition time before starting a
conversion.
Note:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
≤
=
=
25 pF
2.5 kΩ
1/2 LSb
3V → Rss = 4 kΩ
85°C (system max.)
ACQUISITION TIME
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 2-2:
VHOLD
or
TC
Example 2-3 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 2-1:
TACQ
To calculate the minimum acquisition time, Equation 2-1
may be used. This equation assumes that 1/2 LSb error
is used (4096 steps for the 12-bit A/D). The 1/2 LSb error
is the maximum error allowed for the A/D to meet its
specified resolution.
A/D MINIMUM CHARGING TIME
=
(VREF – (VREF/4096)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
=
– (CHOLD)(RIC + RSS + RS) ln(1/4096)
EQUATION 2-3:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
=
TAMP + TC + TCOFF
TAMP
=
0.2 µs
TCOFF
=
(Temp – 25°C)(0.02 µs/°C)
(85°C – 25°C)(0.02 µs/°C)
1.2 µs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 µs.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/4096) µs
-(25 pF) (1 kΩ + 4 kΩ + 2.5 kΩ) ln(0.0002441) µs
1.56 µs
TACQ
=
0.2 µs + 1.56 μs + 1.2 µs
2.96 µs
DS39894B-page 36
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
2.2
Selecting and Configuring
Acquisition Time
2.3
Selecting the A/D Conversion
Clock
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option to use an
automatically determined acquisition time.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 13 TAD per 12-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
Acquisition time may be set with the ACQT2:ACQT0
bits (ADCON2), which provide a range of 2 to
20 TAD. When the GO/DONE bit is set, the A/D module
continues to sample the input for the selected acquisition time, then automatically begins a conversion.
Since the acquisition time is programmed, there may
be no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.
•
•
•
•
•
•
•
Manual
acquisition
is
selected
when
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than the
minimum TAD (see parameter 130 for more
information).
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal RC Oscillator
Table 2-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 2-1:
TAD vs. DEVICE OPERATING FREQUENCIES
Assumes TAD Min. = 0.8 μs
A/D Clock Source (TAD)
Note 1:
2:
Operation
ADCS2:ADCS0
Maximum FOSC
2 TOSC
000
2.50 MHz
4 TOSC
100
5.00 MHz
8 TOSC
001
10.00 MHz
16 TOSC
101
20.00 MHz
32 TOSC
010
40.00 MHz
64 TOSC
RC(1)
110
40.00 MHz
x11
1.00 MHz(2)
The RC source has a typical TAD time of 2.5 μs.
For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a FOSC
divider should be used instead; otherwise, the A/D accuracy specification may not be met.
© 2009 Microchip Technology Inc.
DS39894B-page 37
PIC18F8723 FAMILY
2.4
Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ADCS2:ADCS0 bits in
ADCON2 should be updated in accordance with the
clock source to be used. The ACQT2:ACQT0 bits do
not need to be adjusted as the ADCS2:ADCS0 bits
adjust the TAD time for the new clock speed. After entering the mode, an A/D acquisition or conversion may be
started. Once started, the device should continue to be
clocked by the same clock source until the conversion
has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
2.5
Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Analog conversion on pins configured as digital pins
can be performed. The voltage on the pin
will be accurately converted.
2: Analog levels on any pin defined as a digital input may cause the digital input buffer
to consume current out of the device’s
specification limits.
Operation in Sleep mode requires the A/D FRC clock to
be selected. If the ACQT2:ACQT0 bits are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry to Sleep mode. The IDLEN
bit (OSCCON) must have already been cleared
prior to starting the conversion.
DS39894B-page 38
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
2.6
A/D Conversions
After the A/D conversion is completed or aborted, a
2 TCY wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
Figure 2-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Note:
Figure 2-5 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the
ACQT2:ACQT0 bits are set to ‘010’ and a 4 TAD acquisition time has been selected before the conversion
starts.
2.7
Discharge
The discharge phase is used to initialize the value of
the holding capacitor. The array is discharged before
every sample. This feature helps to optimize the unity
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
FIGURE 2-4:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Code should wait at least 2 μs after
enabling the A/D before beginning an
acquisition and conversion cycle.
A/D CONVERSION TAD CYCLES (ACQT = 000, TACQ = 0)
TCY – TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13 TAD1
b11
b10
b9
b8
b7
b6
b3
b4
b5
b2
b1
b0
Conversion starts
Discharge
(typically 200 ns)
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input
A/D CONVERSION TAD CYCLES (ACQT = 010, TACQ = 4 TAD)
FIGURE 2-5:
TAD Cycles
TACQT Cycles
1
2
3
4
1
Automatic
Acquisition
Time
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
© 2009 Microchip Technology Inc.
2
b11
3
b10
4
b9
5
b8
6
b7
7
b6
8
b5
9
b4
10
b3
11
b2
12
b1
13
b0
TAD1
Discharge
(typically
200 ns)
Conversion starts
(Holding capacitor is disconnected)
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input
DS39894B-page 39
PIC18F8723 FAMILY
2.8
Use of the ECCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the ECCP2 module. This requires that the
CCP2M3:CCP2M0
bits
(CCP2CON)
be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion, and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the
TABLE 2-2:
Name
INTCON
desired location). The appropriate analog input channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected before the Special Event Trigger
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
REGISTERS ASSOCIATED WITH A/D OPERATION
Bit 7
Bit 6
GIE/GIEH PEIE/GIEL
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
(3)
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
(3)
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
(3)
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
(3)
PIR2
OSCFIF
CMIF
—
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
(3)
PIE2
OSCFIE
CMIE
—
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
(3)
IPR2
OSCFIP
CMIP
—
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
(3)
ADRESH
A/D Result Register High Byte
(3)
ADRESL
A/D Result Register Low Byte
(3)
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
(3)
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
(3)
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
(3)
TRISA
TRISA7(1)
TRISA6(1)
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
(3)
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
(3)
TRISH(2)
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
(3)
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: PORTA and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
2: These registers are not implemented on PIC18F6628/6723 devices.
3: For these Reset values, see the “PIC18F8722 Family Data Sheet” (DS39646).
DS39894B-page 40
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
3.0
SPECIAL FEATURES OF THE
CPU
Note:
3.1
For additional details on the Configuration
bits, refer to Section 25.1 “Configuration
Bits” in the “PIC18F8722 Family Data
Sheet” (DS39646). Device ID information
presented in this section is for the
PIC18F8723 family only.
Device ID Registers
The Device ID registers are “read-only” registers.
They identify the device type and revision to device
programmers and can be read by firmware using table
reads.
PIC18F8723 family devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These
include:
• Device ID Registers
TABLE 3-1:
DEVICE IDs
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
3FFFFEh DEVID1
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
xxxx xxxx(1)
3FFFFFh
DEVID2
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
xxxx xxxx(1)
Legend:
Note 1:
x = unknown
See Register 3-1 and Register 3-2 for DEVID values. DEVID registers are read-only and cannot be programmed by the
user.
File Name
© 2009 Microchip Technology Inc.
DS39894B-page 41
PIC18F8723 FAMILY
REGISTER 3-1:
DEVID1: DEVICE ID REGISTER 1 FOR PIC18F8723 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Read-only bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
bit 7-5
DEV2:DEV0: Device ID bits
See Register 3-2 for a complete listing.
bit 4-0
REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 3-2:
DEVID2: DEVICE ID REGISTER 2 FOR PIC18F8723 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
Legend:
R = Read-only bit
P = Programmable bit
-n = Value when device is unprogrammed
bit 7-0
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
DEV10:DEV3: Device ID bits
DS39894B-page 42
DEV10:DEV3
(DEVID2)
DEV2:DEV0
(DEVID1)
Device
0100 1001
110
PIC18F6628
0100 1010
000
PIC18F6723
0100 1001
111
PIC18F8628
0100 1010
001
PIC18F8723
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
4.0
ELECTRICAL CHARACTERISTICS
Note: Other than some basic data, this section documents only the PIC18F8723 family’s specifications that differ
from those of the PIC18F8722 family devices. For detailed information on the electrical specifications shared
by the PIC18F8723 family and PIC18F8722 family devices, see the “PIC18F8722 Family Data Sheet”
(DS39646).
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the RG5/MCLR/VPP pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the RG5/MCLR/
VPP pin, rather than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2009 Microchip Technology Inc.
DS39894B-page 43
PIC18F8723 FAMILY
FIGURE 4-1:
PIC18F8723 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
Voltage
5.0V
4.5V
PIC18F8723 Family
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
FMAX
Frequency
FMAX = 20 MHz in 8-Bit External Memory mode.
FMAX = 40 MHz in all other modes.
FIGURE 4-2:
PIC18F8723 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED)
6.0V
5.5V
Voltage
5.0V
PIC18F8723 Family
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
FMAX
Frequency
FMAX = 20 MHz in 8-Bit External Memory mode.
FMAX = 25 MHz in all other modes.
DS39894B-page 44
© 2009 Microchip Technology Inc.
PIC18F8723 FAMILY
FIGURE 4-3:
PIC18LF8723 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
Voltage
5.0V
PIC18LF8723 Family
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
FMAX
4 MHz
Frequency
In 8-Bit External Memory mode:
FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V;
FMAX = 25 MHz, if VDDAPPMIN > 4.2V.
In all other modes:
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz;
FMAX = 40 MHz, if VDDAPPMIN > 4.2V.
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
© 2009 Microchip Technology Inc.
DS39894B-page 45
PIC18F8723 FAMILY
TABLE 4-1:
Param
No.
A/D CONVERTER CHARACTERISTICS: PIC18F8723 FAMILY (INDUSTRIAL)
Sym
Characteristic
Min
Typ
Max
Units
Conditions
ΔVREF ≥ 3.0V
A01
NR
Resolution
—
—
12
bit
A03
EIL
Integral Linearity Error
—
