PIC18F87J11 FAMILY
64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers
Flexible Oscillator Structure:
Peripheral Highlights (continued):
• Four Crystal modes, Including High-Precision PLL
• Two External Clock modes, up to 48 MHz
• Internal Oscillator Block:
- Provides 8 user-selectable frequencies from
31 kHz to 8 MHz
- Provides a complete range of clock speeds,
from 31 kHz to 32 MHz when used with PLL
- User-tunable to compensate for frequency drift
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor (FSCM):
- Allows for safe shutdown if any clock stops
• 8-Bit Parallel Master Port/Enhanced Parallel Slave
Port (PMP/EPSP) with 16 Address Lines
• Dual Analog Comparators with Input Multiplexing
• 10-Bit, up to 15-Channel Analog-to-Digital Converter
module (A/D):
- Auto-acquisition capability
- Conversion available during Sleep
External Memory Bus (80-pin devices only):
• Address Capability of up to 2 Mbytes
• 8-Bit or 16-Bit Interface
• 12-Bit, 16-Bit and 20-Bit Addressing modes
Peripheral Highlights:
Special Microcontroller Features:
• High-Current Sink/Source 25 mA/25mA on PORTB
and PORTC
• Four Programmable External Interrupts
• Four Input Change Interrupts
• One 8/16-Bit Timer/Counter
• Two 8-Bit Timers/Counters
• Two 16-Bit Timers/Counters
• Two Capture/Compare/PWM (CCP) modules
• Three Enhanced Capture/Compare/PWM (ECCP)
modules:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
• Two Master Synchronous Serial Port (MSSP)
modules supporting 3-Wire SPI (all 4 modes) and
I2C™ Master and Slave modes
• Two Enhanced USART modules:
- Supports RS-485, RS-232 and LIN/J2602
- Auto-wake-up on Start bit
- Auto-Baud Detect
EUSART
Comparators
Timers
8/16-Bit
External Bus
PMP/EPSP
• Low-Power, High-Speed CMOS Flash Technology
• C Compiler Optimized Architecture for Re-Entrant
Code
• Power Management Features:
- Run: CPU on, peripherals on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
• Priority Levels for Interrupts
• Self-Programmable under Software Control
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™
(ICSP™) via Two Pins
• In-Circuit Debug (ICD) with 3 Breakpoints via Two Pins
• Operating Voltage Range of 2.0V to 3.6V
• 5.5V Tolerant Inputs (digital only pins)
• On-Chip 2.5V Regulator
• Flash Program Memory of 10000 Erase/Write Cycles
and 20-Year Data Retention
PIC18F66J11
64 kB
3904
52
11
2/3
2
Y
Y
2
2
2/3
N
Y
PIC18F66J16
96 kB
3904
52
11
2/3
2
Y
Y
2
2
2/3
N
Y
PIC18F67J11
128 kB
3904
52
11
2/3
2
Y
Y
2
2
2/3
N
Y
PIC18F86J11
64 kB
3904
68
15
2/3
2
Y
Y
2
2
2/3
Y
Y
PIC18F86J16
96 kB
3904
68
15
2/3
2
Y
Y
2
2
2/3
Y
Y
PIC18F87J11
128 kB
3904
68
15
2/3
2
Y
Y
2
2
2/3
Y
Y
Device
Flash
Program
Memory
(bytes)
SRAM
Data
Memory
(bytes)
2007-2012 Microchip Technology Inc.
MSSP
I/O
10-Bit CCP/ECCP
A/D (ch)
(PWM)
SPI
Master
I2C™
DS39778E-page 1
PIC18F87J11 FAMILY
Pin Diagrams
RD7/PMD7/SS2
RD6/PMD6/SCK2/SCL2
RD5/PMD5/SDI2/SDA2
RD4/PMD4/SDO2
RD3/PMD3
RD2/PMD2
RD1/PMD1
VSS
VDD
RE7/PMA9/ECCP2(1)/P2A(1)
RD0/PMD0
RE6/PMA10/P1B
RE5/PMA11/P1C
RE4/PMA12/P3B
RE3/PMA13/P3C/REFO
RE2/PMBE/P2B
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RE1/PMWR/P2C
RE0/PMRD/P2D
1
2
RG0/PMA8/ECCP3/P3A
RG1/PMA7/TX2/CK2
RG2/PMA6/RX2/DT2
3
4
5
6
7
RG3/PMCS1/CCP4/P3D
MCLR
RG4/PMCS2/CCP5/P1D
VSS
VDDCORE/VCAP
RF7/SS1
RF6/AN11/C1INA
RF5/AN10/C1INB/CVREF
RF4/AN9/C2INA
RF3/AN8/C2INB
RF2/PMA5/AN7/C1OUT
48
47
46
45
44
43
42
41
40
PIC18F6XJ11
8
9
10
11
12
13
PIC18F6XJ16
39
38
14
15
16
RB0/INT0/FLT0
RB1/INT1/PMA4
RB2/INT2/PMA3
RB3/INT3/PMA2
RB4/KBI0/PMA1
RB5/KBI1/PMA0
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
37
36
35
RB7/KBI3/PGD
RC5/SDO1
RC4/SDI1/SDA1
34
RC3/SCK1/SCL1
RC2/ECCP1/P1A
33
Legend:
Note 1:
DS39778E-page 2
RC7/RX1/DT1
RC6/TX1/CK1
RC1/T1OSI/ECCP2(1)/P2A(1)
RC0/T1OSO/T13CKI
RA4/T0CKI
RA5/AN4
VDD
VSS
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
AVSS
AVDD
ENVREG
RF1/AN6/C2OUT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Shaded pins indicate pins that are tolerant up to +5.5V.
The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
Pin Diagrams (Continued)
RD1/AD1/PMD1(3)
RD2/AD2/PMD2(3)
RD3/AD3/PMD3(3)
RD4/AD4/PMD4(3)/SDO2
RD5/AD5/PMD5(3)/SDI2/SDA2
RD6/AD6/PMD6(3)/SCK2/SCL2
RD7/AD7/PMD7(3)/SS2
RJ0/ALE
RJ1/OE
RE7/AD15/PMA9/ECCP2(1)/P2A(1)
RD0/AD0/PMD0(3)
VDD
VSS
RE2/AD10/PMBE(3)/P2B
RE3/AD11/PMA13/P3C(2)/REFO
RE4/AD12/PMA12/P3B(2)
RE5/AD13/PMA11/P1C(2)
RE6/AD14/PMA10/P1B(2)
RH1/A17
RH0/A16
80-Pin TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2/A18/PMD7(3)
1
60
RJ2/WRL
RH3/A19/PMD6(3)
2
RE1/AD9/PMWR(3)/P2C
RE0/AD8/PMRD(3)/P2D
RG0/PMA8/ECCP3/P3A
RG1/PMA7/TX2/CK2
3
4
5
6
7
59
58
RJ3/WRH
RB0/INT0/FLT0
RB1/INT1/PMA4
51
50
49
48
47
46
45
15
16
17
18
44
43
42
41
RB2/INT2/PMA3
RB3/INT3/PMA2/ECCP2(1)/P2A(1)
RB4/KBI0/PMA1
RB5/KBI1/PMA0
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
RB7/KBI3/PGD
RC5/SDO1
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RJ7/UB
RJ6/LB
RC1/T1OSI/ECCP2(1)/P2A(1)
RC0/T1OSO/T13CKI
RC6/TX1/CK1
RC7/RX1/DT1
RJ4/BA0
RJ5/CE
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RA4/PMD5(3)/T0CKI
20
RA5/PMD4(3)/AN4
RH6/PMRD(3)/AN14/ P1C(2)/C1INC
RA0/AN0
VSS
VDD
19
RH5/PMBE(3)/AN13/P3B(2)/C2IND
RH4/PMD3(3)/AN12/P3C(2)/C2INC
RF1/AN6/C2OUT
ENVREG
AVDD
RH7/PMWR(3)/AN15/P1B(2)
Legend:
Note 1:
2:
3:
52
PIC18F8XJ11
PIC18F8XJ16
10
11
12
13
14
RA2/AN2/VREFRA1/AN1
RF7/PMD0(3)/SS1
RF6/PMD1(3)/AN11/C1INA
RF5/PMD2(3)/AN10/ C1INB/CVREF
RF4/AN9/C2INA
RF3/AN8/C2INB
RF2/PMA5/AN7/C1OUT
8
9
AVSS
RA3/AN3/VREF+
RG2/PMA6/RX2/DT2
RG3/PMCS1/CCP4/P3D
MCLR
RG4/PMCS2/CCP5/P1D
VSS
VDDCORE/VCAP
57
56
55
54
53
Shaded pins indicate pins that are tolerant up to +5.5V.
The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit and Processor mode settings.
P1B, P1C, P3B, and P3C pin placement depends on the ECCPMX Configuration bit setting.
PMP pin placement depends on the PMPMX Configuration bit setting.
2007-2012 Microchip Technology Inc.
DS39778E-page 3
PIC18F87J11 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 31
3.0 Oscillator Configurations ............................................................................................................................................................ 37
4.0 Power-Managed Modes ............................................................................................................................................................. 47
5.0 Reset .......................................................................................................................................................................................... 55
6.0 Memory Organization ................................................................................................................................................................. 67
7.0 Flash Program Memory .............................................................................................................................................................. 95
8.0 External Memory Bus ............................................................................................................................................................... 105
9.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 117
10.0 Interrupts .................................................................................................................................................................................. 119
11.0 I/O Ports ................................................................................................................................................................................... 135
12.0 Parallel Master Port .................................................................................................................................................................. 167
13.0 Timer0 Module ......................................................................................................................................................................... 193
14.0 Timer1 Module ......................................................................................................................................................................... 197
15.0 Timer2 Module ......................................................................................................................................................................... 203
16.0 Timer3 Module ......................................................................................................................................................................... 205
17.0 Timer4 Module ......................................................................................................................................................................... 209
18.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 211
19.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 219
20.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 237
21.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 285
22.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 309
23.0 Comparator Module.................................................................................................................................................................. 319
24.0 Comparator Voltage Reference Module ................................................................................................................................... 327
25.0 Special Features of the CPU .................................................................................................................................................... 331
26.0 Instruction Set Summary .......................................................................................................................................................... 347
27.0 Development Support............................................................................................................................................................... 397
28.0 Electrical Characteristics .......................................................................................................................................................... 401
29.0 Packaging Information.............................................................................................................................................................. 441
Appendix A: Revision History............................................................................................................................................................. 447
Appendix B: Device Differences......................................................................................................................................................... 447
The Microchip Web Site ..................................................................................................................................................................... 449
Customer Change Notification Service .............................................................................................................................................. 449
Customer Support .............................................................................................................................................................................. 449
Reader Response .............................................................................................................................................................................. 450
Index ................................................................................................................................................................................................. 451
Product Identification System............................................................................................................................................................. 463
DS39778E-page 4
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2007-2012 Microchip Technology Inc.
DS39778E-page 5
PIC18F87J11 FAMILY
NOTES:
DS39778E-page 6
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC18F66J11
• PIC18F86J11
• PIC18F66J16
• PIC18F86J16
• PIC18F67J11
• PIC18F87J11
• A Phase Lock Loop (PLL) frequency multiplier,
available to all of the oscillator modes, which
allows a wide range of clock speeds from 16 MHz
to 40 MHz
The internal oscillator block provides a stable reference
source that gives the family additional features for
robust operation:
This family introduces a line of low-voltage, general
purpose microcontrollers with the main traditional
advantage of all PIC18 microcontrollers, namely, high
computational performance and a rich feature set at an
extremely competitive price point. These features
make the PIC18F87J11 family a logical choice for
many high-performance applications, where an
extended peripheral feature set is required, and cost is
a primary consideration.
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
1.1
1.1.3
1.1.1
Core Features
TECHNOLOGY
All of the devices in the PIC18F87J11 family incorporate
a range of features that can significantly reduce power
consumption during operation. Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal RC oscillator, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• On-the-Fly Mode Switching: The
power-managed modes are invoked by user code
during operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.
1.1.2
OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC18F87J11 family offer four
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• Two Crystal modes, using crystals or ceramic
resonators.
• Two External Clock modes, offering the option of
a divide-by-4 clock output.
• An internal oscillator block which provides an
8 MHz clock and an INTRC source (approximately
31 kHz, stable over temperature and VDD).
The oscillator block also provides a range of
6 user-selectable clock frequencies, between
125 kHz to 4 MHz, for a total of 8 clock
frequencies. This option frees an oscillator pin for
use as an additional general purpose I/O.
2007-2012 Microchip Technology Inc.
EXPANDED MEMORY
The PIC18F87J11 family provides ample room for
application code, from 64 Kbytes to 128 Kbytes of code
space. The Flash cells for program memory are rated
to last up to 10,000 erase/write cycles. Data retention
without refresh is conservatively estimated to be
greater than 20 years.
The Flash program memory is readable, writable, and
during normal operation, the PIC18F87J11 family also
provides plenty of room for dynamic application data,
with up to 3904 bytes of data RAM.
1.1.4
EXTERNAL MEMORY BUS
In the event that 128 Kbytes of memory are inadequate
for an application, the 80-pin members of the
PIC18F87J11 family also implement an External Memory Bus (EMB). This allows the controller’s internal
Program Counter (PC) to address a memory space of
up to 2 Mbytes, permitting a level of data access that
few 8-bit devices can claim. This allows additional
memory options, including:
• Using combinations of on-chip and external
memory up to the 2-Mbyte limit
• Using external Flash memory for reprogrammable
application code or large data tables
• Using external RAM devices for storing large
amounts of variable data
1.1.5
EXTENDED INSTRUCTION SET
The PIC18F87J11 family implements the optional
extension to the PIC18 instruction set, adding 8 new
instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code, originally developed in high-level
languages, such as ‘C’.
DS39778E-page 7
PIC18F87J11 FAMILY
1.1.6
EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members, or even
jumping from 64-pin to 80-pin devices.
The PIC18F87J11 family is also pin compatible with
other PIC18 families, such as the PIC18F87J10,
PIC18F85J11, PIC18F8720 and PIC18F8722. This
allows a new dimension to the evolution of applications,
allowing developers to select different price points
within Microchip’s PIC18 portfolio, while maintaining
the same feature set.
1.2
Other Special Features
• Communications: The PIC18F87J11 family
incorporates a range of serial and parallel communication peripherals. These devices all include
2 independent Enhanced USARTs and 2 Master
SSP modules, capable of both SPI and I2C™
(Master and Slave) modes of operation. The
devices also have a parallel port and can be
configured to function as either a Parallel Master
Port (PMP) or as a Parallel Slave Port.
• CCP Modules: All devices in the family incorporate
two Capture/Compare/PWM (CCP) modules and
three Enhanced CCP (ECCP) modules to maximize
flexibility in control applications. Up to four different
time bases may be used to perform several
different operations at once. Each of the three
ECCP modules offers up to four PWM outputs,
allowing for a total of 12 PWMs. The ECCPs also
offer many beneficial features, including polarity
selection, programmable dead time, auto-shutdown
and restart, and Half-Bridge and Full-Bridge Output
modes.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, and
thus, reducing code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 28.0 “Electrical Characteristics” for
time-out periods.
DS39778E-page 8
1.3
Details on Individual Family
Members
Devices in the PIC18F87J11 family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in three
ways:
1.
2.
3.
Flash program memory (three sizes, ranging
from 64 Kbytes for PIC18FX6J11 devices to
128 Kbytes for PIC18FX7J11 devices).
I/O ports (7 bidirectional ports on 64-pin devices,
9 bidirectional ports on 80-pin devices).
A/D input channels (11 on 64-pin devices, 15 on
80-pin devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1 and Table 1-2.
The pinouts for all devices are listed in Table 1-3 and
Table 1-4.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-1:
DEVICE FEATURES FOR THE PIC18F6XJ1X (64-PIN DEVICES)
Features
PIC18F66J11
PIC18F66J16
PIC18F67J11
DC – 48 MHz
DC – 48 MHz
DC – 48 MHz
64K
96K
128K
Program Memory (Instructions)
32768
49152
65536
Data Memory (Bytes)
3904
3904
3904
Operating Frequency
Program Memory (Bytes)
Interrupt Sources
29
I/O Ports
Ports A, B, C, D, E, F, G
Timers
5
Capture/Compare/PWM Modules
2
Enhanced Capture/Compare/PWM Modules
3
Serial Communications
MSSP (2), Enhanced USART (2)
Parallel Communications (PMP)
Yes
10-Bit Analog-to-Digital Module
11 Input Channels
Resets (and Delays)
Instruction Set
POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
75 Instructions, 83 with Extended Instruction Set Enabled
Packages
TABLE 1-2:
64-Pin TQFP
DEVICE FEATURES FOR THE PIC18F8XJ1X (80-PIN DEVICES)
Features
PIC18F86J11
PIC18F86J16
PIC18F87J11
DC – 48 MHz
DC – 48 MHz
DC – 48 MHz
64K
96K
128K
Program Memory (Instructions)
32768
49152
65536
Data Memory (Bytes)
3904
3904
3904
Operating Frequency
Program Memory (Bytes)
Interrupt Sources
I/O Ports
Timers
29
Ports A, B, C, D, E, F, G, H, J
5
Capture/Compare/PWM Modules
2
Enhanced Capture/Compare/PWM Modules
3
Serial Communications
MSSP (2), Enhanced USART (2)
Parallel Communications (PMP)
Yes
10-Bit Analog-to-Digital Module
15 Input Channels
Resets (and Delays)
Instruction Set
Packages
2007-2012 Microchip Technology Inc.
POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
75 Instructions, 83 with Extended Instruction Set Enabled
80-Pin TQFP
DS39778E-page 9
PIC18F87J11 FAMILY
FIGURE 1-1:
PIC18F6XJ1X (64-PIN) BLOCK DIAGRAM
Data Bus
Table Pointer
RA(1)
Data Memory
(2.0, 3.9
Kbytes)
PCLATU PCLATH
21
PORTA
Data Latch
8
8
inc/dec logic
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address
31 Level Stack
4
BSR
Address Latch
STKPTR
Program Memory
(96 Kbytes)
8
4
Access
Bank
12
FSR0
FSR1
FSR2
Data Latch
PORTB
RB(1)
12
PORTC
RC(1)
inc/dec
logic
Table Latch
Address
Decode
ROM Latch
Instruction Bus
PORTD
RD(1)
IR
Instruction
Decode and
Control
OSC2/CLKO
OSC1/CLKI
Timing
Generation
8 MHz
INTOSC
INTRC
Oscillator
8
State Machine
Control Signals
PRODH PRODL
3
Power-up
Timer
Precision
Band Gap
Reference
8
ECCP1
Note
RF(1)
ALU
8
PORTG
VDD, VSS
RG(1)
MCLR
A/D
10-Bit
Timer0
Timer1
Timer2
Timer3
Timer4
ECCP2
ECCP3
CCP4
CCP5
EUSART1
EUSART2
1:
See Table 1-3 for I/O port pin descriptions.
2:
BOR functionality is provided when the on-board voltage regulator is enabled.
DS39778E-page 10
PORTF
8
Brown-out
Reset(2)
Voltage
Regulator
PMP
8
8
Watchdog
Timer
ENVREG
VDDCORE/VCAP
8
W
8
Power-on
Reset
RE(1)
8 x 8 Multiply
BITOP
Oscillator
Start-up Timer
PORTE
Comparators
MSSP1
MSSP2
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 1-2:
PIC18F8XJ1X (80-PIN) BLOCK DIAGRAM
Data Bus
Table Pointer
8
inc/dec logic
21
31 Level Stack
System Bus Interface
Address Latch
PCU PCH PCL
Program Counter
Address Latch
Program Memory
(128 Kbytes)
STKPTR
RA(1)
Data Memory
(2.0, 3.9
Kbytes)
PCLATU PCLATH
20
PORTA
Data Latch
8
PORTB
RB(1)
12
Data Address
4
4
12
BSR
Data Latch
PORTC
Access
Bank
FSR0
FSR1
FSR2
RC(1)
12
inc/dec
logic
8
Table Latch
PORTD
RD(1)
Address
Decode
ROM Latch
Instruction Bus
PORTE
IR
RE(1)
AD, A
(Multiplexed with PORTD,
PORTE and PORTH)
8
OSC2/CLKO
OSC1/CLKI
Timing
Generation
Power-up
Timer
8 MHz
INTOSC
3
8
W
BITOP
8
PMP
Note
ECCP1
8
RH(1)
PORTJ
Brown-out
Reset(2)
VDD, VSS
RJ(1)
MCLR
A/D
10-Bit
Timer0
Timer1
Timer2
Timer3
Timer4
ECCP2
ECCP3
CCP4
CCP5
EUSART1
EUSART2
1:
See Table 1-4 for I/O port pin descriptions.
2:
BOR functionality is provided when the on-board voltage regulator is enabled.
2007-2012 Microchip Technology Inc.
PORTH
8
Watchdog
Timer
Voltage
Regulator
VDDCORE/VCAP
PORTG
8
ALU
Power-on
Reset
ENVREG
8
RG(1)
Oscillator
Start-up Timer
Precision
Band Gap
Reference
RF(1)
8 x 8 Multiply
8
INTRC
Oscillator
PORTF
PRODH PRODL
Instruction
Decode &
Control
State Machine
Control Signals
Comparators
MSSP1
MSSP2
DS39778E-page 11
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS
Pin Number
64-TQFP
Pin
Type
Buffer
Type
MCLR
7
I
ST
OSC1/CLKI/RA7
39
Pin Name
OSC1
I
CLKI
I
RA7
I/O
OSC2/CLKO/RA6
Description
Master Clear (Reset) input. This pin is an active-low Reset
to the device.
Oscillator crystal or external clock input. Available only in
External Oscillator modes (EC/ECPLL and HS/HSPLL).
ST
Main oscillator input connection.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS
otherwise.
CMOS Main clock input connection.
External clock source input. Always associated
with pin function, OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
TTL General purpose I/O pin. Available only in INTIO2 and
INTPLL2 Oscillator modes.
40
OSC2
O
—
CLKO
O
—
RA6
I/O
TTL
Oscillator crystal or clock output. Available only in External
Oscillator modes (EC/ECPLL and HS/HSPLL).
Main oscillator feedback output connection.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
System cycle clock output (FOSC/4).
In EC, ECPLL, INTIO1 and INTPLL1 Oscillator modes,
OSC2 pin outputs CLKO which has 1/4 the frequency
of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin. Available only in INTIO1 and
INTPLL1 Oscillator modes.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
DS39778E-page 12
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
64-TQFP
Pin
Type
Buffer
Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
24
RA1/AN1
RA1
AN1
23
RA2/AN2/VREFRA2
AN2
VREF-
22
RA3/AN3/VREF+
RA3
AN3
VREF+
21
RA4/T0CKI
RA4
T0CKI
28
RA5/AN4
RA5
AN4
27
RA6
RA7
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog Input 1.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
I/O
I
ST
ST
I/O
I
TTL
Analog
—
—
—
See the OSC2/CLKO/RA6 pin.
—
—
—
See the OSC1/CLKI/RA7 pin.
Digital I/O.
Timer0 external clock input.
Digital I/O.
Analog Input 4.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
2007-2012 Microchip Technology Inc.
DS39778E-page 13
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
64-TQFP
Pin
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/FLT0/INT0
RB0
FLT0
INT0
48
RB1/INT1/PMA4
RB1
INT1
PMA4
47
RB2/INT2/PMA3
RB2
INT2
PMA3
46
RB3/INT3/PMA2
RB3
INT3
PMA2
45
RB4/KBI0/PMA1
RB4
KBI0
PMA1
44
RB5/KBI1/PMA0
RB5
KBI1
PMA0
43
RB6/KBI2/PGC
RB6
KBI2
PGC
42
RB7/KBI3/PGD
RB7
KBI3
PGD
37
I/O
I
I
TTL
ST
ST
Digital I/O.
ECCP1/2/3 Fault input.
External Interrupt 0.
I/O
I
O
TTL
ST
—
Digital I/O.
External Interrupt 1.
Parallel Master Port address.
I/O
I
O
TTL
ST
—
Digital I/O.
External Interrupt 2.
Parallel Master Port address.
I/O
I
O
TTL
ST
—
Digital I/O.
External Interrupt 3.
Parallel Master Port address.
I/O
I
I/O
TTL
TTL
—
Digital I/O.
Interrupt-on-change pin.
Parallel Master Port address.
I/O
I
I/O
TTL
TTL
—
Digital I/O.
Interrupt-on-change pin.
Parallel Master Port address.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming
clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
DS39778E-page 14
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
64-TQFP
Pin
Type
Buffer
Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
30
RC1/T1OSI/ECCP2/P2A
RC1
T1OSI
ECCP2(1)
P2A(1)
29
RC2/ECCP1/P1A
RC2
ECCP1
P1A
33
RC3/SCK1/SCL1
RC3
SCK1
SCL1
34
RC4/SDI1/SDA1
RC4
SDI1
SDA1
35
RC5/SDO1
RC5
SDO1
36
RC6/TX1/CK1
RC6
TX1
CK1
31
RC7/RX1/DT1
RC7
RX1
DT1
32
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
I/O
I
I/O
O
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM Output A.
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
ECCP1 PWM Output A.
I/O
I/O
I/O
ST
ST
I2C
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
I
I/O
ST
ST
I2C
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
ST
—
Digital I/O.
SPI data out.
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
2007-2012 Microchip Technology Inc.
DS39778E-page 15
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
64-TQFP
Pin
Type
Buffer
Type
Description
PORTD is a bidirectional I/O port.
RD0/PMD0
RD0
PMD0
58
RD1/PMD1
RD1
PMD1
55
RD2/PMD2
RD2
PMD2
54
RD3/PMD3
RD3
PMD3
53
RD4/PMD4/SDO2
RD4
PMD4
SDO2
52
RD5/PMD5/SDI2/SDA2
RD5
PMD5
SDI2
SDA2
51
RD6/PMD6/SCK2/SCL2
RD6
PMD6
SCK2
SCL2
50
RD7/PMD7/SS2
RD7
PMD7
SS2
49
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Master Port data.
SPI data out.
I/O
I/O
I
I/O
ST
TTL
ST
ST
Digital I/O.
Parallel Master Port data.
SPI data in.
I2C data I/O.
I/O
I/O
I/O
I/O
ST
TTL
ST
ST
Digital I/O.
Parallel Master Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
Parallel Master Port data.
SPI slave select input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
DS39778E-page 16
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
64-TQFP
Pin
Type
Buffer
Type
Description
PORTE is a bidirectional I/O port.
RE0/PMRD/P2D
RE0
PMRD
P2D
2
RE1/PMWR/P2C
RE1
PMWR
P2C
1
RE2/PMBE/P2B
RE2
PMBE
P2B
64
RE3/PMA13/P3C/REFO
RE3
PMA13
P3C
REFO
63
RE4/PMA12/P3B
RE4
PMA12
P3B
62
RE5/PMA11/P1C
RE5
PMA11
P1C
61
RE6/PMA10/P1B
RE6
PMA10
P1B
60
RE7/PMA9/ECCP2/P2A
RE7
PMA9
ECCP2(2)
P2A(2)
59
I/O
I/O
O
ST
—
—
Digital I/O.
Parallel Master Port read strobe.
ECCP2 PWM Output D.
I/O
I/O
O
ST
—
—
Digital I/O.
Parallel Master Port write strobe.
ECCP2 PWM Output C.
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port byte enable
ECCP2 PWM Output B.
I/O
O
O
O
ST
—
—
—
Digital I/O.
Parallel Master Port address.
ECCP3 PWM Output C.
Reference clock out.
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port address.
ECCP3 PWM Output B.
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port address.
ECCP1 PWM Output C.
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port address.
ECCP1 PWM Output B.
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port address.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM Output A.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
2007-2012 Microchip Technology Inc.
DS39778E-page 17
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
64-TQFP
Pin
Type
Buffer
Type
Description
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT
RF1
AN6
C2OUT
17
RF2/PMA5/AN7/C1OUT
RF2
PMA5
AN7
C1OUT
16
RF3/AN8/C2INB
RF3
AN8
C2INB
15
RF4/AN9/C2INA
RF4
AN9
C2INA
14
RF5/AN10/C1INB/CVREF
RF5
AN10
C1INB
CVREF
13
RF6/AN11/C1INA
RF6
AN11
C1INA
12
RF7/SS1
RF7
SS1
11
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 6.
Comparator 2 output.
I/O
O
I
O
ST
—
Analog
—
Digital I/O.
Parallel Master Port address.
Analog Input 7.
Comparator 1 output.
I/O
I
I
ST
Analog
Analog
Digital input.
Analog Input 8.
Comparator 2 Input B.
I/O
I
I
ST
Analog
Analog
Digital input.
Analog Input 8.
Comparator 2 Input A.
I/O
I
I
O
ST
Analog
Analog
Analog
Digital input.
Analog Input 10.
Comparator 1 Input B.
Comparator reference voltage output.
I/O
I
I
ST
Analog
Analog
Digital I/O.
Analog Input 11.
Comparator 1 Input A.
I/O
I
ST
TTL
Digital I/O.
SPI slave select input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
DS39778E-page 18
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
64-TQFP
Pin
Type
Buffer
Type
Description
PORTG is a bidirectional I/O port.
RG0/PMA8/ECCP3/P3A
RG0
PMA8
ECCP3
P3A
3
RG1/PMA7/TX2/CK2
RG1
PMA7
TX2
CK2
4
RG2/PMA6/RX2/DT2
RG2
PMA6
RX2
DT2
5
RG3/PMCS1/CCP4/P3D
RG3
PMCS1
CCP4
P3D
6
RG4/PMCS2/CCP5/P1D
RG4
PMCS2
CCP5
P1D
8
VSS
9, 25, 41, 56
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port address.
Capture 3 input/Compare 3 output/PWM3 output.
ECCP3 PWM Output A.
I/O
O
O
I/O
ST
—
—
ST
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
I/O
O
I
I/O
ST
—
ST
ST
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port Chip Select 1.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM Output D.
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port Chip Select 2.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM Output D.
P
—
Ground reference for logic and I/O pins.
VDD
26, 38, 57
P
—
Positive supply for peripheral digital logic and I/O pins.
AVss
20
P
—
Ground reference for analog modules.
AVDD
19
P
—
Positive supply for analog modules.
ENVREG
18
I
ST
Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
10
P
—
P
—
VCAP
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator
enabled).
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
2007-2012 Microchip Technology Inc.
DS39778E-page 19
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS
Pin Number
80-TQFP
Pin
Type
Buffer
Type
MCLR
9
I
ST
OSC1/CLKI/RA7
49
Pin Name
OSC1
I
CLKI
I
RA7
I/O
OSC2/CLKO/RA6
Description
Master Clear (Reset) input. This pin is an active-low Reset to
the device.
Oscillator crystal or external clock input. Available only in
External Oscillator modes (EC/ECPLL and HS/HSPLL).
ST
Main oscillator input connection.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS
otherwise.
CMOS Main clock input connection.
External clock source input. Always associated
with pin function, OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
TTL General purpose I/O pin. Available only in INTIO2 and
INTPLL2 Oscillator modes.
50
OSC2
O
—
CLKO
O
—
RA6
I/O
TTL
Oscillator crystal or clock output. Available only in External
Oscillator modes (EC/ECPLL and HS/HSPLL).
Main oscillator feedback output connection.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
System cycle clock output (FOSC/4).
In EC, ECPLL, INTIO1 and INTPLL1 Oscillator modes,
OSC2 pin outputs CLKO which has 1/4 the frequency
of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin. Available only in INTIO and INTPLL
Oscillator modes.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
DS39778E-page 20
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
80-TQFP
Pin
Type
Buffer
Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
30
RA1/AN1
RA1
AN1
29
RA2/AN2/VREFRA2
AN2
VREF-
28
RA3/AN3/VREF+
RA3
AN3
VREF+
27
RA4/PMD5/T0CKI
RA4
PMD5(7)
T0CKI
34
RA5/PMD4/AN4
RA5
PMD4(7)
AN4
33
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog Input 1.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
I/O
I/O
I
ST
TTL
ST
I/O
I/O
I
TTL
TTL
Analog
Digital I/O.
Parallel Master Port data.
Timer0 external clock input.
Digital I/O.
Parallel Master Port data.
Analog Input 4.
RA6
—
—
—
See the OSC2/CLKO/RA6 pin.
RA7
—
—
—
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
2007-2012 Microchip Technology Inc.
DS39778E-page 21
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
80-TQFP
Pin
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/FLT0/INT0
RB0
FLT0
INT0
58
RB1/INT1/PMA4
RB1
INT1
PMA4
57
RB2/INT2/PMA3
RB2
INT2
PMA3
56
RB3/INT3/PMA2/
ECCP2/P2A
RB3
INT3
PMA2
ECCP2(1)
P2A(1)
55
RB4/KBI0/PMA1
RB4
KBI0
PMA1
54
RB5/KBI1/PMA0
RB5
KBI1
PMA0
53
RB6/KBI2/PGC
RB6
KBI2
PGC
52
RB7/KBI3/PGD
RB7
KBI3
PGD
47
I/O
I
I
TTL
ST
ST
Digital I/O.
ECCP1/2/3 Fault input.
External Interrupt 0.
I/O
I
O
TTL
ST
—
Digital I/O.
External Interrupt 1.
Parallel Master Port address.
I/O
I
O
TTL
ST
—
Digital I/O.
External Interrupt 2.
Parallel Master Port address.
I/O
I
O
I/O
O
TTL
ST
—
ST
—
Digital I/O.
External Interrupt 3.
Parallel Master Port address.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM Output A.
I/O
I
I/O
TTL
TTL
—
Digital I/O.
Interrupt-on-change pin.
Parallel Master Port address.
I/O
I
I/O
TTL
TTL
—
Digital I/O.
Interrupt-on-change pin.
Parallel Master Port address.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
DS39778E-page 22
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
80-TQFP
Pin
Type
Buffer
Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
36
RC1/T1OSI/ECCP2/P2A
RC1
T1OSI
ECCP2(2)
P2A(2)
35
RC2/ECCP1/P1A
RC2
ECCP1
P1A
43
RC3/SCK1/SCL1
RC3
SCK1
SCL1
44
RC4/SDI1/SDA1
RC4
SDI1
SDA1
45
RC5/SDO1
RC5
SDO1
46
RC6/TX1/CK1
RC6
TX1
CK1
37
RC7/RX1/DT1
RC7
RX1
DT1
38
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
I/O
I
I/O
O
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM Output A.
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
ECCP1 PWM Output A.
I/O
I/O
I/O
ST
ST
I2C
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
I
I/O
ST
ST
I2C
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
ST
—
Digital I/O.
SPI data out.
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
2007-2012 Microchip Technology Inc.
DS39778E-page 23
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
80-TQFP
Pin
Type
Buffer
Type
Description
PORTD is a bidirectional I/O port.
RD0/AD0/PMD0
RD0
AD0
PMD0(6)
72
RD1/AD1/PMD1
RD1
AD1
PMD1(6)
69
RD2/AD2/PMD2
RD2
AD2
PMD2(6)
68
RD3/AD3/PMD3
RD3
AD3
PMD3(6)
67
RD4/AD4/PMD4/SDO2
RD4
AD4
PMD4(6)
SDO2
66
RD5/AD5/PMD5/
SDI2/SDA2
RD5
AD5
PMD5(6)
SDI2
SDA2
65
RD6/AD6/PMD6/
SCK2/SCL2
RD6
AD6
PMD6(6)
SCK2
SCL2
64
RD7/AD7/PMD7/SS2
RD7
AD7
PMD7(6)
SS2
63
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External Memory Address/Data 0.
Parallel Master Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External Memory Address/Data 1.
Parallel Master Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External Memory Address/Data 2.
Parallel Master Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External Memory Address/Data 3.
Parallel Master Port data.
I/O
I/O
I/O
O
ST
TTL
TTL
—
Digital I/O.
External Memory Address/Data 4.
Parallel Master Port data.
SPI data out.
I/O
I/O
I/O
I
I/O
ST
TTL
TTL
ST
ST
Digital I/O.
External Memory Address/Data 5.
Parallel Master Port data.
SPI data in.
I2C data I/O.
I/O
I/O
I/O
I/O
I/O
ST
TTL
TTL
ST
ST
Digital I/O.
External Memory Address/Data 6.
Parallel Master Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
I/O
I/O
I
ST
TTL
TTL
TTL
Digital I/O.
External Memory Address/Data 7.
Parallel Master Port data.
SPI slave select input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
DS39778E-page 24
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
80-TQFP
Pin
Type
Buffer
Type
Description
PORTE is a bidirectional I/O port.
RE0/AD8/PMRD/P2D
RE0
AD8
PMRD(6)
P2D
4
RE1/AD9/PMWR/P2C
RE1
AD9
PMWR(6)
P2C
3
RE2/AD10/PMBE/P2B
RE2
AD10
PMBE(6)
P2B
78
RE3/AD11/PMA13/P3C/REFO
RE3
AD11
PMA13
P3C(3)
REFO
77
RE4/AD12/PMA12/P3B
RE4
AD12
PMA12
P3B(3)
76
RE5/AD13/PMA11/P1C
RE5
AD13
PMA11
P1C(3)
75
RE6/AD14/PMA10/P1B
RE6
AD14
PMA10
P1B(3)
74
RE7/AD15/PMA9/ECCP2/P2A
RE7
AD15
PMA9
ECCP2(4)
P2A(4)
73
I/O
I/O
I/O
O
ST
TTL
—
—
Digital I/O.
External Memory Address/Data 8.
Parallel Master Port read strobe.
ECCP2 PWM Output D.
I/O
I/O
I/O
O
ST
TTL
—
—
Digital I/O.
External Memory Address/Data 9.
Parallel Master Port write strobe.
ECCP2 PWM Output C.
I/O
I/O
O
O
ST
TTL
—
—
Digital I/O.
External Memory Address/Data 10.
Parallel Master Port byte enable.
ECCP2 PWM Output B.
I/O
I/O
O
O
O
ST
TTL
—
—
—
Digital I/O.
External Memory Address/Data 11.
Parallel Master Port address.
ECCP3 PWM Output C.
Reference clock out.
I/O
I/O
O
O
ST
TTL
—
—
Digital I/O.
External Memory Address/Data 12.
Parallel Master Port address.
ECCP3 PWM Output B.
I/O
I/O
O
O
ST
TTL
—
—
Digital I/O.
External Memory Address/Data 13.
Parallel Master Port address.
ECCP1 PWM Output C.
I/O
I/O
O
O
ST
TTL
—
—
Digital I/O.
External Memory Address/Data 14.
Parallel Master Port address.
ECCP1 PWM Output B.
I/O
I/O
O
I/O
O
ST
TTL
—
ST
—
Digital I/O.
External Memory Address/Data 15.
Parallel Master Port address.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM Output A.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
2007-2012 Microchip Technology Inc.
DS39778E-page 25
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
80-TQFP
Pin
Type
Buffer
Type
Description
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT
RF1
AN6
C2OUT
23
RF2/PMA5/AN7/C1OUT
RF2
PMA5
AN7
C1OUT
18
RF3/AN8/C2INB
RF3
AN8
C2INB
17
RF4/AN9/C2INA
RF4
AN9
C2INA
16
RF5/PMD2/AN10/
C1INB/CVREF
RF5
PMD2(7)
AN10
C1INB
CVREF
15
RF6/PMD1/AN11/C1INA
RF6
PMD1(7)
AN11
C1INA
14
RF7/PMD0/SS1
RF7
PMD0(7)
SS1
13
I/O
I
O
ST
Analog
—
Digital I/O.
Analog Input 6.
Comparator 2 output.
I/O
O
I
O
ST
—
Analog
—
Digital I/O.
Parallel Master Port address.
Analog Input 7.
Comparator 1 output.
I/O
I
I
ST
Analog
Analog
Digital input.
Analog Input 8.
Comparator 2 Input B.
I/O
I
I
ST
Analog
Analog
Digital input.
Analog Input 8.
Comparator 2 Input A.
I/O
I/O
I
I
O
ST
TTL
Analog
Analog
Analog
Digital I/O.
Parallel Master Port address.
Analog Input 10.
Comparator 1 Input B.
Comparator reference voltage output.
I/O
I/O
I
I
ST
TTL
Analog
Analog
Digital I/O.
Parallel Master Port address.
Analog Input 11.
Comparator 1 Input A.
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
Parallel Master Port address.
SPI slave select input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
DS39778E-page 26
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
80-TQFP
Pin
Type
Buffer
Type
Description
PORTG is a bidirectional I/O port.
RG0/PMA8/ECCP3/P3A
RG0
PMA8
ECCP3
P3A
5
RG1/PMA7/TX2/CK2
RG1
PMA7
TX2
CK2
6
RG2/PMA6/RX2/DT2
RG2
PMA6
RX2
DT2
7
RG3/PMCS1/CCP4/P3D
RG3
PMCS1
CCP4
P3D
8
RG4/PMCS2/CCP5/P1D
RG4
PMCS2
CCP5
P1D
10
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port address.
Capture 3 input/Compare 3 output/PWM3 output.
ECCP3 PWM Output A.
I/O
O
O
I/O
ST
—
—
ST
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
I/O
I/O
I
I/O
ST
—
ST
ST
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
I/O
I/O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port Chip Select 1.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM Output D.
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port Chip Select 2.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM Output D.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
2007-2012 Microchip Technology Inc.
DS39778E-page 27
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
80-TQFP
Pin
Type
Buffer
Type
Description
PORTH is a bidirectional I/O port.
RH0/A16
RH0
A16
79
RH1/A17
RH1
A17
80
RH2/A18/PMD7
RH2
A18
PMD7(7)
1
RH3/A19/PMD6
RH3
A19
PMD6(7)
2
RH4/PMD3/AN12/
P3C/C2INC
RH4
PMD3(7)
AN12
P3C(5)
C2INC
22
RH5/PMBE/AN13/
P3B/C2IND
RH5
PMBE(7)
AN13
P3B(5)
C2IND
21
RH6/PMRD/AN14/
P1C/C1INC
RH6
PMRD(7)
AN14
P1C(5)
C1INC
20
RH7/PMWR/AN15/P1B
RH7
PMWR(7)
AN15
P1B(5)
19
I/O
O
ST
TTL
Digital I/O.
External Memory Address/Data 16.
I/O
O
ST
TTL
Digital I/O.
External Memory Address/Data 17.
I/O
O
I/O
ST
TTL
TTL
Digital I/O.
External Memory Address/Data 18.
Parallel Master Port data.
I/O
O
I/O
ST
TTL
TTL
Digital I/O.
External Memory Address/Data 19.
Parallel Master Port data.
I/O
I/O
I
O
I
ST
TTL
Analog
—
Analog
Digital I/O.
Parallel Master Port address.
Analog Input 12.
ECCP3 PWM Output C.
Comparator 2 Input C.
I/O
O
I
O
I
ST
—
Analog
—
Analog
Digital I/O.
Parallel Master Port byte enable.
Analog Input 13.
ECCP3 PWM Output B.
Comparator 2 Input D.
I/O
I/O
I
O
I
ST
—
Analog
—
Analog
Digital I/O.
Parallel Master Port read strobe.
Analog Input 14.
ECCP1 PWM Output C.
Comparator 1 Input C.
I/O
I/O
I
O
ST
—
Analog
—
Digital I/O.
Parallel Master Port write strobe.
Analog Input 15.
ECCP1 PWM Output B.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
DS39778E-page 28
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
80-TQFP
Pin
Type
Buffer
Type
Description
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
ALE
62
RJ1/OE
RJ1
OE
61
RJ2/WRL
RJ2
WRL
60
RJ3/WRH
RJ3
WRH
59
RJ4/BA0
RJ4
BA0
39
RJ5/CE
RJ5
CE
40
RJ6/LB
RJ6
LB
41
RJ7/UB
RJ7
UB
42
I/O
O
ST
—
Digital I/O.
External memory address latch enable.
I/O
O
ST
—
Digital I/O.
External memory output enable.
I/O
O
ST
—
Digital I/O.
External memory write low control.
I/O
O
ST
—
Digital I/O.
External memory write high control.
I/O
O
ST
—
Digital I/O.
External Memory Byte Address 0 control.
I/O
O
ST
—
Digital I/O
External memory chip enable control.
I/O
O
ST
—
Digital I/O.
External memory low byte control.
I/O
O
ST
—
Digital I/O.
External memory high byte control.
VSS
11, 31, 51,
70
P
—
Ground reference for logic and I/O pins.
VDD
32, 48, 71
P
—
Positive supply for peripheral digital logic and I/O pins.
AVss
26
P
—
Ground reference for analog modules.
AVDD
25
P
—
Positive supply for analog modules.
ENVREG
24
I
ST
Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
12
P
—
P
—
VCAP
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = ST with I2C™ or SMB levels
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
2007-2012 Microchip Technology Inc.
DS39778E-page 29
PIC18F87J11 FAMILY
NOTES:
DS39778E-page 30
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
2.0
GUIDELINES FOR GETTING
STARTED WITH PIC18FJ
MICROCONTROLLERS
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTIONS
C2(2)
• All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”)
• All AVDD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
• ENVREG (if implemented) and VCAP/VDDCORE pins
(see Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)”)
VCAP/VDDCORE
C1
VSS
VDD
VDD
VSS
C3(2)
C6(2)
C5(2)
C4(2)
Key (all values are recommendations):
• PGC/PGD pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
R1: 10 kΩ
Note:
C7
PIC18FXXJXX
C1 through C6: 0.1 F, 20V ceramic
• VREF+/VREF- pins are used when external voltage
reference for analog modules is implemented
(1) (1)
ENVREG
MCLR
These pins must also be connected if they are being
used in the end application:
Additionally, the following pins may be required:
VSS
VDD
R2
VSS
The following pins must always be connected:
R1
VDD
Getting started with the PIC18F87J11 family family of
8-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.
VDD
AVSS
Basic Connection Requirements
AVDD
2.1
C7: 10 F, 6.3V or greater, tantalum or ceramic
R2: 100Ω to 470Ω
Note 1:
2:
See Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)” for
explanation of ENVREG pin connections.
The example shown is for a PIC18F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
The minimum mandatory connections are shown in
Figure 2-1.
2007-2012 Microchip Technology Inc.
DS39778E-page 31
PIC18F87J11 FAMILY
2.2
2.2.1
Power Supply Pins
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2
TANK CAPACITORS
On boards with power traces running longer than
six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
DS39778E-page 32
2.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: Device Reset, and Device Programming
and Debugging. If programming and debugging are
not required in the end application, a direct
connection to VDD may be all that is required. The
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R1
R2
JP
MCLR
PIC18FXXJXX
C1
Note 1:
R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2:
R2 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
2.4
Voltage Regulator Pins (ENVREG
and VCAP/VDDCORE)
The on-chip voltage regulator enable pin, ENVREG,
must always be connected directly to either a supply
voltage or to ground. Tying ENVREG to VDD enables
the regulator, while tying it to ground disables the
regulator. Refer to Section 25.3 “On-Chip Voltage
Regulator” for details on connecting and using the
on-chip regulator.
Note that the “LF” versions of some low pin count
PIC18FJ parts (e.g., the PIC18LF45J10) do not have
the ENVREG pin. These devices are provided with the
voltage regulator permanently disabled; they must
always be provided with a supply voltage on the
VDDCORE pin.
FIGURE 2-3:
When the regulator is enabled, a low-ESR (< 5Ω)
capacitor is required on the VCAP/VDDCORE pin to
stabilize the voltage regulator output voltage. The
VCAP/VDDCORE pin must not be connected to VDD and
must use a capacitor of 10 µF connected to ground. The
type can be ceramic or tantalum. Suitable examples of
capacitors are shown in Table 2-1. Capacitors with
equivalent specifications can be used.
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
10
ESR ()
1
0.1
Designers may use Figure 2-3 to evaluate ESR
equivalence of candidate devices.
0.01
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 28.0 “Electrical
Characteristics” for additional information.
0.001
0.01
Note:
When the regulator is disabled, the VCAP/VDDCORE pin
must be tied to a voltage supply at the VDDCORE level.
Refer to Section 28.0 “Electrical Characteristics” for
information on VDD and VDDCORE.
0.1
1
10
100
Frequency (MHz)
1000 10,000
Typical data measurement at 25°C, 0V DC bias.
.
TABLE 2-1:
SUITABLE CAPACITOR EQUIVALENTS
Make
Part #
Nominal
Capacitance
Base Tolerance
Rated Voltage
Temp. Range
TDK
C3216X7R1C106K
10 µF
±10%
16V
-55 to 125ºC
TDK
C3216X5R1C106K
10 µF
±10%
16V
-55 to 85ºC
Panasonic
ECJ-3YX1C106K
10 µF
±10%
16V
-55 to 125ºC
Panasonic
ECJ-4YB1C106K
10 µF
±10%
16V
-55 to 85ºC
Murata
GRM32DR71C106KA01L
10 µF
±10%
16V
-55 to 125ºC
Murata
GRM31CR61C106KC31L
10 µF
±10%
16V
-55 to 85ºC
2007-2012 Microchip Technology Inc.
DS39778E-page 33
PIC18F87J11 FAMILY
CONSIDERATIONS FOR CERAMIC
CAPACITORS
In recent years, large value, low-voltage, surface-mount
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
physical size and other properties make ceramic
capacitors very attractive in many types of applications.
Ceramic capacitors are suitable for use with the
VDDCORE voltage regulator of this microcontroller.
However, some care is needed in selecting the capacitor to ensure that it maintains sufficient capacitance
over the intended operating range of the application.
Typical low-cost, 10 µF ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial tolerance specifications for these types of capacitors are
often specified as ±10% to ±20% (X5R and X7R), or
-20%/+80% (Y5V). However, the effective capacitance
that these capacitors provide in an application circuit will
also vary based on additional factors, such as the
applied DC bias voltage and the temperature. The total
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification.
The X5R and X7R capacitors typically exhibit satisfactory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer's data
sheets for exact specifications). However, Y5V capacitors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme
temperature tolerance, a 10 µF nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum VDDCORE voltage regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
VDDCORE regulator if the application must operate over
a wide temperature range.
In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very significant, but is often overlooked or is not always
documented.
A typical DC bias voltage vs. capacitance graph for
X7R type and Y5V type capacitors is shown in
Figure 2-4.
FIGURE 2-4:
Capacitance Change (%)
2.4.1
DC BIAS VOLTAGE vs.
CAPACITANCE
CHARACTERISTICS
10
0
-10
16V Capacitor
-20
-30
-40
10V Capacitor
-50
-60
-70
6.3V Capacitor
-80
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DC Bias Voltage (VDC)
When selecting a ceramic capacitor to be used with the
VDDCORE voltage regulator, it is suggested to select a
high-voltage rating, so that the operating voltage is a
small percentage of the maximum rated capacitor
voltage. For example, choose a ceramic capacitor
rated at 16V for the 2.5V VDDCORE voltage. Suggested
capacitors are shown in Table 2-1.
2.5
ICSP Pins
The PGC and PGD pins are used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes, and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communications to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin input voltage high
(VIH) and input low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGCx/PGDx pins), programmed
into the device, matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 27.0 “Development Support”.
DS39778E-page 34
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
2.6
External Oscillator Pins
FIGURE 2-5:
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency
secondary
oscillator
(refer to
Section 3.0 “Oscillator Configurations” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Single-Sided and In-Line Layouts:
Copper Pour
(tied to ground)
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design”
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
2.7
Unused I/Os
Primary Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
OSC1
C1
`
OSC2
GND
C2
`
T1OSO
T1OS I
Timer1 Oscillator
Crystal
Layout suggestions are shown in Figure 2-5. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
In planning the application’s routing and I/O assignments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times,
and other similar noise).
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
`
T1 Oscillator: C1
T1 Oscillator: C2
Fine-Pitch (Dual-Sided) Layouts:
Top Layer Copper Pour
(tied to ground)
Bottom Layer
Copper Pour
(tied to ground)
OSCO
C2
Oscillator
Crystal
GND
C1
OSCI
DEVICE PINS
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
2007-2012 Microchip Technology Inc.
DS39778E-page 35
PIC18F87J11 FAMILY
NOTES:
DS39778E-page 36
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
3.0
OSCILLATOR
CONFIGURATIONS
3.1
Oscillator Types
All of these modes are selected by the user by
programming the FOSC Configuration bits.
The PIC18F87J11 family of devices can be operated in
eight different oscillator modes:
1.
2.
3.
4.
5.
6.
7.
8.
HS
HSPLL
High-Speed Crystal/Resonator
High-Speed Crystal/Resonator
with Software PLL Control
EC
External Clock with FOSC/4 Output
ECPLL
External Clock with Software PLL
Control
INTIO1 Internal Oscillator Block with FOSC/4
Output on RA6 and I/O on RA7
INTIO2 Internal Oscillator Block with I/O on
RA6 and RA7
INTPLL1 Internal
Oscillator
Block
with
Software
PLL Control, FOSC/4 Output on RA6
and I/O on RA7
INTPLL2 Internal Oscillator Block with Software
PLL Control and I/O on RA6 and RA7
FIGURE 3-1:
In addition, PIC18F87J11 family devices can switch
between different clock sources, either under software
control or automatically under certain conditions. This
allows for additional power savings by managing
device clock speed in real time without resetting the
application.
The clock sources for the PIC18F87J11 family of
devices are shown in Figure 3-1.
PIC18F87J11 FAMILY CLOCK DIAGRAM
PIC18F87J11 Family
OSCTUNE
T1OSO
T1OSI
HSPLL, ECPLL, INTPLL
4 x PLL
OSC1
Secondary Oscillator
T1OSC
T1OSCEN
Enable
Oscillator
OSCCON
OSCCON
8 MHz
4 MHz
Internal
Oscillator
Block
2 MHz
8 MHz
(INTOSC)
Postscaler
8 MHz
Source
1 MHz
500 kHz
250 kHz
125 kHz
Internal Oscillator
2007-2012 Microchip Technology Inc.
31 kHz (INTRC)
CPU
111
110
IDLEN
101
100
011
010
001
1 31 kHz
000
0
INTRC
Source
Peripherals
MUX
Sleep
HS, EC
MUX
OSC2
Primary Oscillator
Clock
Control
FOSC
OSCCON
Clock Source Option
for Other Modules
OSCTUNE
WDT, PWRT, FSCM
and Two-Speed Start-up
DS39778E-page 37
PIC18F87J11 FAMILY
3.2
Control Registers
The OSCCON register (Register 3-1) controls the main
aspects of the device clock’s operation. It selects the
oscillator type to be used, which of the power-managed
modes to invoke and the output frequency of the
INTOSC source. It also provides status on the oscillators.
OSCCON: OSCILLATOR CONTROL REGISTER(1)
REGISTER 3-1:
R/W-0
R/W-1
IDLEN
The OSCTUNE register (Register 3-2) controls the
tuning and operation of the internal oscillator block. It
also implements the PLLEN bits which control the
operation of the Phase Locked Loop (PLL) (see
Section 3.4.3 “PLL Frequency Multiplier”).
IRCF2
(3)
R/W-1
(3)
IRCF1
R/W-0
IRCF0
(3)
R(2)
OSTS
U-1
—
R/W-0
SCS1
(5)
R/W-0
SCS0(5)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IDLEN: Idle Enable bit
1 = Device enters an Idle mode when a SLEEP instruction is executed
0 = Device enters Sleep mode when a SLEEP instruction is executed
bit 6-4
IRCF: INTOSC Source Frequency Select bits(3)
111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz (default)
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC)(4)
bit 3
OSTS: Oscillator Start-up Timer Time-out Status bit(2)
1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready
bit 2
Unimplemented: Read as ‘1’
bit 1-0
SCS: System Clock Select bits(5)
11 = Internal oscillator block
10 = Primary oscillator
01 = Timer1 oscillator
00 = Default primary oscillator (as defined by the FOSC Configuration bits)
Note 1:
2:
3:
4:
5:
Default (legacy) SFR at this address, available when WDTCON = 0.
Reset state depends on the state of the IESO Configuration bit.
Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
The source is selected by the INTSRC bit (OSCTUNE), see text.
Modifying these bits will cause an immediate clock source switch.
DS39778E-page 38
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 3-2:
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTSRC
PLLEN
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived from INTRC 31 kHz oscillator
bit 6
PLLEN: Frequency Multiplier PLL Enable bit
1 = PLL is enabled
0 = PLL is disabled
bit 5-0
TUN: Fast RC Oscillator (INTOSC) Frequency Tuning bits
011111 = Maximum frequency
•
•
•
•
000001
000000 = Center frequency. Fast RC Oscillator is running at the calibrated frequency.
111111
•
•
•
•
100000 = Minimum frequency
3.3
Clock Sources and
Oscillator Switching
Essentially, PIC18F87J11 family devices have three
independent clock sources:
• Primary oscillators
• Secondary oscillators
• Internal oscillator
The primary oscillators can be thought of as the main
device oscillators. These are any external oscillators
connected to the OSC1 and OSC2 pins, and include
the External Crystal and Resonator modes, and the
External Clock modes. If selected by the FOSC
Configuration bits, the internal oscillator block (either
the 31 kHz INTRC or the 8 MHz INTOSC source) may
be considered a primary oscillator. The particular mode
is defined by the FOSCx Configuration bits. The details
of these modes are covered in Section 3.4 “External
Oscillator Modes”.
as a secondary oscillator source. This oscillator, in all
power-managed modes, is often the time base for
functions, such as a Real-Time Clock (RTC). The
Timer1 oscillator is discussed in greater detail in
Section 14.0 “Timer1 Module”.
In addition to being a primary clock source in some circumstances, the internal oscillator is available as a
power-managed mode clock source. The INTRC
source is also used as the clock source for several
special features, such as the WDT and Fail-Safe Clock
Monitor. The internal oscillator block is discussed in
more detail in Section 3.5 “Internal Oscillator
Block”.
The PIC18F87J11 family includes features that allow
the device clock source to be switched from the main
oscillator, chosen by device configuration, to one of the
alternate clock sources. When an alternate clock
source is enabled, various power-managed operating
modes are available.
The secondary oscillators are external clock sources
that are not connected to the OSC1 or OSC2 pins.
These sources may continue to operate even after the
controller is placed in a power-managed mode.
PIC18F87J11 family devices offer the Timer1 oscillator
2007-2012 Microchip Technology Inc.
DS39778E-page 39
PIC18F87J11 FAMILY
3.3.1
CLOCK SOURCE SELECTION
The System Clock Select bits, SCS
(OSCCON), select the clock source. The available clock sources are the primary clock defined by the
FOSC Configuration bits, the secondary clock
(Timer1 oscillator) and the internal oscillator. The clock
source changes after one or more of the bits are written
to, following a brief clock transition interval.
The OSTS (OSCCON) and T1RUN (T1CON)
bits indicate which clock source is currently providing
the device clock. The OSTS bit indicates that the
Oscillator Start-up Timer (OST) has timed out and the
primary clock is providing the device clock in primary
clock modes. The T1RUN bit indicates when the
Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only
one of these bits will be set at any time. If neither of
these bits is set, the INTRC is providing the clock, or
the internal oscillator has just started and is not yet
stable.
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
“Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control register (T1CON). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEP instruction will be ignored.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEP instruction or a very
long delay may occur while the Timer1
oscillator starts.
DS39778E-page 40
3.3.1.1
System Clock Selection and Device
Resets
Since the SCSx bits are cleared on all forms of Reset,
this means the primary oscillator defined by the
FOSC Configuration bits is used as the primary
clock source on device Resets. This could either be the
internal oscillator block by itself, or one of the other
primary clock sources (HS, EC, HSPLL, ECPLL1/2 or
INTPLL1/2).
In those cases when the internal oscillator block, without PLL, is the default clock on Reset, the Fast RC
Oscillator (INTOSC) will be used as the device clock
source. It will initially start at 4 MHz; the postscaler
selection that corresponds to the Reset value of the
IRCF bits (‘110’).
Regardless of which primary oscillator is selected,
INTRC will always be enabled on device power-up. It
serves as the clock source until the device has loaded
its configuration values from memory. It is at this point
that the FOSCx Configuration bits are read and the
oscillator selection of the operational mode is made.
Note that either the primary clock source, or the internal
oscillator, will have two bit setting options for the possible
values of the SCS bits at any given time.
3.3.2
OSCILLATOR TRANSITIONS
PIC18F87J11 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 4.1.2 “Entering Power-Managed Modes”.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
3.4
TABLE 3-2:
External Oscillator Modes
3.4.1
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS (HS MODES)
In HS or HSPLL Oscillator modes, a crystal or ceramic
resonator is connected to the OSC1 and OSC2 pins to
establish oscillation. Figure 3-2 shows the pin
connections.
The oscillator design requires the use of a crystal rated
for parallel resonant operation.
Note:
Use of a crystal rated for series resonant
operation may give a frequency out of the
crystal manufacturer’s specifications.
TABLE 3-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Typical Capacitor Values Used:
Mode
Freq.
OSC1
OSC2
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Capacitor values are for design guidance only.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
Vdd and temperature range for the application. Refer
to the following application notes for oscillator specific
information:
• AN588, “PIC® Microcontroller Oscillator Design
Guide”
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC® and PIC® Devices”
• AN849, “Basic PIC® Oscillator Design”
• AN943, “Practical PIC® Oscillator Analysis and
Design”
• AN949, “Making Your Oscillator Work”
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Typical Capacitor Values
Tested:
Crystal
Freq.
Osc Type
HS
C1
C2
4 MHz
27 pF
27 pF
8 MHz
22 pF
22 pF
20 MHz
15 pF
15 pF
Capacitor values are for design guidance only.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
Vdd and temperature range for the application.
Refer to the Microchip application notes cited in
Table 3-1 for oscillator specific information. Also see
the notes following this table for additional
information.
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
3: Rs may be required to avoid overdriving
crystals with low drive level specification.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
FIGURE 3-2:
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS OR HSPLL
CONFIGURATION)
See the notes following Table 3-2 for additional
information.
C1(1)
OSC1
XTAL
RF(3)
OSC2
C2(1)
2007-2012 Microchip Technology Inc.
RS(2)
To
Internal
Logic
Sleep
PIC18F87J11
Note 1:
See Table 3-1 and Table 3-2 for initial values of
C1 and C2.
2:
A series resistor (RS) may be required for AT
strip cut crystals.
3:
RF varies with the oscillator mode chosen.
DS39778E-page 41
PIC18F87J11 FAMILY
3.4.2
EXTERNAL CLOCK INPUT
(EC MODES)
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency,
divided by 4, is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-3:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
3.4.3.1
HSPLL and ECPLL Modes
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external
oscillating source to produce frequencies up to
40 MHz.
The PLL is enabled by programming the FOSC
Configuration bits to either ‘111’ (for ECPLL) or ‘101’ (for
HSPLL). In addition, the PLLEN bit (OSCTUNE)
must also be set. Clearing PLLEN disables the PLL,
regardless of the chosen oscillator configuration. It also
allows additional flexibility for controlling the application’s clock speed in software.
FIGURE 3-5:
PLL BLOCK DIAGRAM
HSPLL or ECPLL (CONFIG2L)
PLL Enable (OSCTUNE)
OSC1/CLKI
Clock from
Ext. System
PIC18F87J11
FOSC/4
OSC2/CLKO
OSC2
HS or EC
Mode
OSC1
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-4. In
this configuration, the divide-by-4 output on OSC2 is
not available. Current consumption in this configuration
will be somewhat higher than EC mode, as the internal
oscillator’s feedback circuitry will be enabled (in EC
mode, the feedback circuit is disabled).
FIGURE 3-4:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
OSC1
Clock from
Ext. System
PIC18F87J11
(HS Mode)
Open
3.4.3
OSC2
FIN
Phase
Comparator
FOUT
Loop
Filter
VCO
MUX
4
3.4.3.2
SYSCLK
PLL and INTOSC
The PLL is also available to the internal oscillator block
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 32 MHz. The operation of INTOSC with the PLL is
described in Section 3.5.2 “INTPLL Modes”.
PLL FREQUENCY MULTIPLIER
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency oscillator circuit, or to clock the device up to its highest rated
frequency from a crystal oscillator. This may be useful for
customers who are concerned with the External Memory
Interface (EMI) due to high-frequency crystals, or users
who require higher clock speeds from an internal
oscillator.
DS39778E-page 42
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
3.5
Internal Oscillator Block
The PIC18F87J11 family of devices includes an
internal oscillator block which generates two different
clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for
an external oscillator circuit on the OSC1 and/or OSC2
pins.
The main output is the Fast RC oscillator, or INTOSC,
an 8 MHz clock source which can be used to directly
drive the device clock. It also drives a postscaler, which
can provide a range of clock frequencies from 31 kHz
to 4 MHz. INTOSC is enabled when a clock frequency
from 125 kHz to 8 MHz is selected. The INTOSC output can also be enabled when 31 kHz is selected,
depending on the INTSRC bit (OSCTUNE).
The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled:
•
•
•
•
Power-up Timer
Fail-Safe Clock Monitor
Watchdog Timer
Two-Speed Start-up
These features are discussed in greater detail in
Section 25.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTOSC
with postscaler or INTRC direct) is selected by configuring the IRCFx bits of the OSCCON register. The
default frequency on device Resets is 4 MHz.
3.5.1
INTIO MODES
Using the internal oscillator as the clock source eliminates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
oscillator configurations, which are determined by the
FOSCx Configuration bits, are available:
• In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 (see Figure 3-6) for
digital input and output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6 (see Figure 3-7), both for
digital input and output.
2007-2012 Microchip Technology Inc.
FIGURE 3-6:
INTIO1 OSCILLATOR MODE
I/O (OSC1)
RA7
PIC18F87J11
OSC2
FOSC/4
FIGURE 3-7:
INTIO2 OSCILLATOR MODE
RA7
I/O (OSC1)
RA6
I/O (OSC2)
PIC18F87J11
3.5.2
INTPLL MODES
The 4x Phase Locked Loop (PLL) can be used with the
internal oscillator block to produce faster device clock
speeds than are normally possible with the internal
oscillator sources. When enabled, the PLL produces a
clock speed of 16 MHz or 32 MHz.
PLL operation is controlled through software. The control bit, PLLEN (OSCTUNE), is used to enable or
disable its operation. The PLL is available only to
INTOSC when the device is configured to use one of
the INTPLL modes as the primary clock source
(FOSC = 011 or 010). Additionally, the PLL will
only function when the selected output frequency is
either 4 MHz or 8 MHz (OSCCON = 111 or 110).
Like the INTIO modes, there are two distinct INTPLL
modes available:
• In INTPLL1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output. Externally, this is identical in appearance
to INTIO1 (Figure 3-6).
• In INTPLL2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output. Externally, this is identical to INTIO2
(Figure 3-7).
DS39778E-page 43
PIC18F87J11 FAMILY
3.5.3
INTERNAL OSCILLATOR OUTPUT
FREQUENCY AND TUNING
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8 MHz. It
can be adjusted in the user’s application by writing to
TUN (OSCTUNE) in the OSCTUNE
register (Register 3-2).
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. The
oscillator will stabilize within 1 ms. Code execution
continues during this shift and there is no indication that
the shift has occurred.
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC or vice versa. The frequency of
INTRC is not affected by OSCTUNE.
3.5.4
INTOSC FREQUENCY DRIFT
The INTOSC frequency may drift as VDD or temperature changes, and can affect the controller operation in
a variety of ways. It is possible to adjust the INTOSC
frequency by modifying the value in the OSCTUNE register. Depending on the device, this may have no effect
on the INTRC clock source frequency.
Tuning INTOSC requires knowing when to make the
adjustment, in which direction it should be made, and in
some cases, how large a change is needed. Three
compensation techniques are shown here.
3.5.4.1
Compensating with the EUSARTx
An adjustment may be required when the EUSARTx
begins to generate Framing Errors or receives data
with errors while in Asynchronous mode. Framing
Errors indicate that the device clock frequency is too
high. To adjust for this, decrement the value in
OSCTUNE to reduce the clock frequency. On the other
hand, errors in data may suggest that the clock speed
is too low. To compensate, increment OSCTUNE to
increase the clock frequency.
3.5.4.2
Compensating with the Timers
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is much greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
DS39778E-page 44
3.5.4.3
Compensating with the CCP Module
in Capture Mode
A CCP module can use free-running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast. To compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow. To compensate, increment the OSCTUNE
register.
3.6
Reference Clock Output
In addition to the FOSC/4 clock output in certain oscillator modes, the device clock in the PIC18F87J11 family
can also be configured to provide a reference clock output signal to a port pin. This feature is available in all
oscillator configurations and allows the user to select a
greater range of clock sub-multiples to drive external
devices in the application.
This reference clock output is controlled by the
REFOCON register (Register 3-3). Setting the ROON
bit (REFOCON) makes the clock signal available
on the REFO (RE3) pin. The RODIV bits enable
the selection of 16 different clock divider options.
The ROSSLP and ROSEL bits (REFOCON) control the availability of the reference output during Sleep
mode. The ROSEL bit determines if the oscillator on
OSC1 and OSC2, or the current system clock source,
is used for the reference clock output. The ROSSLP bit
determines if the reference source is available on RE3
when the device is in Sleep mode.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for an EC or HS mode;
otherwise, the oscillator on OSC1 and OSC2 will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
The REFOCON register is an alternate SFR and
shares the same memory address as the OSCCON
register. It is accessed by setting the ADSHR bit in the
WDTCON register (WDTCON).
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 3-3:
R/W-0
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
U-0
ROON
—
R/W-0
ROSSLP
R/W-0
(1)
ROSEL
R/W-0
R/W-0
R/W-0
R/W-0
RODIV3
RODIV2
RODIV1
RODIV0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ROON: Reference Oscillator Output Enable bit
1 = Reference oscillator output is available on REFO pin
0 = Reference oscillator output is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
ROSSLP: Reference Oscillator Output Stop in Sleep bit
1 = Reference oscillator continues to run in Sleep
0 = Reference oscillator is disabled in Sleep
bit 4
ROSEL: Reference Oscillator Source Select bit(1)
1 = Primary oscillator (EC or HS) is used as the base clock
0 = System clock is used as the base clock; base clock reflects any clock switching of the device
bit 3-0
RODIV: Reference Oscillator Divisor Select bits
1111 = Base clock value divided by 32,768
1110 = Base clock value divided by 16,384
1101 = Base clock value divided by 8,192
1100 = Base clock value divided by 4,096
1011 = Base clock value divided by 2,048
1010 = Base clock value divided by 1,024
1001 = Base clock value divided by 512
1000 = Base clock value divided by 256
0111 = Base clock value divided by 128
0110 = Base clock value divided by 64
0101 = Base clock value divided by 32
0100 = Base clock value divided by 16
0011 = Base clock value divided by 8
0010 = Base clock value divided by 4
0001 = Base clock value divided by 2
0000 = Base clock value
Note 1:
If ROSEL = 1, an EC or HS oscillator must be configured as the default oscillator with the FOSCx
Configuration bits to maintain clock output during Sleep mode.
2007-2012 Microchip Technology Inc.
DS39778E-page 45
PIC18F87J11 FAMILY
3.7
Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In RC_RUN and RC_IDLE modes, the internal
oscillator provides the device clock source. The 31 kHz
INTRC output can be used directly to provide the clock
and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 25.2 “Watchdog Timer (WDT)” through
Section 25.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
TABLE 3-3:
Timer1 oscillator may be operating to support a RealTime Clock (RTC). Other features may be operating
that do not require a device clock source (i.e., MSSP
slave, PSP, INTx pins and others). Peripherals that
may add significant current consumption are listed in
Section 28.2, DC Characteristics: Power-Down and
Supply Current PIC18F87J11 Family (Industrial).
3.8
Power-up Delays
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applications. The delays ensure that the device is kept in
Reset until the device power supply is stable under normal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 5.6 “Power-up Timer (PWRT)”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (Parameter 33,
Table 28-13); it is always enabled.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS modes). The OST does
this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
There is a delay of interval, TCSD (Parameter 38,
Table 28-13), following POR, while the controller
becomes ready to execute instructions.
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode
OSC1 Pin
OSC2 Pin
EC, ECPLL
Floating, pulled by external clock
At logic low (clock/4 output)
HS, HSPLL
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
INTOSC, INTPLL1/2
I/O pin, RA6, direction controlled by
TRISA
I/O pin RA6, direction controlled by
TRISA
Note:
See Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.
DS39778E-page 46
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
4.0
4.1.1
POWER-MANAGED MODES
CLOCK SOURCES
The PIC18F87J11 family of devices provides the ability
to manage power consumption by simply managing
clocking to the CPU and the peripherals. In general, a
lower clock frequency and a reduction in the number of
circuits being clocked, constitutes lower consumed
power. For the sake of managing power in an
application, there are three primary modes of operation:
The SCS bits allow the selection of one of three
clock sources for power-managed modes. They are:
• Run mode
• Idle mode
• Sleep mode
4.1.2
• The primary clock, as defined by the FOSC
Configuration bits
• The secondary clock (Timer1 oscillator)
• The internal oscillator
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 4.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
These modes define which portions of the device are
clocked and at what speed. The Run and Idle modes
may use any of the three available clock sources (primary, secondary or internal oscillator block); the Sleep
mode does not use a clock source.
The power-managed modes include several
power-saving features offered on previous devices.
One is the clock switching feature, offered in other
PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC® MCU
devices, where all device clocks are stopped.
4.1
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
Selecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions: if the CPU is to be clocked or not and which
clock source is to be used. The IDLEN bit
(OSCCON) controls CPU clocking, while the
SCS bits (OSCCON) select the clock
source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table 4-1.
TABLE 4-1:
ENTERING POWER-MANAGED
MODES
POWER-MANAGED MODES
OSCCON
Mode
(1)
IDLEN
Module Clocking
Available Clock and Oscillator Source
SCS
CPU
Peripherals
0
N/A
Off
Off
PRI_RUN
N/A
10
Clocked
Clocked
Primary – HS, EC, HSPLL, ECPLL, INTOSC oscillator;
this is the normal, full-power execution mode
SEC_RUN
N/A
01
Clocked
Clocked
Secondary – Timer1 oscillator
RC_RUN
N/A
11
Clocked
Clocked
Internal oscillator block(2)
PRI_IDLE
1
10
Off
Clocked
Primary – HS, EC, HSPLL, ECPLL, INTOSC
SEC_IDLE
1
01
Off
Clocked
Secondary – Timer1 oscillator
RC_IDLE
1
11
Off
Clocked
Internal oscillator block(2)
Sleep
Note 1:
2:
None – All clocks are disabled
IDLEN reflects its value when the SLEEP instruction is executed.
Includes the INTRC and INTOSC postcaler (internal oscillator block).
2007-2012 Microchip Technology Inc.
DS39778E-page 47
PIC18F87J11 FAMILY
4.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Two bits indicate the current clock source and its status:
OSTS (OSCCON) and T1RUN (T1CON). In
general, only one of these bits will be set while in a given
power-managed mode. When the OSTS bit is set, the
primary clock is providing the device clock. When the
T1RUN bit is set, the Timer1 oscillator is providing the
clock. If neither of these bits is set, INTRC is clocking the
device.
Note:
4.1.4
Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
DS39778E-page 48
4.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
4.2.1
PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 25.4 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set (see
Section 3.2 “Control Registers”).
4.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high-accuracy clock source.
SEC_RUN mode is entered by setting the SCS
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 4-1). The primary oscillator is shut down, the T1RUN bit (T1CON) is set and
the OSTS bit is cleared.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the
oscillator has started. In such situations, initial oscillator operation is far from stable and
unpredictable operation may result.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
FIGURE 4-1:
Figure 4-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCSx bits are not affected by the wake-up; the Timer1
oscillator continues to run.
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
1
T1OSI
2
3
n-1
Q3
Q4
Q1
Q2
Q3
n
Clock Transition
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
PC
FIGURE 4-2:
PC + 2
PC + 4
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
2
n-1 n
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC
SCS Bits Changed
PC + 4
OSTS Bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2007-2012 Microchip Technology Inc.
DS39778E-page 49
PIC18F87J11 FAMILY
4.2.3
RC_RUN MODE
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
block while the primary clock is started. When the
primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4). When the clock
switch is complete, the OSTS bit is set and the primary
clock is providing the device clock. The IDLEN and
SCSx bits are not affected by the switch. The INTRC
block source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conservation of all the Run modes while still executing code.
It works well for user applications which are not highly
timing-sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting SCS to ‘11’.
When the clock source is switched to the internal
oscillator block (see Figure 4-3), the primary oscillator
is shut down and the OSTS bit is cleared.
FIGURE 4-3:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
1
INTRC
2
3
n-1
Q3
Q4
Q1
Q2
Q3
n
Clock Transition
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
FIGURE 4-4:
PC
PC + 2
PC + 4
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q1
Q2
Q3
Q4
Q2 Q3 Q4 Q1 Q2 Q3
Q1
INTRC
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
2
n-1 n
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC
SCS Bits Changed
PC + 4
OSTS Bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39778E-page 50
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
4.3
Sleep Mode
4.4
The power-managed Sleep mode is identical to the legacy Sleep mode offered in all other PIC devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 4-5). All
clock source status bits are cleared.
Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
Entering Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS bits
becomes ready (see Figure 4-6), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
(see Section 25.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCSx
bits are not affected by the wake-up.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(Parameter 38, Table 28-13) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCSx bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode,
currently specified by the SCS bits.
FIGURE 4-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC + 2
PC
FIGURE 4-6:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
OSC1
PLL Clock
Output
TOST(1)
TPLL(1)
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
PC + 2
PC + 4
PC + 6
OSTS Bit Set
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2007-2012 Microchip Technology Inc.
DS39778E-page 51
PIC18F87J11 FAMILY
4.4.1
PRI_IDLE MODE
4.4.2
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing-sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN
first, then set the SCSx bits to ‘10’ and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC Configuration bits. The OSTS bit
remains set (see Figure 4-7).
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set IDLEN first, then
set SCS to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscillator, the
primary oscillator is shut down, the OSTS bit is cleared
and the T1RUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The
IDLEN and SCSx bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 4-8).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code execution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCSx bits are not affected by the wake-up (see
Figure 4-8).
FIGURE 4-7:
SEC_IDLE MODE
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE
mode. If the T1OSCEN bit is not set when
the SLEEP instruction is executed, the
SLEEP instruction will be ignored and
entry to SEC_IDLE mode will not occur. If
the Timer1 oscillator is enabled, but not
yet running, peripheral clocks will be
delayed until the oscillator has started. In
such situations, initial oscillator operation
is far from stable and unpredictable
operation may result.
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q1
Q4
Q3
Q2
Q1
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
FIGURE 4-8:
PC
PC + 2
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Q2
Q3
Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
DS39778E-page 52
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
4.4.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the internal
oscillator block. This mode allows for controllable
power conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCSx bits and execute SLEEP. When the
clock source is switched to the INTOSC block, the primary oscillator is shut down and the OSTS bit is
cleared.
When a wake event occurs, the peripherals continue to
be clocked from the internal oscillator block. After a
delay of TCSD following the wake event, the CPU
begins executing code being clocked by the INTRC.
The IDLEN and SCSx bits are not affected by the
wake-up. The INTRC source will continue to run if
either the WDT or the Fail-Safe Clock Monitor is
enabled.
4.5
Exiting Idle and Sleep Modes
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes sections (see Section 4.2 “Run Modes”,
Section 4.3 “Sleep Mode” and Section 4.4 “Idle
Modes”).
4.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON) is set. Otherwise, code
execution continues or resumes without branching
(see Section 10.0 “Interrupts”).
4.5.2
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 4.2 “Run
Modes” and Section 4.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 25.2 “Watchdog
Timer (WDT)”).
The Watchdog Timer and postscaler are cleared by one
of the following events:
• Executing a SLEEP or CLRWDT instruction
• The loss of a currently selected clock source (if
the Fail-Safe Clock Monitor is enabled)
4.5.3
EXIT BY RESET
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
4.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped
• The primary clock source is either the EC or
ECPLL mode
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC). However, a
fixed delay of interval, TCSD, following the wake event,
is still required when leaving Sleep and Idle modes to
allow the CPU to prepare for execution. Instruction
execution resumes on the first clock cycle following this
delay.
A fixed delay of interval, TCSD, following the wake event
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
2007-2012 Microchip Technology Inc.
DS39778E-page 53
PIC18F87J11 FAMILY
NOTES:
DS39778E-page 54
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
5.0
RESET
The PIC18F87J11 family of devices differentiate
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
i)
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Configuration Mismatch (CM)
Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.6.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 25.2 “Watchdog
Timer (WDT)”.
FIGURE 5-1:
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 5-1.
5.1
RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 5.7 “Reset State of Registers”.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 10.0 “Interrupts”.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET Instruction
Configuration Word Mismatch
Stack
Pointer
Stack Full/Underflow Reset
External Reset
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD Rise POR Pulse
Detect
VDD
Brown-out
Reset(1)
S
PWRT
32 s
INTRC
Note 1:
PWRT
66 ms
11-Bit Ripple Counter
R
Q
Chip_Reset
The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip
voltage regulator when there is insufficient source voltage to maintain regulation.
2007-2012 Microchip Technology Inc.
DS39778E-page 55
PIC18F87J11 FAMILY
REGISTER 5-1:
RCON: RESET CONTROL REGISTER
R/W-0
U-0
R/W-1
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
—
CM
RI
TO
PD
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enables priority levels on interrupts
0 = Disables priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
Unimplemented: Read as ‘0’
bit 5
CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has not occurred
0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration
Mismatch Reset occurs)
bit 4
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed, causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3
TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2
PD: Power-Down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1
POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent
Power-on Resets may be detected.
2: If the on-chip voltage regulator is disabled, BOR remains at ‘0’ at all times. See Section 5.4.1 “Detecting
BOR” for more information.
3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).
DS39778E-page 56
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
5.2
Master Clear (MCLR)
FIGURE 5-2:
The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR Reset path
which detects and ignores small pulses.
5.3
D
MCLR
C
Power-on Reset events are captured by the POR bit
(RCON). The state of the bit is set to ‘0’ whenever
a Power-on Reset occurs; it does not change for any
other Reset event. POR is not reset to ‘1’ by any
hardware event. To capture multiple events, the user
manually resets the bit to ‘1’ in software following any
Power-on Reset.
5.4
Brown-out Reset (BOR)
The PIC18F87J11 family of devices incorporates a
simple Brown-out Reset function when the internal regulator is enabled (ENVREG pin is tied to VDD). Any
drop of VDD below VBOR (Parameter D005) for greater
than time, TBOR, will reset the device. A Reset may or
may not occur if VDD falls below VBOR for less than
TBOR. The chip will remain in Brown-out Reset until
VDD rises above VBOR.
Once a Brown-out Reset has occurred, the Power-up
Timer will keep the chip in Reset for TPWRT
(Parameter 33). If VDD drops below VBOR while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once VDD rises above VBOR, the Power-up
Timer will execute the additional time delay.
2007-2012 Microchip Technology Inc.
PIC18F87J11
Note 1:
External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode, D, helps discharge the capacitor
quickly when VDD powers down.
2:
R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3:
R1 1 k will limit any current flowing into
MCLR from external capacitor, C, in the event
of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k to 10 k) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (Parameter D004). For a slow rise
time, see Figure 5-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
R
R1
Power-on Reset (POR)
A Power-on Reset condition is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
VDD
VDD
The MCLR pin is not driven low by any internal Resets,
including the WDT.
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
5.4.1
DETECTING BOR
The BOR bit always resets to ‘0’ on any Brown-out
Reset or Power-on Reset event. This makes it difficult
to determine if a Brown-out Reset event has occurred
just by reading the state of BOR alone. A more reliable
method is to simultaneously check the state of both
POR and BOR. This assumes that the POR bit is reset
to ‘1’ in software immediately after any Power-on Reset
event. If BOR is ‘0’ while POR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
If the voltage regulator is disabled, Brown-out Reset
functionality is disabled. In this case, the BOR bit
cannot be used to determine a Brown-out Reset event.
The BOR bit is still cleared by a Power-on Reset event.
5.5
Configuration Mismatch (CM)
The Configuration Mismatch (CM) Reset is designed to
detect and attempt to recover from random, memory
corrupting events. These include Electrostatic Discharge
(ESD) events, which can cause widespread, single bit
changes throughout the device and result in catastrophic
failure.
In PIC18FXXJ Flash devices, the device Configuration
registers (located in the configuration memory space)
are continuously monitored during operation by
comparing their values to complimentary shadow registers. If a mismatch is detected between the two sets
of registers, a CM Reset automatically occurs. These
events are captured by the CM bit (RCON). The
state of the bit is set to ‘0’ whenever a CM event occurs;
it does not change for any other Reset event.
DS39778E-page 57
PIC18F87J11 FAMILY
A CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT time-out or Stack Event
Resets. As with all hard and power Reset events, the
device Configuration Words are reloaded from the
Flash Configuration Words in program memory as the
device restarts.
5.6
Power-up Timer (PWRT)
PIC18F87J11 family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is always enabled. The
main function is to ensure that the device voltage is
stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F87J11 family devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32 s = 66 ms. While the PWRT
is counting, the device is held in Reset.
TABLE 5-1:
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC Parameter 33 for details.
5.6.1
TIME-OUT SEQUENCE
If enabled, the PWRT time-out is invoked after the POR
pulse has cleared. The total time-out will vary based on
the status of the PWRT. Figure 5-3, Figure 5-4,
Figure 5-5 and Figure 5-6 all depict time-out
sequences on power-up with the Power-up Timer
enabled.
Since the time-outs occur from the POR pulse and if
MCLR is kept low long enough, the PWRT will expire.
Bringing MCLR high will begin execution immediately
(Figure 5-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXXXX device
operating in parallel.
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2) and Brown-out Reset
Oscillator
Configuration
HSPLL
PWRTEN = 0
66
HS, XT, LP
ms(1)
66
+ 1024 TOSC + 2
ms(1)
ms(2)
1024 TOSC + 2 ms(2)
1024 TOSC + 2 ms(2)
1024 TOSC
1024 TOSC
EC, ECIO
66
ms(1)
—
—
RC, RCIO
66 ms(1)
—
—
ms(1)
—
—
INTIO1, INTIO2
Note 1:
2:
+ 1024 TOSC
PWRTEN = 1
Exit from
Power-Managed Mode
66
66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2 ms is the nominal time required for the PLL to lock.
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
FIGURE 5-3:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
DS39778E-page 58
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 5-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 5-5:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 5-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
3.3V
VDD
0V
1V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
2007-2012 Microchip Technology Inc.
DS39778E-page 59
PIC18F87J11 FAMILY
5.7
different Reset situations, as indicated in Table 5-2.
These bits are used in software to determine the nature
of the Reset.
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Table 5-3 describes the Reset states for all of the
Special Function Registers (SFRs). These are
categorized by Power-on and Brown-out Resets,
Master Clear and WDT Resets, and WDT wake-ups.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register (CM, RI,
TO, PD, POR and BOR) are set or cleared differently in
TABLE 5-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
RCON Register
STKPTR Register
Program
Counter(1)
CM
RI
TO
PD
POR
BOR
STKFUL
STKUNF
Power-on Reset
0000h
1
1
1
1
0
0
0
0
RESET instruction
0000h
u
0
u
u
u
u
u
u
Brown-out Reset
0000h
1
1
1
1
u
0
u
u
Configuration Mismatch Reset
0000h
0
u
u
u
u
u
u
u
MCLR Reset during
power-managed Run modes
0000h
u
u
1
u
u
u
u
u
MCLR Reset during
power-managed Idle modes
and Sleep mode
0000h
u
u
1
0
u
u
u
u
MCLR Reset during full-power
execution
0000h
u
u
u
u
u
u
u
u
Stack Full Reset (STVREN = 1)
0000h
u
u
u
u
u
u
1
u
Stack Underflow Reset
(STVREN = 1)
0000h
u
u
u
u
u
u
u
1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
u
u
u
u
u
u
u
1
WDT time-out during full-power
or power-managed Run modes
0000h
u
u
0
u
u
u
u
u
WDT time-out during
power-managed Idle or Sleep
modes
PC + 2
u
u
0
0
u
u
u
u
Interrupt exit from
power-managed modes
PC + 2
u
u
u
0
u
u
u
u
Condition
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
DS39778E-page 60
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 5-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS(4)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Resets
TOSU
PIC18F6XJ1X PIC18F8XJ1X
---0 0000
---0 0000
---0 uuuu(1)
TOSH
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu(1)
TOSL
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu(1)
STKPTR
PIC18F6XJ1X PIC18F8XJ1X
00-0 0000
uu-0 0000
uu-u uuuu(1)
PCLATU
PIC18F6XJ1X PIC18F8XJ1X
---0 0000
---0 0000
---u uuuu
PCLATH
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PCL
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
PC + 2(2)
TBLPTRU
PIC18F6XJ1X PIC18F8XJ1X
--00 0000
--00 0000
--uu uuuu
TBLPTRH
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
TABLAT
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PRODH
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
PIC18F6XJ1X PIC18F8XJ1X
0000 000x
0000 000u
uuuu uuuu(3)
INTCON2
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
1111 1111
uuuu uuuu(3)
INTCON3
PIC18F6XJ1X PIC18F8XJ1X
1100 0000
1100 0000
uuuu uuuu(3)
INDF0
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
N/A
POSTINC0
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
N/A
Register
Wake-up via WDT
or Interrupt
POSTDEC0
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
N/A
PREINC0
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
N/A
PLUSW0
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
FSR0H
PIC18F6XJ1X PIC18F8XJ1X
---- xxxx
---- 0000
---- uuuu
FSR0L
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
N/A
POSTINC1
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
N/A
N/A
POSTDEC1
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
N/A
PREINC1
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
N/A
PLUSW1
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
FSR1H
PIC18F6XJ1X PIC18F8XJ1X
---- xxxx
---- 0000
---- uuuu
FSR1L
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
PIC18F6XJ1X PIC18F8XJ1X
---- 0000
---- 0000
---- uuuu
N/A
Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be effected (to cause wake-up).
4: See Table 5-2 for Reset value for specific conditions.
2007-2012 Microchip Technology Inc.
DS39778E-page 61
PIC18F87J11 FAMILY
INITIALIZATION CONDITIONS FOR ALL REGISTERS(4) (CONTINUED)
TABLE 5-3:
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Resets
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
Register
INDF2
Wake-up via WDT
or Interrupt
N/A
POSTINC2
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
N/A
POSTDEC2
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
N/A
PREINC2
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
N/A
PLUSW2
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
N/A
FSR2H
PIC18F6XJ1X PIC18F8XJ1X
---- xxxx
---- 0000
---- uuuu
FSR2L
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
PIC18F6XJ1X PIC18F8XJ1X
---x xxxx
---u uuuu
---u uuuu
TMR0H
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
TMR0L
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
1111 1111
uuuu uuuu
OSCCON
PIC18F6XJ1X PIC18F8XJ1X
0110 q100
0110 q100
0110 q10u
REFOCON
PIC18F6XJ1X PIC18F8XJ1X
0-00 0000
u-uu uuuu
u-uu uuuu
CM1CON
PIC18F6XJ1X PIC18F8XJ1X
0001 1111
0001 1111
uuuu uuuu
CM2CON
PIC18F6XJ1X PIC18F8XJ1X
0001 1111
0001 1111
uuuu uuuu
RCON
PIC18F6XJ1X PIC18F8XJ1X
0-11 1100
0-qq qquu
u-qq qquu
TMR1H
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
ODCON1
PIC18F6XJ1X PIC18F8XJ1X
---0 0000
---u uuuu
---u uuuu
TMR1L
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
ODCON2
PIC18F6XJ1X PIC18F8XJ1X
---- --00
---- --uu
---- --uu
T1CON
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
u0uu uuuu
uuuu uuuu
ODCON3
PIC18F6XJ1X PIC18F8XJ1X
---- --00
---- --uu
---- --uu
TMR2
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PADCFG1
PIC18F6XJ1X PIC18F8XJ1X
---- ---0
---- ---u
---- ---u
PR2
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
1111 1111
1111 1111
MEMCON
PIC18F6XJ1X PIC18F8XJ1X
0-00 --00
0-00 --00
u-uu --uu
T2CON
PIC18F6XJ1X PIC18F8XJ1X
-000 0000
-000 0000
-uuu uuuu
SSP1BUF
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSP1ADD
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
SSP1MSK
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
uuuu uuuu
uuuu uuuu
SSP1STAT
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
SSP1CON1
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
SSP1CON2
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
(4)
Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be effected (to cause wake-up).
4: See Table 5-2 for Reset value for specific conditions.
DS39778E-page 62
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 5-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS(4) (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Resets
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
ADCON1
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
ANCON0
PIC18F6XJ1X PIC18F8XJ1X
00-0 0000
uu-u uuuu
uu-u uuuu
ANCON1
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
uuuu uuuu
uuuu uuuu
WDTCON
PIC18F6XJ1X PIC18F8XJ1X
0x-0 ---0
0x-u ---0
ux-u ---u
ECCP1AS
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
ECCP1DEL
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
CCPR1H
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
ECCP2AS
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
ECCP2DEL
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
CCPR2H
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
ECCP3AS
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
ECCP3DEL
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
CCPR3H
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR3L
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP3CON
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
SPBRG1
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
RCREG1
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
TXREG1
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXSTA1
PIC18F6XJ1X PIC18F8XJ1X
0000 0010
0000 0010
uuuu uuuu
RCSTA1
PIC18F6XJ1X PIC18F8XJ1X
0000 000x
0000 000x
uuuu uuuu
SPBRG2
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
RCREG2
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
TXREG2
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
TXSTA2
PIC18F6XJ1X PIC18F8XJ1X
0000 0010
0000 0010
uuuu uuuu
EECON2
PIC18F6XJ1X PIC18F8XJ1X
---- ----
---- ----
---- ----
EECON1
PIC18F6XJ1X PIC18F8XJ1X
--00 x00-
--00 u00-
--00 u00-
Register
ADRESH
Wake-up via WDT
or Interrupt
Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be effected (to cause wake-up).
4: See Table 5-2 for Reset value for specific conditions.
2007-2012 Microchip Technology Inc.
DS39778E-page 63
PIC18F87J11 FAMILY
INITIALIZATION CONDITIONS FOR ALL REGISTERS(4) (CONTINUED)
TABLE 5-3:
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Resets
IPR3
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
1111 1111
uuuu uuuu
PIR3
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu(3)
PIE3
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
IPR2
PIC18F6XJ1X PIC18F8XJ1X
111- 1111
111- 1111
uuu- uuuu
PIR2
PIC18F6XJ1X PIC18F8XJ1X
000- 0000
000- 0000
uuu- uuuu(3)
PIE2
PIC18F6XJ1X PIC18F8XJ1X
000- 0000
000- 0000
uuu- uuuu
IPR1
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
1111 1111
uuuu uuuu
PIR1
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu(3)
PIE1
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
RCSTA2
PIC18F6XJ1X PIC18F8XJ1X
0000 000x
0000 000x
uuuu uuuu
OSCTUNE
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
TRISJ
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
1111 1111
uuuu uuuu
TRISH
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
1111 1111
uuuu uuuu
TRISG
PIC18F6XJ1X PIC18F8XJ1X
---1 1111
---1 1111
---u uuuu
TRISF
PIC18F6XJ1X PIC18F8XJ1X
1111 111-
1111 111-
uuuu uuu-
TRISE
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
1111 1111
uuuu uuuu
TRISD
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
1111 1111
uuuu uuuu
TRISC
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
1111 1111
uuuu uuuu
TRISB
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
1111 1111
uuuu uuuu
TRISA
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
1111 1111
uuuu uuuu
LATJ
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATH
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATG
PIC18F6XJ1X PIC18F8XJ1X
---x xxxx
---u uuuu
---u uuuu
LATF
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxx-
uuuu uuu-
uuuu uuu-
LATE
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATD
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATA
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
Register
Wake-up via WDT
or Interrupt
Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be effected (to cause wake-up).
4: See Table 5-2 for Reset value for specific conditions.
DS39778E-page 64
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 5-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS(4) (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Resets
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTH
PIC18F6XJ1X PIC18F8XJ1X
0000 xxxx
uuuu uuuu
uuuu uuuu
PORTG
PIC18F6XJ1X PIC18F8XJ1X
000x xxxx
000u uuuu
uuuu uuuu
PORTF
PIC18F6XJ1X PIC18F8XJ1X
x001 100-
xuuu uuu-
xuuu uuu-
PORTE
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTD
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
PIC18F6XJ1X PIC18F8XJ1X
000x 0000
000u 0000
uuuu uuuu
SPBRGH1
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
BAUDCON1
PIC18F6XJ1X PIC18F8XJ1X
0100 0-00
0100 0-00
uuuu u-uu
SPBRGH2
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
BAUDCON2
PIC18F6XJ1X PIC18F8XJ1X
0100 0-00
0100 0-00
uuuu u-uu
TMR3H
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
uuuu uuuu
uuuu uuuu
TMR4
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PR4
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
1111 1111
1111 1111
CVRCON
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
T4CON
PIC18F6XJ1X PIC18F8XJ1X
-000 0000
-000 0000
-uuu uuuu
CCPR4H
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR4L
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP4CON
PIC18F6XJ1X PIC18F8XJ1X
--00 0000
--00 0000
--uu uuuu
CCPR5H
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR5L
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP5CON
PIC18F6XJ1X PIC18F8XJ1X
--00 0000
--00 0000
--uu uuuu
SSP2BUF
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSP2ADD
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
SSP2MSK
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
SSP2STAT
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
SSP2CON1
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
SSP2CON2
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
CMSTAT
PIC18F6XJ1X PIC18F8XJ1X
---- --11
---- --11
---- --uu
Register
PORTJ
Wake-up via WDT
or Interrupt
Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be effected (to cause wake-up).
4: See Table 5-2 for Reset value for specific conditions.
2007-2012 Microchip Technology Inc.
DS39778E-page 65
PIC18F87J11 FAMILY
INITIALIZATION CONDITIONS FOR ALL REGISTERS(4) (CONTINUED)
TABLE 5-3:
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Resets
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMDOUT1H
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMADDRL
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMDOUT1L
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMDIN1H
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMDIN1L
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMCONH
PIC18F6XJ1X PIC18F8XJ1X
0-00 0000
0-00 0000
u-uu uuuu
PMCONL
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMMODEH
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMMODEL
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMDOUT2H
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMDOUT2L
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMDIN2H
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMDIN2L
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMEH
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMEL
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
uuuu uuuu
PMSTATH
PIC18F6XJ1X PIC18F8XJ1X
00-- 0000
00-- 0000
uu-- uuuu
PMSTATL
PIC18F6XJ1X PIC18F8XJ1X
10-- 1111
10-- 1111
uu-- uuuu
Register
PMADDRH
Wake-up via WDT
or Interrupt
Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be effected (to cause wake-up).
4: See Table 5-2 for Reset value for specific conditions.
DS39778E-page 66
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
6.0
MEMORY ORGANIZATION
There are two types of memory in PIC18 Flash
microcontroller devices:
• Program Memory
• Data RAM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for
concurrent access of the two memory spaces.
Additional detailed information on the operation of the
Flash program memory is provided in Section 7.0
“Flash Program Memory”.
FIGURE 6-1:
6.1
Program Memory Organization
PIC18 microcontrollers implement a 21-bit Program
Counter (PC) which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOP instruction).
The entire PIC18F87J11 family of devices offers three
different on-chip Flash program memory sizes, from
64 Kbytes (up to 16,384 single-word instructions) to
128 Kbytes (65,536 single-word instructions). The
program memory maps for individual family members
are shown in Figure 6-3.
MEMORY MAPS FOR PIC18F87J11 FAMILY DEVICES
PC
CALL, CALLW, RCALL,
RETURN, RETFIE, RETLW,
ADDULNK, SUBULNK
21
Stack Level 1
Stack Level 31
PIC18FX6J11
PIC18FX6J16
PIC18FX7J11
On-Chip
Memory
On-Chip
Memory
On-Chip
Memory
Config. Words
000000h
00FFFFh
Config. Words
Config. Words
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
01FFFFh
User Memory Space
017FFFh
1FFFFFF
Note:
Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.
2007-2012 Microchip Technology Inc.
DS39778E-page 67
PIC18F87J11 FAMILY
6.1.1
HARD MEMORY VECTORS
6.1.2
FLASH CONFIGURATION WORDS
All PIC18 devices have a total of three hard-coded
return vectors in their program memory space. The
Reset vector address is the default value to which the
Program Counter returns on all device Resets; it is
located at 0000h.
Because PIC18F87J11 family devices do not have
persistent configuration memory, the top four words of
on-chip program memory are reserved for configuration
information. On Reset, the configuration information is
copied into the Configuration registers.
PIC18 devices also have two interrupt vector
addresses for the handling of high-priority and
low-priority interrupts. The high-priority interrupt vector
is located at 0008h and the low-priority interrupt vector
is at 0018h. Their locations in relation to the program
memory map are shown in Figure 6-2.
The Configuration Words are stored in their program
memory location in numerical order, starting with the
lower byte of CONFIG1 at the lowest address and
ending with the upper byte of CONFIG4. For these
devices, only Configuration Words, CONFIG1 through
CONFIG3, are used; CONFIG4 is reserved. The actual
addresses of the Flash Configuration Word for devices
in the PIC18F87J11 family are shown in Table 6-1.
Their location in the memory map is shown with the
other memory vectors in Figure 6-2.
FIGURE 6-2:
HARD VECTOR AND
CONFIGURATION WORD
LOCATIONS FOR
PIC18F87J11 FAMILY
DEVICES
Reset Vector
0000h
High-Priority Interrupt Vector
0008h
Low-Priority Interrupt Vector
0018h
Additional details on the device Configuration Words
are provided in Section 25.1 “Configuration Bits”.
TABLE 6-1:
Device
PIC18F66J11
On-Chip
Program Memory
PIC18F86J11
PIC18F66J16
PIC18F86J16
PIC18F67J11
PIC18F87J11
Flash Configuration Words
FLASH CONFIGURATION
WORD FOR PIC18F87J11
FAMILY DEVICES
Program
Memory
(Kbytes)
Configuration
Word
Addresses
64
FFF8h to
FFFFh
96
17FF8h to
17FFFh
128
1FFF8h to
1FFFFh
(Top of Memory-7)
(Top of Memory)
Read as ‘0’
1FFFFFh
Legend:
(Top of Memory) represents upper boundary
of on-chip program memory space (see
Figure 6-1 for device-specific values).
Shaded area represents unimplemented
memory. Areas are not shown to scale.
DS39778E-page 68
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
6.1.3
PIC18F8XJ11/8XJ16 PROGRAM
MEMORY MODES
• The Extended Microcontroller Mode allows
access to both internal and external program
memories as a single block. The device can
access its entire on-chip program memory; above
this, the device accesses external program
memory up to the 2-Mbyte program space limit.
Execution automatically switches between the
two memories as required.
The 80-pin devices in this family can address up to a
total of 2 Mbytes of program memory. This is achieved
through the External Memory Bus (EMB). There are two
distinct operating modes available to the controllers:
• Microcontroller (MC)
• Extended Microcontroller (EMC)
The setting of the EMBx Configuration bits also controls the address bus width of the External Memory
Bus. This is covered in more detail in Section 8.0
“External Memory Bus”.
The program memory mode is determined by setting
the EMBx Configuration bits (CONFIG3L), as
shown in Register 6-1. (See also Section 25.1
“Configuration Bits” for additional details on the
device Configuration bits.)
In all modes, the microcontroller has complete access
to data RAM.
The program memory modes operate as follows:
Figure 6-3 compares the memory maps of the different
program memory modes. The differences between
on-chip and external memory access limitations are
more fully explained in Table 6-2.
• The Microcontroller Mode accesses only on-chip
Flash memory. Attempts to read above the top of
on-chip memory causes a read of all ‘0’s (a NOP
instruction).
The Microcontroller mode is also the only operating
mode available to 64-pin devices.
REGISTER 6-1:
CONFIG3L: CONFIGURATION REGISTER 3 LOW
R/WO-1
R/WO-1
R/WO-1
R/WO-1
R/WO-1
U-0
U-0
U-0
WAIT(1)
BW(1)
EMB1(1)
EMB0(1)
EASHFT(1)
—
—
—
bit 7
bit 0
Legend:
WO = Write-Once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WAIT: External Bus Wait Enable bit(1)
1 = Wait states on the external bus are disabled
0 = Wait states on the external bus are enabled and selected by MEMCON
bit 6
BW: Data Bus Width Select bit(1)
1 = 16-Bit Data Width modes
0 = 8-Bit Data Width modes
bit 5-4
EMB1:EMB0: External Memory Bus Configuration bits(1)
11 = Microcontroller mode, external bus disabled
10 = Extended Microcontroller mode, 12-bit address width for external bus
01 = Extended Microcontroller mode, 16-bit address width for external bus
00 = Extended Microcontroller mode, 20-bit address width for external bus
bit 3
EASHFT: External Address Bus Shift Enable bit(1)
1 = Address shifting is enabled – external address bus is shifted to start at 000000h
0 = Address shifting is disabled – external address bus reflects the PC value
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
These bits are implemented only on 80-pin devices.
2007-2012 Microchip Technology Inc.
DS39778E-page 69
PIC18F87J11 FAMILY
6.1.4
EXTENDED MICROCONTROLLER
MODE AND ADDRESS SHIFTING
To avoid this, the Extended Microcontroller mode
implements an address shifting option to enable automatic address translation. In this mode, addresses
presented on the external bus are shifted down by the
size of the on-chip program memory and are remapped
to start at 0000h. This allows the complete use of the
external memory device’s memory space as an
extension of the device’s on-chip program memory.
By default, devices in Extended Microcontroller mode
directly present the Program Counter value on the
external address bus for those addresses in the range
of the external memory space. In practical terms, this
means addresses in the external memory device below
the top of on-chip memory are unavailable.
FIGURE 6-3:
MEMORY MAPS FOR PIC18F87J11 FAMILY PROGRAM MEMORY MODES
Microcontroller Mode(1)
On-Chip
Memory
Space
Extended Microcontroller Mode(2)
External
Memory
Space
On-Chip
Memory
Space
No
Access
On-Chip
Memory
Space
000000h
On-Chip
Program
Memory
On-Chip
Program
Memory
(Top of Memory)
(Top of Memory) + 1
(Top of Memory)
(Top of Memory) + 1
Reads
as ‘0’s
External
Memory
Space
000000h
000000h
On-Chip
Program
Memory
Extended Microcontroller Mode
with Address Shifting(2)
External
Memory
(Top of Memory)
(Top of Memory) + 1(3)
External
Memory
Mapped
to
External
Memory 1FFFFFh –
Space (Top of Memory)
Mapped
to
External
Memory
Space
1FFFFFh
1FFFFFh
1FFFFFh
Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure 6-1 for device-specific
values). Shaded areas represent unimplemented, or inaccessible areas, depending on the mode.
Note 1: This mode is the only available mode on 64-pin devices and the default mode on 80-pin devices.
2: These modes are only available on 80-pin devices.
3: Addresses starting at the top of the program memory are translated to start at 0000h of the external device whenever
the EASHFT Configuration bit is set.
TABLE 6-2:
MEMORY ACCESS FOR PIC18F8X11/8616 PROGRAM MEMORY MODES
Internal Program Memory
Operating Mode
External Program Memory
Execution
From
Table Read
From
Table Write
To
Execution
From
Table Read
From
Table Write
To
Microcontroller
Yes
Yes
Yes
No Access
No Access
No Access
Extended Microcontroller
Yes
Yes
Yes
Yes
Yes
Yes
DS39778E-page 70
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
6.1.5
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the Program Counter by any operation that writes
PCL. Similarly, the upper two bytes of the Program
Counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 6.1.8.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the Program Counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the Program Counter.
6.1.6
RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW
or a RETFIE instruction (and on ADDULNK and
SUBULNK instructions if the extended instruction set is
enabled). PCLATU and PCLATH are not affected by
any of the RETURN or CALL instructions.
FIGURE 6-4:
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
Top-of-Stack Special Function Registers. Data can also
be pushed to, or popped from, the stack using these
registers.
A CALL type instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
6.1.6.1
Top-of-Stack (TOS) Access
Only the top of the return address stack is readable and
writable. A set of three registers, TOSU:TOSH:TOSL,
hold the contents of the stack location pointed to by the
STKPTR register (Figure 6-4). This allows users to
implement a software stack if necessary. After a CALL,
RCALL or interrupt (and ADDULNK and SUBULNK
instructions if the extended instruction set is enabled),
the software can read the pushed value by reading the
TOSU:TOSH:TOSL registers. These values can be
placed on a user-defined software stack. At return
time, the software can return these values to
TOSU:TOSH:TOSL and do a return.
The user must disable the Global Interrupt Enable bits
while accessing the stack to prevent inadvertent stack
corruption.
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
Stack Pointer
Top-of-Stack Registers
TOSU
00h
TOSH
1Ah
11111
11110
11101
TOSL
34h
Top-of-Stack
2007-2012 Microchip Technology Inc.
001A34h
000D58h
STKPTR
00010
00011
00010
00001
00000
DS39778E-page 71
PIC18F87J11 FAMILY
6.1.6.2
Return Stack Pointer (STKPTR)
The STKPTR register (Register 6-2) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to
Section 25.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.
REGISTER 6-2:
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and set the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
Note:
6.1.6.3
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack, without disturbing normal program execution, is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
STKPTR: STACK POINTER REGISTER
R/C-0
R/C-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STKFUL(1)
STKUNF(1)
—
SP4
SP3
SP2
SP1
SP0
bit 7
bit 0
Legend:
C = Clearable Only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
STKFUL: Stack Full Flag bit(1)
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6
STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP: Stack Pointer Location bits
Note 1:
x = Bit is unknown
Bit 7 and bit 6 are cleared by user software or by a POR.
DS39778E-page 72
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
6.1.6.4
Stack Full and Underflow Resets
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 1L. When STVREN is set, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
6.1.7
FAST REGISTER STACK
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers to provide a “fast return”
option for interrupts. This stack is only one level deep
and is neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push values into the Stack registers. The values in
the registers are then loaded back into the working
registers if the RETFIE, FAST instruction is used to
return from the interrupt.
6.1.8
LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
6.1.8.1
Computed GOTO
A computed GOTO is accomplished by adding an offset
to the Program Counter. An example is shown in
Example 6-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value, ‘nn’, to the calling
function.
If both low and high-priority interrupts are enabled, the
Stack registers cannot be used reliably to return from
low-priority interrupts. If a high-priority interrupt occurs
while servicing a low-priority interrupt, the Stack
register values stored by the low-priority interrupt will
be overwritten. In these cases, users must save the key
registers in software during a low-priority interrupt.
The offset value (in WREG) specifies the number of
bytes that the Program Counter should advance and
should be multiples of 2 (LSb = 0).
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FAST instruction is then executed to restore
these registers from the Fast Register Stack.
EXAMPLE 6-2:
Example 6-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
EXAMPLE 6-1:
CALL SUB1, FAST
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
RETURN FAST
SUB1
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
2007-2012 Microchip Technology Inc.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
ORG
TABLE
6.1.8.2
MOVF
CALL
nn00h
ADDWF
RETLW
RETLW
RETLW
.
.
.
COMPUTED GOTO USING
AN OFFSET VALUE
OFFSET, W
TABLE
PCL
nnh
nnh
nnh
Table Reads
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored, two bytes per
program word, while programming. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from the
program memory. Data is transferred from program
memory, one byte at a time.
Table read operation is discussed further
Section 7.1 “Table Reads and Table Writes”.
in
DS39778E-page 73
PIC18F87J11 FAMILY
6.2
6.2.2
PIC18 Instruction Cycle
6.2.1
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction
cycle, while the decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the Program Counter to change
(e.g., GOTO), then two cycles are required to complete
the instruction (Example 6-3).
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping, quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the Program Counter
is incremented on every Q1. The instruction is fetched
from the program memory and latched into the Instruction Register (IR) during Q4. The instruction is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 6-5.
FIGURE 6-5:
INSTRUCTION FLOW/PIPELINING
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
PC
PC + 2
PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC)
EXAMPLE 6-3:
1. MOVLW 55h
Execute INST (PC + 2)
Fetch INST (PC + 4)
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
Fetch 1
Execute 1
2. MOVWF PORTB
3. BRA SUB_1
4. BSF
Execute INST (PC)
Fetch INST (PC + 2)
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
Fetch 2
TCY2
TCY3
TCY4
TCY5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush (NOP)
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS39778E-page 74
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
6.2.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). To maintain alignment
with instruction boundaries, the PC increments in steps
of 2 and the LSB will always read ‘0’ (see Section 6.1.5
“Program Counter”).
Figure 6-6 shows an example of how instruction words
are stored in the program memory.
FIGURE 6-6:
INSTRUCTIONS IN PROGRAM MEMORY
Program Memory
Byte Locations
6.2.4
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruction. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC
which accesses the desired byte address in program
memory. Instruction #2 in Figure 6-6 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 26.0 “Instruction Set Summary”
provides further details of the instruction set.
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
Instruction 3:
MOVFF
123h, 456h
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence, immediately after the
first word, the data in the second word is accessed and
EXAMPLE 6-4:
LSB = 1
LSB = 0
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Word Address
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
used by the instruction sequence. If the first word is
skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 6-4 shows how this works.
Note:
See Section 6.5 “Program Memory and
the Extended Instruction Set” for
information on two-word instructions in
the extended instruction set.
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; No, skip this word
ADDWF
REG3
; continue code
1111 0100 0101 0110
0010 0100 0000 0000
; Execute this word as a NOP
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; Yes, execute this word
1111 0100 0101 0110
0010 0100 0000 0000
; 2nd word of instruction
ADDWF
2007-2012 Microchip Technology Inc.
REG3
; continue code
DS39778E-page 75
PIC18F87J11 FAMILY
6.3
Note:
Data Memory Organization
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 6.6 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. The
PIC18F87J11 family implements all available banks
and provide 3936 bytes of data memory available to the
user. Figure 6-7 shows the data memory organization
for the devices.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
section.
To ensure that commonly used registers (select SFRs
and select GPRs) can be accessed in a single cycle,
PIC18 devices implement an Access Bank. This is a
256-byte memory space that provides fast access to
select SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 6.3.2 “Access Bank”
provides a detailed description of the Access RAM.
6.3.1
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address. The instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR). The upper four bits
are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLB instruction.
The value of the BSR indicates the bank in data memory. The 8 bits in the instruction show the location in the
bank and can be thought of as an offset from the bank’s
lower boundary. The relationship between the BSR’s
value and the bank division in data memory is shown in
Figure 6-8.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 0Fh, will end up resetting the Program Counter.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 6-7 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
BANK SELECT REGISTER
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
DS39778E-page 76
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 6-7:
DATA MEMORY MAP FOR PIC18F87J11 FAMILY DEVICES
BSR
00h
= 0000
= 0001
= 0010
= 0011
= 0100
= 0101
= 0110
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
= 1111
Note 1:
2:
When a = 0:
Data Memory Map
Bank 0
FFh
00h
Bank 1
Access RAM
GPR
GPR
1FFh
200h
FFh
00h
Bank 2
GPR
FFh
00h
Bank 3
2FFh
300h
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are general
purpose RAM (from Bank 0).
The remaining 160 bytes are
Special Function Registers
(from Bank 15).
When a = 1:
The BSR specifies the bank
used by the instruction.
GPR
3FFh
400h
FFh
00h
Bank 4
GPR
FFh
00h
4FFh
500h
GPR
Bank 5
FFh
00h
5FFh
600h
GPR
Bank 6
FFh
00h
6FFh
700h
GPR
Bank 7
FFh
00h
7FFh
800h
GPR
Bank 8
FFh
00h
Bank 9
FFh
00h
Bank 10
GPR
GPR
FFh
00h
Bank 11
000h
05Fh
060h
0FFh
100h
GPR
FFh
00h
Bank 12
FFh
00h
Bank 13
FFh
00h
Bank 14
GPR
GPR
GPR
FFh
00h
GPR(1,2)
FFh
SFR
Bank 15
Access Bank
Access RAM Low
00h
5Fh
Access RAM High 60h
(SFRs)
FFh
8FFh
900h
9FFh
A00h
AFFh
B00h
BFFh
C00h
CFFh
D00h
DFFh
E00h
EFFh
F00h
F5Fh
F60h
FFFh
Addresses, F5Ah through F5Fh, are also used by SFRs, but are not part of the Access RAM. Users must
always use the complete address, or load the proper BSR value, to access these registers.
Addresses, F40h to F59h, are not implemented and are not accessible to the user.
2007-2012 Microchip Technology Inc.
DS39778E-page 77
PIC18F87J11 FAMILY
FIGURE 6-8:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
BSR(1)
7
0
0
0
0
0
0
0
1
0
000h
Data Memory
00h
Bank 0
100h
Bank 1
Bank Select(2)
200h
300h
Bank 2
FFh
00h
From Opcode(2)
7
1
1
1
1
1
1
0
1
1
FFh
00h
FFh
00h
Bank 3
through
Bank 13
E00h
Bank 14
F00h
FFFh
Note 1:
2:
6.3.2
Bank 15
FFh
00h
FFh
The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR)
to the registers of the Access Bank.
The MOVFF instruction embeds the entire 12-bit address in the instruction.
ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation, but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Bank 15. The lower half is known
as the “Access RAM” and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 6-7).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
DS39778E-page 78
FFh
00h
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 6.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
6.3.3
GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom
of the SFR area. GPRs are not initialized by a
Power-on Reset and are unchanged on all other
Resets.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
6.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers used
by the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of data
memory (FFFh) and extend downward to occupy more
than the top half of Bank 15 (F5Ah to FFFh). A list of these
registers is given inTable 6-3, Table 6-4 and Table 6-5.
section. Registers related to the operation of the
peripheral features are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s
Note:
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
TABLE 6-3:
Addresses, F5Ah through F5Fh, are not
part of the Access Bank. These registers
must always be accessed using the Bank
Select Register. Addresses, F40h to
F59h, are not implemented and are not
accessible to the user.
SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J11 FAMILY DEVICES
Address
Name
Address
FFFh
TOSU
FDFh
INDF2(1)
Name
POSTINC2(1)
FFEh
TOSH
FDEh
FFDh
TOSL
FDDh POSTDEC2(1)
FFCh
STKPTR
FDCh
FFBh
PCLATU
FFAh
FF9h
Address
FBFh
Name
ECCP1AS
Address
Name
Address
F9Fh
IPR1
F7Fh
SPBRGH1
Name
Address
Name
F5Fh
PMDIN2H
FBEh ECCP1DEL
F9Eh
PIR1
F7Eh
BAUDCON1
F5Eh
PMDIN2L
FBDh
CCPR1H
F9Dh
PIE1
F7Dh
SPBRGH2
F5Dh
PMEH
PREINC2(1)
FBCh
CCPR1L
F9Ch
RCSTA2
F7Ch
BAUDCON2
F5Ch
PMEL
FDBh
PLUSW2(1)
FBBh
CCP1CON
F9Bh
OSCTUNE
F7Bh
TMR3H
F5Bh
PMSTATH
PCLATH
FDAh
FSR2H
FBAh
ECCP2AS
F9Ah
TRISJ(2)
F7Ah
TMR3L
F5Ah
PMSTATL
PCL
FD9h
FSR2L
FB9h ECCP2DEL
F99h
TRISH(2)
F79h
T3CON
F59h
—
FF8h
TBLPTRU
FD8h
STATUS
FB8h
CCPR2H
F98h
TRISG
F78h
TMR4
F58h
—
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
CCPR2L
F97h
TRISF
F77h
PR4(3)
F57h
—
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
CCP2CON
F96h
TRISE
F76h
T4CON
F56h
—
FF5h
TABLAT
FD5h
T0CON
FB5h
ECCP3AS
F95h
TRISD
F75h
CCPR4H
F55h
—
FF4h
PRODH
FD4h
—
FB4h ECCP3DEL
F94h
TRISC
F74h
CCPR4L
F54h
—
FF3h
PRODL
FD3h
OSCCON(3)
FB3h
CCPR3H
F93h
TRISB
F73h
CCP4CON
F53h
—
FF2h
INTCON
FD2h
CM1CON
FB2h
CCPR3L
F92h
TRISA
F72h
CCPR5H
F52h
—
FF1h
INTCON2
FD1h
CM2CON
FB1h
CCP3CON
F91h
LATJ(2)
F71h
CCPR5L
F51h
—
FF0h
INTCON3
FD0h
RCON
FB0h
SPBRG1
F90h
LATH(2)
F70h
CCP5CON
F50h
—
FEFh
INDF0(1)
FCFh
TMR1H(3)
FAFh
RCREG1
F8Fh
LATG
F6Fh
SSP2BUF
F4Fh
—
FEEh
POSTINC0(1)
FCEh
TMR1L(3)
FAEh
TXREG1
F8Eh
LATF
F6Eh
SSP2ADD
F4Eh
—
FEDh POSTDEC0(1)
FCDh
T1CON(3)
FADh
TXSTA1
F8Dh
LATE
F6Dh
SSP2STAT
F4Dh
—
FECh
PREINC0(1)
FCCh
TMR2(3)
FACh
RCSTA1
F8Ch
LATD
F6Ch
SSP2CON1
F4Ch
—
FEBh
PLUSW0(1)
FCBh
PR2(3)
FABh
SPBRG2
F8Bh
LATC
F6Bh
SSP2CON2
F4Bh
—
FEAh
FSR0H
FCAh
T2CON
FAAh
RCREG2
F8Ah
LATB
F6Ah
CMSTAT
F4Ah
—
FE9h
FSR0L
FC9h
SSP1BUF
FA9h
TXREG2
F89h
LATA
F69h
PMADDRH(4)
F49h
—
FE8h
WREG
FC8h
SSP1ADD
FA8h
TXSTA2
F88h
PORTJ(2)
F68h
PMADDRL(4)
F48h
—
FE7h
INDF1(1)
FC7h
SSP1STAT
FA7h
EECON2
F87h
PORTH(2)
F67h
PMDIN1H
F47h
—
FE6h
POSTINC1(1)
FC6h
SSP1CON1
FA6h
EECON1
F86h
PORTG
F66h
PMDIN1L
F46h
—
FE5h POSTDEC1(1)
FC5h
SSP1CON2
FA5h
IPR3
F85h
PORTF
F65h
PMCONH
F45h
—
FE4h
PREINC1(1)
FC4h
ADRESH
FA4h
PIR3
F84h
PORTE
F64h
PMCONL
F44h
—
FE3h
PLUSW1(1)
FC3h
ADRESL
FA3h
PIE3
F83h
PORTD
F63h
PMMODEH
F43h
—
FE2h
FSR1H
FC2h
ADCON0(3)
FA2h
IPR2
F82h
PORTC
F62h
PMMODEL
F42h
—
FE1h
FSR1L
FC1h
ADCON1(3)
FA1h
PIR2
F81h
PORTB
F61h
PMDOUT2H
F41h
—
FE0h
BSR
FC0h
WDTCON
FA0h
PIE2
F80h
PORTA
F60h
PMDOUT2L
F40h
—
This is not a physical register.
This register is not available on 64-pin devices.
This register shares the same address with another register (see Table 6-4 for alternate register).
The PMADDRH/L and PMDOUT1H/L register pairs share the same address. PMADDR is used in Master modes and PMDOUT1 is used in
Slave modes.
5: Addresses, F40 to F59, are not implemented and are not accessible to the user.
Note 1:
2:
3:
4:
2007-2012 Microchip Technology Inc.
DS39778E-page 79
PIC18F87J11 FAMILY
6.3.4.1
Shared Address SFRs
6.3.4.2
In several locations in the SFR bank, a single address
is used to access two different hardware registers. In
these cases, a “legacy” register of the standard PIC18
SFR set (such as OSCCON, T1CON, etc.) shares its
address with an alternate register. These alternate registers are associated with enhanced configuration
options for peripherals or with new device features not
included in the standard PIC18 SFR map. A complete
list of shared register addresses and the registers
associated with them is provided in Table 6-4.
Access to the alternate registers is enabled in software
by setting the ADSHR bit in the WDTCON register
(Register 6-3). ADSHR must be manually set or
cleared to access the alternate or legacy registers, as
required. Since the bit remains in a given state until
changed, users should always verify the state of
ADSHR before writing to any of the shared SFR
addresses.
TABLE 6-4:
Address
Name
(D)
OSCCON
(A)
REFOCON
FCFh
(D)
TMR1H
(A)
ODCON1
(D)
TMR1L
(A)
In addition to the shared address SFRs, there are
several registers that share the same address in the
SFR space, but are not accessed with the ADSHR bit.
Instead, the register’s definition and use depends on
the operating mode of its associated peripheral. These
registers are:
• SSPxADD and SSPxMSK: These are two
separate hardware registers, accessed through a
single SFR address. The operating mode of the
MSSPx module determines which register is
being accessed. See Section 20.4.3.4 “7-Bit
Address Masking Mode” for additional details.
• PMADDRH/L and PMDOUT2H/L: In this case,
these named buffer pairs are actually the same
physical registers. The PMP module’s operating
mode determines what function the registers take
on. See Section 12.1.2 “Data Registers” for
additional details.
SHARED SFR ADDRESSES FOR PIC18F87J11 FAMILY DEVICES
FD3h
FCEh
Context Defined SFRs
Address
Name
Address
FCDh
(D)
T1CON
(A)
ODCON3
FCCh
(D)
TMR2
(A)
PADCFG1
(D)
PR2
FCBh
ODCON2
(A)
(D)
ADCON0
(A)
ANCON1
FC1h
(D)
ADCON1
(A)
ANCON0
(D)
PR4
(A)
CVRCON
F77h
(1)
MEMCON
Name
FC2h
Legend: (D) = Default SFR, accessible only when ADSHR = 0; (A) = Alternate SFR, accessible only when ADSHR = 1.
Note 1: This bit is implemented in 80-pin devices only.
DS39778E-page 80
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 6-3:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0
R-x
U-0
R/W-0
U-0
U-0
U-0
U-0
REGSLP
LVDSTAT
—
ADSHR
—
—
—
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
REGSLP: Voltage Regulator Low-Power Operation Enable bit
For details of bit operation, see Register 25-9.
bit 6
LVDSTAT: LVD Status bit
1 = VDDCORE > 2.45V
0 = VDDCORE < 2.45V
bit 5
Unimplemented: Read as ‘0’
bit 4
ADSHR: Shared Address SFR Select bit
1 = Alternate SFR is selected
0 = Default (Legacy) SFR is selected
bit 3-1
Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit
For details of bit operation, see Register 25-9.
2007-2012 Microchip Technology Inc.
x = Bit is unknown
DS39778E-page 81
PIC18F87J11 FAMILY
TABLE 6-5:
File Name
REGISTER FILE SUMMARY (PIC18F87J11 FAMILY)
Bit 7
Bit 6
Bit 5
—
—
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Details
on
Page:
---0 0000
61, 71
TOSH
Top-of-Stack High Byte (TOS)
0000 0000
61, 71
TOSL
Top-of-Stack Low Byte (TOS)
0000 0000
61, 71
00-0 0000
61, 72
---0 0000
61, 71
61, 71
TOSU
STKPTR
STKFUL
STKUNF
—
PCLATU
—
—
bit 21(1)
Top-of-Stack Upper Byte (TOS)
Value on
POR, BOR
SP4
SP3
SP2
SP1
SP0
Holding Register for PC
PCLATH
Holding Register for PC
0000 0000
PCL
PC Low Byte (PC)
0000 0000
61, 71
--00 0000
61, 104
TBLPTRU
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR)
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR)
0000 0000
61, 104
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR)
0000 0000
61, 104
TABLAT
Program Memory Table Latch
0000 0000
61, 104
PRODH
Product Register High Byte
xxxx xxxx
61, 117
PRODL
Product Register Low Byte
xxxx xxxx
61, 117
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
61, 121
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
1111 1111
61, 121
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
INTCON3
1100 0000
61, 121
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
61, 89
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
61, 90
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
61, 90
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
61, 90
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
61, 90
FSR0H
---- 0000
61, 89
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
—
xxxx xxxx
61, 89
WREG
Working Register
xxxx xxxx
61, 73
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
61, 89
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
61, 90
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
61, 90
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
61, 90
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
61, 90
---- 0000
61, 89
xxxx xxxx
61, 89
---- 0000
61, 76
FSR1H
—
FSR1L
—
—
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
Indirect Data Memory Address Pointer 1 High Byte
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
62, 89
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
62, 90
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
62, 90
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
62, 90
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
62, 90
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
x = unknown; u = unchanged; — = unimplemented; q = value depends on condition; Bold = shared access SFRs
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address; available when WDTCON = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2 = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I2C™ Slave mode. See Section 20.4.3.2
“Address Masking Modes” for details.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 12.1.2 “Data Registers” for more information.
DS39778E-page 82
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 6-5:
File Name
FSR2H
FSR2L
REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
—
—
—
—
Bit 3
Bit 2
Bit 1
Bit 0
Indirect Data Memory Address Pointer 2 High Byte
Indirect Data Memory Address Pointer 2 Low Byte
STATUS
—
—
TMR0H
Timer0 Register High Byte
TMR0L
Timer0 Register Low Byte
—
N
OV
Z
DC
C
Value on
POR, BOR
Details
on
Page:
---- 0000
62, 89
xxxx xxxx
62, 89
---x xxxx
62, 87
0000 0000
62, 195
xxxx xxxx
62, 195
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
62, 194
OSCCON(2)/
IDLEN
IRCF2
IRCF1
IRCF0
OSTS(4)
—
SCS1
SCS0
0110 q100
62, 38
REFOCON(3)
ROON
—
ROSSLP
ROSEL
RODIV3
RODIV2
RODIV1
RODIV0
0-00 0000
62, 45
CM1CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
0001 1111
62, 320
CM2CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
0001 1111
62, 320
RCON
IPEN
—
CM
RI
TO
PD
POR
BOR
0-11 1100
60, 62,
133
xxxx xxxx
62, 198
—
CCP5OD
CCP4OD
ECCP3OD
ECCP2OD
T0CON
TMR1H(2)/
Timer1 Register High Byte
ODCON1(3)
TMR1L(2)/
—
—
ECCP1OD ---0 0000
62, 138
xxxx xxxx
62, 198
Timer1 Register Low Byte
ODCON2(3)
(2)
T1CON /
ODCON3(3)
TMR2(2)/
—
—
—
—
—
—
U2OD
U1OD
---- --00
62, 138
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
0000 0000
62, 198
—
—
—
—
—
—
SPI2OD
SPI1OD
---- --00
62, 138
0000 0000
62, 203
Timer2 Register
PADCFG1(3)
PR2(2)/
—
—
—
—
—
—
—
PMPTTL
Timer2 Period Register
MEMCON(3,7)
T2CON
EDBIS
—
—
WAIT1
WAIT0
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
---- ---0
62, 139
1111 1111
62, 203
62, 106
—
WM1
WM0
0-00 --00
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
62, 203
xxxx xxxx
62, 238,
248
SSP1BUF
MSSP1 Receive Buffer/Transmit Register
SSP1ADD/
MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode)
0000 0000
62, 248
SSP1MSK(5)
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
0000 0000
62, 255
SSP1STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
62, 239,
249
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
62, 240,
250
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN/
SEN
0000 0000
GCEN
ACKSTAT
ADMSK5(6)
ADMSK4(6)
ADMSK3(6)
ADMSK2(6)
ADMSK1(6)
SEN
62, 251,
283
ADRESH
A/D Result Register High Byte
xxxx xxxx
63, 309
ADRESL
A/D Result Register Low Byte
xxxx xxxx
63, 309
63, 309
ADCON0(2)/
VCFG1
VCFG0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
0000 0000
ANCON1(3)
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
0000 0000
63, 311
ADCON1(2)/
ADFM
ADCAL
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
0000 0000
63, 310
PCFG7
PCFG6
—
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
00-0 0000
63, 311
REGSLP
LVDSTAT
—
ADSHR
—
—
—
SWDTEN
0x-0 ---0
63, 339
ANCON0(3)
WDTCON
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
x = unknown; u = unchanged; — = unimplemented; q = value depends on condition; Bold = shared access SFRs
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address; available when WDTCON = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2 = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I2C™ Slave mode. See Section 20.4.3.2
“Address Masking Modes” for details.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 12.1.2 “Data Registers” for more information.
2007-2012 Microchip Technology Inc.
DS39778E-page 83
PIC18F87J11 FAMILY
TABLE 6-5:
File Name
ECCP1AS
REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0
ECCP1DEL
P1RSEN
P1DC6
P1DC5
P1DC4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
Page:
PSS1AC1
PSS1AC0
PSS1BD1
PSS1BD0
0000 0000
63, 235
P1DC3
P1DC2
P1DC1
P1DC0
0000 0000
63, 235
CCPR1H
Capture/Compare/PWM Register 1 HIgh Byte
xxxx xxxx
63, 235
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
63, 235
CCP1CON
P1M1
ECCP2AS
P1M0
DC1B1
DC1B0
ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0
ECCP2DEL
P2RSEN
P2DC6
P2DC5
P2DC4
CCP1M3
CCP1M2
CCP1M1
CCP1M0
0000 0000
63, 235
PSS2AC1
PSS2AC0
PSS2BD1
PSS2BD0
0000 0000
63, 235
P2DC3
P2DC2
P2DC1
P2DC0
0000 0000
63, 235
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx
63, 235
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx
63, 235
CCP2CON
P2M1
ECCP3AS
P2M0
DC2B1
DC2B0
ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0
ECCP3DEL
P3RSEN
P3DC6
P3DC5
P3DC4
CCP2M3
CCP2M2
CCP2M1
CCP2M0
0000 0000
63, 235
PSS3AC1
PSS3AC0
PSS3BD1
PSS3BD0
0000 0000
63, 235
P3DC3
P3DC2
P3DC1
P3DC0
0000 0000
63, 235
CCPR3H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
63, 235
CCPR3L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
63, 235
0000 0000
63, 235
CCP3CON
P3M1
P3M0
DC3B1
DC3B0
CCP3M3
CCP3M2
CCP3M1
CCP3M0
SPBRG1
EUSART1 Baud Rate Generator Register Low Byte
0000 0000
63, 289
RCREG1
EUSART1 Receive Register
0000 0000
63, 297,
299
TXREG1
EUSART1 Transmit Register
xxxx xxxx
63, 295,
296
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
63, 295
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
63, 297
SPBRG2
EUSART2 Baud Rate Generator Register Low Byte
0000 0000
63, 289
RCREG2
EUSART2 Receive Register
0000 0000
63, 297,
299
TXREG2
EUSART2 Transmit Register
0000 0000
63, 295,
296
0000 0010
63, 295
TXSTA2
EECON2
EECON1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Program Memory Control Register 2 (not a physical register)
---- ----
63, 96
—
—
WPROG
FREE
WRERR
WREN
WR
—
--00 x00-
63, 96
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
1111 1111
64, 130
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
0000 0000
64, 124
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
0000 0000
64, 127
IPR2
OSCFIP
CM2IP
CM1IP
—
BCL1IP
LVDIP
TMR3IP
CCP2IP
111- 1111
64, 130
PIR2
OSCFIF
CM2IF
CM1IF
—
BCL1IF
LVDIF
TMR3IF
CCP2IF
000- 0000
64, 124
PIE2
OSCFIE
CM2IE
CM1IE
—
BCL1IE
LVDIE
TMR3IE
CCP2IE
000- 0000
64, 127
IPR1
PMPIP
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
1111 1111
64, 130
PIR1
PMPIF
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
0000 0000
64, 124
PIE1
PMPIE
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
0000 0000
64, 127
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
64, 297
INTSRC
PLLEN
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
0000 0000
64, 39
OSCTUNE
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
x = unknown; u = unchanged; — = unimplemented; q = value depends on condition; Bold = shared access SFRs
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address; available when WDTCON = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2 = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I2C™ Slave mode. See Section 20.4.3.2
“Address Masking Modes” for details.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 12.1.2 “Data Registers” for more information.
DS39778E-page 84
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 6-5:
File Name
REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
Page:
64, 165
TRISJ(7)
TRISJ7
TRISJ6
TRISJ5
TRISJ4
TRISJ3
TRISJ2
TRISJ1
TRISJ0
1111 1111
TRISH(7)
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
1111 1111
64, 163
—
—
—
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
---1 1111
64, 160
TRISG
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
1111 111-
64, 157
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
1111 1111
64, 154
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
1111 1111
64, 151
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
64, 148
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
64, 145
TRISA
TRISA7(8)
TRISA6(8)
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
64, 142
LATJ(7)
LATJ7
LATJ6
LATJ5
LATJ4
LATJ3
LATJ2
LATJ1
LATJ0
xxxx xxxx
64, 165
LATH(7)
LATH7
LATH6
LATH5
LATH4
LATH3
LATH2
LATH1
LATH0
xxxx xxxx
64, 163
LATG
—
—
—
LATG4
LATG3
LATG2
LATG1
LATG0
---x xxxx
64, 160
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
—
xxxx xxx-
64, 157
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
xxxx xxxx
64, 154
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx xxxx
64, 151
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
xxxx xxxx
64, 148
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx xxxx
64, 145
LATA
LATA7(8)
LATA6(8)
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx xxxx
64, 142
RJ7
RJ6
RJ5
RJ4
RJ3
RJ2
RJ1
RJ0
xxxx xxxx
65, 165
PORTJ(7)
PORTH(7)
PORTG
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
0000 xxxx
65, 163
RDPU
REPU
RJPU(7)
RG4
RG3
RG2
RG1
RG0
000x xxxx
65, 160
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
x000 000-
65, 157
PORTE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
xxxx xxxx
65, 154
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
65, 151
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
65, 148
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
65, 145
PORTA
RA7(8)
RA6(8)
RA5
RA4
RA3
RA2
RA1
RA0
000x 0000
65, 142
0000 0000
65, 289
0100 0-00
65, 289
0000 0000
65, 289
0100 0-00
65, 289
65, 210
SPBRGH1
EUSART1 Baud Rate Generator Register High Byte
BAUDCON1
SPBRGH2
ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
EUSART2 Baud Rate Generator Register High Byte
BAUDCON2
ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
TMR3H
Timer3 Register High Byte
xxxx xxxx
TMR3L
Timer3 Register Low Byte
xxxx xxxx
65, 210
0000 0000
65, 210
T3CON
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
TMR4
Timer4 Register
0000 0000
65, 209
PR4(2)/
Timer4 Period Register
1111 1111
65, 210
CVRCON(3)
T4CON
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
CVREN
—
CVROE
CVRR
CVRSS
CVR3
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0
CVR2
CVR1
CVR0
0000 0000
65, 328
TMR4ON
T4CKPS1
T4CKPS0
-000 0000
65, 209
x = unknown; u = unchanged; — = unimplemented; q = value depends on condition; Bold = shared access SFRs
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address; available when WDTCON = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2 = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I2C™ Slave mode. See Section 20.4.3.2
“Address Masking Modes” for details.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 12.1.2 “Data Registers” for more information.
2007-2012 Microchip Technology Inc.
DS39778E-page 85
PIC18F87J11 FAMILY
TABLE 6-5:
File Name
REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
Page:
65, 212
CCPR4H
Capture/Compare/PWM Register 4 High Byte
xxxx xxxx
CCPR4L
Capture/Compare/PWM Register 4 Low Byte
xxxx xxxx
65, 212
--00 0000
65, 212
CCP4CON
—
—
DC4B1
DC4B0
CCP4M3
CCP4M2
CCP4M1
CCP4M0
CCPR5H
Capture/Compare/PWM Register 5 High Byte
xxxx xxxx
65, 212
CCPR5L
Capture/Compare/PWM Register 5 Low Byte
xxxx xxxx
65, 212
CCP5CON
—
—
DC5B1
DC5B0
CCP5M3
CCP5M2
CCP5M1
CCP5M0
SSP2BUF
MSSP2 Receive Buffer/Transmit Register
SSP2ADD/
MSSP2 Address Register (I2C™ Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode)
--00 0000
65, 212
xxxx xxxx
65, 238,
248
0000 0000
65, 248
SSP2MSK(5)
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
0000 0000
65, 255
SSP2STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
65, 239,
249
SSP2CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
65, 240,
250
SSP2CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN/
SEN
0000 0000
GCEN
ACKSTAT
ADMSK5(6)
ADMSK4(6)
ADMSK3(6)
ADMSK2(6)
ADMSK1(6)
SEN
65, 251,
283
—
—
—
—
COUT2
COUT1
---- --11
65, 321
CMSTAT
PMADDRH/
—
—
CS2
CS1
Parallel Master Port Address High Byte
PMDOUT1H(9) Parallel Port Out Data High Byte (Buffer 1)
0000 0000
66, 174
0000 0000
66, 177
PMADDRL/
Parallel Master Port Address Low Byte
0000 0000
66, 174
PMDOUT1L(9)
Parallel Port Out Data Low Byte (Buffer 0)
0000 0000
66, 174
PMDIN1H
Parallel Port In Data High Byte (Buffer 1)
0000 0000
66, 174
PMDIN1L
Parallel Port In Data Low Byte (Buffer 0)
0000 0000
66, 174
PMCONH
PMPEN
—
PSIDL
ADRMUX1
ADRMUX0
PTBEEN
PTWREN
PTRDEN
0-00 0000
66, 168
PMCONL
CSF1
CSF0
ALP
CS2P
CS1P
BEP
WRSP
RDSP
0000 0000
66, 169
PMMODEH
BUSY
IRQM1
IRQM0
INCM1
INCM0
MODE16
MODE1
MODE0
0000 0000
66, 170
PMMODEL
WAITB1
WAITB0
WAITM3
WAITM2
WAITM1
WAITM0
WAITE1
WAITE0
0000 0000
66, 171
PMDOUT2H
Parallel Port Out Data High Byte (Buffer 3)
0000 0000
66, 174
PMDOUT2L
Parallel Port Out Data Low Byte (Buffer 2)
0000 0000
66, 174
PMDIN2H
Parallel Port In Data High Byte (Buffer 3)
0000 0000
66, 174
PMDIN2L
Parallel Port In Data Low Byte (Buffer 2)
0000 0000
66, 174
66, 171
PMEH
PTEN15
PTEN14
PTEN13
PTEN12
PTEN11
PTEN10
PTEN9
PTEN8
0000 0000
PMEL
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
0000 0000
66, 172
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
00-- 0000
66, 172
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
10-- 1111
66, 173
PMSTATH
PMSTATL
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
x = unknown; u = unchanged; — = unimplemented; q = value depends on condition; Bold = shared access SFRs
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address; available when WDTCON = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2 = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I2C™ Slave mode. See Section 20.4.3.2
“Address Masking Modes” for details.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 12.1.2 “Data Registers” for more information.
DS39778E-page 86
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
6.3.5
STATUS REGISTER
The STATUS register, shown in Register 6-4, contains
the arithmetic status of the ALU. The STATUS register
can be the operand for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
then the write to these five bits is disabled.
These bits are set or cleared according to the device
logic. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended. For example, CLRF STATUS will set the Z bit
but leave the other bits unchanged. The STATUS
register then reads back as ‘000u u1uu’. It is
REGISTER 6-4:
recommended, therefore, that only BCF, BSF, SWAPF,
MOVFF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C, DC, OV or N bits in the STATUS
register.
For other instructions not affecting any Status bits, see
the instruction set summaries in Table 26-2 and
Table 26-3.
Note:
The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
STATUS REGISTER
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
N
OV
Z
DC(1)
C(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit(1)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/borrow bit(2)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand.
For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand.
2007-2012 Microchip Technology Inc.
DS39778E-page 87
PIC18F87J11 FAMILY
6.4
Data Addressing Modes
Note:
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 6.6 “Data Memory
and the Extended Instruction Set” for
more information.
While the program memory can be addressed in only
one way, through the Program Counter, information in
the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
•
•
•
•
Inherent
Literal
Direct
Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 6.6.1 “Indexed
Addressing with Literal Offset”.
6.4.1
INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device, or they operate implicitly on
one register. This addressing mode is known as
Inherent Addressing; examples include SLEEP, RESET
and DAW.
Other instructions work in a similar way, but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode, because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
6.4.2
DIRECT ADDRESSING
Direct Addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit Literal Address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 6.3.3 “General
DS39778E-page 88
Purpose Register File”), or a location in the Access
Bank (Section 6.3.2 “Access Bank”) as the data
source for the instruction.
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 6.3.1 “Bank Select Register”) are used with
the address to determine the complete 12-bit address
of the register. When ‘a’ is ‘0’, the address is interpreted
as being a register in the Access Bank. Addressing that
uses the Access RAM is sometimes also known as
Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
6.4.3
INDIRECT ADDRESSING
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures such as
tables and arrays in data memory.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code using
loops, such as the example of clearing an entire RAM
bank in Example 6-5. It also enables users to perform
Indexed Addressing and other Stack Pointer
operations for program memory in data memory.
EXAMPLE 6-5:
NEXT
LFSR
CLRF
BTFSS
BRA
CONTINUE
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
FSR0, 100h ;
POSTINC0
; Clear INDF
; register then
; inc pointer
FSR0H, 1
; All done with
; Bank1?
NEXT
; NO, clear next
; YES, continue
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
6.4.3.1
FSR Registers and the
INDF Operand
the SFR space but are not physically implemented.
Reading or writing to a particular INDF register actually
accesses its corresponding FSR register pair. A read
from INDF1, for example, reads the data at the address
indicated by FSR1H:FSR1L. Instructions that use the
INDF registers as operands actually use the contents
of their corresponding FSR as a pointer to the instruction’s target. The INDF operand is just a convenient
way of using the pointer.
At the core of Indirect Addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
Indirect Addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can
be thought of as “virtual” registers: they are mapped in
FIGURE 6-9:
INDIRECT ADDRESSING
000h
Using an instruction with one of the
Indirect Addressing registers as the
operand....
Bank 0
ADDWF, INDF1, 1
100h
Bank 1
200h
...uses the 12-bit address stored in
the FSR pair associated with that
register....
300h
FSR1H:FSR1L
7
0
x x x x 1 1 1 1
7
0
Bank 2
Bank 3
through
Bank 13
1 1 0 0 1 1 0 0
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
FCCh. This means the contents of
location FCCh will be added to that
of the W register and stored back in
FCCh.
E00h
Bank 14
F00h
FFFh
Bank 15
Data Memory
2007-2012 Microchip Technology Inc.
DS39778E-page 89
PIC18F87J11 FAMILY
6.4.3.2
FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on its stored value. They are:
• POSTDEC: accesses the FSR value, then
automatically decrements it by ‘1’ afterwards
• POSTINC: accesses the FSR value, then
automatically increments it by ‘1’ afterwards
• PREINC: increments the FSR value by ‘1’, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of -128 to 127) to that of the FSR and uses
the new value in the operation
In this context, accessing an INDF register uses the
value in the FSR registers without changing them.
Similarly, accessing a PLUSW register gives the FSR
value offset by the value in the W register; neither value
is actually changed in the operation. Accessing the
other virtual registers changes the value of the FSR
registers.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
6.4.3.3
Operations by FSRs on FSRs
Indirect Addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations. As a
specific case, assume that FSR0H:FSR0L contains
FE7h, the address of INDF1. Attempts to read the
value of the INDF1, using INDF0 as an operand, will
return 00h. Attempts to write to INDF1, using INDF0 as
the operand, will result in a NOP.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses Indirect Addressing.
Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
DS39778E-page 90
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
6.5
Program Memory and the
Extended Instruction Set
The operation of program memory is unaffected by the
use of the extended instruction set.
Enabling the extended instruction set adds five
additional two-word commands to the existing PIC18
instruction set: ADDFSR, CALLW, MOVSF, MOVSS and
SUBFSR. These instructions are executed as described
in Section 6.2.4 “Two-Word Instructions”.
6.6
Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core
PIC18 instructions is different. This is due to the introduction of a new addressing mode for the data memory
space. This mode also alters the behavior of Indirect
Addressing using FSR2 and its associated operands.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.
6.6.1
INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under the
proper conditions, instructions that use the Access
Bank, which are most of the bit-oriented and
byte-oriented instructions, can invoke a form of
Indexed Addressing using an offset specified in the
instruction. This special addressing mode is known as
Indexed Addressing with Literal Offset, or Indexed
Literal Offset mode.
2007-2012 Microchip Technology Inc.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0)
• The file address argument is less than or equal to
5Fh
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in Direct Addressing) or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
6.6.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing
modes are unaffected.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’) or include a file address of 60h
or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible addressing modes when the extended
instruction set is enabled is shown in Figure 6-10.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 26.2.1
“Extended Instruction Syntax”.
DS39778E-page 91
PIC18F87J11 FAMILY
FIGURE 6-10:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When a = 0 and f 60h:
The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and FFFh. This is the same as
locations F60h to FFFh
(Bank 15) of data memory.
Locations below 060h are not
available in this addressing
mode.
000h
060h
Bank 0
100h
00h
Bank 1
through
Bank 14
60h
Valid range
for ‘f’
FFh
F00h
Access RAM
Bank 15
F60h
SFRs
FFFh
Data Memory
When a = 0 and f5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
000h
Bank 0
060h
100h
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
Bank 15
F60h
SFRs
FFFh
Data Memory
When a = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
BSR
00000000
000h
Bank 0
060h
100h
Bank 1
through
Bank 14
001001da ffffffff
F00h
Bank 15
F60h
SFRs
FFFh
Data Memory
DS39778E-page 92
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
6.6.3
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower part of Access RAM
(00h to 5Fh) is mapped. Rather than containing just the
contents of the bottom part of Bank 0, this mode maps
the contents from Bank 0 and a user-defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see Section 6.3.2 “Access
Bank”). An example of Access Bank remapping in this
addressing mode is shown in Figure 6-11.
FIGURE 6-11:
Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use Direct Addressing as before. Any Indirect or
Indexed Addressing operation that explicitly uses any
of the indirect file operands (including FSR2) will continue to operate as standard Indirect Addressing. Any
instruction that uses the Access Bank, but includes a
register address of greater than 05Fh, will use Direct
Addressing and the normal Access Bank map.
6.6.4
BSR IN INDEXED LITERAL
OFFSET MODE
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL
OFFSET ADDRESSING
Example Situation:
ADDWF f, d, a
FSR2H:FSR2L = 120h
000h
05Fh
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
100h
120h
17Fh
Bank 0
200h
Window
Bank 1
00h
Bank 1 “Window”
5Fh
60h
Special Function Registers
at F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
Not Accessible
Bank 2
through
Bank 14
SFRs
FFh
Access Bank
F00h
Bank 15
F60h
FFFh
SFRs
Data Memory
2007-2012 Microchip Technology Inc.
DS39778E-page 93
PIC18F87J11 FAMILY
NOTES:
DS39778E-page 94
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
7.0
FLASH PROGRAM MEMORY
7.1
Table Reads and Table Writes
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 64 bytes at a time or two bytes at a time. Program memory is erased in blocks of 1024 bytes at a
time. A bulk erase operation may not be issued from
user code.
• Table Read (TBLRD)
• Table Write (TBLWT)
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 7-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 7.5 “Writing
to Flash Program Memory”. Figure 7-2 shows the
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.
FIGURE 7-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
Table Pointer(1)
TBLPTRU
TBLPTRH
TBLPTRL
Table Latch (8-bit)
TABLAT
Program Memory
(TBLPTR)
Note 1:
Table Pointer register points to a byte in program memory.
2007-2012 Microchip Technology Inc.
DS39778E-page 95
PIC18F87J11 FAMILY
FIGURE 7-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1:
7.2
Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL. The process for physically writing data to the program memory array is discussed in
Section 7.5 “Writing to Flash Program Memory”.
Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
•
•
•
•
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
7.2.1
EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 7-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The WPROG bit, when set, allows the user to program
a single word (two bytes) upon the execution of the WR
command. If this bit is cleared, the WR command
programs a block of 64 bytes.
DS39778E-page 96
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the write operation.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 7-1:
EECON1: EEPROM CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-x
R/W-0
R/S-0
U-0
—
—
WPROG
FREE
WRERR
WREN
WR
—
bit 7
bit 0
Legend:
S = Settable bit (cannot be cleared in software)
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
WPROG: One Word-Wide Program bit
1 = Programs 2 bytes on the next WR command
0 = Programs 64 bytes on the next WR command
bit 4
FREE: Flash Row Erase Enable bit
1 = Erases the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Performs write only
bit 3
WRERR: Flash Program Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation or an improper write attempt)
0 = The write operation completed
bit 2
WREN: Flash Program Write Enable bit
1 = Allows write cycles to Flash program memory
0 = Inhibits write cycles to Flash program memory
bit 1
WR: Write Control bit
1 = Initiates a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.)
0 = Write cycle is complete
bit 0
Unimplemented: Read as ‘0’
2007-2012 Microchip Technology Inc.
DS39778E-page 97
PIC18F87J11 FAMILY
7.2.2
TABLE LATCH REGISTER (TABLAT)
7.2.4
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
7.2.3
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
TABLE POINTER REGISTER
(TBLPTR)
When a TBLWT is executed, the seven LSbs of the
Table Pointer register (TBLPTR) determine which
of the 64 program memory holding registers is written
to. When the timed write to program memory begins
(via the WR bit), the 12 MSbs of the TBLPTR
(TBLPTR) determine which program memory
block of 1024 bytes is written to. For more detail, see
Section 7.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the Configuration bits.
When an erase of program memory is executed, the
12 MSbs of the Table Pointer register point to the
1024-byte block that will be erased. The Least
Significant bits are ignored.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 7-1. These operations on the TBLPTR only affect
the low-order 21 bits.
TABLE 7-1:
TABLE POINTER BOUNDARIES
Figure 7-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
FIGURE 7-3:
21
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU
16
15
TBLPTRH
8
7
TBLPTRL
0
ERASE: TBLPTR
TABLE WRITE: TBLPTR
TABLE READ: TBLPTR
DS39778E-page 98
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
7.3
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
FIGURE 7-4:
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 7-4
shows the interface between the internal program
memory and the TABLAT.
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
Instruction Register
(IR)
EXAMPLE 7-1:
FETCH
TBLRD
TBLPTR = xxxxx0
TABLAT
Read Register
READING A FLASH PROGRAM MEMORY WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVF
MOVWF
TABLAT, W
WORD_EVEN
TABLAT, W
WORD_ODD
2007-2012 Microchip Technology Inc.
; read into TABLAT and increment
; get data
; read into TABLAT and increment
; get data
DS39778E-page 99
PIC18F87J11 FAMILY
7.4
Erasing Flash Program Memory
The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or
through ICSP control, can larger blocks of program
memory be bulk erased. Word erase in the Flash array
is not supported.
When initiating an erase sequence from the microcontroller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 12 bits of the
TBLPTR point to the block being erased.
TBLPTR are ignored.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. For
protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 7-2:
7.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1.
2.
3.
4.
5.
6.
7.
8.
Load Table Pointer register with address of row
being erased.
Set the WREN and FREE bits (EECON1)
to enable the erase operation.
Disable interrupts.
Write H'55' to EECON2.
Write H'AA' to EECON2.
Set the WR bit. This will begin the row erase
cycle.
The CPU will stall for duration of the erase for
TIW (see Parameter D133A).
Re-enable interrupts.
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
EECON1,
EECON1,
INTCON,
H'55'
EECON2
H'AA'
EECON2
EECON1,
INTCON,
; enable write to memory
; enable Row Erase operation
; disable interrupts
ERASE_ROW
Required
Sequence
DS39778E-page 100
WREN
FREE
GIE
; write H'55'
WR
GIE
; write H'AA'
; start erase (CPU stall)
; re-enable interrupts
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
7.5
The on-chip timer controls the write time. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
Writing to Flash Program Memory
The programming block is 32 words or 64 bytes.
Programming one word or two bytes at a time is also
supported.
Note 1: Unlike previous PIC18 Flash devices,
members of the PIC18F87J11 family do
not reset the holding registers after a
write occurs. The holding registers must
be cleared or overwritten before a
programming sequence.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT instruction may need to be executed 64 times for
each programming operation (if WPROG = 0). All of the
table write operations will essentially be short writes
because only the holding registers are written. At the
end of updating the 64 holding registers, the EECON1
register must be written to in order to start the
programming operation with a long write.
2: To maintain the endurance of the program memory cells, each Flash byte
should not be programmed more than
one time between erase operations.
Before attempting to modify the contents
of the target cell a second time, a row
erase of the target row or a bulk erase of
the entire memory, must be performed.
The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
FIGURE 7-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
TBLPTR = xxxxx0
8
TBLPTR = xxxxx1
Holding Register
TBLPTR = xxxxx2
Holding Register
8
TBLPTR = xxxx3F
Holding Register
Holding Register
Program Memory
7.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
Read 1024 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer register with address being
erased.
Execute the row erase procedure.
Load Table Pointer register with address of first
byte being written, minus 1.
Write the 64 bytes into the holding registers with
auto-increment.
Set the WREN bit (EECON1) to enable byte
writes.
2007-2012 Microchip Technology Inc.
8.
9.
10.
11.
12.
Disable interrupts.
Write H'55' to EECON2.
Write H'AA' to EECON2.
Set the WR bit. This will begin the write cycle.
The CPU will stall for duration of the write for TIW
(Parameter D133A).
13. Re-enable interrupts.
14. Repeat Steps 6 through 13 until all 1024 bytes
are written to program memory.
15. Verify the memory (table read).
An example of the required code is shown in
Example 7-3 on the following page.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
DS39778E-page 101
PIC18F87J11 FAMILY
EXAMPLE 7-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base address
; of the memory block, minus 1
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
MOVLW
MOVWF
EECON1, WREN
EECON1, FREE
INTCON, GIE
H'55'
EECON2
H'AA'
EECON2
EECON1, WR
INTCON, GIE
D'16'
WRITE_COUNTER
; enable write to memory
; enable Row Erase operation
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64'
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
ERASE_BLOCK
; write H'55'
; write H'AA'
; start erase (CPU stall)
; re-enable interrupts
; Need to write 16 blocks of 64 to write
; one erase block of 1024
RESTART_BUFFER
; point to buffer
FILL_BUFFER
...
; read the new data from I2C, SPI,
; PSP, USART, etc.
WRITE_BUFFER
MOVLW
MOVWF
WRITE_BYTE_TO_HREGS
MOVFF
MOVWF
TBLWT+*
D’64
COUNTER
; number of bytes in holding register
POSTINC0, WREG
TABLAT
;
;
;
;
;
DECFSZ
BRA
COUNTER
WRITE_BYTE_TO_HREGS
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
EECON1,
INTCON,
H'55'
EECON2
H'AA'
EECON2
EECON1,
INTCON,
EECON1,
DECFSZ
BRA
WRITE_COUNTER
RESTART_BUFFER
get low byte of buffer data
present data to table latch
write data, perform a short write
to internal TBLWT holding register.
loop until buffers are full
PROGRAM_MEMORY
Required
Sequence
DS39778E-page 102
WREN
GIE
; enable write to memory
; disable interrupts
; write H'55'
WR
GIE
WREN
;
;
;
;
write H'AA'
start program (CPU stall)
re-enable interrupts
disable write to memory
; done with one write cycle
; if not done replacing the erase block
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
7.5.2
FLASH PROGRAM MEMORY WRITE
SEQUENCE (WORD
PROGRAMMING).
3.
4.
5.
6.
7.
8.
The PIC18F87J11 family of devices have a feature that
allows programming a single word (two bytes). This
feature is enable when the WPROG bit is set. If the
memory location is already erased, the following
sequence is required to enable this feature:
1.
2.
Load the Table Pointer register with the address
of the data to be written
Write the 2 bytes into the holding registers and
perform a table write
EXAMPLE 7-4:
9.
Set the WREN bit (EECON1) to enable byte
writes.
Disable interrupts.
Write H'55' to EECON2.
Write H'AA' to EECON2.
Set the WR bit. This will begin the write cycle.
The CPU will stall for duration of the write for TIW
(see Parameter D133A).
Re-enable interrupts.
SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
MOVLW
MOVWF
TBLWT*+
MOVLW
MOVWF
TBLWT*
DATA0
TABLAT
; Load TBLPTR with the base address
DATA1
TABLAT
PROGRAM_MEMORY
Required
Sequence
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
BCF
EECON1,
EECON1,
INTCON,
H'55'
EECON2
H'AA'
EECON2
EECON1,
INTCON,
EECON1,
EECON1,
2007-2012 Microchip Technology Inc.
WPROG
WREN
GIE
; enable single word write
; enable write to memory
; disable interrupts
; write H'55'
WR
GIE
WPROG
WREN
;
;
;
;
;
write H'AA'
start program (CPU stall)
re-enable interrupts
disable single word write
disable write to memory
DS39778E-page 103
PIC18F87J11 FAMILY
7.5.3
WRITE VERIFY
7.6
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.4
Flash Program Operation During
Code Protection
See Section 25.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset, during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 7-2:
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Name
Bit 7
Bit 6
Bit 5
TBLPTRU
—
—
bit 21
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
Program Memory Table Pointer Upper Byte (TBLPTR)
61
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR)
61
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR)
61
TABLAT
61
Program Memory Table Latch
INTCON
GIE/GIEH PEIE/GIEL
EECON2
Program Memory Control Register 2 (not a physical register)
EECON1
—
—
TMR0IE
WPROG
INT0IE
FREE
RBIE
WRERR
TMR0IF
INT0IF
RBIF
61
63
WREN
WR
—
63
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash program memory access.
DS39778E-page 104
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
8.0
EXTERNAL MEMORY BUS
Note:
The External Memory Bus (EMB) is not
implemented on 64-pin devices.
The External Memory Bus allows the device to access
external memory devices (such as Flash, EPROM,
SRAM, etc.) as program or data memory. It supports
both 8 and 16-Bit Data Width modes and three address
widths of up to 20 bits.
TABLE 8-1:
The bus is implemented with 28 pins, multiplexed
across four I/O ports. Three ports (PORTD, PORTE
and PORTH) are multiplexed with the address/data bus
for a total of 20 available lines, while PORTJ is
multiplexed with the bus control signals.
A list of the pins and their functions is provided in
Table 8-1.
PIC18F87J11 FAMILY EXTERNAL BUS – I/O PORT FUNCTIONS
Name
Port
Bit
External Memory Bus Function
RD0/AD0
PORTD
0
Address Bit 0 or Data Bit 0
RD1/AD1
PORTD
1
Address Bit 1 or Data Bit 1
RD2/AD2
PORTD
2
Address Bit 2 or Data Bit 2
RD3/AD3
PORTD
3
Address Bit 3 or Data Bit 3
RD4/AD4
PORTD
4
Address Bit 4 or Data Bit 4
RD5/AD5
PORTD
5
Address Bit 5 or Data Bit 5
RD6/AD6
PORTD
6
Address Bit 6 or Data Bit 6
RD7/AD7
PORTD
7
Address Bit 7 or Data Bit 7
RE0/AD8
PORTE
0
Address Bit 8 or Data Bit 8
RE1/AD9
PORTE
1
Address Bit 9 or Data Bit 9
RE2/AD10
PORTE
2
Address Bit 10 or Data Bit 10
RE3/AD11
PORTE
3
Address Bit 11 or Data Bit 11
RE4/AD12
PORTE
4
Address Bit 12 or Data Bit 12
RE5/AD13
PORTE
5
Address Bit 13 or Data Bit 13
RE6/AD14
PORTE
6
Address Bit 14 or Data Bit 14
RE7/AD15
PORTE
7
Address Bit 15 or Data Bit 15
RH0/A16
PORTH
0
Address Bit 16
RH1/A17
PORTH
1
Address Bit 17
RH2/A18
PORTH
2
Address Bit 18
RH3/A19
PORTH
3
Address Bit 19
RJ0/ALE
PORTJ
0
Address Latch Enable (ALE) Control Pin
RJ1/OE
PORTJ
1
Output Enable (OE) Control Pin
RJ2/WRL
PORTJ
2
Write Low (WRL) Control Pin
RJ3/WRH
PORTJ
3
Write High (WRH) Control Pin
RJ4/BA0
PORTJ
4
Byte Address Bit 0 (BA0)
RJ5/CE
PORTJ
5
Chip Enable (CE) Control Pin
RJ6/LB
PORTJ
6
Lower Byte Enable (LB) Control Pin
RJ7/UB
PORTJ
7
Upper Byte Enable (UB) Control Pin
Note:
For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional
multiplexed features may be available on some pins.
2007-2012 Microchip Technology Inc.
DS39778E-page 105
PIC18F87J11 FAMILY
8.1
External Memory Bus Control
The operation of the interface is controlled by the
MEMCON register (Register 8-1). This register is
available in all program memory operating modes
except Microcontroller mode. In this mode, the register
is disabled and cannot be written to.
The EBDIS bit (MEMCON) controls the operation
of the bus and related port functions. Clearing EBDIS
enables the interface and disables the I/O functions of
the ports, as well as any other functions multiplexed to
those pins. Setting the bit enables the I/O ports and
other functions, but allows the interface to override
everything else on the pins when an external memory
operation is required. By default, the external bus is
always enabled and disables all other I/O.
The WAITx bits allow for the addition of Wait states to
external memory operations. The use of these bits is
discussed in Section 8.3 “Wait States”.
The WMx bits select the particular operating mode
used when the bus is operating in 16-Bit Data Width
mode. These are discussed in more detail in
Section 8.6 “16-Bit Data Width Modes”. These bits
have no effect when an 8-bit Data Width mode is
selected.
The MEMCON register (see Register 8-1) shares the
same memory space as the PR2 register and can be
alternately selected, based on the designation of the
ADSHR bit in the WDTCON register (see
Register 25-9).
The operation of the EBDIS bit is also influenced by the
program memory mode being used. This is discussed
in more detail in Section 8.5 “Program Memory
Modes and the External Memory Bus”.
REGISTER 8-1:
MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
EBDIS
—
WAIT1
WAIT0
—
—
WM1
WM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EBDIS: External Bus Disable bit
1 = External bus is enabled when the microcontroller accesses external memory; otherwise, all
external bus drivers are mapped as I/O ports
0 = External bus is always enabled, I/O ports are disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
WAIT: Table Reads and Writes Bus Cycle Wait Count bits
11 = Table reads and writes will wait 0 TCY
10 = Table reads and writes will wait 1 TCY
01 = Table reads and writes will wait 2 TCY
00 = Table reads and writes will wait 3 TCY
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
WM: TBLWT Operation with 16-Bit Data Bus Width Select bits
1x = Word Write mode: TABLAT word output, WRH is active when TABLAT is written
01 = Byte Select mode: TABLAT data is copied on both MSB and LSB, WRH and (UB or LB) will activate
00 = Byte Write mode: TABLAT data is copied on both MSB and LSB, WRH or WRL will activate
DS39778E-page 106
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
8.2
8.2.1
Address and Data Width
The PIC18F87J11 family of devices can be independently configured for different address and data widths
on the same memory bus. Both address and data width
are set by Configuration bits in the CONFIG3L register.
As Configuration bits, this means that these options
can only be configured by programming the device and
are not controllable in software.
The BW bit selects an 8-bit or 16-bit data bus width.
Setting this bit (default) selects a data width of 16 bits.
The EMB bits determine both the program memory operating mode and the address bus width. The
available options are 20-bit, 16-bit and 12-bit, as well
as Microcontroller mode (external bus disabled).
Selecting a 16-bit or 12-bit width makes a corresponding number of high-order lines available for I/O
functions. These pins are no longer affected by the
setting of the EBDIS bit. For example, selecting a
16-Bit Addressing mode (EMB = 01) disables
A and allows PORTH to function without
interruptions from the bus. Using the smaller address
widths allows users to tailor the memory bus to the size
of the external memory space for a particular design
while freeing up pins for dedicated I/O operation.
Because the EMBx bits have the effect of disabling pins
for memory bus operations, it is important to always
select an address width at least equal to the data width.
If a 12-bit address width is used with a 16-bit data
width, the upper four bits of data will not be available on
the bus.
All combinations of address and data widths require
multiplexing of address and data information on the
same lines. The address and data multiplexing, as well
as I/O ports made available by the use of smaller
address widths, are summarized in Table 8-2.
TABLE 8-2:
Data Width
By default, the address presented on the external bus
is the value of the PC. In practical terms, this means
that addresses in the external memory device, below
the top of on-chip memory, are unavailable to the
microcontroller. To access these physical locations, the
glue logic between the microcontroller and the external
memory must somehow translate the addresses.
To simplify the interface, the external bus offers an
extension of Extended Microcontroller mode that
automatically performs address shifting. This feature is
controlled by the EASHFT Configuration bit. Setting
this bit offsets addresses on the bus by the size of the
microcontroller’s on-chip program memory and sets
the bottom address at 0000h. This allows the device to
use the entire range of physical addresses of the
external memory.
8.2.2
This addressing mode is available in both 8-bit and
certain 16-Bit Data Width modes. Additional details are
provided in Section 8.6.3 “16-Bit Byte Select Mode”
and Section 8.7 “8-Bit Data Width Mode”.
ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS
Address Width
Multiplexed Data and
Address Lines (and
Corresponding Ports)
16-Bit
AD
(PORTD)
20-Bit
16-Bit
16-Bit
21-BIT ADDRESSING
As an extension of the 20-bit address width operation,
the External Memory Bus can also fully address a
2-Mbyte memory space. This is done by using the Bus
Address bit 0 (BA0) control line as the Least Significant
bit of the address. The UB and LB control signals may
also be used with certain memory devices to select the
upper and lower bytes within a 16-bit wide data word.
12-Bit
8-Bit
ADDRESS SHIFTING ON THE
EXTERNAL BUS
20-Bit
2007-2012 Microchip Technology Inc.
AD
(PORTD,
PORTE)
Address Only
Lines (and
Corresponding Ports)
Ports Available
for I/O
AD
(PORTE)
PORTE,
All of PORTH
AD
(PORTE)
All of PORTH
A, AD
(PORTH,
PORTE)
—
—
All of PORTH
A
(PORTH)
—
DS39778E-page 107
PIC18F87J11 FAMILY
8.3
Wait States
While it may be assumed that external memory devices
will operate at the microcontroller clock rate, this is
often not the case. In fact, many devices require longer
times to write or retrieve data than the time allowed by
the execution of table read or table write operations.
To compensate for this, the External Memory Bus can
be configured to add a fixed delay to each table operation using the bus. Wait states are enabled by setting
the WAIT Configuration bit. When enabled, the amount
of delay is set by the WAIT bits (MEMCON).
The delay is based on multiples of microcontroller
instruction cycle time and are added following the
instruction cycle when the table operation is executed.
The range is from no delay to 3 TCY (default value).
8.4
Port Pin Weak Pull-ups
With the exception of the upper address lines,
A the pins associated with the External Memory Bus are equipped with weak pull-ups. The pull-ups
are controlled by the upper three bits of the PORTG
register (PORTG). They are named RDPU,
REPU and RJPU, and control pull-ups on PORTD,
PORTE and PORTJ, respectively. Setting one of these
bits enables the corresponding pull-ups for that port. All
pull-ups are disabled by default on all device Resets.
functions. When EBDIS = 0, the pins function as the
external bus. When EBDIS = 1, the pins function as I/O
ports.
If the device fetches or accesses external memory while
EBDIS = 1, the pins will switch to external bus. If the
EBDIS bit is set by a program executing from external
memory, the action of setting the bit will be delayed until
the program branches into the internal memory. At that
time, the pins will change from external bus to I/O ports.
If the device is executing out of internal memory when
EBDIS = 0, the memory bus address/data and control
pins will not be active. They will go to a state where the
active address/data pins are tri-state; the CE, OE,
WRH, WRL, UB and LB signals are ‘1’, and ALE and
BA0 are ‘0’. Note that only those pins associated with
the current address width are forced to tri-state; the
other pins continue to function as I/O. In the case of
16-bit address width, for example, only AD
(PORTD and PORTE) are affected; A
(PORTH) continue to function as I/O.
In all External Memory modes, the bus takes priority
over any other peripherals that may share pins with it.
This includes the Parallel Master Port and serial
communication modules which would otherwise take
priority over the I/O port.
8.6
16-Bit Data Width Modes
In Extended Microcontroller mode, the port pull-ups
can be useful in preserving the memory state on the
external bus while the bus is temporarily disabled
(EBDIS = ‘1’).
In 16-Bit Data Width mode, the External Memory Interface (EMI) can be connected to external memories in
three different configurations:
8.5
• 16-Bit Byte Write
• 16-Bit Word Write
• 16-Bit Byte Select
Program Memory Modes and the
External Memory Bus
The PIC18F87J11 family of devices is capable of operating in one of two program memory modes, using
combinations of on-chip and external program memory.
The functions of the multiplexed port pins depend on
the program memory mode selected, as well as the
setting of the EBDIS bit.
In Microcontroller Mode, the bus is not active and the
pins have their port functions only. Writes to the
MEMCOM register are not permitted. The Reset value
of EBDIS (‘0’) is ignored and EMB pins behave as I/O
ports.
In Extended Microcontroller Mode, the external
program memory bus shares I/O port functions on the
pins. When the device is fetching or doing table
read/table write operations on the external program
memory space, the pins will have the external bus
function.
If the device is fetching and accessing internal program
memory locations only, the EBDIS control bit will
change the pins from external memory to I/O port
DS39778E-page 108
The configuration to be used is determined by the
WM
bits
in
the
MEMCON
register
(MEMCON). These three different configurations allow the designer maximum flexibility in using
both 8-bit and 16-bit devices with 16-bit data.
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits, AD, are available on the External Memory Interface bus. Following
the address latch, the Output Enable signal (OE) will
enable both bytes of program memory at once to form
a 16-bit instruction word. The Chip Enable signal (CE)
is active at any time that the microcontroller accesses
external memory, whether reading or writing; it is
inactive (asserted high) whenever the device is in
Sleep mode.
In Byte Select mode, JEDEC standard Flash memories
will require BA0 for the byte address line and one I/O
line to select between Byte and Word mode. The other
16-bit modes do not need BA0. JEDEC standard static
RAM memories will use the UB or LB signals for byte
selection.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
8.6.1
16-BIT BYTE WRITE MODE
Figure 8-1 shows an example of 16-Bit Byte Write
mode for PIC18F87J11 family devices. This mode is
used for two separate 8-bit memories connected for
16-bit operation. This generally includes basic EPROM
and Flash devices; it allows table writes to byte-wide
external memories.
FIGURE 8-1:
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
16-BIT BYTE WRITE MODE EXAMPLE
D
PIC18F87J11
AD
(MSB)
373
A
D
(LSB)
A
A
D
D
CE
AD
373
OE
D
CE
WR(2)
OE
WR(2)
ALE
A(1)
CE
OE
WRH
WRL
Address Bus
Data Bus
Control Lines
Note 1:
2:
Upper order address lines are used only for 20-bit address widths.
This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
2007-2012 Microchip Technology Inc.
DS39778E-page 109
PIC18F87J11 FAMILY
8.6.2
16-BIT WORD WRITE MODE
Figure 8-2 shows an example of 16-Bit Word Write
mode for PIC18F87J11 family devices. This mode is
used for word-wide memories which include some of
the EPROM and Flash type memories. This mode
allows opcode fetches and table reads from all forms of
16-bit memory and table writes to any type of
word-wide external memories. This method makes a
distinction between TBLWT cycles to even or odd
addresses.
During a TBLWT cycle to an even address
(TBLPTR = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is
tri-stated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 8-2:
During a TBLWT cycle to an odd address
(TBLPTR = 1), the TABLAT data is presented on
the upper byte of the AD bus. The contents of
the holding latch are presented on the lower byte of the
AD bus.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSb of the TBLPTR, but it is left unconnected.
Instead, the UB and LB signals are active to select both
bytes. The obvious limitation to this method is that the
table write must be done in pairs on a specific word
boundary to correctly write a word location.
16-BIT WORD WRITE MODE EXAMPLE
PIC18F87J11
AD
373
A
D
AD
A
JEDEC Word
EPROM Memory
D
CE
OE
WR(2)
373
ALE
A(1)
CE
OE
WRH
Address Bus
Data Bus
Control Lines
Note 1:
2:
DS39778E-page 110
Upper order address lines are used only for 20-bit address widths.
This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
8.6.3
16-BIT BYTE SELECT MODE
Figure 8-3 shows an example of 16-Bit Byte Select
mode. This mode allows table write operations to
word-wide external memories with byte selection
capability. This generally includes both word-wide
Flash and SRAM devices.
During a TBLWT cycle, the TABLAT data is presented
on the upper and lower byte of the AD bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written, based on the Least
Significant bit of the TBLPTR register.
FIGURE 8-3:
Flash and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
16-BIT BYTE SELECT MODE EXAMPLE
PIC18F87J11
AD
373
A
A
JEDEC Word
FLASH Memory
D
D
138(3)
AD
373
CE
A0
BYTE/WORD
ALE
OE WR(1)
A(2)
OE
WRH
WRL
A
A
BA0
JEDEC Word
SRAM Memory
I/O
D
LB
CE
LB
UB
UB
D
OE WR(1)
Address Bus
Data Bus
Control Lines
Note 1:
This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
2:
Upper order address lines are used only for 20-bit address width.
3:
Demultiplexing is only required when multiple memory devices are accessed.
2007-2012 Microchip Technology Inc.
DS39778E-page 111
PIC18F87J11 FAMILY
8.6.4
16-BIT MODE TIMING
The presentation of control signals on the External
Memory Bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 8-4 and Figure 8-5.
FIGURE 8-4:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED
MICROCONTROLLER MODE)
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
0Ch
A
CF33h
AD
9256h
CE
ALE
OE
Memory
Cycle
Opcode Fetch
TBLRD*
from 000100h
Opcode Fetch
MOVLW 55h
from 000102h
TBLRD 92h
from 199E67h
Opcode Fetch
ADDLW 55h
from 000104h
Instruction
Execution
INST(PC – 2)
TBLRD Cycle 1
TBLRD Cycle 2
MOVLW
FIGURE 8-5:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED
MICROCONTROLLER MODE)
Q1
Q2
Q4
Q1
Q2
3AAAh
Q3
Q4
Q1
00h
00h
A
AD
Q3
0003h
3AABh
0E55h
CE
ALE
OE
Memory
Cycle
Instruction
Execution
DS39778E-page 112
Opcode Fetch
SLEEP
from 007554h
Opcode Fetch
MOVLW 55h
from 007556h
INST(PC – 2)
SLEEP
Sleep Mode, Bus Inactive
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
8.7
will enable one byte of program memory for a portion of
the instruction cycle, then BA0 will change and the
second byte will be enabled to form the 16-bit instruction word. The Least Significant bit of the address, BA0,
must be connected to the memory devices in this
mode. The Chip Enable signal (CE) is active at any
time that the microcontroller accesses external
memory, whether reading or writing. It is inactive
(asserted high) whenever the device is in Sleep mode.
8-Bit Data Width Mode
In 8-Bit Data Width mode, the External Memory Bus
operates only in Multiplexed mode; that is, data shares
the 8 Least Significant bits of the address bus.
Figure 8-6 shows an example of 8-Bit Multiplexed
mode for 80-pin devices. This mode is used for a single
8-bit memory connected for 16-bit operation. The
instructions will be fetched as two 8-bit bytes on a
shared data/address bus. The two bytes are sequentially fetched within one instruction cycle (TCY).
Therefore, the designer must choose external memory
devices according to timing calculations based on
1/2 TCY (2 times the instruction rate). For proper memory speed selection, glue logic propagation delay times
must be considered, along with setup and hold times.
This generally includes basic EPROM and Flash
devices. It allows table writes to byte-wide external
memories.
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD bus. The appropriate level of the BA0 control
line is strobed on the LSb of the TBLPTR.
The Address Latch Enable (ALE) pin indicates that the
address bits, AD, are available on the External
Memory Interface bus. The Output Enable signal (OE)
FIGURE 8-6:
8-BIT MULTIPLEXED MODE EXAMPLE
D
PIC18F87J11
AD
ALE
373
A
A
A0
D
D
AD(1)
A
CE
(1)
OE
WR(2)
BA0
CE
OE
WRL
Address Bus
Data Bus
Control Lines
Note 1:
2:
Upper order address bits are only used for 20-bit address width. The upper AD byte is used for all
address widths except 8-bit.
This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
2007-2012 Microchip Technology Inc.
DS39778E-page 113
PIC18F87J11 FAMILY
8.7.1
8-BIT MODE TIMING
The presentation of control signals on the External
Memory Bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 8-7 and Figure 8-8.
FIGURE 8-7:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED
MICROCONTROLLER MODE)
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
A
Q3
Q4
Q1
Q2
Q3
Q4
0Ch
CFh
AD
33h
AD
92h
CE
ALE
OE
Memory
Cycle
Instruction
Execution
FIGURE 8-8:
Opcode Fetch
TBLRD*
from 000100h
Opcode Fetch
MOVLW 55h
from 000102h
TBLRD 92h
from 199E67h
Opcode Fetch
ADDLW 55h
from 000104h
INST(PC – 2)
TBLRD Cycle 1
TBLRD Cycle 2
MOVLW
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED
MICROCONTROLLER MODE)
Q1
Q2
Q4
Q1
Q2
3Ah
AD
AAh
00h
Q3
Q4
Q1
00h
00h
A
AD
Q3
3Ah
03h
ABh
0Eh
55h
BA0
CE
ALE
OE
Memory
Cycle
Instruction
Execution
DS39778E-page 114
Opcode Fetch
SLEEP
from 007554h
Opcode Fetch
MOVLW 55h
from 007556h
INST(PC – 2)
SLEEP
Sleep Mode, Bus Inactive
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
8.8
Operation in Power-Managed
Modes
In alternate, power-managed Run modes, the external
bus continues to operate normally. If a clock source
with a lower speed is selected, bus operations will run
at that speed. In these cases, excessive access times
for the external memory may result if Wait states have
been enabled and added to external memory operations. If operations in a lower power Run mode are
anticipated, users should provide in their applications
for adjusting memory access times at the lower clock
speeds.
2007-2012 Microchip Technology Inc.
In Sleep and Idle modes, the microcontroller core does
not need to access data; bus operations are suspended. The state of the external bus is frozen, with the
address/data pins and most of the control pins holding
at the same state they were in when the mode was
invoked. The only potential changes are the CE, LB
and UB pins, which are held at logic high.
DS39778E-page 115
PIC18F87J11 FAMILY
NOTES:
DS39778E-page 116
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
9.0
8 x 8 HARDWARE MULTIPLIER
9.1
Introduction
EXAMPLE 9-1:
MOVF
MULWF
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
ARG1, W
ARG2
EXAMPLE 9-2:
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applications previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 9-1.
9.2
8 x 8 UNSIGNED
MULTIPLY ROUTINE
;
; ARG1 * ARG2 ->
; PRODH:PRODL
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
ARG1, W
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH, F
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
;
;
;
;
;
ARG1 * ARG2 ->
PRODH:PRODL
Test Sign Bit
PRODH = PRODH
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
Operation
Example 9-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 9-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
TABLE 9-1:
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Routine
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
Multiply Method
Without hardware multiply
Program
Memory
(Words)
Cycles
(Max)
@ 48 MHz
@ 10 MHz
@ 4 MHz
13
69
5.7 s
27.6 s
69 s
Time
Hardware multiply
1
1
83.3 ns
400 ns
1 s
Without hardware multiply
33
91
7.5 s
36.4 s
91 s
Hardware multiply
6
6
500 ns
2.4 s
6 s
Without hardware multiply
21
242
20.1 s
96.8 s
242 s
Hardware multiply
28
28
2.3 s
11.2 s
28 s
Without hardware multiply
52
254
21.6 s
102.6 s
254 s
Hardware multiply
35
40
3.3 s
16.0 s
40 s
2007-2012 Microchip Technology Inc.
DS39778E-page 117
PIC18F87J11 FAMILY
Example 9-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 9-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 9-1:
RES3:RES0
=
=
EXAMPLE 9-3:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L)
EQUATION 9-2:
RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L) +
(-1 ARG2H ARG1H:ARG1L 216) +
(-1 ARG1H ARG2H:ARG2L 216)
EXAMPLE 9-4:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
ARG1L * ARG2H->
PRODH:PRODL
Add cross
products
ARG1H * ARG2L->
PRODH:PRODL
Add cross
products
Example 9-4 shows the sequence to do a 16 x 16
signed multiply. Equation 9-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
DS39778E-page 118
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
;
;
;
;
;
;
ARG1L * ARG2H ->
PRODH:PRODL
Add cross
products
;
;
;
;
;
;
;
;
;
;
;
MOVF
MULWF
;
;
;
;
;
;
;
;
;
;
16 x 16 SIGNED
MULTIPLY ROUTINE
;
;
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
;
;
;
;
;
;
;
;
;
ARG1H * ARG2L ->
PRODH:PRODL
Add cross
products
;
;
SIGN_ARG1
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
;
CONT_CODE
:
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
10.0
INTERRUPTS
Members of the PIC18F87J11 family of devices have
multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a
high-priority level or a low-priority level. The high-priority
interrupt vector is at 0008h and the low-priority interrupt
vector is at 0018h. High-priority interrupt events will
interrupt any low-priority interrupts that may be in
progress.
There are thirteen registers which are used to control
interrupt operation. These registers are:
•
•
•
•
•
•
•
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2, PIR3
PIE1, PIE2, PIE3
IPR1, IPR2, IPR3
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic
bit names in these registers. This allows the
assembler/compiler to automatically take care of the
placement of these bits within the specified register.
In general, interrupt sources have three bits to control
their operation. They are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high-priority or low-priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON), along with the
GIEH bit, enables all interrupts that have the priority bit
cleared (low priority). When the interrupt flag, enable bit
and appropriate Global Interrupt Enable bit are set, the
interrupt will vector immediately to address 0008h or
0018h, depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
2007-2012 Microchip Technology Inc.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC16 mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON is the PEIE bit
which enables/disables all peripheral interrupt sources.
INTCON is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
0008h in Compatibility mode.
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL
bit. High-priority interrupt sources can interrupt a
low-priority interrupt. Low-priority interrupts are not
processed while high-priority interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine (ISR),
the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
The “Return from Interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
For external interrupt events, such as the INTx pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
Note:
Do not use the MOVFF instruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
DS39778E-page 119
PIC18F87J11 FAMILY
FIGURE 10-1:
PIC18F87J11 FAMILY INTERRUPT LOGIC
Wake-up if in
Idle or Sleep modes
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
Interrupt to CPU
Vector to Location
0008h
GIE/GIEH
IPEN
PIR3
PIE3
IPR3
IPEN
PEIE/GIEL
IPEN
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
DS39778E-page 120
Interrupt to CPU
Vector to Location
0018h
IPEN
GIE/GIEH
PEIE/GIEL
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
10.1
INTCON Registers
Note:
The INTCON registers are readable and writable
registers which contain various enable, priority and flag
bits.
REGISTER 10-1:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high-priority interrupts
0 = Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low-priority peripheral interrupts (if GIEH = 1)
0 = Disables all low-priority peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB pins changed state (must be cleared in software)
0 = None of the RB pins have changed state
Note 1:
A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction
cycle, will end the mismatch condition and allow the bit to be cleared.
2007-2012 Microchip Technology Inc.
DS39778E-page 121
PIC18F87J11 FAMILY
REGISTER 10-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port TRIS values
bit 6
INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5
INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4
INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3
INTEDG3: External Interrupt 3 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 2
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
INT3IP: INT3 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
DS39778E-page 122
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 10-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
INT3IE: INT3 External Interrupt Enable bit
1 = Enables the INT3 external interrupt
0 = Disables the INT3 external interrupt
bit 4
INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2
INT3IF: INT3 External Interrupt Flag bit
1 = The INT3 external interrupt occurred (must be cleared in software)
0 = The INT3 external interrupt did not occur
bit 1
INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
2007-2012 Microchip Technology Inc.
DS39778E-page 123
PIC18F87J11 FAMILY
10.2
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
Note 1: Interrupt flag bits are set when an
interrupt condition occurs, regardless of
the state of its corresponding enable bit or
the Global Interrupt Enable bit, GIE
(INTCON).
2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 10-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
PMPIF
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PMPIF: Parallel Master Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5
RC1IF: EUSART1 Receive Interrupt Flag bit
1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0 = The EUSART1 receive buffer is empty
bit 4
TX1IF: EUSART1 Transmit Interrupt Flag bit
1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0 = The EUSART1 transmit buffer is full
bit 3
SSP1IF: MSSP1 Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2
CCP1IF: ECCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
DS39778E-page 124
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 10-5:
R/W-0
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
OSCFIF
CM2IF
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
CM1IF
—
BCL1IF
LVDIF
TMR3IF
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OSCFIF: Oscillator Fail Interrupt Flag bit
1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = Device clock operating
bit 6
CM2IF: Comparator 2 Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 5
CM1IF: Comparator 1 Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 4
Unimplemented: Read as ‘0’
bit 3
BCL1IF: Bus Collision Interrupt Flag bit (MSSP1 module)
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 2
LVDIF: Low-Voltage Detect Interrupt Flag bit
1 = A low-voltage condition occurred (must be cleared in software)
0 = VDDCORE has not fallen below the low-voltage trip point (about 2.45V)
bit 1
TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 0
CCP2IF: ECCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
2007-2012 Microchip Technology Inc.
DS39778E-page 125
PIC18F87J11 FAMILY
REGISTER 10-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SSP2IF: MSSP2 Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 6
BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module)
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 5
RC2IF: EUSART2 Receive Interrupt Flag bit
1 = The EUSART2 receive buffer, RCREG2, is full (cleared when RCREG2 is read)
0 = The EUSART2 receive buffer is empty
bit 4
TX2IF: EUSART2 Transmit Interrupt Flag bit
1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared when TXREG2 is written)
0 = The EUSART2 transmit buffer is full
bit 3
TMR4IF: TMR4 to PR4 Match Interrupt Flag bit
1 = TMR4 to PR4 match occurred (must be cleared in software)
0 = No TMR4 to PR4 match occurred
bit 2
CCP5IF: CCP5 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
CCP4IF: CCP4 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 0
CCP3IF: ECCP3 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
DS39778E-page 126
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
10.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 10-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMPIE
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PMPIE: Parallel Master Port Read/Write Interrupt Enable bit
1 = Enables the PM read/write interrupt
0 = Disables the PM read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5
RC1IE: EUSART1 Receive Interrupt Enable bit
1 = Enables the EUSART1 receive interrupt
0 = Disables the EUSART1 receive interrupt
bit 4
TX1IE: EUSART1 Transmit Interrupt Enable bit
1 = Enables the EUSART1 transmit interrupt
0 = Disables the EUSART1 transmit interrupt
bit 3
SSP1IE: MSSP1 Interrupt Enable bit
1 = Enables the MSSP1 interrupt
0 = Disables the MSSP1 interrupt
bit 2
CCP1IE: ECCP1 Interrupt Enable bit
1 = Enables the ECCP1 interrupt
0 = Disables the ECCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
2007-2012 Microchip Technology Inc.
x = Bit is unknown
DS39778E-page 127
PIC18F87J11 FAMILY
REGISTER 10-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
OSCFIE
CM2IE
CM1IE
—
BCL1IE
LVDIE
TMR3IE
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6
CM2IE: Comparator 2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5
CM1IE: Comparator 1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4
Unimplemented: Read as ‘0’
bit 3
BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module)
1 = Enabled
0 = Disabled
bit 2
LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
CCP2IE: ECCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
DS39778E-page 128
x = Bit is unknown
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 10-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SSP2IE: MSSP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6
BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
1 = Enabled
0 = Disabled
bit 5
RC2IE: EUSART2 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4
TX2IE: EUSART2 Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
CCP5IE: CCP5 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
CCP4IE: CCP4 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
CCP3IE: ECCP3 Interrupt Enable bit
1 = Enabled
0 = Disabled
2007-2012 Microchip Technology Inc.
x = Bit is unknown
DS39778E-page 129
PIC18F87J11 FAMILY
10.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 10-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PMPIP
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PMPIP: Parallel Master Port Read/Write Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RC1IP: EUSART1 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TX1IP: EUSART1 Transmit Interrupt Priority bit
x = Bit is unknown
1 = High priority
0 = Low priority
bit 3
SSP1IP: MSSP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP1IP: ECCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
DS39778E-page 130
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
R/W-1
R/W-1
U-0
R/W-1
R/W-1
R/W-1
R/W-1
OSCFIP
CM2IP
CM1IP
—
BCL1IP
LVDIP
TMR3IP
CCP2IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
CM2IP: Comparator 2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
C12IP: Comparator 1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
Unimplemented: Read as ‘0’
bit 3
BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module)
1 = High priority
0 = Low priority
bit 2
LVDIP: Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
CCP2IP: ECCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
2007-2012 Microchip Technology Inc.
x = Bit is unknown
DS39778E-page 131
PIC18F87J11 FAMILY
REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SSP2IP: MSSP2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module)
1 = High priority
0 = Low priority
bit 5
RC2IP: EUSART2 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TX2IP: EUSART2 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
TMR4IE: TMR4 to PR4 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP5IP: CCP5 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
CCP4IP: CCP4 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
CCP3IP: ECCP3 Interrupt Priority bit
1 = High priority
0 = Low priority
DS39778E-page 132
x = Bit is unknown
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
10.5
RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
modes. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 10-13: RCON: RESET CONTROL REGISTER
R/W-0
U-0
R/W-1
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
—
CM
RI
TO
PD
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
Unimplemented: Read as ‘0’
bit 5
CM: Configuration Mismatch Flag bit
For details of bit operation, see Register 5-1.
bit 4
RI: RESET Instruction Flag bit
For details of bit operation, see Register 5-1.
bit 3
TO: Watchdog Timer Time-out Flag bit
For details of bit operation, see Register 5-1.
bit 2
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 5-1.
bit 1
POR: Power-on Reset Status bit
For details of bit operation, see Register 5-1.
bit 0
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 5-1.
2007-2012 Microchip Technology Inc.
x = Bit is unknown
DS39778E-page 133
PIC18F87J11 FAMILY
10.6
INTx Pin Interrupts
10.7
TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Flag bit, INTxIF, must be cleared in software in
the Interrupt Service Routine before re-enabling the
interrupt.
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON). Interrupt priority for Timer0 is
determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2). See Section 13.0
“Timer0 Module” for further details on the Timer0
module.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from the power-managed
modes if bit, INTxIE, was set prior to going into the
power-managed modes, with the exception of Deep
Sleep, which can only be woken from INT0. If the
Global Interrupt Enable bit, GIE, is set, the processor
will branch to the interrupt vector following wake-up.
10.8
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the Interrupt Priority bits,
INT1IP (INTCON3), INT2IP (INTCON3) and
INT3IP (INTCON2). There is no priority bit
associated with INT0; it is always a high-priority
interrupt source.
EXAMPLE 10-1:
An input change on PORTB sets flag bit, RBIF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2).
10.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack. If a fast
return from interrupt is not used (see Section 6.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 10-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
W_TEMP
MOVFF
STATUS, STATUS_TEMP
MOVFF
BSR, BSR_TEMP
;
; USER ISR CODE
;
MOVFF
BSR_TEMP, BSR
MOVF
W_TEMP, W
MOVFF
STATUS_TEMP, STATUS
DS39778E-page 134
PORTB Interrupt-on-Change
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
11.0
I/O PORTS
11.1
Depending on the device selected and features
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three memory-mapped registers for its
operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Output Latch register)
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register writes to
the Output Latch (LAT) register.
Setting a TRIS bit (= 1) makes the corresponding port
pin an input (i.e., puts the corresponding output driver
in a High-Impedance mode). Clearing a TRIS bit (= 0)
makes the corresponding port pin an output (i.e., puts
the contents of the corresponding LAT bit on the
selected pin).
I/O Port Pin Capabilities
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than VDD input levels.
11.1.1
INPUT PINS AND VOLTAGE
CONSIDERATIONS
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are
used as digital only inputs are able to handle DC
voltages up to 5.5V, a level typical for digital logic
circuits. In contrast, pins that also have analog input
functions of any kind (such as A/D and comparator
inputs) can only tolerate voltages up to VDD. Voltage
excursions beyond VDD on these pins should be
avoided.
Table 11-1 summarizes the input capabilities. Refer to
Section 28.0 “Electrical Characteristics” for more
details.
TABLE 11-1:
Port or Pin
The Output Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
the PORT register.
PORTA
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 11-1.
PORTH(1)
FIGURE 11-1:
Tolerated
Input
Description
VDD
Only VDD input levels
are tolerated.
5.5V
Tolerates input levels
above VDD, useful for
most standard logic.
PORTC
PORTF
PORTB
PORTC
GENERIC I/O PORT
OPERATION
INPUT VOLTAGE LEVELS
PORTD
PORTE
RD LAT
Data
Bus
WR LAT
or PORT
PORTF
PORTG
D
PORTH(1)
Q
(1)
I/O Pin
CK
Note 1:
Data Latch
D
WR TRIS
Q
11.1.2
CK
TRIS Latch
Input
Buffer
RD TRIS
Q
D
ENEN
RD PORT
Note 1:
PORTJ(1)
I/O pins have diode protection to VDD and VSS.
2007-2012 Microchip Technology Inc.
These ports are not available on 64-pin
devices.
PIN OUTPUT DRIVE
When used as digital I/O, the output pin drive strengths
vary for groups of pins intended to meet the needs for
a variety of applications. In general, there are three
classes of output pins in terms of drive capability.
PORTB and PORTC, as well as PORTA, are
designed to drive higher current loads, such as LEDs.
PORTD, PORTE and PORTJ are capable of driving
digital circuits associated with external memory
devices; they can also drive LEDs, but only those with
smaller current requirements. PORTF, PORTG and
PORTH, along with PORTA, have the lowest
drive level, but are capable of driving normal digital
circuit loads with a high input impedance.
DS39778E-page 135
PIC18F87J11 FAMILY
Table 11-2 summarizes the output capabilities of the
ports. Refer to the “Absolute Maximum Ratings” in
Section 28.0 “Electrical Characteristics” for more
details.
TABLE 11-2:
Port
PORTA
OUTPUT DRIVE LEVELS
Drive
Description
Minimum Intended for indication.
PORTF
PORTG
PORTH(1)
PORTD
Medium
Sufficient drive levels for
external memory interfacing
as well as indication.
High
Suitable for direct LED drive
levels.
PORTE
PORTJ(1)
PORTB
PORTC
Note 1:
11.1.3
11.1.4
INTERFACING TO A 5V SYSTEM
Though the VDDMAX of the PIC18F87J11 family is 3.6V,
these devices are still capable of interfacing with 5V
systems, even if the VIH of the target system is above
3.6V. This is accomplished by adding a pull-up resistor
to the port pin (Figure 11-2), clearing the LAT bit for that
pin and manipulating the corresponding TRIS bit
(Figure 11-1) to either allow the line to be pulled high,
or to drive the pin low. Only port pins that are tolerant of
voltages up to 5.5V can be used for this type of
interface (refer to Section 11.1.1 “Input Pins and
Voltage Considerations”).
FIGURE 11-2:
+5V SYSTEM HARDWARE
INTERFACE
+5V
PIC18F87J11
These ports are not available on 64-pin
devices.
+5V Device
RD7
PULL-UP CONFIGURATION
Four of the I/O ports (PORTB, PORTD, PORTE and
PORTJ) implement configurable weak pull-ups on all
pins. These are internal pull-ups that allow floating
digital input signals to be pulled to a consistent level,
without the use of external resistors.
The pull-ups are enabled with a single bit for each of the
ports: RBPU (INTCON2) for PORTB, and RDPU,
REPU and RJPU (PORTG) for the other ports.
DS39778E-page 136
EXAMPLE 11-1:
BCF
LATD, 7
BCF
BSF
TRISD, 7
TRISD, 7
COMMUNICATING WITH
THE +5V SYSTEM
;
;
;
;
;
set up LAT register so
changing TRIS bit will
drive line low
send a 0 to the 5V system
send a 1 to the 5V system
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
11.1.5
11.1.6
OPEN-DRAIN OUTPUTS
The output pins for several peripherals are also
equipped with a configurable, open-drain output option.
This allows the peripherals to communicate with external digital logic operating at a higher voltage level,
without the use of level translators.
The open-drain option is implemented on port pins specifically associated with the data and clock outputs of
the EUSARTs, the MSSP modules (in SPI mode) and
the CCP and ECCP modules. It is selectively enabled
by setting the open-drain control bit for the corresponding module in the ODCON registers (Register 11-1,
Register 11-2 and Register 11-3). Their configuration is
discussed in more detail with the individual port where
these peripherals are multiplexed.
The ODCON registers all reside in the SFR configuration
space and share the same SFR addresses as the Timer1
registers (see Section 6.3.4.1 “Shared Address SFRs”
for more details). The ODCON registers are accessed by
setting the ADSHR bit (WDTCON).
TTL INPUT BUFFER OPTION
Many of the digital I/O ports use Schmitt Trigger (ST)
input buffers. While this form of buffering works well
with many types of input, some applications may
require TTL-level signals to interface with external logic
devices. This is particularly true with the EMB and the
Parallel Master Port (PMP), which are particularly likely
to be interfaced to TTL-level logic or memory devices.
The inputs for the PMP can be optionally configured for
TTL buffers with the PMPTTL bit in the PADCFG1 register (Register 11-4). Setting this bit configures all data
and control input pins for the PMP to use TTL buffers.
By default, these PMP inputs use the port’s ST buffers.
As with the ODCON registers, the PADCFG1 register
resides in the SFR configuration space; it shares the
same memory address as the TMR2 register.
PADCFG1 is accessed by setting the ADSHR bit
(WDTCON).
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor provided by the user to a higher voltage level, up to 5V on
digital only pins (Figure 11-3). When a digital logic high
signal is output, it is pulled up to the higher voltage level.
FIGURE 11-3:
USING THE OPEN-DRAIN
OUTPUT (EUSARTx
SHOWN AS EXAMPLE)
+5V
3.3V
PIC18F87J11
VDD
TXX
(at logic ‘1’)
3.3V
2007-2012 Microchip Technology Inc.
5V
DS39778E-page 137
PIC18F87J11 FAMILY
REGISTER 11-1:
ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
CCP5OD
CCP4OD
ECCP3OD
ECCP2OD
ECCP1OD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-3
CCP5OD:CCP4OD: CCPx Open-Drain Output Enable bits
1 = Open-drain output is on the CCPx pin (Capture/PWM modes) is enabled
0 = Open-drain output is disabled
bit 2-0
ECCP3OD:ECCP1OD: ECCPx Open-Drain Output Enable bits
1 = Open-drain output is on the ECCPx pin (Capture mode) is enabled
0 = Open-drain output is disabled
REGISTER 11-2:
ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
U2OD
U1OD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1-0
U2OD:U1OD: EUSARTx Open-Drain Output Enable bits
1 = Open-drain output is on the TXx pin is enabled
0 = Open-drain output is disabled
REGISTER 11-3:
x = Bit is unknown
ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
SPI2OD
SPI1OD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1-0
SPI2OD:SPI1OD: SPI Open-Drain Output Enable bits
1 = Open-drain output is on the SDOx pin is enabled
0 = Open-drain output is disabled
DS39778E-page 138
x = Bit is unknown
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 11-4:
PADCFG1: I/O PAD CONFIGURATION CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
PMPTTL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-1
Unimplemented: Read as ‘0’
bit 0
PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffers
2007-2012 Microchip Technology Inc.
x = Bit is unknown
DS39778E-page 139
PIC18F87J11 FAMILY
11.2
PORTA, TRISA and
LATA Registers
PORTA is an 8-bit wide, bidirectional port. It may function as a 6-bit or 7-bit port, depending on the oscillator
mode selected. The corresponding Data Direction and
Output Latch registers are TRISA and LATA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin; it is also multiplexed as the Parallel Master Port data pin (in 80-pin
devices). The other PORTA pins are multiplexed with
the analog VREF+ and VREF- inputs. The operation of
pins, RA, as A/D Converter inputs is selected
by clearing or setting the appropriate PCFGx control
bits in the ANCON0 register.
Note 1: RA5 (RA5/PMD4/AN4) is multiplexed as
an analog input in all devices and Parallel
Master Port data in 80-pin devices.
2: RA5 and RA are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
The RA4/T0CKI pin is a Schmitt Trigger input. All other
PORTA pins have TTL input levels and full CMOS
output drivers.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally
serve as the external circuit connections for the
external (primary) oscillator circuit (HS and HSPLL
Oscillator modes), or the external clock input (EC and
ECPLL Oscillator modes). In these cases, RA6 and
RA7 are not available as digital I/O, and their
corresponding TRIS and LAT bits are read as ‘0’.
For INTIO and INTPLL Oscillator modes (FOSC2 Configuration bit is ‘0’), either RA7 or both RA6 and RA7
automatically become available as digital I/O, depending on the oscillator mode selected. When RA6 is not
configured as a digital I/O, in these cases, it provides a
clock output at FOSC/4. A list of the possible configurations for RA6 and RA7, based on oscillator mode, is
provided in Table 11-3. For these pins, the corresponding PORTA, TRISA and LATA bits are only defined
when the pins are configured as I/O.
TABLE 11-3:
Oscillator Mode
(FOSC Configuration)
RA6
RA7
INTPLL1 (011)
CLKO
I/O
INTPLL2 (010)
I/O
I/O
INTIO1 (001)
CLKO
I/O
INTIO2 (000)
I/O
I/O
Legend: CLKO = FOSC/4 clock output;
I/O = digital port.
EXAMPLE 11-2:
CLRF
CLRF
BSF
MOVLW
MOVWF
BCF
MOVLW
MOVWF
DS39778E-page 140
FUNCTION OF RA IN
INTIO AND INTPLL MODES
PORTA
INITIALIZING PORTA
;
;
;
LATA
;
;
WDTCON,ADSHR ;
;
1Fh
;
ANCON0
;
WDTCON,ADSHR ;
;
H'CF'
;
;
;
TRISA
;
;
Initialize PORTA by
clearing output
data latches
Alternate method to
clear data latches
Enable write/read to
the shared SFR
Configure A/D
for digital inputs
Disable write/read
to the shared SFR
Value used to
initialize
data direction
Set RA as inputs,
RA as outputs
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 11-4:
Pin Name
RA0/AN0
PORTA FUNCTIONS
Function
RA0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/PMD5/
T0CKI/
OSC1/CLKI/
RA7
Legend:
Note 1:
I/O
Type
Description
0
O
DIG
LATA data output; not affected by analog input.
I
TTL
PORTA data input; disabled when analog input is enabled.
AN0
1
I
ANA
A/D Input Channel 0. Default input configuration on POR; does not
affect digital output.
RA1
0
O
DIG
LATA data output; not affected by analog input.
1
I
TTL
PORTA data input; disabled when analog input is enabled.
AN1
1
I
ANA
A/D Input Channel 1. Default input configuration on POR; does not
affect digital output.
RA2
0
O
DIG
LATA data output; not affected by analog input. Disabled when
CVREF output is enabled.
1
I
TTL
PORTA data input. Disabled when analog functions enabled;
disabled when CVREF output is enabled.
AN2
1
I
ANA
A/D Input Channel 2. Default input configuration on POR; not affected
by analog output.
VREF-
1
I
ANA
A/D low reference voltage input.
RA3
0
O
DIG
LATA data output; not affected by analog input.
1
I
TTL
PORTA data input; disabled when analog input is enabled.
AN3
1
I
ANA
A/D Input Channel 3. Default input configuration on POR.
VREF+
1
I
ANA
A/D high reference voltage input.
RA4
0
O
DIG
LATA data output.
1
I
ST
PORTA data input; default configuration on POR.
x
O
DIG
Parallel Master Port data output.
x
I
TTL
Parallel Master Port data output.
Timer0 clock input.
T0CKI
x
I
ST
RA5
0
O
DIG
LATA data output; not affected by analog input.
1
I
TTL
PORTA data input; disabled when analog input is enabled.
x
O
DIG
Parallel Master Port data output.
PMD4(1)
OSC2/CLKO/
RA6
I/O
1
PMD5(1)
RA5/PMD4/AN4
TRIS
Setting
x
I
TTL
Parallel Master Port data output.
AN4
1
I
ANA
A/D Input Channel 4. Default configuration on POR.
OSC2
x
O
ANA
Main oscillator feedback output connection (HS and HSPLL modes).
CLKO
x
O
DIG
System cycle clock output, FOSC/4 (EC, ECPLL, INTIO1 and INTPLL1
modes).
RA6
0
O
DIG
LATA data output; disabled when FOSC2 Configuration bit is set.
1
I
TTL
PORTA data input; disabled when FOSC2 Configuration bit is set.
OSC1
x
I
ANA
Main oscillator input connection (HS and HSPLL modes).
CLKI
x
I
ANA
Main external clock source input (EC and ECPLL modes).
RA7
0
O
DIG
LATA data output; disabled when FOSC2 Configuration bit is set.
1
I
TTL
PORTA data input; disabled when FOSC2 Configuration bit is set.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate PMP configuration when the PMPMX Configuration bit is ‘0’; available on 80-pin devices only.
2007-2012 Microchip Technology Inc.
DS39778E-page 141
PIC18F87J11 FAMILY
TABLE 11-5:
Name
PORTA
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Bit 6
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
LATA6(1)
LATA5
LATA4
LATA3
LATA2
TRISA5
TRISA4
TRISA3
TRISA2
—
PCFG4
PCFG3
PCFG2
(1)
LATA
LATA7
TRISA
TRISA7(1)
(2)
ANCON0
PCFG7
TRISA6
Bit 5
(1)
PCFG6
Bit 4
Bit 3
Bit 2
Bit 0
Reset
Values
on Page:
RA1
RA0
65
LATA1
LATA0
64
TRISA1
TRISA0
64
PCFG1
PCFG0
63
Bit 1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: Implemented only in specific oscillator modes (FOSC2 Configuration bit = 0); otherwise, read as ‘0’.
2: Configuration SFR, overlaps with the default SFR at this address; available only when WDTCON = 1.
DS39778E-page 142
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
11.3
PORTB, TRISB and
LATB Registers
PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. All pins on
PORTB are digital only and tolerate voltages up to
5.5V.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON).
This interrupt can wake the device from power-managed
modes. The user, in the Interrupt Service Routine, can
clear the interrupt in the following manner:
1.
2.
3.
Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction).
Wait one instruction cycle (such as executing a
NOP instruction).
Clear flag bit, RBIF.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
For 80-pin devices, RB3 can be configured as the
alternate peripheral pin for the ECCP2 module and
Enhanced PWM Output 2A by clearing the CCP2MX
Configuration bit. This applies only to 80-pin devices
operating in Extended Microcontroller mode. If the
device is in Microcontroller mode, the alternate
assignment for ECCP2 is RE7. As with other ECCP2
configurations, the user must ensure that the TRISB
bit is set appropriately for the intended operation. Ports,
RB1, RB2, RB3, RB4 and RB5, are multiplexed with
the Parallel Master Port address.
EXAMPLE 11-3:
CLRF
PORTB
CLRF
LATB
MOVLW
H'CF'
MOVWF
TRISB
INITIALIZING PORTB
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
clearing output
data latches
Alternate method to clear
output data latches
Value used to initialize
data direction
Set RB as inputs
RB as outputs
RB as inputs
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after a one TCY delay.
2007-2012 Microchip Technology Inc.
DS39778E-page 143
PIC18F87J11 FAMILY
TABLE 11-6:
PORTB FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
RB0/INT0/FLT0
RB0
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
1
I
ST
External Interrupt 0 input.
INT0
FLT0
1
I
ST
Enhanced PWM Fault input (ECCP1 module); enabled in software.
RB1
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
RB1/INT1/
PMA4
INT1
1
I
ST
External Interrupt 1 input.
PMA4
x
O
—
Parallel Master Port address out.
RB2
0
O
DIG
LATB data output.
PORTB data input; weak pull-up when RBPU bit is cleared.
RB2/INT2/
PMA3
RB3/INT3/
PMA2/ECCP2/
P2A
1
I
TTL
INT2
1
I
ST
External Interrupt 2 input.
PMA3
x
O
—
Parallel Master Port address out.
RB3
0
O
DIG
LATB data output.
PORTB data input; weak pull-up when RBPU bit is cleared.
1
I
TTL
INT3
1
I
ST
External Interrupt 3 input.
PMA2
x
O
—
Parallel Master Port address out.
ECCP2(1)
0
O
DIG
ECCP2 compare output and CCP2 PWM output; takes priority over port
data.
1
I
ST
ECCP2 capture input.
P2A(1)
0
O
DIG
ECCP2 Enhanced PWM output, Channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RB4
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
I
TTL
—
RB4/KBI0/
PMA1
KBI0
x
O
RB5
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
I
TTL
Interrupt-on-pin change.
KBI1
x
O
—
RB6
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
KBI2
1
I
TTL
Interrupt-on-pin change.
PGC
x
I
ST
Serial execution (ICSP™) clock input for ICSP and ICD operation.(2)
RB7
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
KBI3
1
I
TTL
Interrupt-on-pin change.
PGD
x
O
DIG
Serial execution data output for ICSP and ICD operation.(2)
x
I
ST
Serial execution data input for ICSP and ICD operation.(2)
RB7/KBI3/PGD
2:
Parallel Master Port address out.
PMA0
RB6/KBI2/PGC
Note 1:
Interrupt-on-pin change.
PMA1
RB5/KBI1/
PMA0
Legend:
Description
Parallel Master Port address out.
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode,
80-pin devices only); the default assignment is RC1.
All other pin functions are disabled when ICSP™ or ICD is enabled.
DS39778E-page 144
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 11-7:
Name
PORTB
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
65
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
64
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
64
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
61
TMR0IP
INT3IP
RBIP
61
INT3IF
INT2IF
INT1IF
61
INTCON
INTCON2
RBPU
INTCON3
INT2IP
INTEDG0 INTEDG1 INTEDG2 INTEDG3
INT1IP
INT3IE
INT2IE
INT1IE
Legend: Shaded cells are not used by PORTB.
2007-2012 Microchip Technology Inc.
DS39778E-page 145
PIC18F87J11 FAMILY
11.4
PORTC, TRISC and
LATC Registers
PORTC is an 8-bit wide, bidirectional port. Only
PORTC pins, RC2 through RC7, are digital only pins
and can tolerate input voltages up to 5.5V.
PORTC is multiplexed with ECCP, MSSPx and
EUSARTx peripheral functions (Table 11-8). The pins
have Schmitt Trigger input buffers. The pins for ECCP,
SPI and EUSARTx are also configurable for open-drain
output whenever these functions are active. Open-drain
configuration is selected by setting the SPIxOD,
ECCPxOD, and UxOD control bits in the ODCON registers (see Section 11.1.3 “Pull-up Configuration” for
more information).
RC1 is normally configured as the default peripheral
pin for the ECCP2 module. Assignment of ECCP2 is
controlled by Configuration bit, CCP2MX (default state,
CCP2MX = 1).
DS39778E-page 146
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
Note:
These pins are configured as digital inputs
on any device Reset.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 11-4:
CLRF
PORTC
CLRF
LATC
MOVLW
H'CF'
MOVWF
TRISC
INITIALIZING PORTC
;
;
;
;
;
;
;
;
;
;
Initialize PORTC by
clearing output
data latches
Alternate method to clear
output data latches
Value used to initialize
data direction
Set RC as inputs
RC as outputs
RC as inputs
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 11-8:
Pin Name
RC0/T1OSO/
T13CKI
RC1/T1OSI/
ECCP2/P2A
RC2/ECCP1/
P1A
PORTC FUNCTIONS
Function
TRIS
Setting
I/O
I/O
Type
RC0
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
T1OSO
x
O
ANA
T13CKI
1
I
ST
Timer1/Timer3 counter input.
RC1
0
O
DIG
LATC data output.
1
I
ST
T1OSI
x
I
ANA
Timer1 oscillator input; enabled when Timer1 oscillator is enabled. Disables
digital I/O.
ECCP2(1)
0
O
DIG
ECCP2 compare output and ECCP2 PWM output; takes priority over port data.
1
I
ST
ECCP2 capture input.
P2A(1)
0
O
DIG
ECCP2 Enhanced PWM output, Channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RC2
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
0
O
DIG
ECCP1 compare output and ECCP1 PWM output; takes priority over port data.
1
I
ST
ECCP1 capture input.
P1A
0
O
DIG
ECCP1 Enhanced PWM output, Channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RC3
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
0
O
DIG
SPI clock output (MSSP1 module); takes priority over port data.
ECCP1
RC3/SCK1/
SCL1
SCK1
SCL1
RC4/SDI1/
SDA1
RC4
RC5/SDO1
RC7/RX1/DT1
Legend:
Note 1:
Timer1 oscillator output; enabled when Timer1 oscillator is enabled.
Disables digital I/O.
PORTC data input.
1
I
ST
SPI clock input (MSSP1 module).
0
O
DIG
I2C™ clock output (MSSP1 module); takes priority over port data.
1
I
ST
I2C clock input (MSSP1 module); input type depends on module setting.
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
SDI1
1
I
ST
SPI data input (MSSP1 module).
SDA1
1
O
DIG
I2C data output (MSSP1 module); takes priority over port data.
1
I
ST
I2C data input (MSSP1 module); input type depends on module setting.
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
SDO1
0
O
DIG
SPI data output (MSSP1 module); takes priority over port data.
RC6
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
TX1
1
O
DIG
Synchronous serial data output (EUSART1 module); takes priority over port data.
CK1
1
O
DIG
Synchronous serial data input (EUSART1 module). User must configure as
an input.
RC5
RC6/TX1/CK1
Description
RC7
1
I
ST
Synchronous serial clock input (EUSART1 module).
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
RX1
1
I
ST
Asynchronous serial receive data input (EUSART1 module).
DT1
1
O
DIG
Synchronous serial data output (EUSART1 module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSART1 module). User must configure as
an input.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignment for ECCP2/P2A when the CCP2MX Configuration bit is set.
2007-2012 Microchip Technology Inc.
DS39778E-page 147
PIC18F87J11 FAMILY
TABLE 11-9:
Name
PORTC
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
65
LATC
LATC7
LATBC6
LATC5
LATCB4
LATC3
LATC2
LATC1
LATC0
64
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
64
DS39778E-page 148
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
11.5
PORTD, TRISD and
LATD Registers
PORTD is an 8-bit wide, bidirectional port. All pins on
PORTD are digital only and tolerate voltages up to
5.5V.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note:
These pins are configured as digital inputs
on any device Reset.
On 80-pin devices, PORTD is multiplexed with the
system bus as part of the External Memory Interface
(EMI). I/O port and other functions are only available
when the interface is disabled by setting the EBDIS bit
(MEMCON). When the interface is enabled,
PORTD is the low-order byte of the multiplexed
address/data bus (AD). The TRISD bits are also
overridden.
Each of the PORTD pins has a weak internal pull-up.
This is performed by clearing bit, RDPU (PORTG).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on all device Resets.
EXAMPLE 11-5:
CLRF
PORTD
CLRF
LATD
MOVLW
H'CF'
MOVWF
TRISD
INITIALIZING PORTD
;
;
;
;
;
;
;
;
;
;
Initialize PORTD by
clearing output
data latches
Alternate method to clear
output data latches
Value used to initialize
data direction
Set RD as inputs
RD as outputs
RD as inputs
PORTD is also multiplexed with the data functions of
the Parallel Master Port data. In this mode, Parallel
Master Port takes priority over the other digital I/O (but
not the External Memory Bus). This multiplexing is
available when PMPMX = 1. When the Parallel Master
Port is active, the input buffers are TTL. For more
information, refer to Section 12.0 “Parallel Master
Port”.
2007-2012 Microchip Technology Inc.
DS39778E-page 149
PIC18F87J11 FAMILY
TABLE 11-10: PORTD FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
RD0
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
x
O
DIG
External Memory Interface, Address/Data Bit 0 output.(1)
x
I
TTL
External Memory Interface, Data Bit 0 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
x
O
DIG
External Memory Interface, Address/Data bit 1 output.(1)
x
I
TTL
External Memory Interface, Data Bit 1 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
x
O
DIG
External Memory Interface, Address/Data Bit 2 output.(1)
x
I
TTL
External Memory Interface, Data Bit 2 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
x
O
DIG
External Memory Interface, Address/Data Bit 3 output.(1)
x
I
TTL
External Memory Interface, Data Bit 3 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
x
O
DIG
External Memory Interface, Address/Data Bit 4 output.(1)
x
I
TTL
External Memory Interface, Data Bit 4 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
SDO2
0
O
DIG
SPI data output (MSSP2 module); takes priority over port data.
RD5
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
x
O
DIG
External Memory Interface, Address/Data Bit 5 output.(1)
x
I
TTL
External Memory Interface, Data Bit 5 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
SDI2
1
I
ST
SPI data input (MSSP2 module).
SDA2
1
O
DIG
I2C™ data output (MSSP2 module); takes priority over port data.
1
I
ST
I2C data input (MSSP2 module); input type depends on module
setting.
RD0/AD0/
PMD0
AD0(2)
PMD0(3)
RD1/AD1/
PMD1
RD1
AD1(2)
PMD1(3)
RD2/AD2/
PMD2
RD2
AD2(2)
PMD2(3)
RD3/AD3/
PMD3
RD3
AD3(2)
PMD3(3)
RD4/AD4/
PMD4/SDO2
RD4
AD4(2)
PMD4(3)
RD5/AD5/
PMD5/SDI2/
SDA2
AD5(2)
PMD5
Legend:
Note 1:
2:
3:
(3)
Description
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
External Memory Interface I/O takes priority over all other digital and PMP I/O.
These bits are available on 80-pin devices only.
Default configuration for PMP (PMPMX Configuration bit = 1).
DS39778E-page 150
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 11-10: PORTD FUNCTIONS (CONTINUED)
Pin Name
RD6/AD6/
PMD6/SCK2/
SCL2
Function
TRIS
Setting
I/O
I/O
Type
RD6
0
O
DIG
AD6(2)
PMD6(3)
SCK2
SCL2
RD7/AD7/
PMD7/SS2
RD7
AD7(2)
PMD7(3)
SS2
Legend:
Note 1:
2:
3:
Description
LATD data output.
1
I
ST
x
O
DIG-3
PORTD data input.
x
I
TTL
External Memory Interface, Data Bit 6 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
0
O
DIG
SPI clock output (MSSP2 module); takes priority over port data.
1
I
ST
SPI clock input (MSSP2 module).
0
O
DIG
I2C™ clock output (MSSP2 module); takes priority over port data.
1
I
ST
I2C clock input (MSSP2 module); input type depends on module
setting.
0
O
DIG
LATD data output.
External Memory Interface, Address/Data Bit 6 output.(1)
1
I
ST
PORTD data input.
x
O
DIG
External Memory Interface, Address/Data Bit 7 output.(1)
x
I
TTL
External Memory Interface, Data Bit 7 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
x
I
TTL
Slave select input for MSSP2 module.
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
External Memory Interface I/O takes priority over all other digital and PMP I/O.
These bits are available on 80-pin devices only.
Default configuration for PMP (PMPMX Configuration bit = 1).
TABLE 11-11: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name
PORTD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
65
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
64
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
64
PORTG
RDPU
REPU
RJPU(1)
RG4
RG3
RG2
RG1
RG0
65
Legend: Shaded cells are not used by PORTD.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
2007-2012 Microchip Technology Inc.
DS39778E-page 151
PIC18F87J11 FAMILY
11.6
PORTE, TRISE and
LATE Registers
PORTE is an 8-bit wide, bidirectional port. All pins on
PORTE are digital only and tolerate voltages up to
5.5V.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note:
These pins are configured as digital inputs
on any device Reset.
On 80-pin devices, PORTE is multiplexed with the
system bus as part of the External Memory Interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON). When the interface is enabled,
PORTE is the high-order byte of the multiplexed
Address/Data bus (AD). The TRISE bits are
also overridden.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, REPU (PORTG). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
DS39778E-page 152
PORTE is also multiplexed with Enhanced PWM
Outputs B and C for ECCP1 and ECCP3, and
Outputs B, C and D for ECCP2. For all devices, their
default assignments are on PORTE. On 80-pin
devices, the multiplexing for the outputs of ECCP1 and
ECCP3 is controlled by the ECCPMX Configuration bit.
Clearing this bit reassigns the P1B/P1C and P3B/P3C
outputs to PORTH.
For devices operating in Microcontroller mode, the RE7
pin can be configured as the alternate peripheral pin for
the ECCP2 module and Enhanced PWM Output 2A;
this is done by clearing the CCP2MX Configuration bit.
PORTE is also multiplexed with the Parallel Master
Port address lines. When PMPMX = 0, RE1 and RE0
are multiplexed with the control signals, PMWR and
PMRD.
RE3 can also be configured as the Reference Clock
Output (REFO) from the system clock. For further
details, refer to Section 3.6 “Reference Clock
Output”.
EXAMPLE 11-6:
CLRF
PORTE
CLRF
LATE
MOVLW
03h
MOVWF
TRISE
INITIALIZING PORTE
;
;
;
;
;
;
;
;
;
Initialize PORTE by
clearing output
data latches
Alternate method to clear
output data latches
Value used to initialize
data direction
Set RE as inputs
RE as outputs
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 11-12:
Pin Name
RE0/AD8/
PMRD/P2D
PORTE FUNCTIONS
Function
TRIS
Setting
I/O
I/O
Type
RE0
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External Memory Interface, Address/Data Bit 8 output.(2)
x
I
TTL
External Memory Interface, Data Bit 8 input.(2)
x
O
DIG
Parallel Master Port read strobe pin.
x
I
TTL
Parallel Master Port read pin.
P2D
0
O
DIG
ECCP2 Enhanced PWM output, Channel D; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE1
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
AD9(3)
x
O
DIG
External Memory Interface, Address/Data Bit 9 output.(2)
x
I
TTL
External Memory Interface, Data Bit 9 input.(2)
x
O
DIG
Parallel Master Port write strobe pin.
AD8(3)
PMRD(5)
RE1/AD9/
PMWR/P2C
PMWR
RE2/AD10/
PMBE/P2B
(5)
x
I
TTL
Parallel Master Port write pin.
P2C
0
O
DIG
ECCP2 Enhanced PWM output, Channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE2
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External Memory Interface, Address/Data Bit 10 output.(2)
x
I
TTL
External Memory Interface, Data Bit 10 input.(2)
AD10(3)
PMBE
RE3/AD11/
PMA13/P3C/
REFO
RE4/AD12/
PMA12/P3B
(5)
x
O
DIG
Parallel Master Port byte enable.
P2B
0
O
DIG
ECCP2 Enhanced PWM output, Channel B; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE3
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External Memory Interface, Address/Data Bit 11 output.(2)
x
I
TTL
External Memory Interface, Data Bit 11 input.(2)
AD11(3)
PMA13
x
O
DIG
Parallel Master Port address.
P3C(1)
0
O
DIG
ECCP3 Enhanced PWM output, Channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
REFO
x
O
DIG
Reference output clock.
RE4
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External Memory Interface, Address/Data Bit 12 output.(2)
x
I
TTL
External Memory Interface, Data Bit 12 input.(2)
PMA12
x
O
DIG
Parallel Master Port address.
P3B(1)
0
O
DIG
ECCP3 Enhanced PWM output, Channel B; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
AD12(3)
Legend:
Note 1:
2:
3:
4:
5:
Description
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
External Memory Interface I/O takes priority over all other digital and PMP I/O.
Available on 80-pin devices only.
Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
Default configuration for PMP (PMPMX Configuration bit = 1).
2007-2012 Microchip Technology Inc.
DS39778E-page 153
PIC18F87J11 FAMILY
TABLE 11-12:
Pin Name
PORTE FUNCTIONS (CONTINUED)
Function
TRIS
Setting
I/O
I/O
Type
RE5
0
O
DIG
LATE data output.
RE5/AD13/
PMA11/P1C
1
I
ST
PORTE data input.
x
O
DIG
External Memory Interface, Address/Data Bit 13 output.(2)
x
I
TTL
External Memory Interface, Data Bit 13 input.(2)
PMA11
x
O
DIG
Parallel Master Port address.
(1)
0
O
DIG
ECCP1 Enhanced PWM output, Channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External Memory Interface, Address/Data Bit 14 output.(2)
x
I
TTL
External Memory Interface, Data Bit 14 input.(2)
AD13(3)
P1C
RE6/AD14/
PMA10/P1B
RE6
AD14(3)
RE7/AD15/
PMA9/ECCP2/
P2A
PMA10
x
O
DIG
Parallel Master Port address.
P1B(1)
0
O
DIG
ECCP1 Enhanced PWM output, Channel B; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE7
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
AD15(3)
x
O
DIG
External Memory Interface, Address/Data Bit 15 output.(2)
x
I
TTL
External Memory Interface, Data Bit 15 input.(2)
x
O
DIG
Parallel Master Port address.
0
O
DIG
ECCP2 compare output and ECCP2 PWM output; takes priority over
port data.
1
I
ST
ECCP2 capture input.
0
O
DIG
ECCP2 Enhanced PWM output, Channel A; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
PMA9
ECCP2
(4)
(4)
P2A
Legend:
Note 1:
2:
3:
4:
5:
Description
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
External Memory Interface I/O takes priority over all other digital and PMP I/O.
Available on 80-pin devices only.
Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
Default configuration for PMP (PMPMX Configuration bit = 1).
TABLE 11-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
PORTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
65
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
64
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
64
REPU
RJPU(1)
RG4
RG3
RG2
RG1
RG0
65
PORTG
RDPU
Legend: Shaded cells are not used by PORTE.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
DS39778E-page 154
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
11.7
PORTF, LATF and TRISF Registers
PORTF is a 7-bit wide, bidirectional port. Only Pin 7 of
PORTF has no analog input; it is the only pin that can
tolerate voltages up to 5.5V.
All pins on PORTF are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
PORTF is multiplexed with analog peripheral functions.
RF1 through RF6 may also be used as analog input
channels for the A/D Converter. All pins may be used as
comparator inputs or outputs by setting the appropriate
bits in the CMCON register. To use RF as digital
inputs, it is also necessary to turn off the comparators.
Note 1: On device Resets, the RF pins are
configured as analog inputs and are read
as ‘0’.
2: To configure PORTF as digital I/O, set the
corresponding bits in the ANCON0 and
ANCON1 registers.
2007-2012 Microchip Technology Inc.
When Configuration bit, PMPMX = 0, PORTF is
multiplexed with the Parallel Master Port data. This
multiplexing is available only in 80-pin devices.
EXAMPLE 11-7:
CLRF
PORTF
INITIALIZING PORTF
;
;
;
CLRF LATF
;
;
BSF
WDTCON,ADSHR ;
;
MOVLW C0h
;
MOVWF ANCON0
;
MOVLW 0Fh
;
MOVWF ANCON1
;
BCF
WDTCON,ADSHR ;
;
MOVLW CEh
;
MOVWF TRISF
;
;
Initialize PORTF by
clearing output
data latches
Alternate method to
clear output latches
Enable write/read to
the shared SFR
make RF1:RF2 digital
make RF digital
Disable write/read to
the shared SFR
Set RF5:RF4 as outputs,
RF, as inputs
DS39778E-page 155
PIC18F87J11 FAMILY
TABLE 11-14: PORTF FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
RF1
0
O
DIG
LATF data output; not affected by analog input.
1
I
ST
PORTF data input; disabled when analog input is enabled.
RF1/AN6/
C2OUT
AN6
1
I
ANA
A/D Input Channel 6. Default configuration on POR.
C2OUT
x
O
DIG
Comparator 2 output.
RF2
0
O
DIG
LATF data output; not affected by analog input.
1
I
ST
PORTF data input; disabled when analog input is enabled.
PMA5
x
O
DIG
Parallel Master Port address.
AN7
1
I
ANA
A/D Input Channel 7. Default configuration on POR.
C1OUT
x
O
DIG
Comparator 1 output.
RF3
0
O
DIG
LATF data output; not affected by analog input.
1
I
ST
PORTF data input; disabled when analog input is enabled.
AN8
1
I
ANA
A/D Input Channel 8. Default configuration on POR.
C2INB
x
I
ANA
Comparator 2 Input B.
RF4
0
O
DIG
LATF data output; not affected by analog input.
1
I
ST
PORTF data input; disabled when analog input is enabled.
1
I
ANA
A/D Input Channel 9. Default configuration on POR.
RF2/PMA5/
AN7//C1OUT
RF3/AN8/
C2INB
RF4/AN9/
C2INA
AN9
C2INA
x
I
ANA
Comparator 2 Input A.
RF5
0
O
DIG
LATF data output; not affected by analog input. Disabled when
CVREF output is enabled.
1
I
ST
PORTF data input; disabled when analog input is enabled.
Disabled when CVREF output is enabled.
x
O
DIG
Parallel Master Port data out.
RF5/PMD2/
AN10/C1INB/
CVREF
PMD2(1)
x
I
TTL
Parallel Master Port data input.
AN10
1
I
ANA
A/D Input Channel 10 and Comparator C1+ input. Default input
configuration on POR.
C1INB
x
I
ANA
Comparator 1 Input B.
CVREF
x
O
ANA
Comparator voltage reference output. Enabling this feature disables
digital I/O.
RF6
0
O
DIG
LATF data output; not affected by analog input.
1
I
ST
PORTF data input; disabled when analog input is enabled.
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
AN11
1
I
ANA
A/D Input Channel 11 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
C1INA
x
I
ANA
Comparator 1 Input A.
RF7
0
O
DIG
LATF data output.
1
I
ST
PORTF data input.
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
1
I
TTL
Slave select input for MSSP1 module.
RF6/PMD1/
AN11/C1INA
PMD1(1)
RF7/PMD0/
SS1
PMD0(1)
SS1
Legend:
Note 1:
Description
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only.
DS39778E-page 156
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 11-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Name
PORTF
LATF
TRISF
ANCON0
(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
65
64
64
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
—
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
PCFG7
PCFG6
—
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
63
ANCON1(1) PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
63
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.
Note 1: Configuration SFR overlaps with the default SFR at this address; available only when WDTCON = 1.
2007-2012 Microchip Technology Inc.
DS39778E-page 157
PIC18F87J11 FAMILY
11.8
PORTG, TRISG and
LATG Registers
PORTG is a 5-bit wide, bidirectional port. All pins on
PORTG are digital only and tolerate voltages up to
5.5V.
PORTG is multiplexed with EUSART2 functions
(Table 11-16). PORTG pins have Schmitt Trigger input
buffers. PORTG is also multiplexed with address and
control functions of the Parallel Master Port.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
DS39778E-page 158
Although the port itself is only five bits wide,
PORTG bits are still implemented. These are
used to control the weak pull-ups on the I/O ports associated with the External Memory Bus (PORTD, PORTE
and PORTJ). Setting these bits enables the pull-ups.
Since these are control bits and are not associated with
port I/O, the corresponding TRISG and LATG bits are
not implemented.
EXAMPLE 11-8:
CLRF
PORTG
CLRF
LATG
MOVLW
04h
MOVWF
TRISG
INITIALIZING PORTG
;
;
;
;
;
;
;
;
;
;
Initialize PORTG by
clearing output
data latches
Alternate method to clear
output data latches
Value used to initialize
data direction
Set RG1:RG0 as outputs
RG2 as input
RG4:RG3 as outputs
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 11-16: PORTG FUNCTIONS
Pin Name
RG0/PMA8/
ECCP3/P3A
Function
TRIS
Setting
I/O
I/O
Type
RG0
0
O
DIG
1
I
ST
PORTG data input.
x
O
DIG
Parallel Master Port address.
O
DIG
ECCP3 compare and PWM output; takes priority over port data.
PMA8
ECCP3
RG1/PMA7/
TX2/CK2
RG2/PMA6/
RX2/DT2
I
ST
ECCP3 capture input.
0
O
DIG
ECCP3 Enhanced PWM output, Channel A; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG1
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
PMA7
x
O
DIG
Parallel Master Port address.
TX2
1
O
DIG
Synchronous serial data output (EUSART2 module); takes priority over
port data.
CK2
1
O
DIG
Synchronous serial data input (EUSART2 module). User must configure
as an input.
1
I
ST
Synchronous serial clock input (EUSART2 module).
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
PMA6
x
O
DIG
Parallel Master Port address.
RX2
1
I
ST
Asynchronous serial receive data input (EUSART2 module).
DT2
1
O
DIG
Synchronous serial data output (EUSART2 module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSART2 module). User must configure
as an input.
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
x
O
DIG
Parallel Master Port Address Chip Select 1
x
I
TTL
Parallel Master Port Address Chip Select 1.
0
O
DIG
CCP4 compare output and CCP4 PWM output; takes priority over port data.
1
I
ST
CCP4 capture input.
P3D
0
O
DIG
ECCP3 Enhanced PWM output, Channel D; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG4
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
PMCS2
x
O
DIG
Parallel Master Port Address Chip Select 2
CCP5
0
O
DIG
CCP5 compare output and CCP5 PWM output; takes priority over port data.
1
I
ST
CCP5 capture input.
0
O
DIG
ECCP1 Enhanced PWM output, Channel D; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG3
PMCS1
CCP4
RG4/PMCS2/
CCP5/P1D
P1D
Legend:
LATG data output.
P3A
RG2
RG3/PMCS1/
CCP4/P3D
Description
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
2007-2012 Microchip Technology Inc.
DS39778E-page 159
PIC18F87J11 FAMILY
TABLE 11-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Name
Bit 6
Bit 5
RDPU
REPU
RJPU(1)
RG4
RG3
RG2
RG1
RG0
65
LATG
—
—
—
LATG4
LATG3
LATG2
LATG1
LATG0
64
TRISG
—
—
—
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
64
PORTG
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page:
Bit 7
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
DS39778E-page 160
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
11.9
Note:
PORTH, LATH and
TRISH Registers
PORTH is available only on 80-pin
devices.
PORTH is an 8-bit wide, bidirectional I/O port. PORTH
pins are digital only and tolerate voltages up to
5.5V.
All pins on PORTH are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
When the External Memory Interface is enabled, four of
the PORTH pins function as the high-order address
lines for the interface. The address output from the
interface takes priority over other digital I/O. The
corresponding TRISH bits are also overridden. PORTH
pins, RH4 through RH7, are multiplexed with analog
converter inputs. The operation of these pins as analog
inputs is selected by clearing or setting the
corresponding bits in the ANCON1 register. RH2 to
RH6 are multiplexed with the Parallel Master Port and
RH4 to RH6 are multiplexed as comparator inputs.
2007-2012 Microchip Technology Inc.
PORTH can also be configured as the alternate
Enhanced PWM Output Channels B and C for the
ECCP1 and ECCP3 modules. This is done by clearing
the ECCPMX Configuration bit.
EXAMPLE 11-9:
CLRF
CLRF
BSF
MOVLW
MOVWF
BCF
MOVLW
MOVWF
PORTH
INITIALIZING PORTH
;
;
;
LATH
;
;
WDTCON,ADSHR ;
;
F0h
;
ANCON1
;
WDTCON,ADSHR ;
;
H'CF'
;
;
TRISH
;
;
;
Initialize PORTH by
clearing output
data latches
Alternate method to
clear output latches
Enable write/read to
the shared SFR
Configure PORTH as
digital I/O
Disable write/read to
the shared SFR
Value used to initialize
data direction
Set RH as inputs
RH as outputs
RH as inputs
DS39778E-page 161
PIC18F87J11 FAMILY
TABLE 11-18: PORTH FUNCTIONS
Pin Name
RH0/A16
RH1/A17
RH2/A18/
PMD7
RH3/A19/
PMD6
Function
TRIS
Setting
I/O
I/O
Type
RH0
0
O
DIG
1
I
ST
PORTH data input.
A16
x
O
DIG
External Memory Interface, Address Line 16. Takes priority over port data.
RH1
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
A17
x
O
DIG
External Memory Interface, Address Line 17. Takes priority over port data.
RH2
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
x
O
DIG
External Memory Interface, Address Line 18. Takes priority over port data.
PMD7(2)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
A19
x
O
DIG
External Memory Interface, Address Line 19. Takes priority over port data.
PMD6(2)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
x
I
TTL
Parallel Master Port data out.
x
O
DIG
Parallel Master Port data input.
I
ANA
A/D Input Channel 12. Default input configuration on POR; does not affect
digital output.
RH4
PMD3(2)
AN12
RH5/PMBE/
AN13/P3B/
C2IND
P3C(1)
0
O
DIG
ECCP3 Enhanced PWM output, Channel C; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
C2INC
x
I
ANA
Comparator 2 Input C.
RH5
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
x
O
DIG
Parallel Master Port data byte enable.
I
ANA
A/D Input Channel 13. Default input configuration on POR; does not affect
digital output.
O
DIG
ECCP3 Enhanced PWM output, Channel B; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
PMBE(2)
AN13
RH6/PMRD/
AN14/P1C/
C1INC
P3B(1)
0
C2IND
x
I
ANA
Comparator 2 Input D.
RH6
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
x
O
DIG
Parallel Master Port read strobe.
x
I
TTL
Parallel Master Port read in.
I
ANA
A/D Input Channel 14. Default input configuration on POR; does not affect
digital output.
PMRD
(2)
AN14
Legend:
Note 1:
2:
LATH data output.
A18
RH3
RH4/PMD3/
AN12/P3C/
C2INC
Description
P1C(1)
0
O
DIG
ECCP1 Enhanced PWM output, Channel C; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
C1INC
x
I
ANA
Comparator 1 Input C.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignments for P1B/P1C and P3B/P3C when the ECCPMX Configuration bit is cleared. Default assignments
are PORTE.
Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only.
DS39778E-page 162
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 11-18: PORTH FUNCTIONS (CONTINUED)
Pin Name
RH7/PMWR/
AN15/P1B
Function
TRIS
Setting
I/O
I/O
Type
RH7
0
O
DIG
PMWR(2)
LATH data output.
1
I
ST
PORTH data input.
x
O
DIG
Parallel Master Port write strobe.
x
I
TTL
Parallel Master Port write in.
I
ANA
A/D input channel 15. Default input configuration on POR; does not affect
digital output.
O
DIG
ECCP1 Enhanced PWM output, channel B; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
AN15
P1B(1)
Description
0
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignments for P1B/P1C and P3B/P3C when the ECCPMX Configuration bit is cleared. Default assignments
are PORTE.
Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only.
Legend:
Note 1:
2:
TABLE 11-19: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Name
PORTH(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
64
LATH(1)
LATH7
LATH6
LATH5
LATH4
LATH3
LATH2
LATH1
LATH0
65
TRISH(1)
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
64
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
63
ANCON1
(2)
Legend: Shaded cells are not used by PORTH.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
2: Configuration SFR, overlaps with the default SFR at this address; available only when WDTCON = 1.
2007-2012 Microchip Technology Inc.
DS39778E-page 163
PIC18F87J11 FAMILY
11.10 PORTJ, TRISJ and
LATJ Registers
Note:
PORTJ is available only on 80-pin devices.
PORTJ is an 8-bit wide, bidirectional port. All pins on
PORTJ are digital only and tolerate voltages up to 5.5V.
All pins on PORTJ are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note:
These pins are configured as digital inputs
on any device Reset.
When the External Memory Interface is enabled, all of
the PORTJ pins function as control outputs for the
interface. This occurs automatically when the interface
is enabled by clearing the EBDIS control bit
(MEMCON). The TRISJ bits are also overridden.
DS39778E-page 164
Each of the PORTJ pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit RJPU (PORTG). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
EXAMPLE 11-10:
CLRF
PORTJ
CLRF
LATJ
MOVLW
H'CF'
MOVWF
TRISJ
;
;
;
;
;
;
;
;
;
;
INITIALIZING PORTJ
Initialize PORTG by
clearing output
data latches
Alternate method to clear
output data latches
Value used to initialize
data direction
Set RJ3:RJ0 as inputs
RJ5:RJ4 as output
RJ7:RJ6 as inputs
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 11-20: PORTJ FUNCTIONS
Pin Name
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
Function
TRIS
Setting
I/O
I/O
Type
RJ0
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
ALE
x
O
DIG
External Memory Interface address latch enable control output; takes
priority over digital I/O.
RJ1
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
OE
x
O
DIG
External Memory Interface output enable control output; takes priority
over digital I/O.
RJ2
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
WRL
x
O
DIG
External Memory Bus write low byte control; takes priority over
digital I/O.
RJ3
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
WRH
x
O
DIG
External Memory Interface write high byte control output; takes priority
over digital I/O.
RJ4
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
BA0
x
O
DIG
External Memory Interface Byte Address 0 control output; takes
priority over digital I/O.
RJ5
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
CE
x
O
DIG
External Memory Interface chip enable control output; takes priority
over digital I/O.
RJ6
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
LB
x
O
DIG
External Memory Interface lower byte enable control output; takes
priority over digital I/O.
RJ7
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
x
O
DIG
External Memory Interface upper byte enable control output; takes
priority over digital I/O.
UB
Legend:
Description
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 11-21: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Name
PORTJ(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
RJ7
RJ6
RJ5
RJ4
RJ3
RJ2
RJ1
RJ0
65
LATJ(1)
LATJ7
LATJ6
LATJ5
LATJ4
LATJ3
LATJ2
LATJ1
LATJ0
64
TRISJ(1)
TRISJ7
TRISJ6
TRISJ5
TRISJ4
TRISJ3
TRISJ2
TRISJ1
TRISJ0
64
PORTG
RDPU
REPU
RJPU(1)
RG4
RG3
RG2
RG1
RG0
65
Legend: Shaded cells are not used by PORTJ.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
2007-2012 Microchip Technology Inc.
DS39778E-page 165
PIC18F87J11 FAMILY
NOTES:
DS39778E-page 166
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
12.0
PARALLEL MASTER PORT
The Parallel Master Port module (PMP) is a parallel,
8-bit I/O module, specifically designed to communicate
with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory devices
and microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP is highly
configurable. The PMP module can be configured to
serve as either a Parallel Master Port or as a Parallel
Slave Port.
FIGURE 12-1:
Key features of the PMP module include:
• Up to 16 Programmable Address Lines
• Up to Two Chip Select Lines
• Programmable Strobe Options
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support
- Address Support
- 4-Byte Deep, Auto-Incrementing Buffer
• Programmable Wait States
• Selectable Input Voltage Levels
PMP MODULE OVERVIEW
Address Bus
Data Bus
Control Lines
PIC18
Parallel Master Port
PMA
PMALL
PMA
PMALH
Up to 16-Bit Address
EEPROM
PMA
PMA
PMCS1
PMA
PMCS2
PMBE
PMRD
PMRD/PMWR
Microcontroller
LCD
FIFO
Buffer
PMWR
PMENB
PMD
PMA
PMA
2007-2012 Microchip Technology Inc.
8-Bit Data
DS39778E-page 167
PIC18F87J11 FAMILY
12.1
The
PMCON
registers
(Register 12-1
and
Register 12-2) control basic module operations, including turning the module on or off. They also configure
address multiplexing and control strobe configuration.
Module Registers
The PMP module has a total of 14 Special Function
Registers for its operation, plus one additional register
to set configuration options. Of these, 8 registers are
used for control and 6 are used for PMP data transfer.
12.1.1
The PMMODE registers (Register 12-3 and
Register 12-4) configure the various Master and Slave
Operating modes, the data width and interrupt
generation.
CONTROL REGISTERS
The eight PMP Control registers are:
•
•
•
•
The PMEH and PMEL registers (Register 12-5 and
Register 12-6) configure the module’s operation at the
hardware (I/O pin) level.
PMCONH and PMCONL
PMMODEH and PMMODEL
PMSTATL and PMSTATH
PMEH and PMEL
REGISTER 12-1:
The
PMSTAT
registers
(Register 12-7
and
Register 12-8) provide status flags for the module’s
input and output buffers, depending on the operating
mode.
PMCONH: PARALLEL PORT CONTROL HIGH BYTE REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMPEN
—
PSIDL
ADRMUX1
ADRMUX0
PTBEEN
PTWREN
PTRDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PMPEN: Parallel Master Port Enable bit
1 = PMP is enabled
0 = PMP is disabled, no off-chip access is performed
bit 6
Unimplemented: Read as ‘0’
bit 5
PSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 4-3
ADRMUX: Address/Data Multiplexing Selection bits
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD pins
01 = Lower 8 bits of address are multiplexed on PMD pins, upper 8 bits are on PMA
00 = Address and data appear on separate pins
bit 2
PTBEEN: Byte Enable Port Enable bit (16-bit Master mode)
1 = PMBE port is enabled
0 = PMBE port is disabled
bit 1
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
bit 0
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled
0 = PMRD/PMWR port is disabled
DS39778E-page 168
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 12-2:
PMCONL: PARALLEL PORT CONTROL LOW BYTE REGISTER
R/W-0
R/W-0
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0
R/W-0
R/W-0
CSF1
CSF0
ALP
CS2P
CS1P
BEP
WRSP
RDSP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
CSF: Chip Select Function bits
11 = Reserved
10 = PMCS1 and PMCS2 function as chip select
01 = PMCS2 functions as chip select, PMCS1 is used as Address Bit 14 (PMADDRH Address Bit 6)
00 = PMCS2 and PMCS1 are used as Address Bits 15 and 14 (PMADDRH Address Bits 7 and 6)
bit 5
ALP: Address Latch Polarity bit(1)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
bit 4
CS2P: Chip Select 2 Polarity bit(1)
1 = Active-high (PMCS2)
0 = Active-low (PMCS2)
bit 3
CS1P: Chip Select 1 Polarity bit(1)
1 = Active-high (PMCS1/PMCS)
0 = Active-low (PMCS1/PMCS)
bit 2
BEP: Byte Enable Polarity bit
1 = Byte enable active-high (PMBE)
0 = Byte enable active-low (PMBE)
bit 1
WRSP: Write Strobe Polarity bit
For Slave modes and Master mode 2 (PMMODEH = 00, 01, 10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR)
For Master mode 1 (PMMODEH = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
bit 0
RDSP: Read Strobe Polarity bit
For Slave modes and Master mode 2 (PMMODEH = 00, 01, 10):
1 = Read strobe active-high (PMRD)
0 = Read strobe active-low (PMRD)
For Master mode 1 (PMMODEH = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)
Note 1:
These bits have no effect when their corresponding pins are used as address lines.
2007-2012 Microchip Technology Inc.
DS39778E-page 169
PIC18F87J11 FAMILY
REGISTER 12-3:
PMMODEH: PARALLEL PORT MODE HIGH BYTE REGISTER
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUSY
IRQM1
IRQM0
INCM1
INCM0
MODE16
MODE1
MODE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
bit 6-5
IRQM: Interrupt Request Mode bits
11 = Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP
mode), or on a read or write operation when PMA = 11 (Addressable PSP mode only)
10 = No interrupt generated, processor stall is activated
01 = Interrupt is generated at the end of the read/write cycle
00 = No interrupt is generated
bit 4-3
INCM: Increment Mode bits
11 = PSP read and write buffers auto-increment (Legacy PSP mode only)
10 = Decrements ADDR by 1 every read/write cycle
01 = Increments ADDR by 1 every read/write cycle
00 = No increment or decrement of address
bit 2
MODE16: 8/16-Bit Mode bit
1 = 16-Bit mode: Data register is 16 bits, a read or write to the Data register invokes two 8-bit transfers
0 = 8-Bit mode: Data register is 8 bits, a read or write to the Data register invokes one 8-bit transfer
bit 1-0
MODE: Parallel Port Mode Select bits
11 = Master Mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA and PMD)
10 = Master Mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA and PMD)
01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD and PMA)
00 = Legacy Parallel Slave Port mode, control signals (PMRD, PMWR, PMCS and PMD)
DS39778E-page 170
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 12-4:
PMMODEL: PARALLEL PORT MODE LOW BYTE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAITB1(1)
WAITB0(1)
WAITM3
WAITM2
WAITM1
WAITM0
WAITE1(1)
WAITE0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
WAITB: Data Setup to Read/Write Wait State Configuration bits(1)
11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY
10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY
01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY
00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY
bit 5-2
WAITM: Read to Byte Enable Strobe Wait State Configuration bits
1111 = Wait of additional 15 TCY
...
0001 = Wait of additional 1 TCY
0000 = No additional Wait cycles (operation forced into one TCY)
bit 1-0
WAITE1:WAITE0: Data Hold After Strobe Wait State Configuration bits(1)
11 = Wait of 4 TCY
10 = Wait of 3 TCY
01 = Wait of 2 TCY
00 = Wait of 1 TCY
Note 1:
WAITB and WAITE bits are ignored whenever WAITM = 0000.
REGISTER 12-5:
PMEH: PARALLEL PORT ENABLE HIGH BYTE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN15
PTEN14
PTEN13
PTEN12
PTEN11
PTEN10
PTEN9
PTEN8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
PTEN: PMCSx Strobe Enable bits
1 = PMA15 and PMA14 function as either PMA or PMCS2 and PMCS1
0 = PMA15 and PMA14 function as port I/O
bit 5-0
PTEN: PMP Address Port Enable bits
1 = PMA function as PMP address lines
0 = PMA function as port I/O
2007-2012 Microchip Technology Inc.
DS39778E-page 171
PIC18F87J11 FAMILY
REGISTER 12-6:
PMEL: PARALLEL PORT ENABLE LOW BYTE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
PTEN: PMP Address Port Enable bits
1 = PMA function as PMP address lines
0 = PMA function as port I/O
bit 1-0
PTEN: PMALH/PMALL Strobe Enable bits
1 = PMA1 and PMA0 function as either PMA or PMALH and PMALL
0 = PMA1 and PMA0 pads function as port I/O
REGISTER 12-7:
PMSTATH: PARALLEL PORT STATUS HIGH BYTE REGISTER
R-0
R/W-0
U-0
U-0
R-0
R-0
R-0
R-0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IBF: Input Buffer Full Status bit
1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 6
IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full input byte register occurred (must be cleared in software)
0 = No overflow occurred
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
IB3F:IB0F: Input Buffer Status Full bits
1 = Input buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input buffer does not contain any unread data
DS39778E-page 172
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 12-8:
PMSTATL: PARALLEL PORT STATUS LOW BYTE REGISTER
R-1
R/W-0
U-0
U-0
R-1
R-1
R-1
R-1
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6
OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty output byte register (must be cleared in software)
0 = No underflow occurred
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
OB3E:OB0E: Output Buffer n Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted
2007-2012 Microchip Technology Inc.
DS39778E-page 173
PIC18F87J11 FAMILY
12.1.2
DATA REGISTERS
The PMP module uses 6 registers for transferring data
into and out of the microcontroller. They are arranged
as three pairs to allow the option of 16-bit data
operations:
•
•
•
•
PMDIN1H and PMDIN1L
PMDIN2H and PMDIN2L
PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L
PMDOUT2H and PMDOUT2L
The PMDIN1 register is used for incoming data in Slave
modes, and both input and output data in Master
modes. The PMDIN2 register is used for buffering input
data in select Slave modes.
The PMADDRx/PMDOUT1x registers are actually a
single register pair; the name and function is dictated
by the module’s operating mode. In Master modes, the
registers functions as the PMADDRH and PMADDRL
registers, and contain the address of any incoming or
outgoing data. In Slave modes, the registers function
as PMDOUT1H and PMDOUT1L and are used for
outgoing data.
PMADDRH differs from PMADDRL in that it can also
have limited PMP control functions. When the module
is operating in select Master mode configurations, the
REGISTER 12-9:
upper two bits of the register can be used to determine
the operation of chip select signals. If chip select
signals are not used, PMADDR simply functions to hold
the upper 8 bits of the address. The function of the
individual bits in PMADDRH is shown in Register 12-9.
The PMDOUT2H and PMDOUT2L registers are only
used in buffered Slave modes and serve as a buffer for
outgoing data.
12.1.3
PAD CONFIGURATION CONTROL
REGISTER
In addition to the module level configuration options,
the PMP module can also be configured at the I/O pin
for electrical operation. This option allows users to
select either the normal Schmitt Trigger input buffer on
digital I/O pins shared with the PMP, or use TTL level
compatible buffers instead. Buffer configuration is
controlled by the PMPTTL bit in the PADCFG1 register.
The PADCFG1 register is one of the shared address
SFRs, and has the same address as the TMR2 register. PADCFG1 is accessed by setting the ADSHR bit
(WDTCON). Refer to Section 6.3.4.1 “Shared
Address SFRs” for more information.
PMADDRH: PARALLEL PORT ADDRESS REGISTER, HIGH BYTE
(MASTER MODES ONLY)(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CS2
CS1
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
1 = bit is set
0 = bit is cleared
bit 7
CS2: Chip Select 2 bit
If PMCON = 10 or 01:
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive
If PMCON = 11 or 00:
Bit functions as ADDR.
bit 6
CS1: Chip Select 1 bit
If PMCON = 10:
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive
If PMCON = 11 or 0x:
Bit functions as ADDR.
bit 5-0
ADDR: Destination Address bits
Note 1:
x = bit is unknown
In Enhanced Slave mode, PMADDRH functions as PMDOUT1H, one of the Output Data Buffer registers.
DS39778E-page 174
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
12.1.4
PMP MULTIPLEXING OPTIONS
(80-PIN DEVICES)
By default, the PMP and the External Memory Bus
multiplex some of their signals to the same I/O pins on
PORTD and PORTE. It is possible that some applications may require the PMP signals to be located
elsewhere. For these instances, the 80-pin devices can
be configured to multiplex the PMP to different I/O
ports. PMP configuration is determined by the PMPMX
Configuration bit setting; by default, the PMP and EMB
modules share PORTD and PORTE. The optional pin
configuration is shown in Table 12-1.
TABLE 12-1:
PMP PIN MULTIPLEXING FOR
80-PIN DEVICES
Pin Assignment
PMP Function
PMPMX = 1
PMPMX = 0
PMD0
PORTD
PORTF
PMD1
PORTD
PORTF
PMD2
PORTD
PORTF
PMD3
PORTD
PORTH
PMD4
PORTD
PORTA
PMD5
PORTD
PORTA
PMD6
PORTD
PORTH
PMD7
PORTD
PORTH
PMBE
PORTE
PORTH
PMWR
PORTE
PORTH
PMRD
PORTE
PORTH
FIGURE 12-2:
12.2
Slave Port Modes
The primary mode of operation for the module is configured using the MODE bits in the PMMODEH
register. The setting affects whether the module acts as
a slave or a master and it determines the usage of the
control pins.
12.2.1
LEGACY MODE (PSP)
In Legacy mode (PMMODEH = 00 and
PMPEN = 1), the module is configured as a Parallel
Slave Port with the associated enabled module pins
dedicated to the module. In this mode, an external
device, such as another microcontroller or microprocessor, can asynchronously read and write data using
the 8-bit data bus (PMD), the read (PMRD), write
(PMWR) and chip select (PMCS1) inputs. It acts as a
slave on the bus and responds to the read/write control
signals.
Figure 12-2 shows the connection of the Parallel Slave
Port. When chip select is active and a write strobe
occurs (PMCS = 1 and PMWR = 1), the data from
PMD is captured into the PMDIN1L register.
LEGACY PARALLEL SLAVE PORT EXAMPLE
Master
PIC18 Slave
PMD
PMD
PMCS
PMCS1
PMRD
PMRD
PMWR
PMWR
2007-2012 Microchip Technology Inc.
Address Bus
Data Bus
Control Lines
DS39778E-page 175
PIC18F87J11 FAMILY
12.2.1.1
WRITE TO SLAVE PORT
12.2.1.2
When chip select is active and a write strobe occurs
(PMCS = 1 and PMWR = 1), the data from PMD
is captured into the PMDIN1L register. The PMPIF and
IBF flag bits are set when the write ends. The timing for
the control signals in Write mode is shown in
Figure 12-3. The polarity of the control signals are
configurable.
FIGURE 12-3:
READ FROM SLAVE PORT
When chip select is active and a read strobe occurs
(PMCS = 1 and PMRD = 1), the data from the
PMDOUTL1 register (PMDOUTL1) is presented
onto PMD.The timing for the control signals in
Read mode is shown in Figure 12-4.
PARALLEL SLAVE PORT WRITE WAVEFORMS
|
|
|
|
|
|
|
Q4
|
Q1
|
Q2
|
Q3
|
Q4
|
Q1
|
Q2
|
Q3
|
Q4
PMCS1
PMWR
PMRD
PMD
IBF
OBE
PMPIF
FIGURE 12-4:
PARALLEL SLAVE PORT READ WAVEFORMS
|
|
|
|
|
|
|
Q4
PMCS1
PMWR
PMRD
PMD
IBF
OBE
PMPIF
DS39778E-page 176
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
12.2.2
BUFFERED PARALLEL SLAVE
PORT MODE
Buffered Parallel Slave Port mode is functionally identical to the Legacy Parallel Slave Port mode with one
exception: the implementation of 4-level read and write
buffers. Buffered PSP mode is enabled by setting the
INCMx bits in the PMMODE register. If the INCM
bits are set to ‘11’, the PMP module will act as the
Buffered Parallel Slave Port.
When the Buffered mode is active, the
PMDIN1L,PMDIN1H, PMDIN2L and PMDIN2H registers become the write buffers and the PMDOUT1L,
PMDOUT1H, PMDOUT2L and PMDOUT2H registers
become the read buffers. Buffers are numbered 0
through 3, starting with the lower byte of PMDIN1L to
PMDIN2H as the read buffers, and PMDOUT1L to
PMDOUT2H as the write buffers.
12.2.2.1
READ FROM SLAVE PORT
For read operations, the bytes will be sent out sequentially, starting with Buffer 0 (PMDOUT1L) and
ending with Buffer 3 (PMDOUT2H) for every read
strobe. The module maintains an internal pointer to
keep track of which buffer is to be read. Each of the buffers has a corresponding read status bit, OBxE, in the
PMSTATL register. This bit is cleared when a buffer
contains data that has not been written to the bus, and
is set when data is written to the bus. If the current buffer location being read from is empty, a buffer underflow
FIGURE 12-5:
is generated, and the Buffer Overflow flag bit OBUF is
set. If all 4 OBxE status bits are set, then the Output
Buffer Empty flag (OBE) will also be set.
12.2.2.2
WRITE TO SLAVE PORT
For write operations, the data is be stored sequentially,
starting with Buffer 0 (PMDIN1L) and ending with
Buffer 3 (PMDIN2H 25C. Below 25C, TCOFF = 0 ms.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048) s
-(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s
1.05 s
TACQ
=
0.2 s + 1.05 s + 1.2 s
2.45 s
DS39778E-page 314
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
22.2
Selecting and Configuring
Automatic Acquisition Time
The ADCON1 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensuring the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT bits
(ADCON1) remain in their Reset state (‘000’) and
is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQTx bits can be set to select a programmable acquisition time for the A/D module. When
the GO/DONE bit is set, the A/D module continues to
sample the input for the selected acquisition time, then
automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait
for an acquisition time between selecting a channel and
setting the GO/DONE bit.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
22.3
Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable.
There are seven possible options for TAD:
•
•
•
•
•
•
•
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal RC Oscillator
TABLE 22-1:
TAD vs. DEVICE OPERATING
FREQUENCIES
AD Clock Source (TAD)
ADCS
Maximum Device
Frequency
2 TOSC
000
2.86 MHz
4 TOSC
100
5.71 MHz
8 TOSC
001
11.43 MHz
16 TOSC
101
22.86 MHz
32 TOSC
010
40.00 MHz
64 TOSC
110
40.00 MHz
RC(2)
x11
1.00 MHz(1)
Operation
Note 1:
2:
22.4
The RC source has a typical TAD time of
4 s.
For device frequencies above 1 MHz, the
device must be in Sleep mode for the
entire conversion or the A/D accuracy
may be out of specification.
Configuring Analog Port Pins
The ANCON0, ANCON1, TRISA, TRISF and TRISH
registers control the operation of the A/D port pins. The
port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is
cleared (output), the digital output level (VOH or VOL)
will be converted.
The A/D operation is independent of the state of the
CHS bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible but greater than the
minimum TAD (see Parameter 130 in Table 28-31 for
more information).
Table 22-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
2007-2012 Microchip Technology Inc.
DS39778E-page 315
PIC18F87J11 FAMILY
22.5
A/D Conversions
22.6
Figure 22-3 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
An A/D conversion can be started by the “Special Event
Trigger” of the ECCP2 module. This requires that the
CCP2M bits (CCP2CON) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE bit
will be set, starting the A/D acquisition and conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate TACQ time is selected before
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
Figure 22-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the ACQT
bits are set to ‘010’ and selecting a 4 TAD acquisition
time before the conversion starts.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
After the A/D conversion is completed or aborted, a
2 TAD Wait is required before the next acquisition can
be started. After this Wait, acquisition on the selected
channel is automatically started.
Note:
Use of the ECCP2 Trigger
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 22-3:
A/D CONVERSION TAD CYCLES (ACQT = 000, TACQ = 0)
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b4
b1
b0
b6
b7
b2
b9
b8
b3
b5
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
Next Q4: ADRESH/ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
A/D CONVERSION TAD CYCLES (ACQT = 010, TACQ = 4 TAD)
FIGURE 22-4:
TAD Cycles
TACQT Cycles
1
2
3
Automatic
Acquisition
Time
4
1
3
4
5
6
7
8
9
10
11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
DS39778E-page 316
2
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
22.7
A/D Converter Calibration
The A/D Converter in the PIC18F87J11 family of
devices includes a self-calibration feature which compensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON1). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for the offset. Thus, subsequent offsets
will be compensated. An example of a calibration
routine is shown in Example 22-1.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
22.8
Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
EXAMPLE 22-1:
BSF
BCF
BCF
BSF
BSF
BSF
CALIBRATION
BTFSC
BRA
BCF
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT and
ADCS bits in ADCON1 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been completed. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires the A/D RC clock to
be selected. If bits, ACQT, are set to ‘000’ and a
conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCSx bits in the OSCCON register must have already
been cleared prior to starting the conversion.
SAMPLE A/D CALIBRATION ROUTINE
WDTCON,ADSHR
ANCON0,PCFG0
WDTCON,ADSHR
ADCON0,ADON
ADCON1,ADCAL
ADCON0,GO
ADCON0,GO
CALIBRATION
ADCON1,ADCAL
2007-2012 Microchip Technology Inc.
;Enable write/read to the shared SFR
;Make Channel 0 analog
;Disable write/read to the shared SFR
;Enable A/D module
;Enable Calibration
;Start a dummy A/D conversion
;
;Wait for the dummy conversion to finish
;
;Calibration done, turn off calibration enable
;Proceed with the actual A/D conversion
DS39778E-page 317
PIC18F87J11 FAMILY
TABLE 22-2:
Name
SUMMARY OF A/D REGISTERS
Bit 7
INTCON
Bit 6
Bit 5
GIE/GIEH PEIE/GIEL TMR0IE
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
61
PIR1
PMPIF
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
64
PIE1
PMPIE
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
64
IPR1
PMPIP
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
64
PIR2
OSCFIF
CM2IF
CM1IF
—
BCL1IF
LVDIF
TMR3IF
CCP2IF
64
PIE2
OSCFIE
CM2IE
CM1IE
—
BCL1IE
LVDIE
TMR3IE
CCP2IE
64
IPR2
OSCFIP
CM2IP
CM1IP
—
BCL1IP
LVDIP
TMR3IP
CCP2IP
64
ADRESH
A/D Result Register High Byte
63
ADRESL
A/D Result Register Low Byte
63
(2)
ADCON0
VCFG1
VCFG0
CHS3
CHS3
CHS1
CHS0
GO/DONE
ADON
63
ANCON0(3)
PCFG7
PCFG6
—
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
63
(2)
ADCON1
ANCON1(3)
ADFM
ADCAL
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
63
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
63
CCP2CON
P2M1
P2M0
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
63
PORTA
RA7(4)
RA6(4)
RA5
RA4
RA3
RA2
RA1
RA0
65
TRISA
TRISA7(4)
TRISA6(4)
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
64
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
65
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
64
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
65
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
64
PORTH(1)
TRISH(1)
Legend:
Note 1:
2:
3:
4:
— = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
This register is not implemented on 64-pin devices.
Default (legacy) SFR at this address, available when WDTCON = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are
unimplemented.
DS39778E-page 318
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
23.0
COMPARATOR MODULE
23.1
The analog comparator module contains two comparators that can be independently configured in a variety of
ways. The inputs can be selected from the analog
inputs and two internal voltage references. The digital
outputs are available at the pin level and can also be
read through the control register. Multiple output and
interrupt event generation are also available. A generic
single comparator from the module is shown in
Figure 23-1.
Registers
The CMxCON registers (Register 23-1) select the input
and output configuration for each comparator, as well
as the settings for interrupt generation.
The CMSTAT register (Register 23-2) provides the output results of the comparators. The bits in this register
are read-only.
Key features of the module includes:
•
•
•
•
•
Independent comparator control
Programmable input configuration
Output to both pin and register levels
Programmable output polarity
Independent interrupt generation for each
comparator with configurable interrupt-on-change
FIGURE 23-1:
COMPARATOR SIMPLIFIED BLOCK DIAGRAM
CxOUT
(CMSTAT)
CCH
CxINB
0
CxINC
1(1)
CxIND
2(1,2)
VIRV
Interrupt
Logic
CMxIF
3
EVPOL
CREF
VIN-
CxINA
0
CVREF
1
Note 1:
2:
COE
–
VIN+
Cx
Polarity
Logic
CON
CPOL
CxOUT
Available in 80-pin devices only.
Implemented in Comparator 2 only.
2007-2012 Microchip Technology Inc.
DS39778E-page 319
PIC18F87J11 FAMILY
REGISTER 23-1:
R/W-0
CMxCON: COMPARATORx CONTROL REGISTER
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
bit 0
CON
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
CON: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 6
COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 5
bit 4-3
EVPOL: Interrupt Polarity Select bits
11 = Interrupt generation on any change of the output(1)
10 = Interrupt generation only on high-to-low transition of the output
01 = Interrupt generation only on low-to-high transition of the output
00 = Interrupt generation is disabled
CREF: Comparator Reference Select bit (non-inverting input)
1 = Non-inverting input connects to internal CVREF voltage
0 = Non-inverting input connects to CxINA pin
bit 2
bit 1-0
CCH: Comparator Channel Select bits
11 = Inverting input of comparator connects to VIRV
10 = Inverting input of comparator connects to CxIND pin(2)
01 = Inverting input of comparator connects to CxINC pin(2)
00 = Inverting input of comparator connects to CxINB pin
Note 1:
2:
The CMxIF bit is automatically set any time this mode is selected and must be cleared by the application
after the initial configuration.
Available in 80-pin devices only.
DS39778E-page 320
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 23-2:
CMSTAT: COMPARATOR OUTPUT STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R-1
—
—
—
—
—
—
COUT2
bit 7
R-1
COUT1
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
bit 7-2
Unimplemented: Read as ‘0’
bit 1-0
COUT: Comparator x Status bits
If CPOL = 0 (non-inverted polarity):
1 = Comparator’s VIN+ > VIN0 = Comparator’s VIN+ < VINIf CPOL = 1 (inverted polarity):
1 = Comparator VIN+ < VIN0 = Comparator VIN+ > VIN-
2007-2012 Microchip Technology Inc.
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DS39778E-page 321
PIC18F87J11 FAMILY
23.2
Comparator Operation
23.3
Comparator Response Time
A single comparator is shown in Figure 23-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 23-2 represent
the uncertainty due to input offsets and response time.
Response time is the minimum time, after selecting a
new reference voltage or input source, before the comparator output has a valid level. The response time of
the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be
considered when determining the total response to a
comparator input change. Otherwise, the maximum
delay of the comparators should be used (see
Section 28.0 “Electrical Characteristics”).
FIGURE 23-2:
SINGLE COMPARATOR
23.4
+
A simplified circuit for an analog input is shown in
Figure 23-3. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 k is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
VIN+
VIN-
Output
–
VINVIN+
Output
FIGURE 23-3:
Analog Input Connection
Considerations
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RS < 10k
Comparator
Input
AIN
CPIN
5 pF
VA
RIC
VT = 0.6V
ILEAKAGE
±500 nA
VSS
Legend:
DS39778E-page 322
CPIN
VT
ILEAKAGE
RIC
RS
VA
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the pin due to various junctions
Interconnect Resistance
Source Impedance
Analog Voltage
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
23.5
Comparator Control and
Configuration
Each comparator has up to eight possible combinations of inputs: up to four external analog inputs, and
one of two internal voltage references.
Both comparators allow a selection of the signal from
pin, CxINA, or the voltage from the comparator reference (CVREF) on the non-inverting channel. This is
compared to either CxINB, CxINC, CxIND or the microcontroller’s fixed internal reference voltage (VIRV, 1.2V
nominal) on the inverting channel. The comparator
inputs and outputs are tied to fixed I/O pins, defined in
Table 23-1. The available configurations and their
corresponding bit settings are shown in Figure 23-1.
TABLE 23-1:
Comparator
1
COMPARATOR INPUTS AND
OUTPUTS
Input or Output
I/O Pin
C1INA (VIN+)
RF6
C1INB (VIN-)
RF5
C1INC
(VIN-)(1)
RH6(1)
C1OUT
2
Note 1:
23.5.1
RF2
C2INA(VIN+)
RF4
C2INB(VIN-)
RF3
C2INC(VIN-)(1)
C2IND(VIN-)(1)
RH4(1)
C2OUT
RF1
RH5(1)
Available in 80-pin devices only.
COMPARATOR ENABLE AND
INPUT SELECTION
Setting the CON bit of the CMxCON register
(CMxCON) enables the comparator for operation.
Clearing the CON bit disables the comparator resulting
in minimum current consumption.
The CCH bits in the CMxCON register
(CMxCON) direct either one of three analog input
pins, or the Internal Reference Voltage (VIRV), to the
comparator VIN-. Depending on the comparator operating mode, either an external or internal voltage
reference may be used. The analog signal present at
VIN- is compared to the signal at VIN+ and the digital
output of the comparator is adjusted accordingly.
The
external
reference
is
used
when
CREF (CMxCON) = 0 and VIN+ is connected to the
CxINA pin. When external voltage references are used,
the comparator module can be configured to have the
reference sources externally. The reference signal
must be between VSS and VDD, and can be applied to
either pin of the comparator.
2007-2012 Microchip Technology Inc.
The comparator module also allows the selection of an
internally generated voltage reference (CVREF) from
the comparator voltage reference module. This module
is described in more detail in Section 24.0 “Comparator Voltage Reference Module”. The reference from
the comparator voltage reference module is only available when CREF = 1. In this mode, the internal voltage
reference is applied to the comparator’s VIN+ pin.
Note:
23.5.1.1
The comparator input pin, selected by
CCH, must be configured as an input
by setting both the corresponding TRISF or
TRISH bit, and the corresponding PCFGx
bit in the ANCON1 register.
Comparator Configurations in 64-Pin
and 80-Pin Devices
In PIC18F87J11 family devices, the C and D input channels for both comparators are linked to pins in PORTH
and cannot be reassigned to alternate analog inputs.
Because of this, 64-pin devices offer a total of 4 different
configurations for each comparator. In contrast, 80-pin
devices offer a choice of 6 configurations for
Comparator 1 and 8 configurations for Comparator 2.
The configurations shown in Figure 23-1 are footnoted to
indicate where they are not available.
23.5.2
COMPARATOR ENABLE AND
OUTPUT SELECTION
The comparator outputs are read through the CMSTAT
register. The CMSTAT reads the Comparator 1 output and CMSTAT reads the Comparator 2 output.
These bits are read-only.
The comparator outputs may also be directly output to
the RF1 and RF2 I/O pins by setting the COE bit
(CMxCON). When enabled, multiplexors in the
output path of the pins switch to the output of the comparator. The TRISF bits still function as the digital
output enable bits for the RF1 and RF2 pins while in
this mode.
By default, the comparator’s output is at logic high
whenever the voltage on VIN+ is greater than on VIN-.
The polarity of the comparator outputs can be inverted
using the CPOL bit (CMxCON).
The uncertainty of each of the comparators is related to
the input offset voltage and the response time given in
the specifications, as discussed in Section 23.2
“Comparator Operation”.
DS39778E-page 323
PIC18F87J11 FAMILY
FIGURE 23-4:
COMPARATOR I/O CONFIGURATIONS
Comparator Off
CON = 0, CREF = x, CCH = xx
COE
VIN-
–
Cx
VIN+
Off (Read as ‘0’)
CxOUT
Pin
Comparator CxINC > CxINA Compare(1)
CON = 1, CREF = 0, CCH = 01
Comparator CxINB > CxINA Compare
CON = 1, CREF = 0, CCH = 00
COE
CxINB
CxINA
VIN-
COE
–
Cx
VIN+
CxOUT
Pin
Comparator CxIND > CxINA Compare(1,2)
CON = 1, CREF = 0, CCH = 10
CxINC
VIN-
CxINA
VIN+
–
Cx
CxOUT
Pin
Comparator VIRV > CxINA Compare
CON = 1, CREF = 0, CCH = 11
COE
CxIND
VIN-
CxINA
VIN+
COE
–
Cx
CxOUT
Pin
VIRV
VIN-
CxINA
VIN+
–
Cx
CxOUT
Pin
Comparator CxINC > CVREF Compare(1)
CON = 1, CREF = 1, CCH = 01
Comparator CxINB > CVREF Compare
CON = 1, CREF = 1, CCH = 00
COE
CxINB
CVREF
VIN-
COE
–
Cx
VIN+
CxOUT
Pin
Comparator CxIND > CVREF Compare(1,2)
CON = 1, CREF = 1, CCH = 10
CxINC
VIN-
CVREF
VIN+
–
Cx
CxOUT
Pin
Comparator VIRV > CVREF Compare
CON = 1, CREF = 1, CCH = 11
COE
CxIND
CVREF
Legend:
Note 1:
2:
VINVIN+
COE
–
Cx
CxOUT
Pin
VIRV
VIN-
CVREF
VIN+
–
Cx
CxOUT
Pin
VIRV = Fixed Interval Reference Voltage (1.2V nominal), CVREF = Comparator Voltage Reference module output.
Configurations are available on both Comparators 1 and 2 in all package sizes unless otherwise noted.
Configuration is available in 80-pin devices only.
Configuration is available in Comparator 2 only (80-pin devices).
DS39778E-page 324
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
23.6
Comparator Interrupts
The comparator interrupt flag is set whenever any of
the following occurs:
• Low-to-high transition of the comparator output
• High-to-low transition of the comparator output
• Any change in the comparator output
The comparator interrupt selection is done by the
EVPOL bits in the CMxCON register
(CMxCON).
In order to provide maximum flexibility, the output of the
comparator may be inverted using the CPOL bit in the
CMxCON register (CMxCON). This is functionally
identical to reversing the inverting and non-inverting
inputs of the comparator for a particular mode.
An interrupt is generated on the low-to-high or high-tolow transition of the comparator output. This mode of
interrupt generation is dependent on EVPOL in
the CMxCON register. If EVPOL = 01 or 10, the
interrupt is generated on a low-to-high or high-to-low
TABLE 23-2:
CPOL
transition of the comparator output. Once the interrupt
is generated, it is required to clear the interrupt flag by
software.
When EVPOL = 11, the comparator interrupt flag
is set whenever there is a change in the output value of
either comparator. Software will need to maintain information about the status of the output bits, as read from
CMSTAT, to determine the actual change that
occurred. The CMxIF bits (PIR2) are the Comparator Interrupt Flags. The CMxIF bits must be reset by
clearing them. Since it is also possible to write a ‘1’ to
this register, a simulated interrupt may be initiated.
Table 23-2 shows the interrupt generation with respect
to comparator input voltages and EVPOLx bit settings.
Both the CMxIE bits (PIE2) and the PEIE bit
(INTCON) must be set to enable the interrupt. In
addition, the GIE bit (INTCON) must also be set. If
any of these bits are clear, the interrupt is not enabled,
though the CMxIF bits will still be set if an interrupt
condition occurs.
COMPARATOR INTERRUPT GENERATION
EVPOL
00
01
0
10
11
00
01
1
10
11
2007-2012 Microchip Technology Inc.
Comparator
Input Change
CxOUT Transition
Interrupt
Generated
VIN+ > VIN-
Low-to-High
No
VIN+ < VIN-
High-to-Low
No
VIN+ > VIN-
Low-to-High
Yes
VIN+ < VIN-
High-to-Low
No
VIN+ > VIN-
Low-to-High
No
VIN+ < VIN-
High-to-Low
Yes
VIN+ > VIN-
Low-to-High
Yes
VIN+ < VIN-
High-to-Low
Yes
VIN+ > VIN-
High-to-Low
No
VIN+ < VIN-
Low-to-High
No
VIN+ > VIN-
High-to-Low
No
VIN+ < VIN-
Low-to-High
Yes
VIN+ > VIN-
High-to-Low
Yes
VIN+ < VIN-
Low-to-High
No
VIN+ > VIN-
High-to-Low
Yes
VIN+ < VIN-
Low-to-High
Yes
DS39778E-page 325
PIC18F87J11 FAMILY
23.7
Comparator Operation
During Sleep
23.8
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
Each operational comparator will consume additional
current. To minimize power consumption while in Sleep
mode, turn off the comparators (CON = 0) before
entering Sleep. If the device wakes up from Sleep, the
contents of the CMxCON register are not affected.
TABLE 23-3:
Name
A device Reset forces the CMxCON registers to their
Reset state. This forces both comparators and the
voltage reference to the OFF state.
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7
INTCON
Effects of a Reset
Bit 6
Bit 5
GIE/GIEH PEIE/GIEL TMR0IE
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
61
PIR2
OSCFIF
CM2IF
CM1IF
—
BCL1IF
LVDIF
TMR3IF
CCP2IF
64
PIE2
OSCFIE
CM2IE
CM1IE
—
BCL1IE
LVDIE
TMR3IE
CCP2IE
64
IPR2
OSCFIP
CM2IP
CM1IP
—
BCL1IP
LVDIP
TMR3IP
CCP2IP
64
CM1CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
62
CM2CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
62
—
—
—
—
—
—
COUT2
COUT1
62
CVRCON(2)
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
65
(2)
ANCON1
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
63
ANCON0(2)
PCFG7
PCFG6
—
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
63
CMSTAT
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
65
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
—
64
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
64
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
65
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
64
PORTH(1)
(1)
TRISH
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These registers are not implemented on 64-pin devices.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
DS39778E-page 326
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
24.0
COMPARATOR VOLTAGE
REFERENCE MODULE
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable reference
voltage. Although its primary purpose is to provide a
reference for the analog comparators, it may also be
used independently of them.
FIGURE 24-1:
A block diagram of the module is shown in Figure 24-1.
The resistor ladder is segmented to provide two ranges
of CVREF values and has a power-down function to
conserve power when the reference is not being used.
The module’s supply reference can be provided from
either device VDD/VSS or an external voltage reference.
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+
VDD
CVRSS = 1
8R
CVRSS = 0
CVR
R
CVREN
R
R
16-to-1 MUX
R
16 Steps
R
CVREF
R
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
2007-2012 Microchip Technology Inc.
DS39778E-page 327
PIC18F87J11 FAMILY
24.1
Configuring the Comparator
Voltage Reference
The comparator voltage reference module is controlled
through the CVRCON register (Register 24-1). The
comparator voltage reference provides two ranges of
output voltage, each with 16 distinct levels. The range
to be used is selected by the CVRR bit (CVRCON).
The primary difference between the ranges is the size
of the steps selected by the CVREF Selection bits
(CVR), with one range offering finer resolution.
The equations used to calculate the output of the
comparator voltage reference are as follows:
If CVRR = 1:
CVREF = ((CVR)/24) x (CVRSRC)
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit
(CVRCON).
The settling time of the comparator voltage reference must be considered when changing the CVREF
output (see Table 28-3 in Section 28.0 “Electrical
Characteristics”).
The CVRCON register is a shared address SFR and
uses the same address as the PR4 register. The
CVRCON register is accessed by setting the ADSHR
bit (WDTCON).
If CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR)/32) x (CVRSRC)
REGISTER 24-1:
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE(1)
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit is powered on
0 = CVREF circuit is powered down
bit 6
CVROE: Comparator VREF Output Enable bit(1)
1 = CVREF voltage level is also output on the RF5/AN10/C1INB/CVREF pin
0 = CVREF voltage is disconnected from the RF5/AN10/C1INB/CVREF pin
bit 5
CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
bit 4
CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator reference source, CVRSRC = AVDD – AVSS
bit 3-0
CVR: Comparator VREF Value Selection bits (0 (CVR3:CVR0) 15)
When CVRR = 1:
CVREF = ((CVR)/24) (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR)/32) (CVRSRC)
Note 1:
CVROE overrides the TRISF bit setting.
DS39778E-page 328
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
24.2
Voltage Reference Accuracy/Error
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 24-1) keep CVREF from approaching the reference source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 28.0 “Electrical Characteristics”.
24.3
Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
CVROE bit is set. Enabling the voltage reference output onto RA2 when it is configured as a digital input will
increase current consumption. Connecting RF5 as a
digital output with CVRSS enabled will also increase
current consumption.
FIGURE 24-2:
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 24-2 shows an example buffering technique.
24.4
Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
24.5
Effects of a Reset
A device Reset disables the voltage reference by
clearing CVREN (CVRCON). This Reset also
disconnects the reference from the RA2 pin by clearing
CVROE, and selects the high-voltage range by clearing
CVRR. The CVRx value select bits are also cleared.
COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC18F87J11
CVREF
Module
Note 1:
TABLE 24-1:
R(1)
Voltage
Reference
Output
Impedance
+
–
RF5
CVREF Output
R is dependent upon the comparator voltage reference configuration bits, CVRCON and CVRCON.
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
CVRCON(2)
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
65
CM1CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
62
CM2CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
62
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
64
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
64
—
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
63
PCFG13 PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
63
TRISA
TRISA7
TRISF7
TRISF
ANCON0
(1)
(2)
ANCON1(2)
TRISA6
(1)
TRISF6
PCFG7
PCFG6
PCFG15
PCFG14
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.
Note 1: These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are
unimplemented.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
2007-2012 Microchip Technology Inc.
DS39778E-page 329
PIC18F87J11 FAMILY
NOTES:
DS39778E-page 330
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
25.0
SPECIAL FEATURES OF THE
CPU
PIC18F87J11 family devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These are:
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 3.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet. In
addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F87J11 family of
devices have a configurable Watchdog Timer which is
controlled in software.
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executed
almost immediately on start-up, while the primary clock
source completes its start-up delays.
25.1.1
CONSIDERATIONS FOR
CONFIGURING THE PIC18F87J11
FAMILY DEVICES
Unlike previous PIC18 microcontrollers, devices of the
PIC18F87J11 family do not use persistent memory
registers to store configuration information. The configuration bytes are implemented as volatile memory
which means that configuration data must be
programmed each time the device is powered up.
Configuration data is stored in the four words at the top
of the on-chip program memory space, known as the
Flash Configuration Words. It is stored in program
memory in the same order shown in Table 25-2, with
CONFIG1L at the lowest address and CONFIG3H at
the highest. The data is automatically loaded in the
proper Configuration registers during device power-up
or after any device Reset.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
The four Most Significant bits of CONFIG1H,
CONFIG2H and CONFIG3H in program memory
should also be ‘1111’. This makes these Configuration
Words appear to be NOP instructions in the remote
event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
25.1
Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h. A complete list
is shown in Table 25-2. A detailed explanation of the
various bit functions is provided in Register 25-1
through Register 25-6.
2007-2012 Microchip Technology Inc.
DS39778E-page 331
PIC18F87J11 FAMILY
TABLE 25-1:
MAPPING OF THE FLASH CONFIGURATION WORDS TO THE
CONFIGURATION REGISTERS
Configuration Byte
Code Space Address
Configuration Register
Address
CONFIG1L
XXXF8h
300000h
CONFIG1H
XXXF9h
300001h
CONFIG2L
XXXFAh
300002h
CONFIG2H
XXXFBh
300003h
CONFIG3L
XXXFCh
300004h
CONFIG3H
XXXFDh
300005h
TABLE 25-2:
CONFIGURATION BITS AND DEVICE IDs
Bit 7
Bit 6
Bit 5
300000h CONFIG1L
DEBUG
XINST
300001h CONFIG1H
—(2)
—(2)
300002h CONFIG2L
IESO
FCMEN
—
—
—
FOSC2
FOSC1
FOSC0
11-- -111
300003h CONFIG2H
—(2)
—(2)
—(2)
—(2)
WDTPS3
WDTPS2
WDTPS1
WDTPS0
1111 1111
300004h CONFIG3L
WAIT(3)
BW(3)
EMB1(3)
EMB0(3)
EASHFT(3)
—
—
—
300005h CONFIG3H
—(2)
—(2)
—(2)
—(2)
3FFFFEh DEVID1
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
xxx0 0000(4)
3FFFFFh DEVID2
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
0100 00xx(4)
Legend:
Note 1:
2:
3:
4:
Bit 4
Bit 3
STVREN
—
—(2)
—(2)
Default/
Unprogrammed
Value(1)
File Name
Bit 2
Bit 1
Bit 0
—
—
—
WDTEN
111- ---1
—
CP0
—
—
1111 -111
MSSPMSK PMPMX(3) ECCPMX(3) CCP2MX
1111 1--1111 1111
x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset
states, the configuration bytes maintain their previously programmed states.
The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it
is accidentally executed.
These bits are implemented in 80-pin devices only.
See Register 25-7 and Register 25-8 for DEVID values. These registers are read-only and cannot be programmed by
the user.
DS39778E-page 332
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 25-1:
CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
R/WO-1
R/WO-1
R/WO-1
U-0
U-0
U-0
U-0
R/WO-1
DEBUG
XINST
STVREN
—
—
—
—
WDTEN
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
DEBUG: Background Debugger Enable bit
1 = Background debugger is disabled; RB6 and RB7 are configured as general purpose I/O pins
0 = Background debugger is enabled; RB6 and RB7 are dedicated to In-Circuit Debug
bit 6
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode are enabled
0 = Instruction set extension and Indexed Addressing mode are disabled (Legacy mode)
bit 5
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow is enabled
0 = Reset on stack overflow/underflow is disabled
bit 4-1
Unimplemented: Read as ‘0’
bit 0
WDTEN: Watchdog Timer Enable bit
1 = WDT is enabled
0 = WDT is disabled (control is placed on the SWDTEN bit)
REGISTER 25-2:
CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
U-1
U-1
U-1
U-1
U-0
R/WO-1
U-1
U-1
—
—
—
—
—
CP0
—
—
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Maintain as ‘11110’
bit 2
CP0: Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is code-protected
bit 1-0
Unimplemented: Read as ‘0’
2007-2012 Microchip Technology Inc.
x = Bit is unknown
DS39778E-page 333
PIC18F87J11 FAMILY
REGISTER 25-3:
CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
R/WO-1
R/WO-1
U-0
U-0
U-0
R/WO-1
R/WO-1
R/WO-1
IESO
FCMEN
—
—
—
FOSC2
FOSC1
FOSC0
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit
1 = Two-Speed Start-up is enabled
0 = Two-Speed Start-up is disabled
bit 6
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 5-3
Unimplemented: Read as ‘0’
bit 2-0
FOSC: Oscillator Selection bits
111 = EC oscillator with PLL enabled; CLKO on RA6 (ECPLL)
110 = EC oscillator; CLKO on RA6 (EC)
101 = HS oscillator with PLL enabled (HSPLL)
100 = HS oscillator (HS)
011 = Internal oscillator with PLL enabled; CLKO on RA6, port function on RA7 (INTPLL1)
010 = Internal oscillator with PLL enabled; port function on RA6 and RA7 (INTPLL2)
001 = Internal oscillator block; CLKO on RA6, port function on RA7 (INTIO1)
000 = Internal oscillator block; port function on RA6 and RA7 (INTIO2)
DS39778E-page 334
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 25-4:
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-1
U-1
U-1
U-1
R/WO-1
R/WO-1
R/WO-1
R/WO-1
—
—
—
—
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Maintain as ‘1’
bit 3-0
WDTPS: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
2007-2012 Microchip Technology Inc.
x = Bit is unknown
DS39778E-page 335
PIC18F87J11 FAMILY
REGISTER 25-5:
R/WO-1
CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)
R/WO-1
(1)
(1)
BW
WAIT
R/WO-1
R/WO-1
(1)
(1)
EMB1
EMB0
R/WO-1
EASHFT
(1)
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WAIT: External Bus Wait Enable bit(1)
1 = Wait states on the external bus are disabled
0 = Wait states on the external bus are enabled and selected by MEMCON
bit 6
BW: Data Bus Width Select bit(1)
1 = 16-Bit Data Width modes
0 = 8-Bit Data Width modes
bit 5-4
EMB: External Memory Bus Configuration bits(1)
11 = Microcontroller mode, external bus is disabled
10 = Extended Microcontroller mode, 12-bit address width for external bus
01 = Extended Microcontroller mode, 16-bit address width for external bus
00 = Extended Microcontroller mode, 20-bit address width for external bus
bit 3
EASHFT: External Address Bus Shift Enable bit(1)
1 = Address shifting is enabled – external address bus is shifted to start at 000000h
0 = Address shifting is disabled – external address bus reflects the PC value
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
These bits are implemented on 80-pin devices only.
DS39778E-page 336
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 25-6:
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-1
U-1
U-1
U-1
R/WO-1
R/WO-1
R/WO-1
R/WO-1
—
—
—
—
MSSPMSK
PMPMX(1)
ECCPMX(1)
CCP2MX
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
Unimplemented: Maintain as ‘1’
bit 3
MSSPMSK: MSSP Address Masking Mode Select bit
1 = 7-Bit Address Masking mode is enabled
0 = 5-Bit Address Masking mode is enable
bit 2
PMPMX: PMP Pin Multiplex bit(1)
1 = PMP data and control are multiplexed to the same pins as the External Memory Bus (PORTD and
PORTE)
0 = PMP data and control are multiplexed to alternate pin assignments (PORTA, PORTF and
PORTH)
bit 1
ECCPMX: ECCPx MUX bit(1)
1 = ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5;
ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3
0 = ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6;
ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4
bit 0
CCP2MX: ECCP2 MUX bit
1 = ECCP2/P2A is multiplexed with RC1
0 = ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (all devices) or with RB3 in Extended
Microcontroller mode (80-pin devices only)
Note 1:
These bits are implemented on 80-pin devices only.
2007-2012 Microchip Technology Inc.
DS39778E-page 337
PIC18F87J11 FAMILY
REGISTER 25-7:
DEVID1: DEVICE ID REGISTER 1 FOR PIC18F87J11 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
DEV: Device ID bits
See Register 25-8 for a complete listing.
bit 4-0
REV: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 25-8:
x = Bit is unknown
DEVID2: DEVICE ID REGISTER 2 FOR PIC18F87J11 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
DEV: Device ID bits:
DS39778E-page 338
DEV
(DEVID2)
DEV
(DEVID1)
0100 0100
010
PIC18F66J11
0100 0100
011
PIC18F66J16
0100 0100
100
PIC18F67J11
0100 0100
111
PIC18F86J11
0100 0101
000
PIC18F86J16
0100 0101
001
PIC18F87J11
Device
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
25.2
Watchdog Timer (WDT)
For PIC18F87J11 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPSx
bits in Configuration Register 2H. Available periods
range from about 4 ms to 135 seconds (2.25 minutes
depending on voltage, temperature and WDT postscaler). The WDT and postscaler are cleared whenever
a SLEEP or CLRWDT instruction is executed, or a clock
failure (primary or Timer1 oscillator) has occurred.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
25.2.1
CONTROL REGISTER
The WDTCON register (Register 25-9) is a readable
and writable register. The SWDTEN bit enables or disables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
The ADSHR bit selects which SFRs are currently
selected and accessible. See Section 6.3.4.1 “Shared
Address SFRs” for additional details.
The LVDSTAT is a read-only status bit which is continuously updated and provides information about the current
level of VDDCORE. This bit is only valid when the on-chip
voltage regulator is enabled.
FIGURE 25-1:
SWDTEN
WDT BLOCK DIAGRAM
Enable WDT
INTRC Control
WDT Counter
INTRC Oscillator
Wake-up from
Power-Managed
Modes
128
Programmable Postscaler
1:1 to 1:32,768
CLRWDT
All Device Resets
Reset
WDT
Reset
WDT
WDTPS
4
Sleep
2007-2012 Microchip Technology Inc.
DS39778E-page 339
PIC18F87J11 FAMILY
REGISTER 25-9:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0
R-x
U-0
R/W-0
U-0
U-0
U-0
U-0
REGSLP
LVDSTAT
—
ADSHR
—
—
—
SWDTEN(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
REGSLP: Voltage Regulator Low-Power Operation Enable bit
1 = On-chip regulator enters low-power operation when device enters Sleep mode
0 = On-chip regulator is active, even in Sleep mode
bit 6
LVDSTAT: LVD Status bit
1 = VDDCORE > 2.45V
0 = VDDCORE < 2.45V
bit 5
Unimplemented: Read as ‘0’
bit 4
ADSHR: Shared Address SFR Select bit
For details of bit operation, see Register 6-3.
bit 3-1
Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1:
This bit has no effect if the Configuration bit, WDTEN, is enabled.
TABLE 25-3:
Name
RCON
WDTCON
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7
Bit 6
Bit 5
IPEN
—
REGSLP LVDSTAT
Bit 0
Reset Values
on Page:
Bit 4
Bit 3
Bit 2
Bit 1
CM
RI
TO
PD
POR
BOR
62
—
ADSHR
—
—
—
SWDTEN
63
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
DS39778E-page 340
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
25.3
On-Chip Voltage Regulator
All of the PIC18F87J11 family devices power their core
digital logic at a nominal 2.5V. For designs that are
required to operate at a higher typical voltage, such as
3.3V, all devices in the PIC18F87J11 family incorporate
an on-chip regulator that allows the device to run its
core logic from VDD.
The regulator is controlled by the ENVREG pin. Tying
VDD to the pin enables the regulator, which in turn,
provides power to the core from the other VDD pins.
When the regulator is enabled, a low-ESR filter capacitor must be connected to the VDDCORE/VCAP pin
(Figure 25-2). This helps to maintain the stability of the
regulator. The recommended value for the filter capacitor is provided in Section 28.3 “DC Characteristics:
PIC18F87J11 Family (Industrial)”.
If ENVREG is tied to VSS, the regulator is disabled. In
this case, separate power for the core logic at a nominal 2.5V must be supplied to the device on the
VDDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the VDDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 25-2 for possible
configurations.
25.3.1
FIGURE 25-2:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
Regulator Enabled (ENVREG tied to VDD):
3.3V
PIC18F87J11
VDD
ENVREG
VDDCORE/VCAP
CF
VSS
Regulator Disabled (ENVREG tied to ground):
2.5V(1)
3.3V(1)
PIC18F87J11
VDD
ENVREG
VDDCORE/VCAP
VSS
VOLTAGE REGULATOR TRACKING
MODE AND LOW-VOLTAGE
DETECTION
When it is enabled, the on-chip regulator provides a
constant voltage of 2.5V nominal to the digital core
logic. The regulator can provide this level from a VDD of
about 2.5V, all the way up to the device’s VDDMAX. It
does not have the capability to boost VDD levels below
2.5V. In order to prevent “brown-out” conditions, when
the voltage drops too low for the regulator, the regulator
enters Tracking mode. In Tracking mode, the regulator
output follows VDD, with a typical voltage drop of
100 mV.
The on-chip regulator includes a simple, Low-Voltage
Detect (LVD) circuit. If VDD drops too low to maintain
approximately 2.45V on VDDCORE, the circuit sets the
Low-Voltage Detect Interrupt Flag, LVDIF (PIR2).
This can be used to generate an interrupt and put the
application into a low-power operational mode, or
trigger an orderly shutdown. Low-Voltage Detection is
only available when the regulator is enabled.
Regulator Disabled (VDD tied to VDDCORE):
2.5V(1)
PIC18F87J11
VDD
ENVREG
VDDCORE/VCAP
VSS
Note 1:
These are typical operating voltages. Refer
to Section 28.1 “DC Characteristics:
Supply Voltage” for the full operating
ranges of VDD and VDDCORE.
The Low-Voltage Detect interrupt is edge-sensitive.
The interrupt flag will only be set once per falling edge
of VDDCORE. Firmware can clear the interrupt flag, but
a new interrupt will not be generated until VDDCORE
rises back above, and then falls below, the 2.45 threshold. Upon device Resets, the interrupt flag will reset to
‘0’, even if VDDCORE is less than 2.45V. When the
regulator is enabled, the LVDSTAT bit in the WDTCON
register can be polled to determine the current level of
VDDCORE.
2007-2012 Microchip Technology Inc.
DS39778E-page 341
PIC18F87J11 FAMILY
25.3.2
ON-CHIP REGULATOR AND BOR
Substantial Sleep mode power savings can be obtained
by setting the REGSLP bit, but device wake-up time will
increase in order to insure the regulator has enough time
to stabilize. The REGSLP bit is automatically cleared by
hardware when a Low-Voltage Detect condition occurs.
When the on-chip regulator is enabled, PIC18F87J11
family devices also have a simple brown-out capability.
If the voltage supplied to the regulator is inadequate to
maintain a regulated level, the regulator Reset circuitry
will generate a Brown-out Reset. This event is captured
by the BOR flag bit (RCON).
25.4
The operation of the Brown-out Reset is described in
more detail in Section 5.4 “Brown-out Reset (BOR)”
and Section 5.4.1 “Detecting BOR”. The brown-out
voltage levels are specific in Section 28.1 “DC Characteristics: Supply Voltage PIC18F87J11 Family
(Industrial)”.
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execution, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
25.3.3
Two-Speed Start-up should be enabled only if the
primary oscillator mode is HS or HSPLL
(Crystal-Based) modes. Since the EC and ECPLL
modes do not require an Oscillator Start-up Timer
delay, Two-Speed Start-up should be disabled.
POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE must
never exceed VDD by 0.3 volts.
25.3.4
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the internal oscillator block as the clock source, following the
time-out of the Power-up Timer after a Power-on Reset is
enabled. This allows almost immediate code execution
while the primary oscillator starts and the OST is running.
Once the OST times out, the device automatically
switches to PRI_RUN mode.
OPERATION IN SLEEP MODE
When enabled, the on-chip regulator always consumes
a small incremental amount of current over IDD. This
includes when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator can be configured
to automatically disable itself whenever the device
goes into Sleep mode. This feature is controlled by the
REGSLP bit (WDTCON, Register 25-9). Setting
this bit disables the regulator in Sleep mode and
reduces its current consumption to a minimum.
FIGURE 25-3:
Two-Speed Start-up
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Q1
Q3
Q2
Q4
Q2 Q3 Q4 Q1 Q2 Q3
Q1
INTRC
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
2
n-1
n
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake from Interrupt Event
Note 1:
DS39778E-page 342
PC + 2
PC + 4
PC + 6
OSTS bit Set
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
25.4.1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including serial SLEEP instructions (refer to
Section 4.1.4 “Multiple Sleep Commands”). In practice, this means that user code can change the
SCS bit settings or issue SLEEP instructions
before the OST times out. This would allow an application to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
25.5
Fail-Safe Clock Monitor
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected
(Figure 25-5). This causes the following:
• The FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2)
• The device clock source is switched to the internal
oscillator block (OSCCON is not updated to show
the current clock source – this is the fail-safe
condition)
• The WDT is reset
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable
for timing-sensitive applications. In these cases, it may
be desirable to select another clock configuration and
enter an alternate power-managed mode. This can be
done to attempt a partial recovery or execute a
controlled shutdown. See Section 4.1.4 “Multiple
Sleep Commands” and Section 25.4.1 “Special
Considerations for Using Two-Speed Start-up” for
more details.
The Fail-Safe Clock Monitor (FSCM) allows the
microcontroller to continue operation in the event of an
external oscillator failure by automatically switching the
device clock to the internal oscillator block. The FSCM
function is enabled by setting the FCMEN Configuration
bit.
The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block
fails, no failure would be detected, nor would any action
be possible.
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provide a
backup clock in the event of a clock failure. Clock
monitoring (shown in Figure 25-4) is accomplished by
creating a sample clock signal which is the INTRC output, divided by 64. This allows ample time between
FSCM sample clocks for a peripheral clock edge to
occur. The peripheral device clock and the sample
clock are presented as inputs to the Clock Monitor
(CM) latch. The CM is set on the falling edge of the
device clock source but cleared on the rising edge of
the sample clock.
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
FIGURE 25-4:
FSCM BLOCK DIAGRAM
25.5.1
FSCM AND THE WATCHDOG TIMER
As already noted, the clock source is switched to the
INTRC clock when a clock failure is detected; this may
mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value,
a decrease in clock speed allows a WDT time-out to
occur and a subsequent device Reset. For this reason,
fail-safe clock events also reset the WDT and postscaler, allowing it to start timing from when execution
speed was changed and decreasing the likelihood of
an erroneous time-out.
Clock Monitor
Latch (CM)
(edge-triggered)
Peripheral
Clock
INTRC
Source
÷ 64
(32 s)
488 Hz
(2.048 ms)
S
Q
C
Q
Clock
Failure
Detected
2007-2012 Microchip Technology Inc.
DS39778E-page 343
PIC18F87J11 FAMILY
FIGURE 25-5:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
Device
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
Note:
25.5.2
CM Test
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
EXITING FAIL-SAFE OPERATION
The fail-safe condition is terminated by either a device
Reset or by entering a power-managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 2H (with any
required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The INTRC
oscillator provides the device clock until the primary
clock source becomes ready (similar to a Two-Speed
Start-up). The clock source is then switched to the
primary clock (indicated by the OSTS bit in the
OSCCON register becoming set). The Fail-Safe Clock
Monitor then resumes monitoring the peripheral clock.
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTRC oscillator. The OSCCON register will remain in
its Reset state until a power-managed mode is entered.
25.5.3
CM Test
FSCM INTERRUPTS IN
POWER-MANAGED MODES
By entering a power-managed mode, the clock
multiplexor selects the clock source selected by the
OSCCON register. Fail-Safe Clock Monitoring of the
power-managed clock source resumes in the
power-managed mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTRC multiplexor. An automatic transition back
to the failed clock source will not occur.
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTRC source.
DS39778E-page 344
25.5.4
POR OR WAKE-UP FROM SLEEP
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset (POR)
or low-power Sleep mode. When the primary device
clock is either the EC or INTRC modes, monitoring can
begin immediately following these events.
For HS or HSPLL modes, the situation is somewhat
different. Since the oscillator may require a start-up
time considerably longer than the FSCM sample clock
time, a false clock failure may be detected. To prevent
this, the internal oscillator block is automatically configured as the device clock and functions until the primary
clock is stable (the OST and PLL timers have timed
out). This is identical to Two-Speed Start-up mode.
Once the primary clock is stable, the INTRC returns to
its role as the FSCM source.
Note:
The same logic that prevents false
oscillator failure interrupts on POR, or
wake from Sleep, will also prevent the
detection of the oscillator’s failure to start
at all following these events. This can be
avoided by monitoring the OSTS bit and
using a timing routine to determine if the
oscillator is taking too long to start. Even
so, no oscillator failure interrupt will be
flagged.
As noted in Section 25.4.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alternate
power-managed mode while waiting for the primary
clock to become stable. When the new power-managed
mode is selected, the primary clock is disabled.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
25.6
Program Verification and
Code Protection
For all devices in the PIC18F87J11 family of devices,
the on-chip program memory space is treated as a
single block. Code protection for this block is controlled
by one Configuration bit, CP0. This bit inhibits external
reads and writes to the program memory space. It has
no direct effect in normal execution mode.
25.6.1
CONFIGURATION REGISTER
PROTECTION
The Configuration registers are protected against
untoward changes or reads in two ways. The primary
protection is the write-once feature of the Configuration
bits which prevents reconfiguration once the bit has
been programmed during a power cycle. To safeguard
against unpredictable events, Configuration bit
changes resulting from individual cell level disruptions
(such as ESD events) will cause a parity error and
trigger a device Reset. This is seen by the user as a
Configuration Match Reset.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the CP0 bit is set, the source data for device
configuration is also protected as a consequence.
2007-2012 Microchip Technology Inc.
25.7
In-Circuit Serial Programming
PIC18F87J11 family microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
25.8
In-Circuit Debugger
When the DEBUG Configuration bit is programmed to
a ‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB® IDE. When the microcontroller has
this feature enabled, some resources are not available
for general use. Table 25-4 shows which resources are
required by the background debugger.
TABLE 25-4:
DEBUGGER RESOURCES
I/O Pins:
RB6, RB7
Stack:
2 Levels
Program Memory:
< 1 Kbyte
Data Memory:
< 16 Bytes
DS39778E-page 345
PIC18F87J11 FAMILY
NOTES:
DS39778E-page 346
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
26.0
INSTRUCTION SET SUMMARY
The PIC18F87J11 family of devices incorporate the
standard set of 75 PIC18 core instructions, as well as
an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software
stack. The extended set is discussed later in this
section.
26.1
Standard Instruction Set
The standard PIC18 instruction set adds many
enhancements to the previous PIC® instruction sets,
while maintaining an easy migration from these instruction sets. Most instructions are a single program
memory word (16 bits), but there are four instructions
that require two program memory locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
•
•
•
•
Byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
The PIC18 instruction set summary in Table 26-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 26-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.
The file register (specified by ‘f’)
The destination of the result (specified by ‘d’)
The accessed memory (specified by ‘a’)
The file register designator, ‘f’, specifies which file register is to be used by the instruction. The destination
designator, ‘d’, specifies where the result of the
operation is to be placed. If ‘d’ is ‘0’, the result is placed
in the WREG register. If ‘d’ is ‘1’, the result is placed in
the file register specified in the instruction.
All bit-oriented instructions have three operands:
1.
2.
3.
The file register (specified by ‘f’)
The bit in the file register (specified by ‘b’)
The accessed memory (specified by ‘a’)
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
The control instructions may use some of the following
operands:
• A program memory address (specified by ‘n’)
• The mode of the CALL or RETURN instructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required
(specified by ‘—’)
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter is changed as a result of the instruction. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the Program Counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two-word branch instructions (if true) would take 3 s.
Figure 26-1 shows the general formats that the instructions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The instruction set summary, shown in Table 26-2, lists
the standard instructions recognized by the Microchip
MPASM™ Assembler.
Section 26.1.1 “Standard Instruction Set” provides
a description of each instruction.
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register designator, ‘f’, represents the number of the file in which the
bit is located.
2007-2012 Microchip Technology Inc.
DS39778E-page 347
PIC18F87J11 FAMILY
TABLE 26-1:
OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
Bit address within an 8-bit file register (0 to 7).
BSR
Bank Select Register. Used to select the current RAM bank.
C, DC, Z, OV, N
ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
d
Destination select bit:
d = 0: store result in WREG
d = 1: store result in file register f
dest
Destination: either the WREG register or the specified register file location.
f
8-bit register file address (00h to FFh), or 2-bit FSR designator (0h to 3h).
fs
12-bit register file address (000h to FFFh). This is the source address.
fd
12-bit register file address (000h to FFFh). This is the destination address.
GIE
Global Interrupt Enable bit.
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label
Label name.
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No Change to register (such as TBLPTR with table reads and writes)
*+
Post-Increment register (such as TBLPTR with table reads and writes)
*-
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
+*
n
The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC
Program Counter.
PCL
Program Counter Low Byte.
PCH
Program Counter High Byte.
PCLATH
Program Counter High Byte Latch.
PCLATU
Program Counter Upper Byte Latch.
PD
Power-Down bit.
PRODH
Product of Multiply High Byte.
PRODL
Product of Multiply Low Byte.
s
Fast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR
21-bit Table Pointer (points to a program memory location).
TABLAT
8-bit Table Latch.
TO
Time-out bit.
TOS
Top-of-Stack.
u
Unused or Unchanged.
WDT
Watchdog Timer.
WREG
Working register (accumulator).
x
Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
zs
7-bit offset value for Indirect Addressing of register files (source).
7-bit offset value for Indirect Addressing of register files (destination).
zd
{
}
Optional argument.
[text]
Indicates Indexed Addressing.
(text)
The contents of text.
[expr]
Specifies bit n of the register indicated by the pointer, expr.
Assigned to.
< >
Register bit field.
In the set of.
italics
User-defined term (font is Courier New).
DS39778E-page 348
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 26-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15
10
9
OPCODE
Example Instruction
8 7
d
0
a
f (FILE #)
ADDWF MYREG, W, B
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
OPCODE
15
f (Source FILE #)
12 11
MOVFF MYREG1, MYREG2
0
f (Destination FILE #)
1111
f = 12-bit file register address
Bit-oriented file register operations
15
12 11
9 8 7
0
OPCODE b (BIT #) a
f (FILE #)
BSF MYREG, bit, B
b = 3-bit position of bit in file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
OPCODE
k (literal)
MOVLW 7Fh
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
OPCODE
15
n (literal)
12 11
GOTO Label
0
n (literal)
1111
n = 20-bit immediate value
15
8 7
OPCODE
15
S
0
CALL MYFUNC
n (literal)
12 11
0
n (literal)
1111
S = Fast bit
15
11 10
OPCODE
15
0
n (literal)
8 7
OPCODE
2007-2012 Microchip Technology Inc.
BRA MYFUNC
0
n (literal)
BC MYFUNC
DS39778E-page 349
PIC18F87J11 FAMILY
TABLE 26-2:
PIC18F87J11 FAMILY INSTRUCTION SET
Mnemonic,
Operands
16-Bit Instruction Word
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
fs, fd
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
SUBWF f, d, a
SUBWFB f, d, a
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, Skip =
Compare f with WREG, Skip >
Compare f with WREG, Skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move fs (source) to 1st word
fd (destination) 2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
Borrow
Subtract WREG from f
Subtract WREG from f with
Borrow
Swap Nibbles in f
Test f, Skip if 0
Exclusive OR WREG with f
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1
1
1
1
1
1
1
1
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
1
1
0101 11da
0101 10da
ffff
ffff
ffff C, DC, Z, OV, N 1, 2
ffff C, DC, Z, OV, N
1
0011 10da
1 (2 or 3) 0110 011a
1
0001 10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
None
None
1, 2
C, DC, Z, OV, N
1, 2
C, Z, N
Z, N
C, Z, N
Z, N
1, 2
None
C, DC, Z, OV, N
4
1, 2
SWAPF
TSTFSZ
XORWF
f, d, a
f, a
f, d, a
Note 1:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input
and is driven low by an external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared if assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a
NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures
that all program memory locations have a valid instruction.
2:
3:
4:
DS39778E-page 350
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 26-2:
PIC18F87J11 FAMILY INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
f, b, a
f, b, a
f, b, a
f, b, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1
1
1 (2 or 3)
1 (2 or 3)
1
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call Subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to Address 1st word
2nd word
No Operation
No Operation
Pop Top of Return Stack (TOS)
Push Top of Return Stack (TOS)
Relative Call
Software Device Reset
Return from Interrupt Enable
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
None
None
None
None
None
None
None
None
None
None
1
1
1
1
2
1
2
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
Return with Literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100
0000 0000
0000 0000
kkkk
0001
0000
1, 2
1, 2
3, 4
3, 4
1, 2
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
n
n
n
n
n
n
n
n
n
n, s
CLRWDT —
DAW
—
GOTO
n
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
s
RETLW k
RETURN s
SLEEP
—
Note 1:
2:
3:
4:
1
1
2
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
kkkk None
001s None
0011 TO, PD
4
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input
and is driven low by an external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared if assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a
NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures
that all program memory locations have a valid instruction.
2007-2012 Microchip Technology Inc.
DS39778E-page 351
PIC18F87J11 FAMILY
TABLE 26-2:
PIC18F87J11 FAMILY INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Add Literal and WREG
AND Literal with WREG
Inclusive OR Literal with WREG
Move Literal (12-bit) 2nd word
to FSR (f)
1st word
Move Literal to BSR
Move Literal to WREG
Multiply Literal with WREG
Return with Literal in WREG
Subtract WREG from Literal
Exclusive OR Literal with WREG
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
None
None
None
None
C, DC, Z, OV, N
Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD*
TBLRD*+
TBLRD*TBLRD+*
TBLWT*
TBLWT*+
TBLWT*TBLWT+*
Note 1:
2:
3:
4:
Table Read
2
Table Read with Post-Increment
Table Read with Post-Decrement
Table Read with Pre-Increment
Table Write
2
Table Write with Post-Increment
Table Write with Post-Decrement
Table Write with Pre-Increment
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input
and is driven low by an external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared if assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a
NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures
that all program memory locations have a valid instruction.
DS39778E-page 352
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
26.1.1
STANDARD INSTRUCTION SET
ADDLW
ADD Literal to W
ADDWF
ADD W to f
Syntax:
ADDLW
Syntax:
ADDWF
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(W) + (f) dest
Status Affected:
N, OV, C, DC, Z
k
Operands:
0 k 255
Operation:
(W) + k W
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1111
kkkk
kkkk
Description:
The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
Words:
1
Cycles:
1
Encoding:
0010
Description:
Q1
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to
W
Example:
ADDLW
ffff
ffff
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
15h
Before Instruction
W
= 10h
After Instruction
W =
25h
01da
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q Cycle Activity:
Decode
f {,d {,a}}
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
Note:
REG, 0, 0
17h
0C2h
0D9h
0C2h
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
2007-2012 Microchip Technology Inc.
DS39778E-page 353
PIC18F87J11 FAMILY
ADDWFC
ADD W and Carry bit to f
ANDLW
AND Literal with W
Syntax:
ADDWFC
Syntax:
ANDLW
Operands:
0 f 255
d [0,1]
a [0,1]
f {,d {,a}}
Operation:
(W) + (f) + (C) dest
Status Affected:
N,OV, C, DC, Z
Encoding:
0010
Description:
00da
ffff
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Operands:
0 k 255
Operation:
(W) .AND. k W
Status Affected:
N, Z
Encoding:
ffff
k
0000
1011
kkkk
kkkk
Description:
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to
W
Example:
ANDLW
Before Instruction
W
=
After Instruction
W
=
05Fh
A3h
03h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWFC
Before Instruction
Carry bit =
REG
=
W
=
After Instruction
Carry bit =
REG
=
W
=
DS39778E-page 354
REG, 0, 1
1
02h
4Dh
0
02h
50h
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
ANDWF
AND W with f
BC
Branch if Carry
Syntax:
ANDWF
Syntax:
BC
Operands:
0 f 255
d [0,1]
a [0,1]
f {,d {,a}}
Operation:
(W) .AND. (f) dest
Status Affected:
N, Z
Encoding:
0001
Description:
Operands:
-128 n 127
Operation:
if Carry bit is ‘1’,
(PC) + 2 + 2n PC
Status Affected:
None
Encoding:
01da
ffff
ffff
1110
Description:
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ANDWF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
REG, 0, 0
17h
C2h
02h
C2h
2007-2012 Microchip Technology Inc.
0010
nnnn
nnnn
If the Carry bit is ’1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
n
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
After Instruction
If Carry
PC
If Carry
PC
BC
5
=
address (HERE)
=
=
=
=
1;
address (HERE + 12)
0;
address (HERE + 2)
DS39778E-page 355
PIC18F87J11 FAMILY
BCF
Bit Clear f
BN
Branch if Negative
Syntax:
BCF
Syntax:
BN
Operands:
0 f 255
0b7
a [0,1]
f, b {,a}
Operation:
0 f
Status Affected:
None
Encoding:
1001
Description:
Operands:
-128 n 127
Operation:
if Negative bit is ‘1’,
(PC) + 2 + 2n PC
Status Affected:
None
Encoding:
bbba
ffff
ffff
1110
Description:
Bit ‘b’ in register ‘f’ is cleared.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
BCF
Before Instruction
FLAG_REG = C7h
After Instruction
FLAG_REG = 47h
DS39778E-page 356
FLAG_REG,
7, 0
0110
nnnn
nnnn
If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Q Cycle Activity:
Decode
n
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
After Instruction
If Negative
PC
If Negative
PC
BN
Jump
=
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
BNC
Syntax:
BNN
n
n
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if Carry bit is ‘0’,
(PC) + 2 + 2n PC
Operation:
if Negative bit is ‘0’,
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
Description:
0011
nnnn
nnnn
If the Carry bit is ‘0’, then the program
will branch.
Encoding:
1110
Description:
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
nnnn
nnnn
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
0111
If the Negative bit is ‘0’, then the
program will branch.
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
If No Jump:
Example:
If No Jump:
HERE
Before Instruction
PC
After Instruction
If Carry
PC
If Carry
PC
BNC
Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
2007-2012 Microchip Technology Inc.
Example:
HERE
Before Instruction
PC
After Instruction
If Negative
PC
If Negative
PC
BNN
Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
DS39778E-page 357
PIC18F87J11 FAMILY
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
BNOV
Syntax:
BNZ
n
n
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if Overflow bit is ‘0’,
(PC) + 2 + 2n PC
Operation:
if Zero bit is ‘0’,
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
Description:
0101
nnnn
nnnn
If the Overflow bit is ‘0’, then the
program will branch.
Encoding:
1110
Description:
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
nnnn
nnnn
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
0001
If the Zero bit is ‘0’, then the program
will branch.
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
If No Jump:
If No Jump:
Example:
HERE
Before Instruction
PC
After Instruction
If Overflow
PC
If Overflow
PC
DS39778E-page 358
BNOV Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
Example:
HERE
Before Instruction
PC
After Instruction
If Zero
PC
If Zero
PC
BNZ
Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
BRA
Syntax:
BSF
Operands:
-1024 n 1023
Operands:
Operation:
(PC) + 2 + 2n PC
Status Affected:
None
0 f 255
0b7
a [0,1]
Operation:
1 f
Status Affected:
None
Encoding:
n
1101
Description:
0nnn
nnnn
nnnn
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words:
1
Cycles:
2
Encoding:
1000
Description:
Q1
Q2
Q3
Q4
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Example:
bbba
ffff
ffff
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Decode
f, b {,a}
Words:
1
Cycles:
1
Q Cycle Activity:
HERE
Before Instruction
PC
After Instruction
PC
BRA
Jump
=
address (HERE)
=
address (Jump)
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
BSF
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
2007-2012 Microchip Technology Inc.
FLAG_REG, 7, 1
=
0Ah
=
8Ah
DS39778E-page 359
PIC18F87J11 FAMILY
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
BTFSC f, b {,a}
Syntax:
BTFSS f, b {,a}
Operands:
0 f 255
0b7
a [0,1]
Operands:
0 f 255
0b (W)
(unsigned comparison)
Operation:
(f) –W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
None
Status Affected:
None
Encoding:
Description:
0110
f {,a}
010a
ffff
ffff
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
Encoding:
0110
Description:
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
1
Cycles:
1(2)
Note:
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
3 cycles if skip and followed
by a 2-word instruction.
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q3
Process
Data
Q4
No
operation
Q2
Read
register ‘f’
Q1
Q2
Q3
No
No
No
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
No
No
operation
operation
operation
No
No
No
operation
operation
operation
Q4
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
If skip:
Example:
ffff
Q Cycle Activity:
Words:
Q Cycle Activity:
Q1
Decode
000a
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
f {,a}
HERE
NGREATER
GREATER
Before Instruction
PC
W
After Instruction
If REG
PC
If REG
PC
Q4
No
operation
No
operation
CPFSGT REG, 0
:
:
=
=
Address (HERE)
?
=
=
W;
Address (GREATER)
W;
Address (NGREATER)
2007-2012 Microchip Technology Inc.
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NLESS
LESS
Before Instruction
PC
W
After Instruction
If REG
PC
If REG
PC
CPFSLT REG, 1
:
:
=
=
Address (HERE)
?
<
=
=
W;
Address (LESS)
W;
Address (NLESS)
DS39778E-page 365
PIC18F87J11 FAMILY
DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
DAW
Syntax:
DECF f {,d {,a}}
Operands:
None
Operands:
Operation:
If [W > 9] or [DC = 1] then,
(W) + 6 W;
else,
(W) W
0 f 255
d [0,1]
a [0,1]
Operation:
(f) – 1 dest
Status Affected:
C, DC, N, OV, Z
Encoding:
If [W > 9] or [C = 1] then,
(W) + 6 W,
C =1;
else,
(W) W
Status Affected:
0000
Description:
0000
0000
0000
0111
Description:
DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
Example 1:
A5h
0
0
05h
1
0
ffff
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
DAW
Before Instruction
W
=
C
=
DC
=
After Instruction
W
=
C
=
DC
=
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
C
Encoding:
01da
Example:
DECF
Before Instruction
CNT
=
Z
=
After Instruction
CNT
=
Z
=
CNT,
1, 0
01h
0
00h
1
Example 2:
Before Instruction
W
=
C
=
DC
=
After Instruction
W
=
C
=
DC
=
DS39778E-page 366
CEh
0
0
34h
1
0
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
DECFSZ
Decrement f, Skip if 0
DCFSNZ
Decrement f, Skip if not 0
Syntax:
DECFSZ f {,d {,a}}
Syntax:
DCFSNZ
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) – 1 dest,
skip if result = 0
Operation:
(f) – 1 dest,
skip if result 0
Status Affected:
None
Status Affected:
None
Encoding:
0010
Description:
11da
ffff
ffff
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
Encoding:
0100
Description:
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Words:
1
Cycles:
1(2)
Note:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
DECFSZ
GOTO
CNT, 1, 1
LOOP
Example:
HERE
CONTINUE
Before Instruction
PC
=
After Instruction
CNT
=
If CNT
=
PC =
If CNT
PC =
Address (HERE)
CNT – 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
2007-2012 Microchip Technology Inc.
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
If skip and followed by 2-word instruction:
ffff
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Decode
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
11da
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
f {,d {,a}}
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
ZERO
NZERO
Before Instruction
TEMP
After Instruction
TEMP
If TEMP
PC
If TEMP
PC
DCFSNZ
:
:
TEMP, 1, 0
=
?
=
=
=
=
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
DS39778E-page 367
PIC18F87J11 FAMILY
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
GOTO k
Syntax:
INCF
Operands:
0 k 1048575
Operands:
Operation:
k PC
Status Affected:
None
0 f 255
d [0,1]
a [0,1]
Operation:
(f) + 1 dest
Status Affected:
C, DC, N, OV, Z
Encoding:
1st word (k)
2nd word(k)
1110
1111
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description:
GOTO allows an unconditional branch
anywhere within entire 2-Mbyte memory
range. The 20-bit value ‘k’ is loaded into
PC. GOTO is always a two-cycle
instruction.
Words:
2
Cycles:
2
Encoding:
0010
Description:
Q1
Q2
Q3
Q4
Read literal
‘k’,
No
operation
Read literal
‘k’,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example:
GOTO THERE
After Instruction
PC =
Address (THERE)
ffff
ffff
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
INCF
Before Instruction
CNT
=
Z
=
C
=
DC
=
After Instruction
CNT
=
Z
=
C
=
DC
=
DS39778E-page 368
10da
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q Cycle Activity:
Decode
f {,d {,a}}
CNT, 1, 0
FFh
0
?
?
00h
1
1
1
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
INCFSZ
Increment f, Skip if 0
INFSNZ
Syntax:
INCFSZ
Syntax:
INFSNZ
0 f 255
d [0,1]
a [0,1]
f {,d {,a}}
Increment f, Skip if not 0
f {,d {,a}}
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
Operation:
(f) + 1 dest,
skip if result = 0
Operation:
(f) + 1 dest,
skip if result 0
Status Affected:
None
Status Affected:
None
Encoding:
0011
Description:
11da
ffff
ffff
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
Encoding:
0100
Description:
10da
ffff
ffff
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Words:
1
Cycles:
1(2)
Note:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
Before Instruction
PC
=
After Instruction
CNT
=
If CNT
=
PC
=
If CNT
PC
=
INCFSZ
:
:
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
2007-2012 Microchip Technology Inc.
CNT, 1, 0
Example:
HERE
ZERO
NZERO
Before Instruction
PC
=
After Instruction
REG
=
If REG
PC
=
If REG
=
PC
=
INFSNZ
REG, 1, 0
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
DS39778E-page 369
PIC18F87J11 FAMILY
IORLW
Inclusive OR Literal with W
IORWF
Inclusive OR W with f
Syntax:
IORLW k
Syntax:
IORWF
Operands:
0 k 255
Operands:
Operation:
(W) .OR. k W
Status Affected:
N, Z
0 f 255
d [0,1]
a [0,1]
Operation:
(W) .OR. (f) dest
Status Affected:
N, Z
Encoding:
0000
1001
kkkk
kkkk
Description:
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed
in W.
Words:
1
Cycles:
1
Encoding:
0001
Description:
Q1
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to
W
Example:
IORLW
Before Instruction
W
=
After Instruction
W
=
ffff
ffff
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
35h
9Ah
BFh
00da
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q Cycle Activity:
Decode
f {,d {,a}}
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
IORWF
Before Instruction
RESULT =
W
=
After Instruction
RESULT =
W
=
DS39778E-page 370
RESULT, 0, 1
13h
91h
13h
93h
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
LFSR
Load FSR
MOVF
Move f
Syntax:
LFSR f, k
Syntax:
MOVF
Operands:
0f2
0 k 4095
Operands:
Operation:
k FSRf
0 f 255
d [0,1]
a [0,1]
Status Affected:
None
Operation:
f dest
Status Affected:
N, Z
Encoding:
1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Description:
The 12-bit literal ‘k’ is loaded into the
file select register pointed to by ‘f’.
Words:
2
Cycles:
2
Encoding:
0101
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example:
After Instruction
FSR2H
FSR2L
03h
ABh
00da
ffff
ffff
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’. Location ‘f’
can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
LFSR 2, 3ABh
=
=
f {,d {,a}}
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
W
Example:
MOVF
Before Instruction
REG
W
After Instruction
REG
W
2007-2012 Microchip Technology Inc.
REG, 0, 0
=
=
22h
FFh
=
=
22h
22h
DS39778E-page 371
PIC18F87J11 FAMILY
MOVFF
Move f to f
MOVLB
Move Literal to Low Nibble in BSR
Syntax:
MOVFF fs,fd
Syntax:
MOVLB k
Operands:
0 fs 4095
0 fd 4095
Operands:
0 k 255
Operation:
k BSR
Status Affected:
None
Operation:
(fs) fd
Status Affected:
None
Encoding:
1st word (source)
2nd word (destin.)
Encoding:
1100
1111
Description:
ffff
ffff
ffff
ffff
ffffs
ffffd
The contents of source register ‘fs’ are
moved to destination register ‘fd’.
Location of source ‘fs’ can be anywhere
in the 4096-byte data space (000h to
FFFh) and location of destination ‘fd’
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF is particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register
Words:
2
Cycles:
2
0000
0001
kkkk
kkkk
Description:
The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR always remains ‘0’
regardless of the value of k7:k4.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write literal
‘k’ to BSR
MOVLB
5
Example:
Before Instruction
BSR Register =
After Instruction
BSR Register =
02h
05h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
Before Instruction
REG1
REG2
After Instruction
REG1
REG2
DS39778E-page 372
REG1, REG2
=
=
33h
11h
=
=
33h
33h
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
MOVLW
Move Literal to W
MOVWF
Move W to f
Syntax:
MOVLW k
Syntax:
MOVWF
Operands:
0 k 255
Operands:
Operation:
kW
0 f 255
a [0,1]
Status Affected:
None
Encoding:
0000
Description:
1110
kkkk
kkkk
The eight-bit literal ‘k’ is loaded into W.
Words:
1
Cycles:
1
Operation:
(W) f
Status Affected:
None
Encoding:
0110
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
Example:
After Instruction
W
=
MOVLW
f {,a}
111a
ffff
ffff
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
5Ah
5Ah
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
MOVWF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
2007-2012 Microchip Technology Inc.
REG, 0
4Fh
FFh
4Fh
4Fh
DS39778E-page 373
PIC18F87J11 FAMILY
MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
MULLW
Syntax:
MULWF
Operands:
0 f 255
a [0,1]
Operation:
(W) x (f) PRODH:PRODL
Status Affected:
None
k
Operands:
0 k 255
Operation:
(W) x k PRODH:PRODL
Status Affected:
None
Encoding:
0000
Description:
1101
kkkk
kkkk
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in PRODH:PRODL register pair.
PRODH contains the high byte.
Encoding:
0000
Description:
W is unchanged.
None of the Status flags are affected.
1
Cycles:
1
Q1
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
MULLW
=
=
=
=
=
=
0C4h
E2h
?
?
E2h
ADh
08h
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULWF
Before Instruction
W
REG
PRODH
PRODL
After Instruction
W
REG
PRODH
PRODL
DS39778E-page 374
ffff
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Decode
Before Instruction
W
PRODH
PRODL
After Instruction
W
PRODH
PRODL
ffff
Note that neither Overflow nor Carry is
possible in this operation. A Zero result is
possible but not detected.
Q Cycle Activity:
Example:
001a
An unsigned multiplication is carried out
between the contents of W and the
register file location ‘f’. The 16-bit result is
stored in the PRODH:PRODL register
pair. PRODH contains the high byte. Both
W and ‘f’ are unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected.
Words:
f {,a}
REG, 1
=
=
=
=
C4h
B5h
?
?
=
=
=
=
C4h
B5h
8Ah
94h
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
NEGF
Negate f
Syntax:
NEGF
Operands:
0 f 255
a [0,1]
f {,a}
Operation:
(f) + 1 f
Status Affected:
N, OV, C, DC, Z
Encoding:
0110
Description:
110a
ffff
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Syntax:
NOP
Operands:
None
Operation:
No operation
Status Affected:
None
0000
1111
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Cycles:
No Operation
Encoding:
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
Words:
NOP
0000
xxxx
Description:
No operation.
Words:
1
Cycles:
1
0000
xxxx
0000
xxxx
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
NEGF
Before Instruction
REG
=
After Instruction
REG
=
REG, 1
0011 1010 [3Ah]
1100 0110 [C6h]
2007-2012 Microchip Technology Inc.
DS39778E-page 375
PIC18F87J11 FAMILY
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
POP
Syntax:
PUSH
Operands:
None
Operands:
None
Operation:
(TOS) bit bucket
Operation:
(PC + 2) TOS
Status Affected:
None
Status Affected:
None
Encoding:
0000
0000
0000
0110
Encoding:
0000
0000
0000
0101
Description:
The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
Description:
The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
POP TOS
value
No
operation
POP
GOTO
NEW
Example:
Q2
Q3
Q4
PUSH
PC + 2 onto
return stack
No
operation
No
operation
Example:
Before Instruction
TOS
Stack (1 level down)
=
=
0031A2h
014332h
After Instruction
TOS
PC
=
=
014332h
NEW
DS39778E-page 376
Q1
Decode
PUSH
Before Instruction
TOS
PC
=
=
345Ah
0124h
After Instruction
PC
TOS
Stack (1 level down)
=
=
=
0126h
0126h
345Ah
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
RCALL
Relative Call
RESET
Reset
Syntax:
RCALL
Syntax:
RESET
n
Operands:
-1024 n 1023
Operands:
None
Operation:
(PC) + 2 TOS,
(PC) + 2 + 2n PC
Operation:
Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected:
None
Status Affected:
All
Encoding:
1101
Description:
1nnn
nnnn
nnnn
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words:
1
Cycles:
2
Encoding:
0000
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
1111
1111
This instruction provides a way to
execute a MCLR Reset in software.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
reset
No
operation
No
operation
Example:
Q Cycle Activity:
0000
Description:
After Instruction
Registers =
Flags*
=
RESET
Reset Value
Reset Value
PUSH PC
to stack
No
operation
Example:
No
operation
HERE
RCALL Jump
Before Instruction
PC =
Address (HERE)
After Instruction
PC =
Address (Jump)
TOS =
Address (HERE + 2)
2007-2012 Microchip Technology Inc.
DS39778E-page 377
PIC18F87J11 FAMILY
RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
RETFIE {s}
Syntax:
RETLW k
Operands:
s [0,1]
Operands:
0 k 255
Operation:
(TOS) PC,
1 GIE/GIEH or PEIE/GIEL;
if s = 1,
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Operation:
k W,
(TOS) PC,
PCLATU, PCLATH are unchanged
Status Affected:
None
Status Affected:
0000
0000
Description:
0000
0001
Words:
1
Cycles:
2
Q Cycle Activity:
kkkk
kkkk
W is loaded with the eight-bit literal ‘k’.
The Program Counter is loaded from
the top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Words:
1
Cycles:
2
000s
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low-priority
Global Interrupt Enable bit. If ‘s’ = 1, the
contents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers W,
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs.
1100
Description:
GIE/GIEH, PEIE/GIEL.
Encoding:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
POP PC
from stack,
write to W
No
operation
No
operation
No
operation
No
operation
Example:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
POP PC
from stack
Set GIEH or
GIEL
No
operation
Encoding:
No
operation
Example:
RETFIE
After Interrupt
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL
DS39778E-page 378
No
operation
No
operation
1
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
CALL TABLE ;
;
;
;
:
TABLE
ADDWF PCL ;
RETLW k0
;
RETLW k1
;
:
:
RETLW kn
;
Before Instruction
W
=
After Instruction
W
=
W contains table
offset value
W now has
table value
W = offset
Begin table
End of table
07h
value of kn
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
RETURN {s}
Syntax:
RLCF
Operands:
s [0,1]
Operands:
Operation:
(TOS) PC;
if s = 1,
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
0 f 255
d [0,1]
a [0,1]
Operation:
(f) dest,
(f) C,
(C) dest
Status Affected:
C, N, Z
Status Affected:
None
Encoding:
0000
Description:
Encoding:
0000
0001
001s
0011
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the Program Counter. If
‘s’= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs.
Words:
1
Cycles:
2
Q1
Q2
Q3
Q4
No
operation
Process
Data
POP PC
from stack
No
operation
No
operation
No
operation
No
operation
01da
ffff
ffff
The contents of register ‘f’ are rotated
one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register
‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Decode
f {,d {,a}}
register f
C
Words:
1
Cycles:
1
Q Cycle Activity:
Example:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
RETURN
After Instruction:
PC = TOS
Example:
Before Instruction
REG
=
C
=
After Instruction
REG
=
W
=
C
=
2007-2012 Microchip Technology Inc.
RLCF
REG, 0, 0
1110 0110
0
1110 0110
1100 1100
1
DS39778E-page 379
PIC18F87J11 FAMILY
RLNCF
Rotate Left f (No Carry)
RRCF
Rotate Right f through Carry
Syntax:
RLNCF
Syntax:
RRCF
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) dest,
(f) dest
Operation:
Status Affected:
N, Z
(f) dest,
(f) C,
(C) dest
Status Affected:
C, N, Z
Encoding:
0100
Description:
f {,d {,a}}
01da
ffff
ffff
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Encoding:
0011
Description:
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Cycles:
1
Q1
Decode
Q2
Read
register ‘f’
Example:
Before Instruction
REG
=
After Instruction
REG
=
DS39778E-page 380
RLNCF
Q3
Process
Data
Q4
Write to
destination
Words:
1
Cycles:
register f
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
REG, 1, 0
1010 1011
0101 0111
ffff
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’.
C
Q Cycle Activity:
ffff
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
register f
1
00da
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
f {,d {,a}}
Example:
RRCF
Before Instruction
REG
=
C
=
After Instruction
REG
=
W
=
C
=
REG, 0, 0
1110 0110
0
1110 0110
0111 0011
0
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
RRNCF
Rotate Right f (No Carry)
SETF
Set f
Syntax:
RRNCF
Syntax:
SETF
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
(f) dest,
(f) dest
Status Affected:
N, Z
Encoding:
0100
Description:
f {,d {,a}}
00da
Operation:
FFh f
Status Affected:
None
Encoding:
ffff
ffff
0110
Description:
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
register f
Words:
1
Cycles:
1
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
Before Instruction
REG
=
After Instruction
REG
=
Example 2:
ffff
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
SETF
Before Instruction
REG
After Instruction
REG
REG,1
=
5Ah
=
FFh
REG, 1, 0
1101 0111
1110 1011
RRNCF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
ffff
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
Q Cycle Activity:
100a
The contents of the specified register
are set to FFh.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If ‘a’
is ‘1’, then the bank will be selected as
per the BSR value.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
f {,a}
REG, 0, 0
?
1101 0111
1110 1011
1101 0111
2007-2012 Microchip Technology Inc.
DS39778E-page 381
PIC18F87J11 FAMILY
SLEEP
Enter Sleep Mode
SUBFWB
Subtract f from W with Borrow
Syntax:
SLEEP
Syntax:
SUBFWB
Operands:
None
Operands:
Operation:
00h WDT,
0 WDT postscaler,
1 TO,
0 PD
0 f 255
d [0,1]
a [0,1]
Operation:
(W) – (f) – (C) dest
Status Affected:
N, OV, C, DC, Z
Status Affected:
TO, PD
Encoding:
0000
Encoding:
0000
0000
0011
0101
Description:
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. The Watchdog Timer and its
postscaler are cleared.
Description:
1
Cycles:
1
Q1
Q2
Q3
Q4
No
operation
Process
Data
Go to
Sleep
Example:
SLEEP
Before Instruction
TO =
?
?
PD =
After Instruction
1†
TO =
0
PD =
† If WDT causes wake-up, this bit is cleared.
DS39778E-page 382
ffff
ffff
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored in
W. If ‘d’ is ‘1’, the result is stored in
register ‘f’.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Decode
01da
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
The processor is put into Sleep mode
with the oscillator stopped.
Words:
f {,d {,a}}
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
SUBFWB
REG, 1, 0
Before Instruction
REG
=
3
W
=
2
C
=
1
After Instruction
REG
=
FF
W
=
2
C
=
0
Z
=
0
N
=
1 ; result is negative
Example 2:
SUBFWB
REG, 0, 0
Before Instruction
REG
=
2
W
=
5
C
=
1
After Instruction
REG
=
2
W
=
3
C
=
1
Z
=
0
N
=
0 ; result is positive
SUBFWB
REG, 1, 0
Example 3:
Before Instruction
REG
=
1
W
=
2
C
=
0
After Instruction
REG
=
0
W
=
2
C
=
1
Z
=
1 ; result is zero
N
=
0
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
SUBLW
Subtract W from Literal
SUBWF
Subtract W from f
Syntax:
SUBLW k
Syntax:
SUBWF
Operands:
0 k 255
Operands:
Operation:
k – (W) W
Status Affected:
N, OV, C, DC, Z
0 f 255
d [0,1]
a [0,1]
Operation:
(f) – (W) dest
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1000
kkkk
kkkk
Description:
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
Words:
1
Cycles:
1
Encoding:
0101
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
Example 1:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
Example 2:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
SUBLW
SUBLW
; result is positive
02h
?
00h
1
1
0
SUBLW
; result is zero
02h
03h
?
FFh
0
0
1
; (2’s complement)
; result is negative
ffff
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
SUBWF
REG, 1, 0
Example 1:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
2007-2012 Microchip Technology Inc.
ffff
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
02h
02h
11da
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
01h
?
01h
1
0
0
f {,d {,a}}
3
2
?
1
2
1
0
0
; result is positive
SUBWF
REG, 0, 0
2
2
?
2
0
1
1
0
SUBWF
; result is zero
REG, 1, 0
1
2
?
FFh ;(2’s complement)
2
0
; result is negative
0
1
DS39778E-page 383
PIC18F87J11 FAMILY
SUBWFB
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
SUBWFB
Syntax:
SWAPF f {,d {,a}}
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) – (W) – (C) dest
Operation:
Status Affected:
N, OV, C, DC, Z
(f) dest,
(f) dest
Status Affected:
None
Encoding:
0101
Description:
f {,d {,a}}
10da
ffff
ffff
Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
Encoding:
0011
Description:
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Read
register ‘f’
Example 1:
SUBWFB
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
Q4
Write to
destination
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
REG, 1, 0
19h
0Dh
1
(0001 1001)
(0000 1101)
0Ch
0Dh
1
0
0
(0000 1011)
(0000 1101)
ffff
Example:
SWAPF
Before Instruction
REG
=
After Instruction
REG
=
REG, 1, 0
53h
35h
; result is positive
SUBWFB REG, 0, 0
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
1Bh
1Ah
0
(0001 1011)
(0001 1010)
1Bh
00h
1
1
0
(0001 1011)
SUBWFB
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
C
Z
N
Q3
Process
Data
ffff
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
10da
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
=
=
=
=
DS39778E-page 384
; result is zero
REG, 1, 0
03h
0Eh
1
(0000 0011)
(0000 1101)
F5h
(1111 0100)
; [2’s comp]
(0000 1101)
0Eh
0
0
1
; result is negative
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TBLRD
Table Read
TBLRD
Table Read (Continued)
Syntax:
TBLRD ( *; *+; *-; +*)
Example 1:
TBLRD
Operands:
None
Operation:
if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT,
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT,
(TBLPTR) + 1 TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT,
(TBLPTR) – 1 TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 TBLPTR,
(Prog Mem (TBLPTR)) TABLAT
Before Instruction
TABLAT
TBLPTR
MEMORY(00A356h)
After Instruction
TABLAT
TBLPTR
Example 2:
Status Affected: None
Encoding:
Description:
0000
0000
0000
TBLRD
Before Instruction
TABLAT
TBLPTR
MEMORY(01A357h)
MEMORY(01A358h)
After Instruction
TABLAT
TBLPTR
*+ ;
=
=
=
55h
00A356h
34h
=
=
34h
00A357h
+* ;
=
=
=
=
AAh
01A357h
12h
34h
=
=
34h
01A358h
10nn
nn=0 *
=1 *+
=2 *=3 +*
This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR = 0:Least Significant Byte of
Program Memory Word
TBLPTR = 1:Most Significant Byte of
Program Memory Word
The TBLRD instruction can modify the value
of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
operation
No operation
(Read Program
Memory)
No
operation
No operation
(Write
TABLAT)
2007-2012 Microchip Technology Inc.
DS39778E-page 385
PIC18F87J11 FAMILY
TBLWT
Table Write
TBLWT
Table Write (Continued)
Syntax:
TBLWT ( *; *+; *-; +*)
Example 1:
TBLWT *+;
Operands:
None
Operation:
if TBLWT*,
(TABLAT) Holding Register,
TBLPTR – No Change;
if TBLWT*+,
(TABLAT) Holding Register,
(TBLPTR) + 1 TBLPTR;
if TBLWT*-,
(TABLAT) Holding Register,
(TBLPTR) – 1 TBLPTR;
if TBLWT+*,
(TBLPTR) + 1 TBLPTR,
(TABLAT) Holding Register
Status Affected:
Example 2:
None
Encoding:
Description:
Before Instruction
TABLAT
=
55h
TBLPTR
=
00A356h
HOLDING REGISTER
(00A356h)
=
FFh
After Instructions (table write completion)
TABLAT
=
55h
TBLPTR
=
00A357h
HOLDING REGISTER
(00A356h)
=
55h
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *=3 +*
This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program Memory
(P.M.). (Refer to Section 6.0 “Memory
Organization” for additional details on
programming Flash memory.)
TBLWT +*;
Before Instruction
TABLAT
=
34h
TBLPTR
=
01389Ah
HOLDING REGISTER
(01389Ah)
=
FFh
HOLDING REGISTER
(01389Bh)
=
FFh
After Instruction (table write completion)
TABLAT
=
34h
TBLPTR
=
01389Bh
HOLDING REGISTER
(01389Ah)
=
FFh
HOLDING REGISTER
(01389Bh)
=
34h
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-Mbyte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
TBLPTR = 0:Least Significant Byte
of Program Memory
Word
TBLPTR = 1:Most Significant Byte
of Program Memory
Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
No
No
No
operation operation operation
No
No
No
No
operation operation operation operation
(Read
(Write to
TABLAT)
Holding
Register)
DS39778E-page 386
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TSTFSZ
Test f, Skip if 0
XORLW
Exclusive OR Literal with W
Syntax:
TSTFSZ f {,a}
Syntax:
XORLW k
Operands:
0 f 255
a [0,1]
Operands:
0 k 255
Operation:
(W) .XOR. k W
Status Affected:
N, Z
Operation:
skip if f = 0
Status Affected:
None
Encoding:
Encoding:
0110
Description:
011a
ffff
ffff
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
0000
1010
kkkk
kkkk
Description:
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
Example:
Before Instruction
W
=
After Instruction
W
=
XORLW
0AFh
B5h
1Ah
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
Before Instruction
PC
After Instruction
If CNT
PC
If CNT
PC
TSTFSZ
:
:
CNT, 1
=
Address (HERE)
=
=
=
00h,
Address (ZERO)
00h,
Address (NZERO)
2007-2012 Microchip Technology Inc.
DS39778E-page 387
PIC18F87J11 FAMILY
XORWF
Exclusive OR W with f
Syntax:
XORWF
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(W) .XOR. (f) dest
Status Affected:
N, Z
Encoding:
0001
Description:
f {,d {,a}}
10da
ffff
ffff
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
Before Instruction
REG
=
W
=
After Instruction
REG
=
W
=
DS39778E-page 388
REG, 1, 0
AFh
B5h
1Ah
B5h
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
26.2
A summary of the instructions in the extended instruction set is provided in Table 26-3. Detailed descriptions
are provided in Section 26.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 26-1
(page 348) apply to both the standard and extended
PIC18 instruction sets.
Extended Instruction Set
In addition to the standard 75 instructions of the PIC18
instruction set, the PIC18F87J11 family of devices also
provide an optional extension to the core CPU functionality. The added features include eight additional
instructions that augment Indirect and Indexed
Addressing operations and the implementation of
Indexed Literal Offset Addressing for many of the
standard PIC18 instructions.
Note:
The additional features of the extended instruction set
are enabled by default on unprogrammed devices.
Users must properly set or clear the XINST Configuration bit during programming to enable or disable these
features.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers, or use them for Indexed
Addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
26.2.1
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed arguments, using one of the File Select Registers and some
offset to specify a source or destination register. When
an argument for an instruction serves as part of
Indexed Addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. The MPASM™ Assembler will
flag an error if it determines that an index or offset value
is not bracketed.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in
byte-oriented and bit-oriented instructions. This is in
addition to other changes in their syntax. For more
details, see Section 26.2.3.1 “Extended Instruction
Syntax with Standard PIC18 Commands”.
• dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• function pointer invocation
• software Stack Pointer manipulation
• manipulation of variables located in a software
stack
TABLE 26-3:
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is
provided as a reference for users who
may be reviewing code that has been
generated by a compiler.
Note:
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
EXTENSIONS TO THE PIC18 INSTRUCTION SET
Mnemonic,
Operands
ADDFSR
ADDULNK
CALLW
MOVSF
f, k
k
MOVSS
zs, zd
PUSHL
k
SUBFSR
SUBULNK
f, k
k
zs, fd
16-Bit Instruction Word
Description
Cycles
MSb
Add Literal to FSR
Add Literal to FSR2 and Return
Call Subroutine using WREG
Move zs (source) to 1st word
fd (destination) 2nd word
Move zs (source) to 1st word
zd (destination) 2nd word
Store Literal at FSR2,
Decrement FSR2
Subtract Literal from FSR
Subtract Literal from FSR2 and
Return
2007-2012 Microchip Technology Inc.
1
2
2
2
LSb
Status
Affected
1000
1000
0000
1011
ffff
1011
xxxx
1010
ffkk
11kk
0001
0zzz
ffff
1zzz
xzzz
kkkk
kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk
None
None
None
None
1
1110
1110
0000
1110
1111
1110
1111
1110
1
2
1110
1110
1001
1001
ffkk
11kk
kkkk
kkkk
None
None
2
None
None
DS39778E-page 389
PIC18F87J11 FAMILY
26.2.2
EXTENDED INSTRUCTION SET
ADDFSR
Add Literal to FSR
ADDULNK
Syntax:
ADDFSR f, k
Syntax:
ADDULNK k
Operands:
0 k 63
f [ 0, 1, 2 ]
Operands:
0 k 63
Operation:
FSR(f) + k FSR(f)
Status Affected:
None
Encoding:
1110
Add Literal to FSR2 and Return
FSR2 + k FSR2,
Operation:
(TOS) PC
Status Affected:
1000
ffkk
kkkk
Description:
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Words:
1
Cycles:
1
None
Encoding:
1110
Description:
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
Example:
After Instruction
FSR2
=
03FFh
Words:
1
Cycles:
2
Q Cycle Activity:
0422h
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
No
Operation
No
Operation
No
Operation
No
Operation
Example:
Note:
kkkk
This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
ADDFSR 2, 23h
Before Instruction
FSR2
=
11kk
The instruction takes two cycles to
execute; a NOP is performed during
the second cycle.
Q Cycle Activity:
Q1
1000
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURN is then
executed by loading the PC with the
TOS.
ADDULNK 23h
Before Instruction
FSR2
=
PC
=
03FFh
0100h
After Instruction
FSR2
=
PC
=
0422h
(TOS)
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
DS39778E-page 390
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
CALLW
Subroutine Call using WREG
MOVSF
Move Indexed to f
Syntax:
CALLW
Syntax:
MOVSF [zs], fd
Operands:
None
Operands:
Operation:
(PC + 2) TOS,
(W) PCL,
(PCLATH) PCH,
(PCLATU) PCU
0 zs 127
0 fd 4095
Operation:
((FSR2) + zs) fd
Status Affected:
None
Status Affected:
None
Encoding:
0000
Description
0000
0001
0100
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOP instruction while the
new next instruction is fetched.
Encoding:
1st word (source)
2nd word (destin.)
Description:
Unlike CALL, there is no option to
update W, STATUS or BSR.
Words:
1
Cycles:
2
Q1
Q2
Q3
Q4
Read
WREG
Push PC to
stack
No
operation
No
operation
No
operation
No
operation
No
operation
Before Instruction
PC
=
PCLATH =
PCLATU =
W
=
After Instruction
PC
=
TOS
=
PCLATH =
PCLATU =
W
=
Words:
2
Cycles:
2
Q Cycle Activity:
CALLW
Decode
address (HERE)
10h
00h
06h
001006h
address (HERE + 2)
10h
00h
06h
2007-2012 Microchip Technology Inc.
zzzzs
ffffd
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h.
Decode
HERE
0zzz
ffff
The contents of the source register are
moved to destination register ‘fd’. The
actual address of the source register is
determined by adding the 7-bit literal
offset ‘zs’, in the first word, to the value
of FSR2. The address of the destination
register is specified by the 12-bit literal
‘fd’ in the second word. Both addresses
can be anywhere in the 4096-byte data
space (000h to FFFh).
Q1
Example:
1011
ffff
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Q Cycle Activity:
Decode
1110
1111
Q2
Q3
Determine
Determine
source addr source addr
No
operation
No
operation
No dummy
read
Example:
MOVSF
Before Instruction
FSR2
Contents
of 85h
REG2
After Instruction
FSR2
Contents
of 85h
REG2
Q4
Read
source reg
Write
register ‘f’
(dest)
[05h], REG2
=
80h
=
=
33h
11h
=
80h
=
=
33h
33h
DS39778E-page 391
PIC18F87J11 FAMILY
MOVSS
Move Indexed to Indexed
PUSHL
Store Literal at FSR2, Decrement FSR2
Syntax:
MOVSS [zs], [zd]
Syntax:
PUSHL k
Operands:
0 zs 127
0 zd 127
Operands:
0 £ k £ 255
Operation:
((FSR2) + zs) ((FSR2) + zd)
Operation:
k (FSR2),
FSR2 – 1 FSR2
Status Affected:
None
Status Affected:
None
Encoding:
1st word (source)
2nd word (dest.)
1110
1111
Description
1011
xxxx
1zzz
xzzz
zzzzs
zzzzd
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets ‘zs’ or ‘zd’,
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
The MOVSS instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h. If the
resultant destination address points to
an Indirect Addressing register, the
instruction will execute as a NOP.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Decode
Decode
Q2
Q3
Determine
Determine
source addr source addr
Determine
dest addr
Example:
1110
Description:
1010
kkkk
kkkk
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2.
FSR2 is decremented by 1 after the
operation.
This instruction allows users to push
values onto a software stack.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
data
Write to
destination
Example:
PUSHL 08h
Before Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01ECh
00h
After Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01EBh
08h
Q4
Read
source reg
Write
to dest reg
MOVSS [05h], [06h]
Before Instruction
FSR2
Contents
of 85h
Contents
of 86h
After Instruction
FSR2
Contents
of 85h
Contents
of 86h
DS39778E-page 392
Determine
dest addr
Encoding:
=
80h
=
33h
=
11h
=
80h
=
33h
=
33h
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
SUBFSR
Subtract Literal from FSR
SUBULNK
Subtract Literal from FSR2 and Return
Syntax:
SUBFSR f, k
Syntax:
SUBULNK k
Operands:
0 £ k £ 63
Operands:
0 £ k £ 63
f Î [ 0, 1, 2 ]
Operation:
FSR2 – k ® FSR2,
Operation:
FSRf – k ® FSRf
Status Affected:
None
Encoding:
1110
(TOS) PC
Status Affected:
1001
ffkk
kkkk
Description:
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified
by ‘f’.
Words:
1
Cycles:
1
1110
Description:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example:
Before Instruction
FSR2
=
After Instruction
FSR2
=
SUBFSR 2, 23h
03FFh
03DCh
11kk
kkkk
This may be thought of as a special case
of the SUBFSR instruction, where f = 3
(binary ‘11’); it operates only on FSR2.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
No
Operation
No
Operation
No
Operation
No
Operation
Example:
Before Instruction
FSR2
=
PC
=
After Instruction
FSR2
=
PC
=
2007-2012 Microchip Technology Inc.
1001
The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURN is then
executed by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during the
second cycle.
Q Cycle Activity:
Decode
None
Encoding:
SUBULNK 23h
03FFh
0100h
03DCh
(TOS)
DS39778E-page 393
PIC18F87J11 FAMILY
26.2.3
Note:
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
Enabling the PIC18 instruction set extension may cause legacy applications to
behave erratically or fail entirely.
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing (Section 6.6.1
“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations:
either as a location in the Access Bank (a = 0) or in a
GPR bank designated by the BSR (a = 1). When the
extended instruction set is enabled and a = 0, however,
a file register argument of 5Fh or less is interpreted as
an offset from the pointer value in FSR2 and not as a
literal address. For practical purposes, this means that
all instructions that use the Access RAM bit as an
argument – that is, all byte-oriented and bit-oriented
instructions, or almost half of the core PIC18 instructions – may behave differently when the extended
instruction set is enabled.
When the content of FSR2 is 00h, the boundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating
backward-compatible code. If this technique is used, it
may be necessary to save the value of FSR2 and
restore it when moving back and forth between C and
assembly routines in order to preserve the Stack
Pointer. Users must also keep in mind the syntax
requirements of the extended instruction set (see
Section 26.2.3.1 “Extended Instruction Syntax with
Standard PIC18 Commands”).
Although the Indexed Literal Offset mode can be very
useful for dynamic stack and pointer manipulation, it
can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are
accustomed to the PIC18 programming must keep in
mind that, when the extended instruction set is
enabled, register addresses of 5Fh or less are used for
Indexed Literal Offset Addressing.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
mode are provided on the following page to show how
execution is affected. The operand conditions shown in
the examples are applicable to all instructions of these
types.
DS39778E-page 394
26.2.3.1
Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register argument ‘f’ in the standard byte-oriented and
bit-oriented commands is replaced with the literal offset
value ‘k’. As already noted, this occurs only when ‘f’ is
less than or equal to 5Fh. When an offset value is used,
it must be indicated by square brackets (“[ ]”). As with
the extended instructions, the use of brackets indicates
to the compiler that the value is to be interpreted as an
index or an offset. Omitting the brackets, or using a
value greater than 5Fh within the brackets, will
generate an error in the MPASM Assembler.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing, the Access RAM argument is
never specified; it will automatically be assumed to be
‘0’. This is in contrast to standard operation (extended
instruction set disabled), when ‘a’ is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
Assembler.
The destination argument ‘d’ functions as before.
In the latest versions of the MPASM Assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing.
26.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
When porting an application to the PIC18F87J11 family,
it is very important to consider the type of code. A large,
re-entrant application that is written in C and would benefit from efficient compilation will do well when using the
instruction set extensions. Legacy applications that
heavily use the Access Bank will most likely not benefit
from using the extended instruction set.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
ADD W to Indexed
(Indexed Literal Offset mode)
BSF
Bit Set Indexed
(Indexed Literal Offset mode)
Syntax:
ADDWF
Syntax:
BSF [k], b
Operands:
0 k 95
d [0,1]
Operands:
0 f 95
0b7
Operation:
(W) + ((FSR2) + k) dest
Operation:
1 ((FSR2) + k)
Status Affected:
N, OV, C, DC, Z
Status Affected:
None
ADDWF
Encoding:
[k] {,d}
0010
Description:
01d0
kkkk
kkkk
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
Words:
1
Cycles:
1
Encoding:
1000
bbb0
kkkk
kkkk
Description:
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write to
destination
Example:
ADDWF
Before Instruction
W
OFST
FSR2
Contents
of 0A2Ch
After Instruction
W
Contents
of 0A2Ch
[OFST] ,0
Example:
BSF
Before Instruction
FLAG_OFST
FSR2
Contents
of 0A0Ah
After Instruction
Contents
of 0A0Ah
[FLAG_OFST], 7
=
=
0Ah
0A00h
=
55h
=
D5h
=
=
=
17h
2Ch
0A00h
=
20h
=
37h
SETF
Set Indexed
(Indexed Literal Offset mode)
=
20h
Syntax:
SETF [k]
Operands:
0 k 95
Operation:
FFh ((FSR2) + k)
Status Affected:
None
Encoding:
0110
1000
kkkk
kkkk
Description:
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write
register
Example:
SETF
Before Instruction
OFST
FSR2
Contents
of 0A2Ch
After Instruction
Contents
of 0A2Ch
2007-2012 Microchip Technology Inc.
[OFST]
=
=
2Ch
0A00h
=
00h
=
FFh
DS39778E-page 395
PIC18F87J11 FAMILY
26.2.5
SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLS
The latest versions of Microchip’s software tools have
been designed to fully support the extended instruction
set for the PIC18F87J11 family. This includes the
MPLAB C18 C Compiler, MPASM assembly language
and MPLAB Integrated Development Environment
(IDE).
When selecting a target device for software
development, MPLAB IDE will automatically set default
Configuration bits for that device. The default setting for
the XINST Configuration bit is ‘0’, disabling the
extended instruction set and Indexed Literal Offset
Addressing. For proper execution of applications
developed to take advantage of the extended
instruction set, XINST must be set during
programming.
DS39778E-page 396
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
• A menu option or dialog box within the
environment that allows the user to configure the
language tool and its settings for the project
• A command line option
• A directive in the source code
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompanying their development systems for the appropriate
information.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
27.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
27.1
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2007-2012 Microchip Technology Inc.
DS39778E-page 397
PIC18F87J11 FAMILY
27.2
MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
27.3
HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple
platforms.
27.4
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
27.5
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
27.6
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS39778E-page 398
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
27.7
MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
27.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
2007-2012 Microchip Technology Inc.
27.9
MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
27.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
DS39778E-page 399
PIC18F87J11 FAMILY
27.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
27.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a breakpoint, the file registers can be examined and modified.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
27.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
DS39778E-page 400
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta A/D, flow rate sensing,
plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
28.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +100°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any digital only input pin or MCLR with respect to VSS (except VDD) ........................................ -0.3V to 6.0V
Voltage on any combined digital and analog pin with respect to VSS ............................................. -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.75V
Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 4.0V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) (Note 2) 0 mA
Output clamp current, IOK (VO < 0 or VO > VDD) (Note 2) 0 mA
Maximum output current sunk by any PORTB and PORTC I/O pins......................................................................25 mA
Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pins ..........................................................8 mA
Maximum output current sunk by any PORTA, PORTF, PORTG and PORTH I/O pins............................................2 mA
Maximum output current sourced by any PORTB and PORTC I/O pins.................................................................25 mA
Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins .....................................................8 mA
Maximum output current sourced by any PORTA, PORTF, PORTG and PORTH I/O pins ......................................2 mA
Maximum current sunk byall ports combined.......................................................................................................200 mA
Maximum current sourced by all ports combined..................................................................................................200 mA
Note 1:
2:
Power dissipation is calculated as follows:
Pdis = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL) + (VTPOUT x ITPOUT)
No clamping diodes are present.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
2007-2012 Microchip Technology Inc.
DS39778E-page 401
PIC18F87J11 FAMILY
FIGURE 28-1:
PIC18F87J11 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED
(INDUSTRIAL)
4.0V
3.6V
3.5V
Voltage (VDD)
3.0V
PIC18F87J11 Family
2.5V
2.35V
2.0V
0
8 MHz
FMAX
Frequency
FMAX = 25 MHz in 8-Bit External Memory mode
FMAX = 48 MHz in all other modes
FIGURE 28-2:
PIC18F87J11 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED
(INDUSTRIAL)()
3.00V
Voltage (VDDCORE)
2.75V
2.7V
2.50V
PIC18F87J11 Family
2.25V
2.35V
2.00V
0
FMAX
8 MHz
Frequency
FMAX = 25 MHz in 8-Bit External Memory mode
FMAX = 48 MHz in all other modes
Note 1: When the on-chip voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCORE VDD 3.6V.
DS39778E-page 402
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
28.1
DC Characteristics:
Supply Voltage
PIC18F87J11 Family (Industrial)
PIC18F87J11 Family
(Industrial)
Param
No.
Symbol
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Characteristic
D001
VDD
D001B
VDDCORE External Supply for
Microcontroller Core
Supply Voltage
Min
Typ
Max
Units
Conditions
VDDCORE
2.0
—
—
3.6
3.6
V
V
ENVREG tied to VSS
ENVREG tied to VDD
2.0
—
2.7
V
ENVREG tied to VSS
D001C
AVDD
Analog Supply Voltage
VDD – 0.3
—
VDD + 0.3
V
D001D
AVSS
Analog Ground Potential VSS – 0.3
—
VSS + 0.3
V
D002
VDR
RAM Data Retention
Voltage(1)
1.5
—
—
V
D003
VPOR
VDD Power-on Reset
Voltage
—
—
0.7
V
D004
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05
—
—
D005
VBOR
Brown-out Reset Voltage
1.75(2)
2.0
2.4
Note 1:
This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing
RAM data.
When the Brown-out Reset is enabled, the part will continue to operate until the BOR occurs. This is valid,
although VDD may be below the minimum VDD voltage.
2:
2007-2012 Microchip Technology Inc.
See Section 5.3 “Power-on
Reset (POR)” for details
V/ms See Section 5.3 “Power-on
Reset (POR)” for details
V
DS39778E-page 403
PIC18F87J11 FAMILY
28.2
DC Characteristics:
PIC18F87J11 Family
(Industrial)
Param
No.
Power-Down and Supply Current
PIC18F87J11 Family (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
Typ
Max
Units
Conditions
0.5
1.4
A
-40°C
0.5
1.4
A
+25°C
5.5
10.2
A
+85°C
0.6
1.5
A
-40°C
0.6
1.5
A
+25°C
6.8
12.6
A
+85°C
2.9
7
A
-40°C
3.6
7
A
+25°C
9.6
19
A
+85°C
Power-Down Current (IPD)(1)
All devices
All devices
All devices
Note 1:
2:
3:
4:
5:
VDD = 2.0V(4)
(Sleep mode)
VDD = 2.5V(4)
(Sleep mode)
VDD = 3.3V(5)
(Sleep mode)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current are disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT is enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
Voltage regulator is disabled (ENVREG = 0, tied to VSS).
Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
DS39778E-page 404
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
28.2
DC Characteristics:
PIC18F87J11 Family
(Industrial)
Param
No.
Power-Down and Supply Current
PIC18F87J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
Typ
Max
Units
Conditions
5
14.2
A
-40°C
5.5
14.2
A
+25°C
+85°C
Supply Current (IDD)(2,3)
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
Note 1:
2:
3:
4:
5:
10
19.0
A
6.8
16.5
A
-40°C
7.6
16.5
A
+25°C
14
22.4
A
+85°C
37
84
A
-40°C
51
84
A
+25°C
72
108
A
+85°C
0.43
0.82
mA
-40°C
0.47
0.82
mA
+25°C
0.52
0.95
mA
+85°C
0.52
0.98
mA
-40°C
0.57
0.98
mA
+25°C
+85°C
0.63
1.10
mA
0.59
0.96
mA
-40°C
0.65
0.96
mA
+25°C
+85°C
0.72
1.18
mA
0.88
1.45
mA
-40°C
1
1.45
mA
+25°C
1.1
1.58
mA
+85°C
1.2
1.72
mA
-40°C
1.3
1.72
mA
+25°C
1.4
1.85
mA
+85°C
1.3
2.87
mA
-40°C
1.4
2.87
mA
+25°C
1.5
2.96
mA
+85°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 31 kHz
(RC_RUN mode,
internal oscillator source)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 1 MHz
(RC_RUN mode,
internal oscillator source)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 4 MHz
(RC_RUN mode,
internal oscillator source)
VDD = 3.3V(5)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current are disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT is enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
Voltage regulator is disabled (ENVREG = 0, tied to VSS).
Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
2007-2012 Microchip Technology Inc.
DS39778E-page 405
PIC18F87J11 FAMILY
28.2
DC Characteristics:
PIC18F87J11 Family
(Industrial)
Param
No.
Power-Down and Supply Current
PIC18F87J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
Typ
Max
Units
Conditions
3
9.4
A
-40°C
3.3
9.4
A
+25°C
8.5
17.2
A
+85°C
4
10.5
A
-40°C
4.3
10.5
A
+25°C
10.3
19.5
A
+85°C
34
82
A
-40°C
48
82
A
+25°C
69
105
A
+85°C
0.33
0.75
mA
-40°C
0.37
0.75
mA
+25°C
Supply Current (IDD) Cont.(2,3)
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
Note 1:
2:
3:
4:
5:
0.41
0.84
mA
+85°C
0.39
0.78
mA
-40°C
0.42
0.78
mA
+25°C
+85°C
0.47
0.91
mA
0.43
0.82
mA
-40°C
0.48
0.82
mA
+25°C
+85°C
0.54
0.95
mA
0.53
0.98
mA
-40°C
0.57
0.98
mA
+25°C
0.61
1.12
mA
+85°C
0.63
1.14
mA
-40°C
0.67
1.14
mA
+25°C
0.72
1.25
mA
+85°C
0.7
1.27
mA
-40°C
0.76
1.27
mA
+25°C
0.82
1.45
mA
+85°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 31 kHz
(RC_IDLE mode,
internal oscillator source)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 1 MHz
(RC_IDLE mode,
internal oscillator source)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 4 MHz
(RC_IDLE mode,
internal oscillator source)
VDD = 3.3V(5)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current are disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT is enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
Voltage regulator is disabled (ENVREG = 0, tied to VSS).
Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
DS39778E-page 406
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
28.2
DC Characteristics:
PIC18F87J11 Family
(Industrial)
Param
No.
Power-Down and Supply Current
PIC18F87J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
Typ
Max
Units
Conditions
0.17
0.35
mA
-40°C
0.18
0.35
mA
+25°C
+85°C
Supply Current (IDD) Cont.(2,3)
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
Note 1:
2:
3:
4:
5:
0.20
0.42
mA
0.29
0.52
mA
-40°C
0.31
0.52
mA
+25°C
0.34
0.61
mA
+85°C
0.59
1.1
mA
-40°C
0.44
0.85
mA
+25°C
0.42
0.85
mA
+85°C
0.70
1.25
mA
-40°C
0.75
1.25
mA
+25°C
0.79
1.36
mA
+85°C
1.10
1.7
mA
-40°C
1.10
1.7
mA
+25°C
+85°C
1.12
1.82
mA
1.55
1.95
mA
-40°C
1.47
1.89
mA
+25°C
1.54
1.92
mA
+85°C
9.9
14.8
mA
-40°C
9.5
14.8
mA
+25°C
10.1
15.2
mA
+85°C
13.3
23.2
mA
-40°C
12.2
22.7
mA
+25°C
12.1
22.7
mA
+85°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 1 MHZ
(PRI_RUN mode,
EC oscillator)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 4 MHz
(PRI_RUN mode,
EC oscillator)
VDD = 3.3V(5)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 48 MHZ
(PRI_RUN mode,
EC oscillator)
VDD = 3.3V(5)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current are disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT is enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
Voltage regulator is disabled (ENVREG = 0, tied to VSS).
Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
2007-2012 Microchip Technology Inc.
DS39778E-page 407
PIC18F87J11 FAMILY
28.2
DC Characteristics:
PIC18F87J11 Family
(Industrial)
Param
No.
Power-Down and Supply Current
PIC18F87J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
Typ
Max
Units
Conditions
4.5
5.2
mA
-40°C
4.4
5.2
mA
+25°C
4.5
5.2
mA
+85°C
5.7
6.7
mA
-40°C
5.5
6.3
mA
+25°C
+85°C
Supply Current (IDD) Cont.(2,3)
All devices
All devices
All devices
All devices
Note 1:
2:
3:
4:
5:
5.3
6.3
mA
10.8
13.5
mA
-40°C
10.8
13.5
mA
+25°C
9.9
13.0
mA
+85°C
13.4
24.1
mA
-40°C
12.3
20.2
mA
+25°C
11.2
19.5
mA
+85°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 4 MHZ,
16 MHz internal
(PRI_RUN HSPLL mode)
VDD = 3.3V(5)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 10 MHZ,
40 MHz internal
(PRI_RUN HSPLL mode)
VDD = 3.3V(5)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current are disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT is enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
Voltage regulator is disabled (ENVREG = 0, tied to VSS).
Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
DS39778E-page 408
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
28.2
DC Characteristics:
PIC18F87J11 Family
(Industrial)
Param
No.
Power-Down and Supply Current
PIC18F87J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
Typ
Max
Units
Conditions
0.10
0.26
mA
-40°C
0.07
0.18
mA
+25°C
+85°C
Supply Current (IDD) Cont.(2,3)
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
Note 1:
2:
3:
4:
5:
0.09
0.22
mA
0.25
0.48
mA
-40°C
0.13
0.30
mA
+25°C
+85°C
0.10
0.26
mA
0.45
0.68
mA
-40°C
0.26
0.45
mA
+25°C
0.30
0.54
mA
+85°C
0.36
0.60
mA
-40°C
0.33
0.56
mA
+25°C
0.35
0.56
mA
+85°C
0.52
0.81
mA
-40°C
0.45
0.70
mA
+25°C
+85°C
0.46
0.70
mA
0.80
1.15
mA
-40°C
0.66
0.98
mA
+25°C
0.65
0.98
mA
+85°C
5.2
6.5
mA
-40°C
4.9
5.9
mA
+25°C
3.4
4.5
mA
+85°C
6.2
12.4
mA
-40°C
5.9
11.5
mA
+25°C
5.8
11.5
mA
+85°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 3.3V(5)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 48 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 3.3V(5)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current are disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT is enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
Voltage regulator is disabled (ENVREG = 0, tied to VSS).
Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
2007-2012 Microchip Technology Inc.
DS39778E-page 409
PIC18F87J11 FAMILY
28.2
DC Characteristics:
PIC18F87J11 Family
(Industrial)
Param
No.
Power-Down and Supply Current
PIC18F87J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
Typ
Max
Units
Conditions
18
35
µA
-40°C
19
35
µA
+25°C
+85°C
Supply Current (IDD) Cont.(2,3)
All devices
All devices
All devices
All devices
All devices
All devices
Note 1:
2:
3:
4:
5:
28
49
µA
20
45
µA
-40°C
21
45
µA
+25°C
+85°C
32
61
µA
0.06
0.11
mA
-40°C
0.07
0.11
mA
+25°C
0.09
0.15
mA
+85°C
14
28
µA
-40°C
15
28
µA
+25°C
24
43
µA
+85°C
15
31
µA
-40°C
16
31
µA
+25°C
27
50
µA
+85°C
0.05
0.10
mA
-40°C
0.06
0.10
mA
+25°C
0.08
0.14
mA
+85°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 32 kHz(3)
(SEC_RUN mode,
Timer1 as clock)
VDD = 3.3V(5)
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 32 kHz(3)
(SEC_IDLE mode,
Timer1 as clock)
VDD = 3.3V(5)
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current are disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT is enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
Voltage regulator is disabled (ENVREG = 0, tied to VSS).
Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
DS39778E-page 410
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
28.2
DC Characteristics:
PIC18F87J11 Family
(Industrial)
Param
No.
D022
(IWDT)
D025
(IOSCB)
D026
(IAD)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Device
2:
3:
4:
5:
Typ
Max
Units
Conditions
Module Differential Currents (IWDT, IOSCB, IAD)
Watchdog Timer
Timer1 Oscillator
A/D Converter
Note 1:
Power-Down and Supply Current
PIC18F87J11 Family (Industrial) (Continued)
2.1
2.2
4.3
3.0
3.1
5.5
5.9
6.2
6.9
7.0
7.0
9.5
8.0
8.0
10.4
12.1
12.1
13.6
A
A
A
A
A
A
A
A
A
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
VDD = 3.3V
14
24
A
-40°C
15
24
A
+25°C
23
36
A
+85°C
17
26
A
-40°C
18
26
A
+25°C
25
38
A
+85°C
19
35
A
-40°C
21
35
A
+25°C
28
44
A
+85°C
3.0
10.0
A
-40°C to +85°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
3.0
10.0
A
-40°C to +85°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
3.2
11.0
A
-40°C to +85°C
VDD = 3.3V
VDD = 2.0V,
VDDCORE = 2.0V(4)
32 kHz on Timer1(3)
VDD = 2.5V,
VDDCORE = 2.5V(4)
32 kHz on Timer1(3)
VDD = 3.3V
32 kHz on Timer1(3)
A/D on, not converting
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current are disabled (such as WDT, Timer1 oscillator, BOR, etc.).
The supply current is mainly a function of the operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT is enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
Voltage regulator is disabled (ENVREG = 0, tied to VSS).
Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
2007-2012 Microchip Technology Inc.
DS39778E-page 411
PIC18F87J11 FAMILY
28.3
DC Characteristics:PIC18F87J11 Family (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Max
Units
with TTL Buffer
VSS
0.15 VDD
V
with Schmitt Trigger Buffer
Conditions
Input Low Voltage
All I/O Ports:
D030
D031
VSS
0.2 VDD
V
D032
MCLR
VSS
0.2 VDD
V
D033
OSC1
VSS
0.3 VDD
V
HS, HSPLL modes
D033A
OSC1
VSS
0.2 VDD
V
EC, ECPLL modes
D034
T13CKI
VSS
0.3
V
0.25 VDD + 0.8V
VDD
V
VDD < 3.3V
2.0
VDD
V
3.3V VDD 3.6V
VIH
Input High Voltage
I/O Ports with Non 5.5V Tolerance:(2)
D040
with TTL Buffer
D040A
D041
with Schmitt Trigger Buffer
0.8 VDD
VDD
V
D041A
RC3 and RC4
0.7 VDD
VDD
V
I2C™ enabled
2.1
VDD
V
SMBus enabled
D041B
I/O Ports with 5.5V Tolerance:(2)
with TTL Buffer
0.25 VDD + 0.8V
5.5
V
VDD < 3.3V
2.0
5.5
V
3.3V VDD 3.6V
0.8 VDD
5.5
V
D042
MCLR
0.8 VDD
VDD
V
D043
OSC1
0.7 VDD
VDD
V
HS, HSPLL modes
D043A
OSC1
0.8 VDD
VDD
V
EC, ECPLL modes
D044
T13CKI
1.6
VDD
V
with Schmitt Trigger Buffer
IIL
Input Leakage Current(1)
D060
I/O Ports with Non 5.5V Tolerance(2)
—
1
A
VSS VPIN VDD,
Pin at high-impedance
D060A
I/O Ports with 5.5V Tolerance(2)
—
1
A
VSS VPIN 5.5V,
Pin at high-impedance
D061
MCLR
—
1
A
Vss VPIN VDD
D063
OSC1
—
5
A
Vss VPIN VDD
80
400
A
VDD = 3.3V, VPIN = VSS
D070
Note 1:
2:
IPU
Weak Pull-up Current
IPURB
PORTB Weak Pull-up Current
Negative current is defined as current sourced by the pin.
Refer to Table 11-1 for the pins that have corresponding tolerance limits.
DS39778E-page 412
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
28.3
DC Characteristics:PIC18F87J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
VOL
D080
Characteristic
Min
Max
Units
Conditions
PORTA, PORTF, PORTG,
PORTH
—
0.4
V
IOL = 2 mA, VDD = 3.3V,
-40C to +85C
PORTD, PORTE, PORTJ
—
0.4
V
IOL = 4 mA, VDD = 3.3V,
-40C to +85C
PORTB, PORTC
—
0.4
V
IOL = 8.5 mA, VDD = 3.3V,
-40C to +85C
OSC2/CLKO
(EC, ECPLL modes)
—
0.4
V
IOL = 1.6 mA, VDD = 3.3V,
-40C to +85C
PORTA, PORTF, PORTG,
PORTH
2.4
—
V
IOH = -2 mA, VDD = 3.3V,
-40C to +85C
PORTD, PORTE, PORTJ
2.4
—
V
IOH = -3 mA, VDD = 3.3V,
-40C to +85C
PORTB, PORTC
2.4
—
V
IOH = -6 mA, VDD = 3.3V,
-40C to +85C
2.4
—
V
IOH = -1 mA, VDD = 3.3V,
-40C to +85C
—
15
pF
In HS mode when
external clock is used to
drive OSC1
Output Low Voltage
I/O Ports:
D083
VOH
D090
Output High Voltage(1)
I/O Ports:
D092
OSC2/CLKO
(INTOSC, EC, ECPLL modes)
V
Capacitive Loading Specs
on Output Pins
D100
COSC2 OSC2 Pin
D101
CIO
All I/O Pins and OSC2
—
50
pF
To meet the AC Timing
Specifications
D102
CB
SCLx, SDAx
—
400
pF
I2C™ Specification
Note 1:
2:
Negative current is defined as current sourced by the pin.
Refer to Table 11-1 for the pins that have corresponding tolerance limits.
2007-2012 Microchip Technology Inc.
DS39778E-page 413
PIC18F87J11 FAMILY
TABLE 28-1:
MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
Program Flash Memory
D130
EP
Cell Endurance
10K
—
—
D131
VPR
VDD for Read
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
VDD
2.35
—
3.6
V
ENVREG tied to VDD
VDDCORE
2.25
—
2.7
V
ENVREG tied to VSS
—
2.8
—
ms
—
33.0
—
20
—
—
Year Provided no other
specifications are violated
mA
D132B VPEW
D133A TIW
E/W -40C to +85C
Voltage for Self-Timed Erase or Write:
Self-Timed Write Cycle Time
Self-Timed Page Erase Cycle Time
D134
TRETD Characteristic Retention
D135
IDDP
Supply Current During Programming
—
3
14
D1xxx
TWE
Writes per Erase Cycle
—
—
1
ms
For each physical address
† Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS39778E-page 414
2007-2012 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 28-2:
COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
D300
VIOFF
Input Offset Voltage
—
±5.0
±25
mV
D301
VICM
Input Common-Mode Voltage
0
—
AVDD – 1.5
V
D302
CMRR
Common-Mode Rejection Ratio
55
—
—
dB
D303
TRESP
Response Time(1)
—
150
400
ns
D304
TMC2OV
Comparator Mode Change to
Output Valid
—
—
10
s
D305
VIRV
Internal Reference Voltage
—
1.2(2)
—
V
Note 1:
2:
Comments
±1.2%
Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
The tolerance is ±1.2%.
TABLE 28-3:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
D310
VRES
Resolution
VDD/24
—
VDD/32
LSb
D311
VRAA
Absolute Accuracy
—
—
1/2
LSb
D312
VRUR
Unit Resistor Value (R)
—
2k
—
D313
TSET
Settling Time(1)
—
—
10
s
Note 1:
Comments
Settling time is measured while CVRR = 1 and the CVR bits transition from ‘0000’ to ‘1111’.
TABLE 28-4:
INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
VRGOUT Regulator Output Voltage
CF
External Filter Capacitor Value
2007-2012 Microchip Technology Inc.
Min
Typ
Max
Units
—
2.5
—
V
4.7
10
—
F
Comments
Capacitor must be low
series resistance
(
