PIC18F87J50 Family
Data Sheet
64/80-Pin High-Performance,
1-Mbit Flash USB Microcontrollers
with nanoWatt Technology
© 2009 Microchip Technology Inc.
DS39775C
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•
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•
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•
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•
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
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Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39775C-page 2
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
64/80-Pin High-Performance, 1-Mbit Flash USB
Microcontrollers with nanoWatt Technology
Universal Serial Bus Features:
Peripheral Highlights (continued):
• USB V2.0 Compliant SIE
• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)
• Supports Control, Interrupt, Isochronous and
Bulk Transfers
• Supports up to 32 Endpoints (16 bidirectional)
• 3.9-Kbyte Dual Access RAM for USB
• On-Chip USB Transceiver
• 10-Bit, up to 12-Channel Analog-to-Digital (A/D)
Converter module:
- Auto-acquisition capability
- Conversion available during Sleep
• Two Enhanced USART modules:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-wake-up on Start bit
- Auto-Baud Detect
Flexible Oscillator Structure:
• High-Precision PLL for USB
• Two External Clock modes, up to 48 MHz
• Internal 31 kHz Oscillator, Tunable Internal
Oscillator, 31 kHz to 8 MHz
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if any clock stops
Peripheral Highlights:
• High-Current Sink/Source 25 mA/25mA
(PORTB and PORTC)
• Four Programmable External Interrupts
• Four Input Change Interrupts
• Two Capture/Compare/PWM (CCP) modules
• Three Enhanced Capture/Compare/PWM (ECCP)
modules:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
• Two Master Synchronous Serial Port (MSSP)
modules supporting 3-Wire SPI (all 4 modes) and
I2C™ Master and Slave modes
• 8-Bit Parallel Master Port/Enhanced Parallel
Slave Port with 16 Address Lines
• Dual Analog Comparators with Input Multiplexing
© 2009 Microchip Technology Inc.
External Memory Bus
(80-pin devices only):
• Address Capability of up to 2 Mbytes
• 8-Bit or 16-Bit Interface
• 12-Bit, 16-Bit and 20-Bit Addressing modes
Special Microcontroller Features:
• 5.5V Tolerant Inputs (digital-only pins)
• Low-Power, High-Speed CMOS Flash Technology
• C Compiler Optimized Architecture for
Re-Entrant Code
• Power Management Features:
- Run: CPU on, peripherals on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
• Priority Levels for Interrupts
• Self-Programmable under Software Control
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™
(ICSP™) via Two Pins
• In-Circuit Debug (ICD) with 3 Breakpoints via
Two Pins
• Operating Voltage Range of 2.0V to 3.6V
• On-Chip 2.5V Regulator
• Flash Program Memory of 10000 Erase/Write
Cycles and 20-Year Data Retention
DS39775C-page 3
SPI
Master
I2C™
EUSART
Comparators
Timers
8/16-Bit
External Bus
PMP/PSP
PIC18F87J50 FAMILY
2
Y
Y
2
2
2/3
N
Y
2
Y
Y
2
2
2/3
N
Y
2/3
2
Y
Y
2
2
2/3
N
Y
8
2/3
2
Y
Y
2
2
2/3
N
Y
65
12
2/3
2
Y
Y
2
2
2/3
Y
Y
65
12
2/3
2
Y
Y
2
2
2/3
Y
Y
3904*
65
12
2/3
2
Y
Y
2
2
2/3
Y
Y
3904*
65
12
2/3
2
Y
Y
2
2
2/3
Y
Y
MSSP
Device
Flash Program
Memory (bytes)
SRAM Data
Memory
(bytes)
PIC18F65J50
32K
PIC18F66J50
64K
PIC18F66J55
I/O
10-Bit
A/D (ch)
CCP/
ECCP
(PWM)
3904*
49
8
2/3
3904*
49
8
2/3
96K
3904*
49
8
PIC18F67J50
128K
3904*
49
PIC18F85J50
32K
3904*
PIC18F86J50
64K
3904*
PIC18F86J55
96K
PIC18F87J50
128K
*
Includes the dual access RAM used by the USB module which is shared with data memory.
RE2/PMBE/P2B
RE3/PMA13/P3C/REFO
RE4/PMA12/P3B
RE5/PMA11/P1C
RE6/PMA10/P1B
RE7/PMA9/ECCP2(1)/P2A(1)
RD0/PMD0
VDD
VSS
RD1/PMD1
RD2/PMD2
RD3/PMD3
RD4/PMD4/SDO2
RD5/PMD5/SDI2/SDA2
RD6/PMD6/SCK2/SCL2
RD7/PMD7/SS2
Pin Diagrams
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
64-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC18F6XJ5X
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RB0/FLT0/INT0
RB1/INT1/PMA4
RB2/INT2/PMA3
RB3/INT3/PMA2
RB4/KBI0/PMA1
RB5/KBI1/PMA0
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
RB7/KBI3/PGD
RC5/SDO1/C2OUT
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
VUSB
ENVREG
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1
RA0/AN0
VSS
VDD
RA5/AN4/C2INA
RA4/T0CKI
RC1/T1OSI/ECCP2(1)/P2A(1)
RC0/T1OSO/T13CKI
RC6/TX1/CK1
RC7/RX1/DT1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RE1/PMWR/P2C
RE0/PMRD/P2D
RG0/PMA8/ECCP3/P3A
RG1/PMA7/TX2/CK2
RG2/PMA6/RX2/DT2
RG3/PMCS1/CCP4/P3D
MCLR
RG4/PMCS2/CCP5/P1D
VSS
VDDCORE/VCAP
RF7/SS1/C1OUT
RF6/AN11/C1INA
RF5/AN10/C1INB/CVREF
RF4/D+
RF3/DRF2/PMA5/AN7/C2INB
Note
1:
The ECCP2/P2A pin placement depends on the setting of the CCP2MX Configuration bit.
DS39775C-page 4
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
Note
RJ0/ALE
RJ1/OE
61
RD3/AD3/PMD3(3)
67
62
RD2/AD2/PMD2(3)
68
RD7/AD7/PMD7(3)/SS2
RD1/AD1/PMD1(3)
69
63
VSS
70
RD6/AD6/PMD6(3)/SCK2/SCL2
VDD
71
64
RD0/AD0/PMD0
72
RD4/AD4/PMD4(3)/SDO2
RE7/AD15/PMA9/ECCP2(1)/P2A(1)
73
RD5/AD5/PMD5(3)/SDI2/SDA2
RE6/AD14/PMA10/P1B(2)
74
65
RE5/AD13/PMA11/P1C(2)
75
66
RE3/AD11/PMA13/P3C(2)/REFO
RE4/AD12/PMA12/P3B(2)
RE2/AD10/PMBE(3)/P2B
PIC18F8XJ5X
51
50
49
48
47
46
45
44
17
18
19
20
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
VSS
VDD
(4)/AN4/C2INA
RA4/PMD5(4)/T0CKI
RC1/T1OSI/ECCP2(1)/P2A(1)
RC0/T1OSO/T13CKI
RC6/TX1/CK1
RC7/RX1/DT1
RJ4/BA0
RJ2/WRL
RJ3/WRH
RB0/FLT0/INT0
RB1/INT1/PMA4
RB2/INT2/PMA3
RB3/INT3/ECCP2(1)/
P2A(1)/PMA2
RB4/KBI0/PMA1
RB5/KBI1/PMA0
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
RB7/KBI3/PGD
RC5/SDO1/C2OUT
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RJ7/UB
RJ6/LB
RJ5/CE
25
AVDD
RA5/PMD4
24
43
42
41
RH5/PMBE(4)/AN13/P3B(2)/C2IND
RH6/PMRD(4)/AN14/
P1C(2)/C1INC
54
53
52
ENVREG
RF6/PMD1(4)/AN11/C1INA
RF5/PMD2(4)/AN10/
C1INB/CVREF
RF4/D+
RF3/DRF2/PMA5/AN7/C2INB
RH7/PMWR(4)/AN15/P1B(2)
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VUSB
RF7/PMD0(4)/SS1/C1OUT
59
58
57
56
55
22
23
RG2/PMA6/RX2/DT2
RG3/PMCS1/CCP4/P3D
MCLR
RG4/PMCS2/CCP5/P1D
VSS
VDDCORE/VCAP
60
2
21
RE1/AD9/PMWR(3)/P2C
RE0/AD8/PMRD(3)/P2D
RG0/PMA8/ECCP3/P3A
RG1/PMA7/TX2/CK2
1
RH4/PMD3(4)/AN12/P3C(2)/C2INC
RH2/A18/PMD7(4)
RH3/A19/PMD6(4)
76
RH0/A16
78
RH1/A17
80
79
80-Pin TQFP
77
Pin Diagrams (Continued)
1:
The ECCP2/P2A pin placement depends on the setting of the CCP2MX Configuration bit and the program memory mode.
2:
P1B, P1C, P3B and P3C pin placement depends on the setting of the ECCPMX Configuration bit.
3:
PMP pin placement when PMPMX = 1.
4:
PMP pin placement when PMPMX = 0.
© 2009 Microchip Technology Inc.
DS39775C-page 5
PIC18F87J50 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Oscillator Configurations ............................................................................................................................................................ 35
3.0 Power-Managed Modes ............................................................................................................................................................. 47
4.0 Reset .......................................................................................................................................................................................... 55
5.0 Memory Organization ................................................................................................................................................................. 69
6.0 Flash Program Memory .............................................................................................................................................................. 97
7.0 External Memory Bus ............................................................................................................................................................... 107
8.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 119
9.0 Interrupts .................................................................................................................................................................................. 121
10.0 I/O Ports ................................................................................................................................................................................... 137
11.0 Parallel Master Port .................................................................................................................................................................. 167
12.0 Timer0 Module ......................................................................................................................................................................... 191
13.0 Timer1 Module ......................................................................................................................................................................... 195
14.0 Timer2 Module ......................................................................................................................................................................... 201
15.0 Timer3 Module ......................................................................................................................................................................... 203
16.0 Timer4 Module ......................................................................................................................................................................... 207
17.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 209
18.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 217
19.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 233
20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 279
21.0 10-bit Analog-to-Digital Converter (A/D) Module ...................................................................................................................... 301
22.0 Universal Serial Bus (USB) ...................................................................................................................................................... 311
23.0 Comparator Module.................................................................................................................................................................. 337
24.0 Comparator Voltage Reference Module ................................................................................................................................... 345
25.0 Special Features of the CPU .................................................................................................................................................... 349
26.0 Instruction Set Summary .......................................................................................................................................................... 365
27.0 Development Support............................................................................................................................................................... 415
28.0 Electrical Characteristics .......................................................................................................................................................... 419
29.0 Packaging Information.............................................................................................................................................................. 459
Appendix A: Revision History............................................................................................................................................................. 463
Appendix B: Device Differences......................................................................................................................................................... 463
The Microchip Web Site ..................................................................................................................................................................... 477
Customer Change Notification Service .............................................................................................................................................. 477
Customer Support .............................................................................................................................................................................. 477
Reader Response .............................................................................................................................................................................. 478
Product Identification System............................................................................................................................................................. 479
DS39775C-page 6
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
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© 2009 Microchip Technology Inc.
DS39775C-page 7
PIC18F87J50 FAMILY
NOTES:
DS39775C-page 8
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC18F65J50
• PIC18F85J50
• PIC18F66J50
• PIC18F86J50
• PIC18F66J55
• PIC18F86J55
• PIC18F67J50
• PIC18F87J50
This family introduces a new line of low-voltage USB
microcontrollers with the main traditional advantage of
all PIC18 microcontrollers – namely, high computational performance and a rich feature set – at an
extremely competitive price point. These features
make the PIC18F87J10 family a logical choice for
many high-performance applications, where cost is a
primary consideration.
1.1
1.1.1
Core Features
nanoWatt TECHNOLOGY
All of the devices in the PIC18F87J10 family incorporate
a range of features that can significantly reduce power
consumption during operation. Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal RC oscillator, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• On-the-Fly Mode Switching: The
power-managed modes are invoked by user code
during operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.
1.1.2
UNIVERSAL SERIAL BUS (USB)
Devices in the PIC18F87J10 family incorporate a
fully-featured Universal Serial Bus communications
module with a built-in transceiver that is compliant with
the USB Specification Revision 2.0. The module
supports both low-speed and full-speed communication
for all supported data transfer types.
1.1.3
OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC18F87J10 family offer five
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• Two Crystal modes, using crystals or ceramic
resonators.
• Two External Clock modes, offering the option of
a divide-by-4 clock output.
• An internal oscillator block which provides an
8 MHz clock and an INTRC source (approximately 31 kHz, stable over temperature and VDD),
as well as a range of 6 user-selectable clock
frequencies, between 125 kHz to 4 MHz, for a
total of 8 clock frequencies. This option frees an
oscillator pin for use as an additional general
purpose I/O.
• A Phase Lock Loop (PLL) frequency multiplier,
available to the high-speed crystal, external
oscillator and internal oscillator, providing a clock
speed up to 48 MHz.
• Dual clock operation, allowing the USB module to
run from a high-frequency oscillator while the rest
of the microcontroller is clocked at a different
frequency.
The internal oscillator block provides a stable reference
source that gives the family additional features for
robust operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
1.1.4
EXPANDED MEMORY
The PIC18F87J10 family provides ample room for
application code, from 32 Kbytes to 128 Kbytes of code
space. The Flash cells for program memory are rated
to last in excess of 10000 erase/write cycles. Data
retention without refresh is conservatively estimated to
be greater than 20 years.
The Flash program memory is readable and writable
during normal operation. The PIC18F87J10 family also
provides plenty of room for dynamic application data
with up to 3904 bytes of data RAM.
© 2009 Microchip Technology Inc.
DS39775C-page 9
PIC18F87J50 FAMILY
1.1.5
EXTERNAL MEMORY BUS
In the event that 128 Kbytes of memory are inadequate
for an application, the 80-pin members of the
PIC18F87J10 family also implement an External Memory Bus (EMB). This allows the controller’s internal
program counter to address a memory space of up to
2 Mbytes, permitting a level of data access that few
8-bit devices can claim. This allows additional memory
options, including:
• Using combinations of on-chip and external
memory up to the 2-Mbyte limit
• Using external Flash memory for reprogrammable
application code or large data tables
• Using external RAM devices for storing large
amounts of variable data
1.1.6
EXTENDED INSTRUCTION SET
The PIC18F87J10 family implements the optional
extension to the PIC18 instruction set, adding 8 new
instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as ‘C’.
1.1.7
1.3
EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members, or even
jumping from 64-pin to 80-pin devices.
The PIC18F87J10 family is also pin compatible with
other PIC18 families, such as the PIC18F87J10,
PIC18F87J11, PIC18F8720 and PIC18F8722. This
allows a new dimension to the evolution of applications,
allowing developers to select different price points
within Microchip’s PIC18 portfolio, while maintaining
the same feature set.
1.2
• CCP Modules: All devices in the family incorporate
two Capture/Compare/PWM (CCP) modules and
three Enhanced CCP modules to maximize
flexibility in control applications. Up to four different
time bases may be used to perform several
different operations at once. Each of the three
ECCPs offers up to four PWM outputs, allowing for
a total of 12 PWMs. The ECCPs also offer many
beneficial features, including polarity selection,
programmable dead time, auto-shutdown and
restart and Half-Bridge and Full-Bridge Output
modes.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, and
thus, reducing code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 28.0 “Electrical Characteristics” for
time-out periods.
Details on Individual Family
Members
Devices in the PIC18F87J10 family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in two
ways:
1.
2.
Flash program memory (six sizes, ranging from
32 Kbytes for PIC18FX5J50 devices to
128 Kbytes for PIC18FX7J50).
I/O ports (7 bidirectional ports on 64-pin devices,
9 bidirectional ports on 80-pin devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1 and Table 1-2.
The pinouts for all devices are listed in Table 1-3 and
Table 1-4.
Other Special Features
• Communications: The PIC18F87J10 family
incorporates a range of serial and parallel communication peripherals, including a fully featured
Universal Serial Bus communications module that
is compliant with the USB Specification
Revision 2.0. This device also includes 2 independent Enhanced USARTs and 2 Master SSP
modules, capable of both SPI and I2C™ (Master
and Slave) modes of operation. The device also
has a parallel port and can be configured to serve
as either a Parallel Master Port or as a Parallel
Slave Port.
DS39775C-page 10
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 1-1:
DEVICE FEATURES FOR THE PIC18F6XJ5X (64-PIN DEVICES)
Features
PIC18F65J50
PIC18F66J50
PIC18F66J55
PIC18F67J50
DC – 48 MHz
DC – 48 MHz
DC – 48 MHz
DC – 48 MHz
32K
64K
96K
128K
Program Memory (Instructions)
16384
32768
49152
65536
Data Memory (Bytes)
3904
3904
3904
3904
Operating Frequency
Program Memory (Bytes)
Interrupt Sources
30
I/O Ports
Ports A, B, C, D, E, F, G
Timers
5
Capture/Compare/PWM Modules
2
Enhanced Capture/
Compare/PWM Modules
3
Serial Communications
MSSP (2), Enhanced USART (2), USB
Parallel Communications (PMP)
Yes
10-Bit Analog-to-Digital Module
8 Input Channels
Resets (and Delays)
Instruction Set
POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
75 Instructions, 83 with Extended Instruction Set Enabled
Packages
64-Pin TQFP
TABLE 1-2:
DEVICE FEATURES FOR THE PIC18F8XJ5X (80-PIN DEVICES)
Features
PIC18F85J50
PIC18F86J50
PIC18F86J55
PIC18F87J50
DC – 48 MHz
DC – 48 MHz
DC – 48 MHz
DC – 48 MHz
32K
64K
96K
128K
Program Memory (Instructions)
16384
32768
49152
65536
Data Memory (Bytes)
3904
3904
3904
3904
Operating Frequency
Program Memory (Bytes)
Interrupt Sources
I/O Ports
30
Ports A, B, C, D, E, F, G, H, J
Timers
5
Capture/Compare/PWM Modules
2
Enhanced Capture/
Compare/PWM Modules
3
Serial Communications
MSSP (2), Enhanced USART (2), USB
Parallel Communications (PMP)
Yes
10-Bit Analog-to-Digital Module
12 Input Channels
Resets (and Delays)
Instruction Set
Packages
© 2009 Microchip Technology Inc.
POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
75 Instructions, 83 with Extended Instruction Set Enabled
80-Pin TQFP
DS39775C-page 11
PIC18F87J50 FAMILY
FIGURE 1-1:
PIC18F6XJ5X (64-PIN) BLOCK DIAGRAM
Data Bus
Table Pointer
20
Address Latch
PCU PCH PCL
Program Counter
12
Data Address
31 Level Stack
4
BSR
Address Latch
STKPTR
Program Memory
(32-128 Kbytes)
12
PORTC
RC0:RC7(1)
inc/dec
logic
Table Latch
Address
Decode
ROM Latch
Instruction Bus
PORTB
RB0:RB7(1)
4
Access
Bank
12
FSR0
FSR1
FSR2
Data Latch
8
RA0:RA5(1)
Data Memory
(3.9 Kbytes)
PCLATU PCLATH
21
PORTA
Data Latch
8
8
inc/dec logic
PORTD
RD0:RD7(1)
IR
Instruction
Decode and
Control
OSC2/CLKO
OSC1/CLKI
Timing
Generation
8 MHz
INTOSC
INTRC
Oscillator
VUSB
ENVREG
ECCP1
PMP
Note
PRODH PRODL
3
Power-up
Timer
Precision
Band Gap
Reference
W
8
8
8
PORTF
8
RF2:RF7(1)
ALU
8
Watchdog
Timer
PORTG
Brown-out
Reset(2)
Voltage
Regulator
VDD, VSS
RG0:RG4(1)
MCLR
ADC
10-Bit
Timer0
Timer1
Timer2
Timer3
Timer4
ECCP2
ECCP3
CCP4
CCP5
EUSART1
EUSART2
1:
See Table 1-3 for I/O port pin descriptions.
2:
BOR functionality is provided when the on-board voltage regulator is enabled.
DS39775C-page 12
8
8
Power-on
Reset
PORTE
RE0:RE7(1)
8 x 8 Multiply
BITOP
Oscillator
Start-up Timer
USB
Module
VDDCORE/VCAP
8
State Machine
Control Signals
Comparators
MSSP1
MSSP2
USB
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
FIGURE 1-2:
PIC18F8XJ5X (80-PIN) BLOCK DIAGRAM
Data Bus
Table Pointer
inc/dec logic
21
31 Level Stack
Address Latch
System Bus Interface
Address Latch
PCU PCH PCL
Program Counter
PORTB
RB0:RB7(1)
12
Data Address
4
4
12
BSR
STKPTR
Program Memory
(32-128 Kbytes)
RA0:RA5(1)
Data Memory
(3.9 Kbytes)
PCLATU PCLATH
20
PORTA
Data Latch
8
8
FSR0
FSR1
FSR2
Data Latch
PORTC
Access
Bank
RC0:RC7(1)
12
inc/dec
logic
8
Table Latch
PORTD
RD0:RD7(1)
Address
Decode
ROM Latch
Instruction Bus
PORTE
IR
RE0:RE7(1)
AD15:AD0, A19:A16
(Multiplexed with PORTD,
PORTE and PORTH)
8
OSC2/CLKO
OSC1/CLKI
Timing
Generation
Power-up
Timer
8 MHz
INTOSC
VUSB
PMP
Note
ECCP1
8 x 8 Multiply
8
W
BITOP
8
8
8
ALU
PORTH
8
RH0:RH7(1)
Watchdog
Timer
PORTJ
Brown-out
Reset(2)
Voltage
Regulator
VDD, VSS
RJ0:RJ7(1)
MCLR
ADC
10-Bit
Timer0
Timer1
Timer2
Timer3
Timer4
ECCP2
ECCP3
CCP4
CCP5
EUSART1
EUSART2
1:
See Table 1-4 for I/O port pin descriptions.
2:
BOR functionality is provided when the on-board voltage regulator is enabled.
© 2009 Microchip Technology Inc.
PORTG
8
RG0:RG4(1)
Power-on
Reset
Precision
Band Gap
Reference
VDDCORE/VCAP
3
Oscillator
Start-up Timer
USB
Module
ENVREG
RF2:RF7(1)
8
INTRC
Oscillator
PORTF
PRODH PRODL
Instruction
Decode &
Control
State Machine
Control Signals
Comparators
MSSP1
MSSP2
USB
DS39775C-page 13
PIC18F87J50 FAMILY
TABLE 1-3:
PIC18F6XJ5X PINOUT I/O DESCRIPTIONS
Pin Number
64-TQFP
Pin
Type
Buffer
Type
MCLR
7
I
ST
OSC1/CLKI/RA7
OSC1
39
Pin Name
I
CLKI
I
RA7(3)
OSC2/CLKO/RA6
OSC2
I/O
Description
Master Clear (Reset) input. This pin is an active-low Reset
to the device.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS
otherwise.
CMOS Main oscillator input connection.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
TTL Main clock input connection.
General purpose I/O pin.
ST
40
O
—
CLKO
O
—
RA6(3)
I/O
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
Main oscillator feedback output connection.
In RC mode, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
System cycle clock output (FOSC/4).
General purpose I/O pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39775C-page 14
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 1-3:
PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
64-TQFP
Pin
Type
Buffer
Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
24
RA1/AN1
RA1
AN1
23
RA2/AN2/VREFRA2
AN2
VREF-
22
RA3/AN3/VREF+
RA3
AN3
VREF+
21
RA4/T0CKI
RA4
T0CKI
28
RA5/AN4/C2INA
RA5
AN4
C2INA
27
RA6
RA7
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
I/O
I
ST
ST
I/O
I
—
TTL
Analog
Analog
—
—
—
See the OSC2/CLKO/RA6 pin.
—
—
—
See the OSC1/CLKI/RA7 pin.
Digital I/O.
Timer0 external clock input.
Digital I/O.
Analog input 4.
Comparator 2 input A
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39775C-page 15
PIC18F87J50 FAMILY
TABLE 1-3:
PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
64-TQFP
Pin
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/FLT0/INT0
RB0
FLT0
INT0
48
RB1/INT1/PMA4
RB1
INT1
PMA4
47
RB2/INT2/PMA3
RB2
INT2
PMA3
46
RB3/INT3/PMA2
RB3
INT3
PMA2
45
RB4/KBI0/PMA1
RB4
KBI0
PMA1
44
RB5/KBI1/PMA0
RB5
KBI1
PMA0
43
RB6/KBI2/PGC
RB6
KBI2
PGC
42
RB7/KBI3/PGD
RB7
KBI3
PGD
37
I/O
I
I
TTL
ST
ST
Digital I/O.
ECCP1/2/3 Fault input.
External interrupt 0.
I/O
I
O
TTL
ST
—
Digital I/O.
External interrupt 1.
Parallel Master Port address.
I/O
I
O
TTL
ST
—
Digital I/O.
External interrupt 2.
Parallel Master Port address.
I/O
I
O
TTL
ST
—
Digital I/O.
External interrupt 3.
Parallel Master Port address.
I/O
I
I/O
TTL
TTL
—
Digital I/O.
Interrupt-on-change pin.
Parallel Master Port address.
I/O
I
I/O
TTL
TTL
—
Digital I/O.
Interrupt-on-change pin.
Parallel Master Port address.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39775C-page 16
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 1-3:
PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
64-TQFP
Pin
Type
Buffer
Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
30
RC1/T1OSI/ECCP2/P2A
RC1
T1OSI
ECCP2(1)
P2A(1)
29
RC2/ECCP1/P1A
RC2
ECCP1
P1A
33
RC3/SCK1/SCL1
RC3
SCK1
SCL1
34
RC4/SDI1/SDA1
RC4
SDI1
SDA1
35
RC5/SDO1/C2OUT
RC5
SDO1
C2OUT
36
RC6/TX1/CK1
RC6
TX1
CK1
31
RC7/RX1/DT1
RC7
RX1
DT1
32
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
I/O
I
I/O
O
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM output A.
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
ECCP1 PWM output A.
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
O
ST
—
TTL
Digital I/O.
SPI data out.
Comparator 2 output.
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39775C-page 17
PIC18F87J50 FAMILY
TABLE 1-3:
PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
64-TQFP
Pin
Type
Buffer
Type
Description
PORTD is a bidirectional I/O port.
RD0/PMD0
RD0
PMD0
58
RD1/PMD1
RD1
PMD1
55
RD2/PMD2
RD2
PMD2
54
RD3/PMD3
RD3
PMD3
53
RD4/PMD4/SDO2
RD4
PMD4
SDO2
52
RD5/PMD5/SDI2/SDA2
RD5
PMD5
SDI2
SDA2
51
RD6/PMD6/SCK2/SCL2
RD6
PMD6
SCK2
SCL2
50
RD7/PMD7/SS2
RD7
PMD7
SS2
49
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Master Port data.
SPI data out.
I/O
I/O
I
I/O
ST
TTL
ST
ST
Digital I/O.
Parallel Master Port data.
SPI data in.
I2C™ data I/O.
I/O
I/O
I/O
I/O
ST
TTL
ST
ST
Digital I/O.
Parallel Master Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
Parallel Master Port data.
SPI slave select input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39775C-page 18
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 1-3:
PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
64-TQFP
Pin
Type
Buffer
Type
Description
PORTE is a bidirectional I/O port.
RE0/PMRD/P2D
RE0
PMRD
P2D
2
RE1/PMWR/P2C
RE1
PMWR
P2C
1
RE2/PMBE/P2B
RE2
PMBE
P2B
64
RE3/PMA13/P3C/REFO
RE3
PMA13
P3C
REFO
63
RE4/PMA12/P3B
RE4
PMA12
P3B
62
RE5/PMA11/P1C
RE5
PMA11
P1C
61
RE6/PMA10/P1B
RE6
PMA10
P1B
60
RE7/PMA9/ECCP2/P2A
RE7
PMA9
ECCP2(2)
P2A(2)
59
I/O
I/O
O
ST
—
—
Digital I/O.
Parallel Master Port read strobe.
ECCP2 PWM output D.
I/O
I/O
O
ST
—
—
Digital I/O.
Parallel Master Port write strobe.
ECCP2 PWM output C.
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port byte enable
ECCP2 PWM output B.
I/O
O
O
O
ST
—
—
—
Digital I/O.
Parallel Master Port address.
ECCP3 PWM output C.
Reference clock out.
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port address.
ECCP3 PWM output B.
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port address.
ECCP1 PWM output C.
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port address.
ECCP1 PWM output B.
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port address.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM output A.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39775C-page 19
PIC18F87J50 FAMILY
TABLE 1-3:
PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
64-TQFP
Pin
Type
Buffer
Type
Description
PORTF is a bidirectional I/O port.
RF2/PMA5/AN7/C2INB
RF2
PMA5
AN7
C2INB
16
RF3/DRF3
D-
15
RF4/D+
RF4
D+
14
RF5/AN10/C1INB/CVREF
RF5
AN10
C1INB
CVREF
13
RF6/AN11/C1INA
RF6
AN11
C1INA
12
RF7/SS1/C1OUT
RF7
SS1
C1OUT
11
I/O
O
I
I
ST
—
Analog
Analog
Digital I/O.
Parallel Master Port address.
Analog input 7.
Comparator 2 input B.
I
I/O
ST
—
Digital input.
USB differential minus line (input/output).
I
I/O
ST
—
Digital input.
USB differential plus line (input/output).
I
I
I
O
ST
Analog
Analog
Analog
Digital input.
Analog input 10.
Comparator 1 input B.
Comparator reference voltage output.
I/O
I
I
ST
Analog
Analog
Digital I/O.
Analog input 11.
Comparator 1 input A.
I/O
I
O
ST
TTL
TTL
Digital I/O.
SPI slave select input.
Comparator 1 output.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39775C-page 20
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 1-3:
PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
64-TQFP
Pin
Type
Buffer
Type
Description
PORTG is a bidirectional I/O port.
RG0/PMA8/ECCP3/P3A
RG0
PMA8
ECCP3
P3A
3
RG1/PMA7/TX2/CK2
RG1
PMA7
TX2
CK2
4
RG2/PMA6/RX2/DT2
RG2
PMA6
RX2
DT2
5
RG3/PMCS1/CCP4/P3D
RG3
PMCS1
CCP4
P3D
6
RG4/PMCS2/CCP5/P1D
RG4
PMCS2
CCP5
P1D
8
VSS
9, 25, 41, 56
I/O
O
I/O
O
ST
—
—
—
Digital I/O.
Parallel Master Port address.
Capture 3 input/Compare 3 output/PWM3 output.
ECCP3 PWM output A.
I/O
O
O
I/O
ST
—
—
ST
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
I/O
O
I
I/O
ST
—
ST
ST
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port chip select 1.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM output D.
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port chip select 2.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM output D.
P
—
Ground reference for logic and I/O pins.
VDD
26, 38, 57
P
—
Positive supply for peripheral digital logic and I/O pins.
AVSS
20
P
—
Ground reference for analog modules.
AVDD
19
P
—
Positive supply for analog modules.
ENVREG
18
I
ST
Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
10
P
—
P
—
P
—
VCAP
VUSB
17
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator
enabled).
USB voltage input pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39775C-page 21
PIC18F87J50 FAMILY
TABLE 1-4:
PIC18F8XJ5X PINOUT I/O DESCRIPTIONS
Pin Number
80-TQFP
Pin
Type
Buffer
Type
MCLR
9
I
ST
OSC1/CLKI/RA7
OSC1
49
Pin Name
I
I
CLKI
RA7(8)
OSC2/CLKO/RA6
OSC2
I/O
Description
Master Clear (Reset) input. This pin is an active-low Reset
to the device.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS
otherwise.
CMOS Main oscillator input connection.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
TTL Main clock input connection.
General purpose I/O pin.
ST
50
O
—
CLKO
O
—
RA6(8)
I/O
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
Main oscillator feedback output connection.
In RC mode, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
System cycle clock output (FOSC/4).
General purpose I/O pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39775C-page 22
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 1-4:
PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
80-TQFP
Pin
Type
Buffer
Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
30
RA1/AN1
RA1
AN1
29
RA2/AN2/VREFRA2
AN2
VREF-
28
RA3/AN3/VREF+
RA3
AN3
VREF+
27
RA4/PMD5/T0CKI
RA4
PMD5(7)
T0CKI
34
RA5/PMD4/AN4/C2INA
RA5
PMD4(7)
AN4
C2INA
33
RA6
RA7
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
I/O
I/O
I
ST
TTL
ST
I/O
I/O
I
I
TTL
TTL
Analog
Analog
—
—
—
See the OSC2/CLKO/RA6 pin.
—
—
—
See the OSC1/CLKI/RA7 pin.
Digital I/O.
Parallel Master Port data.
Timer0 external clock input.
Digital I/O.
Parallel Master Port data.
Analog input 4.
Comparator 2 input A.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39775C-page 23
PIC18F87J50 FAMILY
TABLE 1-4:
PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
80-TQFP
Pin
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/FLT0/INT0
RB0
FLT0
INT0
58
RB1/INT1/PMA4
RB1
INT1
PMA4
57
RB2/INT2/PMA3
RB2
INT2
PMA3
56
RB3/INT3/ECCP2/
P2A/PMA2
RB3
INT3
ECCP2(1)
P2A(1)
PMA2
55
RB4/KBI0/PMA1
RB4
KBI0
PMA1
54
RB5/KBI1/PMA0
RB5
KBI1
PMA0
53
RB6/KBI2/PGC
RB6
KBI2
PGC
52
RB7/KBI3/PGD
RB7
KBI3
PGD
47
I/O
I
I
TTL
ST
ST
Digital I/O.
ECCP1/2/3 Fault input.
External interrupt 0.
I/O
I
O
TTL
ST
—
Digital I/O.
External interrupt 1.
Parallel Master Port address.
I/O
I
O
TTL
ST
—
Digital I/O.
External interrupt 2.
Parallel Master Port address.
I/O
I
I/O
O
O
TTL
ST
ST
—
—
Digital I/O.
External interrupt 3.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM output A.
Parallel Master Port address.
I/O
I
I/O
TTL
TTL
—
Digital I/O.
Interrupt-on-change pin.
Parallel Master Port address.
I/O
I
I/O
TTL
TTL
—
Digital I/O.
Interrupt-on-change pin.
Parallel Master Port address.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39775C-page 24
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 1-4:
PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
80-TQFP
Pin
Type
Buffer
Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
36
RC1/T1OSI/ECCP2/P2A
RC1
T1OSI
ECCP2(2)
P2A(2)
35
RC2/ECCP1/P1A
RC2
ECCP1
P1A
43
RC3/SCK1/SCL1
RC3
SCK1
SCL1
44
RC4/SDI1/SDA1
RC4
SDI1
SDA1
45
RC5/SDO1/C2OUT
RC5
SDO1
C2OUT
46
RC6/TX1/CK1
RC6
TX1
CK1
37
RC7/RX1/DT1
RC7
RX1
DT1
38
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
I/O
I
I/O
O
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM output A.
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
ECCP1 PWM output A.
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
O
ST
—
TTL
Digital I/O.
SPI data out.
Comparator 2 output.
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39775C-page 25
PIC18F87J50 FAMILY
TABLE 1-4:
Pin Name
PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
80-TQFP
Pin
Type
Buffer
Type
Description
PORTD is a bidirectional I/O port.
RD0/AD0/PMD0
RD0
AD0
PMD0(6)
72
RD1/AD1/PMD1
RD1
AD1
PMD1(6)
69
RD2/AD2/PMD2
RD2
AD2
PMD2(6)
68
RD3/AD3/PMD3
RD3
AD3
PMD3(6)
67
RD4/AD4/PMD4/
SDO2
RD4
AD4
PMD4(6)
SDO2
66
RD5/AD5/PMD5/
SDI2/SDA2
RD5
AD5
PMD5(6)
SDI2
SDA2
65
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 0.
Parallel Master Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 1.
Parallel Master Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 2.
Parallel Master Port data.
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 3.
Parallel Master Port data.
I/O
I/O
I/O
O
ST
TTL
TTL
—
Digital I/O.
External memory address/data 4.
Parallel Master Port data.
SPI data out.
I/O
I/O
I/O
I
I/O
ST
TTL
TTL
ST
ST
Digital I/O.
External memory address/data 5.
Parallel Master Port data.
SPI data in.
I2C™ data I/O.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39775C-page 26
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 1-4:
PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
80-TQFP
Pin
Type
Buffer
Type
Description
PORTD is a bidirectional I/O port (continued).
RD6/AD6/PMD6/
SCK2/SCL2
RD6
AD6
PMD6(6)
SCK2
SCL2
64
RD7/AD7/PMD7/SS2
RD7
AD7
PMD7(6)
SS2
63
I/O
I/O
I/O
I/O
I/O
ST
TTL
TTL
ST
ST
Digital I/O.
External memory address/data 6.
Parallel Master Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
I/O
I/O
I/O
I
ST
TTL
TTL
TTL
Digital I/O.
External memory address/data 7.
Parallel Master Port data.
SPI slave select input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39775C-page 27
PIC18F87J50 FAMILY
TABLE 1-4:
PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
80-TQFP
Pin
Type
Buffer
Type
Description
PORTE is a bidirectional I/O port.
RE0/AD8/PMRD/P2D
RE0
AD8
PMRD(6)
P2D
4
RE1/AD9/PMWR/P2C
RE1
AD9
PMWR(6)
P2C
3
RE2/AD10/PMBE/P2B
RE2
AD10
PMBE(6)
P2B
78
RE3/AD11/PMA13/
P3C/REFO
RE3
AD11
PMA13
P3C(3)
REFO
77
RE4/AD12/PMA12/P3B
RE4
AD12
PMA12
P3B(3)
76
RE5/AD13/PMA11/P1C
RE5
AD13
PMA11
P1C(3)
75
I/O
I/O
I/O
O
ST
TTL
—
—
Digital I/O.
External memory address/data 8.
Parallel Master Port read strobe.
ECCP2 PWM output D.
I/O
I/O
I/O
O
ST
TTL
—
—
Digital I/O.
External memory address/data 9.
Parallel Master Port write strobe.
ECCP2 PWM output C.
I/O
I/O
O
O
ST
TTL
—
—
Digital I/O.
External memory address/data 10.
Parallel Master Port byte enable.
ECCP2 PWM output B.
I/O
I/O
O
O
O
ST
TTL
—
—
—
Digital I/O.
External memory address/data 11.
Parallel Master Port address.
ECCP3 PWM output C.
Reference Clock out.
I/O
I/O
O
O
ST
TTL
—
—
Digital I/O.
External memory address/data 12.
Parallel Master Port address.
ECCP3 PWM output B.
I/O
I/O
O
O
ST
TTL
—
—
Digital I/O.
External memory address/data 13.
Parallel Master Port address.
ECCP1 PWM output C.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39775C-page 28
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 1-4:
PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
80-TQFP
Pin
Type
Buffer
Type
Description
PORTE is a bidirectional I/O port (continued).
RE6/AD14/PMA10/P1B
RE6
AD14
PMA10
P1B(3)
74
RE7/AD15/PMA9/
ECCP2/P2A
RE7
AD15
PMA9
ECCP2(4)
P2A(4)
73
I/O
I/O
O
O
ST
TTL
—
—
Digital I/O.
External memory address/data 14.
Parallel Master Port address.
ECCP1 PWM output B.
I/O
I/O
O
I/O
O
ST
TTL
—
ST
—
Digital I/O.
External memory address/data 15.
Parallel Master Port address.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM output A.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39775C-page 29
PIC18F87J50 FAMILY
TABLE 1-4:
PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
80-TQFP
Pin
Type
Buffer
Type
Description
PORTF is a bidirectional I/O port.
RF2/PMA5/AN7/C2INB
RF2
PMA5
AN7
C2INB
18
RF3/DRF3
D-
17
RF4/D+
RF4
D+
16
RF5/PMD2/AN10/
C1INB/CVREF
RF5
PMD2(7)
AN10
C1INB
CVREF
15
RF6/PMD1/AN11/C1INA
RF6
PMD1(7)
AN11
C1INA
14
RF7/PMD0/SS1/C1OUT
RF7
PMD0(7)
SS1
C1OUT
13
I/O
O
I
I
ST
—
Analog
Analog
Digital I/O.
Parallel Master Port address.
Analog input 7.
Comparator 2 input B.
I/O
I/O
ST
—
Digital I/O.
Analog input 8.
I/O
I/O
ST
—
Digital I/O.
Analog input 9.
I/O
I/O
I
I
O
ST
TTL
Analog
Analog
Analog
Digital I/O.
Parallel Master Port address.
Analog input 10.
Comparator 1 input B.
Comparator reference voltage output.
I/O
I/O
I
I
ST
TTL
Analog
Analog
Digital I/O.
Parallel Master Port address.
Analog input 11.
Comparator 1 input A.
I/O
I/O
I
O
ST
TTL
TTL
—
Digital I/O.
Parallel Master Port address.
SPI slave select input.
Comparator 1 output.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39775C-page 30
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 1-4:
PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
80-TQFP
Pin
Type
Buffer
Type
Description
PORTG is a bidirectional I/O port.
RG0/PMA8/ECCP3/P3A
RG0
PMA8
ECCP3
P3A
5
RG1/PMA7/TX2/CK2
RG1
PMA7
TX2
CK2
6
RG2/PMA6/RX2/DT2
RG2
PMA6
RX2
DT2
7
RG3/PMCS1/CCP4/P3D
RG3
PMCS1
CCP4
P3D
8
RG4/PMCS2/CCP5/P1D
RG4
PMCS2
CCP5
P1D
10
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port address.
Capture 3 input/Compare 3 output/PWM3 output.
ECCP3 PWM output A.
I/O
O
O
I/O
ST
—
—
ST
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
I/O
I/O
I
I/O
ST
—
ST
ST
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
I/O
I/O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port chip select 1.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM output D.
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port chip select 2.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM output D.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39775C-page 31
PIC18F87J50 FAMILY
TABLE 1-4:
PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
80-TQFP
Pin
Type
Buffer
Type
Description
PORTH is a bidirectional I/O port.
RH0/A16
RH0
A16
79
RH1/A17
RH1
A17
80
RH2/A18/PMD7
RH2
A18
PMD7(7)
1
RH3/A19/PMD6
RH3
A19
PMD6(7)
2
RH4/PMD3/AN12/
P3C/C2INC
RH4
PMD3(7)
AN12
P3C(5)
C2INC
22
RH5/PMBE/AN13/
P3B/C2IND
RH5
PMBE(7)
AN13
P3B(5)
C2IND
21
RH6/PMRD/AN14/
P1C/C1INC
RH6
PMRD(7)
AN14
P1C(5)
C1INC
20
I/O
O
ST
TTL
Digital I/O.
External memory address/data 16.
I/O
O
ST
TTL
Digital I/O.
External memory address/data 17.
I/O
O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 18.
Parallel Master Port data.
I/O
O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 19.
Parallel Master Port data.
I/O
I/O
I
O
I
ST
TTL
Analog
—
Analog
Digital I/O.
Parallel Master Port address.
Analog input 12.
ECCP3 PWM output C.
Comparator 2 input C.
I/O
O
I
O
I
ST
—
Analog
—
Analog
Digital I/O.
Parallel Master Port byte enable.
Analog input 13.
ECCP3 PWM output B.
Comparator 2 input D.
I/O
I/O
I
O
I
ST
—
Analog
—
Analog
Digital I/O.
Parallel Master Port read strobe.
Analog input 14.
ECCP1 PWM output C.
Comparator 1 input C.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39775C-page 32
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 1-4:
PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
80-TQFP
Pin
Type
Buffer
Type
Description
PORTH is a bidirectional I/O port (continued).
RH7/PMWR/AN15/P1B
RH7
PMWR(7)
AN15
P1B(5)
19
I/O
I/O
I
O
ST
—
Analog
—
Digital I/O.
Parallel Master Port write strobe.
Analog input 15.
ECCP1 PWM output B.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
© 2009 Microchip Technology Inc.
DS39775C-page 33
PIC18F87J50 FAMILY
TABLE 1-4:
Pin Name
PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
80-TQFP
Pin
Type
Buffer
Type
Description
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
ALE
62
RJ1/OE
RJ1
OE
61
RJ2/WRL
RJ2
WRL
60
RJ3/WRH
RJ3
WRH
59
RJ4/BA0
RJ4
BA0
39
RJ5/CE
RJ5
CE
40
RJ6/LB
RJ6
LB
41
RJ7/UB
RJ7
UB
42
VSS
11, 31, 51, 70
I/O
O
ST
—
Digital I/O.
External memory address latch enable.
I/O
O
ST
—
Digital I/O.
External memory output enable.
I/O
O
ST
—
Digital I/O.
External memory write low control.
I/O
O
ST
—
Digital I/O.
External memory write high control.
I/O
O
ST
—
Digital I/O.
External memory byte address 0 control.
I/O
O
ST
—
Digital I/O
External memory chip enable control.
I/O
O
ST
—
Digital I/O.
External memory low byte control.
I/O
O
ST
—
Digital I/O.
External memory high byte control.
P
—
Ground reference for logic and I/O pins.
VDD
32, 48, 71
P
—
Positive supply for peripheral digital logic and I/O pins.
AVSS
26
P
—
Ground reference for analog modules.
AVDD
25
P
—
Positive supply for analog modules.
ENVREG
24
I
ST
Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
12
P
—
VCAP
VUSB
23
P
—
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
P
—
USB voltage input pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
DS39775C-page 34
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
2.0
2.1
OSCILLATOR
CONFIGURATIONS
Overview
Devices in the PIC18F87J10 family incorporate a
different oscillator and microcontroller clock system
than general purpose PIC18F devices. The addition of
the USB module, with its unique requirements for a
stable clock source, make it necessary to provide a
separate clock source that is compliant with both USB
low-speed and full-speed specifications.
The PIC18F87J50 family has additional prescalers and
postscalers which have been added to accommodate a
wide range of oscillator frequencies. An overview of the
oscillator structure is shown in Figure 2-1.
Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal oscillator block
and clock switching, remain the same. They are
discussed later in this chapter.
2.1.1
OSCILLATOR CONTROL
The operation of the oscillator in PIC18F87J10 family
devices is controlled through three Configuration registers and two control registers. Configuration registers,
CONFIG1L, CONFIG1H and CONFIG2L, select the
oscillator mode, PLL prescaler and CPU divider options.
As Configuration bits, these are set when the device is
programmed and left in that configuration until the
device is reprogrammed.
The OSCCON register (Register 2-2) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use is
discussed in Section 2.4.1 “Oscillator Control
Register”.
The OSCTUNE register (Register 2-1) is used to trim
the INTOSC frequency source, as well as select the
low-frequency clock source that drives several special
features. The OSCTUNE register is also used to
activate or disable the PLL. Its use is described in
Section 2.2.5.1 “OSCTUNE Register”.
2.2
TABLE 2-1:
Mode
OSCILLATOR MODES
Description
ECPLL
External Clock Input mode, the PLL can
be enabled or disabled, CLKO on RA6,
apply external clock signal to RA7
EC
External Clock Input mode, the PLL is
always disabled, CLKO on RA6, apply
external clock signal to RA7
HSPLL
HS
High-Speed Crystal/Resonator mode,
PLL can be enabled or disabled, crystal/
resonator connected between RA6 and
RA7
High-Speed Crystal/Resonator mode,
PLL always disabled, crystal/resonator
connected between RA6 and RA7
INTOSCPLLO Internal Oscillator mode, PLL can be
enabled or disabled, CLKO on RA6, port
function on RA7, the internal oscillator
block is used to derive both the primary
clock source and the postscaled internal
clock
INTOSCPLL
Internal Oscillator mode, PLL can be
enabled or disabled, port function on
RA6 and RA7, the internal oscillator
block is used to derive both the primary
clock source and the postscaled internal
clock
INTOSCO
Internal Oscillator mode, PLL is always
disabled, CLKO on RA6, port function on
RA7, the output of the INTOSC
postscaler serves as both the postscaled
internal clock and the primary clock
source
INTOSC
Internal Oscillator mode, PLL is always
disabled, port function on RA6 and RA7,
the output of the INTOSC postscaler
serves as both the postscaled internal
clock and the primary clock source
Oscillator Types
PIC18F87J10 family devices can be operated in eight
distinct oscillator modes. Users can program the
FOSC2:FOSC0 Configuration bits to select one of the
modes listed in Table 2-1. For oscillator modes which
produce a clock output, “CLKO”, on pin RA6, the output
frequency will be one fourth of the peripheral clock
frequency. The clock output will stop when in Sleep
mode, but will continue during Idle mode (see
Figure 2-1).
© 2009 Microchip Technology Inc.
DS39775C-page 35
PIC18F87J50 FAMILY
2.2.1
OSCILLATOR MODES AND
USB OPERATION
A network of MUXes, clock dividers and a fixed 96 MHz
output PLL have been provided which can be used to
derive various microcontroller core and USB module
frequencies. The oscillator structure of the
PIC18F87J50 family of devices is best understood by
referring to Figure 2-1.
Because of the unique requirements of the USB module,
a different approach to clock operation is necessary. In
order to use the USB module, a fixed 6 MHz or 48 MHz
clock must be internally provided to the USB module for
operation in either Low-Speed or Full-Speed mode,
respectively. The microcontroller core need not be
clocked at the same frequency as the USB module.
FIGURE 2-1:
PIC18F87J50 FAMILY CLOCK DIAGRAM
PLLDIV2:PLLDIV0
PLL Prescaler
Primary Oscillator
OSC2
÷ 12
÷ 10
÷6
÷5
÷4
÷3
÷2
÷1
000
001
010
011
100
101
110
111
4 MHz 96 MHz
PLL(1)
÷2
48 MHz
FSEN
FOSC2
OSC1
1
1
1
0
0
(Note 2)
÷8
÷3
÷2
÷1
÷4
00
11
CPDIV1:CPDIV0
01
10
11
FOSC2:FOSC1
Other
CPU Divider
÷6
Needs 48 MHz for FS
Needs 6 MHz for LS
10
0
CPDIV1:CPDIV0
PLLEN
USB Module
Clock
Primary Clock
Source(4)
IDLE
CPU
00
Secondary Oscillator
Timer1 Clock(3)
T1OSO
T1OSCEN
Postscaled
Internal Clock
T1OSI
00
Peripherals
01
RA6
11
÷4
OSCCON
OSCCON
8 MHz
8 MHz
INTRC
31 kHz
8 MHz
INTOSC Postscaler
4 MHz
Internal
Oscillator
Block
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
111
110
101
100
011
010
001
1 31 kHz
000
0
OSCTUNE
Note 1:
2:
3:
4:
CLKO
Enabled Modes
WDT, PWRT, FSCM
and Two-Speed Start-up
The PLL requires a 4 MHz input and it produces a 96 MHz output. The PLL will not be available until the PLLEN bit
in the OSCTUNE register is set. Once the PLLEN bit is set, the PLL requires up to 2 ms to lock.
In order to use the USB module in Full-Speed mode, this node must be run at 48 MHz. For Low-Speed mode, this
node may be run at either 48 MHz or 24 MHz, but the CPDIV bits must be set such that the USB module is clocked
at 6 MHz.
Selecting the Timer1 clock or postscaled internal clock will turn off the primary oscillator (unless required by the
reference clock of Section 2.5 “Reference Clock Output”) and PLL.
The USB module cannot be used to communicate unless the primary clock source is selected.
DS39775C-page 36
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
2.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In HS and HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-2 shows
the pin connections.
The oscillator design requires the use of a parallel cut
crystal.
Note:
Use of a series cut crystal may give a frequency out of the crystal manufacturer’s
specifications.
FIGURE 2-2:
C1(1)
CRYSTAL/CERAMIC
RESONATOR OPERATION
(XT, HS OR HSPLL
CONFIGURATION)
OSC1
XTAL
RF(3)
PIC18F87J50
OSC2
Note 1: See Table 2-2 and Table 2-3 for initial values of
C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
TABLE 2-2:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Typical Capacitor Values Used:
Mode
Freq
OSC1
OSC2
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following Table 2-3 for additional
information.
Resonators Used:
4.0 MHz
8.0 MHz
Osc Type
HS
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Crystal
Freq
Typical Capacitor Values
Tested:
C1
C2
4 MHz
27 pF
27 pF
8 MHz
22 pF
22 pF
20 MHz
15 pF
15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information.
Crystals Used:
4 MHz
Sleep
RS(2)
C2(1)
To
Internal
Logic
TABLE 2-3:
8 MHz
20 MHz
Note 1: Higher capacitance increases the stability
of oscillator but also increases the
start-up time.
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
4: Rs may be required to avoid overdriving
crystals with low drive level specification.
5: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
An internal postscaler allows users to select a clock
frequency other than that of the crystal or resonator.
Frequency division is determined by the CPDIV
Configuration bits. Users may select a clock frequency
of the oscillator frequency, or 1/2, 1/3 or 1/6 of the
frequency.
An external clock may also be used when the microcontroller is in HS Oscillator mode. In this case, the
OSC2/CLKO pin is left open (Figure 2-3).
16.0 MHz
© 2009 Microchip Technology Inc.
DS39775C-page 37
PIC18F87J50 FAMILY
FIGURE 2-3:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
OSC1
Clock from
Ext. System
PIC18F87J50
Open
2.2.3
OSC2
(HS Mode)
EXTERNAL CLOCK INPUT
The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC and ECPLL Oscillator modes, the oscillator
frequency divided by 4 is available on the OSC2 pin.
This signal may be used for test purposes or to
synchronize other logic. Figure 2-4 shows the pin
connections for the EC Oscillator mode.
FIGURE 2-4:
OSC1/CLKI
Clock from
Ext. System
PIC18F87J50
FOSC/4
2.2.4
EXTERNAL CLOCK INPUT
OPERATION (EC AND
ECPLL CONFIGURATION)
OSC2/CLKO
PLL FREQUENCY MULTIPLIER
PIC18F87J10 family devices include a Phase Locked
Loop (PLL) circuit. This is provided specifically for USB
applications with lower speed oscillators and can also
be used as a microcontroller clock source.
There is also a CPU divider which can be used to derive
the microcontroller clock from the PLL. This allows the
USB peripheral and microcontroller to use the same
oscillator input and still operate at different clock speeds.
The CPU divider can reduce the incoming frequency by
a factor of 1, 2, 3 or 6.
2.2.5
INTERNAL OSCILLATOR BLOCK
The PIC18F87J10 family devices include an internal
oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock
source. The internal oscillator may eliminate the need
for external oscillator circuits on the OSC1 and/or
OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the device clock. It
also drives the INTOSC postscaler which can provide a
range of clock frequencies from 31 kHz to 8 MHz.
Additionally, the INTOSC may be used in conjunction
with the PLL to generate clock frequencies up to
48 MHz.
The other clock source is the internal RC oscillator
(INTRC) which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source. It is also enabled automatically when any of the
following are enabled:
•
•
•
•
Power-up Timer
Fail-Safe Clock Monitor
Watchdog Timer
Two-Speed Start-up
These features are discussed in greater detail in
Section 25.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 44).
The PLL can be enabled in HSPLL, ECPLL,
INTOSCPLL and INTOSCPLLO Oscillator modes by
setting the PLLEN bit (OSCTUNE). It is designed
to produce a fixed 96 MHz reference clock from a
fixed 4 MHz input. The output can then be divided and
used for both the USB and the microcontroller core
clock. Because the PLL has a fixed frequency input
and output, there are eight prescaling options to
match the oscillator input frequency to the PLL. This
prescaler allows the PLL to be used with crystals, resonators and external clocks, which are integer multiple
frequencies of 4 MHz. For example, a 12 MHz crystal
could be used in a prescaler divide by three mode to
drive the PLL.
DS39775C-page 38
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
2.2.5.1
OSCTUNE Register
The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s application. This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
frequency within 8 clock cycles (approximately,
8 * 32 μs = 256 μs). The INTOSC clock will stabilize
within 1 ms. Code execution continues during this shift.
There is no indication that the shift has occurred.
The OSCTUNE register also contains the INTSRC bit.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequency option is selected. This is covered in greater
detail in Section 2.4.1 “Oscillator Control Register”.
The PLLEN bit, contained in the OSCTUNE register,
can be used to enable or disable the internal 96 MHz
PLL when running in one of the PLL type oscillator
modes (e.g., INTOSCPLL). Oscillator modes that do
not contain “PLL” in their name cannot be used with
the PLL. In these modes, the PLL is always disabled
regardless of the setting of the PLLEN bit.
When configured for one of the PLL enabled modes,
setting the PLLEN bit does not immediately switch the
device clock to the PLL output. The PLL requires up to
two milliseconds to start up and lock during which time
the device continues to be clocked. Once the PLL output is ready, the microcontroller core will automatically
switch to the PLL derived frequency.
2.2.5.2
Internal Oscillator Output Frequency
and Drift
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
However, this frequency may drift as VDD or temperature changes, which can affect the controller operation
in a variety of ways.
The low-frequency INTRC oscillator operates independently of the INTOSC source. Any changes in INTOSC
across voltage and temperature are not necessarily
reflected by changes in INTRC and vice versa.
© 2009 Microchip Technology Inc.
2.2.5.3
Compensating for INTOSC Drift
It is possible to adjust the INTOSC frequency by
modifying the value in the OSCTUNE register. This has
no effect on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. When using the EUSART, for example, an
adjustment may be required when it begins to generate
framing errors or receives data with errors while in
Asynchronous mode. Framing errors indicate that the
device clock frequency is too high; to adjust for this,
decrement the value in OSCTUNE to reduce the clock
frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate,
increment OSCTUNE to increase the clock frequency.
It is also possible to verify device clock speed against
a reference clock. Two timers may be used: one timer
is clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator. Both timers are cleared but the timer
clocked by the reference generates interrupts. When
an interrupt occurs, the internally clocked timer is read
and both timers are cleared. If the internally clocked
timer value is greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
Finally, a CCP module can use free-running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the calculated time, the internal oscillator block is running too
fast; to compensate, decrement the OSCTUNE register.
If the measured time is much less than the calculated
time, the internal oscillator block is running too slow; to
compensate, increment the OSCTUNE register.
DS39775C-page 39
PIC18F87J50 FAMILY
REGISTER 2-1:
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTSRC
PLLEN
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator
bit 6
PLLEN: Frequency Multiplier Enable bit
1 = 96 MHz PLL is enabled
0 = 96 MHz PLL is disabled
bit 5-0
2.3
TUN5:TUN0: Frequency Tuning bits
011111 = Maximum frequency
011110
•
•
•
•
•
•
000001
000000 = Center frequency. Oscillator module is running at the calibrated frequency.
111111
•
•
•
•
100000 = Minimum frequency
Oscillator Settings for USB
When the PIC18F87J10 family is used for USB
connectivity, a 6 MHz or 48 MHz clock must be
provided to the USB module for operation in either
Low-Speed or Full-Speed modes, respectively. This
may require some forethought in selecting an oscillator
frequency and programming the device.
way the clock dividers have been implemented in the
PIC18F87J50 family, the microcontroller core must run
at 24 MHz in order for the USB module to get the 6 MHz
clock needed for low-speed USB operation. Several
clocking schemes could be used to meet these two
required conditions. See Table 2-4 and Table 2-5 for
possible combinations which can be used for
low-speed USB operation.
The full range of possible oscillator configurations
compatible with USB operation is shown in Table 2-5.
TABLE 2-4:
2.3.1
LOW-SPEED OPERATION
The USB clock for Low-Speed mode is derived from the
primary oscillator or from the 96 MHz PLL. In order to
operate the USB module in Low-Speed mode, a 6 MHz
clock must be provided to the USB module. Due to the
DS39775C-page 40
CLOCK FOR LOW-SPEED
USB
Clock
Input
CPU
Clock
CPDIV
USB Clock
48
24
48/8 = 6 MHz
24
24
24/4 = 6 MHz
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 2-5:
OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION
Input Oscillator
Frequency
PLL Division
(PLLDIV2:PLLDIV0)
48 MHz
48 MHz
40 MHz
24 MHz
24 MHz
20 MHz
16 MHz
12 MHz
8 MHz
4 MHz
Legend:
Note 1:
N/A
÷12 (000)
÷10 (001)
÷6 (010)
N/A(1)
÷5 (011)
÷4 (100)
÷3 (101)
÷2 (110)
÷1 (111)
Clock Mode
(FOSC2:FOSC0)
EC
ECPLL
ECPLL
HSPLL, ECPLL
EC, HS
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
MCU Clock Division
(CPDIV1:CPDIV0)
Microcontroller
Clock Frequency
None (11)
48 MHz
÷2 (10)
24 MHz
÷3 (01)
16 MHz
÷6 (00)
8 MHz
None (11)
48 MHz
÷2 (10)
24 MHz
÷3 (01)
16 MHz
÷6 (00)
8 MHz
None (11)
48 MHz
÷2 (10)
24 MHz
÷3 (01)
16 MHz
÷6 (00)
8 MHz
None (11)
48 MHz
÷2 (10)
24 MHz
÷3 (01)
16 MHz
÷6 (00)
8 MHz
None (11)
24 MHz
÷2 (10)
12 MHz
÷3 (01)
8 MHz
÷6 (00)
4 MHz
None (11)
48 MHz
÷2 (10)
24 MHz
÷3 (01)
16 MHz
÷6 (00)
8 MHz
None (11)
48 MHz
÷2 (10)
24 MHz
÷3 (01)
16 MHz
÷6 (00)
8 MHz
None (11)
48 MHz
÷2 (10)
24 MHz
÷3 (01)
16 MHz
÷6 (00)
8 MHz
None (11)
48 MHz
÷2 (10)
24 MHz
÷3 (01)
16 MHz
÷6 (00)
8 MHz
None (11)
48 MHz
÷2 (10)
24 MHz
÷3 (01)
16 MHz
÷6 (00)
8 MHz
All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz).
Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,
USB clock of 6 MHz).
Only valid for low-speed USB operation.
© 2009 Microchip Technology Inc.
DS39775C-page 41
PIC18F87J50 FAMILY
2.4
Clock Sources and Oscillator
Switching
Like previous PIC18 enhanced devices, the
PIC18F87J10 family includes a feature that allows the
device clock source to be switched from the main
oscillator to an alternate, low-frequency clock source.
PIC18F87J10 family devices offer two alternate clock
sources. When an alternate clock source is enabled,
the various power-managed operating modes are
available.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary oscillators
• Internal oscillator block
The primary clock sources include the External
Crystal and Resonator modes, the External Clock
modes and the internal oscillator block. The particular
mode is defined by the FOSC2:FOSC0 Configuration
bits. The details of these modes are covered earlier in
this chapter.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.
PIC18F87J10 family devices offer the Timer1 oscillator
as a secondary oscillator. This oscillator, in all
power-managed modes, is often the time base for
functions such as a Real-Time Clock (RTC). Most
often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/T13CKI and RC1/T1OSI/
ECCP2/P2A pins. Like the HS Oscillator mode circuits,
loading capacitors are also connected from each pin to
ground. The Timer1 oscillator is discussed in greater
detail in Section 13.3 “Timer1 Oscillator”.
In addition to being a primary clock source, the
postscaled internal clock is available as a
power-managed mode clock source. The INTRC
source is also used as the clock source for several
special features, such as the WDT and Fail-Safe Clock
Monitor.
2.4.1
OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in
full-power operation and in power-managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC2:FOSC0 Configuration bits), the secondary clock (Timer1 oscillator) and
the postscaled internal clock.The clock source changes
immediately, after one or more of the bits is written to,
following a brief clock transition interval. The SCS bits
are cleared on all forms of Reset.
The Internal Oscillator Frequency Select bits,
IRCF2:IRCF0, select the frequency output provided on
the postscaled internal clock line. The choices are the
INTRC source, the INTOSC source (8 MHz) or one of
the frequencies derived from the INTOSC postscaler
(31 kHz to 4 MHz). If the postscaled internal clock is
supplying the device clock, changing the states of these
bits will have an immediate change on the internal oscillator’s output. On device Resets, the default output
frequency of the INTOSC postscaler is set at 4 MHz.
When an output frequency of 31 kHz is selected
(IRCF2:IRCF0 = 000), users may choose which internal oscillator acts as the source. This is done with the
INTSRC bit in the OSCTUNE register (OSCTUNE).
Setting this bit selects INTOSC as a 31.25 kHz clock
source by enabling the divide-by-256 output of the
INTOSC postscaler. Clearing INTSRC selects INTRC
(nominally 31 kHz) as the clock source.
This option allows users to select the tunable and more
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Regardless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the Watchdog Timer
and the Fail-Safe Clock Monitor.
The OSTS and T1RUN bits indicate which clock source
is currently providing the device clock. The OSTS bit
indicates that the Oscillator Start-up Timer (OST) has
timed out and the primary clock is providing the device
clock in primary clock modes. The T1RUN bit
(T1CON) indicates when the Timer1 oscillator is
providing the device clock in secondary clock modes. In
power-managed modes, only one of these bits will be set
at any time. If none of these bits are set, the INTRC is
providing the clock or the internal oscillator block has just
started and is not yet stable.
The IDLEN bit determines if the device goes into Sleep
mode, or one of the Idle modes, when the SLEEP
instruction is executed.
DS39775C-page 42
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the Timer1 clock. The Timer1 oscillator is enabled by setting the T1OSCEN
bit in the Timer1 Control register
(T1CON). If the Timer1 oscillator is not
enabled, then any attempt to select the
Timer1 clock source will be ignored.
2: It is recommended that the Timer1
oscillator be operating and stable prior to
switching to it as the clock source; otherwise, a very long delay may occur while
the Timer1 oscillator starts.
© 2009 Microchip Technology Inc.
2.4.2
OSCILLATOR TRANSITIONS
PIC18F87J10 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
DS39775C-page 43
PIC18F87J50 FAMILY
REGISTER 2-2:
OSCCON: OSCILLATOR CONTROL REGISTER(1)
R/W-0
R/W-1
R/W-1
R/W-0
R-1(2)
U-1
R/W-0
R/W-0
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
—
SCS1
SCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IDLEN: Idle Enable bit
1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction
bit 6-4
IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz(3)
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC directly)(4)
bit 3
OSTS: Oscillator Start-up Time-out Status bit(2)
1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2
Unimplemented: Read as ‘1’
bit 1-0
SCS1:SCS0: System Clock Select bits
11 = Postscaled internal clock (INTRC/INTOSC derived)
10 = Reserved
01 = Timer1 oscillator
00 = Primary clock source (INTOSC postscaler output when FOSC2:FOSC0 = 001 or 000)
00 = Primary clock source (CPU divider output for other values of FOSC2:FOSC0)
Note 1:
2:
3:
4:
Default (legacy) SFR at this address, available when WDTCON = 0.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
Default output frequency of INTOSC on Reset (4 MHz).
Source selected by the INTSRC bit (OSCTUNE), see text.
DS39775C-page 44
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
2.5
Reference Clock Output
OSC1 and OSC2, or the current system clock source,
is used for the reference clock output. The ROSSLP bit
determines if the reference source is available on RE3
when the device is in Sleep mode.
In addition to the peripheral clock/4 output in certain
oscillator modes, the device clock in the PIC18F87J10
family can also be configured to provide a reference
clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user
to select a greater range of clock submultiples to drive
external devices in the application.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for an EC or HS mode;
otherwise, the oscillator on OSC1 and OSC2 will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
This reference clock output is controlled by the
REFOCON register (Register 2-3). Setting the ROON
bit (REFOCON) makes the clock signal available
on the REFO (RE3) pin. The RODIV3:RODIV0 bits
enable the selection of 16 different clock divider
options.
The REFOCON register is an alternate SFR and
shares the same memory address as the OSCCON
register. It is accessed by setting the ADSHR bit
(WDTCON) in the WDTCON register (see
Register 25-9).
The ROSSLP and ROSEL bits (REFOCON) control the availability of the reference output during Sleep
mode. The ROSEL bit determines if the oscillator on
REGISTER 2-3:
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ROON
—
ROSSLP
ROSEL
RODIV3
RODIV2
RODIV1
RODIV0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ROON: Reference Oscillator Output Enable bit
1 = Reference oscillator enabled on REFO pin
0 = Reference oscillator disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
ROSSLP: Reference Oscillator Output Stop in Sleep bit
1 = Reference oscillator continues to run in Sleep
0 = Reference oscillator is disabled in Sleep
bit 4
ROSEL: Reference Oscillator Source Select bit
1 = Primary oscillator used as the base clock. Note that the crystal oscillator must be enabled using
the FOSC2:FOSC0 bits; crystal maintains the operation in Sleep mode.
0 = System clock used as the base clock; base clock reflects any clock switching of the device
bit 3-0
RODIV3:RODIV0: Reference Oscillator Divisor Select bits
1111 = Base clock value divided by 32,768
1110 = Base clock value divided by 16,384
1101 = Base clock value divided by 8,192
1100 = Base clock value divided by 4,096
1011 = Base clock value divided by 2,048
1010 = Base clock value divided by 1,024
1001 = Base clock value divided by 512
1000 = Base clock value divided by 256
0111 = Base clock value divided by 128
0110 = Base clock value divided by 64
0101 = Base clock value divided by 32
0100 = Base clock value divided by 16
0011 = Base clock value divided by 8
0010 = Base clock value divided by 4
0001 = Base clock value divided by 2
0000 = Base clock value
© 2009 Microchip Technology Inc.
DS39775C-page 45
PIC18F87J50 FAMILY
2.6
Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. Unless the USB
module is enabled, the OSC1 pin (and OSC2 pin if
used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support
various special features regardless of the
power-managed mode (see Section 25.2 “Watchdog
Timer (WDT)”, Section 25.4 “Two-Speed Start-up”
and Section 25.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up). The INTOSC output at 8 MHz
may be used directly to clock the device or may be
divided down by the postscaler. The INTOSC output is
disabled if the clock is provided directly from the INTRC
output.
If the Sleep mode is selected, all clock sources which
are no longer required are stopped. Since all the transistor switching currents have been stopped, Sleep
mode achieves the lowest current consumption of the
device (only leakage currents).
Sleep mode should not be invoked while the USB module is enabled and operating in full-power mode. Before
Sleep mode is selected, the USB module should be put
in the suspend state. This is accomplished by setting
the SUSPND bit in the UCON register.
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
Real-Time Clock. Other features may be operating that
do not require a device clock source (i.e., MSSP slave,
PMP, INTx pins and others). Peripherals that may add
significant current consumption are listed in
Section 28.2 “DC Characteristics: Power-Down and
Supply Current”.
2.7
Power-up Delays
Power-up delays are controlled by two timers so that no
external Reset circuitry is required for most applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal circumstances and the primary clock is operating and stable.
For additional information on power-up delays, see
Section 4.6 “Power-up Timer (PWRT)”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 28-13).
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS mode). The OST does
this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
There is a delay of interval, TCSD (parameter 38,
Table 28-13), following POR, while the controller
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be the
only delay that occurs when any of the EC or internal
oscillator modes are used as the primary clock source.
DS39775C-page 46
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
3.0
POWER-MANAGED MODES
3.1.1
The SCS1:SCS0 bits allow the selection of one of three
clock sources for power-managed modes. They are:
The PIC18F87J10 family devices provide the ability to
manage power consumption by simply managing clocking to the CPU and the peripherals. In general, a lower
clock frequency and a reduction in the number of circuits
being clocked constitutes lower consumed power. For
the sake of managing power in an application, there are
three primary modes of operation:
• The primary clock source, as defined by the
FOSC2:FOSC0 Configuration bits
• The Timer1 clock (provided by the secondary
oscillator)
• The postscaled internal clock (derived from the
internal oscillator block)
• Run mode
• Idle mode
• Sleep mode
3.1.2
These modes define which portions of the device are
clocked and at what speed. The Run and Idle modes
may use any of the three available clock sources
(primary, secondary or internal oscillator block); the
Sleep mode does not use a clock source.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Selecting Power-Managed Modes
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
Selecting a power-managed mode requires two
decisions: if the CPU is to be clocked or not and which
clock source is to be used. The IDLEN bit
(OSCCON) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON) select the clock
source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table 3-1.
TABLE 3-1:
POWER-MANAGED MODES
OSCCON
Mode
ENTERING POWER-MANAGED
MODES
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS1:SCS0 bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
The power-managed modes include several
power-saving features offered on previous PIC®
devices. One is the clock switching feature, offered in
other PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC devices,
where all device clocks are stopped.
3.1
CLOCK SOURCES
(1)
IDLEN
Module Clocking
Available Clock and Oscillator Source
SCS1:SCS0
CPU
Peripherals
0
N/A
Off
Off
PRI_RUN
N/A
00
Clocked
Clocked
Primary clock source (defined by FOSC2:FOSC0);
this is the normal full-power execution mode
SEC_RUN
N/A
01
Clocked
Clocked
Secondary – Timer1 oscillator
RC_RUN
N/A
11
Clocked
Clocked
Postscaled internal clock
PRI_IDLE
1
00
Off
Clocked
Primary clock source (defined by FOSC2:FOSC0)
SEC_IDLE
1
01
Off
Clocked
Secondary – Timer1 oscillator
RC_IDLE
1
11
Off
Clocked
Postscaled internal clock
Sleep
Note 1:
None – All clocks are disabled
IDLEN reflects its value when the SLEEP instruction is executed.
© 2009 Microchip Technology Inc.
DS39775C-page 47
PIC18F87J50 FAMILY
3.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Two bits indicate the current clock source and its
status:
OSTS
(OSCCON)
and
T1RUN
(T1CON). In general, only one of these bits will be
set while in a given power-managed mode. When the
OSTS bit is set, the primary clock is providing the
device clock. When the T1RUN bit is set, the Timer1
oscillator is providing the clock. If neither of these bits
is set, INTRC is clocking the device.
Note:
3.1.4
Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
DS39775C-page 48
3.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
3.2.1
PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 25.4 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set. (see
Section 2.4.1 “Oscillator Control Register”).
3.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high-accuracy clock source.
SEC_RUN mode is entered by setting the SCS1:SCS0
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 3-1), the primary oscillator is shut down, the T1RUN bit (T1CON) is set and
the OSTS bit is cleared.
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
Note:
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 3-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up; the Timer1
oscillator continues to run.
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started. In such situations, initial oscillator operation is far from
stable and unpredictable operation may
result.
FIGURE 3-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
1
T1OSI
2
3
n-1
Q3
Q4
Q1
Q2
Q3
n
Clock Transition
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
PC
FIGURE 3-2:
PC + 2
PC + 4
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
2
n-1 n
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
SCS1:SCS0 Bits Changed
PC + 2
PC
PC + 4
OSTS Bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
© 2009 Microchip Technology Inc.
DS39775C-page 49
PIC18F87J50 FAMILY
3.2.3
RC_RUN MODE
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
block while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 3-4). When the clock
switch is complete, the OSTS bit is set and the primary
clock is providing the device clock. The IDLEN and
SCS bits are not affected by the switch. The INTRC
block source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conservation of all the Run modes while still executing code.
It works well for user applications which are not highly
timing sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting the SCS1:SCS0 bits
(OSCCON) to ‘11’. When the clock source is
switched to the internal oscillator block (see
Figure 3-3), the primary oscillator is shut down and the
OSTS bit is cleared.
FIGURE 3-3:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
1
INTRC
2
3
n-1
Q3
Q4
Q1
Q2
Q3
n
Clock Transition
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
PC
FIGURE 3-4:
PC + 2
PC + 4
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q1
Q2
Q3
Q4
Q2 Q3 Q4 Q1 Q2 Q3
Q1
INTRC
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
2
n-1 n
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
SCS1:SCS0 Bits Changed
PC + 2
PC
PC + 4
OSTS Bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39775C-page 50
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
3.3
Sleep Mode
3.4
The power-managed Sleep mode is identical to the legacy Sleep mode offered in all other PIC devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 3-5). All
clock source status bits are cleared.
Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS1:SCS0 bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS1:SCS0 bits
becomes ready (see Figure 3-6), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
(see Section 25.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 28-13) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS1:SCS0 bits.
FIGURE 3-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
FIGURE 3-6:
PC + 2
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
OSC1
TOST(1)
PLL Clock
Output
TPLL(1)
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
PC + 2
PC + 4
PC + 6
OSTS Bit Set
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
© 2009 Microchip Technology Inc.
DS39775C-page 51
PIC18F87J50 FAMILY
3.4.1
PRI_IDLE MODE
3.4.2
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN
first, then set the SCS bits to ‘00’ and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC1:FOSC0 Configuration bits. The OSTS
bit remains set (see Figure 3-7).
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set IDLEN first, then
set SCS1:SCS0 to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscillator, the
primary oscillator is shut down, the OSTS bit is cleared
and the T1RUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-8).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code execution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 3-8).
FIGURE 3-7:
SEC_IDLE MODE
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q1
Q4
Q3
Q2
Q1
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
FIGURE 3-8:
PC
PC + 2
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Q2
Q3
Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
DS39775C-page 52
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
3.4.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the internal
oscillator block. This mode allows for controllable
power conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTOSC block, the primary
oscillator is shut down and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the internal oscillator block. After a
delay of TCSD following the wake event, the CPU
begins executing code being clocked by the INTRC.
The IDLEN and SCS bits are not affected by the
wake-up. The INTRC source will continue to run if
either the WDT or the Fail-Safe Clock Monitor is
enabled.
3.5
Exiting Idle and Sleep Modes
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes sections (see Section 3.2 “Run Modes”,
Section 3.3 “Sleep Mode” and Section 3.4 “Idle
Modes”).
3.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
3.5.2
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 3.2 “Run
Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 25.2 “Watchdog
Timer (WDT)”).
The Watchdog Timer and postscaler are cleared by one
of the following events:
• Executing a SLEEP or CLRWDT instruction
• The loss of a currently selected clock source (if
the Fail-Safe Clock Monitor is enabled)
3.5.3
EXIT BY RESET
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped; and
• the primary clock source is either the EC or
ECPLL mode.
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC). However, a
fixed delay of interval, TCSD, following the wake event
is still required when leaving Sleep and Idle modes to
allow the CPU to prepare for execution. Instruction
execution resumes on the first clock cycle following this
delay.
A fixed delay of interval, TCSD, following the wake event
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
© 2009 Microchip Technology Inc.
DS39775C-page 53
PIC18F87J50 FAMILY
NOTES:
DS39775C-page 54
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
4.0
RESET
The PIC18F87J10 family of devices differentiate
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
i)
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Configuration Mismatch (CM)
Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.6.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 25.2 “Watchdog
Timer (WDT)”.
FIGURE 4-1:
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
4.1
RCON Register
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 4.7 “Reset State of Registers”.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 9.0 “Interrupts”.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET Instruction
Configuration Word Mismatch
Stack
Pointer
Stack Full/Underflow Reset
External Reset
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
VDD
POR Pulse
Brown-out
Reset(1)
S
PWRT
32 μs
PWRT
INTRC
Note 1:
66 ms
11-Bit Ripple Counter
R
Q
Chip_Reset
The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip
voltage regulator when there is insufficient source voltage to function properly.
© 2009 Microchip Technology Inc.
DS39775C-page 55
PIC18F87J50 FAMILY
REGISTER 4-1:
RCON: RESET CONTROL REGISTER
R/W-0
U-0
R/W-1
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
—
CM
RI
TO
PD
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
Unimplemented: Read as ‘0’
bit 5
CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has not occurred
0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration
Mismatch Reset occurs)
bit 4
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3
TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2
PD: Power-Down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1
POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent
Power-on Resets may be detected.
2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section 4.4.1 “Detecting
BOR” for more information.
3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).
DS39775C-page 56
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
4.2
Master Clear (MCLR)
FIGURE 4-2:
The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR Reset path
which detects and ignores small pulses.
4.3
D
C
POR events are captured by the POR bit (RCON).
The state of the bit is set to ‘0’ whenever a Power-on
Reset occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘1’ in software following any Power-on Reset.
4.4
Brown-out Reset (BOR)
The PIC18F87J10 family of devices incorporates a
simple BOR function when the internal regulator is
enabled (ENVREG pin is tied to VDD). Any drop of VDD
below VBOR (parameter D005) for greater than time
TBOR (parameter 35) will reset the device. A Reset may
or may not occur if VDD falls below VBOR for less than
TBOR. The chip will remain in Brown-out Reset until
VDD rises above VBOR.
Once a BOR has occurred, the Power-up Timer will
keep the chip in Reset for TPWRT (parameter 33). If
VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be initialized. Once VDD
rises above VBOR, the Power-up Timer will execute the
additional time delay.
© 2009 Microchip Technology Inc.
MCLR
PIC18F87J50
Note 1:
External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2:
R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3:
R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004). For a slow rise
time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
R
R1
Power-on Reset (POR)
A Power-on Reset condition is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
VDD
VDD
The MCLR pin is not driven low by any internal Resets,
including the WDT.
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
4.4.1
DETECTING BOR
The BOR bit always resets to ‘0’ on any Brown-out
Reset or Power-on Reset event. This makes it difficult
to determine if a Brown-out Reset event has occurred
just by reading the state of BOR alone. A more reliable
method is to simultaneously check the state of both
POR and BOR. This assumes that the POR bit is reset
to ‘1’ in software immediately after any Power-on Reset
event. If BOR is ‘0’ while POR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
If the voltage regulator is disabled, Brown-out Reset
functionality is disabled. In this case, the BOR bit
cannot be used to determine a Brown-out Reset event.
The BOR bit is still cleared by a Power-on Reset event.
4.5
Configuration Mismatch (CM)
The Configuration Mismatch (CM) Reset is designed to
detect and attempt to recover from random, memory
corrupting events. These include Electrostatic
Discharge (ESD) events, which can cause widespread
single-bit changes throughout the device, and result in
catastrophic failure.
In PIC18FXXJ Flash devices, the device Configuration
registers (located in the configuration memory space)
are continuously monitored during operation by comparing their values to complimentary shadow registers.
If a mismatch is detected between the two sets of
registers, a CM Reset automatically occurs. These
events are captured by the CM bit (RCON). The
state of the bit is set to ‘0’ whenever a CM event occurs;
it does not change for any other Reset event.
DS39775C-page 57
PIC18F87J50 FAMILY
A CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT time-out or Stack Event
Resets. As with all hard and power Reset events, the
device Configuration Words are reloaded from the
Flash Configuration Words in program memory as the
device restarts.
4.6
Power-up Timer (PWRT)
PIC18F87J10 family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is always enabled. The
main function is to ensure that the device voltage is
stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F87J10 family devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32 μs = 66 ms. While the PWRT
is counting, the device is held in Reset.
FIGURE 4-3:
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 for details.
4.6.1
TIME-OUT SEQUENCE
The PWRT time-out is invoked after the POR pulse has
cleared. The total time-out will vary based on the status
of the PWRT. Figure 4-3, Figure 4-4, Figure 4-5 and
Figure 4-6 all depict time-out sequences on power-up
with the Power-up Timer.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR high will begin execution immediately if a clock
source is available (Figure 4-5). This is useful for
testing purposes, or to synchronize more than one
PIC18FXXXX device operating in parallel.
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 4-4:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
DS39775C-page 58
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
3.3V
VDD
0V
1V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
© 2009 Microchip Technology Inc.
DS39775C-page 59
PIC18F87J50 FAMILY
4.7
Reset State of Registers
different Reset situations, as indicated in Table 4-1.
These bits are used in software to determine the nature
of the Reset.
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Table 4-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register (CM, RI,
TO, PD, POR and BOR) are set or cleared differently in
TABLE 4-1:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
RCON Register
STKPTR Register
Program
Counter(1)
CM
RI
TO
PD
POR
BOR
Power-on Reset
0000h
1
1
1
1
0
0
0
0
RESET instruction
0000h
u
0
u
u
u
u
u
u
Brown-out Reset
0000h
1
1
1
1
u
0
u
u
Configuration Mismatch Reset
0000h
0
u
u
u
u
u
u
u
MCLR Reset during
power-managed Run modes
0000h
u
u
1
u
u
u
u
u
MCLR Reset during
power-managed Idle modes and
Sleep mode
0000h
u
u
1
0
u
u
u
u
MCLR Reset during full-power
execution
0000h
u
u
u
u
u
u
u
u
Stack Full Reset (STVREN = 1)
0000h
u
u
u
u
u
u
1
u
Stack Underflow Reset
(STVREN = 1)
0000h
u
u
u
u
u
u
u
1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
u
u
u
u
u
u
u
1
WDT time-out during full-power
or power-managed Run modes
0000h
u
u
0
u
u
u
u
u
WDT time-out during
power-managed Idle or Sleep
modes
PC + 2
u
u
0
0
u
u
u
u
Interrupt exit from
power-managed modes
PC + 2
u
u
u
0
u
u
u
u
Condition
STKFUL STKUNF
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
DS39775C-page 60
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
TOSU
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---0 uuuu(1)
TOSH
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu(1)
TOSL
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu(1)
STKPTR
Feature1
PIC18F8XJ5X
00-0 0000
uu-0 0000
uu-u uuuu(1)
PCLATU
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
PCLATH
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PCL
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
PC + 2(2)
TBLPTRU
Feature1
PIC18F8XJ5X
--00 0000
--00 0000
--uu uuuu
TBLPTRH
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
TABLAT
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PRODH
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
Feature1
PIC18F8XJ5X
0000 000x
0000 000u
uuuu uuuu(3)
INTCON2
Feature1
PIC18F8XJ5X
1111 1111
1111 1111
uuuu uuuu(3)
INTCON3
Feature1
PIC18F8XJ5X
1100 0000
1100 0000
uuuu uuuu(3)
INDF0
Feature1
PIC18F8XJ5X
N/A
N/A
N/A
POSTINC0
Feature1
PIC18F8XJ5X
N/A
N/A
N/A
POSTDEC0
Feature1
PIC18F8XJ5X
N/A
N/A
N/A
PREINC0
Feature1
PIC18F8XJ5X
N/A
N/A
N/A
PLUSW0
Feature1
PIC18F8XJ5X
N/A
N/A
N/A
FSR0H
Feature1
PIC18F8XJ5X
---- xxxx
---- uuuu
---- uuuu
FSR0L
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
Feature1
PIC18F8XJ5X
N/A
N/A
N/A
POSTINC1
Feature1
PIC18F8XJ5X
N/A
N/A
N/A
POSTDEC1
Feature1
PIC18F8XJ5X
N/A
N/A
N/A
PREINC1
Feature1
PIC18F8XJ5X
N/A
N/A
N/A
PLUSW1
Feature1
PIC18F8XJ5X
N/A
N/A
N/A
FSR1H
Feature1
PIC18F8XJ5X
---- xxxx
---- uuuu
---- uuuu
FSR1L
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
Feature1
PIC18F8XJ5X
---- 0000
---- 0000
---- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
© 2009 Microchip Technology Inc.
DS39775C-page 61
PIC18F87J50 FAMILY
TABLE 4-2:
Register
INDF2
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Feature1
PIC18F8XJ5X
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
N/A
N/A
N/A
POSTINC2
Feature1
PIC18F8XJ5X
N/A
N/A
N/A
POSTDEC2
Feature1
PIC18F8XJ5X
N/A
N/A
N/A
PREINC2
Feature1
PIC18F8XJ5X
N/A
N/A
N/A
PLUSW2
Feature1
PIC18F8XJ5X
N/A
N/A
N/A
FSR2H
Feature1
PIC18F8XJ5X
---- xxxx
---- uuuu
---- uuuu
FSR2L
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
Feature1
PIC18F8XJ5X
---x xxxx
---u uuuu
---u uuuu
TMR0H
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
TMR0L
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
Feature1
PIC18F8XJ5X
1111 1111
1111 1111
uuuu uuuu
OSCCON
Feature1
PIC18F8XJ5X
0110 q100
0110 q100
0110 q10u
REFOCON
Feature1
PIC18F8XJ5X
0-00 0000
u-uu uuuu
u-uu uuuu
CM1CON
Feature1
PIC18F8XJ5X
0001 1111
uuuu uuuu
uuuu uuuu
CM2CON
Feature1
PIC18F8XJ5X
0001 1111
uuuu uuuu
uuuu uuuu
RCON
Feature1
PIC18F8XJ5X
0-11 1100
0-qq qquu
u-qq qquu
TMR1H
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
ODCON1
Feature1
PIC18F8XJ5X
---0 0000
---u uuuu
---u uuuu
TMR1L
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
ODCON2
Feature1
PIC18F8XJ5X
---- --00
---- --uu
---- --uu
T1CON
Feature1
PIC18F8XJ5X
0000 0000
u0uu uuuu
uuuu uuuu
ODCON3
Feature1
PIC18F8XJ5X
---- --00
---- --uu
---- --uu
TMR2
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PADCFG1
Feature1
PIC18F8XJ5X
---- ---0
---- ---u
---- ---u
PR2
Feature1
PIC18F8XJ5X
1111 1111
1111 1111
1111 1111
MEMCON
Feature1
PIC18F8XJ5X
0-00 --00
0-00 --00
u-uu --uu
T2CON
Feature1
PIC18F8XJ5X
-000 0000
-000 0000
-uuu uuuu
(4)
SSP1BUF
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSP1ADD
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
SSP1MSK
Feature1
PIC18F8XJ5X
1111 1111
uuuu uuuu
uuuu uuuu
SSP1STAT
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
SSP1CON1
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
SSP1CON2
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
DS39775C-page 62
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
ADRESH
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
ADCON1
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
ANCON0
Feature1
PIC18F8XJ5X
0--0 0000
u--u uuuu
u--u uuuu
ANCON1
Feature1
PIC18F8XJ5X
0000 00--
uuuu uu--
uuuu uu--
WDTCON
Feature1
PIC18F8XJ5X
0x-0 ---0
0x-u ---0
ux-u ---u
ECCP1AS
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
ECCP1DEL
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
CCPR1H
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
ECCP2AS
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
ECCP2DEL
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
CCPR2H
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
ECCP3AS
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
ECCP3DEL
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
CCPR3H
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR3L
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP3CON
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
SPBRG1
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
RCREG1
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
TXREG1
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXSTA1
Feature1
PIC18F8XJ5X
0000 0010
0000 0010
uuuu uuuu
RCSTA1
Feature1
PIC18F8XJ5X
0000 000x
0000 000x
uuuu uuuu
SPBRG2
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
RCREG2
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
TXREG2
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
TXSTA2
Feature1
PIC18F8XJ5X
0000 0010
0000 0010
uuuu uuuu
EECON2
Feature1
PIC18F8XJ5X
---- ----
---- ----
---- ----
EECON1
Feature1
PIC18F8XJ5X
--00 x00-
--00 u00-
--00 u00-
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
© 2009 Microchip Technology Inc.
DS39775C-page 63
PIC18F87J50 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
IPR3
Feature1
PIC18F8XJ5X
1111 1111
1111 1111
uuuu uuuu
PIR3
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu(3)
PIE3
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
IPR2
Feature1
PIC18F8XJ5X
1111 1111
1111 1111
uuuu uuuu
PIR2
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu(3)
PIE2
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
IPR1
Feature1
PIC18F8XJ5X
1111 1111
1111 1111
uuuu uuuu
PIR1
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu(3)
PIE1
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
RCSTA2
Feature1
PIC18F8XJ5X
0000 000x
0000 000x
uuuu uuuu
OSCTUNE
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
TRISJ
Feature1
PIC18F8XJ5X
1111 1111
1111 1111
uuuu uuuu
TRISH
Feature1
PIC18F8XJ5X
1111 1111
1111 1111
uuuu uuuu
TRISG
Feature1
PIC18F8XJ5X
---1 1111
---1 1111
---u uuuu
TRISF
Feature1
PIC18F8XJ5X
111- -1--
111- -1--
uuu- -u--
TRISE
Feature1
PIC18F8XJ5X
1111 1111
1111 1111
uuuu uuuu
TRISD
Feature1
PIC18F8XJ5X
1111 1111
1111 1111
uuuu uuuu
TRISC
Feature1
PIC18F8XJ5X
1111 1111
1111 1111
uuuu uuuu
TRISB
Feature1
PIC18F8XJ5X
1111 1111
1111 1111
uuuu uuuu
TRISA
Feature1
PIC18F8XJ5X
--11 1111
--11 1111
--uu uuuu
LATJ
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATH
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATG
Feature1
PIC18F8XJ5X
---x xxxx
---u uuuu
---u uuuu
LATF
Feature1
PIC18F8XJ5X
xxxx xx--
uuuu uu--
uuuu uu--
LATE
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATD
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATA
Feature1
PIC18F8XJ5X
--xx xxxx
--uu uuuu
--uu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
DS39775C-page 64
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
PORTJ
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTH
Feature1
PIC18F8XJ5X
0000 xxxx
uuuu uuuu
uuuu uuuu
PORTG
Feature1
PIC18F8XJ5X
000x xxxx
000u uuuu
uuuu uuuu
PORTF
Feature1
PIC18F8XJ5X
x00x x0--
u00u u0--
u00u u0--
PORTE
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTD
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
Feature1
PIC18F8XJ5X
--0x 0000
--0u 0000
--uu uuuu
SPBRGH1
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
BAUDCON1
Feature1
PIC18F8XJ5X
0100 0-00
0100 0-00
uuuu u-uu
SPBRGH2
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
BAUDCON2
Feature1
PIC18F8XJ5X
0100 0-00
0100 0-00
uuuu u-uu
TMR3H
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
Feature1
PIC18F8XJ5X
0000 0000
uuuu uuuu
uuuu uuuu
TMR4
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PR4
Feature1
PIC18F8XJ5X
1111 1111
1111 1111
1111 1111
CVRCON
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
T4CON
Feature1
PIC18F8XJ5X
-000 0000
-000 0000
-uuu uuuu
CCPR4H
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR4L
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP4CON
Feature1
PIC18F8XJ5X
--00 0000
--00 0000
--uu uuuu
CCPR5H
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR5L
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP5CON
Feature1
PIC18F8XJ5X
--00 0000
--00 0000
--uu uuuu
SSP2BUF
Feature1
PIC18F8XJ5X
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSP2ADD
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
SSP2MSK
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
SSP2STAT
Feature1
PIC18F8XJ5X
1111 1111
1111 1111
uuuu uuuu
SSP2CON1
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
SSP2CON2
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
CMSTAT
Feature1
PIC18F8XJ5X
---- --11
---- --11
---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
© 2009 Microchip Technology Inc.
DS39775C-page 65
PIC18F87J50 FAMILY
TABLE 4-2:
Register
PMADDRH
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PMDOUT1H
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PMADDRL
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PMDOUT1L
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PMDIN1H
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PMDIN1L
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
UCON
Feature1
PIC18F8XJ5X
-0x0 000-
-0x0 000-
-uuu uuu-
USTAT
Feature1
PIC18F8XJ5X
-xxx xxx-
-xxx xxx-
-uuu uuu-
UEIR
Feature1
PIC18F8XJ5X
0--0 0000
0--0 0000
u--u uuuu
UIR
Feature1
PIC18F8XJ5X
-000 0000
-000 0000
-uuu uuuu
UFRMH
Feature1
PIC18F8XJ5X
---- -xxx
---- -xxx
---- -uuu
UFRML
Feature1
PIC18F8XJ5X
xxxx xxxx
xxxx xxxx
uuuu uuuu
UCFG
Feature1
PIC18F8XJ5X
00-0 0000
00-0 0000
uu-u uuuu
UADDR
Feature1
PIC18F8XJ5X
-000 0000
-uuu uuuu
-uuu uuuu
UEIE
Feature1
PIC18F8XJ5X
0--0 0000
0--0 0000
u--u uuuu
UIE
Feature1
PIC18F8XJ5X
-000 0000
-000 0000
-uuu uuuu
UEP15
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP14
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP13
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP12
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP11
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP10
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP9
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP8
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP7
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP6
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP5
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP4
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP3
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP2
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP1
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
UEP0
Feature1
PIC18F8XJ5X
---0 0000
---0 0000
---u uuuu
PMCONH
Feature1
PIC18F8XJ5X
0-00 0000
0-00 0000
u-uu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
DS39775C-page 66
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
PMCONL
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PMMODEH
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PMMODEL
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PMDOUT2H
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PMDOUT2L
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PMDIN2H
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PMDIN2L
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PMEH
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PMEL
Feature1
PIC18F8XJ5X
0000 0000
0000 0000
uuuu uuuu
PMSTATH
Feature1
PIC18F8XJ5X
00-- 0000
00-- 0000
uu-- uuuu
PMSTATL
Feature1
PIC18F8XJ5X
10-- 1111
10-- 1111
uu-- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
© 2009 Microchip Technology Inc.
DS39775C-page 67
PIC18F87J50 FAMILY
NOTES:
DS39775C-page 68
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
MEMORY ORGANIZATION
5.1
There are two types of memory in PIC18 Flash
microcontroller devices:
• Program Memory
• Data RAM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for
concurrent access of the two memory spaces.
Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0
“Flash Program Memory”.
FIGURE 5-1:
Program Memory Organization
PIC18 microcontrollers implement a 21-bit program
counter which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOP instruction).
The entire PIC18F87J10 family offers a range of
on-chip Flash program memory sizes, from 64 Kbytes
(up to 16,384 single-word instructions) to 128 Kbytes
(65,536 single-word instructions). The program
memory maps for individual family members are shown
in Figure 5-3.
MEMORY MAPS FOR PIC18F87J50 FAMILY DEVICES
CALL, CALLW, RCALL,
RETURN, RETFIE, RETLW,
ADDULNK, SUBULNK
PIC18FX5J50
On-Chip
Memory
PC
21
Stack Level 1
•••
Stack Level 31
PIC18FX6J50
On-Chip
Memory
PIC18FX6J55
On-Chip
Memory
PIC18FX7J50
On-Chip
Memory
Config. Words
000000h
007FFFh
Config. Words
00FFFFh
Config. Words
017FFFh
Config. Words
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
01FFFFh
User Memory Space
5.0
1FFFFFF
Note:
Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.
© 2009 Microchip Technology Inc.
DS39775C-page 69
PIC18F87J50 FAMILY
5.1.1
HARD MEMORY VECTORS
5.1.2
FLASH CONFIGURATION WORDS
All PIC18 devices have a total of three hard-coded
return vectors in their program memory space. The
Reset vector address is the default value to which the
program counter returns on all device Resets; it is
located at 0000h.
Because PIC18F87J10 family devices do not have persistent configuration memory, the top four words of
on-chip program memory are reserved for configuration
information. On Reset, the configuration information is
copied into the Configuration registers.
PIC18 devices also have two interrupt vector
addresses for the handling of high-priority and
low-priority interrupts. The high-priority interrupt vector
is located at 0008h and the low-priority interrupt vector
is at 0018h. Their locations in relation to the program
memory map are shown in Figure 5-2.
The Configuration Words are stored in their program
memory location in numerical order, starting with the
lower byte of CONFIG1 at the lowest address and ending with the upper byte of CONFIG4. For these devices,
only Configuration Words, CONFIG1 through
CONFIG3, are used; CONFIG4 is reserved. The actual
addresses of the Flash Configuration Word for devices
in the PIC18F87J10 family are shown in Table 5-1.
Their location in the memory map is shown with the
other memory vectors in Figure 5-2.
FIGURE 5-2:
HARD VECTOR AND
CONFIGURATION WORD
LOCATIONS FOR
PIC18F87J50 FAMILY
DEVICES
Reset Vector
0000h
High-Priority Interrupt Vector
0008h
Low-Priority Interrupt Vector
0018h
Additional details on the device Configuration Words
are provided in Section 25.1 “Configuration Bits”.
TABLE 5-1:
Device
PIC18F65J50
On-Chip
Program Memory
PIC18F85J50
PIC18F66J50
PIC18F86J50
PIC18F66J55
PIC18F86J55
Flash Configuration Words
(Top of Memory-7)
(Top of Memory)
PIC18F67J50
PIC18F87J50
FLASH CONFIGURATION
WORD FOR PIC18F87J50
FAMILY DEVICES
Program
Memory
(Kbytes)
Configuration
Word
Addresses
32
7FF8h to 7FFFh
64
FFF8h to FFFFh
96
17FF8h to
17FFFh
128
1FFF8h to
1FFFFh
Read as ‘0’
1FFFFFh
Legend:
(Top of Memory) represents upper boundary
of on-chip program memory space (see
Figure 5-1 for device-specific values).
Shaded area represents unimplemented
memory. Areas are not shown to scale.
DS39775C-page 70
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
5.1.3
PIC18F87J50 FAMILY PROGRAM
MEMORY MODES
The 80-pin devices in this family can address up to a
total of 2 Mbytes of program memory. This is achieved
through the External Memory Bus. There are two
distinct operating modes available to the controllers:
• Microcontroller (MC)
• Extended Microcontroller (EMC)
The program memory mode is determined by setting
the EMB Configuration bits (CONFIG3L), as
shown in Register 5-1. (See also Section 25.1
“Configuration Bits” for additional details on the
device Configuration bits.)
The program memory modes operate as follows:
• The Microcontroller Mode accesses only on-chip
Flash memory. Attempts to read above the top of
on-chip memory causes a read of all ‘0’s (a NOP
instruction).
REGISTER 5-1:
The Microcontroller mode is also the only operating
mode available to 64-pin devices.
• The Extended Microcontroller Mode allows
access to both internal and external program
memories as a single block. The device can
access its entire on-chip program memory; above
this, the device accesses external program
memory up to the 2-Mbyte program space limit.
Execution automatically switches between the
two memories as required.
The setting of the EMB Configuration bits also controls
the address bus width of the External Memory Bus.
This is covered in more detail in Section 7.0 “External
Memory Bus”.
In all modes, the microcontroller has complete access
to data RAM.
Figure 5-3 compares the memory maps of the different
program memory modes. The differences between
on-chip and external memory access limitations are
more fully explained in Table 5-2.
CONFIG3L: CONFIGURATION REGISTER 3 LOW
R/WO-1
R/WO-1
R/WO-1
R/WO-1
R/WO-1
U-0
U-0
U-0
WAIT(1)
BW(1)
EMB1(1)
EMB0(1)
EASHFT(1)
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WAIT: External Bus Wait Enable bit(1)
1 = Wait states on the external bus are disabled
0 = Wait states on the external bus are enabled and selected by MEMCON
bit 6
BW: Data Bus Width Select bit(1)
1 = 16-Bit Data Width modes
0 = 8-Bit Data Width modes
bit 5-4
EMB1:EMB0: External Memory Bus Configuration bits(1)
11 = Microcontroller mode, external bus disabled
10 = Extended Microcontroller mode, 12-bit address width for external bus
01 = Extended Microcontroller mode, 16-bit address width for external bus
00 = Extended Microcontroller mode, 20-bit address width for external bus
bit 3
EASHFT: External Address Bus Shift Enable bit(1)
1 = Address shifting enabled – external address bus is shifted to start at 000000h
0 = Address shifting disabled – external address bus reflects the PC value
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
Implemented only on 80-pin devices.
© 2009 Microchip Technology Inc.
DS39775C-page 71
PIC18F87J50 FAMILY
5.1.4
EXTENDED MICROCONTROLLER
MODE AND ADDRESS SHIFTING
To avoid this, the Extended Microcontroller mode
implements an address shifting option to enable automatic address translation. In this mode, addresses
presented on the external bus are shifted down by the
size of the on-chip program memory and are remapped
to start at 0000h. This allows the complete use of the
external memory device’s memory space.
By default, devices in Extended Microcontroller mode
directly present the program counter value on the
external address bus for those addresses in the range
of the external memory space. In practical terms, this
means addresses in the external memory device below
the top of on-chip memory are unavailable.
FIGURE 5-3:
MEMORY MAPS FOR PIC18F87J50 FAMILY PROGRAM MEMORY MODES
Microcontroller Mode(1)
On-Chip
Memory
Space
Extended Microcontroller Mode(2)
External
Memory
Space
(Top of Memory)
(Top of Memory) + 1
External
Memory
(Top of Memory)
(Top of Memory) + 1(3)
External
Memory
Mapped
to
External
Memory 1FFFFFh –
Space (Top of Memory)
Mapped
to
External
Memory
Space
1FFFFFh
1FFFFFh
1FFFFFh
Note 1:
2:
3:
000000h
On-Chip
Program
Memory
On-Chip
Program
Memory
(Top of Memory)
(Top of Memory) + 1
Legend:
On-Chip
Memory
Space
000000h
No
Access
Reads
‘0’s
External
Memory
Space
On-Chip
Memory
Space
000000h
On-Chip
Program
Memory
Extended Microcontroller Mode
with Address Shifting(2)
(Top of Memory) represents upper boundary of on-chip program memory space (see Figure 5-1 for device-specific
values). Shaded areas represent unimplemented, or inaccessible areas, depending on the mode.
This mode is the only available mode on 64-pin devices and the default on 80-pin devices.
These modes are only available on 80-pin devices.
Addresses starting at the top of the program memory are translated to start at 0000h of the external device
whenever the EASHFT Configuration bit is set.
TABLE 5-2:
MEMORY ACCESS FOR PIC18F8XJ5X PROGRAM MEMORY MODES
Internal Program Memory
Operating Mode
External Program Memory
Execution
From
Table Read
From
Table Write
To
Execution
From
Table Read
From
Table Write
To
Microcontroller
Yes
Yes
Yes
No Access
No Access
No Access
Extended Microcontroller
Yes
Yes
Yes
Yes
Yes
Yes
DS39775C-page 72
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
5.1.5
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.8.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.6
RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW
or a RETFIE instruction (and on ADDULNK and
SUBULNK instructions if the extended instruction set is
enabled). PCLATU and PCLATH are not affected by
any of the RETURN or CALL instructions.
FIGURE 5-4:
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
Top-of-Stack Special Function Registers. Data can also
be pushed to, or popped from the stack, using these
registers.
A CALL type instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
5.1.6.1
Top-of-Stack Access
Only the top of the return address stack (TOS) is readable and writable. A set of three registers,
TOSU:TOSH:TOSL, hold the contents of the stack
location pointed to by the STKPTR register
(Figure 5-4). This allows users to implement a software
stack if necessary. After a CALL, RCALL or interrupt
(and ADDULNK and SUBULNK instructions if the
extended instruction set is enabled), the software can
read
the
pushed
value
by
reading
the
TOSU:TOSH:TOSL registers. These values can be
placed on a user-defined software stack. At return time,
the software can return these values to
TOSU:TOSH:TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
Top-of-Stack Registers
TOSU
00h
TOSH
1Ah
TOSL
34h
Top-of-Stack
© 2009 Microchip Technology Inc.
11111
11110
11101
001A34h
000D58h
Stack Pointer
STKPTR
00010
00011
00010
00001
00000
DS39775C-page 73
PIC18F87J50 FAMILY
5.1.6.2
Return Stack Pointer (STKPTR)
The STKPTR register (Register 5-2) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to
Section 25.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.
REGISTER 5-2:
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and set the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
Note:
5.1.6.3
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack, without disturbing normal program execution, is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
STKPTR: STACK POINTER REGISTER
R/C-0
R/C-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STKFUL(1)
STKUNF(1)
—
SP4
SP3
SP2
SP1
SP0
bit 7
bit 0
Legend:
C = Clearable only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
STKFUL: Stack Full Flag bit(1)
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6
STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1:
x = Bit is unknown
Bit 7 and bit 6 are cleared by user software or by a POR.
DS39775C-page 74
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
5.1.6.4
Stack Full and Underflow Resets
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 1L. When STVREN is set, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
5.1.7
FAST REGISTER STACK
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers to provide a “fast return”
option for interrupts. This stack is only one level deep
and is neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push values into the Stack registers. The values in
the registers are then loaded back into the working
registers if the RETFIE, FAST instruction is used to
return from the interrupt.
5.1.8
LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.1.8.1
Computed GOTO
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
If both low and high-priority interrupts are enabled, the
Stack registers cannot be used reliably to return from
low-priority interrupts. If a high-priority interrupt occurs
while servicing a low-priority interrupt, the Stack
register values stored by the low-priority interrupt will
be overwritten. In these cases, users must save the key
registers in software during a low-priority interrupt.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FAST instruction is then executed to restore
these registers from the Fast Register Stack.
EXAMPLE 5-2:
Example 5-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
EXAMPLE 5-1:
CALL SUB1, FAST
•
•
•
•
RETURN FAST
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
© 2009 Microchip Technology Inc.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
ORG
TABLE
5.1.8.2
MOVF
CALL
nn00h
ADDWF
RETLW
RETLW
RETLW
.
.
.
COMPUTED GOTO USING
AN OFFSET VALUE
OFFSET, W
TABLE
PCL
nnh
nnh
nnh
Table Reads
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per
program word while programming. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from the
program memory. Data is transferred from program
memory one byte at a time.
Table read operation is discussed further
Section 6.1 “Table Reads and Table Writes”.
in
DS39775C-page 75
PIC18F87J50 FAMILY
5.2
PIC18 Instruction Cycle
5.2.1
5.2.2
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction
cycle, while the decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to change (e.g.,
GOTO), then two cycles are required to complete the
instruction (Example 5-3).
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the Instruction Register (IR) during Q4. The instruction is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 5-5.
FIGURE 5-5:
INSTRUCTION FLOW/PIPELINING
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
PC
PC + 2
PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC)
EXAMPLE 5-3:
1. MOVLW 55h
Execute INST (PC + 2)
Fetch INST (PC + 4)
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
Fetch 1
Execute 1
2. MOVWF PORTB
3. BRA SUB_1
4. BSF
Execute INST (PC)
Fetch INST (PC + 2)
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
Fetch 2
TCY2
TCY3
TCY4
TCY5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush (NOP)
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS39775C-page 76
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
5.2.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). To maintain alignment
with instruction boundaries, the PC increments in steps
of 2 and the LSB will always read ‘0’ (see Section 5.1.5
“Program Counter”).
Figure 5-6 shows an example of how instruction words
are stored in the program memory.
FIGURE 5-6:
INSTRUCTIONS IN PROGRAM MEMORY
Program Memory
Byte Locations →
5.2.4
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruction. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-6 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 26.0 “Instruction Set Summary”
provides further details of the instruction set.
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
Instruction 3:
MOVFF
123h, 456h
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
EXAMPLE 5-4:
LSB = 1
LSB = 0
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Word Address
↓
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 5-4 shows how this works.
Note:
See Section 5.5 “Program Memory and
the Extended Instruction Set” for
information on two-word instructions in the
extended instruction set.
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; No, skip this word
ADDWF
REG3
; continue code
1111 0100 0101 0110
0010 0100 0000 0000
; Execute this word as a NOP
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; Yes, execute this word
ADDWF
REG3
; continue code
1111 0100 0101 0110
0010 0100 0000 0000
© 2009 Microchip Technology Inc.
; 2nd word of instruction
DS39775C-page 77
PIC18F87J50 FAMILY
5.3
Note:
Data Memory Organization
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.6 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. The
PIC18F87J10 family implements all available banks
and provides 3904 bytes of data memory available to
the user. Figure 5-7 shows the data memory
organization for the devices.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
section.
To ensure that commonly used registers (select SFRs
and select GPRs) can be accessed in a single cycle,
PIC18 devices implement an Access Bank. This is a
256-byte memory space that provides fast access to
select SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.3 “Access Bank”
provides a detailed description of the Access RAM.
5.3.1
USB RAM
The entire data memory is actually mapped to a special
dual access RAM. When the USB module is disabled,
the GPRs in these banks are used like any other GPR
in the data memory space.
When the USB module is enabled, the memory in these
banks is allocated as buffer RAM for USB operation.
This area is shared between the microcontroller core
and the USB Serial Interface Engine (SIE) and is used
to transfer data directly between the two.
5.3.2
BANK SELECT REGISTER
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR3:BSR0). The upper four
bits are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLB instruction.
The value of the BSR indicates the bank in data memory. The 8 bits in the instruction show the location in the
bank and can be thought of as an offset from the bank’s
lower boundary. The relationship between the BSR’s
value and the bank division in data memory is shown in
Figure 5-8.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 0Fh, will end up resetting the program counter.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 5-7 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
It is theoretically possible to use the areas of USB RAM
that are not allocated as USB buffers for normal
scratchpad memory or other variable storage. In
practice, the dynamic nature of buffer allocation makes
this risky at best. Additionally, Bank 4 is used for USB
buffer management when the module is enabled and
should not be used for any other purposes during that
time. Additional information on USB RAM and buffer
operation is provided in Section 22.0 “Universal
Serial Bus (USB)”
DS39775C-page 78
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
FIGURE 5-7:
DATA MEMORY MAP FOR PIC18F87J50 FAMILY DEVICES
BSR
00h
= 0000
= 0001
= 0010
= 0011
= 0100
= 0101
= 0110
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
= 1111
When a = 0:
Data Memory Map
Bank 0
FFh
00h
Access RAM
GPR(1)
(1)
Bank 1
GPR
1FFh
200h
FFh
00h
GPR(1)
Bank 2
FFh
00h
Bank 3
2FFh
300h
The first 96 bytes are general
purpose RAM (from Bank 0).
The remaining 160 bytes are
Special Function Registers
(from Bank 15).
When a = 1:
The BSR specifies the bank
used by the instruction.
3FFh
400h
GPR, BDT(1)
Bank 4
FFh
00h
4FFh
500h
GPR(1)
Bank 5
FFh
00h
Bank 6
FFh
00h
Bank 7
FFh
00h
Bank 8
FFh
00h
Bank 9
FFh
00h
Bank 10
FFh
00h
FFh
00h
Bank 12
FFh
00h
Bank 13
FFh
00h
Bank 14
Bank 15
The BSR is ignored and the
Access Bank is used.
GPR(1)
FFh
00h
Bank 11
000h
05Fh
060h
0FFh
100h
FFh
00h
40h
60h
GPR(1)
GPR(1)
GPR(1)
GPR(1)
GPR(1)
GPR(1)
(1)
GPR
GPR(1)
GPR(1)
GPR(1)
SFR(2)
5FFh
600h
6FFh
700h
Access Bank
Access RAM Low
7FFh
800h
00h
5Fh
Access RAM High 60h
(SFRs)
FFh
8FFh
900h
9FFh
A00h
AFFh
B00h
BFFh
C00h
CFFh
D00h
DFFh
E00h
EFFh
F00h
F3Fh
F5Fh
Access RAM
FFh
Note 1:
2:
FFFh
These banks also serve as RAM buffers for USB operation. See Section 5.3.1 “USB RAM” for more information.
Addresses, F40h through F5Fh, are not part of the Access Bank, therefore, specifying a BSR should be used to
access these registers.
© 2009 Microchip Technology Inc.
DS39775C-page 79
PIC18F87J50 FAMILY
FIGURE 5-8:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
BSR(1)
7
0
0
0
0
0
0
0
Bank Select(2)
1
0
000h
Data Memory
Bank 0
100h
Bank 1
200h
300h
Bank 2
00h
7
FFh
00h
11
From Opcode(2)
11
11
11
11
1
0
1
1
FFh
00h
FFh
00h
Bank 3
through
Bank 13
E00h
Bank 14
F00h
FFFh
Note 1:
2:
5.3.3
Bank 15
FFh
00h
FFh
00h
FFh
The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR) to
the registers of the Access Bank.
The MOVFF instruction embeds the entire 12-bit address in the instruction.
ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation, but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Bank 15. The lower half is known
as the “Access RAM” and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 5-7).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
DS39775C-page 80
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 5.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
5.3.4
GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom
of the SFR area. GPRs are not initialized by a
Power-on Reset and are unchanged on all other
Resets.
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
5.3.5
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
more than the top half of Bank 15 (F40h to FFFh). A list
of these registers is given inTable 5-3, Table 5-4 and
Table 5-5.
ALU’s STATUS register is described later in this
section. Registers related to the operation of the
peripheral features are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s
Note:
Addresses, F40h through F5Fh, are not
part of the Access Bank, therefore specifying a BSR should be used to access these
registers.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
TABLE 5-3:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J50 FAMILY DEVICES
Address
Name
Address
FFFh
TOSU
FDFh
INDF2(1)
Name
FFEh
TOSH
FDEh
POSTINC2(1)
FFDh
TOSL
FDDh POSTDEC2(1)
FFCh
STKPTR
FDCh
FFBh
PCLATU
FFAh
FF9h
Address
FBFh
Name
ECCP1AS
Address
Name
Address
F9Fh
IPR1
F7Fh
SPBRGH1
Name
Address
Name
F5Fh
UCFG
FBEh ECCP1DEL
F9Eh
PIR1
F7Eh
BAUDCON1
F5Eh
UADDR
FBDh
CCPR1H
F9Dh
PIE1
F7Dh
SPBRGH2
F5Dh
UEIE
PREINC2(1)
FBCh
CCPR1L
F9Ch
RCSTA2
F7Ch
BAUDCON2
F5Ch
UIE
FDBh
PLUSW2(1)
FBBh
CCP1CON
F9Bh
OSCTUNE
F7Bh
TMR3H
F5Bh
UEP15
PCLATH
FDAh
FSR2H
FBAh
ECCP2AS
F9Ah
TRISJ(2)
F7Ah
TMR3L
F5Ah
UEP14
PCL
FD9h
FSR2L
FB9h ECCP2DEL
F99h
TRISH(2)
F79h
T3CON
F59h
UEP13
UEP12
FF8h
TBLPTRU
FD8h
STATUS
FB8h
CCPR2H
F98h
TRISG
F78h
TMR4
F58h
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
CCPR2L
F97h
TRISF
F77h
PR4(3)
F57h
UEP11
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
CCP2CON
F96h
TRISE
F76h
T4CON
F56h
UEP10
FF5h
TABLAT
FD5h
T0CON
FB5h
ECCP3AS
FF4h
PRODH
FD4h
FF3h
PRODL
FD3h
OSCCON(3)
FB3h
CCPR3H
F93h
FF2h
INTCON
FD2h
CM1CON
FB2h
CCPR3L
F92h
FF1h
INTCON2
FD1h
CM2CON
FB1h
CCP3CON
F91h
LATJ(2)
FF0h
INTCON3
FD0h
RCON
FB0h
SPBRG1
F90h
LATH(2)
FEFh
INDF0(1)
FCFh
TMR1H(3)
FAFh
RCREG1
F8Fh
LATG
FEEh
POSTINC0(1)
FCEh
TMR1L(3)
FAEh
TXREG1
F8Eh
LATF
F6Eh
SSP2ADD
F4Eh
UEP2
(1)
FCDh
T1CON(3)
FADh
TXSTA1
F8Dh
LATE
F6Dh
SSP2STAT
F4Dh
UEP1
FEDh POSTDEC0
FB4h ECCP3DEL
F95h
TRISD
F75h
CCPR4H
F55h
UEP9
F94h
TRISC
F74h
CCPR4L
F54h
UEP8
TRISB
F73h
CCP4CON
F53h
UEP7
TRISA
F72h
CCPR5H
F52h
UEP6
F71h
CCPR5L
F51h
UEP5
F70h
CCP5CON
F50h
UEP4
F6Fh
SSP2BUF
F4Fh
UEP3
FECh
PREINC0(1)
FCCh
TMR2(3)
FACh
RCSTA1
F8Ch
LATD
F6Ch
SSP2CON1
F4Ch
UEP0
FEBh
(1)
PLUSW0
FCBh
PR2(3)
FABh
SPBRG2
F8Bh
LATC
F6Bh
SSP2CON2
F4Bh
PMCONH
FEAh
FSR0H
FCAh
T2CON
FAAh
RCREG2
F8Ah
LATB
F6Ah
CMSTAT
F4Ah
PMCONL
FE9h
FSR0L
FC9h
SSP1BUF
FA9h
TXREG2
F89h
LATA
F69h
PMADDRH(4)
F49h
PMMODEH
FE8h
WREG
FC8h
SSP1ADD
FA8h
TXSTA2
F88h
PORTJ(2)
F68h
PMADDRL(4)
F48h
PMMODEL
F87h
(2)
F67h
PMDIN1H
F47h PMDOUT2H
F46h PMDOUT2L
FE7h
(1)
INDF1
FC7h
SSP1STAT
FA7h
EECON2
POSTINC1(1)
FC6h
SSP1CON1
FA6h
EECON1
F86h
PORTG
F66h
PMDIN1L
FE5h POSTDEC1(1)
FC5h
SSP1CON2
FA5h
IPR3
F85h
PORTF
F65h
UCON
FE6h
PORTH
F45h
PMDIN2H
FE4h
PREINC1(1)
FC4h
ADRESH
FA4h
PIR3
F84h
PORTE
F64h
USTAT
F44h
PMDIN2L
FE3h
PLUSW1(1)
FC3h
ADRESL
FA3h
PIE3
F83h
PORTD
F63h
UEIR
F43h
PMEH
FE2h
FSR1H
FC2h
ADCON0(3)
FA2h
IPR2
F82h
PORTC
F62h
UIR
F42h
PMEL
FE1h
FSR1L
FC1h
ADCON1(3)
FA1h
PIR2
F81h
PORTB
F61h
UFRMH
F41h
PMSTATH
FE0h
BSR
FC0h
WDTCON
FA0h
PIE2
F80h
PORTA
F60h
UFRML
F40h
PMSTATL
Note
1:
2:
3:
4:
This is not a physical register.
This register is not available on 64-pin devices.
This register shares the same address with another register (see Table 5-4 for alternate register).
PMADDRH and PMDOUTH share the same address and PMADDRL and PMDOUTL share the same address. PMADDRx is used in Master
modes and PMDOUTx is used in Slave modes.
© 2009 Microchip Technology Inc.
DS39775C-page 81
PIC18F87J50 FAMILY
5.3.5.1
Shared Address SFRs
5.3.5.2
In several locations in the SFR bank, a single address
is used to access two different hardware registers. In
these cases, a “legacy” register of the standard PIC18
SFR set (such as OSCCON, T1CON, etc.) shares its
address with an alternate register. These alternate registers are associated with enhanced configuration
options for peripherals, or with new device features not
included in the standard PIC18 SFR map. A complete
list of shared register addresses and the registers
associated with them is provided in Table 5-4.
Access to the alternate registers is enabled in software
by setting the ADSHR bit in the WDTCON register
(Register 5-3). ADSHR must be manually set or
cleared to access the alternate or legacy registers, as
required. Since the bit remains in a given state until
changed, users should always verify the state of
ADSHR before writing to any of the shared SFR
addresses.
TABLE 5-4:
Address
Name
(D)
OSCCON
(A)
REFOCON
FCFh
(D)
TMR1H
(A)
ODCON1
(D)
TMR1L
(A)
Legend:
Note 1:
In addition to the shared address SFRs, there are several registers that share the same address in the SFR
space, but are not accessed with the ADSHR bit.
Instead, the register’s definition and use depends on
the operating mode of its associated peripheral. These
registers are:
• SSPxADD and SSPxMSK: These are two separate hardware registers, accessed through a
single SFR address. The operating mode of the
MSSP modules determines which register is
being accessed. See Section 19.4.3.4 “7-Bit
Address Masking Mode” for additional details.
• PMADDRH/L and PMDOUT2H/L: In this case,
these named buffer pairs are actually the same
physical registers. The PMP module’s operating
mode determines what function the registers take
on. See Section 11.1.2 “Data Registers” for
additional details.
SHARED SFR ADDRESSES FOR PIC18F87J50 FAMILY DEVICES
FD3h
FCEh
Context Defined SFRs
Address
Name
FCDh
(D)
T1CON
(A)
ODCON3
FCCh
(D)
TMR2
(A)
PADCFG1
(D)
PR2
(A)
MEMCON(1)
FCBh
ODCON2
Address
Name
FC2h
(D)
ADCON0
(A)
ANCON1
FC1h
(D)
ADCON1
(A)
ANCON0
(D)
PR4
(A)
CVRCON
F77h
(D) = Default SFR, accessible only when ADSHR = 0; (A) = Alternate SFR, accessible only when ADSHR = 1.
Implemented in 80-pin devices only.
REGISTER 5-3:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0
R-x
U-0
R/W-0
U-0
U-0
U-0
U-0
REGSLP
LVDSTAT
—
ADSHR
—
—
—
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
REGSLP: Voltage Regulator Low-Power Operation Enable bit
For details of bit operation, see Register 25-9 on page 359.
bit 6
LVDSTAT: Low-Voltage Detect Status bit
1 = VDDCORE > 2.45V nominal
0 = VDDCORE < 2.45V nominal
bit 5
Unimplemented: Read as ‘0’
bit 4
ADSHR: Shared Address SFR Select bit
1 = Alternate SFR is selected
0 = Default (legacy) SFR is selected
bit 3-1
Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit
For details of bit operation, see Register 25-9.
DS39775C-page 82
x = Bit is unknown
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 5-5:
File Name
REGISTER FILE SUMMARY (PIC18F87J50 FAMILY)
Bit 7
Bit 6
Bit 5
—
—
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Details
on
Page:
---0 0000
61, 73
TOSH
Top-of-Stack High Byte (TOS)
0000 0000
61, 73
TOSL
Top-of-Stack Low Byte (TOS)
0000 0000
61, 73
00-0 0000
61, 74
---0 0000
61, 73
61, 73
TOSU
STKPTR
STKFUL
STKUNF
—
PCLATU
—
—
bit 21(1)
Top-of-Stack Upper Byte (TOS)
Value on
POR, BOR
SP4
SP3
SP2
SP1
SP0
Holding Register for PC
PCLATH
Holding Register for PC
0000 0000
PCL
PC Low Byte (PC)
0000 0000
61, 73
--00 0000
61, 106
TBLPTRU
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR)
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR)
0000 0000
61, 106
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR)
0000 0000
61, 106
TABLAT
Program Memory Table Latch
0000 0000
61, 106
PRODH
Product Register High Byte
xxxx xxxx
61, 119
PRODL
Product Register Low Byte
xxxx xxxx
61, 119
0000 000x
61, 123
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
1111 1111
61, 123
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
1100 0000
61, 123
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
61, 91
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
61, 92
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
61, 92
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
61, 92
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
61, 92
FSR0H
---- xxxx
61, 91
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
—
xxxx xxxx
61, 91
WREG
Working Register
xxxx xxxx
61, 75
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
61, 91
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
61, 92
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
61, 92
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
61, 92
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
61, 92
---- xxxx
61, 91
xxxx xxxx
61, 91
FSR1H
—
FSR1L
—
—
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
Indirect Data Memory Address Pointer 1 High Byte
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
---- 0000
61, 78
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
62, 91
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
62, 92
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
62, 92
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
62, 92
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
62, 92
---- xxxx
62, 91
INDF2
FSR2H
—
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
—
—
—
—
—
—
Bank Select Register
Indirect Data Memory Address Pointer 2 High Byte
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address, available when WDTCON = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2 = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 19.4.3.2 “Address
Masking Modes” for details
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
© 2009 Microchip Technology Inc.
DS39775C-page 83
PIC18F87J50 FAMILY
TABLE 5-5:
File Name
FSR2L
REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
xxxx xxxx
62, 91
OV
Z
DC
C
---x xxxx
62, 89
Indirect Data Memory Address Pointer 2 Low Byte
STATUS
—
—
—
N
Details
on
Page:
Bit 3
TMR0H
Timer0 Register High Byte
0000 0000
62, 193
TMR0L
Timer0 Register Low Byte
xxxx xxxx
62, 193
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
62, 192
OSCCON(2)/
IDLEN
IRCF2
IRCF1
IRCF0
OSTS(4)
—
SCS1
SCS0
0110 q100
62, 44
REFOCON(3)
ROON
—
ROSSLP
ROSEL
RODIV3
RODIV2
RODIV1
RODIV0
0-00 0000
62, 45
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
0001 1111
62, 345
CM2CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
0001 1111
62, 345
RCON
IPEN
—
CM
RI
TO
PD
POR
BOR
0-11 1100
60, 62,
135
xxxx xxxx
62, 196
—
CCP5OD
CCP4OD
ECCP3OD
ECCP2OD
ECCP1OD
---0 0000
62, 139
xxxx xxxx
62, 196
---- --00
62, 139
CM1CON
TMR1H(2)/
ODCON1(3)
TMR1L(2)/
ODCON2(3)
T1CON(2)/
ODCON3(3)
TMR2(2)/
PADCFG1(3)
PR2(2)/
Timer1 Register High Byte
—
—
Timer1 Register Low Byte
—
—
—
—
—
—
U2OD
U1OD
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
0000 0000
62, 196
—
—
—
—
—
—
SPI2OD
SPI1OD
---- --00
62, 139
0000 0000
62, 201
—
—
—
—
—
—
PMPTTL
---- ---0
62, 140
1111 1111
62, 201
WAIT1
WAIT0
—
—
WM1
WMO
0-00 --00
62, 108
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
62, 201
xxxx xxxx
62, 243,
278
0000 0000
62, 248
Timer2 Register
—
Timer2 Period Register
MEMCON(3)
T2CON
EDBIS
—
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
SSP1BUF
MSSP1 Receive Buffer/Transmit Register
SSP1ADD/
MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C™ Master mode)
SSP1MSK(5)
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
1111 1111
62, 250
SSP1STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
62, 233,
244
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
62, 233,
245
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
GCEN
ACKSTAT
ADMSK5(6)
ADMSK4(6)
ADMSK3(6)
ADMSK2(6)
ADMSK1(6)
SEN
62, 233,
246
63, 310
ADRESH
A/D Result Register High Byte
xxxx xxxx
ADRESL
A/D Result Register Low Byte
xxxx xxxx
63, 310
ADON
0000 0000
63, 301
63, 301
ADCON0(2)/
VCFG1
VCFG0
CHS3
CHS2
CHS1
CHS0
ANCON1(3)
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
—
—
0000 00--
ADCON1(2)/
ADFM
ADCAL
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
0000 0000
63, 301
ANCON0(3)
PCFG7
—
—
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0--0 0000
63, 301
REGSLP
LVDSTAT
—
ADSHR
—
—
—
SWDTEN
0x-0 ---0
63, 358
WDTCON
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
GO/DONE
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address, available when WDTCON = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2 = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 19.4.3.2 “Address
Masking Modes” for details
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
DS39775C-page 84
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 5-5:
File Name
ECCP1AS
ECCP1DEL
REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0
P1RSEN
P1DC6
P1DC5
P1DC4
Value on
POR, BOR
Details
on
Page:
PSS1BD0
0000 0000
63, 232
P1DC0
0000 0000
63, 232
Bit 3
Bit 2
Bit 1
Bit 0
PSS1AC1
PSS1AC0
PSS1BD1
P1DC3
P1DC2
P1DC1
CCPR1H
Capture/Compare/PWM Register 1 HIgh Byte
xxxx xxxx
63, 232
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
63, 232
CCP1CON
ECCP2AS
ECCP2DEL
P1M1
P1M0
DC1B1
DC1B0
ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0
P2RSEN
P2DC6
P2DC5
P2DC4
CCP1M3
CCP1M2
CCP1M1
CCP1M0
0000 0000
63, 232
PSS2AC1
PSS2AC0
PSS2BD1
PSS2BD0
0000 0000
63, 232
P2DC3
P2DC2
P2DC1
P2DC0
0000 0000
63, 232
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx
63, 232
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx
63, 232
CCP2CON
ECCP3AS
ECCP3DEL
P2M1
P2M0
DC2B1
DC2B0
ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0
P3RSEN
P3DC6
P3DC5
P3DC4
CCP2M3
CCP2M2
CCP2M1
CCP2M0
0000 0000
63, 232
PSS3AC1
PSS3AC0
PSS3BD1
PSS3BD0
0000 0000
63, 232
P3DC3
P3DC2
P3DC1
P3DC0
0000 0000
63, 232
CCPR3H
Capture/Compare/PWM Register 3 High Byte
xxxx xxxx
63, 232
CCPR3L
Capture/Compare/PWM Register 3 Low Byte
xxxx xxxx
63, 232
0000 0000
63, 232
CCP3CON
P3M1
P3M0
DC3B1
DC3B0
CCP3M3
CCP3M2
CCP3M1
CCP3M0
SPBRG1
EUSART1 Baud Rate Generator Register Low Byte
0000 0000
63, 283
RCREG1
EUSART1 Receive Register
0000 0000
63, 291,
292
TXREG1
EUSART1 Transmit Register
xxxx xxxx
63, 289,
290
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
63, 289
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
63, 291
SPBRG2
EUSART2 Baud Rate Generator Register Low Byte
0000 0000
63, 283
RCREG2
EUSART2 Receive Register
0000 0000
63, 291,
292
TXREG2
EUSART2 Transmit Register
0000 0000
63, 289,
290
0000 0010
63, 289
TXSTA2
EECON2
EECON1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Program Memory Control Register 2 (not a physical register)
—
—
WPROG
FREE
WRERR
WREN
WR
—
---- ----
63, 98
--00 x00-
63, 98
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
1111 1111
64, 132
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
0000 0000
64, 126
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
0000 0000
64, 129
IPR2
OSCFIP
CM2IP
CM1IP
USBIP
BCL1IP
LVDIP
TMR3IP
CCP2IP
1111 1111
64, 132
PIR2
OSCFIF
CM2IF
CM1IF
USBIF
BCL1IF
LVDIF
TMR3IF
CCP2IF
0000 0000
64, 126
PIE2
OSCFIE
CM2IE
CM1IE
USBIE
BCL1IE
LVDIE
TMR3IE
CCP2IE
0000 0000
64, 129
IPR1
PMPIP
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
1111 1111
64, 132
PIR1
PMPIF
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
0000 0000
64, 126
PIE1
PMPIE
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
0000 0000
64, 129
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
64, 291
INTSRC
PLLEN
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
0000 0000
64, 39
OSCTUNE
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address, available when WDTCON = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2 = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 19.4.3.2 “Address
Masking Modes” for details
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
© 2009 Microchip Technology Inc.
DS39775C-page 85
PIC18F87J50 FAMILY
TABLE 5-5:
File Name
REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
Page:
TRISJ(7)
TRISJ7
TRISJ6
TRISJ5
TRISJ4
TRISJ3
TRISJ2
TRISJ1
TRISJ0
1111 1111
64, 165
TRISH(7)
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
1111 1111
64, 163
TRISG
—
—
—
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
---1 1111
64, 160
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
—
—
111- -1--
64, 157
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
1111 1111
64, 154
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
1111 1111
64, 151
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
64, 148
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
64, 145
TRISA
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
--11 1111
64, 142
LATJ(7)
LATJ7
LATJ6
LATJ5
LATJ4
LATJ3
LATJ2
LATJ1
LATJ0
xxxx xxxx
64, 165
LATH(7)
LATH7
LATH6
LATH5
LATH4
LATH3
LATH2
LATH1
LATH0
xxxx xxxx
64, 163
—
—
—
LATG4
LATG3
LATG2
LATG1
LATG0
---x xxxx
64, 160
64, 157
LATG
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
—
—
xxxx xx--
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
xxxx xxxx
64, 154
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx xxxx
64, 151
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
xxxx xxxx
64, 148
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx xxxx
64, 145
LATA
—
—
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
--xx xxxx
64, 142
PORTJ(7)
RJ7
RJ6
RJ5
RJ4
RJ3
RJ2
RJ1
RJ0
xxxx xxxx
65, 165
PORTH(7)
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
0000 xxxx
65, 163
PORTG
RDPU
REPU
RJPU(7)
RG4
RG3
RG2
RG1
RG0
000x xxxx
65, 160
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
—
—
x00x x0--
65, 157
PORTE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
xxxx xxxx
65, 154
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
65, 151
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
65, 148
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
65, 145
PORTA
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000
65, 142
SPBRGH1
BAUDCON1
SPBRGH2
BAUDCON2
EUSART1 Baud Rate Generator Register High Byte
ABDOVF
RCIDL
SCKP
BRG16
—
WUE
ABDEN
BRG16
—
WUE
ABDEN
EUSART2 Baud Rate Generator Register High Byte
ABDOVF
RCIDL
TMR3H
Timer3 Register High Byte
TMR3L
Timer3 Register Low Byte
T3CON
DTRXP
RD16
T3CCP2
DTRXP
T3CKPS1
SCKP
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
0000 0000
65, 283
0100 0-00
65, 283
0000 0000
65, 283
0100 0-00
65, 283
xxxx xxxx
65, 208
xxxx xxxx
65, 208
0000 0000
65, 208
TMR4
Timer4 Register
0000 0000
65, 207
PR4(2)/
Timer4 Period Register
1111 1111
65, 208
CVRCON(3)
T4CON
CVREN
—
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
CVROE
CVRR
CVRSS
CVR3
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0
CVR2
CVR1
CVR0
0000 0000
65, 346
TMR4ON
T4CKPS1
T4CKPS0
-000 0000
65, 207
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address, available when WDTCON = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2 = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 19.4.3.2 “Address
Masking Modes” for details
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
DS39775C-page 86
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 5-5:
File Name
REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
Page:
65, 210
CCPR4H
Capture/Compare/PWM Register 4 High Byte
xxxx xxxx
CCPR4L
Capture/Compare/PWM Register 4 Low Byte
xxxx xxxx
65, 210
--00 0000
65, 210
CCP4CON
—
—
DC4B1
DC4B0
CCP4M3
CCP4M2
CCP4M1
CCP4M0
CCPR5H
Capture/Compare/PWM Register 5 High Byte
xxxx xxxx
65, 210
CCPR5L
Capture/Compare/PWM Register 5 Low Byte
xxxx xxxx
65, 210
CCP5CON
—
—
DC5B1
DC5B0
CCP5M3
CCP5M2
CCP5M1
CCP5M0
SSP2BUF
MSSP2 Receive Buffer/Transmit Register
SSP2ADD/
MSSP2 Address Register (I2C™ Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode)
--00 0000
65, 210
xxxx xxxx
65, 243,
278
0000 0000
65, 243
SSP2MSK(5)
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
0000 0000
65, 250
SSP2STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
1111 1111
65, 233,
244
SSP2CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
65, 233,
245
SSP2CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
GCEN
ACKSTAT
ADMSK5(6)
ADMSK4(6)
ADMSK3(6)
ADMSK2(6)
ADMSK1(6)
SEN
65, 233,
245
—
—
—
—
COUT2
COUT1
CMSTAT
---- --11
65, 339
0000 0000
66, 174
PMDOUT1H(8) Parallel Port Out Data High Byte (Buffer 1)
0000 0000
66, 177
PMADDRL/
Parallel Master Port Address Low Byte
0000 0000
66, 174
PMDOUT1L(8)
Parallel Port Out Data Low Byte (Buffer 0)
0000 0000
66, 174
PMDIN1H
Parallel Port In Data High Byte (Buffer 1)
0000 0000
66, 174
PMDIN1L
Parallel Port In Data Low Byte (Buffer 0)
0000 0000
66, 174
-0x0 000-
66, 312
PMADDRH/
UCON
USTAT
—
—
CS2
CS1
Parallel Master Port Address High Byte
—
PPBRST
SE0
PKTDIS
USBEN
RESUME
SUSPND
—
—
ENDP3
ENDP2
ENDP1
ENDP0
DIR
PPBI
—
-xxx xxx-
66, 316
BTSEF
—
—
BTOEF
DFN8EF
CRC16EF
CRC5EF
PIDEF
0--0 0000
66, 329
UIR
—
SOFIF
STALLIF
IDLEIF
TRNIF
ACTVIF
UERRIF
URSTIF
-000 0000
66, 326
UFRMH
—
—
—
—
—
FRM10
FRM9
FRM8
---- -xxx
66, 318
UFRML
FRM7
FRM6
FRM5
FRM4
FRM3
FRM2
FRM1
FRM0
xxxx xxxx
66, 318
UTEYE
—
—
UPUEN
UTRDIS
FSEN
PPB1
PPB0
00-0 0000
66, 313
UEIR
UCFG
UADDR
—
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
-000 0000
66, 318
BTSEE
—
—
BTOEE
DFN8EE
CRC16EE
CRC5EE
PIDEE
0--0 0000
66, 330
UIE
—
SOFIE
STALLIE
IDLEIE
TRNIE
ACTVIE
UERRIE
URSTIE
-000 0000
66, 328
UEP15
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEP14
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEP13
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEP12
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEP11
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEP10
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEP9
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEP8
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEIE
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address, available when WDTCON = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2 = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 19.4.3.2 “Address
Masking Modes” for details
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
© 2009 Microchip Technology Inc.
DS39775C-page 87
PIC18F87J50 FAMILY
TABLE 5-5:
File Name
REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
Page:
UEP7
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEP6
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEP5
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEP4
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEP3
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEP2
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEP1
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
UEP0
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
66, 317
PMCONH
PMPEN
—
PSIDL
ADRMUX1
ADRMUX0
PTBEEN
PTWREN
PTRDEN
0-00 0000
66, 168
PMCONL
CSF1
CSF0
ALP
CS2P
CS1P
BEP
WRSP
RDSP
0000 0000
67, 169
PMMODEH
BUSY
IRQM1
IRQM0
INCM1
INCM0
MODE16
MODE1
MODE0
0000 0000
67, 170
PMMODEL
WAITB1
WAITB0
WAITM3
WAITM2
WAITM1
WAITM0
WAITE1
WAITE0
0000 0000
67, 171
PMDOUT2H
Parallel Port Out Data High Byte (Buffer 3)
0000 0000
67, 174
PMDOUT2L
Parallel Port Out Data Low Byte (Buffer 2)
0000 0000
67, 174
PMDIN2H
Parallel Port In Data High Byte (Buffer 3)
0000 0000
67, 174
PMDIN2L
Parallel Port In Data Low Byte (Buffer 2)
0000 0000
67, 174
PMEH
PTEN15
PTEN14
PTEN13
PTEN12
PTEN11
PTEN10
PTEN9
PTEN8
0000 0000
67, 171
PMEL
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
0000 0000
67, 172
PMSTATH
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
00-- 0000
67, 172
PMSTATL
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
10-- 1111
67, 173
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address, available when WDTCON = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2 = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 19.4.3.2 “Address
Masking Modes” for details
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
DS39775C-page 88
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
5.3.6
STATUS REGISTER
The STATUS register, shown in Register 5-4, contains
the arithmetic status of the ALU. The STATUS register
can be the operand for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
then the write to these five bits is disabled.
These bits are set or cleared according to the device
logic. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended. For example, CLRF STATUS will set the Z bit
but leave the other bits unchanged. The STATUS
REGISTER 5-4:
U-0
For other instructions not affecting any Status bits, see
the instruction set summaries in Table 26-2 and
Table 26-3.
Note:
The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
STATUS REGISTER
U-0
—
register then reads back as ‘000u u1uu’. It is recommended, therefore, that only BCF, BSF, SWAPF,
MOVFF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C, DC, OV or N bits in the STATUS
register.
U-0
—
—
R/W-x
N
R/W-x
R/W-x
R/W-x
R/W-x
Z
DC(1)
C(2)
OV
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit(1)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/borrow bit(2)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source
register.
For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.
© 2009 Microchip Technology Inc.
DS39775C-page 89
PIC18F87J50 FAMILY
5.4
Data Addressing Modes
Note:
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 5.6 “Data Memory
and the Extended Instruction Set” for
more information.
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
•
•
•
•
Inherent
Literal
Direct
Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 5.6.1 “Indexed
Addressing with Literal Offset”.
5.4.1
INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device, or they operate implicitly on
one register. This addressing mode is known as
Inherent Addressing. Examples include SLEEP, RESET
and DAW.
Other instructions work in a similar way, but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode, because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
5.4.2
DIRECT ADDRESSING
Direct Addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit Literal Address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.4 “General
DS39775C-page 90
Purpose Register File”), or a location in the Access
Bank (Section 5.3.3 “Access Bank”) as the data
source for the instruction.
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.2 “Bank Select Register”) are used with
the address to determine the complete 12-bit address
of the register. When ‘a’ is ‘0’, the address is interpreted
as being a register in the Access Bank. Addressing that
uses the Access RAM is sometimes also known as
Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
5.4.3
INDIRECT ADDRESSING
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures such as
tables and arrays in data memory.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code using
loops, such as the example of clearing an entire RAM
bank in Example 5-5. It also enables users to perform
Indexed Addressing and other Stack Pointer
operations for program memory in data memory.
EXAMPLE 5-5:
NEXT
LFSR
CLRF
BTFSS
BRA
CONTINUE
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
FSR0, 100h ;
POSTINC0
; Clear INDF
; register then
; inc pointer
FSR0H, 1
; All done with
; Bank1?
NEXT
; NO, clear next
; YES, continue
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
5.4.3.1
FSR Registers and the
INDF Operand
mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register
actually accesses its corresponding FSR register pair.
A read from INDF1, for example, reads the data at the
address indicated by FSR1H:FSR1L. Instructions that
use the INDF registers as operands actually use the
contents of their corresponding FSR as a pointer to the
instruction’s target. The INDF operand is just a
convenient way of using the pointer.
At the core of Indirect Addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
Indirect Addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers: they are
FIGURE 5-9:
INDIRECT ADDRESSING
000h
Using an instruction with one of the
Indirect Addressing registers as the
operand....
Bank 0
ADDWF, INDF1, 1
100h
Bank 1
200h
...uses the 12-bit address stored in
the FSR pair associated with that
register....
300h
FSR1H:FSR1L
7
0
x x x x 1 1 1 1
7
0
Bank 2
Bank 3
through
Bank 13
1 1 0 0 1 1 0 0
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
FCCh. This means the contents of
location FCCh will be added to that
of the W register and stored back in
FCCh.
E00h
Bank 14
F00h
FFFh
Bank 15
Data Memory
© 2009 Microchip Technology Inc.
DS39775C-page 91
PIC18F87J50 FAMILY
5.4.3.2
FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on its stored value. They are:
• POSTDEC: accesses the FSR value, then
automatically decrements it by ‘1’ afterwards
• POSTINC: accesses the FSR value, then
automatically increments it by ‘1’ afterwards
• PREINC: increments the FSR value by ‘1’, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the new value in the operation
In this context, accessing an INDF register uses the
value in the FSR registers without changing them.
Similarly, accessing a PLUSW register gives the FSR
value offset by the value in the W register; neither value
is actually changed in the operation. Accessing the
other virtual registers changes the value of the FSR
registers.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
DS39775C-page 92
5.4.3.3
Operations by FSRs on FSRs
Indirect Addressing operations that target other FSRs
or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers
will not result in successful operations. As a specific
case, assume that FSR0H:FSR0L contains FE7h, the
address of INDF1. Attempts to read the value of the
INDF1, using INDF0 as an operand, will return 00h.
Attempts to write to INDF1, using INDF0 as the
operand, will result in a NOP.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses Indirect Addressing.
Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
5.5
Program Memory and the
Extended Instruction Set
The operation of program memory is unaffected by the
use of the extended instruction set.
Enabling the extended instruction set adds five
additional two-word commands to the existing PIC18
instruction set: ADDFSR, CALLW, MOVSF, MOVSS and
SUBFSR. These instructions are executed as described
in Section 5.2.4 “Two-Word Instructions”.
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
5.6
Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core
PIC18 instructions is different. This is due to the introduction of a new addressing mode for the data memory
space. This mode also alters the behavior of Indirect
Addressing using FSR2 and its associated operands.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in Direct Addressing) or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
5.6.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing
modes are unaffected.
5.6.1
Additionally, byte-oriented and bit-oriented instructions
are not affected if they use the Access Bank (Access
RAM bit is ‘1’) or include a file address of 60h or above.
Instructions meeting these criteria will continue to
execute as before. A comparison of the different possible addressing modes when the extended instruction
set is enabled is shown in Figure 5-10.
INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented
instructions – can invoke a form of Indexed Addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset, or Indexed Literal Offset mode.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 26.2.1
“Extended Instruction Syntax”.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
and
• The file address argument is less than or equal to
5Fh.
© 2009 Microchip Technology Inc.
DS39775C-page 93
PIC18F87J50 FAMILY
FIGURE 5-10:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When a = 0 and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and FFFh. This is the same as
locations F60h to FFFh
(Bank 15) of data memory.
Locations below 060h are not
available in this addressing
mode.
000h
060h
Bank 0
100h
00h
Bank 1
through
Bank 14
F00h
60h
Valid range
for ‘f’
Access RAM
FFh
Bank 15
F60h
SFRs
FFFh
When a = 0 and f ≤ 5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When a = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
Data Memory
000h
Bank 0
060h
100h
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
Bank 15
F60h
SFRs
FFFh
Data Memory
BSR
00000000
000h
Bank 0
060h
100h
Bank 1
through
Bank 14
001001da ffffffff
F00h
Bank 15
F60h
SFRs
FFFh
DS39775C-page 94
Data Memory
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
5.6.3
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower part of Access RAM
(00h to 5Fh) is mapped. Rather than containing just the
contents of the bottom part of Bank 0, this mode maps
the contents from Bank 0 and a user-defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see Section 5.3.3 “Access
Bank”). An example of Access Bank remapping in this
addressing mode is shown in Figure 5-11.
FIGURE 5-11:
Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use Direct Addressing as before. Any Indirect or
Indexed Addressing operation that explicitly uses any
of the indirect file operands (including FSR2) will continue to operate as standard Indirect Addressing. Any
instruction that uses the Access Bank, but includes a
register address of greater than 05Fh, will use Direct
Addressing and the normal Access Bank map.
5.6.4
BSR IN INDEXED LITERAL
OFFSET MODE
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL
OFFSET ADDRESSING
Example Situation:
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
000h
05Fh
Bank 0
100h
120h
17Fh
200h
Window
Bank 1
00h
Bank 1 “Window”
5Fh
60h
Special Function Registers
at F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
Not Accessible
Bank 2
through
Bank 14
SFRs
FFh
Access Bank
F00h
Bank 15
F60h
FFFh
SFRs
Data Memory
© 2009 Microchip Technology Inc.
DS39775C-page 95
PIC18F87J50 FAMILY
NOTES:
DS39775C-page 96
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
6.0
FLASH PROGRAM MEMORY
6.1
Table Reads and Table Writes
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 64 bytes at a time or two bytes at a time. Program memory is erased in blocks of 1024 bytes at a
time. A bulk erase operation may not be issued from
user code.
• Table Read (TBLRD)
• Table Write (TBLWT)
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 6-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5 “Writing
to Flash Program Memory”. Figure 6-2 shows the
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1:
Table Pointer register points to a byte in program memory.
© 2009 Microchip Technology Inc.
DS39775C-page 97
PIC18F87J50 FAMILY
FIGURE 6-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1:
6.2
Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.
Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
•
•
•
•
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
6.2.1
EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The WPROG bit, when set, will allow programming
two bytes per word on the execution of the WR command. If this bit is cleared, the WR command will result
in programming on a block of 64 bytes.
DS39775C-page 98
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the write operation.
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
REGISTER 6-1:
EECON1: EEPROM CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-x
R/W-0
R/S-0
U-0
—
—
WPROG
FREE
WRERR(1)
WREN
WR
—
bit 7
bit 0
Legend:
S = Settable only bit (cannot be cleared in software)
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
WPROG: One Word-Wide Program bit
1 = Program 2 bytes on the next WR command
0 = Program 64 bytes on the next WR command
bit 4
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write only
bit 3
WRERR: Flash Program Error Flag bit(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0 = The write operation completed
bit 2
WREN: Flash Program Write Enable bit
1 = Allows write cycles to Flash program memory
0 = Inhibits write cycles to Flash program memory
bit 1
WR: Write Control bit
1 = Initiates a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle is complete
bit 0
Unimplemented: Read as ‘0’
Note 1:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
© 2009 Microchip Technology Inc.
DS39775C-page 99
PIC18F87J50 FAMILY
6.2.2
TABLE LATCH REGISTER (TABLAT)
6.2.4
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
6.2.3
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
TABLE POINTER REGISTER
(TBLPTR)
When a TBLWT is executed, the seven LSbs of the
Table Pointer register (TBLPTR) determine which
of the 64 program memory holding registers is written
to. When the timed write to program memory begins
(via the WR bit), the 12 MSbs of the TBLPTR
(TBLPTR) determine which program memory
block of 1024 bytes is written to. For more detail, see
Section 6.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the Configuration bits.
When an erase of program memory is executed, the
12 MSbs of the Table Pointer register point to the
1024-byte block that will be erased. The Least
Significant bits are ignored.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 6-1. These operations on the TBLPTR only affect
the low-order 21 bits.
TABLE 6-1:
TABLE POINTER BOUNDARIES
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
FIGURE 6-3:
21
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU
16
15
TBLPTRH
8
7
TBLPTRL
0
ERASE: TBLPTR
TABLE WRITE: TBLPTR
TABLE READ: TBLPTR
DS39775C-page 100
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
6.3
Reading the Flash Program
Memory
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
FIGURE 6-4:
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
Instruction Register
(IR)
EXAMPLE 6-1:
FETCH
TBLRD
TBLPTR = xxxxx0
TABLAT
Read Register
READING A FLASH PROGRAM MEMORY WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVF
MOVWF
TABLAT, W
WORD_EVEN
TABLAT, W
WORD_ODD
© 2009 Microchip Technology Inc.
; read into TABLAT and increment
; get data
; read into TABLAT and increment
; get data
DS39775C-page 101
PIC18F87J50 FAMILY
6.4
Erasing Flash Program Memory
The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or
through ICSP control, can larger blocks of program
memory be bulk erased. Word erase in the Flash array
is not supported.
When initiating an erase sequence from the microcontroller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 12 bits of the
TBLPTR point to the block being erased.
TBLPTR are ignored.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. For
protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 6-2:
6.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1.
2.
3.
4.
5.
6.
7.
8.
Load Table Pointer register with address of row
being erased.
Set the WREN and FREE bits (EECON1)
to enable the erase operation.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit. This will begin the row erase
cycle.
The CPU will stall for duration of the erase for
TIW (see parameter D133A).
Re-enable interrupts.
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
EECON1,
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
; enable write to memory
; enable Row Erase operation
; disable interrupts
ERASE_ROW
Required
Sequence
DS39775C-page 102
WREN
FREE
GIE
; write 55h
WR
GIE
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
6.5
Writing to Flash Program Memory
The on-chip timer controls the write time. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
The programming block is 32 words or 64 bytes.
Programming one word or two bytes at a time is also
supported.
Note 1: Unlike previous PIC® devices, members
of the PIC18F87J10 family do not reset
the holding registers after a write occurs.
The holding registers must be cleared or
overwritten before a programming
sequence.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT instruction may need to be executed 64 times for
each programming operation (if WPROG = 0). All of the
table write operations will essentially be short writes
because only the holding registers are written. At the
end of updating the 64 holding registers, the EECON1
register must be written to in order to start the
programming operation with a long write.
2: To maintain the endurance of the program
memory cells, each Flash byte should not
be programmed more than one time
between erase operations. Before
attempting to modify the contents of the
target cell a second time, a row erase of
the target row, or a bulk erase of the entire
memory, must be performed.
The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
TBLPTR = xxxxx0
8
TBLPTR = xxxxx1
Holding Register
TBLPTR = xxxx3F
TBLPTR = xxxxx2
Holding Register
8
Holding Register
Holding Register
Program Memory
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
Read 1024 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer register with address being
erased.
Execute the row erase procedure.
Load Table Pointer register with address of first
byte being written, minus 1.
Write the 64 bytes into the holding registers with
auto-increment.
Set the WREN bit (EECON1) to enable byte
writes.
© 2009 Microchip Technology Inc.
8.
9.
10.
11.
12.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit. This will begin the write cycle.
The CPU will stall for duration of the write for TIW
(see parameter D133A).
13. Re-enable interrupts.
14. Repeat steps 6 through 13 until all 1024 bytes
are written to program memory.
15. Verify the memory (table read).
An example of the required code is shown in
Example 6-3 on the following page.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
DS39775C-page 103
PIC18F87J50 FAMILY
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base address
; of the memory block, minus 1
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
MOVLW
MOVWF
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
D'16'
WRITE_COUNTER
; enable write to memory
; enable Row Erase operation
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64'
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
ERASE_BLOCK
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
; Need to write 16 blocks of 64 to write
; one erase block of 1024
RESTART_BUFFER
; point to buffer
FILL_BUFFER
...
; read the new data from I2C, SPI,
; PSP, USART, etc.
WRITE_BUFFER
MOVLW
MOVWF
WRITE_BYTE_TO_HREGS
MOVFF
MOVWF
TBLWT+*
D’64
COUNTER
; number of bytes in holding register
POSTINC0, WREG
TABLAT
;
;
;
;
;
DECFSZ COUNTER
BRA
WRITE_BYTE_TO_HREGS
get low byte of buffer data
present data to table latch
write data, perform a short write
to internal TBLWT holding register.
loop until buffers are full
PROGRAM_MEMORY
Required
Sequence
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
EECON1,
WREN
GIE
; write 55h
WR
GIE
WREN
DECFSZ WRITE_COUNTER
BRA
RESTART_BUFFER
DS39775C-page 104
; enable write to memory
; disable interrupts
;
;
;
;
write 0AAh
start program (CPU stall)
re-enable interrupts
disable write to memory
; done with one write cycle
; if not done replacing the erase block
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
6.5.2
FLASH PROGRAM MEMORY WRITE
SEQUENCE (WORD PRORAMMING).
3.
The PIC18F87J10 family of devices have a feature that
allows programming a single word (two bytes). This
feature is enabled when the WPROG bit is set. If the
memory location is already erased, the following
sequence is required to enable this feature:
1.
2.
4.
5.
6.
7.
8.
Load the Table Pointer register with the address
of the data to be written. (It must be an even
address.)
Write the 2 bytes into the holding registers by
performing table writes. (Do not post-increment
on the second table write.)
EXAMPLE 6-4:
9.
Set the WREN bit (EECON1) to enable
writes and the WPROG bit (EECON1) to
select Word Write mode.
Disable interrupts.
Write 55h to EECON2.
Write AAh to EECON2.
Set the WR bit. This will begin the write cycle.
The CPU will stall for duration of the write for TIW
(see parameter D133A).
Re-enable interrupts.
SINGLE WORD WRITE TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
; Load TBLPTR with the base address
MOVWF
TBLPTRL
MOVLW
MOVWF
TBLWT*+
MOVLW
MOVWF
TBLWT*
DATA0
TABLAT
; LSB of word to be written
DATA1
TABLAT
; MSB of word to be written
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
BCF
EECON1,
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
EECON1,
EECON1,
; The table pointer must be loaded with an even
address
; The last table write must not increment the table
pointer! The table pointer needs to point to the
MSB before starting the write operation.
PROGRAM_MEMORY
Required
Sequence
© 2009 Microchip Technology Inc.
WPROG
WREN
GIE
; enable single word write
; enable write to memory
; disable interrupts
; write 55h
WR
GIE
WPROG
WREN
;
;
;
;
;
write 0AAh
start program (CPU stall)
re-enable interrupts
disable single word write
disable write to memory
DS39775C-page 105
PIC18F87J50 FAMILY
6.5.3
6.6
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.4
Flash Program Operation During
Code Protection
See Section 25.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 6-2:
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Name
Bit 7
Bit 6
Bit 5
TBLPTRU
—
—
bit 21
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page:
Program Memory Table Pointer Upper Byte (TBLPTR)
61
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR)
61
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR)
61
TABLAT
61
Program Memory Table Latch
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
EECON2
Program Memory Control Register 2 (not a physical register)
EECON1
—
—
WPROG
INT0IE
FREE
RBIE
WRERR
TMR0IF
WREN
INT0IF
RBIF
61
63
WR
—
63
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash program memory access.
DS39775C-page 106
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
7.0
EXTERNAL MEMORY BUS
Note:
The External Memory Bus
implemented on 64-pin devices.
is
not
The External Memory Bus (EMB) allows the device to
access external memory devices (such as Flash,
EPROM, SRAM, etc.) as program or data memory. It
supports both 8 and 16-Bit Data Width modes and
three address widths of up to 20 bits.
TABLE 7-1:
The bus is implemented with 28 pins, multiplexed
across four I/O ports. Three ports (PORTD, PORTE
and PORTH) are multiplexed with the address/data bus
for a total of 20 available lines, while PORTJ is
multiplexed with the bus control signals.
A list of the pins and their functions is provided in
Table 7-1.
PIC18F87J50 FAMILY EXTERNAL BUS – I/O PORT FUNCTIONS
Name
Port
Bit
External Memory Bus Function
RD0/AD0
PORTD
0
Address bit 0 or Data bit 0
RD1/AD1
PORTD
1
Address bit 1 or Data bit 1
RD2/AD2
PORTD
2
Address bit 2 or Data bit 2
RD3/AD3
PORTD
3
Address bit 3 or Data bit 3
RD4/AD4
PORTD
4
Address bit 4 or Data bit 4
RD5/AD5
PORTD
5
Address bit 5 or Data bit 5
RD6/AD6
PORTD
6
Address bit 6 or Data bit 6
RD7/AD7
PORTD
7
Address bit 7 or Data bit 7
RE0/AD8
PORTE
0
Address bit 8 or Data bit 8
RE1/AD9
PORTE
1
Address bit 9 or Data bit 9
RE2/AD10
PORTE
2
Address bit 10 or Data bit 10
RE3/AD11
PORTE
3
Address bit 11 or Data bit 11
RE4/AD12
PORTE
4
Address bit 12 or Data bit 12
RE5/AD13
PORTE
5
Address bit 13 or Data bit 13
RE6/AD14
PORTE
6
Address bit 14 or Data bit 14
RE7/AD15
PORTE
7
Address bit 15 or Data bit 15
RH0/A16
PORTH
0
Address bit 16
RH1/A17
PORTH
1
Address bit 17
RH2/A18
PORTH
2
Address bit 18
RH3/A19
PORTH
3
Address bit 19
RJ0/ALE
PORTJ
0
Address Latch Enable (ALE) Control pin
RJ1/OE
PORTJ
1
Output Enable (OE) Control pin
RJ2/WRL
PORTJ
2
Write Low (WRL) Control pin
RJ3/WRH
PORTJ
3
Write High (WRH) Control pin
RJ4/BA0
PORTJ
4
Byte Address bit 0 (BA0)
RJ5/CE
PORTJ
5
Chip Enable (CE) Control pin
RJ6/LB
PORTJ
6
Lower Byte Enable (LB) Control pin
RJ7/UB
PORTJ
7
Upper Byte Enable (UB) Control pin
Note:
For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional
multiplexed features may be available on some pins.
© 2009 Microchip Technology Inc.
DS39775C-page 107
PIC18F87J50 FAMILY
7.1
External Memory Bus Control
The operation of the interface is controlled by the
MEMCON register (Register 7-1). This register is
available in all program memory operating modes
except Microcontroller mode. In this mode, the register
is disabled and cannot be written to.
The EBDIS bit (MEMCON) controls the operation
of the bus and related port functions. Clearing EBDIS
enables the interface and disables the I/O functions of
the ports, as well as any other functions multiplexed to
those pins. Setting the bit enables the I/O ports and
other functions, but allows the interface to override
everything else on the pins when an external memory
operation is required. By default, the external bus is
always enabled and disables all other I/O.
The WAIT bits allow for the addition of wait states to
external memory operations. The use of these bits is
discussed in Section 7.3 “Wait States”.
The WM bits select the particular operating mode used
when the bus is operating in 16-Bit Data Width mode.
These are discussed in more detail in Section 7.6
“16-Bit Data Width Modes”. These bits have no effect
when an 8-Bit Data Width mode is selected.
The MEMCON register (see Register 7-1) shares the
same memory space as the PR2 register and can be
alternately selected based on the designation of the
ADSHR bit in the WDTCON register (see
Register 25-9).
The operation of the EBDIS bit is also influenced by the
program memory mode being used. This is discussed
in more detail in Section 7.5 “Program Memory
Modes and the External Memory Bus”.
REGISTER 7-1:
MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
EBDIS
—
WAIT1
WAIT0
—
—
WM1
WM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
x = Bit is unknown
EBDIS: External Bus Disable bit
1 = External bus enabled when microcontroller accesses external memory; otherwise, all external bus
drivers are mapped as I/O ports
0 = External bus always enabled, I/O ports are disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
WAIT1:WAIT0: Table Reads and Writes Bus Cycle Wait Count bits
11 = Table reads and writes will wait 0 TCY
10 = Table reads and writes will wait 1 TCY
01 = Table reads and writes will wait 2 TCY
00 = Table reads and writes will wait 3 TCY
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
WM1:WM0: TBLWT Operation with 16-Bit Data Bus Width Select bits
1x = Word Write mode: TABLAT word output, WRH active when TABLAT is written
01 = Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB) will activate
00 = Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate
DS39775C-page 108
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
7.2
Address and Data Width
7.2.1
The PIC18F87J10 family of devices can be independently configured for different address and data widths
on the same memory bus. Both address and data width
are set by Configuration bits in the CONFIG3L register.
As Configuration bits, this means that these options
can only be configured by programming the device and
are not controllable in software.
The BW bit selects an 8-bit or 16-bit data bus width.
Setting this bit (default) selects a data width of 16 bits.
The EMB1:EMB0 bits determine both the program
memory operating mode and the address bus width.
The available options are 20-bit, 16-bit and 12-bit, as
well as Microcontroller mode (external bus disabled).
Selecting a 16-bit or 12-bit width makes a corresponding number of high-order lines available for I/O
functions. These pins are no longer affected by the
setting of the EBDIS bit. For example, selecting a
16-Bit Addressing mode (EMB1:EMB0 = 01) disables
A19:A16 and allows PORTH to function without
interruptions from the bus. Using the smaller address
widths allows users to tailor the memory bus to the size
of the external memory space for a particular design
while freeing up pins for dedicated I/O operation.
Because the EMB bits have the effect of disabling pins
for memory bus operations, it is important to always
select an address width at least equal to the data width.
If a 12-bit address width is used with a 16-bit data
width, the upper four bits of data will not be available on
the bus.
All combinations of address and data widths require
multiplexing of address and data information on the
same lines. The address and data multiplexing, as well
as I/O ports made available by the use of smaller
address widths, are summarized in Table 7-2.
TABLE 7-2:
Data Width
By default, the address presented on the external bus
is the value of the PC. In practical terms, this means
that addresses in the external memory device below
the top of on-chip memory are unavailable to the microcontroller. To access these physical locations, the glue
logic between the microcontroller and the external
memory must somehow translate addresses.
To simplify the interface, the external bus offers an
extension of Extended Microcontroller mode that
automatically performs address shifting. This feature is
controlled by the EASHFT Configuration bit. Setting
this bit offsets addresses on the bus by the size of the
microcontroller’s on-chip program memory and sets
the bottom address at 0000h. This allows the device to
use the entire range of physical addresses of the
external memory.
7.2.2
This addressing mode is available in both 8-Bit and
certain 16-Bit Data Width modes. Additional details are
provided in Section 7.6.3 “16-Bit Byte Select Mode”
and Section 7.7 “8-Bit Data Width Mode”.
ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS
Address Width
Multiplexed Data and
Address Lines (and
Corresponding Ports)
16-bit
AD7:AD0
(PORTD)
20-bit
16-bit
16-bit
21-BIT ADDRESSING
As an extension of 20-bit address width operation, the
External Memory Bus can also fully address a 2-Mbyte
memory space. This is done by using the Bus Address
bit 0 (BA0) control line as the Least Significant bit of the
address. The UB and LB control signals may also be
used with certain memory devices to select the upper
and lower bytes within a 16-bit wide data word.
12-bit
8-bit
ADDRESS SHIFTING ON THE
EXTERNAL BUS
20-bit
© 2009 Microchip Technology Inc.
AD15:AD0
(PORTD,
PORTE)
Address Only
Lines (and
Corresponding Ports)
Ports Available
for I/O
AD11:AD8
(PORTE)
PORTE,
All of PORTH
AD15:AD8
(PORTE)
All of PORTH
A19:A16, AD15:AD8
(PORTH,
PORTE)
—
—
All of PORTH
A19:A16
(PORTH)
—
DS39775C-page 109
PIC18F87J50 FAMILY
7.3
Wait States
While it may be assumed that external memory devices
will operate at the microcontroller clock rate, this is
often not the case. In fact, many devices require longer
times to write or retrieve data than the time allowed by
the execution of table read or table write operations.
To compensate for this, the External Memory Bus can
be configured to add a fixed delay to each table operation using the bus. Wait states are enabled by setting
the WAIT Configuration bit. When enabled, the amount
of delay is set by the WAIT1:WAIT0 bits
(MEMCON). The delay is based on multiples of
microcontroller instruction cycle time and are added
following the instruction cycle when the table operation
is executed. The range is from no delay to 3 TCY
(default value).
7.4
Port Pin Weak Pull-ups
With the exception of the upper address lines,
A19:A16, the pins associated with the External Memory
Bus are equipped with weak pull-ups. The pull-ups are
controlled by the upper three bits of the PORTG
register (PORTG). They are named RDPU,
REPU and RJPU and control pull-ups on PORTD,
PORTE and PORTJ, respectively. Setting one of these
bits enables the corresponding pull-ups for that port. All
pull-ups are disabled by default on all device Resets.
functions. When EBDIS = 0, the pins function as the
external bus. When EBDIS = 1, the pins function as I/O
ports.
If the device fetches or accesses external memory
while EBDIS = 1, the pins will switch to external bus. If
the EBDIS bit is set by a program executing from external memory, the action of setting the bit will be delayed
until the program branches into the internal memory. At
that time, the pins will change from external bus to I/O
ports.
If the device is executing out of internal memory when
EBDIS = 0, the memory bus address/data and control
pins will not be active. They will go to a state where the
active address/data pins are tri-state; the CE, OE,
WRH, WRL, UB and LB signals are ‘1’ and ALE and
BA0 are ‘0’. Note that only those pins associated with
the current address width are forced to tri-state; the
other pins continue to function as I/O. In the case of
16-bit address width, for example, only AD
(PORTD and PORTE) are affected; A19:A16
(PORTH) continue to function as I/O.
In all external memory modes, the bus takes priority
over any other peripherals that may share pins with it.
This includes the Parallel Master Port and serial
communication modules which would otherwise take
priority over the I/O port.
7.6
16-Bit Data Width Modes
In Extended Microcontroller mode, the port pull-ups
can be useful in preserving the memory state on the
external bus while the bus is temporarily disabled
(EBDIS = ‘1’).
In 16-Bit Data Width mode, the external memory
interface can be connected to external memories in
three different configurations:
7.5
• 16-Bit Byte Write
• 16-Bit Word Write
• 16-Bit Byte Select
Program Memory Modes and the
External Memory Bus
The PIC18F87J10 family of devices is capable of
operating in one of two program memory modes, using
combinations of on-chip and external program memory.
The functions of the multiplexed port pins depend on
the program memory mode selected, as well as the
setting of the EBDIS bit.
In Microcontroller Mode, the bus is not active and the
pins have their port functions only. Writes to the
MEMCOM register are not permitted. The Reset value
of EBDIS (‘0’) is ignored and EMB pins behave as I/O
ports.
In Extended Microcontroller Mode, the external
program memory bus shares I/O port functions on the
pins. When the device is fetching or doing table
read/table write operations on the external program
memory space, the pins will have the external bus
function.
If the device is fetching and accessing internal program
memory locations only, the EBDIS control bit will
change the pins from external memory to I/O port
DS39775C-page 110
The configuration to be used is determined by the
WM1:WM0 bits
in the MEMCON register
(MEMCON). These three different configurations
allow the designer maximum flexibility in using both
8-bit and 16-bit devices with 16-bit data.
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits, AD, are available on the external memory interface bus. Following
the address latch, the Output Enable signal (OE) will
enable both bytes of program memory at once to form
a 16-bit instruction word. The Chip Enable signal (CE)
is active at any time that the microcontroller accesses
external memory, whether reading or writing; it is
inactive (asserted high) whenever the device is in
Sleep mode.
In Byte Select mode, JEDEC standard Flash memories
will require BA0 for the byte address line and one I/O
line to select between Byte and Word mode. The other
16-bit modes do not need BA0. JEDEC standard static
RAM memories will use the UB or LB signals for byte
selection.
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
7.6.1
16-BIT BYTE WRITE MODE
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
Figure 7-1 shows an example of 16-Bit Byte Write
mode for PIC18F87J10 family devices. This mode is
used for two separate 8-bit memories connected for
16-bit operation. This generally includes basic EPROM
and Flash devices. It allows table writes to byte-wide
external memories.
FIGURE 7-1:
16-BIT BYTE WRITE MODE EXAMPLE
D
PIC18F87J50
AD
(MSB)
373
A
D
(LSB)
A
A
D
D
CE
AD
373
OE
D
CE
WR(2)
OE
WR(2)
ALE
A(1)
CE
OE
WRH
WRL
Address Bus
Data Bus
Control Lines
Note 1:
2:
Upper order address lines are used only for 20-bit address widths.
This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
© 2009 Microchip Technology Inc.
DS39775C-page 111
PIC18F87J50 FAMILY
7.6.2
16-BIT WORD WRITE MODE
Figure 7-2 shows an example of 16-Bit Word Write
mode for PIC18F87J10 family devices. This mode is
used for word-wide memories which include some of
the EPROM and Flash-type memories. This mode
allows opcode fetches and table reads from all forms of
16-bit memory and table writes to any type of
word-wide external memories. This method makes a
distinction between TBLWT cycles to even or odd
addresses.
During a TBLWT cycle to an even address
(TBLPTR = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is
tri-stated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 7-2:
During a TBLWT cycle to an odd address
(TBLPTR = 1), the TABLAT data is presented on
the upper byte of the AD15:AD0 bus. The contents of
the holding latch are presented on the lower byte of the
AD15:AD0 bus.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSb of the TBLPTR, but it is left unconnected.
Instead, the UB and LB signals are active to select both
bytes. The obvious limitation to this method is that the
table write must be done in pairs on a specific word
boundary to correctly write a word location.
16-BIT WORD WRITE MODE EXAMPLE
PIC18F87J50
AD
373
A
D
AD
A
JEDEC Word
EPROM Memory
D
CE
OE
WR(2)
373
ALE
A(1)
CE
OE
WRH
Address Bus
Data Bus
Control Lines
Note 1:
2:
Upper order address lines are used only for 20-bit address widths.
This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
DS39775C-page 112
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
7.6.3
16-BIT BYTE SELECT MODE
Figure 7-3 shows an example of 16-Bit Byte Select
mode. This mode allows table write operations to
word-wide external memories with byte selection
capability. This generally includes both word-wide
Flash and SRAM devices.
During a TBLWT cycle, the TABLAT data is presented
on the upper and lower byte of the AD15:AD0 bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written, based on the Least
Significant bit of the TBLPTR register.
FIGURE 7-3:
Flash and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
16-BIT BYTE SELECT MODE EXAMPLE
PIC18F87J50
AD
373
A
A
JEDEC Word
FLASH Memory
D
D
138(3)
AD
373
CE
A0
BYTE/WORD
ALE
OE WR(1)
A(2)
OE
WRH
WRL
A
A
BA0
JEDEC Word
SRAM Memory
I/O
D
LB
CE
LB
UB
UB
D
OE WR(1)
Address Bus
Data Bus
Control Lines
Note 1:
This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
2:
Upper order address lines are used only for 20-bit address width.
3:
Demultiplexing is only required when multiple memory devices are accessed.
© 2009 Microchip Technology Inc.
DS39775C-page 113
PIC18F87J50 FAMILY
7.6.4
16-BIT MODE TIMING
The presentation of control signals on the External
Memory Bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 7-4 and Figure 7-5.
FIGURE 7-4:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED
MICROCONTROLLER MODE)
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
0Ch
A
CF33h
AD
9256h
CE
ALE
OE
Memory
Cycle
Opcode Fetch
TBLRD *
from 000100h
Opcode Fetch
MOVLW 55h
from 000102h
TBLRD 92h
from 199E67h
Opcode Fetch
ADDLW 55h
from 000104h
Instruction
Execution
INST(PC – 2)
TBLRD Cycle 1
TBLRD Cycle 2
MOVLW
FIGURE 7-5:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED
MICROCONTROLLER MODE)
Q1
Q2
Q4
Q1
Q2
3AAAh
Q3
Q4
Q1
00h
00h
A
AD
Q3
0003h
3AABh
0E55h
CE
ALE
OE
Memory
Cycle
Instruction
Execution
DS39775C-page 114
Opcode Fetch
SLEEP
from 007554h
Opcode Fetch
MOVLW 55h
from 007556h
INST(PC – 2)
SLEEP
Sleep Mode, Bus Inactive
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
7.7
8-Bit Data Width Mode
The Address Latch Enable (ALE) pin indicates that the
address bits, AD, are available on the external
memory interface bus. The Output Enable signal (OE)
will enable one byte of program memory for a portion of
the instruction cycle, then BA0 will change and the
second byte will be enabled to form the 16-bit instruction word. The Least Significant bit of the address, BA0,
must be connected to the memory devices in this
mode. The Chip Enable signal (CE) is active at any
time that the microcontroller accesses external
memory, whether reading or writing. It is inactive
(asserted high) whenever the device is in Sleep mode.
In 8-Bit Data Width mode, the External Memory Bus
operates only in Multiplexed mode; that is, data shares
the 8 Least Significant bits of the address bus.
Figure 7-6 shows an example of 8-Bit Multiplexed
mode for 80-pin devices. This mode is used for a single
8-bit memory connected for 16-bit operation. The
instructions will be fetched as two 8-bit bytes on a
shared data/address bus. The two bytes are sequentially fetched within one instruction cycle (TCY).
Therefore, the designer must choose external memory
devices according to timing calculations based on
1/2 TCY (2 times the instruction rate). For proper memory speed selection, glue logic propagation delay times
must be considered, along with setup and hold times.
FIGURE 7-6:
This generally includes basic EPROM and Flash
devices. It allows table writes to byte-wide external
memories.
8-BIT MULTIPLEXED MODE EXAMPLE
D
PIC18F87J50
AD
ALE
373
A
A
A0
D
D
AD(1)
CE
A(1)
OE
WR(2)
BA0
CE
OE
WRL
Address Bus
Data Bus
Control Lines
Note 1:
2:
Upper order address bits are only used for 20-bit address width. The upper AD byte is used for all
address widths except 8-bit.
This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
© 2009 Microchip Technology Inc.
DS39775C-page 115
PIC18F87J50 FAMILY
7.7.1
8-BIT MODE TIMING
The presentation of control signals on the External
Memory Bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 7-7 and Figure 7-8.
FIGURE 7-7:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED
MICROCONTROLLER MODE)
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
A
0Ch
AD
CFh
33h
AD
Q4
Q1
Q2
Q3
Q4
92h
CE
ALE
OE
Memory
Cycle
Instruction
Execution
FIGURE 7-8:
Opcode Fetch
TBLRD *
from 000100h
Opcode Fetch
MOVLW 55h
from 000102h
TBLRD 92h
from 199E67h
Opcode Fetch
ADDLW 55h
from 000104h
INST(PC – 2)
TBLRD Cycle 1
TBLRD Cycle 2
MOVLW
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED
MICROCONTROLLER MODE)
Q1
Q2
Q4
Q1
Q2
3Ah
AD
AAh
00h
Q3
Q4
Q1
00h
00h
A
AD
Q3
3Ah
03h
ABh
0Eh
55h
BA0
CE
ALE
OE
Memory
Cycle
Instruction
Execution
DS39775C-page 116
Opcode Fetch
SLEEP
from 007554h
Opcode Fetch
MOVLW 55h
from 007556h
INST(PC – 2)
SLEEP
Sleep Mode, Bus Inactive
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
7.8
Operation in Power-Managed
Modes
In alternate, power-managed Run modes, the external
bus continues to operate normally. If a clock source
with a lower speed is selected, bus operations will run
at that speed. In these cases, excessive access times
for the external memory may result if wait states have
been enabled and added to external memory operations. If operations in a lower power Run mode are
anticipated, users should provide in their applications
for adjusting memory access times at the lower clock
speeds.
© 2009 Microchip Technology Inc.
In Sleep and Idle modes, the microcontroller core does
not need to access data; bus operations are
suspended. The state of the external bus is frozen, with
the address/data pins and most of the control pins holding at the same state they were in when the mode was
invoked. The only potential changes are the CE, LB
and UB pins, which are held at logic high.
DS39775C-page 117
PIC18F87J50 FAMILY
NOTES:
DS39775C-page 118
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
8.0
8 x 8 HARDWARE MULTIPLIER
8.1
Introduction
EXAMPLE 8-1:
MOVF
MULWF
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
ARG1, W
ARG2
EXAMPLE 8-2:
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applications previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.
8.2
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
ARG1, W
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH, F
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
Operation
;
; ARG1 * ARG2 ->
; PRODH:PRODL
;
;
;
;
;
ARG1 * ARG2 ->
PRODH:PRODL
Test Sign Bit
PRODH = PRODH
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
Example 8-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
TABLE 8-1:
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Routine
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
Multiply Method
Program
Memory
(Words)
Cycles
(Max)
@ 48 MHz
@ 10 MHz
@ 4 MHz
Without hardware multiply
13
69
5.7 μs
27.6 μs
69 μs
Time
Hardware multiply
1
1
83.3 ns
400 ns
1 μs
Without hardware multiply
33
91
7.5 μs
36.4 μs
91 μs
Hardware multiply
6
6
500 ns
2.4 μs
6 μs
Without hardware multiply
21
242
20.1 μs
96.8 μs
242 μs
Hardware multiply
28
28
2.3 μs
11.2 μs
28 μs
Without hardware multiply
52
254
21.6 μs
102.6 μs
254 μs
Hardware multiply
35
40
3.3 μs
16.0 μs
40 μs
© 2009 Microchip Technology Inc.
DS39775C-page 119
PIC18F87J50 FAMILY
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 8-1:
RES3:RES0
=
=
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L)
EQUATION 8-2:
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
= (ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L) +
(-1 • ARG2H • ARG1H:ARG1L • 216) +
(-1 • ARG1H • ARG2H:ARG2L • 216)
EXAMPLE 8-4:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
ARG1L * ARG2H->
PRODH:PRODL
Add cross
products
ARG1H * ARG2L->
PRODH:PRODL
Add cross
products
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
DS39775C-page 120
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
;
;
;
;
;
;
ARG1L * ARG2H ->
PRODH:PRODL
Add cross
products
;
;
;
;
;
;
;
;
;
;
;
MOVF
MULWF
;
;
;
;
;
;
;
;
;
;
16 x 16 SIGNED
MULTIPLY ROUTINE
;
;
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
;
;
;
;
;
;
;
;
;
ARG1H * ARG2L ->
PRODH:PRODL
Add cross
products
;
;
SIGN_ARG1
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
;
CONT_CODE
:
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
9.0
INTERRUPTS
Members of the PIC18F87J10 family of devices have
multiple interrupt sources and an interrupt priority
feature that allows most interrupt sources to be
assigned a high-priority level or a low-priority level. The
high-priority interrupt vector is at 0008h and the
low-priority interrupt vector is at 0018h. High-priority
interrupt events will interrupt any low-priority interrupts
that may be in progress.
There are thirteen registers which are used to control
interrupt operation. These registers are:
•
•
•
•
•
•
•
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2, PIR3
PIE1, PIE2, PIE3
IPR1, IPR2, IPR3
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the
assembler/compiler to automatically take care of the
placement of these bits within the specified register.
In general, interrupt sources have three bits to control
their operation. They are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 0008h or 0018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
© 2009 Microchip Technology Inc.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC® mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON is the PEIE bit
which enables/disables all peripheral interrupt sources.
INTCON is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
0008h in Compatibility mode.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High-priority interrupt sources can interrupt a
low-priority interrupt. Low-priority interrupts are not
processed while high-priority interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bits must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
For external interrupt events, such as the INTx pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
Note:
Do not use the MOVFF instruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
DS39775C-page 121
PIC18F87J50 FAMILY
FIGURE 9-1:
PIC18F87J50 FAMILY INTERRUPT LOGIC
Wake-up if in
Idle or Sleep modes
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
Interrupt to CPU
Vector to Location
0008h
GIE/GIEH
IPEN
PIR3
PIE3
IPR3
IPEN
PEIE/GIEL
IPEN
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
DS39775C-page 122
Interrupt to CPU
Vector to Location
0018h
IPEN
GIE/GIEH
PEIE/GIEL
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
9.1
INTCON Registers
Note:
The INTCON registers are readable and writable
registers which contain various enable, priority and flag
bits.
REGISTER 9-1:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high-priority interrupts
0 = Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low-priority peripheral interrupts
0 = Disables all low-priority peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note 1:
A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and
allow the bit to be cleared.
© 2009 Microchip Technology Inc.
DS39775C-page 123
PIC18F87J50 FAMILY
REGISTER 9-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5
INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4
INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3
INTEDG3: External Interrupt 3 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 2
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
INT3IP: INT3 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
DS39775C-page 124
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
REGISTER 9-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
INT3IE: INT3 External Interrupt Enable bit
1 = Enables the INT3 external interrupt
0 = Disables the INT3 external interrupt
bit 4
INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2
INT3IF: INT3 External Interrupt Flag bit
1 = The INT3 external interrupt occurred (must be cleared in software)
0 = The INT3 external interrupt did not occur
bit 1
INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
© 2009 Microchip Technology Inc.
DS39775C-page 125
PIC18F87J50 FAMILY
9.2
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
REGISTER 9-4:
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON).
2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
PMPIF
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PMPIF: Parallel Master Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 =No read or write has occurred
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5
RC1IF: EUSART1 Receive Interrupt Flag bit
1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0 = The EUSART1 receive buffer is empty
bit 4
TX1IF: EUSART1 Transmit Interrupt Flag bit
1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0 = The EUSART1 transmit buffer is full
bit 3
SSP1IF: Master Synchronous Serial Port Interrupt Flag bit (MSSP1 module)
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2
CCP1IF: ECCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
DS39775C-page 126
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
REGISTER 9-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OSCFIF
CM2IF
CM1IF
USBIF
BCL1IF
LVDIF
TMR3IF
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OSCFIF: Oscillator Fail Interrupt Flag bit
1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = Device clock operating
bit 6
CM2IF: Comparator 2 Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 5
CM1IF: Comparator 1 Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 4
USBIF: USB Interrupt Flag bit
1 = USB has requested an interrupt (must be cleared in software)
0 = No USB interrupt request
bit 3
BCL1IF: Bus Collision Interrupt Flag bit (MSSP1 module)
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 2
LVDIF: Low-Voltage Detect Interrupt Flag bit
1 = A low-voltage condition occurred (must be cleared in software)
0 = Device VDDCORE voltage is above the regulator low-voltage trip point (above 2.45V)
bit 1
TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 0
CCP2IF: ECCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
© 2009 Microchip Technology Inc.
DS39775C-page 127
PIC18F87J50 FAMILY
REGISTER 9-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 6
BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module)
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 5
RC2IF: EUSART2 Receive Interrupt Flag bit
1 = The EUSART2 receive buffer, RCREG2, is full (cleared when RCREG2 is read)
0 = The EUSART2 receive buffer is empty
bit 4
TX2IF: EUSART2 Transmit Interrupt Flag bit
1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared when TXREG2 is written)
0 = The EUSART2 transmit buffer is full
bit 3
TMR4IF: TMR4 to PR4 Match Interrupt Flag bit
1 = TMR4 to PR4 match occurred (must be cleared in software)
0 = No TMR4 to PR4 match occurred
bit 2
CCP5IF: CCP5 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
CCP4IF: CCP4 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 0
CCP3IF: ECCP3 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
DS39775C-page 128
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 9-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMPIE
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PMPIE: Parallel Master Port Read/Write Interrupt Enable bit
1 = Enables the PM read/write interrupt
0 = Disables the PM read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5
RC1IE: EUSART1 Receive Interrupt Enable bit
1 = Enables the EUSART1 receive interrupt
0 = Disables the EUSART1 receive interrupt
bit 4
TX1IE: EUSART1 Transmit Interrupt Enable bit
1 = Enables the EUSART1 transmit interrupt
0 = Disables the EUSART1 transmit interrupt
bit 3
SSP1IE: Master Synchronous Serial Port Interrupt Enable bit (MSSP1 module)
1 = Enables the MSSP1 interrupt
0 = Disables the MSSP1 interrupt
bit 2
CCP1IE: ECCP1 Interrupt Enable bit
1 = Enables the ECCP1 interrupt
0 = Disables the ECCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
© 2009 Microchip Technology Inc.
DS39775C-page 129
PIC18F87J50 FAMILY
REGISTER 9-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OSCFIE
CM2IE
CM1IE
USBIE
BCL1IE
LVDIE
TMR3IE
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6
CM2IE: Comparator 2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5
CM1IE: Comparator 1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4
USBIE: USB Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3
BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module)
1 = Enabled
0 = Disabled
bit 2
LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
CCP2IE: ECCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
DS39775C-page 130
x = Bit is unknown
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
REGISTER 9-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6
BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
1 = Enabled
0 = Disabled
bit 5
RC2IE: EUSART2 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4
TX2IE: EUSART2 Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
CCP5IE: CCP5 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
CCP4IE: CCP4 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
CCP3IE: ECCP3 Interrupt Enable bit
1 = Enabled
0 = Disabled
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS39775C-page 131
PIC18F87J50 FAMILY
9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 9-10:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PMPIP
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PMPIP: Parallel Master Port Read/Write Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RC1IP: EUSART1 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TX1IP: EUSART1 Transmit Interrupt Priority bit
x = Bit is unknown
1 = High priority
0 = Low priority
bit 3
SSP1IP: Master Synchronous Serial Port Interrupt Priority bit (MSSP1 module)
1 = High priority
0 = Low priority
bit 2
CCP1IP: ECCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
DS39775C-page 132
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
REGISTER 9-11:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
OSCFIP
CM2IP
CM1IP
USBIP
BCL1IP
LVDIP
TMR3IP
CCP2IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
CM2IP: Comparator 2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
C12IP: Comparator 1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
USBIP: USB Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module)
1 = High priority
0 = Low priority
bit 2
LVDIP: Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
CCP2IP: ECCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS39775C-page 133
PIC18F87J50 FAMILY
REGISTER 9-12:
IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module)
1 = High priority
0 = Low priority
bit 5
RC2IP: EUSART2 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TX2IP: EUSART2 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
TMR4IE: TMR4 to PR4 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP5IP: CCP5 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
CCP4IP: CCP4 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
CCP3IP: ECCP3 Interrupt Priority bit
1 = High priority
0 = Low priority
DS39775C-page 134
x = Bit is unknown
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
9.5
RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
modes. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 9-13:
RCON: RESET CONTROL REGISTER
R/W-0
U-0
R/W-1
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
—
CM
RI
TO
PD
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
Unimplemented: Read as ‘0’
bit 5
CM: Configuration Mismatch Flag bit
For details of bit operation, see Register 4-1.
bit 4
RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-1.
bit 3
TO: Watchdog Timer Time-out Flag bit
For details of bit operation, see Register 4-1.
bit 2
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 4-1.
bit 1
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-1.
bit 0
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS39775C-page 135
PIC18F87J50 FAMILY
9.6
INTx Pin Interrupts
9.7
TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Flag bit, INTxIF, must be cleared in software in
the Interrupt Service Routine before re-enabling the
interrupt.
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh → 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON). Interrupt priority for Timer0 is
determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2). See Section 12.0
“Timer0 Module” for further details on the Timer0
module.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from the power-managed
modes if bit INTxIE was set prior to going into the
power-managed modes. If the Global Interrupt Enable
bit, GIE, is set, the processor will branch to the interrupt
vector following wake-up.
9.8
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the interrupt priority bits,
INT1IP (INTCON3), INT2IP (INTCON3) and
INT3IP (INTCON2). There is no priority bit
associated with INT0. It is always a high-priority
interrupt source.
EXAMPLE 9-1:
An input change on PORTB sets flag bit, RBIF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2).
9.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack. If a fast
return from interrupt is not used (see Section 5.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 9-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
W_TEMP
MOVFF
STATUS, STATUS_TEMP
MOVFF
BSR, BSR_TEMP
;
; USER ISR CODE
;
MOVFF
BSR_TEMP, BSR
MOVF
W_TEMP, W
MOVFF
STATUS_TEMP, STATUS
DS39775C-page 136
PORTB Interrupt-on-Change
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
10.0
I/O PORTS
10.1
Depending on the device selected and features
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three memory-mapped registers for its
operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Output Latch register)
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register writes to
the output latch (LAT) register.
Setting a TRIS bit (= 1) makes the corresponding
PORT pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRIS bit
(= 0) makes the corresponding PORT pin an output
(i.e., put the contents of the corresponding LAT bit on
the selected pin).
I/O Port Pin Capabilities
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than VDD input levels.
10.1.1
INPUT PINS AND VOLTAGE
CONSIDERATIONS
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V, a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
(such as A/D and comparator inputs) can only tolerate
voltages up to VDD. Voltage excursions beyond VDD on
these pins should be avoided.
Table 10-1 summarizes the input capabilities. Refer to
Section 28.0 “Electrical Characteristics” for more
details.
TABLE 10-1:
Port or Pin
The Data Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
PORT register.
PORTC
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
PORTB
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
PORTA
INPUT VOLTAGE LEVELS
Tolerated
Input
Description
VDD
Only VDD input levels
tolerated.
5.5V
Tolerates input levels
above VDD, useful for
most standard logic.
PORTF
PORTH(1)
PORTC
PORTD
PORTE
PORTF
PORTG
RD LAT
Data
Bus
WR LAT
or PORT
PORTH(1)
D
PORTJ(1)
Q
I/O pin
Data Latch
D
WR TRIS
Note 1:
CK
10.1.2
Q
CK
TRIS Latch
Input
Buffer
RD TRIS
Q
D
ENEN
RD PORT
© 2009 Microchip Technology Inc.
These ports are not available on 64-pin
devices.
PIN OUTPUT DRIVE
When used as digital I/O, the output pin drive strengths
vary for groups of pins intended to meet the needs for
a variety of applications. In general, there are three
classes of output pins in terms of drive capability.
PORTB and PORTC, as well as PORTA, are
designed to drive higher current loads, such as LEDs.
PORTD, PORTE and PORTJ are capable of driving
digital circuits associated with external memory
devices. They can also drive LEDs, but only those with
smaller current requirements. PORTF, PORTG and
PORTH, along with PORTA, have the lowest
drive level, but are capable of driving normal digital
circuit loads with a high input impedance.
DS39775C-page 137
PIC18F87J50 FAMILY
Table 10-2 summarizes the output capabilities of the
ports. Refer to the “Absolute Maximum Ratings” in
Section 28.0 “Electrical Characteristics” for more
details.
TABLE 10-2:
Port
OUTPUT DRIVE LEVELS
Drive
PORTA
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor
provided by the user to a higher voltage level, up to
5.5V (Figure 10-2). When a digital logic high signal is
output, it is pulled up to the higher voltage level.
Description
FIGURE 10-2:
Minimum Intended for indication.
USING THE OPEN-DRAIN
OUTPUT (USART SHOWN
AS EXAMPLE)
PORTF
PORTG
PORTH
PORTD
PIC18F87J50
Medium
PORTE
PORTJ(1)
PORTB
High
PORTC
Note 1:
10.1.3
Sufficient drive levels for
external memory interfacing
as well as indication.
TXX
(at logic ‘1’)
5V
These ports are not available on 64-pin
devices.
PULL-UP CONFIGURATION
The pull-ups are enabled with a single bit for each of the
ports: RBPU (INTCON2) for PORTB, and RDPU,
REPU and RJPU (PORTG) for the other ports.
10.1.4
VDD
Suitable for direct LED drive
levels.
Four of the I/O ports (PORTB, PORTD, PORTE and
PORTJ) implement configurable weak pull-ups on all
pins. These are internal pull-ups that allow floating
digital input signals to be pulled to a consistent level,
without the use of external resistors.
Note:
+5V
3.3V
(1)
RJPU is implemented on 80-pin devices
only.
OPEN-DRAIN OUTPUTS
The output pins for several peripherals are also
equipped with a configurable open-drain output option.
This allows the peripherals to communicate with
external digital logic operating at a higher voltage level,
without the use of level translators.
10.1.5
TTL INPUT BUFFER OPTION
Many of the digital I/O ports use Schmitt Trigger (ST)
input buffers. While this form of buffering works well
with many types of input, some applications may
require TTL level signals to interface with external logic
devices. This is particularly true with the EMB and the
Parallel Master Port (PMP), which are particularly likely
to be interfaced to TTL level logic or memory devices.
The inputs for the PMP can be optionally configured for
TTL buffers with the PMPTTL bit in the PADCFG1 register (Register 10-4). Setting this bit configures all data
and control input pins for the PMP to use TTL buffers.
By default, these PMP inputs use the port’s ST buffers.
As with the ODCON registers, the PADCFG1 register
resides in the SFR configuration space; it shares the
same memory address as the TMR2 register.
PADCFG1 is accessed by setting the ADSHR bit
(WDTCON).
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the EUSARTs, the MSSP modules (in SPI mode) and
the CCP and ECCP modules. It is selectively enabled
by setting the open-drain control bit for the corresponding module in the ODCON registers (Register 10-1,
Register 10-2 and Register 10-3). Their configuration
is discussed in more detail with the individual port
where these peripherals are multiplexed.
The ODCON registers all reside in the SFR configuration
space, and share the same SFR addresses as the Timer1
registers (see Section 5.3.5.1 “Shared Address SFRs”
for more details). The ODCON registers are accessed by
setting the ADSHR bit (WDTCON).
DS39775C-page 138
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
REGISTER 10-1:
ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
CCP5OD
CCP4OD
ECCP3OD
ECCP2OD
ECCP1OD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-3
CCP5OD:CCP4OD: CCPx Open-Drain Output Enable bits
1 = Open-drain output on CCPx pin (Capture/PWM modes) enabled
0 = Open-drain output disabled
bit 2-0
ECCP3OD:ECCP1OD: ECCPx Open-Drain Output Enable bits
1 = Open-drain output on ECCPx pin (Capture mode) enabled
0 = Open-drain output disabled
REGISTER 10-2:
ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
U2OD
U1OD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1-0
U2OD:U1OD: EUSARTx Open-Drain Output Enable bits
1 = Open-drain output on TXx/CKx pin enabled
0 = Open-drain output disabled
REGISTER 10-3:
x = Bit is unknown
ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
SPI2OD
SPI1OD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1-0
SPI2OD:SPI1OD: SPI Open-Drain Output Enable bits
1 = Open-drain output on SDOx pin enabled
0 = Open-drain output disabled
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS39775C-page 139
PIC18F87J50 FAMILY
REGISTER 10-4:
PADCFG1: PAD CONFIGURATION CONTROL REGISTER 1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
PMPTTL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-1
Unimplemented: Read as ‘0’
bit 0
PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffers
10.2
PORTA, TRISA and
LATA Registers
PORTA is a 6-bit wide, bidirectional port. The
corresponding Data Direction register is TRISA. The
corresponding Output Latch register is LATA.
The RA4 pin is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. It is also multiplexed as the Parallel Master Port Data pin. The other
PORTA pins are multiplexed with the analog VREF+ and
VREF- inputs. The operation of pins RA5:RA0 as A/D
Converter inputs is selected by clearing or setting the
control bits in the ANCON0 register.
Note 1: The RA5 (RA5/PMD4/AN4/C2INA) pin is a
multiplexed A/D convertor, Parallel Master
Port data and also a Comparator 2 input A.
(PMP pin placement depends on the
PMPMX Configuration bit.)
2: RA5 and RA3:RA0 are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
The RA4/T0CKI pin is a Schmitt Trigger input. All other
PORTA pins have TTL input levels and full CMOS
output drivers.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally
serve as the external circuit connections for the
external (primary) oscillator circuit (HS and HSPLL
Oscillator modes), or the external clock input (EC and
ECPLL Oscillator modes). In these cases, RA6 and
RA7 are not available as digital I/O and their
corresponding TRIS and LAT bits are read as ‘0’.
For INTOSCx and INTOSCPLLx Oscillator modes
(FOSC2 Configuration bit is ‘0’), either RA7, or both
RA6 and RA7, automatically become available as digital I/O, depending on the oscillator mode selected.
When RA6 is not configured as a digital I/O, in these
cases, it provides a clock output at FOSC/4. A list of the
possible configurations for RA6 and RA7, based on
oscillator mode, is provided in Register 10-3. For these
pins, the corresponding PORTA, TRISA and LATA bits
are only defined when the pins are configured as I/O.
TABLE 10-3:
FUNCTION OF RA7:RA6 IN
INTOSC AND INTOSCPLL
MODES
Oscillator Mode
(FOSC2:FOSC0 Configuration bits)
INTOSCPLLO (011)
INTOSCPLL (010)
INTOSCO (001)
INTOSC (000)
RA6
RA7
CLKO
I/O
I/O
I/O
CLKO
I/O
I/O
I/O
Legend: CLKO = FOSC/4 clock output; I/O = digital
port.
EXAMPLE 10-1:
CLRF
CLRF
BSF
MOVLW
MOVWF
BCF
MOVLW
MOVWF
DS39775C-page 140
x = Bit is unknown
PORTA
INITIALIZING PORTA
;
;
;
LATA
;
;
WDTCON,ADSHR ;
;
1Fh
;
ANCON0
;
WDTCON,ADSHR ;
;
0CFh
;
;
;
TRISA
;
;
Initialize PORTA by
clearing output
data latches
Alternate method to
clear data latches
Enable write/read to
the shared SFR
Configure A/D
for digital inputs
Disable write/read
to the shared SFR
Value used to
initialize
data direction
Set RA as inputs,
RA as outputs
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 10-4:
Pin Name
RA0/AN0
PORTA FUNCTIONS
Function
TRIS
Setting
DIG
LATA data output; not affected by analog input.
I
TTL
PORTA data input; disabled when analog input enabled.
I
ANA
A/D input channel 0. Default input configuration on POR; does not
affect digital output.
O
DIG
LATA data output; not affected by analog input.
I
TTL
PORTA data input; disabled when analog input enabled.
AN1
0
1
1
I
ANA
A/D input channel 1. Default input configuration on POR; does not
affect digital output.
RA2
0
O
DIG
LATA data output; not affected by analog input. Disabled when
CVREF output enabled.
1
I
TTL
PORTA data input. Disabled when analog functions enabled;
disabled when CVREF output enabled.
AN2
1
I
ANA
A/D input channel 2 . Default input configuration on POR; not affected
by analog output.
VREF-
1
0
1
1
1
0
1
x
x
x
0
1
x
x
1
1
I
ANA
A/D low reference voltage input.
RA1
RA3/AN3/VREF+
RA3
AN3
VREF+
RA4/T0CKI/
PMD5
RA4
T0CKI
PMD5(1,2)
RA5/PMD4/
AN4/C2INA
RA5
PMD4(1,2)
AN4
C2INA
Legend:
Description
O
AN0
RA2/AN2/VREF-
I/O
Type
0
1
1
RA0
RA1/AN1
I/O
O
DIG
LATA data output; not affected by analog input.
I
TTL
PORTA data input; disabled when analog input enabled.
I
ANA
A/D input channel 3. Default input configuration on POR.
I
ANA
A/D high reference voltage input.
O
DIG
LATA data output.
I
ST
PORTA data input; default configuration on POR.
I
ST
Timer0 clock input.
O
DIG
Parallel Master Port data output.
Parallel Master Port data output.
I
TTL
O
DIG
LATA data output; not affected by analog input.
I
TTL
PORTA data input; disabled when analog input enabled.
O
DIG
Parallel Master Port data output.
I
TTL
Parallel Master Port data output.
I
ANA
A/D input channel 4. Default configuration on POR.
I
ANA
Comparator2 input A.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1:
2:
When PMPMX = 0.
Available on 80-pin devices only.
© 2009 Microchip Technology Inc.
DS39775C-page 141
PIC18F87J50 FAMILY
TABLE 10-5:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 6
PORTA
—
—
RA5
RA4
RA3
RA2
RA1
RA0
65
LATA
—
—
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
64
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
64
PCFG7
—
—
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
63
TRISA
(1)
ANCON0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
Bit 7
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
DS39775C-page 142
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
10.3
PORTB, TRISB and
LATB Registers
PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. All pins on
PORTB are digital only and tolerate voltages up to
5.5V.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins
(of RB7:RB4) are compared with the old value latched
on the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON).
This interrupt can wake the device from
power-managed modes. The user, in the Interrupt
Service Routine, can clear the interrupt in the following
manner:
a)
b)
Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
Clear flag bit, RBIF.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
For 80-pin devices, RB3 can be configured as the
alternate peripheral pin for the ECCP2 module and
Enhanced PWM output 2A by clearing the CCP2MX
Configuration bit. This applies only to 80-pin devices
operating in Extended Microcontroller mode. If the
device is in Microcontroller mode, the alternate
assignment for ECCP2 is RE7. As with other ECCP2
configurations, the user must ensure that the TRISB
bit is set appropriately for the intended operation. Ports,
RB1, RB2, RB3, RB4 and RB5, are multiplexed with
the Parallel Master Port address.
EXAMPLE 10-2:
CLRF
PORTB
CLRF
LATB
MOVLW
0CFh
MOVWF
TRISB
INITIALIZING PORTB
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
clearing output
data latches
Alternate method to clear
output data latches
Value used to initialize
data direction
Set RB as inputs
RB as outputs
RB as inputs
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared.
© 2009 Microchip Technology Inc.
DS39775C-page 143
PIC18F87J50 FAMILY
TABLE 10-6:
PORTB FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
RB0/FLT0/INT0
RB0
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
RB1/INT1/
PMA4
RB2/INT2/
PMA3
RB3/INT3/
ECCP2/P2A/
PMA2
RB4/KBI0/
PMA1
FLT0
1
I
ST
Enhanced PWM Fault input (ECCP1 module); enabled in software.
INT0
1
I
ST
External interrupt 0 input.
RB1
0
O
DIG
LATB data output.
PORTB data input; weak pull-up when RBPU bit is cleared.
1
I
TTL
INT1
1
I
ST
External interrupt 1 input.
PMA4
x
O
—
Parallel Master Port address out.
RB2
0
O
DIG
LATB data output.
PORTB data input; weak pull-up when RBPU bit is cleared.
1
I
TTL
INT2
1
I
ST
External interrupt 2 input.
PMA3
x
O
—
Parallel Master Port address out.
RB3
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
INT3
1
I
ST
External interrupt 3 input.
ECCP2(1)
0
O
DIG
ECCP2 compare output and ECCP2 PWM output; takes priority over port
data.
1
I
ST
ECCP2 capture input.
P2A(1)
0
O
DIG
ECCP2 Enhanced PWM output, channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
PMA2
x
O
—
RB4
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
I
TTL
Interrupt-on-pin change.
KBI0
RB5/KBI1/
PMA0
RB7/KBI3/PGD
Legend:
Note 1:
2:
Parallel Master Port address out.
PMA1
x
O
—
RB5
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
I
TTL
PMA0
x
O
—
RB6
0
O
DIG
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
KBI2
1
I
TTL
Interrupt-on-pin change.
PGC
x
I
ST
Serial execution (ICSP™) clock input for ICSP and ICD operation.(2)
RB7
0
O
DIG
LATB data output.
1
I
TTL
PORTB data input; weak pull-up when RBPU bit is cleared.
KBI3
1
I
TTL
Interrupt-on-pin change.
PGD
x
O
DIG
Serial execution data output for ICSP and ICD operation.(2)
x
I
ST
Serial execution data input for ICSP and ICD operation.(2)
KBI1
RB6/KBI2/PGC
Description
Parallel Master Port address out.
Interrupt-on-pin change.
Parallel Master Port address out.
LATB data output.
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode,
80-pin devices only). Default assignment is RC1.
All other pin functions are disabled when ICSP™ or ICD are enabled.
DS39775C-page 144
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 10-7:
Name
PORTB
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
65
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
64
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
64
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
61
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT3IP
RBIP
61
INT2IF
INT1IF
61
INTCON
GIE/GIEH PEIE/GIEL
INTCON2
RBPU
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
Legend: Shaded cells are not used by PORTB.
© 2009 Microchip Technology Inc.
DS39775C-page 145
PIC18F87J50 FAMILY
10.4
PORTC, TRISC and
LATC Registers
PORTC is an 8-bit wide, bidirectional port. Only
PORTC pins, RC2 through RC7, are digital only pins
and can tolerate input voltages up to 5.5V.
PORTC is multiplexed with CCP, MSSP and EUSART
peripheral functions (Table 10-8). The pins have
Schmitt Trigger input buffers. The pins for CCP, SPI
and EUSART are also configurable for open-drain output whenever these functions are active. Open-drain
configuration is selected by setting the SPIxOD,
ECCPxOD and UxOD control bits in the ODCON registers (see Section 10.1.3 “Pull-up Configuration” for
more information).
RC1 is normally configured as the default peripheral
pin for the ECCP2 module. Assignment of ECCP2 is
controlled by Configuration bit, CCP2MX (default state,
CCP2MX = 1).
Note:
These pins are configured as digital inputs
on any device Reset.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 10-3:
CLRF
PORTC
CLRF
LATC
MOVLW
0CFh
MOVWF
TRISC
INITIALIZING PORTC
;
;
;
;
;
;
;
;
;
;
Initialize PORTC by
clearing output
data latches
Alternate method to clear
output data latches
Value used to initialize
data direction
Set RC as inputs
RC as outputs
RC as inputs
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
DS39775C-page 146
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 10-8:
Pin Name
RC0/T1OSO/
T13CKI
RC1/T1OSI/
ECCP2/P2A
RC2/ECCP1/
P1A
RC3/SCK1/
SCL1
PORTC FUNCTIONS
Function
TRIS
Setting
I/O
I/O
Type
RC0
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
T1OSO
x
O
ANA
T13CKI
1
I
ST
Timer1/Timer3 counter input.
RC1
0
O
DIG
LATC data output.
1
I
ST
T1OSI
x
I
ANA
Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables
digital I/O.
ECCP2(1)
0
O
DIG
ECCP2 compare output and ECCP2 PWM output; takes priority over port
data.
I
ST
ECCP2 capture input.
0
O
DIG
ECCP2 Enhanced PWM output, channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RC2
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
ECCP1
0
O
DIG
ECCP1 compare output and ECCP1 PWM output; takes priority over port
data.
1
I
ST
ECCP1 capture input.
P1A
0
O
DIG
ECCP1 Enhanced PWM output, channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RC3
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
0
O
DIG
SPI clock output (MSSP1 module); takes priority over port data.
RC4
Legend:
Note 1:
1
I
ST
SPI clock input (MSSP1 module).
0
O
DIG
I2C™ clock output (MSSP1 module); takes priority over port data.
1
I
ST
I2C clock input (MSSP1 module); input type depends on module setting.
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
SDI1
1
I
ST
SPI data input (MSSP1 module).
SDA1
1
O
DIG
I2C data output (MSSP1 module); takes priority over port data.
1
I
ST
I2C data input (MSSP1 module); input type depends on module setting.
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
SDO1
0
O
DIG
SPI data output (MSSP1 module); takes priority over port data.
C2OUT
x
O
DIG
Comparator 2 output.
RC6
0
O
DIG
LATC data output.
1
I
ST
PORTC data input.
TX1
1
O
DIG
Synchronous serial data output (EUSART1 module); takes priority over port data.
CK1
1
O
DIG
Synchronous serial data input (EUSART1 module). User must configure as
an input.
1
I
ST
Synchronous serial clock input (EUSART1 module).
RC5
RC6/TX1/CK1
PORTC data input.
1
SCL1
RC5/SDO1/
C2OUT
Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables
digital I/O.
P2A(1)
SCK1
RC4/SDI1/
SDA1
Description
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
© 2009 Microchip Technology Inc.
DS39775C-page 147
PIC18F87J50 FAMILY
TABLE 10-8:
PORTC FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
RC7/RX1/DT1
RC7
0
O
DIG
1
I
ST
PORTC data input.
RX1
1
I
ST
Asynchronous serial receive data input (EUSART1 module).
DT1
1
O
DIG
Synchronous serial data output (EUSART1 module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSART1 module). User must configure as
an input.
Legend:
Note 1:
PORTC
LATC data output.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
TABLE 10-9:
Name
Description
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
65
LATC
LATC7
LATBC6
LATC5
LATCB4
LATC3
LATC2
LATC1
LATC0
64
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
64
DS39775C-page 148
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
10.5
PORTD, TRISD and
LATD Registers
PORTD is an 8-bit wide, bidirectional port. All pins on
PORTD are digital only and tolerate voltages up to
5.5V.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note:
These pins are configured as digital inputs
on any device Reset.
On 80-pin devices, PORTD is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON). When the interface is enabled,
PORTD is the low-order byte of the multiplexed
address/data bus (AD7:AD0). The TRISD bits are also
overridden.
Each of the PORTD pins has a weak internal pull-up.
The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit, RDPU (PORTG). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
EXAMPLE 10-4:
CLRF
PORTD
CLRF
LATD
MOVLW
0CFh
MOVWF
TRISD
INITIALIZING PORTD
;
;
;
;
;
;
;
;
;
;
Initialize PORTD by
clearing output
data latches
Alternate method to clear
output data latches
Value used to initialize
data direction
Set RD as inputs
RD as outputs
RD as inputs
PORTD can also be configured to function as an 8-bit
wide Parallel Master Port data. In this mode, Parallel
Master Port takes priority over the other digital I/O (but
not the external memory interface). This multiplexing is
available when PMPMX = 1. When the Parallel Master
Port is active, the input buffers are TTL. For more
information, refer to Section 11.0 “Parallel Master
Port”
© 2009 Microchip Technology Inc.
DS39775C-page 149
PIC18F87J50 FAMILY
TABLE 10-10: PORTD FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
RD0
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
AD0(2)
x
O
DIG
External memory interface, address/data bit 0 output.(1)
x
I
TTL
External memory interface, data bit 0 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
0
O
DIG
LATD data output.
RD0/AD0/
PMD0
PMD0(3)
RD1/AD1/
PMD1
RD1
AD1(2)
PMD1
RD2/AD2/
PMD2
(3)
RD2
AD2(2)
PMD2(3)
RD3/AD3/
PMD3
RD3
AD3(2)
PMD3
RD4/AD4/
PMD4/SDO2
(3)
RD4
AD4(2)
PMD4(3)
RD5/AD5/
PMD5/SDI2/
SDA2
Note 1:
2:
3:
1
I
ST
PORTD data input.
x
O
DIG
External memory interface, address/data bit 1 output.(1)
x
I
TTL
External memory interface, data bit 1 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
x
O
DIG
External memory interface, address/data bit 2 output.(1)
x
I
TTL
External memory interface, data bit 2 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
x
O
DIG
External memory interface, address/data bit 3 output.(1)
x
I
TTL
External memory interface, data bit 3 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
x
O
DIG
External memory interface, address/data bit 4 output.(1)
x
I
TTL
External memory interface, data bit 4 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
SDO2
0
O
DIG
SPI data output (MSSP2 module); takes priority over port data.
RD5
0
O
DIG
LATD data output.
1
I
ST
PORTD data input.
x
O
DIG
External memory interface, address/data bit 5 output.(1)
x
I
TTL
External memory interface, data bit 5 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
AD5(2)
PMD5
Legend:
Description
(3)
SDI2
1
I
ST
SPI data input (MSSP2 module).
SDA2
1
O
DIG
I2C™ data output (MSSP2 module); takes priority over port data.
1
I
ST
I2C data input (MSSP2 module); input type depends on module setting.
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
External memory interface I/O takes priority over all other digital and PMP I/O.
Available on 80-pin devices only.
When PMPMX = 1.
DS39775C-page 150
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 10-10: PORTD FUNCTIONS (CONTINUED)
Pin Name
RD6/AD6/
PMD6/SCK2/
SCL2
Function
TRIS
Setting
I/O
I/O
Type
RD6
0
O
DIG
AD6(2)
PMD6(3)
SCK2
SCL2
RD7/AD7/
PMD7/SS2
RD7
AD7(2)
PMD7(3)
SS2
Legend:
Note 1:
2:
3:
Description
LATD data output.
1
I
ST
x
O
DIG-3
PORTD data input.
x
I
TTL
External memory interface, data bit 6 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
0
O
DIG
SPI clock output (MSSP2 module); takes priority over port data.
1
I
ST
SPI clock input (MSSP2 module).
0
O
DIG
I2C™ clock output (MSSP2 module); takes priority over port data.
1
I
ST
I2C clock input (MSSP2 module); input type depends on module
setting.
0
O
DIG
LATD data output.
External memory interface, address/data bit 6 output.(1)
1
I
ST
PORTD data input.
x
O
DIG
External memory interface, address/data bit 7 output.(1)
x
I
TTL
External memory interface, data bit 7 input.(1)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
x
I
TTL
Slave select input for MSSP (MSSP2 module).
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
External memory interface I/O takes priority over all other digital and PMP I/O.
Available on 80-pin devices only.
When PMPMX = 1.
TABLE 10-11: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name
PORTD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
65
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
64
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
64
PORTG
RDPU
REPU
RJPU(1)
RG4
RG3
RG2
RG1
RG0
65
Legend: Shaded cells are not used by PORTD.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
© 2009 Microchip Technology Inc.
DS39775C-page 151
PIC18F87J50 FAMILY
10.6
PORTE, TRISE and
LATE Registers
PORTE is an 8-bit wide, bidirectional port. All pins on
PORTE are digital only and tolerate voltages up to
5.5V.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note:
These pins are configured as digital inputs
on any device Reset.
On 80-pin devices, PORTE is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled, by setting the EBDIS bit
(MEMCON). When the interface is enabled,
PORTE is the high-order byte of the multiplexed
address/data bus (AD15:AD8). The TRISE bits are also
overridden.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit REPU (PORTG). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
PORTE is also multiplexed with Enhanced PWM
outputs B and C for ECCP1 and ECCP3 and outputs B,
C and D for ECCP2. For all devices, their default
assignments are on PORTE. On 80-pin devices,
the multiplexing for the outputs of ECCP1 and ECCP3
is controlled by the ECCPMX Configuration bit.
Clearing this bit reassigns the P1B/P1C and P3B/P3C
outputs to PORTH.
For devices operating in Microcontroller mode, pin RE7
can be configured as the alternate peripheral pin for the
ECCP2 module and Enhanced PWM output 2A. This is
done by clearing the CCP2MX Configuration bit.
PORTE is also multiplexed with the Parallel Master
Port address lines. When PMPMX = 0, RE1 and RE0
are multiplexed with the control signals, PMPWR and
PMPRD.
RE3 can also be configured as the Reference Clock
Output (REFO) from the system clock. for further
details on this, refer to Section 2.5 “Reference Clock
Output”.
EXAMPLE 10-5:
CLRF
PORTE
CLRF
LATE
MOVLW
03h
INITIALIZING PORTE
; Initialize PORTE by
;
;
;
;
;
;
MOVWF
DS39775C-page 152
TRISE
;
;
clearing output
data latches
Alternate method to clear
output data latches
Value used to initialize
data direction
Set RE as inputs
RE as outputs
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 10-12:
Pin Name
RE0/AD8/
PMRD/P2D
PORTE FUNCTIONS
Function
TRIS
Setting
I/O
I/O
Type
RE0
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External memory interface, address/data bit 8 output.(2)
x
I
TTL
External memory interface, data bit 8 input.(2)
x
O
DIG
Parallel Master Port read strobe pin.
x
I
TTL
Parallel Master Port read pin.
P2D
0
O
DIG
ECCP2 Enhanced PWM output, channel D; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE1
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External memory interface, address/data bit 9 output.(2)
x
I
TTL
External memory interface, data bit 9 input.(2)
x
O
DIG
Parallel Master Port write strobe pin.
x
I
TTL
Parallel Master Port write pin.
P2C
0
O
DIG
ECCP2 Enhanced PWM output, channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE2
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
AD10(3)
x
O
DIG
External memory interface, address/data bit 10 output.(2)
x
I
TTL
External memory interface, data bit 10 input.(2)
PMBE(5)
x
O
DIG
Parallel Master Port byte enable.
P2B
0
O
DIG
ECCP2 Enhanced PWM output, channel B; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE3
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External memory interface, address/data bit 11 output.(2)
x
I
TTL
External memory interface, data bit 11 input.(2)
AD8(3)
PMRD
RE1/AD9/
PMWR/P2C
(5)
AD9(3)
PMWR
RE2/AD10/
PMBE/P2B
RE3/AD11/
PMA13/P3C/
REFO
RE4/AD12/
PMA12/P3B
(5)
AD11(3)
PMA13
x
O
DIG
Parallel Master Port address.
P3C(1)
0
O
DIG
ECCP3 Enhanced PWM output, channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
REFO
x
O
DIG
Reference output clock.
RE4
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External memory interface, address/data bit 12 output.(2)
x
I
TTL
External memory interface, data bit 12 input.(2)
AD12(3)
Legend:
Note 1:
2:
3:
4:
5:
Description
PMA12
x
O
DIG
Parallel Master Port address.
P3B(1)
0
O
DIG
ECCP3 Enhanced PWM output, channel B; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
External memory interface I/O takes priority over all other digital and PMP I/O.
Available on 80-pin devices only.
Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller
mode).
Default configuration for PMP (PMPMX Configuration bit = 1).
© 2009 Microchip Technology Inc.
DS39775C-page 153
PIC18F87J50 FAMILY
TABLE 10-12:
Pin Name
PORTE FUNCTIONS (CONTINUED)
Function
TRIS
Setting
I/O
I/O
Type
RE5
0
O
DIG
LATE data output.
RE5/AD13/
PMA11/P1C
1
I
ST
PORTE data input.
x
O
DIG
External memory interface, address/data bit 13 output.(2)
x
I
TTL
External memory interface, data bit 13 input.(2)
PMA11
x
O
DIG
Parallel Master Port address.
(1)
0
O
DIG
ECCP1 Enhanced PWM output, channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
x
O
DIG
External memory interface, address/data bit 14 output.(2)
x
I
TTL
External memory interface, data bit 14 input.(2)
AD13(3)
P1C
RE6/AD14/
PMA10/P1B
RE6
AD14(3)
RE7/AD15/
PMA9/ECCP2/
P2A
PMA10
x
O
DIG
Parallel Master Port address.
P1B(1)
0
O
DIG
ECCP1 Enhanced PWM output, channel B; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE7
0
O
DIG
LATE data output.
1
I
ST
PORTE data input.
AD15(3)
x
O
DIG
External memory interface, address/data bit 15 output.(2)
x
I
TTL
External memory interface, data bit 15 input.(2)
x
O
DIG
Parallel Master Port address.
0
O
DIG
ECCP2 compare output and ECCP2 PWM output; takes priority over
port data.
1
I
ST
ECCP2 capture input.
0
O
DIG
ECCP2 Enhanced PWM output, channel A; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
PMA9
ECCP2
(4)
(4)
P2A
Legend:
Note 1:
2:
3:
4:
5:
Description
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
External memory interface I/O takes priority over all other digital and PMP I/O.
Available on 80-pin devices only.
Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller
mode).
Default configuration for PMP (PMPMX Configuration bit = 1).
TABLE 10-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
PORTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
65
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
64
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
64
PORTG
RDPU
REPU
RJPU(1)
RG4
RG3
RG2
RG1
RG0
65
Legend: Shaded cells are not used by PORTE.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
DS39775C-page 154
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
10.7
PORTF, LATF and TRISF Registers
PORTF is a 6-bit wide, bidirectional port. RF2, RF5 and
RF6 are analog inputs. These ports are configured as
analog inputs on a device Reset.
All pins on PORTF are implemented with Schmitt Trigger input buffers. Each pin is individually configurable
as an input or output.
Pins, RF3 and RF4, are multiplexed with the USB module. Depending on the configuration of the module, they
can serve as the differential data lines for the on-chip
USB transceiver. Both RF3 and RF4 have Schmitt
Trigger input buffers. As digital ports, they can only
function as digital inputs; the on-chip USB transceiver
must be disabled (UTRDIS (UCFG) bit = 1) to use
the pin as digital inputs. When configured for USB operation, the data direction is determined automatically by
the configuration and status of the USB module at any
given time.
When Configuration bit, PMPMX = 0, PORTF is multiplexed with Parallel Master data port. This multiplexing
is available only in 80 pin devices.
EXAMPLE 10-6:
CLRF
CLRF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
MOVLW
MOVWF
INITIALIZING PORTF
PORTF
; Initialize PORTF by
; clearing output
; data latches
LATF
; Alternate method to
; clear output latches
WDTCON,ADSHR ; Enable write/read to
; the shared SFR
80h
; make RF2 digital
ANCON0
;
0Ch
; make RF digital
ANCON1
;
WDTCON,ADSHR ; Disable write/read to
; the shared SFR
C0h
;
TRISF
; Set RF5:RF2 as outputs,
; RF as inputs
Note 1: On device Resets, pins RF2, RF5 and
RF6 are configured as analog inputs and
are read as ‘0’.
2: To configure PORTF as digital I/O, set the
corresponding bits in ANCON0 and
ANCON1.
© 2009 Microchip Technology Inc.
DS39775C-page 155
PIC18F87J50 FAMILY
TABLE 10-14: PORTF FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
RF2
0
O
DIG
LATF data output; not affected by analog input.
1
I
ST
PORTF data input; disabled when analog input enabled.
PMA5
x
O
DIG
Parallel Master Port address.
AN7
1
I
ANA
A/D input channel 7. Default configuration on POR.
C2INB
x
I
ANA
Comparator 2 input B.
RF3
1
I
ST
PORTF data input; disabled when analog input enabled.
O
XVCR
USB bus differential minus line output (internal transceiver).
I
XVCR
USB bus differential minus line input (internal transceiver).
RF2/PMA5/
AN7/C2INB
RF3/D-
DRF4/D+
RF4
I
ST
O
XVCR
I
XVCR
0
O
DIG
LATF data output; not affected by analog input. Disabled when
CVREF output enabled.
1
I
ST
PORTF data input; disabled when analog input enabled. Disabled
when CVREF output enabled.
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
AN10
1
I
ANA
A/D input channel 10 and Comparator C1+ input. Default input
configuration on POR.
C1INB
x
I
ANA
Comparator 1 input B.
CVREF
x
O
ANA
Comparator voltage reference output. Enabling this feature disables
digital I/O.
RF6
0
O
DIG
LATF data output; not affected by analog input.
1
I
ST
PORTF data input; disabled when analog input enabled.
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
1
I
ANA
A/D input channel 11 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
Comparator 1 input A.
1
D+
RF5
RF5/PMD2/
AN10/C1INB/
CVREF
PMD2(1)
RF6/PMD1/
AN11/C1INA
PMD1(1)
AN11
USB bus differential plus line output (internal transceiver).
USB bus differential plus line input (internal transceiver).
x
I
ANA
RF7
0
O
DIG
LATF data output.
1
I
ST
PORTF data input.
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
SS1
1
I
TTL
Slave select input for MSSP1.
C1OUT
x
O
DIG
Comparator 1 output.
PMD0(1)
Note 1:
PORTF data input; disabled when analog input enabled.
C1INA
RF7/PMD0/
SS1/C1OUT
Legend:
Description
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
XVCR = USB Transceiver, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only.
DS39775C-page 156
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 10-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Name
PORTF
LATF
TRISF
ANCON0
(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
RF7
RF6
RF5
RF4
RF3
RF2
—
—
65
—
64
64
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
—
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
—
—
PCFG7
ANCON1(1) PCFG15
—
—
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
63
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
—
—
63
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.
Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
© 2009 Microchip Technology Inc.
DS39775C-page 157
PIC18F87J50 FAMILY
10.8
PORTG, TRISG and
LATG Registers
PORTG is a 5-bit wide, bidirectional port. The corresponding Data Direction register is TRISG. All pins on
PORTG are digital only and tolerate voltages up to
5.5V.
PORTG is multiplexed with EUSART2 functions
(Table 10-16). PORTG pins have Schmitt Trigger input
buffers. PORTG has pins multiplexed with the Parallel
Master Port.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
DS39775C-page 158
Although the port itself is only five bits wide,
PORTG bits are still implemented. These are
used to control the weak pull-ups on the I/O ports
associated with the External Memory Bus (PORTD,
PORTE and PORTJ). Setting these bits enables the
pull-ups. Since these are control bits and are not
associated with port I/O, the corresponding TRISG and
LATG bits are not implemented.
EXAMPLE 10-7:
CLRF
PORTG
CLRF
LATG
MOVLW
04h
MOVWF
TRISG
INITIALIZING PORTG
;
;
;
;
;
;
;
;
;
;
Initialize PORTG by
clearing output
data latches
Alternate method to clear
output data latches
Value used to initialize
data direction
Set RG1:RG0 as outputs
RG2 as input
RG4:RG3 as outputs
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 10-16: PORTG FUNCTIONS
Pin Name
RG0/PMA8/
ECCP3/P3A
Function
TRIS
Setting
I/O
I/O
Type
RG0
0
O
DIG
1
I
ST
PORTG data input.
x
O
DIG
Parallel Master Port address.
O
DIG
ECCP3 compare and PWM output; takes priority over port data.
PMA8
ECCP3
RG1/PMA7/
TX2/CK2/
RG2/PMA6/
RX2/DT2
I
ST
ECCP3 capture input.
0
O
DIG
ECCP3 Enhanced PWM output, channel A; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG1
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
PMA7
x
O
DIG
Parallel Master Port address.
TX2
1
O
DIG
Synchronous serial data output (EUSART2 module); takes priority over
port data.
CK2
1
O
DIG
Synchronous serial data input (EUSART2 module). User must configure
as an input.
1
I
ST
Synchronous serial clock input (EUSART2 module).
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
PMA6
x
O
DIG
Parallel Master Port address.
RX2
1
I
ST
Asynchronous serial receive data input (EUSART2 module).
DT2
1
O
DIG
Synchronous serial data output (EUSART2 module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSART2 module). User must configure
as an input.
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
x
O
DIG
Parallel Master Port address chip select 1
x
I
TTL
Parallel Master Port address chip select 1 in.
0
O
DIG
CCP4 compare output and CCP4 PWM output; takes priority over port data.
1
I
ST
CCP4 capture input.
P3D
0
O
DIG
ECCP3 Enhanced PWM output, channel D; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG4
0
O
DIG
LATG data output.
1
I
ST
PORTG data input.
PMCS2
x
O
DIG
Parallel Master Port address chip select 2
CCP5
0
O
DIG
CCP5 compare output and CCP5 PWM output; takes priority over port data.
1
I
ST
CCP5 capture input.
0
O
DIG
ECCP1 Enhanced PWM output, channel D; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG3
PMCS1
CCP4
RG4/PMCS2/
CCP5/P1D
P1D
Legend:
LATG data output.
P3A
RG2
RG3/PMCS1/
CCP4/P3D
Description
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
© 2009 Microchip Technology Inc.
DS39775C-page 159
PIC18F87J50 FAMILY
TABLE 10-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Name
Bit 3
Bit 2
Reset
Values on
Page:
RG1
RG0
65
LATG1
LATG0
64
TRISG0
64
Bit 6
Bit 5
RDPU
REPU
RJPU(1)
RG4
RG3
RG2
LATG
—
—
—
LATG4
LATG3
LATG2
TRISG
—
—
—
TRISG4
TRISG3
TRISG2
TRISG1
PORTG
Bit 4
Bit 0
Bit 7
Bit 1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
DS39775C-page 160
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
10.9
Note:
PORTH, LATH and
TRISH Registers
PORTH is available only on 80-pin
devices.
PORTH is an 8-bit wide, bidirectional I/O port. PORTH
pins are digital only and tolerate voltages up to
5.5V.
All pins on PORTH are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
When the external memory interface is enabled, four of
the PORTH pins function as the high-order address
lines for the interface. The address output from the
interface takes priority over other digital I/O. The
corresponding TRISH bits are also overridden. PORTH
pins, RH4 through RH7, are multiplexed with analog
converter inputs. The operation of these pins as analog
inputs is selected by clearing or setting the
corresponding bits in the ANCON1 register. RH3 to
RH6 is multiplexed with Parallel Master Port and RH4
to RH6 are multiplexed as comparator pins.
© 2009 Microchip Technology Inc.
PORTH can also be configured as the alternate
Enhanced PWM output channels B and C for the
ECCP1 and ECCP3 modules. This is done by clearing
the ECCPMX Configuration bit.
EXAMPLE 10-8:
CLRF
CLRF
BSF
MOVLW
MOVWF
BCF
MOVLW
MOVWF
INITIALIZING PORTH
PORTH
; Initialize PORTH by
; clearing output
; data latches
LATH
; Alternate method to
; clear output latches
WDTCON,ADSHR; Enable write/read to
; the shared SFR
F0h
; Configure PORTH as
ANCON1
; digital I/O
WDTCON,ADSHR; Disable write/read to
; the shared SFR
0CFh
; Value used to initialize
; data direction
TRISH
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
DS39775C-page 161
PIC18F87J50 FAMILY
TABLE 10-18: PORTH FUNCTIONS
Pin Name
RH0/A16
RH1/A17
RH2/A18/
PMD7
RH3/A19/
PMD6
Function
TRIS
Setting
I/O
I/O
Type
RH0
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
A16
x
O
DIG
External memory interface, address line 16. Takes priority over port data.
RH1
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
A17
x
O
DIG
External memory interface, address line 17. Takes priority over port data.
RH2
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
A18
x
O
DIG
External memory interface, address line 18. Takes priority over port data.
PMD7(2)
x
O
DIG
Parallel Master Port data out.
RH3
RH4/PMD3/
AN12/P3C/
C2INC
x
I
TTL
Parallel Master Port data input.
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
A19
x
O
DIG
External memory interface, address line 19. Takes priority over port data.
PMD6(2)
x
O
DIG
Parallel Master Port data out.
x
I
TTL
Parallel Master Port data input.
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
RH4
PMD3(2)
X
I
TTL
Parallel Master Port data out.
X
O
DIG
Parallel Master Port data input.
I
ANA
A/D input channel 12. Default input configuration on POR; does not affect
digital output.
O
DIG
ECCP3 Enhanced PWM output, channel C; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
AN12
RH5/PMBE/
AN13/P3B/
C2IND
P3C(1)
0
C2INC
x
I
ANA
Comparator 2 input C.
RH5
0
O
DIG
LATH data output.
1
I
ST
PORTH data input.
x
O
DIG
Parallel Master Port Data byte enable.
I
ANA
A/D input channel 13. Default input configuration on POR; does not affect
digital output.
O
DIG
ECCP3 Enhanced PWM output, channel B; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
PMBE(2)
AN13
RH6/PMRD/
AN14/P1C/
C1INC
P3B(1)
0
C2IND
x
I
ANA
Comparator 2 input D.
RH6
0
O
DIG
LATH data output.
PMRD(2)
1
I
ST
PORTH data input.
x
O
DIG
Parallel Master Port read strobe.
x
I
TTL
Parallel Master Port read in.
I
ANA
A/D input channel 14. Default input configuration on POR; does not affect
digital output.
AN14
Legend:
Note 1:
2:
Description
P1C(1)
0
O
DIG
ECCP1 Enhanced PWM output, channel C; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
C1INC
x
I
ANA
Comparator 1 input C.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is cleared. Default assignments are
PORTE.
When PMPMX = 0.
DS39775C-page 162
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 10-18: PORTH FUNCTIONS (CONTINUED)
Pin Name
RH7/PMWR/
AN15/P1B/
Function
TRIS
Setting
I/O
I/O
Type
RH7
0
O
DIG
1
I
ST
PORTH data input.
PMWR(2)
x
O
DIG
Parallel Master Port write strobe.
x
I
TTL
Parallel Master Port write in.
I
ANA
A/D input channel 15. Default input configuration on POR; does not affect
digital output.
O
DIG
ECCP1 Enhanced PWM output, channel B; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
AN15
P1B(1)
Legend:
Note 1:
2:
0
Description
LATH data output.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is cleared. Default assignments are
PORTE.
When PMPMX = 0.
TABLE 10-19: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Name
PORTH(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
64
LATH(1)
LATH7
LATH6
LATH5
LATH4
LATH3
LATH2
LATH1
LATH0
65
TRISH(1)
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
64
ANCON1(2)
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
—
—
63
Legend: Shaded cells are not used by PORTH.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON = 1.
© 2009 Microchip Technology Inc.
DS39775C-page 163
PIC18F87J50 FAMILY
10.10 PORTJ, TRISJ and
LATJ Registers
Note:
PORTJ is available only on 80-pin devices.
PORTJ is an 8-bit wide, bidirectional port. All pins on
PORTJ are digital only and tolerate voltages up to 5.5V.
All pins on PORTJ are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note:
These pins are configured as digital inputs
on any device Reset.
When the external memory interface is enabled, all of
the PORTJ pins function as control outputs for the
interface. This occurs automatically when the interface
is enabled by clearing the EBDIS control bit
(MEMCON). The TRISJ bits are also overridden.
DS39775C-page 164
Each of the PORTJ pins has a weak internal pull-up.
The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit RJPU (PORTG). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
EXAMPLE 10-9:
CLRF
PORTJ
CLRF
LATJ
MOVLW
0CFh
MOVWF
TRISJ
INITIALIZING PORTJ
;
;
;
;
;
;
;
;
;
;
Initialize PORTG by
clearing output
data latches
Alternate method to clear
output data latches
Value used to initialize
data direction
Set RJ3:RJ0 as inputs
RJ5:RJ4 as output
RJ7:RJ6 as inputs
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
TABLE 10-20: PORTJ FUNCTIONS
Pin Name
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
Function
TRIS
Setting
I/O
I/O
Type
RJ0
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
ALE
x
O
DIG
External memory interface address latch enable control output; takes
priority over digital I/O.
RJ1
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
OE
x
O
DIG
External memory interface output enable control output; takes priority
over digital I/O.
RJ2
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
WRL
x
O
DIG
External Memory Bus write low byte control; takes priority over
digital I/O.
RJ3
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
WRH
x
O
DIG
External memory interface write high byte control output; takes priority
over digital I/O.
RJ4
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
BA0
x
O
DIG
External memory interface byte address 0 control output; takes priority
over digital I/O.
RJ5
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
CE
x
O
DIG
External memory interface chip enable control output; takes priority
over digital I/O.
RJ6
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
LB
x
O
DIG
External memory interface lower byte enable control output; takes
priority over digital I/O.
RJ7
0
O
DIG
LATJ data output.
1
I
ST
PORTJ data input.
x
O
DIG
External memory interface upper byte enable control output; takes
priority over digital I/O.
UB
Legend:
Description
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-21: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Name
PORTJ(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
RJ7
RJ6
RJ5
RJ4
RJ3
RJ2
RJ1
RJ0
65
LATJ(1)
LATJ7
LATJ6
LATJ5
LATJ4
LATJ3
LATJ2
LATJ1
LATJ0
64
TRISJ(1)
TRISJ7
TRISJ6
TRISJ5
TRISJ4
TRISJ3
TRISJ2
TRISJ1
TRISJ0
64
PORTG
RDPU
REPU
RJPU(1)
RG4
RG3
RG2
RG1
RG0
65
Legend: Shaded cells are not used by PORTJ.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
© 2009 Microchip Technology Inc.
DS39775C-page 165
PIC18F87J50 FAMILY
NOTES:
DS39775C-page 166
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
11.0
PARALLEL MASTER PORT
The Parallel Master Port module (PMP) is a parallel,
8-bit I/O module, specifically designed to communicate
with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory devices
and microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP is highly
configurable. The PMP module can be configured to
serve as either a Parallel Master Port or as a Parallel
Slave Port.
FIGURE 11-1:
Key features of the PMP module include:
• Up to 16 Programmable Address Lines
• Up to Two Chip Select Lines
• Programmable Strobe Options
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support
- Address Support
- 4-Byte Deep, Auto-Incrementing Buffer
• Programmable Wait States
• Selectable Input Voltage Levels
PMP MODULE OVERVIEW
Address Bus
Data Bus
Control Lines
PIC18
Parallel Master Port
PMA
PMALL
PMA
PMALH
Up to 16-Bit Address
EEPROM
PMA
PMA
PMCS1
PMA
PMCS2
PMBE
PMRD
PMRD/PMWR
Microcontroller
LCD
FIFO
Buffer
PMWR
PMENB
PMD
PMA
PMA
© 2009 Microchip Technology Inc.
8-Bit Data
DS39775C-page 167
PIC18F87J50 FAMILY
11.1
Module Registers
The
PMCON
registers
(Register 11-1
and
Register 11-2) control basic module operations, including turning the module on or off. They also configure
address multiplexing and control strobe configuration.
The PMP module has a total of 14 Special Function
Registers for its operation, plus one additional register
to set configuration options. Of these, 8 registers are
used for control and 6 are used for PMP data transfer.
11.1.1
The
PMMODE
registers
(Register 11-3
and
Register 11-4) configure the various Master and Slave
operating modes, the data width and interrupt
generation.
CONTROL REGISTERS
The eight PMP Control registers are:
The PMEH and PMEL registers (Register 11-5 and
Register 11-6) configure the module’s operation at the
hardware (I/O pin) level.
• PMCONH and PMCONL
• PMMODEH and PMMODEL
• PMSTATL and PMSTATH
The
PMSTAT
registers
(Register 11-5
and
Register 11-6) provide status flags for the module’s
input and output buffers, depending on the operating
mode.
• PMEH and PMEL
REGISTER 11-1:
PMCONH: PARALLEL PORT CONTROL REGISTER HIGH BYTE
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMPEN
—
PSIDL
ADRMUX1
ADRMUX0
PTBEEN
PTWREN
PTRDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PMPEN: Parallel Master Port Enable bit
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
bit 6
Unimplemented: Read as ‘0’
bit 5
PSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 4-3
ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD pins
01 = Lower 8 bits of address are multiplexed on PMD pins, upper 8 bits are on PMA
00 = Address and data appear on separate pins
bit 2
PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)
1 = PMBE port enabled
0 = PMBE port disabled
bit 1
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
bit 0
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled
DS39775C-page 168
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
REGISTER 11-2:
PMCONL: PARALLEL PORT CONTROL REGISTER LOW BYTE
R/W-0
R/W-0
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0
R/W-0
R/W-0
CSF1
CSF0
ALP
CS2P
CS1P
BEP
WRSP
RDSP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
CSF1:CSF0: Chip Select Function bits
11 = Reserved
10 = PMCS1 and PMCS2 function as chip select
01 = PMCS2 functions as chip select, PMCS1 used as address bit 14 (PMADDRH address bit 6)
00 = PMCS2 and PMCS1 used as address bits 15 and 14 (PMADDRH address bits 7 and 6)
bit 5
ALP: Address Latch Polarity bit(1)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
bit 4
CS2P: Chip Select 2 Polarity bit(1)
1 = Active-high (PMCS2)
0 = Active-low (PMCS2)
bit 3
CS1P: Chip Select 1 Polarity bit(1)
1 = Active-high (PMCS1/PMCS)
0 = Active-low (PMCS1/PMCS)
bit 2
BEP: Byte Enable Polarity bit
1 = Byte enable active-high (PMBE)
0 = Byte enable active-low (PMBE)
bit 1
WRSP: Write Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODEH = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR)
For Master Mode 1 (PMMODEH = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
bit 0
RDSP: Read Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODEH = 00,01,10):
1 = Read strobe active-high (PMRD)
0 = Read strobe active-low (PMRD)
For Master Mode 1 (PMMODEH = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)
Note 1:
These bits have no effect when their corresponding pins are used as address lines.
© 2009 Microchip Technology Inc.
DS39775C-page 169
PIC18F87J50 FAMILY
REGISTER 11-3:
PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUSY
IRQM1
IRQM0
INCM1
INCM0
MODE16
MODE1
MODE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
bit 6-5
IRQM1:IRQM0: Interrupt Request Mode bits
11 = Interrupt generated when read buffer 3 is read or write buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA = 11 (Addressable PSP mode only)
10 = No interrupt generated, processor stall activated
01 = Interrupt generated at the end of the read/write cycle
00 = No interrupt generated
bit 4-3
INCM1:INCM0: Increment Mode bits
11 = PSP read and write buffers auto-increment (Legacy PSP mode only)
10 = Decrement ADDR by 1 every read/write cycle
01 = Increment ADDR by 1 every read/write cycle
00 = No increment or decrement of address
bit 2
MODE16: 8/16-Bit Mode bit
1 = 16-Bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers
0 = 8-Bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer
bit 1-0
MODE1:MODE0: Parallel Port Mode Select bits
11 = Master Mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA and PMD)
10 = Master Mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA and PMD)
01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD and PMA)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD)
DS39775C-page 170
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY
REGISTER 11-4:
R/W-0
WAITB1
PMMODEL: PARALLEL PORT MODE REGISTER LOW BYTE
R/W-0
(1)
R/W-0
(1)
WAITB0
WAITM3
R/W-0
WAITM2
R/W-0
WAITM1
R/W-0
WAITM0
R/W-0
WAITE1
(1)
R/W-0
WAITE0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
WAITB1:WAITB0: Data Setup to Read/Write Wait State Configuration bits(1)
11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY
10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY
01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY
00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY
bit 5-2
WAITM3:WAITM0: Read to Byte Enable Strobe Wait State Configuration bits
1111 = Wait of additional 15 TCY
...
0001 = Wait of additional 1 TCY
0000 = No additional wait cycles (operation forced into one TCY)
bit 1-0
WAITE1:WAITE0: Data Hold After Strobe Wait State Configuration bits(1)
11 = Wait of 4 TCY
10 = Wait of 3 TCY
01 = Wait of 2 TCY
00 = Wait of 1 TCY
Note 1:
WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000.
REGISTER 11-5:
PMEH: PARALLEL PORT ENABLE REGISTER HIGH BYTE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN15
PTEN14
PTEN13
PTEN12
PTEN11
PTEN10
PTEN9
PTEN8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
PTEN15:PTEN14: PMCSx Strobe Enable bits
1 = PMA15 and PMA14 function as either PMA or PMCS2 and PMCS1
0 = PMA15 and PMA14 function as port I/O
bit 5-0
PTEN13:PTEN8: PMP Address Port Enable bits
1 = PMA function as PMP address lines
0 = PMA function as port I/O
© 2009 Microchip Technology Inc.
DS39775C-page 171
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REGISTER 11-6:
PMEL: PARALLEL PORT ENABLE REGISTER LOW BYTE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
PTEN7:PTEN2: PMP Address Port Enable bits
1 = PMA function as PMP address lines
0 = PMA function as port I/O
bit 1-0
PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits
1 = PMA1 and PMA0 function as either PMA or PMALH and PMALL
0 = PMA1 and PMA0 pads functions as port I/O
REGISTER 11-7:
PMSTATH: PARALLEL PORT STATUS REGISTER HIGH BYTE
R-0
R/W-0
U-0
U-0
R-0
R-0
R-0
R-0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IBF: Input Buffer Full Status bit
1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 6
IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full input byte register occurred (must be cleared in software)
0 = No overflow occurred
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
IB3F:IB0F: Input Buffer x Status Full bits
1 = Input buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input buffer does not contain any unread data
DS39775C-page 172
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REGISTER 11-8:
PMSTATL: PARALLEL PORT STATUS REGISTER LOW BYTE
R-1
R/W-0
U-0
U-0
R-1
R-1
R-1
R-1
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6
OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty output byte register (must be cleared in software)
0 = No underflow occurred
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
OB3E:OB0E: Output Buffer x Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted
© 2009 Microchip Technology Inc.
DS39775C-page 173
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11.1.2
DATA REGISTERS
The PMP module uses 6 registers for transferring data
into and out of the microcontroller. They are arranged
as three pairs to allow the option of 16-bit data
operations:
•
•
•
•
PMDIN1H and PMDIN1L
PMDIN2H and PMDIN2L
PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L
PMDOUT2H and PMDOUT2L
The PMDIN1 register is used for incoming data in Slave
modes, and both input and output data in Master
modes. The PMDIN2 register is used for buffering input
data in select Slave modes.
The PMADDRx/PMDOUT1x registers are actually a
single register pair; the name and function is dictated
by the module’s operating mode. In Master modes, the
registers functions as the PMADDRH and PMADDRL
registers, and contain the address of any incoming or
outgoing data. In Slave modes, the registers function
as PMDOUT1H and PMDOUT1L and are used for
outgoing data.
PMADDRH differs from PMADDRL in that it can also
have limited PMP control functions. When the module
is operating in select Master mode configurations, the
REGISTER 11-9:
upper two bits of the register can be used to determine
the operation of chip select signals. If chip select
signals are not used, PMADDR simply functions to hold
the upper 8 bits of the address. The function of the
individual bits in PMADDRH is shown in Register 11-9.
The PMDOUT2H and PMDOUT2L registers are only
used in Buffered Slave modes and serve as a buffer for
outgoing data.
11.1.3
PAD CONFIGURATION CONTROL
REGISTER
In addition to the module level configuration options,
the PMP module can also be configured at the I/O pin
for electrical operation. This option allows users to
select either the normal Schmitt Trigger input buffer on
digital I/O pins shared with the PMP, or use TTL level
compatible buffers instead. Buffer configuration is
controlled by the PMPTTL bit in the PADCFG1 register.
The PADCFG1 register is one of the shared address
SFRs, and has the same address as the TMR2 register. PADCFG1 is accessed by setting the ADSHR bit
(WDTCON). Refer to Section 5.3.5.1 “Shared
Address SFRs” for more information.
PMADDRH: PARALLEL PORT ADDRESS REGISTER,
HIGH BYTE (MASTER MODES ONLY)(1)
R/W-0
R/W-0
CS2
CS1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CS2: Chip Select 2 bit
If PMCON = 10 or 01:
1 = Chip select 2 is active
0 = Chip select 2 is inactive
If PMCON = 11 or 00:
Bit functions as ADDR.
bit 6
CS1: Chip Select 1 bit
If PMCON = 10:
1 = Chip select 1 is active
0 = Chip select 1 is inactive
If PMCON = 11 or 0x:
Bit functions as ADDR.
bit 5-0
ADDR5:ADDR0: Parallel Port Destination Address bits
Note 1:
x = Bit is unknown
In Enhanced Slave mode, PMADDRH functions as PMDOUT1H, one of the Output Data Buffer registers.
DS39775C-page 174
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11.1.4
PMP MULTIPLEXING
OPTIONS(80-PINS DEVICES)
By default, the PMP and the External Memory Bus
(EMB) multiplex some of their signals to the same I/O
pins on PORTD and PORTE. It is possible that some
applications may require the use of both modules at the
same time. For these instances, the 80-pin devices can
be configured to multiplex the PMP to different I/O
ports. PMP configuration is determined by the PMPMX
Configuration bit setting; by default, the PMP and EMB
modules share PORTD and PORTE. The optional pin
configuration is shown in Table 11-1.
TABLE 11-1:
PMP PIN MULTIPLEXING
80-PIN DEVICES
Pin Assignment
PMP
Function
PMPMX = 1
PMPMX= 0
PMD0
PORTD
PORTF
PMD1
PORTD
PORTF
PMD2
PORTD
PORTF
PMD3
PORTD
PORTH
PMD4
PORTD
PORTA
PMD5
PORTD
PORTA
PMD6
PORTD
PORTH
PMD7
PORTD
PORTH
PMBE
PORTE
PORTH
PMWR
PORTE
PORTH
PMRD
PORTE
PORTH
FIGURE 11-2:
11.2
Slave Port Modes
The primary mode of operation for the module is configured using the MODE1:MODE0 bits in the
PMMODEH register. The setting affects whether the
module acts as a slave or a master and it determines
the usage of the control pins.
11.2.1
LEGACY MODE (PSP)
In Legacy mode (PMMODEH = 00 and
PMPEN = 1), the module is configured as a Parallel
Slave Port with the associated enabled module pins
dedicated to the module. In this mode, an external
device, such as another microcontroller or microprocessor, can asynchronously read and write data
using the 8-bit data bus (PMD), the read (PMRD),
write (PMWR) and chip select (PMCS1) inputs. It acts
as a slave on the bus and responds to the read/write
control signals.
Figure 11-2 shows the connection of the Parallel Slave
Port. When chip select is active and a write strobe
occurs (PMCS = 1 and PMWR = 1), the data from
PMD is captured into the PMDIN1L register.
LEGACY PARALLEL SLAVE PORT EXAMPLE
Master
PIC18 Slave
PMD
PMD
PMCS
PMCS1
PMRD
PMRD
PMWR
PMWR
© 2009 Microchip Technology Inc.
Address Bus
Data Bus
Control Lines
DS39775C-page 175
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11.2.2
WRITE TO SLAVE PORT
When chip select is active and a write strobe occurs
(PMCS = 1 and PMWR = 1), the data from PMD
is captured into the lower PMDIN1L register. The
PMPIF and IBF flag bits are set when the write
ends.The timing for the control signals in Write mode is
shown in Figure 11-3. The polarity of the control signals
are configurable.
FIGURE 11-3:
11.2.3
READ FROM SLAVE PORT
When chip select is active and a read strobe occurs
(PMCS = 1 and PMRD = 1), the data from the
PMDOUTL1 register (PMDOUTL1) is presented
onto PMD.The timing for the control signals in
Read mode is shown in Figure 11-4.
PARALLEL SLAVE PORT WRITE WAVEFORMS
|
Q4
|
Q1
|
Q2
|
Q3
|
Q4
|
Q1
|
Q2
|
Q3
|
Q4
PMCS1
PMWR
PMRD
PMD
IBF
OBE
PMPIF
FIGURE 11-4:
PARALLEL SLAVE PORT READ WAVEFORMS
|
Q4
PMCS1
PMWR
PMRD
PMD
IBF
OBE
PMPIF
DS39775C-page 176
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11.2.4
BUFFERED PARALLEL SLAVE
PORT MODE
Buffered Parallel Slave Port mode is functionally identical to the legacy Parallel Slave Port mode with one
exception: the implementation of 4-level read and write
buffers. Buffered PSP mode is enabled by setting the
INCM bits in the PMMODEH register. If the INCM
bits are set to ‘11’, the PMP module will act as the
buffered Parallel Slave Port.
When the Buffered mode is active, the PMDIN1L,
PMDIN1H, PMDIN2L and PMDIN2H registers become
the write buffers and the PMDOUT1L, PMDOUT1H,
PMDOUT2L and PMDOUT2H registers become the
read buffers. Buffers are numbered 0 through 3, starting with the lower byte of PMDIN1L to PMDIN2H as the
read buffers and PMDOUT1L to PMDOUT2H as the
write buffers.
11.2.4.1
READ FROM SLAVE PORT
For read operations, the bytes will be sent out sequentially, starting with Buffer 0 (PMDOUT1L) and
ending with Buffer 3 (PMDOUT2H) for every read
strobe. The module maintains an internal pointer to
keep track of which buffer is to be read. Each of the
buffers has a corresponding read status bit, OBxE, in
the PMSTATL register. This bit is cleared when a buffer
contains data that has not been written to the bus, and
is set when data is written to the bus. If the current
buffer location being read from is empty, a buffer under-
FIGURE 11-5:
flow is generated, and the Buffer Overflow flag bit
OBUF is set. If all four OBxE status bits are set, then
the Output Buffer Empty flag (OBE) will also be set.
11.2.4.2
WRITE TO SLAVE PORT
For write operations, the data is be stored sequentially,
starting with Buffer 0 (PMDIN1L) and ending with
Buffer 3 (PMDIN2H
