PIC18FXX8
Data Sheet
28/40-Pin High-Performance,
Enhanced Flash Microcontrollers
with CAN Module
© 2006 Microchip Technology Inc.
DS41159E
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
DS41159E-page ii
© 2006 Microchip Technology Inc.
PIC18FXX8
28/40-Pin High-Performance, Enhanced Flash
Microcontrollers with CAN
High-Performance RISC CPU:
Advanced Analog Features:
• Linear program memory addressing up to
2 Mbytes
• Linear data memory addressing to 4 Kbytes
• Up to 10 MIPS operation
• DC – 40 MHz clock input
• 4 MHz-10 MHz oscillator/clock input with
PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• 10-bit, up to 8-channel Analog-to-Digital Converter
module (A/D) with:
- Conversion available during Sleep
- Up to 8 channels available
• Analog Comparator module:
- Programmable input and output multiplexing
• Comparator Voltage Reference module
• Programmable Low-Voltage Detection (LVD) module:
- Supports interrupt-on-Low-Voltage Detection
• Programmable Brown-out Reset (BOR)
Peripheral Features:
CAN bus Module Features:
• High current sink/source 25 mA/25 mA
• Three external interrupt pins
• Timer0 module: 8-bit/16-bit timer/counter with
8-bit programmable prescaler
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter with 8-bit
period register (time base for PWM)
• Timer3 module: 16-bit timer/counter
• Secondary oscillator clock option – Timer1/Timer3
• Capture/Compare/PWM (CCP) modules;
CCP pins can be configured as:
- Capture input: 16-bit, max resolution 6.25 ns
- Compare: 16-bit, max resolution 100 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bit
Max. PWM freq. @:8-bit resolution = 156 kHz
10-bit resolution = 39 kHz
• Enhanced CCP module which has all the features
of the standard CCP module, but also has the
following features for advanced motor control:
- 1, 2 or 4 PWM outputs
- Selectable PWM polarity
- Programmable PWM dead time
• Master Synchronous Serial Port (MSSP) with two
modes of operation:
- 3-wire SPI™ (Supports all 4 SPI modes)
- I2C™ Master and Slave mode
• Addressable USART module:
- Supports interrupt-on-address bit
• Complies with ISO CAN Conformance Test
• Message bit rates up to 1 Mbps
• Conforms to CAN 2.0B Active Spec with:
- 29-bit Identifier Fields
- 8-byte message length
- 3 Transmit Message Buffers with prioritization
- 2 Receive Message Buffers
- 6 full, 29-bit Acceptance Filters
- Prioritization of Acceptance Filters
- Multiple Receive Buffers for High Priority
Messages to prevent loss due to overflow
- Advanced Error Management Features
© 2006 Microchip Technology Inc.
Special Microcontroller Features:
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator
• Programmable code protection
• Power-saving Sleep mode
• Selectable oscillator options, including:
- 4x Phase Lock Loop (PLL) of primary oscillator
- Secondary Oscillator (32 kHz) clock input
• In-Circuit Serial ProgrammingTM (ICSPTM) via two pins
Flash Technology:
•
•
•
•
Low-power, high-speed Enhanced Flash technology
Fully static design
Wide operating voltage range (2.0V to 5.5V)
Industrial and Extended temperature ranges
DS41159E-page 1
Comparators
PIC18FXX8
CCP/
ECCP
(PWM)
PIC18F248
16K
8192
768
256
22
5
—
1/0
Y
Y
Y
1/3
PIC18F258
32K
16384
1536
256
22
5
—
1/0
Y
Y
Y
1/3
PIC18F448
16K
8192
768
256
33
8
2
1/1
Y
Y
Y
1/3
PIC18F458
32K
16384
1536
256
33
8
2
1/1
Y
Y
Y
1/3
Program Memory
Device
Data Memory
I/O
Flash # Single-Word SRAM EEPROM
(bytes) Instructions (bytes) (bytes)
10-bit
A/D
(ch)
MSSP
Master
I2C™
USART
SPI™
Timers
8/16-bit
Pin Diagrams
PDIP
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RB3/CANRX
RB2/CANTX/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4/ECCP1/P1A
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3/C2INRD2/PSP2/C2IN+
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1
RA0/AN0/CVREF
MCLR/VPP
NC
RB7/PGD
RB6/PGC
RB5/PGM
RB4
NC
PIC18F448
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC18F458
MCLR/VPP
RA0/AN0/CVREF
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/AN5/RD
RE1/AN6/WR/C1OUT
RE2/AN7/CS/C2OUT
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0/C1IN+
RD1/PSP1/C1IN-
6
5
4
3
2
1
44
43
42
41
40
PLCC
7
8
9
10
11
12
13
14
15
16
17
PIC18F448
PIC18F458
39
38
37
36
35
34
33
32
31
30
29
RB3/CANRX
RB2/CANTX/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4/ECCP1/P1A
RC7/RX/DT
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0/C1IN+
RD1/PSP1/C1INRD2/PSP2/C2IN+
RD3/PSP3/C2INRC4/SDI/SDA
RC5/SDO
RC6/TX/CK
NC
18
19
20
21
22
23
24
25
26
27
28
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/AN5/RD
RE1/AN6/WR/C1OUT
RE2/AN7/CS/C2OUT
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CK1
NC
DS41159E-page 2
© 2006 Microchip Technology Inc.
PIC18FXX8
Pin Diagrams (Continued)
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3/C2INRD2/PSP2/C2IN+
RD1/PSP1/C1INRD0/PSP0/C1IN+
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI
NC
TQFP
1
2
3
4
5
6
7
8
9
10
11
PIC18F448
PIC18F458
33
32
31
30
29
28
27
26
25
24
23
NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/CS/C2OUT
RE1/AN6/WR/C1OUT
RE0//AN5/RD
RA5/AN4/SS/LVDIN
RA4/T0CKI
RA0/AN0/CVREF
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
NC
NC
RB4
RB5/PGM
RB6/PGC
RB7/PGD
MCLR/VPP
12
13
14
15
16
17
18
19
20
21
22
RC7/RX/DT
RD4/PSP4/ECCP1/P1A
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
VDD
RB0/INT0
RB1/INT1
RB2/CANTX/INT2
RB3/CANRX
SPDIP, SOIC
© 2006 Microchip Technology Inc.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC18F248
PIC18F258
MCLR/VPP
RA0/AN0/CVREF
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RB3/CANRX
RB2/CANTX/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
DS41159E-page 3
PIC18FXX8
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 17
3.0 Reset .......................................................................................................................................................................................... 25
4.0 Memory Organization ................................................................................................................................................................. 37
5.0 Data EEPROM Memory ............................................................................................................................................................ 59
6.0 Flash Program Memory .............................................................................................................................................................. 65
7.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 75
8.0 Interrupts .................................................................................................................................................................................... 77
9.0 I/O Ports ..................................................................................................................................................................................... 93
10.0 Parallel Slave Port .................................................................................................................................................................... 107
11.0 Timer0 Module ......................................................................................................................................................................... 109
12.0 Timer1 Module ......................................................................................................................................................................... 113
13.0 Timer2 Module ......................................................................................................................................................................... 117
14.0 Timer3 Module ......................................................................................................................................................................... 119
15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 123
16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 131
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 143
18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 183
19.0 CAN Module ............................................................................................................................................................................. 199
20.0 Compatible 10-Bit Analog-to-Digital Converter (A/D) Module .................................................................................................. 241
21.0 Comparator Module.................................................................................................................................................................. 249
22.0 Comparator Voltage Reference Module ................................................................................................................................... 255
23.0 Low-Voltage Detect .................................................................................................................................................................. 259
24.0 Special Features of the CPU .................................................................................................................................................... 265
25.0 Instruction Set Summary .......................................................................................................................................................... 281
26.0 Development Support............................................................................................................................................................... 323
27.0 Electrical Characteristics .......................................................................................................................................................... 329
28.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 361
29.0 Packaging Information.............................................................................................................................................................. 377
Appendix A: Data Sheet Revision History.......................................................................................................................................... 385
Appendix B: Device Differences......................................................................................................................................................... 385
Appendix C: Device Migrations .......................................................................................................................................................... 386
Appendix D: Migrating From Other PICmicro® Devices ..................................................................................................................... 386
Index .................................................................................................................................................................................................. 387
On-Line Support................................................................................................................................................................................. 397
Systems Information and Upgrade Hot Line ...................................................................................................................................... 397
Reader Response .............................................................................................................................................................................. 398
PIC18FXX8 Product Identification System......................................................................................................................................... 399
DS41159E-page 4
© 2006 Microchip Technology Inc.
PIC18FXX8
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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Register on our web site at www.microchip.com to receive the most current information on all of our products.
© 2006 Microchip Technology Inc.
DS41159E-page 5
PIC18FXX8
NOTES:
DS41159E-page 6
© 2006 Microchip Technology Inc.
PIC18FXX8
1.0
DEVICE OVERVIEW
2.
This document contains device specific information for
the following devices:
3.
•
•
•
•
4.
PIC18F248
PIC18F258
PIC18F448
PIC18F458
These devices are available in 28-pin, 40-pin and
44-pin packages. They are differentiated from each
other in four ways:
1.
PIC18FX58 devices have twice the Flash
program memory and data RAM of PIC18FX48
devices (32 Kbytes and 1536 bytes vs.
16 Kbytes and 768 bytes, respectively).
TABLE 1-1:
All other features for devices in the PIC18FXX8 family,
including the serial communications modules, are
identical. These are summarized in Table 1-1.
Block diagrams of the PIC18F2X8 and PIC18F4X8
devices are provided in Figure 1-1 and Figure 1-2,
respectively. The pinouts for these device families are
listed in Table 1-2.
PIC18FXX8 DEVICE FEATURES
Features
Operating Frequency
Internal
Program
Memory
PIC18F2X8 devices implement 5 A/D channels,
as opposed to 8 for PIC18F4X8 devices.
PIC18F2X8 devices implement 3 I/O ports,
while PIC18F4X8 devices implement 5.
Only PIC18F4X8 devices implement the
Enhanced CCP module, analog comparators
and the Parallel Slave Port.
PIC18F248
PIC18F258
PIC18F448
PIC18F458
DC – 40 MHz
DC – 40 MHz
DC – 40 MHz
DC – 40 MHz
Bytes
16K
32K
16K
32K
# of Single-Word
Instructions
8192
16384
8192
16384
Data Memory (Bytes)
768
1536
768
1536
Data EEPROM Memory (Bytes)
256
256
256
256
Interrupt Sources
17
17
21
21
Ports A, B, C
Ports A, B, C
Ports A, B, C, D, E
Ports A, B, C, D, E
Timers
4
4
4
4
Capture/Compare/PWM Modules
1
1
1
1
Enhanced Capture/Compare/
PWM Modules
—
—
1
1
I/O Ports
Serial Communications
Parallel Communications (PSP)
10-bit Analog-to-Digital Converter
Analog Comparators
Analog Comparators VREF Output
MSSP, CAN,
MSSP, CAN,
MSSP, CAN,
MSSP, CAN,
Addressable USART Addressable USART Addressable USART Addressable USART
No
No
Yes
Yes
5 input channels
5 input channels
8 input channels
8 input channels
No
No
2
2
N/A
N/A
Yes
Yes
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
Programmable Low-Voltage Detect
Yes
Yes
Yes
Yes
Programmable Brown-out Reset
Yes
Yes
Yes
Yes
CAN Module
Yes
Yes
Yes
Yes
In-Circuit Serial Programming™
(ICSP™)
Yes
Yes
Yes
Yes
Instruction Set
75 Instructions
75 Instructions
75 Instructions
75 Instructions
Packages
28-pin SPDIP
28-pin SOIC
28-pin SPDIP
28-pin SOIC
40-pin PDIP
44-pin PLCC
44-pin TQFP
40-pin PDIP
44-pin PLCC
44-pin TQFP
Resets (and Delays)
© 2006 Microchip Technology Inc.
DS41159E-page 7
PIC18FXX8
FIGURE 1-1:
PIC18F248/258 BLOCK DIAGRAM
Data Bus
PORTA
21 Table Pointer
8
8
Data RAM
up to 1536 bytes
inc/dec logic
21
RA0/AN0/CVREF
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
OSC2/CLKO/RA6
Data Latch
Address Latch
21
PCLATU PCLATH
PCU PCH PCL
Program Counter
Program Memory
up to 32 Kbytes
RB0/INT0
RB1/INT1
RB2/CANTX/INT2
RB3/CANRX
RB4
RB5/PGM
RB6/PGC
RB7/PGD
Address
12
4
BSR
Address Latch
PORTB
12
31 Level Stack
4
FSR0 Bank0, F
FSR1
FSR2
12
Data Latch
Decode
Table Latch
inc/dec
logic
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
16
ROM Latch
IR
8
PRODH PRODL
Instruction
Decode &
Control
8 x 8 Multiply
3
OSC2/CLKO/RA6
OSC1/CLKI
T1OSI
T1OSO
Power-up
Timer
Timing
Generation
4X PLL
Precision
Band Gap
Reference
W
8
BITOP
8
Oscillator
Start-up Timer
8
8
8
ALU
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Test Mode
Select
8
Band Gap
MCLR
PBOR
PLVD
Data EEPROM
DS41159E-page 8
Timer0
Timer1
CCP1
VDD, VSS
Timer2
USART
Timer3
10-bit
ADC
Synchronous
Serial Port
CAN Module
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 1-2:
PIC18F448/458 BLOCK DIAGRAM
Data Bus
PORTA
21 Table Pointer
8
8
Data RAM
up to 1536 Kbytes
inc/dec logic
21
RA0/AN0/CVREF
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
OSC2/CLKO/RA6
Data Latch
Address Latch
21
PCLATU PCLATH
PCU PCH PCL
Program Counter
Program Memory
up to 32 Kbytes
RB0/INT0
RB1/INT1
RB2/CANTX/INT2
RB3/CANRX
RB4
RB5/PGM
RB6/PGC
RB7/PGD
12
4
BSR
Address Latch
PORTB
12
Address
31 Level Stack
4
FSR0 Bank0, F
FSR1
FSR2
12
Data Latch
Decode
Table Latch
inc/dec
logic
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
16
ROM Latch
IR
8
PORTD
RD0/PSP0/C1IN+
RD1/PSP1/C1INRD2/PSP2/C2IN+
RD3/PSP3/C2INRD4/PSP4/ECCP1/P1A
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
PRODH PRODL
Instruction
Decode &
Control
8 x 8 Multiply
OSC2/CLKO/RA6
OSC1/CLKI
Power-up
Timer
Timing
Generation
T1OSI
T1OSO
8
3
Oscillator
Start-up Timer
Precision
Band Gap
Reference
8
PORTE
8
RE0/AN5/RD
RE1/AN6/WR//C1OUT
RE2/AN7/CS/C2OUT
ALU
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Test Mode
Select
4X
PLL
W
8
BITOP
8
8
Band Gap
MCLR
PBOR
PLVD
Data EEPROM
Timer0
Comparators
© 2006 Microchip Technology Inc.
Timer1
CCP1
VDD, VSS
USART
Timer2
Enhanced
CCP
Timer3
10-bit
ADC
USART
Synchronous
Serial Port
Parallel
Slave Port
CAN Module
DS41159E-page 9
PIC18FXX8
TABLE 1-2:
PIC18FXX8 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
PIC18F248/258
MCLR/VPP
PIC18F448/458
SPDIP, SOIC
PDIP
TQFP
PLCC
1
1
18
2
Pin
Type
Buffer
Type
MCLR
I
ST
VPP
P
—
—
—
NC
—
—
OSC1/CLKI
9
13
12, 13, 1, 17,
33, 34 28, 40
30
14
OSC1
I
CLKI
I
OSC2/CLKO/RA6
OSC2
10
14
31
CLKO
RA6
Legend: TTL
ST
I
P
DS41159E-page 10
TTL compatible input
Schmitt Trigger input with CMOS levels
Input
Power
Master Clear (input) or
programming voltage (output).
Master Clear (Reset) input.
This pin is an active low Reset
to the device.
Programming voltage input.
These pins should be left
unconnected.
Oscillator crystal or external clock
input.
Oscillator crystal input or
CMOS/ST
external clock source input. ST
buffer when configured in RC
mode; otherwise, CMOS.
CMOS
External clock source input.
Always associated with pin
function OSC1 (see OSC1/
CLKI, OSC2/CLKO pins).
15
O
—
O
—
I/O
=
=
=
=
Description
CMOS
Analog
O
OD
TTL
=
=
=
=
Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or
resonator in Crystal Oscillator
mode.
In RC mode, OSC2 pin outputs
CLKO, which has 1/4 the
frequency of OSC1 and
denotes the instruction cycle
rate.
General purpose I/O pin.
CMOS compatible input or output
Analog input
Output
Open-Drain (no P diode to VDD)
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 1-2:
PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PIC18F248/258
PIC18F448/458
SPDIP, SOIC
PDIP
TQFP
PLCC
2
2
19
3
Pin
Type
Buffer
Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0/CVREF
RA0
AN0
CVREF
RA1/AN1
RA1
AN1
3
RA2/AN2/VREFRA2
AN2
VREF-
4
RA3/AN3/VREF+
RA3
AN3
VREF+
5
RA4/T0CKI
RA4
6
3
4
5
6
20
21
22
23
7
7
24
TTL
Analog
Analog
Digital I/O.
Analog input 0.
Comparator voltage reference
output.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage
(Low) input.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage
(High) input.
I/O
TTL/OD
I
ST
Digital I/O – open-drain when
configured as output.
Timer0 external clock input.
I/O
I
I
I
TTL
Analog
ST
Analog
CMOS
Analog
O
OD
=
=
=
=
4
5
6
7
T0CKI
RA5/AN4/SS/LVDIN
RA5
AN4
SS
LVDIN
I/O
I
O
8
RA6
Legend: TTL
ST
I
P
Digital I/O.
Analog input 4.
SPI™ slave select input.
Low-Voltage Detect input.
See the OSC2/CLKO/RA6 pin.
=
=
=
=
TTL compatible input
Schmitt Trigger input with CMOS levels
Input
Power
© 2006 Microchip Technology Inc.
CMOS compatible input or output
Analog input
Output
Open-Drain (no P diode to VDD)
DS41159E-page 11
PIC18FXX8
TABLE 1-2:
PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PIC18F248/258
SPDIP, SOIC
PIC18F448/458
PDIP
TQFP
Pin
Type
Buffer
Type
Description
PLCC
PORTB is a bidirectional I/O port.
PORTB can be software
programmed for internal weak
pull-ups on all inputs.
RB0/INT0
RB0
INT0
21
RB1/INT1
RB1
INT1
22
RB2/CANTX/INT2
RB2
CANTX
INT2
23
RB3/CANRX
RB3
CANRX
24
RB4
25
37
14
41
RB5/PGM
RB5
26
38
15
42
33
34
35
36
8
9
10
11
36
27
39
16
28
40
17
PGD
Legend: TTL
ST
I
P
Digital I/O.
External interrupt 0.
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
I/O
O
I
TTL
TTL
ST
Digital I/O.
Transmit signal for CAN bus.
External interrupt 2.
I/O
I
TTL
TTL
Digital I/O.
Receive signal for CAN bus.
I/O
TTL
Digital I/O.
Interrupt-on-change pin.
I/O
TTL
I
ST
Digital I/O.
Interrupt-on-change pin.
Low-voltage ICSP™
programming enable.
I/O
TTL
I
ST
I/O
TTL
38
39
43
PGC
RB7/PGD
RB7
TTL
ST
37
PGM
RB6/PGC
RB6
I/O
I
44
I/O
=
=
=
=
DS41159E-page 12
TTL compatible input
Schmitt Trigger input with CMOS levels
Input
Power
Digital I/O. In-Circuit
Debugger pin.
Interrupt-on-change pin.
ICSP programming clock.
CMOS
Analog
O
OD
ST
=
=
=
=
Digital I/O. In-Circuit
Debugger pin.
Interrupt-on-change pin.
ICSP programming data.
CMOS compatible input or output
Analog input
Output
Open-Drain (no P diode to VDD)
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 1-2:
PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PIC18F248/258
SPDIP, SOIC
PIC18F448/458
PDIP
TQFP
Pin
Type
Buffer
Type
Description
PLCC
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
11
RC1/T1OSI
RC1
T1OSI
12
RC2/CCP1
RC2
CCP1
13
RC3/SCK/SCL
RC3
SCK
14
15
16
17
18
32
35
36
37
16
15
RC5/SDO
RC5
SDO
16
RC6/TX/CK
RC6
TX
17
23
24
25
42
43
44
Legend: TTL
ST
I
P
18
=
=
=
=
26
1
TTL compatible input
Schmitt Trigger input with CMOS levels
Input
Power
© 2006 Microchip Technology Inc.
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock
input.
I/O
I
ST
CMOS
I/O
I/O
ST
ST
Digital I/O.
Capture 1 input/Compare 1
output/PWM1 output.
I/O
I/O
ST
ST
I/O
ST
Digital I/O.
Synchronous serial clock
input/output for SPI™ mode.
Synchronous serial clock
input/output for I2C™ mode.
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
ST
—
Digital I/O.
SPI data out.
I/O
O
ST
—
I/O
ST
Digital I/O.
USART asynchronous
transmit.
USART synchronous clock
(see RX/DT).
I/O
I
I/O
ST
ST
ST
Digital I/O.
Timer1 oscillator input.
19
20
25
26
27
CK
RC7/RX/DT
RC7
RX
DT
ST
—
ST
18
SCL
RC4/SDI/SDA
RC4
SDI
SDA
I/O
O
I
29
CMOS
Analog
O
OD
=
=
=
=
Digital I/O.
USART asynchronous receive.
USART synchronous data
(see TX/CK).
CMOS compatible input or output
Analog input
Output
Open-Drain (no P diode to VDD)
DS41159E-page 13
PIC18FXX8
TABLE 1-2:
PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PIC18F248/258
SPDIP, SOIC
PIC18F448/458
PDIP
TQFP
Pin
Type
Buffer
Type
Description
PLCC
PORTD is a bidirectional I/O port.
These pins have TTL input buffers
when external memory is enabled.
RD0/PSP0/C1IN+
RD0
PSP0
C1IN+
—
RD1/PSP1/C1INRD1
PSP1
C1IN-
—
RD2/PSP2/C2IN+
RD2
PSP2
C2IN+
—
RD3/PSP3/C2INRD3
PSP3
C2IN-
—
RD4/PSP4/ECCP1/
P1A
RD4
PSP4
ECCP1
P1A
—
RD5/PSP5/P1B
RD5
PSP5
P1B
—
RD6/PSP6/P1C
RD6
PSP6
P1C
—
RD7/PSP7/P1D
RD7
PSP7
P1D
—
Legend: TTL
ST
I
P
=
=
=
=
DS41159E-page 14
19
20
21
22
27
28
29
30
38
39
40
41
2
3
4
5
TTL compatible input
Schmitt Trigger input with CMOS levels
Input
Power
21
I/O
I/O
I
ST
TTL
Analog
Digital I/O.
Parallel Slave Port data.
Comparator 1 input.
I/O
I/O
I
ST
TTL
Analog
Digital I/O.
Parallel Slave Port data.
Comparator 1 input.
I/O
I/O
I
ST
TTL
Analog
Digital I/O.
Parallel Slave Port data.
Comparator 2 input.
I/O
I/O
I
ST
TTL
Analog
Digital I/O.
Parallel Slave Port data.
Comparator 2 input.
I/O
I/O
I/O
O
ST
TTL
ST
—
Digital I/O.
Parallel Slave Port data.
ECCP1 capture/compare.
ECCP1 PWM output A.
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output B.
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output C.
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output D.
22
23
24
30
31
32
33
CMOS
Analog
O
OD
=
=
=
=
CMOS compatible input or output
Analog input
Output
Open-Drain (no P diode to VDD)
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 1-2:
PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
PIC18F248/258
PIC18F448/458
SPDIP, SOIC
PDIP
TQFP
PLCC
RE0/AN5/RD
RE0
AN5
RD
—
8
25
9
RE1/AN6/WR/C1OUT
RE1
AN6
WR
—
Pin
Type
Buffer
Type
Description
PORTE is a bidirectional I/O port.
9
26
—
10
ST
Analog
TTL
Digital I/O.
Analog input 5.
Read control for Parallel Slave
Port (see WR and CS pins).
I/O
I
I
ST
Analog
TTL
O
Analog
Digital I/O.
Analog input 6.
Write control for Parallel Slave
Port (see CS and RD pins).
Comparator 1 output.
I/O
I
I
ST
Analog
TTL
10
C1OUT
RE2/AN7/CS/C2OUT
RE2
AN7
CS
I/O
I
I
27
11
C2OUT
Digital I/O.
Analog input 7.
Chip select control for Parallel
Slave Port (see RD and WR
pins).
Comparator 2 output.
O
Analog
VSS
19, 8
12, 31
6, 29
13, 34
—
—
Ground reference for logic and
I/O pins.
VDD
20
11, 32
7, 28
12, 35
—
—
Positive supply for logic and I/O
pins.
Legend: TTL
ST
I
P
=
=
=
=
TTL compatible input
Schmitt Trigger input with CMOS levels
Input
Power
© 2006 Microchip Technology Inc.
CMOS
Analog
O
OD
=
=
=
=
CMOS compatible input or output
Analog input
Output
Open-Drain (no P diode to VDD)
DS41159E-page 15
PIC18FXX8
NOTES:
DS41159E-page 16
© 2006 Microchip Technology Inc.
PIC18FXX8
2.0
OSCILLATOR
CONFIGURATIONS
2.1
Oscillator Types
FIGURE 2-1:
C1(1)
The PIC18FXX8 can be operated in one of eight oscillator modes, programmable by three configuration bits
(FOSC2, FOSC1 and FOSC0).
1.
2.
3.
4.
LP
XT
HS
HS4
5.
6.
RC
RCIO
7.
8.
EC
ECIO
2.2
Low-Power Crystal
Crystal/Resonator
High-Speed Crystal/Resonator
High-Speed Crystal/Resonator with
PLL enabled
External Resistor/Capacitor
External Resistor/Capacitor with I/O
pin enabled
External Clock
External Clock with I/O pin enabled
Crystal Oscillator/Ceramic
Resonators
In XT, LP, HS or HS4 (PLL) Oscillator modes, a crystal
or ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections. An external clock source may also
be connected to the OSC1 pin, as shown in Figure 2-3
and Figure 2-4.
The PIC18FXX8 oscillator design requires the use of a
parallel cut crystal.
Note:
Use of a series cut crystal may give a frequency out of the crystal manufacturer’s
specifications.
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP OSC
CONFIGURATION)
OSC1
XTAL
To
Internal
Logic
RF(3)
Sleep
RS(2)
C2(1)
PIC18FXX8
OSC2
Note 1: See Table 2-1 and Table 2-2 for recommended
values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the crystal chosen.
TABLE 2-1:
CERAMIC RESONATORS
Ranges Tested:
Mode
Freq
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
68-100 pF
15-68 pF
15-68 pF
68-100 pF
15-68 pF
15-68 pF
HS
8.0 MHz
16.0 MHz
10-68 pF
10-22 pF
10-68 pF
10-22 pF
These values are for design guidance only.
See notes following Table 2-2.
Resonators Used:
455 kHz
Panasonic EFO-A455K04B
±0.3%
2.0 MHz
Murata Erie CSA2.00MG
±0.5%
4.0 MHz
Murata Erie CSA4.00MG
±0.5%
8.0 MHz
Murata Erie CSA8.00MT
±0.5%
16.0 MHz
Murata Erie CSA16.00MX
±0.5%
All resonators used did not have built-in capacitors.
© 2006 Microchip Technology Inc.
DS41159E-page 17
PIC18FXX8
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc Type
Crystal
Freq
LP
32.0 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1.0 MHz
15 pF
15 pF
4.0 MHz
15 pF
15 pF
XT
HS
Cap. Range
C1
Cap. Range
C2
4.0 MHz
15 pF
15 pF
8.0 MHz
15-33 pF
15-33 pF
20.0 MHz
15-33 pF
15-33 pF
25.0 MHz
15-33 pF
15-33 pF
These values are for design guidance only.
See notes on this page.
2.3
RC Oscillator
For timing insensitive applications, the “RC” and “RCIO”
device options offer additional cost savings. The RC
oscillator frequency is a function of the supply voltage,
the resistor (REXT) and capacitor (CEXT) values and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the difference in lead frame capacitance between package types
will also affect the oscillation frequency, especially for
low CEXT values. The user also needs to take into
account variation due to tolerance of external R and C
components used. Figure 2-2 shows how the RC
combination is connected.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
Crystals Used
Note:
32.0 kHz
Epson C-001R32.768K-A
±20 PPM
200 kHz
STD XTL 200.000KHz
±20 PPM
1.0 MHz
ECS ECS-10-13-1
±50 PPM
4.0 MHz
ECS ECS-40-20-1
±50 PPM
8.0 MHz
EPSON CA-301 8.000M-C
±30 PPM
20.0 MHz EPSON CA-301 20.000M-C
±30 PPM
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 2-1).
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
4: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
DS41159E-page 18
If the oscillator frequency divided by 4
signal is not required in the application, it
is recommended to use RCIO mode to
save current.
FIGURE 2-2:
RC OSCILLATOR MODE
VDD
PIC18FXX8
REXT
OSC1
Internal
Clock
CEXT
VSS
FOSC/4
Recommended values:
OSC2/CLKO
3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
The RCIO Oscillator mode functions like the RC mode,
except that the OSC2 pin becomes an additional
general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
© 2006 Microchip Technology Inc.
PIC18FXX8
2.4
FIGURE 2-4:
External Clock Input
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is no oscillator start-up time required after a Power-on Reset or
after a recovery from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-3:
EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
OSC1
Clock from
Ext. System
FOSC/4
PIC18FXX8
OSC2
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional
general purpose I/O pin. Figure 2-4 shows the pin
connections for the ECIO Oscillator mode.
EXTERNAL CLOCK INPUT
OPERATION (ECIO
CONFIGURATION)
OSC1
Clock from
Ext. System
PIC18FXX8
I/O (OSC2)
2.5
HS4 (PLL)
A Phase Locked Loop circuit is provided as a programmable option for users that want to multiply the
frequency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high-frequency crystals.
The PLL can only be enabled when the oscillator
configuration bits are programmed for HS mode. If they
are programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
The PLL is one of the modes of the FOSC2:FOSC0
configuration bits. The oscillator mode is specified
during device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out referred to as TPLL.
FIGURE 2-5:
PLL BLOCK DIAGRAM
FOSC2:FOSC0 = 110
Phase
Comparator
FIN
Crystal
Osc
OSC1
© 2006 Microchip Technology Inc.
FOUT
Loop
Filter
VCO
MUX
OSC2
SYSCLK
Divide by 4
DS41159E-page 19
PIC18FXX8
2.6
2.6.1
Oscillator Switching Feature
The PIC18FXX8 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low-frequency clock source.
For the PIC18FXX8 devices, this alternate clock source
is the Timer1 oscillator. If a low-frequency crystal
(32 kHz, for example) has been attached to the Timer1
oscillator pins and the Timer1 oscillator has been
enabled, the device can switch to a Low-Power Execution mode. Figure 2-6 shows a block diagram of the
system clock sources. The clock switching feature is
enabled by programming the Oscillator Switching
Enable (OSCSEN) bit in Configuration register,
CONFIG1H, to a ‘0’. Clock switching is disabled in an
erased device. See Section 12.2 “Timer1 Oscillator”
for further details of the Timer1 oscillator and
Section 24.1 “Configuration Bits” for Configuration
register details.
FIGURE 2-6:
SYSTEM CLOCK SWITCH BIT
The system clock source switching is performed under
software control. The system clock switch bit, SCS
(OSCCON register), controls the clock switching. When
the SCS bit is ‘0’, the system clock source comes from
the main oscillator selected by the FOSC2:FOSC0
configuration bits. When the SCS bit is set, the system
clock source comes from the Timer1 oscillator. The SCS
bit is cleared on all forms of Reset.
Note:
The Timer1 oscillator must be enabled to
switch the system clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control register (T1CON). If the Timer1 oscillator is not
enabled, any write to the SCS bit will be
ignored (SCS bit forced cleared) and the
main oscillator continues to be the system
clock source.
DEVICE CLOCK SOURCES
PIC18FXX8
Main Oscillator
OSC2
4 x PLL
Sleep
TOSC/4
Timer 1 Oscillator
T T 1P
T1OSO
T1OSCEN
Enable
Oscillator
T1OSI
TSCLK
MUX
TOSC
OSC1
Clock
Source
Clock Source Option
for Other Modules
Note:
REGISTER 2-1:
I/O pins have diode protection to VDD and VSS.
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
—
bit 7
bit 7-1
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
SCS
bit 0
Unimplemented: Read as ‘0’
SCS: System Clock Switch bit
When OSCSEN configuration bit = 0 and T1OSCEN bit is set:
1 = Switch to Timer1 oscillator/clock pin
0 = Use primary oscillator/clock input pin
When OSCSEN is clear or T1OSCEN is clear:
Bit is forced clear.
Legend:
R = Readable bit
-n = Value at POR
DS41159E-page 20
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
2.6.2
OSCILLATOR TRANSITIONS
The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
The PIC18FXX8 devices contain circuitry to prevent
“glitches” when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to. This
ensures that the new clock source is stable and that its
pulse width will not be less than the shortest pulse
width of the two clock sources.
If the main oscillator is configured for an external
crystal (HS, XT, LP), the transition will take place after
an oscillator start-up time (TOST) has occurred. A timing
diagram indicating the transition from the Timer1
oscillator to the main oscillator for HS, XT and LP
modes is shown in Figure 2-8.
Figure 2-7 shows a timing diagram indicating the transition from the main oscillator to the Timer1 oscillator.
The Timer1 oscillator is assumed to be running all the
time. After the SCS bit is set, the processor is frozen at
the next occurring Q1 cycle. After eight synchronization
cycles are counted from the Timer1 oscillator,
operation resumes. No additional delays are required
after the synchronization cycles.
FIGURE 2-7:
TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1 Q2 Q3 Q4 Q1
Q1
Q2
Q4
Q3
Q1
Q2
Q3
Q4
Q1
TT1P
1
T1OSI
2
3
4
5
6
7
8
Tscs
OSC1
TOSC
Internal
System
Clock
SCS
(OSCCON)
Program
Counter
TDLY
PC
PC + 4
PC + 2
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
FIGURE 2-8:
TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q3
Q4
Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3
TT1P
T1OSI
1
OSC1
TOST
2
3
4
5
6
7
8
TSCS
OSC2
TOSC
Internal System
Clock
SCS
(OSCCON)
Program
Counter
PC
PC + 2
PC + 4
Note 1: TOST = 1024 TOSC (drawing not to scale).
© 2006 Microchip Technology Inc.
DS41159E-page 21
PIC18FXX8
If the main oscillator is configured for HS4 (PLL) mode,
an oscillator start-up time (TOST) plus an additional PLL
time-out (TPLL) will occur. The PLL time-out is typically
2 ms and allows the PLL to lock to the main oscillator
frequency. A timing diagram indicating the transition
from the Timer1 oscillator to the main oscillator for HS4
mode is shown in Figure 2-9.
FIGURE 2-9:
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram indicating the transition from the Timer1 oscillator to the main
oscillator for RC, RCIO, EC and ECIO modes is shown
in Figure 2-10.
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
Q4
TT1P
Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T1OSI
OSC1
TOST
TPLL
OSC2
TSCS
TOSC
PLL Clock
Input
1
2
3
4
5
6
8
7
Internal System
Clock
SCS
(OSCCON)
Program
Counter
PC
PC + 2
PC + 4
Note 1: TOST = 1024 TOSC (drawing not to scale).
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3
Q4
T1OSI
Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TT1P
TOSC
OSC1
1
2
3
4
5
6
7
8
OSC2
Internal System
Clock
SCS
(OSCCON)
TSCS
Program
Counter
PC
PC + 2
PC + 4
Note 1: RC Oscillator mode assumed.
DS41159E-page 22
© 2006 Microchip Technology Inc.
PIC18FXX8
2.7
Effects of Sleep Mode on the
On-Chip Oscillator
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, Sleep mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during Sleep will increase the current
consumed during Sleep. The user can wake from
Sleep through external Reset, Watchdog Timer Reset
or through an interrupt.
2.8
Power-up Delays
Power-up delays are controlled by two timers so that no
external Reset circuitry is required for most applications. The delays ensure that the device is kept in
TABLE 2-3:
Reset until the device power supply and clock are
stable. For additional information on Reset operation,
see Section 3.0 “Reset”.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of TPWRT (parameter
#D033) on power-up only (POR and BOR). The second
timer is the Oscillator Start-up Timer (OST), intended to
keep the chip in Reset until the crystal oscillator is
stable.
With the PLL enabled (HS4 Oscillator mode), the timeout sequence following a Power-on Reset is different
from other oscillator modes. The time-out sequence is
as follows: the PWRT time-out is invoked after a POR
time delay has expired, then the Oscillator Start-up
Timer (OST) is invoked. However, this is still not a
sufficient amount of time to allow the PLL to lock at high
frequencies. The PWRT timer is used to provide an
additional fixed 2 ms (nominal) to allow the PLL ample
time to lock to the incoming clock frequency.
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode
OSC1 Pin
OSC2 Pin
RC
Floating, external resistor should pull high
At logic low
RCIO
Floating, external resistor should pull high
Configured as PORTA, bit 6
ECIO
Floating
Configured as PORTA, bit 6
EC
Floating
At logic low
LP, XT and HS
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note:
See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR Reset.
© 2006 Microchip Technology Inc.
DS41159E-page 23
PIC18FXX8
NOTES:
DS41159E-page 24
© 2006 Microchip Technology Inc.
PIC18FXX8
3.0
RESET
The PIC18FXX8 differentiates between various kinds
of RESET:
a)
b)
c)
d)
e)
f)
g)
h)
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset during normal
operation
Programmable Brown-out Reset (PBOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset”
FIGURE 3-1:
state on Power-on Reset, MCLR, WDT Reset, Brownout Reset, MCLR Reset during Sleep and by the
RESET instruction.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD,
POR and BOR are set or cleared differently in different
Reset situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
Reset. See Table 3-3 for a full description of the Reset
states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
A WDT Reset does not drive MCLR pin low.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLR
Sleep
WDT
Module
WDT
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
BOREN
S
OST/PWRT
OST
10-bit Ripple Counter
OSC1
Chip_Reset
R
Q
PWRT
On-chip
RC OSC(1)
10-bit Ripple Counter
Enable PWRT
Enable OST(2)
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 3-1 for time-out situations.
© 2006 Microchip Technology Inc.
DS41159E-page 25
PIC18FXX8
3.1
Power-on Reset (POR)
3.3
Power-up Timer (PWRT)
A Power-on Reset pulse is generated on-chip when a
VDD rise is detected. To take advantage of the POR
circuitry, connect the MCLR pin directly (or through a
resistor) to VDD. This eliminates external RC components usually needed to create a Power-on Reset
delay. A minimum rise rate for VDD is specified (refer to
parameter D004). For a slow rise time, see Figure 3-2.
The Power-up Timer provides a fixed nominal time-out
(parameter #33), only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in Reset as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an acceptable level. A configuration bit (PWRTEN in CONFIG2L
register) is provided to enable/disable the PWRT.
When the device starts normal operation (exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating conditions are met. Brown-out Reset may be used to meet
the voltage start-up condition.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameter #33 for details.
3.2
MCLR
PIC18FXX8 devices have a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
differs from previous devices of this family. Voltages
applied to the pin that exceed its specification can
result in both Resets and current draws outside of
device specification during the Reset event. For this
reason, Microchip recommends that the MCLR pin no
longer be tied directly to VDD. The use of an RC
network, as shown in Figure 3-2, is suggested.
FIGURE 3-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
VDD
D
R
R1
MCLR
C
PIC18FXXX
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
3.4
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This additional
delay ensures that the crystal oscillator or resonator
has started and stabilized.
The OST time-out is invoked only for XT, LP, HS and
HS4 modes and only on Power-on Reset or wake-up
from Sleep.
3.5
PLL Lock Time-out
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to provide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(TPLL) is typically 2 ms and follows the oscillator
start-up time-out (OST).
3.6
Brown-out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set), the Brown-out Reset
circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation resets the
chip. A Reset may not occur if VDD falls below parameter D005 for less than parameter #35. The chip will
remain in Brown-out Reset until VDD rises above BVDD.
The Power-up Timer will then be invoked and will keep
the chip in Reset an additional time delay (parameter
#33). If VDD drops below BVDD while the Power-up
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
VDD rises above BVDD, the Power-up Timer will
execute the additional time delay.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current flowing into MCLR from external capacitor C, in
the event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
DS41159E-page 26
© 2006 Microchip Technology Inc.
PIC18FXX8
3.7
Time-out Sequence
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18FXX8 device
operating in parallel.
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired, then OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
TABLE 3-1:
Table 3-2 shows the Reset conditions for some Special
Function Registers, while Table 3-3 shows the Reset
conditions for all registers.
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2)
Oscillator
Configuration
Brown-out(2)
PWRTEN = 0
PWRTEN = 1
Wake-up from
Sleep or
Oscillator Switch
HS with PLL enabled(1) 72 ms + 1024 TOSC + 2 ms 1024 TOSC + 2 ms 72 ms + 1024 TOSC + 2 ms 1024 TOSC + 2 ms
HS, XT, LP
72 ms + 1024 TOSC
1024 TOSC
72 ms + 1024 TOSC
1024 TOSC
EC
72 ms
—
72 ms
—
External RC
72 ms
—
72 ms
—
Note 1:
2:
2 ms = Nominal time required for the 4x PLL to lock.
72 ms is the nominal Power-up Timer delay.
REGISTER 3-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-0
R/W-1
IPEN
—
—
RI
TO
PD
POR
BOR
bit 7
TABLE 3-2:
bit 0
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Register
RI
TO
PD
POR
BOR
STKFUL
STKUNF
Power-on Reset
0000h
0--1 110q
1
1
1
0
0
u
u
MCLR Reset during normal
operation
0000h
0--0 011q
u
u
u
u
u
u
u
Software Reset during normal
operation
0000h
0--0 011q
0
u
u
u
u
u
u
Stack Full Reset during normal
operation
0000h
0--0 011q
u
u
u
1
1
u
1
Stack Underflow Reset during
normal operation
0000h
0--0 011q
u
u
u
1
1
1
u
MCLR Reset during Sleep
0000h
0--0 011q
u
1
0
u
u
u
u
WDT Reset
0000h
0--0 011q
u
0
1
u
u
u
u
WDT Wake-up
PC + 2
0--1 101q
u
0
0
u
u
u
u
Condition
Brown-out Reset
Interrupt wake-up from Sleep
0000h
0--1 110q
1
1
1
u
0
u
u
PC + 2(1)
0--1 101q
u
1
0
u
u
u
u
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (000008h or 000018h).
© 2006 Microchip Technology Inc.
DS41159E-page 27
PIC18FXX8
FIGURE 3-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 3-4:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 3-5:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS41159E-page 28
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 3-6:
SLOW RISE TIME (MCLR TIED TO VDD)
5V
VDD
1V
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-7:
TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
IINTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
TPLL
OST TIME-OUT
PLL TIME-OUT
INTERNAL RESET
Note:
TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the PWRT timer.
© 2006 Microchip Technology Inc.
DS41159E-page 29
PIC18FXX8
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU
PIC18F2X8 PIC18F4X8
---0 0000
---0 0000
---0 uuuu(3)
TOSH
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu(3)
TOSL
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu(3)
STKPTR
PIC18F2X8 PIC18F4X8
00-0 0000
uu-0 0000
uu-u uuuu(3)
PCLATU
PIC18F2X8 PIC18F4X8
---0 0000
---0 0000
---u uuuu
PCLATH
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
PCL
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
PC + 2(2)
TBLPTRU
PIC18F2X8 PIC18F4X8
--00 0000
--00 0000
--uu uuuu
TBLPTRH
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
TABLAT
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
PRODH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
PIC18F2X8 PIC18F4X8
0000 000x
0000 000u
uuuu uuuu(1)
INTCON2
PIC18F2X8 PIC18F4X8
111- -1-1
111- -1-1
uuu- -u-u(1)
INTCON3
PIC18F2X8 PIC18F4X8
11-0 0-00
11-0 0-00
uu-u u-uu(1)
INDF0
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
POSTINC0
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
Register
POSTDEC0
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
PREINC0
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
PLUSW0
PIC18F2X8 PIC18F4X8
N/A
N/A
FSR0H
PIC18F2X8 PIC18F4X8
---- xxxx
---- uuuu
---- uuuu
N/A
FSR0L
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
POSTINC1
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
POSTDEC1
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
PREINC1
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
PLUSW1
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).
DS41159E-page 30
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
FSR1H
PIC18F2X8 PIC18F4X8
---- xxxx
---- uuuu
---- uuuu
FSR1L
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
PIC18F2X8 PIC18F4X8
---- 0000
---- 0000
---- uuuu
INDF2
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
POSTINC2
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
POSTDEC2
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
Register
PREINC2
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
PLUSW2
PIC18F2X8 PIC18F4X8
N/A
N/A
N/A
FSR2H
PIC18F2X8 PIC18F4X8
---- xxxx
---- uuuu
---- uuuu
FSR2L
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
PIC18F2X8 PIC18F4X8
---x xxxx
---u uuuu
---u uuuu
TMR0H
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
TMR0L
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
PIC18F2X8 PIC18F4X8
1111 1111
1111 1111
uuuu uuuu
OSCCON
PIC18F2X8 PIC18F4X8
---- ---0
---- ---0
---- ---u
LVDCON
PIC18F2X8 PIC18F4X8
--00 0101
--00 0101
--uu uuuu
WDTCON
PIC18F2X8 PIC18F4X8
---- ---0
---- ---0
---- ---u
RCON(4)
PIC18F2X8 PIC18F4X8
0--1 110q
0--0 011q
0--1 101q
TMR1H
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
PIC18F2X8 PIC18F4X8
0-00 0000
u-uu uuuu
u-uu uuuu
TMR2
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
PR2
PIC18F2X8 PIC18F4X8
1111 1111
1111 1111
1111 1111
T2CON
PIC18F2X8 PIC18F4X8
-000 0000
-000 0000
-uuu uuuu
SSPBUF
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
SSPCON1
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
SSPCON2
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
ADRESH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
PIC18F2X8 PIC18F4X8
0000 00-0
0000 00-0
uuuu uu-u
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).
© 2006 Microchip Technology Inc.
DS41159E-page 31
PIC18FXX8
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
ADCON1
PIC18F2X8 PIC18F4X8
00-- 0000
00-- 0000
uu-- uuuu
CCPR1H
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
PIC18F2X8 PIC18F4X8
--00 0000
--00 0000
--uu uuuu
ECCPR1H
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
ECCPR1L
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
ECCP1CON
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
0000 0000
ECCP1DEL
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
0000 0000
ECCPAS
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
0000 0000
CVRCON
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
CMCON
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
TMR3H
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
PIC18F2X8 PIC18F4X8
0000 0000
uuuu uuuu
uuuu uuuu
SPBRG
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
RCREG
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
TXREG
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
TXSTA
PIC18F2X8 PIC18F4X8
0000 -010
0000 -010
uuuu -uuu
RCSTA
PIC18F2X8 PIC18F4X8
0000 000x
0000 000u
uuuu uuuu
EEADR
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEDATA
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
EECON2
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
EECON1
PIC18F2X8 PIC18F4X8
xx-0 x000
uu-0 u000
uu-0 u000
IPR3
PIC18F2X8 PIC18F4X8
1111 1111
1111 1111
uuuu uuuu
PIR3
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
PIE3
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
IPR2
PIC18F2X8 PIC18F4X8
-1-1 1111
-1-1 1111
-u-u uuuu
PIR2
PIC18F2X8 PIC18F4X8
-0-0 0000
-0-0 0000
-u-u uuuu(1)
PIE2
PIC18F2X8 PIC18F4X8
-0-0 0000
-0-0 0000
-u-u uuuu
IPR1
PIC18F2X8 PIC18F4X8
1111 1111
1111 1111
uuuu uuuu
PIR1
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu(1)
PIE1
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
Register
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).
DS41159E-page 32
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TRISE
PIC18F2X8 PIC18F4X8
0000 -111
0000 -111
uuuu -uuu
TRISD
PIC18F2X8 PIC18F4X8
1111 1111
1111 1111
uuuu uuuu
TRISC
PIC18F2X8 PIC18F4X8
1111 1111
1111 1111
uuuu uuuu
TRISB
PIC18F2X8 PIC18F4X8
1111 1111
1111 1111
(5)
uuuu uuuu
-111 1111
-uuu uuuu(5)
---- -xxx
---- -uuu
---- -uuu
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIC18F2X8 PIC18F4X8
-xxx xxxx(5)
-uuu uuuu(5)
-uuu uuuu(5)
TRISA
PIC18F2X8 PIC18F4X8
-111 1111
LATE
PIC18F2X8 PIC18F4X8
LATD
LATC
LATB
LATA(5)
(5)
(5)
PORTE
PIC18F2X8 PIC18F4X8
---- -xxx
---- -000
---- -uuu
PORTD
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
PIC18F2X8 PIC18F4X8
-x0x 0000(5)
-u0u 0000(5)
-uuu uuuu(5)
TXERRCNT
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
RXERRCNT
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
COMSTAT
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
CIOCON
PIC18F2X8 PIC18F4X8
--00 ----
--00 ----
--uu ----
BRGCON3
PIC18F2X8 PIC18F4X8
-0-- -000
-0-- -000
-u-- -uuu
BRGCON2
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
BRGCON1
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
(5)
CANCON
PIC18F2X8 PIC18F4X8
xxxx xxx-
uuuu uuu-
uuuu uuu-
CANSTAT(6)
PIC18F2X8 PIC18F4X8
xxx- xxx-
uuu- uuu-
uuu- uuu-
RXB0D7
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D6
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D5
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D4
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D3
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D2
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D1
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0D0
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).
© 2006 Microchip Technology Inc.
DS41159E-page 33
PIC18FXX8
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
RXB0DLC
PIC18F2X8 PIC18F4X8
-xxx xxxx
-uuu uuuu
-uuu uuuu
RXB0EIDL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0EIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0SIDL
PIC18F2X8 PIC18F4X8
xxxx x-xx
uuuu u-uu
uuuu u-uu
RXB0SIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB0CON
PIC18F2X8 PIC18F4X8
000- 0000
000- 0000
uuu- uuuu
RXB1D7
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1D6
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1D5
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1D4
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1D3
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1D2
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1D1
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1D0
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1DLC
PIC18F2X8 PIC18F4X8
-xxx xxxx
-uuu uuuu
-uuu uuuu
RXB1EIDL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1EIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1SIDL
PIC18F2X8 PIC18F4X8
xxxx x-xx
uuuu u-uu
uuuu u-uu
RXB1SIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1CON
PIC18F2X8 PIC18F4X8
000- 0000
000- 0000
uuu- uuuu
TXB0D7
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D6
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D5
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D4
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D3
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D2
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D1
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D0
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0DLC
PIC18F2X8 PIC18F4X8
-x-- xxxx
-u-- uuuu
-u-- uuuu
TXB0EIDL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0EIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0SIDL
PIC18F2X8 PIC18F4X8
xxx- x-xx
uuu- u-uu
uuu- u-uu
Register
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).
DS41159E-page 34
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TXB0SIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0CON
PIC18F2X8 PIC18F4X8
-000 0-00
-000 0-00
-uuu u-uu
TXB1D7
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D6
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D5
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D4
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D3
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D2
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D1
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D0
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1DLC
PIC18F2X8 PIC18F4X8
-x-- xxxx
-u-- uuuu
-u-- uuuu
TXB1EIDL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1EIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1SIDL
PIC18F2X8 PIC18F4X8
xxx- x-xx
uuu- u-uu
uuu- u-uu
TXB1SIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1CON
PIC18F2X8 PIC18F4X8
0000 0000
0000 0000
uuuu uuuu
TXB2D7
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2D6
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2D5
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2D4
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2D3
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2D2
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2D1
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2D0
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2DLC
PIC18F2X8 PIC18F4X8
-x-- xxxx
-u-- uuuu
-u-- uuuu
TXB2EIDL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2EIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2SIDL
PIC18F2X8 PIC18F4X8
xxx- x-xx
uuu- u-uu
uuu- u-uu
TXB2SIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB2CON
PIC18F2X8 PIC18F4X8
-000 0-00
-000 0-00
-uuu u-uu
RXM1EIDL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXM1EIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
Register
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).
© 2006 Microchip Technology Inc.
DS41159E-page 35
PIC18FXX8
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
RXM1SIDL
PIC18F2X8 PIC18F4X8
xxx- --xx
uuu- --uu
uuu- --uu
RXM1SIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXM0EIDL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXM0EIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXM0SIDL
PIC18F2X8 PIC18F4X8
xxx- --xx
uuu- --uu
uuu- --uu
RXM0SIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF5EIDL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF5EIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF5SIDL
PIC18F2X8 PIC18F4X8
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF5SIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF4EIDL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF4EIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF4SIDL
PIC18F2X8 PIC18F4X8
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF4SIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF3EIDL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF3EIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF3SIDL
PIC18F2X8 PIC18F4X8
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF3SIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF2EIDL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF2EIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF2SIDL
PIC18F2X8 PIC18F4X8
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF2SIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF1EIDL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF1EIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF1SIDL
PIC18F2X8 PIC18F4X8
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF1SIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF0EIDL
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF0EIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF0SIDL
PIC18F2X8 PIC18F4X8
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF0SIDH
PIC18F2X8 PIC18F4X8
xxxx xxxx
uuuu uuuu
uuuu uuuu
Register
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).
DS41159E-page 36
© 2006 Microchip Technology Inc.
PIC18FXX8
4.0
MEMORY ORGANIZATION
There are three memory blocks in Enhanced MCU
devices. These memory blocks are:
• Enhanced Flash Program Memory
• Data Memory
• EEPROM Data Memory
4.1.1
Data and program memory use separate busses,
which allows concurrent access of these blocks.
Additional detailed information on data EEPROM and
Flash program memory is provided in Section 5.0
“Data EEPROM Memory” and Section 6.0 “Flash
Program Memory”, respectively.
4.1
Figure 4-1 shows the diagram for program memory
map and stack for the PIC18F248 and PIC18F448.
Figure 4-2 shows the diagram for the program memory
map and stack for the PIC18F258 and PIC18F458.
Program Memory Organization
The PIC18F258/458 devices have a 21-bit program
counter that is capable of addressing a 2-Mbyte
program memory space.
INTERNAL PROGRAM MEMORY
OPERATION
The PIC18F258 and the PIC18F458 have 32 Kbytes of
internal Enhanced Flash program memory. This means
that the PIC18F258 and the PIC18F458 can store up to
16K of single-word instructions. The PIC18F248 and
PIC18F448 have 16 Kbytes of Enhanced Flash
program memory. This translates into 8192 single-word
instructions, which can be stored in the program
memory. Accessing a location between the physically
implemented memory and the 2-Mbyte address will
cause a read of all ‘0’s (a NOP instruction).
The Reset vector address is at 0000h and the interrupt
vector addresses are at 0008h and 0018h.
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC18F248/448
FIGURE 4-2:
PROGRAM MEMORY MAP
AND STACK FOR
PIC18F258/458
PC
21
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
PC
21
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
•
•
•
•
•
•
Stack Level 31
Stack Level 31
Reset Vector
Reset Vector
0000h
0000h
High Priority Interrupt Vector 0008h
High Priority Interrupt Vector 0008h
Low Priority Interrupt Vector 0018h
Low Priority Interrupt Vector 0018h
User Memory Space
3FFFh
4000h
Read ‘0’
On-Chip
Program Memory
7FFFh
8000h
User Memory Space
On-Chip
Program Memory
Read ‘0’
1FFFFFh
200000h
© 2006 Microchip Technology Inc.
1FFFFFh
200000h
DS41159E-page 37
PIC18FXX8
4.2
Return Address Stack
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
PUSH, CALL or RCALL instruction is executed, or an
interrupt is Acknowledged. The PC value is pulled off
the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of
the RETURN instructions.
The stack operates as a 31-word by 21-bit stack
memory and a 5-bit Stack Pointer register, with the
Stack Pointer initialized to 00000b after all Resets.
There is no RAM associated with Stack Pointer
00000b. This is only a Reset value. During a CALL type
instruction, causing a push onto the stack, the Stack
Pointer is first incremented and the RAM location
pointed to by the Stack Pointer is written with the contents of the PC. During a RETURN type instruction,
causing a pop from the stack, the contents of the RAM
location indicated by the STKPTR are transferred to the
PC and then the Stack Pointer is decremented.
The stack space is not part of either program or data
space. The Stack Pointer is readable and writable and
the data on the top of the stack is readable and writable
through SFR registers. Status bits indicate if the stack
pointer is at or beyond the 31 levels provided.
4.2.1
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL allow
access to the contents of the stack location indicated by
the STKPTR register. This allows users to implement a
software stack, if necessary. After a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
The user should disable the global interrupt enable bits
during this time to prevent inadvertent stack
operations.
DS41159E-page 38
4.2.2
RETURN STACK POINTER
(STKPTR)
The STKPTR register contains the Stack Pointer value,
the STKFUL (Stack Full) status bit and the STKUNF
(Stack Underflow) status bits. Register 4-1 shows the
STKPTR register. The value of the Stack Pointer can be
0 through 31. The Stack Pointer increments when values are pushed onto the stack and decrements when
values are popped off the stack. At Reset, the Stack
Pointer value will be ‘0’. The user may read and write
the Stack Pointer value. This feature can be used by a
Real-Time Operating System for return stack
maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Overflow Reset Enable) configuration bit. Refer to
Section 21.0 “Comparator Module” for a description
of the device configuration bits. If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to ‘0’.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
The 32nd push will overwrite the 31st push (and so on),
while STKPTR remains at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at ‘0’. The STKUNF bit will remain set
until cleared in software or a POR occurs.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken.
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 4-1:
STKPTR: STACK POINTER REGISTER
R/C-0
R/C-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STKFUL
STKUNF
—
SP4
SP3
SP2
SP1
SP0
bit 7
bit 0
bit 7
STKFUL: Stack Full Flag bit
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6
STKUNF: Stack Underflow Flag bit
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0 SP4:SP0: Stack Pointer Location bits
Note:
Bit 7 and bit 6 need to be cleared following a stack underflow or a stack overflow.
Legend:
FIGURE 4-3:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
C = Clearable bit
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
11111
11110
11101
TOSU
00h
TOSH
1Ah
TOSL
34h
Top-of-Stack 001A34h
000D58h
000000h
STKPTR
00010
00011
00010
00001
00000(1)
Note 1: No RAM associated with this address; always maintained ‘0’s.
© 2006 Microchip Technology Inc.
DS41159E-page 39
PIC18FXX8
4.2.3
PUSH AND POP INSTRUCTIONS
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program execution, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the Stack Pointer and load the
current PC value onto the stack. TOSU, TOSH and
TOSL can then be modified to place a return address
on the stack.
EXAMPLE 4-1:
CALL SUB1, FAST
STACK FULL/UNDERFLOW RESETS
These Resets are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disabled, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device
Reset. When the STVREN bit is enabled, a full or
underflow condition will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. The
STKFUL or STKUNF bits are only cleared by the user
software or a POR.
4.3
Fast Register Stack
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
•
•
•
•
•
RETURN FAST
SUB1
The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed
onto the stack then becomes the TOS value.
4.2.4
FAST REGISTER STACK
CODE EXAMPLE
4.4
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
PCL, PCLATH and PCLATU
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits
wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called
the PCH register. This register contains the PC
bits and is not directly readable or writable. Updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC bits and is not directly
readable or writable. Updates to the PCU register may
be performed through the PCLATU register.
A “fast return” option is available for interrupts and
calls. A fast register stack is provided for the Status,
WREG and BSR registers and is only one layer in
depth. The stack is not readable or writable and is
loaded with the current value of the corresponding
register when the processor vectors for an interrupt.
The values in the fast register stack are then loaded
back into the working registers if the FAST RETURN
instruction is used to return from the interrupt.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSb of PCL is fixed to a value of ‘0’.
The PC increments by 2 to address sequential
instructions in the program memory.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority
interrupt will be overwritten.
The contents of PCLATH and PCLATU will be
transferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the
program counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1
“Computed GOTO”).
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
If high priority interrupts are not disabled during low
priority interrupts, users must save the key registers in
software during a low priority interrupt.
If no interrupts are used, the fast register stack can be
used to restore the Status, WREG and BSR registers at
the end of a subroutine call. To use the fast register
stack for a subroutine call, a FAST CALL instruction
must be executed.
Example 4-1 shows a source code example that uses
the fast register stack.
DS41159E-page 40
© 2006 Microchip Technology Inc.
PIC18FXX8
4.5
Clocking Scheme/Instruction
Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the
Program Counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-4.
FIGURE 4-4:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Internal
Phase
Clock
Q2
Q3
Q4
PC
OSC2/CLKO
(RC Mode)
4.6
PC
Fetch INST (PC)
Execute INST (PC – 2)
PC + 2
Fetch INST (PC + 2)
Execute INST (PC)
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
two cycles are required to complete the instruction
(Example 4-2).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
© 2006 Microchip Technology Inc.
4.7
PC + 4
Fetch INST (PC + 4)
Execute INST (PC + 2)
Instructions in Program Memory
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). Figure 4-3 shows an
example of how instruction words are stored in the
program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and
the LSB will always read ‘0’ (see Section 4.4 “PCL,
PCLATH and PCLATU”).
The CALL and GOTO instructions have an absolute
program memory address embedded into the instruction. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC,
which accesses the desired byte address in program
memory. Instruction #2 in Example 4-3 shows how the
instruction “GOTO 000006h” is encoded in the program
memory. Program branch instructions that encode a
relative address offset operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions by which the PC will
be offset. Section 25.0 “Instruction Set Summary”
provides further details of the instruction set.
DS41159E-page 41
PIC18FXX8
EXAMPLE 4-2:
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
TCY0
TCY1
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
TCY3
TCY5
Execute 3
Fetch 4
PORTA, BIT3 (Forced NOP)
Flush
Fetch SUB_1
5. Instruction @ address SUB_1
Note:
TCY4
Execute 2
Fetch 3
3. BRA SUB_1
4. BSF
TCY2
Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is
“flushed” from the pipeline while the new instruction is being fetched and then executed.
EXAMPLE 4-3:
INSTRUCTIONS IN PROGRAM MEMORY
Instruction
Opcode
Memory
0E55h
55h
—
MOVLW 055h
GOTO 000006h
MOVFF 123h, 456h
000007h
0EF03h, 0F000h
0C123h, 0F456h
DS41159E-page 42
000008h
0Eh
000009h
03h
00000Ah
0EFh
00000Bh
00h
00000Ch
0F0h
00000Dh
23h
00000Eh
0C1h
00000Fh
56h
000010h
0F4h
—
Address
000011h
000012h
© 2006 Microchip Technology Inc.
PIC18FXX8
4.7.1
TWO-WORD INSTRUCTIONS
The PIC18FXX8 devices have 4 two-word instructions:
MOVFF, CALL, GOTO and LFSR. The 4 Most Significant bits of the second word are set to ‘1’s and indicate
a special NOP instruction. The lower 12 bits of the
second word contain the data to be used by the
instruction. If the first word of the instruction is executed,
the data in the second word is accessed. If the second
word of the instruction is executed by itself (first word
was skipped), it will execute as a NOP. This action is
necessary when the two-word instruction is preceded by
a conditional instruction that changes the PC. A program
example that demonstrates this concept is shown in
Example 4-4. Refer to Section 25.0 “Instruction Set
Summary” for further details of the instruction set.
4.8
Look-up Tables
Look-up tables are implemented two ways. These are:
• Computed GOTO
• Table Reads
4.8.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL).
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
EXAMPLE 4-4:
instruction executed will be one of the RETLW 0xnn
instructions that returns the value 0xnn to the calling
function.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
Note 1: The LSb of PCL is fixed to a value of ‘0’.
Hence, computed GOTO to an odd address
is not possible.
2: The ADDWF PCL instruction does not
update PCLATH/PCLATU. A read operation on PCL must be performed to update
PCLATH and PCLATU.
4.8.2
TABLE READS/TABLE WRITES
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Look-up table data may be stored as 2 bytes per
program word by using table reads and writes. The
Table Pointer (TBLPTR) specifies the byte address and
the Table Latch (TABLAT) contains the data that is read
from, or written to, program memory. Data is
transferred to/from program memory, one byte at a
time.
A description of the table read/table write operation is
shown in Section 6.1 “Table Reads and Table Writes”.
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
1100 0001 0010 0011
MOVFF
REG1, REG2 ; No, execute 2-word instruction
ADDWF
REG3
1111 0100 0101 0110
0010 0100 0000 0000
; is RAM location 0?
; 2nd operand holds address of REG2
; continue code
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
1100 0001 0010 0011
MOVFF
REG1, REG2 ; Yes
1111 0100 0101 0110
0010 0100 0000 0000
© 2006 Microchip Technology Inc.
; is RAM location 0?
; 2nd operand becomes NOP
ADDWF
REG3
; continue code
DS41159E-page 43
PIC18FXX8
4.9
Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 4-6
shows the data memory organization for the
PIC18FXX8 devices.
The data memory map is divided into as many as
16 banks that contain 256 bytes each. The lower 4 bits
of the Bank Select Register (BSR) select which
bank will be accessed. The upper 4 bits for the BSR are
not implemented.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s application. The SFRs start at the last location of Bank 15
(FFFh) and grow downwards. GPRs start at the first
location of Bank 0 and grow upwards. Any read of an
unimplemented location will read as ‘0’s.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of
the File Select Register (FSR). Each FSR holds a
12-bit address value that can be used to access any
location in the data memory map without banking.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing or by the use of the MOVFF instruction. The
MOVFF instruction is a two-word/two-cycle instruction,
that moves a value from one register to another.
4.9.1
GENERAL PURPOSE
REGISTER FILE
The register file can be accessed either directly or
indirectly. Indirect addressing operates through the File
Select Registers (FSR). The operation of indirect
addressing is shown in Section 4.12 “Indirect
Addressing, INDF and FSR Registers”.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
Data RAM is available for use as GPR registers by all
instructions. Bank 15 (F00h to FFFh) contains SFRs.
All other banks of data memory contain GPR registers,
starting with Bank 0.
4.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 4-1.
The SFRs can be classified into two sets: those associated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The SFRs are typically distributed among the
peripherals whose functions they control.
The unused SFR locations will be unimplemented and
read as ‘0’s. See Table 4-1 for addresses for the SFRs.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 4.10
“Access Bank” provides a detailed description of the
Access RAM.
DS41159E-page 44
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 4-5:
DATA MEMORY MAP FOR PIC18F248/448
BSR
= 0000
= 0001
= 0010
Data Memory Map
00h
Access RAM
FFh
00h
GPR
Bank 0
GPR
Bank 1
1FFh
200h
FFh
00h
Bank 2
GPR
300h
FFh
= 0011
= 1110
000h
05Fh
060h
0FFh
100h
Bank 3
to
Bank 14
Access Bank
00h
Access Bank Low
(GPR)
5Fh
60h
Access Bank High
(SFR)
FFh
When a = 0,
the BSR is ignored and
the Access Bank is used.
Unused
Read ‘00h’
The first 96 bytes are
general purpose RAM
(from Bank 0).
The next 160 bytes are
Special Function
Registers (from Bank 15).
= 1111
00h
Unused
FFh
SFR
Bank 15
© 2006 Microchip Technology Inc.
EFFh
F00h
F5Fh
F60h
FFFh
When a = 1,
the BSR is used to specify
the RAM location that the
instruction uses.
DS41159E-page 45
PIC18FXX8
FIGURE 4-6:
DATA MEMORY MAP FOR PIC18F258/458
BSR
= 0000
= 0001
Data Memory Map
00h
Access RAM
FFh
00h
GPR
Bank 0
GPR
Bank 1
FFh
00h
= 0010
Bank 2
= 0011
1FFh
200h
GPR
2FFh
300h
FFh
00h
Bank 3
GPR
3FFh
400h
FFh
= 0100
= 0101
000h
05Fh
060h
0FFh
100h
Bank 4
Access Bank
GPR
4FFh
500h
00h
GPR
Bank 5
FFh
5FFh
600h
Access Bank low
(GPR)
Access Bank high
(SFR)
00h
5Fh
60h
FFh
= 0110
= 1110
Bank 6
to
Bank 14
When a = 0,
the BSR is ignored and the
Access Bank is used.
Unused
Read ‘00h’
The first 96 bytes are
general purpose RAM
(from Bank 0).
= 1111
00h
SFR
FFh
SFR
Bank 15
EFFh
F00h
F5Fh
F60h
FFFh
The next 160 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
the BSR is used to specify
the RAM location that the
instruction uses.
DS41159E-page 46
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 4-1:
Address
SPECIAL FUNCTION REGISTER MAP
Name
Address
FFFh TOSU
FDFh
Name
INDF2(2)
Address
Name
Address
FBFh CCPR1H
(2)
Name
F9Fh IPR1
FFEh TOSH
FDEh POSTINC2
FBEh CCPR1L
F9Eh PIR1
FFDh TOSL
FDDh POSTDEC2(2)
FBDh CCP1CON
F9Dh PIE1
FFCh STKPTR
FDCh PREINC2(2)
FBCh ECCPR1H(5)
F9Ch
FFBh PCLATU
(2)
FBBh ECCPR1L(5)
F9Bh
—
F9Ah
—
F99h
—
F98h
—
F97h
—
FDBh PLUSW2
FFAh PCLATH
FDAh FSR2H
FBAh ECCP1CON
FF9h PCL
FD9h FSR2L
FB9h
—
—
(5)
FF8h TBLPTRU
FD8h STATUS
FB8h
FF7h TBLPTRH
FD7h TMR0H
FB7h ECCP1DEL(5)
FF6h TBLPTRL
FD6h TMR0L
FF5h TABLAT
FD5h T0CON
FF4h PRODH
FD4h
FF3h PRODL
FD3h OSCCON
FF2h INTCON
FF1h INTCON2
—
FB6h
ECCPAS(5)
F96h TRISE(5)
FB5h
CVRCON(5)
F95h TRISD(5)
FB4h CMCON(5)
F94h TRISC
FB3h TMR3H
F93h TRISB
FD2h LVDCON
FB2h TMR3L
F92h TRISA
FD1h WDTCON
FB1h T3CON
F91h
—
—
FF0h INTCON3
FD0h RCON
FB0h
F90h
—
FEFh INDF0(2)
FCFh TMR1H
FAFh SPBRG
F8Fh
—
FCEh TMR1L
FAEh RCREG
F8Eh
—
FCDh T1CON
FADh TXREG
F8Dh LATE(5)
FCCh TMR2
FACh TXSTA
F8Ch LATD(5)
FCBh PR2
FABh RCSTA
F8Bh LATC
FEAh FSR0H
FCAh T2CON
FAAh
FE9h FSR0L
FC9h SSPBUF
FA9h EEADR
FE8h WREG
FC8h SSPADD
FA8h EEDATA
F88h
—
FE7h INDF1(2)
FC7h SSPSTAT
FA7h EECON2
F87h
—
FE6h POSTINC1(2)
FC6h SSPCON1
FA6h EECON1
F86h
—
FE5h POSTDEC1(2)
FC5h SSPCON2
FA5h IPR3
F85h
—
PREINC1(2)
FC4h ADRESH
FA4h PIR3
F84h PORTE(5)
(2)
FC3h ADRESL
FA3h PIE3
F83h PORTD(5)
FE2h FSR1H
FC2h ADCON0
FA2h IPR2
F82h PORTC
FE1h FSR1L
FC1h ADCON1
FA1h PIR2
F81h PORTB
FE0h BSR
FC0h
FA0h PIE2
F80h PORTA
(2)
FEEh POSTINC0
FEDh
POSTDEC0(2)
FECh PREINC0(2)
FEBh PLUSW0
FE4h
FE3h PLUSW1
Note 1:
2:
3:
4:
5:
(2)
—
—
—
F8Ah LATB
F89h LATA
Unimplemented registers are read as ‘0’.
This is not a physical register.
Contents of register are dependent on WIN2:WIN0 bits in the CANCON register.
CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given
for each instance of the CANSTAT register due to the Microchip header file requirement.
These registers are not implemented on the PIC18F248 and PIC18F258.
© 2006 Microchip Technology Inc.
DS41159E-page 47
PIC18FXX8
TABLE 4-1:
Address
SPECIAL FUNCTION REGISTER MAP (CONTINUED)
Name
F7Fh
—
Address
F5Fh
Name
Address
—
F3Fh
(4)
Name
Address
—
Name
F1Fh RXM1EIDL
F3Eh CANSTATRO3
(4)
F7Eh
—
F5Eh CANSTATRO1
F7Dh
—
F5Dh RXB1D7
F3Dh TXB1D7
F1Dh RXM1SIDL
F1Eh RXM1EIDH
F7Ch
—
F5Ch RXB1D6
F3Ch TXB1D6
F1Ch RXM1SIDH
F7Bh
—
F5Bh RXB1D5
F3Bh TXB1D5
F1Bh RXM0EIDL
F7Ah
—
F5Ah RXB1D4
F3Ah TXB1D4
F1Ah RXM0EIDH
F79h
—
F59h RXB1D3
F39h TXB1D3
F19h RXM0SIDL
F78h
—
F58h RXB1D2
F38h TXB1D2
F18h RXM0SIDH
F77h
—
F57h RXB1D1
F37h TXB1D1
F17h RXF5EIDL
F76h TXERRCNT
F56h RXB1D0
F36h TXB1D0
F16h RXF5EIDH
F75h RXERRCNT
F55h RXB1DLC
F35h TXB1DLC
F15h RXF5SIDL
F74h COMSTAT
F54h RXB1EIDL
F34h TXB1EIDL
F14h RXF5SIDH
F73h CIOCON
F53h RXB1EIDH
F33h TXB1EIDH
F13h RXF4EIDL
F72h BRGCON3
F52h RXB1SIDL
F32h TXB1SIDL
F12h RXF4EIDH
F71h BRGCON2
F51h RXB1SIDH
F31h TXB1SIDH
F11h RXF4SIDL
F70h BRGCON1
F50h RXB1CON
F30h TXB1CON
F10h RXF4SIDH
F6Fh CANCON
F4Fh
F2Fh
F0Fh RXF3EIDL
F6Eh CANSTAT
—
—
F4Eh CANSTATRO2(4)
F2Eh CANSTATRO4(4)
F0Eh RXF3EIDH
RXB0D7(3)
F4Dh TXB0D7
F2Dh TXB2D7
F0Dh RXF3SIDL
F6Ch RXB0D6(3)
F4Ch TXB0D6
F2Ch TXB2D6
F0Ch RXF3SIDH
F6Bh RXB0D5(3)
F4Bh TXB0D5
F2Bh TXB2D5
F0Bh RXF2EIDL
RXB0D4(3)
F4Ah TXB0D4
F2Ah TXB2D4
F0Ah RXF2EIDH
F69h RXB0D3(3)
F49h TXB0D3
F29h TXB2D3
F09h RXF2SIDL
RXB0D2(3)
F48h TXB0D2
F28h TXB2D2
F08h RXF2SIDH
F67h RXB0D1(3)
F47h TXB0D1
F27h TXB2D1
F07h RXF1EIDL
(3)
F6Dh
F6Ah
F68h
F46h TXB0D0
F26h TXB2D0
F06h RXF1EIDH
F65h RXB0DLC(3)
F45h TXB0DLC
F25h TXB2DLC
F05h RXF1SIDL
RXB0EIDL(3)
F44h TXB0EIDL
F24h TXB2EIDL
F04h RXF1SIDH
F63h RXB0EIDH(3)
F43h TXB0EIDH
F23h TXB2EIDH
F03h RXF0EIDL
(3)
F42h TXB0SIDL
F22h TXB2SIDL
F02h RXF0EIDH
F61h RXB0SIDH(3)
F41h TXB0SIDH
F21h TXB2SIDH
F01h RXF0SIDL
(3)
F40h TXB0CON
F20h TXB2CON
F00h RXF0SIDH
F66h RXB0D0
F64h
F62h RXB0SIDL
F60h RXB0CON
Note:
Note 1:
2:
3:
4:
5:
Shaded registers are available in Bank 15, while the rest are in Access Bank low.
Unimplemented registers are read as ‘0’.
This is not a physical register.
Contents of register are dependent on WIN2:WIN0 bits in the CANCON register.
CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given
for each instance of the CANSTAT register due to the Microchip header file requirement.
These registers are not implemented on the PIC18F248 and PIC18F258.
DS41159E-page 48
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 4-2:
File Name
REGISTER FILE SUMMARY
Bit 7
Bit 6
Bit 5
—
—
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Details on
Page:
---0 0000
30, 38
TOSH
Top-of-Stack High Byte (TOS)
0000 0000
30, 38
TOSL
Top-of-Stack Low Byte (TOS)
0000 0000
30, 38
Return Stack Pointer
00-0 0000
30, 39
Holding Register for PC
---0 0000
30, 40
TOSU
STKPTR
STKFUL
STKUNF
—
PCLATU
—
—
bit 21(2)
Top-of-Stack Upper Byte (TOS)
Value on
POR, BOR
PCLATH
Holding Register for PC
0000 0000
30, 40
PCL
PC Low Byte (PC)
0000 0000
30, 40
--00 0000
30, 68
TBLPTRU
—
—
bit 21(2)
Program Memory Table Pointer Upper Byte (TBLPTR)
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR)
0000 0000
30, 68
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR)
0000 0000
30, 68
TABLAT
Program Memory Table Latch
0000 0000
30, 68
PRODH
Product Register High Byte
xxxx xxxx
30, 75
PRODL
Product Register Low Byte
xxxx xxxx
30, 75
30, 79
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
INTCON2
RBPU
INTEDG0
INTEDG1
—
—
TMR0IP
—
RBIP
111- -1-1
30, 80
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
11-0 0-00
30, 81
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
30, 55
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
30, 55
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
30, 55
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
30, 55
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register)
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High
N/A
30, 55
---- xxxx
30, 55
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
30, 55
WREG
Working Register
xxxx xxxx
30, 55
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
30, 55
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
30, 55
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
30, 55
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
30, 55
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register)
FSR1H
FSR1L
BSR
—
—
—
—
Indirect Data Memory Address Pointer 1 High
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
—
Bank Select Register
N/A
30, 55
---- xxxx
31, 55
xxxx xxxx
31, 55
---- 0000
31, 54
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
31, 55
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
31, 55
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
31, 55
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
31, 55
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register)
FSR2H
FSR2L
STATUS
—
—
—
—
Indirect Data Memory Address Pointer 2 High
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
OV
Z
DC
C
N/A
31, 55
---- xxxx
31, 55
xxxx xxxx
31, 55
---x xxxx
31, 57
31, 111
TMR0H
Timer0 Register High Byte
0000 0000
TMR0L
Timer0 Register Low Byte
xxxx xxxx
31, 111
T0PS0
1111 1111
31, 109
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
OSCCON
—
—
—
—
—
—
—
SCS
---- ---0
31, 20
LVDCON
—
—
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
--00 0101
31, 261
WDTCON
—
—
—
—
—
—
—
SWDTEN
---- ---0
31, 272
IPEN
—
—
RI
TO
PD
POR
BOR
RCON
Legend:
Note 1:
2:
3:
0--1 110q 31, 58, 91
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes.
© 2006 Microchip Technology Inc.
DS41159E-page 49
PIC18FXX8
TABLE 4-2:
File Name
REGISTER FILE SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
Page:
TMR1H
Timer1 Register High Byte
xxxx xxxx
31, 116
TMR1L
Timer1 Register Low Byte
xxxx xxxx
31, 116
T1CON
RD16
0-00 0000
31, 113
TMR2
Timer2 Register
0000 0000
31, 118
PR2
Timer2 Period Register
1111 1111
31, 118
-000 0000
31, 117
T2CON
—
—
TOUTPS3
T1CKPS1
TOUTPS2
T1CKPS0
TOUTPS1
T1OSCEN
TOUTPS0
T1SYNC
TMR2ON
TMR1CS
TMR1ON
T2CKPS1
T2CKPS0
SSPBUF
SSP Receive Buffer/Transmit Register
xxxx xxxx
31, 146
SSPADD
SSP Address Register in I2C™ Slave mode. SSP Baud Rate Reload Register in I2C Master mode.
0000 0000
31, 152
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
31, 144,
153
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
31, 145,
145
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
SSPCON2
0000 0000
31, 155
ADRESH
A/D Result Register High Byte
xxxx xxxx
31, 243
ADRESL
A/D Result Register Low Byte
xxxx xxxx
31, 243
ADCON0
ADCON1
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0
31, 241
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
00-- 0000
32, 242
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
32, 124
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
32, 124
--00 0000
32, 123
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
ECCPR1H(1)
Enhanced Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
32, 133
ECCPR1L(1)
Enhanced Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
32, 133
ECCP1M1 ECCP1M0 0000 0000
32, 131
ECCP1CON(1)
EPWM1M1
EPWM1M0
EDC1B1
EDC1B0
ECCP1M3
ECCP1M2
ECCP1DEL(1)
EPDC7
EPDC6
EPDC5
EPDC4
EPDC3
EPDC2
EPDC1
EPDC0
0000 0000
32, 140
ECCPAS(1)
ECCPASE
ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
0000 0000
32, 142
CVRCON(1)
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
0000 0000
32, 255
CMCON(1)
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000
32, 249
TMR3H
Timer3 Register High Byte
xxxx xxxx
32, 121
TMR3L
Timer3 Register Low Byte
xxxx xxxx
32, 121
T3CON
RD16
T3ECCP1
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
0000 0000
32, 119
USART Baud Rate Generator
0000 0000
32, 185
RCREG
USART Receive Register
0000 0000
32, 191
TXREG
USART Transmit Register
0000 0000
32, 189
SPBRG
TXSTA
RCSTA
TMR3CS
TMR3ON
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
32, 183
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
32, 184
EEADR
EEPROM Address Register
xxxx xxxx
32, 59
EEDATA
EEPROM Data Register
xxxx xxxx
32, 59
EECON2
EEPROM Control Register 2 (not a physical register)
xxxx xxxx
32, 59
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
IPR3
EECON1
IRXIP
WAKIP
ERRIP
TXB2IP
TXB1IP
TXB0IP
RXB1IP
RXB0IP
1111 1111
32, 90
PIR3
IRXIF
WAKIF
ERRIF
TXB2IF
TXB1IF
TXB0IF
RXB1IF
RXB0IF
0000 0000
32, 84
PIE3
IRXIE
WAKIE
ERRIE
TXB2IE
TXB1IE
TXB0IE
RXB1IE
RXB0IE
0000 0000
32, 87
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
ECCP1IP(1) -1-1 1111
32, 89
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
ECCP1IF(1) -0-0 0000
32, 83
PIE2
—
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
ECCP1IE(1) -0-0 0000
32, 86
Legend:
Note 1:
2:
3:
xx-0 x000 32, 60, 67
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes.
DS41159E-page 50
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 4-2:
File Name
REGISTER FILE SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
Page:
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111
32, 88
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
32, 82
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
IBF
OBF
IBOV
PSPMODE
—
TRISE(1)
Data Direction bits for PORTE(1)
0000 0000
32, 85
0000 -111
33, 105
TRISD(1)
Data Direction Control Register for PORTD(1)
1111 1111
33, 102
TRISC
Data Direction Control Register for PORTC
1111 1111
33, 100
TRISB
Data Direction Control Register for PORTB
1111 1111
33, 96
-111 1111
33, 93
---- -xxx
33, 104
TRISA(3)
—
LATE(1)
—
Data Direction Control Register for PORTA
—
—
—
—
Read PORTE Data Latch, Write
PORTE Data Latch(1)
LATD(1)
Read PORTD Data Latch, Write PORTD Data Latch(1)
xxxx xxxx
33, 102
LATC
Read PORTC Data Latch, Write PORTC Data Latch
xxxx xxxx
33, 100
LATB
Read PORTB Data Latch, Write PORTB Data Latch
xxxx xxxx
33, 96
-xxx xxxx
33, 93
Read PORTE pins, Write PORTE Data ---- -xxx
Latch(1)
33, 104
LATA(3)
—
PORTE(1)
—
Read PORTA Data Latch, Write PORTA Data Latch
—
—
—
—
PORTD(1)
Read PORTD pins, Write PORTD Data Latch(1)
xxxx xxxx
33, 102
PORTC
Read PORTC pins, Write PORTC Data Latch
xxxx xxxx
33, 100
PORTB
Read PORTB pins, Write PORTB Data Latch
xxxx xxxx
33, 96
-x0x 0000
33, 93
PORTA(3)
—
Read PORTA pins, Write PORTA Data Latch
TXERRCNT
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
0000 0000
33, 209
RXERRCNT
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
0000 0000
33, 214
RXB0OVFL
RXB1OVFL
TXBO
TXBP
RXBP
TXWARN
RXWARN
EWARN
0000 0000
33, 205
—
—
ENDRHI
CANCAP
—
—
—
—
--00 ----
33, 221
COMSTAT
CIOCON
BRGCON3
—
WAKFIL
—
—
—
SEG2PH2
SEG2PH1
SEG2PH0 -0-- -000
33, 220
BRGCON2
SEG2PHTS
SAM
SEG1PH2
SEG1PH1
SEG1PH0
PRSEG2
PRSEG1
PRSEG0
0000 0000
33, 219
BRGCON1
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
0000 0000
33, 218
CANCON
REQOP2
REQOP1
REQOP0
ABAT
WIN2
WIN1
WIN0
—
xxxx xxx-
33, 201
CANSTAT
OPMODE2
OPMODE1
OPMODE0
—
ICODE2
ICODE1
ICODE0
—
xxx- xxx-
33, 202
RXB0D7
RXB0D77
RXB0D76
RXB0D75
RXB0D74
RXB0D73
RXB0D72
RXB0D71
RXB0D70
xxxx xxxx
33, 214
RXB0D6
RXB0D67
RXB0D66
RXB0D65
RXB0D64
RXB0D63
RXB0D62
RXB0D61
RXB0D60
xxxx xxxx
33, 214
RXB0D5
RXB0D57
RXB0D56
RXB0D55
RXB0D54
RXB0D53
RXB0D52
RXB0D51
RXB0D50
xxxx xxxx
33, 214
RXB0D4
RXB0D47
RXB0D46
RXB0D45
RXB0D44
RXB0D43
RXB0D42
RXB0D41
RXB0D40
xxxx xxxx
33, 214
RXB0D3
RXB0D37
RXB0D36
RXB0D35
RXB0D34
RXB0D33
RXB0D32
RXB0D31
RXB0D30
xxxx xxxx
33, 214
RXB0D2
RXB0D27
RXB0D26
RXB0D25
RXB0D24
RXB0D23
RXB0D22
RXB0D21
RXB0D20
xxxx xxxx
33, 214
RXB0D1
RXB0D17
RXB0D16
RXB0D15
RXB0D14
RXB0D13
RXB0D12
RXB0D11
RXB0D10
xxxx xxxx
33, 214
RXB0D0
RXB0D07
RXB0D06
RXB0D05
RXB0D04
RXB0D03
RXB0D02
RXB0D01
RXB0D00
xxxx xxxx
33, 214
—
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
-xxx xxxx
34, 213
34, 213
RXB0DLC
RXB0EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
RXB0EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
34, 212
RXB0SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
xxxx x-xx
34, 212
SID6
SID5
RXB0SIDH
SID10
SID9
SID8
SID7
RXB0CON
RXFUL
RXM1
RXM0
—
Legend:
Note 1:
2:
3:
RXRTRRO RXB0DBEN
SID4
SID3
xxxx xxxx
34, 212
JTOFF
FILHIT0
000- 0000
34, 210
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes.
© 2006 Microchip Technology Inc.
DS41159E-page 51
PIC18FXX8
TABLE 4-2:
REGISTER FILE SUMMARY (CONTINUED)
Bit 0
Value on
POR, BOR
Details on
Page:
ICODE0
—
xxx- xxx-
33, 202
RXB1D71
RXB1D70
xxxx xxxx
34, 214
RXB1D61
RXB1D60
xxxx xxxx
34, 214
RXB1D52
RXB1D51
RXB1D50
xxxx xxxx
34, 214
RXB1D43
RXB1D42
RXB1D41
RXB1D40
xxxx xxxx
34, 214
RXB1D34
RXB1D33
RXB1D32
RXB1D31
RXB1D30
xxxx xxxx
34, 214
RXB1D25
RXB1D24
RXB1D23
RXB1D22
RXB1D21
RXB1D20
xxxx xxxx
34, 214
RXB1D16
RXB1D15
RXB1D14
RXB1D13
RXB1D12
RXB1D11
RXB1D10
xxxx xxxx
34, 214
RXB1D07
RXB1D06
RXB1D05
RXB1D04
RXB1D03
RXB1D02
RXB1D01
RXB1D00
xxxx xxxx
34, 214
—
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
-xxx xxxx
34, 213
34, 213
File Name
Bit 7
Bit 6
Bit 5
CANSTATRO1
OPMODE2
OPMODE1
OPMODE0
—
ICODE2
ICODE1
RXB1D7
RXB1D77
RXB1D76
RXB1D75
RXB1D74
RXB1D73
RXB1D72
RXB1D6
RXB1D67
RXB1D66
RXB1D65
RXB1D64
RXB1D63
RXB1D62
RXB1D5
RXB1D57
RXB1D56
RXB1D55
RXB1D54
RXB1D53
RXB1D4
RXB1D47
RXB1D46
RXB1D45
RXB1D44
RXB1D3
RXB1D37
RXB1D36
RXB1D35
RXB1D2
RXB1D27
RXB1D26
RXB1D1
RXB1D17
RXB1D0
RXB1DLC
Bit 4
Bit 3
Bit 2
Bit 1
RXB1EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
RXB1EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
34, 212
RXB1SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
xxxx x-xx
34, 212
34, 212
RXB1SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
RXB1CON
RXFUL
RXM1
RXM0
—
RXRTRRO
FILHIT2
FILHIT1
FILHIT0
000- 0000
34, 211
OPMODE2
OPMODE1
OPMODE0
—
ICODE2
ICODE1
ICODE0
—
xxx- xxx-
33, 202
TXB0D7
TXB0D77
TXB0D76
TXB0D75
TXB0D74
TXB0D73
TXB0D72
TXB0D71
TXB0D70
xxxx xxxx
34, 208
TXB0D6
TXB0D67
TXB0D66
TXB0D65
TXB0D64
TXB0D63
TXB0D62
TXB0D61
TXB0D60
xxxx xxxx
34, 208
TXB0D5
TXB0D57
TXB0D56
TXB0D55
TXB0D54
TXB0D53
TXB0D52
TXB0D51
TXB0D50
xxxx xxxx
34, 208
TXB0D4
TXB0D47
TXB0D46
TXB0D45
TXB0D44
TXB0D43
TXB0D42
TXB0D41
TXB0D40
xxxx xxxx
34, 208
TXB0D3
TXB0D37
TXB0D36
TXB0D35
TXB0D34
TXB0D33
TXB0D32
TXB0D31
TXB0D30
xxxx xxxx
34, 208
TXB0D2
TXB0D27
TXB0D26
TXB0D25
TXB0D24
TXB0D23
TXB0D22
TXB0D21
TXB0D20
xxxx xxxx
34, 208
TXB0D1
TXB0D17
TXB0D16
TXB0D15
TXB0D14
TXB0D13
TXB0D12
TXB0D11
TXB0D10
xxxx xxxx
34, 208
TXB0D0
TXB0D07
TXB0D06
TXB0D05
TXB0D04
TXB0D03
TXB0D02
TXB0D01
TXB0D00
xxxx xxxx
34, 208
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx
34, 209
34, 208
CANSTATRO2
TXB0DLC
TXB0EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
TXB0EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
34, 207
TXB0SIDL
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx
34, 207
TXB0SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
35, 207
TXB0CON
—
TXABT
TXLARB
TXERR
TXREQ
—
TXPRI1
TXPRI0
-000 0-00
35, 206
CANSTATRO3
OPMODE2
OPMODE1
OPMODE0
—
ICODE2
ICODE1
ICODE0
—
xxx- xxx-
33, 202
TXB1D7
TXB1D77
TXB1D76
TXB1D75
TXB1D74
TXB1D73
TXB1D72
TXB1D71
TXB1D70
xxxx xxxx
35, 208
TXB1D6
TXB1D67
TXB1D66
TXB1D65
TXB1D64
TXB1D63
TXB1D62
TXB1D61
TXB1D60
xxxx xxxx
35, 208
TXB1D5
TXB1D57
TXB1D56
TXB1D55
TXB1D54
TXB1D53
TXB1D52
TXB1D51
TXB1D50
xxxx xxxx
35, 208
TXB1D4
TXB1D47
TXB1D46
TXB1D45
TXB1D44
TXB1D43
TXB1D42
TXB1D41
TXB1D40
xxxx xxxx
35, 208
TXB1D3
TXB1D37
TXB1D36
TXB1D35
TXB1D34
TXB1D33
TXB1D32
TXB1D31
TXB1D30
xxxx xxxx
35, 208
TXB1D2
TXB1D27
TXB1D26
TXB1D25
TXB1D24
TXB1D23
TXB1D22
TXB1D21
TXB1D20
xxxx xxxx
35, 208
TXB1D1
TXB1D17
TXB1D16
TXB1D15
TXB1D14
TXB1D13
TXB1D12
TXB1D11
TXB1D10
xxxx xxxx
35, 208
TXB1D0
TXB1D07
TXB1D06
TXB1D05
TXB1D04
TXB1D03
TXB1D02
TXB1D01
TXB1D00
xxxx xxxx
35, 208
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx
35, 209
35, 208
TXB1DLC
TXB1EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
TXB1EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
35, 207
TXB1SIDL
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx
35, 207
TXB1SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
35, 207
TXB1CON
—
TXABT
TXLARB
TXERR
TXREQ
—
TXPRI1
TXPRI0
0000 0000
35, 206
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes.
DS41159E-page 52
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 4-2:
REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
CANSTATRO4
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
Page:
OPMODE2
OPMODE1
OPMODE0
—
ICODE2
ICODE1
ICODE0
—
xxx- xxx-
33, 202
TXB2D7
TXB2D77
TXB2D76
TXB2D75
TXB2D74
TXB2D73
TXB2D72
TXB2D71
TXB2D70
xxxx xxxx
35, 208
TXB2D6
TXB2D67
TXB2D66
TXB2D65
TXB2D64
TXB2D63
TXB2D62
TXB2D61
TXB2D60
xxxx xxxx
35, 208
TXB2D5
TXB2D57
TXB2D56
TXB2D55
TXB2D54
TXB2D53
TXB2D52
TXB2D51
TXB2D50
xxxx xxxx
35, 208
TXB2D4
TXB2D47
TXB2D46
TXB2D45
TXB2D44
TXB2D43
TXB2D42
TXB2D41
TXB2D40
xxxx xxxx
35, 208
TXB2D3
TXB2D37
TXB2D36
TXB2D35
TXB2D34
TXB2D33
TXB2D32
TXB2D31
TXB2D30
xxxx xxxx
35, 208
TXB2D2
TXB2D27
TXB2D26
TXB2D25
TXB2D24
TXB2D23
TXB2D22
TXB2D21
TXB2D20
xxxx xxxx
35, 208
TXB2D1
TXB2D17
TXB2D16
TXB2D15
TXB2D14
TXB2D13
TXB2D12
TXB2D11
TXB2D10
xxxx xxxx
35, 208
TXB2D0
TXB2D07
TXB2D06
TXB2D05
TXB2D04
TXB2D03
TXB2D02
TXB2D01
TXB2D00
xxxx xxxx
35, 208
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx
35, 209
35, 208
TXB2DLC
TXB2EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
TXB2EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
35, 207
TXB2SIDL
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx
35, 207
TXB2SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
35, 207
TXB2CON
—
TXABT
TXLARB
TXERR
TXREQ
—
TXPRI1
TXPRI0
-000 0-00
35, 206
35, 217
RXM1EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
RXM1EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
35, 217
RXM1SIDL
SID2
SID1
SID0
—
—
—
EID17
EID16
xxx- --xx
36, 217
RXM1SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
36, 216
RXM0EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
36, 217
RXM0EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
36, 217
RXM0SIDL
SID2
SID1
SID0
—
—
—
EID17
EID16
xxx- --xx
36, 217
RXM0SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
36, 216
RXF5EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
36, 216
RXF5EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
36, 216
RXF5SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
xxx- x-xx
36, 215
RXF5SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
36, 215
RXF4EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
36, 216
RXF4EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
36, 216
RXF4SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
xxx- x-xx
36, 215
RXF4SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
36, 215
RXF3EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
36, 216
RXF3EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
36, 216
RXF3SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
xxx- x-xx
36, 215
RXF3SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
36, 215
RXF2EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
36, 216
RXF2EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
36, 216
RXF2SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
xxx- x-xx
36, 215
RXF2SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
36, 215
RXF1EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
36, 216
RXF1EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
36, 216
RXF1SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
xxx- x-xx
36, 215
RXF1SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
36, 215
RXF0EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx
36, 216
RXF0EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx
36, 216
RXF0SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
xxx- x-xx
36, 215
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx
36, 215
RXF0SIDH
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes.
© 2006 Microchip Technology Inc.
DS41159E-page 53
PIC18FXX8
4.10
Access Bank
4.11
The Access Bank is an architectural enhancement that
is very useful for C compiler code optimization. The
techniques used by the C compiler are also useful for
programs written in assembly.
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
This data memory region can be used for:
•
•
•
•
•
BSR holds the upper 4 bits of the 12-bit RAM
address. The BSR bits will always read ‘0’s and
writes will have no effect.
Intermediate computational values
Local variables of subroutines
Faster context saving/switching of variables
Common variables
Faster evaluation/control of SFRs (no banking)
A MOVLB instruction has been provided in the
instruction set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all ‘0’s and all writes are ignored. The
Status register bits will be set/cleared as appropriate for
the instruction performed.
The Access Bank is comprised of the upper 160 bytes
in Bank 15 (SFRs) and the lower 96 bytes in Bank 0.
These two sections will be referred to as Access Bank
High and Access Bank Low, respectively. Figure 4-6
indicates the Access Bank areas.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank.
A MOVFF instruction ignores the BSR since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 “Indirect Addressing, INDF and FSR
Registers” provides a description of indirect addressing, which allows linear addressing of the entire RAM
space.
When forced in the Access Bank (a = 0), the last
address in Access Bank Low is followed by the first
address in Access Bank High. Access Bank High maps
most of the Special Function Registers so that these
registers can be accessed without any software
overhead.
FIGURE 4-7:
Bank Select Register (BSR)
DIRECT ADDRESSING
Direct Addressing
BSR
Bank Select(2)
7
From Opcode(3)
0
Location Select(3)
00h
01h
0Eh
0Fh
000h
100h
0E00h
0F00h
0FFh
1FFh
0EFFh
0FFFh
Bank 14
Bank 15
Data
Memory(1)
Bank 0
Bank 1
Note 1: For register file map detail, see Table 4-1.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR) to the
registers of the Access Bank.
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
DS41159E-page 54
© 2006 Microchip Technology Inc.
PIC18FXX8
4.12
Indirect Addressing, INDF and
FSR Registers
Indirect addressing is a mode of addressing data memory where the data memory address in the instruction
is not fixed. A SFR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-8
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address
specified by the value of the FSR register.
Indirect addressing is possible by using one of the INDF
registers. Any instruction using the INDF register actually
accesses the register indicated by the File Select Register, FSR. Reading the INDF register itself, indirectly
(FSR = 0), will read 00h. Writing to the INDF register
indirectly, results in a no operation. The FSR register
contains a 12-bit address which is shown in Figure 4-8.
The INDFn (0 ≤ n ≤ 2) register is not a physical register.
Addressing INDFn actually addresses the register
whose address is contained in the FSRn register
(FSRn is a pointer). This is indirect addressing.
Example 4-5 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 4-5:
NEXT
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
LFSR
FSR0, 100h ;
CLRF
POSTINC0
BTFSS
FSR0H, 1
BRA
CONTINUE
:
NEXT
;
;
;
;
;
;
;
;
4.12.1
INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated with
it, plus four additional register addresses. Performing an
operation on one of these five registers determines how
the FSR will be modified during indirect addressing.
• When data access is done to one of the five
INDFn locations, the address selected will
configure the FSRn register to:
- Do nothing to FSRn after an indirect access
(no change) – INDFn
- Auto-decrement FSRn after an indirect
access (post-decrement) – POSTDECn
- Auto-increment FSRn after an indirect
access (post-increment) – POSTINCn
- Auto-increment FSRn before an indirect
access (pre-increment) – PREINCn
- Use the value in the WREG register as an
offset to FSRn. Do not modify the value of the
WREG or the FSRn register after an indirect
access (no change) – PLUSWn
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
Status register. For example, if the indirect address
causes the FSR to equal ‘0’, the Z bit will not be set.
Clear INDF
register
& inc pointer
All done
w/ Bank1?
NO, clear next
Incrementing or decrementing an FSR affects all
12 bits. That is, when FSRnL overflows from an
increment, FSRnH will be incremented automatically.
YES, continue
Each FSR has an address associated with it that
performs an indexed indirect access. When a data
access to this INDFn location (PLUSWn) occurs, the
FSRn is configured to add the 2’s complement value in
the WREG register and the value in FSR to form the
address before an indirect access. The FSR value is not
changed.
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12 bits wide. To store the 12 bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect addressing, with the value in the corresponding FSR register
being the address of the data.
If an instruction writes a value to INDF0, the value will
be written to the address indicated by FSR0H:FSR0L.
A read from INDF1 reads the data from the address
indicated by FSR1H:FSR1L. INDFn can be used in
code anywhere an operand can be used.
© 2006 Microchip Technology Inc.
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all ‘0’s are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOP instruction and the
Status bits are not affected.
Adding these features allows the FSRn to be used as a
software stack pointer in addition to its uses for table
operations in data memory.
If an FSR register contains a value that indicates one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(Status bits are not affected).
If an indirect addressing operation is done where the
target address is an FSRnH or FSRnL register, the
write operation will dominate over the pre- or
post-increment/decrement functions.
DS41159E-page 55
PIC18FXX8
FIGURE 4-8:
INDIRECT ADDRESSING
Indirect Addressing
FSR Register
11
8
7
FSRnH
0
FSRnL
Location Select
0000h
Data
Memory(1)
0FFFh
Note 1: For register file map detail, see Table 4-1.
DS41159E-page 56
© 2006 Microchip Technology Inc.
PIC18FXX8
4.13
Status Register
The Status register, shown in Register 4-2, contains the
arithmetic status of the ALU. The Status register can be
the destination for any instruction, as with any other
register. If the Status register is the destination for an
instruction that affects the Z, DC, C, OV or N bits, then
the write to these five bits is disabled. These bits are set
or cleared according to the device logic. Therefore, the
result of an instruction with the Status register as
destination may be different than intended.
REGISTER 4-2:
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the Status register as
000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to
alter the Status register, because these instructions do
not affect the Z, C, DC, OV or N bits from the Status
register. For other instructions which do not affect the
status bits, see Table 25-2.
Note:
The C and DC bits operate as a Borrow
and Digit Borrow bit respectively, in
subtraction.
STATUS REGISTER
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
N
OV
Z
DC
C
bit 7
bit 0
bit 7-5
Unimplemented: Read as ‘0’
bit 4
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result of the ALU
operation was negative (ALU MSb = 1).
1 = Result was negative
0 = Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
Note:
bit 0
For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s
complement of the second operand. For rotate (RRCF, RRNCF, RLCF and RLNCF)
instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
C: Carry/Borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note:
For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low-order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 57
PIC18FXX8
4.14
RCON Register
Note 1: If the BOREN configuration bit is set,
BOR is ‘1’ on Power-on Reset. If the
BOREN configuration bit is clear, BOR is
unknown on Power-on Reset.
The BOR status bit is a “don’t care” and is
not necessarily predictable if the brownout circuit is disabled (the BOREN configuration bit is clear). BOR must then be set
by the user and checked on subsequent
Resets to see if it is clear, indicating a
brown-out has occurred.
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device Reset. These flags include the TO, PD, POR,
BOR and RI bits. This register is readable and writable.
2: It is recommended that the POR bit be set
after a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
REGISTER 4-3:
RCON: RESET CONTROL REGISTER
R/W-0
U-0
U-0
R/W-1
R/W
R/W
R/W-0
R/W-0
IPEN
—
—
RI
TO
PD
POR
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5
Unimplemented: Read as ‘0’
bit 4
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed
0 = The RESET instruction was executed causing a device Reset
(must be set in software after a Brown-out Reset occurs)
bit 3
TO: Watchdog Time-out Flag bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2
PD: Power-down Detection Flag bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 1
POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
DS41159E-page 58
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
5.0
DATA EEPROM MEMORY
The data EEPROM is readable and writable during
normal operation over the entire VDD range. The data
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).
There are four SFRs used to read and write the
program and data EEPROM memory. These registers
are:
•
•
•
•
EECON1
EECON2
EEDATA
EEADR
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed. The
PIC18FXX8 devices have 256 bytes of data EEPROM
with an address range from 00h to FFh.
The EEPROM data memory is rated for high erase/
write cycles. A byte write automatically erases the location and writes the new data (erase-before-write). The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature, as well as
from chip-to-chip. Please refer to the specifications for
exact limits.
© 2006 Microchip Technology Inc.
5.1
EEADR Register
The address register can address up to a maximum of
256 bytes of data EEPROM.
5.2
EECON1 and EECON2 Registers
EECON1 is the control register for EEPROM memory
accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the EEPROM write sequence.
Control bits, RD and WR, initiate read and write operations, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset, during normal operation. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR) due to the Reset condition forcing the
contents of the registers to zero.
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.
DS41159E-page 59
PIC18FXX8
REGISTER 5-1:
EECON1: EEPROM CONTROL REGISTER 1
R/W-x
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access program Flash memory
0 = Access data EEPROM memory
bit 6
CFGS: Flash Program/Data EE or Configuration Select bit
1 = Access Configuration registers
0 = Access program Flash or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(reset by hardware)
0 = Perform write only
bit 3
WRERR: Write Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR or any WDT Reset during self-timed programming in normal operation)
0 = The write operation completed
Note:
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
bit 2
WREN: Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM or Flash memory
bit 1
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0 = Write cycle is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0 = Does not initiate an EEPROM read
Legend:
DS41159E-page 60
R = Readable bit
W = Writable bit
S = Settable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
5.3
Reading the Data EEPROM
Memory
5.4
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD and
CFGS control bits (EECON1) and then set
control bit RD (EECON1). The data is available in
the very next instruction cycle of the EEDATA register;
therefore, it can be read by the next instruction.
EEDATA will hold this value until another read
operation or until it is written to by the user (during a
write operation).
EXAMPLE 5-1:
DATA EEPROM READ
MOVLW
MOVWF
DATA_EE_ADDR
EEADR
BCF
BCS
BSF
MOVF
EECON1,
EECON1,
EECON1,
EEDATA,
EEPGD
CFGS
RD
W
;
;Data Memory Address
;to read
;Point to DATA memory
;
;EEPROM Read
;W = EEDATA
Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data written to the EEDATA register. Then, the sequence in
Example 5-2 must be followed to initiate the write cycle.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. The user may either
enable this interrupt or roll this bit. EEIF must be
cleared by software.
EXAMPLE 5-2:
Required
Sequence
DATA EEPROM WRITE
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDATA
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
;
;
;
;
;
;
;
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
;
;
;
;
;
;
;
.
.
.
BCF
Data Memory Address to read
Data Memory Value to write
Point to DATA memory
Access program FLASH or Data EEPROM memory
Enable writes
Disable interrupts
Write 55h
Write AAh
Set WR bit to begin write
Enable interrupts
; user code execution
EECON1, WREN
© 2006 Microchip Technology Inc.
; Disable writes on write complete (EEIF set)
DS41159E-page 61
PIC18FXX8
5.5
Write Verify
5.7
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
Operation During Code-Protect
Data EEPROM memory has its own code-protect
mechanism. External read and write operations are
disabled if either of these mechanisms are enabled.
Generally, a write failure will be a bit which was written
as a ‘1’, but reads back as a ‘0’ (due to leakage off the
cell).
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect configuration bit. Refer to Section 24.0
“Special Features of the CPU” for additional
information.
5.6
5.8
Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
reduce the probability of an accidental write during
brown-out, power glitch or software malfunction.
The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often).
Frequently changing values will typically be updated
more often than specification D124 or D124A. If this is
not the case, an array refresh must be performed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory. A simple data EEPROM
refresh routine is shown in Example 5-3.
Note:
EXAMPLE 5-3:
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124 or D124A.
DATA EEPROM REFRESH ROUTINE
CLRF
BCF
BCF
BCF
BSF
EEADR
EECON1,
EECON1,
INTCON,
EECON1,
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
EECON1, RD
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
$-2
INCFSZ
BRA
EEADR, F
Loop
; Increment address
; Not zero, do it again
BCF
BSF
EECON1, WREN
INTCON, GIE
; Disable writes
; Enable interrupts
CFGS
EEPGD
GIE
WREN
Loop
DS41159E-page 62
Using the Data EEPROM
;
;
;
;
;
;
;
;
;
;
;
;
;
Start at address 0
Set for memory
Set for Data EEPROM
Disable interrupts
Enable writes
Loop to refresh array
Read current address
Write 55h
Write AAh
Set WR bit to begin write
Wait for write to complete
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 5-1:
Name
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Bit 7
Bit 6
Bit 5
Value on
all other
Resets
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
EEADR
EEPROM Address Register
xxxx xxxx uuuu uuuu
EEDATA
EEPROM Data Register
xxxx xxxx uuuu uuuu
EECON2
EEPROM Control Register 2 (not a physical register)
—
CFGS
—
FREE
WRERR
WREN
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP ECCP1IP(1) -1-1 1111 -1-1 1111
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF ECCP1IF(1) -0-0 0000 -0-0 0000
PIE2
—
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE ECCP1IE(1) -0-0 0000 -0-0 0000
Legend:
Note 1:
WR
RD
—
EEPGD
EECON1
xx-0 x000 uu-0 u000
x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
© 2006 Microchip Technology Inc.
DS41159E-page 63
PIC18FXX8
NOTES:
DS41159E-page 64
© 2006 Microchip Technology Inc.
PIC18FXX8
6.0
FLASH PROGRAM MEMORY
6.1
Table Reads and Table Writes
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data
RAM:
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 8 bytes at a time. Program memory is erased
in blocks of 64 bytes at a time. A bulk erase operation
may not be issued from user code.
• Table Read (TBLRD)
• Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Writing or erasing program memory will cease instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 6-1 shows the operation of a table read with
program memory and data RAM.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5
“Writing to Flash Program Memory”. Figure 6-2
shows the operation of a table write with program
memory and data RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word aligned. Therefore, a table block
can start and end at any byte address. If a table write is
being used to write executable code into program
memory, program instructions will need to be word
aligned.
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer points to a byte in program memory.
© 2006 Microchip Technology Inc.
DS41159E-page 65
PIC18FXX8
FIGURE 6-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL.
The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash
Program Memory”.
6.2
Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
•
•
•
•
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
6.2.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit EEPGD determines if the access will be a
program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
Control bit CFGS determines if the access will be to the
Configuration/Calibration registers or to program
memory/data EEPROM memory. When set,
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 24.0
“Special Features of the CPU”). When clear, memory
selection access is determined by EEPGD.
DS41159E-page 66
The FREE bit, when set, will allow a program memory
erase operation. When the FREE bit is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal operation. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR) due to Reset values of zero.
Control bits, RD and WR, initiate read and write operations, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation. The RD
bit cannot be set when accessing program memory
(EEPGD = 1).
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 6-1:
EECON1: EEPROM CONTROL REGISTER 1
R/W-x
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access program Flash memory
0 = Access data EEPROM memory
bit 6
CFGS: Flash Program/Data EE or Configuration Select bit
1 = Access Configuration registers
0 = Access program Flash or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write only
bit 3
WRERR: Write Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR or any WDT Reset during self-timed programming in normal operation)
0 = The write operation completed
Note:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
bit 2
WREN: Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM or Flash memory
bit 1
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
S = Settable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 67
PIC18FXX8
6.2.2
TABLAT – TABLE LATCH REGISTER
6.2.4
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data RAM.
6.2.3
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the Table
Pointer determine which byte is read from program
memory into TABLAT.
TBLPTR – TABLE POINTER
REGISTER
When a TBLWT is executed, the three LSbs of the Table
Pointer (TBLPTR) determine which of the eight
program memory holding registers is written to. When
the timed write to program memory (long write) begins,
the 19 MSbs of the Table Pointer, TBLPTR
(TBLPTR), will determine which program
memory block of 8 bytes is written to. For more detail,
see Section 6.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the configuration bits.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer (TBLPTR) point to
the 64-byte block that will be erased. The Least
Significant bits (TBLPTR) are ignored.
The Table Pointer, TBLPTR, is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways based on the table
operation. These operations are shown in Table 6-1.
These operations on the TBLPTR only affect the
low-order 21 bits.
TABLE 6-1:
Operation on Table Pointer
TBLRD*
TBLWT*
TBLRD*+
TBLWT*+
TBLRD*TBLWT*TBLRD+*
TBLWT+*
21
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example
FIGURE 6-3:
TABLE POINTER BOUNDARIES
TBLPTR is not modified
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU
16
15
TBLPTRH
8
7
TBLPTRL
0
ERASE – TBLPTR
WRITE – TBLPTR
READ – TBLPTR
DS41159E-page 68
© 2006 Microchip Technology Inc.
PIC18FXX8
6.3
Reading the Flash Program
Memory
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
FIGURE 6-4:
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx0
TBLPTR = xxxxx1
Instruction Register
(IR)
EXAMPLE 6-1:
FETCH
TBLRD
TABLAT
Read Register
READING A FLASH PROGRAM MEMORY WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVF
MOVWF
TABLAT, W
WORD_LSB
TABLAT, W
WORD_MSB
© 2006 Microchip Technology Inc.
; read into TABLAT and increment
; get data
; read into TABLAT and increment
; get data
DS41159E-page 69
PIC18FXX8
6.4
Erasing Flash Program Memory
6.4.1
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
bulk erased. Word erase in the Flash array is not
supported.
The sequence of events for erasing a block of internal
program memory location is:
1.
When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR point to the block being erased.
TBLPTR are ignored.
2.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash
program memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
3.
4.
5.
6.
For protection, the write initiate sequence for EECON2
must be used.
7.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 6-2:
FLASH PROGRAM MEMORY
ERASE SEQUENCE
8.
Load Table Pointer with address of row being
erased.
Set the EECON1 register for the erase operation:
• set the EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set the WREN bit to enable writes;
• set the FREE bit to enable the erase.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit. This will begin the row erase
cycle.
The CPU will stall for duration of the erase
(about 2 ms using internal timer).
Re-enable interrupts.
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
upper (CODE_ADDR)
TBLPTRU
high (CODE_ADDR)
TBLPTRH
low (CODE_ADDR)
TBLPTRL
; load TBLPTR with the base
; address of the memory block
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
EECON1,
EECON1,
EECON1,
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
;
;
;
;
;
ERASE_ROW
Required
Sequence
DS41159E-page 70
EEPGD
CFGS
WREN
FREE
GIE
point to FLASH program memory
access FLASH program memory
enable write to memory
enable Row Erase operation
disable interrupts
; write 55H
WR
INTCON, GIE
;
;
;
;
write 0AAH
start erase (CPU stall)
NOP needed for proper code execution
re-enable interrupts
© 2006 Microchip Technology Inc.
PIC18FXX8
6.5
6.5.1
Writing to Flash Program Memory
The minimum programming block is 4 words or 8 bytes.
Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 8 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction has to be executed 8 times for
each programming operation. All of the table write
operations will essentially be short writes, because only
the holding registers are written. At the end of updating
8 registers, the EECON1 register must be written to, to
start the programming operation with a long write.
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range of
the device for byte or word operations.
FLASH PROGRAM MEMORY WRITE
SEQUENCE
8.
9.
10.
11.
12.
13.
14.
15.
Read 64 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer with address being erased.
Do the row erase procedure.
Load Table Pointer with address of first byte
being written.
Write the first 8 bytes into the holding registers
using the TBLWT instruction, auto-increment
may be used.
Set the EECON1 register for the write operation:
• set the EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set the WREN to enable byte writes.
Disable interrupts.
Write 55h to EECON2.
Write AAh to EECON2.
Set the WR bit. This will begin the write cycle.
The CPU will stall for duration of the write (about
2 ms using internal timer).
Re-enable interrupts.
Repeat steps 6-14 seven times to write
64 bytes.
Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
Note:
FIGURE 6-5:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 8 bytes in
the holding registers.
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx1
Holding Register
8
TBLPTR = xxxxx2
Holding Register
Holding Register
8
TBLPTR = xxxxx7
Holding Register
Program Memory
© 2006 Microchip Technology Inc.
DS41159E-page 71
PIC18FXX8
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64
COUNTER
high (BUFFER_ADDR)
FSR0H
low (BUFFER_ADDR)
FSR0L
upper (CODE_ADDR)
TBLPTRU
high (CODE_ADDR)
TBLPTRH
low (CODE_ADDR)
TBLPTRL
TBLRD*+
MOVF
MOVWF
DECFSZ
BRA
TABLAT, W
POSTINC0
COUNTER
READ_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
; number of bytes in erase block
; point to buffer
; Load TBLPTR with the base
; address of the memory block
READ_BLOCK
;
;
;
;
;
read into TABLAT, and inc
get data
store data
done?
repeat
MODIFY_WORD
; point to buffer
; update buffer word
ERASE_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
Required
MOVWF
Sequence
MOVLW
MOVWF
BSF
NOP
BSF
TBLRD*WRITE_BUFFER_BACK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
PROGRAM_LOOP
MOVLW
MOVWF
WRITE_WORD_TO_HREGS
MOVFW
MOVWF
TBLWT+*
upper (CODE_ADDR)
TBLPTRU
high (CODE_ADDR)
TBLPTRH
low (CODE_ADDR)
TBLPTRL
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
;
;
;
;
;
point to FLASH program memory
access FLASH program memory
enable write to memory
enable Row Erase operation
disable interrupts
; write 55H
; write AAH
; start erase (CPU stall)
INTCON, GIE
; re-enable interrupts
; dummy read decrement
8
COUNTER_HI
high (BUFFER_ADDR)
FSR0H
low (BUFFER_ADDR)
FSR0L
; number of write buffer groups of 8 bytes
8
COUNTER
; number of bytes in holding register
POSTINC0, W
TABLAT
;
;
;
;
;
DECFSZ COUNTER
BRA
WRITE_WORD_TO_HREGS
DS41159E-page 72
; load TBLPTR with the base
; address of the memory block
; point to buffer
get low byte of buffer data
present data to table latch
write data, perform a short write
to internal TBLWT holding register.
loop until buffers are full
© 2006 Microchip Technology Inc.
PIC18FXX8
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
WRITE_WORD_TO_HREGS
MOVFW
POSTINC0, W
MOVWF
TABLAT
TBLWT+*
DECFSZ COUNTER
BRA
WRITE_WORD_TO_HREGS
;
;
;
;
;
get low byte of buffer data
present data to table latch
write data, perform a short write
to internal TBLWT holding register.
loop until buffers are full
;
;
;
;
;
point to FLASH program memory
access FLASH program memory
enable write to memory
disable interrupts
write 55h
PROGRAM_MEMORY
Required
Sequence
6.5.2
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
DECFSZ
BRA
BCF
EECON1,
EECON1,
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
EEPGD
CFGS
WREN
GIE
; write 0AAh
; start program (CPU stall)
WR
INTCON, GIE
COUNTER_HI
PROGRAM_LOOP
EECON1, WREN
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and reprogrammed if needed.The WRERR bit is set when a write
operation is interrupted by a MCLR Reset or a WDT
Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
© 2006 Microchip Technology Inc.
; re-enable interrupts
; loop until done
; disable write to memory
6.5.4
PROTECTION AGAINST SPURIOUS
WRITES
To reduce the probability against spurious writes to
Flash program memory, the write initiate sequence
must also be followed. See Section 24.0 “Special
Features of the CPU” for more detail.
6.6
Flash Program Operation During
Code Protection
See Section 24.0 “Special Features of the CPU” for
details on code protection of Flash program memory.
DS41159E-page 73
PIC18FXX8
TABLE 6-2:
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Value on:
POR, BOR
Value on
all other
Resets
--00 0000
--00 0000
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR)
0000 0000
0000 0000
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR)
0000 0000
0000 0000
TABLAT
Program Memory Table Latch
0000 0000
0000 0000
INTCON
GIE/GIEH
0000 000x
0000 000u
EECON2
EEPROM Control Register 2 (not a physical register)
—
—
Name
Bit 7
Bit 6
Bit 5
TBLPTRU
—
—
bit 21
PEIE/
GIEL
TMR0IE
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Program Memory Table Pointer Upper Byte
(TBLPTR)
INTE
RBIE
TMR0IF
INTF
EEPGD
CFGS
—
FREE
WRERR
WREN
xx-0 x000
uu-0 u000
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP ECCP1IP(1) -1-1 1111
-1-1 1111
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF ECCP1IF(1) -0-0 0000
-0-0 0000
EECON1
PIE2
Legend:
Note 1:
—
CMIE
—
EEIE
BCLIE
LVDIE
WR
RBIF
RD
TMR3IE ECCP1IE
(1)
-0-0 0000
-0-0 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
DS41159E-page 74
© 2006 Microchip Technology Inc.
PIC18FXX8
7.0
8 x 8 HARDWARE MULTIPLIER
7.1
Introduction
7.2
Example 7-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX8 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored in the 16-bit product register
pair (PRODH:PRODL). The multiplier does not affect
any flags in the ALUSTA register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 7-1:
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
MOVF
MULWF
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
;
PRODH:PRODL
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
ARG1, W
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH
;
;
;
;
;
ARG1 * ARG2 ->
PRODH:PRODL
Test Sign Bit
PRODH = PRODH
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
PERFORMANCE COMPARISON
Routine
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 7-2:
Table 7-1 shows a performance comparison between
Enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
TABLE 7-1:
Operation
Program
Memory
(Words)
Cycles
(Max)
Without hardware multiply
13
Hardware multiply
1
Without hardware multiply
33
Hardware multiply
6
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Multiply Method
© 2006 Microchip Technology Inc.
Time
@ 40 MHz
@ 10 MHz
@ 4 MHz
69
6.9 μs
27.6 μs
69 μs
1
100 ns
400 ns
1 μs
91
9.1 μs
36.4 μs
91 μs
6
600 ns
2.4 μs
6 μs
21
242
24.2 μs
96.8 μs
242 μs
24
24
2.4 μs
9.6 μs
24 μs
52
254
25.4 μs
102.6 μs
254 μs
36
36
3.6 μs
14.4 μs
36 μs
DS41159E-page 75
PIC18FXX8
Example 7-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 7-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 7-1:
RES3:RES0
=
=
EXAMPLE 7-3:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L)
EQUATION 7-2:
RES3:RES0
=
ARG1H:ARG1L • ARG2H:ARG2L
=
(ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L)+
(-1 • ARG2H • ARG1H:ARG1L • 216) +
(-1 • ARG1H • ARG2H:ARG2L • 216)
EXAMPLE 7-4:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1
PRODH, W
RES2
WREG
RES3
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1
PRODH, W
RES2
WREG
RES3
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
16 x 16 SIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1
PRODH, W
RES2
WREG
RES3
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1
PRODH, W
RES2
WREG
RES3
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
ARG1L * ARG2H ->
PRODH:PRODL
Add cross
products
ARG1H * ARG2L ->
PRODH:PRODL
Add cross
products
Example 7-4 shows the sequence to do a 16 x 16
signed multiply. Equation 7-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the arguments, each argument pair’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
DS41159E-page 76
;
;
;
;
;
;
;
;
ARG1L * ARG2H ->
PRODH:PRODL
Add cross
products
;
;
;
;
;
;
;
;
;
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
;
;
;
;
;
;
;
;
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
;
;
;
;
;
;
;
;
;
ARG1H * ARG2L ->
PRODH:PRODL
Add cross
products
;
;
SIGN_ARG1
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
;
CONT_CODE
:
© 2006 Microchip Technology Inc.
PIC18FXX8
8.0
INTERRUPTS
The PIC18FXX8 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high priority
level or a low priority level. The high priority interrupt
vector is at 000008h and the low priority interrupt vector
is at 000018h. High priority interrupt events will
override any low priority interrupts that may be in
progress.
There are 13 registers that are used to control interrupt
operation. These registers are:
•
•
•
•
•
•
•
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2, PIR3
PIE1, PIE2, PIE3
IPR1, IPR2, IPR3
It is recommended that the Microchip header files,
supplied with MPLAB® IDE, be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
Each interrupt source has three bits to control its
operation. The functions of these bits are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON register). When interrupt priority is
enabled, there are two bits that enable interrupts
globally. Setting the GIEH bit (INTCON) enables all
interrupts. Setting the GIEL bit (INTCON register)
enables all interrupts that have the priority bit cleared.
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h,
depending on the priority level. Individual interrupts can
be disabled through their corresponding enable bits.
© 2006 Microchip Technology Inc.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PICmicro® mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. The PEIE bit (INTCON register)
enables/disables all peripheral interrupt sources. The
GIE bit (INTCON register) enables/disables all interrupt
sources. All interrupts branch to address 000008h in
Compatibility mode.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
Note:
Do not use the MOVFF instruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
DS41159E-page 77
PIC18FXX8
FIGURE 8-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Wake-up if in Sleep mode
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Interrupt to CPU
Vector to Location
0008h
GIE/GIEH
TMR1IF
TMR1IE
TMR1IP
IPEN
IPEN
GIEL/PEIE
XXXXIF
XXXXIE
XXXXIP
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR1IF
TMR1IE
TMR1IP
XXXXIF
XXXXIE
XXXXIP
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Interrupt to CPU
Vector to Location
0018h
PEIE/GIEL
GIE/GIEH
INT1IF
Additional Peripheral Interrupts INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
DS41159E-page 78
© 2006 Microchip Technology Inc.
PIC18FXX8
8.1
INTCON Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows software polling.
The INTCON registers are readable and writable registers which contain various enable, priority and flag bits.
Because of the number of interrupts to be controlled,
PIC18FXX8 devices have three INTCON registers.
They are detailed in Register 8-1 through Register 8-3.
REGISTER 8-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
GIE/GIEH PEIE/GIEL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
bit 7
bit 7
bit 0
GIE/GIEH: Global Interrupt Enable bit
When IPEN (RCON) = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN (RCON) = 1:
1 = Enables all high priority interrupts
0 = Disables all priority interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN (RCON) = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN (RCON) = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software by reading PORTB)
0 = The INT0 external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note:
A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 79
PIC18FXX8
REGISTER 8-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
RBPU
bit 7
R/W-1
R/W-1
INTEDG0 INTEDG1
U-0
U-0
R/W-1
U-0
—
—
TMR0IP
—
bit 7
RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5
INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4-3
Unimplemented: Read as ‘0’
bit 2
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
Unimplemented: Read as ‘0’
bit 0
RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
R/W-1
RBIP
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Note:
DS41159E-page 80
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows software polling.
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 8-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
R/W-1
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
bit 7
bit 0
bit 7
INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
Unimplemented: Read as ‘0’
bit 4
INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2
Unimplemented: Read as ‘0’
bit 1
INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Note:
© 2006 Microchip Technology Inc.
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows software polling.
DS41159E-page 81
PIC18FXX8
8.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON
register).
The Peripheral Interrupt Request (PIR) registers
contain the individual flag bits for the peripheral
interrupts (Register 8-4 through Register 8-6). Due to
the number of peripheral interrupt sources, there are
three Peripheral Interrupt Request (Flag) registers
(PIR1, PIR2, PIR3).
REGISTER 8-4:
2: User software should ensure the appropriate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
PSPIF
(1)
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The USART receive buffer is empty
bit 4
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The USART transmit buffer is full
bit 3
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
DS41159E-page 82
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 8-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CMIF(1)
—
EEIF
BCLIF
LVDIF
TMR3IF
ECCP1IF(1)
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
CMIF: Comparator Interrupt Flag bit(1)
1 = Comparator input has changed
0 = Comparator input has not changed
bit 5
Unimplemented: Read as ‘0’
bit 4
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = Write operation is complete (must be cleared in software)
0 = Write operation is not complete
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 2
LVDIF: Low-Voltage Detect Interrupt Flag bit
1 = A low-voltage condition occurred (must be cleared in software)
0 = The device voltage is above the Low-Voltage Detect trip point
bit 1
TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 0
ECCP1IF: ECCP1 Interrupt Flag bit(1)
Capture mode:
1 = A TMR1 (TMR3) register capture occurred (must be cleared in software)
0 = No TMR1 (TMR3) register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 83
PIC18FXX8
REGISTER 8-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRXIF
WAKIF
ERRIF
TXB2IF
TXB1IF
TXB0IF
RXB1IF
RXB0IF
bit 7
bit 0
bit 7
IRXIF: Invalid Message Received Interrupt Flag bit
1 = An invalid message has occurred on the CAN bus
0 = An invalid message has not occurred on the CAN bus
bit 6
WAKIF: Bus Activity Wake-up Interrupt Flag bit
1 = Activity on the CAN bus has occurred
0 = Activity on the CAN bus has not occurred
bit 5
ERRIF: CAN bus Error Interrupt Flag bit
1 = An error has occurred in the CAN module (multiple sources)
0 = An error has not occurred in the CAN module
bit 4
TXB2IF: Transmit Buffer 2 Interrupt Flag bit
1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 2 has not completed transmission of a message
bit 3
TXB1IF: Transmit Buffer 1 Interrupt Flag bit
1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 1 has not completed transmission of a message
bit 2
TXB0IF: Transmit Buffer 0 Interrupt Flag bit
1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 0 has not completed transmission of a message
bit 1
RXB1IF: Receive Buffer 1 Interrupt Flag bit
1 = Receive Buffer 1 has received a new message
0 = Receive Buffer 1 has not received a new message
bit 0
RXB0IF: Receive Buffer 0 Interrupt Flag bit
1 = Receive Buffer 0 has received a new message
0 = Receive Buffer 0 has not received a new message
Legend:
DS41159E-page 84
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
8.3
PIE Registers
The Peripheral Interrupt Enable (PIE) registers contain
the individual enable bits for the peripheral interrupts
(Register 8-7 through Register 8-9). Due to the number
of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3).
When IPEN is clear, the PEIE bit must be set to enable
any of these peripheral interrupts.
REGISTER 8-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
(1)
PSPIE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 85
PIC18FXX8
REGISTER 8-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CMIE(1)
—
EEIE
BCLIE
LVDIE
TMR3IE
ECCP1IE(1)
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
CMIE: Comparator Interrupt Enable bit(1)
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
bit 5
Unimplemented: Read as ‘0’
bit 4
EEIE: EEPROM Write Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3
BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enables the TMR3 overflow interrupt
0 = Disables the TMR3 overflow interrupt
bit 0
ECCP1IE: ECCP1 Interrupt Enable bit(1)
1 = Enables the ECCP1 interrupt
0 = Disables the ECCP1 interrupt
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
DS41159E-page 86
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 8-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IRXIE
WAKIE
ERRIE
TXB2IE
TXB1IE
TXB0IE
RXB1IE
RXB0IE
bit 7
bit 0
bit 7
IRXIE: Invalid CAN Message Received Interrupt Enable bit
1 = Enables the invalid CAN message received interrupt
0 = Disables the invalid CAN message received interrupt
bit 6
WAKIE: Bus Activity Wake-up Interrupt Enable bit
1 = Enables the bus activity wake-up interrupt
0 = Disables the bus activity wake-up interrupt
bit 5
ERRIE: CAN bus Error Interrupt Enable bit
1 = Enables the CAN bus error interrupt
0 = Disables the CAN bus error interrupt
bit 4
TXB2IE: Transmit Buffer 2 Interrupt Enable bit
1 = Enables the Transmit Buffer 2 interrupt
0 = Disables the Transmit Buffer 2 interrupt
bit 3
TXB1IE: Transmit Buffer 1 Interrupt Enable bit
1 = Enables the Transmit Buffer 1 interrupt
0 = Disables the Transmit Buffer 1 interrupt
bit 2
TXB0IE: Transmit Buffer 0 Interrupt Enable bit
1 = Enables the Transmit Buffer 0 interrupt
0 = Disables the Transmit Buffer 0 interrupt
bit 1
RXB1IE: Receive Buffer 1 Interrupt Enable bit
1 = Enables the Receive Buffer 1 interrupt
0 = Disables the Receive Buffer 1 interrupt
bit 0
RXB0IE: Receive Buffer 0 Interrupt Enable bit
1 = Enables the Receive Buffer 0 interrupt
0 = Disables the Receive Buffer 0 interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 87
PIC18FXX8
8.4
IPR Registers
The Interrupt Priority (IPR) registers contain the individual priority bits for the peripheral interrupts. Due to the
number of peripheral interrupt sources, there are three
Peripheral Interrupt Priority registers (IPR1, IPR2 and
IPR3). The operation of the priority bits requires that
the Interrupt Priority Enable bit (IPEN) be set.
REGISTER 8-10:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)
1 = High priority
0 = Low priority
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RCIP: USART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TXIP: USART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
DS41159E-page 88
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 8-11:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
U-0
R/W-1
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
CMIP(1)
—
EEIP
BCLIP
LVDIP
TMR3IP
ECCP1IP(1)
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
CMIP: Comparator Interrupt Priority bit(1)
1 = High priority
0 = Low priority
bit 5
Unimplemented: Read as ‘0’
bit 4
EEIP: EEPROM Write Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
LVDIP: Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
ECCP1IP: ECCP1 Interrupt Priority bit(1)
1 = High priority
0 = Low priority
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 89
PIC18FXX8
REGISTER 8-12:
IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IRXIP
WAKIP
ERRIP
TXB2IP
TXB1IP
TXB0IP
RXB1IP
RXB0IP
bit 7
bit 0
bit 7
IRXIP: Invalid Message Received Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
WAKIP: Bus Activity Wake-up Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
ERRIP: CAN bus Error Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TXB2IP: Transmit Buffer 2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
TXB1IP: Transmit Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
TXB0IP: Transmit Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
RXB1IP: Receive Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
RXB0IP: Receive Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
DS41159E-page 90
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
8.5
RCON Register
The Reset Control (RCON) register contains the IPEN
bit which is used to enable prioritized interrupts. The
functions of the other bits in this register are discussed
in more detail in Section 4.14 “RCON Register”.
REGISTER 8-13:
RCON: RESET CONTROL REGISTER
R/W-0
IPEN
bit 7
U-0
—
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5
Unimplemented: Read as ‘0’
bit 4
RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-3.
bit 3
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-3.
bit 2
PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-3.
bit 1
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-3.
bit 0
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-3.
R/W-0
BOR
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 91
PIC18FXX8
8.6
INT Interrupts
8.8
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/CANTX/INT2 pins are edge triggered: either rising
if the corresponding INTEDGx bit is set in the
INTCON2 register, or falling if the INTEDGx bit is clear.
When a valid edge appears on the RBx/INTx pin, the
corresponding flag bit INTxIF is set. This interrupt can
be disabled by clearing the corresponding enable bit
INTxIE. Flag bit INTxIF must be cleared in software in
the Interrupt Service Routine before re-enabling the
interrupt. All external interrupts (INT0, INT1 and INT2)
can wake-up the processor from Sleep if bit INTxIE was
set prior to going into Sleep. If the Global Interrupt
Enable bit, GIE, is set, the processor will branch to the
interrupt vector following wake-up.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits INT1IP
(INTCON3) and INT2IP (INTCON3). There is
no priority bit associated with INT0; it is always a high
priority interrupt source.
8.7
PORTB Interrupt-on-Change
An input change on PORTB sets flag bit RBIF
(INTCON register). The interrupt can be enabled/
disabled by setting/clearing enable bit RBIE (INTCON
register). Interrupt priority for PORTB interrupt-onchange is determined by the value contained in the
interrupt priority bit RBIP (INTCON2 register).
8.9
Context Saving During Interrupts
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, Status and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 4.3 “Fast
Register Stack”), the user may need to save the
WREG, Status and BSR registers in software. Depending on the user’s application, other registers may also
need to be saved. Example 8-1 saves and restores the
WREG, Status and BSR registers during an Interrupt
Service Routine.
TMR0 Interrupt
In 8-bit mode (which is the default), an overflow (FFh →
00h) in the TMR0 register will set flag bit TMR0IF. In
16-bit mode, an overflow (FFFFh → 0000h) in the
TMR0H:TMR0L registers will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit TMR0IE (INTCON register). Interrupt priority
for Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2 register). See
Section 11.0 “Timer0 Module” for further details.
EXAMPLE 8-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
W_TEMP
MOVFF
STATUS, STATUS_TEMP
MOVFF
BSR, BSR_TEMP
;
; USER ISR CODE
;
MOVFF
BSR_TEMP, BSR
MOVF
W_TEMP, W
MOVFF
STATUS_TEMP, STATUS
DS41159E-page 92
; W_TEMP is in Low Access bank
; STATUS_TEMP located anywhere
; BSR located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
© 2006 Microchip Technology Inc.
PIC18FXX8
9.0
I/O PORTS
Depending on the device selected, there are up to five
general purpose I/O ports available on PIC18FXX8
devices. Some pins of the I/O ports are multiplexed
with an alternate function from the peripheral features
on the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
Each port has three registers for its operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The data latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are
driving.
9.1
PORTA, TRISA and LATA
Registers
PORTA is a 7-bit wide, bidirectional port. The corresponding Data Direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin). On
a Power-on Reset, these pins are configured as inputs
and read as ‘0’.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
Read-modify-write operations on the LATA register
read and write the latched output value for PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA4/
T0CKI pin is a Schmitt Trigger input and an open-drain
output. All other RA port pins have TTL input levels and
full CMOS output drivers.
The other PORTA pins are multiplexed with analog
inputs and the analog VREF+ and VREF- inputs. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register 1). On a Power-on Reset, these pins are
configured as analog inputs and read as ‘0’.
Note:
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set, when using them as analog inputs.
EXAMPLE 9-1:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
© 2006 Microchip Technology Inc.
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA6 and RA4 are configured as
digital inputs.
PORTA ;
;
LATA
;
;
07h
;
ADCON1 ;
0CFh
;
;
TRISA ;
;
INITIALIZING PORTA
Initialize PORTA by
clearing output data latches
Alternate method to clear
output data latches
Configure A/D
for digital inputs
Value used to initialize
data direction
Set RA3:RA0 as inputs,
RA5:RA4 as outputs
DS41159E-page 93
PIC18FXX8
FIGURE 9-1:
RA3:RA0 AND RA5 PINS
BLOCK DIAGRAM
FIGURE 9-2:
RD LATA
Data Bus
WR LATA or
WR PORTA
RA4/T0CKI PIN BLOCK
DIAGRAM
RD LATA
Q
D
Data Bus
VDD
CK
Q
WR LATA or
WR PORTA
P
Data Latch
Q
D
CK
Q
N
I/O pin(1)
Data Latch
Q
D
WR TRISA
Analog
Input Mode
CK
I/O pin(1)
N
Q
WR TRISA
VSS
TRIS Latch
D
Q
CK
Q
VSS
TRIS Latch
RD TRISA
Q
RD TRISA
TTL
Input
Buffer
D
TTL
Input
Buffer
Schmitt
Trigger
Input
Buffer
Q
EN
D
EN
RD PORTA
RD PORTA
TMR0 Clock Input
SS Input (RA5 only)
Note 1: I/O pin has diode protection to VSS only.
To A/D Converter and LVD Modules
Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 9-3:
OSC2/CLKO/RA6 PIN BLOCK DIAGRAM
(FOSC = 101, 111)
From OSC1
CLKO (FOSC/4)
1
Oscillator
Circuit
Data Latch
Data Bus
WR PORTA
D
CK
Q
0
VDD
Q
OSC2/CLKO
RA6 pin(2)
P
TRIS Latch
D
Q
N
WR TRISA
CK
Q
(FOSC = 100,
101, 110, 111)
VSS
RD TRISA
Q
D
Data Latch
Schmitt
Trigger
Input Buffer
EN
RD PORTA
(FOSC = 110, 100)
Note
1: CLKO is 1/4 of FOSC.
2: I/O pin has diode protection to VDD and VSS.
DS41159E-page 94
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 9-1:
PORTA FUNCTIONS
Name
RA0/AN0/CVREF
Bit#
Buffer
bit 0
TTL
Function
Input/output, analog input or analog comparator voltage reference
output.
RA1/AN1
bit 1
TTL
Input/output or analog input.
RA2/AN2/VREF-
bit 2
TTL
Input/output, analog input or VREF-.
TTL
Input/output, analog input or VREF+.
RA3/AN3/VREF+
bit 3
RA4/T0CKI
bit 4
RA5/AN4/SS/LVDIN
bit 5
TTL
Input/output, analog input, slave select input for synchronous serial port
or Low-Voltage Detect input.
OSC2/CLKO/RA6
bit 6
TTL
Oscillator clock output or input/output.
ST/OD Input/output, external clock input for Timer0, output is open-drain type.
Legend: TTL = TTL input, ST = Schmitt Trigger input, OD = Open-Drain
TABLE 9-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
PORTA
—
RA6
RA5
RA4
RA3
RA2
RA1
RA0
-00x 0000 -uuu uuuu
LATA
—
Latch A Data Output Register
—
PORTA Data Direction Register
Name
TRISA
ADCON1
Legend:
ADFM ADCS2
—
—
PCFG3
-xxx xxxx -uuu uuuu
-111 1111 -111 1111
PCFG2
PCFG1
PCFG0 00-- 0000 uu-- uuuu
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
© 2006 Microchip Technology Inc.
DS41159E-page 95
PIC18FXX8
9.2
PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATB register,
read and write the latched output value for PORTB.
EXAMPLE 9-2:
CLRF
PORTB
CLRF
LATB
MOVLW
0CFh
MOVWF
TRISB
INITIALIZING PORTB
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RB3:RB0 as inputs
RB5:RB4 as outputs
RB7:RB6 as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2 register).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Note 1: While in Low-Voltage ICSP mode, the
RB5 pin can no longer be used as a
general purpose I/O pin and should not
be held low during normal operation to
protect against inadvertent ICSP mode
entry.
2: When using Low-Voltage ICSP Programming (LVP), the pull-up on RB5 becomes
disabled. If TRISB bit 5 is cleared,
thereby setting RB5 as an output, LATB
bit 5 must also be cleared for proper
operation.
Four of the PORTB pins (RB7:RB4) have an interrupton-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are ORed together to generate the RB Port Change
Interrupt with Flag bit RBIF (INTCON register).
DS41159E-page 96
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 9-4:
RB7:RB4 PINS BLOCK
DIAGRAM
FIGURE 9-5:
RB1:RB0 PINS BLOCK
DIAGRAM
VDD
VDD
RBPU(2)
Data Bus
WR LATB
or
WR PORTB
Weak
P Pull-up
Data Bus
Q
I/O pin(1)
CK
TTL
Input
Buffer
CK
D
Q
I/O pin(1)
WR Port
TRIS Latch
D
Q
WR TRISB
Weak
P Pull-up
Data Latch
Data Latch
D
RBPU(2)
CK
TRIS Latch
D
Q
ST
Buffer
WR TRIS
TTL
Input
Buffer
CK
RD TRISB
RD LATB
RD TRIS
Latch
Q
D
Q
D
RD PORTB
EN
Q1
EN
Set RBIF
RD Port
Q
From other
RB7:RB4 pins
D
EN
Q3
RBx/INTx
Schmitt Trigger
Buffer
RBx/INTx
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2 register).
© 2006 Microchip Technology Inc.
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2 register).
DS41159E-page 97
PIC18FXX8
FIGURE 9-6:
RB2/CANTX/INT2 PIN BLOCK DIAGRAM
OPMODE2:OPMODE0 = 000
ENDRHI
CANTX
0
RD LATB
VDD
Data Latch
Data Bus
D
Q
WR PORTB or
WR LATB
CK
Q
1
P
TRIS Latch
Q
D
RB2/CANTX/
INT2 pin(1)
N
WR TRISB
CK
Q
VSS
Schmitt
Trigger
RD TRISB
Q
D
EN
RD PORTB
Note 1: I/O pin has diode protection to VDD and VSS.
FIGURE 9-7:
RB3/CANRX PIN BLOCK DIAGRAM
CANCON
VDD
RBPU(2)
P Weak
Pull-up
Data Latch
Data Bus
WR LATB or PORTB
D
Q
I/O pin(1)
CK
TRIS Latch
D
Q
WR TRISB
CK
TTL
Input
Buffer
RD TRISB
RD LATB
Q
D
EN
RD PORTB
RB3 or CANRX
Schmitt Trigger
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2).
.
DS41159E-page 98
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 9-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
RB0/INT0
bit 0
TTL/ST(1) Input/output pin or external interrupt 0 input.
Internal software programmable weak pull-up.
RB1/INT1
bit 1
TTL/ST(1) Input/output pin or external interrupt 1 input.
Internal software programmable weak pull-up.
RB2/CANTX/
INT2
bit 2
TTL/ST(1) Input/output pin, CAN bus transmit pin or external interrupt 2 input.
Internal software programmable weak pull-up.
RB3/CANRX
bit 3
TTL
Input/output pin or CAN bus receive pin.
Internal software programmable weak pull-up.
RB4
bit 4
TTL
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB5/PGM
bit 5
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Low-voltage serial programming enable.
RB6/PGC
bit 6
TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming clock.
RB7/PGD
bit 7
TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 9-4:
Name
PORTB
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
LATB
LATB Data Output Register
xxxx xxxx
uuuu uuuu
TRISB
PORTB Data Direction Register
1111 1111
1111 1111
INTCON
GIE/GIEH PEIE/GIEL
INTCON2
RBPU
INTCON3
INT2IP
Legend:
TMR0IE
INTEDG0 INTEDG1
INT1IP
—
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
—
—
TMR0IP
—
RBIP
111- -1-1
111- -1-1
INT2IE
INT1IE
—
INT2IF
INT1IF
11-0 0-00
11-1 0-00
x = unknown, u = unchanged. Shaded cells are not used by PORTB.
© 2006 Microchip Technology Inc.
DS41159E-page 99
PIC18FXX8
9.3
PORTC, TRISC and LATC
Registers
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The pin override value is not loaded into the TRIS
register. This allows read-modify-write of the TRIS
register, without concern due to peripheral overrides.
EXAMPLE 9-3:
Read-modify-write operations on the LATC register,
read and write the latched output value for PORTC.
PORTC is multiplexed with several peripheral functions
(Table 9-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
FIGURE 9-8:
CLRF
PORTC
CLRF
LATC
MOVLW
0CFh
MOVWF
TRISC
INITIALIZING PORTC
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTC by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RC3:RC0 as inputs
RC5:RC4 as outputs
RC7:RC6 as inputs
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Peripheral Out Select
Peripheral Data Out
VDD
0
P
RD LATC
Data Bus
WR LATC
or
WR PORTC
1
D
Q
CK
Q
Data Latch
D
WR TRISC
I/O pin(1)
CK
Q
Q
TRIS OVERRIDE
N
VSS
TRIS
Override
TRIS Latch
RD TRISC
Schmitt
Trigger
Peripheral Enable
Q
Peripheral Data In
Override
RC0
Yes
Timer1 Oscillator
for Timer1/Timer3
RC1
Yes
Timer1 Oscillator
for Timer1/Timer3
RC2
No
—
RC3
Yes
SPI™/I2C™
Master Clock
RC4
Yes
I2C Data Out
RC5
Yes
SPI Data Out
RC6
Yes
USART Async
Xmit, Sync Clock
RC7
Yes
USART Sync Data
Out
D
EN
RD PORTC
Pin
Peripheral
Note 1: I/O pins have diode protection to VDD and VSS.
DS41159E-page 100
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 9-5:
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0/T1OSO/T1CKI
bit 0
ST
Input/output port pin, Timer1 oscillator output or Timer1/Timer3 clock
input.
RC1/T1OSI
bit 1
ST
Input/output port pin or Timer1 oscillator input.
RC2/CCP1
bit 2
ST
Input/output port pin or Capture 1 input/Compare 1 output/
PWM1 output.
RC3/SCK/SCL
bit 3
ST
Input/output port pin or synchronous serial clock for SPI™/I2C™.
RC4/SDI/SDA
bit 4
ST
Input/output port pin or SPI data in (SPI mode) or data I/O (I2C mode).
RC5/SDO
bit 5
ST
Input/output port pin or synchronous serial port data output.
RC6/TX/CK
bit 6
ST
Input/output port pin, addressable USART asynchronous transmit or
addressable USART synchronous clock.
RC7/RX/DT
bit 7
ST
Input/output port pin, addressable USART asynchronous receive or
addressable USART synchronous data.
Legend: ST = Schmitt Trigger input
TABLE 9-6:
Name
PORTC
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
LATC
LATC Data Output Register
xxxx xxxx
uuuu uuuu
TRISC
PORTC Data Direction Register
1111 1111
1111 1111
Legend: x = unknown, u = unchanged
© 2006 Microchip Technology Inc.
DS41159E-page 101
PIC18FXX8
9.4
Note:
PORTD, TRISD and LATD
Registers
This port is only available on the
PIC18F448 and PIC18F458.
PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register for the port is TRISD.
Setting a TRISD bit (= 1) will make the corresponding
PORTD pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISD
bit (= 0) will make the corresponding PORTD pin an
output (i.e., put the contents of the output latch on the
selected pin).
Read-modify-write operations on the LATD register
read and write the latched output value for PORTD.
PORTD uses Schmitt Trigger input buffers. Each pin is
individually configurable as an input or output.
FIGURE 9-9:
PORTD can be configured as an 8-bit wide, microprocessor port (Parallel Slave Port or PSP) by setting
the control bit PSPMODE (TRISE). In this mode,
the input buffers are TTL. See Section 10.0 “Parallel
Slave Port” for additional information.
PORTD is also multiplexed with the analog comparator
module and the ECCP module.
EXAMPLE 9-4:
CLRF
PORTD
CLRF
LATD
MOVLW
MOVWF
MOVLW
07h
CMCON
0CFh
MOVWF
TRISD
INITIALIZING PORTD
;
;
;
;
;
;
;
Initialize PORTD by
clearing output
data latches
Alternate method
to clear output
data latches
comparator off
;
;
;
;
;
;
Value used to
initialize data
direction
Set RD3:RD0 as inputs
RD5:RD4 as outputs
RD7:RD6 as inputs
PORTD BLOCK DIAGRAM IN I/O PORT MODE
PORT/PSP Select
PSP Data Out
VDD
P
RD LATD
Data Bus
WR LATD
or
PORTD
D
CK
Q
N
RD0/PSP0/
C1IN+ pin(1)
Data Latch
D
WR TRISD
Q
CK
Q
Vss
Q
TRIS Latch
RD TRISD
Schmitt
Trigger
PSP Read
Q
D
EN
RD PORTD
PSP Write
C1IN+
Note 1: I/O pins have diode protection to VDD and VSS.
DS41159E-page 102
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 9-7:
PORTD FUNCTIONS
Name
Bit#
Buffer Type
Function
RD0/PSP0/C1IN+
bit 0
ST/TTL(1)
Input/output port pin, Parallel Slave Port bit 0 or C1IN+ comparator
input.
RD1/PSP1/C1IN-
bit 1
ST/TTL(1)
Input/output port pin, Parallel Slave Port bit 1 or C1IN- comparator
input.
RD2/PSP2/C2IN+
bit 2
ST/TTL(1)
Input/output port pin, Parallel Slave Port bit 2 or C2IN+ comparator
input.
RD3/PSP3/C2IN-
bit 3
ST/TTL(1)
Input/output port pin, Parallel Slave Port bit 3 or C2IN- comparator
input.
RD4/PSP4/ECCP1/P1A bit 4
ST/TTL(1)
Input/output port pin, Parallel Slave Port bit 4 or ECCP1/P1A pin.
RD5/PSP5/P1B
bit 5
ST/TTL(1)
Input/output port pin, Parallel Slave Port bit 5 or P1B pin.
RD6/PSP6/P1C
bit 6
ST/TTL(1)
Input/output port pin, Parallel Slave Port bit 6 or P1C pin.
RD7/PSP7/P1D
bit 7
ST/TTL(1)
Input/output port pin, Parallel Slave Port bit 7 or P1D pin.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 9-8:
Name
PORTD
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
0000 -111
0000 -111
LATD
LATD Data Output Register
TRISD
PORTD Data Direction Register
TRISE
IBF
OBF
IBOV
PSPMODE
—
TRISE2 TRISE1 TRISE0
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
© 2006 Microchip Technology Inc.
DS41159E-page 103
PIC18FXX8
9.5
PORTE, TRISE and LATE
Registers
Note:
When the Parallel Slave Port is active, the PORTE pins
function as its control inputs. For additional details,
refer to Section 10.0 “Parallel Slave Port”.
This port is only available on the
PIC18F448 and PIC18F458.
PORTE pins are also multiplexed with inputs for the A/D
converter and outputs for the analog comparators. When
selected as an analog input, these pins will read as ‘0’s.
Direction bits TRISE control the direction of the RE
pins, even when they are being used as analog inputs.
The user must make sure to keep the pins configured as
inputs when using them as analog inputs.
PORTE is a 3-bit wide, bidirectional port. PORTE has
three pins (RE0/AN5/RD, RE1/AN6/WR/C1OUT and
RE2/AN7/CS/C2OUT) which are individually configurable as inputs or outputs. These pins have Schmitt
Trigger input buffers.
Read-modify-write operations on the LATE register,
read and write the latched output value for PORTE.
EXAMPLE 9-5:
The corresponding Data Direction register for the port
is TRISE. Setting a TRISE bit (= 1) will make the
corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode).
Clearing a TRISE bit (= 0) will make the corresponding
PORTE pin an output (i.e., put the contents of the
output latch on the selected pin).
The TRISE register also controls the operation of the
Parallel Slave Port through the control bits in the upper
half of the register. These are shown in Register 9-1.
FIGURE 9-10:
CLRF
PORTE
CLRF
LATE
MOVLW
03h
MOVWF
TRISE
INITIALIZING PORTE
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTE by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RE1:RE0 as inputs
RE2 as an output
(RE4=0 - PSPMODE Off)
PORTE BLOCK DIAGRAM
Peripheral Out Select
Peripheral Data Out
VDD
0
P
RD LATE
Data Bus
WR LATE
or
WR PORTE
WR TRISE
1
D
Q
CK
Q
I/O pin(1)
Data Latch
D
Q
CK
Q
N
VSS
TRIS
Override
TRIS Latch
RD TRISE
Schmitt
Trigger
Peripheral Enable
Q
D
TRIS OVERRIDE
Pin
Override Peripheral
RE0
Yes
PSP
RD PORTE
RE1
Yes
PSP
Peripheral Data In
RE2
Yes
PSP
EN
Note 1: I/O pins have diode protection to VDD and VSS.
DS41159E-page 104
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 9-1:
TRISE REGISTER
R-0
R-0
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
IBF
OBF
IBOV
PSPMODE
—
TRISE2
TRISE1
TRISE0
bit 7
bit 0
bit 7
IBF: Input Buffer Full Status bit
1 = A word has been received and waiting to be read by the CPU
0 = No word has been received
bit 6
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read
(must be cleared in software)
0 = No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel Slave Port mode
0 = General Purpose I/O mode
bit 3
Unimplemented: Read as ‘0’
bit 2
TRISE2: RE2 Direction Control bit
1 = Input
0 = Output
bit 1
TRISE1: RE1 Direction Control bit
1 = Input
0 = Output
bit 0
TRISE0: RE0 Direction Control bit
1 = Input
0 = Output
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 105
PIC18FXX8
TABLE 9-9:
PORTE FUNCTIONS
Name
Bit#
Buffer Type
Function
RE0/AN5/RD
bit 0
ST/TTL(1)
Input/output port pin, analog input or read control input in Parallel
Slave Port mode.
RE1/AN6/WR/C1OUT
bit 1
ST/TTL(1)
Input/output port pin, analog input, write control input in Parallel Slave
Port mode or Comparator 1 output.
RE2/AN7/CS/C2OUT
bit 2
ST/TTL(1)
Input/output port pin, analog input, chip select control input in Parallel
Slave Port mode or Comparator 2 output.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 9-10:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
TRISE
IBF
OBF
IBOV
PSPMODE
—
TRISE2
TRISE1
TRISE0
0000 -111
0000 -111
PORTE
—
—
—
—
—
Read PORTE pin/
Write PORTE Data Latch
---- -xxx
---- -uuu
LATE
—
—
—
—
—
Read PORTE Data Latch/
Write PORTE Data Latch
---- -xxx
---- -uuu
—
—
00-- 0000
00-- 0000
Name
ADCON1 ADFM ADCS2
PCFG3 PCFG2
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
DS41159E-page 106
© 2006 Microchip Technology Inc.
PIC18FXX8
10.0
PARALLEL SLAVE PORT
Note:
FIGURE 10-1:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
The Parallel Slave Port is only available on
PIC18F4X8 devices.
One bit of PORTD
In addition to its function as a general I/O port, PORTD
can also operate as an 8-bit wide Parallel Slave Port
(PSP) or microprocessor port. PSP operation is
controlled by the 4 upper bits of the TRISE register
(Register 9-1). Setting control bit PSPMODE
(TRISE) enables PSP operation. In Slave mode,
the port is asynchronously readable and writable by the
external world.
Data Bus
D
WR LATD
or
WR PORTD
Q
RDx pin
CK
Q
RD PORTD
The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
the control bit PSPMODE enables the PORTE I/O pins
to become control inputs for the microprocessor port.
When set, port pin RE0 is the RD input, RE1 is the WR
input and RE2 is the CS (chip select) input. For this
functionality, the corresponding data direction bits of
the TRISE register (TRISE) must be configured
as inputs (set).
TTL
Data Latch
D
ENEN
RD LATD
Set Interrupt Flag
PSPIF (PIR1)
PORTE pins
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The timing for the control signals in Write and Read
modes is shown in Figure 10-2 and Figure 10-3,
respectively.
Read
TTL
RD
Chip Select
TTL
CS
Write
TTL
Note:
FIGURE 10-2:
WR
I/O pins have diode protection to VDD and VSS.
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
© 2006 Microchip Technology Inc.
DS41159E-page 107
PIC18FXX8
FIGURE 10-3:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
TABLE 10-1:
Name
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
PORTD
Port Data Latch when written; Port pins when read
xxxx xxxx uuuu uuuu
LATD
LATD Data Output bits
xxxx xxxx uuuu uuuu
TRISD
PORTD Data Direction bits
1111 1111 1111 1111
PORTE
LATE
TRISE
INTCON
PIR1
—
—
—
—
—
RE2
RE1
RE0
LATE Data Output bits
IBF
OBF
---- -xxx ---- -000
---- -xxx ---- -uuu
IBOV
GIE/GIEH PEIE/GIEL TMR0IE
PSPMODE
—
PORTE Data Direction bits
0000 -111 0000 -111
INT0IE
RBIE
TMR0IF
0000 000x 0000 000u
INT0IF
RBIF
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
DS41159E-page 108
© 2006 Microchip Technology Inc.
PIC18FXX8
11.0
TIMER0 MODULE
Register 11-1 shows the Timer0 Control register
(T0CON).
The Timer0 module has the following features:
• Software selectable as an 8-bit or
16-bit timer/counter
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt-on-overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
• Edge select for external clock
REGISTER 11-1:
Figure 11-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
The T0CON register is a readable and writable register
that controls all the aspects of Timer0, including the
prescale selection.
Note:
Timer0 is enabled on POR.
T0CON: TIMER0 CONTROL REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
bit 7
bit 0
bit 7
TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6
T08BIT: Timer0 8-bit/16-bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0
T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 Prescale value
110 = 1:128 Prescale value
101 = 1:64 Prescale value
100 = 1:32 Prescale value
011 = 1:16 Prescale value
010 = 1:8 Prescale value
001 = 1:4 Prescale value
000 = 1:2 Prescale value
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 109
PIC18FXX8
FIGURE 11-1:
TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus
1
8
RA4/T0CKI
pin(2)
T0SE
1
FOSC/4
Sync with
Internal
Clocks
0
Programmable
Prescaler
TMR0L
0
(2 TCY Delay)
3
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
T0PS2, T0PS1, T0PS0
T0CS
(1)
Note 1: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
2: I/O pins have diode protection to VDD and VSS.
FIGURE 11-2:
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
T0CKI pin(2)
1
1
T0SE
FOSC/4
0
Programmable
Prescaler
0
Sync with
Internal
Clocks
TMR0L
TMR0
High Byte
8
(2 TCY Delay)
3
Read TMR0L
T0PS2, T0PS1, T0PS0
T0CS(1)
Set Interrupt
Flag bit TMR0IF
on Overflow
Write TMR0L
PSA
8
8
TMR0H
8
Data Bus
Note 1: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
2: I/O pins have diode protection to VDD and VSS.
DS41159E-page 110
© 2006 Microchip Technology Inc.
PIC18FXX8
11.1
11.2.1
Timer0 Operation
Timer0 can operate as a timer or as a counter.
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution).
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0L
register is written, the increment is inhibited for the
following two instruction cycles. The user can work
around this by writing an adjusted value to the TMR0L
register.
11.3
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
11.4
Prescaler
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 11-1). The high byte
of the Timer0 timer/counter is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This
provides the ability to read all 16 bits of Timer0 without
having to verify that the read of the high and low byte
were valid, due to a rollover between successive reads
of the high and low byte.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
A write to the high byte of Timer0 must also take place
through the TMR0H Buffer register. Timer0 high byte is
updated with the contents of the buffered value of
TMR0H when a write occurs to TMR0L. This allows all
16 bits of Timer0 to be updated at once.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, x.... etc.) will clear the prescaler
count.
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
TABLE 11-1:
Name
16-Bit Mode Timer Reads
and Writes
Timer0 can be set in 16-bit mode by clearing the
T08BIT in T0CON. Registers TMR0H and TMR0L are
used to access the 16-bit timer value.
An 8-bit counter is available as a prescaler for the
Timer0 module. The prescaler is not readable or
writable.
Note:
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode or
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF bit. The interrupt can be masked by clearing
the TMR0IE bit. The TMR0IF bit must be cleared in
software by the Timer0 module Interrupt Service
Routine before re-enabling this interrupt. The TMR0
interrupt cannot awaken the processor from Sleep
since the timer is shut-off during Sleep.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment either on every
rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge
Select bit (T0SE). Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input are
discussed below.
11.2
SWITCHING PRESCALER
ASSIGNMENT
REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
uuuu uuuu
TMR0L
Timer0 Module Low Byte Register
xxxx xxxx
TMR0H
Timer0 Module High Byte Register
0000 0000
0000 0000
INTCON
GIE/GIEH
T0CON
TMR0ON
TRISA
—
Legend:
Note 1:
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
1111 1111
-111 1111
-111 1111
PORTA Data Direction Register(1)
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
Bit 6 of PORTA, LATA and TRISA is enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, it is
disabled and reads as ‘0’.
© 2006 Microchip Technology Inc.
DS41159E-page 111
PIC18FXX8
NOTES:
DS41159E-page 112
© 2006 Microchip Technology Inc.
PIC18FXX8
12.0
TIMER1 MODULE
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter
(two 8-bit registers: TMR1H and TMR1L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module special event trigger
REGISTER 12-1:
Register 12-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 Oscillator
Enable bit (T1OSCEN). Timer1 can be enabled/
disabled by setting/clearing control bit, TMR1ON
(T1CON register).
Figure 12-1 is a simplified block diagram of the Timer1
module.
Note:
Timer1 is disabled on POR.
T1CON: TIMER1 CONTROL REGISTER
R/W-0
U-0
RD16
—
R/W-0
R/W-0
R/W-0
T1CKPS1 T1CKPS0 T1OSCEN
R/W-0
R/W-0
R/W-0
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 6
Unimplemented: Read as ‘0’
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut-off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 113
PIC18FXX8
12.1
Timer1 Operation
When TMR1CS is clear, Timer1 increments every
instruction cycle. When TMR1CS is set, Timer1
increments on every rising edge of the external clock
input or the Timer1 oscillator, if enabled.
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC value is
ignored.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON register).
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (Section 15.1
“CCP1 Module”).
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag bit
TMR1
TMR1H
Synchronized
Clock Input
0
CLR
TMR1L
1
TMR1ON
On/Off
T1SYNC
T1OSC
T1CKI/T1OSO
T1OSCEN
Enable
Oscillator(1)
T1OSI
1
FOSC/4
Internal
Clock
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
T1CKPS1:T1CKPS0
Sleep Input
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus
8
TMR1H
8
8
Write TMR1L
Special Event Trigger
Read TMR1L
TMR1IF
Overflow
Interrupt
Flag bit
Timer 1
High Byte
Synchronized
Clock Input
0
TMR1
8
TMR1L
1
TMR1ON
On/Off
T1SYNC
T1OSC
T1CKI/T1OSO
T1OSI
1
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
Sleep Input
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
DS41159E-page 114
© 2006 Microchip Technology Inc.
PIC18FXX8
12.2
Timer1 Oscillator
12.4
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON register). The
oscillator is a low-power oscillator rated up to 50 kHz. It
will continue to run during Sleep. It is primarily intended
for a 32 kHz crystal. Table 12-1 shows the capacitor
selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
TABLE 12-1:
Osc Type
LP
CAPACITOR SELECTION FOR
THE ALTERNATE
OSCILLATOR
Freq
C1
C2
32 kHz
TBD(1)
TBD(1)
Crystal to be Tested:
32.768 kHz Epson C-001R32.768K-A
±20 PPM
Note 1: Microchip suggests 33 pF as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external components.
4: Capacitor values are for design guidance
only.
12.3
Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The TMR1
Interrupt, if enabled, is generated on overflow which is
latched in interrupt flag bit, TMR1IF (PIR registers). This
interrupt can be enabled/disabled by setting/clearing
TMR1 Interrupt Enable bit, TMR1IE (PIE registers).
© 2006 Microchip Technology Inc.
Resetting Timer1 Using a CCP
Trigger Output
If the CCP module is configured in Compare mode
to
generate
a
“special
event
trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit,
TMR1IF (PIR registers).
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a special
event trigger from CCP1, the write will take precedence.
In this mode of operation, the CCPR1H:CCPR1L register
pair effectively becomes the period register for Timer1.
12.5
Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit (T1CON
register) is set, the address for TMR1H is mapped to a
buffer register for the high byte of Timer1. A read from
TMR1L will load the contents of the high byte of Timer1
into the Timer1 High Byte Buffer register. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, is valid
due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
DS41159E-page 115
PIC18FXX8
TABLE 12-2:
Name
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111 1111 1111
INTCON GIE/GIEH PEIE/GIEL
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
T1CON
Legend:
Note 1:
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
DS41159E-page 116
© 2006 Microchip Technology Inc.
PIC18FXX8
13.0
TIMER2 MODULE
13.1
The Timer2 module timer has the following features:
•
•
•
•
•
•
•
8-bit timer (TMR2 register)
8-bit period register (PR2)
Readable and writable (both registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Interrupt on TMR2 match of PR2
SSP module optional use of TMR2 output to
generate clock shift
Register 13-1 shows the Timer2 Control register.
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON register) to minimize power consumption.
Figure 13-1 is a simplified block diagram of the Timer2
module. The prescaler and postscaler selection of
Timer2 are controlled by this register.
Timer2 Operation
Timer2 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable and is cleared on any device
Reset. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON register). The match
output of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit TMR2IF, PIR
registers).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
Note:
REGISTER 13-1:
Timer2 is disabled on POR.
T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
R/W-0
TMR2ON
R/W-0
R/W-0
T2CKPS1 T2CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 117
PIC18FXX8
13.2
Timer2 Interrupt
13.3
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
FIGURE 13-1:
Output of TMR2
The output of TMR2 (before the postscaler) is a clock
input to the Synchronous Serial Port module which
optionally uses it to generate the shift clock.
TIMER2 BLOCK DIAGRAM
Sets Flag
bit TMR2IF
TMR2
Output(1)
Prescaler
1:1, 1:4, 1:16
FOSC/4
TMR2
2
Reset
Comparator
EQ
Postscaler
1:1 to 1:16
T2CKPS1:T2CKPS0
4
PR2
TOUTPS3:TOUTPS0
Note 1:
TABLE 13-1:
Name
TMR2 register output can be software selected by the SSP module as a baud clock.
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Value on
all other
Resets
Bit 0
Value on
POR, BOR
0000 000x 0000 000u
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111 1111 1111
INTCON GIE/GIEH PEIE/GIEL
TMR2
T2CON
PR2
Legend:
Note 1:
Timer2 Module Register
—
0000 0000 0000 0000
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register
1111 1111 1111 1111
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
DS41159E-page 118
© 2006 Microchip Technology Inc.
PIC18FXX8
14.0
TIMER3 MODULE
Figure 14-1 is a simplified block diagram of the Timer3
module.
The Timer3 module timer/counter has the following
features:
Register 14-1 shows the Timer3 Control register. This
register controls the operating mode of the Timer3
module and sets the CCP1 and ECCP1 clock source.
• 16-bit timer/counter
(two 8-bit registers: TMR3H and TMR3L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP1/ECCP1 module trigger
Register 12-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 Oscillator
Enable bit (T1OSCEN) which can be a clock source for
Timer3.
Note:
REGISTER 14-1:
Timer3 is disabled on POR.
T3CON:TIMER3 CONTROL REGISTER
R/W-0
RD16
R/W-0
R/W-0
R/W-0
T3ECCP1 T3CKPS1 T3CKPS0
R/W-0
R/W-0
R/W-0
R/W-0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
bit 7
bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
bit 6,3
T3ECCP1:T3CCP1: Timer3 and Timer1 to CCP1/ECCP1 Enable bits
1x = Timer3 is the clock source for compare/capture CCP1 and ECCP1 modules
01 = Timer3 is the clock source for compare/capture of ECCP1,
Timer1 is the clock source for compare/capture of CCP1
00 = Timer1 is the clock source for compare/capture CCP1 and ECCP1 modules
bit 5-4
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 2
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling edge)
0 = Internal clock (FOSC/4)
bit 0
TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 119
PIC18FXX8
14.1
Timer3 Operation
When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is set),
the RC1/T1OSI and RC0/T1OSO/T1CKI pins become
inputs. That is, the TRISC value is ignored.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON register).
FIGURE 14-1:
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (Section 15.1
“CCP1 Module”).
TIMER3 BLOCK DIAGRAM
CCP Special Trigger
T3CCPx
0
TMR3IF
Overflow
Interrupt
Flag bit
TMR3H
CLR
TMR3L
1
TMR3ON
On/Off
T3SYNC
T1OSC
T1OSO/
T1CKI
Synchronized
Clock Input
1
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
T1OSI
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
Sleep Input
TMR3CS
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus
8
TMR3H
8
8
Write TMR3L
Read TMR3L
TMR3IF Overflow
Interrupt Flag
bit
8
CCP Special Trigger
T3CCPx
0
TMR3
TMR3H
TMR3L
CLR
Synchronized
Clock Input
1
To Timer1 Clock Input
T1OSO/
T1CKI
T1OSI
TMR3ON
On/Off
T3SYNC
T1OSC
1
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
T3CKPS1:T3CKPS0
Sleep Input
TMR3CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS41159E-page 120
© 2006 Microchip Technology Inc.
PIC18FXX8
14.2
Timer1 Oscillator
14.4
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN bit (T1CON register). The oscillator is a
low-power oscillator rated up to 50 kHz. Refer to
Section 12.0 “Timer1 Module” for Timer1 oscillator
details.
14.3
If the CCP module is configured in Compare mode
to
generate
a
“special
event
trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer3.
Note:
Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to 0FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR3IF (PIR registers). This interrupt can be enabled/disabled by setting/
clearing TMR3 Interrupt Enable bit, TMR3IE (PIE
registers).
TABLE 14-1:
Name
Resetting Timer3 Using a CCP
Trigger Output
Bit 7
The special event triggers from the CCP
module will not set interrupt flag bit
TMR3IF (PIR registers).
Timer3 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If
Timer3 is running in Asynchronous Counter mode, this
Reset operation may not work. In the event that a write
to Timer3 coincides with a special event trigger from
CCP1, the write will take precedence. In this mode of
operation, the CCPR1H:CCPR1L register pair becomes
the period register for Timer3. Refer to Section 15.0
“Capture/Compare/PWM (CCP) Modules” for CCP
details.
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Value on
all other
Resets
Bit 0
Value on
POR, BOR
RBIF
0000 000x 0000 000u
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
PIE2
—
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE ECCP1IE -0-0 0000 -0-0 0000
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP ECCP1IP -1-1 1111 -1-1 1111
INTCON
GIE/ GIEH PEIE/GIEL
ECCP1IF -0-0 0000 -0-0 0000
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
T1CON
RD16
—
T3CON
RD16
T3ECCP1
Legend:
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
T3CKPS1 T3CKPS0
T3CCP1
T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
© 2006 Microchip Technology Inc.
DS41159E-page 121
PIC18FXX8
NOTES:
DS41159E-page 122
© 2006 Microchip Technology Inc.
PIC18FXX8
15.0
CAPTURE/COMPARE/PWM
(CCP) MODULES
module has a Capture special event trigger that can be
used as a message received time-stamp for the CAN
module (refer to Section 19.0 “CAN Module” for CAN
operation) which the ECCP module does not. The
ECCP module, on the other hand, has Enhanced PWM
functionality and auto-shutdown capability. Aside from
these, the operation of the module described in this
section is the same as the ECCP.
The CCP (Capture/Compare/PWM) module contains a
16-bit register that can operate as a 16-bit Capture
register, as a 16-bit Compare register or as a PWM
Duty Cycle register.
The operation of the CCP module is identical to that
of the ECCP module (discussed in detail in
Section 16.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”) with two exceptions. The CCP
REGISTER 15-1:
The control register for the CCP module is shown in
Register 15-1. Table 15-2 (following page) details the
interactions of the CCP and ECCP modules.
CCP1CON: CCP1 CONTROL REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The upper eight bits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Capture mode, CAN message received (CCP1 only)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize CCP pin low, on compare match force CCP pin high
(CCPIF bit is set)
1001 = Compare mode, initialize CCP pin high, on compare match force CCP pin low
(CCPIF bit is set)
1010 = Compare mode, CCP pin is unaffected
(CCPIF bit is set)
1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP resets TMR1 or TMR3
and starts an A/D conversion if the A/D module is enabled)
11xx = PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 123
PIC18FXX8
15.1
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON). When a capture is made, the
interrupt request flag bit, CCP1IF (PIR registers), is set.
It must be cleared in software. If another capture
occurs before the value in register CCPR1 is read, the
old captured value will be lost.
Table 15-1 shows the timer resources of the CCP
module modes.
15.2.1
TABLE 15-1:
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC bit.
CCP1 MODE – TIMER
RESOURCE
CCP1 Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
15.2
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the 16bit value of the TMR1 or TMR3 register when an event
occurs on pin RC2/CCP1. An event is defined as:
•
•
•
•
Note:
15.2.2
CCP PIN CONFIGURATION
If the RC2/CCP1 is configured as an output, a write to the port can cause a capture
condition.
TIMER1/TIMER3 MODE SELECTION
The timers used with the capture feature (either Timer1
and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer
used with each CCP module is selected in the T3CON
register.
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
TABLE 15-2:
CCP1
Mode
INTERACTION OF CCP1 AND ECCP1 MODULES
ECCP1
Mode
Interaction
Capture
Capture
TMR1 or TMR3 time base. Time base can be different for each CCP.
Capture
Compare
The compare could be configured for the special event trigger which clears either TMR1
or TMR3, depending upon which time base is used.
Compare
Compare
The compare(s) could be configured for the special event trigger which clears TMR1 or
TMR3, depending upon which time base is used.
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM
Capture
None.
PWM
Compare
None.
DS41159E-page 124
© 2006 Microchip Technology Inc.
PIC18FXX8
15.2.3
SOFTWARE INTERRUPT
15.2.5
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE registers) clear to avoid false interrupts
and should clear the flag bit CCP1IF, following any
such change in operating mode.
15.2.4
CCP1 PRESCALER
There are four prescaler settings specified by bits
CCP1M3:CCP1M0. Whenever the CCP1 module is
turned off, or the CCP1 module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
FIGURE 15-1:
CAN MESSAGE TIME-STAMP
The CAN capture event occurs when a message is
received in either of the receive buffers. The CAN
module provides a rising edge to the CCP1 module to
cause a capture event. This feature is provided to
time-stamp the received CAN messages.
This feature is enabled by setting the CANCAP bit of
the CAN I/O control register (CIOCON). The
message receive signal from the CAN module then
takes the place of the events on RC2/CCP1.
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
MOVLW
CCP1CON, F
NEW_CAPT_PS
MOVWF
CCP1CON
;
;
;
;
;
;
Turn CCP module off
Load WREG with the
new prescaler mode
value and CCP ON
Load CCP1CON with
this value
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set Flag bit CCP1IF
(PIR1)
T3CCP1
T3ECCP1
TMR3H
TMR3
Enable
Prescaler
÷ 1, 4, 16
CCP1 pin
CCPR1H
and
Edge Detect
TMR3L
CCPR1L
TMR1
Enable
T3ECCP1
T3CCP1
TMR1H
TMR1L
CCP1CON
Qs
Note: I/O pins have diode protection to VDD and VSS.
© 2006 Microchip Technology Inc.
DS41159E-page 125
PIC18FXX8
15.3
15.3.2
Compare Mode
In Compare mode, the 16-bit CCPR1 and ECCPR1
register value is constantly compared against either the
TMR1 register pair value or the TMR3 register pair
value. When a match occurs, the CCP1 pin can have
one of the following actions:
•
•
•
•
Driven high
Driven low
Toggle output (high-to-low or low-to-high)
Remains unchanged
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the appropriate TRISC bit.
Note:
Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the data latch.
FIGURE 15-2:
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.3.3
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0. At the same time, interrupt flag
bit CCP1IF is set.
15.3.1
TIMER1/TIMER3 MODE SELECTION
15.3.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets either
the TMR1 or TMR3 register pair. Additionally, the
ECCP1 special event trigger will start an A/D
conversion if the A/D module is enabled.
Note:
The special event trigger from the ECCP1
module will not set the Timer1 or Timer3
interrupt flag bits.
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will:
Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit)
Set bit GO/DONE which starts an A/D conversion (ECCP1 only)
TMR1H
TMR3H
TMR1L
TMR3L
Special Event Trigger
Set Flag bit CCP1IF
(PIR1)
Q
CCP1
R
Output Enable
Note
S
1:
DS41159E-page 126
Output
Logic
Match
T3CCP1
T3ECCP1
0
1
Comparator
CCPR1H
CCPR1L
CCP1CON
Mode Select
I/O pins have diode protection to VDD and VSS.
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 15-3:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111 1111 1111
TRISD
PORTD Data Direction Register
1111 1111 1111 1111
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
T1CON
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
CCP1CON
—
PIR2
PIE2
IPR2
DC1B0
TMR1CS
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
DC1B1
CCP1M3
CCP1M2
CCP1M1
—
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
ECCP1IF -0-0 0000 -0-0 0000
—
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
ECCP1IE -0-0 0000 -0-0 0000
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
ECCP1IP -1-1 1111 -1-1 1111
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
T3CON
Legend:
Note 1:
TMR1ON 0-00 0000 u-uu uuuu
RD16
T3ECCP1 T3CKPS1 T3CKPS0
T3CCP1
T3SYNC
TMR3CS
CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR3ON 0000 0000 uuuu uuuu
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
© 2006 Microchip Technology Inc.
DS41159E-page 127
PIC18FXX8
15.4
15.4.1
PWM Mode
In Pulse-Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula.
EQUATION 15-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
Figure 15-3 shows a simplified block diagram of the
CCP module in PWM mode.
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.4.3
“Setup for PWM Operation”.
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
FIGURE 15-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty Cycle Registers
Note:
CCP1CON
CCPR1L (Master)
15.4.2
CCPR1H (Slave)
R
Comparator
Q
RC2/CCP1
(Note 1)
TMR2
S
TRISC
Comparator
Clear Timer,
set CCP1 pin and
latch D.C.
PR2
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock,
or 2 bits of the prescaler, to create 10-bit time base.
The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON. The following equation is
used to calculate the PWM duty cycle in time.
EQUATION 15-2:
PWM Duty Cycle = (CCPR1L:CCP1CON) •
TOSC • (TMR2 Prescale Value)
A PWM output (Figure 15-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
CCPR1L and CCP1CON can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
FIGURE 15-4:
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
PWM OUTPUT
Period
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
DS41159E-page 128
© 2006 Microchip Technology Inc.
PIC18FXX8
15.4.3
The maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation.
The following steps should be taken when configuring
the CCP module for PWM operation:
EQUATION 15-3:
1.
F OSC
log ⎛ ---------------⎞
⎝ F PWM⎠
PWM Resolution (max) = -----------------------------bits
log ( 2 )
2.
3.
Note:
4.
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TABLE 15-4:
SETUP FOR PWM OPERATION
5.
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON bits.
Make the CCP1 pin an output by clearing the
TRISC bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.76 kHz
39.06 kHz
156.3 kHz
312.5 kHz
416.6 kHz
16
4
1
1
1
1
0FFh
0FFh
0FFh
3Fh
1Fh
17h
10
10
10
8
7
5.5
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 15-5:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111 1111 1111
TRISD
PORTD Data Direction Register
1111 1111 1111 1111
TMR2
Timer2 Module Register
0000 0000 0000 0000
PR2
Timer2 Module Period Register
1111 1111 1111 1111
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L
Capture/Compare/PWM Register1 (LSB)
CCPR1H
Capture/Compare/PWM Register1 (MSB)
CCP1CON
Legend:
Note 1:
—
—
DC1B1
DC1B0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3
CCP1M2
CCP1M1
CCP1M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
© 2006 Microchip Technology Inc.
DS41159E-page 129
PIC18FXX8
NOTES:
DS41159E-page 130
© 2006 Microchip Technology Inc.
PIC18FXX8
16.0
Note:
ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
The ECCP (Enhanced Capture/Compare/
PWM) module is only available on
PIC18F448 and PIC18F458 devices.
This module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
REGISTER 16-1:
bit 5-4
bit 3-0
The control register
Register 16-1.
for
ECCP1
is
shown
in
ECCP1CON: ECCP1 CONTROL REGISTER
R/W-0
R/W-0
EPWM1M1 EPWM1M0
bit 7
bit 7-6
The operation of the ECCP module differs from the
CCP (discussed in detail in Section 15.0 “Capture/
Compare/PWM (CCP) Modules”) with the addition of
an Enhanced PWM module which allows for up to 4
output channels and user selectable polarity. These
features are discussed in detail in Section 16.5
“Enhanced PWM Mode”. The module can also be
programmed for automatic shutdown in response to
various analog or digital events.
R/W-0
EDC1B1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0
bit 0
EPWM1M: PWM Output Configuration bits
If ECCP1M = 00, 01, 10:
xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins
If ECCP1M = 11:
00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins
01 = Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output; P1A, P1B modulated with deadband control; P1C, P1D assigned as
port pins
11 = Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive
EDC1B: PWM Duty Cycle Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in ECCPR1L.
ECCP1M: ECCP1 Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Unused (reserved)
0010 = Compare mode, toggle output on match (ECCP1IF bit is set)
0011 = Unused (reserved)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (ECCP1IF bit is set)
1001 = Compare mode, clear output on match (ECCP1IF bit is set)
1010 = Compare mode, ECCP1 pin is unaffected (ECCP1IF bit is set)
1011 = Compare mode, trigger special event (ECCP1IF bit is set; ECCP resets TMR1or TMR3
and starts an A/D conversion if the A/D module is enabled)
1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low
Legend:
R = Readable bit
-n = Value at POR
© 2006 Microchip Technology Inc.
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DS41159E-page 131
PIC18FXX8
16.1
ECCP1 Module
Enhanced Capture/Compare/PWM Register 1 (ECCPR1)
is comprised of two 8-bit registers: ECCPR1L (low
byte) and ECCPR1H (high byte). The ECCP1CON
register controls the operation of ECCP1; the additional
registers, ECCPAS and ECCP1DEL, control Enhanced
PWM specific features. All registers are readable and
writable.
Table 16-1 shows the timer resources for the ECCP
module modes. Table 16-2 describes the interactions
of the ECCP module with the standard CCP module.
TABLE 16-2:
In PWM mode, the ECCP module can have up to four
available outputs, depending on which operating mode
is selected. These outputs are multiplexed with PORTD
and the Parallel Slave Port. Both the operating mode
and the output pin assignments are configured by setting
PWM output configuration bits, EPWM1M1:EPWM1M0
(ECCP1CON). The specific pin assignments for
the various output modes are shown in Table 16-3.
TABLE 16-1:
ECCP1 MODE – TIMER
RESOURCE
ECCP1 Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
INTERACTION OF CCP1 AND ECCP1 MODULES
ECCP1 Mode
CCP1 Mode
Interaction
Capture
Capture
TMR1 or TMR3 time base. Time base can be different for each CCP.
Capture
Compare
The compare could be configured for the special event trigger which clears either
TMR1 or TMR3 depending upon which time base is used.
Compare
Compare
The compare(s) could be configured for the special event trigger which clears TMR1
or TMR3 depending upon which time base is used.
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM
Capture
None
PWM
Compare
None
TABLE 16-3:
PIN ASSIGNMENTS FOR VARIOUS ECCP MODES
ECCP1CON
Configuration
RD4
RD5
RD6
RD7
Conventional CCP Compatible
00xx11xx
ECCP1
RD,
PSP
RD,
PSP
RD,
PSP
Dual Output PWM(2)
10xx11xx
P1A
P1B
RD,
PSP
RD,
PSP
Quad Output PWM(2)
x1xx11xx
P1A
P1B
P1C
P1D
ECCP Mode(1)
Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.
Note 1: In all cases, the appropriate TRISD bits must be cleared to make the corresponding pin an output.
2: In these modes, the PSP I/O control for PORTD is overridden by P1B, P1C and P1D.
DS41159E-page 132
© 2006 Microchip Technology Inc.
PIC18FXX8
16.2
Capture Mode
16.3
The Capture mode of the ECCP module is virtually
identical in operation to that of the standard CCP module as discussed in Section 15.1 “CCP1 Module”.
The differences are in the registers and port pins
involved:
Compare Mode
The Compare mode of the ECCP module is virtually
identical in operation to that of the standard CCP
module as discussed in Section 15.2 “Capture
Mode”. The differences are in the registers and port
pins as described in Section 16.2 “Capture Mode”.
All other details are exactly the same.
• The 16-bit Capture register is ECCPR1
(ECCPR1H and ECCPR1L);
• The capture event is selected by control bits
ECCP1M3:ECCP1M0 (ECCP1CON);
• The interrupt bits are ECCP1IE (PIE2) and
ECCP1IF (PIR2); and
• The capture input pin is RD4 and its corresponding
direction control bit is TRISD.
16.3.1
Except as noted below, the special event trigger output
of ECCP1 functions identically to that of the standard
CCP module. It may be used to start an A/D conversion
if the A/D module is enabled.
Note:
Other operational details, including timer selection,
output pin configuration and software interrupts, are
exactly the same as the standard CCP module.
16.2.1
SPECIAL EVENT TRIGGER
The special event trigger from the ECCP1
module will not set the Timer1 or Timer3
interrupt flag bits.
CAN MESSAGE TIME-STAMP
The special capture event for the reception of CAN messages (Section 15.2.5 “CAN Message Time-Stamp”)
is not available with the ECCP module.
TABLE 16-4:
Name
REGISTERS ASSOCIATED WITH ENHANCED CAPTURE, COMPARE,
TIMER1 AND TIMER3
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Value on
all other
Resets
Bit 0
Value on
POR, BOR
RBIF
0000 000x 0000 000u
INT0IE
RBIE
TMR0IF
INT0IF
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
ECCP1IF -0-0 0000 -0-0 0000
PIE2
—
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
ECCP1IE -0-0 0000 -0-0 0000
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
ECCP1IP -1-1 1111 -1-1 1111
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
Bit 4
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
T1CON
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0-00 0000 u-uu uuuu
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
T3CON
RD16
T3ECCP1 T3CKPS1 T3CKPS0
T3CCP1
T3SYNC
TMR3CS TMR3ON 0000 0000 uuuu uuuu
TRISD
PORTD Data Direction Register
1111 1111 1111 1111
ECCPR1L
Capture/Compare/PWM Register1 (LSB)
xxxx xxxx uuuu uuuu
ECCPR1H
Capture/Compare/PWM Register1 (MSB)
ECCP1CON EPWM1M1 EPWM1M0 EDC1B1
Legend:
EDC1B0
xxxx xxxx uuuu uuuu
ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 0000 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module and Timer1.
© 2006 Microchip Technology Inc.
DS41159E-page 133
PIC18FXX8
16.4
Standard PWM Mode
Figure 16-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when the assigned timer resets) in
order to prevent glitches on any of the outputs. The
exception is the PWM Delay register, ECCP1DEL,
which is loaded at either the duty cycle boundary or the
boundary period (whichever comes first). Because of
the buffering, the module waits until the assigned timer
resets instead of starting immediately. This means that
Enhanced PWM waveforms do not exactly match the
standard PWM waveforms, but are instead offset by
one full instruction cycle (4 TOSC).
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode as described in Section 15.4
“PWM Mode”. The differences in registers and ports
are as described in Section 16.2 “Capture Mode”. In
addition, the two Least Significant bits of the 10-bit
PWM duty cycle value are represented by
ECCP1CON.
Note:
When setting up single output PWM
operations, users are free to use either of
the processes described in Section 15.4.3
“Setup for PWM Operation” or
Section 16.5.8 “Setup for PWM Operation”. The latter is more generic, but will
work for either single or multi-output PWM.
16.5
As before, the user must manually configure the
appropriate TRISD bits for output.
16.5.1
The EPWM1M bits in the ECCP1CON register
allow one of four configurations:
Enhanced PWM Mode
•
•
•
•
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applications. The module is an upwardly compatible version of
the standard CCP module and is modified to provide up
to four outputs, designated P1A through P1D. Users
are also able to select the polarity of the signal (either
active-high or active-low). The module’s output mode
and polarity are configured by setting the
EPWM1M1:EPWM1M0 and ECCP1M3:ECCP1M0 bits
of the ECCP1CON register (ECCP1CON and
ECCP1CON, respectively).
FIGURE 16-1:
PWM OUTPUT CONFIGURATIONS
Single Output
Half-Bridge Output
Full-Bridge Output, Forward mode
Full-Bridge Output, Reverse mode
The Single Output mode is the standard PWM mode
discussed in Section 15.4 “PWM Mode”. The HalfBridge and Full-Bridge Output modes are covered in
detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 16-2.
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
ECCP1CON
EPWM1M1
Duty Cycle Registers
2
ECCP1M
4
ECCPR1L
ECCP1/P1A
RD4/PSP4/ECCP1/P1A
TRISD
ECCPR1H (Slave)
P1B
R
Comparator
Q
Output
Controller
RD5/PSP5/P1B
TRISD
RD6/PSP6/P1C
P1C
TMR2
(Note 1)
TRISD
S
P1D
Comparator
PR2
Note:
Clear Timer,
set ECCP1 pin and
latch D.C.
RD7/PSP7/P1D
TRISD
ECCP1DEL
The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.
DS41159E-page 134
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 16-2:
PWM OUTPUT RELATIONSHIPS
0
ECCP1CON
SIGNAL
PR2 + 1
Duty
Cycle
Period
P1A Modulated, Active-High
00
P1A Modulated, Active-Low
P1A Modulated, Active-High
P1A Modulated, Active-Low
10
Delay
Delay
P1B Modulated, Active-High
P1B Modulated, Active-Low
P1A Active, Active-High
P1A Active, Active-Low
P1B Inactive, Active-High
P1B Inactive, Active-Low
01
P1C Inactive, Active-High
P1C Inactive, Active-Low
P1D Modulated, Active-High
P1D Modulated, Active-Low
P1A Inactive, Active-High
P1A Inactive, Active-Low
P1B Modulated, Active-High
P1B Modulated, Active-Low
11
P1C Active, Active-High
P1C Active, Active-Low
P1D Inactive, Active-High
P1D Inactive, Active-Low
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Duty Cycle = TOSC * (CCPR1L:CCP1CON) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * ECCP1DEL
© 2006 Microchip Technology Inc.
DS41159E-page 135
PIC18FXX8
16.5.2
HALF-BRIDGE MODE
FIGURE 16-3:
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The RD4/PSP4/
ECCP1/P1A pin has the PWM output signal, while the
RD5/PSP5/P1B pin has the complementary PWM
output signal (Figure 16-3). This mode can be used for
half-bridge applications, as shown in Figure 16-4, or for
full-bridge applications where four power switches are
being modulated with two PWM signals.
In Half-Bridge Output mode, the programmable deadband delay can be used to prevent shoot-through
current in bridge power devices. The value of register
ECCP1DEL dictates the number of clock cycles before
the output is driven active. If the value is greater than
the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.5.4
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
HALF-BRIDGE PWM
OUTPUT
Period
Period
Duty Cycle
P1A(2)
td
td
P1B(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as asserted high.
Since the P1A and P1B outputs are multiplexed with
the PORTD and PORTD data latches, the
TRISD and TRISD bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 16-4:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
PIC18F448/458
FET
Driver
+
V
-
P1A
+
Load
FET
Driver
+
V
-
P1B
VHalf-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18F448/458
FET
Driver
FET
Driver
P1A
+
FET
Driver
Load
FET
Driver
P1B
V-
DS41159E-page 136
© 2006 Microchip Technology Inc.
PIC18FXX8
16.5.3
FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In
the Forward mode, pin RD4/PSP4/ECCP1/P1A is continuously active and pin RD7/PSP7/P1D is modulated.
In the Reverse mode, RD6/PSP6/P1C pin is continuously active and RD5/PSP5/P1B pin is modulated.
These are illustrated in Figure 16-5.
FIGURE 16-5:
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTD data latches. The TRISD bits
must be cleared to make the P1A, P1B, P1C and P1D
pins output.
FULL-BRIDGE PWM OUTPUT
FORWARD MODE
Period
P1A(2)
Duty Cycle
P1B(2)
P1C(2)
P1D(2)
(1)
(1)
REVERSE MODE
Period
Duty Cycle
P1A(2)
P1B(2)
P1C(2)
P1D(2)
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as asserted high.
© 2006 Microchip Technology Inc.
DS41159E-page 137
PIC18FXX8
FIGURE 16-6:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC18F448/458
FET
Driver
QB
QD
FET
Driver
P1D
+
Load
P1C
FET
Driver
P1B
FET
Driver
QA
QC
VP1A
16.5.3.1
Direction Change in Full-Bridge
Mode
In the Full-Bridge Output mode, the EPWM1M1 bit in
the ECCP1CON register allows the user to control the
forward/reverse direction. When the application firmware changes this direction control bit, the ECCP1
module will assume the new direction on the next PWM
cycle. The current PWM cycle still continues, however,
the non-modulated outputs, P1A and P1C signals, will
transition to the new direction TOSC, 4 TOSC or 16 TOSC
earlier (for T2CKRS = 00, 01 or 1x, respectively)
before the end of the period. During this transition
cycle, the modulated outputs, P1B and P1D, will go to
the inactive state (Figure 16-7).
Note that in the Full-Bridge Output mode, the ECCP
module does not provide any dead-band delay. In
general, since only one output is modulated at all times,
dead-band delay is not required. However, there is a
situation where a dead-band delay might be required.
This situation occurs when all of the following
conditions are true:
1.
2.
Figure 16-8 shows an example where the PWM
direction changes from forward to reverse at a near
100% duty cycle. At time t1, the outputs P1A and P1D
become inactive, while output P1C becomes active. In
this example, since the turn-off time of the power
devices is longer than the turn-on time, a shoot-through
current flows through power devices QB and QD (see
Figure 16-6) for the duration of ‘t’. The same phenomenon will occur to power devices QA and QC for PWM
direction change from reverse to forward.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
1.
2.
Avoid changing PWM output direction at or near
100% duty cycle.
Use switch drivers that compensate the slow
turn off of the power devices. The total turn-off
time (toff) of the power device and the driver
must be less than the turn-on time (ton).
The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
The turn-off time of the power switch, including
the power device and driver circuit, is greater
than turn-on time.
DS41159E-page 138
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 16-7:
PWM DIRECTION CHANGE
Period(1)
SIGNAL
Period
DC
P1A (Active-High)
P1B (Active-High)
P1C (Active-High)
(2)
P1D (Active-High)
Note 1: The direction bit in the ECCP1 Control Register (ECCP1CON.EPWM1M1) is written any time during the PWM
cycle.
2: The P1A and P1C signals switch at intervals of TOSC, 4 TOSC or 16 TOSC, depending on the Timer2 prescaler
value earlier when changing direction. The modulated P1B and P1D signals are inactive at this time.
FIGURE 16-8:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period
Reverse Period
P1A(1)
P1B(1)
(PWM)
P1C(1)
P1D(1)
(PWM)
ton(2)
External Switch C(1)
toff(3)
External Switch D(1)
Potential
Shoot-Through
Current(1)
t = toff – ton(2,3)
t1
Note 1: All signals are shown as active-high.
2: ton is the turn-on delay of power switch and driver.
3: toff is the turn-off delay of power switch and driver.
© 2006 Microchip Technology Inc.
DS41159E-page 139
PIC18FXX8
16.5.4
PROGRAMMABLE DEAD-BAND
DELAY
In half-bridge or full-bridge applications, where all
power switches are modulated at the PWM frequency
at all times, the power switches normally require longer
time to turn off than to turn on. If both the upper and
lower power switches are switched at the same time
(one turned on and the other turned off), both switches
will be on for a short period of time until one switch
completely turns off. During this time, a very high
current (shoot-through current) flows through both
power switches, shorting the bridge supply. To avoid
this potentially destructive shoot-through current from
flowing during switching, turning on the power switch is
normally delayed to allow the other switch to
completely turn off.
In the Half-Bridge Output mode, a digitally programmable
dead-band delay is available to avoid shoot-through
current from destroying the bridge power switches. The
delay occurs at the signal transition from the non-active
state to the active state. See Figure 16-3 for illustration.
The ECCP1DEL register (Register 16-2) sets the amount
of delay.
16.5.5
SYSTEM IMPLEMENTATION
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external pullup and/or pull-down resistors on the PWM output pins.
When the microcontroller powers up, all of the I/O pins
are in the high-impedance state. The external pull-up
and pull-down resistors must keep the power switch
REGISTER 16-2:
devices in the off state until the microcontroller drives
the I/O pins with the proper signal levels, or activates
the PWM output(s).
16.5.6
START-UP CONSIDERATIONS
Prior to enabling the PWM outputs, the P1A, P1B, P1C
and P1D latches may not be in the proper states.
Enabling the TRISD bits for output at the same time
with the ECCP1 module may cause damage to the
power switch devices. The ECCP1 module must be
enabled in the proper output mode with the TRISD bits
enabled as inputs. Once the ECCP1 completes a full
PWM cycle, the P1A, P1B, P1C and P1D output
latches are properly initialized. At this time, the TRISD
bits can be enabled for outputs to start driving the
power switch devices. The completion of a full PWM
cycle is indicated by the TMR2IF bit going from a ‘0’ to
a ‘1’.
16.5.7
OUTPUT POLARITY
CONFIGURATION
The ECCP1M bits in the ECCP1CON register
allow user to choose the logic conventions (asserted
high/low) for each of the outputs.
The PWM output polarities must be selected before the
PWM outputs are enabled. Charging the polarity
configuration while the PWM outputs are active is not
recommended since it may result in unpredictable
operation.
ECCP1DEL: PWM DELAY REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EPDC7
EPDC6
EPDC5
EPDC4
EPDC3
EPDC2
EPDC1
EPDC0
bit 7
bit 7-0
bit 0
EPDC: PWM Delay Count for Half-Bridge Output Mode bits
Number of FOSC/4 (TOSC * 4) cycles between the P1A transition and the P1B transition.
Legend:
DS41159E-page 140
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
16.5.8
SETUP FOR PWM OPERATION
2.
The following steps should be taken when configuring
the ECCP1 module for PWM operation:
1.
Configure the PWM module:
a) Disable the ECCP1/P1A, P1B, P1C and/or
P1D outputs by setting the respective TRISD
bits.
b) Set the PWM period by loading the PR2
register.
c) Set the PWM duty cycle by loading the
ECCPR1L register and ECCP1CON
bits.
d) Configure the ECCP1 module for the
desired PWM operation by loading the
ECCP1CON register with the appropriate
value. With the ECCP1M bits, select
the active-high/low levels for each PWM
output. With the EPWM1M bits, select
one of the available output modes.
e) For Half-Bridge Output mode, set the deadband delay by loading the ECCP1DEL
register with the appropriate value.
TABLE 16-5:
Name
3.
Configure and start TMR2:
a) Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit in the PIR1 register.
b) Set the TMR2 prescale value by loading the
T2CKPS bits (T2CON).
c) Enable Timer2 by setting the TMR2ON bit
(T2CON) register.
Enable PWM outputs after a new cycle has
started:
a) Wait until TMR2 overflows (TMR2IF bit
becomes a ‘1’). The new PWM cycle begins
here.
b) Enable the ECCP1/P1A, P1B, P1C and/or
P1D pin outputs by clearing the respective
TRISD bits.
REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2
Value on
POR, BOR
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
IPEN
—
—
RI
TO
PD
POR
BOR
0--1 110q 0--0 011q
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
ECCP1IF -0-0 0000 -0-0 0000
PIE2
—
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
ECCP1IE -0-0 0000 -0-0 0000
INTCON
RCON
TMR2
Timer2 Module Register
PR2
Timer2 Module Period Register
T2CON
—
TOUTPS3
ECCP1IP -1-1 1111 -1-1 1111
0000 0000 0000 0000
1111 1111 1111 1111
TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
TRISD
PORTD Data Direction Register
1111 1111 1111 1111
ECCPR1H
Enhanced Capture/Compare/PWM Register 1 High Byte
xxxx xxxx uuuu uuuu
ECCPR1L
Enhanced Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx uuuu uuuu
ECCP1CON EPWM1M1 EPWM1M0
ECCPAS
ECCP1DEL
Legend:
ECCPASE
ECCPAS2
EPDC7
EPDC6
EDC1B1
EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 0000 0000
ECCPAS1 ECCPAS0 PSSAC1
EPDC5
EPDC4
EPDC3
PSSAC0
PSSBD1
PSSBD0 0000 0000 0000 0000
EPDC2
EPDC1
EPDC0
0000 0000 uuuu uuuu
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module.
© 2006 Microchip Technology Inc.
DS41159E-page 141
PIC18FXX8
16.6
Enhanced CCP Auto-Shutdown
When the ECCP is programmed for any of the PWM
modes, the output pins associated with its function may
be configured for auto-shutdown.
Auto-shutdown allows the internal output of either of
the two comparator modules, or the external
interrupt 0, to asynchronously disable the ECCP output
pins. Thus, an external analog or digital event can
discontinue an ECCP sequence. The comparator output(s) to be used is selected by setting the proper mode
bits in the ECCPAS register. To use external interrupt
INT0 as a shutdown event, INT0IE must be set. To use
either of the comparator module outputs as a shutdown
event, corresponding comparators must be enabled.
When a shutdown occurs, the selected output values
(PSSACn, PSSBDn) are written to the ECCP port pins.
REGISTER 16-3:
The internal shutdown signal is gated with the outputs
and will immediately and asynchronously disable the
outputs. If the internal shutdown is still in effect at the
time a new cycle begins, that entire cycle is
suppressed, thus eliminating narrow, glitchy pulses.
The ECCPASE bit is set by hardware upon a comparator event and can only be cleared in software. The
ECCP outputs can be re-enabled only by clearing the
ECCPASE bit.
The Auto-Shutdown mode can be manually entered by
writing a ‘1’ to the ECCPASE bit.
ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
R/W-0
R/W-0
R/W-0
R/W-0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
bit 7
bit 0
bit 7
ECCPASE: ECCP Auto-Shutdown Event Status bit
0 = ECCP outputs enabled, no shutdown event
1 = A shutdown event has occurred, must be reset in software to re-enable ECCP
bit 6-4
ECCPAS: ECCP Auto-Shutdown bits
000 = No auto-shutdown enabled, comparators have no effect on ECCP
001 = Comparator 1 output will cause shutdown
010 = Comparator 2 output will cause shutdown
011 = Either Comparator 1 or 2 can cause shutdown
100 = INT0
101 = INT0 or Comparator 1 output
110 = INT0 or Comparator 2 output
111 = INT0 or Comparator 1 or Comparator 2 output
bit 3-2
PSSACn: Pins A and C Shutdown State Control bits
00 = Drive Pins A and C to ‘0’
01 = Drive Pins A and C to ‘1’
1x = Pins A and C tri-state
bit 1-0
PSSBDn: Pins B and D Shutdown State Control bits
00 = Drive Pins B and D to ‘0’
01 = Drive Pins B and D to ‘1’
1x = Pins B and D tri-state
Legend:
DS41159E-page 142
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
17.0
17.1
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mode
- Slave mode (with general address call)
17.3
SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four modes
of SPI are supported. To accomplish communication,
typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/AN4/SS/LVDIN
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1:
MSSP BLOCK DIAGRAM
(SPI™ MODE)
The I2C interface supports the following modes in
hardware:
Internal
Data Bus
Read
• Master mode
• Multi-Master mode
• Slave mode
17.2
Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual configuration bits
differ significantly, depending on whether the MSSP
module is operated in SPI or I2C mode.
Additional details are provided under the individual
sections.
Write
SSPBUF reg
RC4/SDI/SDA
SSPSR reg
RC5/SDO
RA5/AN4/
SS/LVDIN
Shift
Clock
bit0
SS Control
Enable
Edge
Select
2
Clock Select
RC3/SCK/
SCL
SSPM3:SSPM0
SMP:CKE 4
TMR2 Output
2
2
(
Edge
Select
)
Prescaler TOSC
4, 16, 64
Data to TX/RX in SSPSR
TRIS bit
© 2006 Microchip Technology Inc.
DS41159E-page 143
PIC18FXX8
17.3.1
REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
•
•
•
•
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
MSSP Control Register 1 (SSPCON1)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
MSSP Shift Register (SSPSR) – Not directly
accessible
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 17-1:
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE: SPI Clock Edge Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
Note:
Polarity of clock state is set by the CKP bit (SSPCON1).
bit 5
D/A: Data/Address bit
Used in I2C mode only.
bit 4
P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is
cleared.
bit 3
S: Start bit
Used in I2C mode only.
bit 2
R/W: Read/Write Information bit
Used in I2C mode only.
bit 1
UA: Update Address bit
Used in I2C mode only.
bit 0
BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Legend:
DS41159E-page 144
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 17-2:
SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user
must read the SSPBUF even if only transmitting data to avoid setting overflow (must be
cleared in software).
0 = No overflow
Note:
bit 5
In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note:
When enabled, these pins must be properly configured as input or output.
bit 4
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note:
Bit combinations not specifically listed here are either reserved or implemented in
I2C mode only.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 145
PIC18FXX8
17.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1 and SSPSTAT).
These control bits allow the following to be specified:
•
•
•
•
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full detect bit BF
(SSPSTAT) and the interrupt flag bit SSPIF are set.
This double-buffering of the received data (SSPBUF)
allows the next byte to start reception before reading
the data that was just received. Any write to the
EXAMPLE 17-1:
LOOP BTFSS
BRA
MOVF
SSPBUF register during transmission/reception of data
will be ignored and the Write Collision detect bit, WCOL
(SSPCON1), will be set. User software must clear
the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed
successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
Full bit, BF (SSPSTAT), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally, the MSSP interrupt is used to
determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 17-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.
LOADING THE SSPBUF (SSPSR) REGISTER
SSPSTAT, BF
LOOP
SSPBUF, W
;Has data been received(transmit complete)?
;No
;WREG reg = contents of SSPBUF
MOVWF
RXDATA
;Save in user RAM, if data is meaningful
MOVF
MOVWF
TXDATA, W
SSPBUF
;W reg = contents of TXDATA
;New data to xmit
DS41159E-page 146
© 2006 Microchip Technology Inc.
PIC18FXX8
17.3.3
ENABLING SPI I/O
17.3.4
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON1), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the SSPCON
registers and then, set the SSPEN bit. This configures
the SDI, SDO, SCK and SS pins as serial port pins. For
the pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed as follows:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC bit cleared
• SCK (Master mode) must have TRISC bit
cleared
• SCK (Slave mode) must have TRISC bit set
• SS must have TRISA bit set
TYPICAL CONNECTION
Figure 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be
programmed to the same Clock Polarity (CKP), then
both controllers would send and receive data at the
same time. Whether the data is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• Master sends dummy data – Slave sends data
Any serial port function that is not desired may be overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 17-2:
SPI™ MASTER/SLAVE CONNECTION
SPI™ Master SSPM3:SSPM0 = 00xxb
SPI™ Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
SDI
Shift Register
(SSPSR)
MSb
Serial Input Buffer
(SSPBUF)
LSb
© 2006 Microchip Technology Inc.
Shift Register
(SSPSR)
MSb
SCK
PROCESSOR 1
SDO
Serial Clock
LSb
SCK
PROCESSOR 2
DS41159E-page 147
PIC18FXX8
17.3.5
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 17-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
FIGURE 17-3:
The clock polarity is selected by appropriately programming the CKP bit (SSPCON1). This then, would
give waveforms for SPI communication as shown in
Figure 17-3, Figure 17-5 and Figure 17-6, where the
MSB is transmitted first. In Master mode, the SPI clock
rate (bit rate) is user programmable to be one of the
following:
•
•
•
•
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 17-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
SPI™ MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit7
bit 0
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
DS41159E-page 148
Next Q4 cycle
after Q2↓
© 2006 Microchip Technology Inc.
PIC18FXX8
17.3.6
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep. Before enabling the module in SPI Slave
mode, the clock line must match the proper Idle state.
The clock line can be observed by reading the SCK pin.
The Idle state is determined by the CKP bit
(SSPCON1).
17.3.7
SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1 = 04h). The pin must not be driven
low for the SS pin to function as an input. The data latch
FIGURE 17-4:
must be high. When the SS pin is low, transmission and
reception are enabled and the SDO pin is driven. When
the SS pin goes high, the SDO pin is no longer driven,
even if in the middle of a transmitted byte and becomes
a floating output. External pull-up/pull-down resistors
may be desirable depending on the application.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON1 = 0100),
the SPI module will reset if the SS pin is set
to VDD.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 6
bit 7
bit 0
bit 0
bit 7
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
© 2006 Microchip Technology Inc.
Next Q4 cycle
after Q2↓
DS41159E-page 149
PIC18FXX8
FIGURE 17-5:
SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
FIGURE 17-6:
SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
DS41159E-page 150
Next Q4 cycle
after Q2↓
© 2006 Microchip Technology Inc.
PIC18FXX8
17.3.8
SLEEP OPERATION
17.3.10
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1:
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
17.3.9
EFFECTS OF A RESET
Name
SPI™ BUS MODES
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0
1
0, 1
0
0
1, 0
1
1
1, 1
1
0
There is also an SMP bit which controls when the data
is sampled.
A Reset disables the MSSP module and terminates the
current transfer.
TABLE 17-2:
BUS MODE COMPATIBILITY
REGISTERS ASSOCIATED WITH SPI™ OPERATION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111 1111 1111
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
TRISC
TRISA
SSPBUF
PSPIP
PORTC Data Direction Register
—
TRISA6
TRISA5
1111 1111 1111 1111
Synchronous Serial Port Receive Buffer/Transmit Register
-111 1111 -111 1111
xxxx xxxx uuuu uuuu
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000 0000 0000
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 0000 0000
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI™ mode.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
© 2006 Microchip Technology Inc.
DS41159E-page 151
PIC18FXX8
17.4
I2C Mode
17.4.1
The MSSP module in I 2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs or outputs
through the TRISC bits.
FIGURE 17-7:
MSSP BLOCK DIAGRAM
(I2C™ MODE)
Internal
Data Bus
Read
SSPBUF reg
Shift
Clock
LSb
MSb
Match Detect
•
•
•
•
•
MSSP Control Register 1 (SSPCON1)
MSSP Control Register 2 (SSPCON2)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
SSPSR reg
RC4/
SDI/
SDA
The MSSP module has six registers for I2C operation.
These are:
SSPADD register holds the slave device address
when the SSP is configured in I2C Slave mode. When
the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the Baud Rate
Generator reload value.
Write
RC3/SCK/
SCL
REGISTERS
Addr Match
During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
SSPADD reg
Start and
Stop bit Detect
DS41159E-page 152
Set, Reset
S, P bits
(SSPSTAT reg)
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 17-3:
SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6
CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Note:
bit 3
S: Start bit
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
Note:
bit 2
This bit is cleared on Reset and when SSPEN is cleared.
This bit is cleared on Reset and when SSPEN is cleared.
R/W: Read/Write Information bit (I2C mode only)
In Slave mode:
1 = Read
0 = Write
Note:
This bit holds the R/W bit information following the last address match. This bit is
only valid from the address match to the next Start bit, Stop bit or not ACK bit.
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
Note:
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is
in Idle mode.
bit 1
UA: Update Address bit (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
In Transmit mode:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
In Receive mode:
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 153
PIC18FXX8
REGISTER 17-4:
SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for
a transmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must
be cleared in software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note:
When enabled, the SDA and SCL pins must be properly configured as input or output.
bit 4
CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (Slave Idle)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Note:
Bit combinations not specifically listed here are either reserved or implemented in
SPI mode only.
Legend:
DS41159E-page 154
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 17-5:
SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
Note:
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence Idle
bit 3
RCEN: Receive Enable bit (Master Mode only)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2
PEN: Stop Condition Enable bit (Master mode only)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enable bit (Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is enabled for slave transmit only (Legacy mode)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Note:
© 2006 Microchip Technology Inc.
x = Bit is unknown
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
DS41159E-page 155
PIC18FXX8
17.4.2
OPERATION
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON1).
The SSPCON1 register allows control of the I 2C
operation. Four mode selection bits (SSPCON1)
allow one of the following I 2C modes to be selected:
I2C Master mode, clock = OSC/4 (SSPADD +1)
I 2C Slave mode (7-bit address)
I 2C Slave mode (10-bit address)
I 2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I 2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I 2C Firmware Controlled Master mode, slave is
Idle
•
•
•
•
Selection of any I 2C mode with the SSPEN bit set
forces the SCL and SDA pins to be open-drain, provided these pins are programmed to inputs by setting
the appropriate TRISC bits. To ensure proper operation
of the module, pull-up resistors must be provided
externally to the SCL and SDA pins.
17.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I 2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits.
When an address is matched, or the data transfer after
an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
17.4.3.1
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock
(SCL) line. The value of register SSPSR is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1.
2.
3.
4.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
The SSPSR register value is loaded into the
SSPBUF register.
The Buffer Full bit BF is set.
An ACK pulse is generated.
MSSP Interrupt Flag bit, SSPIF (PIR1), is
set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs
of the address. The sequence of events for 10-bit
address is as follows, with steps 7 through 9 for the
slave-transmitter:
1.
2.
3.
4.
5.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPSTAT), was set
before the transfer was received.
• The overflow bit, SSPOV (SSPCON1), was
set before the transfer was received.
Addressing
6.
7.
8.
9.
Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT) are set).
Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive Repeated Start condition.
Receive first (high) byte of address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
DS41159E-page 156
© 2006 Microchip Technology Inc.
PIC18FXX8
17.4.3.2
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT) is
set or bit SSPOV (SSPCON1) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1) must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2 = 1), RC3/SCK/SCL
will be held low (clock stretch) following each data
transfer. The clock must be released by setting bit
CKP (SSPCON1). See Section 17.4.4 “Clock
Stretching” for more detail.
17.4.3.3
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low regardless of SEN (see Section 17.4.4 “Clock
Stretching” for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register,
which also loads the SSPSR register. Then, pin RC3/
SCK/SCL should be enabled by setting bit CKP
(SSPCON1). The eight data bits are shifted out on
the falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 17-9).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
© 2006 Microchip Technology Inc.
DS41159E-page 157
DS41159E-page 158
CKP
2
A6
3
4
A4
5
A3
Receiving Address
A5
6
A2
(CKP does not reset to ‘0’ when SEN = 0)
SSPOV (SSPCON1)
BF (SSPSTAT)
(PIR1)
SSPIF
1
SCL
S
A7
7
A1
8
9
ACK
R/W = 0
1
D7
3
4
D4
5
D3
Receiving Data
D5
Cleared in software
SSPBUF is read
2
D6
6
D2
7
D1
8
D0
9
ACK
1
D7
2
D6
3
4
D4
5
D3
Receiving Data
D5
6
D2
7
D1
8
D0
Bus master
terminates
transfer
P
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
9
ACK
FIGURE 17-8:
SDA
PIC18FXX8
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
© 2006 Microchip Technology Inc.
© 2006 Microchip Technology Inc.
1
CKP
2
A6
Data in
sampled
BF (SSPSTAT)
SSPIF (PIR1)
S
A7
3
A5
4
A4
5
A3
6
A2
Receiving Address
7
A1
8
R/W = 1
9
ACK
SCL held low
while CPU
responds to SSPIF
1
D7
4
D4
5
D3
Cleared in software
3
D5
6
D2
CKP is set in software
SSPBUF is written in software
2
D6
Transmitting Data
7
8
D0
9
ACK
From SSPIF ISR
D1
1
D7
4
D4
5
D3
6
D2
CKP is set in software
7
8
D0
9
ACK
From SSPIF ISR
D1
Transmitting Data
Cleared in software
3
D5
SSPBUF is written in software
2
D6
P
FIGURE 17-9:
SCL
SDA
PIC18FXX8
I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
DS41159E-page 159
DS41159E-page 160
2
1
4
1
5
0
7
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
6
A9 A8
8
9
(CKP does not reset to ‘0’ when SEN = 0)
UA (SSPSTAT)
SSPOV (SSPCON1)
CKP
3
1
Cleared in software
BF (SSPSTAT)
(PIR1)
SSPIF
1
SCL
S
1
ACK
R/W = 0
A7
2
4
A4
5
A3
6
8
A0
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware
when SSPADD is updated
with low byte of address
7
A2 A1
Cleared in software
3
A5
Dummy read of SSPBUF
to clear BF flag
1
A6
Receive Second Byte of Address
9
ACK
1
D7
4
5
6
Cleared in software
3
7
8
9
1
2
4
5
6
Cleared in software
3
D3 D2
Receive Data Byte
D1 D0 ACK D7 D6 D5 D4
Cleared by hardware when
SSPADD is updated with high
byte of address
2
D3 D2
Receive Data Byte
D6 D5 D4
Clock is held low until
update of SSPADD has
taken place
7
8
D1 D0
9
P
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
ACK
FIGURE 17-10:
SDA
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
PIC18FXX8
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
© 2006 Microchip Technology Inc.
© 2006 Microchip Technology Inc.
2
CKP (SSPCON1)
UA (SSPSTAT)
BF (SSPSTAT)
(PIR1)
SSPIF
1
S
SCL
1
4
1
5
0
6
7
A9 A8
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
3
1
Receive First Byte of Address
1
8
9
ACK
1
3
4
5
Cleared in software
2
7
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with low
byte of address
6
A6 A5 A4 A3 A2 A1
8
A0
Receive Second Byte of Address
Dummy read of SSPBUF
to clear BF flag
A7
9
ACK
2
3
1
4
1
Cleared in software
1
1
5
0
6
8
9
ACK
R/W = 1
1
2
4
5
6
CKP is set in software
9
P
Completion of
data transmission
clears BF flag
8
ACK
Bus master
terminates
transfer
CKP is automatically cleared in hardware holding SCL low
7
D4 D3 D2 D1 D0
Cleared in software
3
D7 D6 D5
Transmitting Data Byte
Clock is held low until
CKP is set to ‘1’
Write of SSPBUF
BF flag is clear
initiates transmit
at the end of the
third address sequence
7
A9 A8
Cleared by hardware when
SSPADD is updated with high
byte of address
Dummy read of SSPBUF
to clear BF flag
Sr
1
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
FIGURE 17-11:
SDA
R/W = 0
Clock is held low until
update of SSPADD has
taken place
PIC18FXX8
I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
DS41159E-page 161
PIC18FXX8
17.4.4
CLOCK STRETCHING
Both 7 and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence.
The SEN bit (SSPCON2) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
17.4.4.1
Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPCON1 register is automatically cleared, forcing the SCL output to be held
low. The CKP being cleared to ‘0’ will assert the SCL
line low. The CKP bit must be set in the user’s ISR
before reception is allowed to continue. By holding the
SCL line low, the user has time to service the ISR and
read the contents of the SSPBUF before the master
device can initiate another receive sequence. This will
prevent buffer overruns from occurring.
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
17.4.4.2
17.4.4.3
Clock Stretching for 7-bit Slave
Transmit Mode
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock if the BF bit is clear. This occurs regardless
of the state of the SEN bit.
The user’s ISR must set the CKP bit before transmission is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 17-9).
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
17.4.4.4
Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is
controlled during the first two address sequences by
the state of the UA bit, just as it is in 10-bit Slave
Receive mode. The first two addresses are followed
by a third address sequence which contains the highorder bits of the 10-bit address and the R/W bit set to
‘1’. After the third address sequence is performed, the
UA bit is not set, the module is now configured in
Transmit mode and clock stretching is controlled by
the BF flag as in 7-bit Slave Transmit mode (see
Figure 17-11).
Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by reading the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
DS41159E-page 162
© 2006 Microchip Technology Inc.
PIC18FXX8
17.4.4.5
Clock Synchronization and
the CKP bit
If a user clears the CKP bit, the SCL output is forced to
‘0’. Setting the CKP bit will not assert the SCL output
low until the SCL output is already sampled low. If the
user attempts to drive SCL low, the CKP bit will not
FIGURE 17-12:
assert the SCL line until an external I2C master device
has already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other devices
on the I2C bus have deasserted SCL. This ensures that
a write to the CKP bit will not violate the minimum high
time requirement for SCL (see Figure 17-12).
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX – 1
SCL
CKP
Master device
asserts clock
Master device
deasserts clock
WR
SSPCON1
© 2006 Microchip Technology Inc.
DS41159E-page 163
DS41159E-page 164
CKP
SSPOV (SSPCON1)
BF (SSPSTAT)
(PIR1)
SSPIF
1
SCL
S
A7
2
A6
3
4
A4
5
A3
Receiving Address
A5
6
A2
7
A1
8
9
ACK
R/W = 0
3
4
D4
5
D3
Receiving Data
D5
Cleared in software
2
D6
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur
SSPBUF is read
1
D7
6
D2
7
D1
9
ACK
1
D7
BF is set after falling
edge of the 9th clock,
CKP is reset to ‘0’ and
clock stretching occurs
8
D0
CKP
written
to ‘1’ in
software
2
D6
Clock is held low until
CKP is set to ‘1’
3
4
D4
5
D3
Receiving Data
D5
6
D2
7
D1
8
D0
Bus master
terminates
transfer
P
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
9
ACK
Clock is not held low
because ACK = 1
FIGURE 17-13:
SDA
Clock is not held low
because buffer full bit is
clear prior to falling edge
of 9th clock
PIC18FXX8
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
© 2006 Microchip Technology Inc.
© 2006 Microchip Technology Inc.
2
1
UA (SSPSTAT)
SSPOV (SSPCON1)
CKP
3
1
4
1
5
0
6
7
A9 A8
8
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
Cleared in software
BF (SSPSTAT)
(PIR1)
SSPIF
1
SCL
S
1
9
ACK
R/W = 0
A7
2
4
A4
5
A3
6
8
A0
Note:
An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set.
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
of ninth clock
7
A2 A1
Cleared in software
3
A5
Dummy read of SSPBUF
to clear BF flag
1
A6
Receive Second Byte of Address
9
ACK
2
4
5
6
Cleared in software
3
D3 D2
7
Note:
An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set.
8
9
ACK
1
4
5
6
D2
Cleared in software
3
CKP written to ‘1’
in software
2
D3
Receive Data Byte
D7 D6 D5 D4
Clock is held low until
CKP is set to ‘1’
D1 D0
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
of ninth clock
Dummy read of SSPBUF
to clear BF flag
1
D7 D6 D5 D4
Receive Data Byte
Clock is held low until
update of SSPADD has
taken place
7
8
9
Bus master
terminates
transfer
P
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D1 D0
ACK
Clock is not held low
because ACK = 1
FIGURE 17-14:
SDA
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
PIC18FXX8
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
DS41159E-page 165
PIC18FXX8
17.4.5
GENERAL CALL ADDRESS
SUPPORT
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 17-15).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2
set). Following a Start bit detect, 8 bits are shifted into
the SSPSR and the address is compared against the
SSPADD. It is also compared to the general call
address and fixed in hardware.
FIGURE 17-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
Address is compared to General Call Address
after ACK, set interrupt
R/W = 0
ACK D7
General Call Address
SDA
Receiving data
ACK
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
SCL
S
1
2
3
4
5
6
7
8
9
1
9
SSPIF
BF (SSPSTAT)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1)
‘0’
GCEN (SSPCON2)
‘1’
DS41159E-page 166
© 2006 Microchip Technology Inc.
PIC18FXX8
MASTER MODE
Note:
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I 2C bus may be taken when the P bit is
set or the bus is Idle, with both the S and P bits clear.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt if enabled):
In Firmware Controlled Master mode, user code
conducts all I 2C bus operations based on Start and
Stop bit conditions.
•
•
•
•
•
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
Assert a Start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and
SCL.
Write to the SSPBUF register initiating
transmission of data/address.
Configure the I2C port to receive data.
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDA and SCL.
FIGURE 17-16:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Start condition
Stop condition
Data transfer byte transmitted/received
Acknowledge transmit
Repeated Start
MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Internal
Data Bus
Read
SSPM3:SSPM0
SSPADD
Write
SSPBUF
Baud
Rate
Generator
Shift
Clock
SDA
SDA in
SCL in
Bus Collision
© 2006 Microchip Technology Inc.
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
Clock Cntl
SCL
Receive Enable
SSPSR
Clock Arbitrate/WCOL Detect
(hold off clock source)
17.4.6
Set/Reset S, P, WCOL (SSPSTAT);
set SSPIF, BCLIF;
reset ACKSTAT, PEN (SSPCON2)
DS41159E-page 167
PIC18FXX8
17.4.6.1
I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition, or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate receive bit. Serial
data is received via SDA while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an Acknowledge bit is transmitted.
Start and Stop conditions indicate the beginning and
end of transmission.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 17.4.7 “Baud Rate Generator” for more
details.
DS41159E-page 168
A typical transmit sequence would go as follows:
1.
The user generates a Start condition by setting
the Start Enable bit, SEN (SSPCON2).
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all 8 bits are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
11. The user generates a Stop condition by setting
the Stop Enable bit PEN (SSPCON2).
12. Interrupt is generated once the Stop condition is
complete.
© 2006 Microchip Technology Inc.
PIC18FXX8
17.4.7
BAUD RATE GENERATOR
2
In I C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
FIGURE 17-17:
Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
TABLE 17-3:
SSPM3:SSPM0
Reload
SCL
Control
SSPADD
Reload
CLKO
BRG Down Counter
FOSC/4
I2C™ CLOCK RATE w/BRG
FOSC
FCY
FCY * 2
BRG Value
FSCL
(2 Rollovers of BRG)
40 MHz
10 MHz
20 MHz
18h
400 kHz(1)
40 MHz
10 MHz
20 MHz
1Fh
312.5 kHz
40 MHz
10 MHz
20 MHz
63h
100 kHz
16 MHz
4 MHz
8 MHz
09h
400 kHz(1)
16 MHz
4 MHz
8 MHz
0Ch
308 kHz
16 MHz
4 MHz
8 MHz
27h
100 kHz
4 MHz
1 MHz
2 MHz
02h
333 kHz(1)
4 MHz
1 MHz
2 MHz
09h
100kHz
4 MHz
1 MHz
2 MHz
00h
1 MHz(1)
Note 1:
The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
© 2006 Microchip Technology Inc.
DS41159E-page 169
PIC18FXX8
17.4.7.1
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 17-18:
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 17-18).
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX – 1
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
DS41159E-page 170
© 2006 Microchip Technology Inc.
PIC18FXX8
17.4.8
I2C MASTER MODE START
CONDITION TIMING
17.4.8.1
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
To initiate a Start condition, the user sets the Start
condition enable bit, SEN (SSPCON2). If the SDA
and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD
and starts its count. If SCL and SDA are both sampled
high when the Baud Rate Generator times out (TBRG),
the SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the Start condition and
causes the S bit (SSPSTAT) to be set. Following
this, the Baud Rate Generator is reloaded with the
contents of SSPADD and resumes its count.
When the Baud Rate Generator times out (TBRG), the
SEN bit (SSPCON2) will be automatically cleared
by hardware, the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
Note:
WCOL Status Flag
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
If, at the beginning of the Start condition,
the SDA and SCL pins are already sampled low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs;
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
FIGURE 17-19:
FIRST START BIT TIMING
Set S bit (SSPSTAT)
Write to SEN bit occurs here
SDA = 1,
SCL = 1
TBRG
At completion of Start bit,
hardware clears SEN bit
and sets SSPIF bit
TBRG
Write to SSPBUF occurs here
1st bit
SDA
2nd bit
TBRG
SCL
TBRG
S
© 2006 Microchip Technology Inc.
DS41159E-page 171
PIC18FXX8
17.4.9
I2C MASTER MODE REPEATED
START CONDITION TIMING
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode, or the default first address in 10-bit mode. After
the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
A Repeated Start condition occurs when the RSEN bit
(SSPCON2) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the
contents of SSPADD and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit (SSPCON2) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT) will be set. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.
17.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
FIGURE 17-20:
REPEATED START CONDITION WAVEFORM
Set S (SSPSTAT)
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change).
SDA = 1,
SCL = 1
TBRG
TBRG
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
TBRG
1st bit
SDA
Falling edge of ninth clock
End of Xmit
SCL
Write to SSPBUF occurs here
TBRG
TBRG
Sr = Repeated Start
DS41159E-page 172
© 2006 Microchip Technology Inc.
PIC18FXX8
17.4.10
I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit BF and allow the Baud Rate
Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification parameter
#106). SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high (see data setup time specification
parameter #107). When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time, if an
address match occurred, or if data was received properly. The status of ACK is written into the ACKDT bit
on the falling edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 17-21).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the
falling edge of the eighth clock, the master will deassert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2).
Following the falling edge of the ninth clock transmission of the address, the SSPIF bit is set, the BF flag is
cleared and the Baud Rate Generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
17.4.10.1
BF Status Flag
17.4.10.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2) is
cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call)
or when the slave has properly received its data.
17.4.11
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2).
Note:
The RCEN bit should be set after the ACK
sequence is complete or the RCEN bit will
be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes (high-to-low/
low-to-high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The
MSSP is now in Idle state awaiting the next command.
When the buffer is read by the CPU, the BF flag bit is
automatically cleared. The user can then send an
Acknowledge bit at the end of reception by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2).
17.4.11.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
17.4.11.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
17.4.11.3
WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
In Transmit mode, the BF bit (SSPSTAT) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
17.4.10.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
© 2006 Microchip Technology Inc.
DS41159E-page 173
DS41159E-page 174
S
R/W
PEN
SEN
BF (SSPSTAT)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
3
4
5
Cleared in software
2
6
7
8
9
After Start condition, SEN cleared by hardware
SSPBUF written
1
D7
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
SSPBUF written with 7-bit address and R/W,
start transmit
A7
Transmit Address to Slave
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
SSPBUF is written in software
Cleared in software service routine
from SSP interrupt
2
D6
Transmitting Data or Second Half
of 10-bit Address
From slave, clear ACKSTAT bit SSPCON2
P
Cleared in software
9
ACK
ACKSTAT in
SSPCON2 = 1
FIGURE 17-21:
SEN = 0
Write SSPCON2 SEN = 1
Start condition begins
PIC18FXX8
I 2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
© 2006 Microchip Technology Inc.
© 2006 Microchip Technology Inc.
S
ACKEN
SSPOV
BF
(SSPSTAT)
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
SCL
SDA
1
A7
2
4
5
Cleared in software
3
6
A6 A5 A4 A3 A2
Transmit Address to Slave
7
A1
8
9
R/W = 1
ACK
ACK from Slave
2
3
5
6
7
8
D0
9
ACK
2
3
4
5
6
7
Cleared in software
Set SSPIF interrupt
at end of Acknowledge
sequence
Data shifted in on falling edge of CLK
1
D7 D6 D5 D4 D3 D2 D1
Cleared in
software
Set SSPIF at end
of receive
9
ACK is not sent
ACK
P
Set SSPIF interrupt
at end of Acknowledge sequence
Bus master
terminates
transfer
Set P bit
(SSPSTAT)
and SSPIF
PEN bit = 1
written here
SSPOV is set because
SSPBUF is still full
8
D0
RCEN cleared
automatically
Set ACKEN, start Acknowledge sequence
SDA = ACKDT = 1
Receiving Data from Slave
RCEN = 1, start
next receive
ACK from master
SDA = ACKDT = 0
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared in software
Set SSPIF interrupt
at end of receive
4
Cleared in software
1
D7 D6 D5 D4 D3 D2 D1
Receiving Data from Slave
RCEN cleared
automatically
Master configured as a receiver
by programming SSPCON2 (RCEN = 1)
FIGURE 17-22:
SEN = 0
Write to SSPBUF occurs here,
start XMIT
Write to SSPCON2 (SEN = 1),
begin Start Condition
Write to SSPCON2
to start Acknowledge sequence
SDA = ACKDT (SSPCON2) = 0
PIC18FXX8
I 2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
DS41159E-page 175
PIC18FXX8
17.4.12
ACKNOWLEDGE SEQUENCE
TIMING
17.4.13
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is
sampled low, the Baud Rate Generator is reloaded and
counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deasserted. When the SDA pin is
sampled high while SCL is high, the P bit
(SSPSTAT) is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 17-24).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23).
17.4.12.1
17.4.13.1
WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t
occur).
WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur).
FIGURE 17-23:
STOP CONDITION TIMING
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPCON2
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
TBRG
SDA
D0
SCL
TBRG
ACK
8
9
SSPIF
Set SSPIF at the end
of receive
Cleared in
software
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 17-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT) is set.
Write to SSPCON2
Set PEN
PEN bit (SSPCON2) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
DS41159E-page 176
© 2006 Microchip Technology Inc.
PIC18FXX8
17.4.14
SLEEP OPERATION
17.4.17
2
While in Sleep mode, the I C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
17.4.15
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag BCLIF and reset the I2C
port to its Idle state (Figure 17-25).
EFFECT OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.4.16
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I 2C bus may
be taken when the P bit (SSPSTAT) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
If a Start, Repeated Start, Stop or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted and the respective control bits in
the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if
the I2C bus is free, the user can resume communication
by asserting a Start condition.
The states where arbitration can be lost are:
•
•
•
•
•
MULTI -MASTER
COMMUNICATION, BUS COLLISION
AND BUS ARBITRATION
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can
be taken when the P bit is set in the SSPSTAT register or
the bus is Idle and the S and P bits are cleared.
FIGURE 17-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0
SDA line pulled low
by another source
SDA released
by master
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
Bus collision has occurred.
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
© 2006 Microchip Technology Inc.
DS41159E-page 177
PIC18FXX8
17.4.17.1
Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a)
SDA or SCL are sampled low at the beginning of
the Start condition (Figure 17-26).
SCL is sampled low before SDA is asserted low
(Figure 17-27).
b)
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 17-28). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0 and during this time, if the SCL pins
are sampled as ‘0’, a bus collision does not occur. At
the end of the BRG count, the SCL pin is asserted low.
Note:
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its Idle state
(Figure 17-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
FIGURE 17-26:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus collision because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module reset into Idle state.
SEN
BCLIF
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software.
DS41159E-page 178
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 17-27:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SCL = 0 before SDA = 0,
bus collision occurs. Set BCLIF.
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S
‘0’
‘0’
SSPIF
‘0’
‘0’
FIGURE 17-28:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Less than TBRG
SDA
Set SSPIF
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SCL
S
SCL pulled low after BRG
Time-out
SEN
BCLIF
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
‘0’
S
SSPIF
SDA = 0, SCL = 1,
set SSPIF
© 2006 Microchip Technology Inc.
Interrupts cleared
in software
DS41159E-page 179
PIC18FXX8
17.4.17.2
Bus Collision During a Repeated
Start Condition
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition
(Figure 17-30).
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 17-29).
If SDA is sampled high, the BRG is reloaded and begins
FIGURE 17-29:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
‘0’
S
‘0’
SSPIF
FIGURE 17-30:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
BCLIF
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
Interrupt cleared
in software
RSEN
S
‘0’
SSPIF
DS41159E-page 180
© 2006 Microchip Technology Inc.
PIC18FXX8
17.4.17.3
Bus Collision During a Stop
Condition
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 17-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 17-32).
Bus collision occurs during a Stop condition if:
a)
b)
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 17-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG
TBRG
SDA sampled
low after TBRG,
set BCLIF
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
‘0’
SSPIF
‘0’
FIGURE 17-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
Assert SDA
SCL
SCL goes low before SDA goes high,
set BCLIF
PEN
BCLIF
P
‘0’
SSPIF
‘0’
© 2006 Microchip Technology Inc.
DS41159E-page 181
PIC18FXX8
NOTES:
DS41159E-page 182
© 2006 Microchip Technology Inc.
PIC18FXX8
18.0
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex).
The SPEN (RCSTA register) and the TRISC bits
have to be set and the TRISC bit must be cleared
in order to configure pins RC6/TX/CK and RC7/RX/DT
as the Universal Synchronous Asynchronous Receiver
Transmitter.
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the three serial
I/O modules incorporated into PIC18FXX8 devices.
(USART is also known as a Serial Communications
Interface or SCI.) The USART can be configured as a
full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals
and personal computers, or it can be configured as a
half-duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
REGISTER 18-1:
Register 18-1 shows the Transmit Status and Control
register (TXSTA) and Register 18-2 shows the Receive
Status and Control register (RCSTA).
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
bit 7
bit 7
bit 6
bit 5
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note:
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
SREN/CREN overrides TXEN in Sync mode.
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
Unimplemented: Read as ‘0’
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Legend:
R = Readable bit
-n = Value at POR
© 2006 Microchip Technology Inc.
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DS41159E-page 183
PIC18FXX8
REGISTER 18-2:
RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive (this bit is cleared after reception is complete)
Synchronous mode – Slave:
Unused in this mode.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and load of the receive buffer when RSR
is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
bit 2
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: 9th bit of Received Data
Can be address/data bit or a parity bit.
Legend:
DS41159E-page 184
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
18.1
USART Baud Rate Generator
(BRG)
Example 18-1 shows the calculation of the baud rate
error for the following conditions:
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free running, 8-bit timer. In
Asynchronous mode, bit BRGH (TXSTA register) also
controls the baud rate. In Synchronous mode, bit
BRGH is ignored. Table 18-1 shows the formula for
computation of the baud rate for different USART
modes which only apply in Master mode (internal
clock).
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 18-1. From this, the error in
baud rate can be determined.
18.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
EXAMPLE 18-1:
CALCULATING BAUD RATE ERROR
Desired Baud Rate
= FOSC/(64 (X + 1))
Solving for X:
X
X
X
= ((FOSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate
= 16000000/(64 (25 + 1))
= 9615
Error
= (Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
= (9615 – 9600)/9600
= 0.16%
TABLE 18-1:
BAUD RATE FORMULA
SYNC
0
1
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
(Asynchronous) Baud Rate = FOSC/(64 (X + 1))
(Synchronous) Baud Rate = FOSC/(4 (X + 1))
Baud Rate = FOSC/(16 (X + 1))
NA
Legend: X = value in SPBRG (0 to 255)
TABLE 18-2:
Name
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000u
0000 0000
0000 0000
SPBRG
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
© 2006 Microchip Technology Inc.
DS41159E-page 185
PIC18FXX8
TABLE 18-3:
BAUD
RATE
(Kbps)
BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 40 MHz
SPBRG
value
(decimal)
33 MHz
SPBRG
value
(decimal)
25 MHz
SPBRG
value
(decimal)
20 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
KBAUD
%
ERROR
KBAUD
%
ERROR
KBAUD
%
ERROR
0.3
NA
-
-
NA
-
-
NA
-
-
NA
-
-
1.2
NA
-
-
NA
-
-
NA
-
-
NA
-
-
2.4
NA
-
-
NA
-
-
NA
-
-
NA
-
-
9.6
NA
-
-
NA
-
-
NA
-
-
NA
-
-
19.2
NA
-
-
NA
-
-
NA
-
-
NA
-
-
76.8
76.92
+0.16
129
77.10
+0.39
106
77.16
+0.47
80
76.92
+0.16
64
96
96.15
+0.16
103
95.93
-0.07
85
96.15
+0.16
64
96.15
+0.16
51
300
303.03
+1.01
32
294.64
-1.79
27
297.62
-0.79
20
294.12
-1.96
16
500
500
0
19
485.30
-2.94
16
480.77
-3.85
12
500
0
9
HIGH
10000
-
0
8250
-
0
6250
-
0
5000
-
0
LOW
39.06
-
255
32.23
-
255
24.41
-
255
19.53
-
255
FOSC = 16 MHz
SPBRG
value
(decimal)
10 MHz
SPBRG
value
(decimal)
7.15909 MHz
SPBRG
value
(decimal)
5.0688 MHz
SPBRG
value
(decimal)
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
KBAUD
%
ERROR
KBAUD
%
ERROR
KBAUD
%
ERROR
0.3
NA
-
-
NA
-
-
NA
-
-
NA
-
-
1.2
NA
-
-
NA
-
-
NA
-
-
NA
-
-
2.4
NA
-
-
NA
-
-
NA
-
-
NA
-
-
9.6
NA
-
-
NA
-
-
9.62
+0.23
185
9.60
0
131
19.2
19.23
+0.16
207
19.23
+0.16
129
19.24
+0.23
92
19.20
0
65
76.8
76.92
+0.16
51
75.76
-1.36
32
77.82
+1.32
22
74.54
-2.94
16
96
95.24
-0.79
41
96.15
+0.16
25
94.20
-1.88
18
97.48
+1.54
12
300
307.70
+2.56
12
312.50
+4.17
7
298.35
-0.57
5
316.80
+5.60
3
500
500
0
7
500
0
4
447.44
-10.51
3
422.40
-15.52
2
HIGH
4000
-
0
2500
-
0
1789.80
-
0
1267.20
-
0
LOW
15.63
-
255
9.77
-
255
6.99
-
255
4.95
-
255
FOSC = 4 MHz
SPBRG
value
(decimal)
3.579545 MHz
SPBRG
value
(decimal)
1 MHz
SPBRG
value
(decimal)
32.768 kHz
SPBRG
value
(decimal)
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
KBAUD
%
ERROR
KBAUD
%
ERROR
KBAUD
%
ERROR
0.3
NA
-
-
NA
-
-
NA
-
-
0.30
+1.14
1.2
NA
-
-
NA
-
-
1.20
+0.16
207
1.17
-2.48
6
2.4
NA
-
-
NA
-
-
2.40
+0.16
103
2.73
+13.78
2
0
26
9.6
9.62
+0.16
103
9.62
+0.23
92
9.62
+0.16
25
8.20
-14.67
19.2
19.23
+0.16
51
19.04
-0.83
46
19.23
+0.16
12
NA
-
-
76.8
76.92
+0.16
12
74.57
-2.90
11
83.33
+8.51
2
NA
-
-
96
1000
+4.17
9
99.43
+3.57
8
83.33
-13.19
2
NA
-
300
333.33
+11.11
2
298.30
-0.57
2
250
-16.67
0
NA
-
-
500
500
0
1
447.44
-10.51
1
NA
-
-
NA
-
-
HIGH
1000
-
0
894.89
-
0
250
-
0
8.20
-
0
LOW
3.91
-
255
3.50
-
255
0.98
-
255
0.03
-
255
DS41159E-page 186
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 18-4:
BAUD
RATE
(Kbps)
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 40 MHz
SPBRG
value
(decimal)
33 MHz
SPBRG
value
(decimal)
25 MHz
SPBRG
value
(decimal)
20 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
KBAUD
%
ERROR
KBAUD
%
ERROR
KBAUD
%
ERROR
0.3
NA
-
-
NA
-
-
NA
-
-
NA
-
1.2
NA
-
-
NA
-
-
NA
-
-
NA
-
-
2.4
NA
-
-
2.40
-0.07
214
2.40
-0.15
162
2.40
+0.16
129
-
9.6
9.62
+0.16
64
9.55
-0.54
53
9.53
-0.76
40
9.47
-1.36
32
19.2
18.94
-1.36
32
19.10
-0.54
26
19.53
+1.73
19
19.53
+1.73
15
76.8
78.13
+1.73
7
73.66
-4.09
6
78.13
+1.73
4
78.13
+1.73
3
96
89.29
-6.99
6
103.13
+7.42
4
97.66
+1.73
3
104.17
+8.51
2
300
312.50
+4.17
1
257.81
-14.06
1
NA
-
-
312.50
+4.17
0
500
625
+25.00
0
NA
-
-
NA
-
-
NA
-
-
HIGH
625
-
0
515.63
-
0
390.63
-
0
312.50
-
0
LOW
2.44
-
255
2.01
-
255
1.53
-
255
1.22
-
255
FOSC = 16 MHz
SPBRG
value
(decimal)
10 MHz
SPBRG
value
(decimal)
7.15909 MHz
SPBRG
value
(decimal)
5.0688 MHz
SPBRG
value
(decimal)
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
KBAUD
%
ERROR
KBAUD
%
ERROR
0.3
NA
-
-
NA
-
-
NA
-
-
NA
-
-
1.2
1.20
+0.16
207
1.20
+0.16
129
1.20
+0.23
92
1.20
0
65
KBAUD
%
ERROR
2.4
2.40
+0.16
103
2.40
+0.16
64
2.38
-0.83
46
2.40
0
32
9.6
9.62
+0.16
25
9.77
+1.73
15
9.32
-2.90
11
9.90
+3.13
7
19.2
19.23
+0.16
12
19.53
+1.73
7
18.64
-2.90
5
19.80
+3.13
3
76.8
83.33
+8.51
2
78.13
+1.73
1
111.86
+45.65
0
79.20
+3.13
0
-
96
83.33
-13.19
2
78.13
-18.62
1
NA
-
-
NA
-
300
250
-16.67
0
156.25
-47.92
0
NA
-
-
NA
-
-
500
NA
-
-
NA
-
-
NA
-
-
NA
-
-
HIGH
250
-
0
156.25
-
0
111.86
-
0
79.20
-
0
LOW
0.98
-
255
0.61
-
255
0.44
-
255
0.31
-
255
FOSC = 4 MHz
SPBRG
value
(decimal)
3.579545 MHz
SPBRG
value
(decimal)
1 MHz
SPBRG
value
(decimal)
32.768 kHz
SPBRG
value
(decimal)
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
KBAUD
%
ERROR
KBAUD
%
ERROR
KBAUD
%
ERROR
0.3
0.30
-0.16
207
0.30
+0.23
185
0.30
+0.16
51
0.26
-14.67
1
1.2
1.20
+1.67
51
1.19
-0.83
46
1.20
+0.16
12
NA
-
-
2.4
2.40
+1.67
25
2.43
+1.32
22
2.23
-6.99
6
NA
-
-
9.6
8.93
-6.99
6
9.32
-2.90
5
7.81
-18.62
1
NA
-
-
19.2
20.83
+8.51
2
18.64
-2.90
2
15.63
-18.62
0
NA
-
-
76.8
62.50
-18.62
0
55.93
-27.17
0
NA
-
-
NA
-
-
96
NA
-
-
NA
-
-
NA
-
-
NA
-
-
300
NA
-
-
NA
-
-
NA
-
-
NA
-
-
500
NA
-
-
NA
-
-
NA
-
-
NA
-
-
HIGH
62.50
-
0
55.93
-
0
15.63
-
0
0.51
-
0
LOW
0.24
-
255
0.22
-
255
0.06
-
255
0.002
-
255
© 2006 Microchip Technology Inc.
DS41159E-page 187
PIC18FXX8
TABLE 18-5:
BAUD
RATE
(Kbps)
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 40 MHz
KBAUD
%
ERROR
0.3
NA
-
1.2
NA
-
2.4
NA
9.6
SPBRG
value
(decimal)
33 MHz
SPBRG
value
(decimal)
25 MHz
-
NA
-
-
NA
-
-
-
NA
9.60
-0.07
214
129
19.28
+0.39
32
76.39
-0.54
25
98.21
+2.31
20 MHz
SPBRG
value
(decimal)
KBAUD
-
NA
-
-
NA
-
-
-
NA
NA
-
-
19.2
19.23
+0.16
76.8
75.76
-1.36
96
96.15
+0.16
300
312.50
+4.17
7
294.64
-1.79
6
312.50
+4.17
4
500
500
0
4
515.63
+3.13
3
520.83
+4.17
2
HIGH
2500
-
0
2062.50
-
0
1562.50
-
0
1250
-
0
LOW
9.77
-
255
8,06
-
255
6.10
-
255
4.88
-
255
FOSC = 16 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
%
ERROR
SPBRG
value
(decimal)
10 MHz
KBAUD
%
ERROR
-
NA
-
-
-
NA
-
-
-
-
NA
-
-
9.59
-0.15
162
9.62
+0.16
129
106
19.30
+0.47
80
19.23
+0.16
64
26
78.13
+1.73
19
78.13
+1.73
15
20
97.66
+1.73
15
96.15
+0.16
12
312.50
+4.17
3
416.67
-16.67
2
SPBRG
value
(decimal)
7.15909 MHz
SPBRG
value
(decimal)
5.0688 MHz
SPBRG
value
(decimal)
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
KBAUD
%
ERROR
KBAUD
%
ERROR
KBAUD
%
ERROR
0.3
NA
-
-
NA
-
-
NA
-
-
NA
-
1.2
NA
-
-
NA
-
-
NA
-
-
NA
-
-
2.4
NA
-
-
NA
-
-
2.41
+0.23
185
2.40
0
131
-
9.6
9.62
+0.16
103
9.62
+0.16
64
9.52
-0.83
46
9.60
0
32
19.2
19.23
+0.16
51
18.94
-1.36
32
19.45
+1.32
22
18.64
-2.94
16
76.8
76.92
+0.16
12
78.13
+1.73
7
74.57
-2.90
5
79.20
+3.13
3
96
100
+4.17
9
89.29
-6.99
6
89.49
-6.78
4
105.60
+10.00
2
300
333.33
+11.11
2
312.50
+4.17
1
447.44
+49.15
0
316.80
+5.60
0
500
500
0
1
625
+25.00
0
447.44
-10.51
0
NA
-
-
HIGH
1000
-
0
625
-
0
447.44
-
0
316.80
-
0
LOW
3.91
-
255
2.44
-
255
1.75
-
255
1.24
-
255
FOSC = 4 MHz
SPBRG
value
(decimal)
3.579545 MHz
SPBRG
value
(decimal)
1 MHz
SPBRG
value
(decimal)
32.768 kHz
SPBRG
value
(decimal)
BAUD
RATE
(Kbps)
KBAUD
%
ERROR
KBAUD
%
ERROR
KBAUD
%
ERROR
0.3
NA
-
-
NA
-
-
0.30
+0.16
207
0.29
-2.48
6
1.2
1.20
+0.16
207
1.20
+0.23
185
1.20
+0.16
51
1.02
-14.67
1
2.4
2.40
+0.16
103
2.41
+0.23
92
2.40
+0.16
25
2.05
-14.67
0
9.6
9.62
+0.16
25
9.73
+1.32
22
8.93
-6.99
6
NA
-
-
19.2
19.23
+0.16
12
18.64
-2.90
11
20.83
+8.51
2
NA
-
-
76.8
NA
-
-
74.57
-2.90
2
62.50
-18.62
0
NA
-
-
96
NA
-
-
111.86
+16.52
1
NA
-
-
NA
-
-
300
NA
-
-
223.72
-25.43
0
NA
-
-
NA
-
-
KBAUD
%
ERROR
500
NA
-
-
NA
-
-
NA
-
-
NA
-
-
HIGH
250
-
0
55.93
-
0
62.50
-
0
2.05
-
0
LOW
0.98
-
255
0.22
-
255
0.24
-
255
0.008
-
255
DS41159E-page 188
© 2006 Microchip Technology Inc.
PIC18FXX8
18.2
USART Asynchronous Mode
interrupt can be enabled/disabled by setting/clearing
enable bit TXIE (PIE1 register). Flag bit TXIF will be set
regardless of the state of enable bit TXIE and cannot be
cleared in software. It will reset only when new data is
loaded into the TXREG register. While flag bit, TXIF,
indicated the status of the TXREG register, another bit,
TRMT (TXSTA register), shows the status of the TSR
register. Status bit TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit, so the user has to poll this bit in order to
determine if the TSR register is empty.
In this mode, the USART uses standard Non-Returnto-Zero (NRZ) format (one Start bit, eight or nine data
bits and one Stop bit). The most common data format
is 8 bits. An on-chip dedicated 8-bit Baud Rate
Generator can be used to derive standard baud rate
frequencies from the oscillator. The USART transmits
and receives the LSb first. The USART’s transmitter
and receiver are functionally independent but use the
same data format and baud rate. The Baud Rate
Generator produces a clock, either x16 or x64 of the bit
shift rate, depending on the BRGH bit (TXSTA register). Parity is not supported by the hardware but can be
implemented in software (and stored as the ninth data
bit). Asynchronous mode is stopped during Sleep.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.
Asynchronous mode is selected by clearing the SYNC
bit (TXSTA register).
Steps to follow when setting up an Asynchronous
Transmission:
The USART Asynchronous module consists of the
following important elements:
1.
•
•
•
•
2.
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver.
18.2.1
3.
4.
USART ASYNCHRONOUS
TRANSMITTER
5.
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The TSR register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG register is
empty and flag bit TXIF (PIR1 register) is set. This
FIGURE 18-1:
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 18.1 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts
transmission).
6.
7.
Note:
TXIF is not cleared immediately upon
loading data into the transmit buffer
TXREG. The flag bit becomes valid in the
second instruction cycle following the load
instruction.
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG register
TXIE
8
MSb
LSb
• • •
(8)
Pin Buffer
and Control
0
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
TX9
Baud Rate Generator
© 2006 Microchip Technology Inc.
TX9D
DS41159E-page 189
PIC18FXX8
FIGURE 18-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 18-3:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Interrupt Reg. Flag)
Word 2
Start bit
TRMT bit
(Transmit Shift
Reg. Empty Flag)
bit 0
bit 1
Word 1
bit 7/8
Stop bit
Start bit
bit 0
Word 2
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 18-6:
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
Bit 3
RBIE
Bit 2
Bit 1
TMR0IF INT0IF
Value on
all other
Resets
Bit 0
Value on
POR, BOR
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x 0000 000u
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
RCSTA
TXREG
TXSTA
SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
USART Transmit Register
CSRC
TX9
TXEN
0000 0000 0000 0000
SPBRG
Baud Rate Generator Register
Legend:
Note 1:
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
DS41159E-page 190
0000 0000 0000 0000
© 2006 Microchip Technology Inc.
PIC18FXX8
18.2.2
USART ASYNCHRONOUS
RECEIVER
18.2.3
The receiver block diagram is shown in Figure 18-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high-speed shifter, operating at x16 times the
baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would
typically be used in RS-232 systems.
This mode would typically be used in RS-485 systems.
Steps to follow when setting up an Asynchronous
Reception with Address Detect Enable:
1.
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is required,
set the BRGH bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
7. The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 18.1 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
Enable the reception by setting bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
FIGURE 18-4:
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
÷ 64
or
÷ 16
Baud Rate Generator
RSR Register
MSb
Stop
(8)
7
• • •
1
LSb
0
Start
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
Interrupt
RCIF
Data Bus
RCIE
Note:
I/O pins have diode protection to VDD and VSS.
© 2006 Microchip Technology Inc.
DS41159E-page 191
PIC18FXX8
FIGURE 18-5:
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX (pin)
bit 1
bit 7/8 Stop
bit
Rcv Shift
Reg
Rcv Buffer Reg
Start
bit
bit 0
Start
bit
Stop
bit
bit 7/8
Stop
bit
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
bit 7/8
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 18-7:
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/GIEH
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE
0000 0000
0000 0000
IPR1
(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP TMR2IP TMR1IP
1111 1111
1111 1111
RX9
SREN
CREN
ADDEN
0000 000x
0000 000u
RCSTA
RCREG
TXSTA
SPBRG
Legend:
Note 1:
PSPIP
SPEN
PEIE/GIEL TMR0IE
Bit 4
FERR
OERR
RX9D
USART Receive Register
CSRC
TX9
TXEN
Baud Rate Generator Register
SYNC
—
BRGH
TRMT
TX9D
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
DS41159E-page 192
© 2006 Microchip Technology Inc.
PIC18FXX8
18.3
USART Synchronous
Master Mode
software. It will reset only when new data is loaded into
the TXREG register. While flag bit, TXIF, indicates the
status of the TXREG register, another bit, TRMT
(TXSTA register), shows the status of the TSR register.
TRMT is a read-only bit which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR
register is empty. The TSR is not mapped in data
memory, so it is not available to the user.
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA register).
In addition, enable bit SPEN (RCSTA register) is set in
order to configure the RC6/TX/CK and RC7/RX/DT I/O
pins to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA register).
18.3.1
Steps to follow when setting up a Synchronous Master
Transmission:
1.
USART SYNCHRONOUS MASTER
TRANSMISSION
2.
3.
4.
5.
6.
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG is empty and interrupt
bit TXIF (PIR1 register) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1 register). Flag bit TXIF will be set regardless of
the state of enable bit TXIE and cannot be cleared in
TABLE 18-8:
Initialize the SPBRG register for the appropriate
baud rate (Section 18.1 “USART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
7.
Note:
TXIF is not cleared immediately upon
loading data into the transmit buffer
TXREG. The flag bit becomes valid in the
second instruction cycle following the load
instruction.
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
PIR1
PSPIF
(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111
1111 1111
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000u
0000 0000
0000 0000
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
RCSTA
TXREG
TXSTA
SPBRG
Legend:
Note 1:
USART Transmit Register
CSRC
TX9
Baud Rate Generator Register
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
© 2006 Microchip Technology Inc.
DS41159E-page 193
PIC18FXX8
FIGURE 18-6:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT
pin
bit 0
bit 1
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
RC6/TX/CK
pin
Write to
TXREG Reg
Write Word 1
TXIF bit
(Interrupt Flag)
Write Word 2
TRMT bit TRMT
TXEN bit
‘1’
‘1’
Note: Sync Master mode; SPBRG = 0; continuous transmission of two 8-bit words.
FIGURE 18-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit 0
bit 1
bit 2
bit 6
bit 7
RC6/TX/CK pin
Write to
TXREG Reg
TXIF bit
TRMT bit
TXEN bit
DS41159E-page 194
© 2006 Microchip Technology Inc.
PIC18FXX8
18.3.2
USART SYNCHRONOUS MASTER
RECEPTION
Steps to follow when setting up a Synchronous Master
Reception:
1.
Initialize the SPBRG register for the appropriate
baud rate (Section 18.1 “USART Baud Rate
Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
Once Synchronous Master mode is selected, reception
is enabled by setting either enable bit SREN (RCSTA
register) or enable bit CREN (RCSTA register). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
TABLE 18-9:
Name
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
0000 000u
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111
1111 1111
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000u
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
RCSTA
RCREG
USART Receive Register
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
SPBRG
Baud Rate Generator Register
Legend:
Note 1:
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
FIGURE 18-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
© 2006 Microchip Technology Inc.
DS41159E-page 195
PIC18FXX8
18.4
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in that the shift clock is supplied externally at the RC6/
TX/CK pin (instead of being supplied internally in
Master mode). This allows the device to transfer or
receive data while in Sleep mode. Slave mode is
entered by clearing bit CSRC (TXSTA register).
18.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode and bit SREN, which is a “don’t care” in Slave
mode.
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
Steps to follow when setting up a Synchronous Slave
Reception:
a)
1.
18.4.1
b)
c)
d)
e)
USART SYNCHRONOUS SLAVE
TRANSMIT
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will be set.
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
Steps to follow when setting up a Synchronous Slave
Transmission:
1.
2.
3.
4.
5.
6.
7.
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
DS41159E-page 196
2.
3.
4.
5.
6.
7.
8.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is
complete. An interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/GIEH
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111
1111 1111
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000u
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
RCSTA
TXREG
TXSTA
SPBRG
Legend:
Note 1:
PEIE/GIEL TMR0IE
Bit 4
USART Transmit Register
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
Baud Rate Generator Register
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111 1111 1111
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x 0000 000u
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
RCSTA
RCREG
TXSTA
SPBRG
Legend:
Note 1:
USART Receive Register
CSRC
TX9
0000 0000 0000 0000
Baud Rate Generator Register
0000 0000 0000 0000
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
© 2006 Microchip Technology Inc.
DS41159E-page 197
PIC18FXX8
NOTES:
DS41159E-page 198
© 2006 Microchip Technology Inc.
PIC18FXX8
19.0
CAN MODULE
19.1
Overview
The Controller Area Network (CAN) module is a serial
interface, useful for communicating with other peripherals or microcontroller devices. This interface/protocol
was designed to allow communications within noisy
environments.
The CAN module is a communication controller,
implementing the CAN 2.0 A/B protocol as defined in
the BOSCH specification. The module will support
CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B
Active versions of the protocol. The module implementation is a full CAN system. The CAN specification is
not covered within this data sheet. The reader may
refer to the BOSCH CAN specification for further
details.
The module features are as follows:
• Complies with ISO CAN Conformance Test
• Implementation of the CAN protocol CAN 1.2,
CAN 2.0A and CAN 2.0B
• Standard and extended data frames
• 0-8 bytes data length
• Programmable bit rate up to 1 Mbit/sec
• Support for remote frames
• Double-buffered receiver with two prioritized
received message storage buffers
• 6 full (standard/extended identifier) acceptance
filters, 2 associated with the high priority receive
buffer and 4 associated with the low priority
receive buffer
• 2 full acceptance filter masks, one each
associated with the high and low priority receive
buffers
• Three transmit buffers with application specified
prioritization and abort capability
• Programmable wake-up functionality with
integrated low-pass filter
• Programmable Loopback mode supports self-test
operation
• Signaling via interrupt capabilities for all CAN
receiver and transmitter error states
• Programmable clock source
• Programmable link to timer module for
time-stamping and network synchronization
• Low-power Sleep mode
© 2006 Microchip Technology Inc.
19.1.1
OVERVIEW OF THE MODULE
The CAN bus module consists of a protocol engine and
message buffering and control. The CAN protocol
engine handles all functions for receiving and transmitting messages on the CAN bus. Messages are
transmitted by first loading the appropriate data
registers. Status and errors can be checked by reading
the appropriate registers. Any message detected on
the CAN bus is checked for errors and then matched
against filters to see if it should be received and stored
in one of the 2 receive registers.
The CAN module supports the following frame types:
•
•
•
•
•
•
Standard Data Frame
Extended Data Frame
Remote Frame
Error Frame
Overload Frame Reception
Interframe Space
CAN module uses RB3/CANRX and RB2/CANTX/INT2
pins to interface with CAN bus. In order to configure
CANRX and CANTX as CAN interface:
• bit TRISB must be set;
• bit TRISB must be cleared.
19.1.2
TRANSMIT/RECEIVE BUFFERS
The PIC18FXX8 has three transmit and two receive
buffers, two acceptance masks (one for each receive
buffer) and a total of six acceptance filters. Figure 19-1
is a block diagram of these buffers and their connection
to the protocol engine.
DS41159E-page 199
PIC18FXX8
FIGURE 19-1:
CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM
BUFFERS
Accept
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
Message
Request
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
Acceptance Mask
RXM1
Acceptance Filter
RXM2
TXB0
MESSAGE
Accept
TXB1
MESSAGE
Acceptance Mask
RXM0
Acceptance Filter
RXF3
Acceptance Filter
RXF0
Acceptance Filter
RXF4
Acceptance Filter
RXF1
Acceptance Filter
RXF5
RXB0
RXB1
TXB2
MESSAGE
Message
Queue
Control
Identifier
Transmit Byte Sequencer
Data and
Identifier
Data and
Identifier
Identifier
Message Assembly Buffer
PROTOCOL
ENGINE
Receive Shift
Transmit Shift
RXERRCNT
Comparator
CRC Register
Bus-Off
Bit Timing
Generator
Transmit
Logic
Err-Pas
Protocol
FSM
Bit Timing
Logic
Transmit
Error
Counter
TX
DS41159E-page 200
Receive
Error
Counter
TXERRCNT
RX
© 2006 Microchip Technology Inc.
PIC18FXX8
19.2
Note:
19.2.1
CAN Module Registers
Not all CAN registers are available in the
Access Bank.
The registers described in this section control the
overall operation of the CAN module and show its
operational status.
There are many control and data registers associated
with the CAN module. For convenience, their
descriptions have been grouped into the following
sections:
•
•
•
•
•
•
CAN CONTROL AND STATUS
REGISTERS
Control and Status Registers
Transmit Buffer Registers (Data and Control)
Receive Buffer Registers (Data and Control)
Baud Rate Control Registers
I/O Control Register
Interrupt Status and Control Registers
REGISTER 19-1:
CANCON: CAN CONTROL REGISTER
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
REQOP2
REQOP1
REQOP0
ABAT
WIN2
WIN1
WIN0
—
bit 7
bit 0
bit 7-5
REQOP2:REQOP0: Request CAN Operation Mode bits
1xx = Request Configuration mode
011 = Request Listen Only mode
010 = Request Loopback mode
001 = Request Disable mode
000 = Request Normal mode
bit 4
ABAT: Abort All Pending Transmissions bit
1 = Abort all pending transmissions (in all transmit buffers)
0 = Transmissions proceeding as normal
bit 3-1
WIN2:WIN0: Window Address bits
This selects which of the CAN buffers to switch into the Access Bank area. This allows access
to the buffer registers from any data memory bank. After a frame has caused an interrupt, the
ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer. See
Example 19-1 for code example.
111 = Receive Buffer 0
110 = Receive Buffer 0
101 = Receive Buffer 1
100 = Transmit Buffer 0
011 = Transmit Buffer 1
010 = Transmit Buffer 2
001 = Receive Buffer 0
000 = Receive Buffer 0
bit 0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 201
PIC18FXX8
REGISTER 19-2:
CANSTAT: CAN STATUS REGISTER
R-1
R-0
R-0
OPMODE2 OPMODE1 OPMODE0
U-0
R-0
R-0
R-0
U-0
—
ICODE2
ICODE1
ICODE0
—
bit 7
bit 7-5
bit 0
OPMODE2:OPMODE0: Operation Mode Status bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Configuration mode
011 = Listen Only mode
010 = Loopback mode
001 = Disable mode
000 = Normal mode
Note:
Before the device goes into Sleep mode, select Disable mode.
bit 4
Unimplemented: Read as ‘0’
bit 3-1
ICODE2:ICODE0: Interrupt Code bits
When an interrupt occurs, a prioritized coded interrupt value will be present in the
ICODE2:ICODE0 bits. These codes indicate the source of the interrupt. The ICODE2:ICODE0
bits can be copied to the WIN2:WIN0 bits to select the correct buffer to map into the Access
Bank area. See Example 19-1 for code example.
111 = Wake-up on interrupt
110 = RXB0 interrupt
101 = RXB1 interrupt
100 = TXB0 interrupt
011 = TXB1 interrupt
010 = TXB2 interrupt
001 = Error interrupt
000 = No interrupt
bit 0
Unimplemented: Read as ‘0’
Legend:
DS41159E-page 202
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
EXAMPLE 19-1:
WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS
TX/RX BUFFERS
; Save application required context.
; Poll interrupt flags and determine source of interrupt
; This was found to be CAN interrupt
; TempCANCON and TempCANSTAT are variables defined in Access Bank low
MOVFF
CANCON, TempCANCON
; Save CANCON.WIN bits
; This is required to prevent CANCON
; from corrupting CAN buffer access
; in-progress while this interrupt
; occurred
MOVFF
CANSTAT, TempCANSTAT
;
;
;
;
;
Save CANSTAT register
This is required to make sure that
we use same CANSTAT value rather
than one changed by another CAN
interrupt.
MOVF
ANDLW
ADDWF
TempCANSTAT, W
b’00001110’
PCL, F
; Retrieve ICODE bits
BRA
BRA
BRA
BRA
BRA
BRA
BRA
NoInterrupt
ErrorInterrupt
TXB2Interrupt
TXB1Interrupt
TXB0Interrupt
RXB1Interrupt
RXB0Interrupt
; Perform computed GOTO
; to corresponding interrupt cause
;
;
;
;
;
;
;
;
000
001
010
011
100
101
110
111
=
=
=
=
=
=
=
=
No interrupt
Error interrupt
TXB2 interrupt
TXB1 interrupt
TXB0 interrupt
RXB1 interrupt
RXB0 interrupt
Wake-up on interrupt
WakeupInterrupt
BCF
PIR3, WAKIF
; Clear the interrupt flag
;
; User code to handle wake-up procedure
;
;
; Continue checking for other interrupt source or return from here
…
NoInterrupt
…
; PC should never vector here. User may
; place a trap such as infinite loop or pin/port
; indication to catch this error.
ErrorInterrupt
BCF
PIR3, ERRIF
…
RETFIE
; Clear the interrupt flag
; Handle error.
TXB2Interrupt
BCF
PIR3, TXB2IF
GOTO
AccessBuffer
; Clear the interrupt flag
TXB1Interrupt
BCF
PIR3, TXB1IF
GOTO
AccessBuffer
; Clear the interrupt flag
TXB0Interrupt
BCF
PIR3, TXB0IF
GOTO
AccessBuffer
; Clear the interrupt flag
RXB1Interrupt
BCF
PIR3, RXB1IF
GOTO
Accessbuffer
; Clear the interrupt flag
© 2006 Microchip Technology Inc.
DS41159E-page 203
PIC18FXX8
EXAMPLE 19-1:
WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS
TX/RX BUFFERS (CONTINUED)
RXB0Interrupt
BCF
PIR3, RXB0IF
GOTO
AccessBuffer
; Clear the interrupt flag
AccessBuffer
; This is either TX or RX interrupt
; Copy CANCON.ICODE bits to CANSTAT.WIN bits
MOVF
CANCON, W
; Clear CANCON.WIN bits before copying
; new ones.
ANDLW
b’11110001’
; Use previously saved CANCON value to
; make sure same value.
MOVWF
CANCON
; Copy masked value back to TempCANCON
MOVF
ANDLW
TempCANSTAT, W
b’00001110’
; Retrieve ICODE bits
; Use previously saved CANSTAT value
; to make sure same value.
IORWF
CANCON
; Copy ICODE bits to WIN bits.
; Copy the result to actual CANCON
; Access current buffer…
; User code
; Restore CANCON.WIN bits
MOVF
CANCON, W
ANDLW
b’11110001’
IORWF
TempCANCON, W
MOVWF
; Preserve current non WIN bits
; Restore original WIN bits
CANCON
; Do not need to restore CANSTAT - it is read-only register.
; Return from interrupt or check for another module interrupt source
DS41159E-page 204
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-3:
COMSTAT: COMMUNICATION STATUS REGISTER
R/C-0
R/C-0
RXB0OVFL RXB1OVFL
R-0
R-0
R-0
TXBO
TXBP
RXBP
R-0
R-0
TXWARN RXWARN
bit 7
R-0
EWARN
bit 0
bit 7
RXB0OVFL: Receive Buffer 0 Overflow bit
1 = Receive Buffer 0 overflowed
0 = Receive Buffer 0 has not overflowed
bit 6
RXB1OVFL: Receive Buffer 1 Overflow bit
1 = Receive Buffer 1 overflowed
0 = Receive Buffer 1 has not overflowed
bit 5
TXBO: Transmitter Bus-Off bit
1 = Transmit Error Counter > 255
0 = Transmit Error Counter ≤ 255
bit 4
TXBP: Transmitter Bus Passive bit
1 = Transmission Error Counter > 127
0 = Transmission Error Counter ≤ 127
bit 3
RXBP: Receiver Bus Passive bit
1 = Receive Error Counter > 127
0 = Receive Error Counter ≤ 127
bit 2
TXWARN: Transmitter Warning bit
1 = 127 ≥ Transmit Error Counter > 95
0 = Transmit Error Counter ≤ 95
bit 1
RXWARN: Receiver Warning bit
1 = 127 ≥ Receive Error Counter > 95
0 = Receive Error Counter ≤ 95
bit 0
EWARN: Error Warning bit
This bit is a flag of the RXWARN and TXWARN bits.
1 = The RXWARN or the TXWARN bits are set
0 = Neither the RXWARN or the TXWARN bits are set
Legend:
R = Readable bit
W = Writable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 205
PIC18FXX8
19.2.2
CAN TRANSMIT BUFFER
REGISTERS
This section describes the CAN Transmit Buffer
registers and their associated control registers.
REGISTER 19-4:
TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS
U-0
R-0
R-0
R-0
R/W-0
U-0
R/W-0
R/W-0
—
TXABT
TXLARB
TXERR
TXREQ
—
TXPRI1
TXPRI0
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
TXABT: Transmission Aborted Status bit
1 = Message was aborted
0 = Message was not aborted
bit 5
TXLARB: Transmission Lost Arbitration Status bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 4
TXERR: Transmission Error Detected Status bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3
TXREQ: Transmit Request Status bit
1 = Requests sending a message. Clears the TXABT, TXLARB and TXERR bits.
0 = Automatically cleared when the message is successfully sent
Note:
Clearing this bit in software while the bit is set will request a message abort.
bit 2
Unimplemented: Read as ‘0’
bit 1-0
TXPRI1:TXPRI0: Transmit Priority bits
11 = Priority Level 3 (highest priority)
10 = Priority Level 2
01 = Priority Level 1
00 = Priority Level 0 (lowest priority)
Note:
These bits set the order in which the Transmit Buffer will be transferred. They do
not alter the CAN message identifier.
Legend:
DS41159E-page 206
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-5:
TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER,
HIGH BYTE REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 7
bit 7-0
bit 0
SID10:SID3: Standard Identifier bits if EXIDE = 0 (TXBnSID Register) or
Extended Identifier bits EID28:EID21 if EXIDE = 1
Legend:
REGISTER 19-6:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
TXBnSIDL: TRANSMIT BUFFER n STANDARD IDENTIFIER,
LOW BYTE REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
bit 7
bit 0
bit 7-5
SID2:SID0: Standard Identifier bits if EXIDE = 0 or
Extended Identifier bits EID20:EID18 if EXIDE = 1
bit 4
Unimplemented: Read as ‘0’
bit 3
EXIDE: Extended Identifier enable bit
1 = Message will transmit extended ID, SID10:SID0 becomes EID28:EID18
0 = Message will transmit standard ID, EID17:EID0 are ignored
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID17:EID16: Extended Identifier bits
Legend:
REGISTER 19-7:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
TXBnEIDH: TRANSMIT BUFFER n EXTENDED IDENTIFIER,
HIGH BYTE REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
bit 7
bit 7-0
bit 0
EID15:EID8: Extended Identifier bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 207
PIC18FXX8
REGISTER 19-8:
TXBnEIDL: TRANSMIT BUFFER n EXTENDED IDENTIFIER,
LOW BYTE REGISTERS
R/W-x
EID7
bit 7
bit 7-0
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 0
EID7:EID0: Extended Identifier bits
Legend:
REGISTER 19-9:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
TXBnDm: TRANSMIT BUFFER n DATA FIELD BYTE m REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0
bit 7
bit 0
bit 7-0
TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 < m < 8)
Each Transmit Buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers:
TXB0D0 to TXB0D7.
Legend:
DS41159E-page 208
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-10: TXBnDLC: TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS
U-0
R/W-x
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
TXRTR: Transmission Frame Remote Transmission Request bit
1 = Transmitted message will have TXRTR bit set
0 = Transmitted message will have TXRTR bit cleared
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
DLC3:DLC0: Data Length Code bits
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Data Length = 8 bytes
0111 = Data Length = 7 bytes
0110 = Data Length = 6 bytes
0101 = Data Length = 5 bytes
0100 = Data Length = 4 bytes
0011 = Data Length = 3 bytes
0010 = Data Length = 2 bytes
0001 = Data Length = 1 bytes
0000 = Data Length = 0 bytes
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 19-11: TXERRCNT: TRANSMIT ERROR COUNT REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
bit 7
bit 7-0
bit 0
TEC7:TEC0: Transmit Error Counter bits
This register contains a value which is derived from the rate at which errors occur. When the
error count overflows, the bus-off state occurs. When the bus has 128 occurrences of
11 consecutive recessive bits, the counter value is cleared.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 209
PIC18FXX8
19.2.3
CAN RECEIVE BUFFER
REGISTERS
This section shows the Receive Buffer registers with
their associated control registers.
REGISTER 19-12: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER
R/C-0
RXFUL
(1)
R/W-0
RXM1
R/W-0
(1)
RXM0
(1)
U-0
—
R-0
R/W-0
RXRTRRO RXB0DBEN
R-0
R-0
JTOFF
FILHIT0
bit 7
bit 7
bit 0
RXFUL: Receive Full Status bit(1)
1 = Receive buffer contains a received message
0 = Receive buffer is open to receive a new message
Note:
This bit is set by the CAN module and must be cleared by software after the buffer
is read.
bit 6-5
RXM1:RXM0: Receive Buffer Mode bits(1)
11 = Receive all messages (including those with errors)
10 = Receive only valid messages with extended identifier
01 = Receive only valid messages with standard identifier
00 = Receive all valid messages
bit 4
Unimplemented: Read as ‘0’
bit 3
RXRTRRO: Receive Remote Transfer Request Read-Only bit
1 = Remote transfer request
0 = No remote transfer request
bit 2
RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit
1 = Receive Buffer 0 overflow will write to Receive Buffer 1
0 = No Receive Buffer 0 overflow to Receive Buffer 1
bit 1
JTOFF: Jump Table Offset bit (read-only copy of RXB0DBEN)
1 = Allows jump table offset between 6 and 7
0 = Allows jump table offset between 1 and 0
Note:
bit 0
This bit allows same filter jump table for both RXB0CON and RXB1CON.
FILHIT0: Filter Hit bit
This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0.
1 = Acceptance Filter 1 (RXF1)
0 = Acceptance Filter 0 (RXF0)
Note 1: Bits RXFUL, RXM1 and RXM0 of RXB0CON are not mirrored in RXB1CON.
Legend:
DS41159E-page 210
R = Readable bit
W = Writable bit C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-13: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER
R/C-0
R/W-0
R/W-0
U-0
R-0
R-0
R-0
R-0
RXFUL(1)
RXM1(1)
RXM0(1)
—
RXRTRRO
FILHIT2
FILHIT1
FILHIT0
bit 7
bit 7
bit 0
RXFUL: Receive Full Status bit(1)
1 = Receive buffer contains a received message
0 = Receive buffer is open to receive a new message
Note:
This bit is set by the CAN module and should be cleared by software after the buffer
is read.
bit 6-5
RXM1:RXM0: Receive Buffer Mode bits(1)
11 = Receive all messages (including those with errors)
10 = Receive only valid messages with extended identifier
01 = Receive only valid messages with standard identifier
00 = Receive all valid messages
bit 4
Unimplemented: Read as ‘0’
bit 3
RXRTRRO: Receive Remote Transfer Request bit (read-only)
1 = Remote transfer request
0 = No remote transfer request
bit 2-0
FILHIT2:FILHIT0: Filter Hit bits
These bits indicate which acceptance filter enabled the last message reception into Receive
Buffer 1.
111 = Reserved
110 = Reserved
101 = Acceptance Filter 5 (RXF5)
100 = Acceptance Filter 4 (RXF4)
011 = Acceptance Filter 3 (RXF3)
010 = Acceptance Filter 2 (RXF2)
001 = Acceptance Filter 1 (RXF1), only possible when RXB0DBEN bit is set
000 = Acceptance Filter 0 (RXF0), only possible when RXB0DBEN bit is set
Note 1: Bits RXFUL, RXM1 and RXM0 of RXB1CON are not mirrored in RXB0CON.
Legend:
R = Readable bit
W = Writable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 211
PIC18FXX8
REGISTER 19-14: RXBnSIDH: RECEIVE BUFFER n STANDARD IDENTIFIER,
HIGH BYTE REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 7
bit 7-0
bit 0
SID10:SID3: Standard Identifier bits if EXID = 0 (RXBnSIDL Register) or
Extended Identifier bits EID28:EID21 if EXID = 1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 19-15: RXBnSIDL: RECEIVE BUFFER n STANDARD IDENTIFIER,
LOW BYTE REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
U-0
R/W-x
R/W-x
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
bit 7
bit 0
bit 7-5
SID2:SID0: Standard Identifier bits if EXID = 0 or
Extended Identifier bits EID20:EID18 if EXID = 1
bit 4
SRR: Substitute Remote Request bit
This bit is always ‘0’ when EXID = 1 or equal to the value of RXRTRRO (RXnBCON)
when EXID = 0.
bit 3
EXID: Extended Identifier bit
1 = Received message is an extended data frame, SID10:SID0 are EID28:EID18
0 = Received message is a standard data frame
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID17:EID16: Extended Identifier bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 19-16: RXBnEIDH: RECEIVE BUFFER n EXTENDED IDENTIFIER,
HIGH BYTE REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
bit 7
bit 7-0
bit 0
EID15:EID8: Extended Identifier bits
Legend:
DS41159E-page 212
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-17: RXBnEIDL: RECEIVE BUFFER n EXTENDED IDENTIFIER,
LOW BYTE REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
bit 7
bit 7-0
bit 0
EID7:EID0: Extended Identifier bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 19-18: RXBnDLC: RECEIVE BUFFER n DATA LENGTH CODE REGISTERS
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
RXRTR: Receiver Remote Transmission Request bit
1 = Remote transfer request
0 = No remote transfer request
bit 5
RB1: Reserved bit 1
Reserved by CAN spec and read as ‘0’.
bit 4
RB0: Reserved bit 0
Reserved by CAN spec and read as ‘0’.
bit 3-0
DLC3:DLC0: Data Length Code bits
1111 = Invalid
1110 = Invalid
1101 = Invalid
1100 = Invalid
1011 = Invalid
1010 = Invalid
1001 = Invalid
1000 = Data Length = 8 bytes
0111 = Data Length = 7 bytes
0110 = Data Length = 6 bytes
0101 = Data Length = 5 bytes
0100 = Data Length = 4 bytes
0011 = Data Length = 3 bytes
0010 = Data Length = 2 bytes
0001 = Data Length = 1 bytes
0000 = Data Length = 0 bytes
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 213
PIC18FXX8
REGISTER 19-19: RXBnDm: RECEIVE BUFFER n DATA FIELD BYTE m REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0
bit 7
bit 7-0
bit 0
RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0 ≤ n < 1 and 0 < m < 7)
Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers:
RXB0D0 to RXB0D7.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 19-20: RXERRCNT: RECEIVE ERROR COUNT REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
bit 7
bit 7-0
bit 0
REC7:REC0: Receive Error Counter bits
This register contains the receive error value as defined by the CAN specifications.
When RXERRCNT > 127, the module will go into an error passive state. RXERRCNT does not
have the ability to put the module in “Bus-Off” state.
Legend:
DS41159E-page 214
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
19.2.3.1
Message Acceptance Filters and
Masks
This subsection describes the message acceptance
filters and masks for the CAN receive buffers.
REGISTER 19-21: RXFnSIDH: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER,
HIGH BYTE REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 7
bit 7-0
bit 0
SID10:SID3: Standard Identifier Filter bits if EXIDEN = 0 or
Extended Identifier Filter bits EID28:EID21 if EXIDEN = 1
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 19-22: RXFnSIDL: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER,
LOW BYTE REGISTERS
R/W-x
R/W-x
R/W-x
U-0
R/W-x
U-0
R/W-x
R/W-x
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16
bit 7
bit 0
bit 7-5
SID2:SID0: Standard Identifier Filter bits if EXIDEN = 0 or
Extended Identifier Filter bits EID20:EID18 if EXIDEN = 1
bit 4
Unimplemented: Read as ‘0’
bit 3
EXIDEN: Extended Identifier Filter Enable bit
1 = Filter will only accept extended ID messages
0 = Filter will only accept standard ID messages
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID17:EID16: Extended Identifier Filter bits
Legend:
R = Readable bit
-n = Value at POR
© 2006 Microchip Technology Inc.
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DS41159E-page 215
PIC18FXX8
REGISTER 19-23: RXFnEIDH: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER,
HIGH BYTE REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
bit 7
bit 7-0
bit 0
EID15:EID8: Extended Identifier Filter bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 19-24: RXFnEIDL: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER,
LOW BYTE REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
bit 7
bit 7-0
bit 0
EID7:EID0: Extended Identifier Filter bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 19-25: RXMnSIDH: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK,
HIGH BYTE REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 7
bit 7-0
bit 0
SID10:SID3: Standard Identifier Mask bits or Extended Identifier Mask bits EID28:EID21
Legend:
DS41159E-page 216
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-26: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK,
LOW BYTE REGISTERS
R/W-x
R/W-x
R/W-x
U-0
U-0
U-0
R/W-x
R/W-x
SID2
SID1
SID0
—
—
—
EID17
EID16
bit 7
bit 0
bit 7-5
SID2:SID0: Standard Identifier Mask bits or Extended Identifier Mask bits EID20:EID18
bit 4-2
Unimplemented: Read as ‘0’
bit 1-0
EID17:EID16: Extended Identifier Mask bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 19-27: RXMnEIDH: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK,
HIGH BYTE REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
bit 7
bit 7-0
bit 0
EID15:EID8: Extended Identifier Mask bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 19-28: RXMnEIDL: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK,
LOW BYTE REGISTERS
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
bit 7
bit 7-0
bit 0
EID7:EID0: Extended Identifier Mask bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 217
PIC18FXX8
19.2.4
CAN BAUD RATE REGISTERS
This subsection describes the CAN Baud Rate
registers.
REGISTER 19-29: BRGCON1: BAUD RATE CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
bit 7
bit 0
bit 7-6
SJW1:SJW0: Synchronized Jump Width bits
11 = Synchronization Jump Width Time = 4 x TQ
10 = Synchronization Jump Width Time = 3 x TQ
01 = Synchronization Jump Width Time = 2 x TQ
00 = Synchronization Jump Width Time = 1 x TQ
bit 5-0
BRP5:BRP0: Baud Rate Prescaler bits
111111 = TQ = (2 x 64)/FOSC
111110 = TQ = (2 x 63)/FOSC
:
:
000001 = TQ = (2 x 2)/FOSC
000000 = TQ = (2 x 1)/FOSC
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Note:
DS41159E-page 218
x = Bit is unknown
This register is accessible in Configuration mode only.
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-30: BRGCON2: BAUD RATE CONTROL REGISTER 2
R/W-0
R/W-0
SEG2PHTS
SAM
R/W-0
R/W-0
R/W-0
R/W-0
SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2
R/W-0
R/W-0
PRSEG1
PRSEG0
bit 7
bit 0
bit 7
SEG2PHTS: Phase Segment 2 Time Select bit
1 = Freely programmable
0 = Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater
bit 6
SAM: Sample of the CAN bus Line bit
1 = Bus line is sampled three times prior to the sample point
0 = Bus line is sampled once at the sample point
bit 5-3
SEG1PH2:SEG1PH0: Phase Segment 1 bits
111 = Phase Segment 1 Time = 8 x TQ
110 = Phase Segment 1 Time = 7 x TQ
101 = Phase Segment 1 Time = 6 x TQ
100 = Phase Segment 1 Time = 5 x TQ
011 = Phase Segment 1 Time = 4 x TQ
010 = Phase Segment 1 Time = 3 x TQ
001 = Phase Segment 1 Time = 2 x TQ
000 = Phase Segment 1 Time = 1 x TQ
bit 2-0
PRSEG2:PRSEG0: Propagation Time Select bits
111 = Propagation Time = 8 x TQ
110 = Propagation Time = 7 x TQ
101 = Propagation Time = 6 x TQ
100 = Propagation Time = 5 x TQ
011 = Propagation Time = 4 x TQ
010 = Propagation Time = 3 x TQ
001 = Propagation Time = 2 x TQ
000 = Propagation Time = 1 x TQ
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Note:
© 2006 Microchip Technology Inc.
x = Bit is unknown
This register is accessible in Configuration mode only.
DS41159E-page 219
PIC18FXX8
REGISTER 19-31: BRGCON3: BAUD RATE CONTROL REGISTER 3
U-0
R/W-0
U-0
U-0
U-0
—
WAKFIL
—
—
—
R/W-0
R/W-0
R/W-0
SEG2PH2(1) SEG2PH1(1) SEG2PH0(1)
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
WAKFIL: Selects CAN bus Line Filter for Wake-up bit
1 = Use CAN bus line filter for wake-up
0 = CAN bus line filter is not used for wake-up
bit 5-3
Unimplemented: Read as ‘0’
bit 2-0
SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits(1)
111 = Phase Segment 2 Time = 8 x TQ
110 = Phase Segment 2 Time = 7 x TQ
101 = Phase Segment 2 Time = 6 x TQ
100 = Phase Segment 2 Time = 5 x TQ
011 = Phase Segment 2 Time = 4 x TQ
010 = Phase Segment 2 Time = 3 x TQ
001 = Phase Segment 2 Time = 2 x TQ
000 = Phase Segment 2 Time = 1 x TQ
Note 1: Ignored if SEG2PHTS bit (BRGCON2) is clear.
Legend:
DS41159E-page 220
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
19.2.5
CAN MODULE I/O CONTROL
REGISTER
This register controls the operation of the CAN module’s
I/O pins in relation to the rest of the microcontroller.
REGISTER 19-32: CIOCON: CAN I/O CONTROL REGISTER
U-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
—
ENDRHI
CANCAP
—
—
—
—
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5
ENDRHI: Enable Drive High bit
1 = CANTX pin will drive VDD when recessive
0 = CANTX pin will tri-state when recessive
bit 4
CANCAP: CAN Message Receive Capture Enable bit
1 = Enable CAN capture, CAN message receive signal replaces input on RC2/CCP1
0 = Disable CAN capture, RC2/CCP1 input to CCP1 module
bit 3-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 221
PIC18FXX8
19.2.6
CAN INTERRUPT REGISTERS
The registers in this section are the same as described
in Section 8.0 “Interrupts”. They are duplicated here
for convenience.
REGISTER 19-33: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRXIF
WAKIF
ERRIF
TXB2IF
TXB1IF
TXB0IF
RXB1IF
RXB0IF
bit 7
bit 0
bit 7
IRXIF: CAN Invalid Received Message Interrupt Flag bit
1 = An invalid message has occurred on the CAN bus
0 = No invalid message on CAN bus
bit 6
WAKIF: CAN bus Activity Wake-up Interrupt Flag bit
1 = Activity on CAN bus has occurred
0 = No activity on CAN bus
bit 5
ERRIF: CAN bus Error Interrupt Flag bit
1 = An error has occurred in the CAN module (multiple sources)
0 = No CAN module errors
bit 4
TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit
1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 2 has not completed transmission of a message
bit 3
TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit
1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 1 has not completed transmission of a message
bit 2
TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit
1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 0 has not completed transmission of a message
bit 1
RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit
1 = Receive Buffer 1 has received a new message
0 = Receive Buffer 1 has not received a new message
bit 0
RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit
1 = Receive Buffer 0 has received a new message
0 = Receive Buffer 0 has not received a new message
Legend:
DS41159E-page 222
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-34: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRXIE
WAKIE
ERRIE
TXB2IE
TXB1IE
TXB0IE
RXB1IE
RXB0IE
bit 7
bit 0
bit 7
IRXIE: CAN Invalid Received Message Interrupt Enable bit
1 = Enable invalid message received interrupt
0 = Disable invalid message received interrupt
bit 6
WAKIE: CAN bus Activity Wake-up Interrupt Enable bit
1 = Enable bus activity wake-up interrupt
0 = Disable bus activity wake-up interrupt
bit 5
ERRIE: CAN bus Error Interrupt Enable bit
1 = Enable CAN bus error interrupt
0 = Disable CAN bus error interrupt
bit 4
TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit
1 = Enable Transmit Buffer 2 interrupt
0 = Disable Transmit Buffer 2 interrupt
bit 3
TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit
1 = Enable Transmit Buffer 1 interrupt
0 = Disable Transmit Buffer 1 interrupt
bit 2
TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit
1 = Enable Transmit Buffer 0 interrupt
0 = Disable Transmit Buffer 0 interrupt
bit 1
RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit
1 = Enable Receive Buffer 1 interrupt
0 = Disable Receive Buffer 1 interrupt
bit 0
RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit
1 = Enable Receive Buffer 0 interrupt
0 = Disable Receive Buffer 0 interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 223
PIC18FXX8
REGISTER 19-35: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IRXIP
WAKIP
ERRIP
TXB2IP
TXB1IP
TXB0IP
RXB1IP
RXB0IP
bit 7
bit 0
bit 7
IRXIP: CAN Invalid Received Message Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
WAKIP: CAN bus Activity Wake-up Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
ERRIP: CAN bus Error Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
DS41159E-page 224
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 19-1:
Address
CAN CONTROLLER REGISTER MAP
Name
F7Fh
Address
—
F5Fh
Name
Address
—
F7Eh
—
F5Eh CANSTATRO1
F7Dh
—
F5Dh
F7Ch
—
F7Bh
—
F7Ah
F79h
F3Fh
(2)
Name
Address
—
F3Eh CANSTATRO3
(2)
Name
F1Fh
RXM1EIDL
F1Eh
RXM1EIDH
TXB1D7
F1Dh
RXM1SIDL
F3Ch
TXB1D6
F1Ch
RXM1SIDH
F3Bh
TXB1D5
F1Bh
RXM0EIDL
RXB1D4
F3Ah
TXB1D4
F1Ah
RXM0EIDH
RXB1D3
F39h
TXB1D3
F19h
RXM0SIDL
F58h
RXB1D2
F38h
TXB1D2
F18h
RXM0SIDH
F57h
RXB1D1
F37h
TXB1D1
F17h
RXF5EIDL
RXB1D7
F3Dh
F5Ch
RXB1D6
F5Bh
RXB1D5
—
F5Ah
—
F59h
F78h
—
F77h
—
F76h TXERRCNT
F56h
RXB1D0
F36h
TXB1D0
F16h
RXF5EIDH
F75h RXERRCNT
F55h
RXB1DLC
F35h
TXB1DLC
F15h
RXF5SIDL
F74h
COMSTAT
F54h
RXB1EIDL
F34h
TXB1EIDL
F14h
RXF5SIDH
F73h
CIOCON
F53h
RXB1EIDH
F33h
TXB1EIDH
F13h
RXF4EIDL
F72h
BRGCON3
F52h
RXB1SIDL
F32h
TXB1SIDL
F12h
RXF4EIDH
F71h
BRGCON2
F51h
RXB1SIDH
F31h
TXB1SIDH
F11h
RXF4SIDL
F70h
BRGCON1
F50h
RXB1CON
F30h
TXB1CON
F10h
RXF4SIDH
F6Fh
CANCON
F4Fh
—
F2Fh
—
F0Fh
RXF3EIDL
F6Eh
CANSTAT
F4Eh
CANSTATRO2(2)
F2Eh
CANSTATRO4(2)
F0Eh
RXF3EIDH
F6Dh
RXB0D7
F4Dh
TXB0D7
F2Dh
TXB2D7
F0Dh
RXF3SIDL
F6Ch
RXB0D6
F4Ch
TXB0D6
F2Ch
TXB2D6
F0Ch
RXF3SIDH
F6Bh
RXB0D5
F4Bh
TXB0D5
F2Bh
TXB2D5
F0Bh
RXF2EIDL
F6Ah
RXB0D4
F4Ah
TXB0D4
F2Ah
TXB2D4
F0Ah
RXF2EIDH
F69h
RXB0D3
F49h
TXB0D3
F29h
TXB2D3
F09h
RXF2SIDL
F68h
RXB0D2
F48h
TXB0D2
F28h
TXB2D2
F08h
RXF2SIDH
F67h
RXB0D1
F47h
TXB0D1
F27h
TXB2D1
F07h
RXF1EIDL
F66h
RXB0D0
F46h
TXB0D0
F26h
TXB2D0
F06h
RXF1EIDH
F65h
RXB0DLC
F45h
TXB0DLC
F25h
TXB2DLC
F05h
RXF1SIDL
F64h
RXB0EIDL
F44h
TXB0EIDL
F24h
TXB2EIDL
F04h
RXF1SIDH
F63h
RXB0EIDH
F43h
TXB0EIDH
F23h
TXB2EIDH
F03h
RXF0EIDL
F62h
RXB0SIDL
F42h
TXB0SIDL
F22h
TXB2SIDL
F02h
RXF0EIDH
F61h
RXB0SIDH
F41h
TXB0SIDH
F21h
TXB2SIDH
F01h
RXF0SIDL
F60h
RXB0CON
F40h
TXB0CON
F20h
TXB2CON
F00h
RXF0SIDH
Note 1:
2:
Shaded registers are available in Access Bank low area while the rest are available in Bank 15.
CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given
for each instance of the CANSTAT register due to the Microchip Header file requirement.
© 2006 Microchip Technology Inc.
DS41159E-page 225
PIC18FXX8
19.3
CAN Modes of Operation
The PIC18FXX8 has six main modes of operation:
•
•
•
•
•
•
Configuration mode
Disable mode
Normal Operation mode
Listen Only mode
Loopback mode
Error Recognition mode
All modes, except Error Recognition, are requested by
setting the REQOP bits (CANCON); Error Recognition is requested through the RXM bits of the Receive
Buffer register(s). Entry into a mode is Acknowledged
by monitoring the OPMODE bits.
When changing modes, the mode will not actually
change until all pending message transmissions are
complete. Because of this, the user must verify that the
device has actually changed into the requested mode
before fUrther Operations Are Executed.
19.3.1
CONFIGURATION MODE
The CAN module has to be initialized before the
activation. This is only possible if the module is in the
Configuration mode. The Configuration mode is
requested by setting the REQOP2 bit. Only when the
OPMODE2 status bit has a high level can the initialization be performed. Afterwards, the Configuration
registers, the Acceptance Mask registers and the
Acceptance Filter registers can be written. The module
is activated by setting the REQOP control bits to zero.
The module will protect the user from accidentally
violating the CAN protocol through programming
errors. All registers which control the configuration of
the module can not be modified while the module is online. The CAN module will not be allowed to enter the
Configuration mode while a transmission is taking
place. The CONFIG bit serves as a lock to protect the
following registers.
•
•
•
•
Configuration registers
Bus Timing registers
Identifier Acceptance Filter registers
Identifier Acceptance Mask registers
In the Configuration mode, the module will not transmit
or receive. The error counters are cleared and the
interrupt flags remain unchanged. The programmer will
have access to Configuration registers that are access
restricted in other modes.
DS41159E-page 226
19.3.2
DISABLE MODE
In Disable mode, the module will not transmit or
receive. The module has the ability to set the WAKIF bit
due to bus activity, however, any pending interrupts will
remain and the error counters will retain their value.
If REQOP is set to ‘001’, the module will enter the
Module Disable mode. This mode is similar to disabling
other peripheral modules by turning off the module
enables. This causes the module internal clock to stop
unless the module is active (i.e., receiving or transmitting a message). If the module is active, the module will
wait for 11 recessive bits on the CAN bus, detect that
condition as an IDLE bus, then accept the module
disable command. OPMODE = 001 indicates
whether the module successfully went into Module
Disable mode.
The WAKIF interrupt is the only module interrupt that is
still active in the Module Disable mode. If the WAKIE is
set, the processor will receive an interrupt whenever
the CAN bus detects a dominant state, as occurs with
a SOF. If the processor receives an interrupt while it is
sleeping, more than one message may get lost. User
firmware must anticipate this condition and request
retransmission. If the processor is running while it
receives an interrupt, only the first message may get
lost.
The I/O pins will revert to normal I/O function when the
module is in the Module Disable mode.
19.3.3
NORMAL MODE
This is the standard operating mode of the PIC18FXX8.
In this mode, the device actively monitors all bus
messages and generates Acknowledge bits, error
frames, etc. This is also the only mode in which the
PIC18FXX8 will transmit messages over the CAN bus.
19.3.4
LISTEN ONLY MODE
Listen Only mode provides a means for the
PIC18FXX8 to receive all messages, including
messages with errors. This mode can be used for bus
monitor applications or for detecting the baud rate in
‘hot plugging’ situations. For auto-baud detection, it is
necessary that there are at least two other nodes which
are communicating with each other. The baud rate can
be detected empirically by testing different values until
valid messages are received. The Listen Only mode is
a silent mode, meaning no messages will be transmitted while in this state, including error flags or
Acknowledge signals. The filters and masks can be
used to allow only particular messages to be loaded
into the receive registers, or the filter masks can be set
to all zeros to allow a message with any identifier to
pass. The error counters are reset and deactivated in
this state. The Listen Only mode is activated by setting
the mode request bits in the CANCON register.
© 2006 Microchip Technology Inc.
PIC18FXX8
19.3.5
LOOPBACK MODE
This mode will allow internal transmission of messages
from the transmit buffers to the receive buffers without
actually transmitting messages on the CAN bus. This
mode can be used in system development and testing.
In this mode, the ACK bit is ignored and the device will
allow incoming messages from itself, just as if they
were coming from another node. The Loopback mode
is a silent mode, meaning no messages will be transmitted while in this state, including error flags or
Acknowledge signals. The TXCAN pin will revert to port
I/O while the device is in this mode. The filters and
masks can be used to allow only particular messages
to be loaded into the receive registers. The masks can
be set to all zeros to provide a mode that accepts all
messages. The Loopback mode is activated by setting
the mode request bits in the CANCON register.
19.3.6
19.4.2
TRANSMIT PRIORITY
Transmit priority is a prioritization within the
PIC18FXX8 of the pending transmittable messages.
This is independent from and not related to any prioritization implicit in the message arbitration scheme built
into the CAN protocol. Prior to sending the SOF, the
priority of all buffers that are queued for transmission is
compared. The transmit buffer with the highest priority
will be sent first. If two buffers have the same priority
setting, the buffer with the highest buffer number will be
sent first. There are four levels of transmit priority. If
TXP bits for a particular message buffer are set to ‘11’,
that buffer has the highest possible priority. If TXP bits
for a particular message buffer are ‘00’, that buffer has
the lowest possible priority.
FIGURE 19-2:
ERROR RECOGNITION MODE
The module can be set to ignore all errors and receive
all message. The Error Recognition mode is activated
by setting the RXM bits in the RXBnCON
registers to ‘11’. In this mode, all messages, valid or
invalid, are received and copied to the receive buffer.
19.4
19.4.1
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
CAN Message Transmission
TRANSMIT BUFFERS
The PIC18FXX8 implements three transmit buffers
(Figure 19-2). Each of these buffers occupies 14 bytes
of SRAM and are mapped into the device memory
map.
For the MCU to have write access to the message
buffer, the TXREQ bit must be clear, indicating that the
message buffer is clear of any pending message to be
transmitted. At a minimum, the TXBnSIDH, TXBnSIDL
and TXBnDLC registers must be loaded. If data bytes
are present in the message, the TXBnDm registers
must also be loaded. If the message is to use extended
identifiers, the TXBnEIDm registers must also be
loaded and the EXIDE bit set.
TRANSMIT BUFFER
BLOCK DIAGRAM
Message
Request
Message
Queue
Control
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
TXB0
MESSAGE
TXB1
MESSAGE
TXB2
MESSAGE
Transmit Byte Sequencer
Prior to sending the message, the MCU must initialize
the TXInE bit to enable or disable the generation of an
interrupt when the message is sent. The MCU must
also initialize the TXP priority bits (see Section 19.4.2
“Transmit Priority”).
© 2006 Microchip Technology Inc.
DS41159E-page 227
PIC18FXX8
19.4.3
INITIATING TRANSMISSION
To initiate message transmission, the TXREQ bit must
be set for each buffer to be transmitted. When TXREQ
is set, the TXABT, TXLARB and TXERR bits will be
cleared.
Setting the TXREQ bit does not initiate a message
transmission; it merely flags a message buffer as ready
for transmission. Transmission will start when the
device detects that the bus is available. The device will
then begin transmission of the highest priority message
that is ready.
When the transmission has completed successfully,
the TXREQ bit will be cleared, the TXBnIF bit will be set
and an interrupt will be generated if the TXBnIE bit is
set.
If the message transmission fails, the TXREQ will
remain set, indicating that the message is still pending
for transmission and one of the following condition flags
will be set. If the message started to transmit but
encountered an error condition, the TXERR and the
IRXIF bits will be set and an interrupt will be generated.
If the message lost arbitration, the TXLARB bit will be
set.
DS41159E-page 228
19.4.4
ABORTING TRANSMISSION
The MCU can request to abort a message by clearing
the TXREQ bit associated with the corresponding
message buffer (TXBnCON). Setting the ABAT bit
(CANCON) will request an abort of all pending
messages. If the message has not yet started transmission, or if the message started but is interrupted by loss
of arbitration or an error, the abort will be processed.
The abort is indicated when the module sets the ABT
bits for the corresponding buffer (TXBnCON). If the
message has started to transmit, it will attempt to
transmit the current message fully. If the current
message is transmitted fully and is not lost to arbitration
or an error, the ABT bit will not be set because the
message was transmitted successfully. Likewise, if a
message is being transmitted during an abort request
and the message is lost to arbitration or an error, the
message will not be retransmitted and the ABT bit will
be set, indicating that the message was successfully
aborted.
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 19-3:
INTERNAL TRANSMIT MESSAGE FLOWCHART
Start
The message transmission sequence begins when
the device determines that the TXREQ for any of the
transmit registers has been set.
Are any
TXREQ
bits = 1?
No
Clearing the TXREQ bit while it is set, or setting
the ABAT bit before the message has started
transmission, will abort the message.
Yes
Clear: TXABT, TXLARB
and TXERR
No
Is CAN bus
Available to Start
Transmission?
No
Is
TXREQ = 0
ABAT = 1?
Yes
Yes
Examine TXPRI to
Determine Highest Priority Message
Begin Transmission (SOF)
Was
Message Transmitted
Successfully?
No
Set
TXERR = 1
Yes
Set TXREQ = 0
Is
TXLARB = 1?
Yes
Generate
Interrupt
Is
TXIE = 1?
No
A message can also be
aborted if a message
error or lost arbitration
condition occurred during
transmission.
Yes Arbitration Lost During
Transmission
No
Is
TXREQ = 0
or TXABT = 1?
Yes
Set
TXBUFE = 1
No
The TXIE bit determines if an interrupt should be generated when a
message is successfully transmitted.
Abort Transmission:
Set TXABT = 1
END
© 2006 Microchip Technology Inc.
DS41159E-page 229
PIC18FXX8
19.5
19.5.1
Message Reception
RECEIVE MESSAGE BUFFERING
The PIC18FXX8 includes two full receive buffers with
multiple acceptance filters for each. There is also a
separate Message Assembly Buffer (MAB) which acts
as a third receive buffer (see Figure 19-4).
19.5.2
RECEIVE BUFFERS
Of the three receive buffers, the MAB is always committed to receiving the next message from the bus. The
remaining two receive buffers are called RXB0 and
RXB1 and can receive a complete message from the
protocol engine. The MCU can access one buffer while
the other buffer is available for message reception or
holding a previously received message.
The MAB assembles all messages received. These
messages will be transferred to the RXBn buffers only
if the acceptance filter criteria are met.
Note:
The entire contents of the MAB are moved
into the receive buffer once a message is
accepted. This means that regardless of
the type of identifier (standard or
extended) and the number of data bytes
received, the entire receive buffer is overwritten with the MAB contents. Therefore,
the contents of all registers in the buffer
must be assumed to have been modified
when any message is received.
When a message is moved into either of the receive
buffers, the appropriate RXBnIF bit is set. This bit must
be cleared by the MCU when it has completed processing the message in the buffer in order to allow a new
message to be received into the buffer. This bit
provides a positive lockout to ensure that the MCU has
finished with the message before the PIC18FXX8
attempts to load a new message into the receive buffer.
If the RXBnIE bit is set, an interrupt will be generated to
indicate that a valid message has been received.
19.5.3
The RXM bits set special Receive modes. Normally,
these bits are set to ‘00’ to enable reception of all valid
messages as determined by the appropriate acceptance filters. In this case, the determination of whether
or not to receive standard or extended messages is
determined by the EXIDE bit in the Acceptance Filter
register. If the RXM bits are set to ‘01’ or ‘10’, the
receiver will accept only messages with standard or
extended identifiers, respectively. If an acceptance
filter has the EXIDE bit set, such that it does not correspond with the RXM mode, that acceptance filter is
rendered useless. These two modes of RXM bits can
be used in systems where it is known that only standard
or extended messages will be on the bus. If the RXM
bits are set to ‘11’, the buffer will receive all messages
regardless of the values of the acceptance filters. Also,
if a message has an error before the end of frame, that
portion of the message assembled in the MAB before
the error frame will be loaded into the buffer. This mode
has some value in debugging a CAN system and would
not be used in an actual system environment.
19.5.4
TIME-STAMPING
The CAN module can be programmed to generate a
time-stamp for every message that is received. When
enabled, the module generates a capture signal for
CCP1 which in turns captures the value of either
Timer1 or Timer3. This value can be used as the
message time-stamp.
To use the time-stamp capability, the CANCAP bit
(CIOCAN) must be set. This replaces the capture
input for CCP1 with the signal generated from the CAN
module. In addition, CCP1CON must be set to
‘0011’ to enable the CCP special event trigger for CAN
events.
FIGURE 19-4:
RECEIVE BUFFER BLOCK
DIAGRAM
Accept Acceptance Mask
RXM1
RECEIVE PRIORITY
RXB0 is the higher priority buffer and has two message
acceptance filters associated with it. RXB1 is the lower
priority buffer and has four acceptance filters associated with it. The lower number of acceptance filters
makes the match on RXB0 more restrictive and implies
a higher priority for that buffer. Additionally, the
RXB0CON register can be configured such if RXB0
contains a valid message and another valid message is
received, an overflow error will not occur and the new
message will be moved into RXB1 regardless of the
acceptance criteria of RXB1. There are also two
programmable acceptance filter masks available, one
for each receive buffer (see Section 19.6 “Message
Acceptance Filters and Masks”).
When a message is received, bits of the
RXBnCON register will indicate the acceptance filter
number that enabled reception and whether the
received message is a remote transfer request.
DS41159E-page 230
Acceptance Filter
RXM2
Accept
Acceptance Mask
RXM0
Acceptance Filter
RXF3
Acceptance Filter
RXF0
Acceptance Filter
RXF4
Acceptance Filter
RXF1
Acceptance Filter
RXF5
RXB0
Identifier
RXB1
Data and
Identifier
Data and
Identifier
Identifier
Message Assembly Buffer
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 19-5:
INTERNAL MESSAGE RECEPTION FLOWCHART
Start
Detect
Start of
Message?
No
Yes
Begin Loading Message into
Message Assembly Buffer (MAB)
Generate
Error
Frame
Valid
Message
Received?
No
Yes
Yes, meets criteria
Yes, meets criteria
Message
for RXB1
for RXBO
Identifier meets a
Filter Criteria?
No
Go to Start
The RXFUL bit determines if the
receive register is empty and able
to accept a new message.
The RXB0DBEN bit determines if
RXB0 can rollover into RXB1 if it is
full.
Is
RXFUL = 0?
No
Yes
Is
RX0DBEN = 1?
Yes
No
Move Message into RXB0
Generate Overrun Error:
Set RXB0OVFL
Generate Overrun Error:
Set RXB1OVFL
No
Set RXRDY = 1
Is
RXFUL = 0?
Yes
Move Message into RXB1
Set FILHIT
according to which Filter
Criteria was met
Is
ERRIE = 1?
No
Set RXRDY = 1
Yes
Go to Start
Is
RXIE = 1?
Yes
Generate
Interrupt
No
Set FILHIT
according to which Filter
Criteria was met
Yes
Is
RXIE = 1?
No
Set CANSTAT according
to which Receive Buffer the
Message was loaded into
© 2006 Microchip Technology Inc.
DS41159E-page 231
PIC18FXX8
19.6
Message Acceptance Filters
and Masks
For RXB1, the RXB1CON register contains the
FILHIT bits. They are coded as follows:
The message acceptance filters and masks are used to
determine if a message in the message assembly
buffer should be loaded into either of the receive buffers. Once a valid message has been received into the
MAB, the identifier fields of the message are compared
to the filter values. If there is a match, that message will
be loaded into the appropriate receive buffer. The filter
masks are used to determine which bits in the identifier
are examined with the filters. A truth table is shown
below in Table 19-2 that indicates how each bit in the
identifier is compared to the masks and filters to determine if a message should be loaded into a receive
buffer. The mask essentially determines which bits to
apply the acceptance filters to. If any mask bit is set to
a zero, then that bit will automatically be accepted
regardless of the filter bit.
TABLE 19-2:
FILTER/MASK TRUTH TABLE
Mask
bit n
Filter bit n
Message
Identifier
bit n001
Accept or
Reject
bit n
0
x
x
Accept
1
0
0
Accept
1
0
1
Reject
1
1
0
Reject
1
1
1
Accept
Legend:
x = don’t care
As shown in the receive buffer block diagram
(Figure 19-4), acceptance filters RXF0 and RXF1 and
filter mask RXM0 are associated with RXB0. Filters
RXF2, RXF3, RXF4 and RXF5 and mask RXM1 are
associated with RXB1. When a filter matches and a
message is loaded into the receive buffer, the filter
number that enabled the message reception is loaded
into the FILHIT bit(s).
FIGURE 19-6:
•
•
•
•
•
•
101 = Acceptance Filter 5 (RXF5)
100 = Acceptance Filter 4 (RXF4)
011 = Acceptance Filter 3 (RXF3)
010 = Acceptance Filter 2 (RXF2)
001 = Acceptance Filter 1 (RXF1)
000 = Acceptance Filter 0 (RXF0)
Note:
‘000’ and ‘001’ can only occur if the
RXB0DBEN bit is set in the RXB0CON
register allowing RXB0 messages to
rollover into RXB1.
The coding of the RXB0DBEN bit enables these three
bits to be used similarly to the FILHIT bits and to
distinguish a hit on filter RXF0 and RXF1, in either
RXB0, or after a rollover into RXB1.
•
•
•
•
111 = Acceptance Filter 1 (RXF1)
110 = Acceptance Filter 0 (RXF0)
001 = Acceptance Filter 1 (RXF1)
000 = Acceptance Filter 0
If the RXB0DBEN bit is clear, there are six codes
corresponding to the six filters. If the RXB0DBEN bit is
set, there are six codes corresponding to the six filters
plus two additional codes corresponding to RXF0 and
RXF1 filters that rollover into RXB1.
If more than one acceptance filter matches, the FILHIT
bits will encode the binary value of the lowest
numbered filter that matched. In other words, if filter
RXF2 and filter RXF4 match, FILHIT will be loaded with
the value for RXF2. This essentially prioritizes the
acceptance filters with a lower number filter having
higher priority. Messages are compared to filters in
ascending order of filter number.
The mask and filter registers can only be modified
when the PIC18FXX8 is in Configuration mode. The
mask and filter registers cannot be read outside of
Configuration mode. When outside of Configuration
mode, all mask and filter registers will be read as ‘0’.
MESSAGE ACCEPTANCE MASK AND FILTER OPERATION
Acceptance Filter Register
RXFn0
Acceptance Mask Register
RXMn0
RXMn1
RXFn1
RXFnn
RxRqst
RXMnn
Message Assembly Buffer
Identifier
DS41159E-page 232
© 2006 Microchip Technology Inc.
PIC18FXX8
19.7
Baud Rate Setting
All nodes on a given CAN bus must have the same
nominal bit rate. The CAN protocol uses Non-Returnto-Zero (NRZ) coding which does not encode a clock
within the data stream. Therefore, the receive clock
must be recovered by the receiving nodes and
synchronized to the transmitters clock.
As oscillators and transmission time may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data transmission edges to synchronize and maintain the receiver
clock. Since the data is NRZ coded, it is necessary to
include bit stuffing to ensure that an edge occurs at
least every six bit times to maintain the Digital Phase
Lock Loop (DPLL) synchronization.
The bit timing of the PIC18FXX8 is implemented using
a DPLL that is configured to synchronize to the
incoming data and provides the nominal timing for the
transmitted data. The DPLL breaks each bit time into
multiple segments made up of minimal periods of time
called the Time Quanta (TQ).
Bus timing functions executed within the bit time frame,
such as synchronization to the local oscillator, network
transmission delay compensation and sample point
positioning, are defined by the programmable bit timing
logic of the DPLL.
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different clock
frequencies of the individual devices, the bit rate has to
be adjusted by appropriately setting the baud rate
prescaler and number of time quanta in each segment.
The Nominal Bit Rate is the number of bits transmitted
per second, assuming an ideal transmitter with an ideal
oscillator, in the absence of resynchronization. The
nominal bit rate is defined to be a maximum of 1 Mb/s.
FIGURE 19-7:
The Nominal Bit Time is defined as:
TBIT = 1/Nominal Bit Rate
The nominal bit time can be thought of as being divided
into separate, non-overlapping time segments. These
segments (Figure 19-7) include:
•
•
•
•
Synchronization Segment (Sync_Seg)
Propagation Time Segment (Prop_Seg)
Phase Buffer Segment 1 (Phase_Seg1)
Phase Buffer Segment 2 (Phase_Seg2)
The time segments (and thus, the nominal bit time) are,
in turn, made up of integer units of time called time
quanta or TQ (see Figure 19-7). By definition, the
nominal bit time is programmable from a minimum of
8 TQ to a maximum of 25 TQ. Also, by definition, the
minimum nominal bit time is 1 μs corresponding to a
maximum 1 Mb/s rate. The actual duration is given by
the relationship:
Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg +
Phase_Seg1 + Phase_Seg2)
The time quantum is a fixed unit derived from the
oscillator period. It is also defined by the programmable
baud rate prescaler, with integer values from 1 to 64, in
addition to a fixed divide-by-two for clock generation.
Mathematically, this is
TQ (μs) = (2 * (BRP + 1))/FOSC (MHz)
or
TQ (μs) = (2 * (BRP + 1)) * TOSC (μs)
where FOSC is the clock frequency, TOSC is the
corresponding oscillator period and BRP is an integer
(0 through 63) represented by the binary values of
BRGCON1.
BIT TIME PARTITIONING
Input
Signal
Bit
Time
Intervals
Sync Propagation
Segment Segment
Phase
Segment 1
Phase
Segment 2
TQ
Sample Point
Nominal Bit Time
© 2006 Microchip Technology Inc.
DS41159E-page 233
PIC18FXX8
19.7.1
TIME QUANTA
19.7.2
SYNCHRONIZATION SEGMENT
As already mentioned, the time quanta is a fixed unit
derived from the oscillator period and baud rate
prescaler. Its relationship to TBIT and the nominal bit
rate is shown in Example 19-2.
This part of the bit time is used to synchronize the
various CAN nodes on the bus. The edge of the input
signal is expected to occur during the sync segment.
The duration is 1 TQ.
EXAMPLE 19-2:
19.7.3
CALCULATING TQ,
NOMINAL BIT RATE AND
NOMINAL BIT TIME
TQ (μs) = (2 * (BRP + 1))/FOSC (MHz)
TBIT (μs) = TQ (μs) * number of TQ per bit interval
Nominal Bit Rate (bits/s) = 1/TBIT
This part of the bit time is used to compensate for
physical delay times within the network. These delay
times consist of the signal propagation time on the bus
line and the internal delay time of the nodes. The length
of the Propagation Segment can be programmed from
1 TQ to 8 TQ by setting the PRSEG2:PRSEG0 bits.
19.7.4
CASE 1:
For FOSC = 16 MHz, BRP = 00h and
Nominal Bit Time = 8 TQ:
TQ = (2 * 1)/16 = 0.125 μs (125 ns)
TBIT = 8 * 0.125 = 1 μs (10-6s)
Nominal Bit Rate = 1/10-6 = 106 bits/s (1 Mb/s)
CASE 2:
For FOSC = 20 MHz, BRP = 01h and
Nominal Bit Time = 8 TQ:
TQ = (2 * 2)/20 = 0.2 μs (200 ns)
TBIT = 8 * 0.2 = 1.6 μs (1.6 * 10-6s)
Nominal Bit Rate = 1/1.6 * 10-6s =
625,000 bits/s
(625 Kb/s)
CASE 3:
For FOSC = 25 MHz, BRP = 3Fh and
Nominal Bit Time = 25 TQ:
TQ = (2 * 64)/25 = 5.12 μs
TBIT = 25 * 5.12 = 128 μs (1.28 * 10-4s)
Nominal Bit Rate = 1/1.28 * 10-4 =
7813 bits/s
(7.8 Kb/s)
The frequencies of the oscillators in the different nodes
must be coordinated in order to provide a system wide
specified nominal bit time. This means that all oscillators must have a TOSC that is an integral divisor of TQ.
It should also be noted that although the number of TQ
is programmable from 4 to 25, the usable minimum is
8 TQ. A bit time of less than 8 TQ in length is not
ensured to operate correctly.
DS41159E-page 234
PROPAGATION SEGMENT
PHASE BUFFER SEGMENTS
The phase buffer segments are used to optimally
locate the sampling point of the received bit within the
nominal bit time. The sampling point occurs between
Phase Segment 1 and Phase Segment 2. These
segments can be lengthened or shortened by the
resynchronization process. The end of Phase Segment
1 determines the sampling point within a bit time.
Phase Segment 1 is programmable from 1 TQ to 8 TQ
in duration. Phase Segment 2 provides delay before
the next transmitted data transition and is also
programmable from 1 TQ to 8 TQ in duration. However,
due to IPT requirements, the actual minimum length of
Phase Segment 2 is 2 TQ or it may be defined to be
equal to the greater of Phase Segment 1 or the
Information Processing Time (IPT).
19.7.5
SAMPLE POINT
The sample point is the point of time at which the bus
level is read and the value of the received bit is determined. The sampling point occurs at the end of Phase
Segment 1. If the bit timing is slow and contains many
TQ, it is possible to specify multiple sampling of the bus
line at the sample point. The value of the received bit is
determined to be the value of the majority decision of
three values. The three samples are taken at the sample point and twice before, with a time of TQ/2 between
each sample.
19.7.6
INFORMATION PROCESSING TIME
The Information Processing Time (IPT) is the time
segment, starting at the sample point, that is reserved
for calculation of the subsequent bit level. The CAN
specification defines this time to be less than or equal
to 2 TQ. The PIC18FXX8 defines this time to be 2 TQ.
Thus, Phase Segment 2 must be at least 2 TQ long.
© 2006 Microchip Technology Inc.
PIC18FXX8
19.8
Synchronization
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time
(Sync_Seg). The circuit will then adjust the values of
Phase Segment 1 and Phase Segment 2, as
necessary. There are two mechanisms used for
synchronization.
19.8.1
HARD SYNCHRONIZATION
Hard synchronization is only done when there is a recessive to dominant edge during a bus Idle condition, indicating the start of a message. After hard
synchronization, the bit time counters are restarted with
Sync_Seg. Hard synchronization forces the edge which
has occurred to lie within the synchronization segment of
the restarted bit time. Due to the rules of synchronization, if a hard synchronization occurs, there will not be a
resynchronization within that bit time.
19.8.2
RESYNCHRONIZATION
As a result of resynchronization, Phase Segment 1
may be lengthened or Phase Segment 2 may be shortened. The amount of lengthening or shortening of the
phase buffer segments has an upper bound given by
the Synchronization Jump Width (SJW). The value of
the SJW will be added to Phase Segment 1 (see
Figure 19-8) or subtracted from Phase Segment 2 (see
Figure 19-9). The SJW is programmable between 1 TQ
and 4 TQ.
Clocking information will only be derived from recessive to dominant transitions. The property, that only a
fixed maximum number of successive bits have the
same value, ensures resynchronization to the bit
stream during a frame.
FIGURE 19-8:
The phase error of an edge is given by the position of
the edge relative to Sync_Seg, measured in TQ. The
phase error is defined in magnitude of TQ as follows:
• e = 0 if the edge lies within Sync_Seg.
• e > 0 if the edge lies before the sample point.
• e < 0 if the edge lies after the sample point of the
previous bit.
If the magnitude of the phase error is less than or equal
to the programmed value of the synchronization jump
width, the effect of a resynchronization is the same as
that of a hard synchronization.
If the magnitude of the phase error is larger than the
synchronization jump width and if the phase error is
positive, then Phase Segment 1 is lengthened by an
amount equal to the synchronization jump width.
If the magnitude of the phase error is larger than the
resynchronization jump width and if the phase error is
negative, then Phase Segment 2 is shortened by an
amount equal to the synchronization jump width.
19.8.3
SYNCHRONIZATION RULES
• Only one synchronization within one bit time is
allowed.
• An edge will be used for synchronization only if
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
• All other recessive to dominant edges, fulfilling
rules 1 and 2, will be used for resynchronization
with the exception that a node transmitting a
dominant bit will not perform a resynchronization
as a result of a recessive to dominant edge with a
positive phase error.
LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1)
Input
Signal
Bit
Time
Segments
Sync
Prop
Segment
Phase
Segment 1
≤ SJW
Phase
Segment 2
TQ
Sample Point
Nominal Bit Length
Actual Bit Length
© 2006 Microchip Technology Inc.
DS41159E-page 235
PIC18FXX8
FIGURE 19-9:
Sync
SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2)
Prop
Segment
Phase
Segment 1
TQ
Phase
Segment 2
≤ SJW
Sample Point
Actual Bit Length
Nominal Bit Length
19.9
Programming Time Segments
Some requirements for programming of the time
segments:
• Prop Seg + Phase Seg 1 ≥ Phase Seg 2
• Phase Seg 2 ≥ Sync Jump Width
For example, assume that a 125 kHz CAN baud rate is
desired using 20 MHz for FOSC. With a TOSC of 50 ns,
a baud rate prescaler value of 04h gives a TQ of 500 ns.
To obtain a nominal bit rate of 125 kHz, the nominal bit
time must be 8 μs or 16 TQ.
Using 1 TQ for the Sync Segment, 2 TQ for the Propagation Segment and 7 TQ for Phase Segment 1 would
place the sample point at 10 TQ after the transition.
This leaves 6 TQ for Phase Segment 2.
By the rules above, the Sync Jump Width could be the
maximum of 4 TQ. However, normally a large SJW is
only necessary when the clock generation of the different nodes is inaccurate or unstable, such as using
ceramic resonators. Typically, an SJW of 1 is enough.
19.10 Oscillator Tolerance
As a rule of thumb, the bit timing requirements allow
ceramic resonators to be used in applications with
transmission rates of up to 125 Kbit/sec. For the full bus
speed range of the CAN protocol, a quartz oscillator is
required. A maximum node-to-node oscillator variation
of 1.7% is allowed.
19.11.1
BRGCON1
The BRP bits control the baud rate prescaler. The
SJW bits select the synchronization jump width in
terms of multiples of TQ.
19.11.2
BRGCON2
The PRSEG bits set the length of the Propagation Segment in terms of TQ. The SEG1PH bits set the length of
Phase Segment 1 in TQ. The SAM bit controls how
many times the RXCAN pin is sampled. Setting this bit
to a ‘1’ causes the bus to be sampled three times; twice
at TQ/2 before the sample point and once at the normal
sample point (which is at the end of Phase Segment 1).
The value of the bus is determined to be the value read
during at least two of the samples. If the SAM bit is set
to a ‘0’, then the RXCAN pin is sampled only once at
the sample point. The SEG2PHTS bit controls how the
length of Phase Segment 2 is determined. If this bit is
set to a ‘1’, then the length of Phase Segment 2 is
determined by the SEG2PH bits of BRGCON3. If the
SEG2PHTS bit is set to a ‘0’, then the length of Phase
Segment 2 is the greater of Phase Segment 1 and the
information processing time (which is fixed at 2 TQ for
the PIC18FXX8).
19.11.3
BRGCON3
The PHSEG2 bits set the length (in TQ) of Phase
Segment 2 if the SEG2PHTS bit is set to a ‘1’. If the
SEG2PHTS bit is set to a ‘0’, then the PHSEG2
bits have no effect.
19.11 Bit Timing Configuration
Registers
The Configuration registers (BRGCON1, BRGCON2,
BRGCON3) control the bit timing for the CAN bus
interface. These registers can only be modified when
the PIC18FXX8 is in Configuration mode.
DS41159E-page 236
© 2006 Microchip Technology Inc.
PIC18FXX8
19.12 Error Detection
19.12.6
The CAN protocol provides sophisticated error detection
mechanisms. The following errors can be detected.
Detected errors are made public to all other nodes via
error frames. The transmission of the erroneous
message is aborted and the frame is repeated as soon
as possible. Furthermore, each CAN node is in one of
the three error states “error-active”, “error-passive” or
“bus-off” according to the value of the internal error
counters. The error-active state is the usual state,
where the bus node can transmit messages and
activate error frames (made of dominant bits) without
any restrictions. In the error-passive state, messages
and passive error frames (made of recessive bits) may
be transmitted. The bus-off state makes it temporarily
impossible for the station to participate in the bus
communication. During this state, messages can
neither be received nor transmitted.
19.12.1
CRC ERROR
With the Cyclic Redundancy Check (CRC), the
transmitter calculates special check bits for the bit
sequence, from the start of a frame until the end of the
data field. This CRC sequence is transmitted in the
CRC field. The receiving node also calculates the CRC
sequence using the same formula and performs a
comparison to the received sequence. If a mismatch is
detected, a CRC error has occurred and an error frame
is generated. The message is repeated.
19.12.2
ACKNOWLEDGE ERROR
In the Acknowledge field of a message, the transmitter
checks if the Acknowledge slot (which was sent out as
a recessive bit) contains a dominant bit. If not, no other
node has received the frame correctly. An Acknowledge Error has occurred; an error frame is generated
and the message will have to be repeated.
19.12.3
FORM ERROR
If a node detects a dominant bit in one of the four
segments, including end of frame, interframe space,
Acknowledge delimiter or CRC delimiter, then a Form
Error has occurred and an error frame is generated.
The message is repeated.
19.12.4
BIT ERROR
A Bit Error occurs if a transmitter sends a dominant bit
and detects a recessive bit, or if it sends a recessive bit
and detects a dominant bit, when monitoring the actual
bus level and comparing it to the just transmitted bit. In
the case where the transmitter sends a recessive bit
and a dominant bit is detected during the arbitration
field and the Acknowledge slot, no Bit Error is
generated because normal arbitration is occurring.
19.12.5
STUFF BIT ERROR
If, between the start of frame and the CRC delimiter, six
consecutive bits with the same polarity are detected,
the bit stuffing rule has been violated. A Stuff Bit Error
occurs and an error frame is generated. The message
is repeated.
© 2006 Microchip Technology Inc.
19.12.7
ERROR STATES
ERROR MODES AND ERROR
COUNTERS
The PIC18FXX8 contains two error counters: the
Receive Error Counter (RXERRCNT) and the Transmit
Error Counter (TXERRCNT). The values of both
counters can be read by the MCU. These counters are
incremented or decremented in accordance with the
CAN bus specification.
The PIC18FXX8 is error-active if both error counters
are below the error-passive limit of 128. It is errorpassive if at least one of the error counters equals or
exceeds 128. It goes to bus-off if the transmit error
counter equals or exceeds the bus-off limit of 256. The
device remains in this state until the bus-off recovery
sequence is received. The bus-off recovery sequence
consists of 128 occurrences of 11 consecutive
recessive bits (see Figure 19-10). Note that the CAN
module, after going bus-off, will recover back to erroractive without any intervention by the MCU if the bus
remains Idle for 128 x 11 bit times. If this is not desired,
the error Interrupt Service Routine should address this.
The current error mode of the CAN module can be read
by the MCU via the COMSTAT register.
Additionally, there is an Error State Warning flag bit,
EWARN, which is set if at least one of the error
counters equals or exceeds the error warning limit of
96. EWARN is reset if both error counters are less than
the error warning limit.
DS41159E-page 237
PIC18FXX8
FIGURE 19-10:
ERROR MODES STATE DIAGRAM
Reset
ErrorActive
RXERRCNT < 127 or
TXERRCNT < 127
128 occurrences of
11 consecutive
“recessive” bits
RXERRCNT > 127 or
TXERRCNT > 127
ErrorPassive
TXERRCNT > 255
BusOff
19.13 CAN Interrupts
19.13.1
The module has several sources of interrupts. Each of
these interrupts can be individually enabled or
disabled. The CANINTF register contains interrupt
flags. The CANINTE register contains the enables for
the 8 main interrupts. A special set of read-only bits in
the CANSTAT register, the ICODE bits, can be used in
combination with a jump table for efficient handling of
interrupts.
The source of a pending interrupt is indicated in the
ICODE (Interrupt Code) bits of the CANSTAT register
(ICODE). Interrupts are internally prioritized such
that the higher priority interrupts are assigned lower
ICODE values. Once the highest priority interrupt condition has been cleared, the code for the next highest
priority interrupt that is pending (if any) will be reflected
by the ICODE bits (see Table 19-3, following page).
Note that only those interrupt sources that have their
associated CANINTE enable bit set will be reflected in
the ICODE bits.
All interrupts have one source, with the exception of the
error interrupt. Any of the error interrupt sources can set
the error interrupt flag. The source of the error interrupt
can be determined by reading the Communication
Status register, COMSTAT.
The interrupts can be broken up into two categories:
receive and transmit interrupts.
The receive related interrupts are:
•
•
•
•
•
Receive Interrupts
Wake-up Interrupt
Receiver Overrun Interrupt
Receiver Warning Interrupt
Receiver Error-Passive Interrupt
The transmit related interrupts are:
•
•
•
•
Transmit Interrupts
Transmitter Warning Interrupt
Transmitter Error-Passive Interrupt
Bus-Off Interrupt
DS41159E-page 238
19.13.2
INTERRUPT CODE BITS
TRANSMIT INTERRUPT
When the transmit interrupt is enabled, an interrupt will
be generated when the associated transmit buffer
becomes empty and is ready to be loaded with a new
message. The TXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU resetting the TXBnIF bit to a ‘0’.
19.13.3
RECEIVE INTERRUPT
When the receive interrupt is enabled, an interrupt will
be generated when a message has been successfully
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving
the EOF field. The RXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU resetting the RXBnIF bit to a ‘0’.
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 19-3:
VALUES FOR ICODE
ICOD
Interrupt
Boolean Expression
000
None
ERR•WAK•TX0•TX1•TX2•RX0•
RX1
001
Error
ERR
010
TXB2
ERR•TX0•TX1•TX2
011
TXB1
ERR•TX0•TX1
100
TXB0
ERR•TX0
101
RXB1
ERR•TX0•TX1•TX2•RX0•RX1
110
RXB0
ERR•TX0•TX1•TX2•RX0
111
Wake on
Interrupt
ERR•TX0•TX1•TX2•RX0•RX1•
WAK
Key:
ERR = ERRIF * ERRIE RX0 = RXB0IF * RXB0IE
TX0 = TXB0IF * TXB0IE RX1 = RXB1IF * RXB1IE
TX1 = TXB1IF * TXB1IE WAK = WAKIF * WAKIE
TX2 = TXB2IF * TXB2IE
19.13.6
When the error interrupt is enabled, an interrupt is
generated if an overflow condition occurs or if the error
state of transmitter or receiver has changed. The error
flags in COMSTAT will indicate one of the following
conditions.
19.13.6.1
MESSAGE ERROR INTERRUPT
When an error occurs during transmission or reception
of a message, the message error flag IRXIF will be set
and if the IRXIE bit is set, an interrupt will be generated.
This is intended to be used to facilitate baud rate
determination when used in conjunction with Listen
Only mode.
19.13.5
BUS ACTIVITY WAKE-UP
INTERRUPT
When the PIC18FXX8 is in Sleep mode and the bus
activity wake-up interrupt is enabled, an interrupt will be
generated and the WAKIF bit will be set when activity is
detected on the CAN bus. This interrupt causes the
PIC18FXX8 to exit Sleep mode. The interrupt is reset
by the MCU, clearing the WAKIF bit.
© 2006 Microchip Technology Inc.
Receiver Overflow
An overflow condition occurs when the MAB has
assembled a valid received message (the message
meets the criteria of the acceptance filters) and the
receive buffer associated with the filter is not available
for loading of a new message. The associated
COMSTAT.RXnOVFL bit will be set to indicate the
overflow condition. This bit must be cleared by the
MCU.
19.13.6.2
Receiver Warning
The receive error counter has reached the MCU
warning limit of 96.
19.13.6.3
Transmitter Warning
The transmit error counter has reached the MCU
warning limit of 96.
19.13.6.4
19.13.4
ERROR INTERRUPT
Receiver Bus Passive
The receive error counter has exceeded the errorpassive limit of 127 and the device has gone to
error-passive state.
19.13.6.5
Transmitter Bus Passive
The transmit error counter has exceeded the errorpassive limit of 127 and the device has gone to
error-passive state.
19.13.6.6
Bus-Off
The transmit error counter has exceeded 255 and the
device has gone to bus-off state.
19.13.7
INTERRUPT ACKNOWLEDGE
Interrupts are directly associated with one or more
status flags in the PIR register. Interrupts are pending
as long as one of the flags is set. Once an interrupt flag
is set by the device, the flag cannot be reset by the
microcontroller until the interrupt condition is removed.
DS41159E-page 239
PIC18FXX8
NOTES:
DS41159E-page 240
© 2006 Microchip Technology Inc.
PIC18FXX8
20.0
COMPATIBLE 10-BIT ANALOGTO-DIGITAL CONVERTER (A/D)
MODULE
The Analog-to-Digital (A/D) Converter module has five
inputs for the PIC18F2X8 devices and eight for the
PIC18F4X8 devices. This module has the ADCON0
and ADCON1 register definitions that are compatible
with the PICmicro® mid-range A/D module.
The A/D allows conversion of an analog input signal to
a corresponding 10-bit digital number.
REGISTER 20-1:
The A/D module has four registers. These registers are:
•
•
•
•
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
The ADCON0 register, shown in Register 20-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 20-2, configures
the functions of the port pins.
ADCON0: A/D CONTROL REGISTER 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
bit 7
bit 7-6
bit 5-3
bit 0
ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)
ADCON1
ADCON0
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
Clock Conversion
FOSC/2
FOSC/8
FOSC/32
FRC (clock derived from the internal A/D RC oscillator)
FOSC/4
FOSC/16
FOSC/64
FRC (clock derived from the internal A/D RC oscillator)
CHS2:CHS0: Analog Channel Select bits
000 = Channel 0 (AN0)
001 = Channel 1 (AN1)
010 = Channel 2 (AN2)
011 = Channel 3 (AN3)
100 = Channel 4 (AN4)
101 = Channel 5 (AN5)(1)
110 = Channel 6 (AN6)(1)
111 = Channel 7 (AN7)(1)
Note 1: These channels are unimplemented on PIC18F2X8 (28-pin) devices. Do not select
any unimplemented channel.
bit 2
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically
cleared by hardware when the A/D conversion is complete)
0 = A/D conversion not in progress
Unimplemented: Read as ‘0’
ADON: A/D On bit
1 = A/D converter module is powered up
0 = A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 241
PIC18FXX8
REGISTER 20-2:
ADCON1: A/D CONTROL REGISTER 1
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ‘0’.
bit 6
ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)
ADCON1
ADCON0
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
Clock Conversion
FOSC/2
FOSC/8
FOSC/32
FRC (clock derived from the internal A/D RC oscillator)
FOSC/4
FOSC/16
FOSC/64
FRC (clock derived from the internal A/D RC oscillator)
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits
PCFG
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
VREF+
VREF-
C/R
0000
A
A
A
A
A
A
A
A
VDD
VSS
8/0
0001
A
A
A
A
VREF+
A
A
A
AN3
VSS
7/1
0010
D
D
D
A
A
A
A
A
VDD
VSS
5/0
0011
D
D
D
A
VREF+
A
A
A
AN3
VSS
4/1
0100
D
D
D
D
A
D
A
A
VDD
VSS
3/0
0101
D
D
D
D
VREF+
D
A
A
AN3
VSS
2/1
011x
D
D
D
D
D
D
D
D
—
—
0/0
1000
A
A
A
A
VREF+
VREF-
A
A
AN3
AN2
6/2
1001
D
D
A
A
A
A
A
A
VDD
VSS
6/0
1010
D
D
A
A
VREF+
A
A
A
AN3
VSS
5/1
1011
D
D
A
A
VREF+
VREF-
A
A
AN3
AN2
4/2
1100
D
D
D
A
VREF+
VREF-
A
A
AN3
AN2
3/2
1101
D
D
D
D
VREF+
VREF-
A
A
AN3
AN2
2/2
1110
D
D
D
D
D
D
D
A
VDD
VSS
1/0
1111
D
D
D
D
VREF+
VREF-
D
A
AN3
AN2
1/2
A = Analog input D = Digital I/O
C/R = # of analog input channels/# of A/D voltage references
Note:
Shaded cells indicate channels available only on PIC18F4X8 devices.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Note:
DS41159E-page 242
x = Bit is unknown
On any device Reset, the port pins that are multiplexed with analog functions (ANx)
are forced to be analog inputs.
© 2006 Microchip Technology Inc.
PIC18FXX8
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS) or the voltage level on the RA3/AN3/
VREF+ pin and RA2/AN2/VREF- pin.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter which generates the result via successive
approximation.
FIGURE 20-1:
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input (RA3 can also be a
voltage reference) or as a digital I/O.
The ADRESH and ADRESL registers contain the result
of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/ADRESL
registers, the GO/DONE bit (ADCON0) is cleared
and A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 20-1.
A/D BLOCK DIAGRAM
CHS2:CHS0
111
AN7(1)
110
AN6(1)
101
AN5(1)
100
VAIN
011
(Input Voltage)
010
10-bit
Converter
A/D
001
PCFG0
000
VDD
AN4
AN3
AN2
AN1
AN0
VREF+
Reference
voltage
VREF-
VSS
Note 1: Channels AN5 through AN7 are not available on PIC18F2X8 devices.
2: All I/O pins have diode protection to VDD and VSS.
© 2006 Microchip Technology Inc.
DS41159E-page 243
PIC18FXX8
The value that is in the ADRESH/ADRESL registers is
not modified for a Power-on Reset. The ADRESH/
ADRESL registers will contain unknown data after a
Power-on Reset.
6.
7.
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 20.1
“A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be
started. The following steps should be followed for
doing an A/D conversion:
1.
2.
3.
4.
5.
Read A/D Result registers (ADRESH/ADRESL);
clear bit ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
20.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 20-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
OR
• Waiting for the A/D interrupt
FIGURE 20-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
Rs
ANx
RIC ≤ 1k
CPIN
VAIN
5 pF
VT = 0.6V
SS
RSS
I LEAKAGE
± 500 nA
CHOLD = 120 pF
VSS
Legend: CPIN
= input capacitance
VT
= threshold voltage
I LEAKAGE = leakage current at the pin due to
various junctions
RIC
SS
CHOLD
DS41159E-page 244
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
VDD
6V
5V
4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch (kΩ)
© 2006 Microchip Technology Inc.
PIC18FXX8
To calculate the minimum acquisition time,
Equation 20-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 20-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system assumptions:
•
•
•
•
•
•
CHOLD
Rs
Conversion Error
VDD
Temperature
VHOLD
EQUATION 20-1:
TACQ
120 pF
2.5 kΩ
1/2 LSb
5V → Rss = 7 kΩ
50°C (system max.)
0V @ time = 0
ACQUISITION TIME
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 20-2:
VHOLD
or
Tc
=
A/D MINIMUM CHARGING TIME
=
(VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS)))
=
-(120 pF)(1 kΩ + RSS + RS) ln(1/2047)
EXAMPLE 20-1:
TACQ
=
=
≤
=
=
=
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25°C.
TACQ
=
2 μs + TC + [(Temp – 25°C)(0.05 μs/°C)]
TC
=
-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004885)
-120 pF (10.5 kΩ) ln(0.0004885)
-1.26 μs (-7.6241)
9.61 μs
TACQ
=
2 μs + 9.61 μs + [(50°C – 25°C)(0.05 μs/°C)]
11.61 μs + 1.25 μs
12.86 μs
Note:
When using external voltage references with the A/D converter, the source impedance of the external
voltage references must be less than 20Ω to obtain the specified A/D resolution. Higher reference source
impedances will increase both offset and gain errors. Resistive voltage dividers will not provide a sufficiently
low source impedance.
To maintain the best possible performance in A/D conversions, external VREF inputs should be buffered with
an operational amplifier or other low output impedance circuit.
© 2006 Microchip Technology Inc.
DS41159E-page 245
PIC18FXX8
20.2
Selecting the A/D Conversion
Clock
20.3
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 12 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. The seven possible options for TAD are:
•
•
•
•
•
•
•
Configuring Analog Port Pins
The ADCON1, TRISA and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their corresponding
TRIS bits set (input). If the TRIS bit is cleared (output),
the digital output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal RC oscillator.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 μs.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN4:AN0
pins) may cause the input buffer to
consume current that is out of the
device’s specification.
Table 20-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 20-1:
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Operation
ADCS2:ADCS0
Device Frequency
20 MHz
ns(2)
5 MHz
ns(2)
1.25 MHz
333.33 kHz
2 TOSC
000
100
1.6 μs
6 μs
4 TOSC
100
200 ns(2)
800 ns(2)
3.2 μs
12 μs
8 TOSC
001
400 ns(2)
1.6 μs
6.4 μs
24 μs(3)
16 TOSC
101
ns(2)
3.2 μs
12.8 μs
48 μs(3)
32 TOSC
010
6.4 μs
25.6 μs(3)
96 μs(3)
μs(3)
192 μs(3)
2-6 μs(1)
800
1.6 μs
400
64 TOSC
110
3.2 μs
12.8 μs
51.2
RC
011
2-6 μs(1)
2-6 μs(1)
2-6 μs(1)
Legend:
Note 1:
2:
3:
Shaded cells are outside of recommended range.
The RC source has a typical TAD time of 4 μs.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
TABLE 20-2:
TAD vs. DEVICE OPERATING FREQUENCIES (FOR EXTENDED, LF DEVICES)
AD Clock Source (TAD)
Operation
2 TOSC
ADCS2:ADCS0
000
Device Frequency
4 MHz
500
ns(2)
μs(2)
2 MHz
1.0
μs(2)
2.0
μs(2)
1.25 MHz
1.6
μs(2)
3.2
μs(2)
333.33 kHz
6 μs
12 μs
4 TOSC
100
1.0
8 TOSC
001
2.0 μs(2)
4.0 μs
6.4 μs
24 μs(3)
16 TOSC
101
4.0 μs(2)
8.0 μs
12.8 μs
48 μs(3)
μs(3)
96 μs(3)
192 μs(3)
32 TOSC
010
8.0 μs
16.0 μs
25.6
64 TOSC
110
16.0 μs
32.0 μs
51.2 μs(3)
011
(1)
(1)
RC
Legend:
Note 1:
2:
3:
3-9 μs
3-9 μs
(1)
3-9 μs
3-9 μs(1)
Shaded cells are outside of recommended range.
The RC source has a typical TAD time of 6 μs.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
DS41159E-page 246
© 2006 Microchip Technology Inc.
PIC18FXX8
20.4
20.4.1
A/D Conversions
Figure 20-4 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conversion. The A/D Result register pair will not be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL
registers). After the A/D conversion is aborted, a 2 TAD
wait is required before the next acquisition is started.
After this 2 TAD wait, acquisition on the selected
channel is automatically started.
Note:
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16 bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 20-3 shows the operation of the A/D result justification. The extra bits are loaded with ‘0’s. When an
A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 20-3:
A/D RESULT JUSTIFICATION
10-bit Result
ADFM = 0
ADFM = 1
7
0
2107
7
0765
0000 00
0000 00
ADRESH
ADRESL
10-bit Result
Right Justified
© 2006 Microchip Technology Inc.
0
ADRESH
ADRESL
10-bit Result
Left Justified
DS41159E-page 247
PIC18FXX8
20.5
Use of the ECCP Trigger
acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location). The
appropriate analog input channel must be selected and
the minimum acquisition done before the “special event
trigger” sets the GO/DONE bit (starts a conversion).
An A/D conversion can be started by the “special event
trigger” of the ECCP module. This requires that the
ECCP1M3:ECCP1M0 bits (ECCP1CON) be programmed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion and the
Timer1 (or Timer3) counter will be reset to zero. Timer1
(or Timer3) is reset to automatically repeat the A/D
FIGURE 20-4:
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
A/D CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9
b8
b7
b6
b4
b5
b3
b1
b2
b0
b0
Conversion Starts
Holding capacitor is disconnected from analog input
(typically 100 ns)
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Set GO bit
TABLE 20-3:
Name
INTCON
SUMMARY OF A/D REGISTERS
Bit 7
Bit 6
GIE/GIEH PEIE/GIEL
Value on
all other
Resets
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
(1)
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111 1111 1111
PIR2
—
CMIF(1)
—
EEIF
BCLIF
LVDIF
TMR3IF
PIE2
—
CMIE(1)
—
EEIE
BCLIE
LVDIE
TMR3IE ECCP1IE(1) -0-0 0000 -0-0 0000
—
CMIP(1)
—
EEIP
BCLIP
LVDIP
TMR3IP ECCP1IP(1) -1-1 1111 -1-1 1111
IPR2
ECCP1IF(1) -0-0 0000 -0-0 0000
ADRESH
A/D Result Register
xxxx xxxx uuuu uuuu
ADRESL
A/D Result Register
xxxx xxxx uuuu uuuu
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0 0000 00-0
ADCON1
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
00-- 0000 00-- 0000
PORTA
—
RA6
RA5
RA4
RA3
RA2
RA1
RA0
-x0x 0000 -u0u 0000
TRISA
—
PORTE
—
—
—
—
—
RE2
RE1
RE0
LATE
—
—
—
—
—
LATE2
LATE1
LATE0
---- -xxx ---- -uuu
TRISE
IBF
OBF
IBOV
PSPMODE
—
TRISE2
TRISE1
TRISE0
0000 -111 0000 -111
Legend:
Note 1:
PORTA Data Direction Register
-111 1111 -111 1111
---- -xxx ---- -000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
These bits are reserved on PIC18F2X8 devices; always maintain these bits clear.
DS41159E-page 248
© 2006 Microchip Technology Inc.
PIC18FXX8
21.0
Note:
COMPARATOR MODULE
The analog comparators are
available on the PIC18F448
PIC18F458.
only
and
The CMCON register, shown in Register 21-1, controls
the comparator input and output multiplexers. A block
diagram of the comparator is shown in Figure 21-1.
The comparator module contains two analog comparators. The inputs to the comparators are
multiplexed with the RD0 through RD3 pins. The on-chip
voltage reference (Section 22.0 “Comparator Voltage
Reference Module”) can also be an input to the
comparators.
REGISTER 21-1:
CMCON: COMPARATOR CONTROL REGISTER
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
bit 7
bit 7
bit 0
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1:
1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1:
1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VIN-
bit 5
C2INV: Comparator 2 Output Inversion bit
1 = C2 output inverted
0 = C2 output not inverted
bit 4
C1INV: Comparator 1 Output Inversion bit
1 = C1 output inverted
0 = C1 output not inverted
bit 3
CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1 = C1 VIN- connects to RD0/PSP0
C2 VIN- connects to RD2/PSP2
0 = C1 VIN- connects to RD1/PSP1
C2 VIN- connects to RD3/PSP3
bit 2-0
CM2:CM0: Comparator Mode bits
Figure 21-1 shows the Comparator modes and CM2:CM0 bit settings.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 249
PIC18FXX8
21.1
Comparator Configuration
There are eight modes of operation for the comparators. The CMCON register is used to select these
modes. Figure 21-1 shows the eight possible modes.
The TRISD register controls the data direction of the
comparator pins for each mode. If the Comparator
FIGURE 21-1:
A
VIN-
RD0/PSP0 A
VIN+
A
VIN-
RD3/PSP3
RD2/PSP2 A
Comparator interrupts should be disabled
during a Comparator mode change;
otherwise, a false interrupt may occur.
VIN+
A
VIN-
RD0/PSP0 A
VIN+
Comparators Off
CM2:CM0 = 111
D
VIN-
RD0/PSP0 D
VIN+
D
VIN-
RD2/PSP2 D
VIN+
RD1/PSP1
C1
Off (Read as ‘0’)
C2
Off (Read as ‘0’)
RD3/PSP3
RD1/PSP1
C1
C1
Off (Read as ‘0’)
C2
Off (Read as ‘0’)
Two Independent Comparators with Outputs
CM2:CM0 = 011
Two Independent Comparators
CM2:CM0 = 010
RD1/PSP1
Note:
COMPARATOR I/O OPERATING MODES
Comparators Reset (POR Default Value)
CM2:CM0 = 000
RD1/PSP1
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
Section 27.0 “Electrical Characteristics”.
C1OUT
RD0/PSP0
A
VIN-
A
VIN+
C1
C1OUT
C2
C2OUT
RE1/AN6/WR/C1OUT
RD3/PSP3
RD2/PSP2
A
VIN-
A
VIN+
C2
C2OUT
RD3/PSP3
RD2/PSP2
A
VIN-
A
VIN+
RE2/AN7/CS/C2OUT
Two Common Reference Comparators
CM2:CM0 = 100
RD1/PSP1
A
RD0/PSP0 A
Two Common Reference Comparators with Outputs
CM2:CM0 = 101
VINVIN+
A
VIN-
RD0/PSP0 A
VIN+
RD1/PSP1
C1
C1OUT
C1
C1OUT
C2
C2OUT
RE1/AN6/WR/
C1OUT
A
VIN-
RD2/PSP2 D
VIN+
RD3/PSP3
C2
C2OUT
A
VIN-
RD2/PSP2 D
VIN+
RD3/PSP3
RE2/AN7/CS/C2OUT
One Independent Comparator with Output
CM2:CM0 = 001
A
VIN-
RD0/PSP0 A
VIN+
RD1/PSP1
RD1/PSP1
C1
C1OUT
RE1/AN6/WR/C1OUT
D
VIN-
RD2/PSP2 D
VIN+
RD3/PSP3
Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 110
A
RD0/PSP0 A
RD3/PSP3
VINVIN+
C1
C1OUT
C2
C2OUT
A
RD2/PSP2 A
C2
CIS = 0
CIS = 1
CIS = 0
CIS = 1
VINVIN+
Off (Read as ‘0’)
CVREF
From VREF Module
A = Analog Input, port reads zeros always
D = Digital Input
CIS (CMCON) is the Comparator Input Switch
DS41159E-page 250
© 2006 Microchip Technology Inc.
PIC18FXX8
21.2
21.3.2
Comparator Operation
A single comparator is shown in Figure 21-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 21-2 represent
the uncertainty due to input offsets and response time.
The comparator module also allows the selection of an
internally generated voltage reference for the comparators. Section 22.0 “Comparator Voltage Reference
Module” contains a detailed description of the module
that provides this signal. The internal reference signal is
used when comparators are in mode CM = 110
(Figure 21-1). In this mode, the internal voltage
reference is applied to the VIN+ pin of both comparators.
21.4
21.3
Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal present at VIN- is compared to the signal
at VIN+ and the digital output of the comparator is
adjusted accordingly (Figure 21-2).
FIGURE 21-2:
SINGLE COMPARATOR
VIN-
+
-
Output
VIN
VIN–
VIN
+
VIN+
Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (Section 27.0
“Electrical Characteristics”).
21.5
VIN+
INTERNAL REFERENCE SIGNAL
Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RE1 and RE2
I/O pins. When enabled, multiplexors in the output path
of the RE1 and RE2 pins will switch and the output of
each pin will be the unsynchronized output of the
comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 21-3 shows the comparator output block
diagram.
The TRISE bits will still function as an output enable/
disable for the RE1 and RE2 pins while in this mode.
Output
Output
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON).
21.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the comparators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
© 2006 Microchip Technology Inc.
Note 1: When reading the Port register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin defined as a digital input may cause the input buffer to
consume more current than is specified.
DS41159E-page 251
PIC18FXX8
FIGURE 21-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
+
CxINV
To RE1 or
RE2 pin
Bus
Data
Q
Read CMCON
Set
CMIF
bit
D
EN
Q
From
Other
Comparator
D
EN
CL
Read CMCON
Reset
21.6
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON, to
determine the actual change that occurred. The CMIF
bit (PIR2 register) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing ‘0’. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE2 register) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
DS41159E-page 252
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2
register) interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of CMCON will end the
mismatch condition.
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
© 2006 Microchip Technology Inc.
PIC18FXX8
21.7
Comparator Operation During
Sleep
21.8
A device Reset forces the CMCON register to its Reset
state, causing the comparator module to be in the
Comparator Reset mode, CM = 000. This
ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at Reset time. The comparators will be
powered down during the Reset interval.
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
While the comparator is powered up, higher Sleep
currents than shown in the power-down current
specification will occur. Each operational comparator
will consume additional current, as shown in the comparator specifications. To minimize power consumption
while in Sleep mode, turn off the comparators,
CM = 111, before entering Sleep. If the device
wakes up from Sleep, the contents of the CMCON
register are not affected.
FIGURE 21-4:
Effects of a Reset
21.9
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 21-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
ANALOG INPUT MODEL
VDD
VT = 0.6V
RS < 10k
RIC
AIN
CPIN
5 pF
VA
VT = 0.6V
I LEAKAGE
±500 nA
VSS
Legend:
CPIN
VT
I LEAKAGE
RIC
RS
VA
© 2006 Microchip Technology Inc.
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the pin due to various junctions
Interconnect Resistance
Source Impedance
Analog Voltage
DS41159E-page 253
PIC18FXX8
TABLE 21-1:
Name
CMCON
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
C2OUT C1OUT C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000 0000 0000
CVRCON CVREN CVROE CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
0000 0000 0000 0000
INTCON
TMR0IF INT0IF
RBIF
0000 000x 0000 000u
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
PIR2
—
CMIF(1)
—
EEIF
BCLIF
LVDIF
PIE2
—
CMIE(1)
—
EEIE
BCLIE
LVDIE TMR3IE ECCP1IE(1) -0-0 0000 -0-0 0000
—
(1)
—
EEIP
BCLIP
LVDIP TMR3IP ECCP1IP(1) -1-1 1111 -1-1 1111
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx xxxx uuuu uuuu
IPR2
PORTD
RD7
CMIP
RD6
LATD
LATD7 LATD6
TRISD
PORTD Data Direction Register
TMR3IF ECCP1IF(1) -0-0 0000 -0-0 0000
1111 1111 1111 1111
PORTE
—
—
—
—
—
RE2
RE1
RE0
---- -xxx ---- -000
LATE
—
—
—
—
—
LATE2
LATE1
LATE0
---- -xxx ---- -uuu
TRISE
IBF(1)
OBF(1)
IBOV(1)
PSPMODE(1)
—
TRISE2 TRISE1
TRISE0
0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’
Note 1: These bits are reserved on PIC18F2X8 devices; always maintain these bits clear.
DS41159E-page 254
© 2006 Microchip Technology Inc.
PIC18FXX8
22.0
Note:
COMPARATOR VOLTAGE
REFERENCE MODULE
22.1
The comparator voltage reference is only
available on the PIC18F448 and
PIC18F458.
This module is a 16-tap resistor ladder network that
provides a selectable voltage reference. The resistor
ladder is segmented to provide two ranges of CVREF
values and has a power-down function to conserve
power when the reference is not being used. The
CVRCON register controls the operation of the
reference, as shown in Register 22-1. The block
diagram is shown in Figure 22-1.
The comparator and reference supply voltage can
come from either VDD and VSS, or the external VREF+
and VREF-, that are multiplexed with RA3 and RA2. The
comparator reference supply voltage is controlled by
the CVRSS bit.
Configuring the Comparator
Voltage Reference
The comparator voltage reference can output 16 distinct
voltage levels for each range. The equations used to
calculate the output of the comparator voltage reference
are as follows.
EQUATION 22-1:
If CVRR = 1:
CVREF = (CVR/24) x CVRSRC
where:
CVRSS = 1, CVRSRC = (VREF+) – (VREF-)
CVRSS = 0, CVRSRC = AVDD – AVSS
EQUATION 22-2:
If CVRR = 0:
CVREF = (CVRSRC x 1/4) + (CVR/32) x CVRSRC
where:
CVRSS = 1, CVRSRC = (VREF+) – (VREF-)
CVRSS = 0, CVRSRC = AVDD – AVSS
The settling time of the Comparator Voltage Reference
must be considered when changing the RA0/AN0/
CVREF output (see Table 27-4 in Section 27.2 “DC
Characteristics”).
REGISTER 22-1:
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down
bit 6
CVROE: Comparator VREF Output Enable bit
1 = CVREF voltage level is also output on the RA0/AN0/CVREF pin
0 = CVREF voltage is disconnected from the RA0/AN0/CVREF pin
bit 5
CVRR: Comparator VREF Range Selection bit
1 = 0.00 CVRSRC to 0.625 CVRSRC with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.719 CVRSRC with CVRSRC/32 step size
bit 4
CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator reference source, CVRSRC = VDD – VSS
bit 3-0
CVR: Comparator VREF Value Selection 0 ≤ CVR3:CVR0 ≤ 15 bits
When CVRR = 1:
CVREF = (CVR3:CVR0/24) • (CVRSRC)
When CVRR = 0:
CVREF = 1/4 • (CVRSRC) + (CVR3:CVR0/32) • (CVRSRC)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 255
PIC18FXX8
FIGURE 22-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
VDD VREF+
CVRSS = 1
CVREN
16 Stages
CVRSS = 0
8R
R
R
R
R
CVRR
8R
CVRSS = 1
CVRSS = 0
RA0/AN0/CVREF
or CVREF of Comparator
22.2
16-to-1 Analog MUX
Voltage Reference Accuracy/Error
22.4
RA2/AN2/VREFCVR3
(From CVRCON)
CVR0
Effects of a Reset
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 22-1) keep VREF from approaching the reference source rails. The voltage reference is derived
from the reference source; therefore, the VREF output
changes with fluctuations in that source. The absolute
accuracy of the voltage reference can be found in
Section 27.0 “Electrical Characteristics”.
A device Reset disables the voltage reference by
clearing bit CVREN (CVRCON register). This Reset
also disconnects the reference from the RA2 pin by
clearing bit CVROE (CVRCON register) and selects the
high-voltage range by clearing bit CVRR (CVRCON
register). The CVRSS value select bits, CVRCON,
are also cleared.
22.3
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA0/AN0 pin if the
TRISA bit is set and the CVROE bit (CVRCON)
is set. Enabling the voltage reference output onto the
RA0/AN0 pin, with an input signal present, will increase
current consumption. Connecting RA0/AN0 as a digital
output, with CVRSS enabled, will also increase current
consumption.
Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
22.5
Connection Considerations
The RA0/AN0 pin can be used as a simple D/A output
with limited drive capability. Due to the limited current
drive capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 22-2 shows an example buffering technique.
DS41159E-page 256
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 22-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
R(1)
CVREF
Module
RA0/AN0
•
+
–
•
CVREF Output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the voltage reference configuration CVRCON and CVRCON.
TABLE 22-1:
Name
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
CVRCON
CVREN CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
0000 0000 0000 0000
CMCON
C2OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000 0000 0000
TRISA
—
C1OUT
TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -111 1111 -111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’.
Shaded cells are not used with the comparator voltage reference.
© 2006 Microchip Technology Inc.
DS41159E-page 257
PIC18FXX8
NOTES:
DS41159E-page 258
© 2006 Microchip Technology Inc.
PIC18FXX8
23.0
LOW-VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application
software can do “housekeeping tasks” before the
device voltage exits the valid operating range. This can
be done using the Low-Voltage Detect module.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When the voltage of the device becomes lower than the
specified point, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the
interrupt vector address and the software can then
respond to that interrupt source.
The Low-Voltage Detect circuitry is completely under
software control. This allows the circuitry to be “turned
off” by the software which minimizes the current
consumption for the device.
The block diagram for the LVD module is shown in
Figure 23-2. A comparator uses an internally generated reference voltage as the set point. When the
selected tap output of the device voltage crosses the
set point (is lower than), the LVDIF bit is set.
Each node in the resistor divider represents a “trip point”
voltage. The “trip point” voltage is the minimum supply
voltage level at which the device can operate before the
LVD module asserts an interrupt. When the supply
voltage is equal to the trip point, the voltage tapped off of
the resistor array is equal to the internal reference
voltage generated by the voltage reference module. The
comparator then generates an interrupt signal, setting
the LVDIF bit. This voltage is software programmable to
any one of 16 values (see Figure 23-2). The trip point is
selected by programming the LVDL3:LVDL0 bits
(LVDCON).
TYPICAL LOW-VOLTAGE DETECT APPLICATION
Voltage
FIGURE 23-1:
Figure 23-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage VA,
the LVD logic generates an interrupt. This occurs at
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to shutdown the system. Voltage point VB is the
minimum valid operating voltage specification. This
occurs at time TB. The difference TB – TA is the total
time for shutdown.
VA
VB
Legend:
VA = LVD trip point
VB = Minimum valid device
operating voltage
Time
© 2006 Microchip Technology Inc.
TA
TB
DS41159E-page 259
PIC18FXX8
FIGURE 23-2:
LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM
LVDIN
LVDL3:LVDL0
LVDCON
Register
16-to-1 MUX
VDD
Internally Generated
Reference Voltage,
1.2V Typical
LVDEN
The LVD module has an additional feature that allows
the user to supply the trip voltage to the module from an
external source. This mode is enabled when bits
LVDL3:LVDL0 are set to ‘1111’. In this state, the comparator input is multiplexed from the external input pin
LVDIN to one input of the comparator (Figure 23-3).
FIGURE 23-3:
LVDIF
The other input is connected to the internally generated
voltage reference (parameter #D423 in Section 27.2
“DC Characteristics”). This gives users flexibility,
because it allows them to configure the Low-Voltage
Detect interrupt to occur at any voltage in the valid
operating range.
LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD
VDD
LVDCON
Register
16-to-1 MUX
LVDL3:LVDL0
LVDIN
Externally Generated
Trip Point
LVDEN
LVD
VxEN
BODEN
EN
BGAP
DS41159E-page 260
© 2006 Microchip Technology Inc.
PIC18FXX8
23.1
Control Register
The Low-Voltage Detect Control register controls the
operation of the Low Voltage Detect circuitry.
REGISTER 23-1:
LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER
U-0
U-0
R-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
—
—
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5
IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified
voltage range
0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
bit 4
LVDEN: Low-Voltage Detect Power Enable bit
1 = Enables LVD, powers up LVD circuit
0 = Disables LVD, powers down LVD circuit
bit 3-0
LVDL3:LVDL0: Low-Voltage Detection Limit bits
1111 = External analog input is used (input comes from the LVDIN pin)
1110 = 4.45V min.-4.83V max.
1101 = 4.16V min.-4.5V max.
1100 = 3.96V min.-4.2V max.
1011 = 3.76V min.-4.08V max.
1010 = 3.57V min.-3.87V max.
1001 = 3.47V min.-3.75V max.
1000 = 3.27V min.-3.55V max.
0111 = 2.98V min.-3.22V max.
0110 = 2.77V min.-3.01V max.
0101 = 2.67V min.-2.89V max.
0100 = 2.48V min.-2.68V max.
0011 = 2.37V min.-2.57V max.
0010 = 2.18V min.-2.36V max.
0001 = 1.98V min.-2.14V max.
0000 = Reserved
Note:
LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage
of the device, are not tested.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
x = Bit is unknown
DS41159E-page 261
PIC18FXX8
23.2
Operation
The following steps are needed to set up the LVD
module:
Depending on the power source for the device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be
constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for
short periods where the voltage is checked. After doing
the check, the LVD module may be disabled.
1.
2.
3.
Each time that the LVD module is enabled, the circuitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
4.
5.
6.
Write the value to the LVDL3:LVDL0 bits
(LVDCON register) which selects the desired
LVD trip point.
Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
Enable the LVD module (set the LVDEN bit in
the LVDCON register).
Wait for the LVD module to stabilize (the IRVST
bit to become set).
Clear the LVD interrupt flag, which may have
falsely become set, until the LVD module has
stabilized (clear the LVDIF bit).
Enable the LVD interrupt (set the LVDIE and the
GIE bits).
Figure 23-4 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 23-4:
LOW-VOLTAGE DETECT WAVEFORMS
CASE 1:
LVDIF may not be set
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
TIRVST
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
TIRVST
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since LVD condition still exists
DS41159E-page 262
© 2006 Microchip Technology Inc.
PIC18FXX8
23.2.1
REFERENCE VOLTAGE SET POINT
The internal reference voltage of the LVD module may be
used by other internal circuitry (the Programmable
Brown-out Reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires a time to become stable before a low-voltage
condition can be reliably detected. This time is invariant
of system clock speed. This start-up time is specified in
electrical specification parameter #36. The low-voltage
interrupt flag will not be enabled until a stable reference
voltage is reached. Refer to the waveform in Figure 23-4.
23.2.2
CURRENT CONSUMPTION
23.3
Operation During Sleep
When enabled, the LVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wakeup from Sleep. Device execution will continue from the
interrupt vector address if interrupts have been globally
enabled.
23.4
Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the LVD module to be turned off.
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
© 2006 Microchip Technology Inc.
DS41159E-page 263
PIC18FXX8
NOTES:
DS41159E-page 264
© 2006 Microchip Technology Inc.
PIC18FXX8
24.0
SPECIAL FEATURES OF
THE CPU
Sleep mode is designed to offer a very Low-Current
Power-Down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits is used to select various options.
There are several features intended to maximize
system reliability, minimize cost through elimination of
external components, provide power-saving operating
modes and offer code protection. These are:
• Oscillator Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming
24.1
The configuration bits can be programmed (read as ‘0’)
or left unprogrammed (read as ‘1’), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh)
which can only be accessed using table reads and
table writes.
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
EECON1 register WR bit starts a self-timed write to the
Configuration register. In normal operation mode, a
TBLWT instruction, with the TBLPTR pointed to the
Configuration register, sets up the address and the
data for the Configuration register write. Setting the WR
bit starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell.
All PIC18FXX8 devices have a Watchdog Timer which
is permanently enabled via the configuration bits or
software controlled. It runs off its own RC oscillator for
added reliability. There are two timers that offer
necessary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
Reset until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT) which provides a fixed
delay on power-up only, designed to keep the part in
Reset while the power supply stabilizes. With these two
timers on-chip, most applications need no external
Reset circuitry.
TABLE 24-1:
Configuration Bits
CONFIGURATION BITS AND DEVICE IDS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
—
FOSC2
FOSC1
FOSC0
--1- -111
300001h
CONFIG1H
—
—
OSCSEN
—
300002h
CONFIG2L
—
—
—
—
BORV1
BORV0
BOREN
PWRTEN
---- 1111
300003h
CONFIG2H
—
—
—
—
WDTPS2
WDTPS1
WDTPS0
WDTEN
---- 1111
300006h
CONFIG4L
DEBUG
—
—
—
—
LVP
—
STVREN
1--- -1-1
300008h
CONFIG5L
—
—
—
—
CP3
CP2
CP1
CP0
---- 1111
300009h
CONFIG5H
CPD
CPB
—
—
—
—
—
—
11-- ----
30000Ah
CONFIG6L
—
—
—
—
WRT3
WRT2
WRT1
WRT0
---- 1111
30000Bh
CONFIG6H
WRTD
WRTB
WRTC
—
—
—
—
—
111- ----
30000Ch
CONFIG7L
—
—
—
—
EBTR3
EBTR2
EBTR1
EBTR0
---- 1111
30000Dh
CONFIG7H
—
EBTRB
—
—
—
—
—
—
-1-- ----
3FFFFEh
DEVID1
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
(1)
3FFFFFh
DEVID2
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
0000 1000
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
See Register 24-11 for DEVID1 values.
© 2006 Microchip Technology Inc.
DS41159E-page 265
PIC18FXX8
REGISTER 24-1:
CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
U-0
U-0
R/P-1
U-0
U-0
R/P-1
R/P-1
R/P-1
—
—
OSCSEN
—
—
FOSC2
FOSC1
FOSC0
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5
OSCSEN: Oscillator System Clock Switch Enable bit
1 = Oscillator system clock switch option is disabled (main oscillator is source)
0 = Oscillator system clock switch option is enabled (oscillator switching is enabled)
bit 4-3
Unimplemented: Read as ‘0’
bit 2-0
FOSC2:FOSC0: Oscillator Selection bits
111 = RC oscillator w/OSC2 configured as RA6
110 = HS oscillator with PLL enabled/clock frequency = (4 x FOSC)
101 = EC oscillator w/OSC2 configured as RA6
100 = EC oscillator w/OSC2 configured as divide-by-4 clock output
011 = RC oscillator
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
REGISTER 24-2:
bit 1
bit 0
U-0
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
—
—
—
—
BORV1
BORV0
BOREN
PWRTEN
bit 0
Unimplemented: Read as ‘0’
BORV1:BORV0: Brown-out Reset Voltage bits
11 = VBOR set to 2.0V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR set to 4.5V
BOREN: Brown-out Reset Enable bit
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
DS41159E-page 266
u = Unchanged from programmed state
CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
bit 7
bit 7-4
bit 3-2
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 24-3:
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
—
bit 7
bit 7-4
bit 3-1
U-0
—
U-0
—
R/P-1
WDTPS2
R/P-1
WDTPS0
R/P-1
WDTEN
bit 0
The Watchdog Timer postscale select bits configuration used in the PIC18FXXX
devices has changed from the configuration used in the PIC18CXXX devices.
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
REGISTER 24-4:
R/P-1
WDTPS1
Unimplemented: Read as ‘0’
WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
Note:
bit 0
U-0
—
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1
U-0
U-0
U-0
U-0
R/P-1
U-0
R/P-1
DEBUG
—
—
—
—
LVP
—
STVREN
bit 7
bit 0
bit 7
DEBUG: Background Debugger Enable bit
1 = Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins.
0 = Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.
bit 6-3
Unimplemented: Read as ‘0’
bit 2
LVP: Low-Voltage ICSP Enable bit
1 = Low-Voltage ICSP enabled
0 = Low-Voltage ICSP disabled
bit 1
Unimplemented: Read as ‘0’
bit 0
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack Full/Underflow will cause Reset
0 = Stack Full/Underflow will not cause Reset
Legend:
R = Readable bit
C = Clearable bit
-n = Value when device is unprogrammed
© 2006 Microchip Technology Inc.
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
DS41159E-page 267
PIC18FXX8
REGISTER 24-5:
CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
U-0
U-0
U-0
U-0
R/C-1
R/C-1
R/C-1
R/C-1
—
—
—
—
CP3(1)
CP2(1)
CP1
CP0
bit 7
bit 0
bit 7-4
Unimplemented: Read as ‘0’
bit 3
CP3: Code Protection bit(1)
1 = Block 3 (006000-007FFFh) not code-protected
0 = Block 3 (006000-007FFFh) code-protected
bit 2
CP2: Code Protection bit(1)
1 = Block 2 (004000-005FFFh) not code-protected
0 = Block 2 (004000-005FFFh) code-protected
bit 1
CP1: Code Protection bit
1 = Block 1 (002000-003FFFh) not code-protected
0 = Block 1 (002000-003FFFh) code-protected
bit 0
CP0: Code Protection bit
1 = Block 0 (000200-001FFFh) not code-protected
0 = Block 0 (000200-001FFFh) code-protected
Note 1: Unimplemented in PIC18FX48 devices; maintain this bit set.
Legend:
R = Readable bit
C = Clearable bit
-n = Value when device is unprogrammed
REGISTER 24-6:
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
R/C-1
R/C-1
U-0
U-0
U-0
U-0
U-0
U-0
CPD
CPB
—
—
—
—
—
—
bit 7
bit 0
bit 7
CPD: Data EEPROM Code Protection bit
1 = Data EEPROM not code-protected
0 = Data EEPROM code-protected
bit 6
CPB: Boot Block Code Protection bit
1 = Boot Block (000000-0001FFh) not code-protected
0 = Boot Block (000000-0001FFh) code-protected
bit 5-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
C = Clearable bit
-n = Value when device is unprogrammed
DS41159E-page 268
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 24-7:
CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)
U-0
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
—
—
—
—
WRT3(1)
WRT2(1)
WRT1
WRT0
bit 7
bit 0
bit 7-4
Unimplemented: Read as ‘0’
bit 3
WRT3: Write Protection bit(1)
1 = Block 3 (006000-007FFFh) not write-protected
0 = Block 3 (006000-007FFFh) write-protected
bit 2
WRT2: Write Protection bit(1)
1 = Block 2 (004000-005FFFh) not write-protected
0 = Block 2 (004000-005FFFh) write-protected
bit 1
WRT1: Write Protection bit
1 = Block 1 (002000-003FFFh) not write-protected
0 = Block 1 (002000-003FFFh) write-protected
bit 0
WRT0: Write Protection bit
1 = Block 0 (000200-001FFFh) not write-protected
0 = Block 0 (000200-001FFFh) write-protected
Note 1: Unimplemented in PIC18FX48 devices; maintain this bit set.
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
REGISTER 24-8:
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)
R/P-1
R/P-1
R-1
U-0
U-0
U-0
U-0
U-0
WRTD
WRTB
WRTC
—
—
—
—
—
bit 7
bit 0
bit 7
WRTD: Data EEPROM Write Protection bit
1 = Data EEPROM not write-protected
0 = Data EEPROM write-protected
bit 6
WRTB: Boot Block Write Protection bit
1 = Boot Block (000000-0001FFh) not write-protected
0 = Boot Block (000000-0001FFh) write-protected
bit 5
WRTC: Configuration Register Write Protection bit
1 = Configuration registers (300000-3000FFh) not write-protected
0 = Configuration registers (300000-3000FFh) write-protected
Note:
bit 4-0
This bit is read-only and cannot be changed in user mode.
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
© 2006 Microchip Technology Inc.
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
DS41159E-page 269
PIC18FXX8
REGISTER 24-9:
CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
—
—
—
—
EBTR3(1)
EBTR2(1)
EBTR1
EBTR0
bit 7
bit 0
bit 7-4
Unimplemented: Read as ‘0’
bit 3
EBTR3: Table Read Protection bit(1)
1 = Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
0 = Block 3 (006000-007FFFh) protected from table reads executed in other blocks
bit 2
EBTR2: Table Read Protection bit(1)
1 = Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
0 = Block 2 (004000-005FFFh) protected from table reads executed in other blocks
bit 1
EBTR1: Table Read Protection bit
1 = Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
0 = Block 1 (002000-003FFFh) protected from table reads executed in other blocks
bit 0
EBTR0: Table Read Protection bit
1 = Block 0 (000200-001FFFh) not protected from table reads executed in other blocks
0 = Block 0 (000200-001FFFh) protected from table reads executed in other blocks
Note 1: Unimplemented in PIC18FX48 devices; maintain this bit set.
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
REGISTER 24-10: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0
R/P-1
U-0
U-0
U-0
U-0
U-0
U-0
—
EBTRB
—
—
—
—
—
—
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
EBTRB: Boot Block Table Read Protection bit
1 = Boot Block (000000-0001FFh) not protected from table reads executed in other blocks
0 = Boot Block (000000-0001FFh) protected from table reads executed in other blocks
bit 5-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
DS41159E-page 270
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 24-11: DEVID1: DEVICE ID REGISTER 1 FOR PIC18FXX8 DEVICES
(BYTE ADDRESS 3FFFFEh)
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
bit 7-5
DEV2:DEV0: Device ID bits
These bits are used with the DEV bits in the Device ID Register 2 to identify the
part number.
000 = PIC18F248
001 = PIC18F448
010 = PIC18F258
011 = PIC18F458
bit 4-0
REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
REGISTER 24-12: DEVID2: DEVICE ID REGISTER 2 FOR PIC18FXX8 DEVICES
(BYTE ADDRESS 3FFFFFh)
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 7-0
bit 0
DEV10:DEV3: Device ID bits
These bits are used with the DEV bits in the Device ID Register 1 to identify the
part number.
00001000 = PIC18FXX8
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
© 2006 Microchip Technology Inc.
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
DS41159E-page 271
PIC18FXX8
24.2
Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator which does not require any external components. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKI pin. That means that the
WDT will run, even if the clock on the OSC1/CLKI and
OSC2/CLKO/RA6 pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
The WDT time-out period values may be found in
Section 27.0 “Electrical Characteristics” under
parameter #31. Values for the WDT postscaler may be
assigned using the configuration bits.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation
(Watchdog Timer wake-up). The TO bit in the RCON
register will be cleared upon a WDT time-out.
The Watchdog Timer is enabled/disabled by a device
configuration bit. If the WDT is enabled, software
execution may not disable this function. When the
WDTEN configuration bit is cleared, the SWDTEN bit
enables/disables the operation of the WDT.
Note:
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler if assigned to
the WDT and prevent it from timing out
and generating a device Reset condition.
Note:
When a CLRWDT instruction is executed
and the postscaler is assigned to the WDT,
the postscaler count will be cleared but the
postscaler assignment is not changed.
24.2.1
CONTROL REGISTER
Register 24-13 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
configuration bit only when the configuration bit has
disabled the WDT.
REGISTER 24-13: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
SWDTEN
bit 7
bit 0
bit 7-1
Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is turned off if the WDTEN configuration bit in the Configuration register = 0
Legend:
DS41159E-page 272
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
© 2006 Microchip Technology Inc.
PIC18FXX8
24.2.2
WDT POSTSCALER
The WDT has a postscaler that can extend the WDT
Reset period. The postscaler is selected at the time of
device programming by the value written to the
CONFIG2H Configuration register.
FIGURE 24-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDT Timer
Postscaler
8
WDTPS2:WDTPS0
8-to-1 MUX
WDTEN
Configuration bit
SWDTEN bit
WDT
Time-out
Note:
TABLE 24-2:
Name
CONFIG2H
RCON
WDTCON
WDTPS2:WDTPS0 are bits in register CONFIG2H.
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
—
WDTPS2
WDTPS1
WDTPS0
WDTEN
IPEN
—
—
RI
TO
PD
POR
BOR
—
—
—
—
—
—
—
SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
© 2006 Microchip Technology Inc.
DS41159E-page 273
PIC18FXX8
24.3
Power-Down Mode (Sleep)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (RCON) is cleared, the
TO bit (RCON) is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or high-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external circuitry
is drawing current from the I/O pin, power-down the A/D
and disable external clocks. Pull all I/O pins that are
high-impedance inputs, high or low externally, to avoid
switching currents caused by floating inputs. The T0CKI
input should also be at VDD or VSS for lowest current
consumption. The contribution from on-chip pull-ups on
PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
24.3.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
External Reset input on MCLR pin.
Watchdog Timer wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change or a
peripheral interrupt.
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
PSP read or write.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
3. TMR3 interrupt. Timer3 must be operating as an
asynchronous counter.
4. CCP Capture mode interrupt.
5. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
6. MSSP (Start/Stop) bit detect interrupt.
7. MSSP transmit or receive in Slave mode
(SPI/I2C).
8. USART RX or TX (Synchronous Slave mode).
9. A/D conversion (when A/D clock source is RC).
10. EEPROM write operation complete.
11. LVD interrupt.
External MCLR Reset will cause a device Reset. All
other events are considered a continuation of program
execution and will cause a “wake-up”. The TO and PD
bits in the RCON register can be used to determine the
cause of the device Reset. The PD bit, which is set on
power-up, is cleared when Sleep is invoked. The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 2) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
24.3.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If an interrupt condition (interrupt flag bit and
interrupt enable bits are set) occurs before the
execution of a SLEEP instruction, the SLEEP
instruction will complete as a NOP. Therefore, the
WDT and WDT postscaler will not be cleared, the
TO bit will not be set and the PD bit will not be
cleared.
• If the interrupt condition occurs during or after
the execution of a SLEEP instruction, the device
will immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT
instruction should be executed before a SLEEP
instruction.
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
DS41159E-page 274
© 2006 Microchip Technology Inc.
PIC18FXX8
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
FIGURE 24-2:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKO(4)
INT pin
INTF Flag
(INTCON)
Interrupt Latency(3)
GIEH bit
(INTCON)
Processor in
Sleep
INSTRUCTION FLOW
PC
PC
Instruction
Fetched Inst(PC) = Sleep
Instruction
Inst(PC – 1)
Executed
Note
1:
2:
3:
4:
PC + 2
Inst(PC + 2)
Sleep
PC + 4
PC + 4
PC + 4
Inst(PC + 4)
Inst(PC + 2)
Dummy Cycle
0008h
000Ah
Inst(0008h)
Inst(000Ah)
Dummy Cycle
Inst(0008h)
XT, HS or LP Oscillator mode assumed.
GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Oscillator modes.
CLKO is not available in these oscillator modes but shown here for timing reference.
© 2006 Microchip Technology Inc.
DS41159E-page 275
PIC18FXX8
24.4
Program Verification and
Code Protection
Each of the five blocks has three code protection bits
associated with them. They are:
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro devices.
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
The user program memory is divided into five blocks.
One of these is a boot block of 512 bytes. The remainder of the memory is divided into four blocks on binary
boundaries.
Figure 24-3 shows the program memory organization
for 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
FIGURE 24-3:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18FXX8
MEMORY SIZE/DEVICE
16 Kbytes
(PIC18FX48)
32 Kbytes
(PIC18FX58)
Address
Range
Boot Block
Boot Block
000000h
0001FFh
Block 0
Block 0
Block Code Protection
Controlled By:
CPB, WRTB, EBTRB
000200h
CP0, WRT0, EBTR0
001FFFh
002000h
Block 1
Block 1
CP1, WRT1, EBTR1
003FFFh
004000h
Unimplemented
Read ‘0’s
Block 2
Unimplemented
Read ‘0’s
Block 3
CP2, WRT2, EBTR2
005FFFh
006000h
CP3, WRT3, EBTR3
007FFFh
008000h
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
TABLE 24-3:
SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CP3
CP2
CP1
CP0
300008h
CONFIG5L
—
—
—
—
300009h
CONFIG5H
CPD
CPB
—
—
—
—
—
—
30000Ah
CONFIG6L
—
—
—
—
WRT3
WRT2
WRT1
WRT0
30000Bh
CONFIG6H
WRTD
WRTB
WRTC
—
—
—
—
—
30000Ch
CONFIG7L
—
—
—
—
EBTR3
EBTR2
EBTR1
EBTR0
30000Dh
CONFIG7H
—
EBTRB
—
—
—
—
—
—
Legend: Shaded cells are unimplemented.
DS41159E-page 276
© 2006 Microchip Technology Inc.
PIC18FXX8
24.4.1
PROGRAM MEMORY
CODE PROTECTION
Note:
The user memory may be read to or written from any
location using the table read and table write instructions. The device ID may be read with table reads. The
Configuration registers may be read and written with
the table read and table write instructions.
In user mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from table writes if the
WRTn configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the
EBTRn bit set to ‘0’, a table read instruction that
executes from within that block is allowed to read. A
table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figures 24-4 through 24-6
illustrate table write and table read protection.
FIGURE 24-4:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
TABLE WRITE (WRTn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0001FFh
000200h
WRTB, EBTRB = 11
TBLPTR = 000FFF
WRT0, EBTR0 = 01
PC = 001FFE
TBLWT *
001FFFh
002000h
WRT1, EBTR1 = 11
003FFFh
004000h
PC = 004FFE
WRT2, EBTR2 = 11
TBLWT *
005FFFh
006000h
WRT3, EBTR3 = 11
007FFFh
Results: All table writes disabled to Blockn whenever WRTn = 0.
© 2006 Microchip Technology Inc.
DS41159E-page 277
PIC18FXX8
FIGURE 24-5:
EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
WRTB, EBTRB = 11
0001FFh
000200h
TBLPTR = 000FFF
WRT0, EBTR0 = 10
001FFFh
002000h
PC = 002FFE
TBLRD *
WRT1, EBTR1 = 11
003FFFh
004000h
WRT2, EBTR2 = 11
005FFFh
006000h
WRT3, EBTR3 = 11
007FFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
FIGURE 24-6:
EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
WRTB, EBTRB = 11
0001FFh
000200h
TBLPTR = 000FFF
PC = 001FFE
WRT0, EBTR0 = 10
TBLRD *
001FFFh
002000h
WRT1, EBTR1 = 11
003FFFh
004000h
WRT2, EBTR2 = 11
005FFFh
006000h
WRT3, EBTR3 = 11
007FFFh
Results: Table reads permitted within Blockn even when EBTRBn = 0.
TABLAT register returns the value of the data at the location TBLPTR.
DS41159E-page 278
© 2006 Microchip Technology Inc.
PIC18FXX8
24.4.2
DATA EEPROM
CODE PROTECTION
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits external writes to data EEPROM. The
CPU can continue to read and write data EEPROM
regardless of the protection bit settings.
24.4.3
CONFIGURATION REGISTER
PROTECTION
The Configuration registers can be write-protected.
The WRTC bit controls protection of the Configuration
registers. In user mode, the WRTC bit is readable only.
WRTC can only be written via ICSP or an external
programmer.
24.5
ID Locations
Eight memory locations (200000h-200007h) are
designated as ID locations where the user can store
checksum or other code identification numbers. These
locations are accessible during normal execution
through the TBLRD and TBLWT instructions or during
program/verify. The ID locations can be read when the
device is code-protected.
24.6
In-Circuit Serial Programming
PIC18FXXX microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
24.7
In-Circuit Debugger
When the DEBUG bit in Configuration register,
CONFIG4L, is programmed to a ‘0’, the In-Circuit
Debugger functionality is enabled. This function allows
simple debugging functions when used with
MPLAB® IDE. When the microcontroller has this feature enabled, some of the resources are not available
for general use. Resources used include 2 I/O pins,
stack locations, program memory and data memory.
For more information on the resources required, see
the User’s Guide for the In-Circuit Debugger you are
using.
© 2006 Microchip Technology Inc.
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies. The
Microchip In-Circuit Debugger (ICD) used with the
PIC18FXXX microcontrollers is the MPLAB® ICD 2.
24.8
Low-Voltage ICSP Programming
The LVP bit in Configuration register, CONFIG4L,
enables Low-Voltage ICSP Programming. This mode
allows the microcontroller to be programmed via ICSP
using a VDD source in the operating voltage range. This
only means that VPP does not have to be brought to
VIHH but can instead be left at the normal operating
voltage. In this mode, the RB5/PGM pin is dedicated to
the programming function and ceases to be a general
purpose I/O pin. During programming, VDD is applied to
the MCLR/VPP pin. To enter Programming mode, VDD
must be applied to the RB5/PGM pin, provided the LVP
bit is set. The LVP bit defaults to a (‘1’) from the factory.
Note 1: The High-Voltage Programming mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR pin.
2: While in Low-Voltage ICSP mode, the
RB5 pin can no longer be used as a
general purpose I/O pin.
3: When using Low-Voltage ICSP Programming (LVP) and the pull-ups on PORTB
are enabled, bit 5 in the TRISB register
must be cleared to disable the pull-up on
RB5 and ensure the proper operation of
the device.
If Low-Voltage Programming mode is not used, the LVP
bit can be programmed to a ‘0’ and RB5/PGM becomes
a digital I/O pin. However, the LVP bit may only be
programmed when programming is entered with VIHH
on MCLR/VPP. The LVP bit can only be charged when
using high voltage on MCLR.
It should be noted that once the LVP bit is programmed
to ‘0’, only the High-Voltage Programming mode is
available and only High-Voltage Programming mode
can be used to program the device.
When using Low-Voltage ICSP Programming, the part
must be supplied 4.5V to 5.5V if a bulk erase will be
executed. This includes reprogramming of the codeprotect bits from an ON state to an OFF state. For all
other cases of Low-Voltage ICSP Programming, the
part may be programmed at the normal operating
voltage. This means unique user IDs or user code can
be reprogrammed or added.
DS41159E-page 279
PIC18FXX8
NOTES:
DS41159E-page 280
© 2006 Microchip Technology Inc.
PIC18FXX8
25.0
INSTRUCTION SET SUMMARY
The PIC18 instruction set adds many enhancements to
the previous PICmicro instruction sets, while maintaining
an easy migration from these PICmicro instruction sets.
Most instructions are a single program memory word
(16 bits) but there are three instructions that require two
program memory locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
•
•
•
•
Byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
The PIC18 instruction set summary in Table 25-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 25-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.
The file register (specified by ‘f’)
The destination of the result
(specified by ‘d’)
The accessed memory
(specified by ‘a’)
The file register designator ‘f’ specifies which file
register is to be used by the instruction.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If ‘d’ is zero, the
result is placed in the WREG register. If ‘d’ is one, the
result is placed in the file register specified in the
instruction.
All bit-oriented instructions have three operands:
1.
2.
3.
The file register (specified by ‘f’)
The bit in the file register
(specified by ‘b’)
The accessed memory
(specified by ‘a’)
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register designator ‘f’ represents the number of the file in which the
bit is located.
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
© 2006 Microchip Technology Inc.
The control instructions may use some of the following
operands:
• A program memory address (specified by ‘n’)
• The mode of the CALL or RETURN instructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required
(specified by ‘—’)
All instructions are a single word, except for three
double-word instructions. These three instructions
were made double-word instructions so that all the
required information is available in these 32 bits. In the
second word, the 4 MSbs are ‘1’s. If this second word
is executed as an instruction (by itself), it will execute
as a NOP.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruction. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
Two-word branch instructions (if true) would take 3 μs.
Figure 25-1 shows the general formats that the
instructions can have.
All examples use the format ‘nnh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal
digit.
The Instruction Set Summary, shown in Table 25-2,
lists the instructions recognized by the Microchip
MPASMTM Assembler.
Section 25.2 “Instruction Set” provides a description
of each instruction.
25.1
Read-Modify-Write Operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified and
the result is stored according to either the instruction or
the destination designator ‘d’. A read operation is
performed on a register even if the instruction writes to
that register.
For example, a “CLRF PORTB” instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the
unintended result that the condition that sets the RBIF
flag would be cleared.
DS41159E-page 281
PIC18FXX8
TABLE 25-1:
OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
Bit address within an 8-bit file register (0 to 7).
BSR
Bank Select Register. Used to select the current RAM bank.
d
Destination select bit:
d = 0: store result in WREG
d = 1: store result in file register f
dest
Destination either the WREG register or the specified register file location.
f
8-bit register file address (0x00 to 0xFF).
fs
12-bit register file address (0x000 to 0xFFF). This is the source address.
fd
12-bit register file address (0x000 to 0xFFF). This is the destination address.
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label
Label name.
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No change to register (such as TBLPTR with table reads and writes)
*+
Post-Increment register (such as TBLPTR with table reads and writes)
*-
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
+*
n
The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PRODH
Product of Multiply High Byte.
PRODL
Product of Multiply Low Byte.
s
Fast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
u
Unused or unchanged.
WREG
Working register (accumulator).
x
Don’t care (0 or 1).
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.
TBLPTR
21-bit Table Pointer (points to a program memory location).
TABLAT
8-bit Table Latch.
TOS
Top-of-Stack.
PC
Program Counter
PCL
Program Counter Low Byte.
PCH
Program Counter High Byte.
PCLATH
Program Counter High Byte Latch.
PCLATU
Program Counter Upper Byte Latch.
GIE
Global Interrupt Enable bit.
WDT
Watchdog Timer.
TO
Time-out bit.
PD
Power-Down bit.
C, DC, Z, OV, N
ALU status bits: Carry, Digit Carry, Zero, Overflow, Negative.
[
]
Optional.
(
)
Contents.
→
Assigned to.
< >
Register bit field.
∈
In the set of.
italics
User defined term (font is courier).
DS41159E-page 282
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 25-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15
10
9 8 7
OPCODE d
a
Example Instruction
0
f (FILE #)
ADDWF MYREG, W, B
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
OPCODE
15
0
f (Source FILE #)
12 11
MOVFF MYREG1, MYREG2
0
f (Destination FILE #)
1111
f = 12-bit file register address
Bit-oriented file register operations
15
12 11
9 8 7
OPCODE b (BIT #) a
0
f (FILE #)
BSF MYREG, bit, B
b = 3-bit position of bit in file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
OPCODE
0
k (literal)
MOVLW 0x7F
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
OPCODE
15
0
n (literal)
12 11
GOTO Label
0
n (literal)
1111
n = 20-bit immediate value
15
8 7
OPCODE
15
S
0
CALL MYFUNC
n (literal)
12 11
0
n (literal)
S = Fast bit
15
OPCODE
15
OPCODE
© 2006 Microchip Technology Inc.
11 10
0
BRA MYFUNC
n (literal)
8 7
n (literal)
0
BC MYFUNC
DS41159E-page 283
PIC18FXX8
TABLE 25-2:
PIC18FXXX INSTRUCTION SET
Mnemonic,
Operands
16-Bit Instruction Word
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
fs, fd
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, d, a
SUBWF
SUBWFB f, d, a
SWAPF
TSTFSZ
XORWF
f, d, a
f, a
f, d, a
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move fs (source) to 1st word
fd (destination) 2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
borrow
Subtract WREG from f
Subtract WREG from f with
borrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR WREG with f
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1
1
1
1
1
1
1
1
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
1
1
0101 11da
0101 10da
ffff
ffff
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N 1, 2
1
0011 10da
1 (2 or 3) 0110 011a
1
0001 10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
4
1, 2
1
1
1 (2 or 3)
1 (2 or 3)
1
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1, 2
1, 2
3, 4
3, 4
1, 2
None
None
C, DC, Z, OV, N 1, 2
C, Z, N
Z, N
1, 2
C, Z, N
Z, N
None
C, DC, Z, OV, N 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
Note 1:
2:
3:
4:
5:
f, b, a
f, b, a
f, b, a
f, b, a
f, d, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input
and is driven low by an external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be
cleared if assigned.
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that
all program memory locations have a valid instruction.
If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS41159E-page 284
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 25-2:
PIC18FXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
n
n
n
n
n
n
n
n
n
n, s
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
s
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
No Operation
No Operation
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into Standby mode
CLRWDT —
DAW
—
GOTO
n
Note 1:
2:
3:
4:
5:
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2
1
1
1
1
2
1
2
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
2
2
1
0000 1100
0000 0000
0000 0000
kkkk
0001
0000
1
1
2
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
None
None
None
None
None
None
None
None
None
None
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
kkkk None
001s None
0011 TO, PD
4
When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input
and is driven low by an external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be
cleared if assigned.
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that
all program memory locations have a valid instruction.
If the table write starts the write cycle to internal memory, the write will continue until terminated.
© 2006 Microchip Technology Inc.
DS41159E-page 285
PIC18FXX8
TABLE 25-2:
PIC18FXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
to FSRx
1st word
Move literal to BSR
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with WREG
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
None
None
None
None
C, DC, Z, OV, N
Z, N
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
TBLRD*+
TBLRD*TBLRD+*
TBLWT*
TBLWT*+
TBLWT*TBLWT+*
Note 1:
2:
3:
4:
5:
Table Read
2
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
2 (5)
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input
and is driven low by an external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be
cleared if assigned.
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that
all program memory locations have a valid instruction.
If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS41159E-page 286
© 2006 Microchip Technology Inc.
PIC18FXX8
25.2
Instruction Set
ADDLW
ADD Literal to W
Syntax:
[ label ] ADDLW
Operands:
0 ≤ k ≤ 255
Operation:
(W) + k → W
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
Description:
ADDWF
k
1111
kkkk
1
Cycles:
1
Syntax:
[ label ] ADDWF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) + (f) → dest
Status Affected:
N, OV, C, DC, Z
kkkk
The contents of W are added to the 8-bit
literal ‘k’ and the result is placed in W.
Words:
ADD W to f
Encoding:
0010
Q1
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to W
Example:
ADDLW
0x15
Before Instruction
W
= 0x10
After Instruction
W =
0x25
ffff
ffff
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access Bank
will be selected. If ‘a’ is ‘1’, the BSR is
used.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
© 2006 Microchip Technology Inc.
01da
Description:
Q Cycle Activity:
Decode
f [,d [,a]]
REG, W
0x17
0xC2
0xD9
0xC2
DS41159E-page 287
PIC18FXX8
ADDWFC
ADD W and Carry bit to f
ANDLW
AND Literal with W
Syntax:
[ label ] ADDWFC
Syntax:
[ label ] ANDLW
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
f [,d [,a]]
(W) + (f) + (C) → dest
Operation:
Status Affected:
Encoding:
0010
Description:
00da
ffff
ffff
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is placed
in W. If ‘d’ is ‘1’, the result is placed in
data memory location ‘f’. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’ is ‘1’,
the BSR will not be overridden.
Words:
1
Cycles:
1
0 ≤ k ≤ 255
Operation:
(W) .AND. k → W
Status Affected:
N, Z
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
ADDWFC
Before Instruction
Carry bit =
REG
=
W
=
1
0x02
0x4D
After Instruction
Carry bit =
REG
=
W
=
0
0x02
0x50
DS41159E-page 288
0000
1011
kkkk
kkkk
Description:
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to W
Example:
Q Cycle Activity:
Example:
Operands:
Encoding:
N, OV, C, DC, Z
k
ANDLW
Before Instruction
W
=
After Instruction
W
=
0x5F
0xA3
0x03
REG, W
© 2006 Microchip Technology Inc.
PIC18FXX8
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
f [,d [,a]]
Operation:
(W) .AND. (f) → dest
Status Affected:
N, Z
Encoding:
0001
ffff
ffff
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’ is ‘1’,
the BSR will not be overridden (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
ANDWF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
Branch if Carry
Syntax:
[ label ] BC
-128 ≤ n ≤ 127
Operation:
if Carry bit is ‘1’
(PC) + 2 + 2n → PC
Status Affected:
None
1110
0x02
0xC2
nnnn
nnnn
If the Carry bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
After Instruction
If Carry
PC
If Carry
PC
© 2006 Microchip Technology Inc.
0010
Description:
REG, W
0x17
0xC2
n
Operands:
Encoding:
01da
Description:
Example:
BC
BC
JUMP
=
address (HERE)
=
=
=
=
1;
address (JUMP)
0;
address (HERE + 2)
DS41159E-page 289
PIC18FXX8
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
Operation:
0 → f
Status Affected:
None
Encoding:
1001
f,b[,a]
ffff
ffff
Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’,
the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the
bank will be selected as per the BSR
value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Decode
Q2
Read
register ‘f’
Example:
BCF
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
Branch if Negative
Syntax:
[ label ] BN
Q3
Process
Data
FLAG_REG, 7
Q4
Write
register ‘f’
-128 ≤ n ≤ 127
Operation:
if Negative bit is ‘1’
(PC) + 2 + 2n → PC
Status Affected:
None
1110
0110
nnnn
nnnn
Description:
If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
After Instruction
If Negative
PC
If Negative
PC
DS41159E-page 290
n
Operands:
Encoding:
bbba
Description:
Q1
BN
BN
Jump
=
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
© 2006 Microchip Technology Inc.
PIC18FXX8
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
[ label ] BNC
Syntax:
[ label ] BNN
n
n
Operands:
-128 ≤ n ≤ 127
Operands:
-128 ≤ n ≤ 127
Operation:
if Carry bit is ‘0’
(PC) + 2 + 2n → PC
Operation:
if Negative bit is ‘0’
(PC) + 2 + 2n → PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
0011
nnnn
nnnn
Encoding:
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Description:
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
If No Jump:
Example:
If No Jump:
HERE
Before Instruction
PC
After Instruction
If Carry
PC
If Carry
PC
BNC
Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
© 2006 Microchip Technology Inc.
Example:
HERE
Before Instruction
PC
After Instruction
If Negative
PC
If Negative
PC
BNN
Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
DS41159E-page 291
PIC18FXX8
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
[ label ] BNOV
Syntax:
[ label ] BNZ
n
n
Operands:
-128 ≤ n ≤ 127
Operands:
-128 ≤ n ≤ 127
Operation:
if Overflow bit is ‘0’
(PC) + 2 + 2n → PC
Operation:
if Zero bit is ‘0’
(PC) + 2 + 2n → PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
0101
nnnn
nnnn
Encoding:
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Description:
If the Zero bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
If No Jump:
If No Jump:
Example:
HERE
Before Instruction
PC
After Instruction
If Overflow
PC
If Overflow
PC
DS41159E-page 292
BNOV Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
Example:
HERE
Before Instruction
PC
After Instruction
If Zero
PC
If Zero
PC
BNZ
Jump
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
© 2006 Microchip Technology Inc.
PIC18FXX8
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
[ label ] BRA
Syntax:
[ label ] BSF
Operands:
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
Operation:
1 → f
Status Affected:
None
n
Operands:
-1024 ≤ n ≤ 1023
Operation:
(PC) + 2 + 2n → PC
Status Affected:
None
Encoding:
1101
Description:
0nnn
nnnn
nnnn
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Encoding:
HERE
Before Instruction
PC
After Instruction
PC
BRA
Jump
=
address (HERE)
=
address (Jump)
© 2006 Microchip Technology Inc.
bbba
ffff
ffff
Description:
Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
Example:
1000
f,b[,a]
BSF
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
FLAG_REG, 7
=
0x0A
=
0x8A
DS41159E-page 293
PIC18FXX8
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSC f,b[,a]
Syntax:
[ label ] BTFSS f,b[,a]
Operands:
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
Operation:
skip if (f) = 0
Operation:
skip if (f) = 1
Status Affected:
None
Status Affected:
None
Encoding:
1011
Description:
bbba
ffff
ffff
Encoding:
1010
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped.
If bit ‘b’ is ‘0’, then the next instruction
fetched during the current instruction
execution is discarded and a NOP is
executed instead, making this a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
Description:
Words:
1
Words:
1
Cycles:
1(2)
Note:
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
bbba
ffff
ffff
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruction
fetched during the current instruction
execution is discarded and a NOP is
executed instead, making this a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
FALSE
TRUE
Before Instruction
PC
After Instruction
If FLAG
PC
If FLAG
PC
DS41159E-page 294
BTFSC
:
:
FLAG, 1
=
address (HERE)
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
Example:
HERE
FALSE
TRUE
Before Instruction
PC
After Instruction
If FLAG
PC
If FLAG
PC
BTFSS
:
:
FLAG, 1
=
address (HERE)
=
=
=
=
0;
address (FALSE)
1;
address (TRUE)
© 2006 Microchip Technology Inc.
PIC18FXX8
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
[ label ] BTG f,b[,a]
Syntax:
[ label ] BOV
Operands:
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
Operands:
-128 ≤ n ≤ 127
Operation:
if Overflow bit is ‘1’
(PC) + 2 + 2n → PC
Status Affected:
None
Operation:
(f) → f
Status Affected:
None
Encoding:
0111
Encoding:
bbba
ffff
ffff
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted. If ‘a’ is ‘0’, the Access Bank will
be selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected as
per the BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Read
register ‘f’
BTG
Q4
Process
Data
PORTC,
4
Before Instruction:
PORTC =
0111 0101 [0x75]
After Instruction:
PORTC =
0110 0101 [0x65]
Write
register ‘f’
1110
0100
nnnn
nnnn
Description:
If the Overflow bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
After Instruction
If Overflow
PC
If Overflow
PC
© 2006 Microchip Technology Inc.
n
BOV
JUMP
=
address (HERE)
=
=
=
=
1;
address (JUMP)
0;
address (HERE + 2)
DS41159E-page 295
PIC18FXX8
BZ
Branch if Zero
CALL
Subroutine Call
Syntax:
[ label ] BZ
Syntax:
[ label ] CALL k [,s]
n
Operands:
-128 ≤ n ≤ 127
Operands:
Operation:
if Zero bit is ‘1’
(PC) + 2 + 2n → PC
0 ≤ k ≤ 1048575
s ∈ [0,1]
Operation:
Status Affected:
None
(PC) + 4 → TOS,
k → PC,
if s = 1
(W) → WS,
(Status) → STATUSS,
(BSR) → BSRS
Status Affected:
None
Encoding:
1110
Description:
0000
nnnn
nnnn
If the Zero bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Encoding:
1st word (k)
2nd word(k)
Q1
Q2
Q3
Q4
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
After Instruction
If Zero
PC
If Zero
PC
DS41159E-page 296
BZ
110s
k19kkk
k7kkk
kkkk
Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, Status and BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC.
CALL is a two-cycle instruction.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’,
Push PC to
stack
Read literal
‘k’,
Write to PC
No
operation
No
operation
No
operation
No
operation
Jump
=
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
kkkk0
kkkk8
Description:
Q Cycle Activity:
If Jump:
Decode
1110
1111
Example:
HERE
Before Instruction
PC
=
After Instruction
PC
=
TOS
=
WS
=
BSRS
=
STATUSS=
CALL
THERE,FAST
address (HERE)
address (THERE)
address (HERE + 4)
W
BSR
Status
© 2006 Microchip Technology Inc.
PIC18FXX8
CLRF
Clear f
Syntax:
[ label ] CLRF
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
000h → f
1→Z
Status Affected:
Z
Encoding:
0110
f [,a]
101a
ffff
ffff
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
1 → PD
Status Affected:
TO, PD
Clears the contents of the specified
register. If ‘a’ is ‘0’, the Access Bank will
be selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be selected
as per the BSR value (default).
Encoding:
Description:
CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits TO
and PD are set.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Description:
0000
0000
0000
0100
Q Cycle Activity:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Decode
No
operation
Process
Data
No
operation
Example:
CLRF
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
FLAG_REG
=
0x5A
=
0x00
© 2006 Microchip Technology Inc.
Example:
CLRWDT
Before Instruction
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
PD
=
?
=
=
=
=
0x00
0
1
1
DS41159E-page 297
PIC18FXX8
COMF
Complement f
Syntax:
[ label ] COMF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
f [,d [,a]]
CPFSEQ
Compare f with W, Skip if f = W
Syntax:
[ label ] CPFSEQ
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected:
None
( f ) → dest
Operation:
Status Affected:
N, Z
Encoding:
0001
Description:
11da
ffff
ffff
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default). If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
COMF
Before Instruction
REG
=
After Instruction
REG
=
W
=
REG, W
Encoding:
001a
ffff
ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOP is executed
instead, making this a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
Words:
1
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
0x13
0x13
0xEC
0110
f [,a]
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NEQUAL
EQUAL
Before Instruction
PC Address
W
REG
After Instruction
If REG
PC
If REG
PC
DS41159E-page 298
CPFSEQ REG
:
:
=
=
=
HERE
?
?
=
=
≠
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
© 2006 Microchip Technology Inc.
PIC18FXX8
CPFSGT
Compare f with W, Skip if f > W
CPFSLT
Compare f with W, Skip if f < W
Syntax:
[ label ] CPFSGT
Syntax:
[ label ] CPFSLT
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) − (W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) – (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
None
Status Affected:
None
Encoding:
0110
Description:
f [,a]
010a
ffff
ffff
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Encoding:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
1
Cycles:
1(2)
Note:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
NLESS
LESS
CPFSLT REG
:
:
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Before Instruction
PC
W
After Instruction
If REG
PC
If REG
PC
=
=
Address (HERE)
?
>
=
≤
=
W;
Address (GREATER)
W;
Address (NGREATER)
© 2006 Microchip Technology Inc.
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
CPFSGT REG
:
:
ffff
Words:
No
operation
HERE
NGREATER
GREATER
ffff
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’ is ‘1’,
the BSR will not be overridden (default).
No
operation
Example:
000a
Description:
Q Cycle Activity:
Decode
0110
f [,a]
Example:
Before Instruction
PC
W
After Instruction
If REG
PC
If REG
PC
=
=
Address (HERE)
?
<
=
≥
=
W;
Address (LESS)
W;
Address (NLESS)
DS41159E-page 299
PIC18FXX8
DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
[ label ] DAW
Syntax:
[ label ] DECF f [,d [,a]]
Operands:
None
Operands:
Operation:
If [W > 9] or [DC = 1] then
(W) + 6 → W;
else
(W) → W
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest
Status Affected:
C, DC, N, OV, Z
Encoding:
If [W > 9] or [C = 1] then
(W) + 6 → W;
else
(W) → W
Status Affected:
0000
0000
Description:
0000
0000
Words:
Cycles:
Words:
1
Cycles:
1
Q Cycle Activity:
1
Q1
Q2
Q3
Q4
1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
Example 1:
DAW
Before Instruction
W
=
C
=
DC
=
After Instruction
W
=
C
=
DC
=
Example 2:
Before Instruction
W
=
C
=
DC
=
After Instruction
W
=
C
=
DC
=
DS41159E-page 300
ffff
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
0111
DAW adjusts the eight-bit value in W
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
ffff
Description:
C
Encoding:
01da
0xA5
0
0
Example:
DECF
Before Instruction
CNT
=
Z
=
After Instruction
CNT
=
Z
=
CNT,
0x01
0
0x00
1
0x05
1
0
0xCE
0
0
0x34
1
0
© 2006 Microchip Technology Inc.
PIC18FXX8
DECFSZ
Decrement f, Skip if 0
DCFSNZ
Decrement f, Skip if not 0
Syntax:
[ label ] DECFSZ f [,d [,a]]
Syntax:
[ label ] DCFSNZ
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result = 0
Operation:
(f) – 1 → dest,
skip if result ≠ 0
Status Affected:
None
Status Affected:
None
Encoding:
0010
11da
ffff
ffff
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as per
the BSR value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Encoding:
0100
Description:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Words:
1
Cycles:
1(2)
Note:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
DECFSZ
GOTO
CNT
LOOP
CONTINUE
Before Instruction
PC
=
After Instruction
CNT
=
If CNT
=
PC =
If CNT
≠
PC =
Address (HERE)
CNT – 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
© 2006 Microchip Technology Inc.
ffff
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
If skip and followed by 2-word instruction:
ffff
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Q Cycle Activity:
Decode
11da
f [,d [,a]]
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
ZERO
NZERO
DCFSNZ TEMP
:
:
Example:
Before Instruction
TEMP
After Instruction
TEMP
If TEMP
PC
If TEMP
PC
=
?
=
=
=
≠
=
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
DS41159E-page 301
PIC18FXX8
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Status Affected:
C, DC, N, OV, Z
GOTO k
Operands:
0 ≤ k ≤ 1048575
Operation:
k → PC
Status Affected:
None
Encoding:
1st word (k)
2nd word(k)
1110
1111
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description:
GOTO allows an unconditional branch
anywhere within entire 2-Mbyte memory
range. The 20-bit value ‘k’ is loaded into
PC. GOTO is always a two-cycle
instruction.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
No
operation
Read literal
‘k’,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example:
GOTO THERE
After Instruction
PC =
Address (THERE)
DS41159E-page 302
Encoding:
0010
INCF
f [,d [,a]]
10da
ffff
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default). If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
INCF
Before Instruction
CNT
=
Z
=
C
=
DC
=
After Instruction
CNT
=
Z
=
C
=
DC
=
CNT,
0xFF
0
?
?
0x00
1
1
1
© 2006 Microchip Technology Inc.
PIC18FXX8
INCFSZ
Increment f, Skip if 0
INFSNZ
Increment f, Skip if not 0
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result = 0
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Status Affected:
None
Status Affected:
None
Encoding:
0011
INCFSZ
f [,d [,a]]
11da
ffff
ffff
Encoding:
INFSNZ
0100
f [,d [,a]]
10da
ffff
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
Words:
1
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note:
Q Cycle Activity:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
ZERO
NZERO
INFSNZ REG
Example:
HERE
NZERO
ZERO
Before Instruction
PC
=
After Instruction
CNT
=
If CNT
=
PC
=
If CNT
≠
PC
=
INCFSZ
:
:
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
© 2006 Microchip Technology Inc.
CNT
Example:
Before Instruction
PC
=
After Instruction
REG
=
If REG
≠
PC
=
If REG
=
PC
=
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
DS41159E-page 303
PIC18FXX8
IORLW
Inclusive OR Literal with W
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .OR. (f) → dest
Status Affected:
N, Z
IORLW k
Operands:
0 ≤ k ≤ 255
Operation:
(W) .OR. k → W
Status Affected:
N, Z
Encoding:
0000
1001
kkkk
kkkk
Description:
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed in
W.
Words:
1
Cycles:
1
Encoding:
0001
Q1
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to W
Example:
IORLW
Before Instruction
W
=
After Instruction
W
=
0x9A
0x35
00da
ffff
ffff
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default). If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
0xBF
Example:
IORWF RESULT, W
Before Instruction
RESULT =
W
=
After Instruction
RESULT =
W
=
DS41159E-page 304
f [,d [,a]]
Description:
Q Cycle Activity:
Decode
IORWF
0x13
0x91
0x13
0x93
© 2006 Microchip Technology Inc.
PIC18FXX8
LFSR
Load FSR
MOVF
Move f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0≤f≤2
0 ≤ k ≤ 4095
Operands:
Operation:
k → FSRf
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Status Affected:
None
Operation:
f → dest
Status Affected:
N, Z
Encoding:
LFSR f,k
1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Description:
The 12-bit literal ‘k’ is loaded into the
file select register pointed to by ‘f’.
Words:
2
Cycles:
2
Encoding:
0101
Q1
Q2
Q3
Q4
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
f [,d [,a]]
00da
ffff
ffff
Description:
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding the
BSR value. If ‘a’ = 1, then the bank will
be selected as per the BSR value
(default).
Words:
1
Cycles:
1
Q Cycle Activity:
Decode
MOVF
Q Cycle Activity:
Example:
After Instruction
FSR2H
FSR2L
LFSR 2, 0x3AB
=
=
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write W
0x03
0xAB
Example:
MOVF
Before Instruction
REG
W
After Instruction
REG
W
© 2006 Microchip Technology Inc.
REG, W
=
=
0x22
0xFF
=
=
0x22
0x22
DS41159E-page 305
PIC18FXX8
MOVFF
Move f to f
MOVLB
Move Literal to Low Nibble in BSR
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ fs ≤ 4095
0 ≤ fd ≤ 4095
Operands:
0 ≤ k ≤ 255
Operation:
(fs) → fd
k → BSR
Operation:
Status Affected:
None
Status Affected:
None
Encoding:
1st word (source)
2nd word (destin.)
MOVFF fs,fd
Encoding:
1100
1111
Description:
ffff
ffff
ffff
ffff
ffffs
ffffd
The contents of source register ‘fs’ are
moved to destination register ‘fd’.
Location of source ‘fs’ can be anywhere
in the 4096-byte data space (000h to
FFFh) and location of destination ‘fd’
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF is particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
MOVLB k
0000
0001
kkkk
kkkk
Description:
The 8-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write
literal ‘k’ to
BSR
Example:
MOVLB
Before Instruction
BSR register
After Instruction
BSR register
5
=
0x02
=
0x05
The MOVFF instruction should not be
used to modify interrupt settings while
any interrupt is enabled (see page 77).
Words:
2
Cycles:
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
Before Instruction
REG1
REG2
After Instruction
REG1
REG2
DS41159E-page 306
REG1, REG2
=
=
0x33
0x11
=
=
0x33
0x33
© 2006 Microchip Technology Inc.
PIC18FXX8
MOVLW
Move Literal to W
MOVWF
Move W to f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(W) → f
Status Affected:
None
MOVLW k
Operands:
0 ≤ k ≤ 255
Operation:
k→W
Status Affected:
None
Encoding:
0000
Description:
1110
kkkk
kkkk
The eight-bit literal ‘k’ is loaded into W.
Words:
1
Cycles:
1
Encoding:
0110
Q1
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to W
Example:
After Instruction
W
=
MOVLW
0x5A
f [,a]
111a
ffff
ffff
Description:
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding the
BSR value. If ‘a’ = 1, then the bank will
be selected as per the BSR value
(default).
Words:
1
Cycles:
1
Q Cycle Activity:
Decode
MOVWF
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
0x5A
Example:
MOVWF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
© 2006 Microchip Technology Inc.
REG
0x4F
0xFF
0x4F
0x4F
DS41159E-page 307
PIC18FXX8
MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(W) x (f) → PRODH:PRODL
Status Affected:
None
MULLW
k
Operands:
0 ≤ k ≤ 255
Operation:
(W) x k → PRODH:PRODL
Status Affected:
None
Encoding:
0000
Description:
1101
kkkk
kkkk
An unsigned multiplication is carried out
between the contents of W and the 8-bit
literal ‘k’. The 16-bit result is placed in
the PRODH:PRODL register pair.
PRODH contains the high byte. W is
unchanged.
None of the status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected.
Words:
1
Cycles:
1
Encoding:
0000
Q1
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULLW
Before Instruction
W
PRODH
PRODL
After Instruction
W
PRODH
PRODL
DS41159E-page 308
0xC4
=
=
=
0xE2
?
?
=
=
=
0xE2
0xAD
0x08
001a
f [,a]
ffff
ffff
Description:
An unsigned multiplication is carried out
between the contents of W and the
register file location ‘f’. The 16-bit result
is stored in the PRODH:PRODL
register pair. PRODH contains the high
byte.
Both W and ‘f’ are unchanged.
None of the status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected. If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’= 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Decode
MULWF
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULWF
Before Instruction
W
REG
PRODH
PRODL
After Instruction
W
REG
PRODH
PRODL
REG
=
=
=
=
0xC4
0xB5
?
?
=
=
=
=
0xC4
0xB5
0x8A
0x94
© 2006 Microchip Technology Inc.
PIC18FXX8
NEGF
Negate f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
NEGF
Operation:
(f)+1→f
Status Affected:
N, OV, C, DC, Z
Encoding:
0110
Description:
f [,a]
1
Cycles:
1
110a
ffff
Syntax:
[ label ]
NOP
Operands:
None
Operation:
No operation
Status Affected:
None
0000
1111
ffff
0000
xxxx
Description:
No operation.
Words:
1
Cycles:
1
0000
xxxx
0000
xxxx
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
Example:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
No Operation
Encoding:
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
Words:
NOP
NEGF
Before Instruction
REG
=
After Instruction
REG
=
None.
REG, 1
0011 1010 [0x3A]
1100 0110 [0xC6]
© 2006 Microchip Technology Inc.
DS41159E-page 309
PIC18FXX8
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
(TOS) → bit bucket
Operation:
(PC + 2) → TOS
Status Affected:
None
Status Affected:
None
Encoding:
0000
POP
0000
0000
0110
Encoding:
PUSH
0000
0000
0000
0101
Description:
The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
Description:
The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows the user to
implement a software stack by
modifying TOS and then pushing it onto
the return stack.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
No
operation
POP TOS
value
No
operation
Decode
PUSH PC + 2
onto return
stack
No
operation
No
operation
Example:
POP
GOTO
Example:
NEW
Before Instruction
TOS
Stack (1 level down)
=
=
0x0031A2
0x014332
After Instruction
TOS
PC
=
=
0x014332
NEW
DS41159E-page 310
PUSH
Before Instruction
TOS
PC
=
=
0x00345A
0x000124
After Instruction
PC
TOS
Stack (1 level down)
=
=
=
0x000126
0x000126
0x00345A
© 2006 Microchip Technology Inc.
PIC18FXX8
RCALL
Relative Call
Syntax:
[ label ] RCALL
n
RESET
Reset
Syntax:
[ label ]
RESET
Operands:
-1024 ≤ n ≤ 1023
Operands:
None
Operation:
(PC) + 2 → TOS,
(PC) + 2 + 2n → PC
Operation:
Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected:
None
Status Affected:
All
Encoding:
1101
Description:
1nnn
nnnn
nnnn
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words:
1
Cycles:
2
Q1
Q2
Q3
Q4
Decode
Read literal ‘n’
Process
Data
Write to
PC
No
operation
No
operation
Push PC to
stack
Example:
0000
No
operation
HERE
0000
1111
1111
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
Reset
No
operation
No
operation
Example:
Q Cycle Activity:
No
operation
Encoding:
After Instruction
Registers =
Flags*
=
RESET
Reset Value
Reset Value
RCALL Jump
Before Instruction
PC =
Address (HERE)
After Instruction
PC =
Address (Jump)
TOS =
Address (HERE + 2)
© 2006 Microchip Technology Inc.
DS41159E-page 311
PIC18FXX8
RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
RETFIE [s]
RETLW k
Operands:
s ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) → W,
(STATUSS) → Status,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged.
Operation:
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
Status Affected:
None
Status Affected:
0000
0000
Description:
0000
0001
Words:
1
Cycles:
2
Q Cycle Activity:
kkkk
kkkk
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Words:
1
Cycles:
2
000s
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers W, Status
and BSR. If ‘s’ = 0, no update of these
registers occurs (default).
1100
Description:
GIE/GIEH, PEIE/GIEL.
Encoding:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Pop PC
from stack,
Write to W
No
operation
No
operation
No
operation
No
operation
Example:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
Pop PC from
stack
Set GIEH or
GIEL
No
operation
Encoding:
No
operation
Example:
No
operation
RETFIE 1
After Interrupt
PC
W
BSR
Status
GIE/GIEH, PEIE/GIEL
DS41159E-page 312
No
operation
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
CALL TABLE ;
;
;
;
:
TABLE
ADDWF PCL ;
RETLW k0
;
RETLW k1
;
:
:
RETLW kn
;
Before Instruction
W
=
After Instruction
W
=
W contains table
offset value
W now has
table value
W = offset
Begin table
End of table
0x07
value of kn
© 2006 Microchip Technology Inc.
PIC18FXX8
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) → dest,
(f) → C,
(C) → dest
Status Affected:
C, N, Z
RETURN [s]
Operands:
s ∈ [0,1]
Operation:
(TOS) → PC,
if s = 1
(WS) → W,
(STATUSS) → Status,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
Status Affected:
None
Encoding:
0000
Description:
Encoding:
0000
0001
001s
0011
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers W, Status and BSR. If ‘s’ = 0,
no update of these registers occurs
(default).
f [,d [,a]]
01da
ffff
ffff
The contents of register ‘f’ are rotated
one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register
‘f’ (default). If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
register f
C
Words:
1
Words:
1
Cycles:
2
Cycles:
1
Q Cycle Activity:
RLCF
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
Pop PC
from stack
Decode
Read
register ‘f’
Process
Data
Write to
destination
No
operation
No
operation
No
operation
No
operation
Example:
RETURN
After Interrupt
PC = TOS
© 2006 Microchip Technology Inc.
Example:
Before Instruction
REG
=
C
=
After Instruction
REG
=
W
=
C
=
RLCF
REG, W
1110 0110
0
1110 0110
1100 1100
1
DS41159E-page 313
PIC18FXX8
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) → dest,
(f) → dest
Operation:
Status Affected:
N, Z
(f) → dest,
(f) → C,
(C) → dest
Status Affected:
C, N, Z
Encoding:
0100
Description:
RLNCF
01da
f [,d [,a]]
ffff
ffff
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default). If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
Encoding:
0011
Description:
register f
Words:
1
Cycles:
1
Decode
Q2
Read
register ‘f’
Example:
Before Instruction
REG
=
After Instruction
REG
=
DS41159E-page 314
RLNCF
Q3
Process
Data
Q4
Write to
destination
0101 0111
ffff
ffff
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
Words:
1
Cycles:
register f
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
REG
1010 1011
f [,d [,a]]
00da
C
Q Cycle Activity:
Q1
RRCF
Example:
RRCF
Before Instruction
REG
=
C
=
After Instruction
REG
=
W
=
C
=
REG, W
1110 0110
0
1110 0110
0111 0011
0
© 2006 Microchip Technology Inc.
PIC18FXX8
RRNCF
Rotate Right f (no carry)
SETF
Set f
Syntax:
[ label ]
Syntax:
[ label ] SETF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) → dest,
(f) → dest
Status Affected:
N, Z
Encoding:
0100
Description:
RRNCF
f [,d [,a]]
00da
Operation:
FFh → f
Status Affected:
None
Encoding:
ffff
ffff
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default). If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
1
Cycles:
1
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
Before Instruction
REG
=
After Instruction
REG
=
Example 2:
ffff
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
SETF
Before Instruction
REG
After Instruction
REG
REG
=
0x5A
=
0xFF
REG, 1, 0
1101 0111
1110 1011
RRNCF
Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=
ffff
The contents of the specified register
are set to FFh. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding the
BSR value. If ‘a’ is ‘1’, then the bank will
be selected as per the BSR value
(default).
Example:
Q Cycle Activity:
100a
Description:
register f
Words:
0110
f [,a]
REG, W
?
1101 0111
1110 1011
1101 0111
© 2006 Microchip Technology Inc.
DS41159E-page 315
PIC18FXX8
SLEEP
Enter Sleep Mode
SUBFWB
Subtract f from W with Borrow
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) – (f) – (C) → dest
Status Affected:
N, OV, C, DC, Z
SLEEP
Operands:
None
Operation:
00h → WDT,
0 → WDT postscaler,
1 → TO,
0 → PD
Status Affected:
TO, PD
Encoding:
0000
Encoding:
0000
0000
0011
Description:
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
No
operation
Example:
Q3
Process
Data
Q4
Go to
Sleep
0101
† If WDT causes wake-up, this bit is cleared.
ffff
ffff
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
DS41159E-page 316
01da
f [,d [,a]]
Description:
SLEEP
Before Instruction
TO =
?
?
PD =
After Instruction
TO =
1†
0
PD =
SUBFWB
SUBFWB REG
0x03
0x02
0x01
0xFF
0x02
0x00
0x00
0x01
SUBFWB
; result is negative
REG, 0, 0
2
5
1
2
3
1
0
0
; result is positive
SUBFWB
REG, 1, 0
1
2
0
0
2
1
1
0
; result is zero
© 2006 Microchip Technology Inc.
PIC18FXX8
SUBLW
Subtract W from Literal
SUBWF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
k – (W) → W
Status Affected:
N, OV, C, DC, Z
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) → dest
Status Affected:
N, OV, C, DC, Z
Encoding:
SUBLW k
0000
Description:
1000
kkkk
kkkk
Subtract W from f
SUBWF
f [,d [,a]]
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
Encoding:
Words:
1
Description:
Cycles:
1
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
Words:
1
Cycles:
1
0101
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Example 1:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
Example 2:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
SUBLW
0x02
1
?
1
1
0
0
SUBLW
SUBLW
; result is positive
0x02
; result is zero
0x02
ffff
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
3
?
FF
0
0
1
ffff
Q Cycle Activity:
2
?
0
1
1
0
11da
; (2’s complement)
; result is negative
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
© 2006 Microchip Technology Inc.
SUBWF REG
3
2
?
1
2
1
0
0
; result is positive
SUBWF REG, W
2
2
?
2
0
1
1
0
; result is zero
SUBWF REG
0x01
0x02
?
0xFFh ;(2’s complement)
0x02
0x00 ; result is negative
0x00
0x01
DS41159E-page 317
PIC18FXX8
SUBWFB
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) – (C) → dest
Operation:
Status Affected:
N, OV, C, DC, Z
(f) → dest,
(f) → dest
Status Affected:
None
Encoding:
0101
Description:
SUBWFB
10da
f [,d [,a]]
ffff
ffff
Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per the
BSR value (default).
Encoding:
0011
ffff
ffff
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default). If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Q Cycle Activity:
Q1
Q2
Read
register ‘f’
Example 1:
Q4
Q1
Q2
Q3
Q4
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q3
Process
Data
SUBWFB REG, 1, 0
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
0x19
0x0D
0x01
(0001 1001)
(0000 1101)
0x0C
0x0D
0x01
0x00
0x00
(0000 1011)
(0000 1101)
Example:
SWAPF
Before Instruction
REG
=
After Instruction
REG
=
REG
0x53
0x35
; result is positive
SUBWFB REG, 0, 0
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
0x1B
0x1A
0x00
(0001 1011)
(0001 1010)
0x1B
0x00
0x01
0x01
0x00
(0001 1011)
; result is zero
SUBWFB REG, 1, 0
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
C
Z
N
10da
Description:
Words:
Decode
SWAPF f [,d [,a]]
=
=
=
=
DS41159E-page 318
0x03
0x0E
0x01
(0000 0011)
(0000 1101)
0xF5
(1111 0100)
; [2’s comp]
(0000 1101)
0x0E
0x00
0x00
0x01
; result is negative
© 2006 Microchip Technology Inc.
PIC18FXX8
TBLRD
Table Read
Syntax:
[ label ]
Operands:
None
Operation:
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT;
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) + 1 → TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) – 1 → TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 → TBLPTR;
(Prog Mem (TBLPTR)) → TABLAT
TBLRD ( *; *+; *-; +*)
Status Affected: None
Encoding:
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *=3 +*
Description:
This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to each
byte in the program memory. TBLPTR has a
2-Mbyte address range.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
Word
The TBLRD instruction can modify the value
of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
No operation
No
operation (Read Program operation
Memory)
Example 1:
TBLRD
*+ ;
Before Instruction
TABLAT
TBLPTR
MEMORY(0x00A356)
After Instruction
TABLAT
TBLPTR
Example 2:
TBLRD
No operation
(Write
TABLAT)
=
=
=
0x55
0x00A356
0x34
=
=
0x34
0x00A357
+* ;
Before Instruction
TABLAT
TBLPTR
MEMORY(0x01A357)
MEMORY(0x01A358)
After Instruction
TABLAT
TBLPTR
© 2006 Microchip Technology Inc.
=
=
=
=
0xAA
0x01A357
0x12
0x34
=
=
0x34
0x01A358
DS41159E-page 319
PIC18FXX8
TBLWT
Table Write
Syntax:
[ label ]
TBLWT Table Write (Continued)
TBLWT ( *; *+; *-; +*)
Words: 1
Operands:
None
Cycles: 2
Operation:
if TBLWT*,
(TABLAT) → Holding Register;
TBLPTR – No Change;
if TBLWT*+,
(TABLAT) → Holding Register;
(TBLPTR) + 1 → TBLPTR;
if TBLWT*-,
(TABLAT) → Holding Register;
(TBLPTR) – 1 → TBLPTR;
if TBLWT+*,
(TBLPTR) + 1 → TBLPTR;
(TABLAT) → Holding Register;
Q Cycle Activity:
Description:
0000
0000
0000
Q3
Q4
No
operation
No
operation
No
operation
Example 1:
11nn
nn=0 *
=1 *+
=2 *=3 +*
This instruction uses the 3 LSBs of TBLPTR to
determine which of the 8 holding registers the
TABLAT is written to. The holding registers are
used to program the contents of Program
Memory (P.M.). (Refer to Section 6.0 “Flash
Program Memory” for additional details.)
The TBLPTR (a 21-bit pointer) points to each
byte in the program memory. TBLPTR has a
2-Mbyte address range. The LSb of the
TBLPTR selects which byte of the program
memory location to access.
TBLPTR[0] = 0: Least Significant Byte
of Program Memory
Word
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
Word
The TBLWT instruction can modify the value
of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
DS41159E-page 320
Q2
No
No operation
No
operation
(Read
operation
TABLAT)
Status Affected: None
Encoding:
Q1
Decode
TBLWT
No operation
(Write to Holding
Register)
*+;
Before Instruction
TABLAT
=
0x55
TBLPTR
=
0x00A356
HOLDING REGISTER
(0x00A356)
=
0xFF
After Instructions (table write completion)
TABLAT
=
0x55
TBLPTR
=
0x00A357
HOLDING REGISTER
(0x00A356)
=
0x55
Example 2:
TBLWT
+*;
Before Instruction
TABLAT
=
0x34
TBLPTR
=
0x01389A
HOLDING REGISTER
(0x01389A)
=
0xFF
HOLDING REGISTER
(0x01389B)
=
0xFF
After Instruction (table write completion)
TABLAT
=
0x34
TBLPTR
=
0x01389B
HOLDING REGISTER
(0x01389A)
=
0xFF
HOLDING REGISTER
(0x01389B)
=
0x34
© 2006 Microchip Technology Inc.
PIC18FXX8
TSTFSZ
Test f, Skip if 0
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
skip if f = 0
Status Affected:
None
Encoding:
TSTFSZ f [,a]
Exclusive OR Literal with W
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operation:
(W) .XOR. k → W
Status Affected:
N, Z
Encoding:
0110
Description:
XORLW
011a
ffff
ffff
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction. If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
0000
XORLW k
1010
kkkk
kkkk
Description:
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
Example:
Before Instruction
W
=
After Instruction
W
=
XORLW
0xAF
0xB5
0x1A
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
NZERO
ZERO
TSTFSZ CNT
:
Example:
Before Instruction
PC
After Instruction
If CNT
PC
If CNT
PC
:
=
Address (HERE)
=
=
≠
=
0x00,
Address (ZERO)
0x00,
Address (NZERO)
© 2006 Microchip Technology Inc.
DS41159E-page 321
PIC18FXX8
XORWF
Exclusive OR W with f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .XOR. (f) → dest
Status Affected:
N, Z
Encoding:
0001
XORWF
10da
f [,d [,a]]
ffff
ffff
Description:
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
Before Instruction
REG
=
W
=
After Instruction
REG
=
W
=
DS41159E-page 322
REG
0xAF
0xB5
0x1A
0xB5
© 2006 Microchip Technology Inc.
PIC18FXX8
26.0
DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
• Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD 2
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM Demonstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
- KEELOQ® Evaluation and Programming Tools
- PICDEM MSC
- microID® Developer Kits
- CAN
- PowerSmart® Developer Kits
- Analog
26.1
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows®
based application that contains:
• An interface to debugging tools
- simulator
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Extensive on-line help
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
• Debug using:
- source files (assembly or C)
- mixed assembly and C
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increasing flexibility
and power.
26.2
MPASM Assembler
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and
generated machine code and COFF files for
debugging.
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User defined macros to streamline assembly code
• Conditional assembly for multi-purpose source
files
• Directives that allow complete control over the
assembly process
© 2006 Microchip Technology Inc.
DS41159E-page 323
PIC18FXX8
26.3
MPLAB C17 and MPLAB C18
C Compilers
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
26.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB object librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
26.5
MPLAB C30 C Compiler
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command
line options and language extensions to take full
advantage of the dsPIC30F device hardware capabilities and afford fine control of the compiler code
generator.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been validated and conform to the ANSI C library standard. The
library includes functions for string manipulation,
dynamic memory allocation, data conversion, timekeeping and math functions (trigonometric, exponential
and hyperbolic). The compiler provides symbolic
information for high-level source debugging with the
MPLAB IDE.
DS41159E-page 324
26.6
MPLAB ASM30 Assembler, Linker
and Librarian
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire dsPIC30F instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
26.7
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until
Break or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
26.8
MPLAB SIM30 Software Simulator
The MPLAB SIM30 software simulator allows code
development in a PC hosted environment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler. The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high-speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
© 2006 Microchip Technology Inc.
PIC18FXX8
26.9
MPLAB ICE 2000
High-Performance Universal
In-Circuit Emulator
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of different processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
26.10 MPLAB ICE 4000
High-Performance Universal
In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for highend PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, up to 2 Mb of emulation memory and the
ability to view variables in real-time.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
© 2006 Microchip Technology Inc.
26.11 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the Flash devices. This feature, along with
Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM)
protocol, offers cost effective in-circuit Flash debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.
26.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
26.13 MPLAB PM3 Device Programmer
The MPLAB PM3 is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
a large LCD display (128 x 64) for menus and error
messages and a modular detachable socket assembly
to support various package types. The ICSP™ cable
assembly is included as a standard item. In StandAlone mode, the MPLAB PM3 device programmer can
read, verify and program PICmicro devices without a
PC connection. It can also set code protection in this
mode. MPLAB PM3 connects to the host PC via an RS232 or USB cable. MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates
an SD/MMC card for file storage and secure data applications.
DS41159E-page 325
PIC18FXX8
26.14 PICSTART Plus Development
Programmer
26.17 PICDEM 2 Plus
Demonstration Board
The PICSTART Plus development programmer is an
easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
The PICDEM 2 Plus demonstration board supports
many 18, 28 and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the necessary hardware and software is included to run the demonstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB ICD 2 and MPLAB ICE in-circuit emulators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display, a piezo speaker, an on-board temperature
sensor, four LEDs and sample PIC18F452 and
PIC16F877 Flash microcontrollers.
26.15 PICDEM 1 PICmicro
Demonstration Board
The PICDEM 1 demonstration board demonstrates the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provided with the PICDEM 1 demonstration board can
be programmed with a PRO MATE II device programmer or a PICSTART Plus development programmer.
The PICDEM 1 demonstration board can be connected
to the MPLAB ICE in-circuit emulator for testing. A
prototype area extends the circuitry for additional application components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
26.16 PICDEM.net Internet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface connector, an Ethernet interface, RS-232 interface and a
16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by Jeremy Bentham
DS41159E-page 326
26.18 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
26.19 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capabilities of the 8, 14 and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320
family of microcontrollers. PICDEM 4 is intended to
showcase the many features of these low pin count
parts, including LIN and Motor Control using ECCP.
Special provisions are made for low-power operation
with the supercapacitor circuit and jumpers allow onboard hardware to be disabled to eliminate current
draw in this mode. Included on the demo board are provisions for Crystal, RC or Canned Oscillator modes, a
five volt regulator for use with a nine volt wall adapter
or battery, DB-9 RS-232 interface, ICD connector for
programming via ICSP and development with MPLAB
ICD 2, 2 x 16 liquid crystal display, PCB footprints for
H-Bridge motor driver, LIN transceiver and EEPROM.
Also included are: header for expansion, eight LEDs,
four potentiometers, three push buttons and a prototyping area. Included with the kit is a PIC16F627A and
a PIC18F1320. Tutorial firmware is included along
with the User’s Guide.
© 2006 Microchip Technology Inc.
PIC18FXX8
26.20 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device
programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board Flash memory. A
generous prototype area is available for user hardware
expansion.
26.21 PICDEM 18R PIC18C601/801
Demonstration Board
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/Demultiplexed and 16-bit
Memory modes. The board includes 2 Mb external
Flash memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
26.22 PICDEM LIN PIC16C43X
Demonstration Board
The powerful LIN hardware and software kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
on-board LIN transceivers. A PIC16F874 Flash
microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide
LIN bus communication.
26.24 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM USB Demonstration Board shows off the
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
26.25 Evaluation and
Programming Tools
In addition to the PICDEM series of circuits, Microchip
has a line of evaluation kits and demonstration software
for these products.
• KEELOQ evaluation and programming tools for
Microchip’s HCS Secure Data Products
• CAN developers kit for automotive network
applications
• Analog design boards and filter design software
• PowerSmart battery charging evaluation/
calibration kits
• IrDA® development kit
• microID development and rfLabTM development
software
• SEEVAL® designer kit for memory evaluation and
endurance calculations
• PICDEM MSC demo boards for Switching mode
power supply, high-power IR driver, delta sigma
ADC and flow rate sensor
Check the Microchip web page and the latest Product
Selector Guide for the complete list of demonstration
and evaluation kits.
26.23 PICkitTM 1 Flash Starter Kit
A complete “development system in a box”, the PICkit™
Flash Starter Kit includes a convenient multi-section
board for programming, evaluation and development of
8/14-pin Flash PIC® microcontrollers. Powered via USB,
the board operates under a simple Windows GUI. The
PICkit 1 Starter Kit includes the User’s Guide (on CD
ROM), PICkit 1 tutorial software and code for various
applications. Also included are MPLAB® IDE (Integrated
Development Environment) software, software and
hardware “Tips 'n Tricks for 8-pin Flash PIC®
Microcontrollers” Handbook and a USB interface cable.
Supports all current 8/14-pin Flash PIC microcontrollers,
as well as many future planned devices.
© 2006 Microchip Technology Inc.
DS41159E-page 327
PIC18FXX8
NOTES:
DS41159E-page 328
© 2006 Microchip Technology Inc.
PIC18FXX8
27.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to VSS ............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) .......................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...................................................................................................±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports (combined) ....................................................................................................200 mA
Maximum current sourced by all ports (combined) ...............................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather
than pulling this pin directly to VSS.
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
© 2006 Microchip Technology Inc.
DS41159E-page 329
PIC18FXX8
FIGURE 27-1:
PIC18FXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
Voltage
5.0V
PIC18FXX8
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
Frequency
FIGURE 27-2:
PIC18FXX8 VOLTAGE-FREQUENCY GRAPH (EXTENDED)
6.0V
5.5V
Voltage
5.0V
PIC18FXX8
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
25 MHz
Frequency
DS41159E-page 330
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-3:
PIC18LFXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
Voltage
5.0V
PIC18LFXX8
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
4 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V = 40 MHz, if VDDAPPMIN > 4.2V
Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
© 2006 Microchip Technology Inc.
DS41159E-page 331
PIC18FXX8
27.1
DC Characteristics
PIC18LFXX8
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18FXX8
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
Symbol
No.
VDD
D001
D001
Characteristic/
Device
Min
Typ
Max Units
PIC18LFXX8
2.0
—
5.5
V
PIC18FXX8
Conditions
Supply Voltage
4.2
—
5.5
V
D002
VDR
RAM Data Retention
Voltage(1)
1.5
—
—
V
D003
VPOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
—
0.7
V
D004
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
—
—
VBOR
Brown-out Reset Voltage
BORV1:BORV0 = 11 1.96
—
2.16
V
BORV1:BORV0 = 10 2.64
—
2.92
V
BORV1:BORV0 = 01 4.07
—
4.59
V
BORV1:BORV0 = 00 4.36
—
4.92
V
BORV1:BORV0 = 1x N.A.
—
N.A.
V
BORV1:BORV0 = 01 4.07
—
4.59
V
BORV1:BORV0 = 00 4.36
—
4.92
V
HS, XT, RC and LP Oscillator modes
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
PIC18LFXX8
D005
PIC18FXX8
D005
Not in operating voltage range of device
Legend: Rows are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS
and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC oscillator configuration, current through REXT is not included. The current through the resistor can
be estimated by the formula Ir = VDD/2 REXT (mA) with REXT in kOhm.
5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not
additive. Once one of these modules is enabled, the other may also be enabled without further penalty.
DS41159E-page 332
© 2006 Microchip Technology Inc.
PIC18FXX8
27.1
DC Characteristics (Continued)
PIC18LFXX8
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18FXX8
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
Symbol
No.
IDD
Characteristic/
Device
Min
Typ
Max Units
Conditions
—
—
—
.7
.7
1.7
2
2
4
mA
mA
mA
—
—
—
1
1
2.5
2.5
2.5
5
mA
mA
mA
—
—
—
.7
.7
1.8
2.5
2.5
4
mA
mA
mA
—
—
—
1.7
1.7
1.7
4
4
4
mA
mA
mA
—
—
—
2.5
2.5
2.5
5
5
6
mA
mA
mA
—
—
—
1.8
1.8
1.8
4
5
5
mA
mA
mA
XT oscillator configuration
VDD = 4.2V, +25°C, FOSC = 4 MHz
VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz
VDD = 4.2V, -40°C to +125°C, FOSC = 4 MHz
RC oscillator configuration
VDD = 4.2V, +25°C, FOSC = 4 MHz
VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz
VDD = 4.2V, -40°C to +125°C, FOSC = 4 MHz
RCIO oscillator configuration
VDD = 4.2V, +25°C, FOSC = 4 MHz
VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz
VDD = 4.2V, -40°C to +125°C, FOSC = 4 MHz
—
18
40
μA
LP oscillator, FOSC = 32 kHz, WDT disabled
VDD = 2.0V, -40°C to +85°C
—
—
60
60
150
180
μA
μA
LP oscillator, FOSC = 32 kHz, WDT disabled
VDD = 4.2V, -40°C to +85°C
VDD = 4.2V, -40°C to +125°C
Supply Current(2,3,4)
D010
D010
D010A
D010A
PIC18LFXX8
PIC18FXX8
PIC18LFXX8
PIC18FXX8
XT oscillator configuration
VDD = 2.0V, +25°C, FOSC = 4 MHz
VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz
VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz
RC oscillator configuration
VDD = 2.0V, +25°C, FOSC = 4 MHz
VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz
VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz
RCIO oscillator configuration
VDD = 2.0V, +25°C, FOSC = 4 MHz
VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz
VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz
Legend: Rows are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS
and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC oscillator configuration, current through REXT is not included. The current through the resistor can
be estimated by the formula Ir = VDD/2 REXT (mA) with REXT in kOhm.
5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not
additive. Once one of these modules is enabled, the other may also be enabled without further penalty.
© 2006 Microchip Technology Inc.
DS41159E-page 333
PIC18FXX8
27.1
DC Characteristics (Continued)
PIC18LFXX8
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18FXX8
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
Symbol
No.
IDD
D010C
Characteristic/
Device
Min
Typ
Max Units
—
21
28
mA
—
21
30
mA
—
—
1.3
18
3
28
mA
mA
—
28
40
mA
—
18
28
mA
—
28
40
mA
HS oscillator configurations
FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc configuration
FOSC = 10 MHz, VDD = 5.5V
—
32
65
μA
Timer1 oscillator configuration
FOSC = 32 kHz, VDD = 2.0V
—
—
62
62
250
310
μA
μA
Timer1 oscillator configuration
FOSC = 32 kHz, VDD = 4.2V, -40°C to +85°C
FOSC = 32 kHz, VDD = 4.2V, -40°C to +125°C
—
—
0.3
2
4
10
μA
μA
VDD = 2.0V, -40°C to +85°C
VDD = 4.2V, -40°C to +85°C
—
2
10
μA
VDD = 4.2V, -40°C to +85°C
—
6
40
μA
VDD = 4.2V, -40°C to +125°C
Supply Current(2,3,4)
PIC18LFXX8
D010C
PIC18FXX8
D013
PIC18LFXX8
D013
PIC18FXX8
D014
PIC18LFXX8
D014
PIC18FXX8
IPD
D020
D020
D021B
Conditions
EC, ECIO oscillator configurations
VDD = 4.2V, -40°C to +85°C
EC, ECIO oscillator configurations
VDD = 4.2V, -40°C to +125°C,
FOSC = 25 MHz
HS oscillator configurations
FOSC = 6 MHz, VDD = 2.0V
FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc configuration
FOSC = 10 MHz, VDD = 5.5V
Power-Down Current(3)
PIC18LFXX8
PIC18FXX8
Legend: Rows are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS
and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC oscillator configuration, current through REXT is not included. The current through the resistor can
be estimated by the formula Ir = VDD/2 REXT (mA) with REXT in kOhm.
5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not
additive. Once one of these modules is enabled, the other may also be enabled without further penalty.
DS41159E-page 334
© 2006 Microchip Technology Inc.
PIC18FXX8
27.1
DC Characteristics (Continued)
PIC18LFXX8
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18FXX8
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
Symbol
No.
ΔIWDT
Characteristic/
Device
Min
Typ
Max Units
Conditions
Module Differential Current
D022
Watchdog Timer
PIC18LFXX8
—
—
—
0.75
0.8
7
1.5
8
25
μA
μA
μA
VDD = 2.5V, +25°C
VDD = 2.0V, -40°C to +85°C
VDD = 4.2V, -40°C to +85°C
D022
Watchdog Timer
PIC18FXX8
—
—
—
7
7
7
25
25
45
μA
μA
μA
VDD = 4.2V, +25°C
VDD = 4.2V, -40°C to +85°C
VDD = 4.2V, -40°C to +125°C
D022A ΔIBOR
Brown-out Reset(5)
PIC18LFXX8
—
—
—
38
42
49
50
55
65
μA
μA
μA
VDD = 2.0V, +25°C
VDD = 2.0V, -40°C to +85°C
VDD = 4.2V, -40°C to +85°C
D022A
Brown-out Reset(5)
PIC18FXX8
—
—
—
46
49
50
65
65
75
μA
μA
μA
VDD = 4.2V, +25°C
VDD = 4.2V, -40°C to +85°C
VDD = 4.2V, -40°C to +125°C
D022B ΔILVD
Low-Voltage Detect(5)
PIC18LFXX8
—
—
—
36
40
47
50
55
65
μA
μA
μA
VDD = 2.0V, +25°C
VDD = 2.0V, -40°C to +85°C
VDD = 4.2V, -40°C to +85°C
D022B
Low-Voltage Detect(5)
PIC18FXX8
—
—
—
44
47
47
65
65
75
μA
μA
μA
VDD = 4.2V, +25°C
VDD = 4.2V, -40°C to +85°C
VDD = 4.2V, -40°C to +125°C
Timer1 Oscillator
PIC18LFXX8
—
—
—
6.2
6.2
7.5
40
45
55
μA
μA
μA
VDD = 2.0V, +25°C
VDD = 2.0V, -40°C to +85°C
VDD = 4.2V, -40°C to +85°C
Timer1 Oscillator
PIC18FXX8
—
—
—
7.5
7.5
7.5
55
55
65
μA
μA
μA
VDD = 4.2V, +25°C
VDD = 4.2V, -40°C to +85°C
VDD = 4.2V, -40°C to +125°C
D025
D025
ΔITMR1
Legend: Rows are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS
and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC oscillator configuration, current through REXT is not included. The current through the resistor can
be estimated by the formula Ir = VDD/2 REXT (mA) with REXT in kOhm.
5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not
additive. Once one of these modules is enabled, the other may also be enabled without further penalty.
© 2006 Microchip Technology Inc.
DS41159E-page 335
PIC18FXX8
27.2
DC Characteristics: PIC18FXX8 (Industrial, Extended)
PIC18LFXX8 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic/
Device
Min
Max
Units
Conditions
with TTL buffer
VSS
0.15 VDD
V
VDD < 4.5V
—
0.8
V
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
RC3 and RC4
VSS
VSS
0.2 VDD
0.3 VDD
V
V
Input Low Voltage
I/O ports:
D030
D030A
D031
D032
MCLR
VSS
0.2 VDD
V
D032A
OSC1 (in XT, HS and LP modes)
and T1OSI
VSS
0.3 VDD
V
D033
OSC1 (in RC mode)(1)
VSS
0.2 VDD
V
0.25 VDD + 0.8V
VDD
V
VDD < 4.5V
4.5V ≤ VDD ≤ 5.5V
VIH
Input High Voltage
I/O ports:
D040
with TTL buffer
D040A
D041
with Schmitt Trigger buffer
RC3 and RC4
2.0
VDD
V
0.8 VDD
0.7 VDD
VDD
VDD
V
V
D042
MCLR
0.8 VDD
VDD
V
D042A
OSC1 (in XT, HS and LP modes)
and T1OSI
0.7 VDD
VDD
V
D043
OSC1 (RC mode)(1)
0.9 VDD
VDD
V
Input Leakage Current(2,3)
IIL
D060
I/O ports
—
±1
μA
VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061
MCLR
—
±5
μA
Vss ≤ VPIN ≤ VDD
D063
OSC1
—
±5
μA
Vss ≤ VPIN ≤ VDD
50
450
μA
VDD = 5V, VPIN = VSS
D070
IPU
Weak Pull-up Current
IPURB
PORTB weak pull-up current
Note 1:
2:
3:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro® device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
DS41159E-page 336
© 2006 Microchip Technology Inc.
PIC18FXX8
27.2
DC Characteristics: PIC18FXX8 (Industrial, Extended)
PIC18LFXX8 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
Symbol
No.
VOL
D080
Characteristic/
Device
D080A
OSC2/CLKO
(RC mode)
D083A
VOH
D090
D090A
OSC2/CLKO
(RC mode)
D092A
D150
VOD
Units
Conditions
—
0.6
V
IOL = 8.5 mA, VDD = 4.2V,
-40°C to +85°C
—
0.6
V
IOL = 7.0 mA, VDD = 4.2V,
-40°C to +125°C
—
0.6
V
IOL = 1.6 mA, VDD = 4.2V,
-40°C to +85°C
—
0.6
V
IOL = 1.2 mA, VDD = 4.2V,
-40°C to +125°C
VDD – 0.7
—
V
IOH = -3.0 mA, VDD = 4.2V,
-40°C to +85°C
VDD – 0.7
—
V
IOH = -2.5 mA, VDD = 4.2V,
-40°C to +125°C
VDD – 0.7
—
V
IOH = -1.3 mA, VDD = 4.2V,
-40°C to +85°C
VDD – 0.7
—
V
IOH = -1.0 mA, VDD = 4.2V,
-40°C to +125°C
—
7.5
V
RA4 pin
Output High Voltage(3)
I/O ports
D092
Max
Output Low Voltage
I/O ports
D083
Min
Open-Drain High Voltage
Capacitive Loading Specs on
Output Pins
D101
CIO
All I/O pins and OSC2
(in RC mode)
—
50
pF
To meet the AC Timing
Specifications
D102
CB
SCL, SDA
—
400
pF
In I2C™ mode
Note 1:
2:
3:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro® device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
© 2006 Microchip Technology Inc.
DS41159E-page 337
PIC18FXX8
FIGURE 27-4:
LOW-VOLTAGE DETECT CHARACTERISTICS
VDD
(LVDIF can be
cleared in software)
VLVD
(LVDIF set by hardware)
37
LVDIF
TABLE 27-1:
LOW-VOLTAGE DETECT CHARACTERISTICS
Low-Voltage Detect Characteristics
Param
Symbol
No.
D420
VLVD
DS41159E-page 338
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Characteristic
LVD Voltage
Min
Typ
Max
Units
Conditions
LVV = 0001
1.96
2.06
2.16
V
T ≥ 25°C
LVV = 0010
2.16
2.27
2.38
V
T ≥ 25°C
LVV = 0011
2.35
2.47
2.59
V
T ≥ 25°C
LVV = 0100
2.43
2.58
2.69
V
LVV = 0101
2.64
2.78
2.92
V
LVV = 0110
2.75
2.89
3.03
V
LVV = 0111
2.95
3.1
3.26
V
LVV = 1000
3.24
3.41
3.58
V
LVV = 1001
3.43
3.61
3.79
V
LVV = 1010
3.53
3.72
3.91
V
LVV = 1011
3.72
3.92
4.12
V
LVV = 1100
3.92
4.13
4.34
V
LVV = 1101
4.07
4.33
4.59
V
LVV = 1110
4.36
4.64
4.92
V
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 27-2:
DC CHARACTERISTICS: EEPROM AND ENHANCED FLASH
DC Characteristics
Param
No.
Sym
Standard Operating Conditions
Characteristic
Min
Typ†
Max
Units
9.00
—
13.25
V
—
—
10
mA
Conditions
Internal Program Memory
Programming Specifications
D110
VPP
Voltage on MCLR/VPP pin
D113
IDDP
Supply Current during
Programming
Data EEPROM Memory
D120
ED
Cell Endurance
100K
1M
—
E/W
-40°C to +85°C
D120A
ED
Byte Endurance
10K
100K
—
E/W
+85°C to +125°C
D121
VDRW
VDD for Read/Write
VMIN
—
5.5
V
Using EECON to read/write
VMIN = Minimum operating voltage
D122
TDEW
Erase/Write Cycle Time
—
4
—
ms
D123
TRETD Characteristic Retention
40
—
—
Year
D124
TREF
Number of Total Erase/Write
Cycles to Data EEPROM before
Refresh*
1M
10M
—
Cycles -40°C to +85°C
D124A
TREF
Number of Total Erase/Write
Cycles before Refresh*
100K
1M
—
Cycles +85°C to +125°C
D130
EP
Cell Endurance
10K
100K
—
E/W
-40°C to +85°C
D130A
EP
Cell Endurance
1000
10K
—
E/W
+85°C to +125°C
D131
VPR
VDD for Read
VMIN
—
5.5
V
Provided no other specifications
are violated
Program Flash Memory
VMIN = Minimum operating voltage
D132
VIE
VDD for Block Erase
4.5
—
5.5
V
Using ICSP™ port
D132A
VIW
VDD for Externally Timed Erase
or Write
4.5
—
5.5
V
Using ICSP port
D132B
VPEW
VDD for Self-Timed Write
VMIN
—
5.5
V
VMIN = Minimum operating voltage
D133
TIE
ICSP Erase Cycle Time
—
4
—
ms
D133A
TIW
ICSP Erase or Write Cycle Time
(externally timed)
1
—
—
ms
D133A
TIW
Self-Timed Write Cycle Time
—
2
—
ms
D134
TRETD Characteristic Retention
40
—
—
Year
VDD ≥ 4.5V
VDD ≥ 4.5V
Provided no other specifications
are violated
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
* See Section 5.8 “Using the Data EEPROM” for more information.
© 2006 Microchip Technology Inc.
DS41159E-page 339
PIC18FXX8
TABLE 27-3:
COMPARATOR SPECIFICATIONS
Operating Conditions: VDD range as described in Section 27.1 “DC Characteristics”, -40°C < TA < +125°C
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
Comments
D300
VIOFF
Input Offset Voltage
—
±5.0
±10
mV
D301
VICM
Input Common Mode Voltage
0
—
VDD – 1.5
V
D302
CMRR
CMRR
+55*
—
—
db
D300
TRESP
Response Time(1)
—
300*
350*
400*
600*
ns
ns
D301
TMC2OV Comparator Mode Change to
Output Valid
—
—
10*
μs
*
Note 1:
These parameters are characterized but not tested.
Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from
VSS to VDD.
TABLE 27-4:
PIC18FXX8
PIC18LFXX8
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: VDD range as described in Section 27.1 “DC Characteristics”, -40°C < TA < +125°C
Param No.
Sym
Characteristics
Min
Typ
Max
Units
D310
VRES
Resolution
VDD/24
—
VDD/32
LSB
D311
VRAA
Absolute Accuracy
—
—
0.5
LSB
D312
VRUR
Unit Resistor Value (R)
—
2K*
—
Ω
TSET
Time(1)
—
—
10*
μs
D310
*
Note 1:
Settling
Comments
These parameters are characterized but not tested.
Settling time measured while CVRR = 1 and CVR transitions from 0000 to 1111.
DS41159E-page 340
© 2006 Microchip Technology Inc.
PIC18FXX8
27.3
27.3.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
2. TppS
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-Impedance
High
Low
High
Low
Hold
SU
Setup
DATA input hold
Start condition
STO
Stop condition
pp
cc
CCP1
ck
CLKO
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
H
I
L
Fall
High
Invalid (High-Impedance)
Low
I2C only
AA
output access
BUF
Bus free
TCC:ST (I2C specifications only)
CC
HD
ST
DAT
STA
© 2006 Microchip Technology Inc.
DS41159E-page 341
PIC18FXX8
27.3.2
TIMING CONDITIONS
The temperature and voltages specified in Table 27-5
apply to all timing specifications unless otherwise
noted. Figure 27-5 specifies the load conditions for the
timing specifications.
TABLE 27-5:
TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
AC CHARACTERISTICS
FIGURE 27-5:
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC specification,
Section 27.1 “DC Characteristics”.
LF parts operate for industrial temperatures only.
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1
Load Condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464Ω
VSS
DS41159E-page 342
CL = 50 pF
for all pins except OSC2/CLKO
and including D and E outputs as ports
© 2006 Microchip Technology Inc.
PIC18FXX8
27.3.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 27-6:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
3
4
4
2
CLKO
TABLE 27-6:
Param
Symbol
No.
1A
1
FOSC
TOSC
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic
Min
Max
External CLKI Frequency(1)
Oscillator Frequency(1)
DC
40
MHz EC, ECIO oscillator, -40°C to +85°C
DC
25
MHz EC, ECIO oscillator, +85°C to +125°C
DC
4
MHz RC oscillator
0.1
4
MHz XT oscillator
4
25
MHz HS oscillator, -40°C to +85°C
4
25
MHz HS oscillator, +85°C to +125°C
4
10
MHz HS + PLL oscillator, -40°C to +85°C
4
6.25
MHz HS + PLL oscillator, +85°C to +125°C
DC
200
kHz
25
—
ns
EC, ECIO oscillator, -40°C to +85°C
External CLKI Period(1)
Oscillator Period(1)
Time(1)
2
TCY
Instruction Cycle
3
TosL,
TosH
External Clock in (OSC1)
High or Low Time
4
TosR,
TosF
Note 1:
External Clock in (OSC1)
Rise or Fall Time
Units
Conditions
LP oscillator
40
—
ns
EC, ECIO oscillator, +85°C to +125°C
250
—
ns
RC oscillator
250
10,000
ns
XT oscillator
40
—
ns
HS oscillator, -40°C to +85°C
40
—
ns
HS oscillator, +85°C to +125°C
100
250
ns
HS + PLL oscillator, -40°C to +85°C
160
250
ns
HS + PLL oscillator, +85°C to +125°C
5
200
μs
LP oscillator
100
160
—
—
ns
ns
TCY = 4/FOSC, -40°C to +85°C
TCY = 4/FOSC, +85°C to +125°C
30
—
ns
XT oscillator
2.5
—
ns
LP oscillator
10
—
μs
HS oscillator
—
20
ns
XT oscillator
—
50
ns
LP oscillator
—
7.5
ns
HS oscillator
Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “Min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“Max.” cycle time limit is “DC” (no clock) for all devices.
© 2006 Microchip Technology Inc.
DS41159E-page 343
PIC18FXX8
TABLE 27-7:
Param No.
PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V)
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
HS mode only
HS mode only
—
—
FOSC Oscillator Frequency Range
FSYS On-Chip VCO System Frequency
4
16
—
—
10
40
MHz
MHz
—
trc
PLL Start-up Time (Lock Time)
—
—
2
ms
ΔCLK
CLKO Stability (Jitter)
-2
—
+2
%
—
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 27-7:
CLKO AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKO
13
19
14
12
18
16
I/O Pin
(Input)
15
17
I/O Pin
(Output)
New Value
Old Value
20, 21
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-8:
CLKO AND I/O TIMING REQUIREMENTS
Param No. Symbol
Characteristic
Min
Typ
Max
Units Conditions
10
TosH2ckL OSC1 ↑ to CLKO ↓
—
75
200
ns
(1)
11
TosH2ckH OSC1 ↑ to CLKO ↑
—
75
200
ns
(1)
12
TckR
—
35
100
ns
(1)
CLKO Rise Time
13
TckF
CLKO Fall Time
—
35
100
ns
(1)
14
TckL2ioV
CLKO ↓ to Port Out Valid
—
—
0.5 TCY + 20
ns
(1)
15
TioV2ckH Port In Valid before CLKO ↑
0.25 TCY + 25
—
—
ns
(1)
16
TckH2ioI
Port In Hold after CLKO ↑
0
—
—
ns
(1)
17
TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid
—
50
150
ns
18
TosH2ioI
18A
OSC1 ↑ (Q2 cycle) to Port
Input Invalid (I/O in hold time)
PIC18FXX8
100
—
—
ns
PIC18LFXX8
200
—
—
ns
19
TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup time)
0
—
—
ns
20
TIOR
PIC18FXX8
—
10
25
ns
PIC18LFXX8
—
—
60
ns
PIC18FXX8
—
10
25
ns
PIC18LFXX8
—
—
60
ns
Port Output Rise Time
20A
21
TIOF
Port Output Fall Time
21A
22†
TINP
INT pin High or Low Time
TCY
—
—
ns
23†
TRBP
RB7:RB4 Change INT High or Low Time
TCY
—
—
ns
24†
TRCP
RC7:RC4 Change INT High or Low Time
20
—
—
ns
†
Note 1:
These parameters are asynchronous events not related to any internal clock edges.
Measurements are taken in RC mode where CLKO pin output is 4 x TOSC.
DS41159E-page 344
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 27-5 for load conditions.
FIGURE 27-9:
BROWN-OUT RESET AND LOW-VOLTAGE DETECT TIMING
BVDD (for 35)
VLVD (for 37)
VDD
35, 37
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
TABLE 27-9:
36
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
BROWN-OUT RESET AND LOW-VOLTAGE DETECT REQUIREMENTS
Param
No.
Symbol
30
TmcL
MCLR Pulse Width (low)
2
—
—
μs
31
TWDT
Watchdog Timer Time-out Period
(no prescaler)
7
18
33
ms
Characteristic
Min
Typ
Max
Units
32
TOST
Oscillation Start-up Timer Period
1024 TOSC
—
1024 TOSC
—
33
TPWRT
Power-up Timer Period
28
72
132
ms
34
TIOZ
I/O High-Impedance from MCLR Low
or Watchdog Timer Reset
—
2
—
μs
35
TBOR
Brown-out Reset Pulse Width
36
TIRVST
Time for Internal Reference
Voltage to become stable
37
TLVD
Low-Voltage Detect Pulse Width
© 2006 Microchip Technology Inc.
200
—
—
μs
—
20
50
μs
200
—
—
μs
Conditions
TOSC = OSC1 period
For VDD ≤ BVDD (see D005)
For VDD ≤ VLVD (see D420)
DS41159E-page 345
PIC18FXX8
FIGURE 27-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-10: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
No.
Characteristic
40
Tt0H
T0CKI High Pulse Width
41
Tt0L
T0CKI Low Pulse Width
42
Tt0P
T0CKI Period
No prescaler
With prescaler
No prescaler
With prescaler
No prescaler
With prescaler
45
Tt1H
T1CKI
High Time
Synchronous, no prescaler
Synchronous, PIC18FXX8
with prescaler PIC18LFXX8
Asynchronous PIC18FXX8
PIC18LFXX8
46
Tt1L
T1CKI
Low Time
Synchronous, no prescaler
Synchronous, PIC18FXX8
with prescaler PIC18LFXX8
Asynchronous PIC18FXX8
PIC18LFXX8
47
48
Min
Max
Units
0.5 TCY + 20
—
ns
10
—
ns
0.5 TCY + 20
—
ns
10
—
ns
TCY + 10
—
ns
Greater of:
20 ns or TCY + 40
N
—
ns
0.5 TCY + 20
—
ns
10
—
ns
25
—
ns
30
—
ns
50
—
ns
0.5 TCY + 5
—
ns
10
—
ns
25
—
ns
30
—
ns
TBD
TBD
ns
Greater of:
20 ns or TCY + 40
N
—
ns
Tt1P
T1CKI
Synchronous
Input Period
Asynchronous
60
—
ns
Ft1
T1CKI Oscillator Input Frequency Range
DC
50
kHz
2 TOSC
7 TOSC
—
Tcke2tmrI Delay from External T1CKI Clock Edge to
Timer Increment
Conditions
N = prescale value
(1, 2, 4,..., 256)
N = prescale value
(1, 2, 4, 8)
Legend: TBD = To Be Determined
DS41159E-page 346
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-11:
CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND ECCP1)
CCPx
(Capture Mode)
50
51
52
CCPx
(Compare or PWM Mode)
54
53
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-11: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND ECCP1)
Param
Symbol
No.
50
TccL
Characteristic
CCPx Input Low Time No prescaler
With
prescaler
51
TccH
PIC18FXX8
PIC18LFXX8
52
TccP
CCPx Input Period
53
TccR
CCPx Output Fall Time
54
TccF
CCPx Output Fall Time
© 2006 Microchip Technology Inc.
Max
Units
0.5 TCY + 20
—
ns
10
—
ns
20
—
ns
0.5 TCY + 20
—
ns
PIC18FXX8
10
—
ns
PIC18LFXX8
20
—
ns
3 TCY + 40
N
—
ns
—
25
ns
CCPx Input High Time No prescaler
With
prescaler
Min
PIC18FXX8
PIC18LFXX8
—
45
ns
PIC18FXX8
—
25
ns
PIC18LFXX8
—
45
ns
Conditions
N = prescale
value (1, 4 or 16)
DS41159E-page 347
PIC18FXX8
FIGURE 27-12:
PARALLEL SLAVE PORT TIMING (PIC18F248 AND PIC18F458)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-12: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F248 AND PIC18F458)
Param
No.
62
Symbol
TdtV2wrH
Characteristic
Min
Max
Units
Conditions
Data-In Valid before WR ↑ or CS ↑
(setup time)
20
25
—
—
ns
ns
Extended Temp. range
20
—
ns
63
TwrH2dtI
WR ↑ or CS ↑ to Data-In Invalid PIC18FXX8
(hold time)
PIC18LFXX8
64
TrdL2dtV
RD ↓ and CS ↓ to Data-Out Valid
35
—
ns
—
—
80
90
ns
ns
65
TrdH2dtI
RD ↑ or CS ↓ to Data-Out Invalid
10
30
ns
66
TibfINH
Inhibit the IBF flag bit being cleared from
WR ↑ or CS ↑
—
3 TCY
ns
DS41159E-page 348
Extended Temp. range
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-13:
EXAMPLE SPI™ MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
Bit 6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb In
Bit 6 - - - -1
LSb In
74
73
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-13: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
70
TssL2scH,
TssL2scL
SS ↓ to SCK ↓ or SCK ↑ Input
71
TscH
SCK Input High Time
(Slave mode)
SCK Input Low Time
(Slave mode)
71A
72
TscL
72A
Min
Max Units
TCY
—
ns
Continuous
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
Continuous
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
100
—
ns
1.5 TCY + 40
—
ns
100
—
ns
—
25
ns
73
TdiV2scH,
TdiV2scL
Setup Time of SDI Data Input to SCK Edge
73A
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
74
TscH2diL,
TscL2diL
Hold Time of SDI Data Input to SCK Edge
75
TdoR
SDO Data Output Rise Time
76
TdoF
SDO Data Output Fall Time
78
TscR
SCK Output Rise Time
(Master mode)
PIC18FXX8
PIC18LFXX8
—
45
ns
—
25
ns
PIC18FXX8
—
25
ns
PIC18LFXX8
—
45
ns
79
TscF
SCK Output Fall Time (Master mode)
—
25
ns
80
TscH2doV,
TscL2doV
SDO Data Output Valid after
SCK Edge
PIC18FXX8
—
50
ns
PIC18LFXX8
—
100
ns
Note 1:
2:
Conditions
(Note 1)
(Note 1)
(Note 2)
Requires the use of parameter #73A.
Only if parameter #71A and #72A are used.
© 2006 Microchip Technology Inc.
DS41159E-page 349
PIC18FXX8
FIGURE 27-14:
EXAMPLE SPI™ MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
MSb
SDO
Bit 6 - - - - - -1
LSb
Bit 6 - - - -1
LSb In
75, 76
SDI
MSb In
74
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-14: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param
No.
71
Symbol
TscH
71A
72
TscL
72A
Characteristic
Min
Max Units
SCK Input High Time
(Slave mode)
Continuous
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
SCK Input Low Time
(Slave mode)
Continuous
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
100
—
ns
1.5 TCY + 40
—
ns
100
—
ns
—
25
ns
73
TdiV2scH,
TdiV2scL
Setup Time of SDI Data Input to SCK Edge
73A
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
74
TscH2diL,
TscL2diL
Hold Time of SDI Data Input to SCK Edge
75
TdoR
SDO Data Output Rise Time
76
TdoF
SDO Data Output Fall Time
78
TscR
SCK Output Rise Time
(Master mode)
PIC18FXX8
PIC18LFXX8
—
45
ns
—
25
ns
PIC18FXX8
—
25
ns
PIC18LFXX8
—
45
ns
79
TscF
SCK Output Fall Time (Master mode)
—
25
ns
80
TscH2doV,
TscL2doV
SDO Data Output Valid after
SCK Edge
—
50
ns
—
100
ns
81
TdoV2scH, SDO Data Output Setup to SCK Edge
TdoV2scL
TCY
—
ns
Note 1:
2:
PIC18FXX8
PIC18LFXX8
Conditions
(Note 1)
(Note 1)
(Note 2)
Requires the use of parameter #73A.
Only if parameter #71A and #72A are used.
DS41159E-page 350
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-15:
EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
SDO
MSb
Bit 6 - - - - - -1
LSb
77
75, 76
SDI
MSb In
73
Bit 6 - - - -1
LSb In
74
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-15: EXAMPLE SPI™ MODE REQUIREMENTS, SLAVE MODE TIMING (CKE = 0)
Param
No.
Symbol
Characteristic
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
71
TscH
SCK Input High Time (Slave mode)
TscL
SCK Input Low Time (Slave mode)
71A
72
72A
73
Min
TCY
—
ns
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
Continuous
1.25 TCY + 30
—
ns
40
—
ns
100
—
ns
Continuous
Single Byte
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
73A
TB2B
74
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
75
TdoR
SDO Data Output Rise Time
76
TdoF
SDO Data Output Fall Time
77
TssH2doZ SS ↑ to SDO Output High-Impedance
78
TscR
Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40
PIC18FXX8
—
ns
100
—
ns
—
25
ns
45
ns
—
25
ns
10
50
ns
—
25
ns
45
ns
—
25
ns
—
50
ns
100
ns
—
ns
PIC18LFXX8
SCK Output Rise Time (Master mode) PIC18FXX8
PIC18LFXX8
79
TscF
80
TscH2doV, SDO Data Output Valid after SCK
TscL2doV Edge
83
TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
Note 1:
2:
Max Units Conditions
SCK Output Fall Time (Master mode)
PIC18FXX8
PIC18LFXX8
1.5 TCY + 40
(Note 1)
(Note 1)
(Note 2)
Requires the use of parameter #73A.
Only if parameter #71A and #72A are used.
© 2006 Microchip Technology Inc.
DS41159E-page 351
PIC18FXX8
FIGURE 27-16:
EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
MSb
SDO
LSb
Bit 6 - - - - - -1
77
75, 76
SDI
MSb In
Bit 6 - - - -1
LSb In
74
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-16: EXAMPLE SPI™ SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
71
TscH
71A
72
TscL
72A
Min
Max Units Conditions
TCY
—
ns
SCK Input High Time
(Slave mode)
Continuous
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
SCK Input Low Time
(Slave mode)
Continuous
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
(Note 1)
(Note 2)
73A
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40
—
ns
74
TscH2diL,
TscL2diL
Hold Time of SDI Data Input to SCK Edge
100
—
ns
75
TdoR
SDO Data Output Rise Time
—
25
ns
76
TdoF
SDO Data Output Fall Time
77
TssH2doZ SS ↑ to SDO Output High-Impedance
78
TscR
PIC18FXX8
PIC18LFXX8
SCK Output Rise Time
(Master mode)
79
TscF
80
TscH2doV, SDO Data Output Valid after SCK
TscL2doV Edge
82
TssL2doV SDO Data Output Valid after SS ↓
Edge
83
Note 1:
2:
45
ns
25
ns
10
50
ns
PIC18FXX8
—
25
ns
PIC18LFXX8
—
45
ns
—
25
ns
—
50
ns
PIC18LFXX8
—
100
ns
PIC18FXX8
—
50
ns
PIC18LFXX8
—
100
ns
1.5 TCY + 40
—
ns
SCK Output Fall Time (Master mode)
TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
—
—
PIC18FXX8
(Note 1)
Requires the use of parameter #73A.
Only if parameter #71A and #72A are used.
DS41159E-page 352
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-17:
I2C™ BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-17: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param
No.
Symbol
90
TSU:STA
91
92
93
THD:STA
TSU:STO
Characteristic
Max
Units
Conditions
ns
Only relevant for Repeated
Start condition
ns
After this period, the first
clock pulse is generated
Start Condition
100 kHz mode
4700
—
Setup Time
400 kHz mode
600
—
Start Condition
100 kHz mode
4000
—
Hold Time
400 kHz mode
600
—
Stop Condition
100 kHz mode
4700
—
Setup Time
400 kHz mode
600
—
100 kHz mode
4000
—
400 kHz mode
600
—
THD:STO Stop Condition
Hold Time
FIGURE 27-18:
Min
ns
ns
I2C™ BUS DATA TIMING
103
102
100
101
SCL
106
90
107
92
91
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 27-5 for load conditions.
© 2006 Microchip Technology Inc.
DS41159E-page 353
PIC18FXX8
TABLE 27-18: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param
No.
100
Symbol
THIGH
Characteristic
Clock High Time
Min
Max
Units
100 kHz mode
4.0
—
μs
PIC18FXX8 must operate
at a minimum of 1.5 MHz
400 kHz mode
0.6
—
μs
PIC18FXX8 must operate
at a minimum of 10 MHz
1.5 TCY
—
100 kHz mode
4.7
—
μs
PIC18FXX8 must operate
at a minimum of 1.5 MHz
400 kHz mode
1.3
—
μs
PIC18FXX8 must operate
at a minimum of 10 MHz
1.5 TCY
—
ns
—
1000
ns
20 + 0.1 CB
300
ns
SSP Module
101
TLOW
Clock Low Time
SSP module
102
TR
103
TF
TSU:STA
90
91
THD:STA
THD:DAT
106
107
TSU:DAT
TSU:STO
92
109
TAA
110
TBUF
D102
CB
Note 1:
2:
SDA and SCL Rise 100 kHz mode
Time
400 kHz mode
SDA and SCL Fall
Time
100 kHz mode
Start Condition
Setup Time
100 kHz mode
400 kHz mode
Start Condition
Hold Time
Data Input Hold
Time
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
μs
Data Input Setup
Time
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
Stop Condition
Setup Time
100 kHz mode
4.7
—
μs
400 kHz mode
0.6
—
μs
Output Valid from
Clock
100 kHz mode
—
3500
ns
400 kHz mode
—
—
ns
Bus Free Time
Conditions
300
ns
300
ns
CB is specified to be from
10 to 400 pF
4.7
—
μs
0.6
—
μs
Only relevant for Repeated
Start condition
100 kHz mode
4.0
—
μs
400 kHz mode
0.6
—
μs
400 kHz mode
—
CB is specified to be from
10 to 400 pF
20 + 0.1
CB
100 kHz mode
4.7
—
μs
400 kHz mode
1.3
—
μs
—
400
pF
Bus Capacitive Loading
After this period the first
clock pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement
TSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the
low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output
the next data bit to the SDA line.
Before the SCL line is released, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard
mode I2C bus specification).
DS41159E-page 354
© 2006 Microchip Technology Inc.
PIC18FXX8
MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
FIGURE 27-19:
SCL
93
91
90
92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-19: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS
Param
Symbol
No.
90
TSU:STA
Characteristic
After this period, the
first clock pulse is
generated
400 kHz mode
2(TOSC)(BRG + 1)
—
mode(1)
2(TOSC)(BRG + 1)
—
100 kHz mode
2(TOSC)(BRG + 1)
—
400 kHz mode
2(TOSC)(BRG + 1)
—
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
Stop Condition
100 kHz mode
2(TOSC)(BRG + 1)
—
Setup Time
400 kHz mode
THD:STO Stop Condition
2(TOSC)(BRG + 1)
—
mode(1)
2(TOSC)(BRG + 1)
—
100 kHz mode
2(TOSC)(BRG + 1)
—
400 kHz mode
2(TOSC)(BRG + 1)
—
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
2C™
Maximum pin capacitance = 10 pF for all I
FIGURE 27-20:
ns
Setup Time
Hold Time
Note 1:
Only relevant for
Repeated Start
condition
—
1 MHz
93
ns
2(TOSC)(BRG + 1)
Hold Time
92
Units
100 kHz mode
THD:STA Start Condition
TSU:STO
Max
Start Condition
1 MHz
91
Min
Conditions
ns
ns
pins.
MASTER SSP I2C™ BUS DATA TIMING
103
102
100
101
SCL
90
106
91
107
92
SDA
In
109
109
110
SDA
Out
Note: Refer to Figure 27-5 for load conditions.
© 2006 Microchip Technology Inc.
DS41159E-page 355
PIC18FXX8
TABLE 27-20: MASTER SSP I2C™ BUS DATA REQUIREMENTS
Param.
Symbol
No.
100
101
THIGH
TLOW
Characteristic
Min
Max
Units
Clock High Time 100 kHz mode
2(TOSC)(BRG + 1)
—
ms
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
Clock Low Time 100 kHz mode
2(TOSC)(BRG + 1)
—
ms
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
(1)
2(TOSC)(BRG + 1)
—
ms
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
300
ns
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
100
ns
100 kHz mode
2(TOSC)(BRG + 1)
—
ms
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
1 MHz mode
102
103
90
91
TR
TF
TSU:STA
THD:STA
SDA and SCL
Rise Time
SDA and SCL
Fall Time
Start Condition
Setup Time
Start Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
—
ms
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
0
—
ns
106
THD:DAT
Data Input
Hold Time
100 kHz mode
400 kHz mode
0
0.9
ms
107
TSU:DAT
Data Input
Setup Time
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
92
TSU:STO
Stop Condition
Setup Time
100 kHz mode
2(TOSC)(BRG + 1)
—
ms
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
100 kHz mode
—
3500
ns
400 kHz mode
—
1000
ns
(1)
1 MHz mode
—
—
ns
100 kHz mode
4.7
—
ms
400 kHz mode
1.3
—
ms
—
400
pF
109
110
D102
Note 1:
2:
TAA
TBUF
CB
Output Valid
from Clock
Bus Free Time
Bus Capacitive Loading
Conditions
CB is specified to be
from 10 to 400 pF
CB is specified to be
from 10 to 400 pF
Only relevant for
Repeated Start
condition
After this period, the
first clock pulse is
generated
(Note 2)
Time the bus must be
free before a new
transmission can start
2C™
pins.
Maximum pin capacitance = 10 pF for all I
A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the low period of the SCL
signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the
SDA line.
Before the SCL line is released, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode).
DS41159E-page 356
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-21:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-21: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
Units
—
50
ns
TckH2dtV SYNC XMIT (Master & Slave)
Clock High to Data-Out Valid
PIC18FXX8
PIC18LFXX8
—
150
ns
121
Tckrf
Clock Out Rise Time and Fall Time
(Master mode)
PIC18FXX8
—
25
ns
PIC18LFXX8
—
60
ns
122
Tdtrf
Data-Out Rise Time and Fall Time
PIC18FXX8
—
25
ns
PIC18LFXX8
—
60
ns
120
FIGURE 27-22:
Conditions
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-22: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
125
126
Symbol
TdtV2ckl
TckL2dtl
Characteristic
Min
Max
Units
SYNC RCV (Master & Slave)
Data-Hold before CK ↓ (DT hold time)
10
—
ns
Data-Hold after CK ↓ (DT hold time)
15
—
ns
© 2006 Microchip Technology Inc.
Conditions
DS41159E-page 357
PIC18FXX8
TABLE 27-23: A/D CONVERTER CHARACTERISTICS: PIC18FXX8 (INDUSTRIAL, EXTENDED)
PIC18LFXX8 (INDUSTRIAL)
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
bit
Conditions
VREF = VDD ≥ 3.0V
A01
NR
Resolution
—
—
10
A03
EIL
Integral Linearity Error
—
—