PIC24F04KA201 FAMILY
14/20-Pin General Purpose, 16-Bit Flash Microcontrollers
with XLP Technology
Power Management Modes:
Analog Features:
•
•
•
•
• 10-Bit, up to 9-Channel Analog-to-Digital Converter:
- 500 ksps conversion rate
- Conversion available during Sleep and Idle
• Dual Analog Comparators with Programmable Input/
Output Configuration
• Charge Time Measurement Unit (CTMU):
- Used for capacitance sensing
- Compatible with mTouch™ capacitive sensing
- Time measurement, down to 1 ns resolution
- Delay/pulse generation, down to 1 ns resolution
•
•
•
•
•
Run – CPU, Flash, SRAM and Peripherals On
Doze – CPU Clock Runs Slower than Peripherals
Idle – CPU Off, Flash, SRAM and Peripherals On
Sleep – CPU, Flash and Peripherals Off and SRAM
On
Deep Sleep – CPU, Flash, SRAM and
Most Peripherals Off
Run mode Currents Down to 8 A Typical
Idle mode Currents Down to 2 A Typical
Deep Sleep mode Currents Down to 20 nA Typical
Watchdog Timer 350 nA, 1.8V Typical
High-Performance CPU:
Special Microcontroller Features:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator with 4x PLL Option and
Multiple Divide Options
• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16-Bit x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
• Operating Voltage Range of 1.8V to 3.6V
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
• Flash Program Memory:
- Erase/write cycles: 10000 minimum
- 40 years data retention minimum
• Fail-Safe Clock Monitor
• System Frequency Range Declaration bits:
- Declaring the frequency range helps in optimizing the
current consumption.
• Flexible Watchdog Timer (WDT) with On-Chip,
Low-Power RC Oscillator for Reliable Operation
• In-Circuit Serial Programming™ (ICSP™)
• Programmable High/Low-Voltage Detect (HLVD)
• Brown-out Reset (BOR):
- Standard BOR with three programmable trip points;
can be disabled in Sleep
• Extreme Low-Power DSBOR for Deep Sleep,
LPBOR for all other modes
Peripheral Features:
PIC24F
Device
Pins
Program
Memory
(bytes)
SRAM
(bytes)
Timers
16-Bit
Input
Capture
Output
Compare/
PWM
UART/
IrDA®
SPI
I2C™
10-Bit A/D
(ch)
Comparators
CTMU (ch)
• Serial Communication modules:
- SPI, I2C™ and UART modules
• Three 16-Bit Timers/Counters with Programmable
Prescaler
• 16-Bit Capture Inputs
• 16-Bit Compare/PWM Output
• Configurable Open-Drain Outputs on Digital I/O Pins
• Up to Three External Interrupt Sources
04KA200
04KA201
14
20
4K
4K
512
512
3
3
1
1
1
1
1
1
1
1
1
1
7
9
2
2
7
9
2009-2014 Microchip Technology Inc.
DS30009937C-page 1
PIC24F04KA201 FAMILY
Pin Diagrams
14-Pin PDIP, TSSOP(1)
1
2
3
4
5
6
7
PIC24F04KA200
MCLR/VPP/RA5
PGC2/AN0/VREF+/CN2/RA0
PGD2/AN1/VREF-/CN3/RA1
OSCI/CLKI/AN4/C1INB/CN30/RA2
OSCO/CLKO/AN5/C1INA/CN29/RA3
PGD3/SOSCI/AN2/C2INB/HLVDIN/CN1/RB4
PGC3/SOSCO/AN3/C2INA/T1CK/CN0/RA4
14
13
12
11
10
9
8
VDD
VSS
REFO/U1RX/SS1/T2CK/T3CK/INT0/CTPLS/CN11/RB15
AN10/CVREF/U1TX/SDI1/OCFA/C1OUT/INT1/CTED2/CN12/RB14
OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6
SDA1/U1BCLK/U1RTS/SDO1/CN21/RB9
SCL1/U1CTS/SCK1/CN22/RB8
20-Pin PDIP, SSOP, SOIC(1)
Note 1:
1
2
3
4
5
6
7
8
9
10
PIC24F04KA201
MCLR/VPP/RA5
PGC2/AN0/VREF+/CN2/RA0
PGD2/AN1/VREF-/CN3/RA1
AN2/C2INB/CN4/RB0
AN3/C2INA/CN5/RB1
U1RX/CN6/RB2
OSCI/CLKI/AN4/C1INB/CN30/RA2
OSCO/CLKO/AN5/C1INA/CN29/RA3
PGD3/SOSCI/CN1/RB4
PGC3/SOSCO/T1CK/CN0/RA4
20
19
18
17
16
15
14
13
12
11
VDD
VSS
REFO/SS1/T2CK/T3CK/CN11/RB15
AN10/CVREF/SDI1/OCFA/C1OUT/INT1/CN12/RB14
AN11/SDO1/CTPLS/CN13/RB13
AN12/HLVDIN/SCK1/CTED2/CN14/RB12
OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6
SDA1/U1BCLK/U1RTS/CN21/RB9
SCL1/U1CTS/CN22/RB8
U1TX/INT0/CN23/RB7
All device pins have a maximum voltage of 3.6V and are not 5V tolerant.
DS30009937C-page 2
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
Pin Diagrams (Continued)
PGD2/AN1/VREF-/CN3/RA1
PGC2/AN0/VREF+/CN2/RA0
MCLR/VPP/RA5
VDD
VSS
20-Pin QFN(1,2)
20 19 18 17 16
AN2/C2INB/CN4/RB0
AN3/C2INA/CN5/RB1
15
1
14
2
U1RX/U1BCLK/CN6/RB2 3 PIC24F04KA201 13
OSCI/CLKI/AN4/C1INB/CN30/RA2 4
12
OSCO/CLKO/AN5/C1INA/CN29/RA3 5
11
REFO/SS1/T2CK/T3CK/CN11/RB15
AN10/CVREF/SDI1/OCFA/C1OUT/INT1/CN12/RB14
AN11/SDO1/CTPLS/CN13/RB13
AN12/HLVDIN/SCK1/CTED2/CN14/RB12
OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6
PGD3/SOSCI/CN1/RB4
PGC3/SOSCO/T1CK/CN0/RA4
U1TX/INT0/CN23/RB7
SCL1/U1CTS/CN22/RB8
SDA1/U1BCLK/U1RTS/CN21/RB9
6 7 8 9 10
Note 1:
2:
Connecting the bottom pad to Vss is recommended.
All device pins have a maximum voltage of 3.6V and are not 5V tolerant.
2009-2014 Microchip Technology Inc.
DS30009937C-page 3
PIC24F04KA201 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ........................................................................................................ 15
3.0 CPU ........................................................................................................................................................................................... 19
4.0 Memory Organization ................................................................................................................................................................. 25
5.0 Flash Program Memory .............................................................................................................................................................. 43
6.0 Resets ........................................................................................................................................................................................ 51
7.0 Interrupt Controller ..................................................................................................................................................................... 57
8.0 Oscillator Configuration .............................................................................................................................................................. 81
9.0 Power-Saving Features .............................................................................................................................................................. 91
10.0 I/O Ports ..................................................................................................................................................................................... 99
11.0 Timer1 ..................................................................................................................................................................................... 101
12.0 Timer2/3 ................................................................................................................................................................................... 103
13.0 Input Capture............................................................................................................................................................................ 109
14.0 Output Compare ....................................................................................................................................................................... 111
15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 117
16.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 125
17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 133
18.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 141
19.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 143
20.0 Comparator Module.................................................................................................................................................................. 153
21.0 Comparator Voltage Reference................................................................................................................................................ 157
22.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 159
23.0 Special Features ...................................................................................................................................................................... 163
24.0 Development Support............................................................................................................................................................... 173
25.0 Instruction Set Summary .......................................................................................................................................................... 177
26.0 Electrical Characteristics .......................................................................................................................................................... 185
27.0 Packaging Information.............................................................................................................................................................. 205
Appendix A: Revision History............................................................................................................................................................. 213
Index .................................................................................................................................................................................................. 215
The Microchip Web Site ..................................................................................................................................................................... 219
Customer Change Notification Service .............................................................................................................................................. 219
Customer Support .............................................................................................................................................................................. 219
Product Identification System............................................................................................................................................................. 221
DS30009937C-page 4
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2009-2014 Microchip Technology Inc.
DS30009937C-page 5
PIC24F04KA201 FAMILY
NOTES:
DS30009937C-page 6
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC24F04KA200
• PIC24F04KA201
The PIC24F04KA201 family introduces a new line of
extreme low-power Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and
enhanced computational performance. It also offers a
new migration option for those high-performance applications, which may be outgrowing their 8-bit platforms,
but do not require the numerical processing power of a
digital signal processor.
1.1
1.1.1
Core Features
16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® digital signal controllers. The PIC24F CPU core
offers a wide range of enhancements, such as:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• Linear addressing of up to 12 Mbytes (program
space) and 64 Kbytes (data)
• A 16-element working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32-bit by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as C
• Operational performance up to 16 MIPS
2009-2014 Microchip Technology Inc.
1.1.2
POWER-SAVING TECHNOLOGY
The PIC24F04KA200 and PIC24F04KA201 devices
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:
• On-the-Fly Clock Switching: The device clock
can be changed under software control to the
Timer1 source or the internal, low-power RC
oscillator during operation, allowing users to
incorporate power-saving ideas into their software
designs.
• Doze Mode Operation: When timing-sensitive
applications, such as serial communications,
require the uninterrupted operation of peripherals,
the CPU clock speed can be selectively reduced,
allowing incremental power savings without
missing a beat.
• Instruction-Based Power-Saving Modes: There
are three instruction-based power-saving modes:
- Idle Mode: The core is shut down while leaving
the peripherals active.
- Sleep Mode: The core and peripherals that
require the system clock are shut down, leaving
the peripherals that use their own clock, or the
clock from other devices, active.
- Deep Sleep Mode: The core, peripherals (except
DSWDT), Flash and SRAM are shut down.
1.1.3
OSCILLATOR OPTIONS AND
FEATURES
The PIC24F04KA201 family offers five different
oscillator options, allowing users a range of choices in
developing application hardware. These include:
• Two Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes offering the option of a
divide-by-2 clock output.
• Two fast internal oscillators (FRCs): One with a
nominal 8 MHz output and the other with nominal
500 kHz output. These outputs can also be
divided under software control to provide clock
speed as low as 31 kHz or 2 kHz.
• A Phase Locked Loop (PLL) frequency multiplier,
available to the External Oscillator modes and the
8 MHz FRC oscillator, which allows clock speeds
of up to 32 MHz.
• A separate internal RC oscillator (LPRC) with a
fixed 31 kHz output, which provides a low-power
option for timing-insensitive applications.
DS30009937C-page 7
PIC24F04KA201 FAMILY
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the
internal oscillator and enables the controller to switch to
the internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
1.3
1.1.4
1.
EASY MIGRATION
Regardless of the memory size, all the devices share
the same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also helps in migrating to the next larger
device. This is true when moving between devices with
the same pin count, or even jumping from 14-pin to
20-pin devices. The PIC24F16KA102 family is directly
compatible for migration to larger program and data
memory.
Devices in the PIC24F04KA201 family are available in
14-pin and 20-pin packages. The general block
diagram for all devices is displayed in Figure 1-1.
The devices are different from each other in two ways:
Number of ADC channels (9 channels on 20-pin
parts, 7 channels on 14-pin parts).
Available I/O pins and ports (12 pins on two
ports for 14-pin devices and 18 pins on two ports
for 20-pin devices).
2.
All other features for devices in this family are identical;
these are summarized in Table 1-1.
A list of the pin features available on the
PIC24F04KA201 family devices, sorted by function, is
provided in Table 1-2.
Note:
The PIC24F family is pin compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex.
1.2
Other Special Features
• Communications: The PIC24F04KA201 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There is an I2C™ module that
supports both the Master and Slave modes of
operation. It also comprises a UART with built-in
IrDA® encoders/decoders and an SPI module.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, and
faster sampling speed. The 16-deep result buffer
can be used either in Sleep to reduce power, or in
Active mode to improve throughput.
• Charge Time Measurement Unit (CTMU)
Interface: The PIC24F04KA201 family includes
the new CTMU interface module, which can be
used for capacitive touch sensing using
Microchip’s mTouch™ technology, proximity
sensing and also for precision time measurement
and pulse generation.
DS30009937C-page 8
Details on Individual Family
Members
1.4
Table 1-1 provides the pin location of
individual peripheral features and not how
they are multiplexed on the same pin. This
information is provided in the pinout
diagrams on pages 2 and 3 of the data
sheet. Multiplexed features are sorted by
the priority given to a feature, with the
highest priority peripheral being listed first.
Differences from PIC24F16KA102
Family
The PIC24F04KA201 family architecture is very similar to
that of the PIC24F16KA102 family. The PIC24F04KA201
family is a subset of the PIC24F16KA102 devices.
The PIC24F16KA102
additional features:
family
has
the
following
•
•
•
•
•
Larger Program Memory
Larger Data Memory
CRC Module
Debugging Capabilities through ICSP™
Additional I/O on 20-Pin Devices (up to
24 I/O pins)
• Data EEPROM memory
• Boot Segment and General Segments for
Program Code (with available code protection)
• One Additional UART (2 total)
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
Features
Operating Frequency
PIC24F04KA201
DEVICE FEATURES FOR THE PIC24F04KA201 FAMILY
PIC24F04KA200
TABLE 1-1:
DC – 32 MHz
Program Memory (bytes)
4K
Program Memory (instructions)
1408
Data Memory (bytes)
512
Interrupt Sources (soft vectors/NMI traps)
I/O Ports
Total I/O Pins
25 (21/4)
PORTA
PORTB
PORTA
PORTB
12
18
Timers: Total Number (16-bit)
32-Bit (from paired 16-bit timers)
3
1
Input Capture Channels
1
Output Compare/PWM Channels
Input Change Notification Interrupt
1
11
1
1
1
Serial Communications: UART
SPI (3-wire/4-wire)
I2C™
10-Bit Analog-to-Digital Module (input channels)
17
7
9
Analog Comparators
2
Resets (and delays)
POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode,
REPEAT Instruction, Hardware Traps, Configuration Word
Mismatch (PWRT, OST, PLL Lock)
Instruction Set
Packages
2009-2014 Microchip Technology Inc.
76 Base Instructions, Multiple Addressing Mode Variations
14-Pin PDIP/TSSOP
20-Pin PDIP/SSOP/SOIC/QFN
DS30009937C-page 9
PIC24F04KA201 FAMILY
FIGURE 1-1:
PIC24F04KA201 FAMILY GENERAL BLOCK DIAGRAM
Data Bus
Interrupt
Controller
16
16
16
8
Data Latch
PSV and Table
Data Access
Control Block
Data RAM
PCL
PCH
Program Counter
Repeat
Stack
Control
Control
Logic
Logic
23
Address
Latch
PORTA(1)
RA
16
23
16
Read AGU
Write AGU
Address Latch
Program Memory
PORTB(1)
RB
RB
Data Latch
16
EA MUX
Literal Data
Address Bus
24
Inst Latch
16
16
Inst Register
Instruction
Decode and
Control
Control Signals
16 x 16
W Reg Array
17x17
Multiplier
Power-up
Timer
Timing
OSCO/CLKO
OSCI/CLKI Generation
Divide
Support
Oscillator
Start-up Timer
FRC/LPRC
Oscillators
Power-on
Reset
16-Bit ALU
16
Watchdog
Timer
DSWDT
Precision
Band Gap
Reference
BOR
VDD, VSS
HLVD
REFO
Note 1:
IC1
MCLR
Timer1
Timer2/3
CTMU
10-Bit
ADC
Comparators
OC1/PWM
CN1-17(1)
SPI1
I2C1
UART1
All pins or features are not implemented on all device pinout configurations. See Table 1-2 for I/O port pin
descriptions.
DS30009937C-page 10
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
TABLE 1-2:
PIC24F04KA201 FAMILY PINOUT DESCRIPTIONS
Pin Number
14-Pin
PDIP/TSSOP/
SOIC
20-Pin
PDIP/SSOP/
SOIC
20-Pin
QFN
I/O
Input
Buffer
AN0
2
2
19
I
ANA
AN1
3
3
20
I
ANA
AN2
6
4
1
I
ANA
AN3
7
5
2
I
ANA
AN4
4
7
4
I
ANA
AN5
5
8
5
I
ANA
AN10
11
17
14
I
ANA
AN11
—
16
13
I
ANA
AN12
—
15
12
I
ANA
U1BCLK
9
13
10
O
—
C1INA
5
8
5
I
ANA
Comparator 1 Input A (Positive input)
C1INB
4
7
4
I
ANA
Comparator 1 Input B (Negative input option 1)
C1OUT
11
17
14
O
—
C2INA
7
5
2
I
ANA
Function
C2INB
6
4
1
I
ANA
C2OUT
10
14
11
O
—
CLKI
4
7
4
I
ANA
CLKO
5
8
5
O
—
CN0
7
10
7
I
ST
CN1
6
9
6
I
ST
CN2
2
2
19
I
ST
CN3
3
3
20
I
ST
CN4
—
4
1
I
ST
CN5
—
5
2
I
ST
Description
A/D Analog Inputs
UART1 IrDA® Baud Clock
Comparator 1 Output
Comparator 2 Input A (Positive input)
Comparator 2 Input B (Negative input option 1)
Comparator 2 Output
Main Clock Input Connection
System Clock Output
CN6
—
6
3
I
ST
CN8
10
14
11
I
ST
CN11
12
18
15
I
ST
CN12
11
17
14
I
ST
CN13
—
16
13
I
ST
CN14
—
15
12
I
ST
CN21
9
13
10
I
ST
CN22
8
12
9
I
ST
CN23
—
11
8
I
ST
CN29
5
8
5
I
ST
CN30
4
7
4
I
ST
CVREF
11
17
14
O
ANA
CTED1
10
14
11
I
ST
CTED2
11
15
12
I
ST
CTMU Trigger Edge Input 2
CTPLS
12
16
13
O
—
CTMU Pulse Output
IC1
10
14
11
I
ST
Input Capture 1 Input
INT0
12
11
8
I
ST
INT1
11
17
14
I
ST
INT2
10
14
11
I
ST
Legend:
Interrupt-on-Change Inputs
Comparator Voltage Reference Output
CTMU Trigger Edge Input 1
External Interrupt Inputs
ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer
2009-2014 Microchip Technology Inc.
DS30009937C-page 11
PIC24F04KA201 FAMILY
TABLE 1-2:
PIC24F04KA201 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
HLVDIN
14-Pin
PDIP/TSSOP/
SOIC
20-Pin
PDIP/SSOP/
SOIC
20-Pin
QFN
I/O
Input
Buffer
6
15
12
I
ANA
Description
HLVD Voltage Input
MCLR
1
1
18
I
ST
OC1
10
14
11
O
—
Output Compare/PWM Outputs
OCFA
11
17
14
I
—
Output Compare Fault A
OSCI
4
7
4
I
ANA
Main Oscillator Input Connection
OSCO
5
8
5
O
ANA
Main Oscillator Output Connection
PGC2
2
2
19
I/O
ST
In-Circuit Debugger and ICSP Programming Clock
PGD2
3
3
20
I/O
ST
In-Circuit Debugger and ICSP Programming Data
PGC3
7
10
7
I/O
ST
In-Circuit Debugger and ICSP Programming Clock
In-Circuit Debugger and ICSP Programming Data
PGD3
6
9
6
I/O
ST
RA0
2
2
19
I/O
ST
RA1
3
3
20
I/O
ST
RA2
4
7
4
I/O
ST
RA3
5
8
5
I/O
ST
RA4
7
10
7
I/O
ST
RA5
1
1
18
I/O
ST
RA6
10
14
11
I/O
ST
RB0
—
4
1
I/O
ST
RB1
—
5
2
I/O
ST
RB2
—
6
3
I/O
ST
RB4
6
9
6
I/O
ST
RB8
8
12
9
I/O
ST
RB9
9
13
10
I/O
ST
RB12
—
15
12
I/O
ST
RB13
—
16
13
I/O
ST
Master Clear (device Reset) Input
PORTA Digital I/O
PORTB Digital I/O
RB14
11
17
14
I/O
ST
RB15
12
18
15
I/O
ST
REFO
12
18
15
O
—
Reference Clock Output
SCK1
8
15
12
I/O
ST
SPI1 Serial Clock Input/Output
I2C1 Synchronous Serial Clock Input/Output
I2C1 Data Input/Output
SCL1
8
12
9
I/O
I2C
SDA1
9
13
10
I/O
I2C
SDI1
11
17
14
I
ST
SPI1 Serial Data Input
SDO1
9
16
13
O
—
SPI1 Serial Data Output
SOSCI
6
9
6
I
ANA
SOSCO
7
10
7
O
ANA
SS1
12
18
15
I/O
ST
Secondary Oscillator Input
Secondary Oscillator Output
Slave Select Input/Frame Select Output (SPI1)
T1CK
7
10
7
I
ST
Timer1 Clock
T2CK
12
18
15
I
ST
Timer2 Clock
T3CK
12
18
15
I
ST
Timer3 Clock
U1CTS
8
12
9
I
ST
UART1 Clear to Send Input
U1RTS
9
13
10
O
—
UART1 Request to Send Output
U1RX
12
6
3
I
ST
UART1 Receive
11
11
8
O
—
UART1 Transmit Output
U1TX
Legend:
ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer
DS30009937C-page 12
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
TABLE 1-2:
PIC24F04KA201 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
14-Pin
PDIP/TSSOP/
SOIC
20-Pin
PDIP/SSOP/
SOIC
20-Pin
QFN
I/O
Input
Buffer
VDD
14
20
17
P
—
Positive Supply for Peripheral Digital Logic and I/O
Pins
Programming Mode Entry Voltage
Function
Description
VPP
1
1
18
P
—
VREF-
3
3
20
I
ANA
A/D and Comparator Reference Voltage (low) Input
VREF+
2
2
19
I
ANA
A/D and Comparator Reference Voltage (high) Input
13
19
16
P
—
VSS
Legend:
Ground Reference for Logic and I/O Pin
ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer
2009-2014 Microchip Technology Inc.
DS30009937C-page 13
PIC24F04KA201 FAMILY
NOTES:
DS30009937C-page 14
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
MICROCONTROLLERS
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTIONS
C2(2)
• All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”)
• All AVDD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
• ENVREG/DISVREG and VCAP/VDDCORE pins
(PIC24F devices only)
(see Section 2.4 “Voltage Regulator Pins
(ENVREG/DISVREG and VCAP/VDDCORE)”)
These pins must also be connected if they are being
used in the end application:
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for analog modules is implemented
Note:
VSS
VDD
(1) (1)
(EN/DIS)VREG
MCLR
VCAP/VDDCORE
C1
C7
PIC24FXXXX
VSS
VDD
VDD
VSS
C3(2)
C6(2)
VSS
The following pins must always be connected:
R1
R2
VDD
Getting started with the PIC24F04KA201 family of
16-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.
VDD
AVSS
Basic Connection Requirements
AVDD
2.1
C4(2)
C5(2)
Key (all values are recommendations):
C1 through C6: 0.1 F, 20V ceramic
C7: 10 F, 6.3V or greater, tantalum or ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
Note 1:
2:
See Section 2.4 “Voltage Regulator Pins
(ENVREG/DISVREG and VCAP/VDDCORE)”
for an explanation of ENVREG/DISVREG pin
connections.
The example shown is for a PIC24F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
The minimum mandatory connections are shown in
Figure 2-1.
2009-2014 Microchip Technology Inc.
DS30009937C-page 15
PIC24F04KA201 FAMILY
2.2
2.2.1
Power Supply Pins
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2
2.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: device Reset, and device programming
and debugging. If programming and debugging are
not required in the end application, a direct
connection to VDD may be all that is required. The
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must be
considered. Device programmers and debuggers drive
the MCLR pin. Consequently, specific voltage levels
(VIH and VIL) and fast signal transitions must not be
adversely affected. Therefore, specific values of R1
and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated from
the MCLR pin during programming and debugging
operations by using a jumper (Figure 2-2). The jumper
is replaced for normal run-time operations.
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
VDD
R1
R2
JP
DS30009937C-page 16
MCLR
PIC24FXXXX
C1
Note 1:
R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2:
R2 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including microcontrollers to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
EXAMPLE OF MCLR PIN
CONNECTIONS
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
2.4
Voltage Regulator Pins
(ENVREG/DISVREG and
VCAP/VDDCORE)
Note:
2.5
This section applies only to PIC24F
devices with an on-chip voltage regulator.
The on-chip voltage regulator enable/disable pin
(ENVREG or DISVREG, depending on the device
family) must always be connected directly to either a
supply voltage or to ground. The particular connection
is determined by whether or not the regulator is to be
used:
• For ENVREG, tie to VDD to enable the regulator or
to ground to disable the regulator
• For DISVREG, tie to ground to enable the
regulator or to VDD to disable the regulator
When the regulator is enabled, a low-ESR ( CxINA Compare
CON = 1, CREF = 0, CCH = 11
Comparator CxINB > CxINA Compare
CON = 1, CREF = 0, CCH = 00
CXINB
CXINA
VIN-
COE
-
VBG/2
Cx
VIN+
CxOUT
Pin
Comparator CxINB > CVREF Compare
CON = 1, CREF = 1, CCH = 00
CXINB
CVREF
VINVIN+
DS30009937C-page 154
CxOUT
Pin
CXINA
VIN-
COE
Cx
VIN+
CxOUT
Pin
Comparator VBG > CVREF Compare
CON = 1, CREF = 1, CCH = 11
COE
-
VBG/2
Cx
CxOUT
Pin
CVREF
VINVIN+
COE
Cx
CxOUT
Pin
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
REGISTER 20-1:
CMxCON: COMPARATOR x CONTROL REGISTERS
R/W-0
CON
bit 15
R/W-0
COE
R/W-0
CPOL
R/W-0
CLPWR
U-0
—
U-0
—
R/W-0
CEVT
R-0
COUT
bit 8
R/W-0
EVPOL1
bit 7
R/W-0
EVPOL0
U-0
—
R/W-0
CREF
U-0
—
U-0
—
R/W-0
CCH1
R/W-0
CCH0
bit 0
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-10
bit 9
bit 8
bit 7-6
bit 5
bit 4
bit 3-2
bit 1-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
CON: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
CLPWR: Comparator Low-Power Mode Select bit
1 = Comparator operates in Low-Power mode
0 = Comparator does not operate in Low-Power mode
Unimplemented: Read as ‘0’
CEVT: Comparator Event bit
1 = Comparator event defined by EVPOL has occurred; subsequent triggers and interrupts are
disabled until the bit is cleared
0 = Comparator event has not occurred
COUT: Comparator Output bit
When CPOL = 0:
1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1:
1 = VIN+ < VIN0 = VIN+ > VINEVPOL: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt generated on transition of the comparator output:
If CPOL = 0 (non-inverted polarity):
High-to-low transition only.
If CPOL = 1 (inverted polarity):
Low-to-high transition only.
01 = Trigger/event/interrupt generated on transition of comparator output:
If CPOL = 0 (non-inverted polarity):
Low-to-high transition only.
If CPOL = 1 (inverted polarity):
High-to-low transition only.
00 = Trigger/event/interrupt generation is disabled
Unimplemented: Read as ‘0’
CREF: Comparator Reference Select bits (non-inverting input)
1 = Non-inverting input connects to internal CVREF voltage
0 = Non-inverting input connects to CxINA pin
Unimplemented: Read as ‘0’
CCH: Comparator Channel Select bits
11 = Inverting input of comparator connects to VBG/2
00 = Inverting input of comparator connects to CxINB pin
2009-2014 Microchip Technology Inc.
DS30009937C-page 155
PIC24F04KA201 FAMILY
REGISTER 20-2:
CMSTAT: COMPARATOR MODULE STATUS REGISTER
R/W-0
U-0
U-0
U-0
U-0
U-0
R-0, HSC
R-0, HSC
CMIDL
—
—
—
—
—
C2EVT
C1EVT
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R-0, HSC
R-0, HSC
—
—
—
—
—
—
C2OUT
C1OUT
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CMIDL: Comparator Stop in Idle Mode bit
1 = When device enters Idle mode, the module does not generate interrupts; it is still enabled
0 = Continue operation of all enabled comparators in Idle mode
bit 14-10
Unimplemented: Read as ‘0’
bit 9
C2EVT: Comparator 2 Event Status bit (read-only)
Shows the current event status of Comparator 2 (CM2CON).
bit 8
C1EVT: Comparator 1 Event Status bit (read-only)
Shows the current event status of Comparator 1 (CM1CON).
bit 7-2
Unimplemented: Read as ‘0’
bit 1
C2OUT: Comparator 2 Output Status bit (read-only)
Shows the current output of Comparator 2 (CM2CON).
bit 0
C1OUT: Comparator 1 Output Status bit (read-only)
Shows the current output of Comparator 1 (CM1CON).
DS30009937C-page 156
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
21.0
Note:
COMPARATOR VOLTAGE
REFERENCE
21.1
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information
on the Comparator Voltage Reference,
refer to the “PIC24F Family Reference
Manual”, Section 20. “Comparator
Voltage
Reference
Module”
(DS39709).
Configuring the Comparator
Voltage Reference
The comparator voltage reference module is controlled
through the CVRCON register (Register 21-1). The
comparator voltage reference provides two ranges of
output voltage, each with 16 distinct levels. The range
to be used is selected by the CVRR bit (CVRCON).
The primary difference between the ranges is the size
of the steps selected by the CVREF Selection bits
(CVR), with one range offering finer resolution.
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF-. The voltage source is selected by the CVRSS bit
(CVRCON).
The settling time of the comparator voltage reference
must be considered when changing the CVREF output.
FIGURE 21-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+
AVDD
CVRSS = 1
8R
CVRSS = 0
CVR
R
CVREN
R
R
16-to-1 MUX
R
16 Steps
CVREF
R
R
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
AVSS
2009-2014 Microchip Technology Inc.
DS30009937C-page 157
PIC24F04KA201 FAMILY
REGISTER 21-1:
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down
bit 6
CVROE: Comparator VREF Output Enable bit
1 = CVREF voltage level is output on CVREF pin
0 = CVREF voltage level is disconnected from CVREF pin
bit 5
CVRR: Comparator VREF Range Selection bit
1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size
0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size
bit 4
CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source CVRSRC = VREF+ – VREF0 = Comparator reference source CVRSRC = AVDD – AVSS
bit 3-0
CVR3:CVR0: Comparator VREF Value Selection 0 CVR 15 bits
When CVRR = 1 and CVRSS = 0:
CVREF = (CVR/24) * (CVRSRC)
When CVRR = 0 and CVRSS = 0:
CVREF = 1/4 (CVRSRC) + (CVR/32) * (CVRSRC)
When CVRR = 1 and CVRSS = 1:
CVREF = ((CVR/24) * (CVRSRC)) + VREFWhen CVRR = 0 and CVRSS = 1:
CVREF = (1/4 (CVRSRC) + (CVR/32) * (CVRSRC)) + VREF-
DS30009937C-page 158
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
22.0
Note:
CHARGE TIME
MEASUREMENT UNIT (CTMU)
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Charge Measurement Unit, refer to the
“PIC24F Family Reference Manual”,
Section 11. “Charge Time Measurement
Unit (CTMU)” (DS39724).
The Charge Time Measurement Unit (CTMU) is a
flexible analog module that provides charge measurement, accurate differential time measurement between
pulse sources and asynchronous pulse generation. Its
key features include:
•
•
•
•
•
•
Four edge input trigger sources
Polarity control for each edge source
Control of edge sequence
Control of response to edges
Time measurement resolution of one nanosecond
Accurate current source suitable for capacitive
measurement
Together with other on-chip analog modules, the CTMU
can be used to precisely measure time, measure
capacitance, measure relative changes in capacitance,
or generate output pulses that are independent of the
system clock. The CTMU module is ideal for interfacing
with capacitive-based touch sensors.
22.1
Measuring Capacitance
The CTMU module measures capacitance by
generating an output pulse with a width equal to the
time between edge events on two separate input
channels. The pulse edge events to both input
channels can be selected from four sources: two
internal peripheral modules (OC1 and Timer1) and two
external pins (CTEDG1 and CTEDG2). This pulse is
used with the module’s precision current source to
calculate capacitance according to the relationship:
dV
C = I ------dT
For capacitance measurements, the A/D Converter
samples an external capacitor (CAPP) on one of its
input channels after the CTMU output’s pulse. A
precision resistor (RPR) provides current source
calibration on a second A/D channel. After the pulse
ends, the converter determines the voltage on the
capacitor. The actual calculation of capacitance is
performed in software by the application.
Figure 22-1 displays the external connections used for
capacitance measurements, and how the CTMU and
A/D modules are related in this application. This
example also shows the edge events coming from
Timer1, but other configurations using external edge
sources are possible. A detailed discussion on
measuring capacitance and time with the CTMU
module is provided in the “PIC24F Family Reference
Manual”.
The CTMU is controlled through two registers,
CTMUCON and CTMUICON. CTMUCON enables the
module, and controls edge source selection, edge
source polarity selection, and edge sequencing. The
CTMUICON register selects the current range of
current source and trims the current.
FIGURE 22-1:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR
CAPACITANCE MEASUREMENT
PIC24F Device
Timer1
CTMU
EDG1
Current Source
EDG2
Output Pulse
ANx
A/D Converter
ANY
CAPP
2009-2014 Microchip Technology Inc.
RPR
DS30009937C-page 159
PIC24F04KA201 FAMILY
22.2
When the module is configured for pulse generation
delay by setting the TGEN bit (CTMUCON), the
internal current source is connected to the B input of
Comparator 2. A capacitor (CDELAY) is connected to
the Comparator 2 pin, C2INB, and the comparator
voltage reference, CVREF, is connected to C2INA.
CVREF is then configured for a specific trip point. The
module begins to charge CDELAY when an edge event
is detected. When CDELAY charges above the CVREF
trip point, a pulse is output on CTPLS. The length of the
pulse delay is determined by the value of CDELAY and
the CVREF trip point.
Measuring Time
Time measurements on the pulse width can be similarly
performed using the A/D module’s internal capacitor
(CAD) and a precision resistor for current calibration.
Figure 22-2 displays the external connections used for
time measurements, and how the CTMU and A/D
modules are related in this application. This example
also shows both edge events coming from the external
CTEDG pins, but other configurations using internal
edge sources are possible.
22.3
Pulse Generation and Delay
Figure 22-3 shows the external connections for pulse
generation, as well as the relationship of the different
analog modules required. While CTEDG1 is shown as
the input pulse source, other options are available. A
detailed discussion on pulse generation with the CTMU
module is provided in the “PIC24F Family Reference
Manual”.
The CTMU module can also generate an output pulse
with edges that are not synchronous with the device’s
system clock. More specifically, it can generate a pulse
with a programmable delay from an edge event input to
the module.
FIGURE 22-2:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME
MEASUREMENT
PIC24F Device
CTMU
CTEDG1
EDG1
CTEDG2
EDG2
Current Source
Output Pulse
A/D Converter
ANx
CAD
RPR
FIGURE 22-3:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE
DELAY GENERATION
PIC24F Device
CTEDG1
EDG1
CTMU
CTPLS
Current Source
Comparator
DS30009937C-page 160
C2INB
–
CDELAY
CVREF
C2
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
REGISTER 22-1:
CTMUCON: CTMU CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMUEN
—
CTMUSIDL
TGEN
EDGEN
EDGSEQEN
IDISSEN
CTTRIG
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EDG2POL
EDG2SEL1
EDG2SEL0
EDG1POL
EDG1SEL1
EDG1SEL0
EDG2STAT
EDG1STAT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
CTMUEN: CTMU Enable bit
1 = Module is enabled
0 = Module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
CTMUSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12
TGEN: Time Generation Enable bit
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 10
EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
bit 10
EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
bit 9
IDISSEN: Analog Current Source Control bit
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 8
CTTRIG: Trigger Control bit
1 = Trigger output is enabled
0 = Trigger output is disabled
bit 7
EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 programmed for a positive edge response
0 = Edge 2 programmed for a negative edge response
bit 6-5
EDG2SEL: Edge 2 Source Select bits
11 = CTED1 pin
10 = CTED2 pin
01 = OC1 module
00 = Timer1 module
bit 4
EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 programmed for a positive edge response
0 = Edge 1 programmed for a negative edge response
2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009937C-page 161
PIC24F04KA201 FAMILY
REGISTER 22-1:
CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
bit 3-2
EDG1SEL: Edge 1 Source Select bits
11 = CTED1 pin
10 = CTED2 pin
01 = OC1 module
00 = Timer1 module
bit 1
EDG2STAT: Edge 2 Status bit
1 = Edge 2 event has occurred
0 = Edge 2 event has not occurred
bit 0
EDG1STAT: Edge 1 Status bit
1 = Edge 1 event has occurred
0 = Edge 1 event has not occurred
REGISTER 22-2:
CTMUICON: CTMU CURRENT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
IRNG1
IRNG0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-10
ITRIM: Current Source Trim bits
011111 = Maximum positive change from nominal current
011110
.
.
.
000001 = Minimum positive change from nominal current
000000 = Nominal current output specified by IRNG
111111 = Minimum negative change from nominal current
.
.
.
100010
100001 = Maximum negative change from nominal current
bit 9-8
IRNG: Current Source Range Select bits
11 = 100 Base current
10 = 10 Base current
01 = Base current level (0.55 A nominal)
00 = Current source disabled
bit 7-0
Unimplemented: Read as ‘0’
DS30009937C-page 162
x = Bit is unknown
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
23.0
SPECIAL FEATURES
Note:
23.1
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Watchdog Timer, High-Level Device
Integration and Programming Diagnostics,
refer to the individual sections of the
“PIC24F Family Reference Manual”
provided below:
• Section 9. “Watchdog Timer (WDT)”
(DS39697)
• Section 36. “High-Level Integration
with Programmable High/Low-Voltage
Detect (HLVD)” (DS39725)
• Section 33. “Programming and
Diagnostics” (DS39716)
PIC24F04KA201 family devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
•
•
•
•
•
Flexible Configuration
Watchdog Timer (WDT)
Code Protection
In-Circuit Serial Programming™ (ICSP™)
In-Circuit Emulation
REGISTER 23-1:
Configuration Bits
The Configuration bits can be programmed (read as ‘0’),
or left unprogrammed (read as ‘1’), to select various
device configurations. These bits are mapped starting at
program memory location, F80000h. A complete list is
provided in Table 23-1. A detailed explanation of the
various bit functions is provided in Register 23-1 through
Register 23-7.
The address, F80000h, is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (800000h-FFFFFFh), which can only be
accessed using table reads and table writes.
TABLE 23-1:
CONFIGURATION REGISTERS
LOCATIONS
Configuration
Register
Address
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
FDS
F80004
F80006
F80008
F8000A
F8000C
F8000E
F80010
FGS: GENERAL SEGMENT CONFIGURATION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/C-1
R/C-1
—
—
—
—
—
—
GSS0
GWRP
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
GSS0: General Segment Code Flash Code Protection bit
1 = No protection
0 = Standard security enabled
bit 0
GWRP: General Segment Code Flash Write Protection bit
1 = General segment may be written
0 = General segment is write-protected
2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009937C-page 163
PIC24F04KA201 FAMILY
REGISTER 23-2:
FOSCSEL: OSCILLATOR SELECTION CONFIGURATION REGISTER
R/P-1
U-0
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
IESO
—
—
—
—
FNOSC2
FNOSC1
FNOSC0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IESO: Internal External Switchover bit
1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled)
0 = Internal External Switchover mode disabled (Two-Speed Start-up disabled)
bit 6-3
Unimplemented: Read as ‘0’
bit 2-0
FNOSC: Oscillator Selection bits
000 = Fast RC oscillator (FRC)
001 = Fast RC oscillator with divide-by-N with PLL module (FRCDIV+PLL)
010 = Primary oscillator (XT, HS, EC)
011 = Primary oscillator with PLL module (HS+PLL, EC+PLL)
100 = Secondary oscillator (SOSC)
101 = Low-Power RC oscillator (LPRC)
110 = 500 kHz Low-Power FRC oscillator with divide-by-N (LPFRCDIV)
111 = 8 MHz FRC oscillator with divide-by-N (FRCDIV)
DS30009937C-page 164
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
REGISTER 23-3:
FOSC: OSCILLATOR CONFIGURATION REGISTER
R/P-1
R/P-1
FCKSM1
FCKSM0
R/P-1
R/P-1
R/P-1
R/P-1
SOSCSEL POSCFREQ1 POSCFREQ0 OSCIOFNC
R/P-1
R/P-1
POSCMD1
POSCMD0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
FCKSM: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 5
SOSCSEL: Secondary Oscillator Select Bit
1 = Secondary oscillator configured for high-power operation
0 = Secondary oscillator configured for low-power operation
bit 4-3
POSCFREQ: Primary Oscillator Frequency Range Configuration bits
11 = Primary oscillator/external clock input frequency greater than 8 MHz
10 = Primary oscillator/external clock input frequency between 100 kHz and 8 MHz
01 = Primary oscillator/external clock input frequency less than 100 kHz
00 = Reserved; do not use
bit 2
OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for
the External Clock mode (EC) for the CLKO to be active (POSCMD = 11 or 00)
0 = CLKO output disabled
bit 1-0
POSCMD: Primary Oscillator Configuration bits
11 = Primary oscillator disabled
10 = HS Oscillator mode selected
01 = XT Oscillator mode selected
00 = External Clock mode selected
2009-2014 Microchip Technology Inc.
DS30009937C-page 165
PIC24F04KA201 FAMILY
REGISTER 23-4:
FWDT: WATCHDOG TIMER CONFIGURATION REGISTER
R/P-1
R/P-1
U-0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
FWDTEN
WINDIS
—
FWPSA
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
FWDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)
bit 6
WINDIS: Windowed Watchdog Timer Disable bit
1 = Standard WDT selected; windowed WDT disabled
0 = Windowed WDT enabled
bit 5
Unimplemented: Read as ‘0’
bit 4
FWPSA: WDT Prescaler bit
1 = WDT prescaler ratio of 1:128
0 = WDT prescaler ratio of 1:32
bit 3-0
WDTPS: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
DS30009937C-page 166
x = Bit is unknown
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
REGISTER 23-5:
R/P-1
MCLRE(1)
bit 7
FPOR: RESET CONFIGURATION REGISTER
R/P-1
BORV1(2)
Legend:
R = Readable bit
-n = Value at POR
R/P-1
BORV0(2)
U-0
—
P = Programmable bit
‘1’ = Bit is set
R/P-1
PWRTEN
U-0
—
R/P-1
BOREN1
R/P-1
BOREN0
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
MCLRE: MCLR Pin Enable bit(1)
1 = MCLR pin enabled; RA5 input pin disabled
0 = RA5 input pin enabled; MCLR disabled
BORV: Brown-out Reset Enable bits(2)
11 = Brown-out Reset set to lowest voltage
10 = Brown-out Reset
01 = Brown-out Reset set to highest voltage
00 = Low-power Brown-out Reset occurs around 2.0V
Unimplemented: Read as ‘0’
PWRTEN: Power-up Timer Enable bit
0 = PWRT disabled
1 = PWRT enabled
Unimplemented: Read as ‘0’
BOREN: Brown-out Reset Enable bits
11 = Brown-out Reset enabled in hardware; SBOREN bit disabled
10 = Brown-out Reset enabled only while device is active and disabled in Sleep; SBOREN bit disabled
01 = Brown-out Reset controlled with the SBOREN bit setting
00 = Brown-out Reset disabled in hardware; SBOREN bit disabled
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
2:
The MCLRE fuse can only be changed when using the VPP-Based ICSP™ mode entry. This prevents a
user from accidentally locking out the device from the low-voltage test entry.
Refer to the electrical specifications for BOR voltages.
REGISTER 23-6:
FICD: IN-CIRCUIT DEBUGGER CONFIGURATION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/P-1
R/P-1
—
—
—
—
—
—
FICD1
FICD0
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-2
bit 1-0
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
FICD ICD Pin Select bits
10 = PGC2/PGD2 are used for programming the device
01 = PGC3/PGD3 are used for programming the device
00, 11 = Reserved; do not use
2009-2014 Microchip Technology Inc.
DS30009937C-page 167
PIC24F04KA201 FAMILY
REGISTER 23-7:
FDS: DEEP SLEEP CONFIGURATION REGISTER
R/P-1
R/P-1
U-0
U-0
DSWDTEN
DSLPBOR
—
—
R/P-1
R/P-1
R/P-1
R/P-1
DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
DSWDTEN: Deep Sleep Watchdog Timer Enable bit
1 = DSWDT enabled
0 = DSWDT disabled
bit 6
DSLPBOR: Deep Sleep/Low-Power BOR Enable bit (does not affect operation in non Deep Sleep modes)
1 = Deep Sleep BOR enabled in Deep Sleep
0 = Deep Sleep BOR disabled in Deep Sleep
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
DSWDTPS: Deep Sleep Watchdog Timer Postscale Select bits
The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms.
1111 = 1:2,147,483,648 (25.7 days) nominal
1110 = 1:536,870,912 (6.4 days) nominal
1101 = 1:134,217,728 (38.5 hours) nominal
1100 = 1:33,554,432 (9.6 hours) nominal
1011 = 1:8,388,608 (2.4 hours) nominal
1010 = 1:2,097,152 (36 minutes) nominal
1001 = 1:524,288 (9 minutes) nominal
1000 = 1:131,072 (135 seconds) nominal
0111 = 1:32,768 (34 seconds) nominal
0110 = 1:8,192 (8.5 seconds) nominal
0101 = 1:2,048 (2.1 seconds) nominal
0100 = 1:512 (528 ms) nominal
0011 = 1:128 (132 ms) nominal
0010 = 1:32 (33 ms) nominal
0001 = 1:8 (8.3 ms) nominal
0000 = 1:2 (2.1 ms) nominal
DS30009937C-page 168
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
REGISTER 23-8:
DEVID: DEVICE ID REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 23
bit 16
R
R
R
R
R
R
R
R
FAMID7
FAMID6
FAMID5
FAMID4
FAMID3
FAMID2
FAMID1
FAMID0
bit 15
bit 8
R
R
R
R
R
R
R
R
DEV7
DEV6
DEV5
DEV4
DEV3
DEV2
DEV1
DEV0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-16
Unimplemented: Read as ‘0’
bit 15-8
FAMID: Device Family Identifier bits
00001011 = PIC24F04KA201 family
bit 7-0
DEV: Individual Device Identifier bits
00000000 = PIC24F04KA201
00000010 = PIC24F04KA200
REGISTER 23-9:
x = Bit is unknown
DEVREV: DEVICE REVISION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 23
bit 16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R
R
R
R
—
—
—
—
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-4
Unimplemented: Read as ‘0’
bit 3-0
REV: Minor Revision Identifier bits
2009-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009937C-page 169
PIC24F04KA201 FAMILY
23.2
Watchdog Timer (WDT)
For the PIC24F04KA201 family of devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT time-out period (TWDT) of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the Configuration bits,
WDTPS (FWDT), which allow the selection
of a total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler, time-out periods ranging from
1 ms to 131 seconds can be achieved.
The WDT Flag bit, WDTO (RCON), is not
automatically cleared following a WDT time-out. To
detect subsequent WDT events, the flag must be
cleared in software.
Note:
23.2.1
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
WINDOWED OPERATION
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
Configuration bit, WINDIS (FWDT), to ‘0’.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDT instruction during normal execution
23.2.2
CONTROL REGISTER
The WDT is enabled or disabled by the FWDTEN
Configuration bit. When the FWDTEN Configuration bit
is set, the WDT is always enabled.
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
FIGURE 23-1:
executed. The corresponding SLEEP or IDLE bits
(RCON) will need to be cleared in software after
the device wakes up.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for
critical code segments and disable the WDT during
non-critical segments for maximum power savings.
WDT BLOCK DIAGRAM
SWDTEN
FWDTEN
LPRC Control
FWPSA
WDTPS
Prescaler
(5-Bit/7-Bit)
LPRC Input
31 kHz
Wake from Sleep
WDT
Counter
Postscaler
1:1 to 1:32.768
WDT Overflow
Reset
1 ms/4 ms
All Device Resets
Transition to
New Clock Source
Exit Sleep or
Idle Mode
CLRWDT Instr.
PWRSAV Instr.
Sleep or Idle Mode
DS30009937C-page 170
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
23.3
Deep Sleep Watchdog Timer
(DSWDT)
In PIC24F04KA201 family devices, in addition to the
WDT module, a DSWDT module is present which runs
while the device is in Deep Sleep, if enabled. It is
driven by either the SOSC or LPRC oscillator. The
clock source is selected by the Configuration bit,
DSWCKSEL (FDS).
The DSWDT can be configured to generate a time-out at
2.1 ms to 25.7 days by selecting the respective
postscaler. The postscaler can be selected by the
Configuration bits, DSWDTPS (FDS). When
the DSWDT is enabled, the clock source is also enabled.
DSWDT is one of the sources that can wake-up the
device from Deep Sleep mode.
23.4
Write protection is controlled by the GWRP bit for the
general segment in the Configuration Word. When this
bit is programmed to ‘0’, internal write and erase
operations to program memory are blocked.
23.5
In-Circuit Serial Programming
PIC24F04KA201 family microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock (PGCx) and
data (PGDx) and three other lines for power, ground
and the programming voltage. This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or a custom firmware to be programmed.
Program Verification and
Code Protection
For all devices in the PIC24F04KA201 family, code
protection for the general segment is controlled by the
Configuration bit, GSS0. This bit inhibits external reads
and writes to the program memory space; this has no
direct effect in normal execution mode.
2009-2014 Microchip Technology Inc.
DS30009937C-page 171
PIC24F04KA201 FAMILY
NOTES:
DS30009937C-page 172
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
24.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
24.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2009-2014 Microchip Technology Inc.
DS30009937C-page 173
PIC24F04KA201 FAMILY
24.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16 and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other
relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler
to produce its object file. Notable features of the
assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
24.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
24.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
24.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS30009937C-page 174
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
24.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
24.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2009-2014 Microchip Technology Inc.
24.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
24.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the
target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
24.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
DS30009937C-page 175
PIC24F04KA201 FAMILY
24.11 Demonstration/Development
Boards, Evaluation Kits and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
24.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS30009937C-page 176
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
25.0
Note:
INSTRUCTION SET SUMMARY
This chapter is a brief summary of the
PIC24F instruction set architecture and is
not intended to be a comprehensive
reference source.
The PIC24F instruction set adds many enhancements
to the previous PIC® MCU instruction sets, while
maintaining an easy migration from previous PIC MCU
instruction sets. Most instructions are a single program
memory word. Only three instructions require two
program memory locations.
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction. The instruction set is
highly orthogonal and is grouped into four basic
categories:
•
•
•
•
Word or byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ‘Wb’
without any address modifier
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The control instructions may use some of the following
operands:
• A program memory address
• The mode of the table read and table write
instructions
Table 25-1 lists the general symbols used in describing
the instructions. The PIC24F instruction set summary
in Table 25-2 lists all the instructions, along with the
status flags affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value, ‘f’
• The destination, which could either be the file
register, ‘f’, or the W0 register, which is denoted
as ‘WREG’
Most bit-oriented instructions (including
rotate/shift instructions) have two operands:
The literal instructions that involve data movement may
use some of the following operands:
simple
All instructions are a single word, except for certain
double-word instructions, which were made
double-word instructions so that all of the required
information is available in these 48 bits. In the second
word, the 8 MSbs are ‘0’s. If this second word is
executed as an instruction (by itself), it will execute as
a NOP.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter (PC) is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles, with the additional instruction
cycle(s) executed as a NOP. Notable exceptions are the
BRA (unconditional/computed branch), indirect
CALL/GOTO, all table reads and writes, and
RETURN/RETFIE instructions, which are single-word
instructions but take two or three cycles.
Certain instructions that involve skipping over the
subsequent instruction require either two or three
cycles if the skip is performed, depending on whether
the instruction being skipped is a single-word or
two-word instruction. Moreover, double-word moves
require two cycles. The double-word instructions
execute in two instruction cycles.
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
register ‘Wb’)
2009-2014 Microchip Technology Inc.
DS30009937C-page 177
PIC24F04KA201 FAMILY
TABLE 25-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
Means literal defined by “text”
(text)
Means “content of text”
[text]
Means “the location addressed by text”
{ }
Optional field or operation
Register bit field
.b
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
bit4
4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
Absolute address, label or expression (resolved by the linker)
f
File register address {0000h...1FFFh}
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14
14-bit unsigned literal {0...16384}
lit16
16-bit unsigned literal {0...65535}
lit23
23-bit unsigned literal {0...8388608}; LSB must be ‘0’
None
Field does not require an entry, may be blank
PC
Program Counter
Slit10
10-bit signed literal {-512...511}
Slit16
16-bit signed literal {-32768...32767}
Slit6
6-bit signed literal {-16...16}
Wb
Base W register {W0..W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor working register pair (direct addressing)
Wn
One of 16 working registers {W0..W15}
Wnd
One of 16 destination working registers {W0..W15}
Wns
One of 16 source working registers {W0..W15}
WREG
W0 (working register used in file register instructions)
Ws
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
DS30009937C-page 178
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
TABLE 25-2:
INSTRUCTION SET OVERVIEW
Assembly
Mnemonic
ADD
ADDC
AND
ASR
BCLR
BRA
BSET
BSW
BTG
BTSC
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
ADD
f
f = f + WREG
1
1
C, DC, N, OV, Z
ADD
f,WREG
WREG = f + WREG
1
1
C, DC, N, OV, Z
ADD
#lit10,Wn
Wd = lit10 + Wd
1
1
C, DC, N, OV, Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
1
C, DC, N, OV, Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
1
C, DC, N, OV, Z
ADDC
f
f = f + WREG + (C)
1
1
C, DC, N, OV, Z
ADDC
f,WREG
WREG = f + WREG + (C)
1
1
C, DC, N, OV, Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
1
1
C, DC, N, OV, Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
1
C, DC, N, OV, Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
1
C, DC, N, OV, Z
AND
f
f = f .AND. WREG
1
1
N, Z
AND
f,WREG
WREG = f .AND. WREG
1
1
N, Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
1
1
N, Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
1
1
N, Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
1
1
N, Z
ASR
f
f = Arithmetic Right Shift f
1
1
C, N, OV, Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
1
1
C, N, OV, Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
1
1
C, N, OV, Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
1
1
N, Z
ASR
Wb,#lit5,Wnd
Wnd = Arithmetic Right Shift Wb by lit5
1
1
N, Z
BCLR
f,#bit4
Bit Clear f
1
1
None
BCLR
Ws,#bit4
Bit Clear Ws
1
1
None
BRA
C,Expr
Branch if Carry
1
1 (2)
None
BRA
GE,Expr
Branch if Greater than or Equal
1
1 (2)
None
BRA
GEU,Expr
Branch if Unsigned Greater than or Equal
1
1 (2)
None
BRA
GT,Expr
Branch if Greater than
1
1 (2)
None
BRA
GTU,Expr
Branch if Unsigned Greater than
1
1 (2)
None
BRA
LE,Expr
Branch if Less than or Equal
1
1 (2)
None
BRA
LEU,Expr
Branch if Unsigned Less than or Equal
1
1 (2)
None
BRA
LT,Expr
Branch if Less than
1
1 (2)
None
BRA
LTU,Expr
Branch if Unsigned Less than
1
1 (2)
None
BRA
N,Expr
Branch if Negative
1
1 (2)
None
BRA
NC,Expr
Branch if Not Carry
1
1 (2)
None
BRA
NN,Expr
Branch if Not Negative
1
1 (2)
None
BRA
NOV,Expr
Branch if Not Overflow
1
1 (2)
None
BRA
NZ,Expr
Branch if Not Zero
1
1 (2)
None
BRA
OV,Expr
Branch if Overflow
1
1 (2)
None
BRA
Expr
Branch Unconditionally
1
2
None
BRA
Z,Expr
Branch if Zero
1
1 (2)
None
BRA
Wn
Computed Branch
1
2
None
BSET
f,#bit4
Bit Set f
1
1
None
BSET
Ws,#bit4
Bit Set Ws
1
1
None
BSW.C
Ws,Wb
Write C bit to Ws
1
1
None
BSW.Z
Ws,Wb
Write Z bit to Ws
1
1
None
BTG
f,#bit4
Bit Toggle f
1
1
None
BTG
Ws,#bit4
Bit Toggle Ws
1
1
None
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
1
None
(2 or 3)
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
None
(2 or 3)
2009-2014 Microchip Technology Inc.
DS30009937C-page 179
PIC24F04KA201 FAMILY
TABLE 25-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
BTSS
BTST
BTSTS
Assembly Syntax
# of
Words
Description
# of
Cycles
Status Flags
Affected
BTSS
f,#bit4
Bit Test f, Skip if Set
1
1
None
(2 or 3)
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
None
(2 or 3)
BTST
f,#bit4
Bit Test f
1
1
Z
BTST.C
Ws,#bit4
Bit Test Ws to C
1
1
C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
1
1
Z
BTST.C
Ws,Wb
Bit Test Ws to C
1
1
C
Z
BTST.Z
Ws,Wb
Bit Test Ws to Z
1
1
BTSTS
f,#bit4
Bit Test then Set f
1
1
Z
BTSTS.C
Ws,#bit4
Bit Test Ws to C, then Set
1
1
C
BTSTS.Z
Ws,#bit4
Bit Test Ws to Z, then Set
1
1
Z
CALL
CALL
lit23
Call Subroutine
2
2
None
CALL
Wn
Call Indirect Subroutine
1
2
None
CLR
CLR
f
f = 0x0000
1
1
None
CLR
WREG
WREG = 0x0000
1
1
None
CLR
Ws
Ws = 0x0000
1
1
None
Clear Watchdog Timer
1
1
WDTO, Sleep
CLRWDT
CLRWDT
COM
COM
f
f=f
1
1
N, Z
COM
f,WREG
WREG = f
1
1
N, Z
COM
Ws,Wd
Wd = Ws
1
1
N, Z
CP
f
Compare f with WREG
1
1
C, DC, N, OV, Z
CP
Wb,#lit5
Compare Wb with lit5
1
1
C, DC, N, OV, Z
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
1
1
C, DC, N, OV, Z
CP0
CP0
f
Compare f with 0x0000
1
1
C, DC, N, OV, Z
CP0
Ws
Compare Ws with 0x0000
1
1
C, DC, N, OV, Z
CPB
CPB
f
Compare f with WREG, with Borrow
1
1
C, DC, N, OV, Z
CPB
Wb,#lit5
Compare Wb with lit5, with Borrow
1
1
C, DC, N, OV, Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1
1
C, DC, N, OV, Z
CPSEQ
CPSEQ
Wb,Wn
Compare Wb with Wn, Skip if =
1
1
None
(2 or 3)
CPSGT
CPSGT
Wb,Wn
Compare Wb with Wn, Skip if >
1
1
None
(2 or 3)
CPSLT
CPSLT
Wb,Wn
Compare Wb with Wn, Skip if <
1
1
None
(2 or 3)
CPSNE
CPSNE
Wb,Wn
Compare Wb with Wn, Skip if
1
1
None
(2 or 3)
DAW
DAW
Wn
Wn = Decimal Adjust Wn
1
1
DEC
DEC
f
f = f –1
1
1
C, DC, N, OV, Z
DEC
f,WREG
WREG = f –1
1
1
C, DC, N, OV, Z
CP
C
DEC
Ws,Wd
Wd = Ws – 1
1
1
C, DC, N, OV, Z
DEC2
f
f=f–2
1
1
C, DC, N, OV, Z
DEC2
f,WREG
WREG = f – 2
1
1
C, DC, N, OV, Z
DEC2
Ws,Wd
Wd = Ws – 2
1
1
C, DC, N, OV, Z
DISI
DISI
#lit14
Disable Interrupts for k Instruction Cycles
1
1
None
DIV
DIV.SW
Wm,Wn
Signed 16/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.UW
Wm,Wn
Unsigned 16/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer Divide
1
18
N, Z, C, OV
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
None
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
DEC2
DS30009937C-page 180
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
TABLE 25-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
GOTO
INC
INC2
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
GOTO
Expr
Go to Address
2
2
None
GOTO
Wn
Go to Indirect
1
2
None
INC
f
f=f+1
1
1
C, DC, N, OV, Z
INC
f,WREG
WREG = f + 1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
INC
Ws,Wd
Wd = Ws + 1
1
1
INC2
f
f=f+2
1
1
C, DC, N, OV, Z
INC2
f,WREG
WREG = f + 2
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
INC2
Ws,Wd
Wd = Ws + 2
1
1
IOR
f
f = f .IOR. WREG
1
1
N, Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N, Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N, Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N, Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N, Z
LNK
LNK
#lit14
Link Frame Pointer
1
1
None
LSR
LSR
f
f = Logical Right Shift f
1
1
C, N, OV, Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C, N, OV, Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C, N, OV, Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N, Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
1
1
N, Z
MOV
f,Wn
Move f to Wn
1
1
None
MOV
[Wns+Slit10],Wnd
Move [Wns+Slit10] to Wnd
1
1
None
MOV
f
Move f to f
1
1
N, Z
MOV
f,WREG
Move f to WREG
1
1
N, Z
MOV
#lit16,Wn
Move 16-bit Literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-bit Literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wns,[Wns+Slit10]
Move Wns to [Wns+Slit10]
1
1
None
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
N, Z
MOV.D
Wns,Wd
Move Double from W(ns):W(ns+1) to Wd
1
2
None
MOV.D
Ws,Wnd
Move Double from Ws to W(nd+1):W(nd)
1
2
None
MUL.SS
Wb,Ws,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5)
1
1
None
MUL
f
W3:W2 = f * WREG
1
1
None
NEG
f
f=f+1
1
1
C, DC, N, OV, Z
NEG
f,WREG
WREG = f + 1
1
1
C, DC, N, OV, Z
NEG
Ws,Wd
IOR
MOV
MUL
NEG
NOP
POP
Wd = Ws + 1
1
1
C, DC, N, OV, Z
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
POP
f
Pop f from Top-of-Stack (TOS)
1
1
None
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to W(nd):W(nd+1)
1
2
None
Pop Shadow Registers
1
1
All
POP.S
PUSH
PUSH
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns+1) to Top-of-Stack (TOS)
1
2
None
Push Shadow Registers
1
1
None
PUSH.S
2009-2014 Microchip Technology Inc.
DS30009937C-page 181
PIC24F04KA201 FAMILY
TABLE 25-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
PWRSAV
PWRSAV
#lit1
Go into Sleep or Idle mode
1
1
WDTO, Sleep
RCALL
RCALL
Expr
Relative Call
1
2
None
RCALL
Wn
Computed Call
1
2
None
REPEAT
REPEAT
#lit14
Repeat Next Instruction lit14 + 1 times
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 times
1
1
None
RESET
RESET
Software Device Reset
1
1
None
RETFIE
RETFIE
Return from Interrupt
1
3 (2)
None
RETLW
RETLW
Return with Literal in Wn
1
3 (2)
None
RETURN
RETURN
Return from Subroutine
1
3 (2)
None
RLC
RLC
f
f = Rotate Left through Carry f
1
1
C, N, Z
RLC
f,WREG
WREG = Rotate Left through Carry f
1
1
C, N, Z
C, N, Z
RLNC
RRC
RRNC
#lit10,Wn
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
RLNC
f
f = Rotate Left (No Carry) f
1
1
N, Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N, Z
N, Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
RRC
f
f = Rotate Right through Carry f
1
1
C, N, Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C, N, Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C, N, Z
RRNC
f
f = Rotate Right (No Carry) f
1
1
N, Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N, Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
1
1
N, Z
SE
SE
Ws,Wnd
Wnd = Sign-Extended Ws
1
1
C, N, Z
SETM
SETM
f
f = FFFFh
1
1
None
SETM
WREG
WREG = FFFFh
1
1
None
SETM
Ws
Ws = FFFFh
1
1
None
SL
f
f = Left Shift f
1
1
C, N, OV, Z
SL
f,WREG
WREG = Left Shift f
1
1
C, N, OV, Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C, N, OV, Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N, Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
1
1
N, Z
SUB
f
f = f – WREG
1
1
C, DC, N, OV, Z
SUB
f,WREG
WREG = f – WREG
1
1
C, DC, N, OV, Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C, DC, N, OV, Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C, DC, N, OV, Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C, DC, N, OV, Z
SUBB
f
f = f – WREG – (C)
1
1
C, DC, N, OV, Z
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C, DC, N, OV, Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C, DC, N, OV, Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C, DC, N, OV, Z
SL
SUB
SUBB
SUBR
SUBBR
SWAP
TBLRDH
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
C, DC, N, OV, Z
SUBR
f
f = WREG – f
1
1
C, DC, N, OV, Z
SUBR
f,WREG
WREG = WREG – f
1
1
C, DC, N, OV, Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C, DC, N, OV, Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
C, DC, N, OV, Z
SUBBR
f
f = WREG – f – (C)
1
1
C, DC, N, OV, Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C, DC, N, OV, Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C, DC, N, OV, Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
C, DC, N, OV, Z
SWAP.b
Wn
Wn = Nibble Swap Wn
1
1
None
SWAP
Wn
Wn = Byte Swap Wn
1
1
None
TBLRDH
Ws,Wd
Read Prog to Wd
1
2
None
DS30009937C-page 182
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
TABLE 25-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
TBLRDL
TBLRDL
Ws,Wd
Read Prog to Wd
1
2
None
TBLWTH
TBLWTH
Ws,Wd
Write Ws to Prog
1
2
None
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog
1
2
None
ULNK
ULNK
Unlink Frame Pointer
1
1
None
XOR
XOR
f
f = f .XOR. WREG
1
1
N, Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N, Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N, Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N, Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N, Z
ZE
Ws,Wnd
Wnd = Zero-Extend Ws
1
1
C, Z, N
ZE
2009-2014 Microchip Technology Inc.
DS30009937C-page 183
PIC24F04KA201 FAMILY
NOTES:
DS30009937C-page 184
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
26.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24F04KA201 family electrical characteristics. Additional information will be
provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24F04KA201 family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.0V
Voltage on any combined analog and digital pin with respect to VSS ............................................ -0.3V to (VDD + 0.3V)
Voltage on any digital only pin with respect to VSS ....................................................................... -0.3V to (VDD + 0.3V)
Voltage on MCLR/VPP pin with respect to VSS ......................................................................................... -0.3V to +9.0V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin (1) ..........................................................................................................................250 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (1) ..............................................................................................................200 mA
Note 1:
Maximum allowable current is a function of device maximum power dissipation (see Table 26-1).
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2009-2014 Microchip Technology Inc.
DS30009937C-page 185
PIC24F04KA201 FAMILY
26.1
DC Characteristics
Voltage (VDD)
FIGURE 26-1:
PIC24F04KA201 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
3.60V
3.60V
3.00V
3.00V
1.80V
8 MHz
32 MHz
Frequency
Note:
TABLE 26-1:
For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz *(VDD – 1.8) + 8 MHz.
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
PI/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 26-2:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 14-Pin PDIP
JA
62.4
—
°C/W
1
Package Thermal Resistance, 20-Pin PDIP
JA
60
—
°C/W
1
Package Thermal Resistance, 14-Pin SSOP
JA
108
—
°C/W
1
Package Thermal Resistance, 20-Pin SSOP
JA
71
—
°C/W
1
Package Thermal Resistance, 14-Pin SOIC
JA
75
—
°C/W
1
Package Thermal Resistance, 20-Pin SOIC
JA
80.2
—
°C/W
1
Package Thermal Resistance, 14-Pin QFN
JA
43
—
°C/W
1
Package Thermal Resistance, 20-Pin QFN
JA
32
—
°C/W
1
Note 1:
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
DS30009937C-page 186
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
TABLE 26-3:
DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max Units
DC10
VDD
Supply Voltage
1.8
—
3.6
V
DC12
VDR
RAM Data Retention
Voltage(2)
1.5
—
—
V
DC16
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
VSS
—
0.7
V
DC17
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05
—
—
Note 1:
2:
Conditions
V/ms 0-3.3V in 0.1s
0-2.5V in 60 ms
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered without losing RAM data.
TABLE 26-4:
HIGH/LOW–VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
Symbol
No.
DC18
VHLVD
Characteristic
Min
Typ
Max
Units
HLVD Voltage on VDD HLVDL = 0000
Transition
HLVDL = 0001
—
1.85
1.94
V
1.81
1.90
2.00
V
HLVDL = 0010
1.85
1.95
2.05
V
HLVDL = 0011
1.90
2.00
2.10
V
HLVDL = 0100
1.95
2.05
2.15
V
HLVDL = 0101
2.06
2.17
2.28
V
HLVDL = 0110
2.12
2.23
2.34
V
HLVDL = 0111
2.24
2.36
2.48
V
HLVDL = 1000
2.31
2.43
2.55
V
HLVDL = 1001
2.47
2.60
2.73
V
HLVDL = 1010
2.64
2.78
2.92
V
HLVDL = 1011
2.74
2.88
3.02
V
HLVDL = 1100
2.85
3.00
3.15
V
HLVDL = 1101
2.96
3.12
3.28
V
HLVDL = 1110
3.22
3.39
3.56
V
2009-2014 Microchip Technology Inc.
Conditions
DS30009937C-page 187
PIC24F04KA201 FAMILY
TABLE 26-5:
BOR TRIP POINTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
Sym
No.
DC19
Characteristic
Min
Typ
BOR Voltage on VDD Transition BOR = 00
1.55
2
2.00
V
BOR = 01
2.92
3
3.25
V
BOR = 10
2.63
2.7
2.92
V
BOR = 11
1.75
1.78 2.01
V
TABLE 26-6:
IDD Current
DC20
DS20a
DC20b
DC20c
DC20d
DC20e
DC20f
DC20g
DC22
DC22a
DC22b
DC22c
DC22d
DC22e
DC22f
DC22g
DC23
DC23a
DC23b
DC23c
DC27
DC27a
DC27b
DC27c
DC27d
DC27e
DC27f
DC27g
Note 1:
2:
Conditions
Valid for LPBOR and DSBOR
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter No.
Max Units
Typical(1)
195
365
363
695
11
Max
330
330
330
330
590
590
645
720
600
600
600
600
1100
1100
1100
1100
18
18
18
18
3.40
Units
A
A
A
A
mA
Conditions
-40°C
+25°C
+60°C
+85°C
-40°C
+25°C
+60°C
+85°C
-40°C
+25°C
+60°C
+85°C
-40°C
+25°C
+60°C
+85°C
-40°C
+25°C
+60°C
+85°C
-40°C
1.8V
0.5 MIPS,
FOSC = 1 MHz
3.3V
1.8V
1 MIPS,
FOSC = 2 MHz
3.3V
3.3V
16 MIPS,
FOSC = 32 MHz
3.40
+25°C
mA
2.5V
3.40
+60°C
3.40
+85°C
FRC (4 MIPS),
FOSC = 8 MHz
4.60
-40°C
4.60
+25°C
3.05
mA
3.3V
4.60
+60°C
4.60
+85°C
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
Operating Parameters:
• EC mode with clock input driven with a square wave rail-to-rail
• I/O configured as outputs driven low
• MCLR – VDD
• WDT FSCM disabled
• SRAM, program and data memory active
• All PMD bits set except for modules being measured
2.25
DS30009937C-page 188
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
TABLE 26-6:
DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter No.
IDD Current
DC31
DC31a
DC31b
DC31c
DC31d
DC31e
DC31f
DC31g
Note 1:
2:
Typical(1)
8
15
Max
28
28
28
28
55
55
55
55
Units
A
A
Conditions
-40°C
+25°C
+60°C
1.8V
+85°C
-40°C
+25°C
+60°C
+85°C
3.3V
LPRC (31 kHz)
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
Operating Parameters:
• EC mode with clock input driven with a square wave rail-to-rail
• I/O configured as outputs driven low
• MCLR – VDD
• WDT FSCM disabled
• SRAM, program and data memory active
• All PMD bits set except for modules being measured
TABLE 26-7:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param No.
Typical(1)
Max
Units
Conditions
Set(2)
Idle Current (IIDLE): Core Off, Clock On Base Current, PMD Bits are
DC40
100
-40°C
DC40a
100
+25°C
48
A
1.8V
DC40b
100
+60°C
DC40c
100
+85°C
0.5 MIPS,
FOSC = 1 MHz
DC40d
215
-40°C
DC40e
215
+25°C
106
A
3.3V
DC40f
215
+60°C
DC40g
215
+85°C
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: Operating Parameters:
• Core off
• EC mode with clock input driven with a square wave rail-to-rail
• I/O configured as outputs driven low
• MCLR – VDD
• WDT FSCM disabled
• SRAM, program and data memory active
• All PMD bits set except for modules being measured
2009-2014 Microchip Technology Inc.
DS30009937C-page 189
PIC24F04KA201 FAMILY
TABLE 26-7:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param No.
Typical(1)
Max
Units
Conditions
(2)
Idle Current (IIDLE): Core Off, Clock On Base Current, PMD Bits are Set
DC42
200
-40°C
DC42a
200
+25°C
94
A
1.8V
DC42b
200
+60°C
DC42c
200
+85°C
1 MIPS,
FOSC = 2 MHz
DC42d
395
-40°C
DC42e
395
+25°C
160
A
3.3V
DC42f
395
+60°C
DC42g
395
+85°C
DC43
6.0
-40°C
DC43a
6.0
+25°C
16 MIPS,
3.1
mA
3.3V
FOSC = 32 MHz
DC43b
6.0
+60°C
DC43c
6.0
+85°C
DC44
0.74
-40°C
DC44a
0.74
+25°C
0.56
mA
1.8V
DC44b
0.74
+60°C
DC44c
0.74
+85°C
FRC (4 MIPS),
FOSC = 8 MHz
DC44d
1.50
-40°C
DC44e
1.50
+25°C
0.95
mA
3.3V
DC44f
1.50
+60°C
DC44g
1.50
+85°C
DC50
18
-40°C
DC50a
18
+25°C
2
A
1.8V
DC50b
18
+60°C
DC50c
18
+85°C
LPRC (31 kHz)
DC50d
40
-40°C
DC50e
40
+25°C
4
A
3.3V
DC50f
40
+60°C
DC50g
40
+85°C
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: Operating Parameters:
• Core off
• EC mode with clock input driven with a square wave rail-to-rail
• I/O configured as outputs driven low
• MCLR – VDD
• WDT FSCM disabled
• SRAM, program and data memory active
• All PMD bits set except for modules being measured
DS30009937C-page 190
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
TABLE 26-8:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2)
DC60
0.200
-40°C
DC60a
0.200
+25°C
DC60b
0.025
0.870
A
+60°C
DC60c
1.350
+85°C
DC60d
0.540
-40°C
DC60e
DC60f
0.105
0.540
1.680
A
+25°C
+60°C
DC60g
2.450
DC70
0.150
-40°C
DC70a
0.150
+25°C
DC70b
0.020
0.430
A
+60°C
0.630
+85°C
DC70d
0.300
-40°C
DC70f
0.035
0.300
0.700
A
+25°C
+60°C
DC70g
0.980
DC61
0.65
-40°C
DC61a
0.65
+25°C
DC61b
0.55
0.65
A
+60°C
0.65
+85°C
DC61d
0.95
-40°C
DC61f
DC61g
Note 1:
2:
3:
4:
5:
0.87
0.95
0.95
0.95
3.3V
1.8V
Base Deep Sleep Current
3.3V
+85°C
DC61c
DC61e
Base Power-Down Current
(Sleep)(3)
+85°C
DC70c
DC70e
1.8V
A
+25°C
+60°C
1.8V
Watchdog Timer Current: WDT(3,4)
3.3V
+85°C
Data in the Typical column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled
high. WDT, etc., are all switched off.
The current is the additional current consumed when the module is enabled. This current should be added to
the base IPD current.
Current applies to Sleep only.
Current applies to Deep Sleep only.
2009-2014 Microchip Technology Inc.
DS30009937C-page 191
PIC24F04KA201 FAMILY
TABLE 26-8:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2)
DC62
0.650
-40°C
DC62a
0.650
+25°C
DC62b
0.450
0.650
A
+60°C
DC62c
0.650
+85°C
DC62d
0.980
-40°C
DC62e
DC62f
0.730
0.980
0.980
A
+25°C
+60°C
DC62g
0.980
DC64
7.10
-40°C
DC64a
7.10
+25°C
DC64b
5.5
7.80
A
+60°C
8.30
+85°C
DC64d
7.10
-40°C
DC64f
6.2
7.10
7.80
A
+25°C
+60°C
DC64g
8.30
DC63
6.60
-40°C
DC63a
6.60
+25°C
DC63b
4.5
DC63c
Note 1:
2:
3:
4:
5:
6.60
6.60
Timer1 w/32 kHz Crystal: T132
(SOSC – LP)(3)
3.3V
+85°C
DC64c
DC64e
1.8V
1.8V
HLVD(3,4)
3.3V
+85°C
A
+60°C
3.3V
BOR(3,4)
+85°C
Data in the Typical column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled
high. WDT, etc., are all switched off.
The current is the additional current consumed when the module is enabled. This current should be added to
the base IPD current.
Current applies to Sleep only.
Current applies to Deep Sleep only.
DS30009937C-page 192
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
TABLE 26-8:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2)
DC70
0.200
-40°C
DC70a
0.200
+25°C
DC70b
0.045
0.200
A
+60°C
DC70c
0.200
+85°C
DC70d
0.200
-40°C
DC70e
DC70f
0.095
0.200
0.200
A
+25°C
+60°C
DC70g
0.200
DC71
0.55
-40°C
DC71a
0.55
+25°C
DC71b
0.35
0.55
A
+60°C
0.55
+85°C
DC71d
0.75
-40°C
DC71f
0.55
0.75
0.75
A
+25°C
+60°C
DC71g
0.75
DC72
0.200
-40°C
DC72a
0.200
+25°C
DC72b
0.005
0.200
A
+60°C
0.200
+85°C
DC72d
0.200
-40°C
DC72f
DC72g
Note 1:
2:
3:
4:
5:
0.010
0.200
0.200
0.200
3.3V
1.8V
Deep Sleep Watchdog Timer:
DSWDT (SOSC – LP)(5)
3.3V
+85°C
DC72c
DC72e
LPBOR(3,4)
+85°C
DC71c
DC71e
1.8V
A
+25°C
+60°C
1.8V
Deep Sleep BOR: DSBOR(3,5)
3.3V
+85°C
Data in the Typical column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled
high. WDT, etc., are all switched off.
The current is the additional current consumed when the module is enabled. This current should be added to
the base IPD current.
Current applies to Sleep only.
Current applies to Deep Sleep only.
2009-2014 Microchip Technology Inc.
DS30009937C-page 193
PIC24F04KA201 FAMILY
TABLE 26-9:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Input Low Voltage(4)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
Min
Typ(1)
Max
Units
Conditions
—
—
—
—
I/O Pins
VSS
—
0.2 VDD
V
DI15
MCLR
VSS
—
0.2 VDD
V
DI16
OSCI (XT mode)
VSS
—
0.2 VDD
V
DI17
OSCI (HS mode)
VSS
—
0.2 VDD
V
DI18
I/O Pins with I2C™ Buffer
VSS
—
0.3 VDD
V
SMBus disabled
I/O Pins with SMBus Buffer
VSS
—
0.8
V
SMBus enabled
—
—
—
—
I/O Pins:
with Analog Functions
Digital Only
0.8 VDD
0.8 VDD
—
—
VDD
VDD
V
V
DI25
MCLR
0.8 VDD
—
VDD
V
DI26
OSCI (XT mode)
0.7 VDD
—
VDD
V
DI27
OSCI (HS mode)
0.7 VDD
—
VDD
V
DI28
I/O Pins with I2C Buffer:
with Analog Functions
Digital Only
0.7 VDD
0.7 VDD
—
—
VDD
VDD
V
V
2.1
—
VDD
V
2.5V VPIN VDD
50
250
500
A
VDD = 3.3V, VPIN = VSS
VIL
DI10
DI19
VIH
DI20
DI29
Input High Voltage(4)
I/O Pins with SMBus
DI30
ICNPU CNx Pull-up Current
IIL
Input Leakage
Current(2,3)
DI50
I/O Ports
—
0.050
±0.100
A
VSS VPIN VDD,
Pin at high-impedance
DI51
VREF+, VREF-, AN0, AN1
—
0.300
±0.500
A
VSS VPIN VDD,
Pin at high-impedance
DI55
MCLR
—
—
±5.0
A
VSS VPIN VDD
DI56
OSCI
—
—
±5.0
A
VSS VPIN VDD,
XT and HS modes
Note 1:
2:
3:
4:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Refer to Table 1-2 for I/O pin buffer types.
DS30009937C-page 194
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
TABLE 26-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Param
No.
Sym
VOL
Characteristic
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
Min
Typ(1)
Max
Units
—
—
0.4
V
—
—
0.4
V
IOL = 3.5 mA, VDD = 2.0V
—
—
0.4
V
IOL = 8.0 mA, VDD = 3.6V
—
—
0.4
V
IOL = 4.5 mA, VDD = 1.8V
Output Low Voltage
DO10
All I/O Pins
DO16
OSC2/CLKO
IOL = 6.5 mA, VDD = 3.6V
Output High Voltage
—
—
—
—
DO20
All I/O Pins
3
—
—
V
DO26
OSC2/CLKO
VOH
Note 1:
Conditions
—
IOH = -3.0 mA, VDD = 3.6V
1.8
—
—
V
IOH = -1.0 mA, VDD = 2.0V
3
—
—
V
IOH = -2.5 mA, VDD = 3.6V
1.8
—
—
V
IOH = -1.0 mA, VDD = 2.0V
Data in “Typ” column is at +25°C unless otherwise stated. Parameters are for design guidance only and are not
tested.
TABLE 26-11: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
Min
Typ(1)
10,000(2)
VMIN
2.2
Max
Units
—
—
E/W
—
3.6
V
—
3.6
V
Conditions
Program Flash Memory
D130
EP
Cell Endurance
D131
VPR
VDD for Read
D132
VPEW
Supply Voltage for
Self-Timed Writes
D133A
TIW
Self-Timed Write Cycle Time
D134
TRETD Characteristic Retention
D135
IDDP
Note 1:
2:
Supply Current During
Programming
—
2
—
ms
40
—
—
Year
—
10
—
mA
VMIN = Minimum operating voltage
Provided no other specifications are
violated
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
Self-write and block erase.
2009-2014 Microchip Technology Inc.
DS30009937C-page 195
PIC24F04KA201 FAMILY
TABLE 26-12: COMPARATOR DC SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
D300
VIOFF
Input Offset Voltage*
—
20
40
mV
D301
VICM
Input Common-Mode Voltage*
0
—
VDD
V
CMRR
Common-Mode Rejection Ratio*
55
—
—
dB
D302
Comments
* Parameters are characterized but not tested.
TABLE 26-13: COMPARATOR VOLTAGE REFERENCE DC SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
VDD/24
—
VDD/32
LSb
VRD310 CVRES
Resolution
VRD311 CVRAA
Absolute Accuracy
—
—
AVDD – 1.5
LSb
VRD312 CVRUR
Unit Resistor Value (R)
—
2k
—
Comments
TABLE 26-14: CTMU CURRENT SOURCE SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param
Sym
No.
Min
Typ(1)
Max
Units
IOUT1 CTMU Current Source,
Base Range
—
550
—
nA
CTMUICON = 01
IOUT2 CTMU Current Source,
10x Range
—
5.5
—
A
CTMUICON = 10
IOUT3 CTMU Current Source,
100x Range
—
55
—
A
CTMUICON = 11
Note 1:
Characteristic
Conditions
Nominal value at center point of current trim range (CTMUICON = 000000).
TABLE 26-15: COMPARATOR TIMINGS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
300
TRESP
Response Time*(1)
—
150
400
ns
301
TMC2OV
Comparator Mode Change to
Output Valid*
—
—
10
s
*
Note 1:
Comments
Parameters are characterized but not tested.
Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 26-16: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS
Param
No.
VR310
Note 1:
Symbol
TSET
Characteristic
Settling Time(1)
Min
Typ
Max
Units
—
—
10
s
Comments
Settling time measured while CVRR = 1 and CVR bits transition from ‘0000’ to ‘1111’.
DS30009937C-page 196
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
26.2
AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24F04KA201 family AC characteristics and timing parameters.
TABLE 26-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Operating voltage VDD range as described in Section 26.1 “DC Characteristics”.
AC CHARACTERISTICS
FIGURE 26-2:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSCO
Load Condition 2 – for OSCO
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSCO
15 pF for OSCO output
VSS
TABLE 26-18: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
DO50
COSC2
OSCO/CLKO Pin
—
—
15
pF
In XT and HS modes when
external clock is used to drive
OSCI
DO56
CIO
All I/O Pins and OSCO
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C™ mode
Note 1:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2009-2014 Microchip Technology Inc.
DS30009937C-page 197
PIC24F04KA201 FAMILY
FIGURE 26-3:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OS30
OS30
Q1
Q2
Q3
OSCI
OS20
OS31
OS31
OS25
CLKO
OS40
OS41
TABLE 26-19: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 1.8 to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
Sym
No.
OS10
Characteristic
FOSC External CLKI Frequency
(External clocks allowed
only in EC mode)
Oscillator Frequency
Min
Typ(1)
Max
Units
DC
4
—
—
32
8
MHz
MHz
EC
ECPLL
0.2
4
4
31
—
—
—
—
4
25
8
33
MHz
MHz
MHz
kHz
XT
HS
HSPLL
SOSC
—
—
—
—
62.5
—
DC
ns
Conditions
OS20
TOSC TOSC = 1/FOSC
OS25
TCY
OS30
TosL, External Clock in (OSCI)
TosH High or Low Time
0.45 x TOSC
—
—
ns
EC
OS31
TosR, External Clock in (OSCI)
TosF Rise or Fall Time
—
—
20
ns
EC
OS40
TckR
—
6
10
ns
—
6
10
ns
OS41
TckF
Note 1:
2:
3:
Instruction Cycle Time(2)
CLKO Rise Time(3)
CLKO Fall
Time(3)
See Parameter OS10 for FOSC
value
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an
external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time
limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for
the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
DS30009937C-page 198
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
TABLE 26-20: PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 3.6V)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Min
Typ(2)
Max
Units
FPLLI
PLL Input Frequency Range
4
—
8
MHz
PLL Output Frequency Range
Sym
OS50
OS51
FSYS
16
—
32
MHz
OS52
TLOCK PLL Start-up Time
(Lock Time)
—
—
2
ms
OS53
DCLK
-2
1
2
%
Note 1:
2:
CLKO Stability (Jitter)
Conditions
ECPLL, HSPLL modes
Measured over 100 ms period
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 26-21: AC CHARACTERISTICS: INTERNAL RC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
Min
Typ
Max
Units
Conditions
-2
—
2
%
+25°C
-5
—
5
%
-40°C TA +85°C
Internal FRC Accuracy @ 8 MHz(1)
F20
FRC
Note 1:
3.0V VDD 3.6V
Frequency calibrated at +25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.
TABLE 26-22: AC CHARACTERISTICS: INTERNAL RC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min
Typ
Max
Units
Conditions
-15
—
15
%
+25°C
-15
—
15
%
-40°C TA +85°C
LPRC @ 31 kHz(1)
F21
Note 1:
3.0V VDD 3.6V
Change of LPRC frequency as VDD changes.
2009-2014 Microchip Technology Inc.
DS30009937C-page 199
PIC24F04KA201 FAMILY
FIGURE 26-4:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note:
Refer to Figure 26-2 for load conditions.
TABLE 26-23: CLKO AND I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Sym
Characteristic
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
Min
Typ(1)
Max
Units
—
10
25
ns
DO31
TIOR
DO32
TIOF
Port Output Fall Time
—
10
25
ns
DI35
TINP
INTx pin High or Low
Time (output)
20
—
—
ns
DI40
TRBP
CNx High or Low Time
(input)
2
—
—
TCY
Note 1:
Port Output Rise Time
Conditions
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
DS30009937C-page 200
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
TABLE 26-24: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of:
VDD – 0.3
or 1.8
—
Lesser of:
VDD + 0.3
or 3.6
V
AD02
AVSS
Module VSS Supply
VSS – 0.3
—
VSS + 0.3
V
AD05
VREFH
Reference Voltage High AVSS + 1.7
—
AVSS
AVSS – 0.3
Reference Inputs
AD06
VREFL
Reference Voltage Low
AD07
VREF
Absolute Reference
Voltage
AD10
VINH-VINL Full-Scale Input Span
AD11
VIN
Absolute Input Voltage
AD12
VINL
Absolute VINL Input
Voltage
AD17
RIN
Recommended
Impedance of Analog
Voltage Source
—
AVDD
V
—
AVDD – 1.7
V
—
AVDD + 0.3
V
Analog Input
VREFL
—
VREFH
V
AVSS – 0.3
—
AVDD + 0.3
V
AVSS – 0.3
—
AVDD/2
V
—
2.5K
(Note 2)
10-bit
ADC Accuracy
AD20b NR
Resolution
—
10
—
bits
AD21b INL
Integral Nonlinearity
—
±1
±2
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD22b DNL
Differential Nonlinearity
—
±1
±1.5
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD23b GERR
Gain Error
—
±1
±3
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD24b EOFF
Offset Error
—
±1
±2
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD25b
Monotonicity(1)
—
—
—
—
Note 1:
2:
Guaranteed
The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.
Measurements taken with external VREF+ and VREF- used as the ADC voltage reference.
2009-2014 Microchip Technology Inc.
DS30009937C-page 201
PIC24F04KA201 FAMILY
TABLE 26-25: ADC CONVERSION TIMING REQUIREMENTS(1)
Standard Operating Conditions: 1.8V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
TCY = 75 ns, AD1CON3
in default state
Clock Parameters
AD50
TAD
ADC Clock Period
75
—
—
ns
AD51
TRC
ADC Internal RC Oscillator
Period
—
250
—
ns
AD55
TCONV
Conversion Time
AD56
FCNV
AD57
TSAMP
AD58
TACQ
Acquisition Time
AD59
TSWC
AD60
TDIS
Conversion Rate
—
12
—
TAD
Throughput Rate
—
—
500
ksps
Sample Time
—
1
—
TAD
750
—
—
ns
Switching Time from Convert to
Sample
—
—
(Note 3)
Discharge Time
0.5
—
—
TAD
3
TAD
AVDD 2.7V
(Note 2)
Clock Parameters
AD61
TPSS
Note 1:
2:
3:
Sample Start Delay from Setting
Sample bit (SAMP)
2
—
Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD).
On the following cycle of the device clock.
DS30009937C-page 202
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
TABLE 26-26: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET TIMING REQUIREMENTS
Standard Operating Conditions: 1.8V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ(1)
Max.
Units
—
s
Conditions
SY10
TmcL
MCLR Pulse Width (low)
2
—
SY11
TPWRT
Power-up Timer Period
50
64
90
ms
SY12
TPOR
Power-on Reset Delay
1
5
10
s
SY13
TIOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—
—
100
ns
SY20
TWDT
Watchdog Timer Time-out Period
0.85
1.0
1.15
ms
1.32 prescaler
3.4
4.0
4.6
ms
1:128 prescaler
SY25
TBOR
Brown-out Reset Pulse Width
1
—
—
s
SY35
TFSCM
Fail-Safe Clock Monitor Delay
—
2
2.3
s
SY45
TRST
Configuration Update Time
—
20
—
s
TVREG
On-Chip Voltage Regulator
Output Delay
—
10
—
s
TLOCK
PLL Start-up Time
—
1
—
ms
SY55
SY65
TOST
Oscillator Start-up Time
—
1024
—
TOSC
SY75
TFRC
Fast RC Oscillator Start-up Time
—
1
1.5
s
SY85
TLPRC
Low-Power Oscillator Start-up
Time
—
—
100
s
Note 1:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2009-2014 Microchip Technology Inc.
DS30009937C-page 203
PIC24F04KA201 FAMILY
NOTES:
DS30009937C-page 204
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
27.0
PACKAGING INFORMATION
27.1
Package Marking Information
14-Lead PDIP
Example
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
14-Lead TSSOP
Example
XXXXXXXX
YYWW
NNN
24F4KA e3
0910
017
20-Lead PDIP
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
PIC24F04KA200
-I/P e3
0910017
PIC24F04KA201-I/P e3
0910017
Product-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2009-2014 Microchip Technology Inc.
DS30009937C-page 205
PIC24F04KA201 FAMILY
20-Lead SSOP
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
20-Lead SOIC (.300”)
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
Example
24F04KA201
-I/SS e3
0910017
Example
PIC24F04KA201
-I/SO e3
0910017
YYWWNNN
20-Lead QFN
XXXXXX
XXXXXX
XXXXXX
YYWWNNN
DS30009937C-page 206
Example
24F04
KA201
/MQ e3
0910017
2009-2014 Microchip Technology Inc.
PIC24F04KA201 FAMILY
27.2
Package Details
The following sections give the technical details of the packages.
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