PIC24F16KA304-E/PT

PIC24FV32KA304 FAMILY 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology Power Management Modes Analog Features • • • • Run – CPU, Flash, SRAM and Peripherals On Doze – CPU Clock Runs Slower than Peripherals Idle – CPU Off, Flash, SRAM and Peripherals On Sleep – CPU, Flash and Peripherals Off, and SRAM On • Deep Sleep – CPU, Flash, SRAM and Most Peripherals Off; Multiple Autonomous Wake-up Sources • Low-Power Consumption: - Run mode currents down to 8 μA, typical - Idle mode currents down to 2.2 μA, typical - Deep Sleep mode currents down to 20 nA, typical - Real-Time Clock/Calendar currents down to 700 nA, 32 kHz, 1.8V - Watchdog Timer is 500 nA, 1.8V typical • 12-Bit, Up to 16-Channel Analog-to-Digital Converter: - 100 ksps conversion rate - Conversion available during Sleep and Idle - Auto-sampling, timer-based option for Sleep and Idle modes - Wake on auto-compare option • Dual Rail-to-Rail Analog Comparators with Programmable Input/Output Configuration • On-Chip Voltage Reference • Internal Temperature Sensor • Charge Time Measurement Unit (CTMU): - Used for capacitance sensing, 16 channels - Time measurement, down to 200 ps resolution - Delay/pulse generation, down to 1 ns resolution High-Performance CPU Special Microcontroller Features • Modified Harvard Architecture • Up to 16 MIPS Operation @ 32 MHz • 8 MHz Internal Oscillator with 4x PLL Option and Multiple Divide Options • 17-Bit by 17-Bit Single-Cycle Hardware Multiplier • 32-Bit by 16-Bit Hardware Divider, 16-Bit x 16-Bit Working Register Array • C Compiler Optimized Instruction Set Architecture • Wide Operating Voltage Range: - 1.8V to 3.6V (PIC24F devices) - 2.0V to 5.5V (PIC24FV devices) • Low-Power Wake-up Sources and Supervisors: - Ultra Low-Power Wake-up (ULPWU) for Sleep/Deep Sleep - Low-Power Watchdog Timer (DSWDT) for Deep Sleep - Extreme Low-Power Brown-out Reset (DSBOR) for Deep Sleep, LPBOR for all other modes • System Frequency Range Declaration bits: - Declaring the frequency range optimizes the current consumption. • Standard Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for Reliable Operation • Programmable High/Low-Voltage Detect (HLVD) • Standard Brown-out Reset (BOR) with 3 Programmable Trip Points that can be Disabled in Sleep • High-Current Sink/Source (18 mA/18 mA) on All I/O Pins • Flash Program Memory: - Erase/write cycles: 10,000 minimum - 40 years’ data retention minimum • Data EEPROM: - Erase/write cycles: 100,000 minimum - 40 years’ data retention minimum • Fail-Safe Clock Monitor (FSCM) • Programmable Reference Clock Output • Self-Programmable under Software Control • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via 2 Pins Peripheral Features • Hardware Real-Time Clock and Calendar (RTCC): - Provides clock, calendar and alarm functions - Can run in Deep Sleep mode - Can use 50/60 Hz power line input as clock source • Programmable 32-Bit Cyclic Redundancy Check (CRC) • Multiple Serial Communication modules: - Two 3/4-wire SPI modules - Two I2C™ modules with multi-master/slave support - Two UART modules supporting RS-485, RS-232, LIN/J2602, IrDA® • Five 16-Bit Timers/Counters with Programmable Prescaler: - Can be paired as 32-bit timers/counters • Three 16-Bit Capture Inputs with Dedicated Timers • Three 16-Bit Compare/PWM Outputs with Dedicated Timers • Configurable Open-Drain Outputs on Digital I/O Pins • Up to Three External Interrupt Sources  2011-2013 Microchip Technology Inc. DS39995D-page 1 PIC24FV32KA304 FAMILY Pins Flash Program (bytes) SRAM (bytes) EE Data (bytes) Timers 16-Bit Capture Input Compare/PWM Output UART w/ IrDA® SPI I2C™ 12-Bit A/D (ch) Comparators CTMU (ch) RTCC Memory PIC24FV16KA301/ PIC24F16KA301 20 16K 2K 512 5 3 3 2 2 2 12 3 12 Y PIC24FV32KA301/ PIC24F32KA301 20 32K 2K 512 5 3 3 2 2 2 12 3 12 Y PIC24FV16KA302/ PIC24F16KA302 28 16K 2K 512 5 3 3 2 2 2 13 3 13 Y PIC24FV32KA302/ PIC24F32KA302 28 32K 2K 512 5 3 3 2 2 2 13 3 13 Y PIC24FV16KA304/ PIC24F16KA304 44 16K 2K 512 5 3 3 2 2 2 16 3 16 Y PIC24FV32KA304/ PIC24F32KA304 44 32K 2K 512 5 3 3 2 2 2 16 3 16 Y PIC24F Device DS39995D-page 2  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 20-Pin SPDIP/SSOP/SOIC(1) MCLR/RA5 RA0 RA1 RB0 RB1 RB2 RA2 RA3 RB4 RA4 1 2 3 4 5 6 7 8 9 10 24FVXXKA301 24FXXKA301 Pin Diagrams 20 19 18 17 16 15 14 13 12 11 VDD VSS RB15 RB14 RB13 RB12 RA6 or VCAP RB9 RB8 RB7 Pin Features Pin PIC24FVXXKA301 PIC24FXXKA301 1 MCLR/VPP/RA5 2 PGEC2/VREF+/CVREF+/AN0/C3INC/SCK2/CN2/RA0 PGEC2/VREF+/CVREF+/AN0/C3INC/SCK2/CN2/RA0 3 PGED2/CVREF-/VREF-/AN1/SDO2/CN3/RA1 PGED2/CVREF-/VREF-/AN1/SDO2/CN3/RA1 4 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/SDI2/ OC2/CN4/RB0 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/SDI2/ OC2/CN4/RB0 5 PGEC1/AN3/C1INC/C2INA/U2RX/OC3/CTED12/CN5/RB1 PGEC1/AN3/C1INC/C2INA/U2RX/OC3/CTED12/CN5/RB1 6 AN4/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2 AN4/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2 7 OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2 OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2 8 OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3 OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3 9 PGED3/SOSCI/AN15/U2RTS/CN1/RB4 PGED3/SOSCI/AN15/U2RTS/CN1/RB4 10 PGEC3/SOSCO/SCLKI/U2CTS/CN0/RA4 PGEC3/SOSCO/SCLKI/U2CTS/CN0/RA4 11 U1TX/C2OUT/OC1/IC1/CTED1/INT0/CN23/RB7 U1TX/INT0/CN23/RB7 12 SCL1/U1CTS/C3OUT/CTED10/CN22/RB8 SCL1/U1CTS/C3OUT/CTED10/CN22/RB8 13 SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9 SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9 14 VCAP C2OUT/OC1/IC1/CTED1/INT2/CN8/RA6 MCLR/VPP/RA5 15 AN12/HLVDIN/SCK1/SS2/IC3/CTED2/INT2/CN14/RB12 AN12/HLVDIN/SCK1/SS2/IC3/CTED2/CN14/RB12 16 AN11/SDO1/OCFB/CTPLS/CN13/RB13 AN11/SDO1/OCFB/CTPLS/CN13/RB13 17 CVREF/AN10/C3INB/RTCC/SDI1/C1OUT/OCFA/CTED5/INT1/ CN12/RB14 CVREF/AN10/C3INB/RTCC/SDI1/C1OUT/OCFA/CTED5/INT1/ CN12/RB14 18 AN9/C3INA/SCL2/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15 AN9/C3INA/SCL2/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15 19 VSS/AVSS VSS/AVSS 20 VDD/AVDD VDD/AVDD Legend: Note 1: Pin numbers in bold indicate pin function differences between PIC24FV and PIC24F devices. PIC24F32KA304 device pins have a maximum voltage of 3.6V and are not 5V tolerant.  2011-2013 Microchip Technology Inc. DS39995D-page 3 PIC24FV32KA304 FAMILY Pin Diagrams MCLR/RA5 RA0 RA1 RB0 RB1 RB2 RB3 VSS RA2 RA3 RB4 RA4 VDD RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC24FVXXKA302 PIC24FXXKA302 28-Pin SPDIP/SSOP/SOIC(1,2) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VSS RB15 RB14 RB13 RB12 RB11 RB10 RA6 or VCAP RA7 RB9 RB8 RB7 RB6 Pin Features Pin PIC24FVXXKA302 PIC24FXXKA302 1 MCLR/VPP/RA5 2 VREF+/CVREF+/AN0/C3INC/CTED1/CN2/RA0 VREF+/CVREF+/AN0/C3INC/CTED1/CN2/RA0 3 CVREF-/VREF-/AN1/CN3/RA1 CVREF-/VREF-/AN1/CN3/RA1 4 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0 5 PGEC1/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1 PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 6 AN4/C1INB/C2IND/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2 AN4/C1INB/C2IND/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2 7 AN5/C1INA/C2INC/SCL2/CN7/RB3 AN5/C1INA/C2INC/SCL2/CN7/RB3 8 VSS VSS 9 OSCI/AN13/CLKI/CN30/RA2 OSCI/AN13/CLKI/CN30/RA2 10 OSCO/AN14/CLKO/CN29/RA3 OSCO/AN14/CLKO/CN29/RA3 11 SOSCI/AN15/U2RTS/CN1/RB4 SOSCI/AN15/U2RTS/CN1/RB4 12 SOSCO/SCLKI/U2CTS/CN0/RA4 SOSCO/SCLKI/U2CTS/CN0/RA4 MCLR/VPP/RA5 13 VDD VDD 14 PGED3/ASDA(1)/SCK2/CN27/RB5 PGED3/ASDA(1)/SCK2/CN27/RB5 15 PGEC3/ASCL(1)/SDO2/CN24/RB6 PGEC3/ASCL(1)/SDO2/CN24/RB6 16 U1TX/C2OUT/OC1/INT0/CN23/RB7 U1TX/INT0/CN23/RB7 17 SCL1/U1CTS/C3OUT/CTED10/CN22/RB8 SCL1/U1CTS/C3OUT/CTED10/CN22/RB8 18 SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9 SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9 19 SDI2/IC1/CTED3/CN9/RA7 SDI2/IC1/CTED3/CN9/RA7 20 VCAP C2OUT/OC1/CTED1/INT2/CN8/RA6 21 PGED2/SDI1/OC3/CTED11/CN16/RB10 PGED2/SDI1/OC3/CTED11/CN16/RB10 22 PGEC2/SCK1/OC2/CTED9/CN15/RB11 PGEC2/SCK1/OC2/CTED9/CN15/RB11 23 AN12/HLVDIN/SS2/IC3/CTED2/INT2/CN14/RB12 AN12/HLVDIN/SS2/IC3/CTED2/CN14/RB12 24 AN11/SDO1/OCFB/CTPLS/CN13/RB13 AN11/SDO1/OCFB/CTPLS/CN13/RB13 25 CVREF/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/RB14 CVREF/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/ RB14 26 AN9/C3INA/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15 AN9/C3INA/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15 27 VSS/AVSS VSS/AVSS 28 VDD/AVDD VDD/AVDD Legend: Note 1: 2: Pin numbers in bold indicate pin function differences between PIC24FV and PIC24F devices. Alternative multiplexing for SDA1 (ASDA1) and SCL1 (ASCL1) when the I2CSEL Configuration bit is set. PIC24F32KA304 device pins have a maximum voltage of 3.6V and are not 5V tolerant. DS39995D-page 4  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY Pin Diagrams RA1 RA0 MCLR/RA5 VDD VSS RB15 RB14 28-Pin QFN(1,2,3) 28 27 26 25 24 23 22 1 2 3 4 5 6 7 21 20 PIC24FVXXKA302 19 18 PIC24FXXKA302 17 16 15 8 9 10 11 12 13 14 RB13 RB12 RB11 RB10 RA6 or VCAP RA7 RB9 RB4 RA4 VDD RB5 RB6 RB7 RB8 RB0 RB1 RB2 RB3 VSS RA2 RA3 Pin Features Pin PIC24FVXXKA302 PIC24FXXKA302 1 PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0 2 PGEC1/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1 PGEC1/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1 3 AN4/C1INB/C2IND/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2 AN4/C1INB/C2IND/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2 4 AN5/C1INA/C2INC/SCL2/CN7/RB3 AN5/C1INA/C2INC/SCL2/CN7/RB3 5 VSS VSS PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0 6 OSCI/AN13/CLKI/CN30/RA2 OSCI/AN13/CLKI/CN30/RA2 7 OSCO/AN14/CLKO/CN29/RA3 OSCO/AN14/CLKO/CN29/RA3 8 SOSCI/AN15/U2RTS/CN1/RB4 SOSCI/AN15/U2RTS/CN1/RB4 9 SOSCO/SCLKI/U2CTS/CN0/RA4 SOSCO/SCLKI/U2CTS/CN0/RA4 10 VDD VDD 11 PGED3/ASDA1(2)/SCK2/CN27/RB5 PGED3/ASDA1(2)/SCK2/CN27/RB5 12 PGEC3/ASCL1(2)/SDO2/CN24/RB6 PGEC3/ASCL1(2)/SDO2/CN24/RB6 13 U1TX/C2OUT/OC1/INT0/CN23/RB7 U1TX/INT0/CN23/RB7 14 SCL1/U1CTS/C3OUT/CTED10/CN22/RB8 SCL1/U1CTS/C3OUT/CTED10/CN22/RB8 15 SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9 SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9 16 SDI2/IC1/CTED3/CN9/RA7 SDI2/IC1/CTED3/CN9/RA7 17 VCAP C2OUT/OC1/CTED1/INT2/CN8/RA6 18 PGED2/SDI1/OC3/CTED11/CN16/RB10 PGED2/SDI1/OC3/CTED11/CN16/RB10 19 PGEC2/SCK1/OC2/CTED9/CN15/RB11 PGEC2/SCK1/OC2/CTED9/CN15/RB11 20 AN12/HLVDIN/SS2/IC3/CTED2/INT2/CN14/RB12 AN12/HLVDIN/SS2/IC3/CTED2/CN14/RB12 21 AN11/SDO1/OCFB/CTPLS/CN13/RB13 AN11/SDO1/OCFB/CTPLS/CN13/RB13 22 CVREF/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/ RB14 CVREF/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/ RB14 23 AN9/C3INA/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15 AN9/C3INA/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15 24 VSS/AVSS VSS/AVSS 25 VDD/AVDD VDD/AVDD 26 MCLR/VPP/RA5 MCLR/VPP/RA5 27 VREF+/CVREF+/AN0/C3INC/CTED1/CN2/RA0 VREF+/CVREF+/AN0/C3INC/CN2/RA0 28 CVREF-/VREF-/AN1/CN3/RA1 CVREF-/VREF-/AN1/CN3/RA1 Legend: Note 1: 2: 3: Pin numbers in bold indicate pin function differences between PIC24FV and PIC24F devices. Exposed pad on underside of device is connected to VSS. Alternative multiplexing for SDA1 (ASDA1) and SCL1 (ASCL1) when the I2CSEL Configuration bit is set. PIC24F32KA304 device pins have a maximum voltage of 3.6V and are not 5V tolerant.  2011-2013 Microchip Technology Inc. DS39995D-page 5 PIC24FV32KA304 FAMILY Pin Diagrams PIC24FVXXKA304 PIC24FXXKA304 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 RB4 RA8 RA3 RA2 VSS VDD RC2 RC1 RC0 RB3 RB2 RA10 RA11 RB14 RB15 VSS VDD MCLR/RA5 RA0 RA1 RB0 RB1 RB9 RC6 RC7 RC8 RC9 RA7 RA6 or VCAP RB10 RB11 RB12 RB13 44 43 42 41 40 39 38 37 36 35 34 RB8 RB7 RB6 RB5 VDD VSS RC5 RC4 RC3 RA9 RA4 44-Pin TQFP/QFN Legend: Note 1: 2: 3: Pin numbers in bold indicate pin function differences between PIC24FV and PIC24F devices. Exposed pad on underside of device is connected to VSS. Alternative multiplexing for SDA1 (ASDA1) and SCL1 (ASCL1) when the I2CSEL Configuration bit is set. PIC24F32KA304 device pins have a maximum voltage of 3.6V and are not 5V tolerant. DS39995D-page 6 Pin Features Pin (1,2,3) PIC24FVXXKA304 PIC24FXXKA304 1 SDA1/T1CK/U1RTS/CTED4/CN21/ SDA1/T1CK/U1RTS/CTED4/CN21/ RB9 RB9 2 U1RX/CN18/RC6 U1RX/CN18/RC6 3 U1TX/CN17/RC7 U1TX/CN17/RC7 4 OC2/CN20/RC8 OC2/CN20/RC8 5 IC2/CTED7/CN19/RC9 IC2/CTED7/CN19/RC9 6 IC1/CTED3/CN9/RA7 IC1/CTED3/CN9/RA7 7 VCAP C2OUT/OC1/CTED1/INT2/CN8/RA6 8 PGED2/SDI1/CTED11/CN16/RB10 PGED2/SDI1/CTED11/CN16/RB10 9 PGEC2/SCK1/CTED9/CN15/RB11 PGEC2/SCK1/CTED9/CN15/RB11 10 AN12/HLVDIN/CTED2/INT2/CN14/ RB12 AN12/HLVDIN/CTED2/CN14/RB12 11 AN11/SDO1/CTPLS/CN13/RB13 AN11/SDO1/CTPLS/CN13/RB13 12 OC3/CN35/RA10 OC3/CN35/RA10 13 IC3/CTED8/CN36/RA11 IC3/CTED8/CN36/RA11 14 CVREF/AN10/C3INB/RTCC/ CVREF/AN10/C3INB/RTCC/ C1OUT/OCFA/CTED5/INT1/CN12/ C1OUT/OCFA/CTED5/INT1/CN12/ RB14 RB14 15 AN9/C3INA/T3CK/T2CK/REFO/ SS1/CTED6/CN11/RB15 AN9/C3INA/T3CK/T2CK/REFO/ SS1/CTED6/CN11/RB15 VSS/AVSS 16 VSS/AVSS 17 VDD/AVDD VDD/AVDD 18 MCLR/VPP/RA5 MCLR/VPP/RA5 19 VREF+/CVREF+/AN0/C3INC/ CTED1/CN2/RA0 VREF+/CVREF+/AN0/C3INC/CN2/ RA0 CVREF-/VREF-/AN1/CN3/RA1 20 CVREF-/VREF-/AN1/CN3/RA1 21 PGED1/AN2/ULPWU/CTCMP/ PGED1/AN2/ULPWU/CTCMP/C1IND/ C1IND/C2INB/C3IND/U2TX/CN4/RB0 C2INB/C3IND/U2TX/CN4/RB0 22 PGEC1/AN3/C1INC/C2INA/U2RX/ CTED12/CN5/RB1 PGEC1/AN3/C1INC/C2INA/U2RX/ CTED12/CN5/RB1 23 AN4/C1INB/C2IND/SDA2/T5CK/ T4CK/CTED13/CN6/RB2 AN4/C1INB/C2IND/SDA2/T5CK/ T4CK/CTED13/CN6/RB2 24 AN5/C1INA/C2INC/SCL2/CN7/ RB3 AN5/C1INA/C2INC/SCL2/CN7/RB3 25 AN6/CN32/RC0 AN6/CN32/RC0 26 AN7/CN31/RC1 AN7/CN31/RC1 27 AN8/CN10/RC2 AN8/CN10/RC2 28 VDD VDD 29 VSS VSS 30 OSCI/AN13/CLKI/CN30/RA2 OSCI/AN13/CLKI/CN30/RA2 31 OSCO/AN14/CLKO/CN29/RA3 OSCO/AN14/CLKO/CN29/RA3 32 OCFB/CN33/RA8 OCFB/CN33/RA8 33 SOSCI/AN15/U2RTS/CN1/RB4 SOSCI/AN15/U2RTS/CN1/RB4 34 SOSCO/SCLKI/U2CTS/CN0/RA4 SOSCO/SCLKI/U2CTS/CN0/RA4 35 SS2/CN34/RA9 SS2/CN34/RA9 36 SDI2/CN28/RC3 SDI2/CN28/RC3 37 SDO2/CN25/RC4 SDO2/CN25/RC4 38 SCK2/CN26/RC5 SCK2/CN26/RC5 VSS 39 VSS 40 VDD VDD 41 PGED3/ASDA1(2)/CN27/RB5 PGED3/ASDA1(2)/CN27/RB5 42 PGEC3/ASCL1(2)/CN24/RB6 PGEC3/ASCL1(2)/CN24/RB6 43 C2OUT/OC1/INT0/CN23/RB7 INT0/CN23/RB7 44 SCL1/U1CTS/C3OUT/CTED10/ CN22/RB8 SCL1/U1CTS/C3OUT/CTED10/ CN22/RB8  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY Pin Diagrams RB8 RB7 RB6 RB5 N/C VDD VSS RC5 RC4 RC3 RA9 RA4 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 PIC24FVXXKA304 PIC24FXXKA304 36 35 34 33 32 31 30 29 28 27 26 25 RB4 RA8 RA3 RA2 N/C VSS VDD RC2 RC1 RC0 RB3 RB2 RA10 RA11 RB14 RB15 VSS/AVSS VDD/AVDD MCLR/RA5 N/C RA0 RA1 RB0 RB1 13 14 15 16 17 18 19 20 21 22 23 24 RB9 RC6 RC7 RC8 RC9 RA7 RA6 or VCAP N/C RB10 RB11 RB12 RB13 Legend: Note 1: 2: 3: Pin numbers in bold indicate pin function differences between PIC24FV and PIC24F devices. Exposed pad on underside of device is connected to VSS. Alternative multiplexing for SDA1 (ASDA1) and SCL1 (ASCL1) when the I2CSEL Configuration bit is set. PIC24F32KA3XX device pins have a maximum voltage of 3.6V and are not 5V tolerant.  2011-2013 Microchip Technology Inc. Pin Features Pin 48-Pin UQFN(1,2,3) PIC24FVXXKA304 PIC24FXXKA304 1 SDA1/T1CK/U1RTS/CTED4/CN21/RB9 SDA1/T1CK/U1RTS/CTED4/CN21/ RB9 2 U1RX/CN18/RC6 U1RX/CN18/RC6 3 U1TX/CN17/RC7 U1TX/CN17/RC7 4 OC2/CN20/RC8 OC2/CN20/RC8 5 IC2/CTED7/CN19/RC9 IC2/CTED7/CN19/RC9 6 IC1/CTED3/CN9/RA7 IC1/CTED3/CN9/RA7 7 VCAP C20UT/OC1/CTED1/INT2CN8/RA6 8 N/C N/C 9 PGED2/SDI1/CTED11/CN16/RB10 PGED2/SDI1/CTED11/CN16/RB10 10 PGEC2/SCK1/CTED9/CN15/RB11 PGEC2/SCK1/CTED9/CN15/RB11 11 AN12/HLVDIN/CTED2/INT2/CN14/RB12 AN12/HLVDIN/CTED2/CN14/RB12 12 AN11/SDO1/CTPLS/CN13/RB13 13 OC3/CN35/RA10 OC3/CN35/RA10 14 IC3/CTED8/CN36/RA11 IC3/CTED8/CN36/RA11 15 CVREF/AN10/C3INB/RTCC/C1OUT/ CVREF/AN10/C3INB/RTCC/ C1OUT/OCFA/CTED5/INT1/CN12/RB14 OCFA/CTED5/INT1/CN12/RB14 16 AN9/C3INA/T3CK/T2CK/REFO/ SS1/CTED6/CN11/RB15 AN9/C3INA/T3CK/T2CK/REFO/ SS1/CTED6/CN11/RB15 17 VSS/AVSS VSS/AVSS 18 VDD/AVDD VDD/AVDD 19 MCLR/RA5 MCLR/RA5 20 N/C N/C 21 VREF+/CVREF+/AN0/C3INC/ CTED1/CN2/RA0 VREF+/CVREF+/AN0/C3INC/CN2/ RA0 22 CVREF-/VREF-/AN1/CN3/RA1 CVREF-/VREF-/AN1/CN3/RA1 23 PGED1/AN2/ULPWU/CTCMP/C1IND/ C2INB/C3IND/U2TX/CN4/RB0 PGED1/AN2/ULPWU/CTCMP/C1IND/ C2INB/C3IND/U2TX/CN4/RB0 24 PGEC1/AN3/C1INC/C2INA/U2RX/ CTED12/CN5/RB1 PGEC1/AN3/C1INC/C2INA/U2RX/ CTED12/CN5/RB1 25 AN4/C1INB/C2IND/SDA2/T5CK/ T4CK/CTED13/CN6/RB2 AN4/C1INB/C2IND/SDA2/T5CK/ T4CK/CTED13/CN6/RB2 26 AN5/C1INA/C2INC/SCL2/CN7/RB3 AN5/C1INA/C2INC/SCL2/CN7/RB3 27 AN6/CN32/RC0 AN6/CN32/RC0 28 AN7/CN31/RC1 AN7/CN31/RC1 29 AN8/CN10/RC2 AN8/CN10/RC2 30 VDD VDD 31 VSS VSS 32 N/C N/C 33 OSCI/AN13/CLKI/CN30/RA2 OSCI/AN13/CLKI/CN30/RA2 34 OSCO/AN14/CLKO/CN29/RA3 OSCO/AN14/CLKO/CN29/RA3 35 OCFB/CN33/RA8 OCFB/CN33/RA8 36 SOSCI/AN15/U2RTS/CN1/RB4 SOSCI/AN15/U2RTS/CN1/RB4 37 SOSCO/SCLKI/U2CTS/CN0/RA4 SOSCO/SCLKI/U2CTS/CN0/RA4 38 SS2/CN34/RA9 SS2/CN34/RA9 39 SDI2/CN28/RC3 SDI2/CN28/RC3 40 SDO2/CN25/RC4 SDO2/CN25/RC4 41 SCK2/CN26/RC5 SCK2/CN26/RC5 42 VSS VSS 43 VDD VDD 44 N/C N/C 45 PGED3/ASDA1(2)/CN27/RB5 PGED3/ASDA1(2)/CN27/RB5 46 PGEC3/ASCL1(2)/CN24/RB6 PGEC3/ASCL1(2)/CN24/RB6 47 C2OUT/OC1/INT0/CN23/RB7 INT0/CN23/RB7 48 SCL1/U1CTS/C3OUT/CTED10/ CN22/RB8 SCL1/U1CTS/C3OUT/CTED10/ CN22/RB8 AN11/SDO1/CTPLS/CN13/RB13 DS39995D-page 7 PIC24FV32KA304 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ........................................................................................................ 23 3.0 CPU ........................................................................................................................................................................................... 29 4.0 Memory Organization ................................................................................................................................................................. 35 5.0 Flash Program Memory .............................................................................................................................................................. 57 6.0 Data EEPROM Memory ............................................................................................................................................................. 63 7.0 Resets ........................................................................................................................................................................................ 69 8.0 Interrupt Controller ..................................................................................................................................................................... 75 9.0 Oscillator Configuration ............................................................................................................................................................ 115 10.0 Power-Saving Features ............................................................................................................................................................ 125 11.0 I/O Ports ................................................................................................................................................................................... 135 12.0 Timer1 ..................................................................................................................................................................................... 139 13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................. 141 14.0 Input Capture with Dedicated Timers ....................................................................................................................................... 147 15.0 Output Compare with Dedicated Timers .................................................................................................................................. 151 16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 161 17.0 Inter-Integrated Circuit™ (I2C™) .............................................................................................................................................. 169 18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 177 19.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 185 20.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 199 21.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 205 22.0 12-Bit A/D Converter with Threshold Detect ............................................................................................................................ 207 23.0 Comparator Module.................................................................................................................................................................. 225 24.0 Comparator Voltage Reference................................................................................................................................................ 229 25.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 231 26.0 Special Features ...................................................................................................................................................................... 239 27.0 Development Support............................................................................................................................................................... 251 28.0 Instruction Set Summary .......................................................................................................................................................... 255 29.0 Electrical Characteristics .......................................................................................................................................................... 263 30.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 295 31.0 Packaging Information.............................................................................................................................................................. 325 Appendix A: Revision History............................................................................................................................................................. 351 Index .................................................................................................................................................................................................. 353 The Microchip Web Site ..................................................................................................................................................................... 359 Customer Change Notification Service .............................................................................................................................................. 359 Customer Support .............................................................................................................................................................................. 359 Reader Response .............................................................................................................................................................................. 360 Product Identification System............................................................................................................................................................. 361 DS39995D-page 8  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2011-2013 Microchip Technology Inc. DS39995D-page 9 PIC24FV32KA304 FAMILY NOTES: DS39995D-page 10  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • • • • • • PIC24FV16KA301, PIC24F16KA301 PIC24FV16KA302, PIC24F16KA302 PIC24FV16KA304, PIC24F16KA304 PIC24FV32KA301, PIC24F32KA301 PIC24FV32KA302, PIC24F32KA302 PIC24FV32KA304, PIC24F32KA304 The PIC24FV32KA304 family introduces a new line of extreme low-power Microchip devices. This is a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance. This family also offers a new migration option for those high-performance applications which may be outgrowing their 8-bit platforms, but do not require the numerical processing power of a digital signal processor. 1.1 1.1.1 Core Features 16-BIT ARCHITECTURE Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC® digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: • 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces • Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data) • A 16-element working register array with built-in software stack support • A 17 x 17 hardware multiplier with support for integer math • Hardware support for 32-bit by 16-bit division • An instruction set that supports multiple addressing modes and is optimized for high-level languages, such as C • Operational performance up to 16 MIPS  2011-2013 Microchip Technology Inc. 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FV32KA304 family incorporate a range of features that can significantly reduce power consumption during operation. Key features include: • On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing users to incorporate power-saving ideas into their software designs. • Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. • Instruction-Based Power-Saving Modes: There are three instruction-based power-saving modes: - Idle Mode: The core is shut down while leaving the peripherals active. - Sleep Mode: The core and peripherals that require the system clock are shut down, leaving the peripherals that use their own clock, or the clock from other devices, active. - Deep Sleep Mode: The core, peripherals (except RTCC and DSWDT), Flash and SRAM are shut down. 1.1.3 OSCILLATOR OPTIONS AND FEATURES The PIC24FV32KA304 family offers five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. • Two External Clock modes offering the option of a divide-by-2 clock output. • Two Fast Internal oscillators (FRCs): One with a nominal 8 MHz output and the other with a nominal 500 kHz output. These outputs can also be divided under software control to provide clock speed as low as 31 kHz or 2 kHz. • A Phase Locked Loop (PLL) frequency multiplier, available to the external Oscillator modes and the 8 MHz FRC oscillator, which allows clock speeds of up to 32 MHz. • A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. DS39995D-page 11 PIC24FV32KA304 FAMILY The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor (FSCM). This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.1.4 EASY MIGRATION Regardless of the memory size, all the devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also helps in migrating to the next larger device. This is true when moving between devices with the same pin count, or even jumping from 20-pin or 28-pin devices to 44-pin/48-pin devices. The PIC24F family is pin compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex. 1.2 Other Special Features • Communications: The PIC24FV32KA304 family incorporates a range of serial communication peripherals to handle a range of application requirements. There is an I2C™ module that supports both the Master and Slave modes of operation. It also comprises UARTs with built-in IrDA® encoders/decoders and an SPI module. • Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. • 12-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and faster sampling speed. The 16-deep result buffer can be used either in Sleep to reduce power, or in Active mode to improve throughput. • Charge Time Measurement Unit (CTMU) Interface: The PIC24FV32KA304 family includes the new CTMU interface module, which can be used for capacitive touch sensing, proximity sensing, and also for precision time measurement and pulse generation. DS39995D-page 12 1.3 Details on Individual Family Members Devices in the PIC24FV32KA304 family are available in 20-pin, 28-pin, 44-pin and 48-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are different from each other in four ways: 1. 2. 3. 4. Flash program memory (16 Kbytes for PIC24FV16KA devices, 32 Kbytes for PIC24FV32KA devices). Available I/O pins and ports (18 pins on two ports for 20-pin devices, 22 pins on two ports for 28-pin devices and 38 pins on three ports for 44/48-pin devices). Alternate SCLx and SDAx pins are available only in 28-pin, 44-pin and 48-pin devices and not in 20-pin devices. Members of the PIC24FV32KA301 family are available as both standard and high-voltage devices. High-voltage devices, designated with an “FV” in the part number (such as PIC24FV32KA304), accommodate an operating VDD range of 2.0V to 5.5V, and have an on-board Voltage Regulator that powers the core. Peripherals operate at VDD. Standard devices, designated by “F” (such as PIC24F32KA304), function over a lower VDD range of 1.8V to 3.6V. These parts do not have an internal regulator, and both the core and peripherals operate directly from VDD. All other features for devices in this family are identical; these are summarized in Table 1-1. A list of the pin features available on the PIC24FV32KA304 family devices, sorted by function, is provided in Table 1-3. Note: Table 1-1 provides the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams on pages 3, 4, 5, 6 and 7 of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first.  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY PIC24FV32KA302 PIC24FV16KA304 PIC24FV32KA304 Program Memory (bytes) 16K 32K 16K 32K 16K 32K Program Memory (instructions) 5632 11264 5632 11264 5632 11264 Features Operating Frequency PIC24FV16KA302 PIC24FV32KA301 DEVICE FEATURES FOR THE PIC24FV32KA304 FAMILY PIC24FV16KA301 TABLE 1-1: DC – 32 MHz Data Memory (bytes) 2048 Data EEPROM Memory (bytes) 512 Interrupt Sources (soft vectors/ NMI traps) 30 (26/4) I/O Ports Total I/O Pins PORTA PORTB PORTA PORTB PORTA PORTB PORTC 23 38 22 37 13 16 17 Timers: Total Number (16-bit) 5 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 3 Output Compare/PWM Channels 3 Input Change Notification Interrupt 16 Serial Communications: UART SPI (3-wire/4-wire) 2 I2C™ 12-Bit Analog-to-Digital Module (input channels) 2 12 Analog Comparators 3 Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) Instruction Set Packages  2011-2013 Microchip Technology Inc. 76 Base Instructions, Multiple Addressing Mode Variations 20-Pin PDIP/SSOP/SOIC 28-Pin SPDIP/SSOP/SOIC/QFN 44-Pin QFN/TQFP 48-Pin UQFN DS39995D-page 13 PIC24FV32KA304 FAMILY Operating Frequency PIC24F32KA304 PIC16F16KA304 PIC24F32KA302 PIC24F16KA302 Features PIC24F32KA301 DEVICE FEATURES FOR THE PIC24F32KA304 FAMILY PIC24F16KA301 TABLE 1-2: DC – 32 MHz Program Memory (bytes) 16K 32K 16K 32K 16K 32K Program Memory (instructions) 5632 11264 5632 11264 5632 11264 Data Memory (bytes) 2048 Data EEPROM Memory (bytes) 512 Interrupt Sources (soft vectors/ NMI traps) 30 (26/4) I/O Ports Total I/O Pins PORTA, PORTB PORTA, PORTB PORTA, PORTB, PORTC 24 39 23 38 13 16 18 Timers: Total Number (16-bit) 5 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 3 Output Compare/PWM Channels 3 Input Change Notification Interrupt 17 Serial Communications: UART SPI (3-wire/4-wire) 2 I2C™ 2 12-Bit Analog-to-Digital Module (input channels) 12 Analog Comparators 3 Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) Instruction Set Packages DS39995D-page 14 76 Base Instructions, Multiple Addressing Mode Variations 20-Pin PDIP/SSOP/SOIC 28-Pin SPDIP/SSOP/SOIC/QFN 44-Pin QFN/TQFP 48-Pin UQFN  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 1-1: PIC24FV32KA304 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller 16 16 8 16 Data Latch PSV and Table Data Access Control Block Data RAM PCL PCH Program Counter Stack Repeat Control Control Logic Logic 23 Address Latch PORTA(1) RA 16 23 16 Read AGU Write AGU Address Latch Program Memory PORTB(1) RB Data EEPROM Data Latch 16 EA MUX Literal Data Address Bus 24 Inst Latch 16 16 PORTC(1) RC Inst Register Instruction Decode and Control Control Signals OSCO/CLKO Timing OSCI/CLKI Generation FRC/LPRC Oscillators Note 1: 16 x 16 W Reg Array Oscillator Start-up Timer Power-on Reset Watchdog Timer Voltage Regulator BOR HLVD 17x17 Multiplier Power-up Timer Precision Band Gap Reference VCAP Divide Support 16-Bit ALU 16 DSWDT VDD, VSS MCLR RTCC Timer1 Timer2/3 Timer4/5 CTMU 12-Bit A/D Comparators REFO IC1-3 PWM/ OC1-3 CN1-22(1) SPI1 I2C1 UART1/2 All pins or features are not implemented on all device pinout configurations. See Table 1-3 for I/O port pin descriptions.  2011-2013 Microchip Technology Inc. DS39995D-page 15 Function PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS F FV Pin Number Pin Number I/O Buffer 21 I ANA 22 I ANA 21 23 I ANA 22 24 I ANA 3 23 25 I ANA 7 4 24 26 I ANA — — — 25 27 I ANA 28 — — — 26 28 I ANA 27 29 — — — 27 29 I ANA 23 15 16 18 26 23 15 16 I ANA 25 22 14 15 17 25 22 14 15 I ANA 24 21 11 12 16 24 21 11 12 I ANA 15 23 20 10 11 15 23 20 10 11 I ANA AN13 7 9 6 30 33 7 9 6 30 33 I ANA AN14 8 10 7 31 34 8 10 7 31 34 I ANA 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN AN0 2 2 27 19 21 2 2 27 19 AN1 3 3 28 20 22 3 3 28 20 AN2 4 4 1 21 23 4 4 1 AN3 5 5 2 22 24 5 5 2 AN4 6 6 3 23 25 6 6 AN5 — 7 4 24 26 — AN6 — — — 25 27 AN7 — — — 26 AN8 — — — AN9 18 26 AN10 17 AN11 16 AN12 Description A/D Analog Inputs  2011-2013 Microchip Technology Inc. AN15 9 11 8 33 36 9 11 8 33 36 I ANA ASCL1 — 15 12 42 46 — 15 12 42 46 I/O I2C™ ASDA1 — 14 11 41 45 — 14 11 41 45 I/O I2C AVDD 20 28 25 17 18 20 28 25 17 18 I ANA AVSS 19 27 24 16 17 19 27 24 16 17 I ANA C1INA 8 7 4 24 26 8 7 4 24 26 I ANA Comparator 1 Input A (+) C1INB 7 6 3 23 25 7 6 3 23 25 I ANA Comparator 1 Input B (-) C1INC 5 5 2 22 24 5 5 2 22 24 I ANA Comparator 1 Input C (+) C1IND 4 4 1 21 23 4 4 1 21 23 I ANA Comparator 1 Input D (-) C1OUT 17 25 22 14 15 17 25 22 14 15 O — C2INA 5 5 2 22 24 5 5 2 22 24 I ANA Comparator 2 Input A (+) Alternate I2C1 Clock Input/Output Alternate I2C1 Data Input/Output A/D Supply Pins Comparator 1 Output C2INB 4 4 1 21 23 4 4 1 21 23 I ANA Comparator 2 Input B (-) C2INC 8 7 4 24 26 8 7 4 24 26 I ANA Comparator 2 Input C (+) C2IND 7 6 3 23 25 7 6 3 23 25 I ANA Comparator 2 Input D (-) C2OUT 14 20 17 7 7 11 16 13 43 47 O — Comparator 2 Output PIC24FV32KA304 FAMILY DS39995D-page 16 TABLE 1-3:  2011-2013 Microchip Technology Inc. TABLE 1-3: Function PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F FV Pin Number Pin Number Buffer 16 I ANA Comparator 3 Input A (+) 15 I ANA Comparator 3 Input B (-) 19 21 I ANA Comparator 3 Input C (+) 1 21 23 I ANA Comparator 3 Input D (-) 17 14 44 48 O — 9 6 30 33 I ANA 8 10 7 31 34 O — System Clock Output 37 10 12 9 34 37 I ST Interrupt-on-Change Inputs 36 9 11 8 33 36 I ST 19 21 2 2 27 19 21 I ST 20 22 3 3 28 20 22 I ST 1 21 23 4 4 1 21 23 I ST 5 2 22 24 5 5 2 22 24 I ST 6 6 3 23 25 6 6 3 23 25 I ST CN7 — 7 4 24 26 –- 7 4 24 26 I ST CN8 14 20 17 7 7 –- –- –- — –- I ST CN9 –- 19 16 6 6 –- 19 16 6 6 I ST CN10 –- — — 27 29 –- –- –- 27 29 I ST CN11 18 26 23 15 16 18 26 23 15 16 I ST CN12 17 25 22 14 15 17 25 22 14 15 I ST CN13 16 24 21 11 12 16 24 21 11 12 I ST CN14 15 23 20 10 11 15 23 20 10 11 I ST CN15 –- 22 19 9 10 –- 22 19 9 10 I ST CN16 –- 21 18 8 9 –- 21 18 8 9 I ST CN17 –- — — 3 3 –- — — 3 3 I ST CN18 — — — 2 2 — — — 2 2 I ST CN19 –- — — 5 5 — — –- 5 5 I ST 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN C3INA 18 26 23 15 16 18 26 23 15 C3INB 17 25 22 14 15 17 25 22 14 C3INC 2 2 27 19 21 2 2 27 C3IND 4 4 1 21 23 4 4 C3OUT 12 17 14 44 48 12 CLK I 7 9 6 30 33 7 CLKO 8 10 7 31 34 CN0 10 12 9 34 CN1 9 11 8 33 CN2 2 2 27 CN3 3 3 28 CN4 4 4 CN5 5 CN6 CN20 –- — — 4 4 — –- –- 4 4 I ST CN21 13 18 15 1 1 13 18 15 1 1 I ST CN22 12 17 14 44 48 12 17 14 44 48 I ST Description Comparator 3 Output Main Clock Input PIC24FV32KA304 FAMILY DS39995D-page 17 I/O 20-Pin PDIP/ SSOP/ SOIC Function PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F FV Pin Number Pin Number 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC CN23 11 16 13 CN24 –- 15 12 CN25 –- — — CN26 –- — — CN27 –- 14 11 CN28 –- — — CN29 8 10 7 28-Pin QFN 28-Pin SPDIP/ SSOP/ SOIC I/O Buffer 48-Pin UQFN 20-Pin PDIP/ SSOP/ SOIC 43 47 11 16 13 43 47 I ST 42 46 –- 15 12 42 46 I ST 37 40 –- –- –- 37 40 I ST 38 41 –- –- –- 38 41 I ST 41 45 –- 14 11 41 45 I ST 36 39 –- –- –- 36 39 I ST 31 34 8 10 7 31 34 I ST 44-Pin QFN/ TQFP 28-Pin QFN 44-Pin QFN/ TQFP Description 48-Pin UQFN Interrupt-on-Change Inputs  2011-2013 Microchip Technology Inc. CN30 7 9 6 30 33 7 9 6 30 33 I ST CN31 –- — — 26 28 — — — 26 28 I ST CN32 –- — — 25 27 — — — 25 27 I ST CN33 –- — — 32 35 — — — 32 35 I ST CN34 –- — — 35 38 — — — 35 38 I ST CN35 –- — — 12 13 — — — 12 13 I ST CN36 –- — — 13 14 — — — 13 14 I ST CVREF 17 25 22 14 15 17 25 22 14 15 I ANA Comparator Voltage Reference Output CVREF+ 2 2 27 19 21 2 2 27 19 21 I ANA Comparator Reference Positive Input Voltage CVREF- 3 3 28 20 22 3 3 28 20 22 I ANA Comparator Reference Negative Input Voltage CTCMP 4 4 1 21 23 4 4 1 21 23 I ANA CTED1 14 20 17 7 7 11 2 27 19 21 I ST CTED2 15 23 20 10 11 15 23 20 10 11 I ST CTED3 — 19 16 6 6 — 19 16 6 6 I ST CTED4 13 18 15 1 1 13 18 15 1 1 I ST CTED5 17 25 22 14 15 17 25 22 14 15 I ST CTED6 18 26 23 15 16 18 26 23 15 16 I ST CTED7 — — — 5 5 — — — 5 5 I ST CTED8 — — — 13 14 — — — 13 14 I ST CTED9 — 22 19 9 10 — 22 19 9 10 I ST CTED10 12 17 14 44 48 12 17 14 44 48 I ST CTED11 — 21 18 8 9 — 21 18 8 9 I ST CTED12 5 5 2 22 24 5 5 2 22 24 I ST CTED13 6 6 3 23 25 6 6 3 23 25 I ST CTMU Comparator Input CTMU Trigger Edge Inputs PIC24FV32KA304 FAMILY DS39995D-page 18 TABLE 1-3:  2011-2013 Microchip Technology Inc. TABLE 1-3: Function PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC F FV Pin Number Pin Number 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC I/O 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN Buffer Description CTPLS 16 24 21 11 12 16 24 21 11 12 O — HLVDIN 15 23 20 10 11 15 23 20 10 11 I ST CTMU Pulse Output High/Low-Voltage Detect Input IC1 14 19 16 6 6 11 19 16 6 6 I ST Input Capture 1 Input IC2 13 18 15 5 5 13 18 15 5 5 I ST Input Capture 2 Input IC3 15 23 20 13 14 15 23 20 13 14 I ST Input Capture 3 Input INT0 11 16 13 43 47 11 16 13 43 47 I ST Interrupt 0 Input INT1 17 25 22 14 15 17 25 22 14 15 I ST Interrupt 1 Input INT2 14 20 17 7 7 15 23 20 10 11 I ST Interrupt 2 Input Master Clear (Device Reset) Input (active-low) 1 1 26 18 19 1 1 26 18 19 I ST OC1 14 20 17 7 7 11 16 13 43 47 O — Output Compare/PWM1 Output OC2 4 22 19 4 4 4 22 19 4 4 O — Output Compare/PWM2 Output OC3 5 21 18 12 13 5 21 18 12 13 O — Output Compare/PWM3 Output OCFA 17 25 22 14 15 17 25 22 14 15 O — Output Compare Fault A OFCB 16 24 21 32 35 16 24 21 32 35 O — Output Compare Fault B OSCI 7 9 6 30 33 7 9 6 30 33 I ANA Main Oscillator Input OSCO 8 10 7 31 34 8 10 7 31 34 O ANA Main Oscillator Output PGEC1 5 5 2 22 24 5 5 2 22 24 I/O ST PCED1 4 4 1 21 23 4 4 1 21 23 I/O ST ICSP Data 1 PGEC2 2 22 19 19 10 2 22 19 19 10 I/O ST ICSP Clock 2 ICSP Data 2 ICSP™ Clock 1 PGED2 3 21 18 8 9 3 21 18 8 9 I/O ST PGEC3 10 15 12 42 46 10 15 12 42 46 I/O ST ICSP Clock 3 PGED3 9 14 11 41 45 9 14 11 41 45 I/O ST ICSP Data 3 DS39995D-page 19 PIC24FV32KA304 FAMILY MCLR Function PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC F FV Pin Number Pin Number 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC I/O 28-Pin QFN 44-Pin QFN/ TQFP Buffer Description 48-Pin UQFN RA0 2 2 27 19 21 2 2 27 19 21 I/O ST RA1 3 3 28 20 22 3 3 28 20 22 I/O ST ST RA2 7 9 6 30 33 7 9 6 30 33 I/O RA3 8 10 7 31 34 8 10 7 31 34 I/O ST RA4 10 12 9 34 37 10 12 9 34 37 I/O ST ST RA5 1 1 26 18 19 1 1 26 18 19 I/O RA6 14 20 17 7 7 — — — — — I/O ST RA7 — 19 16 6 6 — 19 16 6 6 I/O ST RA8 — — — 32 35 — — — 32 35 I/O ST RA9 — — — 35 38 — — — 35 38 I/O ST RA10 — — — 12 13 — — — 12 13 I/O ST RA11 — — — 13 14 — — — 13 14 I/O ST RB0 4 4 1 21 23 4 4 1 21 23 I/O ST RB1 5 5 2 22 24 5 5 2 22 24 I/O ST RB2 6 6 3 23 25 6 6 3 23 25 I/O ST RB3 — 7 4 24 26 — 7 4 24 26 I/O ST RB4 9 11 8 33 36 9 11 8 33 36 I/O ST RB5 — 14 11 41 45 — 14 11 41 45 I/O ST RB6 — 15 12 42 46 — 15 12 42 46 I/O ST  2011-2013 Microchip Technology Inc. RB7 11 16 13 43 47 11 16 13 43 47 I/O ST RB8 12 17 14 44 48 12 17 14 44 48 I/O ST RB9 13 18 15 1 1 13 18 15 1 1 I/O ST RB10 — 21 18 8 9 — 21 18 8 9 I/O ST RB11 — 22 19 9 10 — 22 19 9 10 I/O ST RB12 15 23 20 10 11 15 23 20 10 11 I/O ST RB13 16 24 21 11 12 16 24 21 11 12 I/O ST RB14 17 25 22 14 15 17 25 22 14 15 I/O ST RB15 18 26 23 15 16 18 26 23 15 16 I/O ST PORTA Pins PORTB Pins PIC24FV32KA304 FAMILY DS39995D-page 20 TABLE 1-3:  2011-2013 Microchip Technology Inc. TABLE 1-3: Function PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC F FV Pin Number Pin Number 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC 28-Pin QFN 44-Pin QFN/ TQFP I/O Buffer Description 48-Pin UQFN — — — 25 27 — — — 25 27 I/O ST RC1 — — — 26 28 — — — 26 28 I/O ST PORTC Pins RC2 — — — 27 29 — — — 27 29 I/O ST RC3 — — — 36 39 — — — 36 39 I/O ST RC4 — — — 37 40 — — — 37 40 I/O ST RC5 — — — 38 41 — — — 38 41 I/O ST RC6 — — — 2 2 — — — 2 2 I/O ST RC7 — — — 3 3 — — — 3 3 I/O ST RC8 — — — 4 4 — — — 4 4 I/O ST RC9 — — — 5 5 — — — 5 5 I/O ST REFO 18 26 23 15 16 18 26 23 15 16 O — Reference Clock Output RTCC 17 25 22 14 15 17 25 22 14 15 O — Real-Time Clock/Calendar Output SCK1 15 22 19 9 10 15 22 19 9 10 I/O ST SPI1 Serial Input/Output Clock SCK2 2 14 11 38 41 2 14 11 38 41 I/O ST SPI2 Serial Input/Output Clock SCL1 12 17 14 44 48 12 17 14 44 48 I/O I2 C I2C1 Clock Input/Output SCL2 18 7 4 24 26 18 7 4 24 26 I/O I2 C I2C2 Clock Input/Output SCLKI 10 12 9 34 37 10 12 9 34 37 I ST Digital Secondary Clock Input SDA1 13 18 15 1 1 13 18 15 1 1 I/O I2 C I2C1 Data Input/Output SDA2 6 6 3 23 25 6 6 3 23 25 I/O I2C I2C2 Data Input/Output SDI1 17 21 18 8 9 17 21 18 8 9 I ST SPI1 Serial Data Input SDI2 4 19 16 36 39 4 19 16 36 39 I ST SPI2 Serial Data Input SDO1 16 24 21 11 12 16 24 21 11 12 O — SPI1 Serial Data Output SDO2 3 15 12 37 40 3 15 12 37 40 O — SOSCI 9 11 8 33 36 9 11 8 33 36 I ANA Secondary Oscillator Input Secondary Oscillator Output SPI2 Serial Data Output DS39995D-page 21 SOSCO 10 12 9 34 37 10 12 9 34 37 O ANA SS1 18 26 23 15 16 18 26 23 15 16 O — SPI1 Slave Select SS2 15 23 20 35 38 15 23 20 35 38 O — SPI2 Slave Select PIC24FV32KA304 FAMILY RC0 Function PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC F FV Pin Number Pin Number 28-Pin QFN 44-Pin QFN/ TQFP 48-Pin UQFN 20-Pin PDIP/ SSOP/ SOIC 28-Pin SPDIP/ SSOP/ SOIC I/O 28-Pin QFN 44-Pin QFN/ TQFP Buffer Description 48-Pin UQFN T1CK 13 18 15 1 1 13 18 15 1 1 I ST Timer1 Clock T2CK 18 26 23 15 16 18 26 23 15 16 I ST Timer2 Clock T3CK 18 26 23 15 16 18 26 23 15 16 I ST Timer3 Clock T4CK 6 6 3 23 25 6 6 3 23 25 I ST Timer4 Clock T5CK 6 6 3 23 25 6 6 3 23 25 I ST Timer5 Clock UART1 Clear-to-Send Input U1CTS 12 17 14 44 48 12 17 14 44 48 I ST U1RTS 13 18 15 1 1 13 18 15 1 1 O — UART1 Request-to-Send Output U1RX 6 6 3 2 2 6 6 3 2 2 I ST UART1 Receive U1TX 11 16 13 3 3 11 16 13 3 3 O — UART1 Transmit U2CTS 10 12 9 34 37 10 12 9 34 37 I ST UART2 Clear-to-Send Input U2RTS 9 11 8 33 36 9 11 8 33 36 O — UART2 Request-to-Send Output U2RX 5 5 2 22 24 5 5 2 22 24 I ST UART2 Receive U2TX 4 4 1 21 23 4 4 1 21 23 O — ULPWU 4 4 1 21 23 4 4 1 21 23 I ANA UART2 Transmit Ultra Low-Power Wake-up Input VCAP — — — — — 14 20 17 7 7 P — Core Power VDD 20 28,13 25,10 17,28,40 18,30,43 20 28,13 25,10 17,28,40 18,30,43 P — Device Digital Supply Voltage VREF+ 2 2 27 19 21 2 2 27 19 21 I ANA VREF- 3 3 28 20 22 3 3 28 20 22 I ANA VSS 19 27,8 24,5 16,29,39 17,31,42 19 27,8 24,5 16,29,39 17,31,42 P — A/D Reference Voltage Input (+) A/D Reference Voltage Input (-) Device Digital Ground Return PIC24FV32KA304 FAMILY DS39995D-page 22 TABLE 1-3:  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • VCAP pins (see Section 2.4 “Voltage Regulator Pin (VCAP)”) VSS VDD R2 MCLR VCAP C1 C7 PIC24FXXKXX(3) VSS VDD VDD VSS C3(2) C6(2) C5(2) C4(2) These pins must also be connected if they are being used in the end application: Key (all values are recommendations): • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 “External Oscillator Pins”) C7: 10 F, 16V tantalum or ceramic Additionally, the following pins may be required: C1 through C6: 0.1 F, 20V ceramic R1: 10 kΩ R2: 100Ω to 470Ω Note 1: 2: • VREF+/VREF- pins are used when external voltage reference for analog modules is implemented Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. (1) VSS The following pins must always be connected: R1 VDD Getting started with the PIC24FV32KA304 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. VDD AVSS Basic Connection Requirements AVDD 2.1 3: See Section 2.4 “Voltage Regulator Pin (VCAP)” for explanation of VCAP pin connections. The example shown is for a PIC24F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. Some PIC24F K parts do not have a regulator. The minimum mandatory connections are shown in Figure 2-1.  2011-2013 Microchip Technology Inc. DS39995D-page 23 PIC24FV32KA304 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). • Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. 2.2.2 2.3 Master Clear (MCLR) Pin The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application’s requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: VDD R1 R2 JP DS39995D-page 24 MCLR PIC24FXXKXX C1 Note 1: TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. EXAMPLE OF MCLR PIN CONNECTIONS 2: R1  10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R2  470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met.  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY Voltage Regulator Pin (VCAP) Note: This section applies only to PIC24F K devices with an On-Chip Voltage Regulator. Refer to Section 29.0 “Electrical Characteristics” for information on VDD and VDDCORE. FIGURE 2-3: Some of the PIC24F K devices have an internal Voltage Regulator. These devices have the Voltage Regulator output brought out on the VCAP pin. On the PIC24F K devices with regulators, a low-ESR (< 5Ω) capacitor is required on the VCAP pin to stabilize the Voltage Regulator output. The VCAP pin must not be connected to VDD and must use a capacitor of 10 µF connected to ground. The type can be ceramic or tantalum. Suitable examples of capacitors are shown in Table 2-1. Capacitors with equivalent specifications can be used. Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices. The placement of this capacitor should be close to VCAP. It is recommended that the trace length not exceed 0.25 inch (6 mm). Refer to Section 29.0 “Electrical Characteristics” for additional information. TABLE 2-1: Make FREQUENCY vs. ESR PERFORMANCE FOR SUGGESTED VCAP 10 1 ESR () 2.4 0.1 0.01 0.001 0.01 Note: 0.1 1 10 100 Frequency (MHz) 1000 10,000 Typical data measurement at 25°C, 0V DC bias. SUITABLE CAPACITOR EQUIVALENTS Part # Nominal Capacitance Base Tolerance Rated Voltage Temp. Range TDK C3216X7R1C106K 10 µF ±10% 16V -55 to 125ºC TDK C3216X5R1C106K 10 µF ±10% 16V -55 to 85ºC Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to 125ºC Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to 85ºC Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to 125ºC Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to 85ºC  2011-2013 Microchip Technology Inc. DS39995D-page 25 PIC24FV32KA304 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal Voltage Regulator of this microcontroller. However, some care is needed in selecting the capacitor to ensure that it maintains sufficient capacitance over the intended operating range of the application. Typical low-cost, 10 F ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also available, but are less common). The initial tolerance specifications for these types of capacitors are often specified as ±10% to ±20% (X5R and X7R), or -20%/+80% (Y5V). However, the effective capacitance that these capacitors provide in an application circuit will also vary based on additional factors, such as the applied DC bias voltage and the temperature. The total in-circuit tolerance is, therefore, much wider than the initial tolerance specification. The X5R and X7R capacitors typically exhibit satisfactory temperature stability (ex: ±15% over a wide temperature range, but consult the manufacturer’s data sheets for exact specifications). However, Y5V capacitors typically have extreme temperature tolerance specifications of +22%/-82%. Due to the extreme temperature tolerance, a 10 F nominal rated Y5V type capacitor may not deliver enough total capacitance to meet minimum internal Voltage Regulator stability and transient response requirements. Therefore, Y5V capacitors are not recommended for use with the internal regulator if the application must operate over a wide temperature range. In addition to temperature tolerance, the effective capacitance of large value ceramic capacitors can vary substantially, based on the amount of DC voltage applied to the capacitor. This effect can be very significant, but is often overlooked or is not always documented. A typical DC bias voltage vs. capacitance graph for X7R type capacitors is shown in Figure 2-4. FIGURE 2-4: Capacitance Change (%) 2.4.1 DC BIAS VOLTAGE vs. CAPACITANCE CHARACTERISTICS 10 0 -10 16V Capacitor -20 -30 -40 10V Capacitor -50 -60 -70 6.3V Capacitor -80 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DC Bias Voltage (VDC) When selecting a ceramic capacitor to be used with the internal Voltage Regulator, it is suggested to select a high-voltage rating, so that the operating voltage is a small percentage of the maximum rated capacitor voltage. For example, choose a ceramic capacitor rated at 16V for the 3.3V or 2.5V core voltage. Suggested capacitors are shown in Table 2-1. 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100Ω. Pull-up resistors, series diodes and capacitors on the PGC and PGD pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits, and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the “Communication Channel Select” (i.e., PGCx/PGDx pins), programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section 27.0 “Development Support”. DS39995D-page 26  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Single-Sided and In-Line Layouts: Copper Pour (tied to ground) For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site (www.microchip.com): • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” 2.7 Unused I/Os Primary Oscillator Crystal DEVICE PINS Primary Oscillator OSC1 C1 ` OSC2 GND C2 ` T1OSO T1OS I Timer1 Oscillator Crystal Layout suggestions are shown in Figure 2-5. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. In planning the application’s routing and I/O assignments, ensure that adjacent port pins and other signals, in close proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT ` T1 Oscillator: C1 T1 Oscillator: C2 Fine-Pitch (Dual-Sided) Layouts: Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) OSCO C2 Oscillator Crystal GND C1 OSCI DEVICE PINS Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ to 10 kΩ resistor to VSS on unused pins and drive the output to logic low.  2011-2013 Microchip Technology Inc. DS39995D-page 27 PIC24FV32KA304 FAMILY NOTES: DS39995D-page 28  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 3.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the CPU, refer to the “PIC24F Family Reference Manual”, Section 2. “CPU” (DS39703). The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M instructions of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any point. PIC24F devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can act as a data, address or address offset register. The 16th working register (W15) operates as a Software Stack Pointer (SSP) for interrupts and calls. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K word boundary of either program memory or data EEPROM memory, defined by the 8-bit Program Space Visibility Page Address (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing trinary operations (i.e., A + B = C) to be executed in a single cycle. A high-speed, 17-bit by 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. The multiplier supports Signed, Unsigned and Mixed mode, 16-bit by 16-bit or 8-bit by 8-bit integer multiplication. All multiply instructions execute in a single cycle. The 16-bit ALU has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism and a selection of iterative divide instructions to support 32-bit (or 16-bit), divided by 16-bit integer signed and unsigned division. All divide operations require 19 cycles to complete but are interruptible at any cycle boundary. The PIC24F has a vectored exception scheme with up to eight sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. A block diagram of the CPU is illustrated in Figure 3-1. 3.1 Programmer’s Model Figure 3-2 displays the programmer’s model for the PIC24F. All registers in the programmer’s model are memory mapped and can be manipulated directly by instructions. Table 3-1 provides a description of each register. All registers associated with the programmer’s model are memory mapped. The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18, but maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are supported, either directly, or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs. The core supports Inherent (no operand), Relative, Literal, Memory Direct and three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements.  2011-2013 Microchip Technology Inc. DS39995D-page 29 PIC24FV32KA304 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 PCL PCH Program Counter Loop Stack Control Control Logic Logic 23 16 Data RAM Address Latch 23 16 RAGU WAGU Address Latch Program Memory Data EEPROM EA MUX Address Bus Data Latch ROM Latch 24 16 Instruction Decode and Control Literal Data 16 Instruction Reg Control Signals to Various Blocks Hardware Multiplier Divide Support 16 x 16 W Register Array 16 16-Bit ALU 16 To Peripheral Modules TABLE 3-1: CPU CORE REGISTERS Register(s) Name Description W0 through W15 Working Register Array PC 23-Bit Program Counter SR ALU STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register PSVPAG Program Space Visibility Page Address Register RCOUNT Repeat Loop Counter Register CORCON CPU Control Register DS39995D-page 30  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address Registers W8 W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 SPLIM 0 22 0 0 PC 7 0 TBLPAG 7 0 PSVPAG 15 0 RCOUNT SRH SRL — — — — — — — DC IPL 2 1 0 RA N OV Z C 15 15 Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register 0 ALU STATUS Register (SR) 0 — — — — — — — — — — — — IPL3 PSV — — CPU Control Register (CORCON) Registers or bits are shadowed for PUSH.S and POP.S instructions.  2011-2013 Microchip Technology Inc. DS39995D-page 31 PIC24FV32KA304 FAMILY 3.2 CPU Control Registers REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HSC — — — — — — — DC bit 15 bit 8 R/W-0, HSC(1) R/W-0, HSC(1) R/W-0, HSC(1) (2) IPL1(2) IPL2 IPL0(2) R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC RA N OV Z C bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 DC: ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th or 8th low-order bit of the result has occurred bit 7-5 IPL: CPU Interrupt Priority Level Status bits(1,2) 111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: ALU Overflow bit 1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation 0 = No overflow has occurred bit 1 Z: ALU Zero bit 1 = An operation, which effects the Z bit, has set it at some time in the past 0 = The most recent operation, which effects the Z bit, has cleared it (i.e., a non-zero result) bit 0 C: ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit (MSb) of the result occurred 0 = No carry-out from the Most Significant bit (MSb) of the result occurred Note 1: 2: The IPLx Status bits are read-only when NSTDIS (INTCON1) = 1. The IPL Status bits are concatenated with the IPL3 bit (CORCON) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS39995D-page 32  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 3-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — U-0 R/C-0, HSC R/W-0 U-0 U-0 — IPL3(1) PSV — — bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space is visible in data space 0 = Program space is not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: 3.3 x = Bit is unknown User interrupts are disabled when IPL3 = 1. Arithmetic Logic Unit (ALU) The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location.  2011-2013 Microchip Technology Inc. The PIC24F CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware division for 16-bit divisor. 3.3.1 MULTIPLIER The ALU contains a high-speed, 17-bit x 17-bit multiplier. It supports unsigned, signed or mixed sign operation in several multiplication modes: • • • • • • • 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned DS39995D-page 33 PIC24FV32KA304 FAMILY 3.3.2 DIVIDER 3.3.3 The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. Sixteen-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn), and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. TABLE 3-2: Instruction MULTI-BIT SHIFT SUPPORT The PIC24F ALU supports both single bit and single-cycle, multi-bit arithmetic and logic shifts. Multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided in Table 3-2. INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION Description ASR Arithmetic shift right source register by one or more bits. SL Shift left source register by one or more bits. LSR Logical shift right source register by one or more bits. DS39995D-page 34  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 4.0 MEMORY ORGANIZATION As Harvard architecture devices, the PIC24F microcontrollers feature separate program and data memory space and bussing. This architecture also allows the direct access of program memory from the data space during code execution. 4.1 Program Address Space User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. Memory maps for the PIC24FV32KA304 family of devices are shown in Figure 4-1. The program address memory space of the PIC24FV32KA304 family is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during program execution, or from a table operation or data space remapping, as described in Section 4.3 “Interfacing Program and Data Memory Spaces”. PROGRAM SPACE MEMORY MAP FOR PIC24FV32KA304 FAMILY DEVICES User Memory Space FIGURE 4-1: PIC24FV16KA304 PIC24FV32KA304 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h Flash Program Memory (5632 instructions) User Flash Program Memory (11264 instructions) Unimplemented Read ‘0’ 002BFEh 0057FEh Unimplemented Read ‘0’ 7FFE00h Configuration Memory Space Data EEPROM Note: Reserved Data EEPROM 7FFFFFh 800000h Reserved Device Config Registers Device Config Registers Reserved Reserved DEVID (2) DEVID (2) F7FFFEh F80000h F80010h F80012h FEFFFEh FF0000h FFFFFFh Memory areas are not displayed to scale. DS39995D-page 35  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.3 In the PIC24FV32KA304 family, the data EEPROM is mapped to the top of the user program memory space, starting at address, 7FFE00, and expanding up to address, 7FFFFF. The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address, as shown in Figure 4-2. The data EEPROM is organized as 16-bit wide memory and 256 words deep. This memory is accessed using table read and write operations similar to the user code memory. 4.1.4 Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. 4.1.2 DEVICE CONFIGURATION WORDS Table 4-1 provides the addresses of the device Configuration Words for the PIC24FV32KA304 family. Their location in the memory map is shown in Figure 4-1. For more information on device Configuration Words, see Section 26.0 “Special Features”. HARD MEMORY VECTORS All PIC24F devices reserve the addresses between 00000h and 000200h for hard coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 000000h, with the actual address for the start of code at 000002h. TABLE 4-1: DEVICE CONFIGURATION WORDS FOR PIC24FV32KA304 FAMILY DEVICES Configuration Words PIC24F devices also have two Interrupt Vector Tables, located from 000004h to 0000FFh and 000104h to 0001FFh. These vector tables allow each of the many device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the Interrupt Vector Tables (IVT) is provided in Section 8.1 “Interrupt Vector Table (IVT)”. FIGURE 4-2: DATA EEPROM Configuration Word Addresses FBS F80000 FGS F80004 FOSCSEL F80006 FOSC F80008 FWDT F8000A FPOR F8000C FICD F8000E FDS F80010 PROGRAM MEMORY ORGANIZATION msw Address 23 000001h 000003h 000005h 000007h least significant word most significant word 16 8  2011-2013 Microchip Technology Inc. 0 000000h 000002h 000004h 000006h 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) PC Address (lsw Address) Instruction Width DS39995D-page 36 PIC24FV32KA304 FAMILY 4.2 Data Address Space PIC24FV32KA304 family devices implement a total of 1024 words of data memory. If an EA points to a location outside of this area, an all zero word or byte will be returned. The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 4-3. 4.2.1 The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all the data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA = 0) is used for implemented memory addresses, while the upper half (EA = 1) is reserved for the Program Space Visibility (PSV) area (see Section 4.3.3 “Reading Data From Program Memory Using Program Space Visibility”). FIGURE 4-3: DATA SPACE WIDTH DATA SPACE MEMORY MAP FOR PIC24FV32KA304 FAMILY DEVICES MSB Address 0001h 07FFh 0801h Implemented Data RAM MSB LSB SFR Space LSB Address 0000h 07FEh 0800h SFR Space Near Data Space Data RAM 0FFFh 0FFEh 1FFF 1FFEh Unimplemented Read as ‘0’ 7FFFh 8001h 7FFFh 8000h Program Space Visibility Area FFFFh Note: FFFEh Data memory areas are not shown to scale. DS39995D-page 37  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address. To maintain backward compatibility with PIC® MCU devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all Effective Address (EA) calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words. 4.2.3 The 8-Kbyte area between 0000h and 1FFFh is referred to as the Near Data Space (NDS). Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. The remainder of the data space is addressable indirectly. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing (MDA) with a 16-bit address field. For PIC24FV32KA304 family devices, the entire implemented data memory lies in Near Data Space. Data byte reads will read the complete word, which contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and the registers are organized as two parallel, byte-wide entities with shared (word) address decode, but separate write lines. Data byte writes only write to the corresponding side of the array or register, which matches the byte address. 4.2.4 SFR SPACE The first 2 Kbytes of the Near Data Space, from 0000h to 07FFh, are primarily occupied with Special Function Registers (SFRs). These are used by the PIC24F core and peripheral modules for controlling the operation of the device. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed, but the write will not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault. SFRs are distributed among the modules that they control and are generally grouped together by the module. Much of the SFR space contains unused addresses; these are read as ‘0’. The SFR space, where the SFRs are actually implemented, is provided in Table 4-2. Each implemented area indicates a 32-byte region, where at least one address is implemented as an SFR. A complete listing of implemented SFRs, including their addresses, is provided in Table 4-3 through Table 4-25. All byte loads into any W register are loaded into the LSB; the MSB is not modified. A Sign-Extend (SE) instruction is provided to allow the users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users TABLE 4-2: NEAR DATA SPACE IMPLEMENTED REGIONS OF SFR DATA SPACE SFR Space Address xx00 xx20 000h xx60 Core 100h 200h xx40 Timers I2C™ ICN Capture UART 300h — SPI A/D/CMTU 400h — 500h — 600h — 700h — — — xx80 xxA0 xxC0 xxE0 Interrupts — Compare — — — — — — — — — — — — — — — — — — — — — — RTC/Comp CRC — System/DS/HLVD NVM/PMD — — I/O — — — Legend: — = No implemented SFRs in this block.  2011-2013 Microchip Technology Inc. DS39995D-page 38 File Name Start Addr CPU CORE REGISTERS MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets WREG0 0000 WREG0 0000 WREG1 0002 WREG1 0000 WREG2 0004 WREG2 0000 WREG3 0006 WREG3 0000 0000 WREG4 0008 WREG4 WREG5 000A WREG5 0000 WREG6 000C WREG6 0000 WREG7 000E WREG7 0000 WREG8 0010 WREG8 0000 WREG9 0012 WREG9 0000 WREG10 0014 WREG10 0000 WREG11 0016 WREG11 0000 WREG12 0018 WREG12 0000 WREG13 001A WREG13 0000 WREG14 001C WREG14 0000 WREG15 001E WREG15 0000 SPLIM 0020 SPLIM xxxx PCL 002E PCH 0030 — — — — — — — — TBLPAG 0032 — — — — — — — — TBLPAG PSVPAG 0034 — — — — — — — — PSVPAG RCOUNT 0036 PCL 0000 — PCH 0000 0000 0000 RCOUNT xxxxx  2011-2013 Microchip Technology Inc. SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000 CORCON 0044 — — — — — — — — — — — — IPL3 PSV — — 0000 DISICNT 0052 — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DISICNT xxxx PIC24FV32KA304 FAMILY DS39995D-page 39 TABLE 4-3:  2011-2013 Microchip Technology Inc. TABLE 4-4: File Addr Name ICN REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 CN12PDE Bit 11 Bit 10 Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 All Resets CN4PDE CN3PDE CN2PDE CN1PDE CN0PDE 0000 CN14PDE CN13PDE CN30PDE CN29PDE CN28PDE(1,2) CN27PDE(1) CN26PDE(1,2) CN25PDE(1,2) CN24PDE(1) CN23PDE CN22PDE CN21PDE CN20PDE(1,2) CN19PDE(1,2) CN18PDE(1,2) CN17PDE(1,2) CN16PDE(1) — — CNEN1 0062 CN15IE(1) CN14IE CN13IE CNEN2 0064 CN31IE(1,2) CN30IE CN29IE CNEN3 0066 — — — — CNPU1 006E CN15PUE(1) CN14PUE CN13PUE CN12PUE CNPU2 0070 CN31PUE(1,2) CN30PUE CN29PUE CN28PUE(1,2) CN27PUE(1) CN26PUE(1,2) CN25PUE(1,2) CN24PUE(1) CN23PUE CN22PUE CN21PUE CN20PUE(1,2) CN19PUE(1,2) CN18PUE(1,2) CN17PUE(1,2) CN16PUE(1) — — — CN12IE CN11IE CN10IE(1,2) CN28IE(1,2) CN27IE(1) CN26IE(1,2) — — — — — CN11PUE CN10PUE(1,2) — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: 2: 3: These bits are not implemented in 20-pin devices. These bits are not implemented in 28-pin devices. These bits are not implemented in FV devices. — — — CN9IE(1) CN8IE(3) CN7IE(1) CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 CN25IE(1,2) CN24IE(1) CN23IE CN22IE CN21IE CN20IE(1,2) CN19IE(1,2) CN18IE(1,2) CN17IE(1,2) CN16IE(1) 0000 — — — — CN36IE(1,2) CN35IE(1,2) CN34IE(1,2) CN33IE(1,2) CN32IE(1,2) 0000 CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 — — 0000 — CN9PUE(1) — CN36PDE(1,2) CN35PDE(1,2) CN34PDE(1,2) CN33PDE(1,2) CN32PDE(1,2) 0000 — CNPU3 0072 — CN8PDE(3) CN7PDE(1) CN6PDE CN5PDE Bit 4 CNPD2 0058 CN31PDE(1,2) — CN9PDE(1) Bit 8 CNPD1 0056 CN15PDE(1) CNPD3 005A CN11PDE CN10PDE(1,2) Bit 9 CN8PUE(3) CN7PUE(1) CN6PUE CN5PUE — — — — 0000 CN36PUE(1,2) CN35PUE(1,2) CN34PUE(1,2) CN33PUE(1,2) CN32PUE(1,2) 0000 PIC24FV32KA304 FAMILY DS39995D-page 40 File Name Addr INTERRUPT CONTROLLER REGISTER MAP Bit 15 INTCON1 0080 NSTDIS Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 All Resets  2011-2013 Microchip Technology Inc. — — — — — — — — — — STKERR OSCFAIL — 0000 INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 IFS0 0084 NVMIF — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF — OC3IF — — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 IFS2 0088 — — — — — — — — — — IC3IF — — — SPI2IF SPF2IF 0000 IFS3 008A — RTCIF — — — — — — — — — — — MI2C2IF SI2C2IF — 0000 IFS4 008C — — CTMUIF — — — — HLVDIF — — — — CRCIF U2ERIF U1ERIF — 0000 IFS5 008E — — — — — — — — — — — — — — — ULPWUIF 0000 IEC0 0094 NVMIE — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE — OC3IE — — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 IEC2 0098 — — — — — — — — — — IC3IE — — — SPI2IE SPF2IE 0000 IEC3 009A — RTCIE — — — — — — — — — — — MI2C2IE SI2C2IE — 0000 IEC4 009C — — CTMUIE — — — — HLVDIE — — — — CRCIE U2ERIE U1ERIE — 0000 IEC5 009E — — — — — — — — — — — — — — — ULPWUIE 0000 IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444 IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4444 IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 4444 IPC3 00AA — NVMIP2 NVMIP1 NVMIP0 — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 4044 IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0 4444 IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 IPC6 00B0 — T4IP2 T4IP1 T4IP0 — — — — — OC3IP2 OC3IP1 OC3IP0 — — — — 4040 IPC7 00B2 — — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4440 IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 0044 IPC9 00B6 — — — — — — — — — IC3IP2 IC3IP1 IC3IP0 — — — — 0040 IPC12 00BC — — — — — — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440 IPC15 00C2 — — — — — RTCIP2 RTCIP1 RTCIP0 — — — — — — — — 0400 IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — 4440 IPC18 00C8 — — — — — — — — — — — — — HLVDIP2 HLVDIP1 HLVDIP0 0004 IPC19 00CA — — — — — — — — — CTMUIP2 CTMUIP1 CTMUIP0 — — — — 0040 IPC20 00CC — — — — — — — — — — — — — — VHOLD — ILR3 ILR2 ILR1 ILR0 — INTTREG 00E0 CPUIRQ Legend: U2TXIP2 U2TXIP1 U2TXIP0 MI2C2IP2 MI2C2IP1 MI2C2IP0 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. MATHERR ADDRERR Bit 2 VECNUM6 VECNUM5 VECNUM4 VECNUM3 ULPWUIP2 ULPWUIP1 ULPWUIP0 0000 VECNUM2 0000 VECNUM1 VECNUM0 PIC24FV32KA304 FAMILY DS39995D-page 41 TABLE 4-5:  2011-2013 Microchip Technology Inc. TABLE 4-6: File Name TIMER REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TMR1 0100 TMR1 0000 PR1 0102 PR1 FFFF T1CON 0104 TMR2 0106 TON TMR2 0000 TMR3HLD 0108 TMR3HLD 0000 — TSIDL — — — T1ECS1 T1ECS0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 TMR3 010A TMR3 0000 PR2 010C PR2 0000 PR3 010E T2CON 0110 TON — TSIDL — — — — — PR3 — TGATE TCKPS1 TCKPS0 T32 — TCS — FFFF T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 TMR4 0114 TMR4 0000 TMR5HLD 0116 TMR5HLD 0000 FFFF 0118 TMR5 0000 011A PR4 FFFF PR5 011C T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T45 — TCS — 0000 T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets ICOV ICBNE ICM2 ICM1 ICM0 0000 Legend: FFFF — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-7: File Name PR5 INPUT CAPTURE REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 IC1CON1 0140 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 IC1CON2 0142 — — — — — — — IC32 ICTRIG TRIGSTAT — IC1BUF 0144 IC1BUF IC1TMR 0146 IC1TMR IC2CON1 0148 — — ICSIDL IC2CON2 014A — — — IC2TSEL2 IC2TSEL1 IC2TSEL0 — — — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 0000 xxxx — — — ICI1 ICI0 — IC32 ICTRIG TRIGSTAT — ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 0000 000D DS39995D-page 42 IC2BUF 014C IC2BUF IC2TMR 014E IC2TMR IC3CON1 0150 — — ICSIDL IC3CON2 0152 — — — IC3BUF 0154 IC3BUF 0000 IC3TMR 0156 IC3TMR xxxx Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. IC3TSEL2 IC3TSEL1 IC3TSEL0 — — — 0000 xxxx — — — ICI1 ICI0 — IC32 ICTRIG TRIGSTAT — ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 0000 000D PIC24FV32KA304 FAMILY TMR5 PR4 File Name Addr OC1CON1 0190 OUTPUT COMPARE REGISTER MAP Bit 15 Bit 14 Bit 13 — — OCSIDL OC1CON2 0192 FLTMD FLTOUT FLTTRIEN Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 OCINV — DCB1 DCB0 OC32 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C OC1RS 0194 OC1RS 0000 OC1R 0196 OC1R 0000 OC1TMR 0198 OC1TMR OC2CON1 019A — — OCSIDL OC2CON2 019C FLTMD FLTOUT FLTTRIEN OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 OCINV — DCB1 DCB0 OC32 ENFLT0 xxxx OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C OC2RS 019E OC2RS 0000 OC2R 01A0 OC2R 0000 OC2TMR 01A2 OC2TMR OC3CON1 01A4 — — OCSIDL OC3CON2 01A6 FLTMD FLTOUT FLTTRIEN OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 OCINV — DCB1 DCB0 OC32 ENFLT0 xxxx OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C OC3RS 01A8 OC3RS 0000 OC3R 01AA OC3R 0000 OC3TMR 01AC OC3TMR xxxx Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. PIC24FV32KA304 FAMILY DS39995D-page 43 TABLE 4-8:  2011-2013 Microchip Technology Inc.  2011-2013 Microchip Technology Inc. TABLE 4-9: File Name I2Cx REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 I2C1RCV 0200 — — — — — — — — I2CRCV 0000 I2C1TRN 0202 — — — — — — — — I2CTRN 00FF I2C1BRG 0204 — — — — — — — — I2CBRG I2C1CON 0206 I2CEN — A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 I2C1ADD 020A — — — — — — I2C1MSK 020C — — — — — — AMSK9 AMSK8 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 I2C2RCV 0210 — — — — — — — — I2C2TRN 0212 — — — — — — — I2C2BRG 0214 — — — — — — — I2C2CON 0216 I2CEN — A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 I2C2ADD 021A — — — — — — I2C2MSK 021C — — — — — — AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 0000 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets I2CSIDL SCLREL IPMIEN Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0000 I2CADD AMSK7 AMSK6 AMSK5 0000 0000 — I2CTRN 00FF — I2CBRG 0000 I2CADD AMSK9 0000 I2CRCV AMSK8 AMSK7 AMSK6 0000 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-10: File Name Addr UARTx REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 UARTEN — USIDL IREN Bit 11 Bit 10 RTSMD — Bit 9 UEN0 WAKE LPBACK ABAUD RXINV BRGH URXISEL1 URXISEL0 ADDEN RIDLE PERR U1TXREG 0224 — — — — — — — U1RXREG 0226 — — — — — — — U1BRG 0228 U2MODE 0230 U2STA 0232 U2TXREG 0234 — — — — — — — U2RXREG 0236 — — — — — — — U2BRG 0238 UTXBRK UTXEN Bit 6 TRMT 0222 — Bit 7 UEN1 0220 UTXISEL1 UTXINV UTXISEL0 Bit 8 UTXBF U1MODE U1STA DS39995D-page 44 Legend: Bit 6 PDSEL1 PDSEL0 STSEL FERR OERR URXDA — USIDL UTXISEL1 UTXINV UTXISEL0 IREN — RTSMD — UTXBRK UTXEN xxxx U1RXREG 0000 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0000 UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR BRG 0110 U1TXREG BRG UARTEN 0000 PDSEL1 PDSEL0 STSEL FERR OERR URXDA 0000 0110 U2TXREG xxxx U2RXREG 0000 0000 PIC24FV32KA304 FAMILY Legend: I2CSIDL SCLREL IPMIEN Bit 7 All Resets Addr File Name SPIx REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 SPI1STAT 0240 SPIEN — SPISIDL — — SRMPT SPIROV SR1MPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000 SPI1BUF 0248 SPI2STAT 0260 SPIEN — SPISIDL — — SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 SPI2CON2 0264 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000 SPI2BUF Legend: SPI1BUF SPIBEC2 SPIBEC1 SPIBEC0 0268 0000 SPI2BUF 0000 0000 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-12: File Name SPIBEC2 SPIBEC1 SPIBEC0 PORTA REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11(2,3) Bit 10(2,3) Bit 9(2,3) Bit 8(2,3) Bit 7(2) Bit 6(4) Bit 5(1) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 00DF TRISA 02C0 — — — — TRISA11 TRISA10 TRISA9 TRISA8 TRISA7 TRISA6 — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 PORTA 02C2 — — — — RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx LATA 02C4 — — — — LATA11 LATA10 LATA9 LATA8 LATA7 LATA6 — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx 02C6 — — — — ODA11 ODA10 ODA9 ODA8 ODA7 ODA6 — ODA4 ODA3 ODA2 ODA1 ODA0 0000 ODCA Legend: Note 1: 2: 3: 4: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This bit is available only when MCLRE = 1. These bits are not implemented in 20-pin devices. These bits are not implemented in 28-pin devices. These bits are not implemented in FV devices. TABLE 4-13:  2011-2013 Microchip Technology Inc. File Name PORTB REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11(1) Bit 10(1) Bit 9 Bit 8 Bit 7 Bit 6(1) Bit 5(1) Bit 4 Bit 3(1) Bit 2 Bit 1 Bit 0 All Resets TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx ODCB 02CE ODB15 ODB14 ODB13 ODB12 ODB11 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000 Legend: Note 1: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. These bits are not implemented in 20-pin devices. PIC24FV32KA304 FAMILY DS39995D-page 45 TABLE 4-11:  2011-2013 Microchip Technology Inc. TABLE 4-14: PORTC REGISTER MAP(1) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISC 02D0 — — — — — — TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 03FF PORTC 02D2 — — — — — — RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx LATC 02D4 — — — — — — LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx ODCC 02D6 — — — — — — ODC9 ODC8 ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 0000 Legend: Note 1: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. PORTC is not implemented in 20-pin devices or 28-pin devices. TABLE 4-15: File Name PADCFG1 Legend: PAD CONFIGURATION REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 02FC — — — — — — — — — — Bit 5 Bit 4 SMBUSDEL2 SMBUSDEL1 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — — — 0000 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. PIC24FV32KA304 FAMILY DS39995D-page 46 A/D REGISTER MAP All Resets File Name Addr ADC1BUF0 0300 ADC1BUF0 xxxx ADC1BUF1 0302 ADC1BUF1 xxxx ADC1BUF2 0304 ADC1BUF2 xxxx ADC1BUF3 0306 ADC1BUF3 xxxx ADC1BUF4 0308 ADC1BUF4 xxxx ADC1BUF5 030A ADC1BUF5 xxxx ADC1BUF6 030C ADC1BUF6 xxxx ADC1BUF7 030E ADC1BUF7 xxxx ADC1BUF8 0310 ADC1BUF8 xxxx ADC1BUF9 0312 ADC1BUF9 xxxx ADC1BUF10 0314 ADC1BUF10 xxxx ADC1BUF11 0316 ADC1BUF11 xxxx ADC1BUF12 0318 ADC1BUF12 xxxx ADC1BUF13 031A ADC1BUF13 xxxx ADC1BUF14 031C ADC1BUF14 xxxx ADC1BUF15 031E ADC1BUF15 xxxx ADC1BUF16 0320 ADC1BUF16 xxxx ADC1BUF17 0322 ADC1BUF17 AD1CON1 0340 Bit 15 ADON Bit 14 Bit 13 — ADSIDL Bit 12 — Bit 11 — Bit 10 MODE12 Bit 9 FORM1 Bit 8 FORM0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 xxxx SSRC3 SSRC2 SSRC1 SSRC0 — ASAM SAMP DONE 0000  2011-2013 Microchip Technology Inc. AD1CON2 0342 PVCFG1 PVCFG0 NVCFG0 OFFCAL BUFREGEN CSCNA — — BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000 AD1CON3 0344 EXTSAM — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000 AD1CHS 0348 CH0NB2 CH0NB1 CH0NB0 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA2 CH0NA1 CH0NA0 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 AD1CSSH 034E — CSSL30 CSSL29 CSSL28 CSSL27 CSSL26 — — — — — — — — AD1CSSL 0350 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 AD1CON5 0354 ASEN LPEN CTMUREQ BGREQ r — ASINT1 ASINT0 — — — — WM1 AD1CHITH 0356 — — — — — — — — — — — — 0358 CHH15 CHH14 CHH13 CHH12 CHH11 CHH10 CHH9 CHH8 CHH7 CHH6 CHH5 CHH4 AD1CHITL Legend: ADRC — = unimplemented, read as ‘0’; r = reserved. Reset values are shown in hexadecimal. 0000 CSSL17 CSSL16 0000 CSSL2 CSSL1 CSSL0 0000 WM0 CM1 CM0 0000 — — CHH17 CHH16 0000 CHH3 CHH2 CHH1 CHH0 0000 PIC24FV32KA304 FAMILY DS39995D-page 47 TABLE 4-16:  2011-2013 Microchip Technology Inc. TABLE 4-17: CTMU REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets CTMUCON1 035A CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG — — — — — — — — 0000 CTMUCON2 035C EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT EDG2EMOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — 0000 CTMUICON 035E — — 0000 File Name AD1CTMUENH 0360 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 — — — — — — — — — — — — — — — — — — — — CTMEN12 CTMEN11 CTMEN10 CTMEN9 CTMEN8 CTMEN7 CTMEN6 CTMEN5 CTMEN4 CTMEN3 CTMEN2 AD1CTMUENL 0362 CTMEN15 CTMEN14 CTMEN13 Legend: Addr ANSA 04E0 ANSB 04E2 ANSC 04E4 ALRMVAL ANALOG SELECT REGISTER MAP Bit 15 Bit 14 — — ANSB15 ANSB14 — — Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 000F — — — — — — — — — — ANSA3 ANSA2 ANSA1 ANSA0 ANSB13 ANSB12 — — — — — — — ANSB4 ANSB3(1) ANSB2 ANSB1 ANSB0 — — — — — — — — — — — ANSC2(1,2) ANSC1(1,2) ANSC0(1,2) Addr REAL-TIME CLOCK AND CALENDAR REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 0620 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 Bit 0 ALRMVAL ALCFGRPT 0622 ALRMEN ARPT1 ARPT0 0624 RCFGCAL 0626 RTCEN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 RTCPWC 0628 PWCEN PWCPOL PWCCPRE PWCSPRE RTCCLK1 RTCCLK0 RTCOUT1 RTCOUT0 — — — — — — — — RTCWREN 0000 xxxx 0000 xxxx — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-20: File Name RTCVAL — All Resets xxxx ALRMPTR0 RTCVAL Legend: F01F 0007 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. These bits are not implemented in 20-pin devices. These bits are not implemented in 28-pin devices. TABLE 4-19: File Name 0000 CTMEN0 TRIPLE COMPARATOR REGISTER MAP DS39995D-page 48 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 CMSTAT 0630 CMIDL — — — — C3EVT C2EVT C1EVT — CVRCON 0632 — — — — — — — — CVREN CVROE CVRSS — — Bit 4 All Resets Bit 3 Bit 2 Bit 1 Bit 0 — — C3OUT C2OUT C1OUT xxxx CVR4 CVR3 CVR2 CVR1 CVR0 0000 CM1CON 0634 CON COE CPOL CLPWR — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 xxxx CM2CON 0636 CON COE CPOL CLPWR — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 CM3CON 0638 CON COE CPOL CLPWR — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. PIC24FV32KA304 FAMILY Legend: Note 1: 2: 0000 CTMEN1 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-18: File Name CTMEN17 CTMEN16 File Name CRC REGISTER MAP Addr Bit 15 Bit 14 Bit 13 CRCCON1 0640 CRCEN — CSIDL CRCCON2 0642 — — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 — — — PLEN4 PLEN3 Bit 1 Bit 0 All Resets — — — 0000 PLEN2 PLEN1 PLEN0 0000 0000 CRCXORL 0644 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 — CRCXORH 0646 X31 X30 X29 X28 X27 X26 X25 X24 X23 X22 X21 X20 X19 X18 X17 X16 CRCDATL 0648 0000 CRCDATL xxxx xxxx CRCDATH 064A CRCDATH CRCWDATL 064C CRCWDATL xxxx CRCWDATH 064E CRCWDATH xxxx Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-22: File Name CLOCK CONTROL REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 11 Bit 10 Bit 9 CM RCON 0740 TRAPR RETEN — DPSLP OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN OSCTUN 0748 — — — — — REFOCON 074E ROEN — ROSSLP ROSEL HLVDCON 0756 HLVDEN — HLSIDL — Legend: Note 1: 2: Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PMSLP EXTR SWR SWDTEN WDTO SLEEP IDLE BOR — LOCK — CF SOSCDRV SOSCEN NOSC0 CLKLOCK RCDIV2 RCDIV1 RCDIV0 — — — RODIV3 RODIV2 RODIV1 RODIV0 — — — — Bit 2 Bit 1 Bit 0 All Resets POR (Note 1) OSWEN (Note 2) — — — — — — — — 3140 — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 — — — — — — — — 0000 VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 0000 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. RCON register Reset values are dependent on the type of Reset. OSCCON register Reset values are dependent on the Configuration Fuses and by type of Reset. TABLE 4-23:  2011-2013 Microchip Technology Inc. File Name IOPUWR SBOREN Bit 12 DEEP SLEEP REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 DSCON 0758 DSEN — — — — — — DSWAKE 075A — — — — — — — DSGPR0(1) 075C DSGPR0 0000 DSGPR1(1) 075E DSGPR1 0000 Legend: Note 1: Bit 7 Bit 6 Bit 5 RTCCWDIS — — — DSINT0 DSFLT — — — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. The Deep Sleep registers, DSGPR0 and DSGPR1, are only reset on a VDD POR event. Bit 4 All Resets Addr Bit 3 Bit 2 Bit 1 Bit 0 — ULPWDIS DSBOR RELEASE 0000 DSMCLR — DSPOR 0000 DSWDT DSRTCC PIC24FV32KA304 FAMILY DS39995D-page 49 TABLE 4-21:  2011-2013 Microchip Technology Inc. TABLE 4-24: File Name NVM REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 NVMCON 0760 WR WREN WRERR PGMONLY — — — — — ERASE NVMOP5 NVMKEY 0766 — — — — — — — — Legend: Note 1: ULPWCON Legend: Bit 2 Bit 1 Bit 0 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0 NVMKEY All Resets(1) 0000 0000 ULTRA LOW-POWER WAKE-UP REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0768 ULPEN — ULPSIDL — — — — ULPSINK — — — — — — — — 0000 Bit 2 Bit 1 Bit 0 All Resets 0000 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-26: PMD REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PMD1 0770 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADC1MD PMD2 0772 — — — — — IC3MD IC2MD IC1MD — — — — — OC3MD OC2MD OC1MD 0000 PMD3 0774 — — — — — CMPMD RTCCMD — CRCPMD — — — — — I2C2MD — 0000 0776 — — — — — — — — ULPWUMD — — EEMD REFOMD CTMUMD HLVDMD — 0000 PMD4 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS39995D-page 50 PIC24FV32KA304 FAMILY File Name Bit 3 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset value shown is for POR only. The value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. TABLE 4-25: File Name Bit 4 PIC24FV32KA304 FAMILY 4.2.5 4.3 SOFTWARE STACK In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. The Stack Pointer Limit Value (SPLIM) register, associated with the Stack Pointer, sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM is forced to ‘0’ as all stack operations must be word-aligned. Whenever an EA is generated, using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal, and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address, 0DF6 in RAM, initialize the SPLIM with the value, 0DF4. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0800h. This prevents the stack from interfering with the Special Function Register (SFR) space. Note: A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. FIGURE 4-4: Stack Grows Towards Higher Address 0000h CALL STACK FRAME 15 0 PC W15 (before CALL) 000000000 PC W15 (after CALL) POP : [--W15] PUSH : [W15++] DS39995D-page 51 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Apart from the normal execution, the PIC24F architecture provides two methods by which the program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • Remapping a portion of the program space into the data space, PSV Table instructions allow an application to read or write small areas of the program memory. This makes the method ideal for accessing data tables that need to be updated from time to time. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. It can only access the least significant word (lsw) of the program word. 4.3.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Memory Page Address register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit (MSb) of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG = 0) or the configuration memory (TBLPAG = 1). For remapping operations, the 8-bit Program Space Visibility Page Address register (PSVPAG) is used to define a 16K word page in the program space. When the MSb of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike the table operations, this limits remapping operations strictly to the user memory area. Table 4-27 and Figure 4-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, the P bits refer to a program space word, whereas the D bits refer to a data space word.  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TABLE 4-27: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space Access Type Program Space Address Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG Data EA 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG Data EA 1xxx xxxx xxxx xxxx xxxx xxxx 2: 0 0xx xxxx xxxx xxxx xxxx xxx0 Program Space Visibility (Block Remap/Read) Note 1: PC 0 User 0 PSVPAG(2) Data EA(1) 0 xxxx xxxx xxx xxxx xxxx xxxx Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG. PSVPAG can have only two values (‘00’ to access program memory and FF to access data EEPROM) in the PIC24FV32KA304 family. FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) Program Counter 0 0 23 Bits EA 1/0 Table Operations(2) 1/0 TBLPAG 8 Bits 16 Bits 24 Bits Select EA 1 0 (1) Program Space Visibility (Remapping) 0 PSVPAG 8 Bits 15 Bits 23 Bits User/Configuration Space Select Note 1: 2: Byte Select The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space.  2011-2013 Microchip Technology Inc. DS39995D-page 52 PIC24FV32KA304 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY AND DATA EEPROM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program memory without going through data space. It also offers a direct method of reading or writing a word of any address within data EEPROM memory. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. Note: The TBLRDH and TBLWTH instructions are not used while accessing data EEPROM memory. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word-wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word, and TBLRDH and TBLWTH access the space which contains the upper data byte. DS39995D-page 53 Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. 1. TBLRDL (Table Read Low): In Word mode, it maps the lower word of the program space location (P) to a data address (D). In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is ‘1’; the lower byte is selected when it is ‘0’. 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P) to a data address. Note that D, the ‘phantom’ byte, will always be ‘0’. In Byte mode, it maps the upper or lower byte of the program word to D of the data address, as above. Note that the data will always be ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1).  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “Flash Program Memory”. TBLPAG = 0, the table page is located in the user memory space. When TBLPAG = 1, the page is located in configuration space. Note: For all table operations, the area of program memory space to be accessed is determined by the Table Memory Page Address register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When FIGURE 4-6: Only Table Read operations will execute in the configuration memory space, and only then, in implemented areas, such as the Device ID. Table write operations are not allowed. ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space Data EA TBLPAG 23 00 23 15 0 000000h 16 8 0 00000000 00000000 00000000 002BFEh 00000000 ‘Phantom’ Byte TBLRDH.B (Wn = 0) TBLRDL.B (Wn = 1) TBLRDL.B (Wn = 0) TBLRDL.W 800000h  2011-2013 Microchip Technology Inc. The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are provided; write operations are also valid in the user memory area. DS39995D-page 54 PIC24FV32KA304 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into a 16K word page (in PIC24FV16KA3XX devices) and a 32K word page (in PIC24FV32KA3XX devices) of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the data space occurs if the MSb of the data space EA is ‘1’ and PSV is enabled by setting the PSV bit in the CPU Control (CORCON) register. The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page Address (PSVPAG) register. This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads from this area add an additional cycle to the instruction being executed, since two program memory fetches are required. FIGURE 4-7: Although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see Figure 4-7), only the lower 16 bits of the 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions will require one instruction cycle in addition to the specified execution time. All other instructions will require two instruction cycles in addition to the specified execution time. For operations that use PSV, which are executed inside a REPEAT loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction: • Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle. PROGRAM SPACE VISIBILITY OPERATION When CORCON = 1 and EA = 1: Program Space PSVPAG 00 23 15 Data Space 0 000000h 0000h Data EA 002BFEh The data in the page designated by PSVPAG is mapped into the upper half of the data memory space.... 8000h PSV Area ...while the lower 15 bits of the EA specify an exact address within the PSV FFFFh area. This corresponds exactly to the same lower 15 bits of the actual program space address. 800000h  2011-2013 Microchip Technology Inc. DS39995D-page 55 PIC24FV32KA304 FAMILY NOTES: DS39995D-page 56  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 5.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Flash programming, refer to the “PIC24F Family Reference Manual”, Section 4. “Program Memory” (DS39715). The PIC24FV32KA304 family of devices contains internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable when operating with VDD over 1.8V. Flash memory can be programmed in three ways: • In-Circuit Serial Programming™ (ICSP™) • Run-Time Self Programming (RTSP) • Enhanced In-Circuit Serial Programming (Enhanced ICSP) ICSP allows a PIC24FV32KA304 device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (which are named PGECx and PGEDx, respectively), and three other lines for power (VDD), ground (VSS) and Master Clear/Program mode Entry Voltage (MCLR/VPP). This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or custom firmware to be programmed. FIGURE 5-1: Run-Time Self Programming (RTSP) is accomplished using TBLRD (Table Read) and TBLWT (Table Write) instructions. With RTSP, the user may write program memory data in blocks of 32 instructions (96 bytes) at a time, and erase program memory in blocks of 32, 64 and 128 instructions (96,192 and 384 bytes) at a time. The NVMOP (NVMCON) bits decide the erase block size. 5.1 Table Instructions and Flash Programming Regardless of the method used, Flash memory programming is done with the table read and write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using the TBLPAG bits and the Effective Address (EA) from a W register, specified in the table instruction, as depicted in Figure 5-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. ADDRESSING FOR TABLE REGISTERS 24 Bits Using Program Counter Program Counter 0 0 Working Reg EA Using Table Instruction User/Configuration Space Select  2011-2013 Microchip Technology Inc. 1/0 TBLPAG Reg 8 Bits 16 Bits 24-Bit EA Byte Select DS39995D-page 57 PIC24FV32KA304 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 32 instructions or 96 bytes. RTSP allows the user to erase blocks of 1 row, 2 rows and 4 rows (32, 64 and 128 instructions) at a time, and to program one row at a time. It is also possible to program single words. The 1-row (96 bytes), 2-row (192 bytes) and 4-row (384 bytes) erase blocks, and single row write block (96 bytes) are edge-aligned from the beginning of program memory. When data is written to program memory using TBLWT instructions, the data is not written directly to memory. Instead, data written using table writes is stored in holding latches until the programming sequence is executed. Any number of TBLWT instructions can be executed and a write will be successfully performed. However, 32 TBLWT instructions are required to write the full row of memory. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. Data can be loaded in any order and the holding registers can be written to multiple times before performing a write operation. Subsequent writes, however, will wipe out any previous writes. Note: Writing to a location multiple times without erasing it is not recommended. 5.3 Enhanced In-Circuit Serial Programming Enhanced ICSP uses an on-board bootloader, known as the Programming Executive (PE), to manage the programming process. Using an SPI data frame format, the Programming Executive can erase, program and verify program memory. For more information on Enhanced ICSP, see the device programming specification. 5.4 Control Registers There are two SFRs used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 5-1) controls the blocks that need to be erased, which memory type is to be programmed and when the programming cycle starts. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the NVMKEY register. For more information, refer to Section 5.5 “Programming Operations”. 5.5 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. During a program or erase operation, the processor stalls (Waits) until the operation is finished. Setting the WR bit (NVMCON) starts the operation and the WR bit is automatically cleared when the operation is finished. All of the table write operations are single-word writes (two instruction cycles), because only the buffers are written. A programming cycle is required for programming each row. DS39995D-page 58  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY(4) — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ERASE NVMOP5(1) NVMOP4(1) NVMOP3(1) NVMOP2(1) NVMOP1(1) NVMOP0(1) bit 7 bit 0 Legend: SO = Settable Only bit HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit is set R = Readable bit ‘0’ = Bit is cleared x = Bit is unknown U = Unimplemented bit, read as ‘0’ W = Writable bit bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once the operation is complete. 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit 1 = Enables Flash program/erase operations 0 = Inhibits Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt, or termination, has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12 PGMONLY: Program Only Enable bit(4) bit 11-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit 1 = Performs the erase operation specified by NVMOP on the next WR command 0 = Performs the program operation specified by NVMOP on the next WR command bit 5-0 NVMOP: Programming Operation Command Byte bits(1) Erase Operations (when ERASE bit is ‘1’): 1010xx = Erases entire boot block (including code-protected boot block)(2) 1001xx = Erases entire memory (including boot block, configuration block, general block)(2) 011010 = Erases 4 rows of Flash memory(3) 011001 = Erases 2 rows of Flash memory(3) 011000 = Erases 1 row of Flash memory(3) 0101xx = Erases entire configuration block (except code protection bits) 0100xx = Erases entire data EEPROM(4) 0011xx = Erases entire general memory block programming operations 0001xx = Writes 1 row of Flash memory (when ERASE bit is ‘0’)(3) Note 1: 2: 3: 4: All other combinations of NVMOP are no operation. These values are available in ICSP™ mode only. Refer to the device programming specification. The address in the Table Pointer decides which rows will be erased. This bit is used only while accessing data EEPROM.  2011-2013 Microchip Technology Inc. DS39995D-page 59 PIC24FV32KA304 FAMILY 5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of Flash program memory at a time by erasing the programmable row. The general process is as follows: 1. 2. 3. Read a row of program memory (32 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase a row (see Example 5-1): a) Set the NVMOPx bits (NVMCON) to ‘011000’ to configure for row erase. Set the ERASE (NVMCON) and WREN (NVMCON) bits. b) Write the starting address of the block to be erased into the TBLPAG and W registers. c) Write 55h to NVMKEY. d) Write AAh to NVMKEY. e) Set the WR bit (NVMCON). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. EXAMPLE 5-1: DS39995D-page 60 For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 5-5. ERASING A PROGRAM MEMORY ROW – ASSEMBLY LANGUAGE CODE ; Set up NVMCON for row erase operation MOV #0x4058, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP Write the first 32 instructions from data RAM into the program memory buffers (see Example 5-1). Write the program block to Flash memory: a) Set the NVMOPx bits to ‘011000’ to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 55h to NVMKEY. c) Write AAh to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR ; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts for next 5 instructions Write the 55 key Write the AA key Start the erase sequence Insert two NOPs after the erase command is asserted  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY EXAMPLE 5-2: ERASING A PROGRAM MEMORY ROW – ‘C’ LANGUAGE CODE // C example using MPLAB C30 int __attribute__ ((space(auto_psv))) progAddr = 0x1234; // Global variable located in Pgm Memory unsigned int offset; //Set up pointer to the first memory location to be written TBLPAG = __builtin_tblpage(&progAddr); offset = __builtin_tbloffset(&progAddr); // Initialize PM Page Boundary SFR // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4058; // Initialize NVMCON asm("DISI #5"); // // // // __builtin_write_NVM(); EXAMPLE 5-3: Block all interrupts for next 5 instructions C30 function to perform unlock sequence and set WR LOADING THE WRITE BUFFERS – ASSEMBLY LANGUAGE CODE ; Set up NVMCON for row programming operations MOV #0x4004, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] ; Write PM high byte into program latch TBLWTH W3, [W0++] • • • ; 32nd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] TBLWTH W3, [W0] ; Write PM high byte into program latch  2011-2013 Microchip Technology Inc. DS39995D-page 61 PIC24FV32KA304 FAMILY EXAMPLE 5-4: LOADING THE WRITE BUFFERS – ‘C’ LANGUAGE CODE // C example using MPLAB C30 #define NUM_INSTRUCTION_PER_ROW 64 int __attribute__ ((space(auto_psv))) progAddr = 0x1234; // Global variable located in Pgm Memory unsigned int offset; unsigned int i; unsigned int progData[2*NUM_INSTRUCTION_PER_ROW]; // Buffer of data to write //Set up NVMCON for row programming NVMCON = 0x4001; // Initialize NVMCON //Set up pointer to the first memory location to be written TBLPAG = __builtin_tblpage(&progAddr); // Initialize PM Page Boundary SFR offset = __builtin_tbloffset(&progAddr); // Initialize lower word of address //Perform TBLWT instructions to write necessary number of latches for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++) { __builtin_tblwtl(offset, progData[i++]); // Write to address low word __builtin_tblwth(offset, progData[i]); // Write to upper byte offset = offset + 2; // Increment address } EXAMPLE 5-5: INITIATING A PROGRAMMING SEQUENCE – ASSEMBLY LANGUAGE CODE DISI #5 MOV MOV MOV MOV BSET NOP NOP BTSC BRA #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR EXAMPLE 5-6: ; Block all interrupts for next 5 instructions NVMCON, #15 $-2 ; ; ; ; ; ; ; ; Write the 55 key Write the AA key Start the erase sequence 2 NOPs required after setting WR Wait for the sequence to be completed INITIATING A PROGRAMMING SEQUENCE – ‘C’ LANGUAGE CODE // C example using MPLAB C30 asm("DISI #5"); // Block all interrupts for next 5 instructions __builtin_write_NVM(); // Perform unlock sequence and set WR DS39995D-page 62  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 6.0 Note: DATA EEPROM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Data EEPROM, refer to the “PIC24F Family Reference Manual”, Section 5. “Data EEPROM” (DS39720). The data EEPROM memory is a Nonvolatile Memory (NVM), separate from the program and volatile data RAM. Data EEPROM memory is based on the same Flash technology as program memory, and is optimized for both long retention and a higher number of erase/write cycles. The data EEPROM is mapped to the top of the user program memory space, with the top address at program memory address, 7FFE00h to 7FFFFFh. The size of the data EEPROM is 256 words in the PIC24FV32KA304 family devices. The data EEPROM is organized as 16-bit wide memory. Each word is directly addressable, and is readable and writable during normal operation over the entire VDD range. Unlike the Flash program memory, normal program execution is not stopped during a data EEPROM program or erase operation. The data EEPROM programming operations are controlled using the three NVM Control registers: • NVMCON: Nonvolatile Memory Control Register • NVMKEY: Nonvolatile Memory Key Register • NVMADR: Nonvolatile Memory Address Register EXAMPLE 6-1: 6.1 NVMCON Register The NVMCON register (Register 6-1) is also the primary control register for data EEPROM program/erase operations. The upper byte contains the control bits used to start the program or erase cycle, and the flag bit to indicate if the operation was successfully performed. The lower byte of NVMCOM configures the type of NVM operation that will be performed. 6.2 NVMKEY Register The NVMKEY is a write-only register that is used to prevent accidental writes or erasures of data EEPROM locations. To start any programming or erase sequence, the following instructions must be executed first, in the exact order provided: 1. 2. Write 55h to NVMKEY. Write AAh to NVMKEY. After this sequence, a write will be allowed to the NVMCON register for one instruction cycle. In most cases, the user will simply need to set the WR bit in the NVMCON register to start the program or erase cycle. Interrupts should be disabled during the unlock sequence. The MPLAB® C30 C compiler provides a defined library procedure (builtin_write_NVM) to perform the unlock sequence. Example 6-1 illustrates how the unlock sequence can be performed with in-line assembly. DATA EEPROM UNLOCK SEQUENCE //Disable Interrupts For 5 instructions asm volatile ("disi #5"); //Issue Unlock Sequence asm volatile ("mov #0x55, W0 \n" "mov W0, NVMKEY \n" "mov #0xAA, W1 \n" "mov W1, NVMKEY \n"); // Perform Write/Erase operations asm volatile ("bset NVMCON, #WR \n" "nop \n" "nop \n");  2011-2013 Microchip Technology Inc. DS39995D-page 63 PIC24FV32KA304 FAMILY REGISTER 6-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER R/S-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ERASE NVMOP5 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0 bit 7 bit 0 Legend: HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit S = Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit (program or erase) 1 = Initiates a data EEPROM erase or write cycle (can be set, but not cleared in software) 0 = Write cycle is complete (cleared automatically by hardware) bit 14 WREN: Write Enable bit (erase or program) 1 = Enables an erase or program operation 0 = No operation allowed (device clears this bit on completion of the write/erase operation) bit 13 WRERR: Write Flash Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or WDT Reset during programming operation) 0 = The write operation completed successfully bit 12 PGMONLY: Program Only Enable bit 1 = Write operation is executed without erasing target address(es) first 0 = Automatic erase-before-write Write operations are preceded automatically by an erase of the target address(es). bit 11-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase Operation Select bit 1 = Performs an erase operation when WR is set 0 = Performs a write operation when WR is set bit 5-0 NVMOP: Programming Operation Command Byte bits Erase Operations (when ERASE bit is ‘1’): 011010 = Erases 8 words 011001 = Erases 4 words 011000 = Erases 1 word 0100xx = Erases entire data EEPROM Programming Operations (when ERASE bit is ‘0’): 0010xx = Writes 1 word DS39995D-page 64  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 6.3 NVM Address Register 6.4 As with Flash program memory, the NVM Address registers, NVMADRU and NVMADR, form the 24-bit Effective Address (EA) of the selected row or word for data EEPROM operations. The NVMADRU register is used to hold the upper 8 bits of the EA, while the NVMADR register is used to hold the lower 16 bits of the EA. These registers are not mapped into the Special Function Register (SFR) space. Instead, they directly capture the EA of the last table write instruction that has been executed and selects the data EEPROM row to erase. Figure 6-1 depicts the program memory EA that is formed for programming and erase operations. Like program memory operations, the Least Significant bit (LSb) of NVMADR is restricted to even addresses. This is because any given address in the data EEPROM space consists of only the lower word of the program memory width; the upper word, including the uppermost “phantom byte”, are unavailable. This means that the LSb of a data EEPROM address will always be ‘0’. Similarly, the Most Significant bit (MSb) of NVMADRU is always ‘0’, since all addresses lie in the user program space. FIGURE 6-1: DATA EEPROM ADDRESSING WITH TBLPAG AND NVM ADDRESS REGISTERS Data EEPROM Operations The EEPROM block is accessed using table read and write operations similar to those used for program memory. The TBLWTH and TBLRDH instructions are not required for data EEPROM operations since the memory is only 16 bits wide (data on the lower address is valid only). The following programming operations can be performed on the data EEPROM: • • • • Erase one, four or eight words Bulk erase the entire data EEPROM Write one word Read one word Note 1: Unexpected results will be obtained if the user attempts to read the EEPROM while a programming or erase operation is underway. 2: The C30 C compiler includes library procedures to automatically perform the table read and table write operations, manage the Table Pointer and write buffers, and unlock and initiate memory write sequences. This eliminates the need to create assembler macros or time critical routines in C for each application. The library procedures are used in the code examples detailed in the following sections. General descriptions of each process are provided for users who are not using the C30 compiler libraries. 24-Bit PM Address 0 7Fh xxxxh TBLPAG W Register EA NVMADRU NVMADR  2011-2013 Microchip Technology Inc. 0 DS39995D-page 65 PIC24FV32KA304 FAMILY 6.4.1 ERASE DATA EEPROM The data EEPROM can be fully erased, or can be partially erased, at three different sizes: one word, four words or eight words. The bits, NVMOP (NVMCON), decide the number of words to be erased. To erase partially from the data EEPROM, the following sequence must be followed: 1. 2. 3. 4. 5. 6. Configure NVMCON to erase the required number of words: one, four or eight. Load TBLPAG and WREG with the EEPROM address to be erased. Clear the NVMIF status bit and enable the NVM interrupt (optional). Write the key sequence to NVMKEY. Set the WR bit to begin the erase cycle. Either poll the WR bit or wait for the NVM interrupt (NVMIF is set). EXAMPLE 6-2: A typical erase sequence is provided in Example 6-2. This example shows how to do a one-word erase. Similarly, a four-word erase and an eight-word erase can be done. This example uses C library procedures to manage the Table Pointer (builtin_tblpage and builtin_tbloffset) and the Erase Page Pointer (builtin_tblwtl). The memory unlock sequence (builtin_write_NVM) also sets the WR bit to initiate the operation and returns control when complete. SINGLE-WORD ERASE int __attribute__ ((space(eedata))) eeData = 0x1234; /*-------------------------------------------------------------------------------------------The variable eeData must be a Global variable declared outside of any method the code following this comment can be written inside the method that will execute the erase ---------------------------------------------------------------------------------------------*/ unsigned int offset; // Set up NVMCON to erase one word of data EEPROM NVMCON = 0x4058; // Set up a pointer to the EEPROM location to be erased TBLPAG = __builtin_tblpage(&eeData); // Initialize EE Data page pointer offset = __builtin_tbloffset(&eeData); // Initizlize lower word of address __builtin_tblwtl(offset, 0); // Write EEPROM data to write latch asm volatile ("disi #5"); __builtin_write_NVM(); while(NVMCONbits.WR=1); DS39995D-page 66 // // // // Disable Interrupts For 5 Instructions Issue Unlock Sequence & Start Write Cycle Optional: Poll WR bit to wait for write sequence to complete  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 6.4.1.1 Data EEPROM Bulk Erase 6.4.2 SINGLE-WORD WRITE To erase the entire data EEPROM (bulk erase), the address registers do not need to be configured because this operation affects the entire data EEPROM. The following sequence helps in performing a bulk erase: To write a single word in the data EEPROM, the following sequence must be followed: 1. 2. 2. 3. 4. 5. Configure NVMCON to Bulk Erase mode. Clear the NVMIF status bit and enable the NVM interrupt (optional). Write the key sequence to NVMKEY. Set the WR bit to begin the erase cycle. Either poll the WR bit or wait for the NVM interrupt (NVMIF is set). 1. 3. A typical bulk erase sequence is provided in Example 6-3. Erase one data EEPROM word (as mentioned in the previous section) if the PGMONLY bit (NVMCON) is set to ‘1’. Write the data word into the data EEPROM latch. Program the data word into the EEPROM: - Configure the NVMCON register to program one EEPROM word (NVMCON = 0001xx). - Clear the NVMIF status bit and enable the NVM interrupt (optional). - Write the key sequence to NVMKEY. - Set the WR bit to begin the erase cycle. - Either poll the WR bit or wait for the NVM interrupt (NVMIF is set). - To get cleared, wait until NVMIF is set. A typical single-word write sequence is provided in Example 6-4. EXAMPLE 6-3: DATA EEPROM BULK ERASE // Set up NVMCON to bulk erase the data EEPROM NVMCON = 0x4050; // Disable Interrupts For 5 Instructions asm volatile ("disi #5"); // Issue Unlock Sequence and Start Erase Cycle __builtin_write_NVM(); EXAMPLE 6-4: SINGLE-WORD WRITE TO DATA EEPROM int __attribute__ ((space(eedata))) eeData = 0x1234; int newData; // New data to write to EEPROM /*--------------------------------------------------------------------------------------------The variable eeData must be a Global variable declared outside of any method the code following this comment can be written inside the method that will execute the write ----------------------------------------------------------------------------------------------*/ unsigned int offset; // Set up NVMCON to erase one word of data EEPROM NVMCON = 0x4004; // Set up a pointer to the EEPROM location to be erased TBLPAG = __builtin_tblpage(&eeData); // Initialize EE Data page pointer offset = __builtin_tbloffset(&eeData); // Initizlize lower word of address __builtin_tblwtl(offset, newData); // Write EEPROM data to write latch asm volatile ("disi #5"); __builtin_write_NVM(); while(NVMCONbits.WR=1);  2011-2013 Microchip Technology Inc. // // // // Disable Interrupts For 5 Instructions Issue Unlock Sequence & Start Write Cycle Optional: Poll WR bit to wait for write sequence to complete DS39995D-page 67 PIC24FV32KA304 FAMILY 6.4.3 READING THE DATA EEPROM To read a word from data EEPROM, the table read instruction is used. Since the EEPROM array is only 16 bits wide, only the TBLRDL instruction is needed. The read operation is performed by loading TBLPAG and WREG with the address of the EEPROM location, followed by a TBLRDL instruction. EXAMPLE 6-5: A typical read sequence, using the Table Pointer management (builtin_tblpage and builtin_tbloffset) and table read procedures (builtin_tblrdl) from the C30 compiler library, is provided in Example 6-5. Program Space Visibility (PSV) can also be used to read locations in the data EEPROM. READING THE DATA EEPROM USING THE TBLRD COMMAND int __attribute__ ((space(eedata))) eeData = 0x1234; int data; // Data read from EEPROM /*-------------------------------------------------------------------------------------------The variable eeData must be a Global variable declared outside of any method the code following this comment can be written inside the method that will execute the read ---------------------------------------------------------------------------------------------*/ unsigned int offset; // Set TBLPAG offset data = up a pointer to the EEPROM location to be erased = __builtin_tblpage(&eeData); // Initialize EE Data page pointer = __builtin_tbloffset(&eeData); // Initizlize lower word of address __builtin_tblrdl(offset); // Write EEPROM data to write latch DS39995D-page 68  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 7.0 RESETS Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Resets, refer to the “PIC24F Family Reference Manual”, Section 40. “Reset with Programmable Brown-out Reset” (DS39728). The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: • • • • • • • • • POR: Power-on Reset MCLR: Pin Reset SWR: RESET Instruction WDTR: Watchdog Timer Reset BOR: Brown-out Reset Low-Power BOR/Deep Sleep BOR TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode Reset UWR: Uninitialized W Register Reset Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on Power-on Reset (POR) and unchanged by all other Resets. Note: All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 7-1). A Power-on Reset will clear all bits except for the BOR and POR bits (RCON) which are set. The user may set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer (WDT) and device power-saving states. The function of these bits is discussed in other sections of this manual. A simplified block diagram of the Reset module is shown in Figure 7-1. FIGURE 7-1: Refer to the specific peripheral or Section 3.0 “CPU” of this data sheet for register Reset states. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle BOREN 0 SBOREN (RCON) SLEEP 00 1 11 POR Brown-out Reset BOR SYSRST VDD 01 10 VDD Rise Detect Enable Voltage Regulator (PIC24FV32KA3XX only) Configuration Mismatch Trap Conflict Illegal Opcode Uninitialized W Register  2011-2013 Microchip Technology Inc. DS39995D-page 69 PIC24FV32KA304 FAMILY RCON: RESET CONTROL REGISTER(1) REGISTER 7-1: R/W-0, HS TRAPR R/W-0, HS IOPUWR R/W-0 R/W-0 SBOREN RETEN (3) U-0 R/C-0, HS R/W-0 R/W-0 — DPSLP CM PMSLP bit 15 bit 8 R/W-0, HS R/W-0, HS EXTR SWR R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS WDTO SLEEP IDLE BOR POR (2) SWDTEN bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or Uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or Uninitialized W Reset has not occurred bit 13 SBOREN: Software Enable/Disable of BOR bit 1 = BOR is turned on in software 0 = BOR is turned off in software bit 12 RETEN: Retention Sleep Mode control bit(3) 1 = Regulated voltage supply provided solely by the Retention Regulator (RETEN) during Sleep 0 = Regulated voltage supply provided by the main Voltage Regulator (VREG) during Sleep bit 11 Unimplemented: Read as ‘0’ bit 10 DPSLP: Deep Sleep Mode Flag bit 1 = Deep Sleep has occurred 0 = Deep Sleep has not occurred bit 9 CM: Configuration Word Mismatch Reset Flag bit 1 = A Configuration Word Mismatch Reset has occurred 0 = A Configuration Word Mismatch Reset has not occurred bit 8 PMSLP: Program Memory Power During Sleep bit 1 = Program memory bias voltage remains powered during Sleep 0 = Program memory bias voltage is powered down during Sleep and the Voltage Regulator enters Standby mode bit 7 EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed Note 1: 2: 3: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTENx Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled regardless of the SWDTEN bit setting. This is implemented on PIC24FV32KA3XX parts only; not used on PIC24F32KA3XX devices. DS39995D-page 70  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY RCON: RESET CONTROL REGISTER(1) (CONTINUED) REGISTER 7-1: bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred (the BOR is also set after a POR) 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred Note 1: 2: 3: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTENx Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled regardless of the SWDTEN bit setting. This is implemented on PIC24FV32KA3XX parts only; not used on PIC24F32KA3XX devices. TABLE 7-1: RESET FLAG BIT OPERATION Flag Bit TRAPR (RCON) Setting Event Clearing Event Trap Conflict Event POR IOPUWR (RCON) Illegal Opcode or Uninitialized W Register Access POR CM (RCON) Configuration Mismatch Reset POR EXTR (RCON) MCLR Reset POR SWR (RCON) RESET Instruction POR WDTO (RCON) WDT Time-out SLEEP (RCON) PWRSAV #SLEEP Instruction POR IDLE (RCON) PWRSAV #IDLE Instruction POR BOR (RCON) POR, BOR POR (RCON) POR DPSLP (RCON) PWRSAV #SLEEP Instruction with DSEN (DSCON) Set Note: PWRSAV Instruction, POR — — POR All Reset flag bits may be set or cleared by the user software.  2011-2013 Microchip Technology Inc. DS39995D-page 71 PIC24FV32KA304 FAMILY 7.1 Clock Source Selection at Reset If clock switching is enabled, the system clock source at device Reset is chosen, as shown in Table 7-2. If clock switching is disabled, the system clock source is always selected according to the Oscillator Configuration bits. For more information, see Section 9.0 “Oscillator Configuration”. TABLE 7-2: OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED) Reset Type POR Clock Source Determinant FNOSCx Configuration bits (FNOSC) BOR MCLR 7.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 7-3. Note that the System Reset Signal, SYSRST, is released after the POR and PWRT delay times expire. The time at which the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released. COSCx Control bits (OSCCON) WDTO SWR TABLE 7-3: DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type POR(6) BOR Clock Source Note 1: 2: 3: 4: 5: 6: Note: System Clock Delay Notes EC TPOR + TPWRT — FRC, FRCDIV TPOR + TPWRT TFRC 1, 2, 3 LPRC TPOR + TPWRT TLPRC 1, 2, 3 ECPLL TPOR + TPWRT TLOCK 1, 2, 4 FRCPLL TPOR + TPWRT TFRC + TLOCK XT, HS, SOSC TPOR+ TPWRT TOST XTPLL, HSPLL TPOR + TPWRT TOST + TLOCK TPWRT — EC All Others SYSRST Delay 1, 2 1, 2, 3, 4 1, 2, 5 1, 2, 4, 5 2 FRC, FRCDIV TPWRT TFRC 2, 3 LPRC TPWRT TLPRC 2, 3 2, 4 ECPLL TPWRT TLOCK FRCPLL TPWRT TFRC + TLOCK 2, 3, 4 XT, HS, SOSC TPWRT TOST XTPLL, HSPLL TPWRT TFRC + TLOCK 2, 3, 4 — — None Any Clock 2, 5 TPOR = Power-on Reset delay. TPWRT = 64 ms nominal if the Power-up Timer (PWRT) is enabled; otherwise, it is zero. TFRC and TLPRC = RC oscillator start-up times. TLOCK = PLL lock time. TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the oscillator clock to the system. If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC, and in such cases, FRC start-up time is valid. For detailed operating frequency and timing specifications, see Section 29.0 “Electrical Characteristics”. DS39995D-page 72  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 7.2.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate. • The Oscillator Start-up Timer (OST) has not expired (if a crystal oscillator is used). • The PLL has not achieved a lock (if PLL is used). The device will not begin to execute code until a valid clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known. 7.2.2 FAIL-SAFE CLOCK MONITOR (FSCM) AND DEVICE RESETS If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released. If a valid clock source is not available at this time, the device will automatically switch to the FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine (TSR). 7.3 Special Function Register Reset States Most of the Special Function Registers (SFRs) associated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual. The Reset value for each SFR does not depend on the type of Reset with the exception of four registers. The Reset value for the Reset Control register, RCON, will depend on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the type of Reset and the programmed values of the FNOSCx bits in the Flash Configuration Word (FOSCSEL); see Table 7-2. The RCFGCAL and NVMCON registers are only affected by a POR. 7.4 Deep Sleep BOR (DSBOR) Deep Sleep BOR is a very low-power BOR circuitry, used when the device is in Deep Sleep mode. Due to low current consumption, accuracy may vary. 7.5 Brown-out Reset (BOR) The PIC24FV32KA304 family devices implement a BOR circuit, which provides the user several configuration and power-saving options. The BOR is controlled by the BORV and BOREN Configuration bits (FPOR). There are a total of four BOR configurations, which are provided in Table 7-3. The BOR threshold is set by the BORV bits. If BOR is enabled (any values of BOREN, except ‘00’), any drop of VDD below the set threshold point will reset the device. The chip will remain in BOR until VDD rises above the threshold. If the Power-up Timer is enabled, it will be invoked after VDD rises above the threshold. Then, it will keep the chip in Reset for an additional time delay, TPWRT, if VDD drops below the threshold while the Power-up Timer is running. The chip goes back into a BOR and the Power-up Timer will be initialized. Once VDD rises above the threshold, the Power-up Timer will execute the additional time delay. BOR and the Power-up Timer (PWRT) are independently configured. Enabling the Brown-out Reset does not automatically enable the PWRT. 7.5.1 SOFTWARE ENABLED BOR When BOREN = 01, the BOR can be enabled or disabled by the user in software. This is done with the control bit, SBOREN (RCON). Setting SBOREN enables the BOR to function as previously described. Clearing the SBOREN disables the BOR entirely. The SBOREN bit operates only in this mode; otherwise, it is read as ‘0’. Placing BOR under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to change the BOR configuration. It also allows the user to tailor the incremental current that the BOR consumes. While the BOR current is typically very small, it may have some impact in low-power applications. Note: Even when the BOR is under software control, the Brown-out Reset voltage level is still set by the BORV Configuration bits; it cannot be changed in software. The DSBOR trip point is around 2.0V. DSBOR is enabled by configuring DSLPBOR (FDS) = 1. DSLPBOR will re-arm the POR to ensure the device will reset if VDD drops below the POR threshold.  2011-2013 Microchip Technology Inc. DS39995D-page 73 PIC24FV32KA304 FAMILY 7.5.2 DETECTING BOR When BOR is enabled, the BOR bit (RCON) is always reset to ‘1’ on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR and BOR bits are reset to ‘0’ in the software immediately after any POR event. If the BOR bit is ‘1’ while POR is ‘0’, it can be reliably assumed that a BOR event has occurred. Note: Even when the device exits from Deep Sleep mode, both the POR and BOR bits are set. DS39995D-page 74 7.5.3 DISABLING BOR IN SLEEP MODE When BOREN = 10, BOR remains under hardware control and operates as previously described. However, whenever the device enters Sleep mode, BOR is automatically disabled. When the device returns to any other operating mode, BOR is automatically re-enabled. This mode allows for applications to recover from brown-out situations, while actively executing code when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current. Note: BOR levels differ depending on device type; PIC24FV32KA3XX devices are at different levels than those of PIC24F32KA3XX devices. See Section 29.0 “Electrical Characteristics” for BOR voltage levels.  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 8.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Interrupt Controller, refer to the “PIC24F Family Reference Manual”, Section 8. “Interrupts” (DS39707). The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the CPU. It has the following features: • Up to Eight Processor Exceptions and Software Traps • Seven User-Selectable Priority Levels • Interrupt Vector Table (IVT) with up to 118 Vectors • Unique Vector for each Interrupt or Exception Source • Fixed Priority within a Specified User Priority Level • Alternate Interrupt Vector Table (AIVT) for Debug Support • Fixed Interrupt Entry and Return Latencies 8.1 Interrupt Vector Table (IVT) The IVT is shown in Figure 8-1. The IVT resides in the program memory, starting at location, 000004h. The IVT contains 126 vectors, consisting of eight non-maskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). 8.1.1 ALTERNATE INTERRUPT VECTOR TABLE (AIVT) The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 8-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2). If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT. 8.2 Reset Sequence A device Reset is not a true exception, because the interrupt controller is not involved in the Reset process. The PIC24F devices clear their registers in response to a Reset, which forces the Program Counter (PC) to zero. The microcontroller then begins program execution at location, 000000h. The user programs a GOTO instruction at the Reset address, which redirects the program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction. Interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with Vector 0 will take priority over interrupts at any other vector address. PIC24FV32KA304 family devices implement non-maskable traps and unique interrupts; these are summarized in Table 8-1 and Table 8-2.  2011-2013 Microchip Technology Inc. DS39995D-page 75 PIC24FV32KA304 FAMILY Decreasing Natural Order Priority FIGURE 8-1: Note 1: DS39995D-page 76 PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Start of Code 000000h 000002h 000004h 000014h 00007Ch 00007Eh 000080h Interrupt Vector Table (IVT)(1) 0000FCh 0000FEh 000100h 000102h 000114h Alternate Interrupt Vector Table (AIVT)(1) 00017Ch 00017Eh 000180h 0001FEh 000200h See Table 8-2 for the interrupt vector list.  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TABLE 8-1: TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address Trap Source 0 000004h 000104h 1 000006h 000106h Oscillator Failure 2 000008h 000108h Address Error Reserved 3 00000Ah 00010Ah Stack Error 4 00000Ch 00010Ch Math Error 5 00000Eh 00010Eh Reserved 6 000010h 000110h Reserved 7 000012h 000112h Reserved TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Source Vector Number IVT Address Interrupt Bit Locations AIVT Address Flag Enable Priority ADC1 Conversion Done 13 00002Eh 00012Eh IFS0 IEC0 IPC3 Comparator Event 18 000038h 000138h IFS1 IEC1 IPC4 CRC Generator 67 00009Ah 00019Ah IFS4 IEC4 IPC16 CTMU 77 0000AEh 0001AEh IFS4 IEC4 IPC19 External Interrupt 0 0 000014h 000114h IFS0 IEC0 IPC0 External Interrupt 1 20 00003Ch 00013Ch IFS1 IEC1 IPC5 External Interrupt 2 29 00004Eh 00014Eh IFS1 IEC1 IPC7 I2C1 Master Event 17 000036h 000136h IFS1 IEC1 IPC4 I2C1 Slave Event 16 000034h 000134h IFS1 IEC1 IPC4 I2C2 Master Event 50 000078h 000178h IFS3 IEC3 IPC12 I2C2 Slave Event 49 000076h 000176h IFS3 IEC3 IPC12 Input Capture 1 1 000016h 000116h IFS0 IEC0 IPC0 Input Capture 2 5 00001Eh 00011Eh IFS0 IEC0 IPC1 Input Capture 3 37 00005Eh 00015Eh IFS2 IEC2 IPC9 Input Change Notification 19 00003Ah 00013Ah IFS1 IEC1 IPC4 HLVD (High/Low-Voltage Detect) 72 0000A4h 0001A4h IFS4 IEC4 IPC17 NVM – NVM Write Complete 15 000032h 000132h IFS0 IEC0 IPC3 Output Compare 1 2 000018h 000118h IFS0 IEC0 IPC0 Output Compare 2 6 000020h 000120h IFS0 IEC0 IPC1 Output Compare 3 25 000046h 000146h IFS1 IEC1 IPC6 Real-Time Clock/Calendar 62 000090h 000190h IFS3 IEC3 IPC15 SPI1 Error 9 000026h 000126h IFS0 IEC0 IPC2 SPI1 Event 10 000028h 000128h IFS0 IEC0 IPC2 SPI2 Error 32 000054h 000154h IFS2 IEC2 IPC8 SPI2 Event 33 000056h 000156h IFS2 IEC2 IPC8 Timer1 3 00001Ah 00011Ah IFS0 IEC0 IPC0 Timer2 7 000022h 000122h IFS0 IEC0 IPC1 Timer3 8 000024h 000124h IFS0 IEC0 IPC2 Timer4 27 00004Ah 00014Ah IFS1 IEC1 IPC6 Timer5 28 00004Ch 00015Ch IFS1 IEC1 IPC7 UART1 Error 65 000096h 000196h IFS4 IEC4 IPC16 UART1 Receiver 11 00002Ah 00012Ah IFS0 IEC0 IPC2 UART1 Transmitter 12 00002Ch 00012Ch IFS0 IEC0 IPC3 UART2 Error 66 000098h 000198h IFS4 IEC4 IPC16 UART2 Receiver 30 000050h 000150h IFS1 IEC1 IPC7 UART2 Transmitter 31 000052h 000152h IFS1 IEC1 IPC7 Ultra Low-Power Wake-up 80 0000B4h 0001B4h IFS5 IEC5 IPC20  2011-2013 Microchip Technology Inc. DS39995D-page 77 PIC24FV32KA304 FAMILY 8.3 Interrupt Control and Status Registers The PIC24FV32KA304 family of devices implements a total of 23 registers for the interrupt controller: • • • • • INTCON1 INTCON2 IFS0, IFS1, IFS3 and IFS4 IEC0, IEC1, IEC3 and IEC4 IPC0 through IPC5, IPC7 and IPC15 through IPC19 • INTTREG Global Interrupt Enable (GIE) control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the AIVT. The IFSx registers maintain all of the interrupt request flags. Each source of interrupt has a status bit, which is set by the respective peripherals, or external signal, and is cleared via software. The IECx registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. The IPCx registers are used to set the Interrupt Priority Level (IPL) for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. DS39995D-page 78 The INTTREG register contains the associated interrupt vector number and the new CPU Interrupt Priority Level, which are latched into the Vector Number (VECNUM) and the Interrupt Level (ILR) bit fields in the INTTREG register. The new Interrupt Priority Level is the priority of the pending interrupt. The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence listed in Table 8-2. For example, the INT0 (External Interrupt 0) is depicted as having a vector number and a natural order priority of 0. The INT0IF status bit is found in IFS0, the INT0IE enable bit in IEC0 and the INT0IP priority bits are in the first position of IPC0 (IPC0). Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. The ALU STATUS Register (SR) contains the IPL bits (SR). These indicate the current CPU Interrupt Priority Level. The user may change the current CPU Interrupt Priority Level by writing to the IPLx bits. The CORCON register contains the IPL3 bit, which together with IPL, also indicates the current CPU Interrupt Priority Level. IPL3 is a read-only bit so that the trap events cannot be masked by the user’s software. All Interrupt registers are described in Register 8-1 through Register 8-33, in the following sections.  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC — — — — — — — DC(1) bit 15 bit 8 R/W-0, HSC R/W-0, HSC R/W-0, HSC R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC IPL2(2,3) IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9 Unimplemented: Read as ‘0’ bit 7-5 IPL: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: 2: 3: Note: x = Bit is unknown See Register 3-1 for the description of these bits, which are not dedicated to interrupt control functions. The IPL bits are concatenated with the IPL3 bit (CORCON) to form the CPU Interrupt Priority Level. The value in parentheses indicates the Interrupt Priority Level if IPL3 = 1. The IPLx Status bits are read-only when NSTDIS (INTCON1) = 1. Bit 8 and bits 4 through 0 are described in Section 3.0 “CPU”.  2011-2013 Microchip Technology Inc. DS39995D-page 79 PIC24FV32KA304 FAMILY REGISTER 8-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — U-0 — R/C-0, HSC (2) IPL3 R/W-0 U-0 U-0 — — (1) PSV bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 1-0 Unimplemented: Read as ‘0’ Note 1: 2: Note: x = Bit is unknown See Register 3-2 for the description of this bit, which is not dedicated to interrupt control functions. The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU Interrupt Priority Level. Bit 2 is described in Section 3.0 “CPU”. DS39995D-page 80  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14-5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Arithmetic Error Trap Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. x = Bit is unknown DS39995D-page 81 PIC24FV32KA304 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER2 R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Uses Alternate Interrupt Vector Table (AIVT) 0 = Uses standard (default) Interrupt Vector Table (IVT) bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-3 Unimplemented: Read as ‘0’ bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt is on the negative edge 0 = Interrupt is on the positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt is on the negative edge 0 = Interrupt is on the positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt is on the negative edge 0 = Interrupt is on the positive edge DS39995D-page 82 x = Bit is unknown  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 R/W-0, HS NVMIF bit 15 U-0 — R/W-0, HS AD1IF R/W-0, HS U1TXIF R/W-0, HS U1RXIF R/W-0, HS SPI1IF R/W-0, HS SPF1IF R/W-0, HS T3IF bit 8 R/W-0, HS T2IF bit 7 R/W-0, HS OC2IF R/W-0, HS IC2IF U-0 — R/W-0, HS T1IF R/W-0, HS OC1IF R/W-0, HS IC1IF R/W-0, HS INT0IF bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 HS = Hardware Settable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown NVMIF: NVM Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ AD1IF: A/D Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF1IF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2011-2013 Microchip Technology Inc. DS39995D-page 83 PIC24FV32KA304 FAMILY REGISTER 8-5: bit 2 bit 1 bit 0 IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS39995D-page 84  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0, HS U2TXIF bit 15 R/W-0, HS U2RXIF U-0 — U-0 — R/W-0, HS INT2IF R/W-0, HS T5IF R/W-0, HS T4IF Legend: R = Readable bit -n = Value at POR bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8-5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W-0, HS OC3IF U-0 — bit 8 U-0 — R/W-0, HS INT1IF R/W-0, HS CNIF bit 7 bit 15 U-0 — R/W-0, HS CMIF R/W-0 MI2C1IF R/W-0 SI2C1IF bit 0 HS = Hardware Settable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2011-2013 Microchip Technology Inc. DS39995D-page 85 PIC24FV32KA304 FAMILY REGISTER 8-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0, HS U-0 U-0 U-0 R/W-0, HS R/W-0, HS — — IC3IF — — — SPI2IF SPF2IF bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-2 Unimplemented: Read as ‘0’ bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS39995D-page 86 x = Bit is unknown  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0, HS U-0 U-0 U-0 U-0 U-0 U-0 — RTCIF — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS U-0 — — — — — MI2C2IF SI2C2IF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock and Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IF: Master I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. x = Bit is unknown DS39995D-page 87 PIC24FV32KA304 FAMILY REGISTER 8-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0, HS U-0 U-0 U-0 U-0 R/W-0, HS — — CTMUIF — — — — HLVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-9 Unimplemented: Read as ‘0’ bit 8 HLVDIF: High/Low-Voltage Detect Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7-4 Unimplemented: Read as ‘0’ bit 3 CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ DS39995D-page 88 x = Bit is unknown  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — ULPWUIF bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 Unimplemented: Read as ‘0’ bit 0 ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2011-2013 Microchip Technology Inc. x = Bit is unknown DS39995D-page 89 PIC24FV32KA304 FAMILY REGISTER 8-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 R/W-0 NVMIE bit 15 U-0 — R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 T2IE bit 7 R/W-0 OC2IE R/W-0 IC2IE U-0 — R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE R/W-0 INT0IE bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown NVMIE: NVM Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ AD1IE: A/D Conversion Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled SPI1IE: SPI1 Transfer Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled SPF1IE: SPI1 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS39995D-page 90  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-11: bit 1 bit 0 IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2011-2013 Microchip Technology Inc. DS39995D-page 91 PIC24FV32KA304 FAMILY REGISTER 8-12: R/W-0 U2TXIE bit 15 IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 U2RXIE R/W-0 INT2IE R/W-0 T5IE R/W-0 T4IE U-0 — U-0 — R/W-0 INT1IE R/W-0 CNIE bit 7 Legend: R = Readable bit -n = Value at POR bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8-5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W-0 OC3IE U-0 — bit 8 U-0 — bit 15 U-0 — W = Writable bit ‘1’ = Bit is set R/W-0 CMIE R/W-0 MI2C1IE R/W-0 SI2C1IE bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ OC3IE: Output Compare 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled CMIE: Comparator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS39995D-page 92  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-13: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 — — IC3IE — — — SPI2IE SPF2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4-2 Unimplemented: Read as ‘0’ bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2011-2013 Microchip Technology Inc. x = Bit is unknown DS39995D-page 93 PIC24FV32KA304 FAMILY REGISTER 8-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIE — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock and Calendar Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IE: Master I2C2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ DS39995D-page 94 x = Bit is unknown  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIE — — — — HLVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12-9 Unimplemented: Read as ‘0’ bit 8 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7-4 Unimplemented: Read as ‘0’ bit 3 CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. x = Bit is unknown DS39995D-page 95 PIC24FV32KA304 FAMILY REGISTER 8-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ULPWUIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 Unimplemented: Read as ‘0’ bit 0 ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable Bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS39995D-page 96 x = Bit is unknown  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-17: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP: Timer1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP: External Interrupt 0 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2011-2013 Microchip Technology Inc. DS39995D-page 97 PIC24FV32KA304 FAMILY REGISTER 8-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC2IP2 IC2IP1 IC2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP: Timer2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC2IP: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC2IP: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39995D-page 98  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-19: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP: UART1 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP: SPI1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPF1IP: SPI1 Fault Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP: Timer3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2011-2013 Microchip Technology Inc. DS39995D-page 99 PIC24FV32KA304 FAMILY REGISTER 8-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — NVMIP2 NVMIP1 NVMIP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 NVMIP: NVM Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP: A/D Conversion Complete Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS39995D-page 100  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-21: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP: Input Change Notification Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 CMIP: Comparator Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1P: Master I2C1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1P: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2011-2013 Microchip Technology Inc. DS39995D-page 101 PIC24FV32KA304 FAMILY REGISTER 8-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP: External Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS39995D-page 102  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-23: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — T4IP2 T4IP1 T4IP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — OC3IP2 OC3IP1 OC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP: Timer4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-7 Unimplemented: Read as ‘0’ bit 6-4 OC3IP: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. DS39995D-page 103 PIC24FV32KA304 FAMILY REGISTER 8-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2RXIP: UART2 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP: External Interrupt 2 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T5IP: Timer5 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS39995D-page 104  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-25: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP: SPI2 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SPF2IP: SPI2 Fault Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2011-2013 Microchip Technology Inc. DS39995D-page 105 PIC24FV32KA304 FAMILY REGISTER 8-26: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC3IP2 IC3IP1 IC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 IC3IP: Input Capture Channel 3 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39995D-page 106  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP : Master I2C2 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SI2C2IP: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. DS39995D-page 107 PIC24FV32KA304 FAMILY REGISTER 8-28: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP: Real-Time Clock and Calendar Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ DS39995D-page 108  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-29: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP: CRC Generator Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2ERIP: UART2 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U1ERIP: UART1 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. DS39995D-page 109 PIC24FV32KA304 FAMILY REGISTER 8-30: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — HLVDIP2 HLVDIP1 HLVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 HLVDIP: High/Low-Voltage Detect Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled REGISTER 8-31: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CTMUIP2 CTMUIP1 CTMUIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CTMUIP: CTMU Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39995D-page 110  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 8-32: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — ULPWUIP2 ULPWUIP1 ULPWUIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 6-4 ULPWUIP: Ultra Low-Power Wake-up Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) x = Bit is unknown • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2011-2013 Microchip Technology Inc. DS39995D-page 111 PIC24FV32KA304 FAMILY REGISTER 8-33: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit 1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU (this will happen when the CPU priority is higher than the interrupt priority) 0 = No interrupt request is left unacknowledged bit 14 Unimplemented: Read as ‘0’ bit 13 VHOLD: Vector Hold bit Allows Vector Number Capture and Changes which Interrupt is Stored in the VECNUM bit: 1 = VECNUM will contain the value of the highest priority pending interrupt, instead of the current interrupt 0 = VECNUM will contain the value of the last Acknowledged interrupt (last interrupt that has occurred with higher priority than the CPU, even if other interrupts are pending) bit 12 Unimplemented: Read as ‘0’ bit 11-8 ILR: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM: Vector Number of Pending Interrupt bits 0111111 = Interrupt vector pending is Number 135 • • • 0000001 = Interrupt vector pending is Number 9 0000000 = Interrupt vector pending is Number 8 DS39995D-page 112  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 8.4 Interrupt Setup Procedures 8.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS control bit (INTCON1) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources may be programmed to the same non-zero value. Note: 3. 4. At a device Reset, the IPCx registers are initialized, such that all user interrupt sources are assigned to Priority Level 4. Clear the interrupt flag status bit associated with the peripheral in the associated IFSx register. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx register. 8.4.2 8.4.3 TRAP SERVICE ROUTINE (TSR) A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR. 8.4.4 INTERRUPT DISABLE All user interrupts can be disabled using the following procedure: 1. 2. Push the current SR value onto the software stack using the PUSH instruction. Force the CPU to Priority Level 7 by inclusive ORing the value, OEh with SRL. To enable user interrupts, the POP instruction may be used to restore the previous SR value. Only user interrupts with a priority level of 7 or less can be disabled. Trap sources (Level 8-15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of Priority Levels 1-6 for a fixed period. Level 7 interrupt sources are not disabled by the DISI instruction. INTERRUPT SERVICE ROUTINE The method that is used to declare an ISR (Interrupt Service Routine) and initialize the IVT with the correct vector address depends on the programming language (i.e., C or assembly) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of the interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.  2011-2013 Microchip Technology Inc. DS39995D-page 113 PIC24FV32KA304 FAMILY NOTES: DS39995D-page 114  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 9.0 OSCILLATOR CONFIGURATION Note: • Software-controllable switching between various clock sources. • Software-controllable postscaler for selective clocking of CPU for system power savings. • System frequency range declaration bits for EC mode. When using an external clock source, the current consumption is reduced by setting the declaration bits to the expected frequency range. • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Oscillator Configuration, refer to the “PIC24F Family Reference Manual”, Section 38. “Oscillator with 500 kHz Low-Power FRC” (DS39726). A simplified diagram of the oscillator system is shown in Figure 9-1. The oscillator system for the PIC24FV32KA304 family of devices has the following features: • A total of five external and internal oscillator options as clock sources, providing 11 different clock modes. • On-chip 4x Phase Locked Loop (PLL) to boost internal operating frequency on select internal and external oscillator sources. FIGURE 9-1: PIC24FV32KA304 FAMILY CLOCK DIAGRAM Primary Oscillator REFOCON XT, HS, EC OSCO OSCI 4 x PLL 8 MHz 4 MHz Postscaler 8 MHz FRC Oscillator 500 kHz LPFRC Oscillator Reference Clock Generator XTPLL, HSPLL ECPLL,FRCPLL REFO FRCDIV Peripherals CLKDIV FRC CLKO LPRC Postscaler LPRC Oscillator 31 kHz (nominal) Secondary Oscillator SOSC SOSCO SOSCI CPU CLKDIV SOSCEN Enable Oscillator Clock Control Logic Fail-Safe Clock Monitor WDT, PWRT, DSWDT Clock Source Option for Other Modules  2011-2013 Microchip Technology Inc. DS39995D-page 115 PIC24FV32KA304 FAMILY 9.1 CPU Clocking Scheme 9.2 The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins The PIC24FV32KA304 family devices consist of two types of secondary oscillator: - High-Power Secondary Oscillator - Low-Power Secondary Oscillator These can be selected by using the SOSCSEL (FOSC) bit. • Fast Internal RC (FRC) Oscillator - 8 MHz FRC Oscillator - 500 kHz Lower Power FRC Oscillator • Low-Power Internal RC (LPRC) Oscillator with two modes: - High-Power/High Accuracy mode - Low-Power/Low Accuracy mode The primary oscillator and 8 MHz FRC sources have the option of using the internal 4x PLL. The frequency of the FRC clock source can optionally be reduced by the programmable clock divider. The selected clock source generates the processor and peripheral clock sources. The processor clock source is divided by two to produce the internal instruction cycle clock, FCY. In this document, the instruction cycle clock is also denoted by FOSC/2. The internal instruction cycle clock, FOSC/2, can be provided on the OSCO I/O pin for some operating modes of the primary oscillator. TABLE 9-1: Initial Configuration on POR The oscillator source (and operating mode) that is used at a device Power-on Reset (POR) event is selected using Configuration bit settings. The Oscillator Configuration bit settings are located in the Configuration registers in the program memory (for more information, see Section 26.1 “Configuration Bits”). The Primary Oscillator Configuration bits, POSCMD (FOSC), and the Initial Oscillator Select Configuration bits, FNOSC (FOSCSEL), select the oscillator source that is used at a POR. The FRC Primary Oscillator with Postscaler (FRCDIV) is the default (unprogrammed) selection. The secondary oscillator, or one of the internal oscillators, may be chosen by programming these bit locations. The EC mode Frequency Range Configuration bits, POSCFREQ (FOSC), optimize power consumption when running in EC mode. The default configuration is “frequency range is greater than 8 MHz”. The Configuration bits allow users to choose between the various clock modes, shown in Table 9-1. 9.2.1 CLOCK SWITCHING MODE CONFIGURATION BITS The FCKSMx Configuration bits (FOSC) are used jointly to configure device clock switching and the FSCM. Clock switching is enabled only when FCKSM1 is programmed (‘0’). The FSCM is enabled only when FCKSM are both programmed (‘00’). CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD FNOSC 8 MHz FRC Oscillator with Postscaler (FRCDIV) Internal 11 111 1, 2 500 kHz FRC Oscillator with Postscaler (LPFRCDIV) Internal 11 110 1 Low-Power RC Oscillator (LPRC) Notes Internal 11 101 1 Secondary 00 100 1 Primary Oscillator (HS) with PLL Module (HSPLL) Primary 10 011 Primary Oscillator (EC) with PLL Module (ECPLL) Primary 00 011 Primary Oscillator (HS) Primary 10 010 Primary Oscillator (XT) Primary 01 010 Primary Oscillator (EC) Primary 00 010 8 MHz FRC Oscillator with PLL Module (FRCPLL) Internal 11 001 1 8 MHz FRC Oscillator (FRC) Internal 11 000 1 Secondary (Timer1) Oscillator (SOSC) Note 1: 2: The OSCO pin function is determined by the OSCIOFNC Configuration bit. This is the default oscillator mode for an unprogrammed (erased) device. DS39995D-page 116  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 9.3 Control Registers The Clock Divider register (Register 9-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. The operation of the oscillator is controlled by three Special Function Registers (SFRs): The FRC Oscillator Tune register (Register 9-3) allows the user to fine tune the FRC oscillator over a range of approximately ±5.25%. Each bit increment or decrement changes the factory calibrated frequency of the FRC oscillator by a fixed amount. • OSCCON • CLKDIV • OSCTUN The OSCCON register (Register 9-1) is the main control register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0, HSC R-0, HSC R-0, HSC U-0 R/W-x(1) R/W-x(1) R/W-x(1) — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 bit 15 bit 8 R/SO-0, HSC U-0 R-0, HSC(2) U-0 R/CO-0, HS R/W-0(3) R/W-0 R/W-0 CLKLOCK — LOCK — CF SOSCDRV SOSCEN OSWEN bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit HS = Hardware Settable bit CO = Clearable Only bit SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC: Current Oscillator Selection bits 111 = 8 MHz Fast RC Oscillator with Postscaler (FRCDIV) 110 = 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV) 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL) 000 = 8 MHz FRC Oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC: New Oscillator Selection bits(1) 111 = 8 MHz Fast RC Oscillator with Postscaler (FRCDIV) 110 = 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV) 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL) 000 = 8 MHz FRC Oscillator (FRC) Note 1: 2: 3: Reset values for these bits are determined by the FNOSCx Configuration bits. This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC = 0), this bit has no effect.  2011-2013 Microchip Technology Inc. DS39995D-page 117 PIC24FV32KA304 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. bit 6 Unimplemented: Read as ‘0’ bit 5 LOCK: PLL Lock Status bit(2) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 SOSCDRV: Secondary Oscillator Drive Strength bit(3) 1 = High-power SOSC circuit is selected 0 = Low/high-power select is done via the SOSCSRC Configuration bit bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enables the secondary oscillator 0 = Disables the secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiates an oscillator switch to the clock source specified by the NOSC bits 0 = Oscillator switch is complete Note 1: 2: 3: Reset values for these bits are determined by the FNOSCx Configuration bits. This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC = 0), this bit has no effect. DS39995D-page 118  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 9-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit, and reset the CPU and peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE: CPU and Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 11 DOZEN: Doze Enable bit(1) 1 = DOZE bits specify the CPU and peripheral clock ratio 0 = CPU and peripheral clock ratio are set to 1:1 bit 10-8 RCDIV: FRC Postscaler Select bits When COSC (OSCCON) = 111: 111 = 31.25 kHz (divide-by-256) 110 = 125 kHz (divide-by-64) 101 = 250 kHz (divide-by-32) 100 = 500 kHz (divide-by-16) 011 = 1 MHz (divide-by-8) 010 = 2 MHz (divide-by-4) 001 = 4 MHz (divide-by-2) (default) 000 = 8 MHz (divide-by-1) When COSC (OSCCON) = 110: 111 = 1.95 kHz (divide-by-256) 110 = 7.81 kHz (divide-by-64) 101 = 15.62 kHz (divide-by-32) 100 = 31.25 kHz (divide-by-16) 011 = 62.5 kHz (divide-by-8) 010 = 125 kHz (divide-by-4) 001 = 250 kHz (divide-by-2) (default) 000 = 500 kHz (divide-by-1) bit 7-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.  2011-2013 Microchip Technology Inc. DS39995D-page 119 PIC24FV32KA304 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 TUN5 (1) R/W-0 (1) TUN4 R/W-0 (1) TUN3 R/W-0 TUN2 (1) R/W-0 TUN1 (1) R/W-0 TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN: FRC Oscillator Tuning bits(1) 011111 = Maximum frequency deviation 011110 x = Bit is unknown • • • 000001 000000 = Center frequency, oscillator is running at factory calibrated frequency 111111 • • • 100001 100000 = Minimum frequency deviation Note 1: Increments or decrements of TUN may not change the FRC frequency in equal steps over the FRC tuning range and may not be monotonic. DS39995D-page 120  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 9.4 Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: 9.4.1 The Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMDx Configuration bits. While an application can switch to and from Primary Oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. ENABLING CLOCK SWITCHING To enable clock switching, the FCKSM1 Configuration bit in the FOSC Configuration register must be programmed to ‘0’. (Refer to Section 26.0 “Special Features” for further details.) If the FCKSM1 Configuration bit is unprogrammed (‘1’), the clock switching function and FSCM function are disabled. This is the default setting. The NOSCx control bits (OSCCON) do not control the clock selection when clock switching is disabled. However, the COSCx bits (OSCCON) will reflect the clock source selected by the FNOSCx Configuration bits. The OSWEN control bit (OSCCON) has no effect when clock switching is disabled; it is held at ‘0’ at all times. 9.4.2 OSCILLATOR SWITCHING SEQUENCE At a minimum, performing a clock switch requires this basic sequence: 1. 2. 3. 4. 5. If desired, read the COSCx bits (OSCCON) to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSCx bits (OSCCON) for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit to initiate the oscillator switch.  2011-2013 Microchip Technology Inc. Once the basic sequence is completed, the system clock hardware responds automatically, as follows: 1. 2. 3. 4. 5. 6. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. If a valid clock switch has been initiated, the LOCK (OSCCON) and CF (OSCCON) bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the OST expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSCx bits value is transferred to the COSCx bits. The old clock source is turned off at this time, with the exception of LPRC (if WDT, FSCM or RTCC with LPRC as a clock source is enabled) or SOSC (if SOSCEN remains enabled). Note 1: The processor will continue to execute code throughout the clock switching sequence. Timing-sensitive code should not be executed during this time. 2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. DS39995D-page 121 PIC24FV32KA304 FAMILY The following code sequence for a clock switch is recommended: 1. 2. 3. 4. 5. 6. 7. 8. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON, in two back-to-back instructions. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence. Execute the unlock sequence for the OSCCON low byte by writing 46h and 57h to OSCCON, in two back-to-back instructions. Set the OSWEN bit in the instruction immediately following the unlock sequence. Continue to execute code that is not clock-sensitive (optional). Invoke an appropriate amount of software delay (cycle counting) to allow the selected oscillator and/or PLL to start and stabilize. Check to see if OSWEN is ‘0’. If it is, the switch was successful. If OSWEN is still set, then check the LOCK bit to determine the cause of failure. The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example 9-1. EXAMPLE 9-1: BASIC CODE SEQUENCE FOR CLOCK SWITCHING ;Place the new oscillator selection in W0 ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Set new oscillator selection MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON,#0 DS39995D-page 122 9.5 Reference Clock Output In addition to the CLKO output (FOSC/2) available in certain oscillator modes, the device clock in the PIC24FV32KA304 family devices can also be configured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. This reference clock output is controlled by the REFOCON register (Register 9-4). Setting the ROEN bit (REFOCON) makes the clock signal available on the REFO pin. The RODIVx bits (REFOCON) enable the selection of 16 different clock divider options. The ROSSLP and ROSEL bits (REFOCON) control the availability of the reference output during Sleep mode. The ROSEL bit determines if the oscillator on OSC1 and OSC2, or the current system clock source, is used for the reference clock output. The ROSSLP bit determines if the reference source is available on REFO when the device is in Sleep mode. To use the reference clock output in Sleep mode, both the ROSSLP and ROSEL bits must be set. The device clock must also be configured for one of the primary modes (EC, HS or XT); otherwise, if the ROSEL bit is not also set, the oscillator on OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches.  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 9-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Reference oscillator is enabled on REFO pin 0 = Reference oscillator is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep bit 12 ROSEL: Reference Oscillator Source Select bit 1 = Primary oscillator is used as the base clock(1) 0 = System clock is used as the base clock; base clock reflects any clock switching of the device bit 11-8 RODIV: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’ Note 1: The crystal oscillator must be enabled using the FOSC bits; the crystal maintains the operation in Sleep mode.  2011-2013 Microchip Technology Inc. DS39995D-page 123 PIC24FV32KA304 FAMILY NOTES: DS39995D-page 124  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 10.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 39. Power-Saving Features with Deep Sleep” (DS39727). The PIC24FV32KA304 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. All PIC24F devices manage power consumption in four different ways: • Clock Frequency • Instruction-Based Sleep, Idle and Deep Sleep modes • Software Controlled Doze mode • Selective Peripheral Control in Software Combinations of these methods can be used to selectively tailor an application’s power consumption, while still maintaining critical application features, such as timing-sensitive communications. 10.1 Clock Frequency and Clock Switching PIC24F devices allow for a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSCx bits. The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 9.0 “Oscillator Configuration”. 10.2 Instruction-Based Power-Saving Modes PIC24F devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution; Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. Deep Sleep mode stops clock operation, code execution and all peripherals, except RTCC and DSWDT. It also freezes I/O states and removes power to SRAM and Flash memory. EXAMPLE 10-1: PWRSAV PWRSAV BSET PWRSAV The assembly syntax of the PWRSAV instruction is shown in Example 10-1. Note: SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to “wake-up”. 10.2.1 SLEEP MODE Sleep mode includes these features: • The system clock source is shut down. If an on-chip oscillator is used, it is turned off. • The device current consumption will be reduced to a minimum provided that no I/O pin is sourcing current. • The I/O pin directions and states are frozen. • The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source is disabled. • The LPRC clock will continue to run in Sleep mode if the WDT or RTCC with LPRC as the clock source is enabled. • The WDT, if enabled, is automatically cleared prior to entering Sleep mode. • Some device features or peripherals may continue to operate in Sleep mode. This includes items, such as the Input Change Notification on the I/O ports, or peripherals that use an external clock input. Any peripheral that requires the system clock source for its operation will be disabled in Sleep mode. The device will wake-up from Sleep mode on any of these events: • On any interrupt source that is individually enabled • On any form of device Reset • On a WDT time-out On wake-up from Sleep, the processor will restart with the same clock source that was active when Sleep mode was entered. PWRSAV INSTRUCTION SYNTAX #SLEEP_MODE #IDLE_MODE DSCON, #DSEN #SLEEP_MODE ; ; ; ;  2011-2013 Microchip Technology Inc. Put the device into SLEEP mode Put the device into IDLE mode Enable Deep Sleep Put the device into Deep SLEEP mode DS39995D-page 125 PIC24FV32KA304 FAMILY 10.2.2 IDLE MODE Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10.6 “Selective Peripheral Module Control”). • If the WDT or FSCM is enabled, the LPRC will also remain active. The device will wake from Idle mode on any of these events: • Any interrupt that is individually enabled • Any device Reset • A WDT time-out On wake-up from Idle, the clock is re-applied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction or the first instruction in the ISR. 10.2.3 DEEP SLEEP MODE In PIC24FV32KA304 family devices, Deep Sleep mode is intended to provide the lowest levels of power consumption available without requiring the use of external switches to completely remove all power from the device. Entry into Deep Sleep mode is completely under software control. Exit from Deep Sleep mode can be triggered from any of the following events: • • • • • • POR Event MCLR Event RTCC Alarm (if the RTCC is present) External Interrupt 0 Deep Sleep Watchdog Timer (DSWDT) Time-out Ultra Low-Power Wake-up (ULPWU) Event Entering Deep Sleep Mode Deep Sleep mode is entered by setting the DSEN bit in the DSCON register and then executing a Sleep command (PWRSAV #SLEEP_MODE). An unlock sequence is required to set the DSEN bit. Once the DSEN bit has been set, there is no time limit before the SLEEP command can be executed. The DSEN bit is automatically cleared when exiting the Deep Sleep mode. Note: To re-enter Deep Sleep after a Deep Sleep wake-up, allow a delay of at least 3 TCY after clearing the RELEASE bit. The sequence to enter Deep Sleep mode is: 1. 2. 3. INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry into Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode. 10.2.4 10.2.4.1 4. 5. If the application requires the Deep Sleep WDT, enable it and configure its clock source. For more information on Deep Sleep WDT, see Section 10.2.4.5 “Deep Sleep WDT”. If the application requires Deep Sleep BOR, enable it by programming the DSLPBOR Configuration bit (FDS). If the application requires wake-up from Deep Sleep on RTCC alarm, enable and configure the RTCC module For more information on RTCC, see Section 19.0 “Real-Time Clock and Calendar (RTCC)”. If needed, save any critical application context data by writing it to the DSGPR0 and DSGPR1 registers (optional). Enable Deep Sleep mode by setting the DSEN bit (DSCON). Note: 6. An unlock sequence is required to set the DSEN bit. Enter Deep Sleep mode by issuing a PWRSAV #0 instruction. Any time the DSEN bit is set, all bits in the DSWAKE register will be automatically cleared. To set the DSEN bit, the unlock sequence in Example 10-2 is required: EXAMPLE 10-2: THE UNLOCK SEQUENCE //Disable Interrupts For 5 instructions asm volatile(“disi #5”); In Deep Sleep mode, it is possible to keep the device Real-Time Clock and Calendar (RTCC) running without the loss of clock cycles. //Issue Unlock Sequence The device has a dedicated Deep Sleep Brown-out Reset (DSBOR) and a Deep Sleep Watchdog Timer Reset (DSWDT) for monitoring voltage and time-out events. The DSBOR and DSWDT are independent of the standard BOR and WDT used with other power-managed modes (Sleep, Idle and Doze). DS39995D-page 126 asm volatile mov #0x55, W0; mov W0, NVMKEY; mov #0xAA, W1; mov W1, NVMKEY; bset DSCON, #DSEN  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 10.2.4.2 Exiting Deep Sleep Mode Deep Sleep mode exits on any one of the following events: • A POR event on VDD supply. If there is no DSBOR circuit to re-arm the VDD supply POR circuit, the external VDD supply must be lowered to the natural arming voltage of the POR circuit. • A DSWDT time-out. When the DSWDT timer times out, the device exits Deep Sleep. • An RTCC alarm (if RTCEN = 1). • An assertion (‘0’) of the MCLR pin. • An assertion of the INT0 pin (if the interrupt was enabled before Deep Sleep mode was entered). The polarity configuration is used to determine the assertion level (‘0’ or ‘1’) of the pin that will cause an exit from Deep Sleep mode. Exiting from Deep Sleep mode requires a change on the INT0 pin while in Deep Sleep mode. Note: Any interrupt pending when entering Deep Sleep mode is cleared. Exiting Deep Sleep mode generally does not retain the state of the device and is equivalent to a Power-on Reset (POR) of the device. Exceptions to this include the RTCC (if present), which remains operational through the wake-up, the DSGPRx registers and DSWDT. Wake-up events that occur after Deep Sleep exits, but before the POR sequence completes, are ignored and are not be captured in the DSWAKE register. The sequence for exiting Deep Sleep mode is: 1. 2. 3. 4. 5. 6. After a wake-up event, the device exits Deep Sleep and performs a POR. The DSEN bit is cleared automatically. Code execution resumes at the Reset vector. To determine if the device exited Deep Sleep, read the Deep Sleep bit, DPSLP (RCON). This bit will be set if there was an exit from Deep Sleep mode; if the bit is set, clear it. Determine the wake-up source by reading the DSWAKE register. Determine if a DSBOR event occurred during Deep Sleep mode by reading the DSBOR bit (DSCON). If application context data has been saved, read it back from the DSGPR0 and DSGPR1 registers. Clear the RELEASE bit (DSCON). 10.2.4.3 Saving Context Data with the DSGPR0/DSGPR1 Registers As exiting Deep Sleep mode causes a POR, most Special Function Registers reset to their default POR values. In addition, because VCORE power is not supplied in Deep Sleep mode, information in data RAM may be lost when exiting this mode.  2011-2013 Microchip Technology Inc. Applications which require critical data to be saved prior to Deep Sleep may use the Deep Sleep General Purpose registers, DSGPR0 and DSGPR1 or data EEPROM (if available). Unlike other SFRs, the contents of these registers are preserved while the device is in Deep Sleep mode. After exiting Deep Sleep, software can restore the data by reading the registers and clearing the RELEASE bit (DSCON). 10.2.4.4 I/O Pins During Deep Sleep During Deep Sleep, the general purpose I/O pins retain their previous states and the Secondary Oscillator (SOSC) will remain running, if enabled. Pins that are configured as inputs (TRISx bit is set), prior to entry into Deep Sleep, remain high-impedance during Deep Sleep. Pins that are configured as outputs (TRISx bit is clear), prior to entry into Deep Sleep, remain as output pins during Deep Sleep. While in this mode, they continue to drive the output level determined by their corresponding LATx bit at the time of entry into Deep Sleep. Once the device wakes back up, all I/O pins continue to maintain their previous states, even after the device has finished the POR sequence and is executing application code again. Pins configured as inputs during Deep Sleep remain high-impedance and pins configured as outputs continue to drive their previous value. After waking up, the TRIS and LAT registers, and the SOSCEN bit (OSCCON) are reset. If firmware modifies any of these bits or registers, the I/O will not immediately go to the newly configured states. Once the firmware clears the RELEASE bit (DSCON), the I/O pins are “released”. This causes the I/O pins to take the states configured by their respective TRISx and LATx bit values. This means that keeping the SOSC running after waking up requires the SOSCEN bit to be set before clearing RELEASE. If the Deep Sleep BOR (DSBOR) is enabled, and a DSBOR or a true POR event occurs during Deep Sleep, the I/O pins will be immediately released, similar to clearing the RELEASE bit. All previous state information will be lost, including the general purpose DSGPR0 and DSGPR1 contents. If a MCLR Reset event occurs during Deep Sleep, the DSGPRx, DSCON and DSWAKE registers will remain valid, and the RELEASE bit will remain set. The state of the SOSC will also be retained. The I/O pins, however, will be reset to their MCLR Reset state. Since RELEASE is still set, changes to the SOSCEN bit (OSCCON) cannot take effect until the RELEASE bit is cleared. In all other Deep Sleep wake-up cases, application firmware must clear the RELEASE bit in order to reconfigure the I/O pins. DS39995D-page 127 PIC24FV32KA304 FAMILY 10.2.4.5 Deep Sleep WDT To enable the DSWDT in Deep Sleep mode, program the Configuration bit, DSWDTEN (FDS). The device Watchdog Timer (WDT) need not be enabled for the DSWDT to function. Entry into Deep Sleep mode automatically resets the DSWDT. The DSWDT clock source is selected by the DSWDTOSC Configuration bit (FDS). The postscaler options are programmed by the DSWDTPS Configuration bits (FDS). The minimum time-out period that can be achieved is 2.1 ms and the maximum is 25.7 days. For more details on the FDS Configuration register and DSWDT configuration options, refer to Section 26.0 “Special Features”. 10.2.4.6 Switching Clocks in Deep Sleep Mode Both the RTCC and the DSWDT may run from either SOSC or the LPRC clock source. This allows both the RTCC and DSWDT to run without requiring both the LPRC and SOSC to be enabled together, reducing power consumption. Running the RTCC from LPRC will result in a loss of accuracy in the RTCC of approximately 5 to 10%. If a more accurate RTCC is required, it must be run from the SOSC clock source. The RTCC clock source is selected with the RTCOSC Configuration bit (FDS). Under certain circumstances, it is possible for the DSWDT clock source to be off when entering Deep Sleep mode. In this case, the clock source is turned on automatically (if DSWDT is enabled), without the need for software intervention; however, this can cause a delay in the start of the DSWDT counters. In order to avoid this delay when using SOSC as a clock source, the application can activate SOSC prior to entering Deep Sleep mode. 10.2.4.7 Checking and Clearing the Status of Deep Sleep Upon entry into Deep Sleep mode, the status bit, DPSLP (RCON), becomes set and must be cleared by the software. 10.2.4.8 Power-on Resets (PORs) VDD voltage is monitored to produce PORs. Since exiting from Deep Sleep functionally looks like a POR, the technique described in Section 10.2.4.7 “Checking and Clearing the Status of Deep Sleep” should be used to distinguish between Deep Sleep and a true POR event. When a true POR occurs, the entire device, including all Deep Sleep logic (Deep Sleep registers: RTCC, DSWDT, etc.) is reset. 10.2.4.9 Summary of Deep Sleep Sequence To review, these are the necessary steps involved in invoking and exiting Deep Sleep mode: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. The device exits Reset and begins to execute its application code. If DSWDT functionality is required, program the appropriate Configuration bit. Select the appropriate clock(s) for the DSWDT and RTCC (optional). Enable and configure the DSWDT (optional). Enable and configure the RTCC (optional). Write context data to the DSGPRx registers (optional). Enable the INT0 interrupt (optional). Set the DSEN bit in the DSCON register. Enter Deep Sleep by issuing a PWRSV #SLEEP_MODE command. The device exits Deep Sleep when a wake-up event occurs. The DSEN bit is automatically cleared. Read and clear the DPSLP status bit in RCON, and the DSWAKE status bits. Read the DSGPRx registers (optional). Once all state related configurations are complete, clear the RELEASE bit. The application resumes normal operation. On power-up, the software should read this status bit to determine if the Reset was due to an exit from Deep Sleep mode and clear the bit if it is set. Of the four possible combinations of DPSLP and POR bit states, three cases can be considered: • Both the DPSLP and POR bits are cleared. In this case, the Reset was due to some event other than a Deep Sleep mode exit. • The DPSLP bit is clear, but the POR bit is set; this is a normal POR. • Both the DPSLP and POR bits are set. This means that Deep Sleep mode was entered, the device was powered down and Deep Sleep mode was exited. DS39995D-page 128  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY DSCON: DEEP SLEEP CONTROL REGISTER(1) REGISTER 10-1: R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 DSEN — — — — — — RTCCWDIS bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/C-0, HS — — — — — ULPWUDIS DSBOR(2) RELEASE bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DSEN: Deep Sleep Enable bit 1 = Enters Deep Sleep on execution of PWRSAV #0 0 = Enters normal Sleep on execution of PWRSAV #0 bit 14-9 Unimplemented: Read as ‘0’ bit 8 RTCCWDIS: RTCC Wake-up Disable bit 1 = Wake-up from Deep Sleep with RTCC disabled 0 = Wake-up from Deep Sleep with RTCC enabled bit 7-3 Unimplemented: Read as ‘0’ bit 2 ULPWUDIS: ULPWU Wake-up Disable bit 1 = Wake-up from Deep Sleep with ULPWU disabled 0 = Wake-up from Deep Sleep with ULPWU enabled bit 1 DSBOR: Deep Sleep BOR Event bit(2) 1 = The DSBOR was active and a BOR event was detected during Deep Sleep 0 = The DSBOR was not active or was active but did not detect a BOR event during Deep Sleep bit 0 RELEASE: I/O Pin State Release bit 1 = Upon waking from Deep Sleep, I/O pins maintain their previous states to Deep Sleep entry 0 = Release I/O pins from their state previous to Deep Sleep entry, and allow their respective TRISx and LATx bits to control their states Note 1: 2: All register bits are only reset in the case of a POR event outside of Deep Sleep mode. Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this re-arms POR.  2011-2013 Microchip Technology Inc. DS39995D-page 129 PIC24FV32KA304 FAMILY DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER(1) REGISTER 10-2: U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — DSINT0 bit 15 bit 8 R/W-0, HS U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 R/W-0, HS DSFLT — — DSWDT DSRTCC DSMCLR — DSPOR(2,3) bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 DSINT0: Deep Sleep Interrupt-on-Change bit 1 = Interrupt-on-change was asserted during Deep Sleep 0 = Interrupt-on-change was not asserted during Deep Sleep bit 7 DSFLT: Deep Sleep Fault Detect bit 1 = A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been corrupted 0 = No Fault was detected during Deep Sleep bit 6-5 Unimplemented: Read as ‘0’ bit 4 DSWDT: Deep Sleep Watchdog Timer Time-out bit 1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep 0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep bit 3 DSRTCC: Deep Sleep Real-Time Clock and Calendar (RTCC) Alarm bit 1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep 0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep bit 2 DSMCLR: Deep Sleep MCLR Event bit 1 = The MCLR pin was active and was asserted during Deep Sleep 0 = The MCLR pin was not active, or was active, but not asserted during Deep Sleep bit 1 Unimplemented: Read as ‘0’ bit 0 DSPOR: Deep Sleep Power-on Reset Event bit(2,3) 1 = The VDD supply POR circuit was active and a POR event was detected 0 = The VDD supply POR circuit was not active, or was active, but did not detect a POR event Note 1: 2: 3: All register bits are cleared when the DSEN (DSCON) bit is set. All register bits are reset only in the case of a POR event outside of Deep Sleep mode, except bit, DSPOR, which does not reset on a POR event that is caused due to a Deep Sleep exit. Unlike the other bits in this register, this bit can be set outside of Deep Sleep. DS39995D-page 130  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 10.3 Ultra Low-Power Wake-up The Ultra Low-Power Wake-up (ULPWU) on pin, RB0, allows a slow falling voltage to generate an interrupt without excess current consumption. To use this feature: 1. 2. 3. 4. 5. Charge the capacitor on RB0 by configuring the RB0 pin to an output and setting it to ‘1’. Stop charging the capacitor by configuring RB0 as an input. Discharge the capacitor by setting the ULPEN and ULPSINK bits in the ULPWCON register. Configure Sleep mode. Enter Sleep mode. When the voltage on RB0 drops below VIL, the device wakes up and executes the next instruction. This feature provides a low-power technique for periodically waking up the device from Sleep mode. The time-out is dependent on the discharge time of the RC circuit on RB0. When the ULPWU module wakes the device from Sleep mode, the ULPWUIF bit (IFS5) is set. Software can check this bit upon wake-up to determine the wake-up source. See Example 10-3 for initializing the ULPWU module. A series resistor, between RB0 and the external capacitor, provides overcurrent protection for the RB0/AN0/ULPWU pin and enables software calibration of the time-out (see Figure 10-1). FIGURE 10-1: RB0 EXAMPLE 10-3: ULTRA LOW-POWER WAKE-UP INITIALIZATION //******************************* // 1. Charge the capacitor on RB0 //******************************* TRISBbits.TRISB0 = 0; LATBbits.LATB0 = 1; for(i = 0; i < 10000; i++) Nop(); //***************************** //2. Stop Charging the capacitor // on RB0 //***************************** TRISBbits.TRISB0 = 1; //***************************** //3. Enable ULPWU Interrupt //***************************** IFS5bits.ULPWUIF = 0; IEC5bits.ULPWUIE = 1; IPC21bits.ULPWUIP = 0x7; //***************************** //4. Enable the Ultra Low Power // Wakeup module and allow // capacitor discharge //***************************** ULPWCONbits.ULPEN = 1; ULPWCONbit.ULPSINK = 1; //***************************** //5. Enter Sleep Mode //***************************** Sleep(); //for sleep, execution will //resume here SERIES RESISTOR R1 C1 A timer can be used to measure the charge time and discharge time of the capacitor. The charge time can then be adjusted to provide the desired delay in Sleep. This technique compensates for the affects of temperature, voltage and component accuracy. The peripheral can also be configured as a simple, programmable Low-Voltage Detect (LVD) or temperature sensor.  2011-2013 Microchip Technology Inc. DS39995D-page 131 PIC24FV32KA304 FAMILY REGISTER 10-3: ULPWCON: ULPWU CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 ULPEN — ULPSIDL — — — — ULPSINK bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ULPEN: ULPWU Module Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ULPSIDL: ULPWU Stop in Idle Select bit 1 = Discontinues module operation when the device enters Idle mode 0 = Continues module operation in Idle mode bit 12-9 Unimplemented: Read as ‘0’ bit 8 ULPSINK: ULPWU Current Sink Enable bit 1 = Current sink is enabled 0 = Current sink is disabled bit 7-0 Unimplemented: Read as ‘0’ DS39995D-page 132  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 10.4 Voltage Regulator-Based Power-Saving Features 10.4.3 The PIC24FV32KA304 series devices have a Voltage Regulator that has the ability to alter functionality to provide power savings. The on-board regulator is made up of two basic modules: the Voltage Regulator (VREG) and the Retention Regulator (RETREG). With the combination of VREG and RETREG, the following power modes are available: 10.4.1 In Run mode, the main VREG is providing a regulated voltage with enough current to supply a device running at full speed, and the device is not in Sleep or Deep Sleep Mode. The Retention Regulator may or may not be running, but is unused. 10.4.2 SLEEP (STANDBY) MODE In Sleep mode, the device is in Sleep and the main VREG is providing a regulated voltage at a reduced (standby) supply current. This mode provides for limited functionality due to the reduced supply current. It requires a longer time to wake-up from Sleep. TABLE 10-1: In Retention Sleep mode, the device is in Sleep and all regulated voltage is provided solely by the Retention Regulator. Consequently, this mode has lower power consumption than regular Sleep mode, but is also limited in terms of how much functionality can be enabled. Retention Sleep wake-up time is longer than Sleep mode due to the extra time required to raise the VCORE supply rail back to normal regulated levels. Note: RUN MODE RETENTION SLEEP MODE 10.4.4 PIC24F32KA30X family devices do not use an On-Chip Voltage Regulator, so they do not support Retention Sleep mode. DEEP SLEEP MODE In Deep Sleep mode, both the main Voltage Regulator and Retention Regulator are shut down, providing the lowest possible device power consumption. However, this mode provides no retention or functionality of the device and has the longest wake-up time. VOLTAGE REGULATION CONFIGURATION SETTINGS FOR PIC24FV32KA304 FAMILY DEVICES RETCGF Bit (FPOR) RETEN Bit (RCON PMSLP Bit (RCON) Power Mode During Sleep 0 0 1 Sleep 0 0 0 Sleep (Standby) VREG goes to Low-Power Standby mode during Sleep. RETREG is unused. 0 1 0 Retention Sleep VREG is off during Sleep. RETREG is enabled and provides Sleep voltage regulation. 1 X 1 Sleep VREG mode (normal) is unchanged during Sleep. RETREG is disabled at all times. 1 X 0 Sleep (Standby)  2011-2013 Microchip Technology Inc. Description VREG mode (normal) is unchanged during Sleep. RETREG is unused. VREG goes to Low-Power Standby mode during Sleep. RETREG is disabled at all times DS39995D-page 133 PIC24FV32KA304 FAMILY 10.5 Doze Mode Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely. Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed, while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. Doze mode is enabled by setting the DOZEN bit (CLKDIV). The ratio between peripheral and core clock speed is determined by the DOZE bits (CLKDIV). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default. It is also possible to use Doze mode to selectively reduce power consumption in event driven applications. This allows clock-sensitive functions, such as synchronous communications, to continue without interruption. Meanwhile, the CPU Idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV). By default, interrupt events have no effect on Doze mode operation. 10.6 Selective Peripheral Module Control Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock. Even so, peripheral modules still remain clocked, and thus, consume power. There may be cases where the application needs what these modes do not provide: the allocation of power resources to CPU processing, with minimal power consumption from the peripherals. PIC24F devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with two control bits: • The Peripheral Enable bit, generically named, “XXXEN”, located in the module’s main control SFR. • The Peripheral Module Disable (PMD) bit, generically named, “XXXMD”, located in one of the PMD Control registers. Both bits have similar functions in enabling or disabling its associated module. Setting the PMDx bits for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. In this state, the control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect, and read values will be invalid. Many peripheral modules have a corresponding PMDx bit. In contrast, disabling a module by clearing its XXXEN bit, disables its functionality, but leaves its registers available to be read and written to. Power consumption is reduced, but not by as much as the PMDx bits are used. Most peripheral modules have an enable bit; exceptions include capture, compare and RTCC. To achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters Idle mode. This is done through the control bit of the generic name format, “XXXIDL”. By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature disables the module while in Idle mode, allowing further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications. DS39995D-page 134  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 11.0 Note: I/O PORTS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the I/O Ports, refer to the “PIC24F Family Reference Manual”, Section 12. “I/O Ports with Peripheral Pin Select (PPS)” (DS39711). Note that the PIC24FV32KA304 family devices do not support Peripheral Pin Select features. All of the device pins (except VDD and VSS) are shared between the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity. 11.1 Parallel I/O (PIO) Ports A parallel I/O port that shares a pin with a peripheral is, in general, subservient to the peripheral. The peripheral’s output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. Figure 11-1 illustrates how ports are shared with other peripherals and the associated I/O pin to which they are connected. FIGURE 11-1: When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. All port pins have three registers directly associated with their operation as digital I/O. The Data Direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the Data Latch register (LAT), read the latch. Writes to the latch, write the latch. Reads from the port (PORT), read the port pins; writes to the port pins, write the latch. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers, and the port pin will read as zeros. When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. Note: The I/O pins retain their state during Deep Sleep. They will retain this state at wake-up until the software restore bit (RELEASE) is cleared. BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module WR TRIS Output Enable 0 1 Output Data 0 Read TRIS Data Bus I/O 1 D Q I/O Pin CK TRIS Latch D WR LAT + WR PORT Q CK Data Latch Read LAT Input Data Read PORT  2011-2013 Microchip Technology Inc. DS39995D-page 135 PIC24FV32KA304 FAMILY 11.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The maximum open-drain voltage allowed is the same as the maximum VIH specification. 11.2 Configuring Analog Port Pins The use of the ANS and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRISx bit set (input). If the TRISx bit is cleared (output), the digital output level (VOH or VOL) will be converted. REGISTER 11-1: When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. 11.2.1 ANALOG SELECTION REGISTERS I/O pins with shared analog functionality, such as A/D inputs and comparator inputs, must have their digital inputs shut off when analog functionality is used. Note that analog functionality includes an analog voltage being applied to the pin externally. To allow for analog control, the ANSx registers are provided. There is one ANS register for each port (ANSA, ANSB and ANSC). Within each ANSx register, there is a bit for each pin that shares analog functionality with the digital I/O functionality. If a particular pin does not have an analog function, that bit is unimplemented. See Register 11-1 to Register 11-3 for implementation. ANSA: ANALOG SELECTION (PORTA) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — — — ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3-0 ANSA: Analog Select Control bits 1 = Digital input buffer is not active (use for analog input) 0 = Digital input buffer is active DS39995D-page 136 x = Bit is unknown  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 11-2: ANSB: ANALOG SELECTION (PORTB) R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 ANSB15 ANSB14 ANSB13 ANSB12 — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — ANSB4 ANSB3(1) ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 ANSB: Analog Select Control bits 1 = Digital input buffer is not active (use for analog input) 0 = Digital input buffer is active bit 11-5 Unimplemented: Read as ‘0’ bit 4-0 ANSB: Analog Select Control bits(1) 1 = Digital input buffer is not active (use for analog input) 0 = Digital input buffer is active Note 1: x = Bit is unknown The ANSB3 bit is not available on 20-pin devices. REGISTER 11-3: ANSC ANALOG SELECTION (PORTC) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 — — — — — ANSC2(1) ANSC1(1) ANSC0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 ANSC: Analog Select Control bits(1) 1 = Digital input buffer is not active (use for analog input) 0 = Digital input buffer is active Note 1: x = Bit is unknown These bits are not available on 20-pin or 28-pin devices.  2011-2013 Microchip Technology Inc. DS39995D-page 137 PIC24FV32KA304 FAMILY 11.2.2 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. 11.3 Input Change Notification (ICN) The Input Change Notification function of the I/O ports allows the PIC24FV32KA304 family of devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature is capable of detecting input Change-of-States, even in Sleep mode, when the clocks are disabled. Depending on the device pin count, there are up to 23 external signals (CN0 through CN22) that may be selected (enabled) for generating an interrupt request on a Change-of-State. There are six control registers associated with the ICN module. The CNEN1 and CNEN2 registers contain the interrupt enable control bits for each of the CN input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. Each CN pin also has a weak pull-up/pull-down connected to it. The pull-ups act as a current source that is connected to the pin. The pull-downs act as a current sink to eliminate the need for external resistors when push button or keypad devices are connected. EXAMPLE 11-1: MOV MOV NOP; BTSS Setting any of the control bits enables the weak pull-ups for the corresponding pins. The pull-downs are enabled separately, using the CNPD1 and CNPD2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-downs for the corresponding pins. When the internal pull-up is selected, the pin uses VDD as the pull-up source voltage. When the internal pull-down is selected, the pins are pulled down to VSS by an internal resistor. Make sure that there is no external pull-up source/pull-down sink when the internal pull-ups/pull-downs are enabled. Note: Pull-ups and pull-downs on Change Notification pins should always be disabled whenever the port pin is configured as a digital output. PORT WRITE/READ EXAMPLE 0xFF00, W0; W0, TRISB; PORTB, #13; Equivalent ‘C’ Code TRISB = 0xFF00; NOP(); if(PORTBbits.RB13 == 1) { } DS39995D-page 138 On any pin, only the pull-up resistor or the pull-down resistor should be enabled, but not both of them. If the push button or the keypad is connected to VDD, enable the pull-down, or if they are connected to VSS, enable the pull-up resistors. The pull-ups are enabled separately, using the CNPU1 and CNPU2 registers, which contain the control bits for each of the CN pins. //Configure PORTB as inputs and PORTB as outputs //Delay 1 cycle //Next Instruction //Configure PORTB as inputs and PORTB as outputs //Delay 1 cycle // execute following code if PORTB pin 13 is set.  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 12.0 TIMER1 Note: Figure 12-1 illustrates a block diagram of the 16-bit Timer1 module. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Timers, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). To configure Timer1 for operation: 1. 2. 3. 4. The Timer1 module is a 16-bit timer which can serve as the time counter for the Real-Time Clock (RTC) or operate as a free-running, interval timer/counter. Timer1 can operate in three modes: 5. 6. • 16-Bit Timer • 16-Bit Synchronous Counter • 16-Bit Asynchronous Counter Set the TON bit (= 1). Select the timer prescaler ratio using the TCKPS bits. Set the Clock and Gating modes using the TCS and TGATE bits. Set or clear the TSYNC bit to configure synchronous or asynchronous operation. Load the timer period value into the PR1 register. If interrupts are required, set the Timer1 Interrupt Enable bit, T1IE. Use the Timer1 Interrupt Priority bits, T1IP, to set the interrupt priority. Timer1 also supports these features: • Timer Gate Operation • Selectable Prescaler Settings • Timer Operation During CPU Idle and Sleep modes • Interrupt on 16-Bit Period Register Match or Falling Edge of External Gate Signal FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM T1ECS LPRC TCKPS 2 TON SOSCO Prescaler 1, 8, 64, 256 Gate Sync SOSCI SOSCEN TGATE TCS T1CK FOSC/2 TGATE Set T1IF Reset Q D Q CK TMR1 Sync Equal Comparator TSYNC PR1  2011-2013 Microchip Technology Inc. DS39995D-page 139 PIC24FV32KA304 FAMILY REGISTER 12-1: R/W-0 T1CON: TIMER1 CONTROL REGISTER U-0 — TON R/W-0 TSIDL U-0 — U-0 U-0 — — R/W-0 T1ECS1 R/W-0 (1) T1ECS0(1) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timer1 Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 T1ECS: Timer1 Extended Clock Select bits(1) 11 = Reserved; do not use 10 = Timer1 uses the LPRC as the clock source 01 = Timer1 uses the external clock from T1CK 00 = Timer1 uses the Secondary Oscillator (SOSC) as the clock source bit 7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronizes external clock input 0 = Does not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = Timer1 clock source is selected by T1ECS 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: The T1ECSx bits are valid only when TCS = 1. DS39995D-page 140  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 13.0 Note: TIMER2/3 AND TIMER4/5 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Timers, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as four independent,16-bit timers with selectable operating modes. As a 32-bit timer, Timer2/3 or Timer4/5 operate in three modes: • Two Independent 16-Bit Timers (Timer2 and Timer3) with all 16-Bit Operating modes (except Asynchronous Counter mode) • Single 32-Bit Timer • Single 32-Bit Synchronous Counter To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. 2. 3. 4. 5. 6. Set the T32 bit (T2CON or T4CON = 1). Select the prescaler ratio for Timer2 or Timer4 using the TCKPS bits. Set the Clock and Gating modes using the TCS and TGATE bits. Load the timer period value. PR3 (or PR5) will contain the most significant word of the value, while PR2 (or PR4) contains the least significant word. If interrupts are required, set the Timerx Interrupt Enable bit, TxIE. Use the Timerx Interrupt Priority bits, TxIP, to set the interrupt priority. Set the TON bit (TxCON = 1). The timer value, at any point, is stored in the register pair, TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5) always contains the most significant word of the count, while TMR2 (TMR4) contains the least significant word. They also support these features: • Timer Gate Operation • Selectable Prescaler Settings • Timer Operation during Idle mode • Interrupt on a 32-Bit Period Register Match • A/D Event Trigger To configure any of the timers for individual 16-bit operation: Individually, all four of the 16-bit timers can function as synchronous timers or counters. They also offer the features listed above, except for the A/D event trigger (this is implemented only with Timer3). The operating modes and enabled features are determined by setting the appropriate bit(s) in the T2CON, T3CON, T4CON and T5CON registers. The T2CON,T3CON, T4CON and T5CON registers are provided in generic form in Register 13-1 and Register 13-2, respectively. 3. 1. 2. 4. 5. 6. Clear the T32 bit corresponding to that timer (T2CON for Timer2 and Timer3 or T4CON for Timer4 and Timer5). Select the timer prescaler ratio using the TCKPS bits. Set the Clock and Gating modes using the TCS and TGATE bits. Load the timer period value into the PRx register. If interrupts are required, set the Timerx Interrupt Enable bit, TxIE; use the Timerx Interrupt Priority bits, TxIP, to set the interrupt priority. Set the TON bit (TxCON = 1). For 32-bit timer/counter operation, Timer2/Timer4 is the least significant word (lsw) and Timer3/Timer5 is the most significant word (msw) of the 32-bit timer. Note: For 32-bit operation, T3CON or T5CON control bits are ignored. Only T2CON or T4CON control bits are used for setup and control. Timer2 or Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags.  2011-2013 Microchip Technology Inc. DS39995D-page 141 PIC24FV32KA304 FAMILY FIGURE 13-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM TCKPS 2 TON T2CK (T4CK) Prescaler 1, 8, 64, 256 Gate Sync TCY TGATE TGATE TCS 1 Q Set T3IF (T5IF) Q 0 PR3 (PR5) A/D Event Trigger(2) Equal D CK PR2 (PR4) Comparator MSB LSB TMR3 (TMR5) Reset TMR2 (TMR4) Sync 16 Read TMR2 (TMR4) (1) Write TMR2 (TMR4)(1) 16 TMR3HLD (TMR5HLD) 16 Data Bus Note 1: 2: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers. The A/D event trigger is available only on Timer2/3 and Timer4/5 in 32-bit mode, and Timer3 and Timer5 in 16-bit mode. DS39995D-page 142  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 13-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TCKPS TON T2CK (T4CK) Gate Sync 2 Prescaler 1, 8, 64, 256 TGATE TCS TCY 1 Set T2IF (T4IF) 0 Reset Equal Q D Q CK TGATE Sync TMR2 (TMR4) Comparator PR2 (PR4) FIGURE 13-3: TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM T3CK (T5CK) TON Sync TCKPS 2 Prescaler 1, 8, 64, 256 TGATE TCY Set T3IF (T5IF) 1 0 Reset A/D Event Trigger Equal Q D Q CK TCS TGATE TMR3 (TMR5) Comparator PR3 (PR5)  2011-2013 Microchip Technology Inc. DS39995D-page 143 PIC24FV32KA304 FAMILY REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 TCKPS1 R/W-0 R/W-0 U-0 R/W-0 U-0 TCKPS0 T32(1) — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timerx On bit When TxCON = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When TxCON = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timerx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS: Timerx Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 T32: 32-Bit Timer Mode Select bit(1) 1 = Timer2 and Timer3 or Timer4 and Timer5 form a single 32-bit timer 0 = Timer2 and Timer3 or Timer4 and Timer5 act as two 16-bit timers bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit 1 = External clock from pin, TxCK (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation. DS39995D-page 144  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 13-2: R/W-0 TON (1) TyCON: TIMER3 AND TIMER5 CONTROL REGISTER U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 — TGATE(1) TCKPS1(1) TCKPS0(1) U-0 — U-0 R/W-0 U-0 — TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timery Stop in Idle Mode bit(1) 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS: Timery Input Clock Prescale Select bits(1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timery Clock Source Select bit(1) 1 = External clock is from the T3CK pin (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown When 32-bit operation is enabled (TxCON = 1), these bits have no effect on Timery operation. All timer functions are set through the TxCON register.  2011-2013 Microchip Technology Inc. DS39995D-page 145 PIC24FV32KA304 FAMILY NOTES: DS39995D-page 146  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 14.0 INPUT CAPTURE WITH DEDICATED TIMERS Note: 14.1 14.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 34. “Input Capture with Dedicated Timer” (DS39722). All devices in the PIC24FV32KA304 family feature three independent input capture modules. Each of the modules offers a wide range of configuration and operating options for capturing external pulse events, and generating interrupts. Key features of the input capture module include: • Hardware-configurable for 32-bit operation in all modes by cascading two adjacent modules • Synchronous and Trigger modes of output compare operation, with up to 20 user-selectable Sync/trigger sources available • A 4-level FIFO buffer for capturing and holding timer values for several events • Configurable interrupt generation • Up to 6 clock sources available for each module, driving a separate internal 16-bit counter The module is controlled through two registers: ICxCON1 (Register 14-1) and ICxCON2 (Register 14-2). A general block diagram of the module is shown in Figure 14-1. FIGURE 14-1: SYNCHRONOUS AND TRIGGER MODES By default, the input capture module operates in a Free-Running mode. The internal 16-bit counter, ICxTMR, counts up continuously, wrapping around from FFFFh to 0000h on each overflow, with its period synchronized to the selected external clock source. When a capture event occurs, the current 16-bit value of the internal counter is written to the FIFO buffer. In Synchronous mode, the module begins capturing events on the ICx pin as soon as its selected clock source is enabled. Whenever an event occurs on the selected Sync source, the internal counter is reset. In Trigger mode, the module waits for a Sync event from another internal module to occur before allowing the internal counter to run. Standard, free-running operation is selected by setting the SYNCSELx bits to ‘00000’ and clearing the ICTRIG bit (ICxCON2). Synchronous and Trigger modes are selected any time the SYNCSELx bits are set to any value except ‘00000’. The ICTRIG bit selects either Synchronous or Trigger mode; setting the bit selects Trigger mode operation. In both modes, the SYNCSELx bits determine the Sync/trigger source. When the SYNCSELx bits are set to ‘00000’ and ICTRIG is set, the module operates in Software Trigger mode. In this case, capture operations are started by manually setting the TRIGSTAT bit (ICxCON2). INPUT CAPTURE x BLOCK DIAGRAM ICM ICx Pin General Operating Modes ICI Edge Detect Logic and Clock Synchronizer Prescaler Counter 1:1/4/16 Event and Interrupt Logic Set ICxIF ICTSEL IC Clock Sources Trigger and Sync Sources Clock Select Increment 16 ICxTMR 4-Level FIFO Buffer 16 16 Trigger and Reset Sync Logic ICxBUF SYNCSEL Trigger ICOV, ICBNE  2011-2013 Microchip Technology Inc. System Bus DS39995D-page 147 PIC24FV32KA304 FAMILY 14.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, Modules 1 and 2 are paired, as are Modules 3 and 4, and so on.) The odd numbered module (ICx) provides the Least Significant 16 bits of the 32-bit register pairs, and the even numbered module (ICy) provides the Most Significant 16 bits. Wraparounds of the ICx registers cause an increment of their corresponding ICy registers. Cascaded operation is configured in hardware by setting the IC32 bit (ICxCON2) for both modules. 14.2 For 32-bit cascaded operations, the setup procedure is slightly different: 1. 2. 3. Capture Operations The input capture module can be configured to capture timer values and generate interrupts on rising edges on ICx or all transitions on ICx. Captures can be configured to occur on all rising edges or just some (every 4th or 16th). Interrupts can be independently configured to generate on each event or a subset of events. 4. 5. Note: To set up the module for capture operations: 1. 2. 3. 4. 5. 6. 7. 8. If Synchronous mode is to be used, disable the Sync source before proceeding. Make sure that any previous data has been removed from the FIFO by reading ICxBUF until the ICBNE bit (ICxCON1) is cleared. Set the SYNCSELx bits (ICxCON2) to the desired Sync/trigger source. Set the ICTSELx bits (ICxCON1) for the desired clock source. If the desired clock source is running, set the ICTSELx bits before the input capture module is enabled, for proper synchronization with the desired clock source. Set the ICIx bits (ICxCON1) to the desired interrupt frequency. Select Synchronous or Trigger mode operation: a) Check that the SYNCSELx bits are not set to ‘00000’. b) For Synchronous mode, clear the ICTRIG bit (ICxCON2). c) For Trigger mode, set ICTRIG and clear the TRIGSTAT bit (ICxCON2). Set the ICMx bits (ICxCON1) to the desired operational mode. Enable the selected Sync/trigger source. DS39995D-page 148 Set the IC32 bits for both modules (ICyCON2 and (ICxCON2), enabling the even numbered module first. This ensures the modules will start functioning in unison. Set the ICTSELx and SYNCSELx bits for both modules to select the same Sync/trigger and time base source. Set the even module first, then the odd module. Both modules must use the same ICTSELx and SYNCSELx bit settings. Clear the ICTRIG bit of the even module (ICyCON2). This forces the module to run in Synchronous mode with the odd module, regardless of its trigger setting. Use the odd module’s ICIx bits (ICxCON1) to the desired interrupt frequency. Use the ICTRIG bit of the odd module (ICxCON2) to configure Trigger or Synchronous mode operation. 6. For Synchronous mode operation, enable the Sync source as the last step. Both input capture modules are held in Reset until the Sync source is enabled. Use the ICMx bits of the odd module (ICxCON1) to set the desired capture mode. The module is ready to capture events when the time base and the Sync/trigger source are enabled. When the ICBNE bit (ICxCON1) becomes set, at least one capture value is available in the FIFO. Read input capture values from the FIFO until the ICBNE clears to ‘0’. For 32-bit operation, read both the ICxBUF and ICyBUF for the full 32-bit timer value (ICxBUF for the lsw, ICyBUF for the msw). At least one capture value is available in the FIFO buffer when the odd module’s ICBNE bit (ICxCON1) becomes set. Continue to read the buffer registers until ICBNE is cleared (performed automatically by hardware).  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 14-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — bit 15 bit 8 U-0 R/W-0 R/W-0 R-0, HSC R-0, HSC R/W-0 R/W-0 R/W-0 — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture x Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode bit 12-10 ICTSEL: Input Capture x Timer Select bits 111 = System clock (FOSC/2) 110 = Reserved 101 = Reserved 100 = Timer1 011 = Timer5 010 = Timer4 001 = Timer2 000 = Timer3 bit 9-7 Unimplemented: Read as ‘0’ bit 6-5 ICI: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture x Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM: Input Capture Mode Select bits 111 = Interrupt mode: Input capture functions as an interrupt pin only when the device is in Sleep or Idle mode (rising edge detect only, all other control bits are not applicable) 110 = Unused (module disabled) 101 = Prescaler Capture mode: Capture on every 16th rising edge 100 = Prescaler Capture mode: Capture on every 4th rising edge 011 = Simple Capture mode: Capture on every rising edge 010 = Simple Capture mode: Capture on every falling edge 001 = Edge Detect Capture mode: Capture on every edge (rising and falling); ICI 7 or 16 when PLEN 7. bit 7 CRCFUL: CRC FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: CRC FIFO Empty Bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 CRCISEL: CRC interrupt Selection bit 1 = Interrupt on FIFO is empty; CRC calculation is not complete 0 = Interrupt on shift is complete and CRCWDAT result is ready bit 4 CRCGO: Start CRC bit 1 = Starts CRC serial shifter 0 = CRC serial shifter is turned off bit 3 LENDIAN: Data Shift Direction Select bit 1 = Data word is shifted into the CRC, starting with the LSb (little endian) 0 = Data word is shifted into the CRC, starting with the MSb (big endian) bit 2-0 Unimplemented: Read as ‘0’ DS39995D-page 202  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 20-2: CRCCON2: CRC CONTROL REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 DWIDTH: Data Width Select bits Defines the width of the data word (Data Word Width = (DWIDTH) + 1). bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 PLEN: Polynomial Length Select bits Defines the length of the CRC polynomial (Polynomial Length = (PLEN) + 1).  2011-2013 Microchip Technology Inc. DS39995D-page 203 PIC24FV32KA304 FAMILY REGISTER 20-3: CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X15 X14 X13 X12 X11 X10 X9 X8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 X7 X6 X5 X4 X3 X2 X1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 X: XOR of Polynomial Term Xn Enable bits bit 0 Unimplemented: Read as ‘0’ REGISTER 20-4: x = Bit is unknown CRCXORH: CRC XOR POLYNOMIAL REGISTER, HIGH BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X31 X30 X29 X28 X27 X26 X25 X24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X23 X22 X21 X20 X19 X18 X17 X16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown X: XOR of Polynomial Term Xn Enable bits DS39995D-page 204  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 21.0 HIGH/LOW-VOLTAGE DETECT (HLVD) Note: An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the High/Low-Voltage Detect, refer to the “PIC24F Family Reference Manual”, Section 36. “High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)” (DS39725). The HLVD Control register (see Register 21-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned off” by the user under software control, which minimizes the current consumption for the device. The High/Low-Voltage Detect module (HLVD) is a programmable circuit that allows the user to specify both the device voltage trip point and the direction of change. FIGURE 21-1: VDD HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM Externally Generated Trip Point VDD HLVDIN HLVDL 16-to-1 MUX HLVDEN - VDIR Set HLVDIF Internal Voltage Reference 1.024V Typical HLVDEN  2011-2013 Microchip Technology Inc. DS39995D-page 205 PIC24FV32KA304 FAMILY REGISTER 21-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 HLVDEN — HLSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD is enabled 0 = HLVD is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 HLSIDL: HLVD Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 VDIR: Voltage Change Direction Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL) 0 = Event occurs when voltage equals or falls below trip point (HLVDL) bit 6 BGVST: Band Gap Voltage Stable Flag bit 1 = Indicates that the band gap voltage is stable 0 = Indicates that the band gap voltage is unstable bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the internal reference voltage is stable and the high-voltage detect logic generates the interrupt flag at the specified voltage range 0 = Indicates that the internal reference voltage is unstable and the high-voltage detect logic will not generate the interrupt flag at the specified voltage range, and the HLVD interrupt should not be enabled bit 4 Unimplemented: Read as ‘0’ bit 3-0 HLVDL: High/Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Trip Point 1(1) 1101 = Trip Point 2(1) 1100 = Trip Point 3(1) . . . 0000 = Trip Point 15(1) Note 1: For the actual trip point, see Section 29.0 “Electrical Characteristics”. DS39995D-page 206  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 22.0 Note: 12-BIT A/D CONVERTER WITH THRESHOLD DETECT This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the 12-Bit A/D Converter with Threshold Detect, refer to the “PIC24F Family Reference Manual”, Section 51. “12-Bit A/D Converter with Threshold Detect” (DS39739). The PIC24F 12-bit A/D Converter has the following key features: • Successive Approximation Register (SAR) Conversion • Conversion Speeds of up to 100 ksps • Up to 32 Analog Input Channels (Internal and External) • Multiple Internal Reference Input Channels • External Voltage Reference Input Pins • Unipolar Differential Sample-and-Hold (S/H) Amplifier • Automated Threshold Scan and Compare Operation to Pre-Evaluate Conversion Results • Selectable Conversion Trigger Source • Fixed-Length (one word per channel), Configurable Conversion Result Buffer • Four Options for Results Alignment • Configurable Interrupt Generation • Operation During CPU Sleep and Idle modes  2011-2013 Microchip Technology Inc. The 12-bit A/D Converter module is an enhanced version of the 10-bit module offered in some PIC24 devices. Both modules are Successive Approximation Register (SAR) converters at their cores, surrounded by a range of hardware features for flexible configuration. This version of the module extends functionality by providing 12-bit resolution, a wider range of automatic sampling options and tighter integration with other analog modules, such as the CTMU and a configurable results buffer. This module also includes a unique Threshold Detect feature that allows the module itself to make simple decisions based on the conversion results. A simplified block diagram for the module is illustrated in Figure 22-1. DS39995D-page 207 PIC24FV32KA304 FAMILY FIGURE 22-1: 12-BIT A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVSS VREF+ VREF- VR Select AVDD VR+ 16 VR- VBG Comparator VINH VINL AN0 VRS/H VR+ DAC AN1 12-Bit SAR AN2 Conversion Logic AN3 Data Formatting AN4 VINH AN6 AN7 ADC1BUF0: ADC1BUF17 MUX A AN5 AN8 AD1CON1 AD1CON2 VINL AN9 AD1CON3 AD1CON5 AD1CHS AD1CHITL AN15 CTMU Temp. Sensor CTMU MUX B AN14 AD1CHITH AD1CSSL AD1CSSH VINH VINL Sample Control VBG 0.785 * VDD Control Logic Conversion Control Input MUX Control Pin Config. Control 0.215 * VDD AVDD AVss DS39995D-page 208  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY To perform an A/D conversion: 1. 2. Configure the A/D module: a) Configure the port pins as analog inputs and/or select band gap reference inputs (ANS, ANS). b) Select voltage reference source to match the expected range on the analog inputs (AD1CON2). c) Select the analog conversion clock to match the desired data rate with the processor clock (AD1CON3). d) Select the appropriate sample/conversion sequence (AD1CON1 and AD1CON3). e) Select how conversion results are presented in the buffer (AD1CON1). f) Select the interrupt rate (AD1CON2). g) Turn on the A/D module (AD1CON1). Configure the A/D interrupt (if required): a) Clear the AD1IF bit. b) Select the A/D interrupt priority. To perform an A/D sample and conversion using Threshold Detect scanning: 1. 2. Configure the A/D module: a) Configure the port pins as analog inputs (ANS, ANS). b) Select the voltage reference source to match the expected range on the analog inputs (AD1CON2). c) Select the analog conversion clock to match the desired data rate with the processor clock (AD1CON3). d) Select the appropriate sample/conversion sequence (AD1CON1, AD1CON3). e) Select how the conversion results are presented in the buffer (AD1CON1). f) Select the interrupt rate (AD1CON2). Configure the threshold compare channels: a) Enable auto-scan – ASEN bit (AD1CON5). b) Select the Compare mode, “Greater Than, Less Than or Windowed” – CMx bits (AD1CON5). c) Select the threshold compare channels to be scanned (ADCSSH, ADCSSL). d) If the CTMU is required as a current source for a threshold compare channel, enable the corresponding CTMU channel (ADCCTMUENH, ADCCTMUENL). e) Write the threshold values into the corresponding ADC1BUFn registers. f) Turn on the A/D module (AD1CON1). Note: 3.  2011-2013 Microchip Technology Inc. If performing an A/D sample and conversion using Threshold Detect in Sleep Mode, the RC A/D clock source must be selected before entering into Sleep mode. Configure the A/D interrupt (OPTIONAL): a) Clear the AD1IF bit. b) Select the A/D interrupt priority. DS39995D-page 209 PIC24FV32KA304 FAMILY 22.1 A/D Control Registers The 12-bit A/D Converter module uses up to 43 registers for its operation. All registers are mapped in the data memory space. 22.1.1 CONTROL REGISTERS Depending on the specific device, the module has up to eleven control and status registers: • • • • • • AD1CON1: A/D Control Register 1 AD1CON2: A/D Control Register 2 AD1CON3: A/D Control Register 3 AD1CON5: A/D Control Register 5 AD1CHS: A/D Sample Select Register AD1CHITH and AD1CHITL: A/D Scan Compare Hit Registers • AD1CSSL and AD1CSSH: A/D Input Scan Select Registers • AD1CTMUENH and AD1CTMUENL: CTMU Enable Registers The AD1CON1, AD1CON2 and AD1CON3 registers (Register 22-1, Register 22-2 and Register 22-3) control the overall operation of the A/D module. This includes enabling the module, configuring the conversion clock and voltage reference sources, selecting the sampling and conversion triggers, and manually controlling the sample/convert sequences. The AD1CON5 register (Register 22-4) specifically controls features of the Threshold Detect operation, including its function in power-saving modes. The AD1CHS register (Register 22-5) selects the input channels to be connected to the S/H amplifier. It also allows the choice of input multiplexers and the selection of a reference source for differential sampling. The AD1CHITH and AD1CHITL registers (Register 22-6 and Register 22-7) are semaphore registers used with Threshold Detect operations. The status of individual bits, or bit pairs in some cases, DS39995D-page 210 indicate if a match condition has occurred. AD1CHITL is always implemented, whereas AD1CHITH may not be implemented in devices with 16 or fewer channels. The AD1CSSH/L registers (Register 22-8 and Register 22-9) select the channels to be included for sequential scanning. The AD1CTMUENH/L registers (Register 22-10 and Register 22-11) select the channel(s) to be used by the CTMU during conversions. Selecting a particular channel allows the A/D Converter to control the CTMU (particularly, its current source) and read its data through that channel. AD1CTMUENL is always implemented, whereas AD1CTMUENH may not be implemented in devices with 16 or fewer channels. 22.1.2 A/D RESULT BUFFERS The module incorporates a multi-word, dual port RAM, called ADC1BUF. The buffer is composed of at least the same number of word locations as there are external analog channels for a particular device, with a maximum number of 32. The number of buffer addresses is always even. Each of the locations is mapped into the data memory space and is separately addressable. The buffer locations are referred to as ADC1BUF0 through ADC1BUFn (up to 31). The A/D result buffers are both readable and writable. When the module is active (AD1CON = 1), the buffers are read-only, and store the results of A/D conversions. When the module is inactive (AD1CON = 0), the buffers are both readable and writable. In this state, writing to a buffer location programs a conversion threshold for Threshold Detect operations. Buffer contents are not cleared when the module is deactivated with the ADON bit (AD1CON1). Conversion results and any programmed threshold values are maintained when ADON is set or cleared.  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 ADON — ADSIDL — — MODE12 FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HSC R/C-0, HSC SSRC3 SSRC2 SSRC1 SSRC0 — ASAM SAMP DONE bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADON: A/D Operating Mode bit 1 = A/D Converter module is operating 0 = A/D Converter is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: A/D Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-11 Unimplemented: Read as ‘0’ bit 10 MODE12: 12-Bit Operation Mode bit 1 = 12-bit A/D operation 0 = 10-bit A/D operation bit 9-8 FORM: Data Output Format bits (see the following formats) 11 = Fractional result, signed, left-justified 10 = Absolute fractional result, unsigned, left-justified 01 = Decimal result, signed, right-justified 00 = Absolute decimal result, unsigned, right-justified bit 7-4 SSRC: Sample Clock Source Select bits 1111 = Not available; do not use x = Bit is unknown    1000 = Not available; do not use 0111 = Internal counter ends sampling and starts conversion (auto-convert) 0110 = Not available; do not use 0101 = Timer1 event ends sampling and starts conversion 0100 = CTMU event ends sampling and starts conversion 0011 = Timer5 event ends sampling and starts conversion 0010 = Timer3 event ends sampling and starts conversion 0001 = INT0 event ends sampling and starts conversion 0000 = Clearing the SAMP bit in software ends sampling and begins conversion bit 3 Unimplemented: Read as ‘0’ bit 2 ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after the last conversion; SAMP bit is auto-set 0 = Sampling begins when the SAMP bit is manually set bit 1 SAMP: A/D Sample Enable bit 1 = A/D Sample-and-Hold amplifiers are sampling 0 = A/D Sample-and-Hold amplifiers are holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion cycle has completed 0 = A/D conversion cycle has not started or is in progress  2011-2013 Microchip Technology Inc. DS39995D-page 211 PIC24FV32KA304 FAMILY REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 PVCFG1 PVCFG0 NVCFG0 OFFCAL BUFREGEN CSCNA — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS(1) SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM(1) ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 PVCFG: Converter Positive Voltage Reference Configuration bits 11 = 4 * Internal VBG(2) 10 = 2 * Internal VBG(3) 01 = External VREF+ 00 = AVDD bit 13 NVCFG0: Converter Negative Voltage Reference Configuration bits 1 = External VREF0 = AVSS bit 12 OFFCAL: Offset Calibration Mode Select bit 1 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to AVSS 0 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to normal inputs bit 11 BUFREGEN: A/D Buffer Register Enable bit 1 = Conversion result is loaded into a buffer location determined by the converted channel 0 = A/D result buffer is treated as a FIFO bit 10 CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Setting bit 1 = Scans inputs 0 = Does not scan inputs bit 9-8 Unimplemented: Read as ‘0’ bit 7 BUFS: Buffer Fill Status bit(1) 1 = A/D is filling the upper half of the buffer; user should access data in the lower half 0 = A/D is filling the lower half of the buffer; user should access data in the upper half bit 6-2 SMPI: Sample Rate Interrupt Select bits 11111 = Interrupts at the completion of the conversion for each 32nd sample 11110 = Interrupts at the completion of the conversion for each 31st sample    00001 = Interrupts at the completion of the conversion for every other sample 00000 = Interrupts at the completion of the conversion for each sample BUFM: Buffer Fill Mode Select bit(1) 1 = Starts filling the buffer at address, AD1BUF0, on the first interrupt and AD1BUF(n/2) on the next interrupt (Split Buffer mode) 0 = Starts filling the buffer at address, ADCBUF0, and each sequential address on successive interrupts (FIFO mode) bit 1 Note 1: 2: 3: This is only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS is only used when BUFM = 1. The voltage reference setting will not be within the specification with VDD below 4.5V. The voltage reference setting will not be within the specification with VDD below 2.3V. DS39995D-page 212  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 22-2: bit 0 AD1CON2: A/D CONTROL REGISTER 2 (CONTINUED) ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on the first sample and Sample B on the next sample 0 = Always uses channel input selects for Sample A Note 1: 2: 3: This is only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS is only used when BUFM = 1. The voltage reference setting will not be within the specification with VDD below 4.5V. The voltage reference setting will not be within the specification with VDD below 2.3V. REGISTER 22-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 R-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC EXTSAM r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: A/D Conversion Clock Source bit 1 = RC clock 0 = Clock is derived from the system clock bit 14 EXTSAM: Extended Sampling Time bit 1 = A/D is still sampling after SAMP = 0 0 = A/D is finished sampling bit 13 Reserved: Maintain as ‘0’ bit 12-8 SAMC: Auto-Sample Time Select bits 11111 = 31 TAD x = Bit is unknown    00001 = 1 TAD 00000 = 0 TAD bit 7-0 ADCS: A/D Conversion Clock Select bits 11111111-01000000 = Reserved 00111111 = 64·TCY = TAD    00000001 = 2·TCY = TAD 00000000 = TCY = TAD  2011-2013 Microchip Technology Inc. DS39995D-page 213 PIC24FV32KA304 FAMILY REGISTER 22-4: AD1CON5: A/D CONTROL REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 r-0 U-0 R/W-0 R/W-0 ASEN(1) LPEN CTMREQ BGREQ r — ASINT1 ASINT0 bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — WM1 WM0 CM1 CM0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ASEN: Auto-Scan Enable bit(1) 1 = Auto-scan is enabled 0 = Auto-scan is disabled bit 14 LPEN: Low-Power Enable bit 1 = Returns to Low-Power mode after scan 0 = Remains in Full-Power mode after scan bit 13 CTMREQ: CTMU Request bit 1 = CTMU is enabled when the A/D is enabled and active 0 = CTMU is not enabled by the A/D bit 12 BGREQ: Band Gap Request bit 1 = Band gap is enabled when the A/D is enabled and active 0 = Band gap is not enabled by the A/D bit 11 Reserved: Maintain as ‘0’ bit 10 Unimplemented: Read as ‘0’ bit 9-8 ASINT: Auto-Scan (Threshold Detect) Interrupt Mode bits 11 = Interrupt after a Threshold Detect sequence completed and a valid compare has occurred 10 = Interrupt after a valid compare has occurred 01 = Interrupt after a Threshold Detect sequence completed 00 = No interrupt bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 WM: Write Mode bits 11 = Reserved 10 = Auto-compare only (conversion results are not saved, but interrupts are generated when a valid match, as defined by the CMx and ASINTx bits, occurs) 01 = Convert and save (conversion results are saved to locations as determined by the register bits when a match, as defined by the CMx bits, occurs) 00 = Legacy operation (conversion data is saved to a location determined by the buffer register bits) bit 1-0 CM: Compare Mode bits 11 = Outside Window mode (valid match occurs if the conversion result is outside of the window defined by the corresponding buffer pair) 10 = Inside Window mode (valid match occurs if the conversion result is inside the window defined by the corresponding buffer pair) 01 = Greater Than mode (valid match occurs if the result is greater than the value in the corresponding buffer register) 00 = Less Than mode (valid match occurs if the result is less than the value in the corresponding buffer register) Note 1: When using auto-scan with Threshold Detect (ASEN = 1), do not configure the sample clock source to Auto-Convert mode (SSRCx = 7). Any other available SSRCx selection is valid. To use auto-convert as the sample clock source (SSRCx = 7), make sure ASEN is cleared. DS39995D-page 214  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 22-5: AD1CHS: A/D SAMPLE SELECT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB2 CH0NB1 CH0NB0 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA2 CH0NA1 CH0NA0 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 CH0NB: Sample B Channel 0 Negative Input Select bits 111 = AN6(1) 110 = AN5(2) 101 = AN4 100 = AN3 011 = AN2 010 = AN1 001 = AN0 000 = AVSS bit 12-8 CH0SB: S/H Amplifier Positive Input Select for MUX B Multiplexer Setting bits 11111 = Unimplemented, do not use 11110 = AVDD 11101 = AVSS 11100 = Upper guardband rail (0.785 * VDD) 11011 = Lower guardband rail (0.215 * VDD) 11010 = Internal Band Gap Reference (VBG)(3) 11001-10010 = Unimplemented, do not use 10001 = No channels are connected, all inputs are floating (used for CTMU) 10000 = No channels are connected, all inputs are floating (used for CTMU temperature sensor input) 01111 = AN15 01110 = AN14 01101 = AN13 01100 = AN12 01011 = AN11 01010 = AN10 01001 = AN9 01000 = AN8(1) 00111 = AN7(1) 00110 = AN6(1) 00101 = AN5(2) 00100 = AN4 00011 = AN3 00010 = AN2 00001 = AN1 00000 = AN0 bit 7-5 CH0NA: Sample A Channel 0 Negative Input Select bits The same definitions as for CHONB. bit 4-0 CH0SA: Sample A Channel 0 Positive Input Select bits The same definitions as for CHONA. Note 1: 2: 3: This is implemented on 44-pin devices only. This is implemented on 28-pin and 44-pin devices only. The band gap value used for this input is 2x or 4x the internal VBG, which is selected when PVCFG = 1x.  2011-2013 Microchip Technology Inc. DS39995D-page 215 PIC24FV32KA304 FAMILY REGISTER 22-6: AD1CHITH: A/D SCAN COMPARE HIT REGISTER (HIGH WORD)(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — CHH17 CHH16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’. bit 1-0 CHH: A/D Compare Hit bits If CM = 11: 1 = A/D Result Buffer x has been written with data or a match has occurred 0 = A/D Result Buffer x has not been written with data For All Other Values of CM: 1 = A match has occurred on A/D Result Channel x 0 = No match has occurred on A/D Result Channel x Note 1: Unimplemented channels are read as ‘0’. REGISTER 22-7: AD1CHITL: A/D SCAN COMPARE HIT REGISTER (LOW WORD)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHH15 CHH14 CHH13 CHH12 CHH11 CHH10 CHH9 CHH8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHH7 CHH6 CHH5 CHH4 CHH3 CHH2 CHH1 CHH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: x = Bit is unknown CHH: A/D Compare Hit bits If CM = 11: 1 = A/D Result Buffer x has been written with data or a match has occurred 0 = A/D Result Buffer x has not been written with data For all other values of CM: 1 = A match has occurred on A/D Result Channel x 0 = No match has occurred on A/D Result Channel x Unimplemented channels are read as ‘0’. DS39995D-page 216  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 22-8: AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH WORD)(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — CSS30 CSS29 CSS28 CSS27 CSS26 — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — CSS17 CSS16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-10 CSS: A/D Input Scan Selection bits 1 = Includes corresponding channel for input scan 0 = Skips channel for input scan bit 9-2 Unimplemented: Read as ‘0’ bit 1-0 CSS: A/D Input Scan Selection bits 1 = Includes corresponding channel for input scan 0 = Skips channel for input scan Note 1: x = Bit is unknown Unimplemented channels are read as ‘0’. Do not select unimplemented channels for sampling as indeterminate results may be produced. REGISTER 22-9: AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW WORD)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: x = Bit is unknown CSS: A/D Input Scan Selection bits 1 = Includes corresponding ANx input for scan 0 = Skips channel for input scan Unimplemented channels are read as ‘0’. Do not select unimplemented channels for sampling as indeterminate results may be produced.  2011-2013 Microchip Technology Inc. DS39995D-page 217 PIC24FV32KA304 FAMILY REGISTER 22-10: AD1CTMUENH: A/D CTMU ENABLE REGISTER (HIGH WORD)(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — CTMEN17 CTMEN16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’. bit 1-0 CTMEN: CTMU Enabled During Conversion bits 1 = CTMU is enabled and connected to the selected channel during conversion 0 = CTMU is not connected to this channel Note 1: Unimplemented channels are read as ‘0’. REGISTER 22-11: AD1CTMUENL: A/D CTMU ENABLE REGISTER (LOW WORD)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMEN15 CTMEN14 CTMEN13 CTMEN12 CTMUEN11 CTMEN10 CTMEN9 CTMEN8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMEN7 CTMEN6 CTMEN5 CTMEN4 CTMEN3 CTMEN2 CTMEN1 CTMEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: x = Bit is unknown CTMEN: CTMU Enabled During Conversion bits 1 = CTMU is enabled and connected to the selected channel during conversion 0 = CTMU is not connected to this channel Unimplemented channels are read as ‘0’. DS39995D-page 218  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 22.2 A/D Sampling Requirements The analog input model of the 12-bit A/D Converter is shown in Figure 22-2. The total sampling time for the A/D is a function of the holding capacitor charge time. For the A/D Converter to meet its specified accuracy, the Charge Holding Capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin. The Source (RS) impedance, the Interconnect (RIC) impedance and the internal Sampling Switch (RSS) impedance combine to directly affect the time required to charge CHOLD. The combined impedance of the analog sources must, therefore, be small enough to fully charge the holding capacitor within the chosen sample time. To minimize the effects of pin leakage currents on the accuracy of the A/D Converter, the maximum recommended Source impedance, RS, is 2.5 k. After the analog input channel is selected (changed), this FIGURE 22-2: sampling function must be completed prior to starting the conversion. The internal holding capacitor will be in a discharged state prior to each sample operation. At least 1 TAD time period should be allowed between conversions for the sample time. For more details, see Section 29.0 “Electrical Characteristics”. EQUATION 22-1: A/D CONVERSION CLOCK PERIOD TAD = TCY(ADCS + 1) ADCS = Note: TAD – 1 TCY Based on TCY = 2/FOSC; Doze mode and PLL are disabled. 12-BIT A/D CONVERTER ANALOG INPUT MODEL RIC  250 Rs VA ANx CPIN Sampling Switch RSS ILEAKAGE 500 nA RSS  3 k CHOLD = 32 pF VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the Pin Due to Various Junctions RIC = Interconnect Resistance RSS = Sampling Switch Resistance CHOLD = Sample-and-Hold Capacitance (from DAC) Note: The CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs  5 k.  2011-2013 Microchip Technology Inc. DS39995D-page 219 PIC24FV32KA304 FAMILY 22.3 Transfer Function • The first code transition occurs when the input voltage is ((VR+) – (VR-))/4096 or 1.0 LSb. • The 0000 0000 0001 code is centered at VR- + (1.5 * ((VR+) – (VR-))/4096). • The ‘0010 0000 0000’ code is centered at VREFL + (2048.5 * ((VR+) – (VR-))/4096). • An input voltage less than VR- + (((VR-) – (VR-))/4096) converts as ‘0000 0000 0000’. • An input voltage greater than (VR-) + (4095 ((VR+) – (VR-))/4096) converts as ‘1111 1111 1111’. The transfer functions of the A/D Converter in 12-bit resolution are shown in Figure 22-3. The difference of the input voltages, (VINH – VINL), is compared to the reference, ((VR+) – (VR-)). FIGURE 22-3: 12-BIT A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 1111 1111 1111 (4095) 1111 1111 1110 (4094) 0010 0000 0011 (2051) 0010 0000 0010 (2050) 0010 0000 0001 (2049) 0010 0000 0000 (2048) 0001 1111 1111 (2047) 0001 1111 1110 (2046) 0001 1111 1101 (2045) 0000 0000 0001 (1) DS39995D-page 220 (VINH – VINL) VR+ 4096 4095 * (VR+ – VR-) VR- + 4096 VR-+ 2048 * (VR+ – VR-) 4096 VR+ – VR- VR- + 0 Voltage Level VR- 0000 0000 0000 (0)  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 22.4 Buffer Data Formats conversions 11 bits wide. The signed decimal format yields 12-bit and 10-bit values, respectively. The sign bit (bit 12 or bit 10) is sign-extended to fill the buffer. The FORM bits (AD1CON1) select the format. Figure 22-4 and Figure 22-5 show the data output formats that can be selected. Table 22-1 through Table 22-4 show the numerical equivalents for the various conversion result codes. The A/D conversions are fully differential 12-bit values when MODE12 = 1 (AD1CON1) and 10-bit values when MODE12 = 0. When absolute fractional or absolute integer formats are used, the results are 12 or 10 bits wide, respectively. When signed decimal formatting is used, the conversion also includes a sign bit, making 12-bit conversions 13 bits wide, and 10-bit FIGURE 22-4: A/D OUTPUT DATA FORMATS (12-BIT) RAM Contents: d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Read to Bus: Integer 0 0 0 0 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Signed Integer s0 s0 s0 s0 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Fractional (1.15) Signed Fractional (1.15) TABLE 22-1: d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 s0 0 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0 NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES: 12-BIT INTEGER FORMATS VIN/VREF 12-Bit Differential Output Code (13-bit result) +4095/4096 0 1111 1111 1111 0000 1111 1111 1111 +4095 0000 1111 1111 1111 +4095 +4094/4096 0 1111 1111 1110 0000 1111 1111 1110 +4094 0000 1111 1111 1110 +4094 +1 0000 0000 0000 0001 +1 16-Bit Integer Format/ Equivalent Decimal Value 16-Bit Signed Integer Format/ Equivalent Decimal Value  +1/4096 0 1000 0000 0001 0000 0000 0000 0001 0/4096 0 0000 0000 0000 0000 0000 0000 0000 0 0000 0000 0000 0000 0 -1/4096 1 0111 1111 1111 0000 0000 0000 0000 0 1111 1111 1111 1111 -1 -4095/4096 1 0000 0000 0001 0000 0000 0000 0000 0 1111 0000 0000 0001 -4095 -4096/4096 1 0000 0000 0000 0000 0000 0000 0000 0 1111 0000 0000 0000 -4096   2011-2013 Microchip Technology Inc. DS39995D-page 221 PIC24FV32KA304 FAMILY TABLE 22-2: NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES: 12-BIT FRACTIONAL FORMATS 16-Bit Fractional Format/ Equivalent Decimal Value 12-Bit Output Code VIN/VREF 16-Bit Signed Fractional Format/ Equivalent Decimal Value +4095/4096 0 1111 1111 1111 1111 1111 1111 0000 0.999 0111 1111 1111 1000 0.999 +4094/4096 0 1111 1111 1110 1111 1111 1110 0000 0.998 0111 1111 1110 1000 0.998 +1/4096 0 0000 0000 0001 0000 0000 0001 0000 0.001 0000 0000 0000 1000 0.001 0/4096 0 0000 0000 0000 0000 0000 0000 0000 0.000 0000 0000 0000 0000 0.000 -1/4096 1 0111 1111 1111 0000 0000 0000 0000 0.000 1111 1111 1111 1000 -0.001 -4095/4096 1 0000 0000 0001 0000 0000 0000 0000 0.000 1000 0000 0000 1000 -0.999 -4096/4096 1 0000 0000 0000 0000 0000 0000 0000 0.000 1000 0000 0000 0000 -1.000   FIGURE 22-5: A/D OUTPUT DATA FORMATS (10-BIT) RAM Contents: d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Read to Bus: Integer 0 0 0 0 0 0 Signed Integer s0 s0 s0 s0 s0 s0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Fractional (1.15) Signed Fractional (1.15) TABLE 22-3: VIN/VREF d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 s0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0 0 0 0 0 NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES: 10-BIT INTEGER FORMATS 10-Bit Differential Output Code (11-bit result) 16-Bit Integer Format/ Equivalent Decimal Value 16-Bit Signed Integer Format/ Equivalent Decimal Value +1023/1024 011 1111 1111 0000 0011 1111 1111 1023 0000 0001 1111 1111 1023 +1022/1024 011 1111 1110 0000 0011 1111 1110 1022 0000 0001 1111 1110 1022 +1/1024 000 0000 0001 0000 0000 0000 0001 1 0000 0000 0000 0001 1 0/1024 000 0000 0000 0000 0000 0000 0000 0 0000 0000 0000 0000 0 -1/1024 101 1111 1111 0000 0000 0000 0000 0 1111 1111 1111 1111 -1 -1023/1024 100 0000 0001 0000 0000 0000 0000 0 1111 1110 0000 0001 -1023 -1024/1024 100 0000 0000 0000 0000 0000 0000 0 1111 1110 0000 0000 -1024   DS39995D-page 222  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TABLE 22-4: VIN/VREF NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES: 10-BIT FRACTIONAL FORMATS 10-Bit Differential Output Code (11-bit result) 16-Bit Fractional Format/ Equivalent Decimal Value 16-Bit Signed Fractional Format/ Equivalent Decimal Value +1023/1024 011 1111 1111 1111 1111 1100 0000 0.999 0111 1111 1110 0000 0.999 +1022/1024 011 1111 1110 1111 1111 1000 0000 0.998 0111 1111 1000 0000 0.998 +1/1024 000 0000 0001 0000 0000 0100 0000 0.001 0000 0000 0010 0000 0.001 0/1024 000 0000 0000 0000 0000 0000 0000 0.000 0000 0000 0000 0000 0.000 -1/1024 101 1111 1111 0000 0000 0000 0000 0.000 1111 1111 1110 0000 -0.001 -1023/1024 100 0000 0001 0000 0000 0000 0000 0.000 1000 0000 0010 0000 -0.999 -1024/1024 100 0000 0000 0000 0000 0000 0000 0.000 1000 0000 0000 0000 -1.000    2011-2013 Microchip Technology Inc. DS39995D-page 223 PIC24FV32KA304 FAMILY NOTES: DS39995D-page 224  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 23.0 COMPARATOR MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Comparator module, refer to the “PIC24F Family Reference Manual”, Section 46. “Scalable Comparator Module” (DS39734). The comparator module provides three dual input comparators. The inputs to the comparator can be configured to use any one of four external analog inputs, as well as a voltage reference input from either the internal band gap reference, divided by 2 (VBG/2), or the comparator voltage reference generator. FIGURE 23-1: The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. A simplified block diagram of the module is shown in Figure 23-1. Diagrams of the possible individual comparator configurations are shown in Figure 23-2. Each comparator has its own control register, CMxCON (Register 23-1), for enabling and configuring its operation. The output and event status of all three comparators is provided in the CMSTAT register (Register 23-2). COMPARATOR x MODULE BLOCK DIAGRAM CCH CREF EVPOL CXINB CXINC CXIND Input Select Logic CPOL VINVIN+ Trigger/Interrupt Logic CEVT COE C1 COUT VBG/2 C1OUT Pin EVPOL Trigger/Interrupt Logic CPOL CEVT COE VINVIN+ C2 COUT C2OUT Pin EVPOL CPOL CXINA CVREF VINVIN+ Trigger/Interrupt Logic CEVT COE C3 COUT  2011-2013 Microchip Technology Inc. C3OUT Pin DS39995D-page 225 PIC24FV32KA304 FAMILY FIGURE 23-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH = xx VIN- COE – VIN+ Cx Off (Read as ‘0’) Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH = 00 CXINB CXINA VIN- Comparator CxINC > CxINA Compare CON = 1, CREF = 0, CCH = 01 COE – VIN+ CXINC Cx CxOUT Pin CXINA VIN- COE – VIN+ VBG/2 Cx CxOUT Pin Comparator CxINB > CVREF Compare CON = 1, CREF = 1, CCH = 00 CXINB CVREF VINVIN+ CVREF DS39995D-page 226 VINVIN+ CXINA COE – CXINC Cx CxOUT Pin CVREF VIN+ Cx CxOUT Pin VIN- COE – VIN+ Cx CxOUT Pin VIN- COE – VIN+ Cx CxOUT Pin Comparator VBG > CVREF Compare CON = 1, CREF = 1, CCH = 11 COE – COE – Comparator CxINC > CVREF Compare CON = 1, CREF = 1, CCH = 01 Comparator CxIND > CVREF Compare CON = 1, CREF = 1, CCH = 10 CXIND CXINA VIN- Comparator VBG > CxINA Compare CON = 1, CREF = 0, CCH = 11 Comparator CxIND > CxINA Compare CON = 1, CREF = 0, CCH = 10 CXIND CxOUT Pin VBG/2 Cx CxOUT Pin CVREF VINVIN+ COE – Cx CxOUT Pin  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS R/W-0 CON bit 15 R/W-0 COE R/W-0 CPOL R/W-0 CLPWR U-0 — U-0 — R/W-0 CEVT R-0 COUT bit 8 R/W-0 EVPOL1 bit 7 R/W-0 EVPOL0 U-0 — R/W-0 CREF U-0 — U-0 — R/W-0 CCH1 R/W-0 CCH0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11-10 bit 9 bit 8 bit 7-6 bit 5 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CON: Comparator x Enable bit 1 = Comparator is enabled 0 = Comparator is disabled COE: Comparator x Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only CPOL: Comparator x Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted CLPWR: Comparator x Low-Power Mode Select bit 1 = Comparator operates in Low-Power mode 0 = Comparator does not operate in Low-Power mode Unimplemented: Read as ‘0’ CEVT: Comparator x Event bit 1 = Comparator event defined by EVPOL has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred COUT: Comparator x Output bit When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VINEVPOL: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt is generated on the transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt is generated on the transition of the comparator output If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. DS39995D-page 227 PIC24FV32KA304 FAMILY REGISTER 23-1: bit 4 bit 3-2 bit 1-0 CMxCON: COMPARATOR x CONTROL REGISTERS (CONTINUED) CREF: Comparator x Reference Select bits (non-inverting input) 1 = Non-inverting input connects to the internal CVREF voltage 0 = Non-inverting input connects to the CxINA pin Unimplemented: Read as ‘0’ CCH: Comparator x Channel Select bits 11 = Inverting input of the comparator connects to VBG 10 = Inverting input of the comparator connects to the CxIND pin 01 = Inverting input of the comparator connects to the CxINC pin 00 = Inverting input of the comparator connects to the CxINB pin REGISTER 23-2: CMSTAT: COMPARATOR x MODULE STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC CMIDL — — — — C3EVT C2EVT C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC — — — — — C3OUT C2OUT C1OUT bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMIDL: Comparator x Stop in Idle Mode bit 1 = Comparator interrupts are disabled in Idle mode; enabled comparators remain operational 0 = Continues operation of all enabled comparators in Idle mode bit 14-11 Unimplemented: Read as ‘0’ bit 10 C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON). bit 9 C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON). bit 8 C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON). bit 7-3 Unimplemented: Read as ‘0’ bit 2 C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON). bit 1 C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON). bit 0 C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON). DS39995D-page 228  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 24.0 Note: COMPARATOR VOLTAGE REFERENCE 24.1 Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register (Register 24-1). The comparator voltage reference provides a range of output voltages, with 32 distinct levels. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Comparator Voltage Reference, refer to the “PIC24F Family Reference Manual”, Section 20. “Comparator Module Voltage Reference Module” (DS39709). The comparator voltage reference supply voltage can come from either VDD and VSS or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON). The settling time of the comparator voltage reference must be considered when changing the CVREF output. FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 8R CVRSS = 0 CVR R CVREN R R 32-to-1 MUX R 32 Steps R CVREF R R 8R VREF- CVRSS = 1 CVRSS = 0 AVSS  2011-2013 Microchip Technology Inc. DS39995D-page 229 PIC24FV32KA304 FAMILY REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit is powered on 0 = CVREF circuit is powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on the CVREF pin 0 = CVREF voltage level is disconnected from the CVREF pin bit 5 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = VREF+ – VREF0 = Comparator reference source, CVRSRC = AVDD – AVSS bit 4-0 CVR: Comparator VREF Value Selection 0 ≤ CVR ≤ 31 bits When CVRSS = 1: CVREF = (VREF-) + (CVR/32) • (VREF+ – VREF-) When CVRSS = 0: CVREF = (AVSS) + (CVR/32) • (AVDD – AVSS) DS39995D-page 230  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 25.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Charge Measurement Unit, refer to the “PIC24F Family Reference Manual”, Section 53. “Charge Time Measurement Unit (CTMU) with Threshold Detect” (DS39743). The Charge Time Measurement Unit (CTMU) is a flexible analog module that provides charge measurement, accurate differential time measurement between pulse sources and asynchronous pulse generation. Its key features include: • • • • Thirteen external edge input trigger sources Polarity control for each edge source Control of edge sequence Control of response to edge levels or edge transitions • Time measurement resolution of one nanosecond • Accurate current source suitable for capacitive measurement Together with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses that are independent of the system clock. The CTMU module is ideal for interfacing with capacitive-based touch sensors. 25.1 Measuring Capacitance The CTMU module measures capacitance by generating an output pulse, with a width equal to the time between edge events, on two separate input channels. The pulse edge events to both input channels can be selected from several internal peripheral modules (OC1, Timer1, any input capture or comparator module) and up to 13 external pins (CTED1 through CTED13). This pulse is used with the module’s precision current source to calculate capacitance according to the relationship: EQUATION 25-1: dV I = C  ------dT For capacitance measurements, the A/D Converter samples an external capacitor (CAPP) on one of its input channels after the CTMU output’s pulse. A Precision Resistor (RPR) provides current source calibration on a second A/D channel. After the pulse ends, the converter determines the voltage on the capacitor. The actual calculation of capacitance is performed in software by the application. Figure 25-1 illustrates the external connections used for capacitance measurements, and how the CTMU and A/D modules are related in this application. This example also shows the edge events coming from Timer1, but other configurations using external edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the “PIC24F Family Reference Manual”. The CTMU is controlled through three registers: CTMUCON1, CTMUCON2 and CTMUICON. CTMUCON1 enables the module and controls the mode of operation of the CTMU, as well as controlling edge sequencing. CTMUCON2 controls edge source selection and edge source polarity selection. The CTMUICON register selects the current range of current source and trims the current.  2011-2013 Microchip Technology Inc. DS39995D-page 231 PIC24FV32KA304 FAMILY FIGURE 25-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 Current Source EDG2 Output Pulse ANx A/D Converter ANy CAPP 25.2 RPR Measuring Time Time measurements on the pulse width can be similarly performed using the A/D module’s Internal Capacitor (CAD) and a precision resistor for current calibration. Figure 25-2 displays the external connections used for FIGURE 25-2: time measurements, and how the CTMU and A/D modules are related in this application. This example also shows both edge events coming from the external CTEDx pins, but other configurations using internal edge sources are possible. TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC24F Device CTMU CTEDX EDG1 CTEDX EDG2 Current Source Output Pulse ANx A/D Converter CAD RPR DS39995D-page 232  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 25.3 Pulse Generation and Delay When the voltage on CDELAY equals CVREF, CTPLS goes low. With Comparator 2 configured as the second edge, this stops the CTMU from charging. In this state event, the CTMU automatically connects to ground. The IDISSEN bit doesn’t need to be set and cleared before the next CTPLS cycle. The CTMU module can also generate an output pulse with edges that are not synchronous with the device’s system clock. More specifically, it can generate a pulse with a programmable delay from an edge event input to the module. Figure 25-3 illustrates the external connections for pulse generation, as well as the relationship of the different analog modules required. While CTED1 is shown as the input pulse source, other options are available. A detailed discussion on pulse generation with the CTMU module is provided in the “PIC24F Family Reference Manual”. When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON), the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the Comparator Voltage Reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected. While CVREF is greater than the voltage on CDELAY, CTPLS is high. FIGURE 25-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTMU VDD CTED1 EDG1 D Q CK Q CTPLS EDG1 EDG2 R Current Source Comparator – C2 C2INB CDELAY  2011-2013 Microchip Technology Inc. EDG2 CVREF DS39995D-page 233 PIC24FV32KA304 FAMILY REGISTER 25-1: CTMUCON1: CTMU CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CTMUSIDL: CTMU Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation bit 11 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 10 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 9 IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 8 CTTRIG: CTMU Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled bit 7-0 Unimplemented: Read as ‘0’ DS39995D-page 234 x = Bit is unknown  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 25-2: CTMUCON2: CTMU CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 EDG1MOD: Edge 1 Edge-Sensitive Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 14 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 is programmed for a positive edge response 0 = Edge 1 is programmed for a negative edge response bit 13-10 EDG1SEL: Edge 1 Source Select bits 1111 = Edge 1 source is Comparator 3 output 1110 = Edge 1 source is Comparator 2 output 1101 = Edge 1 source is Comparator 1 output 1100 = Edge 1 source is IC3 1011 = Edge 1 source is IC2 1010 = Edge 1 source is IC1 1001 = Edge 1 source is CTED8 1000 = Edge 1 source is CTED7 0111 = Edge 1 source is CTED6 0110 = Edge 1 source is CTED5 0101 = Edge 1 source is CTED4 0100 = Edge 1 source is CTED3(2) 0011 = Edge 1 source is CTED1 0010 = Edge 1 source is CTED2 0001 = Edge 1 source is OC1 0000 = Edge 1 source is Timer1 bit 9 EDG2STAT: Edge 2 Status bit Indicates the status of Edge 2 and can be written to control the current source. 1 = Edge 2 has occurred 0 = Edge 2 has not occurred bit 8 EDG1STAT: Edge 1 Status bit Indicates the status of Edge 1 and can be written to control the current source. 1 = Edge 1 has occurred 0 = Edge 1 has not occurred bit 7 EDG2MOD: Edge 2 Edge-Sensitive Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive Note 1: 2: Edge sources, CTED11 and CTED12, are not available on PIC24FV32KA302 devices. Edge sources, CTED3, CTED11, CTED12 and CTED13, are not available on PIC24FV32KA301 devices.  2011-2013 Microchip Technology Inc. DS39995D-page 235 PIC24FV32KA304 FAMILY REGISTER 25-2: CTMUCON2: CTMU CONTROL REGISTER 2 (CONTINUED) bit 6 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge 0 = Edge 2 is programmed for a negative edge bit 5-2 EDG2SEL: Edge 2 Source Select bits 1111 = Edge 2 source is Comparator 3 output 1110 = Edge 2 source is Comparator 2 output 1101 = Edge 2 source is Comparator 1 output 1100 = Unimplemented; do not use 1011 = Edge 2 source is IC3 1010 = Edge 2 source is IC2 1001 = Edge 2 source is IC1 1000 = Edge 2 source is CTED13(2) 0111 = Edge 2 source is CTED12(1,2) 0110 = Edge 2 source is CTED11(1,2) 0101 = Edge 2 source is CTED10 0100 = Edge 2 source is CTED9 0011 = Edge 2 source is CTED1 0010 = Edge 2 source is CTED2 0001 = Edge 2 source is OC1 0000 = Edge 2 source is Timer1 bit 1-0 Unimplemented: Read as ‘0’ Note 1: 2: Edge sources, CTED11 and CTED12, are not available on PIC24FV32KA302 devices. Edge sources, CTED3, CTED11, CTED12 and CTED13, are not available on PIC24FV32KA301 devices. DS39995D-page 236  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 25-3: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 ITRIM: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . . 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG 111111 = Minimum negative change from nominal current . . . 100010 100001 = Maximum negative change from nominal current bit 9-8 IRNG: Current Source Range Select bits 11 = 100 × Base Current 10 = 10 × Base Current 01 = Base Current Level (0.55 µA nominal) 00 = 1000 × Base Current bit 7-0 Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. x = Bit is unknown DS39995D-page 237 PIC24FV32KA304 FAMILY NOTES: DS39995D-page 238  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 26.0 SPECIAL FEATURES Note: 26.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Watchdog Timer, High-Level Device Integration and Programming Diagnostics, refer to the individual sections of the “PIC24F Family Reference Manual” provided below: The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped, starting at program memory location, F80000h. A complete list of Configuration register locations is provided in Table 26-1. A detailed explanation of the various bit functions is provided in Register 26-1 through Register 26-8. • Section 9. “Watchdog Timer (WDT)” (DS39697) • Section 36. “High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)” (DS39725) • Section 33. “Programming and Diagnostics” (DS39716) The address, F80000h, is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh), which can only be accessed using table reads and table writes. PIC24FV32KA304 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • • • • • Configuration Bits Flexible Configuration Watchdog Timer (WDT) Code Protection In-Circuit Serial Programming™ (ICSP™) In-Circuit Emulation REGISTER 26-1: TABLE 26-1: CONFIGURATION REGISTERS LOCATIONS Configuration Register Address FBS FGS FOSCSEL FOSC FWDT FPOR FICD FDS F80000 F80004 F80006 F80008 F8000A F8000C F8000E F80010 FBS: BOOT SEGMENT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — — — BSS2 BSS1 BSS0 BWRP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-1 BSS: Boot Segment Program Flash Code Protection bits 111 = No boot program Flash segment 011 = Reserved 110 = Standard security, boot program Flash segment starts at 200h, ends at 000AFEh 010 = High-security boot program Flash segment starts at 200h, ends at 000AFEh 101 = Standard security, boot program Flash segment starts at 200h, ends at 0015FEh(1) 001 = High-security, boot program Flash segment starts at 200h, ends at 0015FEh(1) 100 = Standard security; boot program Flash segment starts at 200h, ends at 002BFEh(1) 000 = High-security; boot program Flash segment starts at 200h, ends at 002BFEh(1) bit 0 BWRP: Boot Segment Program Flash Write Protection bit 1 = Boot segment may be written 0 = Boot segment is write-protected Note 1: This selection should not be used in PIC24FV16KA3XX devices.  2011-2013 Microchip Technology Inc. DS39995D-page 239 PIC24FV32KA304 FAMILY REGISTER 26-2: FGS: GENERAL SEGMENT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — GSS0 GWRP bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 GSS0: General Segment Code Flash Code Protection bit 1 = No protection 0 = Standard security is enabled bit 0 GWRP: General Segment Code Flash Write Protection bit 1 = General segment may be written 0 = General segment is write-protected REGISTER 26-3: x = Bit is unknown FOSCSEL: OSCILLATOR SELECTION CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 IESO LPRCSEL SOSCSRC — — FNOSC2 FNOSC1 FNOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled) 0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled) bit 6 LPRCSEL: Internal LPRC Oscillator Power Select bit 1 = High-Power/High-Accuracy mode 0 = Low-Power/Low-Accuracy mode bit 5 SOSCSRC: Secondary Oscillator Clock Source Configuration bit 1 = SOSC analog crystal function is available on the SOSCI/SOSCO pins 0 = SOSC crystal is disabled; digital SCLKI function is selected on the SOSCO pin bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 FNOSC: Oscillator Selection bits 000 = Fast RC Oscillator (FRC) 001 = Fast RC Oscillator with Divide-by-N with PLL module (FRCDIV+PLL) 010 = Primary Oscillator (XT, HS, EC) 011 = Primary Oscillator with PLL module (HS+PLL, EC+PLL) 100 = Secondary Oscillator (SOSC) 101 = Low-Power RC Oscillator (LPRC) 110 = 500 kHz Low-Power FRC Oscillator with Divide-by-N (LPFRCDIV) 111 = 8 MHz FRC Oscillator with Divide-by-N (FRCDIV) DS39995D-page 240  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 26-4: FOSC: OSCILLATOR CONFIGURATION REGISTER R/P-1 R/P-1 FCKSM1 FCKSM0 R/P-1 R/P-1 R/P-1 R/P-1 SOSCSEL POSCFREQ1 POSCFREQ0 OSCIOFNC R/P-1 R/P-1 POSCMD1 POSCMD0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FCKSM: Clock Switching and Fail-Safe Clock Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 5 SOSCSEL: Secondary Oscillator Power Selection Configuration bit 1 = Secondary oscillator is configured for high-power operation 0 = Secondary oscillator is configured for low-power operation bit 4-3 POSCFREQ: Primary Oscillator Frequency Range Configuration bits 11 = Primary oscillator/external clock input frequency is greater than 8 MHz 10 = Primary oscillator/external clock input frequency is between 100 kHz and 8 MHz 01 = Primary oscillator/external clock input frequency is less than 100 kHz 00 = Reserved; do not use bit 2 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal is active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMD = 11 or 00) 0 = CLKO output is disabled bit 1-0 POSCMD: Primary Oscillator Configuration bits 11 = Primary Oscillator mode is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = External Clock mode is selected  2011-2013 Microchip Technology Inc. DS39995D-page 241 PIC24FV32KA304 FAMILY REGISTER 26-5: FWDT: WATCHDOG TIMER CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 FWDTEN1 WINDIS FWDTEN0 FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7,5 FWDTEN: Watchdog Timer Enable bits 11 = WDT is enabled in hardware 10 = WDT is controlled with the SWDTEN bit setting 01 = WDT is enabled only while device is active; WDT is disabled in Sleep, SWDTEN bit is disabled 00 = WDT is disabled in hardware; SWDTEN bit is disabled bit 6 WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard WDT is selected; windowed WDT is disabled 0 = Windowed WDT is enabled; note that executing a CLRWDT instruction while the WDT is disabled in hardware and software (FWDTEN = 00 and SWDTEN (RCON) = 0) will not cause a device Reset bit 4 FWPSA: WDT Prescaler bit 1 = WDT prescaler ratio of 1:128 0 = WDT prescaler ratio of 1:32 bit 3-0 WDTPS: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 DS39995D-page 242  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 26-6: FPOR: RESET CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 MCLRE(2) BORV1(3) BORV0(3) I2C1SEL(1) PWRTEN RETCFG(1) BOREN1 BOREN0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit(2) 1 = MCLR pin is enabled; RA5 input pin is disabled 0 = RA5 input pin is enabled; MCLR is disabled bit 6-5 BORV: Brown-out Reset Enable bits(3) 11 = Brown-out Reset is set to the lowest voltage 10 = Brown-out Reset 01 = Brown-out Reset is set to the highest voltage 00 = Downside protection on POR is enabled – “zero power” is selected bit 4 I2C1SEL: Alternate I2C1 Pin Mapping bit(1) 1 = Default location for SCL1/SDA1 pins 0 = Alternate location for SCL1/SDA1 pins bit 3 PWRTEN: Power-up Timer Enable bit 1 = PWRT is enabled 0 = PWRT is disabled bit 2 RETCFG: Retention Regulator Configuration bit(1) 1 = Retention Regulator is not available 0 = Retention Regulator is available and controlled by the RETEN bit (RCON) during Sleep bit 1-0 BOREN: Brown-out Reset Enable bits 11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled 10 = Brown-out Reset is enabled only while device is active and disabled in Sleep; SBOREN bit is disabled 01 = Brown-out Reset is controlled with the SBOREN bit setting 00 = Brown-out Reset is disabled in hardware; SBOREN bit is disabled Note 1: 2: 3: This setting only applies to the “FV” devices. This bit is reserved and should be maintained as ‘1’ on “F” devices. The MCLRE fuse can only be changed when using the VPP-based ICSP™ mode entry. This prevents a user from accidentally locking out the device from the low-voltage test entry. Refer to Section 29.0 “Electrical Characteristics” for BOR voltages.  2011-2013 Microchip Technology Inc. DS39995D-page 243 PIC24FV32KA304 FAMILY REGISTER 26-7: R/P-1 DEBUG bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-2 bit 1-0 FICD: IN-CIRCUIT DEBUGGER CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 — — — — — FICD1 FICD0 bit 0 P = Programmable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled 0 = Background debugger functions are enabled Unimplemented: Read as ‘0’ FICD: ICD Pin Select bits 11 = PGEC1/PGED1 are used for programming and debugging the device 10 = PGEC2/PGED2 are used for programming and debugging the device 01 = PGEC3/PGED3 are used for programming and debugging the device 00 = Reserved; do not use DS39995D-page 244  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 26-8: FDS: DEEP SLEEP CONFIGURATION REGISTER R/P-1 R/P-1 U-0 DSWDTEN DSBOREN — R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 DSWDTOSC DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DSWDTEN: Deep Sleep Watchdog Timer Enable bit 1 = DSWDT is enabled 0 = DSWDT is disabled bit 6 DSBOREN: Deep Sleep/Low-Power BOR Enable bit (does not affect operation in non Deep Sleep modes) 1 = Deep Sleep BOR is enabled in Deep Sleep 0 = Deep Sleep BOR is disabled in Deep Sleep bit 5 Unimplemented: Read as ‘0’ bit 4 DSWDTOSC: DSWDT Reference Clock Select bit 1 = DSWDT uses LPRC as the reference clock 0 = DSWDT uses SOSC as the reference clock bit 3-0 DSWDTPS: Deep Sleep Watchdog Timer Postscale Select bits The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms. 1111 = 1:2,147,483,648 (25.7 days) nominal 1110 = 1:536,870,912 (6.4 days) nominal 1101 = 1:134,217,728 (38.5 hours) nominal 1100 = 1:33,554,432 (9.6 hours) nominal 1011 = 1:8,388,608 (2.4 hours) nominal 1010 = 1:2,097,152 (36 minutes) nominal 1001 = 1:524,288 (9 minutes) nominal 1000 = 1:131,072 (135 seconds) nominal 0111 = 1:32,768 (34 seconds) nominal 0110 = 1:8,192 (8.5 seconds) nominal 0101 = 1:2,048 (2.1 seconds) nominal 0100 = 1:512 (528 ms) nominal 0011 = 1:128 (132 ms) nominal 0010 = 1:32 (33 ms) nominal 0001 = 1:8 (8.3 ms) nominal 0000 = 1:2 (2.1 ms) nominal  2011-2013 Microchip Technology Inc. DS39995D-page 245 PIC24FV32KA304 FAMILY REGISTER 26-9: DEVID: DEVICE ID REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R R R R R R R R FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-16 Unimplemented: Read as ‘0’ bit 15-8 FAMID: Device Family Identifier bits 01000101 = PIC24FV32KA304 family bit 7-0 DEV: Individual Device Identifier bits 00010111 = PIC24FV32KA304 00000111 = PIC24FV16KA304 00010011 = PIC24FV32KA302 00000011 = PIC24FV16KA302 00011001 = PIC24FV32KA301 00001001 = PIC24FV16KA301 x = Bit is unknown 00010110 = PIC24F32KA304 00000110 = PIC24F16KA304 00010010 = PIC24F32KA302 00000010 = PIC24F16KA302 00011000 = PIC24F32KA301 00001000 = PIC24F16KA301 DS39995D-page 246  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY REGISTER 26-10: DEVREV: DEVICE REVISION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R R R R — — — — REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-4 Unimplemented: Read as ‘0’ bit 3-0 REV: Minor Revision Identifier bits  2011-2013 Microchip Technology Inc. x = Bit is unknown DS39995D-page 247 PIC24FV32KA304 FAMILY 26.2 On-Chip Voltage Regulator All of the PIC24FV32KA304 family devices power their core digital logic at a nominal 3.0V. This may create an issue for designs that are required to operate at a higher typical voltage, as high as 5.0V. To simplify system design, all devices in the “FV” family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is always enabled and provides power to the core from the other VDD pins. A low-ESR capacitor (such as ceramic) must be connected to the VCAP pin (Figure 26-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is discussed in Section 2.4 “Voltage Regulator Pin (VCAP)”, and in Section 29.1 “DC Characteristics”. For “F” devices, the regulator is disabled. Instead, core logic is powered directly from VDD. This allows the devices to operate at an overall lower allowable voltage range (1.8V-3.6V). 26.2.1 VOLTAGE REGULATOR TRACKING MODE AND LOW-VOLTAGE DETECTION For all PIC24FV32KA304 devices, the on-chip regulator provides a constant voltage of 3.2V nominal to the digital core logic. The regulator can provide this level from a VDD of about 3.2V, all the way up to the device’s VDDMAX. It does not have the capability to boost VDD levels below 3.2V. In order to prevent “brown-out” conditions when the voltage drops too low for the regulator, the regulator enters Tracking mode. In Tracking mode, the regulator output follows VDD with a typical voltage drop of 150 mV. When the device enters Tracking mode, it is no longer possible to operate at full speed. To provide information about when the device enters Tracking mode, the on-chip regulator includes a simple, High/Low-Voltage Detect (HLVD) circuit. When VDD drops below full-speed operating voltage, the circuit sets the High/Low-Voltage Detect Interrupt Flag, HLVDIF (IFS4). This can be used to generate an interrupt and put the application into a low-power operational mode or trigger an orderly shutdown. Maximum device speeds as a function of VDD are shown in Section 29.1 “DC Characteristics”, in Figure 29-1 and Figure 29-1. 26.2.2 ON-CHIP REGULATOR AND POR For PIC24FV32KA304 devices, it takes a brief time, designated as TPM, for the Voltage Regulator to generate a stable output. During this time, code execution is disabled. TPM (DC Specification SY71) is applied every time the device resumes operation after any power-down, including Sleep mode. DS39995D-page 248 FIGURE 26-1: CONNECTIONS FOR THE ON-CHIP REGULATOR Regulator Enabled(1): 5.0V PIC24FV32KA304 VDD VCAP CEFC (10 F typ) Note 1: 26.3 VSS These are typical operating voltages. Refer to Section 29.0 “Electrical Characteristics” for the full operating ranges of VDD. Watchdog Timer (WDT) For the PIC24FV32KA304 family of devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 31 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the Configuration bits, WDTPS (FWDT), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler time-out periods, ranging from 1 ms to 131 seconds, can be achieved. The WDT, prescaler and postscaler are reset: • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSCx bits) or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) • When the device exits Sleep or Idle mode to resume normal operation • By a CLRWDT instruction during normal execution  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY If the WDT is enabled in hardware (FWDTEN = 11), it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bit (RCON) will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: 26.3.1 The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. WINDOWED OPERATION 26.3.2 CONTROL REGISTER The WDT is enabled or disabled by the FWDTEN Configuration bits. When both the FWDTEN Configuration bits are set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bits have been programmed to ‘10’. The WDT is enabled in software by setting the SWDTEN control bit (RCON). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments, and disable the WDT during non-critical segments, for maximum power savings. When the FWTEN bits are set to ‘01’, the WDT is only enabled in Run and Idle modes, and is disabled in Sleep. Software control of the SWDTEN bit (RCON) is disabled with this setting. The Watchdog Timer has an optional Fixed Window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction executed before that window causes a WDT Reset, similar to a WDT time-out. Windowed WDT mode is enabled by programming the Configuration bit, WINDIS (FWDT), to ‘0’. FIGURE 26-2: WDT BLOCK DIAGRAM SWDTEN FWDTEN LPRC Control WDTPS FWPSA Prescaler (5-Bit/7-Bit) LPRC Input 31 kHz Wake from Sleep WDT Counter Postscaler 1:1 to 1:32.768 WDT Overflow Reset 1 ms/4 ms All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode  2011-2013 Microchip Technology Inc. DS39995D-page 249 PIC24FV32KA304 FAMILY 26.4 Deep Sleep Watchdog Timer (DSWDT) In PIC24FV32KA304 family devices, in addition to the WDT module, a DSWDT module is present which runs while the device is in Deep Sleep, if enabled. It is driven by either the SOSC or LPRC oscillator. The clock source is selected by the Configuration bit, DSWDTOSC (FDS). The DSWDT can be configured to generate a time-out, at 2.1 ms to 25.7 days, by selecting the respective postscaler. The postscaler can be selected by the Configuration bits, DSWDTPS (FDS). When the DSWDT is enabled, the clock source is also enabled. DSWDT is one of the sources that can wake-up the device from Deep Sleep mode. 26.5 Program Verification and Code Protection For all devices in the PIC24FV32KA304 family, code protection for the boot segment is controlled by the Configuration bit, BSS0, and the general segment by the Configuration bit, GSS0. These bits inhibit external reads and writes to the program memory space This has no direct effect in normal execution mode. 26.6 In-Circuit Serial Programming PIC24FV32KA304 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGECx) and data (PGEDx), and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. 26.7 In-Circuit Debugger When MPLAB® ICD 3, MPLAB REAL ICE™ or PICkit™ 3 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx and PGEDx pins. To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS, PGECx, PGEDx and the pin pair. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. Write protection is controlled by bit, BWRP, for the boot segment and bit, GWRP, for the general segment in the Configuration Word. When these bits are programmed to ‘0’, internal write and erase operations to program memory are blocked. DS39995D-page 250  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 27.0 DEVELOPMENT SUPPORT The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C® for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers - MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 27.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2011-2013 Microchip Technology Inc. DS39995D-page 251 PIC24FV32KA304 FAMILY 27.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 27.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 27.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: 27.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 27.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS39995D-page 252  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 27.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 27.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.  2011-2013 Microchip Technology Inc. 27.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 27.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer’s PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. DS39995D-page 253 PIC24FV32KA304 FAMILY 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured Windows® programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. 27.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39995D-page 254 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta A/D, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 28.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture and is not intended to be a comprehensive reference source. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: • • • • • A literal value to be loaded into a W register or file register (specified by the value of ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand, which is a register ‘Wb’ without any address modifier • The second source operand, which is a literal value • The destination of the result (only if not the same as the first source operand), which is typically a register ‘Wd’ with or without an address modifier The control instructions may use some of the following operands: • A program memory address • The mode of the table read and table write instructions Word or byte-oriented operations Bit-oriented operations Literal operations Control operations Table 28-1 lists the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 28-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand, which is typically a register ‘Wb’ without any address modifier • The second source operand, which is typically a register ‘Ws’ with or without an address modifier • The destination of the result, which is typically a register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: • The file register specified by the value, ‘f’ • The destination, which could either be the file register, ‘f’, or the W0 register, which is denoted as ‘WREG’ Most bit-oriented instructions (including rotate/shift instructions) have two operands: The literal instructions that involve data movement may use some of the following operands: simple All instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all of the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the Program Counter (PC) is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’)  2011-2013 Microchip Technology Inc. DS39995D-page 255 PIC24FV32KA304 FAMILY TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0000h...1FFFh} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; LSB must be ‘0’ None Field does not require an entry, may be blank PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing) Wn One of 16 working registers {W0..W15} Wnd One of 16 destination working registers {W0..W15} Wns One of 16 source working registers {W0..W15} WREG W0 (working register used in File register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } DS39995D-page 256  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z AND f f = f .AND. WREG 1 1 N, Z AND f,WREG WREG = f .AND. WREG 1 1 N, Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None BRA LE,Expr Branch if Less than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None BRA LT,Expr Branch if Less than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW.C Ws,Wb Write C bit to Ws 1 1 None BSW.Z Ws,Wb Write Z bit to Ws 1 1 None BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3)  2011-2013 Microchip Technology Inc. DS39995D-page 257 PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax # of Words Description # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.Z Ws,Wb Bit Test Ws to Z 1 1 BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None Clear Watchdog Timer 1 1 WDTO, Sleep CLRWDT CLRWDT COM COM f f=f 1 1 N, Z COM f,WREG WREG = f 1 1 N, Z COM Ws,Wd Wd = Ws 1 1 N, Z CP f Compare f with WREG 1 1 C, DC, N, OV, Z CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, Z CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,Ws Compare Wb with Ws, with Borrow (Wb – Ws – C) 1 1 C, DC, N, OV, Z CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 None (2 or 3) CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 None (2 or 3) CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 None (2 or 3) CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if  1 1 None (2 or 3) DAW DAW Wn Wn = Decimal Adjust Wn 1 1 DEC DEC f f = f –1 1 1 C, DC, N, OV, Z DEC f,WREG WREG = f –1 1 1 C, DC, N, OV, Z CP C DEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, Z DEC2 f f=f–2 1 1 C, DC, N, OV, Z DEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, Z DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C DEC2 DS39995D-page 258  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic GOTO INC INC2 Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC2 Ws,Wd Wd = Ws + 2 1 1 IOR f f = f .IOR. WREG 1 1 N, Z IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z LNK LNK #lit14 Link Frame Pointer 1 1 None LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z MOV f,Wn Move f to Wn 1 1 None MOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 None MOV f Move f to f 1 1 N, Z MOV f,WREG Move f to WREG 1 1 N, Z MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N, Z MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None NEG f f=f+1 1 1 C, DC, N, OV, Z NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z NEG Ws,Wd IOR MOV MUL NEG NOP POP Wd = Ws + 1 1 1 C, DC, N, OV, Z NOP No Operation 1 1 None NOPR No Operation 1 1 None POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1 2 None Pop Shadow Registers 1 1 All PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None Push Shadow Registers 1 1 None POP.S PUSH PUSH.S  2011-2013 Microchip Technology Inc. DS39995D-page 259 PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 None RETFIE RETFIE Return from Interrupt 1 3 (2) None RETLW RETLW Return with Literal in Wn 1 3 (2) None RETURN RETURN Return from Subroutine 1 3 (2) None RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z C, N, Z RLNC RRC RRNC #lit10,Wn RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 RLNC f f = Rotate Left (No Carry) f 1 1 N, Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z N, Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 RRC f f = Rotate Right through Carry f 1 1 C, N, Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z RRNC f f = Rotate Right (No Carry) f 1 1 N, Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z SETM SETM f f = FFFFh 1 1 None SETM WREG WREG = FFFFh 1 1 None SETM Ws Ws = FFFFh 1 1 None SL f f = Left Shift f 1 1 C, N, OV, Z SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z SUB f f = f – WREG 1 1 C, DC, N, OV, Z SUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, Z SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, Z SL SUB SUBB SUBR SUBBR SWAP TBLRDH SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, Z SUBR f f = WREG – f 1 1 C, DC, N, OV, Z SUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C, DC, N, OV, Z SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, Z C, DC, N, OV, Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None TBLRDH Ws,Wd Read Prog to Wd 1 2 None DS39995D-page 260  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDL TBLRDL Ws,Wd Read Prog to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws to Prog 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N ZE  2011-2013 Microchip Technology Inc. DS39995D-page 261 PIC24FV32KA304 FAMILY NOTES: DS39995D-page 262  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FV32KA304 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FV32KA304 family devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +135°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS (PIC24FVXXKA30X) ....................................................................... -0.3V to +6.5V Voltage on VDD with respect to VSS (PIC24FXXKA30X) .......................................................................... -0.3V to +4.5V Voltage on any combined analog and digital pin with respect to VSS ............................................ -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS ....................................................................... -0.3V to (VDD + 0.3V) Voltage on MCLR/VPP pin with respect to VSS ......................................................................................... -0.3V to +9.0V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin(1)...........................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports(1) ...............................................................................................................200 mA Note 1: Maximum allowable current is a function of the device maximum power dissipation (see Table 29-1). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2011-2013 Microchip Technology Inc. DS39995D-page 263 PIC24FV32KA304 FAMILY 29.1 DC Characteristics Voltage (VDD) FIGURE 29-1: PIC24FV32KA304 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL AND EXTENDED) 5.5V 5.5V 3.20V 3.20V 2.00V 8 MHz 32 MHz Frequency Note: For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz * (VDD – 2.0) + 8 MHz. Voltage (VDD) FIGURE 29-2: PIC24F32KA304 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL AND EXTENDED) 3.60V 3.60V 3.00V 3.00V 1.80V 8 MHz Note: DS39995D-page 264 Frequency 32 MHz For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz * (VDD – 1.8) + 8 MHz.  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TABLE 29-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W PDMAX (TJ – TA)/JA W I/O Pin Power Dissipation: PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation TABLE 29-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes Package Thermal Resistance, 20-Pin SPDIP JA 62.4 — °C/W 1 Package Thermal Resistance, 28-Pin SPDIP JA 60 — °C/W 1 Package Thermal Resistance, 20-Pin SSOP JA 108 — °C/W 1 Package Thermal Resistance, 28-Pin SSOP JA 71 — °C/W 1 Package Thermal Resistance, 20-Pin SOIC JA 75 — °C/W 1 Package Thermal Resistance, 28-Pin SOIC JA 80.2 — °C/W 1 Package Thermal Resistance, 28-Pin QFN JA 32 — °C/W 1 Package Thermal Resistance, 44-Pin QFN JA 29 — °C/W 1 Package Thermal Resistance, 48-Pin UQFN JA — — °C/W 1 Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. TABLE 29-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param No. Symbol DC10 VDD DC12 Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min Typ(1) Supply Voltage 1.8 — 3.6 2.0 — 5.5 V For FV devices VDR RAM Data Retention Voltage(2) 1.5 — — V For F devices 1.7 — — V For FV devices DC16 VPOR VDD Start Voltage to Ensure Internal Power-on Reset Signal VSS — 0.7 V DC17 SVDD VDD Rise Rate to Ensure Internal Power-on Reset Signal 0.05 — — Note 1: 2: Characteristic Max Units V Conditions For F devices V/ms 0-3.3V in 0.1s 0-2.5V in 60 ms Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data.  2011-2013 Microchip Technology Inc. DS39995D-page 265 PIC24FV32KA304 FAMILY TABLE 29-4: HIGH/LOW–VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol No. DC18 Characteristic HLVD Voltage on VDD Transition VHLVD HLVDL = 0000(2) Typ Max Units — — 1.90 V HLVDL = 0001 1.86 — 2.13 V HLVDL = 0010 2.08 — 2.35 V HLVDL = 0011 2.22 — 2.53 V HLVDL = 0100 2.30 — 2.62 V HLVDL = 0101 2.49 — 2.84 V HLVDL = 0110 2.73 — 3.10 V HLVDL = 0111 2.86 — 3.25 V HLVDL = 1000 3.00 — 3.41 V HLVDL = 1001 3.16 — 3.59 V HLVDL = 1010(1) 3.33 — 3.79 V 1011(1) 3.53 — 4.01 V HLVDL = 1100(1) 3.74 — 4.26 V HLVDL = 1101(1) 4.00 — 4.55 V 1110(1) 4.28 — 4.87 V HLVDL = HLVDL = Note 1: 2: Min Conditions These trip points should not be used on PIC24FXXKA30X devices. This trip point should not be used on PIC24FVXXKA30X devices. TABLE 29-5: BOR TRIP POINTS Standard Operating Conditions: Operating temperature Param Sym No. 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Characteristic DC15 BOR Hysteresis DC19 BOR Voltage on VDD Transition Note 1: 2: 3: BORV = 00 Min Typ Max Units — 5 — mV — — — — Conditions Valid for LPBOR and DSBOR (Note 1) BORV = 01 2.90 3 3.38 V BORV = 10 2.53 2.7 3.07 V BORV = 11 1.75 1.85 2.05 V (Note 2) BORV = 11 1.95 2.05 2.16 V (Note 3) LPBOR re-arms the POR circuit but does not cause a BOR. This is valid for PIC24F (3.3V) devices. This is valid for PIC24FV (5V) devices. DS39995D-page 266  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TABLE 29-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: DC CHARACTERISTICS Parameter No. Operating temperature: Device 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Typical Max Units Conditions 269 450 µA 2.0V 465 830 µA 5.0V 200 330 µA 1.8V IDD Current D20 PIC24FV32KA3XX PIC24F32KA3XX DC22 DC24 DC26 DC30 410 750 µA 3.3V PIC24FV32KA3XX 490 — µA 2.0V 880 — µA 5.0V PIC24F32KA3XX 407 — µA 1.8V 800 — µA 3.3V PIC24FV32KA3XX 13.0 20.0 mA 5.0V PIC24F32KA3XX 12.0 18.0 mA 3.3V PIC24FV32KA3XX 2.0 — mA 2.0V 3.5 — mA 5.0V PIC24F32KA3XX 1.80 — mA 1.8V 3.40 — mA 3.3V PIC24FV32KA3XX 48.0 250 µA 2.0V 75.0 450 µA 5.0V 8.1 28 µA 1.8V 13.50 150 µA 3.3V PIC24F32KA3XX Legend: Note 1: 0.5 MIPS, FOSC = 1 MHz(1) 1 MIPS, FOSC = 2 MHz(1) 16 MIPS, FOSC = 32 MHz(1) FRC (4 MIPS), FOSC = 8 MHz LPRC (15.5 KIPS), FOSC = 31 kHz Unshaded rows represent PIC24F32KA3XX devices and shaded rows represent PIC24FV32KA3XX devices. Oscillator is in External Clock mode (FOSCSEL = 010, FOSC = 00).  2011-2013 Microchip Technology Inc. DS39995D-page 267 PIC24FV32KA304 FAMILY TABLE 29-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: DC CHARACTERISTICS Parameter No. Operating temperature: Device 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Typical Max Units 120 200 µA Conditions Idle Current (IIDLE) DC40 PIC24FV32KA3XX PIC24F32KA3XX DC42 PIC24FV32KA3XX PIC24F32KA3XX DC44 DC46 430 µA 5.0V 50 100 µA 1.8V 90 370 µA 3.3V 165 — µA 2.0V 260 — µA 5.0V 95 — µA 1.8V 180 — µA 3.3V 3.1 6.5 mA 5.0V PIC24F32KA3XX 2.9 6.0 mA 3.3V PIC24FV32KA3XX 0.65 — mA 2.0V 1.0 — mA 5.0V 0.55 — mA 1.8V 1.0 — mA 3.3V 60 200 µA 2.0V 70 350 µA 5.0V 2.2 18 µA 1.8V 4.0 60 µA 3.3V PIC24FV32KA3XX PIC24F32KA3XX Legend: Note 1: 160 PIC24FV32KA3XX PIC24F32KA3XX DC50 2.0V 0.5 MIPS, FOSC = 1 MHz(1) 1 MIPS, FOSC = 2 MHz(1) 16 MIPS, FOSC = 32 MHz(1) FRC (4 MIPS), FOSC = 8 MHz LPRC (15.5 KIPS), FOSC = 31 kHz Unshaded rows represent PIC24F32KA3XX devices and shaded rows represent PIC24FV32KA3XX devices. Oscillator is in External Clock mode (FOSCSEL = 010, FOSC = 00). DS39995D-page 268  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: DC CHARACTERISTICS Parameter No. Device Operating temperature Typical(1) Max 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Units Conditions Power-Down Current (IPD) DC60 PIC24FV32KA3XX — 6.0 — 6.0 — PIC24F32KA3XX 0.025 — 0.040 — DC61 PIC24FV32KA3XX DC70 PIC24FV32KA3XX PIC24F32KA3XX Legend: Note 1: 2: 3: 4: 5: 6: -40°C 8.0 8.5 +25°C µA +60°C 9.0 +85°C 15 +125°C — -40°C 8.0 9.0 +25°C µA +60°C 10.0 +85°C 15 +125°C — -40°C 0.80 +25°C 1.5 µA +60°C 2.0 +85°C 7.5 +125°C — -40°C 1.0 +25°C 2.0 2.0V µA +60°C 3.0 +85°C 7.5 +125°C 5.0V Sleep Mode(2) 1.8V 3.3V 0.25 — µA -40°C 2.0V 0.35 3.0 µA +85°C 5.0V — 7.5 µA +125°C 5.0V 0.03 — µA -40°C 2.0V 0.10 2.0 µA +85°C 5.0V — 6.0 µA +125°C 5.0V 0.02 — µA -40°C 1.8V 0.08 1.2 µA +85°C 3.3V — 1.2 µA +125°C 3.3V Low-Voltage Sleep Mode(2) Deep Sleep Mode Unshaded rows represent PIC24F32KA3XX devices and shaded rows represent PIC24FV32KA3XX devices. Data in the Typical column is at 3.3V, +25°C (PIC24F32KA3XX) or 5.0V, +25°C (PIC24FV32KA3XX) unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as outputs and set low, PMSLP is set to ‘0’ and WDT, etc., are all switched off. The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. This current applies to Sleep only. This current applies to Sleep and Deep Sleep. This current applies to Deep Sleep only.  2011-2013 Microchip Technology Inc. DS39995D-page 269 PIC24FV32KA304 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) Standard Operating Conditions: DC CHARACTERISTICS Parameter No. Device Operating temperature Typical(1) 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Max Units 0.50 — µA 0.70 1.5 — 1.5 0.50 Conditions Module Differential Current (IPD)(3) DC71 PIC24FV32KA3XX PIC24F32KA3XX DC72 PIC24FV32KA3XX PIC24F32KA3XX DC75 PIC24FV32KA3XX PIC24F32KA3XX DC76 PIC24FV32KA3XX PIC24F32KA3XX Legend: Note 1: 2: 3: 4: 5: 6: -40°C 2.0V µA +85°C 5.0V µA +125°C 5.0V — µA -40°C 1.8V 0.70 1.5 µA +85°C 3.3V — 1.5 µA +125°C 3.3V 0.80 — µA -40°C 2.0V 1.50 2.0 µA +85°C 5.0V — 2.0 µA +125°C 5.0V 0.70 — µA -40°C 1.8V 1.0 1.5 µA +85°C 3.3V — 1.5 µA +125°C 3.3V 5.4 — µA -40°C 2.0V 8.1 14.0 µA +85°C 5.0V — 14.0 µA +125°C 5.0V 4.9 — µA -40°C 1.8V 7.5 14.0 µA +85°C 3.3V — 14.0 µA +125°C 3.3V 5.6 — µA -40°C 2.0V 6.5 11.2 µA -40°C 5.0V — 11.2 µA +125°C 5.0V 5.6 — µA -40°C 1.8V 6.0 11.2 µA +85°C 3.3V — 11.2 µA +125°C 3.3V Watchdog Timer Current: IWDT(4) 32 kHz Crystal with RTCC, DSWDT or Timer1: ISOSC (SOSCSEL = 0)(5) IHLVD(4) IBOR(4) Unshaded rows represent PIC24F32KA3XX devices and shaded rows represent PIC24FV32KA3XX devices. Data in the Typical column is at 3.3V, +25°C (PIC24F32KA3XX) or 5.0V, +25°C (PIC24FV32KA3XX) unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as outputs and set low, PMSLP is set to ‘0’ and WDT, etc., are all switched off. The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. This current applies to Sleep only. This current applies to Sleep and Deep Sleep. This current applies to Deep Sleep only. DS39995D-page 270  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) Standard Operating Conditions: DC CHARACTERISTICS Parameter No. Device Operating temperature Typical(1) 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Max Units 0.03 — µA 0.05 0.20 — 0.30 0.03 Conditions Module Differential Current (IPD)(3) DC78 PIC24FV32KA3XX PIC24F32KA3XX DC80 PIC24FV32KA3XX PIC24F32KA3XX Legend: Note 1: 2: 3: 4: 5: 6: -40°C 2.0V µA +85°C 5.0V µA +125°C 5.0V — µA -40°C 1.8V 0.05 0.20 µA +85°C 3.3V — 0.30 µA +125°C 3.3V 0.20 — µA -40°C 2.0V 0.70 1.5 µA +85°C 5.0V — 1.5 µA +125°C 5.0V 0.20 — µA -40°C 1.8V 0.35 0.8 µA +85°C 3.3V — 1.5 µA +125°C 3.3V Deep Sleep BOR: ILPBOR(5) Deep Sleep WDT: IDSWDT (LPRC)(6) Unshaded rows represent PIC24F32KA3XX devices and shaded rows represent PIC24FV32KA3XX devices. Data in the Typical column is at 3.3V, +25°C (PIC24F32KA3XX) or 5.0V, +25°C (PIC24FV32KA3XX) unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as outputs and set low, PMSLP is set to ‘0’ and WDT, etc., are all switched off. The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. This current applies to Sleep only. This current applies to Sleep and Deep Sleep. This current applies to Deep Sleep only.  2011-2013 Microchip Technology Inc. DS39995D-page 271 PIC24FV32KA304 FAMILY TABLE 29-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param No. Sym VIL Characteristic Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min Typ(1) Max Units Conditions Input Low Voltage(4) DI10 I/O Pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.2 VDD V DI17 OSCI (HS mode) VSS — 0.2 VDD V DI18 I/O Pins with I2C™ Buffer VSS — 0.3 VDD V SMBus is disabled DI19 I/O Pins with SMBus Buffer VSS — 0.8 V SMBus is enabled I/O Pins: with Analog Functions Digital Only 0.8 VDD 0.8 VDD — — VDD VDD V V DI25 MCLR 0.8 VDD — VDD V DI26 OSCI (XT mode) 0.7 VDD — VDD V DI27 OSCI (HS mode) 0.7 VDD — VDD V DI28 I/O Pins with I2C Buffer: with Analog Functions Digital Only 0.7 VDD 0.7 VDD — — VDD VDD V V 2.1 — VDD V 2.5V  VPIN  VDD 50 250 500 A VDD = 3.3V, VPIN = VSS — 0.05 0.1 A VSS  VPIN  VDD, Pin at high-impedance VIH DI20 DI29 Input High Voltage(4) I/O Pins with SMBus DI30 ICNPU CNx Pull-up Current IIL Input Leakage Current(2,3) DI50 I/O Ports DI55 MCLR — — 0.1 A VSS VPIN VDD DI56 OSCI — — 5 A VSS VPIN VDD, XT and HS modes Note 1: 2: 3: 4: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Refer to Table 1-3 for I/O pin buffer types. DS39995D-page 272  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TABLE 29-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param No. Sym VOL DO10 OSC2/CLKO VOH DO20 Typ(1) Max Units — — 0.4 V IOL = 8.0 mA VDD = 4.5V — — 0.4 V IOL = 4.0 mA VDD = 3.6V — — 0.4 V IOL = 3.5 mA VDD = 2.0V Conditions — — 0.4 V IOL = 2.0 mA VDD = 4.5V — — 0.4 V IOL = 1.2 mA VDD = 3.6V — — 0.4 V IOL = 0.4 mA VDD = 2.0V Output High Voltage All I/O Pins DO26 Min Output Low Voltage All I/O Pins DO16 Note 1: Characteristic Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended OSC2/CLKO 3.8 — — V IOH = -3.5 mA VDD = 4.5V 3 — — V IOH = -3.0 mA VDD = 3.6V 1.6 — — V IOH = -1.0 mA VDD = 2.0V 3.8 — — V IOH = -2.0 mA VDD = 4.5V 3 — — V IOH = -1.0 mA VDD = 3.6V 1.6 — — V IOH = -0.5 mA VDD = 2.0V Data in “Typ” column is at +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min Typ(1) 10,000(2) VMIN Max Units — — E/W — 3.6 V — 2 — ms Conditions Program Flash Memory D130 EP Cell Endurance D131 VPR VDD for Read D133A TIW Self-Timed Write Cycle Time D134 TRETD Characteristic Retention 40 — — Year D135 IDDP — 10 — mA Note 1: 2: Supply Current During Programming VMIN = Minimum operating voltage Provided no other specifications are violated Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Self-write and block erase.  2011-2013 Microchip Technology Inc. DS39995D-page 273 PIC24FV32KA304 FAMILY TABLE 29-12: DC CHARACTERISTICS: DATA EEPROM MEMORY Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param No. Sym Min Typ(1) Max Units 100,000 — — E/W VMIN — 3.6 V Characteristic Conditions Data EEPROM Memory D140 EPD Cell Endurance D141 VPRD VDD for Read D143A TIWD Self-Timed Write Cycle Time — 4 — ms D143B TREF Number of Total Write/Erase Cycles Before Refresh — 10M — E/W D144 TRETDD Characteristic Retention 40 — — Year D145 IDDPD — 7 — mA Note 1: Supply Current During Programming VMIN = Minimum operating voltage Provided no other specifications are violated Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. TABLE 29-13: DC CHARACTERISTICS: COMPARATOR SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated) Param No. Symbol Characteristic Min Typ Max Units D300 VIOFF Input Offset Voltage — 20 40 mV D301 VICM Input Common-Mode Voltage 0 — VDD V D302 CMRR Common-Mode Rejection Ratio 55 — — dB Comments TABLE 29-14: DC CHARACTERISTICS: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated) Param No. Symbol Characteristic Min Typ Max Units VRD310 CVRES Resolution — — VDD/32 LSb VRD311 CVRAA Absolute Accuracy — — AVDD – 1.5 LSb VRD312 CVRUR Unit Resistor Value (R) — 2k —  DS39995D-page 274 Comments  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TABLE 29-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +125°C (unless otherwise stated) Param No. Symbol Characteristics Min Typ Max Units Comments DVR10 VBG Band Gap Reference Voltage 0.973 1.024 1.075 V DVR11 TBG Band Gap Reference Start-up Time — 1 — ms DVR20 VRGOUT Regulator Output Voltage 3.1 3.3 3.6 V -40°C < TA < +85°C 3.0 3.19 3.6 V -40°C < TA < +125°C Series resistance < 3 Ohm recommended; < 5 Ohm is required. DVR21 CEFC External Filter Capacitor Value 4.7 10 — F DVR30 VLVR Retention Regulator Output Voltage — 2.6 — V TABLE 29-16: CTMU CURRENT SOURCE SPECIFICATIONS DC CHARACTERISTICS Param Sym No. Characteristic Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min Typ(1) Max Units Comments DCT10 IOUT1 CTMU Current Source, Base Range — 550 — nA CTMUICON = 01 DCT11 IOUT2 CTMU Current Source, 10x Range — 5.5 — A CTMUICON = 10 DCT12 IOUT3 CTMU Current Source, 100x Range — 55 — A CTMUICON = 11 DCT13 IOUT4 CTMU Current Source, 1000x Range — 550 — A CTMUICON = 00 (Note 2) DCT20 VF Temperature Diode Forward Voltage — .76 — V DCT21 V Voltage Change per Degree Celsius — 1.6 — mV/°C Note 1: 2: Conditions 2.5V < VDD < VDDMAX Nominal value at the center point of the current trim range (CTMUICON = 000000). On PIC24F32KA parts, the current output is limited to the typical current value when IOUT4 is chosen. Do not use this current range with a temperature sensing diode.  2011-2013 Microchip Technology Inc. DS39995D-page 275 PIC24FV32KA304 FAMILY 29.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FV32KA304 family AC characteristics and timing parameters. TABLE 29-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Operating voltage VDD range as described in Section 29.1 “DC Characteristics”. AC CHARACTERISTICS FIGURE 29-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – For All Pins Except OSCO Load Condition 2 – For OSCO VDD/2 CL Pin RL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSCO 15 pF for OSCO output VSS TABLE 29-18: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions 15 pF In XT and HS modes when the external clock is used to drive OSCI COSC2 OSCO/CLKO Pin — — DO56 CIO All I/O Pins and OSCO — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode DO50 Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS39995D-page 276  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 29-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OS30 OS30 Q1 Q2 Q3 OSCI OS20 OS31 OS31 OS25 CLKO OS40 OS41 TABLE 29-19: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param Sym No. OS10 Min Typ(1) Max Units DC 4 — — 32 8 MHz MHz EC ECPLL Oscillator Frequency 0.2 4 4 31 — — — — 4 25 8 33 MHz MHz MHz kHz XT HS XTPLL SOSC — — — — 62.5 — DC ns Characteristic FOSC External CLKI Frequency (External clocks allowed only in EC mode) OS15 Conditions OS20 TOSC TOSC = 1/FOSC OS25 TCY Instruction Cycle Time(2) OS30 TosL, External Clock in (OSCI) TosH High or Low Time 0.45 x TOSC — — ns EC OS31 TosR, External Clock in (OSCI) TosF Rise or Fall Time — — 20 ns EC OS40 TckR — 6 10 ns — 6 10 ns OS41 TckF Note 1: 2: 3: CLKO Rise Time(3) (3) CLKO Fall Time See Parameter OS10 for FOSC value Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).  2011-2013 Microchip Technology Inc. DS39995D-page 277 PIC24FV32KA304 FAMILY TABLE 29-20: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. Characteristic(1) Sym Min Typ(2) Max Units Conditions OS50 FPLLI PLL Input Frequency Range 4 — 8 MHz ECPLL, HSPLL modes, -40°C  TA  +85°C OS51 FSYS PLL Output Frequency Range 16 — 32 MHz -40°C  TA  +85°C OS52 TLOCK PLL Start-up Time (Lock Time) — 1 2 ms OS53 DCLK -2 1 2 % Note 1: 2: CLKO Stability (Jitter) Measured over a 100 ms period These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 29-21: AC CHARACTERISTICS: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min Typ Max Units Conditions Internal FRC Accuracy @ 8 MHz(1) F20 FRC -2 — +2 % -5 — +5 % -15 — 15 % 3.0V  VDD  3.6V, F device 3.2V  VDD  5.5V, FV device +25°C -40°C  TA +85°C 1.8V  VDD  3.6V, F device 2.0V  VDD  5.5V, FV device LPRC @ 31 kHz(2) F21 Note 1: 2: Frequency is calibrated at +25°C and 3.3V. The OSCTUN bits can be used to compensate for temperature drift. The change of LPRC frequency as VDD changes. TABLE 29-22: INTERNAL RC OSCILLATOR SPECIFICATIONS AC CHARACTERISTICS Param No. Characteristic(1) Sym TFRC FRC Start-up Time TLPRC LPRC Start-up Time Note 1: Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min Typ Max Units — 5 — s — 70 — s Conditions These parameters are characterized but not tested in manufacturing. DS39995D-page 278  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 29-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 29-3 for load conditions. TABLE 29-23: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min Typ(1) Max Units DO31 TIOR Port Output Rise Time — 10 25 ns DO32 TIOF Port Output Fall Time — 10 25 ns DI35 TINP INTx Pin High or Low Time (output) 20 — — ns DI40 TRBP CNx High or Low Time (input) 2 — — TCY Note 1: Conditions Data in “Typ” column is at 3.3V, +25°C (PIC24F32KA3XX); 5.0V, +25°C (PIC24FV32KA3XX), unless otherwise stated.  2011-2013 Microchip Technology Inc. DS39995D-page 279 PIC24FV32KA304 FAMILY TABLE 29-24: COMPARATOR TIMINGS Param No. Symbol Characteristic Min Typ Max Units 300 TRESP Response Time*(1) — 150 400 ns 301 TMC2OV Comparator Mode Change to Output Valid* — — 10 s * Note 1: Comments Parameters are characterized but not tested. Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 29-25: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS Param No. Symbol VR310 TSET Note 1: Characteristic Min Typ Max Units — — 10 s Settling Time(1) Comments Settling time is measured while CVRSS = 1 and the CVR bits transition from ‘0000’ to ‘1111’. FIGURE 29-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD MCLR SY12 SY10 Internal POR PWRT SY11 SYSRST System Clock Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 DS39995D-page 280  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 29-7: BROWN-OUT RESET CHARACTERISTICS VDDCORE (Device not in Brown-out Reset) DC15 DC19 (Device in Brown-out Reset) SY25 Reset (Due to BOR) TVREG + TRST TABLE 29-26: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: AC CHARACTERISTICS Param Symbol No. Operating temperature Characteristic 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min. Typ(1) Max. Units — s Conditions SY10 TmcL MCLR Pulse Width (low) 2 — SY11 TPWRT Power-up Timer Period 50 64 90 ms SY12 TPOR Power-on Reset Delay 1 5 10 s SY13 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset — — 100 ns SY20 TWDT Watchdog Timer Time-out Period 0.85 1.0 1.15 ms 1.32 prescaler 3.4 4.0 4.6 ms 1:128 prescaler SY25 TBOR Brown-out Reset Pulse Width 1 — — s SY35 TFSCM Fail-Safe Clock Monitor Delay — 2.0 2.3 s SY45 TRST Internal State Reset Time — 5 — s SY50 TVREG On-Chip Voltage Regulator Output Delay — 10 — s SY55 TLOCK PLL Start-up Time — 100 — s SY65 TOST Oscillator Start-up Time — 1024 — TOSC SY70 TDSWU Wake-up from Deep Sleep Time — 100 — s Based on full discharge of 10 F capacitor on VCAP; includes TPOR and TRST SY71 TPM Program Memory Wake-up Time — 1 — s Sleep wake-up with PMSLP = 0 SY72 TLVR Retention Regulator Wake-up Time — 250 — s SY73 THVLD HVLD Interrupt Response Time — 2 — s Note 1: 2: (Note 2) Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. This applies to PIC24FV32KA3XX devices only.  2011-2013 Microchip Technology Inc. DS39995D-page 281 PIC24FV32KA304 FAMILY FIGURE 29-8: TIMER1/2/3/4/5 EXTERNAL CLOCK INPUT TIMING TxCK Pin TtL TtH TtP TABLE 29-27: TIMER1/2/3/4/5 EXTERNAL CLOCK INPUT REQUIREMENTS Param. Symbol No. TtH Characteristic TxCK High Pulse Time TtL TxCK Low Pulse Time TtP TxCK External Input Period FIGURE 29-9: Sync w/Prescaler Min Max Units TCY + 20 — ns Async w/Prescaler 10 — ns Async Counter 20 — ns TCY + 20 — ns Sync w/Prescaler Async w/Prescaler 10 — ns Async Counter 20 — ns Sync w/Prescaler 2 * TCY + 40 — ns Async w/Prescaler Greater of: 20 or 2 * TCY + 40 N — ns Async Counter 40 — ns Delay for Input Edge Synchronous to Timer Increment Asynchronous 1 2 TCY — 20 ns Conditions Must also meet Parameter Ttp Must also meet Parameter Ttp N = Prescale Value (1, 4, 8, 16) INPUT CAPTURE x TIMINGS ICx Pin (Input Capture Mode) IC10 IC11 IC15 TABLE 29-28: INPUT CAPTURE x REQUIREMENTS Param. Symbol No. IC10 TccL Characteristic ICx Input Low Time – Synchronous Timer No Prescaler With Prescaler IC11 TccH ICx Input Low Time – Synchronous Timer IC15 TccP ICx Input Period – Synchronous Timer DS39995D-page 282 No Prescaler With Prescaler Min Max Units TCY + 20 — ns 20 — ns TCY + 20 — ns 20 — ns 2 * TCY + 40 N — ns Conditions Must also meet Parameter IC15 Must also meet Parameter IC15 N = prescale value (1, 4, 16)  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 29-10: OUTPUT COMPARE x TIMINGS OCx (Output Compare or PWM Mode) OC11 TABLE 29-29: OUTPUT CAPTURE REQUIREMENTS Param. No. Symbol OC11 TCCR OC10 TCCF FIGURE 29-11: OC10 Characteristic OC1 Output Rise Time OC1 Output Fall Time Min Max Units — 10 ns — — ns — 10 ns — — ns Conditions PWM MODULE TIMING REQUIREMENTS OC20 OCFx OC15 PWM TABLE 29-30: PWM TIMING REQUIREMENTS Param. Symbol No. OC15 OC20 Characteristic Min Typ† Max Units Conditions TFD Fault Input to PWM I/O Change — — 25 ns VDD = 3.0V, -40C to +125C TFH Fault Input Pulse Width 50 — — ns VDD = 3.0V, -40C to +125C † Data in “Typ” column is at 5V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested.  2011-2013 Microchip Technology Inc. DS39995D-page 283 PIC24FV32KA304 FAMILY FIGURE 29-12: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM34 IM31 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 29-3 for load conditions. TABLE 29-31: I2C™ BUS START/STOP BIT TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial) -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param Symbol No. IM30 TSU:STA Start Condition Setup Time THD:STA Start Condition Hold Time IM31 TSU:STO Stop Condition Setup Time IM33 Min(1) Max Units 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s Characteristic 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s mode(2) TCY/2 (BRG + 1) — s 100 kHz mode TCY/2 (BRG + 1) — ns 400 kHz mode TCY/2 (BRG + 1) — ns 1 MHz mode(2) TCY/2 (BRG + 1) — ns 1 MHz THD:STO Stop Condition IM34 Hold Time Note 1: 2: Conditions Only relevant for Repeated Start condition After this period, the first clock pulse is generated 2 BRG is the value of the I C™ Baud Rate Generator. Refer to Section 17.3 “Setting Baud Rate When Operating as a Bus Master” for details. Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only). DS39995D-page 284  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 29-13: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM11 IM21 SCLx IM10 IM20 IM26 IM25 SDAx In IM45 IM40 SDAx Out Note: Refer to Figure 29-3 for load conditions. TABLE 29-32: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. IM10 IM11 IM20 IM21 IM25 IM26 IM40 IM45 IM50 Note Symbol Characteristic Min(1) Max Units Conditions Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s (2) 1 MHz mode TCY/2 (BRG + 1) — s TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be Fall Time from 10 to 400 pF 400 kHz mode 20 + 0.1 CB 300 ns (2) 1 MHz mode — 100 ns TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be Rise Time from 10 to 400 pF 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(2) — 300 ns Data Input 100 kHz mode 250 — ns TSU:DAT Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) 100 — ns THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(2) 0 — ns TAA:SCL Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns (2) 1 MHz mode — — ns TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before a new 400 kHz mode 1.3 — s transmission can start 1 MHz mode(2) 0.5 — s CB Bus Capacitive Loading — 400 pF 2 1: BRG is the value of the I C Baud Rate Generator. Refer to Section 17.3 “Setting Baud Rate When Operating as a Bus Master” for details. 2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only). TLO:SCL  2011-2013 Microchip Technology Inc. DS39995D-page 285 PIC24FV32KA304 FAMILY FIGURE 29-14: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS11 IS21 IS10 SCLx IS25 IS20 IS26 SDAx In IS45 IS40 SDAx Out TABLE 29-33: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C (Industrial) -40°C  TA  +125°C (Extended) AC CHARACTERISTICS Param No. IS10 IS11 IS20 IS21 IS25 IS26 IS40 Symbol TLO:SCL THI:SCL TF:SCL TR:SCL TSU:DAT THD:DAT TAA:SCL Characteristic Clock Low Time Clock High Time SDAx and SCLx Fall Time SDAx and SCLx Rise Time Min Max Units 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s 100 kHz mode — 300 ns ns 400 kHz mode 20 + 0.1 CB 300 1 MHz mode(1) — 100 ns 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) — 300 ns 100 kHz mode 250 — ns 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 1 MHz mode(1) 0 0.3 s Output Valid From 100 kHz mode Clock 400 kHz mode 0 3500 ns 0 1000 ns Data Input Setup Time Data Input Hold Time IS50 Note 1: TBF:SDA CB Bus Free Time (1) 0 350 ns 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s 1 MHz mode(1) 0.5 — s — 400 pF 1 MHz mode IS45 Conditions Bus Capacitive Loading CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Time the bus must be free before a new transmission can start Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only). DS39995D-page 286  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) FIGURE 29-15: SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition TABLE 29-34: I2C™ BUS START/STOP BITS TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C (Industrial) -40°C  TA  +125°C (Extended) AC CHARACTERISTICS Param No. IS30 IS31 IS33 IS34 Note 1: Symbol TSU:STA THD:STA TSU:STO THD:STO Characteristic Start Condition Setup Time 100 kHz mode Min Max Units Conditions 4.7 — s Only relevant for Repeated Start condition 400 kHz mode 0.6 — s 1 MHz mode(1) 0.25 — s 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s 1 MHz mode(1) 0.25 — s 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s 1 MHz mode(1) 0.6 — s Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — ns 1 MHz mode(1) 250 — ns Start Condition Hold Time Stop Condition Setup Time After this period, the first clock pulse is generated Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).  2011-2013 Microchip Technology Inc. DS39995D-page 287 PIC24FV32KA304 FAMILY FIGURE 29-16: UARTx BAUD RATE GENERATOR OUTPUT TIMING UxBRG + 1 * TCY TLW THW UxBCLK TBLD TBHD UxTX FIGURE 29-17: UARTx START BIT EDGE DETECTION UxBRG Any Value Start bit Detected, UxBRG Started TCY Cycle Clock TSETUP TSTDELAY UxRX TABLE 29-35: UARTx TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C (Industrial) -40°C  TA  +125°C (Extended) AC CHARACTERISTICS Symbol Characteristics Min Typ Max Units 20 TCY/2 — ns TLW UxBCLK High Time THW UxBCLK Low Time 20 (TCY * UXBRG) + TCY/2 — ns TBLD UxBCLK Falling Edge Delay from UxTX -50 — 50 ns TBHD UxBCLK Rising Edge Delay from UxTX TCY/2 – 50 — TCY/2 + 50 ns TWAK Minimum Low on UxRX Line to Cause Wake-up — 1 — s TCTS Minimum Low on UxCTS Line to Start Transmission Tcy — — ns TSETUP Start bit Falling Edge to System Clock Rising Edge Setup Time 3 — — ns — — TCY + TSETUP ns TSTDELAY Maximum Delay in the Detection of the Start bit Falling Edge DS39995D-page 288  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 29-18: SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 0) SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP31 SDIx LSb SP30 MSb In LSb In Bit 14 - - - -1 SP40 SP41 TABLE 29-36: SPIx MASTER MODE TIMING REQUIREMENTS (CKE = 0) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C (Industrial) -40°C  TA  +125°C (Extended) AC CHARACTERISTICS Param No. Symbol Characteristic Min Typ(1) Max Units — — ns TscL SCKx Output Low Time(2) TCY/2 SP11 TscH SCKx Output High Time(2) TCY/2 — — ns SP20 TscF SCKx Output Fall Time(3) — 10 25 ns SP21 TscR SCKx Output Rise Time(3) — 10 25 ns SP30 TdoF SDOx Data Output Fall Time(3) — 10 25 ns SP10 (3) SP31 TdoR SDOx Data Output Rise Time — 10 25 ns SP35 TscH2doV, TscL2doV SDOx Data Output Valid after SCKx Edge — — 30 ns SP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 20 — — ns SP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 20 — — ns Note 1: 2: 3: Conditions Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 100 ns; therefore, the clock generated in Master mode must not violate this specification. This assumes a 50 pF load on all SPIx pins.  2011-2013 Microchip Technology Inc. DS39995D-page 289 PIC24FV32KA304 FAMILY FIGURE 29-19: SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 1) SP36 SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP10 SP21 SP20 SP20 SP21 SP35 MSb SDOx SP40 SDIx Bit 14 - - - - - -1 LSb SP30,SP31 MSb In Bit 14 - - - -1 LSb In SP41 TABLE 29-37: SPIx MODULE MASTER MODE TIMING REQUIREMENTS (CKE = 1) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min Typ(1) Max Units — — ns TscL SCKx Output Low Time(2) TCY/2 SP11 TscH SCKx Output High Time (2) TCY/2 — — ns SP20 TscF SCKx Output Fall Time(3) — 10 25 ns SP21 TscR SCKx Output Rise Time(3) — 10 25 ns SP30 TdoF SDOx Data Output Fall Time(3) — 10 25 ns SP10 SP31 TdoR — 10 25 ns SP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — — 30 ns SP36 TdoV2sc, SDOx Data Output Setup to TdoV2scL First SCKx Edge 30 — — ns SP40 TdiV2scH, Setup Time of SDIx Data Input TdiV2scL to SCKx Edge 20 — — ns SP41 TscH2diL, TscL2diL 20 — — ns Note 1: 2: 3: SDOx Data Output Rise Time(3) Hold Time of SDIx Data Input to SCKx Edge Conditions Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 100 ns; therefore, the clock generated in Master mode must not violate this specification. This assumes a 50 pF load on all SPIx pins. DS39995D-page 290  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 29-20: SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 0) SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 TABLE 29-38: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 0) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min Typ(1) Max Units — — ns SP70 TscL SCKx Input Low Time 30 SP71 TscH SCKx Input High Time 30 — — ns SP72 TscF SCKx Input Fall Time(2) — 10 25 ns (2) SP73 TscR SCKx Input Rise Time — 10 25 ns SP30 TdoF SDOx Data Output Fall Time(2) — 10 25 ns SP31 TdoR SDOx Data Output Rise Time(2) — 10 25 ns SP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — — 30 ns SP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 20 — — ns SP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 20 — — ns SP50 TssL2scH, TssL2scL SSx to SCKx  or SCKx Input 120 — — ns SP51 TssH2doZ SSx  to SDOx Output High-Impedance(3) 10 — 50 ns SP52 TscH2ssH TscL2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns Note 1: 2: 3: Conditions Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 100 ns; therefore, the clock generated in Master mode must not violate this specification. This assumes a 50 pF load on all SPIx pins.  2011-2013 Microchip Technology Inc. DS39995D-page 291 PIC24FV32KA304 FAMILY FIGURE 29-21: SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 1) SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIx MSb In LSb In Bit 14 - - - -1 SP41 SP40 TABLE 29-39: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 1) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min Typ(1) Max Units SP70 TscL SCKx Input Low Time 30 — — ns SP71 TscH SCKx Input High Time 30 — — ns — 10 25 ns — 10 25 ns — 10 25 ns — 10 25 ns Time(2) SP72 TscF SCKx Input Fall SP73 TscR SCKx Input Rise Time(2) (2) SP30 TdoF SDOx Data Output Fall Time SP31 TdoR SDOx Data Output Rise Time(2) SP35 TscH2doV, SDOx Data Output Valid after SCKx Edge TscL2doV — — 30 ns SP40 TdiV2scH, Setup Time of SDIx Data Input to TdiV2scL SCKx Edge 20 — — ns SP41 TscH2diL, Hold Time of SDIx Data Input to TscL2diL SCKx Edge 20 — — ns SP50 TssL2scH, SSx  to SCKx  or SCKx  Input TssL2scL 120 — — ns SP51 TssH2doZ SSx  to SDOx Output High-Impedance(3) SP52 TscH2ssH SSx  after SCKx Edge TscL2ssH SP60 TssL2doV SDOx Data Output Valid after SSx Edge Note 1: 2: 3: 10 — 50 ns 1.5 TCY + 40 — — ns — — 50 ns Conditions Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 100 ns; therefore, the clock generated in Master mode must not violate this specification. This assumes a 50 pF load on all SPIx pins. DS39995D-page 292  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TABLE 29-40: A/D MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min. Typ Max. Units Conditions Device Supply AD01 AD02 AVDD AVSS Module VDD Supply Module VSS Supply Greater of: VDD – 0.3 or 1.8 — Lesser of: VDD + 0.3 or 3.6 V PIC24FXXKA30X devices Greater of: VDD – 0.3 or 2.0 — Lesser of: VDD + 0.3 or 5.5 V PIC24FVXXKA30X devices VSS – 0.3 — VSS + 0.3 V Reference Inputs AD05 VREFH Reference Voltage High AVSS + 1.7 — AVDD V AD06 VREFL Reference Voltage Low AVSS — AVDD – 1.7 V AD07 VREF Absolute Reference Voltage AVSS – 0.3 — AVDD + 0.3 V AD08 IVREF Reference Voltage Input Current — 1.25 — mA AD09 ZVREF Reference Input Impedance — 10k —  AD10 VINH-VINL Full-Scale Input Span V Analog Input VREFL — VREFH AD11 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V AD12 VINL Absolute VINL Input Voltage AVSS – 0.3 — AVDD/2 V AD17 RIN Recommended Impedance of Analog Voltage Source — — 1k  (Note 2) 12-bit A/D Accuracy AD20b NR Resolution — 12 — bits AD21b INL Integral Nonlinearity — ±1 ±9 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD22b DNL Differential Nonlinearity — ±1 ±5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD23b GERR Gain Error — ±1 ±9 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD24b EOFF Offset Error — ±1 ±5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD25b Monotonicity(1) — — — Note 1: 2: — Guaranteed The A/D conversion result never decreases with an increase in the input voltage. Measurements are taken with external VREF+ and VREF- used as the A/D voltage reference.  2011-2013 Microchip Technology Inc. DS39995D-page 293 PIC24FV32KA304 FAMILY FIGURE 29-22: A/D CONVERSION TIMING BSET AD1CON1, SAMP BCLR AD1CON1, SAMP (Note 2) AD55 Q3/Q4 AD58 A/D AD59 AD50 CLK(1) A/D DATA 11 10 9 ... ... 2 1 0 OLD DATA ADC1BUFn NEW DATA AD1IF TCY SAMP Note 1: SAMPLING STOPPED If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input. 2: TABLE 29-41: A/D CONVERSION TIMING REQUIREMENTS(1) Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX 2.0V to 5.5V PIC24FV32KA3XX Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ Max. Units Conditions TCY = 75 ns, AD1CON3 in default state Clock Parameters AD50 TAD A/D Clock Period AD51 TRC A/D Internal RC Oscillator Period 600 — — ns — 1.67 — µs Conversion Rate AD55 TCONV Conversion Time — — 12 14 — — TAD TAD AD56 FCNV Throughput Rate — — 100 ksps AD57 TSAMP Sample Time AD58 TACQ Acquisition Time AD59 TSWC AD60 AD61 — 1 — TAD 750 — — ns Switching Time from Convert to Sample — — (Note 3) TDIS Discharge Time 12 — — TAD TPSS Sample Start Delay from Setting Sample bit (SAMP) 3 TAD 10-bit results 12-bit results (Note 2) Clock Parameters Note 1: 2: 3: 2 — Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). On the following cycle of the device clock. DS39995D-page 294  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 30.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. Data for VDD levels greater than 3.3V are applicable to PIC24FV32KA304 family devices only. 30.1 Characteristcs for Industrial Temperature Devices (-40°C to +85°C) FIGURE 30-1: TYPICAL AND MAXIMUM IDD vs. FOSC (EC MODE, 2 MHz TO 32 MHz, -40°C TO +85°C) 20.0 18.0 IDD (mA) 16.0 5.5V Max 14.0 5.5 V Typ 12.0 3.3V Max 3.3V Typ 10.0 2.5V Max 8.0 2.5V Typ 6.0 2.0V Max 4.0 2.0V Typ 2.0 0.0 2 6 10 14 18 22 26 30 Frequency (MHz) FIGURE 30-2: TYPICAL AND MAXIMUM IDD vs. FOSC (EC MODE, 1.95 kHz TO 1 MHz, +25°C) 550 IIDLE (µA) 450 5.5V Max 5.5V Typ 3.3V Max 350 3.3V Typ 2.0V Max 250 2.0V Typ 150 50 0 200 400 600 800 1000 Frequency (kHz)  2011-2013 Microchip Technology Inc. DS39995D-page 295 PIC24FV32KA304 FAMILY FIGURE 30-3: TYPICAL AND MAXIMUM IIDLE vs. FREQUENCY (EC MODE, 2 MHz TO 32 MHz) 8.0 IIDLE (mA) 7.0 6.0 5.5V Max 5.0 3.3V Max 5.5V Typ 3.3V Typ 4.0 2.5V Max 3.0 2.5V Typ 2.0V Max 2.0 2.0V Typ 1.0 0.0 2 6 10 14 18 22 26 30 Frequency (MHz) FIGURE 30-4: TYPICAL AND MAXIMUM IIDLE vs. FREQUENCY (EC MODE, 1.95 kHz TO 1 MHz) 180 160 5.5V Max IIDLE (µA) 140 5.5V Typ 120 3.3V Max 100 3.3V Typ 2.0V Max 80 2.0V Typ 60 40 0.0 0.2 0.4 0.6 0.8 1.0 Frequency (MHz) DS39995D-page 296  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 30-5: TYPICAL IDD vs. VDD (8 MHZ, EC MODE) 3.5 3.0 IDD (mA) 2.5 -40C 25C 60C 2.0 85C 1.5 1.0 2 2.5 3 3.5 4 4.5 5 5.5 VDD FIGURE 30-6: TYPICAL IDD vs. VDD (FRC MODE) 3.5 IDD (mA) 3.0 -40 C 25 C 2.5 60 C 85 C 2.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VDD  2011-2013 Microchip Technology Inc. DS39995D-page 297 PIC24FV32KA304 FAMILY FIGURE 30-7: TYPICAL AND MAXIMUM IDD vs. TEMPERATURE (FRC MODE) 3.5 IDD (mA) 3.0 5.5V Max 5.5V Typ 3.3V Max 2.5 3.3V Typ 2.0V Max 2.0V Typ 2.0 1.5 -40 FIGURE 30-8: -15 10 35 Temperature (°C) 60 85 TYPICAL AND MAXIMUM IIDLE vs. VDD (FRC MODE) 1.10 1.00 -40C Typ IDD (mA) -40C Max 0.90 25C Typ 25C Max 60C Typ 0.80 60C Max 85C Typ 0.70 85C Max 0.60 2 2.5 3 3.5 4 4.5 5 5.5 VDD DS39995D-page 298  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 30-9: TYPICAL AND MAXIMUM IIDLE vs. TEMPERATURE (FRC MODE) 1.10 1.00 IDD (mA) 5.5V Max 5.5V Typ 0.90 3.3V Max 3.3V Typ 0.80 2.0V Max 2.0V Typ 0.70 0.60 -40 -15 10 35 60 85 Temperature (°C)  2011-2013 Microchip Technology Inc. DS39995D-page 299 PIC24FV32KA304 FAMILY FIGURE 30-10: FRC FREQUENCY ACCURACY vs. VDD 0.5 Frequency Error (%) 0 -0.5 -40 C 25 C -1 60 C 85 C -1.5 -2 -2.5 2 2.5 3 3.5 4 4.5 5 5.5 VDD FIGURE 30-11: FRC FREQUENCY ACCURACY vs. TEMPERATURE (2.0V  VDD  5.5V) 0.5 0 Frequency Error (%) -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -40 DS39995D-page 300 -20 0 20 Temperature (°C) 40 60 80  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 30-12: LPRC FREQUENCY ACCURACY vs. VDD 1 Frequency Error (%) 0 -1 -40 C -2 25 C 60 C -3 85 C -4 -5 2 2.5 3 3.5 4 4.5 5 5.5 VDD FIGURE 30-13: LPRC FREQUENCY ACCURACY vs. TEMPERATURE (2.0V  VDD  5.5V) 1 Frequency Error (%) 0 -1 -2 -3 -4 -5 -6 -40 -20  2011-2013 Microchip Technology Inc. 0 20 Temperature (°C) 40 60 80 DS39995D-page 301 PIC24FV32KA304 FAMILY FIGURE 30-14: TYPICAL AND MAXIMUM IPD vs. VDD 3.5 3.0 -40C Typ 2.5 IPD (µA) -40C Max 25C Typ 2.0 25C Max 60C Typ 1.5 60C Max 85C Typ 1.0 85C Max 0.5 0.0 2 FIGURE 30-15: 2.5 3 3.5 4 VDD 4.5 5 5.5 TYPICAL AND MAXIMUM IPD vs. TEMPERATURE 2.0 1.5 5.5V Max IPD (µA) 5.5V Typ 3.3V Max 1.0 3.3V Typ 2.0V Max 2.0V Typ 0.5 0.0 -40 DS39995D-page 302 -15 10 35 Temperature (°C) 60 85  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 30-16: TYPICAL AND MAXIMUM IPD vs. VDD (DEEP SLEEP MODE) 1500 1250 -40C Typ -40C Max IPD (nA) 1000 25C Typ 25C Max 750 60C Typ 60C Max 500 85C Typ 85C Max 250 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD FIGURE 30-17: TYPICAL AND MAXIMUM IPD vs. TEMPERATURE (DEEP SLEEP MODE) 1500 1250 5.5V Max IPD (nA) 1000 5.5V Typ 3.3V Max 750 3.3V Typ 2.0V Max 500 2.0V Typ 250 0 -40 -15 10 35 60 85 Temperature (°C)  2011-2013 Microchip Technology Inc. DS39995D-page 303 PIC24FV32KA304 FAMILY FIGURE 30-18: TYPICAL IBOR vs. VDD 10.0 9.0 8.0 IBOR (µA) 7.0 -40 C 6.0 25 C 5.0 60 C 4.0 85 C 3.0 2.0 1.0 0.0 2 2.5 3 3.5 4 4.5 5 5.5 VDD FIGURE 30-19: TYPICAL IWDT vs. VDD 1.2 1.0 0.8 IWDT (µA) -40C 25C 0.6 60C 85C 0.4 0.2 0.0 2 2.5 3 3.5 4 4.5 5 5.5 VDD DS39995D-page 304  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 30-20: TYPICAL IDSBOR vs. VDD 25 IDSBOR (nA) 20 -40 C 15 25 C 60 C 10 85 C 5 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD FIGURE 30-21: TYPICAL IHLVD vs. VDD 10.0 9.0 IHVLD (µA) 8.0 -40C 7.0 25C 60C 6.0 85C 5.0 4.0 3.0 2 2.5 3 3.5 4 4.5 5 5.5 VDD  2011-2013 Microchip Technology Inc. DS39995D-page 305 PIC24FV32KA304 FAMILY FIGURE 30-22: TYPICAL IDSWDT vs. VDD 1.4 1.2 IDSWDT (µA) 1.0 85 C 0.8 60 C 25 C 0.6 -40 C 0.4 0.2 0.0 2 2.5 3 3.5 4 4.5 5 5.5 VDD FIGURE 30-23: TYPICAL VBOR vs. TEMPERATURE (BOR TRIP POINT 3) 1.88 VBOR (V) 1.86 1.84 1.82 1.80 -40 -20 0 20 40 60 80 Temperature (°C) DS39995D-page 306  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 30-24: TYPICAL VOH vs. IOH (GENERAL PURPOSE I/O, AS A FUNCTION OF VDD) 6.0 5.0 VOH (V) 4.0 5.0V 3.0 3.3V 1.8V 2.0 1.0 0.0 0 -5 -10 -15 -20 -25 IOH (mA) FIGURE 30-25: TYPICAL VOH vs. IOH (GENERAL PURPOSE I/O, AS A FUNCTION OF TEMPERATURE, 2.0V  VDD  5.5V) 3.5 VOH (V) 3.0 -40 C 2.5 25 C 60 C 2.0 85 C 1.5 1.0 0 -5  2011-2013 Microchip Technology Inc. -10 -15 IOH (mA) -20 -25 DS39995D-page 307 PIC24FV32KA304 FAMILY FIGURE 30-26: TYPICAL VOL vs. IOL (GENERAL PURPOSE I/O, AS A FUNCTION OF VDD) 1.4 1.2 VOL (V) 1.0 1.8 V 0.8 2.5 V 0.6 3.3 V 5.0 V 0.4 0.2 0.0 0 5 10 15 20 25 IOL (mA) FIGURE 30-27: TYPICAL VOL vs. IOL (GENERAL PURPOSE I/O, AS A FUNCTION OF TEMPERATURE, 2.0V  VDD  5.5V) 1.2 1.0 VOL (V) 0.8 -40 C 25 C 0.6 60 C 85 C 0.4 0.2 0.0 0 5 10 15 20 25 IOL (mA) DS39995D-page 308  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 30-28: VIL/VIH vs. VDD (GENERAL PURPOSE I/O, TEMPERATURES AS NOTED) 3.5 3.0 Ensured Logic High VIL/VIH (V) 2.5 VVih IH Typical Typical 2.0 VVIL IL Typical Typical Indeterminate 1.5 IH Max -40°C VVIH max -40 Min85°C 85C IL Min VVIL 1.0 Ensured Logic Low 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD FIGURE 30-29: VIL/VIH vs. VDD (I2C™, TEMPERATURES AS NOTED) 3.5 3.0 Ensured Logic High VIL/VIH (V) 2.5 VVIH IH Typical Max 85C 2.0 VIH Typical Typical VIL Indeterminate Typical VVIL IH Max -40°C 1.5 Min85°C 85C IL Min VVIL 1.0 Ensured Logic Low 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD  2011-2013 Microchip Technology Inc. DS39995D-page 309 PIC24FV32KA304 FAMILY FIGURE 30-30: VIL/VIH vs. VDD (OSCO, TEMPERATURES AS NOTED) 3.0 2.5 Ensured Logic High VIL/VIH (V) 2.0 VVIH IH Typical Max -40C Indeterminate VVIH IL Typical Typical 1.5 IH Max -40°C VVIL Typical Ensured Logic Low 1.0 VVIL IL Min Min85°C 85C 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD FIGURE 30-31: VIL/VIH vs. VDD (MCLR, TEMPERATURES AS NOTED) 3.0 VIL/VIH (V) 2.5 Ensured Logic High 2.0 VIH Typical VIH Max -40C VIL Typical VIH Typical Indeterminate 1.5 VIL Typical VIH Max -40°C 1.0 VIL Min85°C 85C VIL Min Ensured Logic Low 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD DS39995D-page 310  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 30-32: TYPICAL BAND GAP VOLTAGE vs. VDD 1.035 1.030 -40C 1.025 VBG 25C 60C 1.020 85C 1.015 1.010 2 2.5 3 3.5 4 4.5 5 5.5 VDD TYPICAL BAND GAP VOLTAGE vs. TEMPERATURE (2.0V  VDD  5.5V) FIGURE 30-33: 1.04 VBG 1.03 1.02 1.01 1.00 -40 -15 10 35 60 85 Temperature (°C)  2011-2013 Microchip Technology Inc. DS39995D-page 311 PIC24FV32KA304 FAMILY FIGURE 30-34: TYPICAL VOLTAGE REGULATOR OUTPUT vs. VDD 3.35 3.34 Regulator Output (V) 3.33 3.32 -40 C 3.31 25 C 3.30 60 C 3.29 85 C 3.28 3.27 3.26 3.25 2 2.5 3 3.5 4 4.5 5 5.5 VDD FIGURE 30-35: TYPICAL VOLTAGE REGULATOR OUTPUT vs. TEMPERATURE 3.35 Regulator Output (V) 3.34 3.33 3.32 3.31 2.0V 3.30 3.3V 3.29 5.5V 3.28 3.27 3.26 3.25 -40 -15 10 35 60 85 Temperature (°C) DS39995D-page 312  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 30-36: HLVD TRIP POINT VOLTAGE vs. TEMPERATURE (HLVDL = 0000, PIC24F32KA304 FAMILY DEVICES ONLY 1.90 Average Maximum Minimum Trip Point (V) 1.85 1.80 1.75 1.70 -40 -20 0 20 40 60 80 Temperature (°C) FIGURE 30-37: TEMPERATURE SENSOR DIODE VOLTAGE vs. TEMPERATURE (2.0V  VDD  5.5V) 0.90 Diode Voltage (V) 0.85 0.80 0.75 0.70 0.65 0.60 -40 -20 0 20 40 60 80 Temperature (°C)  2011-2013 Microchip Technology Inc. DS39995D-page 313 PIC24FV32KA304 FAMILY FIGURE 30-38: CTMU OUTPUT CURRENT vs. TEMPERATURE (IRNG = 01, 2.0V  VDD  5.5V) 0.7 Current (µA) 0.65 0.6 0.55 0.5 -40 FIGURE 30-39: -20 0 20 Temperature (°C) 40 60 80 CTMU OUTPUT CURRENT vs. VDD (IRNG = 01) 0.70 Current (µA) 0.65 -40 C 25 C 0.60 60 C 85 C 0.55 0.50 2 2.5 3 3.5 4 4.5 5 5.5 VDD DS39995D-page 314  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 30.2 Note: Characteristics for Extended Temperature Devices (-40°C to +125°C) Data for VDD levels greater than 3.3V are applicable to PIC24FV32KA304 family devices only. TYPICAL AND MAXIMUM IIDLE vs. VDD (FRC MODE) IIDLE (mA) FIGURE 30-40: VDD TYPICAL AND MAXIMUM IIDLE vs. TEMPERATURE (FRC MODE) IIDLE (mA) FIGURE 30-41: Temperature (°C)  2011-2013 Microchip Technology Inc. DS39995D-page 315 PIC24FV32KA304 FAMILY TYPICAL AND MAXIMUM IPD vs. VDD IPD (µA) FIGURE 30-42: VDD TYPICAL AND MAXIMUM IPD vs. TEMPERATURE IPD (µA) FIGURE 30-43: Temperature (°C) DS39995D-page 316  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TYPICAL AND MAXIMUM IPD vs. VDD (DEEP SLEEP MODE) Current (nA) FIGURE 30-44: VDD TYPICAL AND MAXIMUM IPD vs. TEMPERATURE (DEEP SLEEP MODE) Current (nA) FIGURE 30-45: Temperature (°C)  2011-2013 Microchip Technology Inc. DS39995D-page 317 PIC24FV32KA304 FAMILY TYPICAL IWDT vs. VDD IWDT (µA) FIGURE 30-46: VDD TYPICAL IDSBOR vs. VDD IDSBOR (nA) FIGURE 30-47: VDD DS39995D-page 318  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TYPICAL IHLVD vs. VDD IHLVD (µA) FIGURE 30-48: VDD  2011-2013 Microchip Technology Inc. DS39995D-page 319 PIC24FV32KA304 FAMILY TYPICAL VOL vs. IOL (GENERAL I/O, 2.0V  VDD  5.5V) VOL (V) FIGURE 30-49: IOL (MA) TYPICAL VOH vs. IOH (GENERAL I/O, AS A FUNCTION OF TEMPERATURE, 2.0V  VDD  5.5V) VOH (V) FIGURE 30-50: - - - - - IOH (mA) DS39995D-page 320  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 30-51: VIL/VIH vs. VDD (GENERAL PURPOSE I/O, TEMPERATURES AS NOTED) VIH Typical VIL Typical Ensured Logic High VIH Max -40°C VIL/VIH (V) VIL Min 125°C Indeterminate Ensured Logic Low VDD FIGURE 30-52: VIL/VIH vs. VDD (I2C™, TEMPERATURES AS NOTED) VIH Typical Ensured Logic High VIL Typical VIH Max -40°C VIL/VIH (V) VIL Min 125°C Indeterminate Ensured Logic Low VDD  2011-2013 Microchip Technology Inc. DS39995D-page 321 PIC24FV32KA304 FAMILY FIGURE 30-53: VIL/VIH vs. VDD (OSCO, TEMPERATURES AS NOTED) VIH Typical VIL Typical Ensured Logic High VIH Max -40°C VIL/VIH (V) VIL Min 125°C Indeterminate Ensured Logic Low VDD FIGURE 30-54: VIL/VIH vs. VDD (MCLR, TEMPERATURES AS NOTED) VIH Typical VIL Typical VIH Max -40°C VIL/VIH (V) Ensured Logic High VIL Min 125°C Indeterminate Ensured Logic Low VDD DS39995D-page 322  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY TYPICAL BAND GAP VOLTAGE vs. TEMPERATURE (2.0V  VDD  5.5V) VBG (V) FIGURE 30-55: Temperature (°C) TYPICAL VOLTAGE REGULATOR OUTPUT vs. TEMPERATURE Regulator Output (V) FIGURE 30-56: Temperature (°C)  2011-2013 Microchip Technology Inc. DS39995D-page 323 PIC24FV32KA304 FAMILY NOTES: DS39995D-page 324  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 31.0 PACKAGING INFORMATION 31.1 Package Marking Information 20-Lead PDIP (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SPDIP (.300") Example PIC24FV32KA301 -I/P e3 1210017 Example PIC24FV32KA302 -I/SP e3 1210017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SSOP (5.30 mm) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC24FV32KA 301-I/SS e3 1210017 28-Lead SSOP (5.30 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: Example Example PIC24FV32KA 302-I/SS e3 1210017 Product-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( ) e3 can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2011-2013 Microchip Technology Inc. DS39995D-page 325 PIC24FV32KA304 FAMILY 20-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX PIC24FV32KA301 -I/SO e3 1210017 YYWWNNN 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN PIC24FV32KA302 -I/SO e3 1210017 28-Lead QFN (6x6 mm) PIN 1 Example PIN 1 XXXXXXXX XXXXXXXX YYWWNNN DS39995D-page 326 24FV32KA 302-I/ML e3 1210017  2011-2013 Microchip Technology Inc. PIC24FV32KA304 FAMILY 44-Lead QFN (8x8x0.9 mm) PIN 1 Example PIN 1 XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC24FV32KA 304-I/PT e3 1210017 44-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 24FV32KA 304-I/PT e3 1210017 48-Lead UQFN (6x6x0.5 mm) PIN 1 Example PIN 1 XXXXXXXX XXXXXXXX YYWWNNN  2011-2013 Microchip Technology Inc. 24FV32KA 304-I/MV e3 1210017 DS39995D-page 327 PIC24FV32KA304 FAMILY 31.2 Package Details The following sections give the technical details of the packages. /HDG3ODVWLF'XDO,Q/LQH3±PLO%RG\>3',3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ  N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 b eB e 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV ,1&+(6 0,1 1 120 0$;  3LWFK H 7RSWR6HDWLQJ3ODQH $ ± ±  0ROGHG3DFNDJH7KLFNQHVV $    %DVHWR6HDWLQJ3ODQH $  ± ± 6KRXOGHUWR6KRXOGHU:LGWK (    0ROGHG3DFNDJH:LGWK (    2YHUDOO/HQJWK '    7LSWR6HDWLQJ3ODQH /    /HDG7KLFNQHVV F    E    E    H% ± ± 8SSHU/HDG:LGWK /RZHU/HDG:LGWK 2YHUDOO5RZ6SDFLQJ† %6&  1RWHV  3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD  †6LJQLILFDQW&KDUDFWHULVWLF  'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH  'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(