PIC24FJ256GB110T-I/PF

PIC24FJ256GB110 Family Data Sheet 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)  2009 Microchip Technology Inc. DS39897C Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39897C-page 2  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) Power Management: High-Performance CPU: • On-Chip 2.5V Voltage Regulator • Switch between Clock Sources in Real Time • Idle, Sleep and Doze modes with Fast Wake-up and Two-Speed Start-up • Run mode: 1 mA/MIPS, 2.0V Typical • Sleep mode Current Down to 100 nA Typical • Standby Current with 32 kHz Oscillator: 2.5 A, 2.0V typical • • • • • • • Modified Harvard Architecture Up to 16 MIPS Operation at 32 MHz 8 MHz Internal Oscillator 17-Bit x 17-Bit Single-Cycle Hardware Multiplier 32-Bit by 16-Bit Hardware Divider 16 x 16-Bit Working Register Array C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes • Linear Program Memory Addressing, Up to 12 Mbytes • Linear Data Memory Addressing, Up to 64 Kbytes • Two Address Generation Units for Separate Read and Write Addressing of Data Memory Universal Serial Bus Features: Analog Features: USBOTG CTMU JTAG PMP/PSP Comparators I2C™ SPI UART w/IrDA® Compare/ PWM Output Capture Input Timers 16-Bit 10-Bit A/D (ch) • 10-Bit, Up to 16-Channel Analog-to-Digital (A/D) Converter at 500 ksps: - Conversions available in Sleep mode • Three Analog Comparators with Programmable Input/ Output Configuration • Charge Time Measurement Unit (CTMU) Remappable Peripherals Remappable Pins SRAM (Bytes) Program Memory (Bytes) Device Pins • USB v2.0 On-The-Go (OTG) Compliant • Dual Role Capable – can act as either Host or Peripheral • Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s) USB Operation in Host mode • Full-Speed USB Operation in Device mode • High-Precision PLL for USB • Internal Voltage Boost Assist for USB Bus Voltage Generation • Interface for Off-Chip Charge Pump for USB Bus Voltage Generation • Supports up to 32 Endpoints (16 bidirectional): - USB Module can use any RAM location on the device as USB endpoint buffers • On-Chip USB Transceiver with On-Chip Voltage Regulator • Interface for Off-Chip USB Transceiver • Supports Control, Interrupt, Isochronous and Bulk Transfers • On-Chip Pull-up and Pull-Down Resistors PIC24FJ64GB106 64 64K 16K 29 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ128GB106 64 128K 16K 29 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ192GB106 64 192K 16K 29 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ256GB106 64 256K 16K 29 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ64GB108 80 64K 16K 40 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ128GB108 80 128K 16K 40 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ192GB108 80 192K 16K 40 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ256GB108 80 256K 16K 40 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ64GB110 100 64K 16K 44 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ128GB110 100 128K 16K 44 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ192GB110 100 192K 16K 44 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ256GB110 100 256K 16K 44 5 9 9 4 3 3 16 3 Y Y Y Y  2009 Microchip Technology Inc. DS39897C-page 3 PIC24FJ256GB110 FAMILY Peripheral Features: Special Microcontroller Features: • Peripheral Pin Select (PPS): - Allows independent I/O mapping of many peripherals at run time - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes - Up to 44 available pins (100-pin devices) • Three 3-Wire/4-Wire SPI modules (supports 4 Frame modes) with 8-Level FIFO Buffer • Three I2C™ modules support Multi-Master/Slave modes and 7-Bit/10-Bit Addressing • Four UART modules: - Supports RS-485, RS-232, LIN/J2602 protocols and IrDA® - On-chip hardware encoder/decoder for IrDA - Auto-wake-up and Auto-Baud Detect (ABD) - 4-level deep FIFO buffer • Five 16-Bit Timers/Counters with Programmable Prescaler • Nine 16-Bit Capture Inputs, each with a Dedicated Time Base • Nine 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base • 8-Bit Parallel Master Port (PMP/PSP): - Up to 16 address pins - Programmable polarity on control lines • Hardware Real-Time Clock/Calendar (RTCC): - Provides clock, calendar and alarm functions • Programmable Cyclic Redundancy Check (CRC) Generator • Up to 5 External Interrupt Sources • • • • • • DS39897C-page 4 • • • • • • • • Operating Voltage Range of 2.0V to 3.6V Self-Reprogrammable under Software Control 5.5V Tolerant Input (digital pins only) Configurable Open-Drain Outputs on Digital I/O High-Current Sink/Source (18 mA/18 mA) on all I/O Selectable Power Management modes: - Sleep, Idle and Doze modes with fast wake-up Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip, Low-Power RC Oscillator On-Chip LDO Regulator Power-on Reset (POR), Power-up Timer (PWRT), Low-Voltage Detect (LVD) and Oscillator Start-up Timer (OST) Flexible Watchdog Timer (WDT) with On-Chip. Low-Power RC Oscillator for Reliable Operation In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via 2 Pins JTAG Boundary Scan and Programming Support Brown-out Reset (BOR) Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Write protection option for Flash Configuration Words  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD4/CN62/RE4 PMD3/CN61/RE3 PMD2/CN60/RE2 PMD1/CN59/RE1 PMD0/CN58/RE0 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 RP20/PMRD/CN14/RD5 RP25/PMWR/CN13/RD4 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 VCPCON/RP24/CN50/RD1 Pin Diagram (64-Pin TQFP and QFN) 48 1 2 3 4 5 6 7 8 9 10 11 12 47 46 45 PIC24FJ64GB106 PIC24FJ128GB106 PIC24FJ192GB106 PIC24FJ256GB106 13 14 15 16 SOSCO/T1CK/C3INC/RPI37/ CN0/RC14 SOSCI/C3IND/CN1/RC13 DMH/RP11/INT0/CN49/RD0 RP12/PMCS1/CN56/RD11 SCL1/RP3/PMCS2/CN55/RD10 DPLN/SDA1/RP4/CN54/RD9 RTCC/DMLN/RP2/CN53/RD8 44 43 42 41 40 VSS OSCO/CLKO/CN22/RC15 39 38 37 36 OSCI/CLKI/CN23/RC12 VDD D+/RG2 D-/RG3 35 34 33 VUSB VBUS RP16/USBID/CN71/RF3 Legend: Note 1: TCK/AN12/PMA11/CTED2/CN30/RB12 TDI/AN13/PMA10/CTED1/CN31/RB13 AN14/CTPLS/RP14/PMA1/CN32/RB14 AN15/RP29/REFO/PMA0/CN12/RB15 SDA2/RP10/PMA9/CN17/RF4 SCL2/RP17/PMA8/CN18/RF5 PGEC2/AN6/RP6/CN24/RB6 PGED2/AN7/RP7/RCV/CN25/RB7 AVDD AVSS AN8/RP8/CN26/RB8 AN9/RP9/PMA7/CN27/RB9 TMS/CVREF/AN10/PMA13/CN28/RB10 TDO/AN11/PMA12/CN29/RB11 VSS VDD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PMD5/CN63/RE5 SCL3/PMD6/CN64/RE6 SDA3/PMD7/CN65/RE7 C1IND/RP21/PMA5/CN8/RG6 C1INC/RP26/PMA4/CN9/RG7 C2IND/RP19/PMA3/CN10/RG8 MCLR RP27/PMA2/C2INC/CN11/RG9 VSS VDD PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 AN3/C2INA/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/CN4/RB2 PGEC1/AN1/VREF-/RP1/CN3/RB1 PGED1/AN0/VREF+/RP0/PMA6/CN2/RB0 Shaded pins indicate pins tolerant to up to +5.5 VDC. RPn represents remappable pins for the Peripheral Pin Select feature. For QFN devices, the backplane on the underside of the device must also be connected to VSS.  2009 Microchip Technology Inc. DS39897C-page 5 PIC24FJ256GB110 FAMILY PMD5/CN63/RE5 1 SCL3/PMD6/CN64/RE6 2 SDA3/PMD7/CN65/RE7 3 RPI38/CN45/RC1 4 RPI40/CN47/RC3 5 PMA5/RP21/C1IND/CN8/RG6 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 VCPCON/RP24/CN50/RD1 65 64 63 62 61 RP20/PMRD/CN14/RD5 RP25/PMWR/CN13/RD4 CN19/RD13 RPI42/CN57/RD12 VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 ENVREG 75 74 73 72 71 70 69 68 67 66 PMD1/CN59/RE1 PMD0/CN58/RE0 CN77/RG0 CN78/RG1 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 PMD2/CN60/RE2 80 79 78 77 76 PMD4/CN62/RE4 PMD3/CN61/RE3 Pin Diagram (80-Pin TQFP) 60 SOSCO/T1CK/C3INC/RPI37/CN0/RC14 59 SOSCI/C3IND/CN1/RC13 58 DMH/RP11/INT0/CN49/RD0 57 RP12/PMCS1/CN56/RD11 56 SCL1/RP3/PMCS2/CN55/RD10 6 55 SDA1/DPLN/RP4/CN54/RD9 C1INC/RP26/PMA4/CN9/RG7 7 54 DMLN/RTCC/RP2/CN53/RD8 C2IND/RP19/PMA3/CN10/RG8 8 53 SDA2/RPI35/CN44/RA15 MCLR 9 C2INC/RP27/PMA2/CN11/RG9 10 PIC24FJ64GB108 PIC24FJ128GB108 PIC24FJ192GB108 PIC24FJ256GB108 52 SCL2/RPI36/CN43/RA14 51 VSS 50 OSCO/CLKO/CN22/RC15 49 OSCI/CLKI/CN23/RC12 VSS 11 VDD 12 TMS/RPI33/CN66/RE8 13 48 VDD TDO/RPI34/CN67/RE9 14 47 D+/RG2 Legend: 29 30 31 32 33 34 35 36 37 38 39 40 VDD TCK/AN12/PMA11/CTED2/CN30/RB12 TDI/AN13/PMA10/CTED1/CN31/RB13 AN14/CTPLS/RP14/PMA1/CN32/RB14 AN15/REFO/RP29/PMA0/ACN12/RB15 RPI43/CN20/RD14 RP5/CN21/RD15 RP10/PMA9/CN17/RF4 RP17/PMA8/CN18/RF5 AVSS AN8/RP8/CN26/RB8 AN11/PMA12/CN29/RB11 Vss RP16/USBID/CN71/RF3 28 20 AN9/RP9/CN27/RB9 RP30/CN70/RF2 41 PGED1/AN0/RP0/CN2/RB0 AN10/CVREF/PMA13/CN28/RB10 42 27 19 25 26 RP15/CN74/RF8 PGEC1/AN1/RP1/CN3/RB1 AVDD 18 43 24 VBUS AN2/C2INB/VMIO/RP13/CN4/RB2 23 44 VREF-/PMA7/CN41/RA9 17 VREF+/PMA6/CN42/RA10 VUSB AN3/C2INA/VPIO/CN5/RB3 22 D-/RG3 45 21 46 16 PGEC2/AN6/RP6/CN24/RB6 15 PGED2/AN7/RP7/RCV/CN25/RB7 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 Shaded pins indicate pins tolerant to up to +5.5 VDC. RPn represents remappable pins for the Peripheral Pin Select feature. DS39897C-page 6  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PMD2/CN60/RE2 CN80/RG13 CN79/RG12 CN81/RG14 PMD1/CN59/RE1 PMD0/CN58/RE0 CN40/RA7 CN39/RA6 CN77/RG0 CN78/RG1 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 RP20/PMRD/CN14/RD5 RP25/PMWR/CN13/RD4 CN19/RD13 RPI42/CN57/RD12 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 VCPCON/RP24/CN50/RD1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/CN62/RE4 PMD3/CN61/RE3 Pin Diagram (100-Pin TQFP) 1 75 VDD 2 74 PMD5/CN63/RE5 3 73 SCL3/PMD6/CN64/RE6 SDA3/PMD7/CN65/RE7 4 72 VSS SOSCO/T1CK/C3INC/RPI37/ CN0/RC14 SOSCI/C3IND/CN1/RC13 DMH/RP11/INT0/CN49/RD0 5 71 RP12/PMCS1/CN56/RD11 RPI38/CN45/RC1 6 70 RP3/PMCS2/CN55/RD10 RPI39/CN46/RC2 7 69 DPLN/RP4/CN54/RD9 RPI40/CN47/RC3 8 68 DMLN/RTCC/RP2/CN53/RD8 RPI41/CN48/RC4 9 67 SDA1/RPI35/CN44/RA15 C1IND/RP21/PMA5/CN8/RG6 10 66 SCL1/RPI36/CN43/RA14 65 64 VSS OSCO/CLKO/CN22/RC15 63 OSCI/CLKI/CN23/RC12 CN82/RG15 C1INC/RP26/PMA4/CN9/RG7 11 C2IND/RP19/PMA3/CN10/RG8 12 MCLR 13 C2INC/RP27/PMA2/CN11/RG9 14 VSS 15 PIC24FJ64GB110 PIC24FJ128GB110 PIC24FJ192GB110 PIC24FJ256GB110 62 VDD 61 TDO/CN38/RA5 16 60 TDI/CN37/RA4 17 59 SDA2/CN36/RA3 RPI33/CN66/RE8 18 58 SCL2/CN35/RA2 RPI34/CN67/RE9 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 19 57 D+/RG2 20 56 D-/RG3 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 21 55 VUSB AN3/C2INA/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/CN4/RB2 22 54 VBUS 23 53 RP15/CN74/RF8 PGEC1/AN1/RP1/CN3/RB1 24 52 RP30/CN70/RF2 PGED1/AN0/RP0/CN2/RB0 25 51 RP16/USBID/CN71/RF3 Legend: VSS VDD RPI43/CN20/RD14 RP5/CN21/RD15 RP10/PMA9/CN17/RF4 RP17/PMA8/CN18/RF5 PGEC2/AN6/RP6/CN24/RB6 PGED2/AN7/RP7/RCV/CN25/RB7 VREF-/PMA7/CN41/RA9 VREF+/PMA6/CN42/RA10 AVDD AVSS AN8/RP8/CN26/RB8 AN9/RP9/CN27/RB9 AN10/CVREF/PMA13/CN28/RB10 AN11/PMA12/CN29/RB11 VSS VDD TCK/CN34/RA1 RP31/CN76/RF13 RPI32/CN75/RF12 AN12/PMA11/CTED2/CN30/RB12 AN13/PMA10/CTED1/CN31/RB13 AN14/CTPLS/RP14/PMA1/CN32/RB14 AN15/REFO/RP29/PMA0/CN12/RB15 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD TMS/CN33/RA0 Shaded pins indicate pins tolerant to up to +5.5 VDC. RPn and RPIn represent remappable pins for the Peripheral Pin Select features.  2009 Microchip Technology Inc. DS39897C-page 7 PIC24FJ256GB110 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 27 3.0 CPU ........................................................................................................................................................................................... 33 4.0 Memory Organization ................................................................................................................................................................. 39 5.0 Flash Program Memory .............................................................................................................................................................. 63 6.0 Resets ........................................................................................................................................................................................ 71 7.0 Interrupt Controller ..................................................................................................................................................................... 77 8.0 Oscillator Configuration ............................................................................................................................................................ 121 9.0 Power-Saving Features ............................................................................................................................................................ 131 10.0 I/O Ports ................................................................................................................................................................................... 133 11.0 Timer1 ...................................................................................................................................................................................... 161 12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 163 13.0 Input Capture with Dedicated Timers ....................................................................................................................................... 169 14.0 Output Compare with Dedicated Timers .................................................................................................................................. 173 15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 181 16.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 191 17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 199 18.0 Universal Serial Bus with On-The-Go Support (USB OTG) ..................................................................................................... 207 19.0 Parallel Master Port (PMP)....................................................................................................................................................... 241 20.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 251 21.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 263 22.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 267 23.0 Triple Comparator Module........................................................................................................................................................ 277 24.0 Comparator Voltage Reference................................................................................................................................................ 281 25.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 283 26.0 Special Features ...................................................................................................................................................................... 287 27.0 Development Support............................................................................................................................................................... 299 28.0 Instruction Set Summary .......................................................................................................................................................... 303 29.0 Electrical Characteristics .......................................................................................................................................................... 311 30.0 Packaging Information.............................................................................................................................................................. 327 Appendix A: Revision History............................................................................................................................................................. 341 Index ................................................................................................................................................................................................. 343 The Microchip Web Site ..................................................................................................................................................................... 349 Customer Change Notification Service .............................................................................................................................................. 349 Customer Support .............................................................................................................................................................................. 349 Reader Response .............................................................................................................................................................................. 350 Product Identification System............................................................................................................................................................. 351 DS39897C-page 8  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2009 Microchip Technology Inc. DS39897C-page 9 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 10  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ64GB106 • PIC24FJ192GB108 • PIC24FJ128GB106 • PIC24FJ256GB108 • PIC24FJ192GB106 • PIC24FJ64GB110 • PIC24FJ256GB106 • PIC24FJ128GB110 • PIC24FJ64GB108 • PIC24FJ192GB110 • PIC24FJ128GB108 • PIC24FJ256GB110 • Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. • Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software. 1.1.3 This expands on the existing line of Microchip‘s 16-bit microcontrollers, combining an expanded peripheral feature set and enhanced computational performance with a new connectivity option: USB On-The-Go. The PIC24FJ256GB110 family provides a new platform for high-performance USB applications, which may need more than an 8-bit platform, but don’t require the power of a digital signal processor. 1.1 1.1.1 Core Features 16-BIT ARCHITECTURE Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC® digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: • 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces • Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data) • A 16-element working register array with built-in software stack support • A 17 x 17 hardware multiplier with support for integer math • Hardware support for 32 by 16-bit division • An instruction set that supports multiple addressing modes and is optimized for high-level languages such as ‘C’ • Operational performance up to 16 MIPS 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ256GB110 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, Low-Power RC Oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs.  2009 Microchip Technology Inc. OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ256GB110 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. • Two External Clock modes offering the option of a divide-by-2 clock output. • A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. • A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes and the FRC Oscillator, which allows clock speeds of up to 32 MHz. • A separate internal RC Oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.1.4 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger, or even in jumping from 64-pin to 100-pin devices. The PIC24F family is pin-compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device. DS39897C-page 11 PIC24FJ256GB110 FAMILY 1.2 USB On-The-Go With the PIC24FJ256GB110 family of devices, Microchip introduces USB On-The-Go functionality on a single chip to its product line. This new module provides on-chip functionality as a target device compatible with the USB 2.0 standard, as well as limited stand-alone functionality as a USB embedded host. By implementing USB Host Negotiation Protocol (HNP), the module can also dynamically switch between device and host operation, allowing for a much wider range of versatile USB-enabled applications on a microcontroller platform. • Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communications. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in Master modes. • Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. In addition to USB host functionality, PIC24FJ256GB110 family devices provide a true single-chip USB solution, including an on-chip transceiver and voltage regulator, and a voltage boost generator for sourcing bus power during host operations. 1.4 1.3 The devices are differentiated from each other in four ways: Other Special Features • Peripheral Pin Select: The Peripheral Pin Select (PPS) feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins. • Communications: The PIC24FJ256GB110 family incorporates a range of serial communication peripherals to handle a range of application requirements. There are three independent I2C modules that support both Master and Slave modes of operation. Devices also have, through the Peripheral Pin Select feature, four independent UARTs with built-in IrDA encoder/decoders and three SPI modules. • Analog Features: All members of the PIC24FJ256GB110 family include a 10-bit A/D Converter module and a triple comparator module. The A/D module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds. The comparator module includes three analog comparators that are configurable for a wide range of operations. • CTMU Interface: In addition to their other analog features, members of the PIC24FJ256GB110 family include the brand new CTMU interface module. This provides a convenient method for precision time measurement and pulse generation, and can serve as an interface for capacitive sensors. DS39897C-page 12 Details on Individual Family Members Devices in the PIC24FJ256GB110 family are available in 64-pin, 80-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. 1. 2. 3. 4. Flash program memory (64 Kbytes for PIC24FJ64GB1 devices, 128 Kbytes for PIC24FJ128GB1 devices, 192 Kbytes for PIC24FJ192GB1 devices and 256 Kbytes for PIC24FJ256GB1 devices). Available I/O pins and ports (51 pins on 6 ports for 64-pin devices, 65 pins on 7 ports for 80-pin devices and 83 pins on 7 ports for 100-pin devices). Available Interrupt-on-Change Notification (ICN) inputs (49 on 64-pin devices, 63 on 80-pin devices and 81 on 100-pin devices). Available remappable pins (29 pins on 64-pin devices, 40 pins on 80-pin devices and 44 pins on 100-pin devices) All other features for devices in this family are identical. These are summarized in Table 1-1. A list of the pin features available on the PIC24FJ256GB110 family devices, sorted by function, is shown in Table 1-4. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 64-PIN DEVICES Features 64GB106 Operating Frequency Program Memory (bytes) Program Memory (instructions) 128GB106 192GB106 256GB106 DC – 32 MHz 64K 128K 22,016 44,032 Data Memory (bytes) 192K 256K 67,072 87,552 16,384 Interrupt Sources (soft vectors/NMI traps) 66 (62/4) I/O Ports Ports B, C, D, E, F, G Total I/O Pins 51 Remappable Pins 29 (28 I/O, 1 Input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 9(1) Output Compare/PWM Channels 9(1) Input Change Notification Interrupt 49 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2C™ 3 Parallel Communications (PMP/PSP) Yes JTAG Boundary Scan/Programming Yes 10-Bit Analog-to-Digital Module (input channels) 16 Analog Comparators 3 CTMU Interface Resets (and delays) Instruction Set Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations Packages Note 1: 64-Pin TQFP Peripherals are accessible through remappable pins.  2009 Microchip Technology Inc. DS39897C-page 13 PIC24FJ256GB110 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 80-PIN DEVICES Features 64GB108 Operating Frequency Program Memory (bytes) Program Memory (instructions) 128GB108 192GB108 256GB108 DC – 32 MHz 64K 128K 22,016 44,032 Data Memory (bytes) 192K 256K 67,072 87,552 16,384 Interrupt Sources (soft vectors/NMI traps) 66 (62/4) I/O Ports Ports A, B, C, D, E, F, G Total I/O Pins 65 Remappable Pins 40 (31 I/O, 9 Input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 9(1) Output Compare/PWM Channels 9(1) Input Change Notification Interrupt 63 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2C™ 3 Parallel Communications (PMP/PSP) Yes JTAG Boundary Scan/Programming Yes 10-Bit Analog-to-Digital Module (input channels) 16 Analog Comparators 3 CTMU Interface Resets (and delays) Instruction Set Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations Packages Note 1: 80-Pin TQFP Peripherals are accessible through remappable pins. DS39897C-page 14  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 100-PIN DEVICES Features 64GB110 Operating Frequency Program Memory (bytes) Program Memory (instructions) 128GB110 192GB110 256GB110 DC – 32 MHz 64K 128K 192K 256K 22,016 44,032 67,072 87,552 Data Memory (bytes) 16,384 Interrupt Sources (soft vectors/NMI traps) 66 (62/4) I/O Ports Ports A, B, C, D, E, F, G Total I/O Pins 83 Remappable Pins 44 (32 I/O, 12 Input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 9(1) Output Compare/PWM Channels 9(1) Input Change Notification Interrupt 81 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2C™ 3 Parallel Communications (PMP/PSP) Yes JTAG Boundary Scan/Programming Yes 10-Bit Analog-to-Digital Module (input channels) 16 Analog Comparators 3 CTMU Interface Resets (and delays) Instruction Set Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations Packages Note 1: 100-Pin TQFP Peripherals are accessible through remappable pins.  2009 Microchip Technology Inc. DS39897C-page 15 PIC24FJ256GB110 FAMILY FIGURE 1-1: PIC24FJ256GB110 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller PORTA(1) 16 (13 I/O) 16 16 8 Data Latch PSV & Table Data Access Control Block Data RAM PCH PCL Program Counter Repeat Stack Control Control Logic Logic 23 Address Latch PORTB (16 I/O) 16 23 16 Read AGU Write AGU Address Latch PORTC(1) Program Memory (8 I/O) Data Latch 16 EA MUX Literal Data Address Bus 24 Inst Latch 16 16 PORTD(1) (16 I/O) Inst Register Instruction Decode & Control PORTE(1) Control Signals OSCO/CLKO OSCI/CLKI Timing Generation FRC/LPRC Oscillators REFO ENVREG Divide Support 17x17 Multiplier Power-up Timer (10 I/O) 16 x 16 W Reg Array Oscillator Start-up Timer Precision Band Gap Reference Watchdog Timer Voltage Regulator BOR and LVD(2) PORTF(1) 16-Bit ALU Power-on Reset (9 I/O) 16 PORTG(1) (12 I/O) VDDCORE/VCAP Timer1 Timer2/3(3) VDD, VSS Timer4/5(3) MCLR RTCC 10-Bit ADC Comparators(3) USB OTG PMP/PSP IC 1-9(3) Note 1: 2: 3: PWM/OC 1-9(3) ICNs(1) SPI 1/2/3(3) I2C 1/2/3 UART 1/2/3/4(3) CTMU Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-4 for specific implementations by pin count. BOR functionality is provided when the on-board voltage regulator is enabled. These peripheral I/Os are only accessible through remappable pins. DS39897C-page 16  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS Pin Number Function 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer AN0 16 20 25 I ANA AN1 15 19 24 I ANA AN2 14 18 23 I ANA AN3 13 17 22 I ANA AN4 12 16 21 I ANA AN5 11 15 20 I ANA AN6 17 21 26 I ANA AN7 18 22 27 I ANA AN8 21 27 32 I ANA AN9 22 28 33 I ANA AN10 23 29 34 I ANA AN11 24 30 35 I ANA AN12 27 33 41 I ANA AN13 28 34 42 I ANA AN14 29 35 43 I ANA AN15 30 36 44 I ANA Description A/D Analog Inputs. AVDD 19 25 30 P — AVSS 20 26 31 P — C1INA 11 15 20 I ANA Comparator 1 Input A. C1INB 12 16 21 I ANA Comparator 1 Input B. C1INC 5 7 11 I ANA Comparator 1 Input C. C1IND 4 6 10 I ANA Comparator 1 Input D. C2INA 13 17 22 I ANA Comparator 2 Input A. C2INB 14 18 23 I ANA Comparator 2 Input B. C2INC 8 10 14 I ANA Comparator 2 Input C. C2IND 6 8 12 I ANA Comparator 2 Input D. C3INA 55 69 84 I ANA Comparator 3 Input A. C3INB 54 68 83 I ANA Comparator 3 Input B. C3INC 48 60 74 I ANA Comparator 3 Input C. C3IND 47 59 73 I ANA Comparator 3 Input D. CLKI 39 49 63 I ANA CLKO 40 50 64 O — Legend: TTL = TTL input buffer ANA = Analog level input/output  2009 Microchip Technology Inc. Positive Supply for Analog modules. Ground Reference for Analog modules. Main Clock Input Connection. System Clock Output. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39897C-page 17 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer CN0 48 60 74 I ST CN1 47 59 73 I ST CN2 16 20 25 I ST CN3 15 19 24 I ST CN4 14 18 23 I ST CN5 13 17 22 I ST CN6 12 16 21 I ST CN7 11 15 20 I ST CN8 4 6 10 I ST CN9 5 7 11 I ST CN10 6 8 12 I ST CN11 8 10 14 I ST CN12 30 36 44 I ST CN13 52 66 81 I ST CN14 53 67 82 I ST CN15 54 68 83 I ST CN16 55 69 84 I ST CN17 31 39 49 I ST CN18 32 40 50 I ST CN19 — 65 80 I ST CN20 — 37 47 I ST CN21 — 38 48 I ST CN22 40 50 64 I ST CN23 39 49 63 I ST CN24 17 21 26 I ST CN25 18 22 27 I ST CN26 21 27 32 I ST CN27 22 28 33 I ST CN28 23 29 34 I ST CN29 24 30 35 I ST CN30 27 33 41 I ST CN31 28 34 42 I ST CN32 29 35 43 I ST CN33 — — 17 I ST CN34 — — 38 I ST CN35 — — 58 I ST CN36 — — 59 I ST CN37 — — 60 I ST CN38 — — 61 I ST CN39 — — 91 I ST Function CN40 — — 92 I ST CN41 — 23 28 I ST — 24 29 I ST CN42 Legend: TTL = TTL input buffer ANA = Analog level input/output DS39897C-page 18 Description Interrupt-on-Change Inputs. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer CN43 — 52 66 I ST CN44 — 53 67 I ST CN45 — 4 6 I ST CN46 — — 7 I ST CN47 — 5 8 I ST CN48 — — 9 I ST CN49 46 58 72 I ST CN50 49 61 76 I ST CN51 50 62 77 I ST CN52 51 63 78 I ST CN53 42 54 68 I ST CN54 43 55 69 I ST CN55 44 56 70 I ST CN56 45 57 71 I ST CN57 — 64 79 I ST CN58 60 76 93 I ST CN59 61 77 94 I ST CN60 62 78 98 I ST CN61 63 79 99 I ST CN62 64 80 100 I ST CN63 1 1 3 I ST CN64 2 2 4 I ST CN65 3 3 5 I ST CN66 — 13 18 I ST CN67 — 14 19 I ST CN68 58 72 87 I ST CN69 59 73 88 I ST CN70 — 42 52 I ST CN71 33 41 51 I ST CN74 — 43 53 I ST CN75 — — 40 I ST CN76 — — 39 I ST CN77 — 75 90 I ST CN78 — 74 89 I ST CN79 — — 96 I ST CN80 — — 97 I ST CN81 — — 95 I ST CN82 — — 1 I ST CTED1 28 34 42 I ANA CTMU External Edge Input 1. CTED2 27 33 41 I ANA CTMU External Edge Input 2. Function Description Interrupt-on-Change Inputs. CTPLS 29 35 43 O — CTMU Pulse Output. CVREF 23 29 34 O — Comparator Voltage Reference Output. Legend: TTL = TTL input buffer ANA = Analog level input/output  2009 Microchip Technology Inc. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39897C-page 19 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer D+ 37 47 57 I/O — USB Differential Plus line (internal transceiver). D- 36 46 56 I/O — USB Differential Minus line (internal transceiver). DMH 46 58 72 O — D- External Pull-up Control Output. DMLN 42 54 68 O — D- External Pull-down Control Output. DPH 50 62 77 O — D+ External Pull-up Control Output. DPLN 43 55 69 O — D+ External Pull-down Control Output. ENVREG 57 71 86 I ST Voltage Regulator Enable. INT0 46 58 72 I ST External Interrupt Input. MCLR 7 9 13 I ST Master Clear (device Reset) Input. This line is brought low to cause a Reset. OSCI 39 49 63 I ANA Main Oscillator Input Connection. OSCO 40 50 64 O ANA Main Oscillator Output Connection. PGEC1 15 19 24 I/O ST In-Circuit Debugger/Emulator/ICSP™ Programming Clock. PGED1 16 20 25 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data. PGEC2 17 21 26 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock. PGED2 18 22 27 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data. PGEC3 11 15 20 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock. PGED3 12 16 21 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data. PMA0 30 36 44 I/O ST Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). PMA1 29 35 43 I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). PMA2 8 10 14 O — PMA3 6 8 12 O — Parallel Master Port Address (Demultiplexed Master modes). PMA4 5 7 11 O — PMA5 4 6 10 O — PMA6 16 24 29 O — PMA7 22 23 28 O — PMA8 32 40 50 O — PMA9 31 39 49 O — PMA10 28 34 42 O — PMA11 27 33 41 O — PMA12 24 30 35 O — PMA13 23 29 34 O — PMCS1 45 57 71 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe/Address Bit 15. PMCS2 44 56 70 O ST Parallel Master Port Chip Select 2 Strobe/Address Bit 14. 51 63 78 O — Parallel Master Port Byte Enable Strobe. Function PMBE Legend: TTL = TTL input buffer ANA = Analog level input/output DS39897C-page 20 Description ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer PMD0 60 76 93 I/O ST/TTL PMD1 61 77 94 I/O ST/TTL PMD2 62 78 98 I/O ST/TTL PMD3 63 79 99 I/O ST/TTL PMD4 64 80 100 I/O ST/TTL PMD5 1 1 3 I/O ST/TTL PMD6 2 2 4 I/O ST/TTL PMD7 3 3 5 I/O ST/TTL PMRD 53 67 82 O — PMWR 52 66 81 O — Parallel Master Port Write Strobe. RA0 — — 17 I/O ST PORTA Digital I/O. RA1 — — 38 I/O ST RA2 — — 58 I/O ST RA3 — — 59 I/O ST RA4 — — 60 I/O ST RA5 — — 61 I/O ST RA6 — — 91 I/O ST RA7 — — 92 I/O ST RA9 — 23 28 I/O ST RA10 — 24 29 I/O ST RA14 — 52 66 I/O ST RA15 — 53 67 I/O ST RB0 16 20 25 I/O ST RB1 15 19 24 I/O ST RB2 14 18 23 I/O ST RB3 13 17 22 I/O ST RB4 12 16 21 I/O ST RB5 11 15 20 I/O ST RB6 17 21 26 I/O ST RB7 18 22 27 I/O ST RB8 21 27 32 I/O ST RB9 22 28 33 I/O ST RB10 23 29 34 I/O ST RB11 24 30 35 I/O ST RB12 27 33 41 I/O ST RB13 28 34 42 I/O ST RB14 29 35 43 I/O ST RB15 30 36 44 I/O ST Function Legend: TTL = TTL input buffer ANA = Analog level input/output  2009 Microchip Technology Inc. Description Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes). Parallel Master Port Read Strobe. PORTB Digital I/O. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39897C-page 21 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer Description RC1 — 4 6 I/O ST RC2 — — 7 I/O ST RC3 — 5 8 I/O ST RC4 — — 9 I/O ST RC12 39 49 63 I/O ST RC13 47 59 73 I/O ST RC14 48 60 74 I/O ST RC15 40 50 64 I/O ST RCV 18 22 27 I ST USB Receive Input (from external transceiver). RD0 46 58 72 I/O ST PORTD Digital I/O. RD1 49 61 76 I/O ST RD2 50 62 77 I/O ST RD3 51 63 78 I/O ST RD4 52 66 81 I/O ST RD5 53 67 82 I/O ST RD6 54 68 83 I/O ST RD7 55 69 84 I/O ST RD8 42 54 68 I/O ST RD9 43 55 69 I/O ST RD10 44 56 70 I/O ST RD11 45 57 71 I/O ST RD12 — 64 79 I/O ST RD13 — 65 80 I/O ST RD14 — 37 47 I/O ST RD15 — 38 48 I/O ST RE0 60 76 93 I/O ST RE1 61 77 94 I/O ST RE2 62 78 98 I/O ST RE3 63 79 99 I/O ST RE4 64 80 100 I/O ST RE5 1 1 3 I/O ST RE6 2 2 4 I/O ST RE7 3 3 5 I/O ST RE8 — 13 18 I/O ST RE9 — 14 19 I/O ST REFO 30 36 44 O — Legend: TTL = TTL input buffer ANA = Analog level input/output DS39897C-page 22 PORTC Digital I/O. PORTE Digital I/O. Reference Clock Output. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer RF0 58 72 87 I/O ST RF1 59 73 88 I/O ST RF2 — 42 52 I/O ST RF3 33 41 51 I/O ST RF4 31 39 49 I/O ST RF5 32 40 50 I/O ST RF8 — 43 53 I/O ST RF12 — — 40 I/O ST ST Function RF13 — — 39 I/O RG0 — 75 90 I/O ST RG1 — 74 89 I/O ST RG2 37 47 57 I ST RG3 36 46 56 I ST RG6 4 6 10 I/O ST RG7 5 7 11 I/O ST RG8 6 8 12 I/O ST RG9 8 10 14 I/O ST RG12 — — 96 I/O ST RG13 — — 97 I/O ST RG14 — — 95 I/O ST ST RG15 — — 1 I/O RP0 16 20 25 I/O ST RP1 15 19 24 I/O ST RP2 42 54 68 I/O ST RP3 44 56 70 I/O ST RP4 43 55 69 I/O ST RP5 — 38 48 I/O ST RP6 17 21 26 I/O ST RP7 18 22 27 I/O ST RP8 21 27 32 I/O ST RP9 22 28 33 I/O ST RP10 31 39 49 I/O ST RP11 46 58 72 I/O ST RP12 45 57 71 I/O ST RP13 14 18 23 I/O ST RP14 29 35 43 I/O ST RP15 — 43 53 I/O ST RP16 33 41 51 I/O ST RP17 32 40 50 I/O ST RP18 11 15 20 I/O ST 6 8 12 I/O ST RP19 Legend: TTL = TTL input buffer ANA = Analog level input/output  2009 Microchip Technology Inc. Description PORTF Digital I/O. PORTG Digital I/O. Remappable Peripheral (input or output). ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39897C-page 23 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 100-Pin TQFP I/O Input Buffer 64-Pin TQFP, QFN 80-Pin TQFP RP20 53 67 82 I/O ST RP21 4 6 10 I/O ST RP22 51 63 78 I/O ST RP23 50 62 77 I/O ST RP24 49 61 76 I/O ST RP25 52 66 81 I/O ST RP26 5 7 11 I/O ST RP27 8 10 14 I/O ST RP28 12 16 21 I/O ST RP29 30 36 44 I/O ST RP30 — 42 52 I/O ST RP31 — — 39 I/O ST Description Remappable Peripheral (input or output). RPI32 — — 40 I ST RPI33 — 13 18 I ST Remappable Peripheral (input only). RPI34 — 14 19 I ST RPI35 — 53 67 I ST RPI36 — 52 66 I ST RPI37 48 60 74 I ST RPI38 — 4 6 I ST RPI39 — — 7 I ST RPI40 — 5 8 I ST RPI41 — — 9 I ST RPI42 — 64 79 I ST RPI43 — 37 47 I ST RTCC 42 54 68 O — Real-Time Clock Alarm/Seconds Pulse Output. SCL1 44 56 66 I/O I2C I2C1 Synchronous Serial Clock Input/Output. SCL2 32 52 58 I/O I2C I2C2 Synchronous Serial Clock Input/Output. SCL3 2 2 4 I/O I2C I2C3 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. SDA1 43 55 67 I/O I2C SDA2 31 53 59 I/O I2C I2C2 Data Input/Output. SDA3 3 3 5 I/O I2C I2C3 Data Input/Output. SOSCI 47 59 73 I ANA Secondary Oscillator/Timer1 Clock Input. SOSCO 48 60 74 O ANA T1CK 48 60 74 I ST Timer1 Clock. Secondary Oscillator/Timer1 Clock Output. TCK 27 33 38 I ST JTAG Test Clock/Programming Clock Input. TDI 28 34 60 I ST JTAG Test Data/Programming Data Input. JTAG Test Data Output. TDO 24 14 61 O — TMS 23 13 17 I ST JTAG Test Mode Select Input. USBID 33 41 51 I ST USB OTG ID (OTG mode only). USBOEN 12 16 21 O — USB Output Enable Control (for external transceiver). Legend: TTL = TTL input buffer ANA = Analog level input/output DS39897C-page 24 ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer Description VBUS 34 44 54 P — VBUSON 11 15 20 O — USB Voltage, Host mode (5V). VBUSST 58 72 87 I ANA VCAP 56 70 85 P — External Filter Capacitor Connection (regulator enabled). USB VBUS Boost Generator, Comparator Input 1. USB OTG External Charge Pump Control. USB OTG Internal Charge Pump Feedback Control. VCMPST1 58 72 87 I ST VCMPST2 59 73 88 I ST USB VBUS Boost Generator, Comparator Input 2. VCPCON 49 61 76 O — USB OTG VBUS PWM/Charge Output. 10, 26, 38 12, 32, 48 2, 16, 37, 46, 62 P — Positive Supply for Peripheral Digital Logic and I/O Pins. VDDCORE 56 70 85 P — Positive Supply for Microcontroller Core Logic (regulator disabled). VMIO 14 18 23 I/O ST USB Differential Minus Input/Output (external transceiver). VPIO 13 17 22 I/O ST VREF- 15 23 28 I ANA VDD VREF+ VSS VUSB Legend: USB Differential Plus Input/Output (external transceiver). A/D and Comparator Reference Voltage (low) Input. 16 24 29 I ANA 9, 25, 41 11, 31, 51 15, 36, 45, 65, 75 P — Ground Reference for Logic and I/O Pins. 35 45 55 P — USB Voltage (3.3V) TTL = TTL input buffer ANA = Analog level input/output  2009 Microchip Technology Inc. A/D and Comparator Reference Voltage (high) Input. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39897C-page 25 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 26  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG/DISVREG and VCAP/VDDCORE pins (PIC24FJ devices only) (see Section 2.4 “Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)”) These pins must also be connected if they are being used in the end application: • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for analog modules is implemented Note: VDD R2 VSS R1 (1) (1) (EN/DIS)VREG MCLR VCAP/VDDCORE C1 C7 PIC24FXXXX C6(2) VSS VDD VDD VSS C3(2) C5(2) VSS The following pins must always be connected: C2(2) VDD Getting started with the PIC24FJ256GB110 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. RECOMMENDED MINIMUM CONNECTIONS VDD Basic Connection Requirements FIGURE 2-1: AVSS 2.1 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS AVDD 2.0 C4(2) Key (all values are recommendations): C1 through C6: 0.1 F, 20V ceramic C7: 10 F, 6.3V or greater, tantalum or ceramic R1: 10 kΩ R2: 100Ω to 470Ω Note 1: 2: See Section 2.4 “Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)” for explanation of ENVREG/DISVREG pin connections. The example shown is for a PIC24F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1.  2009 Microchip Technology Inc. DS39897C-page 27 PIC24FJ256GB110 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). • Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. 2.2.2 TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including microcontrollers to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. DS39897C-page 28 2.3 Master Clear (MCLR) Pin The MCLR pin provides two specific device functions: device Reset, and device programming and debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application’s requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD R1 R2 JP MCLR PIC24FXXXX C1 Note 1: R1  10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R2  470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Note: Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE) FIGURE 2-3: The on-chip voltage regulator enable/disable pin (ENVREG or DISVREG, depending on the device family) must always be connected directly to either a supply voltage or to ground. The particular connection is determined by whether or not the regulator is to be used: • For ENVREG, tie to VDD to enable the regulator, or to ground to disable the regulator • For DISVREG, tie to ground to enable the regulator or to VDD to disable the regulator Refer to Section 26.2 “On-Chip Voltage Regulator” for details on connecting and using the on-chip regulator. When the regulator is enabled, a low-ESR (16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4042; // Initialize NVMCON asm("DISI #5"); // // // // __builtin_write_NVM(); EXAMPLE 5-3: Block all interrupts with priority >16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write necessary number of latches for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++) { __builtin_tblwtl(offset, progData[i++]); // Write to address low word __builtin_tblwth(offset, progData[i]); // Write to upper byte offset = offset + 2; // Increment address } EXAMPLE 5-5: INITIATING A PROGRAMMING SEQUENCE (ASSEMBLY LANGUAGE CODE) DISI #5 MOV MOV MOV MOV BSET NOP NOP BTSC BRA #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR EXAMPLE 5-6: ; Block all interrupts with priority >16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write latches __builtin_tblwtl(offset, progDataL); __builtin_tblwth(offset, progDataH); asm(“DISI #5”); __builtin_write_NVM();  2009 Microchip Technology Inc. // // // // // // Write to address low word Write to upper byte Block interrupts with priority < 7 for next 5 instructions C30 function to perform unlock sequence and set WR DS39897C-page 69 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 70  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 6.0 Note: RESETS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 7. “Reset” (DS39712). The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: • • • • • • • • • POR: Power-on Reset MCLR: Pin Reset SWR: RESET Instruction WDT: Watchdog Timer Reset BOR: Brown-out Reset CM: Configuration Mismatch Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode Reset UWR: Uninitialized W Register Reset Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets. Note: All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 6-1). A Power-on Reset will clear all bits, except for the BOR and POR bits (RCON), which are set. The user may set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this manual. A simplified block diagram of the Reset module is shown in Figure 6-1. FIGURE 6-1: Refer to the specific peripheral or CPU section of this manual for register Reset states. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle VDD Rise Detect POR Brown-out Reset BOR SYSRST VDD Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register  2009 Microchip Technology Inc. DS39897C-page 71 PIC24FJ256GB110 FAMILY REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) R/W-0, HS TRAPR bit 15 R/W-0, HS IOPUWR U-0 — U-0 — U-0 — U-0 — R/W-0, HS CM R/W-0 PMSLP bit 8 R/W-0, HS EXTR bit 7 R/W-0, HS SWR R/W-0 SWDTEN(2) R/W-0, HS WDTO R/W-0, HS SLEEP R/W-0, HS IDLE R/W-1, HS BOR R/W-1, HS POR bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: HS = Hardware settable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred Unimplemented: Read as ‘0’ CM: Configuration Word Mismatch Reset Flag bit 1 = A Configuration Word Mismatch Reset has occurred 0 = A Configuration Word Mismatch Reset has not occurred PMSLP: Program Memory Power During Sleep bit 1 = Program memory bias voltage remains powered during Sleep. 0 = Program memory bias voltage is powered down during Sleep and voltage regulator enters Standby mode. EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred SLEEP: Wake From Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode IDLE: Wake-up From Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred. Note that BOR is also set after a Power-on Reset. 0 = A Brown-out Reset has not occurred POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS39897C-page 72  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 6-1: RESET FLAG BIT OPERATION Flag Bit Setting Event Clearing Event TRAPR (RCON) Trap Conflict Event POR IOPUWR (RCON) Illegal Opcode or Uninitialized W Register Access POR CM (RCON) Configuration Mismatch Reset POR EXTR (RCON) MCLR Reset POR SWR (RCON) RESET Instruction POR WDTO (RCON) WDT Time-out SLEEP (RCON) PWRSAV #SLEEP Instruction POR IDLE (RCON) PWRSAV #IDLE Instruction POR BOR (RCON) POR, BOR — POR (RCON) POR — Note: 6.1 PWRSAV Instruction, POR All Reset flag bits may be set or cleared by the user software. Clock Source Selection at Reset If clock switching is enabled, the system clock source at device Reset is chosen as shown in Table 6-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 8.0 “Oscillator Configuration” for further details. TABLE 6-2: Reset Type POR BOR MCLR WDTO OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED) Clock Source Determinant FNOSC Configuration bits (CW2) 6.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 6-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire. The time at which the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released. COSC Control bits (OSCCON) SWR  2009 Microchip Technology Inc. DS39897C-page 73 PIC24FJ256GB110 FAMILY TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type POR(6) EC BOR All Others Note 1: 2: 3: 4: 5: 6: Note: Clock Source SYSRST Delay System Clock Delay TPOR + TPWRT — Notes 1, 2 FRC, FRCDIV TPOR + TPWRT TFRC 1, 2, 3, 6 LPRC TPOR + TPWRT TLPRC 1, 2, 3 1, 2, 4 ECPLL TPOR + TPWRT TLOCK FRCPLL TPOR + TPWRT TFRC + TLOCK XT, HS, SOSC TPOR+ TPWRT TOST XTPLL, HSPLL TPOR + TPWRT TOST + TLOCK 1, 2, 3, 4 1, 2, 5 1, 2, 4, 5 EC TPWRT — FRC, FRCDIV TPWRT TFRC 2, 3, 6 LPRC TPWRT TLPRC 2, 3 ECPLL TPWRT TLOCK 2, 4 FRCPLL TPWRT TFRC + TLOCK XT, HS, SOSC TPWRT TOST XTPLL, HSPLL TPWRT TFRC + TLOCK — — Any Clock 2 2, 3, 4 2, 5 2, 3, 4 — TPOR = Power-on Reset delay. TPWRT = 64 ms nominal if regulator is disabled (ENVREG tied to VSS). TFRC and TLPRC = RC Oscillator start-up times. TLOCK = PLL lock time. TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing oscillator clock to the system. If Two-Speed Start-up is enabled, regardless of the Primary Oscillator selected, the device starts with FRC, and in such cases, FRC start-up time is valid. For detailed operating frequency and timing specifications, see Section 29.0 “Electrical Characteristics”. DS39897C-page 74  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 6.2.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate. • The Oscillator Start-up Timer has not expired (if a crystal oscillator is used). • The PLL has not achieved a lock (if PLL is used). The device will not begin to execute code until a valid clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known. 6.2.2 6.3 Special Function Register Reset States Most of the Special Function Registers (SFRs) associated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual. The Reset value for each SFR does not depend on the type of Reset, with the exception of four registers. The Reset value for the Reset Control register, RCON, will depend on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the type of Reset and the programmed values of the FNOSC bits in Flash Configuration Word 2 (CW2) (see Table 6-2). The RCFGCAL and NVMCON registers are only affected by a POR. FAIL-SAFE CLOCK MONITOR (FSCM) AND DEVICE RESETS If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released. If a valid clock source is not available at this time, the device will automatically switch to the FRC Oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine.  2009 Microchip Technology Inc. DS39897C-page 75 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 76  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 7.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 8. “Interrupts” (DS39707). The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24F CPU. It has the following features: • • • • Up to 8 processor exceptions and software traps 7 user-selectable priority levels Interrupt Vector Table (IVT) with up to 118 vectors A unique vector for each interrupt or exception source • Fixed priority within a specified user priority level • Alternate Interrupt Vector Table (AIVT) for debug support • Fixed interrupt entry and return latencies 7.1 Interrupt Vector Table The Interrupt Vector Table (IVT) is shown in Figure 7-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors, consisting of 8 non-maskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2). If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT. 7.2 Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24F devices clear their registers in response to a Reset which forces the PC to zero. The microcontroller then begins program execution at location 000000h. The user programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction. Interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. PIC24FJ256GB110 family devices implement non-maskable traps and unique interrupts. These are summarized in Table 7-1 and Table 7-2.  2009 Microchip Technology Inc. DS39897C-page 77 PIC24FJ256GB110 FAMILY FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE Decreasing Natural Order Priority Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Start of Code Note 1: TABLE 7-1: 000000h 000002h 000004h 000014h 00007Ch 00007Eh 000080h Interrupt Vector Table (IVT)(1) 0000FCh 0000FEh 000100h 000102h 000114h Alternate Interrupt Vector Table (AIVT)(1) 00017Ch 00017Eh 000180h 0001FEh 000200h See Table 7-2 for the interrupt vector list. TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address Trap Source 0 000004h 000104h 1 000006h 000106h Oscillator Failure 2 000008h 000108h Address Error Reserved 3 00000Ah 00010Ah Stack Error 4 00000Ch 00010Ch Math Error 5 00000Eh 00010Eh Reserved 6 000010h 000110h Reserved 7 000012h 000112h Reserved DS39897C-page 78  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Bit Locations Vector Number IVT Address AIVT Address Flag Enable ADC1 Conversion Done 13 00002Eh 00012Eh IFS0 IEC0 IPC3 Comparator Event 18 000038h 000138h IFS1 IEC1 IPC4 CRC Generator 67 00009Ah 00019Ah IFS4 IEC4 IPC16 CTMU Event 77 0000AEh 0001AEh IFS4 IEC4 IPC19 Interrupt Source Priority External Interrupt 0 0 000014h 000114h IFS0 IEC0 IPC0 External Interrupt 1 20 00003Ch 00013Ch IFS1 IEC1 IPC5 External Interrupt 2 29 00004Eh 00014Eh IFS1 IEC1 IPC7 External Interrupt 3 53 00007Eh 00017Eh IFS3 IEC3 IPC13 IPC13 External Interrupt 4 54 000080h 000180h IFS3 IEC3 I2C1 Master Event 17 000036h 000136h IFS1 IEC1 IPC4 I2C1 Slave Event 16 000034h 000134h IFS1 IEC1 IPC4 I2C2 Master Event 50 000078h 000178h IFS3 IEC3 IPC12 I2C2 Slave Event 49 000076h 000176h IFS3 IEC3 IPC12 I2C3 Master Event 85 0000BEh 0001BEh IFS5 IEC5 IPC21 I2C3 Slave Event 84 0000BCh 0001BCh IFS5 IEC5 IPC21 Input Capture 1 1 000016h 000116h IFS0 IEC0 IPC0 Input Capture 2 5 00001Eh 00011Eh IFS0 IEC0 IPC1 Input Capture 3 37 00005Eh 00015Eh IFS2 IEC2 IPC9 Input Capture 4 38 000060h 000160h IFS2 IEC2 IPC9 Input Capture 5 39 000062h 000162h IFS2 IEC2 IPC9 Input Capture 6 40 000064h 000164h IFS2 IEC2 IPC10 Input Capture 7 22 000040h 000140h IFS1 IEC1 IPC5 Input Capture 8 23 000042h 000142h IFS1 IEC1 IPC5 Input Capture 9 93 0000CEh 0001CEh IFS5 IEC5 IPC23 Input Change Notification 19 00003Ah 00013Ah IFS1 IEC1 IPC4 LVD Low-Voltage Detect 72 0000A4h 0001A4h IFS4 IEC4 IPC18 Output Compare 1 2 000018h 000118h IFS0 IEC0 IPC0 Output Compare 2 6 000020h 000120h IFS0 IEC0 IPC1 Output Compare 3 25 000046h 000146h IFS1 IEC1 IPC6 Output Compare 4 26 000048h 000148h IFS1 IEC1 IPC6 Output Compare 5 41 000066h 000166h IFS2 IEC2 IPC10 Output Compare 6 42 000068h 000168h IFS2 IEC2 IPC10 Output Compare 7 43 00006Ah 00016Ah IFS2 IEC2 IPC10 Output Compare 8 44 00006Ch 00016Ch IFS2 IEC2 IPC11 Output Compare 9 92 0000CCh 0001CCh IFS5 IEC5 IPC23 Parallel Master Port 45 00006Eh 00016Eh IFS2 IEC2 IPC11 Real-Time Clock/Calendar 62 000090h 000190h IFS3 IEC3 IPC15 SPI1 Error 9 000026h 000126h IFS0 IEC0 IPC2 SPI1 Event 10 000028h 000128h IFS0 IEC0 IPC2 SPI2 Error 32 000054h 000154h IFS2 IEC2 IPC8 SPI2 Event 33 000056h 000156h IFS2 IEC2 IPC8 SPI3 Error 90 0000C8h 0001C8h IFS5 IEC5 IPC22 SPI3 Event 91 0000CAh 0001CAh IFS5 IEC5 IPC22  2009 Microchip Technology Inc. DS39897C-page 79 PIC24FJ256GB110 FAMILY TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS (CONTINUED) Interrupt Bit Locations Vector Number IVT Address AIVT Address Flag Enable Priority Timer1 3 00001Ah 00011Ah IFS0 IEC0 IPC0 Timer2 7 000022h 000122h IFS0 IEC0 IPC1 Timer3 8 000024h 000124h IFS0 IEC0 IPC2 Timer4 27 00004Ah 00014Ah IFS1 IEC1 IPC6 Timer5 28 00004Ch 00014Ch IFS1 IEC1 IPC7 UART1 Error 65 000096h 000196h IFS4 IEC4 IPC16 UART1 Receiver 11 00002Ah 00012Ah IFS0 IEC0 IPC2 UART1 Transmitter 12 00002Ch 00012Ch IFS0 IEC0 IPC3 UART2 Error 66 000098h 000198h IFS4 IEC4 IPC16 Interrupt Source UART2 Receiver 30 000050h 000150h IFS1 IEC1 IPC7 UART2 Transmitter 31 000052h 000152h IFS1 IEC1 IPC7 UART3 Error 81 0000B6h 0001B6h IFS5 IEC5 IPC20 UART3 Receiver 82 0000B8h 0001B8h IFS5 IEC5 IPC20 UART3 Transmitter 83 0000BAh 0001BAh IFS5 IEC5 IPC20 UART4 Error 87 0000C2h 0001C2h IFS5 IEC5 IPC21 UART4 Receiver 88 0000C4h 0001C4h IFS5 IEC5 IPC22 UART4 Transmitter 89 0000C6h 0001C6h IFS5 IEC5 IPC22 USB Interrupt 86 0000C0h 0001C0h IFS5 IEC5 IPC21 7.3 Interrupt Control and Status Registers The PIC24FJ256GB110 family of devices implements a total of 37 registers for the interrupt controller: • • • • • • INTCON1 INTCON2 IFS0 through IFS5 IEC0 through IEC5 IPC0 through IPC23 (except IPC14 and IPC17) INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table. The IFSx registers maintain all of the interrupt request flags. Each source of interrupt has a status bit which is set by the respective peripherals, or an external signal, and is cleared via software. The IECx registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. The IPCx registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. DS39897C-page 80 The INTTREG register contains the associated interrupt vector number and the new CPU interrupt priority level, which are latched into the Vector Number (VECNUM) and the Interrupt Level (ILR) bit fields in the INTTREG register. The new interrupt priority level is the priority of the pending interrupt. The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the order of their vector numbers, as shown in Table 7-2. For example, the INT0 (External Interrupt 0) is shown as having a vector number and a natural order priority of 0. Thus, the INT0IF status bit is found in IFS0, the INT0IE enable bit in IEC0 and the INT0IP priority bits in the first position of IPC0 (IPC0). Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. The ALU STATUS register (SR) contains the IPL bits (SR). These indicate the current CPU interrupt priority level. The user may change the current CPU priority level by writing to the IPL bits. The CORCON register contains the IPL3 bit, which together with IPL, indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All interrupt registers are described in Register 7-1 through Register 7-39, in the following pages.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-1: SR: ALU STATUS REGISTER (IN CPU) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0 — — — — — — — DC(1) bit 15 bit 8 R/W-0 IPL2 (2,3) R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU interrupt priority level is 7 (15). User interrupts disabled. 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) bit 7-5 Note 1: 2: 3: See Register 3-1 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. The IPL bits are concatenated with the IPL3 bit (CORCON) to form the CPU interrupt priority level. The value in parentheses indicates the interrupt priority level if IPL3 = 1. The IPL Status bits are read-only when NSTDIS (INTCON1) = 1. REGISTER 7-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0 — — — — IPL3(2) PSV(1) — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL3: CPU Interrupt Priority Level Status bit(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 3 Note 1: 2: See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level.  2009 Microchip Technology Inc. DS39897C-page 81 PIC24FJ256GB110 FAMILY REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14-5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Arithmetic Error Trap Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS39897C-page 82 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use Alternate Interrupt Vector Table 0 = Use standard (default) vector table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-5 Unimplemented: Read as ‘0’ bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 3 INT3EP: External Interrupt 3 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 83 PIC24FJ256GB110 FAMILY REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 — bit 15 U-0 — R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPF1IF R/W-0 T3IF bit 8 R/W-0 T2IF bit 7 R/W-0 OC2IF R/W-0 IC2IF U-0 — R/W-0 T1IF R/W-0 OC1IF R/W-0 IC1IF R/W-0 INT0IF bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ AD1IF: A/D Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF1IF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS39897C-page 84  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 U2TXIF bit 15 R/W-0 U2RXIF R/W-0 IC8IF bit 7 R/W-0 IC7IF bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W-0 T5IF R/W-0 T4IF R/W-0 OC4IF R/W-0 OC3IF U-0 — bit 8 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 INT2IF U-0 — W = Writable bit ‘1’ = Bit is set R/W-0 INT1IF R/W-0 CNIF R/W-0 CMIF R/W-0 MI2C1IF R/W-0 SI2C1IF bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ IC8IF: Input Capture Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC7IF: Input Capture Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2009 Microchip Technology Inc. DS39897C-page 85 PIC24FJ256GB110 FAMILY REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — PMPIF OC8IF OC7IF OC6IF OC5IF IC6IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 OC8IF: Output Compare Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 OC7IF: Output Compare Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 OC6IF: Output Compare Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 IC6IF: Input Capture Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-2 Unimplemented: Read as ‘0’ bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS39897C-page 86 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIF — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 — INT4IF INT3IF — — MI2C2IF SI2C2IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-7 Unimplemented: Read as ‘0’ bit 6 INT4IF: External Interrupt 4 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 INT3IF: External Interrupt 3 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IF: Master I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 87 PIC24FJ256GB110 FAMILY REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIF — — — — LVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-9 Unimplemented: Read as ‘0’ bit 8 LVDIF: Low-Voltage Detect Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7-4 Unimplemented: Read as ‘0’ bit 3 CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ DS39897C-page 88 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-10: U-0 — bit 15 R/W-0 U4ERIF bit 7 U-0 — R/W-0 IC9IF R/W-0 OC9IF R/W-0 SPI3IF R/W-0 SPF3IF R/W-0 U4TXIF R/W-0 USB1IF R/W-0 MI2C3IF R/W-0 SI2C3IF R/W-0 U3TXIF R/W-0 U3RXIF R/W-0 U3ERIF bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W-0 U4RXIF bit 8 U-0 — bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 IFS5: INTERRUPT FLAG STATUS REGISTER 5 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ IC9IF: Input Capture Channel 9 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC9IF: Output Compare Channel 9 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI3IF: SPI3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF3IF: SPI3 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U4TXIF: UART4 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U4RXIF: UART4 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U4ERIF: UART4 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred USB1IF: USB1 (USB OTG) Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred MI2C3IF: Master I2C3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C3IF: Slave I2C3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U3TXIF: UART3 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U3RXIF: UART3 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U3ERIF: UART3 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. DS39897C-page 89 PIC24FJ256GB110 FAMILY REGISTER 7-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 — bit 15 U-0 — R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 T2IE bit 7 R/W-0 OC2IE R/W-0 IC2IE U-0 — R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE R/W-0 INT0IE bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ AD1IE: A/D Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI1IE: SPI1 Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPF1IE: SPI1 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as ‘0’ T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS39897C-page 90  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-12: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 U2TXIE bit 15 R/W-0 U2RXIE R/W-0 IC8IE bit 7 R/W-0 IC7IE bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Note 1: R/W-0 T5IE R/W-0 T4IE R/W-0 OC4IE R/W-0 OC3IE U-0 — bit 8 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 INT2IE(1) U-0 — W = Writable bit ‘1’ = Bit is set R/W-0 INT1IE(1) R/W-0 CNIE R/W-0 CMIE R/W-0 MI2C1IE R/W-0 SI2C1IE bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT2IE: External Interrupt 2 Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as ‘0’ IC8IE: Input Capture Channel 8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC7IE: Input Capture Channel 7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as ‘0’ INT1IE: External Interrupt 1 Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled CMIE: Comparator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. See Section 10.4 “Peripheral Pin Select” for more information.  2009 Microchip Technology Inc. DS39897C-page 91 PIC24FJ256GB110 FAMILY REGISTER 7-12: bit 1 bit 0 Note 1: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. See Section 10.4 “Peripheral Pin Select” for more information. DS39897C-page 92  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-13: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 PMPIE: Parallel Master Port Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 OC8IE: Output Compare Channel 8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 OC7IE: Output Compare Channel 7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 OC6IE: Output Compare Channel 6 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 OC5IE: Output Compare Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 IC6IE: Input Capture Channel 6 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 IC5IE: Input Capture Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4-2 Unimplemented: Read as ‘0’ bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 93 PIC24FJ256GB110 FAMILY REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIE — — — — — — bit 15 bit 8 U-0 — R/W-0 INT4IE (1) R/W-0 (1) INT3IE U-0 U-0 R/W-0 R/W-0 U-0 — — MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13-7 Unimplemented: Read as ‘0’ bit 6 INT4IE: External Interrupt 4 Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 INT3IE: External Interrupt 3 Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IE: Master I2C2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. See Section 10.4 “Peripheral Pin Select” for more information. DS39897C-page 94  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIE — — — — LVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12-9 Unimplemented: Read as ‘0’ bit 8 LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7-4 Unimplemented: Read as ‘0’ bit 3 CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 95 PIC24FJ256GB110 FAMILY REGISTER 7-16: U-0 — bit 15 R/W-0 U4ERIE bit 7 U-0 — R/W-0 IC9IE R/W-0 OC9IE R/W-0 SPI3IE R/W-0 SPF3IE R/W-0 U4TXIE R/W-0 USB1IE R/W-0 MI2C3IE R/W-0 SI2C3IE R/W-0 U3TXIE R/W-0 U3RXIE R/W-0 U3ERIE bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W-0 U4RXIE bit 8 U-0 — bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ IC9IE: Input Capture Channel 9 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC9IE: Output Compare Channel 9 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI3IE: SPI3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPF3IE: SPI3 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U4TXIE: UART4 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U4RXIE: UART4 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U4ERIE: UART4 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled USB1IE: USB1 (USB OTG) Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled MI2C3IE: Master I2C3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C3IE: Slave I2C3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U3TXIE: UART3 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U3RXIE: UART3 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U3ERIE: UART3 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as ‘0’ DS39897C-page 96  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-17: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 97 PIC24FJ256GB110 FAMILY REGISTER 7-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC2IP2 IC2IP1 IC2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC2IP: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC2IP: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39897C-page 98 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-19: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPF1IP: SPI1 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 99 PIC24FJ256GB110 FAMILY REGISTER 7-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP: A/D Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39897C-page 100 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-21: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP: Input Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 CMIP: Comparator Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1P: Master I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1P: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 101 PIC24FJ256GB110 FAMILY REGISTER 7-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC8IP2 IC8IP1 IC8IP0 — IC7IP2 IC7IP1 IC7IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP: Input Capture Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC7IP: Input Capture Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39897C-page 102 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-23: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — OC3IP2 OC3IP1 OC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP: Timer4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC4IP: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC3IP: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 103 PIC24FJ256GB110 FAMILY REGISTER 7-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2RXIP: UART2 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T5IP: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39897C-page 104 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-25: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP: SPI2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SPF2IP: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 105 PIC24FJ256GB110 FAMILY REGISTER 7-26: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC3IP2 IC3IP1 IC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC5IP: Input Capture Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC4IP: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC3IP: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39897C-page 106 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-27: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC7IP2 OC7IP1 OC7IP0 — OC6IP2 OC6IP1 OC6IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC5IP2 OC5IP1 OC5IP0 — IC6IP2 IC6IP1 IC6IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 OC7IP: Output Compare Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC6IP: Output Compare Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC5IP: Output Compare Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 IC6IP: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 107 PIC24FJ256GB110 FAMILY REGISTER 7-28: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — PMPIP2 PMPIP1 PMPIP0 — OC8IP2 OC8IP1 OC8IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PMPIP: Parallel Master Port Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 OC8IP: Output Compare Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39897C-page 108 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-29: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — MI2C2P2 MI2C2P1 MI2C2P0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SI2C2P2 SI2C2P1 SI2C2P0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2P: Master I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SI2C2P: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 109 PIC24FJ256GB110 FAMILY REGISTER 7-30: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT4IP2 INT4IP1 INT4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT3IP2 INT3IP1 INT3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 INT4IP: External Interrupt 4 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT3IP: External Interrupt 3 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39897C-page 110 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-31: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 111 PIC24FJ256GB110 FAMILY REGISTER 7-32: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP: CRC Generator Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2ERIP: UART2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U1ERIP: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39897C-page 112 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-33: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — LVDIP2 LVDIP1 LVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 LVDIP: Low-Voltage Detect Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled REGISTER 7-34: x = Bit is unknown IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CTMUIP2 CTMUIP1 CTMUIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CTMUIP: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 113 PIC24FJ256GB110 FAMILY REGISTER 7-35: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U3TXIP2 U3TXIP1 U3TXIP0 — U3RXIP2 U3RXIP1 U3RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U3ERIP2 U3ERIP1 U3ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U3TXIP: UART3 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U3RXIP: UART3 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U3ERIP: UART3 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39897C-page 114 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-36: IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U4ERIP2 U4ERIP1 U4ERIP0 — USB1IP2 USB1IP1 USB1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C3P2 MI2C3P1 MI2C3P0 — SI2C3P2 SI2C3P1 SI2C3P0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U4ERIP: UART4 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 USB1IP: USB1 (USB OTG) Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C3P: Master I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C3P: Slave I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 115 PIC24FJ256GB110 FAMILY REGISTER 7-37: IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI3IP2 SPI3IP1 SPI3IP0 — SPF3IP2 SPF3IP1 SPF3IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U4TXIP2 U4TXIP1 U4TXIP0 — U4RXIP2 U4RXIP1 U4RXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 SPI3IP: SPI3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPF3IP: SPI3 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U4TXIP: UART4 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U4RXIP: UART4 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39897C-page 116 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-38: IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC9IP2 IC9IP1 IC9IP0 — OC9IP2 OC9IP1 OC9IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 IC9IP: Input Capture Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 OC9IP: Output Compare Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 117 PIC24FJ256GB110 FAMILY REGISTER 7-39: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 x = Bit is unknown CPUIRQ: Interrupt Request from Interrupt Controller CPU bit 1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens when the CPU priority is higher than the interrupt priority 0 = No interrupt request is unacknowledged bit 14 Unimplemented: Read as ‘0’ bit 13 VHOLD: Vector Number Capture Configuration bit 1 = VECNUM contains the value of the highest priority pending interrupt 0 = VECNUM contains the value of the last Acknowledged interrupt (i.e., the last interrupt that has occurred with higher priority than the CPU, even if other interrupts are pending) bit 12 Unimplemented: Read as ‘0’ bit 11-8 ILR: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM: Pending Interrupt Vector ID bits (pending vector number is VECNUM + 8) 0111111 = Interrupt vector pending is number 135 • • • 0000001 = Interrupt vector pending is number 9 0000000 = Interrupt vector pending is number 8 DS39897C-page 118  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 7.4 Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS Control bit (INTCON1) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources may be programmed to the same non-zero value. Note: 3. 4. At a device Reset, the IPCx registers are initialized, such that all user interrupt sources are assigned to priority level 4. Clear the interrupt flag status bit associated with the peripheral in the associated IFSx register. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx register. 7.4.2 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR. 7.4.4 INTERRUPT DISABLE All user interrupts can be disabled using the following procedure: 1. 2. Push the current SR value onto the software stack using the PUSH instruction. Force the CPU to priority level 7 by inclusive ORing the value E0h with SRL. To enable user interrupts, the POP instruction may be used to restore the previous SR value. Note that only user interrupts with a priority level of 7 or less can be disabled. Trap sources (level 8-15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. INTERRUPT SERVICE ROUTINE The method that is used to declare an ISR and initialize the IVT with the correct vector address will depend on the programming language (i.e., ‘C’ or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of the interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.  2009 Microchip Technology Inc. DS39897C-page 119 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 120  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 8.0 OSCILLATOR CONFIGURATION Note: • An on-chip USB PLL block to provide a stable, 48 MHz clock for the USB module as well as a range of frequency options for the system clock • Software-controllable switching between various clock sources • Software-controllable postscaler for selective clocking of CPU for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown • A separate and independently configurable system clock output for synchronizing external hardware This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 6. “Oscillator” (DS39700). The oscillator system for PIC24FJ256GB110 family devices has the following features: • A total of four external and internal oscillator options as clock sources, providing 11 different clock modes FIGURE 8-1: A simplified diagram of the oscillator system is shown in Figure 8-1. PIC24FJ256GB110 FAMILY CLOCK DIAGRAM PIC24FJ256GB110 Family 48 MHz USB Clock Primary Oscillator XT, HS, EC OSCO USB PLL ECPLL,FRCPLL PLL & DIV OSCI PLLDIV 8 MHz 4 MHz FRCDIV Peripherals CLKDIV LPRC Oscillator REFO FRC CLKO Postscaler 8 MHz (nominal) Reference Clock Generator CPDIV Postscaler FRC Oscillator REFOCON XTPLL, HSPLL LPRC 31 kHz (nominal) Secondary Oscillator CLKDIV SOSC SOSCO SOSCI CPU SOSCEN Enable Oscillator Clock Control Logic Fail-Safe Clock Monitor WDT, PWRT Clock Source Option for Other Modules  2009 Microchip Technology Inc. DS39897C-page 121 PIC24FJ256GB110 FAMILY 8.1 CPU Clocking Scheme 8.2 The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator The Primary Oscillator and FRC sources have the option of using the internal USB PLL block, which generates both the USB module clock and a separate system clock from the 96 MHZ PLL. Refer to Section 8.5 “Oscillator Modes and USB Operation” for additional information. The Fast Internal FRC provides an 8 MHz clock source. It can optionally be reduced by the programmable clock divider to provide a range of system clock frequencies. The selected clock source generates the processor and peripheral clock sources. The processor clock source is divided by two to produce the internal instruction cycle clock, FCY. In this document, the instruction cycle clock is also denoted by FOSC/2. The internal instruction cycle clock, FOSC/2, can be provided on the OSCO I/O pin for some operating modes of the Primary Oscillator. TABLE 8-1: Initial Configuration on POR The oscillator source (and operating mode) that is used at a device Power-on Reset event is selected using Configuration bit settings. The oscillator Configuration bit settings are located in the Configuration registers in the program memory (refer to Section 26.1 “Configuration Bits” for further details). The Primary Oscillator Configuration bits, POSCMD (Configuration Word 2), and the Initial Oscillator Select Configuration bits, FNOSC (Configuration Word 2), select the oscillator source that is used at a Power-on Reset. The FRC Primary Oscillator with Postscaler (FRCDIV) is the default (unprogrammed) selection. The Secondary Oscillator, or one of the internal oscillators, may be chosen by programming these bit locations. The Configuration bits allow users to choose between the various clock modes, shown in Table 8-1. 8.2.1 CLOCK SWITCHING MODE CONFIGURATION BITS The FCKSM Configuration bits (Configuration Word 2) are used to jointly configure device clock switching and the Fail-Safe Clock Monitor (FSCM). Clock switching is enabled only when FCKSM1 is programmed (‘0’). The FSCM is enabled only when FCKSM are both programmed (‘00’). CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD FNOSC Note Fast RC Oscillator with Postscaler (FRCDIV) Internal 11 111 1, 2 (Reserved) Internal xx 110 1 Low-Power RC Oscillator (LPRC) Internal 11 101 1 Secondary 11 100 1 Primary Oscillator (XT) with PLL Module (XTPLL) Primary 01 011 Primary Oscillator (EC) with PLL Module (ECPLL) Primary 00 011 Primary Oscillator (HS) Primary 10 010 Primary Oscillator (XT) Primary 01 010 Primary Oscillator (EC) Primary 00 010 Fast RC Oscillator with PLL Module (FRCPLL) Internal 11 001 1 Fast RC Oscillator (FRC) Internal 11 000 1 Secondary (Timer1) Oscillator (SOSC) Note 1: 2: OSCO pin function is determined by the OSCIOFCN Configuration bit. This is the default oscillator mode for an unprogrammed (erased) device. DS39897C-page 122  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 8.3 Control Registers The operation of the oscillator is controlled by three Special Function Registers: • OSCCON • CLKDIV • OSCTUN REGISTER 8-1: The OSCCON register (Register 8-1) is the main control register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. The CLKDIV register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC Oscillator. The OSCTUN register (Register 8-3) allows the user to fine tune the FRC Oscillator over a range of approximately ±12%. OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 R-0 U-0 R/W-x(1) R/W-x(1) R/W-x(1) — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 bit 15 bit 8 R/SO-0 R/W-0 R-0(3) U-0 R/CO-0 R/W-0 R/W-0 R/W-0 CLKLOCK IOLOCK(2) LOCK — CF POSCEN SOSCEN OSWEN bit 7 bit 0 Legend: CO = Clear Only bit SO = Set Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC: Current Oscillator Selection bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC: New Oscillator Selection bits(1) 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) Note 1: 2: 3: x = Bit is unknown Reset values for these bits are determined by the FNOSC Configuration bits. The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. Also resets to ‘0’ during any valid clock switch or whenever a non PLL clock mode is selected.  2009 Microchip Technology Inc. DS39897C-page 123 PIC24FJ256GB110 FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. bit 6 IOLOCK: I/O Lock Enable bit(2) 1 = I/O lock is active 0 = I/O lock is not active bit 5 LOCK: PLL Lock Status bit(3) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 POSCEN: Primary Oscillator Sleep Enable bit 1 = Primary Oscillator continues to operate during Sleep mode 0 = Primary Oscillator disabled during Sleep mode bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to clock source specified by the NOSC bits 0 = Oscillator switch is complete Note 1: 2: 3: Reset values for these bits are determined by the FNOSC Configuration bits. The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. Also resets to ‘0’ during any valid clock switch or whenever a non PLL clock mode is selected. DS39897C-page 124  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 8-2: R/W-0 CLKDIV: CLOCK DIVIDER REGISTER R/W-0 ROI R/W-0 DOZE2 DOZE1 R/W-0 DOZE0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-1 RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 CPDIV1 CPDIV0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE: CPU Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 11 DOZEN: DOZE Enable bit(1) 1 = DOZE bits specify the CPU peripheral clock ratio 0 = CPU peripheral clock ratio is set to 1:1 bit 10-8 RCDIV: FRC Postscaler Select bits 111 = 31.25 kHz (divide-by-256) 110 = 125 kHz (divide-by-64) 101 = 250 kHz (divide-by-32) 100 = 500 kHz (divide-by-16) 011 = 1 MHz (divide-by-8) 010 = 2 MHz (divide-by-4) 001 = 4 MHz (divide-by-2) 000 = 8 MHz (divide-by-1) bit 7-6 CPDIV: USB System Clock Select bits (postscaler select from 32 MHz clock branch) 11 = 4 MHz (divide-by-8)(2) 10 = 8 MHz (divide-by-4)(2) 01 = 16 MHz (divide-by-2) 00 = 32 MHz (divide-by-1) bit 5-0 Unimplemented: Read as ‘0’ Note 1: 2: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. This setting is not allowed while the USB module is enabled.  2009 Microchip Technology Inc. DS39897C-page 125 PIC24FJ256GB110 FAMILY REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN: FRC Oscillator Tuning bits(1) 011111 = Maximum frequency deviation 011110 =    000001 = 000000 = Center frequency, oscillator is running at factory calibrated frequency 111111 =    100001 = 100000 = Minimum frequency deviation Note 1: 8.4 Increments or decrements of TUN may not change the FRC frequency in equal steps over the FRC tuning range, and may not be monotonic. Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: The Primary Oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMDx Configuration bits. While an application can switch to and from Primary Oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. DS39897C-page 126 8.4.1 ENABLING CLOCK SWITCHING To enable clock switching, the FCKSM1 Configuration bit in CW2 must be programmed to ‘0’. (Refer to Section 26.1 “Configuration Bits” for further details.) If the FCKSM1 Configuration bit is unprogrammed (‘1’), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting. The NOSCx control bits (OSCCON) do not control the clock selection when clock switching is disabled. However, the COSCx bits (OSCCON) will reflect the clock source selected by the FNOSCx Configuration bits. The OSWEN control bit (OSCCON) has no effect when clock switching is disabled; it is held at ‘0’ at all times.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 8.4.2 OSCILLATOR SWITCHING SEQUENCE A recommended code sequence for a clock switch includes the following: At a minimum, performing a clock switch requires this basic sequence: 1. 1. 2. 2. 3. 4. 5. If desired, read the COSCx bits (OSCCON) to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSCx bits (OSCCON) for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit to initiate the oscillator switch. 3. 4. 5. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 6. 1. 7. 2. 3. 4. 5. 6. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. If a valid clock switch has been initiated, the LOCK (OSCCON) and CF (OSCCON) bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the Oscillator Start-up Timer (OST) expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSCx bit values are transferred to the COSCx bits. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM is enabled) or SOSC (if SOSCEN remains set). Note 1: The processor will continue to execute code throughout the clock switching sequence. Timing-sensitive code should not be executed during this time. 8. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON in two back-to-back instructions. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence. Execute the unlock sequence for the OSCCON low byte by writing 46h and 57h to OSCCON in two back-to-back instructions. Set the OSWEN bit in the instruction immediately following the unlock sequence. Continue to execute code that is not clock-sensitive (optional). Invoke an appropriate amount of software delay (cycle counting) to allow the selected oscillator and/or PLL to start and stabilize. Check to see if OSWEN is ‘0’. If it is, the switch was successful. If OSWEN is still set, then check the LOCK bit to determine the cause of the failure. The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example 8-1. EXAMPLE 8-1: BASIC CODE SEQUENCE FOR CLOCK SWITCHING ;Place the new oscillator selection in W0 ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Set new oscillator selection MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON,#0 2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.  2009 Microchip Technology Inc. DS39897C-page 127 PIC24FJ256GB110 FAMILY 8.5 Oscillator Modes and USB Operation TABLE 8-2: Because of the timing requirements imposed by USB, an internal clock of 48 MHz is required at all times while the USB module is enabled. Since this is well beyond the maximum CPU clock speed, a method is provided to internally generate both the USB and system clocks from a single oscillator source. PIC24FJ256GB110 family devices use the same clock structure as other PIC24FJ devices, but include a two-branch PLL system to generate the two clock signals. The USB PLL block is shown in Figure 8-2. In this system, the input from the Primary Oscillator is divided down by a PLL prescaler to generate a 4 MHz output. This is used to drive an on-chip 96 MHz PLL frequency multiplier to drive the two clock branches. One branch uses a fixed divide-by-2 frequency divider to generate the 48 MHz USB clock. The other branch uses a fixed divide-by-3 frequency divider and configurable PLL prescaler/divider to generate a range of system clock frequencies. The CPDIV bits select the system clock speed; available clock options are listed in Table 8-2. The USB PLL prescaler does not automatically sense the incoming oscillator frequency. The user must manually configure the PLL divider to generate the required 4 MHz output, using the PLLDIV Configuration bits. This limits the choices for Primary Oscillator frequency to a total of 8 possibilities, shown in Table 8-3. FIGURE 8-2: SYSTEM CLOCK OPTIONS DURING USB OPERATION MCU Clock Division (CPDIV) Microcontroller Clock Frequency None (00) 32 MHz 2 (01) 16 MHz 4 (10) 8 MHz 8 (11) 4 MHz TABLE 8-3: VALID PRIMARY OSCILLATOR CONFIGURATIONS FOR USB OPERATIONS Input Oscillator Frequency Clock Mode PLL Division (PLLDIV) 48 MHz ECPLL 12 (111) 40 MHz ECPLL 10 (110) 24 MHz HSPLL, ECPLL 6 (101) 20 MHz HSPLL, ECPLL 5 (100) 16 MHz HSPLL, ECPLL 4 (011) 12 MHz HSPLL, ECPLL 3 (010) 8 MHz ECPLL, XTPLL 2 (001) 4 MHz ECPLL, XTPLL 1 (000) USB PLL BLOCK PLLDIV Input from FRC (4 MHz or 8 MHz)  12  10 6 5 4 3 2 1 111 110 101 100 011 010 001 000 PLLDIS 4 MHz 48 MHz Clock for USB Module 2 96 MHz PLL 3 32 MHz PLL Prescaler Input from POSC PLL Prescaler FNOSC 8 4 2 1 11 10 01 00 PLL Output for System Clock CPDIV DS39897C-page 128  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 8.5.1 CONSIDERATIONS FOR USB OPERATION When using the USB On-The-Go module in PIC24FJ256GB110 family devices, users must always observe these rules in configuring the system clock: • For USB operation, the selected clock source (EC, HS or XT) must meet the USB clock tolerance requirements. • The Primary Oscillator/PLL modes are the only oscillator configurations that permit USB operation. There is no provision to provide a separate external clock source to the USB module. • While the FRCPLL Oscillator mode is available in these devices, it should never be used for USB applications. FRCPLL mode is still available when the application is not using the USB module. However, the user must always ensure that the FRC source is configured to provide a frequency of 4 MHz or 8 MHz (RCDIV = 001 or 000) and that the USB PLL prescaler is configured appropriately. • All other oscillator modes are available; however, USB operation is not possible when these modes are selected. They may still be useful in cases where other power levels of operation are desirable and the USB module is not needed (e.g., the application is in Sleep and waiting for bus attachment).  2009 Microchip Technology Inc. 8.6 Reference Clock Output In addition to the CLKO output (FOSC/2) available in certain oscillator modes, the device clock in the PIC24FJ256GB110 family devices can also be configured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. This reference clock output is controlled by the REFOCON register (Register 8-4). Setting the ROEN bit (REFOCON) makes the clock signal available on the REFO pin. The RODIV bits (REFOCON) enable the selection of 16 different clock divider options. The ROSSLP and ROSEL bits (REFOCON) control the availability of the reference output during Sleep mode. The ROSEL bit determines if the oscillator on OSC1 and OSC2, or the current system clock source, is used for the reference clock output. The ROSSLP bit determines if the reference source is available on REFO when the device is in Sleep mode. To use the reference clock output in Sleep mode, both the ROSSLP and ROSEL bits must be set. The device clock must also be configured for one of the primary modes (EC, HS or XT); otherwise, if the POSCEN bit is not also set, the oscillator on OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches. DS39897C-page 129 PIC24FJ256GB110 FAMILY REGISTER 8-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Reference oscillator enabled on REFO pin 0 = Reference oscillator disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep bit 12 ROSEL: Reference Oscillator Source Select bit 1 = Primary Oscillator used as the base clock. Note that the crystal oscillator must be enabled using the FOSC bits; crystal maintains the operation in Sleep mode. 0 = System clock used as the base clock; base clock reflects any clock switching of the device bit 11-8 RODIV: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’ DS39897C-page 130  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 9.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 10. “Power-Saving Features” (DS39698). The PIC24FJ256GB110 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. All PIC24F devices manage power consumption in four different ways: • • • • Clock frequency Instruction-based Sleep and Idle modes Software controlled Doze mode Selective peripheral control in software Combinations of these methods can be used to selectively tailor an application’s power consumption, while still maintaining critical application features, such as timing-sensitive communications. 9.1 Clock Frequency and Clock Switching PIC24F devices allow for a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits. The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 8.0 “Oscillator Configuration”. 9.2 Instruction-Based Power-Saving Modes Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to “wake-up”. Note: 9.2.1 SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device. SLEEP MODE Sleep mode has these features: • The system clock source is shut down. If an on-chip oscillator is used, it is turned off. • The device current consumption will be reduced to a minimum provided that no I/O pin is sourcing current. • The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source is disabled. • The LPRC clock will continue to run in Sleep mode if the WDT is enabled. • The WDT, if enabled, is automatically cleared prior to entering Sleep mode. • Some device features or peripherals may continue to operate in Sleep mode. This includes items such as the input change notification on the I/O ports, or peripherals that use an external clock input. Any peripheral that requires the system clock source for its operation will be disabled in Sleep mode. The device will wake-up from Sleep mode on any of the these events: • On any interrupt source that is individually enabled • On any form of device Reset • On a WDT time-out On wake-up from Sleep, the processor will restart with the same clock source that was active when Sleep mode was entered. PIC24F devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution; Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembly syntax of the PWRSAV instruction is shown in Example 9-1. EXAMPLE 9-1: PWRSAV PWRSAV PWRSAV INSTRUCTION SYNTAX #SLEEP_MODE #IDLE_MODE  2009 Microchip Technology Inc. ; Put the device into SLEEP mode ; Put the device into IDLE mode DS39897C-page 131 PIC24FJ256GB110 FAMILY 9.2.2 IDLE MODE Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Selective Peripheral Module Control”). • If the WDT or FSCM is enabled, the LPRC will also remain active. The device will wake from Idle mode on any of these events: • Any interrupt that is individually enabled. • Any device Reset. • A WDT time-out. On wake-up from Idle, the clock is reapplied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction or the first instruction in the ISR. 9.2.3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry into Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode. 9.3 Doze Mode Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely. Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. Doze mode is enabled by setting the DOZEN bit (CLKDIV). The ratio between peripheral and core clock speed is determined by the DOZE bits (CLKDIV). There are eight possible configurations, from 1:1 to 1:256, with 1:1 being the default. DS39897C-page 132 It is also possible to use Doze mode to selectively reduce power consumption in event driven applications. This allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the CPU Idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV). By default, interrupt events have no effect on Doze mode operation. 9.4 Selective Peripheral Module Control Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock. Even so, peripheral modules still remain clocked, and thus, consume power. There may be cases where the application needs what these modes do not provide: the allocation of power resources to CPU processing with minimal power consumption from the peripherals. PIC24F devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with two control bits: • The Peripheral Enable bit, generically named, “XXXEN”, located in the module’s main control SFR. • The Peripheral Module Disable (PMD) bit, generically named, “XXXMD”, located in one of the PMD Control registers. Both bits have similar functions in enabling or disabling their associated module. Setting the PMD bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. In this state, the control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect and read values will be invalid. Many peripheral modules have a corresponding PMD bit. In contrast, disabling a module by clearing its XXXEN bit disables its functionality, but leaves its registers available to be read and written to. This reduces power consumption, but not by as much as setting the PMD bit does. Most peripheral modules have an enable bit; exceptions include input capture, output compare and RTCC. To achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters Idle mode. This is done through the control bit of the generic name format, “XXXIDL”. By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 10.0 Note: I/O PORTS When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 12. “I/O Ports with Peripheral Pin Select (PPS)” (DS39711). All of the device pins (except VDD, VSS, MCLR and OSCI/CLKI) are shared between the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity. 10.1 Parallel I/O (PIO) Ports A parallel I/O port that shares a pin with a peripheral is, in general, subservient to the peripheral. The peripheral’s output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. Figure 10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. FIGURE 10-1: All port pins have three registers directly associated with their operation as digital I/O. The Data Direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the Output Latch register (LATx), read the latch. Writes to the latch, write the latch. Reads from the port (PORTx), read the port pins, while writes to the port pins, write the latch. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers, and the port pin, will read as zeros. When a pin is shared with another peripheral or function that is defined as an input only, it is regarded as a dedicated port because there is no other competing source of outputs. BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Peripheral Output Data 0 PIO Module Read TRIS Data Bus WR TRIS 1 Output Enable Output Data 0 D Q I/O Pin CK TRIS Latch D WR LAT + WR PORT Q CK Data Latch Read LAT Input Data Read PORT  2009 Microchip Technology Inc. DS39897C-page 133 PIC24FJ256GB110 FAMILY 10.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired digital only pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. 10.2 When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will not convert an analog input. Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. ANALOG INPUT PINS AND VOLTAGE CONSIDERATIONS The voltage tolerance of pins used as device inputs is dependent on the pin’s input function. Pins that are used as digital only inputs are able to handle DC voltages up to 5.5V, a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind can only tolerate voltages up to VDD. Voltage excursions beyond VDD on these pins are always to be avoided. Table 10-1 summarizes the input capabilities. Refer to Section 29.1 “DC Characteristics” for more details. Note: Configuring Analog Port Pins The AD1PCFGL and TRIS registers control the operation of the A/D port pins. Setting a port pin as an analog input also requires that the corresponding TRIS bit be set. If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. 10.2.1 10.2.2 For easy identification, the pin diagrams at the beginning of the data sheet also indicate 5.5V tolerant pins with dark grey shading. TABLE 10-1: Port or Pin PORTA INPUT VOLTAGE LEVELS(1) Tolerated Input Description VDD Only VDD input levels tolerated. 5.5V Tolerates input levels above VDD, useful for most standard logic. PORTB PORTC PORTD PORTF PORTG, PORTG PORTA, PORTA PORTC PORTD, PORTD PORTE PORTF, PORTF, PORTF PORTG, PORTG Note 1: EXAMPLE 10-1: MOV MOV NOP BTSS 0xFF00, W0 W0, TRISBB PORTB, #13 DS39897C-page 134 Not all port pins shown here are implemented on 64-pin and 80-pin devices. Refer to Section 1.0 “Device Overview” to confirm which ports are available in specific devices. PORT WRITE/READ EXAMPLE ; ; ; ; Configure PORTB as inputs and PORTB as outputs Delay 1 cycle Next Instruction  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 10.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ256GB110 family of devices to generate interrupt requests to the processor in response to a Change-Of-State (COS) on selected input pins. This feature is capable of detecting input Change-Of-States even in Sleep mode, when the clocks are disabled. Depending on the device pin count, there are up to 81 external inputs that may be selected (enabled) for generating an interrupt request on a Change-Of-State. Registers, CNEN1 through CNEN6, contain the interrupt enable control bits for each of the CN input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. Each CN pin has a both a weak pull-up and a weak pull-down connected to it. The pull-ups act as a current source that is connected to the pin, while the pull-downs act as a current sink that is connected to the pin. These eliminate the need for external resistors when push button or keypad devices are connected. The pull-ups and pull-downs are separately enabled using the CNPU1 through CNPU6 registers (for pull-ups) and the CNPD1 through CNPD6 registers (for pull-downs). Each CN pin has individual control bits for its pull-up and pull-down. Setting a control bit enables the weak pull-up or pull-down for the corresponding pin. When the internal pull-up is selected, the pin pulls up to VDD – 0.7V (typical). Make sure that there is no external pull-up source when the internal pull-ups are enabled, as the voltage difference can cause a current path. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. 10.4 Peripheral Pin Select A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. In an application that needs to use more than one peripheral multiplexed on a single pin, inconvenient workarounds in application code or a complete redesign may be the only option. The Peripheral Pin Select (PPS) feature provides an alternative to these choices by enabling the user’s peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The Peripheral Pin Select feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of any one of many digital peripherals to any one of these I/O pins. Peripheral Pin Select is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. 10.4.1 AVAILABLE PINS The Peripheral Pin Select feature is used with a range of up to 44 pins, depending on the particular device and its pin count. Pins that support the Peripheral Pin Select feature include the designation, “RPn” or “RPIn”, in their full pin designation, where “n” is the remappable pin number. “RP” is used to designate pins that support both remappable input and output functions, while “RPI” indicates pins that support remappable input functions only. PIC24FJ256GB110 family devices support a larger number of remappable input only pins than remappable input/output pins. In this device family, there are up to 32 remappable input/output pins, depending on the pin count of the particular device selected; these are numbered, RP0 through RP31. Remappable input only pins are numbered above this range, from RPI32 to RPI43 (or the upper limit for that particular device). See Table 1-4 for a summary of pinout options in each package offering.  2009 Microchip Technology Inc. DS39897C-page 135 PIC24FJ256GB110 FAMILY 10.4.2 AVAILABLE PERIPHERALS The peripherals managed by the Peripheral Pin Select are all digital only peripherals. These include general serial communications (UART and SPI), general purpose timer clock inputs, timer related peripherals (input capture and output compare) and external interrupt inputs. Also included are the outputs of the comparator module, since these are discrete digital signals. Peripheral Pin Select is not available for I2C™ change notification inputs, RTCC alarm outputs or peripherals with analog inputs. A key difference between pin select and non pin select peripherals is that pin select peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non pin select peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. 10.4.2.1 Peripheral Pin Select Function Priority Pin-selectable peripheral outputs (e.g., OC, UART Transmit) take priority over general purpose digital functions on a pin, such as PMP and port I/O. Specialized digital outputs, such as USB functionality, will take priority over PPS outputs on the same pin. The pin diagrams provided at the beginning of this data sheet list peripheral outputs in the order of priority. Refer to them for priority concerns on a particular pin. Unlike PIC24F devices with fixed peripherals, pin-selectable peripheral inputs never take ownership of a pin. The pin’s output buffer is controlled by the TRISx setting or by a fixed peripheral on the pin. If the pin is configured in Digital mode, the PPS input will operate correctly. If an analog function is enabled on the pin, the PPS input will be disabled. 10.4.3 CONTROLLING PERIPHERAL PIN SELECT Peripheral Pin Select features are controlled through two sets of Special Function Registers: one to map peripheral inputs and one to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on if an input or an output is being mapped. 10.4.3.1 Input Mapping The inputs of the Peripheral Pin Select options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates which pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 10-1 through Register 10-21). Each register contains two sets of 6-bit fields, with each set associated with one of the pin-selectable peripherals. Programming a given peripheral’s bit field with an appropriate 6-bit value maps the RPn pin with that value to that peripheral. For any given device, the valid range of values for any of the bit fields corresponds to the maximum number of peripheral pin selections supported by the device. 10.4.3.2 Output Mapping In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Each register contains two 6-bit fields, with each field being associated with one RPn pin (see Register 10-22 through Register 10-37). The value of the bit field corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 10-3). Because of the mapping technique, the list of peripherals for output mapping also includes a null value of ‘000000’. This permits any given pin to remain disconnected from the output of any of the pin-selectable peripherals. DS39897C-page 136  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 10-2: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Function Name Register Function Mapping Bits External Interrupt 1 INT1 RPINR0 INT1R External Interrupt 2 INT2 RPINR1 INT2R External Interrupt 3 INT3 RPINR1 INT3R External Interrupt 4 INT4 RPINR2 INT4R Input Capture 1 IC1 RPINR7 IC1R Input Capture 2 IC2 RPINR7 IC2R Input Capture 3 IC3 RPINR8 IC3R Input Capture 4 IC4 RPINR8 IC4R Input Capture 5 IC5 RPINR9 IC5R Input Name Input Capture 6 IC6 RPINR9 IC6R Input Capture 7 IC7 RPINR10 IC7R Input Capture 8 IC8 RPINR10 IC8R Input Capture 9 IC9 RPINR15 IC9R Output Compare Fault A OCFA RPINR11 OCFAR Output Compare Fault B OCFB RPINR11 OCFBR SPI1 Clock Input SCK1IN RPINR20 SCK1R SPI1 Data Input SDI1 RPINR20 SDI1R SS1IN RPINR21 SS1R SCK2IN RPINR22 SCK2R SPI1 Slave Select Input SPI2 Clock Input SPI2 Data Input SDI2 RPINR22 SDI2R SS2IN RPINR23 SS2R SPI3 Clock Input SCK3IN RPINR23 SCK3R SPI3 Data Input SDI3 RPINR28 SDI3R SPI3 Slave Select Input SS3IN RPINR29 SS3R Timer2 External Clock T2CK RPINR3 T2CKR Timer3 External Clock T3CK RPINR3 T3CKR Timer4 External Clock T4CK RPINR4 T4CKR Timer5 External Clock T5CK RPINR4 T5CKR UART1 Clear To Send U1CTS RPINR18 U1CTSR U1RX RPINR18 U1RXR U2CTS RPINR19 U2CTSR U2RX RPINR19 U2RXR U3CTS RPINR21 U3CTSR SPI2 Slave Select Input UART1 Receive UART2 Clear To Send UART2 Receive UART3 Clear To Send UART3 Receive UART4 Clear To Send UART4 Receive Note 1: U3RX RPINR17 U3RXR U4CTS RPINR27 U4CTSR U4RX RPINR27 U4RXR Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.  2009 Microchip Technology Inc. DS39897C-page 137 PIC24FJ256GB110 FAMILY TABLE 10-3: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT) Output Function Number(1) Function 0 NULL(2) Null 1 C1OUT Comparator 1 Output 2 C2OUT Comparator 2 Output 3 U1TX UART1 Transmit 4 U1RTS 5 U2TX 6 Note 1: 2: 3: (3) U2RTS (3) Output Name UART1 Request To Send UART2 Transmit UART2 Request To Send 7 SDO1 SPI1 Data Output 8 SCK1OUT SPI1 Clock Output 9 SS1OUT SPI1 Slave Select Output 10 SDO2 SPI2 Data Output 11 SCK2OUT SPI2 Clock Output 12 SS2OUT SPI2 Slave Select Output 18 OC1 Output Compare 1 19 OC2 Output Compare 2 20 OC3 Output Compare 3 21 OC4 Output Compare 4 22 OC5 Output Compare 5 23 OC6 Output Compare 6 24 OC7 Output Compare 7 25 OC8 Output Compare 8 28 U3TX UART3 Transmit 29 U3RTS(3) UART3 Request To Send 30 U4TX UART4 Transmit (3) UART4 Request To Send 31 U4RTS 32 SDO3 33 SCK3OUT SPI3 Clock Output 34 SS3OUT SPI3 Slave Select Output SPI3 Data Output 35 OC9 Output Compare 9 36 C3OUT Comparator 3 Output 37-63 (unused) NC Setting the RPORx register with the listed value assigns that output function to the associated RPn pin. The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. IrDA® BCLK functionality uses this output. DS39897C-page 138  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 10.4.3.3 Mapping Limitations 10.4.4.1 The control schema of the Peripheral Pin Select is extremely flexible. Other than systematic blocks that prevent signal contention caused by two physical pins being configured as the same functional input, or two functional outputs configured as the same pin, there are no hardware enforced lockouts. The flexibility extends to the point of allowing a single input to drive multiple peripherals or a single functional output to drive multiple output pins. 10.4.3.4 Mapping Exceptions for PIC24FJ256GB110 Family Devices Although the PPS registers theoretically allow for up to 64 remappable I/O pins, not all of these are implemented in all devices. For PIC24FJ256GB110 family devices, the maximum number of remappable pins available are 44, which includes 12 input only pins. In addition, some pins in the RP and RPI sequences are unimplemented in lower pin count devices. The differences in available remappable pins are summarized in Table 10-4. When developing applications that use remappable pins, users should also keep these things in mind: • For the RPINRx registers, bit combinations corresponding to an unimplemented pin for a particular device are treated as invalid; the corresponding module will not have an input mapped to it. For all PIC24FJ256GB110 family devices, this includes all values greater than 43 (‘101011’). • For RPORx registers, the bit fields corresponding to an unimplemented pin will also be unimplemented. Writing to these fields will have no effect. 10.4.4 Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC24F devices include three features to prevent alterations to the peripheral map: • Control register lock sequence • Continuous state monitoring • Configuration bit remapping lock TABLE 10-4: Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear IOLOCK, a specific command sequence must be executed: 1. 2. 3. Write 46h to OSCCON. Write 57h to OSCCON. Clear (or set) IOLOCK as a single operation. Unlike the similar sequence with the oscillator’s LOCK bit, IOLOCK remains in one state until changed. This allows all of the Peripheral Pin Selects to be configured with a single unlock sequence, followed by an update to all control registers, then locked with a second lock sequence. 10.4.4.2 Continuous State Monitoring In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are constantly monitored in hardware by shadow registers. If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered. 10.4.4.3 CONTROLLING CONFIGURATION CHANGES Control Register Lock Configuration Bit Pin Select Lock As an additional level of safety, the device can be configured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (CW2) Configuration bit blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure will not execute and the Peripheral Pin Select Control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows users unlimited access (with the proper use of the unlock sequence) to the Peripheral Pin Select registers. REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ256GB110 FAMILY DEVICES Device Pin Count RP Pins (I/O) RPI Pins Total Unimplemented Total Unimplemented 64-pin 28 RP5, RP15, RP30, RP31 1 RPI32-36, RPI38-43 80-pin 31 RP31 9 RPI32, RPI39, RPI41 100-pin 32 — 12 —  2009 Microchip Technology Inc. DS39897C-page 139 PIC24FJ256GB110 FAMILY 10.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION The ability to control peripheral pin selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the Peripheral Pin Selects are not available on default pins in the device’s default (Reset) state. Since all RPINRx registers reset to ‘111111’ and all RPORx registers reset to ‘000000’, all Peripheral Pin Select inputs are tied to VSS, and all Peripheral Pin Select outputs are disconnected. Note: In tying Peripheral Pin Select inputs to RP63, RP63 does not have to exist on a device for the registers to be reset to it. This situation requires the user to initialize the device with the proper peripheral configuration before any other application code is executed. Since the IOLOCK bit resets in the unlocked state, it is not necessary to execute the unlock sequence after the device has come out of Reset. For application safety, however, it is best to set IOLOCK and lock the configuration after writing to the control registers. Because the unlock sequence is timing-critical, it must be executed as an assembly language routine in the same manner as changes to the oscillator configuration. If the bulk of the application is written in C or another high-level language, the unlock sequence should be performed by writing in-line assembly. Choosing the configuration requires the review of all Peripheral Pin Selects and their pin assignments, especially those that will not be used in the application. In all cases, unused pin-selectable peripherals should be disabled completely. Unused peripherals should have their inputs assigned to an unused RPn pin function. I/O pins with unused RPn functions should be configured with the null peripheral output. The assignment of a peripheral to a particular pin does not automatically perform any other configuration of the pin’s I/O circuitry. In theory, this means adding a pin-selectable output to a pin may mean inadvertently driving an existing peripheral input when the output is driven. Users must be familiar with the behavior of other fixed peripherals that share a remappable pin and know when to enable or disable them. To be safe, fixed digital peripherals that share the same pin should be disabled when not in use. DS39897C-page 140 Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that feature on. The peripheral must be specifically configured for operation and enabled, as if it were tied to a fixed pin. Where this happens in the application code (immediately following device Reset and peripheral configuration or inside the main application routine) depends on the peripheral and its use in the application. A final consideration is that Peripheral Pin Select functions neither override analog inputs, nor reconfigure pins with analog functions for digital I/O. If a pin is configured as an analog input on device Reset, it must be explicitly reconfigured as digital I/O when used with a Peripheral Pin Select. Example 10-2 shows a configuration for bidirectional communication with flow control using UART1. The following input and output functions are used: • Input Functions: U1RX, U1CTS • Output Functions: U1TX, U1RTS EXAMPLE 10-2: CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS // Unlock Registers __builtin_write_OSCCONL(OSCCON & 0xBF); // Configure Input Functions (Table 9-1)) // Assign U1RX To Pin RP0 RPINR18bits.U1RXR = 0; // Assign U1CTS To Pin RP1 RPINR18bits.U1CTSR = 1; // Configure Output Functions (Table 9-2) // Assign U1TX To Pin RP2 RPOR1bits.RP2R = 3; // Assign U1RTS To Pin RP3 RPOR1bits.RP3R = 4; // Lock Registers __builtin_write_OSCCONL(OSCCON | 0x40);  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 10.4.6 PERIPHERAL PIN SELECT REGISTERS Note: The PIC24FJ256GB110 family of devices implements a total of 37 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (21) • Output Remappable Peripheral Registers (16) REGISTER 10-1: Input and output register values can only be changed if IOLOCK (OSCCON) = 0. See Section 10.4.4.1 “Control Register Lock” for a specific command sequence. RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 INT1R: Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’ REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT3R5 INT3R4 INT3R3 INT3R2 INT3R1 INT3R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 INT3R: Assign External Interrupt 3 (INT3) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INT2R: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits  2009 Microchip Technology Inc. DS39897C-page 141 PIC24FJ256GB110 FAMILY REGISTER 10-3: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT4R5 INT4R4 INT4R3 INT4R2 INT4R1 INT4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 INT4R: Assign External Interrupt 4 (INT4) to Corresponding RPn or RPIn Pin bits REGISTER 10-4: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T3CKR5 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T2CKR5 T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 T3CKR: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 T2CKR: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits DS39897C-page 142  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 10-5: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T5CKR5 T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T4CKR5 T4CKR4 T4CKR3 T4CKR2 T4CKR1 T4CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 T5CKR: Assign Timer5 External Clock (T5CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 T4CKR: Assign Timer4 External Clock (T4CK) to Corresponding RPn or RPIn Pin bits REGISTER 10-6: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC2R: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC1R: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits  2009 Microchip Technology Inc. DS39897C-page 143 PIC24FJ256GB110 FAMILY REGISTER 10-7: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC4R5 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC3R5 IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC4R: Assign Input Capture 4 (IC4) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC3R: Assign Input Capture 3 (IC3) to Corresponding RPn or RPIn Pin bits REGISTER 10-8: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC6R5 IC6R4 IC6R3 IC6R2 IC6R1 IC6R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC5R5 IC5R4 IC5R3 IC5R2 IC5R1 IC5R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC6R: Assign Input Capture 6 (IC6) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC5R: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits DS39897C-page 144  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 10-9: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC8R5 IC8R4 IC8R3 IC8R2 IC8R1 IC8R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC7R5 IC7R4 IC7R3 IC7R2 IC7R1 IC7R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC8R: Assign Input Capture 8 (IC8) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC7R: Assign Input Capture 7 (IC7) to Corresponding RPn or RPIn Pin bits REGISTER 10-10: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — OCFBR5 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 OCFBR: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 OCFAR: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits  2009 Microchip Technology Inc. DS39897C-page 145 PIC24FJ256GB110 FAMILY REGISTER 10-11: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC9R5 IC9R4 IC9R3 IC9R2 IC9R1 IC9R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC9R: Assign Input Capture 9 (IC9) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’ REGISTER 10-12: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U3RXR5 U3RXR4 U3RXR3 U3RXR2 U3RXR1 U3RXR0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U3RXR: Assign UART3 Receive (U3RX) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’ DS39897C-page 146  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 10-13: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U1CTSR: Assign UART1 Clear to Send (U1CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U1RXR: Assign UART1 Receive (U1RX) to Corresponding RPn or RPIn Pin bits REGISTER 10-14: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U2RXR5 U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U2CTSR: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U2RXR: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits  2009 Microchip Technology Inc. DS39897C-page 147 PIC24FJ256GB110 FAMILY REGISTER 10-15: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK1R: Assign SPI1 Clock Input (SCK1IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI1R: Assign SPI1 Data Input (SDI1) to Corresponding RPn or RPIn Pin bits REGISTER 10-16: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U3CTSR: Assign UART3 Clear to Send (U3CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SS1R: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits DS39897C-page 148  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 10-17: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK2R: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI2R: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits REGISTER 10-18: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS2R5 SS2R4 SS2R3 SS2R2 SS2R1 SS2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS2R: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits  2009 Microchip Technology Inc. DS39897C-page 149 PIC24FJ256GB110 FAMILY REGISTER 10-19: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4RXR5 U4RXR4 U4RXR3 U4RXR2 U4RXR1 U4RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U4CTSR: Assign UART4 Clear to Send (U4CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U4RXR: Assign UART4 Receive (U4RX) to Corresponding RPn or RPIn Pin bits REGISTER 10-20: RPINR28: PERIPHERAL PIN SELECT INPUT REGISTER 28 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK3R5 SCK3R4 SCK3R3 SCK3R2 SCK3R1 SCK3R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI3R5 SDI3R4 SDI3R3 SDI3R2 SDI3R1 SDI3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK3R: Assign SPI3 Clock Input (SCK3IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI3R: Assign SPI3 Data Input (SDI3) to Corresponding RPn or RPIn Pin bits DS39897C-page 150  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 10-21: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS3R5 SS3R4 SS3R3 SS3R2 SS3R1 SS3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS3R: Assign SPI3 Slave Select Input (SS31IN) to Corresponding RPn or RPIn Pin bits REGISTER 10-22: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP1R: RP1 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP1 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP0R: RP0 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP0 (see Table 10-3 for peripheral function numbers)  2009 Microchip Technology Inc. DS39897C-page 151 PIC24FJ256GB110 FAMILY REGISTER 10-23: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP3R: RP3 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP3 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP2R: RP2 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP2 (see Table 10-3 for peripheral function numbers) REGISTER 10-24: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — RP5R5(1) RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP5R: RP5 Output Pin Mapping bits(1) Peripheral output number n is assigned to pin, RP5 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP4R: RP4 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP4 (see Table 10-3 for peripheral function numbers) Note 1: Unimplemented on 64-pin devices; read as ‘0’. DS39897C-page 152  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 10-25: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP7R: RP7 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP7 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP6R: RP6 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP6 (see Table 10-3 for peripheral function numbers) REGISTER 10-26: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP9R: RP9 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP9 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP8R: RP8 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP8 (see Table 10-3 for peripheral function numbers)  2009 Microchip Technology Inc. DS39897C-page 153 PIC24FJ256GB110 FAMILY REGISTER 10-27: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP11R: RP11 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP11 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP10R: RP10 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP10 (see Table 10-3 for peripheral function numbers) REGISTER 10-28: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP13R: RP13 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP13 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP12R: RP12 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP12 (see Table 10-3 for peripheral function numbers) DS39897C-page 154  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 10-29: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 — R/W-0 (1) — RP15R5 R/W-0 RP15R4 (1) R/W-0 RP15R3 (1) R/W-0 RP15R2 (1) R/W-0 RP15R1 R/W-0 (1) RP15R0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP15R: RP15 Output Pin Mapping bits(1) Peripheral output number n is assigned to pin, RP0 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP14R: RP14 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP14 (see Table 10-3 for peripheral function numbers) Note 1: Unimplemented on 64-pin devices; read as ‘0’. REGISTER 10-30: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP17R: RP17 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP17 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP16R: RP16 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP16 (see Table 10-3 for peripheral function numbers)  2009 Microchip Technology Inc. DS39897C-page 155 PIC24FJ256GB110 FAMILY REGISTER 10-31: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP19R5 RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP19R: RP19 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP19 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP18R: RP18 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP18 (see Table 10-3 for peripheral function numbers) REGISTER 10-32: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP21R: RP21 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP21 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP20R: RP20 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP20 (see Table 10-3 for peripheral function numbers) DS39897C-page 156  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 10-33: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP23R5 RP23R4 RP23R3 RP23R2 RP23R1 RP23R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP23R: RP23 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP23 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP22R: RP22 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP22 (see Table 10-3 for peripheral function numbers) REGISTER 10-34: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP25R: RP25 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP25 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP24R: RP24 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP24 (see Table 10-3 for peripheral function numbers)  2009 Microchip Technology Inc. DS39897C-page 157 PIC24FJ256GB110 FAMILY REGISTER 10-35: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP27R5 RP27R4 RP27R3 RP27R2 RP27R1 RP27R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP26R5 RP26R4 RP26R3 RP26R2 RP26R1 RP26R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP27R: RP27 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP27 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP26R: RP26 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP26 (see Table 10-3 for peripheral function numbers) REGISTER 10-36: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP29R: RP29 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP29 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP28R: RP28 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP28 (see Table 10-3 for peripheral function numbers) DS39897C-page 158  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 10-37: RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15 U-0 — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — RP31R5(1) RP31R4(1) RP31R3(1) RP31R2(1) RP31R1(1) RP31R0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP30R5 RP30R4 RP30R3 RP30R2 RP30R1 RP30R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP31R: RP31 Output Pin Mapping bits(1) Peripheral output number n is assigned to pin, RP31 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP30R: RP30 Output Pin Mapping bits(2) Peripheral output number n is assigned to pin, RP30 (see Table 10-3 for peripheral function numbers) Note 1: 2: Unimplemented on 64-pin and 80-pin devices; read as ‘0’. Unimplemented on 64-pin devices; read as ‘0’.  2009 Microchip Technology Inc. DS39897C-page 159 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 160  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 11.0 Note: TIMER1 Figure 11-1 presents a block diagram of the 16-bit timer module. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). To configure Timer1 for operation: 1. 2. 3. The Timer1 module is a 16-bit timer which can serve as the time counter for the Real-Time Clock (RTC), or operate as a free-running, interval timer/counter. Timer1 can operate in three modes: 4. 5. • 16-Bit Timer • 16-Bit Synchronous Counter • 16-Bit Asynchronous Counter 6. Set the TON bit (= 1). Select the timer prescaler ratio using the TCKPS bits. Set the Clock and Gating modes using the TCS and TGATE bits. Set or clear the TSYNC bit to configure synchronous or asynchronous operation. Load the timer period value into the PR1 register. If interrupts are required, set the interrupt enable bit, T1IE. Use the priority bits, T1IP, to set the interrupt priority. Timer1 also supports these features: • Timer Gate Operation • Selectable Prescaler Settings • Timer Operation during CPU Idle and Sleep modes • Interrupt on 16-Bit Period Register Match or Falling Edge of External Gate Signal FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM TCKPS SOSCO/ T1CK 1x SOSCEN SOSCI Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 TGATE TCS TGATE Set T1IF 2 TON 1 Q D 0 Q CK Reset 0 TMR1 1 Equal Comparator Sync TSYNC PR1  2009 Microchip Technology Inc. DS39897C-page 161 PIC24FJ256GB110 FAMILY REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER(1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = External clock from T1CK pin (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. DS39897C-page 162  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 12.0 Note: TIMER2/3 AND TIMER4/5 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as four independent, 16-bit timers with selectable operating modes. To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. 2. 3. 4. As 32-bit timers, Timer2/3 and Timer4/5 can each operate in three modes: Set the T32 bit (T2CON or T4CON = 1). Select the prescaler ratio for Timer2 or Timer4 using the TCKPS bits. Set the Clock and Gating modes using the TCS and TGATE bits. If TCS is set to external clock, RPINRx (TxCK) must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select” for more information. Load the timer period value. PR3 (or PR5) will contain the most significant word of the value while PR2 (or PR4) contains the least significant word. If interrupts are required, set the interrupt enable bit, T3IE or T5IE; use the priority bits, T3IP or T5IP, to set the interrupt priority. Note that while Timer2 or Timer4 controls the timer, the interrupt appears as a Timer3 or Timer5 interrupt. Set the TON bit (= 1). • Two independent 16-bit timers with all 16-bit operating modes (except Asynchronous Counter mode) • Single 32-bit timer • Single 32-bit synchronous counter 5. They also support these features: 6. • • • • • The timer value, at any point, is stored in the register pair, TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5) always contains the most significant word of the count, while TMR2 (TMR4) contains the least significant word. Timer Gate Operation Selectable Prescaler Settings Timer Operation during Idle and Sleep modes Interrupt on a 32-Bit Period Register Match ADC Event Trigger (Timer4/5 only) Individually, all four of the 16-bit timers can function as synchronous timers or counters. They also offer the features listed above, except for the ADC Event Trigger; this is implemented only with Timer3. The operating modes and enabled features are determined by setting the appropriate bit(s) in the T2CON, T3CON, T4CON and T5CON registers. T2CON and T4CON are shown in generic form in Register 12-1; T3CON and T5CON are shown in Register 12-2. For 32-bit timer/counter operation, Timer2 and Timer4 are the least significant word; Timer3 and Timer4 are the most significant word of the 32-bit timers. Note: For 32-bit operation, T3CON and T5CON control bits are ignored. Only T2CON and T4CON control bits are used for setup and control. Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags.  2009 Microchip Technology Inc. To configure any of the timers for individual 16-bit operation: 1. 2. 3. 4. 5. 6. Clear the T32 bit corresponding to that timer (T2CON for Timer2 and Timer3 or T4CON for Timer4 and Timer5). Select the timer prescaler ratio using the TCKPS bits. Set the Clock and Gating modes using the TCS and TGATE bits. See Section 10.4 “Peripheral Pin Select” for more information. Load the timer period value into the PRx register. If interrupts are required, set the interrupt enable bit, TxIE; use the priority bits, TxIP, to set the interrupt priority. Set the TON bit (TxCON = 1). DS39897C-page 163 PIC24FJ256GB110 FAMILY FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM TCKPS 2 TON T2CK (T4CK) 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 TGATE(2) TGATE TCS(2) Q 1 Set T3IF (T5IF) Q 0 PR3 (PR5) ADC Event Trigger(3) Equal D CK PR2 (PR4) Comparator MSB LSB TMR3 (TMR5) Reset TMR2 (TMR4) Sync 16 Read TMR2 (TMR4) (1) Write TMR2 (TMR4)(1) 16 TMR3HLD (TMR5HLD) 16 Data Bus Note 1: 2: 3: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers. The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select” for more information. The ADC Event Trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode. DS39897C-page 164  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY FIGURE 12-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TON T2CK (T4CK) TCKPS 2 1x Gate Sync Prescaler 1, 8, 64, 256 01 00 TGATE TCS(1) TCY 1 Set T2IF (T4IF) 0 Reset Equal Q D Q CK TMR2 (TMR4) TGATE(1) Sync Comparator PR2 (PR4) Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select” for more information. FIGURE 12-3: TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM T3CK (T5CK) Sync 1x TON TCKPS 2 Prescaler 1, 8, 64, 256 01 00 TGATE TCY 1 Set T3IF (T5IF) 0 Reset ADC Event Trigger(2) Equal Q D Q CK TCS(1) TGATE(1) TMR3 (TMR5) Comparator PR3 (PR5) Note 1: 2: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select” for more information. The ADC Event Trigger is available only on Timer3.  2009 Microchip Technology Inc. DS39897C-page 165 PIC24FJ256GB110 FAMILY REGISTER 12-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32(1) — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timerx On bit When TxCON = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When TxCON = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS: Timerx Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 T32: 32-Bit Timer Mode Select bit(1) 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit(2) 1 = External clock from pin, TxCK (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: 2: 3: x = Bit is unknown In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation. If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. For more information, see Section 10.4 “Peripheral Pin Select”. Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. DS39897C-page 166  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 12-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1,2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit(1) 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS: Timery Input Clock Prescale Select bits(1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timery Clock Source Select bit(1,2) 1 = External clock from pin TyCK (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: 2: 3: x = Bit is unknown When 32-bit operation is enabled (T2CON or T4CON = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON and T4CON. If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select” for more information. Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended.  2009 Microchip Technology Inc. DS39897C-page 167 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 168  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 13.0 INPUT CAPTURE WITH DEDICATED TIMERS Note: 13.1 13.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 34. “Input Capture with Dedicated Timer” (DS39722). Devices in the PIC24FJ256GB110 family all feature 9 independent input capture modules. Each of the modules offers a wide range of configuration and operating options for capturing external pulse events and generating interrupts. Key features of the input capture module include: • Hardware-configurable for 32-bit operation in all modes by cascading two adjacent modules • Synchronous and Trigger modes of output compare operation, with up to 30 user-selectable trigger/sync sources available • A 4-level FIFO buffer for capturing and holding timer values for several events • Configurable interrupt generation • Up to 6 clock sources available for each module, driving a separate internal 16-bit counter The module is controlled through two registers, ICxCON1 (Register 13-1) and ICxCON2 (Register 13-2). A general block diagram of the module is shown in Figure 13-1. FIGURE 13-1: SYNCHRONOUS AND TRIGGER MODES By default, the input capture module operates in a free-running mode. The internal 16-bit counter, ICxTMR, counts up continuously, wrapping around from FFFFh to 0000h on each overflow, with its period synchronized to the selected external clock source. When a capture event occurs, the current 16-bit value of the internal counter is written to the FIFO buffer. In Synchronous mode, the module begins capturing events on the ICx pin as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the internal counter is reset. In Trigger mode, the module waits for a Sync event from another internal module to occur before allowing the internal counter to run. Standard, free-running operation is selected by setting the SYNCSEL bits to ‘00000’, and clearing the ICTRIG bit (ICxCON2). Synchronous and Trigger modes are selected any time the SYNCSEL bits are set to any value except ‘00000’. The ICTRIG bit selects either Synchronous or Trigger mode; setting the bit selects Trigger mode operation. In both modes, the SYNCSEL bits determine the sync/trigger source. When the SYNCSEL bits are set to ‘00000’ and ICTRIG is set, the module operates in Software Trigger mode. In this case, capture operations are started by manually setting the TRIGSTAT bit (ICxCON2). INPUT CAPTURE BLOCK DIAGRAM ICM ICx Pin(1) General Operating Modes Prescaler Counter 1:1/4/16 ICI Event and Interrupt Logic Edge Detect Logic and Clock Synchronizer Set ICxIF ICTSEL IC Clock Sources Clock Select Trigger and Sync Logic Trigger and Sync Sources Increment 16 ICxTMR 4-Level FIFO Buffer 16 Reset ICxBUF SYNCSEL TRIGGER ICOV, ICBNE Note 1: 16 System Bus The ICx inputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select” for more information.  2009 Microchip Technology Inc. DS39897C-page 169 PIC24FJ256GB110 FAMILY 13.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) The odd numbered module (ICx) provides the Least Significant 16 bits of the 32-bit register pairs, and the even module (ICy) provides the Most Significant 16 bits. Wraparounds of the ICx registers cause an increment of their corresponding ICy registers. Cascaded operation is configured in hardware by setting the IC32 bits (ICxCON2) for both modules. 13.2 For 32-bit cascaded operations, the setup procedure is slightly different: 1. 2. 3. Capture Operations The input capture module can be configured to capture timer values and generate interrupts on rising edges on ICx, or all transitions on ICx. Captures can be configured to occur on all rising edges, or just some (every 4th or 16th). Interrupts can be independently configured to generate on each event, or a subset of events. 4. 5. Note: To set up the module for capture operations: 1. 2. 3. 4. 5. 6. 7. 8. 9. Configure the ICx input for one of the available Peripheral Pin Select pins. If Synchronous mode is to be used, disable the sync source before proceeding. Make sure that any previous data has been removed from the FIFO by reading ICxBUF until the ICBNE bit (ICxCON1) is cleared. Set the SYNCSEL bits (ICxCON2) to the desired sync/trigger source. Set the ICTSEL bits (ICxCON1) for the desired clock source. Set the ICI bits (ICxCON1) to the desired interrupt frequency Select Synchronous or Trigger mode operation: a) Check that the SYNCSEL bits are not set to ‘00000’. b) For Synchronous mode, clear the ICTRIG bit (ICxCON2). c) For Trigger mode, set ICTRIG, and clear the TRIGSTAT bit (ICxCON2). Set the ICM bits (ICxCON1) to the desired operational mode. Enable the selected trigger/sync source. DS39897C-page 170 Set the IC32 bits for both modules (ICyCON2 and (ICxCON2), enabling the even numbered module first. This ensures the modules will start functioning in unison. Set the ICTSEL and SYNCSEL bits for both modules to select the same sync/trigger and time base source. Set the even module first, then the odd module. Both modules must use the same ICTSEL and SYNCSEL settings. Clear the ICTRIG bit of the even module (ICyCON2); this forces the module to run in Synchronous mode with the odd module, regardless of its trigger setting. Use the odd module’s ICI bits (ICxCON1) to the desired interrupt frequency. Use the ICTRIG bit of the odd module (ICxCON2) to configure Trigger or Synchronous mode operation. 6. For Synchronous mode operation, enable the sync source as the last step. Both input capture modules are held in Reset until the sync source is enabled. Use the ICM bits of the odd module (ICxCON1) to set the desired capture mode. The module is ready to capture events when the time base and the trigger/sync source are enabled. When the ICBNE bit (ICxCON1) becomes set, at least one capture value is available in the FIFO. Read input capture values from the FIFO until the ICBNE clears to ‘0’. For 32-bit operation, read both the ICxBUF and ICyBUF for the full 32-bit timer value (ICxBUF for the lsw, ICyBUF for the msw). At least one capture value is available in the FIFO buffer when the odd module’s ICBNE bit (ICxCON1) becomes set. Continue to read the buffer registers until ICBNE is cleared (perform automatically by hardware).  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 13-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — bit 15 bit 8 U-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0 — ICI1 ICI0 ICOV ICBNE ICM2(1) ICM1(1) ICM0(1) bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture x Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode bit 12-10 ICTSEL: Input Capture Timer Select bits 111 = System clock (FOSC/2) 110 = Reserved 101 = Reserved 100 = Timer1 011 = Timer5 010 = Timer4 001 = Timer2 000 = Timer3 bit 9-7 Unimplemented: Read as ‘0’ bit 6-5 ICI: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture x Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM: Input Capture Mode Select bits(1) 111 = Interrupt mode: input capture functions as interrupt pin only when device is in Sleep or Idle mode (rising edge detect only, all other control bits are not applicable) 110 = Unused (module disabled) 101 = Prescaler Capture mode: capture on every 16th rising edge 100 = Prescaler Capture mode: capture on every 4th rising edge 011 = Simple Capture mode: capture on every rising edge 010 = Simple Capture mode: capture on every falling edge 001 = Edge Detect Capture mode: capture on every edge (rising and falling), ICI bits do not control interrupt generation for this mode 000 = Input capture module turned off Note 1: The ICx input must also be configured to an available RPn pin. For more information, see Section 10.4 “Peripheral Pin Select”.  2009 Microchip Technology Inc. DS39897C-page 171 PIC24FJ256GB110 FAMILY REGISTER 13-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IC32 bit 15 bit 8 R/W-0 R/W-0 HS U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 IC32: Cascade Two IC Modules Enable bit (32-bit operation) 1 = ICx and ICy operate in cascade as a 32-bit module (this bit must be set in both modules) 0 = ICx functions independently as a 16-bit module bit 7 ICTRIG: ICx Trigger/Sync Select bit 1 = Trigger ICx from source designated by SYNCSELx bits 0 = Synchronize ICx with source designated by SYNCSELx bits bit 6 TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running (set in hardware, can be set in software) 0 = Timer source has not been triggered and is being held clear bit 5 Unimplemented: Read as ‘0’ bit 4-0 SYNCSEL: Trigger/Synchronization Source Selection bits 11111 = Reserved 11110 = Input Capture 9 11101 = Input Capture 6 11100 = CTMU(1) 11011 = A/D(1) 11010 = Comparator 3(1) 11001 = Comparator 2(1) 11000 = Comparator 1(1) 10111 = Input Capture 4 10110 = Input Capture 3 10101 = Input Capture 2 10100 = Input Capture 1 10011 = Input Capture 8 10010 = Input Capture 7 1000x = reserved 01111 = Timer5 01110 = Timer4 01101 = Timer3 01100 = Timer2 01011 = Timer1 01010 = Input Capture 5 01001 = Output Compare 9 01000 = Output Compare 8 00111 = Output Compare 7 00110 = Output Compare 6 00101 = Output Compare 5 00100 = Output Compare 4 00011 = Output Compare 3 00010 = Output Compare 2 00001 = Output Compare 1 00000 = Not synchronized to any other module Note 1: Use these inputs as trigger sources only and never as sync sources. DS39897C-page 172  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 14.0 Note: OUTPUT COMPARE WITH DEDICATED TIMERS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 35. “Output Compare with Dedicated Timers” (DS39723). Devices in the PIC24FJ256GB110 family all feature 9 independent output compare modules. Each of these modules offers a wide range of configuration and operating options for generating pulse trains on internal device events, and can produce pulse-width modulated waveforms for driving power applications. Key features of the output compare module include: • Hardware-configurable for 32-bit operation in all modes by cascading two adjacent modules • Synchronous and Trigger modes of output compare operation, with up to 30 user-selectable trigger/sync sources available • Two separate period registers (a main register, OCxR, and a secondary register, OCxRS) for greater flexibility in generating pulses of varying widths • Configurable for single-pulse or continuous pulse generation on an output event, or continuous PWM waveform generation • Up to 6 clock sources available for each module, driving a separate internal 16-bit counter 14.1 14.1.1 In Synchronous mode, the module begins performing its compare or PWM operation as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the module’s internal counter is reset. In Trigger mode, the module waits for a sync event from another internal module to occur before allowing the counter to run. Free-running mode is selected by default, or any time that the SYNCSEL bits (OCxCON2) are set to ‘00000’. Synchronous or Trigger modes are selected any time the SYNCSEL bits are set to any value except ‘00000’. The OCTRIG bit (OCxCON2) selects either Synchronous or Trigger mode; setting the bit selects Trigger mode operation. In both modes, the SYNCSEL bits determine the sync/trigger source. 14.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own set of 16-bit timer and duty cycle registers. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) The odd numbered module (OCx) provides the Least Significant 16 bits of the 32-bit register pairs, and the even module (OCy) provides the Most Significant 16 bits. Wraparounds of the OCx registers cause an increment of their corresponding OCy registers. Cascaded operation is configured in hardware by setting the OC32 bits (OCxCON2) for both modules. General Operating Modes SYNCHRONOUS AND TRIGGER MODES By default, the output compare module operates in a free-running mode. The internal 16-bit counter, OCxTMR, runs counts up continuously, wrapping around from FFFFh to 0000h on each overflow, with its period synchronized to the selected external clock source. Compare or PWM events are generated each time a match between the internal counter and one of the period registers occurs.  2009 Microchip Technology Inc. DS39897C-page 173 PIC24FJ256GB110 FAMILY 14.2 Compare Operations 3. In Compare mode (Figure 14-1), the output compare module can be configured for single-shot or continuous pulse generation; it can also repeatedly toggle an output pin on each timer event. To set up the module for compare operations: 1. 2. Configure the OCx output for one of the available Peripheral Pin Select pins. Calculate the required values for the OCxR and (for Double Compare modes) OCxRS duty cycle registers: a) Determine the instruction clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. b) Calculate time to the rising edge of the output pulse relative to the timer start value (0000h). c) Calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. FIGURE 14-1: 4. 5. 6. 7. 8. Write the rising edge value to OCxR, and the falling edge value to OCxRS. Set the Timer Period register, PRy, to a value equal to or greater than the value in OCxRS. Set the OCM bits for the appropriate compare operation (= 0xx). For Trigger mode operations, set OCTRIG to enable Trigger mode. Set or clear TRIGMODE to configure trigger operation, and TRIGSTAT to select a hardware or software trigger. For Synchronous mode, clear OCTRIG. Set the SYNCSEL bits to configure the trigger or synchronization source. If free-running timer operation is required, set the SYNCSEL bits to ‘00000’ (no sync/trigger source). Select the time base source with the OCTSEL bits. If necessary, set the TON bit for the selected timer which enables the compare time base to count. Synchronous mode operation starts as soon as the time base is enabled; Trigger mode operation starts after a trigger source event occurs. OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE) OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0 OCxCON1 OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG Clock Select OC Clock Sources OCxCON2 OCxR Increment Comparator OC Output and Fault Logic OCxTMR Reset Match Event Trigger and Sync Sources Trigger and Sync Logic Comparator OCx Pin(1) Match Event Match Event OCFA/OCFB OCxRS Reset OCx Interrupt Note 1: The OCx outputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select” for more information. DS39897C-page 174  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY For 32-bit cascaded operation, these steps are also necessary: 1. 2. 3. 4. 5. 6. Set the OC32 bits for both registers (OCyCON2 and (OCxCON2). Enable the even numbered module first to ensure the modules will start functioning in unison. Clear the OCTRIG bit of the even module (OCyCON2), so the module will run in Synchronous mode. Configure the desired output and Fault settings for OCy. Force the output pin for OCx to the output state by clearing the OCTRIS bit. If Trigger mode operation is required, configure the trigger options in OCx by using the OCTRIG (OCxCON2), TRIGSTAT (OCxCON2), and SYNCSEL (OCxCON2) bits. Configure the desired compare or PWM mode of operation (OCM) for OCy first, then for OCx. Depending on the output mode selected, the module holds the OCx pin in its default state, and forces a transition to the opposite state when OCxR matches the timer. In Double Compare modes, OCx is forced back to its default state when a match with OCxRS occurs. The OCxIF interrupt flag is set after an OCxR match in Single Compare modes, and after each OCxRS match in Double Compare modes. Single-shot pulse events only occur once, but may be repeated by simply rewriting the value of the OCxCON1 register. Continuous pulse events continue indefinitely until terminated.  2009 Microchip Technology Inc. 14.3 Pulse-Width Modulation (PWM) Mode In PWM mode, the output compare module can be configured for edge-aligned or center-aligned pulse waveform generation. All PWM operations are double-buffered (buffer registers are internal to the module and are not mapped into SFR space). To configure the output compare module for PWM operation: 1. 2. 3. 4. 5. 6. 7. 8. Configure the OCx output for one of the available Peripheral Pin Select pins. Calculate the desired duty cycles and load them into the OCxR register. Calculate the desired period and load it into the OCxRS register. Select the current OCx as the sync source by writing 0x1F to SYNCSEL (OCxCON2), and clearing OCTRIG (OCxCON2). Select a clock source by writing the OCTSEL (OCxCON) bits. Enable interrupts, if required, for the timer and output compare modules. The output compare interrupt is required for PWM Fault pin utilization. Select the desired PWM mode in the OCM (OCxCON1) bits. If a timer is selected as a clock source, set the TMRy prescale value and enable the time base by setting the TON (TxCON) bit. Note: This peripheral contains input and output functions that may need to be configured by the Peripheral Pin Select. See Section 10.4 “Peripheral Pin Select” for more information. DS39897C-page 175 PIC24FJ256GB110 FAMILY FIGURE 14-2: OUTPUT COMPARE BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE) OCxCON1 OCxCON2 OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG OCxR Rollover/Reset OCxR buffer OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0 OCx Pin Clock Select OC Clock Sources Increment Comparator OCxTMR Reset Trigger and Sync Logic Trigger and Sync Sources Match Event Comparator Match Event Rollover OC Output and Fault Logic OCFA/OCFB Match Event OCxRS buffer Rollover/Reset OCxRS OCx Interrupt Reset Note 1: 14.3.1 The OCx outputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select” for more information. PWM PERIOD The PWM period is specified by writing to PRy, the Timer Period register. The PWM period can be calculated using Equation 14-1. EQUATION 14-1: CALCULATING THE PWM PERIOD(1) PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value) where: PWM Frequency = 1/[PWM Period] Note 1: Note: Based on TCY = TOSC * 2, Doze mode and PLL are disabled. A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of 7 written into the PRy register will yield a period consisting of 8 time base cycles. DS39897C-page 176 14.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The OCxRS and OCxR registers can be written to at any time, but the duty cycle value is not latched until a match between PRy and TMRy occurs (i.e., the period is complete). This provides a double buffer for the PWM duty cycle and is essential for glitchless PWM operation. Some important boundary parameters of the PWM duty cycle include: • If OCxR, OCxRS, and PRy are all loaded with 0000h, the OCx pin will remain low (0% duty cycle). • ·If OCxRS is greater than PRy, the pin will remain high (100% duty cycle). See Example 14-1 for PWM mode timing details. Table 14-1 and Table 14-2 show example PWM frequencies and resolutions for a device operating at 4 MIPS and 10 MIPS, respectively.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY CALCULATION FOR MAXIMUM PWM RESOLUTION(1) EQUATION 14-2: log10 Maximum PWM Resolution (bits) = (F PWM ) FCY • (Timer Prescale Value) bits log10(2) Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled. EXAMPLE 14-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS(1) 1. Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1. TCY = 2 * TOSC = 62.5 ns PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s PWM Period = (PR2 + 1) • TCY • (Timer 2 Prescale Value) 19.2 s = (PR2 + 1) • 62.5 ns • 1 PR2 = 306 2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate: PWM Resolution = log10 (FCY/FPWM)/log102) bits = (log10 (16 MHz/52.08 kHz)/log102) bits = 8.3 bits Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. TABLE 14-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1) PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh 16 16 15 12 10 7 5 Resolution (bits) Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled. TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1) PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh 16 16 15 12 10 7 5 Resolution (bits) Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.  2009 Microchip Technology Inc. DS39897C-page 177 PIC24FJ256GB110 FAMILY REGISTER 14-1: U-0 — bit 15 U-0 — R/W-0 Legend: R = Readable bit -n = Value at POR bit 12-10 bit 9-8 bit 7 bit 6-5 bit 4 bit 3 bit 2-0 Note 1: 2: R/W-0 OCSIDL R/W-0 OCTSEL2 R/W-0 OCTSEL1 R/W-0 OCTSEL0 U-0 — U-0 — bit 8 ENFLT0 bit 7 bit 15-14 bit 13 OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 U-0 R/W-0, HCS — — OCFLT0 W = Writable bit ‘1’ = Bit is set R/W-0 TRIGMODE R/W-0 OCM2(1) R/W-0 OCM1(1) R/W-0 OCM0(1) bit 0 HCS = Hardware Clearable/Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ OCSIDL: Stop Output Compare x in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode OCTSEL: Output Compare x Timer Select bits 111 = System Clock 110 = Reserved 101 = Reserved 100 = Timer1 011 = Timer5 010 = Timer4 001 = Timer3 000 = Timer2 Unimplemented: Read as ‘0’ ENFLT0: Fault 0 Input Enable bit 1 = Fault 0 input is enabled 0 = Fault 0 input is disabled Unimplemented: Read as ‘0’ OCFLT0: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in HW only) 0 = No PWM Fault condition has occurred (this bit is only used when OCM = 111) TRIGMODE: Trigger Status Mode Select bit 1 = TRIGSTAT (OCxCON2) is cleared when OCxRS = OCxTMR or in software 0 = TRIGSTAT is only cleared by software OCM: Output Compare x Mode Select bits(1) 111 = Center-aligned PWM mode on OCx(2) 110 = Edge-aligned PWM Mode on OCx(2) 101 = Double Compare Continuous Pulse mode: Initialize OCx pin low, toggle OCx state continuously on alternate matches of OCxR and OCxRS 100 = Double Compare Single-Shot mode: Initialize OCx pin low, toggle OCx state on matches of OCxR and OCxRS for one cycle 011 = Single Compare Continuous Pulse mode: Compare events continuously toggle OCx pin 010 = Single Compare Single-Shot mode: Initialize OCx pin high, compare event forces OCx pin low 001 = Single Compare Single-Shot mode: Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled The OCx output must also be configured to an available RPn pin. For more information, see Section 10.4 “Peripheral Pin Select”. OCFA pin controls the OC1-OC4 channels; OCFB pin controls the OC5-OC9 channels. OCxR and OCxRS are double-buffered only in PWM modes. DS39897C-page 178  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 14-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 bit 15 bit 8 R/W-0 R/W-0 HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTMD: Fault Mode Select bit 1 = Fault mode is maintained until the Fault source is removed and the corresponding OCFLT0 bit is cleared in software 0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts bit 14 FLTOUT: Fault Out bit 1 = PWM output is driven high on a Fault 0 = PWM output is driven low on a Fault bit 13 FLTTRIEN: Fault Output State Select bit 1 = Pin is forced to an output on a Fault condition 0 = Pin I/O condition is unaffected by a Fault bit 12 OCINV: OCMP Invert bit 1 = OCx output is inverted 0 = OCx output is not inverted bit 11-9 Unimplemented: Read as ‘0’ bit 8 OC32: Cascade Two OC Modules Enable bit (32-bit operation) 1 = Cascade module operation enabled 0 = Cascade module operation disabled bit 7 OCTRIG: OCx Trigger/Sync Select bit 1 = Trigger OCx from source designated by the SYNCSELx bits 0 = Synchronize OCx with source designated by the SYNCSELx bits bit 6 TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running 0 = Timer source has not been triggered and is being held clear bit 5 OCTRIS: OCx Output Pin Direction Select bit 1 = OCx pin is tristated 0 = Output compare peripheral x connected to OCx pin Note 1: 2: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. Use these inputs as trigger sources only and never as sync sources.  2009 Microchip Technology Inc. DS39897C-page 179 PIC24FJ256GB110 FAMILY REGISTER 14-2: bit 4-0 OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 SYNCSEL: Trigger/Synchronization Source Selection bits 11111 = This OC module(1) 11110 = Input Capture 9(2) 11101 = Input Capture 6(2) 11100 = CTMU(2) 11011 = A/D(2) 11010 = Comparator 3(2) 11001 = Comparator 2(2) 11000 = Comparator 1(2) 10111 = Input Capture 4(2) 10110 = Input Capture 3(2) 10101 = Input Capture 2(2) 10100 = Input Capture 1(2) 10011 = Input Capture 8(2) 10010 = Input Capture 7(2) 1000x = reserved 01111 = Timer 5 01110 = Timer 4 01101 = Timer 3 01100 = Timer 2 01011 = Timer 1 01010 = Input Capture 5(2) 01001 = Output Compare 9(1) 01000 = Output Compare 8(1) 00111 = Output Compare 7(1) 00110 = Output Compare 6(1) 00101 = Output Compare 5(1) 00100 = Output Compare 4(1) 00011 = Output Compare 3(1) 00010 = Output Compare 2(1) 00001 = Output Compare 1(1) 00000 = Not synchronized to any other module Note 1: 2: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. Use these inputs as trigger sources only and never as sync sources. DS39897C-page 180  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 15.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 23. “Serial Peripheral Interface (SPI)” (DS39699). The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc. The SPI module is compatible with Motorola’s SPI and SIOP interfaces. All devices of the PIC24FJ256GB110 family include three SPI modules The module supports operation in two buffer modes. In Standard mode, data is shifted through a single serial buffer. In Enhanced Buffer mode, data is shifted through an 8-level FIFO buffer. Note: The SPI serial interface consists of four pins: • • • • SDIx: Serial Data Input SDOx: Serial Data Output SCKx: Shift Clock Input or Output SSx: Active-Low Slave Select or Frame Synchronization I/O Pulse The SPI module can be configured to operate using 2, 3 or 4 pins. In the 3-pin mode, SSx is not used. In the 2-pin mode, both SDOx and SSx are not used. Block diagrams of the module in Standard and Enhanced modes are shown in Figure 15-1 and Figure 15-2. Note: In this section, the SPI modules are referred to together as SPIx or separately as SPI1, SPI2 or SPI3. Special Function Registers will follow a similar notation. For example, SPIxCON1 and SPIxCON2 refer to the control registers for any of the 3 SPI modules. Do not perform read-modify-write operations (such as bit-oriented instructions) on the SPIxBUF register in either Standard or Enhanced Buffer mode. The module also supports a basic framed SPI protocol while operating in either Master or Slave mode. A total of four framed SPI configurations are supported.  2009 Microchip Technology Inc. DS39897C-page 181 PIC24FJ256GB110 FAMILY To set up the SPI module for the Standard Master mode of operation: To set up the SPI module for the Standard Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1) = 1. Clear the SPIROV bit (SPIxSTAT). Enable SPI operation by setting the SPIEN bit (SPIxSTAT). Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will start as soon as data is written to the SPIxBUF register. FIGURE 15-1: Clear the SPIxBUF register. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1) = 0. Clear the SMP bit. If the CKE bit (SPIxCON1) is set, then the SSEN bit (SPIxCON1) must be set to enable the SSx pin. Clear the SPIROV bit (SPIxSTAT). Enable SPI operation by setting the SPIEN bit (SPIxSTAT). 3. 4. 5. 6. 7. SPIx MODULE BLOCK DIAGRAM (STANDARD MODE) SCKx 1:1 to 1:8 Secondary Prescaler SSx/FSYNCx Sync Control 1:1/4/16/64 Primary Prescaler Select Edge Control Clock SPIxCON1 SPIxCON1 Shift Control SDOx Enable Master Clock bit 0 SDIx FCY SPIxSR Transfer Transfer SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus DS39897C-page 182  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY To set up the SPI module for the Enhanced Buffer Master mode of operation: To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. 6. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1) = 1. Clear the SPIROV bit (SPIxSTAT). Select Enhanced Buffer mode by setting the SPIBEN bit (SPIxCON2). Enable SPI operation by setting the SPIEN bit (SPIxSTAT). Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will start as soon as data is written to the SPIxBUF register. FIGURE 15-2: 3. 4. 5. 6. 7. 8. Clear the SPIxBUF register. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1) = 0. Clear the SMP bit. If the CKE bit is set, then the SSEN bit must be set, thus enabling the SSx pin. Clear the SPIROV bit (SPIxSTAT). Select Enhanced Buffer mode by setting the SPIBEN bit (SPIxCON2). Enable SPI operation by setting the SPIEN bit (SPIxSTAT). SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE) SCKx 1:1 to 1:8 Secondary Prescaler SSx/FSYNCx Sync Control 1:1/4/16/64 Primary Prescaler Select Edge Control Clock SPIxCON1 SPIxCON1 Shift Control SDOx Enable Master Clock bit0 SDIx FCY SPIxSR Transfer Transfer 8-Level FIFO Receive Buffer 8-Level FIFO Transmit Buffer SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus  2009 Microchip Technology Inc. DS39897C-page 183 PIC24FJ256GB110 FAMILY REGISTER 15-1: R/W-0 SPIEN (1) SPIxSTAT: SPIx STATUS AND CONTROL REGISTER U-0 R/W-0 U-0 U-0 R-0 R-0 R-0 — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 bit 15 bit 8 R-0 R/C-0 HS R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit(1) 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 Unimplemented: Read as ‘0’ bit 10-8 SPIBEC: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode) Master mode: Number of SPI transfers pending. Slave mode: Number of SPI transfers unread. bit 7 SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode) 1 = SPIx Shift register is empty and ready to send or receive 0 = SPIx Shift register is not empty bit 6 SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred bit 5 SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode) 1 = Receive FIFO is empty 0 = Receive FIFO is not empty bit 4-2 SISEL: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode) 111 = Interrupt when SPIx transmit buffer is full (SPITBF bit is set) 110 = Interrupt when last bit is shifted into SPIxSR, as a result, the TX FIFO is empty 101 = Interrupt when the last bit is shifted out of SPIxSR, now the transmit is complete 100 = Interrupt when one data is shifted into the SPIxSR, as a result, the TX FIFO has one open spot 011 = Interrupt when SPIx receive buffer is full (SPIRBF bit set) 010 = Interrupt when SPIx receive buffer is 3/4 or more full 001 = Interrupt when data is available in receive buffer (SRMPT bit is set) 000 = Interrupt when the last data in the receive buffer is read, as a result, the buffer is empty (SRXMPT bit set) Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4 “Peripheral Pin Select” for more information. DS39897C-page 184  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty In Standard Buffer mode: Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR. In Enhanced Buffer mode: Automatically set in hardware when CPU writes SPIxBUF location, loading the last available buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty In Standard Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. In Enhanced Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4 “Peripheral Pin Select” for more information.  2009 Microchip Technology Inc. DS39897C-page 185 PIC24FJ256GB110 FAMILY REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK(1) DISSDO(2) MODE16 SMP CKE(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 (4) SSEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only)(1) 1 = Internal SPI clock is disabled; pin functions as I/O 0 = Internal SPI clock is enabled bit 11 DISSDO: Disable SDOx pin bit(2) 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. bit 8 CKE: SPIx Clock Edge Select bit(3) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) bit 7 SSEN: Slave Select Enable (Slave mode) bit(4) 1 = SSx pin used for Slave mode 0 = SSx pin not used by module; pin controlled by port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: 2: 3: 4: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select” for more information. If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select” for more information. The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). If SSEN = 1, SSx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select” for more information. DS39897C-page 186  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 ... 000 = Secondary prescale 8:1 bit 1-0 PPRE: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: 4: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select” for more information. If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select” for more information. The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). If SSEN = 1, SSx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select” for more information. REGISTER 15-3: R/W-0 SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 FRMEN SPIFSD R/W-0 U-0 U-0 U-0 U-0 U-0 SPIFPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — SPIFE SPIBEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled 0 = Framed SPIx support disabled bit 14 SPIFSD: Frame Sync Pulse Direction Control on SSx pin bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) bit 13 SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only) 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low bit 12-2 Unimplemented: Read as ‘0’ bit 1 SPIFE: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode)  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 187 PIC24FJ256GB110 FAMILY FIGURE 15-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) PROCESSOR 1 (SPI Master) PROCESSOR 2 (SPI Slave) SDIx SDOx Serial Receive Buffer (SPIxRXB) Serial Receive Buffer (SPIxRXB) SDOx SDIx Shift Register (SPIxSR) LSb MSb MSb Serial Transmit Buffer (SPIxTXB) SPIx Buffer (SPIxBUF)(2) Shift Register (SPIxSR) LSb Serial Transmit Buffer (SPIxTXB) SCKx Serial Clock SCKx SPIx Buffer (SPIxBUF)(2) SSx(1) SSEN (SPIxCON1) = 1 and MSTEN (SPIxCON1) = 0 MSTEN (SPIxCON1) = 1) Note 1: 2: FIGURE 15-4: Using the SSx pin in Slave mode of operation is optional. User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES) PROCESSOR 1 (SPI Enhanced Buffer Master) Shift Register (SPIxSR) PROCESSOR 2 (SPI Enhanced Buffer Slave) SDOx SDIx SDIx SDOx LSb MSb MSb 8-Level FIFO Buffer SPIx Buffer (SPIxBUF)(2) Note 1: 2: LSb 8-Level FIFO Buffer SCKx SSx(1) MSTEN (SPIxCON1) = 1 and SPIBEN (SPIxCON2) = 1 Shift Register (SPIxSR) Serial Clock SCKx SPIx Buffer (SPIxBUF)(2) SSx(1) SSEN (SPIxCON1) = 1, MSTEN (SPIxCON1) = 0 and SPIBEN (SPIxCON2) = 1 Using the SSx pin in Slave mode of operation is optional. User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. DS39897C-page 188  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY FIGURE 15-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM PROCESSOR 2 PIC24F (SPI Master, Frame Master) SDIx SDOx SDOx SDIx SCKx SSx FIGURE 15-6: Serial Clock Frame Sync Pulse SCKx SSx SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM PROCESSOR 2 PIC24F (SPI Master, Frame Slave) SDOx SDIx SDIx SDOx SCKx SSx FIGURE 15-7: Serial Clock Frame Sync Pulse SCKx SSx SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PROCESSOR 2 PIC24F (SPI Slave, Frame Master) SDOx SDIx SDIx SDOx SCKx SSx FIGURE 15-8: Serial Clock Frame Sync. Pulse SCKx SSx SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PROCESSOR 2 PIC24F (SPI Slave, Frame Slave) SDIx SDOx SDOx SDIx SCKx SSx  2009 Microchip Technology Inc. Serial Clock Frame Sync Pulse SCKx SSx DS39897C-page 189 PIC24FJ256GB110 FAMILY EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1) FSCK = FCY Primary Prescaler * Secondary Prescaler Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled. TABLE 15-1: SAMPLE SCK FREQUENCIES(1,2) Secondary Prescaler Settings FCY = 16 MHz Primary Prescaler Settings 1:1 2:1 4:1 6:1 8:1 1:1 Invalid 8000 4000 2667 2000 4:1 4000 2000 1000 667 500 16:1 1000 500 250 167 125 64:1 250 125 63 42 31 1:1 5000 2500 1250 833 625 FCY = 5 MHz Primary Prescaler Settings Note 1: 2: 4:1 1250 625 313 208 156 16:1 313 156 78 52 39 64:1 78 39 20 13 10 Based on FCY = FOSC/2, Doze mode and PLL are disabled. SCKx frequencies shown in kHz. DS39897C-page 190  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 16.0 Note: INTER-INTEGRATED CIRCUIT (I2C™) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 24. “Inter-Integrated Circuit (I2C™)” (DS39702). The Inter-Integrated Circuit (I2C) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, display drivers, A/D Converters, etc. The I • • • • • • • • • 2C module supports these features: Independent master and slave logic 7-bit and 10-bit device addresses General call address, as defined in the I2C protocol Clock stretching to provide delays for the processor to respond to a slave data request Both 100 kHz and 400 kHz bus specifications. Configurable address masking Multi-Master modes to prevent loss of messages in arbitration Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address Automatic SCL 16.1 The details of sending a message in Master mode depends on the communications protocol for the device being communicated with. Typically, the sequence of events is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. A block diagram of the module is shown in Figure 16-1. 13.  2009 Microchip Technology Inc. Communicating as a Master in a Single Master Environment Assert a Start condition on SDAx and SCLx. Send the I 2C device address byte to the slave with a write indication. Wait for and verify an Acknowledge from the slave. Send the first data byte (sometimes known as the command) to the slave. Wait for and verify an Acknowledge from the slave. Send the serial memory address low byte to the slave. Repeat steps 4 and 5 until all data bytes are sent. Assert a Repeated Start condition on SDAx and SCLx. Send the device address byte to the slave with a read indication. Wait for and verify an Acknowledge from the slave. Enable master reception to receive serial memory data. Generate an ACK or NACK condition at the end of a received byte of data. Generate a Stop condition on SDAx and SCLx. DS39897C-page 191 PIC24FJ256GB110 FAMILY FIGURE 16-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read TCY/2 DS39897C-page 192  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 16.2 Setting Baud Rate When Operating as a Bus Master 16.3 The I2CxMSK register (Register 16-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register causes the slave module to respond whether the corresponding address bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK is set to ‘00100000’, the slave module will detect both addresses, ‘0000000’ and ‘0100000’. To compute the Baud Rate Generator reload value, use Equation 16-1. EQUATION 16-1: Slave Address Masking COMPUTING BAUD RATE RELOAD VALUE(1,2) FCY FSCL = ---------------------------------------------------------------------FCY I2CxBRG + 1 + -----------------------------10 000 000 or FCY FCY I2CxBRG =  ------------ – ------------------------------ – 1  FSCL 10 000 000 To enable address masking, the IPMI (Intelligent Peripheral Management Interface) must be disabled by clearing the IPMIEN bit (I2CxCON). Note: Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. 2: These clock rate values are for guidance only. The actual clock rate can be affected by various system level parameters. The actual clock rate should be measured in its intended application. TABLE 16-1: As a result of changes in the I2C™ protocol, the addresses in Table 16-2 are reserved and will not be Acknowledged in Slave mode. This includes any address mask settings that include any of these addresses. I2C™ CLOCK RATES(1,2) Required System FSCL FCY I2CxBRG Value (Decimal) (Hexadecimal) Actual FSCL 100 kHz 16 MHz 157 9D 100 kHz 100 kHz 8 MHz 78 4E 100 kHz 100 kHz 4 MHz 39 27 99 kHz 400 kHz 16 MHz 37 25 404 kHz 400 kHz 8 MHz 18 12 404 kHz 400 kHz 4 MHz 9 9 385 kHz 400 kHz 2 MHz 4 4 385 kHz 1 MHz 16 MHz 13 D 1.026 MHz 1 MHz 8 MHz 6 6 1.026 MHz 1 MHz 4 MHz 3 3 0.909 MHz Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled. 2: These clock rate values are for guidance only. The actual clock rate can be affected by various system level parameters. The actual clock rate should be measured in its intended application. TABLE 16-2: I2C™ RESERVED ADDRESSES(1) Slave Address R/W Bit 0000 000 0 General Call Address(2) 0000 000 1 Start Byte 0000 001 x Cbus Address 0000 010 x Reserved 0000 011 x Reserved 0000 1xx x HS Mode Master Code 1111 1xx x Reserved 1111 Note 1: 2: 3: Description 0xx x 10-Bit Slave Upper Byte(3) The address bits listed here will never cause an address match, independent of address mask settings. Address will be Acknowledged only if GCEN = 1. Match on this address can only occur on the upper byte in 10-Bit Addressing mode.  2009 Microchip Technology Inc. DS39897C-page 193 PIC24FJ256GB110 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables I2Cx module. All I2C pins are controlled by port functions. bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: Stop in Idle Mode bit 1 = Discontinues module operation when device enters an Idle mode 0 = Continues module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C Slave) 1 = Releases SCLx clock 0 = Holds SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave transmission. bit 11 IPMIEN: Intelligent Platform Management Interface (IPMI) Enable bit 1 = IPMI Support mode is enabled; all addresses Acknowledged 0 = IPMI mode disabled bit 10 A10M: 10-Bit Slave Addressing bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with SMBus specification 0 = Disables SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enables software or receive clock stretching 0 = Disables software or receive clock stretching DS39897C-page 194  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master. Applicable during master receive.) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (When operating as I2C master. Applicable during master receive.) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware clear at end of master Acknowledge sequence. 0 = Acknowledge sequence not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte. 0 = Receives sequence not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence. 0 = Stop condition not in progress bit 1 RSEN: Repeated Start Condition Enabled bit (when operating as I2C master) 1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence. 0 = Repeated Start condition not in progress bit 0 SEN: Start Condition Enabled bit (when operating as I2C master) 1 = Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence. 0 = Start condition not in progress  2009 Microchip Technology Inc. DS39897C-page 195 PIC24FJ256GB110 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC IWCOL I2COV D/A P R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC S R/W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ACKSTAT: Acknowledge Status bit 1 = NACK was detected last 0 = ACK was detected last Hardware set or clear at end of Acknowledge. bit 14 TRSTAT: Transmit Status bit (When operating as I2C master. Applicable to master transmit operation.) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D/A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by after transmission finishes, or by reception of slave byte. DS39897C-page 196  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R/W: Read/Write Information bit (when operating as I2C slave) 1 = Read – indicates data transfer is output from slave 0 = Write – indicates data transfer is input to slave Hardware set or clear after reception of I 2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.  2009 Microchip Technology Inc. DS39897C-page 197 PIC24FJ256GB110 FAMILY REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK: Mask for Address Bit x Select bits 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position DS39897C-page 198  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 17.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 21. “UART” (DS39708). The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the PIC24F device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and also includes an IrDA® encoder and decoder. The primary features of the UART module are: • Full-Duplex, 8 or 9-Bit Data Transmission through the UxTX and UxRX Pins • Even, Odd or No Parity Options (for 8-bit data) • One or two Stop bits • Hardware Flow Control Option with UxCTS and UxRTS Pins FIGURE 17-1: • Fully Integrated Baud Rate Generator with 16-Bit Prescaler • Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS • 4-Deep, First-In-First-Out (FIFO) Transmit Data Buffer • 4-Deep FIFO Receive Data Buffer • Parity, Framing and Buffer Overrun Error Detection • Support for 9-bit mode with Address Detect (9th bit = 1) • Transmit and Receive Interrupts • Loopback mode for Diagnostic Support • Support for Sync and Break Characters • Supports Automatic Baud Rate Detection • IrDA Encoder and Decoder Logic • 16x Baud Clock Output for IrDA® Support A simplified block diagram of the UART is shown in Figure 17-1. The UART module consists of these key important hardware elements: • Baud Rate Generator • Asynchronous Transmitter • Asynchronous Receiver UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® Hardware Flow Control UxRTS/BCLKx UxCTS Note: UARTx Receiver UxRX UARTx Transmitter UxTX The UART inputs and outputs must all be assigned to available RPn pins before use. Please see Section 10.4 “Peripheral Pin Select” for more information.  2009 Microchip Technology Inc. DS39897C-page 199 PIC24FJ256GB110 FAMILY 17.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 17-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 17-1: Baud Rate = The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG = 0) and the minimum baud rate possible is FCY/(16 * 65536). Equation 17-2 shows the formula for computation of the baud rate with BRGH = 1. EQUATION 17-2: UART BAUD RATE WITH BRGH = 0(1,2) Baud Rate = FCY 16 • (UxBRG + 1) UxBRG = UxBRG = Note 1: FCY –1 16 • Baud Rate FCY denotes the instruction cycle clock frequency (FOSC/2). Based on FCY = FOSC/2, Doze mode and PLL are disabled. 2: Example 17-1 shows the calculation of the baud rate error for the following conditions: • FCY = 4 MHz • Desired Baud Rate = 9600 EXAMPLE 17-1: Desired Baud Rate UART BAUD RATE WITH BRGH = 1(1,2) Note 1: 2: FCY 4 • (UxBRG + 1) FCY 4 • Baud Rate –1 FCY denotes the instruction cycle clock frequency. Based on FCY = FOSC/2, Doze mode and PLL are disabled. The maximum baud rate (BRGH = 1) possible is FCY/4 (for UxBRG = 0) and the minimum baud rate possible is FCY/(4 * 65536). Writing a new value to the UxBRG register causes the BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. BAUD RATE ERROR CALCULATION (BRGH = 0)(1) = FCY/(16 (UxBRG + 1)) Solving for UxBRG value: UxBRG UxBRG UxBRG = ((FCY/Desired Baud Rate)/16) – 1 = ((4000000/9600)/16) – 1 = 25 Calculated Baud Rate= 4000000/(16 (25 + 1)) = 9615 Error Note 1: = (Calculated Baud Rate – Desired Baud Rate) Desired Baud Rate = (9615 – 9600)/9600 = 0.16% Based on FCY = FOSC/2, Doze mode and PLL are disabled. DS39897C-page 200  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 17.2 1. 2. 3. 4. 5. 6. Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt two cycles after being set). Write data byte to lower byte of UxTXREG word. The value will be immediately transferred to the Transmit Shift Register (TSR), and the serial bit stream will start shifting out with next rising edge of the baud clock. Alternately, the data byte may be transferred while UTXEN = 0, and then the user may set UTXEN. This will cause the serial bit stream to begin immediately because the baud clock will start from a cleared state. A transmit interrupt will be generated as per interrupt control bit, UTXISELx. 17.3 1. 2. 3. 4. 5. 6. Transmitting in 8-Bit Data Mode Transmitting in 9-Bit Data Mode Set up the UART (as described in Section 17.2 “Transmitting in 8-Bit Data Mode”). Enable the UART. Set the UTXEN bit (causes a transmit interrupt). Write UxTXREG as a 16-bit value only. A word write to UxTXREG triggers the transfer of the 9-bit data to the TSR. Serial bit stream will start shifting out with the first rising edge of the baud clock. A transmit interrupt will be generated as per the setting of control bit, UTXISELx. 17.4 Break and Sync Transmit Sequence The following sequence will send a message frame header made up of a Break, followed by an auto-baud Sync byte. 1. 2. 3. 4. 5. Configure the UART for the desired mode. Set UTXEN and UTXBRK to set up the Break character. Load the UxTXREG with a dummy character to initiate transmission (value is ignored). Write ‘55h’ to UxTXREG; this loads the Sync character into the transmit FIFO. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits.  2009 Microchip Technology Inc. 17.5 1. 2. 3. 4. 5. Receiving in 8-Bit or 9-Bit Data Mode Set up the UART (as described in Section 17.2 “Transmitting in 8-Bit Data Mode”). Enable the UART. A receive interrupt will be generated when one or more data characters have been received as per interrupt control bit, URXISELx. Read the OERR bit to determine if an overrun error has occurred. The OERR bit must be reset in software. Read UxRXREG. The act of reading the UxRXREG character will move the next character to the top of the receive FIFO, including a new set of PERR and FERR values. 17.6 Operation of UxCTS and UxRTS Control Pins UARTx Clear to Send (UxCTS) and Request to Send (UxRTS) are the two hardware controlled pins that are associated with the UART module. These two pins allow the UART to operate in Simplex and Flow Control mode. They are implemented to control the transmission and reception between the Data Terminal Equipment (DTE). The UEN bits in the UxMODE register configure these pins. 17.7 Infrared Support The UART module provides two types of infrared UART support: one is the IrDA clock output to support external IrDA encoder and decoder device (legacy module support) and the other is the full implementation of the IrDA encoder and decoder. Note that because the IrDA modes require a 16x baud clock, they will only work when the BRGH bit (UxMODE) is ‘0’. 17.7.1 IrDA CLOCK OUTPUT FOR EXTERNAL IRDA SUPPORT To support external IrDA encoder and decoder devices, the BCLKx pin (same as the UxRTS pin) can be configured to generate the 16x baud clock. With UEN = 11, the BCLKx pin will output the 16x baud clock if the UART module is enabled. It can be used to support the IrDA codec chip. 17.7.2 BUILT-IN IrDA ENCODER AND DECODER The UART has full implementation of the IrDA encoder and decoder as part of the UART module. The built-in IrDA encoder and decoder functionality is enabled using the IREN bit (UxMODE). When enabled (IREN = 1), the receive pin (UxRX) acts as the input from the infrared receiver. The transmit pin (UxTX) acts as the output to the infrared transmitter. DS39897C-page 201 PIC24FJ256GB110 FAMILY REGISTER 17-1: R/W-0 UxMODE: UARTx MODE REGISTER U-0 (1) UARTEN — R/W-0 USIDL R/W-0 IREN (2) R/W-0 U-0 R/W-0 R/W-0 RTSMD — UEN1 UEN0 bit 15 bit 8 R/C-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN 0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder enabled 0 = IrDA encoder and decoder disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin in Simplex mode 0 = UxRTS pin in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN1:UEN0: UARTx Enable bits 11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by port latches bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared in hardware on following rising edge 0 = No wake-up enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Note 1: 2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select” for more information. This feature is only available for the 16x BRG mode (BRGH = 0). DS39897C-page 202  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode (baud clock generated from FCY/4) 0 = Standard mode (baud clock generated from FCY/16) bit 2-1 PDSEL: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: 2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select” for more information. This feature is only available for the 16x BRG mode (BRGH = 0).  2009 Microchip Technology Inc. DS39897C-page 203 PIC24FJ256GB110 FAMILY REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 HC R/W-0 R-0 R-1 UTXISEL1 UTXINV(1) UTXISEL0 — UTXBRK UTXEN(2) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15,13 UTXISEL: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: IrDA® Encoder Transmit Polarity Inversion bit(1) IREN = 0: 1 = UxTX Idle ‘0’ 0 = UxTX Idle ‘1’ IREN = 1: 1 = UxTX Idle ‘1’ 0 = UxTX Idle ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission disabled or completed bit 10 UTXEN: Transmit Enable bit(2) 1 = Transmit enabled, UxTX pin controlled by UARTx 0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by port. bit 9 UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued bit 7-6 URXISEL: Receive Interrupt Mode Selection bits 11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer. Receive buffer has one or more characters. Note 1: 2: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select” for more information. DS39897C-page 204  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect. 0 = Address Detect mode disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit (1  0 transition) will reset the receiver buffer and the RSR to the empty state bit 0 URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: 2: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select” for more information.  2009 Microchip Technology Inc. DS39897C-page 205 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 206  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 18.0 Note: UNIVERSAL SERIAL BUS WITH ON-THE-GO SUPPORT (USB OTG) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 27. “USB On-The-Go (OTG)”. PIC24FJ256GB110 family devices contain a full-speed and low-speed compatible, On-The-Go (OTG) USB Serial Interface Engine (SIE). The OTG capability allows the device to act either as a USB peripheral device or as a USB embedded host with limited host capabilities. The OTG capability allows the device to dynamically switch from device to host operation using OTG’s Host Negotiation Protocol (HNP). For more details on OTG operation, refer to the “On-The-Go Supplement to the USB 2.0 Specification”, published by the USB-IF. For more details on USB operation, refer to the “Universal Serial Bus Specification”, v2.0. The USB OTG module offers these features: • USB functionality in Device and Host modes, and OTG capabilities for application-controlled mode switching • Software-selectable module speeds of full speed (12 Mbps) or low speed (1.5 Mbps, available in Host mode only) • Support for all four USB transfer types: control, interrupt, bulk and isochronous • 16 bidirectional endpoints for a total of 32 unique endpoints • DMA interface for data RAM access • Queues up to sixteen unique endpoint transfers without servicing • Integrated, on-chip USB transceiver, with support for off-chip transceivers via a digital interface: • Integrated VBUS generation with on-chip comparators and boost generation, and support of external VBUS comparators and regulators through a digital interface • Configurations for on-chip bus pull-up and pull-down resistors The USB OTG module can function as a USB peripheral device or as a USB host, and may dynamically switch between Device and Host modes under software control. In either mode, the same data paths and buffer descriptors are used for the transmission and reception of data. In discussing USB operation, this section will use a controller-centric nomenclature for describing the direction of the data transfer between the microcontroller and the USB. Rx (Receive) will be used to describe transfers that move data from the USB to the microcontroller, and Tx (Transmit) will be used to describe transfers that move data from the microcontroller to the USB. Table 18-1 shows the relationship between data direction in this nomenclature and the USB tokens exchanged. TABLE 18-1: USB Mode CONTROLLER-CENTRIC DATA DIRECTION FOR USB HOST OR TARGET Direction Rx Tx Device OUT or SETUP IN Host IN OUT or SETUP This chapter presents the most basic operations needed to implement USB OTG functionality in an application. A complete and detailed discussion of the USB protocol and its OTG supplement are beyond the scope of this data sheet. It is assumed that the user already has a basic understanding of USB architecture and the latest version of the protocol. Not all steps for proper USB operation (such as device enumeration) are presented here. It is recommended that application developers use an appropriate device driver to implement all of the necessary features. Microchip provides a number of application-specific resources, such as USB firmware and driver support. Refer to www.microchip.com for the latest firmware and driver support. A simplified block diagram of the USB OTG module is shown in Figure 18-1.  2009 Microchip Technology Inc. DS39897C-page 207 PIC24FJ256GB110 FAMILY FIGURE 18-1: USB OTG MODULE BLOCK DIAGRAM Full-Speed Pull-up Host Pull-down 48 MHz USB Clock D+(1) Registers and Control Interface Transceiver D-(1) Host Pull-down USBID(1) USB SIE VMIO(1) VPIO(1) DMH(1) DPH(1) External Transceiver Interface DMLN(1) DPLN(1) RCV(1) System RAM USBOEN(1) VBUSON(1) SRP Charge USB Voltage Comparators VBUS SRP Discharge VUSB Transceiver Power 3.3V USB 3.3V Regulator VCMPST1(1) VCMPST2(1) VBUSST(1) VCPCON(1) Note 1: VBUS Boost Assist Pins are multiplexed with digital I/O and other device features. DS39897C-page 208  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 18.1 Hardware Configuration 18.1.1 DEVICE MODE 18.1.1.1 D+ Pull-up Resistor PIC24FJ256GB110 family devices have a built-in 1.5 k resistor on the D+ line that is available when the microcontroller in operating in device mode. This is used to signal an external Host that the device is operating in Full Speed Device mode. It is engaged by setting the DPPULUP bit (U1OTGCON). Alternatively, an external resistor may be used on D+, as shown in Figure 18-2. FIGURE 18-2: EXTERNAL PULL-UP FOR FULL-SPEED DEVICE MODE Host Controller/HUB ® PIC MCU To meet compliance specifications, the USB module (and the D+ or D- pull-up resistor) should not be enabled until the host actively drives VBUS high. One of the 5.5V tolerant I/O pins may be used for this purpose. The application should never source any current onto the 5V VBUS pin of the USB cable. The Dual-power option with Self-Power Dominance (Figure 18-5) allows the application to use internal power primarily, but switch to power from the USB when no internal power is available. Dual-power devices must also meet all of the special requirements for inrush current and Suspend mode current previously described, and must not enable the USB module until VBUS is driven high. FIGURE 18-3: BUS POWER ONLY 100 k 3.3V VBUS ~5V Attach Sense VBUS VDD Low IQ Regulator VUSB VUSB VSS 1.5 k D+ D- FIGURE 18-4: 18.1.1.2 Power Modes Many USB applications will likely have several different sets of power requirements and configuration. The most common power modes encountered are: • Bus Power Only, • Self-Power Only and • Dual Power with Self-Power Dominance. Bus Power Only mode (Figure 18-3) is effectively the simplest method. All power for the application is drawn from the USB. To meet the inrush current requirements of the USB 2.0 Specification, the total effective capacitance appearing across VBUS and ground must be no more than 10 F. In the USB Suspend mode, devices must consume no more than 2.5 mA from the 5V VBUS line of the USB cable. During the USB Suspend mode, the D+ or Dpull-up resistor must remain active, which will consume some of the allowed suspend current. In Self-Power Only mode (Figure 18-4), the USB application provides its own power, with very little power being pulled from the USB. Note that an attach indication is added to indicate when the USB has been connected and the host is actively powering VBUS.  2009 Microchip Technology Inc. SELF-POWER ONLY 100 k VBUS ~5V Attach Sense VBUS VSELF ~3.3V VDD VUSB 100 k VSS FIGURE 18-5: DUAL POWER EXAMPLE 100 k VBUS ~5V 3.3V Low IQ Regulator 100 k VSELF ~3.3V Attach Sense VBUS VDD VUSB VSS DS39897C-page 209 PIC24FJ256GB110 FAMILY 18.1.2 18.1.2.1 HOST AND OTG MODES microcontroller is running below VBUS and is not able to source sufficient current, a separate power supply must be provided. D+ and D- Pull-down Resistors PIC24FJ256GB110 family devices have built-in 15 k pull-down resistor on the D+ and D- lines. These are used in tandem to signal to the bus that the microcontroller is operating in Host mode. They are engaged by setting the DPPULDWN and DMPULDWN bits (U1OTGCON). 18.1.2.2 When the application is always operating in Host mode, a simple circuit can be used to supply VBUS and regulate current on the bus (Figure 18-6). For OTG operation, it is necessary to be able to turn VBUS on or off as needed, as the microcontroller switches between Device and Host modes. A typical example using an external charge pump is shown in Figure 18-7. Power Configurations In Host mode, as well as Host mode in On-the-Go operation, the USB 2.0 specification requires that the Host application supply power on VBUS. Since the FIGURE 18-6: HOST INTERFACE EXAMPLE +5V +3.3V +3.3V Thermal Fuse Polymer PTC VUSB 0.1 µF, 3.3V 2 k 150 µF A/D pin 2 k Micro A/B Connector VBUS D+ DID VSS VBUS D+ DID GND FIGURE 18-7: PIC® Microcontroller VDD OTG INTERFACE EXAMPLE VDD PIC® Microcontroller MCP1253 1 µF Micro A/B Connector 4.7 µF VBUS D+ DID GND DS39897C-page 210 GND C+ VIN SELECT CVOUT SHND PGOOD 10 µF I/O I/O 40 k VBUS D+ DID VSS  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 18.1.2.3 VBUS Voltage Generation with External Devices When operating as a USB host, either as an A-device in an OTG configuration or as an embedded host, VBUS must be supplied to the attached device. PIC24FJ256GB110 family devices have an internal VBUS boost assist to help generate the required 5V VBUS from the available voltages on the board. This is comprised of a simple PWM output to control a Switch mode power supply, and built-in comparators to monitor output voltage and limit current. To enable voltage generation: 1. 2. 3. 4. 5. 6. 7. Verify that the USB module is powered (U1PWRC = 1) and that the VBUS discharge is disabled (U1OTGCON = 0). Set the PWM period (U1PWMRRS) and duty cycle (U1PWMRRS) as required. Select the required polarity of the output signal based on the configuration of the external circuit with the PWMPOL bit (U1PWMCON). Select the desired target voltage using the VBUSCHG bit (U1OTGCON). Enable the PWM counter by setting the CNTEN bit to ‘1’ (U1PWMCON). Enable the PWM module by setting the PWMEN bit to ‘1’ (U1PWMCON). generation circuit Enable the VBUS (U1OTGCON = 1). Note: 18.1.3 USING AN EXTERNAL INTERFACE Some applications may require the USB interface to be isolated from the rest of the system. PIC24FJ256GB110 family devices include a complete interface to communicate with and control an external USB transceiver, including the control of data line pull-ups and pull-downs. The VBUS voltage generation control circuit can also be configured for different VBUS generation topologies. Please refer to the “PIC24F Family Reference Manual”, Section 27. “USB On-The-Go (OTG)” for information on using the external interface. 18.1.4 CALCULATING TRANSCEIVER POWER REQUIREMENTS The USB transceiver consumes a variable amount of current depending on the characteristic impedance of the USB cable, the length of the cable, the VUSB supply voltage and the actual data patterns moving across the USB cable. Longer cables have larger capacitances and consume more total energy when switching output states. The total transceiver current consumption will be application-specific. Equation 18-1 can help estimate how much current actually may be required in full-speed applications. Please refer to the “PIC24F Family Reference Manual”, Section 27. “USB On-The-Go (OTG)” for a complete discussion on transceiver power consumption. This section describes the general process for VBUS voltage generation and control. Please refer to the “PIC24F Family Reference Manual” for additional examples. EQUATION 18-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION IXCVR = (40 mA • VUSB • PZERO • PIN • LCABLE) + IPULLUP (3.3V • 5m) Legend: VUSB – Voltage applied to the VUSB pin in volts (3.0V to 3.6V). PZERO – Percentage (in decimal) of the IN traffic bits sent by the PIC® microcontroller that are a value of ‘0’. PIN – Percentage (in decimal) of total bus bandwidth that is used for IN traffic. LCABLE – Length (in meters) of the USB cable. The USB 2.0 Specification requires that full-speed applications use cables no longer than 5m. IPULLUP – Current which the nominal, 1.5 k pull-up resistor (when enabled) must supply to the USB cable.  2009 Microchip Technology Inc. DS39897C-page 211 PIC24FJ256GB110 FAMILY 18.2 USB Buffer Descriptors and the BDT Endpoint buffer control is handled through a structure called the Buffer Descriptor Table (BDT). This provides a flexible method for users to construct and control endpoint buffers of various lengths and configurations. The BDT can be located in any available, 512-byte aligned block of data RAM. The BDT Pointer (U1BDTP1) contains the upper address byte of the BDT, and sets the location of the BDT in RAM. The user must set this pointer to indicate the table’s location. The BDT is composed of Buffer Descriptors (BDs) which are used to define and control the actual buffers in the USB RAM space. Each BD consists of two, 16-bit “soft” (non-fixed-address) registers, BDnSTAT and BDnADR, where n represents one of the 64 possible BDs (range of 0 to 63). BDnSTAT is the status register for BDn, while BDnADR specifies the starting address for the buffer associated with BDn. FIGURE 18-8: Depending on the endpoint buffering configuration used, there are up to 64 sets of buffer descriptors, for a total of 256 bytes. At a minimum, the BDT must be at least 8 bytes long. This is because the USB specification mandates that every device must have Endpoint 0 with both input and output for initial setup. Endpoint mapping in the BDT is dependent on three variables: • Endpoint number (0 to 15) • Endpoint direction (Rx or Tx) • Ping-pong settings (U1CNFG1) Figure 18-8 illustrates how these variables are used to map endpoints in the BDT. In Host mode, only Endpoint 0 buffer descriptors are used. All transfers utilize the Endpoint 0 buffer descriptor and Endpoint Control register (U1EP0). For received packets, the attached device’s source endpoint is indicated by the value of ENDPT in the USB status register (U1STAT). For transmitted packet, the attached device’s destination endpoint is indicated by the value written to the Token register (U1TOK). BDT MAPPING FOR ENDPOINT BUFFERING MODES PPB = 00 No Ping-Pong Buffers PPB = 01 Ping-Pong Buffer on EP0 OUT PPB = 10 Ping-Pong Buffers on all EPs Total BDT Space: 128 bytes Total BDT Space: 132 bytes Total BDT Space: 256 bytes PPB = 11 Ping-Pong Buffers on all other EPs except EP0 Total BDT Space: 248 bytes EP0 Rx Descriptor EP0 Rx Even Descriptor EP0 Rx Even Descriptor EP0 Rx Descriptor EP0 Tx Descriptor EP0 Rx Odd Descriptor EP0 Rx Odd Descriptor EP0 Tx Descriptor EP0 Tx Even Descriptor EP1 Rx Even Descriptor EP0 Tx Odd Descriptor EP1 Rx Odd Descriptor EP1 Rx Even Descriptor EP1 Tx Even Descriptor EP1 Rx Odd Descriptor EP1 Tx Odd Descriptor EP1 Rx Descriptor EP1 Tx Descriptor EP0 Tx Descriptor EP1 Rx Descriptor EP1 Tx Descriptor EP15 Tx Descriptor EP15 Tx Descriptor EP1 Tx Even Descriptor EP1 Tx Odd Descriptor EP15 Tx Odd Descriptor Note: EP15 Tx Odd Descriptor Memory area not shown to scale. DS39897C-page 212  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY BDs have a fixed relationship to a particular endpoint, depending on the buffering configuration. Table 18-2 provides the mapping of BDs to endpoints. This relationship also means that gaps may occur in the BDT if endpoints are not enabled contiguously. This theoretically means that the BDs for disabled endpoints could be used as buffer space. In practice, users should avoid using such spaces in the BDT unless a method of validating BD addresses is implemented. 18.2.1 The buffer descriptors have a different meaning based on the source of the register update. Register 18-1 and Register 18-2 show the differences in BDnSTAT depending on its current “ownership”. When UOWN is set, the user can no longer depend on the values that were written to the BDs. From this point, the USB module updates the BDs as necessary, overwriting the original BD values. The BDnSTAT register is updated by the SIE with the token PID and the transfer count is updated. BUFFER OWNERSHIP 18.2.2 Because the buffers and their BDs are shared between the CPU and the USB module, a simple semaphore mechanism is used to distinguish which is allowed to update the BD and associated buffers in memory. This is done by using the UOWN bit as a semaphore to distinguish which is allowed to update the BD and associated buffers in memory. UOWN is the only bit that is shared between the two configurations of BDnSTAT. DMA INTERFACE The USB OTG module uses a dedicated DMA to access both the BDT and the endpoint data buffers. Since part of the address space of the DMA is dedicated to the Buffer Descriptors, a portion of the memory connected to the DMA must comprise a contiguous address space properly mapped for the access by the module. When UOWN is clear, the BD entry is “owned” by the microcontroller core. When the UOWN bit is set, the BD entry and the buffer memory are “owned” by the USB peripheral. The core should not modify the BD or its corresponding data buffer during this time. Note that the microcontroller core can still read BDnSTAT while the SIE owns the buffer and vice versa. TABLE 18-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES BDs Assigned to Endpoint Endpoint Mode 0 (No Ping-Pong) Out Mode 1 (Ping-Pong on EP0 Out) In Out Mode 2 (Ping-Pong on all EPs) In Out In Mode 3 (Ping-Pong on all other EPs, except EP0) Out In 0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1 1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4 (E), 5 (O) 2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 6 (E), 7 (O) 8 (E), 9 (O) 3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O) 10 (E), 11 (O) 12 (E), 13 (O) 4 8 9 9 10 16 (E), 17 (O) 18 (E), 19 (O) 14 (E), 15 (O) 16 (E), 17 (O) 5 10 11 11 12 20 (E), 21 (O) 22 (E), 23 (O) 18 (E), 19 (O) 20 (E), 21 (O) 6 12 13 13 14 24 (E), 25 (O) 26 (E), 27 (O) 22 (E), 23 (O) 24 (E), 25 (O) 7 14 15 15 16 28 (E), 29 (O) 30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O) 8 16 17 17 18 32 (E), 33 (O) 34 (E), 35 (O) 30 (E), 31 (O) 32 (E), 33 (O) 9 18 19 19 20 36 (E), 37 (O) 38 (E), 39 (O) 34 (E), 35 (O) 36 (E), 37 (O) 10 20 21 21 22 40 (E), 41 (O) 42 (E), 43 (O) 38 (E), 39 (O) 40 (E), 41 (O) 11 22 23 23 24 44 (E), 45 (O) 46 (E), 47 (O) 42 (E), 43 (O) 44 (E), 45 (O) 12 24 25 25 26 48 (E), 49 (O) 50 (E), 51 (O) 46 (E), 47 (O) 48 (E), 49 (O) 13 26 27 27 28 52 (E), 53 (O) 54 (E), 55 (O) 50 (E), 51 (O) 52 (E), 53 (O) 14 28 29 29 30 56 (E), 57 (O) 58 (E), 59 (O) 54 (E), 55 (O) 56 (E), 57 (O) 15 30 31 31 32 60 (E), 61 (O) 62 (E), 63 (O) 58 (E), 59 (O) 60 (E), 61 (O) Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer  2009 Microchip Technology Inc. DS39897C-page 213 PIC24FJ256GB110 FAMILY REGISTER 18-1: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, USB MODE (BD0STAT THROUGH BD63STAT) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x UOWN DTS PID3 PID2 PID1 PID0 BC9 BC8 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UOWN: USB Own bit 1 = The USB module owns the BD and its corresponding buffer; the CPU must not modify the BD or the buffer bit 14 DTS: Data Toggle Packet bit 1 = Data 1 packet 0 = Data 0 packet bit 13-10 PID: Packet Identifier bits (written by the USB module) In Device mode: Represents the PID of the received token during the last transfer. In Host mode: Represents the last returned PID or the transfer status indicator. bit 9-0 BC: Byte Count This represents the number of bytes to be transmitted or the maximum number of bytes to be received during a transfer. Upon completion, the byte count is updated by the USB module with the actual number of bytes transmitted or received. DS39897C-page 214  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 18-2: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, CPU MODE (BD0STAT THROUGH BD63STAT) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x UOWN DTS(1) 0 0 DTSEN BSTALL BC9 BC8 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UOWN: USB Own bit 0 = The microcontroller core owns the BD and its corresponding buffer. The USB module ignores all other fields in the BD. bit 14 DTS: Data Toggle Packet bit(1) 1 = Data 1 packet 0 = Data 0 packet bit 13-12 Reserved Function: Maintain as ‘0’ bit 11 DTSEN: Data Toggle Synchronization Enable bit 1 = Data toggle synchronization is enabled; data packets with incorrect sync value will be ignored 0 = No data toggle synchronization is performed bit 10 BSTALL: Buffer Stall Enable bit 1 = Buffer STALL enabled; STALL handshake issued if a token is received that would use the BD in the given location (UOWN bit remains set, BD value is unchanged); corresponding EPSTALL bit will get set on any STALL handshake 0 = Buffer STALL disabled bit 9-0 BC: Byte Count bits This represents the number of bytes to be transmitted or the maximum number of bytes to be received during a transfer. Upon completion, the byte count is updated by the USB module with the actual number of bytes transmitted or received. Note 1: This bit is ignored unless DTSEN = 1.  2009 Microchip Technology Inc. DS39897C-page 215 PIC24FJ256GB110 FAMILY 18.3 USB Interrupts level consists of USB error conditions, which are enabled and flagged in the U1EIR and U1EIE registers. An interrupt condition in any of these triggers a USB Error Interrupt Flag (UERRIF) in the top level. The USB OTG module has many conditions that can be configured to cause an interrupt. All interrupt sources use the same interrupt vector. Interrupts may be used to trap routine events in a USB transaction. Figure 18-10 provides some common events within a USB frame and their corresponding interrupts. Figure 18-9 shows the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB status interrupts; these are enabled and flagged in the U1IE and U1IR registers, respectively. The second FIGURE 18-9: USB OTG INTERRUPT FUNNEL Top Level (USB Status) Interrupts STALLIF STALLIE ATTACHIF ATTACHIE RESUMEIF RESUMEIE IDLEIF IDLEIE TRNIF TRNIE Second Level (USB Error) Interrupts BTSEF BTSEE DMAEF DMAEE BTOEF BTOEE DFN8EF DFN8EE CRC16EF CRC16EE CRC5EF (EOFEF) CRC5EE (EOFEE) PIDEF PIDEE SOFIF SOFIE URSTIF (DETACHIF) URSTIE (DETACHIE) Set USB1IF (UERRIF) UERRIE IDIF IDIE T1MSECIF TIMSECIE LSTATEIF LSTATEIE ACTVIF ACTVIE SESVDIF SESVDIE SESENDIF SESENDIE VBUSVDIF VBUSVDIE Top Level (USB OTG) Interrupts DS39897C-page 216  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 18.3.1 CLEARING USB OTG INTERRUPTS Unlike device level interrupts, the USB OTG interrupt status flags are not freely writable in software. All USB OTG flag bits are implemented as hardware set only bits. Additionally, these bits can only be cleared in FIGURE 18-10: software by writing a ‘1’ to their locations (i.e., performing a MOV type instruction). Writing a ‘0’ to a flag bit (i.e., a BCLR instruction) has no effect. Note: Throughout this data sheet, a bit that can only be cleared by writing a ‘1’ to its location is referred to as “Write ‘1’ to clear”. In register descriptions, this function is indicated by the descriptor “K”. EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS USB Reset URSTIF From Host From Host To Host SETUP Token Data ACK From Host To Host From Host IN Token Data ACK From Host From Host To Host OUT Token Empty Data ACK Start-of-Frame (SOF) SOFIF Set TRNIF Set TRNIF Set TRNIF Transaction Transaction Complete RESET SOF SETUP DATA SOF STATUS Differential Data Control Transfer(1) 1 ms Frame Note 1: 18.4 The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers will spread across multiple frames. Device Mode Operation The following section describes how to perform a common Device mode task. In Device mode, USB transfers are performed at the transfer level. The USB module automatically performs the status phase of the transfer. 18.4.1 1. 2. 3. 4. 5. 6. 7. ENABLING DEVICE MODE Reset the Ping-Pong Buffer Pointers by setting, then clearing, the Ping-Pong Buffer Reset bit PPBRST (U1CON). Disable all interrupts (U1IE and U1EIE = 00h). Clear any existing interrupt flags by writing FFh to U1IR and U1EIR. Verify that VBUS is present (non OTG devices only).  2009 Microchip Technology Inc. 8. 9. Enable the USB module by setting the USBEN bit (U1CON). Set the OTGEN bit (U1OTGCON) to enable OTG operation. Enable the endpoint zero buffer to receive the first setup packet by setting the EPRXEN and EPHSHK bits for Endpoint 0 (U1EP0 = 1). Power up the USB module by setting the USBPWR bit (U1PWRC). Enable the D+ pull-up resistor to signal an attach by setting DPPULUP (U1OTGCON). DS39897C-page 217 PIC24FJ256GB110 FAMILY 18.4.2 1. 2. 3. 4. Attach to a USB host and enumerate as described in Chapter 9 of the USB 2.0 specification. Create a data buffer, and populate it with the data to send to the host. In the appropriate (EVEN or ODD) Tx BD for the desired endpoint: a) Set up the status register (BDnSTAT) with the correct data toggle (DATA0/1) value and the byte count of the data buffer. b) Set up the address register (BDnADR) with the starting address of the data buffer. c) Set the UOWN bit of the status register to ‘1’. When the USB module receives an IN token, it automatically transmits the data in the buffer. Upon completion, the module updates the status register (BDnSTAT) and sets the Transfer Complete Interrupt Flag, TRNIF (U1IR). 18.4.3 1. 2. 3. 4. RECEIVING AN IN TOKEN IN DEVICE MODE RECEIVING AN OUT TOKEN IN DEVICE MODE Attach to a USB host and enumerate as described in Chapter 9 of the USB 2.0 specification. Create a data buffer with the amount of data you are expecting from the host. In the appropriate (EVEN or ODD) Tx BD for the desired endpoint: a) Set up the status register (BDnSTAT) with the correct data toggle (DATA0/1) value and the byte count of the data buffer. b) Set up the address register (BDnADR) with the starting address of the data buffer. c) Set the UOWN bit of the status register to ‘1’. When the USB module receives an OUT token, it automatically receives the data sent by the host to the buffer. Upon completion, the module updates the status register (BDnSTAT) and sets the Transfer Complete Interrupt Flag, TRNIF (U1IR). DS39897C-page 218 18.5 Host Mode Operation The following sections describe how to perform common Host mode tasks. In Host mode, USB transfers are invoked explicitly by the host software. The host software is responsible for the Acknowledge portion of the transfer. Also, all transfers are performed using the Endpoint 0 control register (U1EP0) and buffer descriptors. 18.5.1 ENABLE HOST MODE AND DISCOVER A CONNECTED DEVICE 1. Enable Host mode by setting U1CON (HOSTEN). This causes the Host mode control bits in other USB OTG registers to become available. 2. Enable the D+ and D- pull-down resistors by setting DPPULDWN and DMPULDWN (U1OTGCON). Disable the D+ and Dpull-up resistors by clearing DPPULUP and DMPULUP (U1OTGCON). 3. At this point, SOF generation begins with the SOF counter loaded with 12,000. Eliminate noise on the USB by clearing the SOFEN bit (U1CON) to disable Start-Of-Frame packet generation. 4. Enable the device attached interrupt by setting ATTACHIE (U1IE). 5. Wait for the device attached interrupt (U1IR = 1). This is signaled by the USB device changing the state of D+ or D- from ‘0’ to ‘1’ (SE0 to J state). After it occurs, wait 100 ms for the device power to stabilize. 6. Check the state of the JSTATE and SE0 bits in U1CON. If the JSTATE bit (U1CON) is ‘0’, the connecting device is low speed. If the connecting device is low speed, set the low LSPDEN and LSPD bits (U1ADDR and U1EP0) to enable low-speed operation. 7. Reset the USB device by setting the USBRST bit (U1CON) for at least 50 ms, sending Reset signaling on the bus. After 50 ms, terminate the Reset by clearing USBRST. 8. To keep the connected device from going into suspend, enable SOF packet generation to keep by setting the SOFEN bit. 9. Wait 10 ms for the device to recover from Reset. 10. Perform enumeration as described by Chapter 9 of the USB 2.0 specification.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 18.5.2 1. 2. 3. 4. 5. 6. 7. COMPLETE A CONTROL TRANSACTION TO A CONNECTED DEVICE Follow the procedure described in Section 18.5.1 “Enable Host Mode and Discover a Connected Device” to discover a device. Set up the Endpoint Control register for bidirectional control transfers by writing 0Dh to U1EP0 (this sets the EPCONDIS, EPTXEN, and EPHSHK bits). Place a copy of the device framework setup command in a memory buffer. See Chapter 9 of the USB 2.0 specification for information on the device framework command set. Initialize the buffer descriptor (BD) for the current (EVEN or ODD) Tx EP0, to transfer the eight bytes of command data for a device framework command (i.e., a GET DEVICE DESCRIPTOR): a) Set the BD data buffer address (BD0ADR) to the starting address of the 8-byte memory buffer containing the command. b) Write 8008h to BD0STAT (this sets the UOWN bit, and sets a byte count of 8). Set the USB device address of the target device in the address register (U1ADDR). After a USB bus Reset, the device USB address will be zero. After enumeration, it will be set to another value between 1 and 127. Write D0h to U1TOK; this is a SETUP token to Endpoint 0, the target device’s default control pipe. This initiates a SETUP token on the bus, followed by a data packet. The device handshake is returned in the PID field of BD0STAT after the packets are complete. When the USB module updates BD0STAT, a transfer done interrupt is asserted (the TRNIF flag is set). This completes the setup phase of the setup transaction as referenced in chapter 9 of the USB specification. To initiate the data phase of the setup transaction (i.e., get the data for the GET DEVICE descriptor command), set up a buffer in memory to store the received data. 8. Initialize the current (EVEN or ODD) Rx or Tx (Rx for IN, Tx for OUT) EP0 BD to transfer the data. a) Write C040h to BD0STAT. This sets the UOWN, configures Data Toggle (DTS) to DATA1, and sets the byte count to the length of the data buffer (64 or 40h, in this case). b) Set BD0ADR to the starting address of the data buffer. 9. Write the token register with the appropriate IN or OUT token to Endpoint 0, the target device’s default control pipe (e.g., write 90h to U1TOK for an IN token for a GET DEVICE DESCRIPTOR command). This initiates an IN token on the bus followed by a data packet from the device to the host. When the data packet completes, the BD0STAT is written and a transfer done interrupt is asserted (the TRNIF flag is set). For control transfers with a single packet data phase, this completes the data phase of the setup transaction as referenced in chapter 9 of the USB specification. If more data needs to be transferred, return to step 8. 10. To initiate the status phase of the setup transaction, set up a buffer in memory to receive or send the zero length status phase data packet. 11. Initialize the current (even or odd) Tx EP0 BD to transfer the status data.: a) Set the BDT buffer address field to the start address of the data buffer b) Write 8000h to BD0STAT (set UOWN bit, configure DTS to DATA0, and set byte count to 0). 12. Write the Token register with the appropriate IN or OUT token to Endpoint 0, the target device’s default control pipe (e.g., write 01h to U1TOK for an OUT token for a GET DEVICE DESCRIPTOR command). This initiates an OUT token on the bus followed by a zero length data packet from the host to the device. When the data packet completes, the BD is updated with the handshake from the device, and a transfer done interrupt is asserted (the TRNIF flag is set). This completes the status phase of the setup transaction as described in Chapter 9 of the USB specification. Note:  2009 Microchip Technology Inc. Only one control transaction can be performed per frame. DS39897C-page 219 PIC24FJ256GB110 FAMILY 18.5.3 1. 2. 3. 4. 5. 6. 7. SEND A FULL-SPEED BULK DATA TRANSFER TO A TARGET DEVICE Follow the procedure described in Section 18.5.1 “Enable Host Mode and Discover a Connected Device” and Section 18.5.2 “Complete a Control Transaction to a Connected Device” to discover and configure a device. To enable transmit and receive transfers with handshaking enabled, write 1Dh to U1EP0. If the target device is a low-speed device, also set the LSPD bit (U1EP0). If you want the hardware to automatically retry indefinitely if the target device asserts a NAK on the transfer, clear the Retry Disable bit, RETRYDIS (U1EP0). Set up the BD for the current (EVEN or ODD) Tx EP0 to transfer up to 64 bytes. Set the USB device address of the target device in the address register (U1ADDR). Write an OUT token to the desired endpoint to U1TOK. This triggers the module’s transmit state machines to begin transmitting the token and the data. Wait for the Transfer Done Interrupt Flag, TRNIF. This indicates that the BD has been released back to the microprocessor, and the transfer has completed. If the retry disable bit is set, the handshake (ACK, NAK, STALL or ERROR (0Fh)) is returned in the BD PID field. If a STALL interrupt occurs, the pending packet must be dequeued and the error condition in the target device cleared. If a detach interrupt occurs (SE0 for more than 2.5 µs), then the target has detached (U1IR is set). Once the transfer done interrupt occurs (TRNIF is set), the BD can be examined and the next data packet queued by returning to step 2. Note: USB speed, transceiver and pull-ups should only be configured during the module setup phase. It is not recommended to change these settings while the module is enabled. 18.6 18.6.1 OTG Operation SESSION REQUEST PROTOCOL (SRP) An OTG A-device may decide to power down the VBUS supply when it is not using the USB link through the Session Request Protocol (SRP). Software may do this by clearing VBUSON (U1OTGCON). When the VBUS supply is powered down, the A-device is said to have ended a USB session. An OTG A-device or Embedded Host may repower the VBUS supply at any time (initiate a new session). An OTG B-device may also request that the OTG A-device repower the VBUS supply (initiate a new session). This is accomplished via Session Request Protocol (SRP). Prior to requesting a new session, the B-device must first check that the previous session has definitely ended. To do this, the B-device must check for two conditions: 1. VBUS supply is below the Session Valid voltage and 2. Both D+ and D- have been low for at least 2 ms. The B-device will be notified of condition 1 by the SESENDIF (U1OTGIR) interrupt. Software will have to manually check for condition 2. Note: When the A-device powers down the VBUS supply, the B-device must disconnect its pull-up resistor from power. If the device is self-powered, it can do this by clearing DPPULUP (U1OTGCON) and DMPULUP (U1OTGCON). The B-device may aid in achieving condition 1 by discharging the VBUS supply through a resistor. Software may do this by setting VBUSDIS (U1OTGCON). After these initial conditions are met, the B-device may begin requesting the new session. The B-device begins by pulsing the D+ data line. Software should do this by setting DPPULUP (U1OTGCON). The data line should be held high for 5 to 10 ms. The B-device then proceeds by pulsing the VBUS supply. Software should do this by setting PUVBUS (U1CNFG2). When an A-device detects SRP signaling (either via the ATTACHIF (U1IR) interrupt or via the SESVDIF (U1OTGIR) interrupt), the A-device must restore the VBUS supply by either setting VBUSON (U1OTGCON), or by setting the I/O port controlling the external power source. The B-device should not monitor the state of the VBUS supply while performing VBUS supply pulsing. When the B-device does detect that the VBUS supply has been restored (via the SESVDIF (U1OTGIR) interrupt), the B-device must re-connect to the USB link by pulling up D+ or D- (via the DPPULUP or DMPULUP). The A-device must complete the SRP by driving USB Reset signaling. DS39897C-page 220  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 18.6.2 HOST NEGOTIATION PROTOCOL (HNP) In USB OTG applications, a Dual Role Device (DRD) is a device that is capable of being either a host or a peripheral. Any OTG DRD must support Host Negotiation Protocol (HNP). HNP allows an OTG B-device to temporarily become the USB host. The A-device must first enable the B-device to follow HNP. Refer to the “On-The-Go Supplement to the USB 2.0 Specification” for more information regarding HNP. HNP may only be initiated at full speed. After being enabled for HNP by the A-device, the B-device requests being the host any time that the USB link is in Suspend state, by simply indicating a disconnect. This can be done in software by clearing DPPULUP and DMPULUP. When the A-device detects the disconnect condition (via the URSTIF (U1IR) interrupt), the A-device may allow the B-device to take over as Host. The A-device does this by signaling connect as a full-speed function. Software may accomplish this by setting DPPULUP. If the A-device responds instead with resume signaling, the A-device remains as host. When the B-device detects the connect condition (via ATTACHIF (U1IR), the B-device becomes host. The B-device drives Reset signaling prior to using the bus. When the B-device has finished in its role as Host, it stops all bus activity and turns on its D+ pull-up resistor by setting DPPULUP. When the A-device detects a suspend condition (Idle for 3 ms), the A-device turns off its D+ pull-up. The A-device may also power-down VBUS supply to end the session. When the A-device detects the connect condition (via ATTACHIF), the A-device resumes host operation, and drives Reset signaling.  2009 Microchip Technology Inc. 18.7 USB OTG Module Registers There are a total of 37 memory mapped registers associated with the USB OTG module. They can be divided into four general categories: • • • • USB OTG Module Control (12) USB Interrupt (7) USB Endpoint Management (16) USB VBUS Power Control (2) This total does not include the (up to) 128 BD registers in the BDT. Their prototypes, described in Register 18-1 and Register 18-2, are shown separately in Section 18.2 “USB Buffer Descriptors and the BDT”. With the exception U1PWMCON and U1PWMRRS, all USB OTG registers are implemented in the Least Significant Byte of the register. Bits in the upper byte are unimplemented, and have no function. Note that some registers are instantiated only in Host mode, while other registers have different bit instantiations and functions in Device and Host modes. Registers described in the following sections are those that have bits with specific control and configuration features. The following registers are used for data or address values only: • U1BDTP1: Specifies the 256-word page in data RAM used for the BDT; 8-bit value with bit 0 fixed as ‘0’ for boundary alignment • U1FRML and U1FRMH: Contains the 11-bit byte counter for the current data frame • U1PWMRRS: Contains the 8-bit value for PWM duty cycle (bits) and PWM period (bits) for the VBUS boost assist PWM module. DS39897C-page 221 PIC24FJ256GB110 FAMILY 18.7.1 USB OTG MODULE CONTROL REGISTERS REGISTER 18-3: U1OTGSTAT: USB OTG STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0, HSC U-0 R-0, HSC U-0 R-0, HSC R-0, HSC U-0 R-0, HSC ID — LSTATE — SESVD SESEND — VBUSVD bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 ID: ID Pin State Indicator bit 1 = No plug is attached, or a type B cable has been plugged into the USB receptacle 0 = A type A plug has been plugged into the USB receptacle bit 6 Unimplemented: Read as ‘0’ bit 5 LSTATE: Line State Stable Indicator bit 1 = The USB line state (as defined by SE0 and JSTATE) has been stable for the previous 1 ms 0 = The USB line state has NOT been stable for the previous 1 ms bit 4 Unimplemented: Read as ‘0’ bit 3 SESVD: Session Valid Indicator bit 1 = The VBUS voltage is above VA_SESS_VLD (as defined in the USB OTG Specification) on the A or B-device 0 = The VBUS voltage is below VA_SESS_VLD on the A or B-device bit 2 SESEND: B-Session End Indicator bit 1 = The VBUS voltage is below VB_SESS_END (as defined in the USB OTG Specification) on the B-device 0 = The VBUS voltage is above VB_SESS_END on the B-device bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVD: A-VBUS Valid Indicator bit 1 = The VBUS voltage is above VA_VBUS_VLD (as defined in the USB OTG Specification) on the A-device 0 = The VBUS voltage is below VA_VBUS_VLD on the A-device DS39897C-page 222  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 18-4: U1OTGCON: USB ON-THE-GO CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 DPPULUP DMPULUP R/W-0 R/W-0 DPPULDWN(1) DMPULDWN(1) R/W-0 R/W-0 VBUSON(1) OTGEN(1) R/W-0 R/W-0 VBUSCHG(1) VBUSDIS(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 DPPULUP: D+ Pull-Up Enable bit 1 = D+ data line pull-up resistor enabled 0 = D+ data line pull-up resistor disabled bit 6 DMPULUP: D- Pull-Up Enable bit 1 = D- data line pull-up resistor enabled 0 = D- data line pull-up resistor disabled bit 5 DPPULDWN: D+ Pull-Down Enable bit(1) 1 = D+ data line pull-down resistor enabled 0 = D+ data line pull-down resistor disabled bit 4 DMPULDWN: D- Pull-Down Enable bit(1) 1 = D- data line pull-down resistor enabled 0 = D- data line pull-down resistor disabled bit 3 VBUSON: VBUS Power-on bit(1) 1 = VBUS line powered 0 = VBUS line not powered bit 2 OTGEN: OTG Features Enable bit(1) 1 = USB OTG enabled; all D+/D- pull-ups and pull-downs bits are enabled 0 = USB OTG disabled; D+/D- pull-ups and pull-downs are controlled in hardware by the settings of the HOSTEN and USBEN bits (U1CON) bit 1 VBUSCHG: VBUS Charge Select bit(1) 1 = VBUS line set to charge to 3.3V 0 = VBUS line set to charge to 5V bit 0 VBUSDIS: VBUS Discharge Enable bit(1) 1 = VBUS line discharged through a resistor 0 = VBUS line not discharged Note 1: These bits are only used in Host mode; do not use in Device mode.  2009 Microchip Technology Inc. DS39897C-page 223 PIC24FJ256GB110 FAMILY REGISTER 18-5: U1PWRC: USB POWER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0, HS U-0 U-0 UACTPND — — R/W-0 U-0 U-0 R/W-0, HC R/W-0 USLPGRD — — USUSPND USBPWR bit 7 bit 0 Legend: HS = Hardware Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 UACTPND: USB Activity Pending bit 1 = Module should not be suspended at the moment (requires USLPGRD bit to be set) 0 = Module may be suspended or powered down bit 6-5 Unimplemented: Read as ‘0’ bit 4 USLPGRD: Sleep/Suspend Guard bit 1 = Indicate to the USB module that it is about to be suspended or powered down 0 = No suspend bit 3-2 Unimplemented: Read as ‘0’ bit 1 USUSPND: USB Suspend Mode Enable bit 1 = USB OTG module is in Suspend mode; USB clock is gated and the transceiver is placed in a low-power state 0 = Normal USB OTG operation bit 0 USBPWR: USB Operation Enable bit 1 = USB OTG module is enabled 0 = USB OTG module is disabled(1) Note 1: Do not clear this bit unless the HOSTEN, USBEN and OTGEN bits (U1CON and U1OTGCON) are all cleared. DS39897C-page 224  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 18-6: U1STAT: USB STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC U-0 U-0 ENDPT3 ENDPT2 ENDPT1 ENDPT0 DIR PPBI(1) — — bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 ENDPT: Number of the Last Endpoint Activity bits (Represents the number of the BDT updated by the last USB transfer). 1111 = Endpoint 15 1110 = Endpoint 14 .... 0001 = Endpoint 1 0000 = Endpoint 0 bit 3 DIR: Last BD Direction Indicator bit 1 = The last transaction was a transmit transfer (Tx) 0 = The last transaction was a receive transfer (Rx) bit 2 PPBI: Ping-Pong BD Pointer Indicator bit(1) 1 = The last transaction was to the ODD BD bank 0 = The last transaction was to the EVEN BD bank bit 1-0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown This bit is only valid for endpoints with available EVEN and ODD BD registers.  2009 Microchip Technology Inc. DS39897C-page 225 PIC24FJ256GB110 FAMILY REGISTER 18-7: U1CON: USB CONTROL REGISTER (DEVICE MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R-x, HSC R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — SE0 PKTDIS — HOSTEN RESUME PPBRST USBEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6 SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero active on the USB bus 0 = No single-ended zero detected bit 5 PKTDIS: Packet Transfer Disable bit 1 = SIE token and packet processing disabled; automatically set when a SETUP token is received 0 = SIE token and packet processing enabled bit 4 Unimplemented: Read as ‘0’ bit 3 HOSTEN: Host Mode Enable bit 1 = USB host capability enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability disabled bit 2 RESUME: Resume Signaling Enable bit 1 = Resume signaling activated 0 = Resume signaling disabled bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the EVEN BD banks 0 = Ping-Pong Buffer Pointers not reset bit 0 USBEN: USB Module Enable bit 1 = USB module and supporting circuitry enabled (device attached); D+ pull-up is activated in hardware 0 = USB module and supporting circuitry disabled (device detached) DS39897C-page 226  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 18-8: U1CON: USB CONTROL REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-x, HSC R-x, HSC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE SE0 TOKBUSY USBRST HOSTEN RESUME PPBRST SOFEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 JSTATE: Live Differential Receiver J State Flag bit 1 = J state (differential ‘0’ in low speed, differential ‘1’ in full speed) detected on the USB 0 = No J state detected bit 6 SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero active on the USB bus 0 = No single-ended zero detected bit 5 TOKBUSY: Token Busy Status bit 1 = Token being executed by the USB module in On-The-Go state 0 = No token being executed bit 4 USBRST: Module Reset bit 1 = USB Reset has been generated; for software Reset, application must set this bit for 50 ms, then clear it 0 = USB Reset terminated bit 3 HOSTEN: Host Mode Enable bit 1 = USB host capability enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability disabled bit 2 RESUME: Resume Signaling Enable bit 1 = Resume signaling activated; software must set bit for 10 ms and then clear to enable remote wake-up 0 = Resume signaling disabled bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the EVEN BD banks 0 = Ping-Pong Buffer Pointers not reset bit 0 SOFEN: Start-Of-Frame Enable bit 1 = Start-Of-Frame token sent every one 1 millisecond 0 = Start-Of-Frame token disabled  2009 Microchip Technology Inc. DS39897C-page 227 PIC24FJ256GB110 FAMILY REGISTER 18-9: U1ADDR: USB ADDRESS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 (1) LSPDEN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 LSPDEN: Low-Speed Enable Indicator bit(1) 1 = USB module operates at low speed 0 = USB module operates at full speed bit 6-0 ADDR: USB Device Address bits Note 1: x = Bit is unknown Host mode only. In Device mode, this bit is unimplemented and read as ‘0’. REGISTER 18-10: U1TOK: USB TOKEN REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PID3 PID2 PID1 PID0 EP3 EP2 EP1 EP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 PID: Token Type Identifier bits 1101 = SETUP (TX) token type transaction(1) 1001 = IN (RX) token type transaction(1) 0001 = OUT (TX) token type transaction(1) bit 3-0 EP: Token Command Endpoint Address bits This value must specify a valid endpoint on the attached device. Note 1: x = Bit is unknown All other combinations are reserved and are not to be used. DS39897C-page 228  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 18-11: U-0 — bit 15 U1SOF: USB OTG START-OF-TOKEN THRESHOLD REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT7 bit 7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ CNT: Start-Of-Frame Size bits; Value represents 10 + (packet size of n bytes). For example: 0100 1010 = 64-byte packet 0010 1010 = 32-byte packet 0001 0010 = 8-byte packet REGISTER 18-12: U1CNFG1: USB CONFIGURATION REGISTER 1 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 15 bit 8 R/W-0 UTEYE bit 7 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 UOEMON(1) — USBSIDL — — PPB1 PPB0 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 bit 7 bit 6 bit 5 bit 4 bit 3-2 bit 1-0 Note 1: x = Bit is unknown Unimplemented: Read as ‘0’ UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test enabled 0 = Eye pattern test disabled UOEMON: USB OE Monitor Enable bit(1) 1 = OE signal active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal inactive Unimplemented: Read as ‘0’ USBSIDL: USB OTG Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as ‘0’ PPB: Ping-Pong Buffers Configuration bit 11 = EVEN/ODD ping-pong buffers enabled for Endpoints 1 to 15 10 = EVEN/ODD ping-pong buffers enabled for all endpoints 01 = EVEN/ODD ping-pong buffer enabled for OUT Endpoint 0 00 = EVEN/ODD ping-pong buffers disabled This bit is only active when the UTRDIS bit (U1CNFG2) is set.  2009 Microchip Technology Inc. DS39897C-page 229 PIC24FJ256GB110 FAMILY REGISTER 18-13: U1CNFG2: USB CONFIGURATION REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 — — — PUVBUS EXTI2CEN R/W-0 R/W-0 UVBUSDIS(1) UVCMPDIS(1) R/W-0 UTRDIS(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 PUVBUS: VBUS Pull-up Enable bit 1 = Pull-up on VBUS pin enabled 0 = Pull-up on VBUS pin disabled bit 3 EXTI2CEN: I2C™ Interface For External Module Control Enable bit 1 = External module(s) controlled via I2C interface 0 = External module(s) controller via dedicated pins bit 2 UVBUSDIS: On-Chip 5V Boost Regulator Builder Disable bit(1) 1 = On-chip boost regulator builder disabled; digital output control interface enabled 0 = On-chip boost regulator builder active bit 1 UVCMPDIS: On-Chip VBUS Comparator Disable bit(1) 1 = On-chip charge VBUS comparator disabled; digital input status interface enabled 0 = On-chip charge VBUS comparator active bit 0 UTRDIS: On-Chip Transceiver Disable bit(1) 1 = On-chip transceiver disabled; digital transceiver interface enabled 0 = On-chip transceiver active Note 1: Never change these bits while the USBPWR bit is set (U1PWRC = 1). DS39897C-page 230  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 18.7.2 USB INTERRUPT REGISTERS REGISTER 18-14: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS U-0 R/K-0, HS IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IDIF: ID State Change Indicator bit 1 = Change in ID state detected 0 = No ID state change bit 6 T1MSECIF: 1 Millisecond Timer bit 1 = The 1 millisecond timer has expired 0 = The 1 millisecond timer has not expired bit 5 LSTATEIF: Line State Stable Indicator bit 1 = USB line state (as defined by the SE0 and JSTATE bits) has been stable for 1 ms, but different from last time 0 = USB line state has not been stable for 1 ms bit 4 ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+/D- lines or VBUS detected 0 = No activity on the D+/D- lines or VBUS detected bit 3 SESVDIF: Session Valid Change Indicator bit 1 = VBUS has crossed VA_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END bit 2 SESENDIF: B-Device VBUS Change Indicator bit 1 = VBUS change on B-device detected; VBUS has crossed VB_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVDIF A-Device VBUS Change Indicator bit 1 = VBUS change on A-device detected; VBUS has crossed VA_VBUS_VLD (as defined in the USB OTG Specification)(1) 0 = No VBUS change on A-device detected Note 1: Note: VBUS threshold crossings may be either rising or falling. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.  2009 Microchip Technology Inc. DS39897C-page 231 PIC24FJ256GB110 FAMILY REGISTER 18-15: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 IDIE: ID Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 5 LSTATEIE: Line State Stable Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 4 ACTVIE: Bus Activity Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 3 SESVDIE: Session Valid Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 2 SESENDIE: B-Device Session End Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVDIE: A-Device VBUS Valid Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled DS39897C-page 232 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 18-16: U1IR: USB INTERRUPT STATUS REGISTER (DEVICE MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS U-0 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R-0 R/K-0, HS STALLIF — RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent bit 6 Unimplemented: Read as ‘0’ bit 5 RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for full speed) 0 = No K-state observed bit 4 IDLEIF: Idle Detect Interrupt bit 1 = Idle condition detected (constant Idle state of 3 ms or more) 0 = No Idle condition detected bit 3 TRNIF: Token Processing Complete Interrupt bit 1 = Processing of current token is complete; read U1STAT register for endpoint information 0 = Processing of current token not complete; clear U1STAT register or load next token from STAT (clearing this bit causes the STAT FIFO to advance) bit 2 SOFIF: Start-Of-Frame Token Interrupt bit 1 = A Start-Of-Frame token received by the peripheral or the Start-Of-Frame threshold reached by the host 0 = No Start-Of-Frame token received or threshold reached bit 1 UERRIF: USB Error Condition Interrupt bit (read-only) 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred bit 0 URSTIF: USB Reset Interrupt bit 1 = Valid USB Reset has occurred for at least 2.5 s; Reset state must be cleared before this bit can be reasserted 0 = No USB Reset has occurred. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.  2009 Microchip Technology Inc. DS39897C-page 233 PIC24FJ256GB110 FAMILY REGISTER 18-17: U1IR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R-0 R/K-0, HS STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF DETACHIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral device during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent bit 6 ATTACHIF: Peripheral Attach Interrupt bit 1 = A peripheral attachment has been detected by the module; set if the bus state is not SE0 and there has been no bus activity for 2.5 s 0 = No peripheral attachement detected bit 5 RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for full speed) 0 = No K-state observed bit 4 IDLEIF: Idle Detect Interrupt bit 1 = Idle condition detected (constant Idle state of 3 ms or more) 0 = No Idle condition detected bit 3 TRNIF: Token Processing Complete Interrupt bit 1 = Processing of current token is complete; read U1STAT register for endpoint information 0 = Processing of current token not complete; clear U1STAT register or load next token from U1STAT bit 2 SOFIF: Start-Of-Frame Token Interrupt bit 1 = A Start-Of-Frame token received by the peripheral or the Start-Of-Frame threshold reached by the host 0 = No Start-Of-Frame token received or threshold reached bit 1 UERRIF: USB Error Condition Interrupt bit 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred bit 0 DETACHIF: Detach Interrupt bit 1 = A peripheral detachment has been detected by the module; Reset state must be cleared before this bit can be reasserted 0 = No peripheral detachment detected. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. DS39897C-page 234  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 18-18: U1IE: USB INTERRUPT ENABLE REGISTER (ALL USB MODES) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 STALLIE ATTACHIE (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RESUMEIE IDLEIE TRNIE SOFIE UERRIE R/W-0 URSTIE DETACHIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 STALLIE: STALL Handshake Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 6 ATTACHIE: Peripheral Attach Interrupt bit (Host mode only)(1) 1 = Interrupt enabled 0 = Interrupt disabled bit 5 RESUMEIE: Resume Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled bit 4 IDLEIE: Idle Detect Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled bit 3 TRNIE: Token Processing Complete Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled bit 2 SOFIE: Start-of-Frame Token Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled bit 1 UERRIE: USB Error Condition Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled bit 0 URSTIE or DETACHIE: USB Reset Interrupt (Device mode) or USB Detach Interrupt (Host mode) Enable bit 1 = Interrupt enabled 0 = Interrupt disabled Note 1: Unimplemented in Device mode, read as ‘0’.  2009 Microchip Technology Inc. DS39897C-page 235 PIC24FJ256GB110 FAMILY REGISTER 18-19: U1EIR: USB ERROR INTERRUPT STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS U-0 BTSEF — R/K-0, HS DMAEF R/K-0, HS R/K-0, HS BTOEF DFN8EF R/K-0, HS CRC16EF R/K-0, HS CRC5EF EOFEF R/K-0, HS PIDEF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 BTSEF: Bit Stuff Error Flag bit 1 = Bit stuff error has been detected 0 = No bit stuff error bit 6 Unimplemented: Read as ‘0’ bit 5 DMAEF: DMA Error Flag bit 1 = A USB DMA error condition detected; the data size indicated by the BD byte count field is less than the number of received bytes. The received data is truncated. 0 = No DMA error bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out bit 3 DFN8EF: Data Field Size Error Flag bit 1 = Data field was not an integral number of bytes 0 = Data field was an integral number of bytes bit 2 CRC16EF: CRC16 Failure Flag bit 1 = CRC16 failed 0 = CRC16 passed bit 1 For Device mode: CRC5EF: CRC5 Host Error Flag bit 1 = Token packet rejected due to CRC5 error 0 = Token packet accepted (no CRC5 error) For Host mode: EOFEF: End-Of-Frame Error Flag bit 1 = End-Of-Frame error has occurred 0 = End-Of-Frame interrupt disabled bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. DS39897C-page 236  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 18-20: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 U-0 BTSEE R/W-0 — DMAEE R/W-0 R/W-0 BTOEE DFN8EE R/W-0 CRC16EE R/W-0 CRC5EE EOFEE R/W-0 PIDEE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 6 Unimplemented: Read as ‘0’ bit 5 DMAEE: DMA Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 1 For Device mode: CRC5EE: CRC5 Host Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled For Host mode: EOFEE: End-of-Frame Error interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 0 PIDEE: PID Check Failure Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 237 PIC24FJ256GB110 FAMILY 18.7.3 USB ENDPOINT MANAGEMENT REGISTERS REGISTER 18-21: U1EPn: USB ENDPOINT CONTROL REGISTERS (n = 0 TO 15) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPD(1) RETRYDIS(1) — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 LSPD: Low-Speed Direct Connection Enable bit (U1EP0 only)(1) 1 = Direct connection to a low-speed device enabled 0 = Direct connection to a low-speed device disabled bit 6 RETRYDIS: Retry Disable bit (U1EP0 only)(1) 1 = Retry NAK transactions disabled 0 = Retry NAK transactions enabled; retry done in hardware bit 5 Unimplemented: Read as ‘0’ bit 4 EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN and EPRXEN = 1: 1 = Disable Endpoint n from Control transfers; only Tx and Rx transfers allowed 0 = Enable Endpoint n for Control (SETUP) transfers; Tx and Rx transfers also allowed. For all other combinations of EPTXEN and EPRXEN: This bit is ignored. bit 3 EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive enabled 0 = Endpoint n receive disabled bit 2 EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit enabled 0 = Endpoint n transmit disabled bit 1 EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled bit 0 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake enabled 0 = Endpoint handshake disabled (typically used for isochronous endpoints) Note 1: These bits are available only for U1EP0, and only in Host mode. For all other U1EPn registers, these bits are always unimplemented and read as ‘0’. DS39897C-page 238  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 18.7.4 USB VBUS POWER CONTROL REGISTER REGISTER 18-22: U1PWMCON: USB VBUS PWM GENERATOR CONTROL REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 PWMEN — — — — — PWMPOL CNTEN bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWMEN: PWM Enable bit 1 = PWM generator is enabled 0 = PWM generator is disabled; output is held in Reset state specified by PWMPOL bit 14-10 Unimplemented: Read as ‘0’ bit 9 PWMPOL: PWM Polarity bit 1 = PWM output is active-low and resets high 0 = PWM output is active-high and resets low bit 8 CNTEN: PWM Counter Enable bit 1 = Counter is enabled 0 = Counter is disabled bit 7-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. DS39897C-page 239 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 240  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 19.0 Note: PARALLEL MASTER PORT (PMP) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 13. “Parallel Master Port (PMP)” (DS39713). The Parallel Master Port (PMP) module is a parallel 8-bit I/O module, specifically designed to communicate with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP is highly configurable. FIGURE 19-1: Key features of the PMP module include: • Up to 16 Programmable Address Lines • Up to 2 Chip Select Lines • Programmable Strobe Options: - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe • Address Auto-Increment/Auto-Decrement • Programmable Address/Data Multiplexing • Programmable Polarity on Control Signals • Legacy Parallel Slave Port Support • Enhanced Parallel Slave Support: - Address Support - 4-Byte Deep Auto-Incrementing Buffer • Programmable Wait States • Selectable Input Voltage Levels PMP MODULE OVERVIEW Address Bus Data Bus Control Lines PIC24F Parallel Master Port PMA PMALL PMA PMALH PMA Up to 16-Bit Address EEPROM PMA PMCS1 PMA PMCS2 PMBE PMRD PMRD/PMWR Microcontroller LCD FIFO Buffer PMWR PMENB PMD PMA PMA  2009 Microchip Technology Inc. 8-Bit Data DS39897C-page 241 PIC24FJ256GB110 FAMILY REGISTER 19-1: PMCON: PARALLEL PORT CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0(1) R/W-0(1) R/W-0 R/W-0 R/W-0 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN bit 15 bit 8 R/W-0 R/W-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PMPEN: Parallel Master Port Enable bit 1 = PMP enabled 0 = PMP disabled, no off-chip access performed bit 14 Unimplemented: Read as ‘0’ bit 13 PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 ADRMUX: Address/Data Multiplexing Selection bits(1) 11 = Reserved 10 = All 16 bits of address are multiplexed on PMD pins 01 = Lower 8 bits of address are multiplexed on PMD pins, upper 3 bits are multiplexed on PMA 00 = Address and data appear on separate pins bit 10 PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode) 1 = PMBE port enabled 0 = PMBE port disabled bit 9 PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled bit 8 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled bit 7-6 CSF1:CSF0: Chip Select Function bits 11 = Reserved 10 = PMCS1 and PMCS2 function as chip select 01 = PMCS2 functions as chip select, PMCS1 functions as address bit 14 00 = PMCS1 and PMCS2 function as address bits 15 and 14 bit 5 ALP: Address Latch Polarity bit(1) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 4 CS2P: Chip Select 2 Polarity bit(1) 1 = Active-high (PMCS2/PMCS2) 0 = Active-low (PMCS2/PMCS2) bit 3 CS1P: Chip Select 1 Polarity bit(1) 1 = Active-high (PMCS1/PMCS1) 0 = Active-low (PMCS1/PMCS1) Note 1: These bits have no effect when their corresponding pins are used as address lines. DS39897C-page 242  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 19-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 2 BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) bit 1 WRSP: Write Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (PMMODE = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 0 RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE = 00,01,10): 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master mode 1 (PMMODE = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines.  2009 Microchip Technology Inc. DS39897C-page 243 PIC24FJ256GB110 FAMILY REGISTER 19-2: PMMODE: PARALLEL PORT MODE REGISTER R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAITB1(1) WAITB0(1) WAITM3 WAITM2 WAITM1 WAITM0 WAITE1(1) WAITE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 BUSY: Busy bit (Master mode only) 1 = Port is busy (not useful when the processor stall is active) 0 = Port is not busy bit 14-13 IRQM: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA = 11 (Addressable PSP mode only) 10 = No interrupt generated, processor stall activated 01 = Interrupt generated at the end of the read/write cycle 00 = No interrupt generated bit 12-11 INCM: Increment Mode bits 11 = PSP read and write buffers auto-increment (Legacy PSP mode only) 10 = Decrement ADDR by 1 every read/write cycle 01 = Increment ADDR by 1 every read/write cycle 00 = No increment or decrement of address bit 10 MODE16: 8/16-Bit Mode bit 1 = 16-bit mode: Data register is 16 bits, a read or write to the Data register invokes two 8-bit transfers 0 = 8-bit mode: Data register is 8 bits, a read or write to the Data register invokes one 8-bit transfer bit 9-8 MODE: Parallel Port Mode Select bits 11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA and PMD) 10 = Master mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA and PMD) 01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD and PMA) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD) bit 7-6 WAITB: Data Setup to Read/Write Wait State Configuration bits(1) 11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY 10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY 01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY 00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY bit 5-2 WAITM: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TCY ... 0001 = Wait of additional 1 TCY 0000 = No additional wait cycles (operation forced into one TCY)(2) bit 1-0 WAITE: Data Hold After Strobe Wait State Configuration bits(1) 11 = Wait of 4 TCY 10 = Wait of 3 TCY 01 = Wait of 2 TCY 00 = Wait of 1 TCY Note 1: 2: The WAITB and WAITE bits are ignored whenever WAITM = 0000. A single-cycle delay is required between consecutive read and/or write operations. DS39897C-page 244  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 19-3: PMADDR: PARALLEL PORT ADDRESS REGISTER R/W-0 R/W-0 CS2 CS1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CS2: Chip Select 2 bit 1 = Chip select 2 is active 0 = Chip select 2 is inactive bit 14 CS1: Chip Select 1 bit 1 = Chip select 1 is active 0 = Chip select 1 is inactive bit 13-0 ADDR: Parallel Port Destination Address bits REGISTER 19-4: x = Bit is unknown PMAEN: PARALLEL PORT ENABLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 PTEN: PMCSx Strobe Enable bit 1 = PMA15 and PMA14 function as either PMA or PMCS2 and PMCS1 0 = PMA15 and PMA14 function as port I/O bit 13-2 PTEN: PMP Address Port Enable bits 1 = PMA function as PMP address lines 0 = PMA function as port I/O bit 1-0 PTEN: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O  2009 Microchip Technology Inc. DS39897C-page 245 PIC24FJ256GB110 FAMILY REGISTER 19-5: PMSTAT: PARALLEL PORT STATUS REGISTER R-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV — — IB3F IB2F IB1F IB0F bit 15 bit 8 R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty bit 14 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte register occurred (must be cleared in software) 0 = No overflow occurred bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 IB3F:IB0F Input Buffer x Status Full bits 1 = Input buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input buffer does not contain any unread data bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bits 1 = A read occurred from an empty output byte register (must be cleared in software) 0 = No underflow occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 OB3E:OB0E Output Buffer x Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted DS39897C-page 246  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 19-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — U-0 — — U-0 — U-0 — U-0 — R/W-0 R/W-0 (1) RTSECSEL PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = PMP module inputs use Schmitt Trigger input buffers Note 1: x = Bit is unknown To enable the actual RTCC output, the RTCOE (RCFGCAL)) bit must also be set.  2009 Microchip Technology Inc. DS39897C-page 247 PIC24FJ256GB110 FAMILY FIGURE 19-2: LEGACY PARALLEL SLAVE PORT EXAMPLE Master PIC24F Slave PMD FIGURE 19-3: PMD PMCS1 PMCS1 PMRD PMRD PMWR PMWR Address Bus Data Bus Control Lines ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE Master PIC24F Slave PMA PMA PMD PMD Write Address Decode Read Address Decode PMDOUT1L (0) PMDIN1L (0) PMCS1 PMCS1 PMDOUT1H (1) PMDIN1H (1) PMRD PMRD PMDOUT2L (2) PMDIN2L (2) PMWR PMWR PMDOUT2H (3) PMDIN2H (3) Address Bus Data Bus Control Lines TABLE 19-1: SLAVE MODE ADDRESS RESOLUTION PMA Output Register (Buffer) Input Register (Buffer) 00 PMDOUT1 (0) PMDIN1 (0) 01 PMDOUT1 (1) PMDIN1 (1) 10 PMDOUT2 (2) PMDIN2 (2) 11 PMDOUT2 (3) PMDIN2 (3) FIGURE 19-4: MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC24F PMA PMD PMCS1 PMCS2 DS39897C-page 248 Address Bus PMRD Data Bus PMWR Control Lines  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY FIGURE 19-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC24F PMA PMD PMA PMCS1 Address Bus PMCS2 Multiplexed Data and Address Bus PMALL PMRD Control Lines PMWR FIGURE 19-6: MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PMD PMA PIC24F PMCS1 PMCS2 PMALL PMALH Multiplexed Data and Address Bus PMRD Control Lines PMWR FIGURE 19-7: EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD PMALL 373 A D 373 PMALH A A D CE OE WR PMCS1 FIGURE 19-8: Address Bus PMRD Data Bus PMWR Control Lines EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD 373 PMALL PMA PMCS1 PMRD PMWR  2009 Microchip Technology Inc. A D A A D CE OE WR Address Bus Data Bus Control Lines DS39897C-page 249 PIC24FJ256GB110 FAMILY FIGURE 19-9: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC24F Parallel Peripheral PMD PMALL AD ALE PMCS1 CS Address Bus PMRD RD Data Bus PMWR WR Control Lines FIGURE 19-10: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA) PIC24F PMA Parallel EEPROM A PMD D PMCS1 CE PMRD OE PMWR WR FIGURE 19-11: Address Bus Data Bus Control Lines PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA) PIC24F Parallel EEPROM PMA A PMD D PMBE A0 PMCS1 CE PMRD OE PMWR WR FIGURE 19-12: Address Bus Data Bus Control Lines LCD CONTROL EXAMPLE (BYTE MODE OPERATION) PIC24F PM PMA0 PMRD/PMWR PMCS1 LCD Controller D RS R/W E Address Bus Data Bus Control Lines DS39897C-page 250  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 20.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) Key features include: • Time data in hours, minutes and seconds, with a granularity of one-half second • 24-hour format (Military Time) display option • Calendar data as date, month and year • Automatic, hardware-based day of the week and leap year calculations for dates from 2000 through 2099 • Time and calendar data in BCD format for _compact firmware • Highly configurable alarm function • External output pin with selectable alarm signal or seconds “tick” signal output • User calibration feature with auto-adjust This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 29. “Real-Time Clock and Calendar (RTCC)” (DS39696). The Real-Time Clock and Calendar (RTCC) provides on-chip, hardware-based clock and calendar functionality with little or no CPU overhead. It is intended for applications where accurate time must be maintained for extended periods with minimal CPU activity and with limited power resources, such as battery-powered applications. FIGURE 20-1: A simplified block diagram of the module is shown in Figure 20-1. The SOSC and RTCC will both remain running while the device is held in Reset with MCLR and will continue running after MCLR is released. RTCC BLOCK DIAGRAM RTCC Clock Domain 32.768 kHz Input from SOSC Oscillator CPU Clock Domain RCFGCAL RTCC Prescalers ALCFGRPT YEAR 0.5s RTCC Timer Alarm Event MTHDY RTCVAL WKDYHR MINSEC Comparator ALMTHDY Compare Registers with Masks ALRMVAL ALWDHR ALMINSEC Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE  2009 Microchip Technology Inc. DS39897C-page 251 PIC24FJ256GB110 FAMILY 20.1 RTCC Module Registers TABLE 20-2: The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 20.1.1 00 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL) to select the desired Timer register pair (see Table 20-1). By writing the RTCVALH byte, the RTCC Pointer value, RTCPTR bits, decrement by one until they reach ‘00’. Once they reach ‘00’, the MINUTES and SECONDS value will be accessible through RTCVALH and RTCVALL until the pointer value is manually changed. TABLE 20-1: RTCPTR ALRMPTR RTCVAL REGISTER MAPPING RTCC Value Register Window RTCVAL RTCVAL 00 MINUTES SECONDS 01 WEEKDAY HOURS 10 MONTH DAY 11 — YEAR The Alarm Value register window (ALRMVALH and ALRMVALL) uses the ALRMPTR bits (ALCFGRPT) to select the desired Alarm register pair (see Table 20-2). ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMVAL ALRMVAL ALRMMIN ALRMSEC 01 ALRMWD ALRMHR 10 ALRMMNTH ALRMDAY 11 — — Considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the ALRMVALH or ALRMVALL bytes will decrement the ALRMPTR value. The same applies to the RTCVALH or RTCVALL bytes with the RTCPTR being decremented. Note: 20.1.2 This only applies to read operations and not write operations. WRITE LOCK In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RCFGCAL) must be set (refer to Example 20-1). Note: To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL) is kept clear at any other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed between the unlock sequence and the setting of RTCWREN; therefore, it is recommended that code follow the procedure in Example 20-1. For applications written in C, the unlock sequence should be implemented using in-line assembly. By writing the ALRMVALH byte, the Alarm Pointer value, ALRMPTR bits, decrement by one until they reach ‘00’. Once they reach ‘00’, the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed. EXAMPLE 20-1: SETTING THE RTCWREN BIT __builtin_write_RTCWEN(); //set the RTCWREN bit DS39897C-page 252  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 20.1.3 RTCC CONTROL REGISTERS RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) REGISTER 20-1: R/W-0 RTCEN U-0 (2) R/W-0 — RTCWREN R-0 RTCSYNC R-0 (3) HALFSEC R/W-0 R/W-0 R/W-0 RTCOE RTCPTR1 RTCPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple bit 11 HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second bit 10 RTCOE: RTCC Output Enable bit 1 = RTCC output enabled 0 = RTCC output disabled bit 9-8 RTCPTR: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers; the RTCPTR value decrements on every read or write of RTCVALH until it reaches ‘00’. RTCVAL: 00 = MINUTES 01 = WEEKDAY 10 = MONTH 11 = Reserved RTCVAL: 00 = SECONDS 01 = HOURS 10 = DAY 11 = YEAR Note 1: 2: 3: The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.  2009 Microchip Technology Inc. DS39897C-page 253 PIC24FJ256GB110 FAMILY REGISTER 20-1: bit 7-0 Note 1: 2: 3: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) CAL: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute ... 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute ... 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register. REGISTER 20-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RTSECSEL(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = PMP module inputs use Schmitt Trigger input buffers Note 1: x = Bit is unknown To enable the actual RTCC output, the RTCOE (RCFGCAL)) bit must also be set. DS39897C-page 254  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 20-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT = 00h and CHIME = 0) 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit 1 = Chime is enabled; ARPT bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT bits stop once they reach 00h bit 13-10 AMASK: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every 4 years) 101x = Reserved – do not use 11xx = Reserved – do not use bit 9-8 ALRMPTR: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers; the ALRMPTR value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVAL: 00 = ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = Unimplemented ALRMVAL: 00 = ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = Unimplemented bit 7-0 ARPT: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times ... 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1.  2009 Microchip Technology Inc. DS39897C-page 255 PIC24FJ256GB110 FAMILY 20.1.4 RTCVAL REGISTER MAPPINGS YEAR: YEAR VALUE REGISTER(1) REGISTER 20-4: U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 YRTEN: Binary Coded Decimal Value of Year’s Tens Digit bits Contains a value from 0 to 9. bit 3-0 YRONE: Binary Coded Decimal Value of Year’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to the YEAR register is only allowed when RTCWREN = 1. REGISTER 20-5: MTHDY: MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. bit 11-8 MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: x = Bit is unknown A write to this register is only allowed when RTCWREN = 1. DS39897C-page 256  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) REGISTER 20-6: U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN = 1. REGISTER 20-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 257 PIC24FJ256GB110 FAMILY 20.1.5 ALRMVAL REGISTER MAPPINGS REGISTER 20-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. bit 11-8 MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: x = Bit is unknown A write to this register is only allowed when RTCWREN = 1. DS39897C-page 258  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1) REGISTER 20-9: U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN = 1. REGISTER 20-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 259 PIC24FJ256GB110 FAMILY 20.2 Calibration The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses for one minute and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value loaded into the lower half of RCFGCAL is multiplied by four and will either be added or subtracted from the RTCC timer, once every minute. Refer to the steps below for RTCC calibration: 1. 2. Using another timer resource on the device, the user must find the error of the 32.768 kHz crystal. Once the error is known, it must be converted to the number of error clock pulses per minute and loaded into the RCFGCAL register. EQUATION 20-1: RTCC CALIBRATION Error (clocks per minute) =(Ideal Frequency† – Measured Frequency) * 60 † Ideal frequency = 32,768 Hz 3. a) If the oscillator is faster then ideal (negative result form step 2), the RCFGCAL register value needs to be negative. This causes the specified number of clock pulses to be substract from the timer counter once every minute. b) If the oscillator is slower then ideal (positive result from step 2) the RCFGCAL register value needs to be positive. This causes the specified number of clock pulses to be added to the timer counter once every minute. 4. Divide the number of error clocks per minute by 4 to get the correct CAL value and load the RCFGCAL register with the correct value. (Each 1-bit increment in CAL adds or subtracts 4 pulses). Writes to the lower half of the RCFGCAL register should only occur when the timer is turned off, or immediately after the rising edge of the seconds pulse. Note: It is up to the user to include, in the error value, the initial error of the crystal, drift due to temperature and drift due to crystal aging. DS39897C-page 260 20.3 Alarm • Configurable from half second to one year • Enabled using the ALRMEN bit (ALCFGRPT, Register 20-3) • One-time alarm and repeat alarm options available 20.3.1 CONFIGURING THE ALARM The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. Writes to ALRMVAL should only take place when ALRMEN = 0. As shown in Figure 20-2, the interval selection of the alarm is configured through the AMASK bits (ALCFGRPT). These bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. The alarm can also be configured to repeat based on a preconfigured interval. The amount of times this occurs once the alarm is enabled is stored in the ARPT bits, ARPT (ALCFGRPT). When the value of the ARPT bits equals 00h and the CHIME bit (ALCFGRPT) is cleared, the repeat function is disabled and only a single alarm will occur. The alarm can be repeated up to 255 times by loading ARPT with FFh. After each alarm is issued, the value of the ARPT bits is decremented by one. Once the value has reached 00h, the alarm will be issued one last time, after which the ALRMEN bit will be cleared automatically and the alarm will turn off. Indefinite repetition of the alarm can occur if the CHIME bit = 1. Instead of the alarm being disabled when the value of the ARPT bits reaches 00h, it rolls over to FFh and continues counting indefinitely while CHIME is set. 20.3.2 ALARM INTERRUPT At every alarm event, an interrupt is generated. In addition, an alarm pulse output is provided that operates at half the frequency of the alarm. This output is completely synchronous to the RTCC clock and can be used as a trigger clock to other peripherals. Note: Changing any of the registers, other then the RCFGCAL and ALCFGRPT registers and the CHIME bit while the alarm is enabled (ALRMEN = 1), can result in a false alarm event leading to a false alarm interrupt. To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0). It is recommended that the ALCFGRPT register and CHIME bit be changed when RTCSYNC = 0.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY FIGURE 20-2: ALARM MASK SETTINGS Alarm Mask Setting (AMASK) Day of the Week Month Day Hours Minutes Seconds 0000 – Every half second 0001 – Every second 0010 – Every 10 seconds s 0011 – Every minute s s m s s m m s s 0100 – Every 10 minutes 0101 – Every hour 0110 – Every day 0111 – Every week d 1000 – Every month 1001 – Every year(1) Note 1: m m h h m m s s h h m m s s d d h h m m s s d d h h m m s s Annually, except when configured for February 29.  2009 Microchip Technology Inc. DS39897C-page 261 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 262  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 21.0 Note: PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR Consider the CRC equation: x16 + x12 + x5 + 1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 30. “Programmable Cyclic Redundancy Check (CRC)” (DS39714). The programmable CRC generator offers the following features: • User-programmable polynomial CRC equation • Interrupt output • Data FIFO The module implements a software configurable CRC generator. The terms of the polynomial and its length can be programmed using the X bits (CRCXOR) and the PLEN bits (CRCCON), respectively. FIGURE 21-1: To program this polynomial into the CRC generator, the CRC register bits should be set as shown in Table 21-1. TABLE 21-1: EXAMPLE CRC SETUP Bit Name Bit Value PLEN 1111 X 000100000010000 Note that for the value of X, the 12th bit and the 5th bit are set to ‘1’, as required by the equation. The 0 bit required by the equation is always XORed. For a 16-bit polynomial, the 16th bit is also always assumed to be XORed; therefore, the X bits do not have the 0 bit or the 16th bit. A simplified block diagram of the module is shown in Figure 21-1. The general topology of the shift engine is shown in Figure 21-2. CRC BLOCK DIAGRAM CRCDAT Variable FIFO (8x16 or 16x8) Shift Clock (2FCY) FIFO Empty Event Set CRCIF CRC Shift Engine CRCWDAT  2009 Microchip Technology Inc. DS39897C-page 263 PIC24FJ256GB110 FAMILY FIGURE 21-2: CRC SHIFT ENGINE DETAIL CRCWDAT Read/Write Bus X(1)(1) Shift Buffer Data Note 1: 2: 21.1 21.1.1 Bit 0 X(n)(1) X(2)(1) Bit 1 Bit n(2) Bit 2 Each XOR stage of the shift engine is programmable. See text for details. Polynomial length n is determined by ([PLEN] + 1) User Interface DATA INTERFACE To start serial shifting, a ‘1’ must be written to the CRCGO bit. The module incorporates a FIFO that is 8 deep when PLEN (CRCCON) > 7, and 16 deep, otherwise. The data for which the CRC is to be calculated must first be written into the FIFO. The smallest data element that can be written into the FIFO is one byte. For example, if PLEN = 5, then the size of the data is PLEN + 1 = 6. When loading data, the two MSbs of the data byte are ignored. Once data is written into the CRCWDAT MSb (as defined by PLEN), the value of VWORD (CRCCON) increments by one. When CRCGO = 1 and VWORD > 0, a word of data to be shifted is moved from the FIFO into the shift engine. When the data word moves from the FIFO to the shift engine, VWORD decrements by one. The serial shifter continues to receive data from the FIFO, shifting until the VWORD reaches 0. The last bit of data will be shifted through the CRC module (PLEN + 1)/2 clock cycles after VWORD reaches 0. This is when the module is completed with the CRC calculation. To empty words already written into a FIFO, the CRCGO bit must be set to ‘1’ and the CRC shifter allowed to run until the CRCMPT bit is set. Also, to get the correct CRC reading, it will be necessary to wait for the CRCMPT bit to go high before reading the CRCWDAT register. If a word is written when the CRCFUL bit is set, the VWORD Pointer will roll over to 0. The hardware will then behave as if the FIFO is empty. However, the condition to generate an interrupt will not be met; therefore, no interrupt will be generated (See Section 21.1.2 “Interrupt Operation”). At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORD bits is done. 21.1.2 INTERRUPT OPERATION When the VWORD bits make a transition from a value of ‘1’ to ‘0’, an interrupt will be generated. Note that the CRC calculation is not complete at this point; an additional time of (PLEN + 1)/2 clock cycles is required before the output can be read. 21.2 21.2.1 Operation in Power-Saving Modes SLEEP MODE Therefore, for a given value of PLEN, it will take (PLEN + 1)/2 * VWORD number of clock cycles to complete the CRC calculations. If Sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes. When VWORD reaches 8 (or 16), the CRCFUL bit will be set. When VWORD reaches 0, the CRCMPT bit will be set. 21.2.2 To continually feed data into the CRC engine, the recommended mode of operation is to initially “prime” the FIFO with a sufficient number of words so no interrupt is generated before the next word can be written. Once that is done, start the CRC by setting the CRCGO bit to ‘1’. From that point onward, the VWORD bits should be polled. If they read less than 8 or 16, another word can be written into the FIFO. DS39897C-page 264 IDLE MODE To continue full module operation in Idle mode, the CSIDL bit must be cleared prior to entry into the mode. If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 21.3 Registers There are four registers used to control programmable CRC operation: • • • • CRCCON CRCXOR CRCDAT CRCWDAT REGISTER 21-1: CRCCON: CRC CONTROL REGISTER U-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0 — — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 bit 8 R-0 R-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CRCFUL CRCMPT — CRCGO PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-8 VWORD: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN > 7, or 16 when PLEN 7. bit 7 CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: FIFO Empty Bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 Unimplemented: Read as ‘0’ bit 4 CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter turned off bit 3-0 PLEN: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1.  2009 Microchip Technology Inc. DS39897C-page 265 PIC24FJ256GB110 FAMILY REGISTER 21-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X15 X14 X13 X12 X11 X10 X9 X8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 X7 X6 X5 X4 X3 X2 X1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 X: XOR of Polynomial Term Xn Enable bits bit 0 Unimplemented: Read as ‘0’ DS39897C-page 266 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 22.0 Note: 10-BIT HIGH-SPEED A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 17. “10-Bit A/D Converter” (DS39705). A block diagram of the A/D Converter is shown in Figure 22-1. To perform an A/D conversion: 1. The 10-bit A/D Converter has the following key features: • • • • • • • • • • • Successive Approximation (SAR) conversion Conversion speeds of up to 500 ksps 16 analog input pins External voltage reference input pins Internal band gap reference inputs Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer Selectable Buffer Fill modes Four result alignment options Operation during CPU Sleep and Idle modes 2. Configure the A/D module: a) Configure port pins as analog inputs and/or select band gap reference inputs (AD1PCFGL and AD1PCFGH). b) Select voltage reference source to match expected range on analog inputs (AD1CON2). c) Select the analog conversion clock to match desired data rate with processor clock (AD1CON3). d) Select the appropriate sample/conversion sequence (AD1CON1 and AD1CON3). e) Select how conversion results are presented in the buffer (AD1CON1). f) Select interrupt rate (AD1CON2). g) Turn on A/D module (AD1CON1). Configure A/D interrupt (if required): a) Clear the AD1IF bit. b) Select A/D interrupt priority. On all PIC24FJ256GB110 family devices, the 10-bit A/D Converter has 16 analog input pins, designated AN0 through AN15. In addition, there are two analog input pins for external voltage reference connections (VREF+ and VREF-). These voltage reference inputs may be shared with other analog input pins.  2009 Microchip Technology Inc. DS39897C-page 267 PIC24FJ256GB110 FAMILY FIGURE 22-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVSS VREF+ VR Select AVDD VR+ 16 VR- VREF- Comparator VINH AN0 VINL VRS/H VR+ DAC AN1 AN2 AN5 MUX A AN4 10-Bit SAR VINH AN3 Conversion Logic Data Formatting AN6 VINL AN7 ADC1BUF0: ADC1BUFF AN8 AN9 AD1CON1 AD1CON2 AD1CON3 AD1CHS AD1PCFGL AN10 AN12 AN13 AN14 MUX B AN11 VINH AD1PCFGH AD1CSSL VINL AN15 VBG VBG/2 DS39897C-page 268 Sample Control Control Logic Conversion Control Input MUX Control Pin Config Control  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ADON(1) — ADSIDL — — — FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HCS R/W-0, HCS SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE bit 7 bit 0 Legend: HCS = Hardware Clearable/Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: A/D Operating Mode bit(1) 1 = A/D Converter module is operating 0 = A/D Converter is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 FORM: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) bit 7-5 SSRC: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = CTMU event ends sampling and starts conversion 101 = Reserved 100 = Timer5 compare ends sampling and starts conversion 011 = Reserved 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion bit 4-3 Unimplemented: Read as ‘0’ bit 2 ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes. SAMP bit is auto-set. 0 = Sampling begins when SAMP bit is set bit 1 SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done Note 1: Values of ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out the conversion values from the buffer before disabling the module.  2009 Microchip Technology Inc. DS39897C-page 269 PIC24FJ256GB110 FAMILY REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 r-0 U-0 R/W-0 U-0 U-0 VCFG2 VCFG1 VCFG0 r — CSCNA — — bit 15 bit 8 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit r = Reserved bit’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x = Bit is unknown VCFG: Voltage Reference Configuration bits VCFG VR+ VR- 000 AVDD AVSS 001 External VREF+ pin AVSS 010 AVDD External VREF- pin 011 External VREF+ pin External VREF- pin 1xx AVDD AVSS bit 12 Reserved: Maintain as ‘0’ bit 11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs bit 9-8 Unimplemented: Read as ‘0’ bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = A/D is currently filling buffer, 08-0F, user should access data in 00-07 0 = A/D is currently filling buffer, 00-07, user should access data in 08-0F bit 6 Unimplemented: Read as ‘0’ bit 5-2 SMPI: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence ..... 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence bit 1 BUFM: Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers (ADC1BUFn and ADC1BUFn) 0 = Buffer configured as one 16-word buffer (ADC1BUFn) bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always uses MUX A input multiplexer settings DS39897C-page 270  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 22-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 r-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC r r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock derived from system clock bit 14-13 Reserved: Maintain as ‘0’ bit 12-8 SAMC: Auto-Sample Time bits 11111 = 31 TAD ····· 00001 = 1 TAD 00000 = 0 TAD (not recommended) bit 7-0 ADCS: A/D Conversion Clock Select bits 11111111 ······ = Reserved, do not use 01000000 00111111 = 64 TCY 00111110 = 63 TCY ······ 00000001 = 2*TCY 00000000 = TCY  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 271 PIC24FJ256GB110 FAMILY REGISTER 22-4: R/W-0 AD1CHS: A/D INPUT SELECT REGISTER U-0 CH0NB — U-0 — R/W-0 R/W-0 (1) CH0SB4 CH0SB3 R/W-0 (1) R/W-0 (1) CH0SB2 CH0SB1 R/W-0 (1) CH0SB0(1) bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VR- bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits(1) 10001 = Channel 0 positive input is internal band gap reference (VBG)(2) 10000 = Channel 0 positive input is VBG/2(2) 01111 = Channel 0 positive input is AN15 01110 = Channel 0 positive input is AN14 01101 = Channel 0 positive input is AN13 01100 = Channel 0 positive input is AN12 01011 = Channel 0 positive input is AN11 01010 = Channel 0 positive input is AN10 01001 = Channel 0 positive input is AN9 01000 = Channel 0 positive input is AN8 00111 = Channel 0 positive input is AN7 00110 = Channel 0 positive input is AN6 00101 = Channel 0 positive input is AN5 00100 = Channel 0 positive input is AN4 00011 = Channel 0 positive input is AN3 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VR- bit 6-5 Unimplemented: Read as ‘0’ bit 4-0 CH0SA: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits Implemented combinations are identical to those for CHOSB (above). Note 1: 2: Combinations, ‘10010’ through ‘11111’, are unimplemented; do not use. Band gap reference must be allowed to stabilize (parameter TBG) before using these channels for a conversion. See Section 29.1 “DC Characteristics” for more information. DS39897C-page 272  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 22-5: AD1PCFGL: A/D PORT CONFIGURATION REGISTER (LOW) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PCFG: Analog Input Pin Configuration Control bits 1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled 0 = Pin configured in Analog mode; I/O port read disabled, A/D samples pin voltage REGISTER 22-6: AD1PCFGH: A/D PORT CONFIGURATION REGISTER (HIGH) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — PCFG17 PCFG16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 PCFG17: A/D Input Configuration Control bit 1 = Analog channel disabled from input scan 0 = Internal band gap (VBG) channel enabled for input scan bit 0 PCFG16: A/D Input Configuration Control bit 1 = Analog channel disabled from input scan 0 = Internal VBG/2 channel enabled for input scan  2009 Microchip Technology Inc. x = Bit is unknown DS39897C-page 273 PIC24FJ256GB110 FAMILY REGISTER 22-7: AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown CSSL: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan EQUATION 22-1: A/D CONVERSION CLOCK PERIOD(1) ADCS = TAD –1 TCY TAD = TCY • (ADCS + 1) Note 1: DS39897C-page 274 Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY FIGURE 22-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD Rs VA RIC  250 VT = 0.6V ANx CPIN 6-11 pF (Typical) VT = 0.6V Sampling Switch RSS  5 k(Typical) RSS ILEAKAGE 500 nA CHOLD = DAC capacitance = 4.4 pF (Typical) VSS Legend: CPIN = Input Capacitance = Threshold Voltage VT ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Sampling Switch Resistance RSS = Sample/Hold Capacitance (from DAC) CHOLD Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs  5 k. FIGURE 22-3: A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1)  2009 Microchip Technology Inc. (VINH – VINL) VR+ 1024 1023*(VR+ – VR-) VR- + 1024 VR- + 512*(VR+ – VR-) 1024 VR- + Voltage Level VR+ – VR- 0 VR- 00 0000 0000 (0) DS39897C-page 275 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 276  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 23.0 TRIPLE COMPARATOR MODULE Note: The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual” chapter. A simplified block diagram of the module in shown in Figure 23-1. Diagrams of the possible individual comparator configurations are shown in Figure 23-2. Each comparator has its own control register, CMxCON (Register 23-1), for enabling and configuring its operation. The output and event status of all three comparators is provided in the CMSTAT register (Register 23-2). The triple comparator module provides three dual input comparators. The inputs to the comparator can be configured to use any one of four external analog inputs as well, as a voltage reference input from either the internal band gap reference divided by two (VBG/2) or the comparator voltage reference generator. FIGURE 23-1: TRIPLE COMPARATOR MODULE BLOCK DIAGRAM EVPOL CCH CREF CPOL VINCXINB CXINC CXIND VIN+ Trigger/Interrupt Logic CEVT COE C1 Input Select Logic C1OUT Pin COUT EVPOL VBG/2 CPOL Trigger/Interrupt Logic CEVT COE VINVIN+ C2 COUT EVPOL CXINA CVREF CPOL VINVIN+ Trigger/Interrupt Logic CEVT COE C3 COUT  2009 Microchip Technology Inc. C2OUT Pin C3OUT Pin DS39897C-page 277 PIC24FJ256GB110 FAMILY FIGURE 23-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CEN = 0, CREF = x, CCH = xx COE VINVIN+ Cx Off (Read as ‘0’) Comparator CxINB > CxINA Compare CEN = 1, CREF = 0, CCH = 00 CXINB CXINA VIN+ Comparator CxINC > CxINA Compare CEN = 1, CREF = 0, CCH = 01 COE VIN- CXINC Cx CxOUT Pin CXINA COE VINVIN+ VBG/2 Cx CxOUT Pin Comparator CxINB > CVREF Compare CEN = 1, CREF = 1, CCH = 00 CXINB CVREF CXINC Cx CxOUT Pin CVREF DS39897C-page 278 VIN+ CVREF Cx CxOUT Pin COE VINVIN+ Cx CxOUT Pin COE VINVIN+ Cx CxOUT Pin Comparator VBG > CVREF Compare CEN = 1, CREF = 1, CCH = 11 COE VIN- VIN+ Comparator CxINC > CVREF Compare CEN = 1, CREF = 1, CCH = 01 Comparator CxIND > CVREF Compare CEN = 1, CREF = 1, CCH = 10 CXIND CXINA COE VINVIN+ CXINA COE VIN- Comparator VBG > CxINA Compare CEN = 1, CREF = 0, CCH = 11 Comparator CxIND > CxINA Compare CEN = 1, CREF = 0, CCH = 10 CXIND CxOUT Pin VBG/2 Cx CxOUT Pin CVREF COE VINVIN+ Cx CxOUT Pin  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R-0 CEN COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CEN: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 14 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin. 0 = Comparator output is internal only bit 13 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 12-10 Unimplemented: Read as ‘0’ bit 9 CEVT: Comparator Event bit 1 = Comparator event defined by EVPOL has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred bit 8 COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VIN- bit 7-6 EVPOL: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt generated on transition of comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled bit 5 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. DS39897C-page 279 PIC24FJ256GB110 FAMILY REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) bit 4 CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to internal CVREF voltage 0 = Non-inverting input connects to CXINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH: Comparator Channel Select bits 11 = Inverting input of comparator connects to VBG/2 10 = Inverting input of comparator connects to CXIND pin 01 = Inverting input of comparator connects to CXINC pin 00 = Inverting input of comparator connects to CXINB pin REGISTER 23-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 CMIDL — — — — C3EVT C2EVT C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — C3OUT C2OUT C1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMIDL: Comparator Stop in Idle Mode bit 1 = Module does not generate interrupts in Idle mode, but is otherwise operational 0 = Module continues normal operation in Idle mode bit 14-11 Unimplemented: Read as ‘0’ bit 10 C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON). bit 9 C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON). bit 8 C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON). bit 7-3 Unimplemented: Read as ‘0’ bit 2 C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON). bit 1 C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON). bit 0 C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON). DS39897C-page 280  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 24.0 Note: 24.1 COMPARATOR VOLTAGE REFERENCE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 20. Comparator Voltage Reference Module” (DS39709). Configuring the Comparator Voltage Reference voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR), with one range offering finer resolution. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON). The settling time of the comparator voltage reference must be considered when changing the CVREF output. The voltage reference module is controlled through the CVRCON register (Register 24-1). The comparator voltage reference provides two ranges of output FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 8R CVRSS = 0 CVR R CVREN R R 16-to-1 MUX R 16 Steps R CVREF R R CVRR VREF- 8R CVRSS = 1 CVRSS = 0 AVSS  2009 Microchip Technology Inc. DS39897C-page 281 PIC24FJ256GB110 FAMILY REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ – VREF0 = Comparator reference source CVRSRC = AVDD – AVSS bit 3-0 CVR: Comparator VREF Value Selection 0  CVR3:CVR0  15 bits When CVRR = 1: CVREF = (CVR/24)  (CVRSRC) When CVRR = 0: CVREF = 1/4  (CVRSRC) + (CVR/32)  (CVRSRC) DS39897C-page 282  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 25.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) 25.1 The CTMU module measures capacitance by generating an output pulse with a width equal to the time between edge events on two separate input channels. The pulse edge events to both input channels can be selected from four sources: two internal peripheral modules (OC1 and Timer1) and two external pins (CTEDG1 and CTEDG2). This pulse is used with the module’s precision current source to calculate capacitance according to the relationship: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual” chapter. The Charge Time Measurement Unit is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. Its key features include: • • • • • • dV I = C  ------dT For capacitance measurements, the A/D Converter samples an external capacitor (CAPP) on one of its input channels after the CTMU output’s pulse. A precision resistor (RPR) provides current source calibration on a second A/D channel. After the pulse ends, the converter determines the voltage on the capacitor. The actual calculation of capacitance is performed in software by the application. Four edge input trigger sources Polarity control for each edge source Control of edge sequence Control of response to edges Time measurement resolution of 1 nanosecond Accurate current source suitable for capacitive measurement Figure 25-1 shows the external connections used for capacitance measurements, and how the CTMU and A/D modules are related in this application. This example also shows the edge events coming from Timer1, but other configurations using external edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the “PIC24F Family Reference Manual”. Together with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance, or generate output pulses that are independent of the system clock. The CTMU module is ideal for interfacing with capacitive-based sensors. The CTMU is controlled through two registers, CTMUCON and CTMUICON. CTMUCON enables the module, and controls edge source selection, edge source polarity selection, and edge sequencing. The CTMUICON register has controls the selection and trim of the current source. FIGURE 25-1: Measuring Capacitance TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 Current Source EDG2 Output Pulse A/D Converter ANx ANY CAPP  2009 Microchip Technology Inc. RPR DS39897C-page 283 PIC24FJ256GB110 FAMILY 25.2 Measuring Time When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON), the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected. When CDELAY charges above the CVREF trip point, a pulse is output on CTPLS. The length of the pulse delay is determined by the value of CDELAY and the CVREF trip point. Time measurements on the pulse width can be similarly performed, using the A/D module’s internal capacitor (CAD) and a precision resistor for current calibration. Figure 25-2 shows the external connections used for time measurements, and how the CTMU and A/D modules are related in this application. This example also shows both edge events coming from the external CTEDG pins, but other configurations using internal edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the “PIC24F Family Reference Manual”. 25.3 Figure 25-3 shows the external connections for pulse generation, as well as the relationship of the different analog modules required. While CTEDG1 is shown as the input pulse source, other options are available. A detailed discussion on pulse generation with the CTMU module is provided in the “PIC24F Family Reference Manual”. Pulse Generation and Delay The CTMU module can also generate an output pulse with edges that are not synchronous with the device’s system clock. More specifically, it can generate a pulse with a programmable delay from an edge event input to the module. FIGURE 25-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC24F Device CTMU CTEDG1 EDG1 CTEDG2 EDG2 Current Source Output Pulse A/D Converter ANx CAD RPR FIGURE 25-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTEDG1 EDG1 CTMU CTPLS Current Source Comparator C2INB CDELAY DS39897C-page 284 C2 CVREF  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 TGEN: Time Generation Enable bit(1) 1 = Enables edge delay generation 0 = Disables edge delay generation bit 10 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 10 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 9 IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 8 CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response bit 6-5 EDG2SEL: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response Note 1: x = Bit is unknown If TGEN = 1, the CTEDGx inputs and CTPLS outputs must be assigned to available RPn pins before use. See Section 10.4 “Peripheral Pin Select” for more information.  2009 Microchip Technology Inc. DS39897C-page 285 PIC24FJ256GB110 FAMILY REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 3-2 EDG1SEL: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred Note 1: If TGEN = 1, the CTEDGx inputs and CTPLS outputs must be assigned to available RPn pins before use. See Section 10.4 “Peripheral Pin Select” for more information. REGISTER 25-2: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 ITRIM: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 ..... 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG 111111 = Minimum negative change from nominal current ..... 100010 100001 = Maximum negative change from nominal current bit 9-8 IRNG: Current Source Range Select bits 11 = 100  Base current 10 = 10  Base current 01 = Base current level (0.55 A nominal) 00 = Current source disabled bit 7-0 Unimplemented: Read as ‘0’ DS39897C-page 286 x = Bit is unknown  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 26.0 Note: SPECIAL FEATURES 26.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the “PIC24F Family Reference Manual”: • Section 9. “Watchdog Timer (WDT)” (DS39697) • Section 32. “High-Level Device Integration” (DS39719) • Section 33. “Programming and Diagnostics” (DS39716) PIC24FJ256GB110 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • • • • • • Flexible Configuration Watchdog Timer (WDT) Code Protection JTAG Boundary Scan Interface In-Circuit Serial Programming In-Circuit Emulation 26.1 In PIC24FJ256GB110 family devices, the configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the three words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific locations are shown in Table 26-1. These are packed representations of the actual device Configuration bits, whose actual locations are distributed among several locations in configuration space. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. Note: Configuration data is reloaded on all types of device Resets. When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location F80000h. A detailed explanation of the various bit functions is provided in Register 26-1 through Register 26-5. Note that address F80000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh) which can only be accessed using table reads and table writes. TABLE 26-1: CONSIDERATIONS FOR CONFIGURING PIC24FJ256GB110 FAMILY DEVICES The upper byte of all Flash Configuration Words in program memory should always be ‘1111 1111’. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing ‘1’s to these locations has no effect on device operation. Note: Performing a page erase operation on the last page of program memory clears the Flash Configuration Words, enabling code protection as a result. Therefore, users should avoid performing page erase operations on the last page of program memory. FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ256GB110 FAMILY DEVICES Device PIC24FJ64GB1 Configuration Word Addresses 1 2 3 ABFEh ABFCh ABFAh PIC24FJ128GB1 157FEh 157FC 157FA PIC24FJ192GB1 20BFEh 20BFC 20BFA PIC24FJ256GB1 2ABFEh 2ABFC 2ABFA  2009 Microchip Technology Inc. DS39897C-page 287 PIC24FJ256GB110 FAMILY REGISTER 26-1: CW1: FLASH CONFIGURATION WORD 1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 r-x R/PO-1 (1) r JTAGEN R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1 GCP GWRP DEBUG r ICS1 ICS0 bit 15 bit 8 R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 FWDTEN WINDIS — FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set bit 23-16 Unimplemented: Read as ‘1’ bit 15 Reserved: The value is unknown; program as ‘0’ bit 14 JTAGEN: JTAG Port Enable bit(1) 1 = JTAG port is enabled 0 = JTAG port is disabled bit 13 GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space bit 12 GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are disabled bit 11 DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode bit 10 Reserved: Always maintain as ‘1’ bit 9-8 ICS1:ICS0: Emulator Pin Placement Select bits 11 = Emulator functions are shared with PGEC1/PGED1 10 = Emulator functions are shared with PGEC2/PGED2 01 = Emulator functions are shared with PGEC3/PGED3 00 = Reserved; do not use bit 7 FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled 0 = Watchdog Timer is disabled bit 6 WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer enabled 0 = Windowed Watchdog Timer enabled; FWDTEN must be ‘1’ bit 5 Unimplemented: Read as ‘1’ bit 4 FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 Note 1: ‘0’ = Bit is cleared The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be modified while programming the device through the JTAG interface. DS39897C-page 288  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 26-1: bit 3-0 Note 1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) WDTPS: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be modified while programming the device through the JTAG interface.  2009 Microchip Technology Inc. DS39897C-page 289 PIC24FJ256GB110 FAMILY REGISTER 26-2: U-1 — bit 23 CW2: FLASH CONFIGURATION WORD 2 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — R/PO-1 IESO bit 15 R/PO-1 PLLDIV2 R/PO-1 PLLDIV1 R/PO-1 PLLDIV0 R/PO-1 PLLDIS R/PO-1 FNOSC2 R/PO-1 FNOSC1 R/PO-1 FNOSC0 bit 8 R/PO-1 FCKSM1 bit 7 R/PO-1 FCKSM0 R/PO-1 OSCIOFCN R/PO-1 IOL1WAY R/PO-1 DISUVREG r-1 r R/PO-1 POSCMD1 R/PO-1 POSCMD0 bit 0 Legend: r = Reserved bit R = Readable bit PO = Program-once bit -n = Value when device is unprogrammed bit 23-16 bit 15 bit 14-12 bit 11 bit 10-8 bit 7-6 bit 5 U-1 — bit 16 U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Unimplemented: Read as ‘1’ IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) enabled 0 = IESO mode (Two-Speed Start-up) disabled PLLDIV: USB 96 MHz PLL Prescaler Select bits 111 = Oscillator input divided by 12 (48 MHz input) 110 = Oscillator input divided by 10 (40 MHz input) 101 = Oscillator input divided by 6 (24 MHz input) 100 = Oscillator input divided by 5 (20 MHz input) 011 = Oscillator input divided by 4 (16 MHz input) 010 = Oscillator input divided by 3 (12 MHz input) 001 = Oscillator input divided by 2 (8 MHz input) 000 = Oscillator input used directly (4 MHz input) PLLDIS: USB 96 MHz PLL Disable bit 1 = PLL disabled 0 = PLL enabled (required for all USB operations) FNOSC: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) FCKSM: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSCIOFCN: OSCO Pin Configuration bit If POSCMD = 11 or 00: 1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RC15 functions as port I/O (RC15) If POSCMD = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RC15. DS39897C-page 290  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 26-2: bit 4 bit 3 bit 2 bit 1-0 IOL1WAY: IOLOCK One-Way Set Enable bit 1 = The IOLOCK bit (OSCCON)can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been completed DISUVREG: Internal USB 3.3V Regulator Disable bit 1 = Regulator is disabled 0 = Regulator is enabled Reserved: Always maintain as ‘1’ POSCMD: Primary Oscillator Configuration bits 11 = Primary Oscillator disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = EC Oscillator mode selected REGISTER 26-3: U-1 — bit 23 CW2: FLASH CONFIGURATION WORD 2 (CONTINUED) CW3: FLASH CONFIGURATION WORD 3 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — bit 16 R/PO-1 WPEND bit 15 R/PO-1 WPCFG R/PO-1 WPDIS U-1 — U-1 — U-1 — U-1 — U-1 — R/PO-1 WPFP7 bit 7 R/PO-1 WPFP6 bit 8 R/PO-1 WPFP5 R/PO-1 WPFP4 Legend: R = Readable bit PO = Program-once bit -n = Value when device is unprogrammed bit 23-16 bit 15 bit 14 bit 13 bit 12-8 bit 7-0 R/PO-1 WPFP3 R/PO-1 WPFP2 R/PO-1 WPFP1 R/PO-1 WPFP0 bit 0 U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Unimplemented: Read as ‘1’ WPEND: Segment Write Protection End Page Select bit 1 = Protected code segment lower boundary is at the bottom of program memory (000000h); upper boundary is the code page specified by WPFP 0 = Protected code segment upper boundary is at the last page of program memory; lower boundary is the code page specified by WPFP WPCFG: Configuration Word Code Page Protection Select bit 1 = Last page (at the top of program memory) and Flash Configuration Words are not protected 0 = Last page and Flash Configuration Words are code protected WPDIS: Segment Write Protection Disable bit 1 = Segmented code protection disabled 0 = Segmented code protection enabled; protected segment defined by WPEND, WPCFG and WPFPx Configuration bits Unimplemented: Read as ‘1’ WPFP: Protected Code Segment Boundary Page bits Designates the 512-word program code page that is the boundary of the protected code segment, starting with Page 0 at the bottom of program memory. If WPEND = 1: Last address of designated code page is the upper boundary of the segment. If WPEND = ‘0’: First address of designated code page is the lower boundary of the segment.  2009 Microchip Technology Inc. DS39897C-page 291 PIC24FJ256GB110 FAMILY REGISTER 26-4: DEVID: DEVICE ID REGISTER U — bit 23 U — U — U — U — U — U — U — bit 15 U — R FAMID7 R FAMID6 R FAMID5 R FAMID4 R FAMID3 R FAMID2 bit 8 R FAMID0 R DEV5 R DEV4 R DEV3 R DEV2 R DEV1 R DEV0 bit 0 R FAMID1 bit 7 Legend: R = Read-only bit bit 23-14 bit 13-6 bit 5-0 U — bit 16 U = Unimplemented bit Unimplemented: Read as ‘1’ FAMID: Device Family Identifier bits 01000000 = PIC24FJ256GB110 family DEV: Individual Device Identifier bits 000001 = PIC24FJ64GB106 000011 = PIC24FJ64GB108 000111 = PIC24FJ64GB110 001001 = PIC24FJ128GB106 001011 = PIC24FJ128GB108 001111 = PIC24FJ128GB110 010001 = PIC24FJ192GB106 010011 = PIC24FJ192GB108 010111 = PIC24FJ192GB110 011001 = PIC24FJ256GB106 011011 = PIC24FJ256GB108 011111 = PIC24FJ256GB110 REGISTER 26-5: DEVREV: DEVICE REVISION REGISTER U — U — U — U — U — U — U — U — bit 16 U — U — U — U — U — U — U — R MAJRV2 bit 8 R MAJRV0 U — U — U — R DOT2 R DOT1 bit 23 bit 15 R MAJRV1 bit 7 Legend: R = Read-only bit bit 23-9 bit 8-6 bit 5-3 bit 2-0 R DOT0 bit 0 U = Unimplemented bit Unimplemented: Read as ‘0’ MAJRV: Major Revision Identifier bits Unimplemented: Read as ‘0’ DOT: Minor Revision Identifier bits DS39897C-page 292  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 26.2 On-Chip Voltage Regulator All PIC24FJ256GB110 family devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ256GB110 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR capacitor (such as ceramic) must be connected to the VDDCORE/VCAP pin (Figure 26-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor (CEFC) is provided in Section 29.1 “DC Characteristics”. If ENVREG is tied to VSS, the regulator is disabled. In this case, separate power for the core logic, at a nominal 2.5V, must be supplied to the device on the VDDCORE/VCAP pin to run the I/O pins at higher voltage levels, typically 3.3V. Alternatively, the VDDCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 26-1 for possible configurations. 26.2.1 FIGURE 26-1: CONNECTIONS FOR THE ON-CHIP REGULATOR Regulator Enabled (ENVREG tied to VDD): 3.3V PIC24FJ256GB VDD ENVREG VDDCORE/VCAP CEFC (10 F typ) VSS Regulator Disabled (ENVREG tied to ground): 2.5V(1) 3.3V(1) PIC24FJ256GB VDD ENVREG VDDCORE/VCAP VSS VOLTAGE REGULATOR TRACKING MODE AND LOW-VOLTAGE DETECTION When it is enabled, the on-chip regulator provides a constant voltage of 2.5V nominal to the digital core logic. Regulator Disabled (VDD tied to VDDCORE): 2.5V(1) PIC24FJ256GB VDD The regulator can provide this level from a VDD of about 2.5V, all the way up to the device’s VDDMAX. It does not have the capability to boost VDD levels below 2.5V. In order to prevent “brown out” conditions when the voltage drops too low for the regulator, the regulator enters Tracking mode. In Tracking mode, the regulator output follows VDD, with a typical voltage drop of 100 mV. When the device enters Tracking mode, it is no longer possible to operate at full speed. To provide information about when the device enters Tracking mode, the on-chip regulator includes a simple, Low-Voltage Detect circuit. When VDD drops below full-speed operating voltage, the circuit sets the Low-Voltage Detect Interrupt Flag, LVDIF (IFS4). This can be used to generate an interrupt and put the application into a low-power operational mode, or trigger an orderly shutdown. ENVREG VDDCORE/VCAP VSS Note 1: These are typical operating voltages. Refer to Section 29.1 “DC Characteristics” for the full operating ranges of VDD and VDDCORE. Low-Voltage Detection (LVD) is only available when the regulator is enabled.  2009 Microchip Technology Inc. DS39897C-page 293 PIC24FJ256GB110 FAMILY 26.2.2 ON-CHIP REGULATOR AND POR When the voltage regulator is enabled, it takes approximately 10 s for it to generate output. During this time, designated as TVREG, code execution is disabled. TVREG is applied every time the device resumes operation after any power-down, including Sleep mode. The length of TVREG is determined by the PMSLP bit (RCON), as described in Section 26.2.5 “Voltage Regulator Standby Mode”. If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of 64 ms nominal delay at device start-up (POR or BOR only). When waking up from Sleep with the regulator disabled, the PMSLP bit determines the wake-up time. When operating with the regulator disabled, setting PMSLP can decrease the device wake-up time. 26.2.3 ON-CHIP REGULATOR AND BOR When the on-chip regulator is enabled, PIC24FJ256GB110 family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain the tracking level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON). The brown-out voltage specifications are provided in the “PIC24FJ Family Reference Manual”, Section 7. “Reset” (DS39712). 26.2.4 POWER-UP REQUIREMENTS The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts. Note: 26.2.5 For more information, see Section 29.0 “Electrical Characteristics”. VOLTAGE REGULATOR STANDBY MODE When enabled, the on-chip regulator always consumes a small incremental amount of current over IDD/IPD, including when the device is in Sleep mode, even though the core digital logic does not require power. To provide additional savings in applications where power resources are critical, the regulator automatically disables itself whenever the device goes into Sleep mode. This feature is controlled by the PMSLP bit (RCON). By default, the bit is cleared, which removes power from the Flash program memory and thus enables Standby mode. When waking up from Standby mode, the regulator must wait for TVREG to expire before wake-up. This extra time is needed to ensure that the regulator can source enough current to power the Flash memory. DS39897C-page 294 For applications which require a faster wake-up time, it is possible to disable regulator Standby mode. The PMSLP bit can be set to turn off Standby mode so that the Flash stays powered when in Sleep mode and the device can wake-up without waiting for TVREG. When PMSLP is set, the power consumption while in Sleep mode, will be approximately 40 A higher than power consumption when the regulator is allowed to enter Standby mode. 26.3 Watchdog Timer (WDT) For PIC24FJ256GB110 family devices, the WDT is driven by the LPRC Oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 31 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPS Configuration bits (CW1), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) • When the device exits Sleep or Idle mode to resume normal operation • By a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON) will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 26.3.1 WINDOWED OPERATION 26.3.2 The Watchdog Timer has an optional Fixed Window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction executed before that window causes a WDT Reset, similar to a WDT time-out. Windowed WDT mode is enabled by programming the WINDIS Configuration bit (CW1) to ‘0’. FIGURE 26-2: CONTROL REGISTER The WDT is enabled or disabled by the FWDTEN Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the SWDTEN control bit (RCON). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. WDT BLOCK DIAGRAM SWDTEN FWDTEN LPRC Control FWPSA WDTPS Prescaler (5-bit/7-bit) LPRC Input 31 kHz Wake from Sleep WDT Counter Postscaler 1:1 to 1:32.768 1 ms/4 ms WDT Overflow Reset All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode 26.4 Program Verification and Code Protection PIC24FJ256GB110 family devices provide two complimentary methods to protect application code from overwrites and erasures. These also help to protect the device from inadvertent configuration changes during run time. 26.4.1 GENERAL SEGMENT PROTECTION For all devices in the PIC24FJ256GB110 family, the on-chip program memory space is treated as a single block, known as the General Segment (GS). Code protection for this block is controlled by one Configuration bit, GCP. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. Write protection is controlled by the GWRP bit in the Configuration Word. When GWRP is programmed to ‘0’, internal write and erase operations to program memory are blocked.  2009 Microchip Technology Inc. 26.4.2 CODE SEGMENT PROTECTION In addition to global General Segment protection, a separate subrange of the program memory space can be individually protected against writes and erases. This area can be used for many purposes where a separate block of write and erase protected code is needed, such as bootloader applications. Unlike common boot block implementations, the specially protected segment in PIC24FJ256GB110 family devices can be located by the user anywhere in the program space, and configured in a wide range of sizes. Code segment protection provides an added level of protection to a designated area of program memory, by disabling the NVM safety interlock whenever a write or erase address falls within a specified range. They do not override General Segment protection controlled by the GCP or GWRP bits. For example, if GCP and GWRP are enabled, enabling segmented code protection for the bottom half of program memory does not undo General Segment protection for the top half. DS39897C-page 295 PIC24FJ256GB110 FAMILY The size and type of protection for the segmented code range are configured by the WPFPx, WPEND, WPCFG and WPDIS bits in Configuration Word 3. Code segment protection is enabled by programming the WPDIS bit (= 0). The WPFP bits specify the size of the segment to be protected, by specifying the 512-word code page that is the start or end of the protected segment. The specified region is inclusive, therefore, this page will also be protected. The WPEND bit determines if the protected segment uses the top or bottom of the program space as a boundary. Programming WPEND (= 0) sets the bottom of program memory (000000h) as the lower boundary of the protected segment. Leaving WPEND unprogrammed (= 1) protects the specified page through the last page of implemented program memory, including the Configuration Word locations. A separate bit, WPCFG, is used to independently protect the last page of program space, including the Flash Configuration Words. Programming WPCFG (= 0) protects the last page regardless of the other bit settings. This may be useful in circumstances where write protection is needed for both a code segment in the bottom of memory, as well as the Flash Configuration Words. 26.4.3 CONFIGURATION REGISTER PROTECTION The Configuration registers are protected against inadvertent or unwanted changes or reads in two ways. The primary protection method is the same as that of the RP registers – shadow registers contain a complimentary value which is constantly compared with the actual value. To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity error and trigger a device Reset. The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the GCP bit is set, the source data for device configuration is also protected as a consequence. Even if General Segment protection is not enabled, the device configuration can be protected by using the appropriate code cement protection setting. The various options for segment code protection are shown in Table 26-2. TABLE 26-2: SEGMENT CODE PROTECTION CONFIGURATION OPTIONS Segment Configuration Bits Write/Erase Protection of Code Segment WPDIS WPEND WPCFG 1 X x No additional protection enabled; all program memory protection configured by GCP and GWRP 0 1 x Addresses from first address of code page defined by WPFP through end of implemented program memory (inclusive) write/erase protected, including Flash Configuration Words 0 0 1 Address 000000h through last address of code page defined by WPFP (inclusive) write/erase protected 0 0 0 Address 000000h through last address of code page defined by WPFP (inclusive) write/erase protected, and the last page is also write/erase protected. DS39897C-page 296  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 26.5 JTAG Interface PIC24FJ256GB110 family devices implement a JTAG interface, which supports boundary scan device testing. 26.6 In-Circuit Serial Programming PIC24FJ256GB110 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGECx) and data (PGEDx) and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.  2009 Microchip Technology Inc. 26.7 In-Circuit Debugger When MPLAB® ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pins. To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS and the PGECx/PGEDx pin pair designated by the ICS Configuration bits. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. DS39897C-page 297 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 298  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 27.0 DEVELOPMENT SUPPORT The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers - MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 27.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2009 Microchip Technology Inc. DS39897C-page 299 PIC24FJ256GB110 FAMILY 27.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 27.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 27.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: 27.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 27.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS39897C-page 300  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 27.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 27.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.  2009 Microchip Technology Inc. 27.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 27.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. DS39897C-page 301 PIC24FJ256GB110 FAMILY 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured Windows® programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. 27.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39897C-page 302 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 28.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture, and is not intended to be a comprehensive reference source. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: • • • • Word or byte-oriented operations Bit-oriented operations Literal operations Control operations • A literal value to be loaded into a W register or file register (specified by the value of ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand which is a register ‘Wb’ without any address modifier • The second source operand which is a literal value • The destination of the result (only if not the same as the first source operand) which is typically a register ‘Wd’ with or without an address modifier The control instructions may use some of the following operands: • A program memory address • The mode of the table read and table write instructions Table 28-1 shows the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 28-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand which is typically a register ‘Wb’ without any address modifier • The second source operand which is typically a register ‘Ws’ with or without an address modifier • The destination of the result which is typically a register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: • The file register specified by the value, ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ Most bit-oriented instructions (including rotate/shift instructions) have two operands: The literal instructions that involve data movement may use some of the following operands: simple All instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register, ‘Wb’)  2009 Microchip Technology Inc. DS39897C-page 303 PIC24FJ256GB110 FAMILY TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0000h...1FFFh} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16383} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388607}; LSB must be ‘0’ None Field does not require an entry, may be blank PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing) Wn One of 16 working registers {W0..W15} Wnd One of 16 destination working registers {W0..W15} Wns One of 16 source working registers {W0..W15} WREG W0 (working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } DS39897C-page 304  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z AND f f = f .AND. WREG 1 1 N, Z AND f,WREG WREG = f .AND. WREG 1 1 N, Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None BRA LE,Expr Branch if Less than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None BRA LT,Expr Branch if Less than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW.C Ws,Wb Write C bit to Ws 1 1 None BSW.Z Ws,Wb Write Z bit to Ws 1 1 None BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3)  2009 Microchip Technology Inc. DS39897C-page 305 PIC24FJ256GB110 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax Description # of Words # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.Z Ws,Wb Bit Test Ws to Z 1 1 BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None Clear Watchdog Timer 1 1 WDTO, Sleep CLRWDT CLRWDT COM COM f f=f 1 1 N, Z COM f,WREG WREG = f 1 1 N, Z COM Ws,Wd Wd = Ws 1 1 N, Z CP f Compare f with WREG 1 1 C, DC, N, OV, Z CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, Z CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,Ws Compare Wb with Ws, with Borrow (Wb – Ws – C) 1 1 C, DC, N, OV, Z CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 None (2 or 3) CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 None (2 or 3) CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 None (2 or 3) CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if  1 1 None (2 or 3) DAW DAW.b Wn Wn = Decimal Adjust Wn 1 1 DEC DEC f f = f –1 1 1 C, DC, N, OV, Z DEC f,WREG WREG = f –1 1 1 C, DC, N, OV, Z CP C DEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, Z DEC2 f f=f–2 1 1 C, DC, N, OV, Z DEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, Z DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C DEC2 DS39897C-page 306  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic GOTO INC INC2 Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC2 Ws,Wd Wd = Ws + 2 1 1 IOR f f = f .IOR. WREG 1 1 N, Z IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z LNK LNK #lit14 Link Frame Pointer 1 1 None LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z MOV f,Wn Move f to Wn 1 1 None MOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 None MOV f Move f to f 1 1 N, Z MOV f,WREG Move f to WREG 1 1 N, Z MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1 MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N, Z MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None NEG f f=f+1 1 1 C, DC, N, OV, Z NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z NEG Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z NOP No Operation 1 1 None NOPR No Operation 1 1 None IOR MOV MUL NEG NOP POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1 2 None Pop Shadow Registers 1 1 All POP.S PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None Push Shadow Registers 1 1 None PUSH.S  2009 Microchip Technology Inc. DS39897C-page 307 PIC24FJ256GB110 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 None RETFIE RETFIE Return from Interrupt 1 3 (2) None RETLW RETLW Return with Literal in Wn 1 3 (2) None RETURN RETURN Return from Subroutine 1 3 (2) None RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z C, N, Z RLNC RRC RRNC #lit10,Wn RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 RLNC f f = Rotate Left (No Carry) f 1 1 N, Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z N, Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 RRC f f = Rotate Right through Carry f 1 1 C, N, Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z RRNC f f = Rotate Right (No Carry) f 1 1 N, Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z SETM SETM f f = FFFFh 1 1 None SETM WREG WREG = FFFFh 1 1 None SETM Ws Ws = FFFFh 1 1 None SL f f = Left Shift f 1 1 C, N, OV, Z SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z SUB f f = f – WREG 1 1 C, DC, N, OV, Z SUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, Z SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, Z SL SUB SUBB SUBR SUBBR SWAP SUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, Z SUBR f f = WREG – f 1 1 C, DC, N, OV, Z SUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C, DC, N, OV, Z SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, Z C, DC, N, OV, Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None DS39897C-page 308  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDH TBLRDH Ws,Wd Read Prog to Wd 1 2 TBLRDL TBLRDL Ws,Wd Read Prog to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws to Prog 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N ZE  2009 Microchip Technology Inc. None DS39897C-page 309 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 310  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ256GB110 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ256GB110 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +100°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +3.0V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (Note 1)................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 1)....................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 29-1). †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2009 Microchip Technology Inc. DS39897C-page 311 PIC24FJ256GB110 FAMILY 29.1 DC Characteristics FIGURE 29-1: PIC24FJ256GB110 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.00V Voltage (VDDCORE)(1) 2.75V 2.75V 2.50V PIC24FJXXXGB1XX 2.25V 2.25V 2.00V 16 MHz 32 MHz Frequency For frequencies between 16 MHz and 32 MHz, FMAX = (64 MHz/V) * (VDDCORE – 2V) + 16 MHz. When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCOREVDD3.6V. Note 1: TABLE 29-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C PIC24FJ256GB110 Family: Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W PDMAX (TJ – TA)/JA W I/O Pin Power Dissipation: PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation TABLE 29-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes Package Thermal Resistance, 14x14x1 mm TQFP JA 50.0 — °C/W (Note 1) Package Thermal Resistance, 12x12x1 mm TQFP JA 69.4 — °C/W (Note 1) Package Thermal Resistance, 10x10x1 mm TQFP JA 76.6 — °C/W (Note 1) Package Thermal Resistance, 9x9x0.9 mm QFN JA 28.0 — °C/W (Note 1) Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS39897C-page 312  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 29-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min Typ(1) Max Units VDD 2.2 — 3.6 V Regulator enabled VDD VDDCORE — 3.6 V Regulator disabled 2.0 — 2.75 V Regulator disabled Characteristic Conditions Operating Voltage DC10 Supply Voltage VDDCORE DC12 VDR RAM Data Retention Voltage(2) 1.5 — — V DC16 VPOR VDD Start Voltage To Ensure Internal Power-on Reset Signal VSS — — V DC17 SVDD VDD Rise Rate to Ensure Internal Power-on Reset Signal 0.05 — — V/ms DC18 VBOR BOR Voltage on VDD Transition. High-to-Low — 2.05 — V Note 1: 2: 0-3.3V in 0.1s 0-2.5V in 60 ms Voltage regulator enabled Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data.  2009 Microchip Technology Inc. DS39897C-page 313 PIC24FJ256GB110 FAMILY TABLE 29-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) DC20 0.83 1.2 mA -40°C DC20a 0.83 1.2 mA +25°C DC20b 0.83 1.2 mA +85°C DC20d 1.1 1.7 mA -40°C DC20e 1.1 1.7 mA +25°C DC20f 1.1 1.7 mA +85°C DC23 3.3 4.5 mA -40°C DC23a 3.3 4.5 mA +25°C DC23b 3.3 4.5 mA +85°C DC23d 4.3 6 mA -40°C DC23e 4.3 6 mA +25°C DC23f 4.3 6 mA +85°C DC24 18.2 24 mA -40°C DC24a 18.2 24 mA +25°C DC24b 18.2 24 mA +85°C DC24d 18.2 24 mA -40°C DC24e 18.2 24 mA +25°C DC24f 18.2 24 mA +85°C DC31 15.0 54 A -40°C DC31a 15.0 54 A +25°C DC31b 20.0 69 A +85°C DC31d 57.0 96 A -40°C DC31e 57.0 96 A +25°C DC31f 95.0 145 A +85°C Note 1: 2: 3: 4: 2.0V(3) 1 MIPS 3.3V(4) 2.0V(3) 4 MIPS 3.3V(4) 2.5V(3) 16 MIPS 3.3V(4) 2.0V(3) LPRC (31 kHz) 3.3V(4) Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. DS39897C-page 314  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 29-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Idle Current (IIDLE)(2) DC40 220 310 A -40°C DC40a 220 310 A +25°C DC40b 220 310 A +85°C DC40d 300 390 A -40°C DC40e 300 390 A +25°C DC40f 300 420 A +85°C DC43 0.85 1.1 mA -40°C DC43a 0.85 1.1 mA +25°C DC43b 0.87 1.2 mA +85°C DC43d 1.1 1.4 mA -40°C DC43e 1.1 1.4 mA +25°C DC43f 1.1 1.4 mA +85°C DC47 4.4 5.6 mA -40°C DC47a 4.4 5.6 mA +25°C DC47b 4.4 5.6 mA +85°C DC47c 4.4 5.6 mA -40°C DC47d 4.4 5.6 mA +25°C DC47e 4.4 5.6 mA +85°C DC50 1.1 1.4 mA -40°C DC50a 1.1 1.4 mA +25°C DC50b 1.1 1.4 mA +85°C DC50d 1.4 1.8 mA -40°C DC50e 1.4 1.8 mA +25°C DC50f 1.4 1.8 mA +85°C DC51 4.3 13 A -40°C DC51a 4.5 13 A +25°C DC51b 10 32 A +85°C DC51d 44 77 A -40°C DC51e 44 77 A +25°C 70 132 A +85°C DC51f Note 1: 2: 3: 4: 2.0V(3) 1 MIPS 3.3V(4) 2.0V(3) 4 MIPS 3.3V(4) 2.5V(3) 16 MIPS 3.3V(4) 2.0V(3) FRC (4 MIPS) 3.3V(4) 2.0V(3) LPRC (31 kHz) 3.3V(4) Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IIDLE current is measured with the core off, OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled.  2009 Microchip Technology Inc. DS39897C-page 315 PIC24FJ256GB110 FAMILY TABLE 29-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units 1 A Conditions Power-Down Current (IPD)(2) DC60 0.1 -40°C DC60a 0.15 1 A +25°C DC60m 2.25 11 A +60°C DC60b 3.7 18 A +85°C DC60c 0.2 1.4 A -40°C DC60d 0.25 1.4 A +25°C DC60n 2.6 16.5 A +60°C DC60e 4.2 27 A +85°C DC60f 3.6 10 A -40°C DC60g 4.0 10 A +25°C DC60p 8.1 25.2 A +60°C DC60h 11.0 36 A +85°C DC61 1.75 3 A -40°C DC61a 1.75 3 A +25°C DC61m 1.75 3 A +60°C DC61b 1.75 3 A +85°C DC61c 2.4 4 A -40°C DC61d 2.4 4 A +25°C DC61n 2.4 4 A +60°C DC61e 2.4 4 A +85°C DC61f 2.8 5 A -40°C DC61g 2.8 5 A +25°C DC61p 2.8 5 A +60°C 2.8 5 A +85°C DC61b Note 1: 2: 3: 4: 5: 2.0V(3) 2.5V(3) Base Power-Down Current(5) 3.3V(4) 2.0V(3) 2.5V(3) Watchdog Timer Current: IWDT(5) 3.3V(4) Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off, PMSLP bit is clear, and the Peripheral Module Disable (PMD) bits for all unused peripherals are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. DS39897C-page 316  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 29-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD)(2) DC62 2.5 7 A -40°C DC62a 2.5 7 A +25°C DC62m 3.0 7 A +60°C DC62b 3.0 7 A +85°C DC62c 2.8 7 A -40°C DC62d 3.0 7 A +25°C DC62n 3.0 7 A +60°C DC62e 3.0 7 A +85°C DC62f 3.5 10 A -40°C DC62g 3.5 10 A +25°C DC62p 4.0 10 A +60°C DC62h 4.0 10 A +85°C Note 1: 2: 3: 4: 5: 2.0V(3) 2.5V(3) RTCC + Timer1 w/32 kHz Crystal: RTCC + ITI32(5) 3.3V(4) Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off, PMSLP bit is clear, and the Peripheral Module Disable (PMD) bits for all unused peripherals are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.  2009 Microchip Technology Inc. DS39897C-page 317 PIC24FJ256GB110 FAMILY TABLE 29-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ(1) Max Units Input Low Voltage(4) DI10 I/O Pins with ST Buffer VSS — 0.2 VDD V DI11 I/O Pins with TTL Buffer VSS — 0.15 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSC1 (XT mode) VSS — 0.2 VDD V DI17 OSC1 (HS mode) VSS — 0.2 VDD V DI18 I/O Pins with I2C™ Buffer: VSS — 0.3 VDD V I/O Pins with SMBus Buffer: VSS — 0.8 V I/O Pins with ST Buffer: with Analog Functions, Digital Only 0.8 VDD 0.8 VDD — — VDD 5.5 V V I/O Pins with TTL Buffer: with Analog Functions, Digital Only 0.25 VDD + 0.8 0.25 VDD + 0.8 — — VDD 5.5 V V DI19 VIH DI20 DI21 Conditions SMBus enabled Input High Voltage(4) DI25 MCLR 0.8 VDD — VDD V DI26 OSC1 (XT mode) 0.7 VDD — VDD V DI27 OSC1 (HS mode) 0.7 VDD — VDD V 0.7 VDD 0.7 VDD — — VDD 5.5 V V VDD 5.5 V V I2C DI28 I/O Pins with Buffer: with Analog Functions, Digital Only DI29 I/O Pins with SMBus Buffer: with Analog Functions, Digital Only 2.5V  VPIN  VDD 2.1 2.1 DI30 ICNPU CNxx Pull-up Current 50 250 400 A VDD = 3.3V, VPIN = VSS DI30A ICNPD CNxx Pull-Down Current — 80 — A VDD = 3.3V, VPIN = VDD IIL Input Leakage Current(2,3) DI50 I/O Ports — — +1 A VSS  VPIN  VDD, Pin at high-impedance DI51 Analog Input Pins — — +1 A VSS  VPIN  VDD, Pin at high-impedance DI52 USB Differential Pins (D+, D-) — — +1 A VUSB VDD DI55 MCLR — — +1 A VSS VPIN VDD DI56 OSC1 — — +1 A VSS VPIN VDD, XT and HS modes Note 1: 2: 3: 4: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Refer to Table 1-4 for I/O pins buffer types. DS39897C-page 318  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 29-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial DC CHARACTERISTICS Param No. Sym VOL Characteristic I/O Ports DO16 OSC2/CLKO DO20 Note 1: Max Units — — 0.4 V IOL = 8.5 mA, VDD = 3.6V — — 0.4 V IOL = 6.0 mA, VDD = 2.0V — — 0.4 V IOL = 8.5 mA, VDD = 3.6V — — 0.4 V IOL = 6.0 mA, VDD = 2.0V OSC2/CLKO 3.0 — — V IOH = -3.0 mA, VDD = 3.6V 2.4 — — V IOH = -6.0 mA, VDD = 3.6V 1.65 — — V IOH = -1.0 mA, VDD = 2.0V 1.4 — — V IOH = -3.0 mA, VDD = 2.0V 2.4 — — V IOH = -6.0 mA, VDD = 3.6V 1.4 — — V IOH = -3.0 mA, VDD = 2.0V Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 29-9: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param No. Conditions Output High Voltage I/O Ports DO26 Typ(1) Output Low Voltage DO10 VOH Min Min Typ(1) Max 10000 — — VMIN — 3.6 V VDDCORE 2.25 — 3.6 V VDD 2.35 — 3.6 V — 3 — ms Sym Characteristic D130 EP Cell Endurance D131 VPR VDD for Read Units Conditions E/W -40C to +85C VMIN = Minimum operating voltage VPEW Supply Voltage for Self-Timed Writes D132A D132B D133A TIW Self-Timed Write Cycle Time D133B TIE Self-Timed Page Erase Time D134 TRETD Characteristic Retention D135 IDDP Note 1: Supply Current during Programming 40 — — 20 — — Year Provided no other specifications are violated ms — 7 — mA Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.  2009 Microchip Technology Inc. DS39897C-page 319 PIC24FJ256GB110 FAMILY TABLE 29-10: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +125°C (unless otherwise stated) Param Symbol No. Characteristics Min Typ Max Units Comments VRGOUT Regulator Output Voltage — 2.5 — V VBG Internal Band Gap Reference — 1.2 — V CEFC External Filter Capacitor Value 4.7 10 — F Series resistance < 3 Ohm recommended; < 5 Ohm required. TVREG Regulator Start-up Time — 10 — s PMSLP = 1, or any POR or BOR — 190 — s Wake for sleep when PMSLP = 0 — — 1 ms TBG DS39897C-page 320 Band Gap Reference Start-up Time  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 29.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ256GB110 family AC characteristics and timing parameters. TABLE 29-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Operating voltage VDD range as described in Section 29.1 “DC Characteristics”. AC CHARACTERISTICS FIGURE 29-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSCO Load Condition 2 – for OSCO VDD/2 CL Pin RL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSCO 15 pF for OSCO output VSS TABLE 29-12: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions DO50 COSC2 OSCO/CLKO pin — — 15 pF In XT and HS modes when external clock is used to drive OSCI. DO56 CIO All I/O pins and OSCO — — 50 pF EC mode. DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode. Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2009 Microchip Technology Inc. DS39897C-page 321 PIC24FJ256GB110 FAMILY FIGURE 29-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS31 OS30 OS31 OS25 CLKO OS40 OS41 TABLE 29-13: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Sym No. OS10 Characteristic FOSC External CLKI Frequency (External clocks allowed only in EC mode) Oscillator Frequency Standard Operating Conditions: 2.50 to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min Typ(1) Max Units DC 4 — — 32 48 MHz MHz EC ECPLL 3 4 10 12 31 — — — — — 10 8 32 32 33 MHz MHz MHz MHz kHz XT XTPLL HS HSPLL SOSC — — — — Conditions OS20 TOSC TOSC = 1/FOSC OS25 TCY 62.5 — DC ns OS30 TosL, External Clock in (OSCI) TosH High or Low Time 0.45 x TOSC — — ns EC OS31 TosR, External Clock in (OSCI) TosF Rise or Fall Time — — 20 ns EC OS40 TckR CLKO Rise Time(3) — 6 10 ns OS41 TckF CLKO Fall Time(3) — 6 10 ns Note 1: 2: 3: Instruction Cycle Time(2) See parameter OS10 for FOSC value Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). DS39897C-page 322  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 29-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V) AC CHARACTERISTICS Param No. Sym Characteristic(1) OS50 FPLLI PLL Input Frequency Range(2) OS51 FSYS PLL Output Frequency Range OS52 TLOCK PLL Start-up Time (Lock Time) OS53 DCLK Note 1: 2: CLKO Stability (Jitter) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min Typ(2) Max Units 4 — 32 MHz 95.76 — 96.24 MHz — — 200 s -0.25 — 0.25 % Conditions ECPLL, HSPLL, XTPLL modes These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 29-15: INTERNAL RC OSCILLATOR SPECIFICATIONS AC CHARACTERISTICS Param No. Sym TFRC Characteristic FRC Start-up Time TLPRC LPRC Start-up Time Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA +85°C for Industrial Min Typ Max Units — 15 — s — 40 — s Conditions TABLE 29-16: INTERNAL RC OSCILLATOR ACCURACY AC CHARACTERISTICS Param No. F20 Characteristic FRC Accuracy@ 8 MHz(1) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA +85°C for Industrial Min Typ Max Units Conditions -2 — 2 % +25°C, 3.0V  VDD 3.6V -5 — 5 % -40°C  TA +85°C, 3.0V  VDD 3.6V -20 — 20 % -40°C  TA +85°C, 3.0V  VDD 3.6V F21 LPRC Accuracy @ 31 kHz(2) Note 1: 2: Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift. Change of LPRC frequency as VDD changes.  2009 Microchip Technology Inc. DS39897C-page 323 PIC24FJ256GB110 FAMILY FIGURE 29-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 29-2 for load conditions. TABLE 29-17: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min Typ(1) Max Units DO31 TIOR Port Output Rise Time — 10 25 ns DO32 TIOF Port Output Fall Time — 10 25 ns DI35 TINP INTx pin High or Low Time (output) 20 — — ns DI40 TRBP CNx High or Low Time (input) 2 — — TCY Note 1: Conditions Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS39897C-page 324  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 29-18: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 2.0 — Lesser of VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V AD05 VREFH Reference Voltage High AVSS + 1.7 — AVDD V AD06 VREFL Reference Voltage Low AVSS — AVDD – 1.7 V AD07 VREF Absolute Reference Voltage AVSS – 0.3 — AVDD + 0.3 V Reference Inputs Analog Input AD10 VINH-VINL Full-Scale Input Span VREFL — VREFH V AD11 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V AD12 VINL Absolute VINL Input Voltage AVSS – 0.3 AVDD/2 V AD13 — Leakage Current — ±0.00 1 ±0.610 A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5 k AD17 RIN Recommended Impedance of Analog Voltage Source — — 2.5K  10-bit (Note 2) ADC Accuracy AD20b Nr Resolution — 10 — bits AD21b INL Integral Nonlinearity — ±1 > > (  !"# $% &" ' ()"&'"!&) & #*&& & #  +'% !& !  &,!- '  ' !!#.#&"# '#%! &"!!#%! &"!!!& $ #/'' !#  ' !#&  .0/ 1+2 1!' !  & $& " !**&"&&  ! .32  %   ' !("!"*&"&&  (%%'& " ! !    * + 1  2009 Microchip Technology Inc. DS39897C-page 335 PIC24FJ256GB110 FAMILY           ##   !" #$  % & ' ( 3& '!&" & 4 #*!(  ! ! &  4 %&& #& && 255***' '5 4 DS39897C-page 336  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY           ##   !" #$  % & ' ( 3& '!&" & 4 #*!(  ! ! &  4 %&& #& && 255***' '5 4 D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 6&! ' !7'&! 8"') %7 #! '     A2 L1 77.. 8 8 89 :  7 #& 9 < &  = 1+ = # #4 4 !!  /  / &#%%  / = / 3&7 & 7 / ; / 3& & 7  .3 3& I 9 ?#& . > 1+ /> 9 7 &  1+ # #4 ?#& . 1+ # #4 7 &  1+ > 7 #4 !!   =  7 #?#& )  @  #%&  D > > > #%& 1&&' E > > > (  !"# $% &" ' ()"&'"!&) & #*&& & #  +'% !& !  &,!- '  ' !!#.#&"# '#%! &"!!#%! &"!!!& $ #/'' !#  ' !#&  .0/ 1+2 1!' !  & $& " !**&"&&  ! .32  %   ' !("!"*&"&&  (%%'& " ! !    * + 1  2009 Microchip Technology Inc. DS39897C-page 337 PIC24FJ256GB110 FAMILY           ##   !" #$  % & ' ( 3& '!&" & 4 #*!(  ! ! &  4 %&& #& && 255***' '5 4 DS39897C-page 338  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY              !" #$  % & ' ( 3& '!&" & 4 #*!(  ! ! &  4 %&& #& && 255***' '5 4 D D1 e E1 E b N α NOTE 1 1 23 A NOTE 2 φ c β A2 A1 L L1 6&! ' !7'&! 8"') %7 #! '     77.. 8 8 89 :  7 #& 9 < &  = /1+ = # #4 4 !!  /  / &#%%  / = / 3&7 & 7 / ; / 3& & 7  .3 3& I 9 ?#& . > ;1+ /> 9 7 &  ;1+ # #4 ?#& . 1+ # #4 7 &  1+ > 7 #4 !!   =  7 #?#& )    #%&  D > > > #%& 1&&' E > > > (  !"# $% &" ' ()"&'"!&) & #*&& & #  +'% !& !  &,!- '  ' !!#.#&"# '#%! &"!!#%! &"!!!& $ #/'' !#  ' !#&  .0/ 1+2 1!' !  & $& " !**&"&&  ! .32  %   ' !("!"*&"&&  (%%'& " ! !    * + 1  2009 Microchip Technology Inc. DS39897C-page 339 PIC24FJ256GB110 FAMILY              !" #$  % & ' ( 3& '!&" & 4 #*!(  ! ! &  4 %&& #& && 255***' '5 4 DS39897C-page 340  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY APPENDIX A: REVISION HISTORY Revision A (October 2007) Original data sheet for the PIC24FJ256GB110 family of devices. Revision B (March 2008) Changes to Section 29.0 “Electrical Characteristics” and minor edits to text throughout document. Revision C (December 2009) Updates all Pin Diagrams to reflect the correct order of priority for multiplexed peripherals. Adds packaging information for the new 64-pin QFN package to Section 30.0 “Packaging Information” and the Product Information System. Updates Section 5.0 “Flash Program Memory” with revised code examples in assembler, and new code examples in C. Updates Section 26.0 “Special Features” with revised text on the operation of the regulator during POR and Standby mode. Updates Section 26.5 “JTAG Interface” to remove references to programming via the interface. Makes multiple additions and changes to Section 29.0 “Electrical Characteristics”, including: • Addition of IPD specifications for operation at 60°C • New DC characteristics of VBOR, VBG, TBG and ICNPD • Addition of new VPEW specification for VDDCORE • New AC characteristics for internal oscillator start-up time (TLPRC) • Combination of all Internal RC accuracy information into a single table Makes other minor typographic corrections throughout the text. Updates Section 6.2 “Device Reset Times” with revised information, particularly Table 6-3. Adds the INTTREG register to Section 4.0 “Memory Organization” and Section 7.0 “Interrupt Controller”. Makes several additions and changes to Section 10.0 “I/O Ports”, including: • revision of Section 10.4.2.1 “Peripheral Pin Select Function Priority” • revisions to Table 10-3, “Selectable Output Sources” Makes several changes and additions to Section 18.0 “Universal Serial Bus with On-The-Go Support (USB OTG)”, including: • changes the name of the bit U1CON from RESET to USBRST • replaces the former Section 18.3 with Section 18.1 “Hardware Configuration”, including an expanded discussion of how to interface the microcontroller to application in different USB modes Updates Section 21.0 “Programmable Cyclic Redundancy Check (CRC) Generator” with new illustrations, and a revised Section 21.1 “User Interface”. Updates Section 22.0 “10-Bit High-Speed A/D Converter” by changing all references to AD1CHS0, to AD1CHS (as well as other locations in the document). Also revises bit field descriptions in registers, AD1CON3 (bits 7:0) and AD1CHS (bits 12:8). Makes minor text edits to bit descriptions in Section 23.0 “Triple Comparator Module” (Register 23-1) and Section 25.0 “Charge Time Measurement Unit (CTMU)” (Register 25-1).  2009 Microchip Technology Inc. DS39897C-page 341 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 342  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY INDEX A SPI Master, Frame Master Connection .................... 189 SPI Master, Frame Slave Connection ...................... 189 SPI Master/Slave Connection (Enhanced Buffer Modes)................................. 188 SPI Master/Slave Connection (Standard Mode)....... 188 SPI Slave, Frame Master Connection ...................... 189 SPI Slave, Frame Slave Connection ........................ 189 SPIx Module (Enhanced Mode)................................ 183 SPIx Module (Standard Mode) ................................. 182 System Clock Diagram ............................................. 121 Triple Comparator Module........................................ 277 UART (Simplified)..................................................... 199 USB OTG Device Mode Power Modes.............................. 209 USB OTG Interrupt Funnel ....................................... 216 USB OTG Module..................................................... 208 USB PLL................................................................... 128 Watchdog Timer (WDT)............................................ 295 A/D Converter Analog Input Model ................................................... 275 Transfer Function...................................................... 275 AC Characteristics ADC Conversion Timing ........................................... 326 CLKO and I/O Timing................................................ 324 Alternate Interrupt Vector Table (AIVT) .............................. 77 Assembler MPASM Assembler................................................... 300 B Block Diagrams 10-Bit High-Speed A/D Converter............................. 268 16-Bit Asynchronous Timer3 and Timer5 ................. 165 16-Bit Synchronous Timer2 and Timer4 ................... 165 16-Bit Timer1 Module................................................ 161 32-Bit Timer2/3 and Timer4/5 ................................... 164 Accessing Program Space Using Table Operations .......................................................... 61 Addressable PMP Example ...................................... 248 Addressing for Table Registers................................... 63 BDT Mapping for Endpoint Buffering Modes ............ 212 CALL Stack Frame...................................................... 59 Comparator Voltage Reference ................................ 281 CPU Programmer’s Model .......................................... 35 CRC Module ............................................................. 263 CRC Shift Engine...................................................... 264 CTMU Connections and Internal Configuration for Capacitance Measurement.......................... 283 CTMU Typical Connections and Internal Configuration for Pulse Delay Generation ........ 284 CTMU Typical Connections and Internal Configuration for Time Measurement ............... 284 Data Access From Program Space Address Generation .......................................................... 60 I2C Module ................................................................ 192 Individual Comparator Configurations....................... 278 Input Capture ............................................................ 169 LCD Control .............................................................. 250 Legacy PMP Example............................................... 248 On-Chip Regulator Connections ............................... 293 Output Compare (16-Bit Mode)................................. 174 Output Compare (Double-Buffered 16-Bit PWM Mode) ........................................... 176 PCI24FJ256GB110 Family (General) ......................... 16 PIC24F CPU Core ...................................................... 34 PMP 8-Bit Multiplexed Address and Data Application................................................ 250 PMP EEPROM (8-Bit Data) ...................................... 250 PMP Master Mode, Demultiplexed Addressing ........ 248 PMP Master Mode, Fully Multiplexed Addressing ........................................................ 249 PMP Master Mode, Partially Multiplexed Addressing ........................................................ 249 PMP Module Overview ............................................. 241 PMP Multiplexed Addressing .................................... 249 PMP Parallel EEPROM (16-Bit Data) ....................... 250 PMP Partially Multiplexed Addressing ...................... 249 PSV Operation ............................................................ 62 Reset System.............................................................. 71 RTCC ........................................................................ 251 Shared I/O Port Structure ......................................... 133  2009 Microchip Technology Inc. C C Compilers MPLAB C18.............................................................. 300 Charge Time Measurement Unit. See CTMU. Code Examples Basic Clock Switching Example ............................... 127 Configuring UART1 Input and Output Functions (PPS) ............................................... 140 Erasing a Program Memory Block, ‘C’........................ 67 Erasing a Program Memory Block, Assembly ............ 66 Initiating a Programming Sequence, ‘C’ ..................... 68 Initiating a Programming Sequence, Assembly.......... 68 Loading the Write Buffers, ‘C’..................................... 68 Loading the Write Buffers, Assembly ......................... 67 Port Write/Read ........................................................ 134 PWRSAV Instruction Syntax .................................... 131 Single-Word Flash Programming, ‘C’ ......................... 69 Single-Word Flash Programming, Assembly.............. 69 Code Protection ................................................................ 295 Code Segment Protection ........................................ 295 Configuration Options....................................... 296 Configuration Protection ........................................... 296 Configuration Bits ............................................................. 287 Core Features..................................................................... 11 CPU Arithmetic Logic Unit (ALU) ........................................ 37 Control Registers........................................................ 36 Core Registers............................................................ 35 Programmer’s Model .................................................. 33 CRC Setup Example ......................................................... 263 User Interface ........................................................... 264 CTMU Measuring Capacitance............................................ 283 Measuring Time........................................................ 284 Pulse Delay and Generation..................................... 284 Customer Change Notification Service............................. 348 Customer Notification Service .......................................... 348 Customer Support............................................................. 348 DS39897C-page 343 PIC24FJ256GB110 FAMILY D Data Memory Address Space............................................................ 41 Memory Map ............................................................... 41 Near Data Space ........................................................ 42 SFR Space.................................................................. 42 Software Stack ............................................................ 59 Space Organization .................................................... 42 DC Characteristics I/O Pin Input Specifications ....................................... 318 I/O Pin Output Specifications .................................... 319 Idle Current ............................................................... 315 Operating Current ..................................................... 314 Power-Down Current ................................................ 316 Program Memory Specifications ............................... 319 Development Support ....................................................... 299 Device Features (Summary) 100-Pin........................................................................ 15 64-Pin.......................................................................... 13 80-Pin.......................................................................... 14 Doze Mode........................................................................ 132 E Electrical Characteristics A/D Specifications ..................................................... 325 Absolute Maximum Ratings ...................................... 311 External Clock ........................................................... 322 Internal Voltage Regulator Specifications ................. 320 Load Conditions and Requirements for Specifications.................................................... 321 PLL Clock Specifications .......................................... 323 Temperature and Voltage Specifications .................. 313 Thermal Conditions ................................................... 312 V/F Graph ................................................................. 312 ENVREG Pin..................................................................... 293 Equations A/D Conversion Clock Period ................................... 274 Baud Rate Reload Calculation .................................. 193 Calculating the PWM Period ..................................... 176 Calculation for Maximum PWM Resolution............... 177 Estimating USB Transceiver Current Consumption..................................................... 211 Relationship Between Device and SPI Clock Speed...................................................... 190 RTCC Calibration ...................................................... 260 UART Baud Rate with BRGH = 0 ............................. 200 UART Baud Rate with BRGH = 1 ............................. 200 Errata .................................................................................... 9 F Flash Configuration Words.................................. 40, 287–291 Flash Program Memory....................................................... 63 and Table Instructions................................................. 63 Enhanced ICSP Operation.......................................... 64 JTAG Operation .......................................................... 64 Programming Algorithm .............................................. 66 RTSP Operation.......................................................... 64 Single-Word Programming.......................................... 69 I I/O Ports Analog Port Pins Configuration ................................. 134 Input Change Notification.......................................... 135 Open-Drain Configuration ......................................... 134 Parallel (PIO) ............................................................ 133 DS39897C-page 344 I2C Peripheral Pin Select ................................................ 135 Pull-ups and Pull-downs ........................................... 135 Clock Rates .............................................................. 193 Reserved Addresses ................................................ 193 Setting Baud Rate as Bus Master............................. 193 Slave Address Masking ............................................ 193 Input Capture 32-Bit Mode .............................................................. 170 Capture Operations .................................................. 170 Synchronous and Trigger Modes.............................. 169 Input Capture with Dedicated Timers ............................... 169 Instruction Set Overview................................................................... 305 Summary .................................................................. 303 Inter-Integrated Circuit. See I2C. ...................................... 191 Internet Address ............................................................... 348 Interrupt Vector Table (IVT) ................................................ 77 Interrupts and Reset Sequence .................................................. 77 Control and Status Registers...................................... 80 Implemented Vectors.................................................. 79 Setup and Service Procedures ................................. 119 Trap Vectors ............................................................... 78 Vector Table ............................................................... 78 IrDA Support ..................................................................... 201 J JTAG Interface.................................................................. 297 M Microchip Internet Web Site.............................................. 348 MPLAB ASM30 Assembler, Linker, Librarian ................... 300 MPLAB Integrated Development Environment Software ................................................................... 299 MPLAB PM3 Device Programmer .................................... 302 MPLAB REAL ICE In-Circuit Emulator System ................ 301 MPLINK Object Linker/MPLIB Object Librarian ................ 300 N Near Data Space ................................................................ 42 O Oscillator Configuration Clock Selection ......................................................... 122 Clock Switching ........................................................ 126 Sequence ......................................................... 127 CPU Clocking Scheme ............................................. 122 Initial Configuration on POR ..................................... 122 USB Operation ......................................................... 128 Special Considerations..................................... 129 Output Compare 32-Bit Mode .............................................................. 173 Synchronous and Trigger Modes.............................. 173 Output Compare with Dedicated Timers........................... 173 P Packaging ......................................................................... 327 Details....................................................................... 329 Marking ..................................................................... 327 Parallel Master Port. See PMP. ........................................ 241 Peripheral Enable Bits ...................................................... 132 Peripheral Module Disable Bits......................................... 132  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Peripheral Pin Select (PPS) .............................................. 135 Available Peripherals and Pins ................................. 136 Configuration Control ................................................ 139 Considerations for Use ............................................. 140 Input Mapping ........................................................... 136 Mapping Exceptions.................................................. 139 Output Mapping ........................................................ 136 Peripheral Priority ..................................................... 136 Registers........................................................... 141–159 Pinout Descriptions ....................................................... 17–25 PMSLP Bit and Wake-up Time.................................................... 294 POR and On-Chip Voltage Regulator................................ 294 Power-Saving Features .................................................... 131 Clock Frequency and Clock Switching...................... 131 Instruction-Based Modes .......................................... 131 Idle .................................................................... 132 Sleep................................................................. 131 Power-up Requirements ................................................... 294 Product Identification System ........................................... 350 Program Memory Access Using Table Instructions................................. 61 Address Construction.................................................. 59 Address Space............................................................ 39 Flash Configuration Words ......................................... 40 Memory Maps ............................................................. 39 Organization................................................................ 40 Program Space Visibility ............................................. 62 Program Space Visibility (PSV) .......................................... 62 Pulse-Width Modulation (PWM) Mode .............................. 175 Pulse-Width Modulation. See PWM. PWM Duty Cycle and Period .............................................. 176 R Reader Response ............................................................. 349 Reference Clock Output.................................................... 129 Register Maps A/D Converter ............................................................. 53 Comparators ............................................................... 56 CPU Core.................................................................... 43 CRC ............................................................................ 56 CTMU.......................................................................... 53 I2C............................................................................... 49 ICN.............................................................................. 44 Input Capture .............................................................. 47 Interrupt Controller ...................................................... 45 NVM ............................................................................ 58 Output Compare ......................................................... 48 Pad Configuration ....................................................... 52 Parallel Master/Slave Port .......................................... 55 Peripheral Pin Select .................................................. 57 PMD ............................................................................ 58 PORTA........................................................................ 51 PORTB........................................................................ 51 PORTC ....................................................................... 51 PORTD ....................................................................... 51 PORTE........................................................................ 52 PORTF........................................................................ 52 PORTG ....................................................................... 52 RTCC .......................................................................... 56 SPI .............................................................................. 50 System ........................................................................ 58 Timers ......................................................................... 46 UART .......................................................................... 50 USB OTG.................................................................... 54  2009 Microchip Technology Inc. Registers AD1CHS (A/D Input Select)...................................... 272 AD1CON1 (A/D Control 1)........................................ 269 AD1CON2 (A/D Control 2)........................................ 270 AD1CON3 (A/D Control 3)........................................ 271 AD1CSSL (A/D Input Scan Select, Low) .................. 274 AD1PCFGH (A/D Port Configuration, High) ............. 273 AD1PCFGL (A/D Port Configuration, Low)............... 273 ALCFGRPT (Alarm Configuration) ........................... 255 ALMINSEC (Alarm Minutes and Seconds Value)..... 259 ALMTHDY (Alarm Month and Day Value) ................ 258 ALWDHR (Alarm Weekday and Hours Value) ......... 259 BDnSTAT Prototype (Buffer Descriptor n Status, CPU Mode)........................................... 215 BDnSTAT Prototype (Buffer Descriptor n Status, USB Mode)........................................... 214 CLKDIV (Clock Divider) ............................................ 125 CMSTAT (Comparator Status) ................................. 280 CMxCON (Comparator x Control) ............................ 279 CORCON (CPU Control) ............................................ 37 CORCON (CPU Core Control) ................................... 81 CRCCON (CRC Control) .......................................... 265 CRCXOR (CRC XOR Polynomial) ........................... 266 CTMUCON (CTMU Control)..................................... 285 CTMUICON (CTMU Current Control) ....................... 286 CVRCON (Comparator Voltage Reference Control) ........................................... 282 CW1 (Flash Configuration Word 1) .......................... 288 CW2 (Flash Configuration Word 2) .......................... 290 CW3 (Flash Configuration Word 3) .......................... 291 DEVID (Device ID).................................................... 292 DEVREV (Device Revision)...................................... 292 I2CxCON (I2Cx Control)........................................... 194 I2CxMSK (I2Cx Slave Mode Address Mask)............ 198 I2CxSTAT (I2Cx Status) ........................................... 196 ICxCON1 (Input Capture x Control 1)....................... 171 ICxCON2 (Input Capture x Control 2)....................... 172 IEC0 (Interrupt Enable Control 0) ............................... 90 IEC1 (Interrupt Enable Control 1) ............................... 91 IEC2 (Interrupt Enable Control 2) ............................... 93 IEC3 (Interrupt Enable Control 3) ............................... 94 IEC4 (Interrupt Enable Control 4) ............................... 95 IEC5 (Interrupt Enable Control 5) ............................... 96 IFS0 (Interrupt Flag Status 0) ..................................... 84 IFS1 (Interrupt Flag Status 1) ..................................... 85 IFS2 (Interrupt Flag Status 2) ..................................... 86 IFS3 (Interrupt Flag Status 3) ..................................... 87 IFS4 (Interrupt Flag Status 4) ..................................... 88 IFS5 (Interrupt Flag Status 5) ..................................... 89 INTCON1 (Interrupt Control 1) ................................... 82 INTCON2 (Interrupt Control 2) ................................... 83 INTTREG (Interrupt Control and Status) .................. 118 IPC0 (Interrupt Priority Control 0) ............................... 97 IPC1 (Interrupt Priority Control 1) ............................... 98 IPC10 (Interrupt Priority Control 10) ......................... 107 IPC11 (Interrupt Priority Control 11) ......................... 108 IPC12 (Interrupt Priority Control 12) ......................... 109 IPC13 (Interrupt Priority Control 13) ......................... 110 IPC15 (Interrupt Priority Control 15) ......................... 111 IPC16 (Interrupt Priority Control 16) ......................... 112 IPC18 (Interrupt Priority Control 18) ......................... 113 IPC19 (Interrupt Priority Control 19) ......................... 113 IPC2 (Interrupt Priority Control 2) ............................... 99 IPC20 (Interrupt Priority Control 20) ......................... 114 IPC21 (Interrupt Priority Control 21) ......................... 115 IPC22 (Interrupt Priority Control 22) ......................... 116 IPC23 (Interrupt Priority Control 23) ......................... 117 DS39897C-page 345 PIC24FJ256GB110 FAMILY IPC3 (Interrupt Priority Control 3) ............................. 100 IPC4 (Interrupt Priority Control 4) ............................. 101 IPC5 (Interrupt Priority Control 5) ............................. 102 IPC6 (Interrupt Priority Control 6) ............................. 103 IPC7 (Interrupt Priority Control 7) ............................. 104 IPC8 (Interrupt Priority Control 8) ............................. 105 IPC9 (Interrupt Priority Control 9) ............................. 106 MINSEC (RTCC Minutes and Seconds Value) ......... 257 MTHDY (RTCC Month and Day Value) .................... 256 NVMCON (Flash Memory Control) ............................. 65 OCxCON1 (Output Compare x Control 1) ................ 178 OCxCON2 (Output Compare x Control 2) ................ 179 OSCCON (Oscillator Control) ................................... 123 OSCTUN (FRC Oscillator Tune) ............................... 126 PADCFG1 (Pad Configuration Control) .................... 247 PADCFG1 (Pad Configuration) ................................. 254 PMADDR (PMP Address) ......................................... 245 PMAEN (PMP Enable) .............................................. 245 PMCON (PMP Control) ............................................. 242 PMMODE (Parallel Port Mode) ................................. 244 PMSTAT (PMP Status) ............................................. 246 RCFGCAL (RTCC Calibration and Configuration) ............................................ 253 RCON (Reset Control) ................................................ 72 REFOCON (Reference Oscillator Control)................ 130 RPINR0 (PPS Input 0) .............................................. 141 RPINR1 (PPS Input 1) .............................................. 141 RPINR10 (PPS Input 10) .......................................... 145 RPINR11 (PPS Input 11) .......................................... 145 RPINR15 (PPS Input 15) .......................................... 146 RPINR17 (PPS Input 17) .......................................... 146 RPINR18 (PPS Input 18) .......................................... 147 RPINR19 (PPS Input 19) .......................................... 147 RPINR2 (PPS Input 2) .............................................. 142 RPINR20 (PPS Input 20) .......................................... 148 RPINR21 (PPS Input 21) .......................................... 148 RPINR22 (PPS Input 22) .......................................... 149 RPINR23 (PPS Input 23) .......................................... 149 RPINR27 (PPS Input 27) .......................................... 150 RPINR28 (PPS Input 28) .......................................... 150 RPINR29 (PPS Input 29) .......................................... 151 RPINR3 (PPS Input 3) ...................................... 142, 143 RPINR7 (PPS Input 7) .............................................. 143 RPINR8 (PPS Input 8) .............................................. 144 RPINR9 (PPS Input 9) .............................................. 144 RPOR0 (PPS Output 0) ............................................ 151 RPOR1 (PPS Output 1) ............................................ 152 RPOR10 (PPS Output 10) ........................................ 156 RPOR11 (PPS Output 11) ........................................ 157 RPOR12 (PPS Output 12) ........................................ 157 RPOR13 (PPS Output 13) ........................................ 158 RPOR14 (PPS Output 14) ........................................ 158 RPOR15 (PPS Output 15) ........................................ 159 RPOR2 (PPS Output 2) ............................................ 152 RPOR3 (PPS Output 3) ............................................ 153 RPOR5 (PPS Output 5) ............................................ 154 RPOR6 (PPS Output 6) ............................................ 154 RPOR7 (PPS Output 7) ............................................ 155 RPOR8 (PPS Output 8) ............................................ 155 RPOR9 (PPS Output 9) ............................................ 156 SPIxCON1 (SPIx Control 1) ...................................... 186 SPIxCON2 (SPIx Control 2) ...................................... 187 SPIxSTAT (SPIx Status) ........................................... 184 SR (ALU STATUS) ............................................... 36, 81 T1CON (Timer1 Control)........................................... 162 DS39897C-page 346 TxCON (Timer2 and Timer4 Control) ....................... 166 TyCON (Timer3 and Timer5 Control) ....................... 167 U1ADDR (USB Address) .......................................... 228 U1CNFG1 (USB Configuration 1)............................. 229 U1CNFG2 (USB Configuration 2)............................. 230 U1CON (USB Control, Device Mode)....................... 226 U1CON (USB Control, Host Mode) .......................... 227 U1EIE (USB Error Interrupt Enable) ......................... 237 U1EIR (USB Error Interrupt Status).......................... 236 U1EPn (USB Endpoint n Control)............................. 238 U1IE (USB Interrupt Enable) .................................... 235 U1IR (USB Interrupt Status, Device Mode) .............. 233 U1IR (USB Interrupt Status, Host Mode).................. 234 U1OTGCON (USB OTG Control) ............................. 223 U1OTGIE (USB OTG Interrupt Enable).................... 232 U1OTGIR (USB OTG Interrupt Status)..................... 231 U1OTGSTAT (USB OTG Status) ............................. 222 U1PWMCON USB (VBUS PWM Generator Control)............................................ 239 U1PWRC (USB Power Control)................................ 224 U1SOF (USB OTG Start-Of-Token Threshold) ........ 229 U1STAT (USB Status) .............................................. 225 U1TOK (USB Token) ................................................ 228 UxMODE (UARTx Mode).......................................... 202 UxSTA (UARTx Status and Control)......................... 204 WKDYHR (RTCC Weekday and Hours Value)......... 257 YEAR (RTCC Year Value)........................................ 256 Resets BOR (Brown-out Reset).............................................. 71 Clock Source Selection............................................... 73 CM (Configuration Mismatch Reset)........................... 71 Delay Times................................................................ 74 Device Times .............................................................. 73 IOPUWR (Illegal Opcode Reset) ................................ 71 MCLR (Pin Reset)....................................................... 71 POR (Power-on Reset)............................................... 71 RCON Flags Operation............................................... 73 SFR States ................................................................. 75 SWR (RESET Instruction) .......................................... 71 TRAPR (Trap Conflict Reset) ..................................... 71 UWR (Uninitialized W Register Reset) ....................... 71 WDT (Watchdog Timer Reset) ................................... 71 Revision History................................................................ 341 RTCC Alarm Configuration .................................................. 260 Calibration ................................................................ 260 Register Mapping...................................................... 252 S Selective Peripheral Power Control .................................. 132 Serial Peripheral Interface. See SPI. SFR Space ......................................................................... 42 Software Simulator (MPLAB SIM) .................................... 301 Software Stack.................................................................... 59 Special Features................................................................. 12 SPI T Timer1............................................................................... 161 Timer2/3 and Timer4/5 ..................................................... 163 Timing Diagrams External Clock........................................................... 322  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U V UART ................................................................................ 199 Baud Rate Generator (BRG)..................................... 200 Operation of UxCTS and UxRTS Pins ...................... 201 Receiving .................................................................. 201 Transmitting 8-Bit Data Mode ................................................ 201 9-Bit Data Mode ................................................ 201 Break and Sync Sequence ............................... 201 Universal Asynchronous Receiver Transmitter. See UART. Universal Serial Bus Buffer Descriptors Assignment in Different Buffering Modes ......... 213 Interrupts and USB Transactions ...................................... 217 Universal Serial Bus. See USB OTG. USB On-The-Go (OTG) ...................................................... 12 USB OTG Buffer Descriptors and BDT ...................................... 212 Device Mode Operation ............................................ 217 DMA Interface ........................................................... 213 Hardware Configuration ............................................ 209 Device Mode ..................................................... 209 External Interface.............................................. 211 Host and OTG Modes ....................................... 210 Transceiver Power Requirements .................... 211 VBUS Voltage Generation.................................. 211 Host Mode Operation................................................ 218 Interrupts................................................................... 216 OTG Operation ......................................................... 220 Registers........................................................... 221–239 VBUS Voltage Generation.......................................... 211 VDDCORE/VCAP Pin ........................................................... 293 Voltage Regulator (On-Chip) ............................................ 293 and BOR................................................................... 294 Standby Mode .......................................................... 294 Tracking Mode.......................................................... 293  2009 Microchip Technology Inc. W Watchdog Timer (WDT).................................................... 294 Control Register........................................................ 295 Windowed Operation ................................................ 295 WWW Address ................................................................. 348 WWW, On-Line Support ....................................................... 9 DS39897C-page 347 PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 348  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.  2009 Microchip Technology Inc. DS39897C-page 349 PIC24FJ256GB110 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC24FJ256GB110 Family Literature Number: DS39897C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39897C-page 350  2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 256 GB1 10 T - I / PT - XXX Examples: a) Microchip Trademark Architecture Flash Memory Family b) Program Memory Size (KB) Product Group PIC24FJ64GB106-I/PT: PIC24F device with USB On-The-Go, 64-Kbyte program memory, 64-pin, Industrial temp.,TQFP package. PIC24FJ256GB110-I/PT: PIC24F device with USB On-The-Go, 256-Kbyte program memory, 100-pin, Industrial temp.,TQFP package. Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture 24 = 16-bit modified Harvard without DSP Flash Memory Family FJ = Flash program memory Product Group GB1 = General purpose microcontrollers with USB On-The-Go Pin Count 06 08 10 = 64-pin = 80-pin = 100-pin Temperature Range I = -40C to +85C (Industrial) Package PF PT Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample = 100-lead (14x14x1 mm) TQFP (Thin Quad Flatpack) = 64-lead, 80-lead, 100-lead (12x12x1 mm) TQFP (Thin Quad Flatpack) MR = 64-lead (9x9x0.9 mm) QFN (Quad Flatpack No Leads)  2009 Microchip Technology Inc. DS39897C-page 351 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4080 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 03/26/09 DS39897C-page 352  2009 Microchip Technology Inc.