PIC24FJ256GB210T-I/BG

PIC24FJ256GB210 Family Data Sheet 64/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)  2010 Microchip Technology Inc. DS39975A Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-209-0 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39975A-page 2  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 64/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) Universal Serial Bus Features: Peripheral Features (Continued): • USB v2.0 On-The-Go (OTG) Compliant • Dual Role Capable – Can act as either Host or Peripheral • Low-Speed (1.5 Mbps) and Full-Speed (12 Mbps) USB Operation in Host mode • Full-Speed USB Operation in Device mode • High-Precision PLL for USB • Supports up to 32 Endpoints (16 bidirectional): - USB module can use the internal RAM location from 0x800 to 0xFFFF as USB endpoint buffers • On-Chip USB Transceiver with Interface for Off-Chip Transceiver • Supports Control, Interrupt, Isochronous and Bulk Transfers • On-Chip Pull-up and Pull-Down Resistors • Peripheral Pin Select: - Up to 44 available pins (100-pin devices) • Three 3-Wire/4-Wire SPI modules (supports 4 Frame modes) • Three I2C™ modules Supporting Multi-Master/Slave modes and 7-Bit/10-Bit Addressing • Four UART modules: - Supports RS-485, RS-232, LIN/J2602 protocols and IrDA® • Five 16-Bit Timers/Counters with Programmable Prescaler • Nine 16-Bit Capture Inputs, each with a Dedicated Time Base • Nine 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base • Hardware Real-Time Clock and Calendar (RTCC) • Enhanced Programmable Cyclic Redundancy Check (CRC) Generator • Up to 5 External Interrupt Sources Peripheral Features: • Enhanced Parallel Master Port/Parallel Slave Port (EPMP/PSP): - Direct access from CPU with an Extended Data Space (EDS) interface - 4, 8 and 16-bit wide data bus - Up to 23 programmable address lines - Up to 2 chip select lines - Up to 2 Acknowledgement lines (one per chip select) - Programmable address/data multiplexing - Programmable address and data Wait states - Programmable polarity on control signals SRAM (bytes) Remappable Pins 16-Bit Timers IC/OC PWM UART w/IrDA® SPI I2C™ 10-Bit A/D (ch) Comparators CTMU EPMP/PSP RTCC USB OTG PIC24FJ128GB206 Program Memory (bytes) PIC24FJ Device Pins Remappable Peripherals 64 128K 96K 29 5 9/9 4 3 3 16 3 Y Y Y Y PIC24FJ256GB206 64 256K 96K 29 5 9/9 4 3 3 16 3 Y Y Y Y PIC24FJ128GB210 100/121 128K 96K 44 5 9/9 4 3 3 24 3 Y Y Y Y PIC24FJ256GB210 100/121 256K 96K 44 5 9/9 4 3 3 24 3 Y Y Y Y  2010 Microchip Technology Inc. DS39975A-page 3 PIC24FJ256GB210 FAMILY High-Performance CPU Analog Features: • • • • • • • • 10-Bit, up to 24-Channel Analog-to-Digital (A/D) Converter at 500 ksps: - Operation is possible in Sleep mode - Band gap reference input feature • Three Analog Comparators with Programmable Input/Output Configuration • Charge Time Measurement Unit (CTMU): - Supports capacitive touch sensing for touch screens and capacitive switches - Minimum time measurement setting at 100 ps • Available LVD Interrupt VLVD Level Modified Harvard Architecture Up to 16 MIPS Operation at 32 MHz 8 MHz Internal Oscillator 17-Bit x 17-Bit Single-Cycle Hardware Multiplier 32-Bit by 16-Bit Hardware Divider 16 x 16-Bit Working Register Array C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes • Linear Program Memory Addressing, up to 12 Mbytes • Data Memory Addressing, up to 16 Mbytes: - 2K SFR space - 30K linear data memory - 66K extended data memory - Remaining (from 16 Mbytes) memory (external) can be accessed using extended data Memory (EDS) and EPMP (EDS is divided into 32-Kbyte pages) • Two Address Generation Units for Separate Read and Write Addressing of Data Memory Power Management: • On-Chip Voltage Regulator of 1.8V • Switch between Clock Sources in Real Time • Idle, Sleep and Doze modes with Fast Wake-up and Two-Speed Start-up • Run Mode: 800 A/MIPS, 3.3V Typical • Sleep mode Current Down to 20 A, 3.3V Typical • Standby Current with 32 kHz Oscillator: 22 A, 3.3V Typical DS39975A-page 4 Special Microcontroller Features: • Operating Voltage Range of 2.2V to 3.6V • 5.5V Tolerant Input (digital pins only) • Configurable Open-Drain Outputs on Digital I/O Ports • High-Current Sink/Source (18 mA/18 mA) on all I/O Ports • Selectable Power Management modes: - Sleep, Idle and Doze modes with fast wake-up • Fail-Safe Clock Monitor (FSCM) Operation: - Detects clock failure and switches to on-chip, FRC oscillator • On-Chip LDO Regulator • Power-on Reset (POR) and Oscillator Start-up Timer (OST) • Brown-out Reset (BOR) • Flexible Watchdog Timer (WDT) with On-Chip Low-Power RC Oscillator for Reliable Operation • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via 2 Pins • JTAG Boundary Scan Support • Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Self-reprogrammable under software control - Write protection option for Configuration Words  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD4/CN62/RE4 PMD3/CN61/RE3 PMD2/CN60/RE2 PMD1/CN59/RE1 PMD0/CN58/RE0 VCMPST2/SESSVLD/CN69/RF1 VBUSST/VCMPST1/VBUSVLD/CN68/RF0 ENVREG VCAP C3INA/SESSEND/CN16/RD7 C3INB/CN15/RD6 RP20/PMRD/CN14/RD5 RP25/PMWR/CN13/RD4 RP22/PMBE0/CN52/RD3 DPH/RP23/PMACK1/CN51/RD2 VCPCON/RP24/VBUSCHG/CN50/RD1 Pin Diagram (64-Pin TQFP/QFN) PMD5/CN63/RE5 1 SCL3/PMD6/CN64/RE6 2 SDA3/PMD7/CN65/RE7 3 C1IND/RP21/PMA5/CN8/RG6 4 C1INC/RP26/PMA4/CN9/RG7 5 C2IND/RP19/PMA3/CN10/RG8 6 MCLR 7 C2INC/RP27/PMA2/CN11/RG9 8 46 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/ RC14 SOSCI/C3IND/CN1/RC13 DMH/RP11/INT0/CN49/RD0 45 RP12/PMACK2/CN56/RD11 44 SCL1/RP3/PMA15/PMCS2/CN55/RD10 43 DPLN/SDA1/RP4/PMA14/PMCS1/CN54/RD9 42 RTCC/DMLN/RP2/CN53/RD8 41 VSS(1) OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 48 47 PIC24FJXXXGB206 9 40 VDD 10 39 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 11 38 VDD PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 12 37 D+/CN83/RG2 D-/CN84/RG3 VSS(1) 13 36 14 35 VUSB PGEC1/AN1/VREF-/RP1/CN3/RB1 15 34 VBUS/RF7 PGED1/AN0/VREF+/PMA6/RP0/CN2/RB0 16 33 RP16/USBID/CN71/RF3 PGEC2/AN6/RP6/CN24/RB6 PGED2/AN7/RP7/RCV/CN25/RB7 AVDD AVSS AN8/RP8/CN26/RB8 AN9/RP9/PMA7/CN27/RB9 TMS/CVREF/AN10/PMA13/CN28/RB10 TDO/AN11/PMA12/CN29/RB11 VSS(1) VDD TCK/AN12/CTEDG2/PMA11/CN30/RB12 TDI/AN13CTEDG1/PMA10/CN31/RB13 AN14/CTPLS/RP14/PMA1/CN32/RB14 AN15/RP29/REFO/PMA0/CN12/RB15 SDA2/RP10/PMA9/CN17/RF4 SCL2/RP17/PMA8/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AN3/C2INA/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/CN4/RB2 Note 1: Legend: The back pad on QFN devices should be connected to VSS. RPn and RPIn represents remappable peripheral pins. Shaded pins indicate pins that are tolerant to up to +5.5V.  2010 Microchip Technology Inc. DS39975A-page 5 PIC24FJ256GB210 FAMILY TABLE 1: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 64-PIN DEVICES Pin Function Pin Function 1 PMD5/CN63/RE5 33 RP16/USBID/CN71/RF3 2 SCL3/PMD6/CN64/RE6 34 VBUS/RF7 3 SDA3/PMD7/CN65/RE7 35 VUSB 4 C1IND/RP21/PMA5/CN8/RG6 36 D-/CN84/RG3 5 C1INC/RP26/PMA4/CN9/RG7 37 D+/CN83/RG2 6 C2IND/RP19/PMA3/CN10/RG8 38 VDD 7 MCLR 39 OSCI/CLKI/CN23/RC12 8 C2INC/RP27/PMA2/CN11/RG9 40 OSCO/CLKO/CN22/RC15 9 VSS 41 VSS 10 VDD 42 RTCC/DMLN/RP2/CN53/RD8 11 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 43 DPLN/SDA1/RP4/PMACK2/CN54/RD9 12 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 44 SCL1/RP3/PMA15/PMCS2(1)/CN55/RD10 13 AN3/C2INA/VPIO/CN5/RB3 45 RP12/PMA14/PMCS1(1)/CN56/RD11 14 AN2/C2INB/VMIO/RP13/CN4/RB2 46 DMH/RP11/INT0/CN49/RD0 15 PGEC1/AN1/VREF-/RP1/CN3/RB1 47 SOSCI/C3IND/CN1/RC13 16 PGED1/AN0/VREF+/PMA6/RP0/CN2/RB0 48 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 17 PGEC2/AN6/RP6/CN24/RB6 49 VCPCON/RP24/VBUSCHG/CN50/RD1 18 PGED2/AN7/RP7/RCV/CN25/RB7 50 DPH/RP23/PMACK1/CN51/RD2 19 AVDD 51 RP22/PMBE0/CN52/RD3 20 AVSS 52 RP25/PMWR/CN13/RD4 21 AN8/RP8/CN26/RB8 53 RP20/PMRD/CN14/RD5 22 AN9/RP9/PMA7/CN27/RB9 54 C3INB/CN15/RD6 23 TMS/CVREF/AN10/PMA13/CN28/RB10 55 C3INA/SESSEND/CN16/RD7 24 TDO/AN11/PMA12/CN29/RB11 56 VCAP 25 VSS 57 ENVREG 26 VDD 58 VBUSST/VCMPST1/VBUSVLD/CN68/RF0 27 TCK/AN12/CTEDG2/PMA11/CN30/RB12 59 VCMPST2/SESSVLD/CN69/RF1 28 TDI/AN13/CTEDG1/PMA10/CN31/RB13 60 PMD0/CN58/RE0 29 AN14/CTPLS/RP14/PMA1/CN32/RB14 61 PMD1/CN59/RE1 30 AN15/RP29/REFO/PMA0/CN12/RB15 62 PMD2/CN60/RE2 31 SDA2/RP10/PMA9/CN17/RF4 63 PMD3/CN61/RE3 32 SCL2/RP17/PMA8/CN18/RF5 64 PMD4/CN62/RE4 Legend: Note 1: RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Pin assignment for PMCSx when CSF are not equal to ‘00’. DS39975A-page 6  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY PMD2/CN60/RE2 CN80/RG13 CN79/RG12 PMA16/CN81/RG14 PMD1/CN59/RE1 PMD0/CN58/RE0 AN22/PMA17/CN40/RA7 AN23/CN39/RA6 PMD8/CN77/RG0 PMD9/CN78/RG1 VCMPST2/SESSVLD/PMD10/CN69/RF1 VBUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 ENVREG VCAP C3INA/SESSEND/PMD15/CN16/RD7 C3INB/PMD14/CN15/RD6 RP20/PMRD/CN14/RD5 RP25/PMWR/CN13/RD4 PMD13/CN19/RD13 RPI42/PMD12/CN57/RD12 RP22/PMBE0/CN52/RD3 DPH/RP23/PMACK1/CN51/RD2 VCPCON/RP24/VBUSCHG/CN50/RD1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/CN62/RE4 PMD3/CN61/RE3 Pin Diagram (100-Pin TQFP) 1 75 VDD 2 74 PMD5/CN63/RE5 3 73 SCL3/PMD6/CN64/RE6 SDA3/PMD7/CN65/RE7 4 72 5 71 RPI38/CN45/RC1 6 70 RPI39/CN46/RC2 7 69 RPI40/CN47/RC3 AN16/RPI41/PMCS2/PMA22/CN48/RC4 8 68 9 67 AN17/C1IND/RP21/PMA5/PMA18/CN8/ RG6 10 66 AN18/C1INC/RP26/PMA4/PMA20/CN9/RG7 11 AN19/C2IND/RP19/PMA3/PMA21/CN10/RG8 12 64 VSS SOSCO/SCLKI/TICK/C3INC/ RPI37/CN0/RC14 SOSCI/C3IND/CN1/RC13 DMH/RP11/INT0/CN49/RD0 RP12/PMA14/PMCS1/CN56/RD11 RP3/PMA15/PMCS2/CN55/ RD10 DPLN/RP4/PMACK2/CN54/ RD9 DMLN/RTCC/RP2/CN53/RD8 SDA1/RPI35/PMBE1/CN44/ RA15 SCL1/RPI36/ PMA22/PMCS2/ CN43/RA14 VSS OSCO/CLKO/CN22/RC15 MCLR 13 63 OSCI/CLKI/CN23/RC12 AN20/C2INC/RP27/PMA2/CN11/RG9 VSS 14 62 VDD 15 61 CN82/RG15 65 PIC24FJXXXGB210 16 60 TMS/CN33/RA0 17 59 SDA2/PMA20/PMA4/CN36/RA3 RPI33/PMCS1/CN66/RE8 AN21/RPI34/PMA19/CN67/RE9 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 18 58 SCL2/CN35/RA2 19 57 D+/CN83/RG2 20 56 D-/CN84/RG3 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 21 55 VUSB AN3/C2INA/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/CN4/RB2 22 54 VBUS/CN73/RF7 23 53 RP15/CN74/RF8 PGEC1/AN1/VREF-/RP1/CN3/RB1 24 52 RP30/CN70/RF2 PGED1/AN0/VREF+/RP0/CN2/RB0 25 51 RP16/USBID/CN71/RF3 Legend: VSS VDD RPI43/CN20/RD14 RP5/CN21/RD15 RP10/PMA9/CN17/RF4 RP17/PMA8/CN18/RF5 AVDD AVSS AN8/RP8/CN26/RB8 AN9/RP9/CN27/RB9 AN10/CVREF/PMA13/CN28/RB10 AN11/PMA12/CN29/RB11 VSS VDD TCK/CN34/RA1 RP31/CN76/RF13 RPI32/PMA18/PMA5/CN75/RF12 AN12/PMA11/CTEDG2/CN30/RB12 AN13/PMA10/CTEDG1/CN31/RB13 AN14/CTPLS/RP14/PMA1/CN32/RB14 AN15/REFO/RP29/PMA0/CN12/RB15 PGEC2/AN6/RP6/CN24/RB6 PGED2/AN7/RP7/RCV/CN25/RB7 VREF-/PMA7/CN41/RA9 VREF+/PMA6/CN42/RA10 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD TDO/CN38/RA5 TDI/PMA21/PMA3/CN37/RA4 RPn and RPIn represent remappable peripheral pins. Shaded pins indicate pins that are tolerant to up to +5.5V.  2010 Microchip Technology Inc. DS39975A-page 7 PIC24FJ256GB210 FAMILY TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES Pin Function Pin Function 1 CN82/RG15 41 AN12/PMA11/CTEDG2/CN30/RB12 2 VDD 42 AN13/PMA10/CTEDG1/CN31/RB13 3 PMD5/CN63/RE5 43 AN14/CTPLS/RP14/PMA1/CN32/RB14 4 SCL3/PMD6/CN64/RE6 44 AN15/REFO/RP29/PMA0/CN12/RB15 5 SDA3/PMD7/CN65/RE7 45 VSS 6 RPI38/CN45/RC1 46 VDD 7 RPI39/CN46/RC2 47 RPI43/CN20/RD14 8 RPI40/CN47/RC3 48 RP5/CN21/RD15 9 AN16/RPI41/PMCS2/PMA22(2)/CN48/RC4 49 RP10/PMA9/CN17/RF4 10 AN17/C1IND/RP21/PMA5/PMA18(2)/CN8/RG6 50 RP17/PMA8/CN18/RF5 11 AN18/C1INC/RP26/PMA4/PMA20(2)/CN9/RG7 51 RP16/USBID/CN71/RF3 12 AN19/C2IND/RP19/PMA3/PMA21(2)/CN10/RG8 52 RP30/CN70/RF2 13 MCLR 53 RP15/CN74/RF8 14 AN20/C2INC/RP27/PMA2/CN11/RG9 54 VBUS/CN73/RF7 15 VSS 55 VUSB 16 VDD 56 D-/CN84/RG3 17 TMS/CN33/RA0 57 D+/CN83/RG2 18 RPI33/PMCS1/CN66/RE8 58 SCL2/CN35/RA2 19 AN21/RPI34/PMA19/CN67/RE9 59 SDA2/PMA20/PMA4(2)/CN36/RA3 20 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 60 TDI/PMA21/PMA3(2)/CN37/RA4 21 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 61 TDO/CN38/RA5 22 AN3/C2INA/VPIO/CN5/RB3 62 VDD 23 AN2/C2INB/VMIO/RP13/CN4/RB2 63 OSCI/CLKI/CN23/RC12 24 PGEC1/AN1/VREF-(1)/RP1/CN3/RB1 64 OSCO/CLKO/CN22/RC15 25 PGED1/AN0/VREF+(1)/RP0/CN2/RB0 65 VSS 26 PGEC2/AN6/RP6/CN24/RB6 66 SCL1/RPI36/PMA22/PMCS2(2)/CN43/RA14 27 PGED2/AN7/RP7/RCV/CN25/RB7 67 SDA1/RPI35/PMBE1/CN44/RA15 28 VREF-/PMA7/CN41/RA9 68 DMLN/RTCC/RP2/CN53/RD8 29 VREF+/PMA6/CN42/RA10 69 DPLN/RP4/PMACK2/CN54/RD9 30 AVDD 70 RP3/PMA15/PMCS2(3)/CN55/RD10 31 AVSS 71 RP12/PMA14/PMCS1(3)/CN56/RD11 32 AN8/RP8/CN26/RB8 72 DMH/RP11/INT0/CN49/RD0 33 AN9/RP9/CN27/RB9 73 SOSCI/C3IND/CN1/RC13 34 AN10/CVREF/PMA13/CN28/RB10 74 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 35 AN11/PMA12/CN29/RB11 75 VSS 36 VSS 76 VCPCON/RP24/VBUSCHG/CN50/RD1 37 VDD 77 DPH/RP23/PMACK1/CN51/RD2 38 TCK/CN34/RA1 78 RP22/PMBE0/CN52/RD3 39 RP31/CN76/RF13 79 RPI42/PMD12/CN57/RD12 40 RPI32/PMA18/PMA5(2)/CN75/RF12 80 PMD13/CN19/RD13 Legend: Note 1: 2: 3: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions. Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed (only in 100-pin devices). Pin assignment for PMCSx when CSF is not equal to ‘00’. DS39975A-page 8  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES (CONTINUED) Pin Function Pin Function 81 RP25/PMWR/CN13/RD4 91 AN23/CN39/RA6 82 RP20/PMRD/CN14/RD5 92 AN22/PMA17/CN40/RA7 83 C3INB/PMD14/CN15/RD6 93 PMD0/CN58/RE0 84 C3INA/SESSEND/PMD15/CN16/RD7 94 PMD1/CN59/RE1 85 VCAP 95 PMA16/CN81/RG14 86 ENVREG 96 CN79/RG12 87 VBUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 97 CN80/RG13 88 VCMPST2/SESSVLD/PMD10/CN69/RF1 98 PMD2/CN60/RE2 89 PMD9/CN78/RG1 99 PMD3/CN61/RE3 90 PMD8/CN77/RG0 100 PMD4/CN62/RE4 Legend: Note 1: 2: 3: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions. Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed (only in 100-pin devices). Pin assignment for PMCSx when CSF is not equal to ‘00’.  2010 Microchip Technology Inc. DS39975A-page 9 PIC24FJ256GB210 FAMILY Pin Diagram – Top View (121-Pin BGA)(1) Note 1: Legend: 1 2 3 4 5 6 7 8 9 10 A RE4 RE3 RG13 RE0 RG0 RF1 ENVREG N/C RD12 RD2 RD1 B N/C RG15 RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14 C RE6 VDD RG12 RG14 RA6 N/C RD7 RD4 VDD RC13 RD11 D RC1 RE7 RE5 VSS VSS N/C RD6 RD13 RD0 n/c RD10 E RC4 RC3 RG6 RC2 VDD RG1 N/C RA15 RD8 RD9 RA14 F MCLR RG8 RG9 RG7 VSS n/c N/C VDD OSCI/ RC12 VSS OSCO/ RC15 G RE8 RE9 RA0 N/C VDD VSS VSS N/C RA5 RA3 RA4 H PGEC3/ RB5 PGED3/ RB4 VSS VDD N/C VDD n/c VBUS/RF7 VUSB D+/RG2 RA2 J RB3 RB2 PGED2/RB7 AVDD RB11 RA1 RB12 N/C N/C RF8 D-/RG3 K PGEC1/ RB1 PGED1/ RB0 RA10 RB8 N/C RF12 RB14 VDD RD15 USBID/ RF3 RF2 L PGEC2/ RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5 11 See Table 3 for complete functional pinout descriptions. RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Shaded pins indicate pins tolerant to up to +5.5V. DS39975A-page 10  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN (BGA) DEVICES Pin Function Pin Function A1 PMD4/CN62/RE4 E5 VDD A2 PMD3/CN61/RE3 E6 PMD9/CN78/RG1 A3 CN80/RG13 E7 N/C A4 PMD0/CN58/RE0 E8 SDA1/RPI35/PMBE1/CN44/RA15 A5 PMD8/CN77/RG0 E9 DMLN/RTCC/RP2/CN53/RD8 A6 VCMPST2/SESSVLD/PMD10/CN69/RF1 E10 DPLN/RP4/PMACK2/CN54/RD9 A7 ENVREG E11 SCL1/RPI36/PMA22/PMCS2(2)/CN43/RA14 A8 N/C F1 MCLR A9 RPI42/PMD12/CN57/RD12 F2 AN19/C2IND/RP19/PMA3/PMA21(2)/CN10/RG8 A10 DPH/RP23/PMACK1/CN51/RD2 F3 AN20/C2INC/RP27/PMA2/CN11/RG9 A11 VCPCON/RP24/VBUSCHG/CN50/RD1 F4 AN18/C1INC/RP26/PMA4/PMA20(2)/CN9/RG7 B1 N/C F5 VSS B2 CN82/RG15 F6 N/C B3 PMD2/CN60/RE2 F7 N/C B4 PMD1/CN59/RE1 F8 VDD B5 AN22/PMA17/CN40/RA7 F9 OSCI/CLKI/CN23/RC12 B6 VBUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 F10 VSS B7 VCAP F11 OSCO/CLKO/CN22/RC15 B8 RP20/PMRD/CN14/RD5 G1 RPI33/PMCS1/CN66/RE8 B9 RP22/PMBE0/CN52/RD3 G2 AN21/RPI34/PMA19/CN67/RE9 B10 VSS G3 TMS/CN33/RA0 B11 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 G4 N/C C1 SCL3/PMD6/CN64/RE6 G5 VDD C2 VDD G6 VSS C3 VSYNC/CN79/RG12 G7 VSS C4 PMA16/CN81/RG14 G8 N/C C5 AN23/CN39/RA6 G9 TDO/CN38/RA5 C6 N/C G10 SDA2/PMA20/PMA4(2)/CN36/RA3 C7 C3INA/SESSEND/PMD15/CN16/RD7 G11 TDI/PMA21/PMA3(2)/CN37/RA4 C8 RP25/PMWR/CN13/RD4 H1 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 C9 VDD H2 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 C10 SOSCI/C3IND/CN1/RC13 H3 VSS C11 RP12/PMA14/PMCS1(3)/CN56/RD11 H4 VDD D1 RPI38/CN45/RC1 H5 N/C D2 SDA3/PMD7/CN65/RE7 H6 VDD D3 PMD5/CN63/RE5 H7 N/C D4 VSS H8 VBUS/CN73/RF7 D5 VSS H9 VUSB D6 N/C H10 D+/CN83/RG2 D7 C3INB/PMD14/CN15/RD6 H11 D8 PMD13/CN19/RD13 J1 AN3/C2INA/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/CN4/RB2 SCL2/CN35/RA2 D9 DMH/RP11/INT0/CN49/RD0 J2 D10 N/C J3 PGED2/AN7/RP7/RCV/CN25/RB7 D11 RP3/PMA15/PMCS2(3)/CN55/RD10 J4 AVDD E1 AN16/RPI41/PMCS2/PMA22(2)/CN48/RC4 J5 AN11/PMA12/CN29/RB11 E2 RPI40/CN47/RC3 J6 TCK/CN34/RA1 E3 AN17/C1IND/RP21/PMA5/PMA18(2)/CN8/RG6 J7 AN12/PMA11/CTEDG2/CN30/RB12 E4 RPI39/CN46/RC2 J8 N/C Legend: Note 1: 2: 3: RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed (only in 100-pin devices). Pin assignment for PMCSx when CSF is not equal to ‘00’.  2010 Microchip Technology Inc. DS39975A-page 11 PIC24FJ256GB210 FAMILY TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN (BGA) DEVICES (CONTINUED) Pin Function Pin Function J9 N/C L1 PGEC2/AN6/RP6/CN24/RB6 J10 RP15/CN74/RF8 L2 VREF-(1)/PMA7/CN41/RA9 J11 D-/CN84/RG3 L3 AVSS K1 PGEC1/AN1/VREF-(1)/RP1/CN3/RB1 L4 AN9/RP9/CN27/RB9 K2 PGED1/AN0/VREF+(1)/RP0/CN2/RB0 L5 AN10/CVREF/PMA13/CN28/RB10 K3 VREF+(1)/PMA6/CN42/RA10 L6 RP31/CN76/RF13 K4 AN8/RP8/CN26/RB8 L7 AN13/PMA10/CTEDG1/CN31/RB13 K5 N/C L8 AN15/REFO/RP29/PMA0/CN12/RB15 K6 RPI32/PMA18/PMA5(2)/CN75/RF12 L9 RPI43/CN20/RD14 K7 AN14/CTPLS/RP14/PMA1/CN32/RB14 L10 RP10/PMA9/CN17/RF4 K8 VDD L11 RP17/PMA8/SCL2/CN18/RF5 K9 RP5/CN21/RD15 — — K10 RP16/USBID/CN71/RF3 — — K11 RP30/CN70/RF2 — — Legend: Note 1: 2: 3: RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed (only in 100-pin devices). Pin assignment for PMCSx when CSF is not equal to ‘00’. DS39975A-page 12  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 31 3.0 CPU ........................................................................................................................................................................................... 37 4.0 Memory Organization ................................................................................................................................................................. 43 5.0 Flash Program Memory.............................................................................................................................................................. 79 6.0 Resets ........................................................................................................................................................................................ 85 7.0 Interrupt Controller ..................................................................................................................................................................... 91 8.0 Oscillator Configuration ............................................................................................................................................................ 137 9.0 Power-Saving Features............................................................................................................................................................ 149 10.0 I/O Ports ................................................................................................................................................................................... 151 11.0 Timer1 ...................................................................................................................................................................................... 183 12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 185 13.0 Input Capture with Dedicated Timers ....................................................................................................................................... 191 14.0 Output Compare with Dedicated Timers .................................................................................................................................. 195 15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 205 16.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 217 17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 225 18.0 Universal Serial Bus with On-The-Go Support (USB OTG) ..................................................................................................... 233 19.0 Enhanced Parallel Master Port (EPMP) ................................................................................................................................... 269 20.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 281 21.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 293 22.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 301 23.0 Triple Comparator Module........................................................................................................................................................ 311 24.0 Comparator Voltage Reference................................................................................................................................................ 317 25.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 319 26.0 Special Features ...................................................................................................................................................................... 323 27.0 Development Support............................................................................................................................................................... 335 28.0 Instruction Set Summary .......................................................................................................................................................... 339 29.0 Electrical Characteristics .......................................................................................................................................................... 347 30.0 Packaging Information.............................................................................................................................................................. 363 Appendix A: Revision History............................................................................................................................................................. 375 Index ................................................................................................................................................................................................. 377 The Microchip Web Site ..................................................................................................................................................................... 383 Customer Change Notification Service .............................................................................................................................................. 383 Customer Support .............................................................................................................................................................................. 383 Reader Response .............................................................................................................................................................................. 384 Product Identification System ............................................................................................................................................................ 385  2010 Microchip Technology Inc. DS39975A-page 13 PIC24FJ256GB210 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39975A-page 14  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ128GB206 • PIC24FJ256GB206 • PIC24FJ128GB210 • PIC24FJ256GB210 The PIC24FJ256GB210 family enhances on the existing line of Microchip‘s 16-bit microcontrollers, adding a large data RAM, up to 96 Kbytes. The PIC24FJ256GB210 family allows the CPU to fetch data directly from an external memory device using the EPMP module. 1.1 1.1.1 Core Features 16-BIT ARCHITECTURE Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC® Digital Signal Controllers (DSCs). The PIC24F CPU core offers a wide range of enhancements, such as: • 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces • Linear addressing of up to 12 Mbytes (program space) and 32 Kbytes (data) • A 16-element working register array with built-in software stack support • A 17 x 17 hardware multiplier with support for integer math • Hardware support for 32 by 16-bit division • An instruction set that supports multiple addressing modes and is optimized for high-level languages, such as ‘C’ • Operational performance up to 16 MIPS 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ256GB210 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. • Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. • Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active with a single instruction in software. 1.1.3 OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ256GB210 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. • Two External Clock modes offering the option of a divide-by-2 clock output. • A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. • A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz. • A separate Low-Power Internal RC Oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor (FSCM). This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.1.4 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger, or even in jumping from 64-pin to 100-pin devices. The PIC24F family is pin compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device.  2010 Microchip Technology Inc. DS39975A-page 15 PIC24FJ256GB210 FAMILY 1.2 USB On-The-Go The USB On-The-Go (USB OTG) module provides on-chip functionality as a target device, compatible with the USB 2.0 standard, as well as limited stand-alone functionality as a USB embedded host. By implementing USB Host Negotiation Protocol (HNP), the module can also dynamically switch between device and host operation, allowing for a much wider range of versatile USB enabled applications on a microcontroller platform. In addition to USB host functionality, PIC24FJ256GB210 family devices provide a true single chip USB solution, including an on-chip transceiver and voltage regulator, and a voltage boost generator for sourcing bus power during host operations. 1.3 Other Special Features • Peripheral Pin Select: The Peripheral Pin Select (PPS) feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins. • Communications: The PIC24FJ256GB210 family incorporates a range of serial communication peripherals to handle a range of application requirements. There are three independent I2C™ modules that support both Master and Slave modes of operation. Devices also have, through the PPS feature, four independent UARTs with built-in IrDA® encoders/decoders and three SPI modules. • Analog Features: All members of the PIC24FJ256GB210 family include a 10-bit A/D Converter (ADC) module and a triple comparator module. The ADC module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and faster sampling speeds. The comparator module includes three analog comparators that are configurable for a wide range of operations. • CTMU Interface: In addition to their other analog features, members of the PIC24FJ256GB210 family include the CTMU interface module. This provides a convenient method for precision time measurement and pulse generation, and can serve as an interface for capacitive sensors. DS39975A-page 16 • Enhanced Parallel Master/Parallel Slave Port: There are general purpose I/O ports, which can be configured for parallel data communications. In this mode, the device can be master or slave on the communication bus. 4-bit, 8-bit and 16-bit data transfers, with up to 23 external address lines, are supported in Master modes. • Real-Time Clock and Calendar: (RTCC) This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. 1.4 Details on Individual Family Members Devices in the PIC24FJ256GB210 family are available in 64-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in seven ways: 1. 2. 3. 4. 5. Flash program memory (128 Kbytes for PIC24FJ128GB2XX devices and 256 Kbytes for PIC24FJ256GB2XX devices). Available I/O pins and ports (52 pins on 6 ports for PIC24FJXXXGB2XX devices and 84 pins on 7 ports for PIC24FJXXXGB2XX devices). Available Interrupt-on-Change Notification (ICN) inputs (52 on PIC24FJXXXGB2XX devices and 84 on PIC24FJXXXGB2XX devices). Available remappable pins (29 pins on PIC24FJXXXGB2XX devices and 44 pins on PIC24FJXXXGB2XX devices). Analog channels for ADC (16 channels for PIC24FJXXXGB206 devices and 24 channels for PIC24FJXXXGB2XX devices). All other features for devices in this family are identical. These are summarized in Table 1-1 and Table 1-2. A list of the pin features available on the PIC24FJ256GB210 family devices, sorted by function, is shown in Table 1-1. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256GB210 FAMILY: 64-PIN Features PIC24FJ128GB206 Operating Frequency PIC24FJ256GB206 DC – 32 MHz Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) 128K 256K 44,032 87,552 96K Interrupt Sources (soft vectors/NMI traps) 65 (61/4) I/O Ports Ports B, C, D, E, F, G Total I/O Pins 52 Remappable Pins 29 (28 I/O, 1 Input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 9(1) Output Compare/PWM Channels 9(1) Input Change Notification Interrupt 52 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2C™ 3 Parallel Communications (EPMP/PSP) Yes JTAG Boundary Scan Yes 10-Bit Analog-to-Digital Converter (ADC) Module (input channels) 16 Analog Comparators 3 CTMU Interface Yes USB OTG Yes Resets (and Delays) Instruction Set POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations Packages Note 1: 64-Pin TQFP and QFN Peripherals are accessible through remappable pins.  2010 Microchip Technology Inc. DS39975A-page 17 PIC24FJ256GB210 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256GB210 FAMILY: 100-PIN DEVICES Features PIC24FJ128GB210 Operating Frequency PIC24FJ256GB210 DC – 32 MHz Program Memory (bytes) 128K Program Memory (instructions) 256K 44,032 Data Memory (bytes) 87,552 96K Interrupt Sources (soft vectors/NMI traps) 65 (61/4) I/O Ports Ports A, B, C, D, E, F, G Total I/O Pins 84 Remappable Pins 44 (32 I/O, 12 input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 9(1) Output Compare/PWM Channels 9(1) Input Change Notification Interrupt 84 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2C™ 3 Parallel Communications (EPMP/PSP) Yes JTAG Boundary Scan Yes 10-Bit Analog-to-Digital Converter (ADC) Module (input channels) 24 Analog Comparators 3 CTMU Interface Yes USB OTG Yes Resets (and delays) Instruction Set POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations Packages Note 1: 100-Pin TQFP and 121-Pin BGA Peripherals are accessible through remappable pins. DS39975A-page 18  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY FIGURE 1-1: PIC24FJ256GB210 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller PORTA(1) 16 (12 I/O) 16 16 8 Data Latch EDS and Table Data Access Control Block Data RAM Up to 0x7FFF PCH PCL Program Counter Repeat Stack Control Control Logic Logic 23 Address Latch PORTB (16 I/O) 16 23 16 Read AGU Write AGU Address Latch Program Memory/ Extended Data Space PORTC(1) (8 I/O) Data Latch 16 EA MUX Literal Data Address Bus 24 Inst Latch 16 16 PORTD(1) (16 I/O) Inst Register Instruction Decode and Control Control Signals OSCO/CLKO OSCI/CLKI 16 x 16 W Reg Array Oscillator Start-up Timer FRC/LPRC Oscillators 16-Bit ALU Power-on Reset Precision Band Gap Reference ENVREG 17x17 Multiplier Power-up Timer Timing Generation REFO PORTE(1) Divide Support 16 (10 I/O) PORTF(1) (10 I/O) Watchdog Timer LVD & BOR Voltage Regulator PORTG(1) (12 I/O) VCAP Timer1 VDD, VSS Timer2/3(2) Timer4/5(2) MCLR RTCC 10-Bit ADC Comparators(2) USB OTG EPMP/PSP IC 1-9(2) Note 1: 2: OC/PWM 1-9(2) ICNs(1) SPI 1/2/3(2) I2C™ 1/2/3 UART 1/2/3/4(2) CTMU(2) Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-1 for specific implementations by pin count. These peripheral I/Os are only accessible through remappable pins.  2010 Microchip Technology Inc. DS39975A-page 19 PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS Pin Number 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer AN0 16 25 K2 I ANA AN1 15 24 K1 I ANA AN2 14 23 J2 I ANA AN3 13 22 J1 I ANA AN4 12 21 H2 I ANA AN5 11 20 H1 I ANA AN6 17 26 L1 I ANA AN7 18 27 J3 I ANA AN8 21 32 K4 I ANA AN9 22 33 L4 I ANA AN10 23 34 L5 I ANA Function Description AN11 24 35 J5 I ANA AN12 27 41 J7 I ANA AN13 28 42 L7 I ANA AN14 29 43 K7 I ANA AN15 30 44 L8 I ANA AN16 — 9 E1 I ANA AN17 — 10 E3 I ANA AN18 — 11 F4 I ANA AN19 — 12 F2 I ANA AN20 — 14 F3 I ANA AN21 — 19 G2 I ANA AN22 — 92 B5 I ANA AN23 — 91 C5 I ANA AVDD 19 30 J4 P — Positive Supply for Analog modules. AVSS 20 31 L3 P — Ground Reference for Analog modules. C1INA 11 20 H1 I ANA C1INB 12 21 H2 I ANA Comparator 1 Input B. C1INC 5 11 F4 I ANA Comparator 1 Input C. A/D Analog Inputs. Comparator 1 Input A. C1IND 4 10 E3 I ANA Comparator 1 Input D. C2INA 13 22 J1 I ANA Comparator 2 Input A. C2INB 14 23 J2 I ANA Comparator 2 Input B. C2INC 8 14 F3 I ANA Comparator 2 Input C. C2IND 6 12 F2 I ANA Comparator 2 Input D. C3INA 55 84 C7 I ANA Comparator 3 Input A. C3INB 54 83 D7 I ANA Comparator 3 Input B. C3INC 48 74 B11 I ANA Comparator 3 Input C. C3IND 47 73 C10 I ANA Comparator 3 Input D. CLKI 39 63 F9 I ST Main Clock Input Connection. 40 64 F11 O — System Clock Output. CLKO Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: 2: 3: 4: The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’. DS39975A-page 20 ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 121-Pin BGA I/O Input Buffer 74 B11 I ST 73 C10 I ST 25 K2 I ST 64-Pin TQFP/QFN 100-Pin TQFP CN0 48 CN1 47 CN2 16 CN3 15 24 K1 I ST CN4 14 23 J2 I ST CN5 13 22 J1 I ST CN6 12 21 H2 I ST CN7 11 20 H1 I ST CN8 4 10 E3 I ST CN9 5 11 F4 I ST CN10 6 12 F2 I ST CN11 8 14 F3 I ST CN12 30 44 L8 I ST CN13 52 81 C8 I ST CN14 53 82 B8 I ST CN15 54 83 D7 I ST CN16 55 84 C7 I ST CN17 31 49 L10 I ST CN18 32 50 L11 I ST CN19 — 80 D8 I ST CN20 — 47 L9 I ST CN21 — 48 K9 I ST CN22 40 64 F11 I ST CN23 39 63 F9 I ST CN24 17 26 L1 I ST CN25 18 27 J3 I ST CN26 21 32 K4 I ST CN27 22 33 L4 I ST CN28 23 34 L5 I ST CN29 24 35 J5 I ST CN30 27 41 J7 I ST CN31 28 42 L7 I ST CN32 29 43 K7 I ST CN33 — 17 G3 I ST CN34 — 38 J6 I ST CN35 — 58 H11 I ST CN36 — 59 G10 I ST CN37 — 60 G11 I ST CN38 — 61 G9 I ST — 91 C5 I ST CN39 Description Interrupt-on-Change Inputs. Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: 2: 3: 4: The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’.  2010 Microchip Technology Inc. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39975A-page 21 PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer CN40 — 92 B5 I ST CN41 — 28 L2 I ST CN42 — 29 K3 I ST CN43 — 66 E11 I ST CN44 — 67 E8 I ST CN45 — 6 D1 I ST CN46 — 7 E4 I ST CN47 — 8 E2 I ST CN48 — 9 E1 I ST CN49 46 72 D9 I ST CN50 49 76 A11 I ST CN51 50 77 A10 I ST CN52 51 78 B9 I ST CN53 42 68 E9 I ST CN54 43 69 E10 I ST CN55 44 70 D11 I ST CN56 45 71 C11 I ST CN57 — 79 A9 I ST CN58 60 93 A4 I ST CN59 61 94 B4 I ST CN60 62 98 B3 I ST Function CN61 63 99 A2 I ST CN62 64 100 A1 I ST CN63 1 3 D3 I ST CN64 2 4 C1 I ST CN65 3 5 D2 I ST CN66 — 18 G1 I ST CN67 — 19 G2 I ST CN68 58 87 B6 I ST CN69 59 88 A6 I ST CN70 — 52 K11 I ST CN71 33 51 K10 I ST CN73 — 54 H8 I ST CN74 — 53 J10 I ST CN75 — 40 K6 I ST CN76 — 39 L6 I ST CN77 — 90 A5 I ST CN78 — 89 E6 I ST CN79 — 96 C3 I ST — 97 A3 I ST CN80 Description Interrupt-on-Change Inputs. Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: 2: 3: 4: The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’. DS39975A-page 22 ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer CN81 — 95 C4 I ST CN82 — 1 B2 I ST CN83 37 57 H10 I ST CN84 36 56 J11 I ST CTEDG1 28 42 L7 I ANA CTEDG2 27 41 J7 I ANA CTPLS 29 43 K7 O — Function Description Interrupt-on-Change Inputs. CTMU External Edge Input 1. CTMU External Edge Input 2. CTMU Pulse Output. CVREF 23 34 L5 O — Comparator Voltage Reference Output. D+ 37 57 H10 I/O — USB Differential Plus Line (internal transceiver). D- 36 56 J11 I/O — USB Differential Minus Line (internal transceiver). DMH 46 72 D9 O — D- External Pull-up Control Output. DMLN 42 68 E9 O — D- External Pull-down Control Output. DPH 50 77 A10 O — D+ External Pull-up Control Output. DPLN 43 69 E10 O — D+ External Pull-down Control Output. ENVREG 57 86 J7 I ST Voltage Regulator Enable. INT0 46 72 D9 I ST External Interrupt Input. MCLR 7 13 F1 I ST Master Clear (device Reset) Input. This line is brought low to cause a Reset. OSCI 39 63 F9 I ANA Main Oscillator Input Connection. OSCO 40 64 F11 O ANA Main Oscillator Output Connection. PGEC1 15 24 K1 I/O ST In-Circuit Debugger/Emulator/ICSP™ Programming Clock 1. PGED1 16 25 K2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 1. PGEC2 17 26 L1 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock 2. PGED2 18 27 J3 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 2. PGEC3 11 20 H1 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock 3. 12 21 H2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 3. PGED3 Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: 2: 3: 4: The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’.  2010 Microchip Technology Inc. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39975A-page 23 PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer PMA0 30 44 L8 I/O ST Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). PMA1 29 43 K7 I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). PMA2 8 14 Function F3 (1) O — (1) PMA3 6 12, 60 F2, G11 O — PMA4 5 11,59(1) F4,G10(1) O — PMA5 4 10,40(1) E3,K6(1) O — PMA6 16 29 K3 O — PMA7 22 28 L2 O — PMA8 32 50 L11 O — PMA9 31 49 L10 O — PMA10 28 42 L7 O — Description PMA11 27 41 J7 O — PMA12 24 35 J5 O — PMA13 23 34 L5 O — PMA14 45 71 C11 O — PMA15 44 70 D11 O — PMA16 — 95 C4 O — PMA17 — 92 B5 O — PMA18 — 40,10(1) K6,E3(1) O — PMA19 — 19 G2 O — PMA20 — 59, 11(1) G10, F4(1) O — PMA21 — 60,12(1) G11,F2(1) O — PMA22 — 66,9(1) E11,E1(1) O — PMACK1 50 77 A10 I ST/TTL Parallel Master Port Acknowledge Input 1. PMACK2 43 69 E10 I ST/TTL Parallel Master Port Acknowledge Input 2. PMALL 30 44 L8 O — Parallel Master Port Lower Address Latch Strobe. PMALH 29 43 K7 O — Parallel Master Port Higher Address Latch Strobe. PMALU — 14 F3 O — Parallel Master Port Upper Address Latch Strobe. PMBE0 51 78 B9 O — Parallel Master Port Byte Enable Strobe 0. PMBE1 — 67 E8 O — Parallel Master Port Byte Enable Strobe 1. PMCS1 45 71(3),18 C11(3),G1 I/O 44 70(2),9, D11(2),E1, O PMCS2 66(1) E11(1) Parallel Master Port Address bits. ST/TTL Parallel Master Port Chip Select Strobe 1. — Parallel Master Port Chip Select Strobe 2. Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: 2: 3: 4: The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’. DS39975A-page 24 ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer PMD0 60 93 A4 I/O ST/TTL PMD1 61 94 B4 I/O ST/TTL PMD2 62 98 B3 I/O ST/TTL Function PMD3 63 99 A2 I/O ST/TTL PMD4 64 100 A1 I/O ST/TTL PMD5 1 3 D3 I/O ST/TTL PMD6 2 4 C1 I/O ST/TTL PMD7 3 5 D2 I/O ST/TTL PMD8 — 90 A5 I/O ST/TTL Description Parallel Master Port Data bits. PMD9 — 89 E6 I/O ST/TTL PMD10 — 88 A6 I/O ST/TTL PMD11 — 87 B6 I/O ST/TTL PMD12 — 79 A9 I/O ST/TTL PMD13 — 80 D8 I/O ST/TTL PMD14 — 83 D7 I/O ST/TTL PMD15 — 84 C7 I/O ST/TTL PMRD 53 82 B8 I/O ST/TTL Parallel Master Port Read Strobe. PMWR 52 81 C8 I/O ST/TTL Parallel Master Port Write Strobe. RA0 — 17 G3 I/O RA1 — 38 J6 I/O ST RA2 — 58 H11 I/O ST ST RA3 — 59 G10 I/O ST RA4 — 60 G11 I/O ST RA5 — 61 G9 I/O ST RA6 — 91 C5 I/O ST RA7 — 92 B5 I/O ST RA9 — 28 L2 I/O ST RA10 — 29 K3 I/O ST RA14 — 66 E11 I/O ST — 67 E8 I/O ST RA15 PORTA Digital I/O. Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: 2: 3: 4: The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’.  2010 Microchip Technology Inc. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39975A-page 25 PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer RB0 16 25 K2 I/O ST RB1 15 24 K1 I/O ST RB2 14 23 J2 I/O ST RB3 13 22 J1 I/O ST RB4 12 21 H2 I/O ST RB5 11 20 H1 I/O ST RB6 17 26 L1 I/O ST RB7 18 27 J3 I/O ST RB8 21 32 K4 I/O ST RB9 22 33 L4 I/O ST RB10 23 34 L5 I/O ST Function RB11 24 35 J5 I/O ST RB12 27 41 J7 I/O ST RB13 28 42 L7 I/O ST RB14 29 43 K7 I/O ST RB15 30 44 L8 I/O ST RC1 — 6 D1 I/O ST RC2 — 7 E4 I/O ST RC3 — 8 E2 I/O ST RC4 — 9 E1 I/O ST RC12 39 63 F9 I/O ST RC13 47 73 C10 I/O ST RC14 48 74 B11 I/O ST RC15 40 64 F11 I/O ST RCV 18 27 J3 I ST Description PORTB Digital I/O. PORTC Digital I/O. USB Receive Input (from external transceiver). Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: 2: 3: 4: The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’. DS39975A-page 26 ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer RD0 46 72 D9 I/O ST RD1 49 76 A11 I/O ST RD2 50 77 A10 I/O ST RD3 51 78 B9 I/O ST RD4 52 81 C8 I/O ST RD5 53 82 B8 I/O ST RD6 54 83 D7 I/O ST RD7 55 84 C7 I/O ST RD8 42 68 E9 I/O ST RD9 43 69 E10 I/O ST RD10 44 70 D11 I/O ST RD11 45 71 C11 I/O ST RD12 — 79 A9 I/O ST RD13 — 80 D8 I/O ST RD14 — 47 L9 I/O ST RD15 — 48 K9 I/O ST RE0 60 93 A4 I/O ST RE1 61 94 B4 I/O ST RE2 62 98 B3 I/O ST RE3 63 99 A2 I/O ST RE4 64 100 A1 I/O ST RE5 1 3 D3 I/O ST RE6 2 4 C1 I/O ST RE7 3 5 D2 I/O ST RE8 — 18 G1 I/O ST RE9 — 19 G2 I/O ST REFO 30 44 L8 O — RF0 58 87 B6 I/O ST RF1 59 88 A6 I/O ST RF2 — 52 K11 I/O ST RF3 33 51 K10 I/O ST RF4 31 49 L10 I/O ST RF5 32 50 L11 I/O ST RF7 34 54 H8 I/O ST RF8 — 53 J10 I/O ST RF12 — 40 K6 I/O ST RF13 — 39 L6 I/O ST Description PORTD Digital I/O. PORTE Digital I/O. Reference Clock Output. PORTF Digital I/O. Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: 2: 3: 4: The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’.  2010 Microchip Technology Inc. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39975A-page 27 PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer RG0 — 90 A5 I/O ST RG1 — 89 E6 I/O ST RG2 37 57 H10 I/O ST RG3 36 56 J11 I/O ST RG6 4 10 E3 I/O ST Function RG7 5 11 F4 I/O ST RG8 6 12 F2 I/O ST RG9 8 14 F3 I/O ST RG12 — 96 C3 I/O ST RG13 — 97 A3 I/O ST RG14 — 95 C4 I/O ST RG15 — 1 B2 I/O ST RP0 16 25 K2 I/O ST RP1 15 24 K1 I/O ST RP2 42 68 E9 I/O ST RP3 44 70 D11 I/O ST RP4 43 69 E10 I/O ST RP5 — 48 K9 I/O ST RP6 17 26 L1 I/O ST RP7 18 27 J3 I/O ST RP8 21 32 K4 I/O ST RP9 22 33 L4 I/O ST RP10 31 49 L10 I/O ST RP11 46 72 D9 I/O ST RP12 45 71 C11 I/O ST RP13 14 23 J2 I/O ST RP14 29 43 K7 I/O ST RP15 — 53 J10 I/O ST RP16 33 51 K10 I/O ST RP17 32 50 L11 I/O ST RP18 11 20 H1 I/O ST 6 12 F2 I/O ST RP19 Description PORTG Digital I/O. Remappable Peripheral (input or output). Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: 2: 3: 4: The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’. DS39975A-page 28 ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function Input Buffer 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O RP20 53 82 B8 I/O ST RP21 4 10 E3 I/O ST RP22 51 78 B9 I/O ST RP23 50 77 A10 I/O ST RP24 49 76 A11 I/O ST RP25 52 81 C8 I/O ST RP26 5 11 F4 I/O ST ST RP27 8 14 F3 I/O RP28 12 21 H2 I/O ST RP29 30 44 L8 I/O ST RP30 — 52 K11 I/O ST RP31 — 39 L6 I/O ST RPI32 — 40 K6 I ST RPI33 — 18 G1 I ST RPI34 — 19 G2 I ST RPI35 — 67 E8 I ST RPI36 — 66 E11 I ST RPI37 48 74 B11 I ST RPI38 — 6 D1 I ST RPI39 — 7 E4 I ST RPI40 — 8 E2 I ST RPI41 — 9 E1 I ST RPI42 — 79 A9 I ST ST Description Remappable Peripheral (input or output). Remappable Peripheral (input only). RPI43 — 47 L9 I RTCC 42 68 E9 O — SCL1 44 66 E11 I/O I2C™ I2C1 Synchronous Serial Clock Input/Output. SCL2 32 58 H11 I/O I2C I2C2 Synchronous Serial Clock Input/Output. Real-Time Clock Alarm/Seconds Pulse Output. SCL3 2 4 C1 I/O I2C SCLKI 48 74 B11 O ANA Secondary Clock Input. SDA1 43 67 E8 I/O I2C I2C1 Data Input/Output. SDA2 31 59 G10 I/O I2C I2C2 Data Input/Output. 2 I2C3 Synchronous Serial Clock Input/Output. SDA3 3 5 D2 I/O I C I2C3 Data Input/Output. SESSEND 55 84 C7 I ST USB VBUS Boost Generator, Comparator Input 3. SESSVLD 59 88 A6 I ST USB VBUS Boost Generator, Comparator Input 2. SOSCI 47 73 C10 I ANA SOSCO 48 74 B11 O ANA T1CK 48 74 B11 I ST Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. Timer1 Clock. Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: 2: 3: 4: The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’.  2010 Microchip Technology Inc. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39975A-page 29 PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 121-Pin BGA I/O Input Buffer 38 J6 I ST JTAG Test Clock Input. 60 G11 I ST JTAG Test Data Input. 61 G9 O — JTAG Test Data Output. 64-Pin TQFP/QFN 100-Pin TQFP TCK 27 TDI 28 TDO 24 Description TMS 23 17 G3 I ST JTAG Test Mode Select Input. USBID 33 51 K10 I ST USB OTG ID (OTG mode only). USBOEN 12 21 H2 O — VBUS 34 54 H8 I ANA USB Output Enable Control (for external transceiver). USB Voltage, Host mode (5V). VBUSCHG 49 76 A11 O — VBUSON 11 20 H1 O — VBUSST 58 87 B6 I ANA VBUSVLD 58 87 B6 I ST USB VBUS Boost Generator, Comparator Input 1. VCAP 56 85 B7 P — External Filter Capacitor Connection (regulator enabled). VCMPST1 58 87 B6 I ST USB VBUS Boost Generator, Comparator Input 1. VCMPST2 59 88 A6 I ST USB VBUS Boost Generator, Comparator Input 2. VCPCON 49 76 A11 O — USB OTG VBUS PWM/Charge Output. 10, 26, 38 2, 16, 37, 46, 62 C2, C9, F8, G5, H6, K8, H4, E5 P — Positive Supply for Peripheral Digital Logic and I/O Pins. VMIO 14 23 J2 I ST USB Differential Minus Input/Output (external transceiver). VPIO 13 22 J1 I ST VREF- 15 28, 24(4) L2, K1(4) I ANA A/D and Comparator Reference Voltage (low) Input. VREF+ 16 29, 25(4) K3, K2(4) I ANA A/D and Comparator Reference Voltage (high) Input. 9, 25, 41 15, 36, 45, 65, 75 B10, F5, F10, G6, G7, H3, D4, D5 P — Ground Reference for Logic and I/O Pins. 35 55 H9 P — USB Voltage (3.3V). VDD VSS VUSB External USB VBUS Charge Output. USB OTG External Charge Pump Control. USB OTG Internal Charge Pump Feedback Control. USB Differential Plus Input/Output (external transceiver). Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: 2: 3: 4: The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’. DS39975A-page 30 ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG and VCAP pins (PIC24FJ devices only) (see Section 2.4 “Voltage Regulator Pins (ENVREG and VCAP)”) VDD R2 VCAP C1 C6(2) VSS VDD VDD VSS C3(2) C5(2) C4(2) Key (all values are recommendations): • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 “External Oscillator Pins”) R1: 10 kΩ Note: C7 PIC24FXXXX C1 through C6: 0.1 F, 20V ceramic • VREF+/VREF- pins used when external voltage reference for analog modules is implemented (1) (1) ENVREG MCLR These pins must also be connected if they are being used in the end application: Additionally, the following pins may be required: VSS R1 VSS The following pins must always be connected: C2(2) VDD Getting started with the PIC24FJ256GB210 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. RECOMMENDED MINIMUM CONNECTIONS VDD Basic Connection Requirements FIGURE 2-1: AVSS 2.1 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS AVDD 2.0 C7: 10 F, 6.3V or greater, tantalum or ceramic R2: 100Ω to 470Ω Note 1: 2: See Section 2.4 “Voltage Regulator Pins (ENVREG and VCAP)” for explanation of ENVREG pin connections. The example shown is for a PIC24F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1.  2010 Microchip Technology Inc. DS39975A-page 31 PIC24FJ256GB210 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). • Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. 2.2.2 TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including microcontrollers to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. DS39975A-page 32 2.3 Master Clear (MCLR) Pin The MCLR pin provides two specific device functions: device Reset, and device programming and debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application’s requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD R1 R2 JP MCLR PIC24FXXXX C1 Note 1: R1  10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R2  470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 2.4 Note: Voltage Regulator Pins (ENVREG and VCAP) FIGURE 2-3: This section applies only to PIC24FJ devices with an on-chip voltage regulator. 10 The on-chip voltage regulator enable pin (ENVREG) must always be connected directly to a supply voltage. When the regulator is enabled, a low-ESR (16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4042; // Initialize NVMCON asm("DISI #5"); // Block all interrupts with priority 16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write latches __builtin_tblwtl(offset, progDataL); // Write to address low word __builtin_tblwth(offset, progDataH); // Write to upper byte asm(“DISI #5”); // Block interrupts with priority VBUS_VLD If UVCMPSEL = 1 VBUSVLD SESSVLD SESSEND Bus Condition 0 0 1 VBUS < VB_SESS_END 0 0 0 VB_SESS_END < VBUS < VA_SESS_VLD 0 1 0 VA_SESS_VLD < VBUS < VA_VBUS_VLD 1 1 0 VBUS > VBUS_VLD DS39975A-page 248  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 18.7 USB OTG Module Registers There are a total of 37 memory mapped registers associated with the USB OTG module. They can be divided into four general categories: • • • • USB OTG Module Control (12) USB Interrupt (7) USB Endpoint Management (16) USB VBUS Power Control (2) This total does not include the (up to) 128 BD registers in the BDT. Their prototypes, described in Register 18-1 and Register 18-2, are shown separately in Section 18.2 “USB Buffer Descriptors and the BDT”.  2010 Microchip Technology Inc. With the exception of U1PWMCON and U1PWMRRS, all USB OTG registers are implemented in the Least Significant Byte of the register. Bits in the upper byte are unimplemented and have no function. Note that some registers are instantiated only in Host mode, while other registers have different bit instantiations and functions in Device and Host modes. The registers described in the following sections are those that have bits with specific control and configuration features. The following registers are used for data or address values only: • U1BDTP1: Specifies the 256-word page in data RAM used for the BDT; 8-bit value with Bit 0 fixed as ‘0’ for boundary alignment. • U1FRML and U1FRMH: Contains the 11-bit byte counter for the current data frame. • U1PWMRRS: Contains the 8-bit value for PWM duty cycle bits and PWM period bits for the VBUS boost assist PWM module. DS39975A-page 249 PIC24FJ256GB210 FAMILY 18.7.1 USB OTG MODULE CONTROL REGISTERS REGISTER 18-3: U1OTGSTAT: USB OTG STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0, HSC U-0 R-0, HSC U-0 R-0, HSC R-0, HSC U-0 R-0, HSC ID — LSTATE — SESVD SESEND — VBUSVD bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 ID: ID Pin State Indicator bit 1 = No plug is attached or a type B cable has been plugged into the USB receptacle 0 = A type A plug has been plugged into the USB receptacle bit 6 Unimplemented: Read as ‘0’ bit 5 LSTATE: Line State Stable Indicator bit 1 = The USB line state (as defined by SE0 and JSTATE) has been stable for the previous 1 ms 0 = The USB line state has not been stable for the previous 1 ms bit 4 Unimplemented: Read as ‘0’ bit 3 SESVD: Session Valid Indicator bit 1 = The VBUS voltage is above VA_SESS_VLD (as defined in the “USB 2.0 OTG Specification”) on the A or B-device 0 = The VBUS voltage is below VA_SESS_VLD on the A or B-device bit 2 SESEND: B Session End Indicator bit 1 = The VBUS voltage is below VB_SESS_END (as defined in the “USB 2.0 OTG Specification”) on the B-device 0 = The VBUS voltage is above VB_SESS_END on the B-device bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVD: A VBUS Valid Indicator bit 1 = The VBUS voltage is above VA_VBUS_VLD (as defined in the “USB 2.0 OTG Specification”) on the A-device 0 = The VBUS voltage is below VA_VBUS_VLD on the A-device DS39975A-page 250  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 18-4: U1OTGCON: USB ON-THE-GO CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 DPPULUP DMPULUP R/W-0 R/W-0 DPPULDWN(1) DMPULDWN(1) R/W-0 R/W-0 VBUSON(1) OTGEN(1) R/W-0 R/W-0 VBUSCHG(1) VBUSDIS(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 DPPULUP: D+ Pull-up Enable bit 1 = D+ data line pull-up resistor is enabled 0 = D+ data line pull-up resistor is disabled bit 6 DMPULUP: D- Pull-up Enable bit 1 = D- data line pull-up resistor is enabled 0 = D- data line pull-up resistor is disabled bit 5 DPPULDWN: D+ Pull-Down Enable bit(1) 1 = D+ data line pull-down resistor is enabled 0 = D+ data line pull-down resistor is disabled bit 4 DMPULDWN: D- Pull-Down Enable bit(1) 1 = D- data line pull-down resistor is enabled 0 = D- data line pull-down resistor is disabled bit 3 VBUSON: VBUS Power-on bit(1) 1 = VBUS line is powered 0 = VBUS line is not powered bit 2 OTGEN: OTG Features Enable bit(1) 1 = USB OTG is enabled; all D+/D- pull-up and pull-down bits are enabled 0 = USB OTG is disabled; D+/D- pull-up and pull-down bits are controlled in hardware by the settings of the HOSTEN and USBEN (U1CON) bits bit 1 VBUSCHG: VBUS Charge Select bit(1) 1 = VBUS line is set to charge to 3.3V 0 = VBUS line is set to charge to 5V bit 0 VBUSDIS: VBUS Discharge Enable bit(1) 1 = VBUS line is discharged through a resistor 0 = VBUS line is not discharged Note 1: These bits are only used in Host mode; do not use in Device mode.  2010 Microchip Technology Inc. DS39975A-page 251 PIC24FJ256GB210 FAMILY REGISTER 18-5: U1PWRC: USB POWER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0, HS U-0 U-0 UACTPND — — R/W-0 U-0 U-0 R/W-0, HC R/W-0 USLPGRD — — USUSPND USBPWR bit 7 bit 0 Legend: HS = Hardware Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 UACTPND: USB Activity Pending bit 1 = Module should not be suspended at the moment (requires the USLPGRD bit to be set) 0 = Module may be suspended or powered down bit 6-5 Unimplemented: Read as ‘0’ bit 4 USLPGRD: Sleep/Suspend Guard bit 1 = Indicate to the USB module that it is about to be suspended or powered down 0 = No suspend bit 3-2 Unimplemented: Read as ‘0’ bit 1 USUSPND: USB Suspend Mode Enable bit 1 = USB OTG module is in Suspend mode; USB clock is gated and the transceiver is placed in a low-power state 0 = Normal USB OTG operation bit 0 USBPWR: USB Operation Enable bit 1 = USB OTG module is enabled 0 = USB OTG module is disabled(1) Note 1: Do not clear this bit unless the HOSTEN, USBEN and OTGEN bits (U1CON and U1OTGCON) are all cleared. DS39975A-page 252  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 18-6: U1STAT: USB STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0, HSC ENDPT3 R-0, HSC R-0, HSC ENDPT2 ENDPT1 R-0, HSC ENDPT0 R-0, HSC DIR R-0, HSC (1) PPBI U-0 U-0 — — bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 ENDPT: Number of the Last Endpoint Activity bits (Represents the number of the BDT updated by the last USB transfer.) 1111 = Endpoint 15 1110 = Endpoint 14 . . . 0001 = Endpoint 1 0000 = Endpoint 0 bit 3 DIR: Last BD Direction Indicator bit 1 = The last transaction was a transmit transfer (TX) 0 = The last transaction was a receive transfer (RX) bit 2 PPBI: Ping-Pong BD Pointer Indicator bit(1) 1 = The last transaction was to the odd BD bank 0 = The last transaction was to the even BD bank bit 1-0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown This bit is only valid for endpoints with available even and odd BD registers.  2010 Microchip Technology Inc. DS39975A-page 253 PIC24FJ256GB210 FAMILY REGISTER 18-7: U1CON: USB CONTROL REGISTER (DEVICE MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R-x, HSC R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — SE0 PKTDIS — HOSTEN RESUME PPBRST USBEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6 SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero is active on the USB bus 0 = No single-ended zero is detected bit 5 PKTDIS: Packet Transfer Disable bit 1 = SIE token and packet processing are disabled; automatically set when a SETUP token is received 0 = SIE token and packet processing are enabled bit 4 Unimplemented: Read as ‘0’ bit 3 HOSTEN: Host Mode Enable bit 1 = USB host capability is enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability is disabled bit 2 RESUME: Resume Signaling Enable bit 1 = Resume signaling is activated 0 = Resume signaling is disabled bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the even BD banks 0 = Ping-Pong Buffer Pointers are not reset bit 0 USBEN: USB Module Enable bit 1 = USB module and supporting circuitry are enabled (device attached); D+ pull-up is activated in hardware 0 = USB module and supporting circuitry are disabled (device detached) DS39975A-page 254  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 18-8: U1CON: USB CONTROL REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-x, HSC R-x, HSC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE SE0 TOKBUSY USBRST HOSTEN RESUME PPBRST SOFEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 JSTATE: Live Differential Receiver J-State Flag bit 1 = J-state (differential ‘0’ in low speed, differential ‘1’ in full speed) is detected on the USB 0 = No J-state is detected bit 6 SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero is active on the USB bus 0 = No single-ended zero is detected bit 5 TOKBUSY: Token Busy Status bit 1 = Token is being executed by the USB module in On-The-Go state 0 = No token is being executed bit 4 USBRST: Module Reset bit 1 = USB Reset has been generated for software Reset; application must set this bit for 50 ms, then clear it 0 = USB Reset is terminated bit 3 HOSTEN: Host Mode Enable bit 1 = USB host capability is enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability is disabled bit 2 RESUME: Resume Signaling Enable bit 1 = Resume signaling is activated; software must set bit for 10 ms and then clear to enable remote wake-up 0 = Resume signaling is disabled bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the even BD banks 0 = Ping-Pong Buffer Pointers are not reset bit 0 SOFEN: Start-of-Frame Enable bit 1 = Start-of-Frame token is sent every one 1 ms 0 = Start-of-Frame token is disabled  2010 Microchip Technology Inc. DS39975A-page 255 PIC24FJ256GB210 FAMILY REGISTER 18-9: U1ADDR: USB ADDRESS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 (1) LSPDEN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 LSPDEN: Low-Speed Enable Indicator bit(1) 1 = USB module operates at low speed 0 = USB module operates at full speed bit 6-0 ADDR: USB Device Address bits Note 1: x = Bit is unknown Host mode only. In Device mode, this bit is unimplemented and read as ‘0’. REGISTER 18-10: U1TOK: USB TOKEN REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PID3 PID2 PID1 PID0 EP3 EP2 EP1 EP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 PID: Token Type Identifier bits 1101 = SETUP (TX) token type transaction(1) 1001 = IN (RX) token type transaction(1) 0001 = OUT (TX) token type transaction(1) bit 3-0 EP: Token Command Endpoint Address bits This value must specify a valid endpoint on the attached device. Note 1: x = Bit is unknown All other combinations are reserved and are not to be used. DS39975A-page 256  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 18-11: U-0 — bit 15 U1SOF: USB OTG START-OF-TOKEN THRESHOLD REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ CNT: Start-of-Frame Size bits Value represents 10 + (packet size of n bytes). For example: 0100 1010 = 64-byte packet 0010 1010 = 32-byte packet 0001 0010 = 8-byte packet REGISTER 18-12: U1CNFG1: USB CONFIGURATION REGISTER 1 U-0 — bit 15 R/W-0 UTEYE bit 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — bit 8 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 UOEMON(1) — USBSIDL — — PPB1 PPB0 bit 0 Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 bit 7 Unimplemented: Read as ‘0’ UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test is enabled 0 = Eye pattern test is disabled bit 6 UOEMON: USB OE Monitor Enable bit(1) 1 = OE signal is active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal is inactive Unimplemented: Read as ‘0’ bit 5 bit 4 USBSIDL: USB OTG Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation in Idle mode bit 3-2 bit 1-0 Unimplemented: Read as ‘0’ PPB: Ping-Pong Buffers Configuration bits 11 = Even/Odd Ping-Pong Buffers are enabled for Endpoints 1 to 15 10 = Even/Odd Ping-Pong Buffers are enabled for all endpoints 01 = Even/Odd Ping-Pong Buffers are enabled for OUT Endpoint 0 00 = Even/Odd Ping-Pong Buffers are disabled Note 1: This bit is only active when the UTRDIS bit (U1CNFG2) is set.  2010 Microchip Technology Inc. DS39975A-page 257 PIC24FJ256GB210 FAMILY REGISTER 18-13: U1CNFG2: USB CONFIGURATION REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 — — UVCMPSEL PUVBUS EXTI2CEN R/W-0 R/W-0 UVBUSDIS(1) UVCMPDIS(1) R/W-0 UTRDIS(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 UVCMPSEL: VBUS Comparator External Interface Selection bit 1 = Use VBUSVLD, SESSVLD and SESSEND as comparator interface pins 0 = Use VCMPST1 and VCMPST2 as comparator interface pins bit 4 PUVBUS: VBUS Pull-Up Enable bit 1 = Pull-up on VBUS pin is enabled 0 = Pull-up on VBUS pin is disabled bit 3 EXTI2CEN: I2C™ Interface For External Module Control Enable bit 1 = External module(s) is controlled via the I2C™ interface 0 = External module(s) controlled via the dedicated pins bit 2 UVBUSDIS: On-Chip 5V Boost Regulator Builder Disable bit(1) 1 = On-chip boost regulator builder is disabled; digital output control interface is enabled 0 = On-chip boost regulator builder is active bit 1 UVCMPDIS: On-Chip VBUS Comparator Disable bit(1) 1 = On-chip charge VBUS comparator is disabled; digital input status interface is enabled 0 = On-chip charge VBUS comparator is active bit 0 UTRDIS: On-Chip Transceiver Disable bit(1) 1 = On-chip transceiver is disabled; digital transceiver interface is enabled 0 = On-chip transceiver is active Note 1: Never change these bits while the USBPWR bit is set (U1PWRC = 1). DS39975A-page 258  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 18.7.2 USB INTERRUPT REGISTERS REGISTER 18-14: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS U-0 R/K-0, HS IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IDIF: ID State Change Indicator bit 1 = Change in ID state is detected 0 = No ID state change is detected bit 6 T1MSECIF: 1 Millisecond Timer bit 1 = The 1 millisecond timer has expired 0 = The 1 millisecond timer has not expired bit 5 LSTATEIF: Line State Stable Indicator bit 1 = USB line state (as defined by the SE0 and JSTATE bits) has been stable for 1 ms, but different from the last time 0 = USB line state has not been stable for 1 ms bit 4 ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+/D- lines or VBUS is detected 0 = No activity on the D+/D- lines or VBUS is detected bit 3 SESVDIF: Session Valid Change Indicator bit 1 = VBUS has crossed VA_SESS_END (as defined in the “USB 2.0 OTG Specification”)(1) 0 = VBUS has not crossed VA_SESS_END bit 2 SESENDIF: B-Device VBUS Change Indicator bit 1 = VBUS change on B-device detected; VBUS has crossed VB_SESS_END (as defined in the “USB 2.0 OTG Specification”)(1) 0 = VBUS has not crossed VA_SESS_END bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVDIF: A-Device VBUS Change Indicator bit 1 = VBUS change on A-device is detected; VBUS has crossed VA_VBUS_VLD (as defined in the “USB 2.0 OTG Specification”)(1) 0 = No VBUS change on A-device is detected Note 1: Note: VBUS threshold crossings may be either rising or falling. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.  2010 Microchip Technology Inc. DS39975A-page 259 PIC24FJ256GB210 FAMILY REGISTER 18-15: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 IDIE: ID Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 5 LSTATEIE: Line State Stable Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 ACTVIE: Bus Activity Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 SESVDIE: Session Valid Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 2 SESENDIE: B-Device Session End Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVDIE: A-Device VBUS Valid Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled DS39975A-page 260 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 18-16: U1IR: USB INTERRUPT STATUS REGISTER (DEVICE MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS U-0 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R-0 R/K-0, HS STALLIF — RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent bit 6 Unimplemented: Read as ‘0’ bit 5 RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for full speed) 0 = No K-state is observed bit 4 IDLEIF: Idle Detect Interrupt bit 1 = Idle condition is detected (constant Idle state of 3 ms or more) 0 = No Idle condition is detected bit 3 TRNIF: Token Processing Complete Interrupt bit 1 = Processing of the current token is complete; read the U1STAT register for endpoint information 0 = Processing of the current token is not complete; clear the U1STAT register or load the next token from STAT (clearing this bit causes the STAT FIFO to advance) bit 2 SOFIF: Start-of-Frame Token Interrupt bit 1 = A Start-of-Frame token is received by the peripheral or the Start-of-Frame threshold is reached by the host 0 = No Start-of-Frame token is received or threshold reached bit 1 UERRIF: USB Error Condition Interrupt bit (read-only) 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred bit 0 URSTIF: USB Reset Interrupt bit 1 = Valid USB Reset has occurred for at least 2.5 s; Reset state must be cleared before this bit can be reasserted 0 = No USB Reset has occurred. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.  2010 Microchip Technology Inc. DS39975A-page 261 PIC24FJ256GB210 FAMILY REGISTER 18-17: U1IR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R-0 R/K-0, HS STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF DETACHIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral device during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent bit 6 ATTACHIF: Peripheral Attach Interrupt bit 1 = A peripheral attachment has been detected by the module; it is set if the bus state is not SE0 and there has been no bus activity for 2.5 s 0 = No peripheral attacement has been detected bit 5 RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for full speed) 0 = No K-state is observed bit 4 IDLEIF: Idle Detect Interrupt bit 1 = Idle condition is detected (constant Idle state of 3 ms or more) 0 = No Idle condition is detected bit 3 TRNIF: Token Processing Complete Interrupt bit 1 = Processing of the current token is complete; read the U1STAT register for endpoint information 0 = Processing of the current token not complete; clear the U1STAT register or load the next token from U1STAT bit 2 SOFIF: Start-of-Frame Token Interrupt bit 1 = A Start-of-Frame token received by the peripheral or the Start-of-Frame threshold reached by the host 0 = No Start-of-Frame token received or threshold reached bit 1 UERRIF: USB Error Condition Interrupt bit 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred bit 0 DETACHIF: Detach Interrupt bit 1 = A peripheral detachment has been detected by the module; Reset state must be cleared before this bit can be reasserted 0 = No peripheral detachment is detected. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. DS39975A-page 262  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 18-18: U1IE: USB INTERRUPT ENABLE REGISTER (ALL USB MODES) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 STALLIE ATTACHIE (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RESUMEIE IDLEIE TRNIE SOFIE UERRIE R/W-0 URSTIE DETACHIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 STALLIE: STALL Handshake Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 ATTACHIE: Peripheral Attach Interrupt bit (Host mode only)(1) 1 = Interrupt is enabled 0 = Interrupt is disabled bit 5 RESUMEIE: Resume Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 IDLEIE: Idle Detect Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 TRNIE: Token Processing Complete Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 2 SOFIE: Start-of-Frame Token Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 UERRIE: USB Error Condition Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 0 URSTIE or DETACHIE: USB Reset Interrupt (Device mode) or USB Detach Interrupt (Host mode) Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: Unimplemented in Device mode, read as ‘0’.  2010 Microchip Technology Inc. DS39975A-page 263 PIC24FJ256GB210 FAMILY REGISTER 18-19: U1EIR: USB ERROR INTERRUPT STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS U-0 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS BTSEF — DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF EOFEF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 BTSEF: Bit Stuff Error Flag bit 1 = Bit stuff error has been detected 0 = No bit stuff error has been detected bit 6 Unimplemented: Read as ‘0’ bit 5 DMAEF: DMA Error Flag bit 1 = A USB DMA error condition is detected; the data size indicated by the BD byte count field is less than the number of received bytes, the received data is truncated 0 = No DMA error bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out bit 3 DFN8EF: Data Field Size Error Flag bit 1 = Data field was not an integral number of bytes 0 = Data field was an integral number of bytes bit 2 CRC16EF: CRC16 Failure Flag bit 1 = CRC16 failed 0 = CRC16 passed bit 1 For Device mode: CRC5EF: CRC5 Host Error Flag bit 1 = Token packet is rejected due to CRC5 error 0 = Token packet is accepted (no CRC5 error) For Host mode: EOFEF: End-of-Frame Error Flag bit 1 = End-of-Frame error has occurred 0 = End-of-Frame interrupt is disabled bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. DS39975A-page 264  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 18-20: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE — DMAEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE EOFEE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 DMAEE: DMA Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 For Device mode: CRC5EE: CRC5 Host Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled For Host mode: EOFEE: End-of-Frame Error interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 0 PIDEE: PID Check Failure Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled  2010 Microchip Technology Inc. x = Bit is unknown DS39975A-page 265 PIC24FJ256GB210 FAMILY 18.7.3 USB ENDPOINT MANAGEMENT REGISTERS REGISTER 18-21: U1EPn: USB ENDPOINT n CONTROL REGISTERS (n = 0 TO 15) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 (1) LSPD R/W-0 (1) RETRYDIS U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 LSPD: Low-Speed Direct Connection Enable bit (U1EP0 only)(1) 1 = Direct connection to a low-speed device is enabled 0 = Direct connection to a low-speed device is disabled bit 6 RETRYDIS: Retry Disable bit (U1EP0 only)(1) 1 = Retry NAK transactions is disabled 0 = Retry NAK transactions is enabled; retry is done in hardware bit 5 Unimplemented: Read as ‘0’ bit 4 EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN and EPRXEN = 1: 1 = Disable Endpoint n from control transfers; only TX and RX transfers are allowed 0 = Enable Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed For all other combinations of EPTXEN and EPRXEN: This bit is ignored. bit 3 EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive is enabled 0 = Endpoint n receive is disabled bit 2 EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit is enabled 0 = Endpoint n transmit is disabled bit 1 EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled bit 0 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake is enabled 0 = Endpoint handshake is disabled (typically used for isochronous endpoints) Note 1: These bits are available only for U1EP0 and only in Host mode. For all other U1EPn registers, these bits are always unimplemented and read as ‘0’. DS39975A-page 266  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 18.7.4 USB VBUS POWER CONTROL REGISTER REGISTER 18-22: U1PWMCON: USB VBUS PWM GENERATOR CONTROL REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 PWMEN — — — — — PWMPOL CNTEN bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWMEN: PWM Enable bit 1 = PWM generator is enabled 0 = PWM generator is disabled; output is held in the Reset state specified by PWMPOL bit 14-10 Unimplemented: Read as ‘0’ bit 9 PWMPOL: PWM Polarity bit 1 = PWM output is active-low and resets high 0 = PWM output is active-high and resets low bit 8 CNTEN: PWM Counter Enable bit 1 = Counter is enabled 0 = Counter is disabled bit 7-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. DS39975A-page 267 PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 268  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 19.0 ENHANCED PARALLEL MASTER PORT (EPMP) Note: Key features of the EPMP module are: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 42. “Enhanced Parallel Master Port (EPMP)” (DS39730). The information in this data sheet supersedes the information in the FRM. The Enhanced Parallel Master Port (EPMP) module provides a parallel 4-bit (Master mode only), 8-bit (Master and Slave modes) or 16-bit (Master mode only) data bus interface to communicate with off-chip modules, such as memories, FIFOs, LCD controllers and other microcontrollers. This module can serve as either the master or the slave on the communication bus. For EPMP Master modes, all external addresses are mapped into the internal Extended Data Space (EDS). This is done by allocating a region of the EDS for each chip select, and then assigning each chip select to a particular external resource, such as a memory or external controller. This region should not be assigned to another device resource, such as RAM or SFRs. To perform a write or read on an external resource, the CPU should simply perform a write or read within the address range assigned for EPMP. • Extended Data Space (EDS) Interface allows Direct Access from the CPU • Up to 23 Programmable Address Lines • Up to 2 Chip Select Lines • Up to 2 Acknowledgement Lines (one per chip select) • 4-Bit, 8-Bit or 16-Bit Wide Data Bus • Programmable Strobe Options (per chip select) - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe • Programmable Address/Data Multiplexing • Programmable Address Wait States • Programmable Data Wait States (per chip select) • Programmable Polarity on Control Signals (per chip select) • Legacy Parallel Slave Port Support • Enhanced Parallel Slave Support - Address Support - 4-Byte Deep Auto-Incrementing Buffer 19.1 Many of the lower order EPMP address pins are shared with ADC inputs. This is an untenable situation for users that need both the ADC channels and the EPMP bus. If the user does not need to use all the address bits, then by clearing the ALTPMP (CW3) Configuration bit, the lower order address bits can be mapped to higher address pins, which frees the ADC channels. Note: TABLE 19-1: Note 1: ALTPMP Setting The alternate PMP pin selection is not available in 64-pin devices (PIC24FJXXXGB206) and so the Configuration bit, ALTPMP, is also not available. ALTERNATE EPMP PINS(1) Pin ALTPMP = 0 ALTPMP = 1 RA14 PMCS2 PMA22 RC4 PMA22 PMCS2 RF12 PMA5 PMA18 RG6 PMA18 PMA5 RG7 PMA20 PMA4 RA3 PMA4 PMA20 RG8 PMA21 PMA3 RA4 PMA3 PMA21 The alternate EPMP pins are valid only for 100-pin devices (PIC24FJXXXGB210).  2010 Microchip Technology Inc. DS39975A-page 269 PIC24FJ256GB210 FAMILY TABLE 19-2: PARALLEL MASTER PORT PIN DESCRIPTION Pin Name Type PMA(1) O Address Bus Bits O Address Bus Bit O Chip Select 2 (alternate location) I/O Data Bus Bit when port size is 16 bits and address is multiplexed O Address Bus Bit O Chip Select 1 (alternate location) I/O Data Bus Bit when port size is 16-bit and address is multiplexed O Address Bus Bits I/O Data Bus Bits when port size is 16 bits and address is multiplexed PMA, PMCS2 PMA, PMCS1 PMA Description PMA O Address Bus Bits PMA, PMALU(1) O Address Bus Bit PMA, PMALH PMA, PMALL PMD O Address latch upper strobe for multiplexed address I/O Address Bus Bit O Address latch high strobe for multiplexed address I/O Address Bus Bit O Address latch low strobe for multiplexed address I/O Data Bus Bits when address is not multiplexed I/O Data Bus Bits PMD O Address Bus Bits when port size is 4 bits and address is multiplexed with 1 address phase PMD I/O Data Bus Bits PMCS1 I/O Chip Select 1 PMCS2 O Chip Select 2 PMWR, PMENB I/O Write strobe or enable signal depending on Strobe mode I/O Read strobe or Read/Write signal depending on Strobe mode PMBE1(1) O Byte indicator PMRD, PMRD/PMWR Note 1: PMBE0 O Nibble or byte indicator PMACK1 I Acknowledgment 1 PMACK2 I Acknowledgment 2 Available only in 100-pin devices (PIC24FJXXXGB210). DS39975A-page 270  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 19-1: PMCON1: EPMP CONTROL REGISTER 1 R/W-0 PMPEN bit 15 U-0 — R/W-0 PSIDL R/W-0 ADRMUX1 R/W-0 ADRMUX0 U-0 — R/W-0 MODE1 R/W-0 MODE0 bit 8 R/W-0 CSF1 bit 7 R/W-0 CSF0 R/W-0 ALP R/W-0 ALMODE U-0 — R/W-0 BUSKEEP R/W-0 IRQM1 R/W-0 IRQM0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12-11 bit 10 bit 9-8 bit 7-6 bit 5 bit 4 bit 3 bit 2 bit 1-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PMPEN: Parallel Master Port Enable bit 1 = EPMP is enabled 0 = EPMP is disabled Unimplemented: Read as ‘0’ PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode ADRMUX: Address/Data Multiplexing Selection bits 11 = Lower address bits are multiplexed with data bits using 3 address phases 10 = Lower address bits are multiplexed with data bits using 2 address phases 01 = Lower address bits are multiplexed with data bits using 1 address phase 00 = Address and data appear on separate pins Unimplemented: Read as ‘0’ MODE: Parallel Port Mode Select bits 11 = Master mode 10 = Enhanced PSP; pins used are PMRD, PMWR, PMCS, PMD and PMA 01 = Buffered PSP; pins used are PMRD, PMWR, PMCS and PMD 00 = Legacy Parallel Slave Port; PMRD, PMWR, PMCS and PMD pins are used CSF: Chip Select Function bits 11 = Reserved 10 = PMA used for Chip Select 2, PMA used for Chip Select 1 01 = PMA used for Chip Select 2, PMCS1 used for Chip Select 1 00 = PMCS2 used for Chip Select 2, PMCS1 used for Chip Select 1 ALP: Address Latch Polarity bit 1 = Active-high (PMALL, PMALH and PMALU) 0 = Active-low (PMALL, PMALH and PMALU) ALMODE: Address Latch Strobe Mode bit 1 = Enable “smart” address strobes (each address phase is only present if the current access would cause a different address in the latch than the previous address) 0 = Disable “smart” address strobes Unimplemented: Read as ‘0’ BUSKEEP: Bus Keeper bit 1 = Data bus keeps its last value when not actively being driven 0 = Data bus is in high-impedance state when not actively being driven IRQM: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode), or on a read or write operation when PMA = 11 (Addressable PSP mode only) 10 = Reserved 01 = Interrupt generated at the end of a read/write cycle 00 = No interrupt is generated  2010 Microchip Technology Inc. DS39975A-page 271 PIC24FJ256GB210 FAMILY REGISTER 19-2: R-0, HSC BUSY PMCON2: EPMP CONTROL REGISTER 2 U-0 — R/C-0, HS ERROR R/C-0, HS TIMEOUT U-0 U-0 U-0 U-0 — — — — bit 15 R/W-0 RADDR23 bit 7 bit 8 R/W-0 RADDR22 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11-8 bit 7-0 Note 1: R/W-0 RADDR21 R/W-0 RADDR20 HS = Hardware Settable bit W = Writable bit ‘1’ = Bit is set R/W-0 RADDR19 R/W-0 RADDR18 R/W-0 RADDR17 R/W-0 RADDR16 bit 0 HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ C = Clearable bit ‘0’ = Bit is cleared x = Bit is unknown BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy Unimplemented: Read as ‘0’ ERROR: Error bit 1 = Transaction error (illegal transaction was requested) 0 = Transaction completed successfully TIMEOUT: Time-Out bit 1 = Transaction timed out 0 = Transaction completed successfully Unimplemented: Read as ‘0’ RADDR: Parallel Master Port Reserved Address Space bits(1) If RADDR = 00000000, then the last EDS address for Chip Select 2 will be 0xFFFFFF. DS39975A-page 272  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 19-3: R/W-0 PTWREN bit 15 U-0 — PMCON3: EPMP CONTROL REGISTER 3 R/W-0 PTRDEN R/W-0 PTBE1EN R/W-0 PTBE0EN U-0 — R/W-0 AWAITM1 R/W-0 AWAITM0 R/W-0 AWAITE bit 8 R/W-0 PTEN22(1) R/W-0 PTEN21(1) R/W-0 PTEN20(1) R/W-0 PTEN19(1) R/W-0 PTEN18(1) R/W-0 PTEN17(1) R/W-0 PTEN16(1) bit 0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10-9 bit bit 8 bit 7 bit 6-0 Note 1: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PTWREN: Write/Enable Strobe Port Enable bit 1 = PMWR/PMENB port is enabled 0 = PMWR/PMENB port is disabled PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port is enabled 0 = PMRD/PMWR port is disabled PTBE1EN: High Nibble/Byte Enable Port Enable bit 1 = PMBE1 port is enabled 0 = PMBE1 port is disabled PTBE0EN: Low Nibble/Byte Enable Port Enable bit 1 = PMBE0 port is enabled 0 = PMBE0 port is disabled Unimplemented: Read as ‘0’ AWAITM: Address Latch Strobe Wait States bits 11 = Wait of 3½ TCY 10 = Wait of 2½ TCY 01 = Wait of 1½ TCY 00 = Wait of ½ TCY AWAITE: Address Hold After Address Latch Strobe Wait States bits 1 = Wait of 1¼ TCY 0 = Wait of ¼ TCY Unimplemented: Read as ‘0’ PTEN: EPMP Address Port Enable bits(1) 1 = PMA function as EPMP address lines 0 = PMA function as port I/Os Not available on 64-pin devices (PIC24FJXXXGB206).  2010 Microchip Technology Inc. DS39975A-page 273 PIC24FJ256GB210 FAMILY REGISTER 19-4: PMCON4: EPMP CONTROL REGISTER 4 R/W-0 PTEN15 bit 15 R/W-0 PTEN14 R/W-0 PTEN13 R/W-0 PTEN12 R/W-0 PTEN11 R/W-0 PTEN10 R/W-0 PTEN9 R/W-0 PTEN8 bit 8 R/W-0 PTEN7 bit 7 R/W-0 PTEN6 R/W-0 PTEN5 R/W-0 PTEN4 R/W-0 PTEN3 R/W-0 PTEN2 R/W-0 PTEN1 R/W-0 PTEN0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-3 bit 2-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PTEN15: PMA15 Port Enable bit 1 = PMA15 functions as either Address Line 15 or Chip Select 2 0 = PMA15 functions as port I/O PTEN14: PMA14 Port Enable bit 1 = PMA14 functions as either Address Line 14 or Chip Select 1 0 = PMA14 functions as port I/O PTEN: EPMP Address Port Enable bits 1 = PMA function as EPMP address lines 0 = PMA function as port I/Os PTEN: PMALU/PMALH/PMALL Strobe Enable bits 1 = PMA function as either address lines or address latch strobes 0 = PMA function as port I/Os DS39975A-page 274  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 19-5: PMCSxCF: CHIP SELECT x CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 CSDIS CSP CSPTEN BEP — WRSP RDSP SM bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ACKP PTSZ1 PTSZ0 — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CSDIS: Chip Select x Disable bit 1 = Disable the Chip Select x functionality 0 = Enable the Chip Select x functionality bit 14 CSP: Chip Select x Polarity bit 1 = Active-high (PMCSx) 0 = Active-low (PMCSx) bit 13 CSPTEN: PMCSx Port Enable bit 1 = PMCSx port is enabled 0 = PMCSx port is disabled bit 12 BEP: Chip Select x Nibble/Byte Enable Polarity bit 1 = Nibble/Byte enable is active-high (PMBE0, PMBE1) 0 = Nibble/Byte enable is active-low (PMBE0, PMBE1) bit 11 Unimplemented: Read as ‘0’ bit 10 WRSP: Chip Select x Write Strobe Polarity bit For Slave modes and Master mode when SM = 0: 1 = Write strobe is active-high (PMWR) 0 = Write strobe is active-low (PMWR) For Master mode when SM = 1: 1 = Enable strobe is active-high (PMENB) 0 = Enable strobe is active-low (PMENB) bit 9 RDSP: Chip Select x Read Strobe Polarity bit For Slave modes and Master mode when SM = 0: 1 = Read strobe is active-high (PMRD) 0 = Read strobe is active-low (PMRD) For Master mode when SM = 1: 1 = Read/write strobe is active-high (PMRD/PMWR) 0 = Read/Write strobe is active-low (PMRD/PMWR) bit 8 SM: Chip Select x Strobe Mode bit 1 = Read/Write and enable strobes (PMRD/PMWR and PMENB) 0 = Read and write strobes (PMRD and PMWR) bit 7 ACKP: Chip Select x Acknowledge Polarity bit 1 = ACK is active-high (PMACK1) 0 = ACK is active-low (PMACK1) bit 6-5 PTSZ: Chip Select x Port Size bits 11 = Reserved 10 = 16-bit port size (PMD) 01 = 4-bit port size (PMD) 00 = 8-bit port size (PMD) bit 4-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. x = Bit is unknown DS39975A-page 275 PIC24FJ256GB210 FAMILY REGISTER 19-6: PMCSxBS: CHIP SELECT x BASE ADDRESS REGISTER R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16 bit 15 bit 8 R/W(1) U-0 U-0 U-0 R/W(1) U-0 U-0 U-0 BASE15 — — — BASE11 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 BASE: Chip Select x Base Address bits(2) bit 6-4 Unimplemented: Read as ‘0’ bit 3 BASE: Chip Select x Base Address bits(2) bit 2-0 Unimplemented: Read as ‘0’ Note 1: 2: x = Bit is unknown Value at POR is 0x0200 for PMCS1BS and 0x0600 for PMCS2BS. If the whole PMCS2BS register is written together as 0x0000, then the last EDS address for the Chip Select 1 will be 0xFFFFFF. In this case, the Chip Select 2 should not be used. PMCS1BS has no such feature. DS39975A-page 276  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 19-7: PMCSxMD: CHIP SELECT x MODE REGISTER R/W-0 ACKM1 bit 15 R/W-0 ACKM0 R/W-0 DWAITB1 bit 7 R/W-0 DWAITB0 bit 13-8 bit 7-6 bit 5-2 U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 Legend: R = Readable bit -n = Value at POR bit 15-14 U-0 — R/W-0 DWAITM3 W = Writable bit ‘1’ = Bit is set R/W-0 DWAITM2 R/W-0 DWAITM1 R/W-0 DWAITM0 R/W-0 DWAITE1 R/W-0 DWAITE0 bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ACKM: Chip Select x Acknowledge Mode bits 11 = Reserved 10 = PMACKx is used to determine when a read/write operation is complete 01 = PMACKx is used to determine when a read/write operation is complete with time-out If DWAITM = 0000, the maximum time-out is 255 TCY, else it is DWAITM cycles. 00 = PMACKx is not used Unimplemented: Read as ‘0’ DWAITB: Chip Select x Data Setup Before Read/Write Strobe Wait States bits 11 = Wait of 3¼ TCY 10 = Wait of 2¼ TCY 01 = Wait of 1¼ TCY 00 = Wait of ¼ TCY DWAITM: Chip Select x Data Read/Write Strobe Wait States bits For Write operations: 1111 = Wait of 15½ TCY ... 0001 = Wait of 1½ TCY 0000 = Wait of ½ TCY For Read operations: 1111 = Wait of 15¾ TCY ... bit 1-0 0001 = Wait of 1¾ TCY 0000 = Wait of ¾ TCY DWAITE: Chip Select x Data Hold After Read/Write Strobe Wait States bits For Write operations: 11 = Wait of 3¼ TCY 10 = Wait of 2¼ TCY 01 = Wait of 1¼ TCY 00 = Wait of ¼ TCY For Read operations: 11 = Wait of 3 TCY 10 = Wait of 2 TCY 01 = Wait of 1 TCY 00 = Wait of 0 TCY  2010 Microchip Technology Inc. DS39975A-page 277 PIC24FJ256GB210 FAMILY REGISTER 19-8: PMSTAT: EPMP STATUS REGISTER (SLAVE MODE ONLY) R-0, HSC IBF bit 15 R/W-0 HS IBOV U-0 — U-0 — R-0, HSC IB3F R-0, HSC IB2F R-0, HSC IB1F R-0, HSC IB0F bit 8 R-1, HSC OBE bit 7 R/W-0 HS OBUF U-0 — U-0 — R-1, HSC OB3E R-1, HSC OB2E R-1, HSC OB1E R-1, HSC OB0E bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-12 bit 11-8 bit 7 bit 6 bit 5-4 bit 3-0 Note 1: HS = Hardware Settable bit W = Writable bit ‘1’ = Bit is set HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input register occurred (must be cleared in software) 0 = No overflow occurred Unimplemented: Read as ‘0’ IBxF: Input Buffer x Status Full bit(1) 1 = Input buffer contains unread data (reading buffer will clear this bit) 0 = Input buffer does not contain unread data OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output register (must be cleared in software) 0 = No underflow occurred Unimplemented: Read as ‘0’ OBxE: Output Buffer x Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains untransmitted data Even though an individual bit represents the byte in the buffer, the bits corresponding to the Word (Byte 0 and 1, or Byte 2 and 3) gets cleared even on byte reading. DS39975A-page 278  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 19-9: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RTSECSEL(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: EPMP Module TTL Input Buffer Select bit 1 = EPMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = EPMP module inputs use Schmitt Trigger input buffers Note 1: x = Bit is unknown To enable the actual RTCC output, the RTCOE (RCFGCAL) bit must also be set.  2010 Microchip Technology Inc. DS39975A-page 279 PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 280  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 20.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) • Visibility of half of one second period • Provides calendar – weekday, date, month and year • Alarm configurable for half a second, one second,10 seconds, one minute, 10 minutes, one hour, one day, one week, one month or one year • Alarm repeat with decrementing counter • Alarm with indefinite repeat chime • Years, 2000 to 2099, leap year correction • BCD format for smaller software overhead • Optimized for long-term battery operation • User calibration of the 32.768 kHz clock crystal/32K INTRC frequency with periodic auto-adjust - Calibration to within ±2.64 seconds error per month - Calibrates up to 260 ppm of crystal error This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 29. “Real-Time Clock and Calendar (RTCC)” (DS39696). The information in this data sheet supersedes the information in the FRM. The Real-Time Clock and Calendar (RTCC) provides a function that can be calibrated. Key features of the RTCC module are: • Operates in Sleep mode • Provides hours, minutes and seconds using 24-hour format FIGURE 20-1: RTCC BLOCK DIAGRAM RTCC Clock Domain 32.768 kHz Input from SOSC CPU Clock Domain RCFGCAL RTCC Prescalers ALCFGRPT YEAR 0.5s RTCC Timer Alarm Event MTHDY RTCVAL WKDYHR MINSEC Comparator ALMTHDY Compare Registers with Masks ALRMVAL ALWDHR ALMINSEC Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE  2010 Microchip Technology Inc. DS39975A-page 281 PIC24FJ256GB210 FAMILY 20.1 RTCC Module Registers TABLE 20-2: The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 20.1.1 To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through the corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL) to select the desired Timer register pair (see Table 20-1). By writing the RTCVALH byte, the RTCC Pointer value, RTCPTR bits, decrement by one until they reach ‘00’. Once they reach ‘00’, the MINUTES and SECONDS value will be accessible through RTCVALH and RTCVALL until the pointer value is manually changed. RTCPTR RTCVAL REGISTER MAPPING RTCC Value Register Window RTCVAL RTCVAL 00 MINUTES SECONDS 01 WEEKDAY HOURS 10 MONTH DAY 11 — YEAR The Alarm Value register window (ALRMVALH and ALRMVALL) uses the ALRMPTR bits (ALCFGRPT) to select the desired Alarm register pair (see Table 20-2). By writing the ALRMVALH byte, the Alarm Pointer value bits, ALRMPTR, decrement by one until they reach ‘00’. Once they reach ‘00’, the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed. EXAMPLE 20-1: asm asm asm asm asm asm ALRMVAL ALRMVAL ALRMSEC 01 ALRMWD ALRMHR 10 ALRMMNTH ALRMDAY 11 — — Considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the ALRMVALH or ALRMVALL bytes, they will decrement the ALRMPTR value. The same applies to the RTCVALH or RTCVALL bytes with the RTCPTR being decremented. Note: 20.1.2 This only applies to read operations and not write operations. WRITE LOCK In order to perform a write to any of the RTCC Timer registers, the RTCWREN (RCFGCAL) bit must be set (refer to Example 20-1). Note: To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL) is kept clear at any other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed between the unlock sequence and the setting of RTCWREN; therefore, it is recommended that code follow the procedure in Example 20-1. For applications written in C, the unlock sequence should be implemented using in-line assembly. SETTING THE RTCWREN BIT volatile("disi #5"); volatile("mov #0x55, w7"); volatile("mov w7, _NVMKEY"); volatile("mov #0xAA, w8"); volatile("mov w8, _NVMKEY"); volatile("bset _RCFGCAL, #13"); DS39975A-page 282 Alarm Value Register Window ALRMMIN 00 REGISTER MAPPING TABLE 20-1: ALRMPTR ALRMVAL REGISTER MAPPING //set the RTCWREN bit  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 20.1.3 RTCC CONTROL REGISTERS REGISTER 20-1: R/W-0 RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) U-0 RTCEN(2) R/W-0 — RTCWREN R-0, HSC RTCSYNC R-0, HSC (3) HALFSEC R/W-0 R/W-0, HSC R/W-0, HSC RTCOE RTCPTR1 RTCPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple bit 11 HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second bit 10 RTCOE: RTCC Output Enable bit 1 = RTCC output is enabled 0 = RTCC output is disabled bit 9-8 RTCPTR: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers. The RTCPTR value decrements on every read or write of RTCVALH until it reaches ‘00’. RTCVAL: 11 = Reserved 10 = MONTH 01 = WEEKDAY 00 = MINUTES RTCVAL: 11 = YEAR 10 = DAY 01 = HOURS 00 = SECONDS Note 1: 2: 3: The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.  2010 Microchip Technology Inc. DS39975A-page 283 PIC24FJ256GB210 FAMILY REGISTER 20-1: bit 7-0 RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) CAL: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute . . . 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment . . . 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute Note 1: 2: 3: The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register. REGISTER 20-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — U-0 — U-0 — U-0 R/W-0 R/W-0 — RTSECSEL(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: EPMP Module TTL Input Buffer Select bit 1 = EPMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = EPMP module inputs use Schmitt Trigger input buffers Note 1: x = Bit is unknown To enable the actual RTCC output, the RTCOE (RCFGCAL) bit must also be set. DS39975A-page 284  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 20-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HSC R/W-0, HSC ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 15 bit 8 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT = 00h and CHIME = 0) 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit 1 = Chime is enabled; ARPT bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT bits stop once they reach 00h bit 13-10 AMASK: Alarm Mask Configuration bits 11xx = Reserved – do not use 101x = Reserved – do not use 1001 = Once a year (except when configured for February 29th, once every 4 years) 1000 = Once a month 0111 = Once a week 0110 = Once a day 0101 = Every hour 0100 = Every 10 minutes 0011 = Every minute 0010 = Every 10 seconds 0001 = Every second 0000 = Every half second bit 9-8 ALRMPTR: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers. The ALRMPTR value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVAL: 11 = Unimplemented 10 = ALRMMNTH 01 = ALRMWD 00 = ALRMMIN ALRMVAL: 11 = Unimplemented 10 = ALRMDAY 01 = ALRMHR 00 = ALRMSEC bit 7-0 ARPT: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times ... 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1.  2010 Microchip Technology Inc. DS39975A-page 285 PIC24FJ256GB210 FAMILY 20.1.4 RTCVAL REGISTER MAPPINGS REGISTER 20-4: YEAR: YEAR VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 YRTEN: Binary Coded Decimal Value of Year’s Tens Digit bits Contains a value from 0 to 9. bit 3-0 YRONE: Binary Coded Decimal Value of Year’s Ones Digit bits Contains a value from 0 to 9. Note 1: x = Bit is unknown A write to the YEAR register is only allowed when RTCWREN = 1. REGISTER 20-5: MTHDY: MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. bit 11-8 MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN = 1. DS39975A-page 286  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 20-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x, HSC R/W-x, HSC R/W-x, HSC — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: x = Bit is unknown A write to this register is only allowed when RTCWREN = 1. REGISTER 20-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2010 Microchip Technology Inc. x = Bit is unknown DS39975A-page 287 PIC24FJ256GB210 FAMILY 20.1.5 ALRMVAL REGISTER MAPPINGS REGISTER 20-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. bit 11-8 MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN = 1. DS39975A-page 288  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 20-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN = 1. REGISTER 20-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2010 Microchip Technology Inc. x = Bit is unknown DS39975A-page 289 PIC24FJ256GB210 FAMILY 20.2 Calibration The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses for one minute and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value loaded into the lower half of RCFGCAL is multiplied by four and will either be added or subtracted from the RTCC timer, once every minute. Refer to the following steps for RTCC calibration: 1. 2. Using another timer resource on the device, the user must find the error of the 32.768 kHz crystal. Once the error is known, it must be converted to the number of error clock pulses per minute and loaded into the RCFGCAL register. EQUATION 20-1: RTCC CALIBRATION Error (clocks per minute) = (Ideal Frequency† – Measured Frequency) x 60 †Ideal Frequency = 32,768H 3. a) If the oscillator is faster then ideal (negative result form Step 2), the RCFGCAL register value needs to be negative. This causes the specified number of clock pulses to be subtracted from the timer counter, once every minute. b) If the oscillator is slower then ideal (positive result from Step 2), the RCFGCAL register value needs to be positive. This causes the specified number of clock pulses to be added to the timer counter, once every minute. 4. Divide the number of error clocks per minute by 4 to get the correct CAL value and load the RCFGCAL register with the correct value. (Each 1-bit increment in CAL adds or subtracts 4 pulses). Writes to the lower half of the RCFGCAL register should only occur when the timer is turned off or immediately after the rising edge of the seconds pulse. Note: It is up to the user to include in the error value the initial error of the crystal, drift due to temperature and drift due to crystal aging. DS39975A-page 290 20.3 Alarm • Configurable from half second to one year • Enabled using the ALRMEN bit (ALCFGRPT, Register 20-3) • One-time alarm and repeat alarm options available 20.3.1 CONFIGURING THE ALARM The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. Writes to ALRMVAL should only take place when ALRMEN = 0. As shown in Figure 20-2, the interval selection of the alarm is configured through the AMASK bits (ALCFGRPT). These bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. The alarm can also be configured to repeat based on a preconfigured interval. The amount of times this occurs, once the alarm is enabled, is stored in the ARPT bits, ARPT (ALCFGRPT). When the value of the ARPT bits equals 00h and the CHIME bit (ALCFGRPT) is cleared, the repeat function is disabled and only a single alarm will occur. The alarm can be repeated up to 255 times by loading ARPT with FFh. After each alarm is issued, the value of the ARPT bits is decremented by one. Once the value has reached 00h, the alarm will be issued one last time, after which the ALRMEN bit will be cleared automatically and the alarm will turn off. Indefinite repetition of the alarm can occur if the CHIME bit = 1. Instead of the alarm being disabled when the value of the ARPT bits reaches 00h, it rolls over to FFh and continues counting indefinitely while CHIME is set. 20.3.2 ALARM INTERRUPT At every alarm event, an interrupt is generated. In addition, an alarm pulse output is provided that operates at half the frequency of the alarm. This output is completely synchronous to the RTCC clock and can be used as a trigger clock to other peripherals. Note: Changing any of the registers, other then the RCFGCAL and ALCFGRPT registers and the CHIME bit while the alarm is enabled (ALRMEN = 1), can result in a false alarm event leading to a false alarm interrupt. To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0). It is recommended that the ALCFGRPT register and CHIME bit be changed when RTCSYNC = 0.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY FIGURE 20-2: ALARM MASK SETTINGS Alarm Mask Setting (AMASK) Day of the Week Month Day Hours Minutes Seconds 0000 – Every half second 0001 – Every second 0010 – Every 10 seconds s 0011 – Every minute s s m s s m m s s 0100 – Every 10 minutes 0101 – Every hour 0110 – Every day 0111 – Every week d 1000 – Every month 1001 – Every year(1) Note 1: m m h h m m s s h h m m s s d d h h m m s s d d h h m m s s Annually, except when configured for February 29.  2010 Microchip Technology Inc. DS39975A-page 291 PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 292  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 21.0 32-BIT PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR Note: The 32-bit programmable CRC generator provides a hardware implemented method of quickly generating checksums for various networking and security applications. It offers the following features: • User-programmable CRC polynomial equation, up to 32 bits • Programmable shift direction (little or big-endian) • Independent data and polynomial lengths • Configurable interrupt output • Data FIFO This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 41. “32-Bit Programmable Cyclic Redundancy Check (CRC)” (DS39729). The information in this data sheet supersedes the information in the FRM. FIGURE 21-1: Figure 21-1 displays a simplified block diagram of the CRC generator. A simple version of the CRC shift engine is displayed in Figure 21-2. CRC BLOCK DIAGRAM CRCDATH CRCDATL Variable FIFO (4x32, 8x16 or 16x8) FIFO Empty Event CRCWDATH CRCISEL CRCWDATL 1 0 LENDIAN Shift Buffer CRC Interrupt 1 CRC Shift Engine 0 Shift Complete Event Shifter Clock 2 * FCY FIGURE 21-2: CRC SHIFT ENGINE DETAIL CRC Shift Engine CRCWDATH CRCWDATL Read/Write Bus X0 Shift Buffer Data Note 1: Xn(1) X1 Bit 0 Bit 1 Bit n(1) n = PLEN + 1.  2010 Microchip Technology Inc. DS39975A-page 293 PIC24FJ256GB210 FAMILY 21.1 21.1.1 User Interface 21.1.2 POLYNOMIAL INTERFACE The CRC module can be programmed for CRC polynomials of up of up the 32nd order, using up to 32 bits. Polynomial length, which reflects the highest exponent in the equation, is selected by the PLEN bits (CRCCON2). The CRCXORL and CRCXORH registers control which exponent terms are included in the equation. Setting a particular bit includes that exponent term in the equation; functionally, this includes an XOR operation on the corresponding bit in the CRC engine. Clearing the bit disables the XOR. For example, consider two CRC polynomials, one a 16-bit and the other a 32-bit equation. DATA INTERFACE The module incorporates a FIFO that works with a variable data width. Input data width can be configured to any value between one and 32 bits using the DWIDTH bits (CRCCON2). When the data width is greater than 15, the FIFO is four words deep. When the DWITDH bits are between 15 and 8, the FIFO is 8 words deep. When the DWIDTH bits are less than 8, the FIFO is 16 words deep. The data for which the CRC is to be calculated must first be written into the FIFO. Even if the data width is less than 8, the smallest data element that can be written into the FIFO is one byte. For example, if DWIDTH is five, then the size of the data is DWIDTH + 1 or six. The data is written as a whole byte; the two unused upper bits are ignored by the module. and Once data is written into the MSb of the CRCDAT registers (that is, MSb as defined by the data width), the value of the VWORD bits (CRCCON1) increments by one. For example, if DWIDTH is 24, the VWORD bits will increment when bit 7 of CRCDATH is written. Therefore, CRCDATL must always be written to before CRCDATH. X32+X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 The CRC engine starts shifting data when the CRCGO bit is set and the value of VWORD is greater than zero. EQUATION 21-1: 16-BIT, 32-BIT CRC POLYNOMIALS X16 + X12 + X5 + 1 To program these polynomials into the CRC generator, set the register bits as shown in Table 21-1. Note that the appropriate positions are set to ‘1’ to indicate they are used in the equation (for example, X26 and X23). The ‘0’ bit required by the equation is always XORed; thus, X0 is a don’t care. For a polynomial of length 32, it is assumed that the 32nd bit will be used. Therefore, the X bits do not have the 32nd bit. Each word is copied out of the FIFO into a buffer register, which decrements VWORD. The data is then shifted out of the buffer. The CRC engine continues shifting at a rate of two bits per instruction cycle, until VWORD reaches zero. This means that for a given data width, it takes half that number of instructions for each word to complete the calculation. For example, it takes 16 cycles to calculate the CRC for a single word of 32-bit data. When VWORD reaches the maximum value for the configured value of DWIDTH (4, 8 or 16), the CRCFUL bit becomes set. When VWORD reaches zero, the CRCMPT bit becomes set. The FIFO is emptied and the VWORD bits are set to ‘00000’ whenever CRCEN is ‘0’. At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORD bits is done. TABLE 21-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALS CRC Control Bits Bit Values 16-Bit Polynomial 32-Bit Polynomial PLEN 01111 11111 X 0000 0000 0000 0001 0000 0100 1100 0001 X 0001 0000 0010 000X 0001 1101 1011 011x DS39975A-page 294  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 21.1.3 DATA SHIFT DIRECTION The LENDIAN bit (CRCCON1) is used to control the shift direction. By default, the CRC will shift data through the engine, MSb first. Setting LENDIAN (= 1) causes the CRC to shift data, LSb first. This setting allows better integration with various communication schemes and removes the overhead of reversing the bit order in software. Note that this only changes the direction the data is shifted into the engine. The result of the CRC calculation will still be a normal CRC result, not a reverse CRC result. 21.1.4 3. 4. 5. 6. 7. INTERRUPT OPERATION Preload the FIFO by writing to the CRCDATL and CRCDATH registers until the CRCFUL bit is set or no data is left. Clear old results by writing 00h to CRCWDATL and CRCWDATH. The CRCWDAT registers can also be left unchanged to resume a previously halted calculation. Set the CRCGO bit to start calculation. Write remaining data into the FIFO as space becomes available. When the calculation completes, CRCGO is automatically cleared. An interrupt will be generated if CRCISEL = 1. Read CRCWDATL and CRCWDATH for the result of the calculation. The module generates an interrupt that is configurable by the user for either of two conditions. 8. If CRCISEL is ‘0’, an interrupt is generated when the VWORD bits make a transition from a value of ‘1’ to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated after the CRC operation finishes and the module sets the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’ will not generate an interrupt. Note that when an interrupt occurs, the CRC calculation would not yet be complete. The module will still need (PLEN + 1)/2 clock cycles after the interrupt is generated until the CRC calculation is finished. There are eight registers used to control programmable CRC operation: 21.1.5 TYPICAL OPERATION To use the module for a typical CRC calculation: 1. 2. Set the CRCEN bit to enable the module. Configure the module for desired operation: a) Program the desired polynomial using the CRCXORL and CRCXORH registers, and the PLEN bits. b) Configure the data width and shift direction using the DWIDTH and LENDIAN bits. c) Select the desired interrupt mode using the CRCISEL bit.  2010 Microchip Technology Inc. • • • • • • • • CRCCON1 CRCCON2 CRCXORL CRCXORH CRCDATL CRCDATH CRCWDATL CRCWDATH The CRCCON1 and CRCCON2 registers (Register 21-1 and Register 21-2) control the operation of the module and configure the various settings. The CRCXOR registers (Register 21-3 and Register 21-4) select the polynomial terms to be used in the CRC equation. The CRCDAT and CRCWDAT registers are each register pairs that serve as buffers for the double-word input data, and CRC processed output, respectively. DS39975A-page 295 PIC24FJ256GB210 FAMILY REGISTER 21-1: CRCCON1: CRC CONTROL 1 REGISTER R/W-0 U-0 R/W-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 R-0, HSC CRCFUL bit 8 R-1, HSC CRCMPT R/W-0 CRCISEL R/W-0, HC CRCGO R/W-0 U-0 U-0 U-0 LENDIAN — — — bit 7 bit 0 Legend: HC = Hardware Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CRCEN: CRC Enable bit 1 = Enables module 0 = Disables module; all state machines, pointers and CRCWDAT/CRCDATH reset; other SFRs are NOT reset bit 14 Unimplemented: Read as ‘0’ bit 13 CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-8 VWORD: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN  7 or 16 when PLEN 7. bit 7 CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: FIFO Empty bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 CRCISEL: CRC Interrupt Selection bit 1 = Interrupt on FIFO is empty; the final word of data is still shifting through the CRC 0 = Interrupt on shift is complete and results are ready bit 4 CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter is turned off bit 3 LENDIAN: Data Shift Direction Select bit 1 = Data word is shifted into the CRC, starting with the LSb (little endian) 0 = Data word is shifted into the CRC, starting with the MSb (big endian) bit 2-0 Unimplemented: Read as ‘0’ DS39975A-page 296  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 21-2: CRCCON2: CRC CONTROL 2 REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 DWIDTH: Data Word Width Configuration bits Configures the width of the data word (data word width – 1). bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 PLEN: Polynomial Length Configuration bits Configures the length of the polynomial (polynomial length – 1). REGISTER 21-3: CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X15 X14 X13 X12 X11 X10 X9 X8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 X7 X6 X5 X4 X3 X2 X1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 X: XOR of Polynomial Term xn Enable bits bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. x = Bit is unknown DS39975A-page 297 PIC24FJ256GB210 FAMILY REGISTER 21-4: CRCXORH: CRC XOR HIGH REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X31 X30 X29 X28 X27 X26 X25 X24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X23 X22 X21 X20 X19 X18 X17 X16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown X: XOR of Polynomial Term xn Enable bits REGISTER 21-5: CRCDATL: CRC DATA LOW REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown DATA: CRC Input Data bits Writing to this register fills the FIFO; reading from this register returns ‘0’. REGISTER 21-6: CRCDATH: CRC DATA HIGH REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown DATA: CRC Input Data bits Writing to this register fills the FIFO; reading from this register returns ‘0’. DS39975A-page 298  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 21-7: CRCWDATL: CRC SHIFT LOW REGISTER R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC SDATA15 SDATA14 SDATA13 SDATA12 SDATA11 SDATA10 SDATA9 SDATA8 bit 15 bit 8 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC SDATA7 SDATA6 SDATA5 SDATA4 SDATA3 SDATA2 SDATA1 SDATA0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown SDATA: CRC Shift Register bits Writing to this register writes to the CRC Shift register through the CRC write bus. Reading from this register reads the CRC read bus. REGISTER 21-8: CRCWDATH: CRC SHIFT HIGH REGISTER R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC SDATA31 SDATA30 SDATA29 SDATA28 SDATA27 SDATA26 SDATA25 SDATA24 bit 15 bit 8 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC SDATA23 SDATA22 SDATA21 SDATA20 SDATA19 SDATA18 SDATA17 SDATA16 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown SDATA: CRC Input Data bits Writing to this register writes to the CRC Shift register through the CRC write bus. Reading from this register reads the CRC read bus.  2010 Microchip Technology Inc. DS39975A-page 299 PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 300  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 22.0 Note: 10-BIT HIGH-SPEED A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 17. “10-Bit A/D Converter” (DS39705). The information in this data sheet supersedes the information in the FRM. A block diagram of the A/D Converter is shown in Figure 22-1. To perform an A/D conversion: 1. The 10-bit A/D Converter has the following key features: • Successive Approximation (SAR) conversion • Conversion speeds of up to 500 ksps • 24 analog input pins (PIC24FJXXXGBX10 devices) and 16 analog input pins (PIC24FJXXXGBX06 devices) • External voltage reference input pins • Internal band gap reference inputs • Automatic Channel Scan mode • Selectable conversion trigger source • 32-word conversion result buffer • Selectable Buffer Fill modes • Four result alignment options • Operation during CPU Sleep and Idle modes 2. Configure the A/D module: a) Configure the port pins as analog inputs and/or select band gap reference inputs (ANCFG registers). b) Select the voltage reference source to match the expected range on analog inputs (AD1CON2). c) Select the analog conversion clock to match the desired data rate with the processor clock (AD1CON3). d) Select the appropriate sample/conversion sequence (AD1CON1 and AD1CON3). e) Select how the conversion results are presented in the buffer (AD1CON1). f) Select the interrupt rate (AD1CON2). g) Turn on the A/D module (AD1CON1). Configure the A/D interrupt (if required): a) Clear the AD1IF bit. b) Select the A/D interrupt priority. On all PIC24FJ256GB210 family devices, the 10-bit A/D Converter has 24 analog input pins, designated AN0 through AN23. In addition, there are two analog input pins for external voltage reference connections (VREF+ and VREF-). These voltage reference inputs may be shared with other analog input pins.  2010 Microchip Technology Inc. DS39975A-page 301 PIC24FJ256GB210 FAMILY FIGURE 22-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVSS VREF+ VR Select AVDD VR+ 16 VR- VREF- Comparator VINH AN0 VINL VRS/H VR+ DAC AN1 AN2 10-Bit SAR MUX A VINH Conversion Logic Data Formatting AD1BUF0: AD1BUF1F VINL AD1CON1 AN23 VBG MUX B AD1CON2 AD1CON3 AD1CHS ANCFG VINH AD1CSSL AD1CSSH VINL VBG/2 VBG/6 VCAP Sample Control Control Logic Conversion Control Input MUX Control Pin Config Control DS39975A-page 302  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ADON(1) — ADSIDL — — — FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R-0, HSC R-0, HSC SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: A/D Operating Mode bit(1) 1 = A/D Converter module is operating 0 = A/D Converter is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 FORM: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) bit 7-5 SSRC: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = CTMU event ends sampling and starts conversion 101 = Reserved 100 = Timer5 compare ends sampling and starts conversion 011 = Reserved 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion bit 4-3 Unimplemented: Read as ‘0’ bit 2 ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after the last conversion completes; the SAMP bit is auto-set. 0 = Sampling begins when the SAMP bit is set bit 1 SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done Note 1: The values of the ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out the conversion values from the buffer before disabling the module.  2010 Microchip Technology Inc. DS39975A-page 303 PIC24FJ256GB210 FAMILY REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 r-0 U-0 R/W-0 U-0 U-0 VCFG2 VCFG1 VCFG0 r — CSCNA — — bit 15 bit 8 R-0, HSC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: r = Reserved bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x = Bit is unknown VCFG: Voltage Reference Configuration bits VCFG VR+ VR- 000 AVDD AVSS 001 External VREF+ pin AVSS 010 AVDD External VREF- pin 011 External VREF+ pin External VREF- pin 1xx AVDD AVSS bit 12 Reserved: Maintain as ‘0’ bit 11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Scan Input Selections for the CH0+ S/H Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs bit 9-8 Unimplemented: Read as ‘0’ bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = A/D is currently filling buffer, 10-1F, user should access data in 00-0F 0 = A/D is currently filling buffer, 00-0F, user should access data in 10-1F bit 6-2 SMPI: Sample/Convert Sequences Per Interrupt Selection bits 11111 = Interrupts at the completion of conversion for each 32nd sample/convert sequence 11110 = Interrupts at the completion of conversion for each 31st sample/convert sequence . . . 00001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 00000 = Interrupts at the completion of conversion for each sample/convert sequence bit 1 BUFM: Buffer Mode Select bit 1 = Buffer is configured as two 16-word buffers (ADC1BUFn and ADC1BUFn) 0 = Buffer is configured as one 32-word buffer (ADC1BUFn) bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for the first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always uses the MUX A input multiplexer settings DS39975A-page 304  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 22-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 r-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC r r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock is derived from the system clock bit 14-13 Reserved: Maintain as ‘0’ bit 12-8 SAMC: Auto-Sample Time bits 11111 = 31 TAD . . . 00001 = 1 TAD 00000 = 0 TAD (not recommended) bit 7-0 ADCS: A/D Conversion Clock Select bits 11111111 = 256 * TCY ······ 00000001 = 2 * TCY 00000000 = TCY  2010 Microchip Technology Inc. x = Bit is unknown DS39975A-page 305 PIC24FJ256GB210 FAMILY REGISTER 22-4: R/W-0 AD1CHS: A/D INPUT SELECT REGISTER U-0 CH0NB — U-0 — R/W-0 CH0SB4 R/W-0 (1) CH0SB3 R/W-0 (1) R/W-0 (1) CH0SB2 CH0SB1 R/W-0 (1) CH0SB0(1) bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — CH0SA4(1) CH0SA3(1) CH0SA2(1) CH0SA1(1) CH0SA0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VR- bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB: Channel 0 Positive Input Select for MUX B(1) Other = Not available; do not use 11111 = No channel used; all inputs are floating; used for CTMU 11011 = Channel 0 positive input is the band gap divided-by-six reference (VBG/6) 11010 = Channel 0 positive input is the core voltage (VCAP) 11001 = Channel 0 positive input is the band gap reference (VBG) 11000 = Channel 0 positive input is the band gap divided-by-two reference (VBG/2) 10111 = Channel 0 positive input is AN23(2) . . . 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VR- bit 6-5 Unimplemented: Read as ‘0’ bit 4-0 CH0SA: Channel 0 Positive Input Select for MUX(1) Other = Not available; do not use 11111 = No Channel used; all inputs are floating; used for CTMU 11011 = Channel 0 positive input is the band gap divided-by-six reference (VBG/6) 11010 = Channel 0 positive input is the core voltage (VCAP) 11001 = Channel 0 positive input is the band gap reference (VBG) 11000 = Channel 0 positive input is the band gap divided-by-two reference (VBG/2) 10111 = Channel 0 positive input is AN23(2) . . . 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 Note 1: 2: Combinations not shown here (11100 to 11110) are unimplemented; do not use. Channel 0 positive inputs, AN16 through AN23, are not available on 64-pin devices (PIC24FJXXXGB206). DS39975A-page 306  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 22-5: ANCFG: A/D BAND GAP REFERENCE CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — VBG6EN VBG2EN VBGEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2 VBG6EN: A/D Input VBG/6 Enable bit 1 = Band gap voltage divided-by-six reference (VBG/6) is enabled 0 = Band gap divided-by-six reference (VBG/6) is disabled bit 1 VBG2EN: A/D Input VBG/2 Enable bit 1 = Band gap voltage divided-by-two reference (VBG/2) is enabled 0 = Band gap divided-by-two reference (VBG/2) is disabled bit 0 VBGEN: A/D Input VBG Enable bit 1 = Band gap voltage reference (VBG) is enabled 0 = Band gap reference (VBG) is disabled REGISTER 22-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown CSSL: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel is selected for input scan 0 = Analog channel is omitted from input scan  2010 Microchip Technology Inc. DS39975A-page 307 PIC24FJ256GB210 FAMILY REGISTER 22-7: AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH) U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CSSL27 CSSL26 CSSL25 CSSL24 bit 15 bit 8 R/W-0 CSSL23 R/W-0 (1) (1) CSSL22 R/W-0 CSSL21 (1) R/W-0 CSSL20 (1) R/W-0 CSSL19 (1) R/W-0 CSSL18 R/W-0 (1) (1) CSSL17 R/W-0 CSSL16(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11 CSSL27: A/D Input Band Gap Scan Selection bit 1 = Band gap divided-by-six reference (VBG/6) is selected for input scan 0 = Analog channel is omitted from input scan bit 10 CSSL26: A/D Input Band Gap Scan Selection bit 1 = Internal core voltage (VCAP) is selected for input scan 0 = Analog channel is omitted from input scan bit 9 CSSL25: A/D Input Half Band Gap Scan Selection bit 1 = Band gap reference (VBG) is selected for input scan 0 = Analog channel is omitted from input scan bit 8 CSSL24: A/D Input Band Gap Scan Selection bit 1 = Band gap divided-by-two reference (VBG/2) is selected for input scan 0 = Analog channel is omitted from input scan bit 7-0 CSSL: Analog Input Pin Scan Selection bits(1) 1 = Corresponding analog channel is selected for input scan 0 = Analog channel is omitted from input scan Note 1: Unimplemented in 64-pin devices, read as ‘0’. EQUATION 22-1: A/D CONVERSION CLOCK PERIOD(1) ADCS = TAD –1 TCY TAD = TCY • (ADCS = 1) Note 1: DS39975A-page 308 Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY FIGURE 22-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD Rs VA RIC  250 VT = 0.6V ANx CPIN 6-11 pF (Typical) VT = 0.6V Sampling Switch RSS  5 k(Typical) RSS CHOLD = DAC Capacitance = 4.4 pF (Typical) ILEAKAGE 500 nA VSS Legend: CPIN = Input Capacitance = Threshold Voltage VT ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC RSS = Sampling Switch Resistance CHOLD = Sample/Hold Capacitance (from DAC) Note: CPIN value depends on the device package and is not tested. The effect of CPIN IS negligible if Rs  5 k. FIGURE 22-3: A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1)  2010 Microchip Technology Inc. (VINH – VINL) VR+ 1024 1023*(VR+ – VR-) VR- + 1024 VR- + 512*(VR+ – VR-) 1024 VR- + Voltage Level VR+ – VR- 0 VR- 00 0000 0000 (0) DS39975A-page 309 PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 310  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 23.0 TRIPLE COMPARATOR MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual”. The triple comparator module provides three dual input comparators. The inputs to the comparator can be configured to use any one of five external analog inputs (CxINA, CxINB, CxINC, CxIND and VREF+) and a voltage reference input from one of the internal band gap references or the comparator voltage reference generator (VBG, VBG/2, VBG/6 and CVREF). FIGURE 23-1: The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. A simplified block diagram of the module in shown in Figure 23-1. Diagrams of the possible individual comparator configurations are shown in Figure 23-2. Each comparator has its own control register, CMxCON (Register 23-1), for enabling and configuring its operation. The output and event status of all three comparators is provided in the CMSTAT register (Register 23-2). TRIPLE COMPARATOR MODULE BLOCK DIAGRAM EVPOL CCH Input Select Logic CXINB 00 CXINC 01 CXIND 10 VBG 00 VBG/2 01 VBG/6 10 VREF+ 11 CPOL VINVIN+ Trigger/Interrupt Logic CEVT COE C1 COUT EVPOL 11 CPOL Trigger/Interrupt Logic CEVT COE VINVIN+ C2 CVREFM(1) COUT 0 CXINA 0 VREF+ 1 CVREF (1) CVREFP C1OUT Pin C2OUT Pin EVPOL + 1 CPOL VINVIN+ Trigger/Interrupt Logic CEVT COE C3 COUT C3OUT Pin CREF Note 1: Refer Register 24-1 for bit details.  2010 Microchip Technology Inc. DS39975A-page 311 PIC24FJ256GB210 FAMILY FIGURE 23-2: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 0 Comparator Off CEN = 0, CREF = x, CCH = xx COE VINVIN+ Cx Off (Read as ‘0’) Comparator CxINB > CxINA Compare CEN = 1, CCH = 00 Comparator CxINC > CxINA Compare CVREFM = xx VIN+ CXINA CEN = 1, CCH = 01 COE VIN- CXINB Cx CxOUT Pin VIN+ CXINA VBG/2 CXINA VIN+ CxOUT Pin COE CVREFM = 00 Cx CxOUT Pin COE VIN- VBG Cx VIN+ CXINA CxOUT Pin Comparator VBG > CxINA Compare CVREFM = 01 CEN = 1, CCH = 11 COE VIN- Cx VIN+ CXINA CEN = 1, CCH = 11 Comparator VBG > CxINA Compare CEN = 1, CCH = 11 COE Comparator VBG > CxINA Compare CVREFM = xx VIN- CXIND CVREFM = xx VIN- CXINC Comparator CxIND > CxINA Compare CEN = 1, CCH = 10 CxOUT Pin VIN+ CXINA CxOUT Pin COE VIN- VBG/6 Cx CVREFM = 10 Cx CxOUT Pin Comparator CxIND > CxINA Compare CEN = 1, CCH = 11 VREF+ CXINA DS39975A-page 312 CVREFM = 11 COE VINVIN+ Cx CxOUT Pin  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY FIGURE 23-3: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 0 Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare CEN = 1, CCH = 00 CEN = 1, CCH = 01 CXINB CVREF CVREFM = xx COE VIN- CXINC VIN+ Cx CVREF CxOUT Pin CXIND CVREF COE VBG Cx CVREF CxOUT Pin VBG/2 CVREF CxOUT Pin CVREFM = 00 COE VINVIN+ CEN = 1, CCH = 11 CVREFM = 01 COE VIN- VBG/6 Cx VIN+ Cx Cx CxOUT Pin Comparator VBG > CVREF Compare Comparator VBG > CVREF Compare CEN = 1, CCH = 11 VIN+ CEN = 1, CCH = 11 CVREFM = xx VINVIN+ COE VIN- Comparator VBG > CVREF Compare Comparator CxIND > CVREF Compare CEN = 1, CCH = 10 CVREFM = xx CxOUT Pin CVREF CVREFM = 10 COE VINVIN+ Cx CxOUT Pin Comparator CxIND > CVREF Compare CEN = 1, CCH = 11 COE VIN- VREF+ VIN+ CVREF FIGURE 23-4: CVREFM = 11 Cx CxOUT Pin INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 1 Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare CEN = 1, CCH = 00 CEN = 1, CCH = 01 CXINB VREF+ CVREFM = xx COE VINVIN+ CXINC Cx CxOUT Pin CXIND VREF+ COE VBG Cx CxOUT Pin VBG/2 VREF+ VIN+ VREF+ COE VBG/6 Cx  2010 Microchip Technology Inc. CxOUT Pin CVREFM = 00 COE VINVIN+ CEN = 1, CCH = 11 CVREFM = 01 VIN- Cx Cx CxOUT Pin Comparator VBG > CVREF Compare Comparator VBG > CVREF Compare CEN = 1, CCH = 11 VIN+ CEN = 1, CCH = 11 CVREFM = xx VINVIN+ COE VIN- Comparator VBG > CVREF Compare Comparator CxIND > CVREF Compare CEN = 1, CCH = 10 VREF+ CVREFM = xx CxOUT Pin VREF+ CVREFM = 10 COE VINVIN+ Cx CxOUT Pin DS39975A-page 313 PIC24FJ256GB210 FAMILY REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0, HS R-0, HSC CEN COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CEN: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 14 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 13 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 12-10 Unimplemented: Read as ‘0’ bit 9 CEVT: Comparator Event bit 1 = Comparator event that is defined by EVPOL has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred bit 8 COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VIN- bit 7-6 EVPOL: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt is generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt is generated on transition of comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled bit 5 Unimplemented: Read as ‘0’ DS39975A-page 314  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) bit 4 CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to the internal CVREF voltage 0 = Non-inverting input connects to the CXINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH: Comparator Channel Select bits 11 = Inverting input of the comparator connects to the internal selectable reference voltage specified by the CVREFM bits in the CVRCON register 10 = Inverting input of the comparator connects to the CXIND pin 01 = Inverting input of the comparator connects to the CXINC pin 00 = Inverting input of the comparator connects to the CXINB pin REGISTER 23-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC CMIDL — — — — C3EVT C2EVT C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC — — — — — C3OUT C2OUT C1OUT bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMIDL: Comparator Stop in Idle Mode bit 1 = Discontinue operation of all comparators when device enters Idle mode 0 = Continue operation of all enabled comparators in Idle mode bit 14-11 Unimplemented: Read as ‘0’ bit 10 C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON). bit 9 C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON). bit 8 C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON). bit 7-3 Unimplemented: Read as ‘0’ bit 2 C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON). bit 1 C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON). bit 0 C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON).  2010 Microchip Technology Inc. DS39975A-page 315 PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 316  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 24.0 Note: COMPARATOR VOLTAGE REFERENCE 24.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 19. “Comparator Module” (DS39710). The information in this data sheet supersedes the information in the FRM. Configuring the Comparator Voltage Reference The voltage reference module is controlled through the CVRCON register (Register 24-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR), with one range offering finer resolution. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON). The settling time of the comparator voltage reference must be considered when changing the CVREF output. FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 8R CVRSS = 0 CVR R CVREN R R 16-to-1 MUX R 16 Steps CVREF CVROE R R CVREF Pin R CVRR VREF- 8R CVRSS = 1 CVRSS = 0 AVSS  2010 Microchip Technology Inc. DS39975A-page 317 PIC24FJ256GB210 FAMILY REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CVREFP CVREFM1 CVREFM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CVREFP: Voltage Reference Select bit (valid only when CREF is ‘1’) 1 = VREF+ is used as a reference voltage to the comparators 0 = The CVR (4-bit DAC) within this module provides the the reference voltage to the comparators bit 9-8 CVREFM: Band Gap Reference Source Select bits (valid only when CCH = 11) 00 = Band gap voltage is provided as an input to the comparators 01 = Band gap voltage divided-by-two is provided as an input to the comparators 10 = Band gap voltage divided-by-six is provided as an input to the comparators 11 = VREF+ pin is provided as an input the comparators bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit is powered on 0 = CVREF circuit is powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on the CVREF pin 0 = CVREF voltage level is disconnected from the CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = VREF+ – VREF0 = Comparator reference source, CVRSRC = AVDD – AVSS bit 3-0 CVR: Comparator VREF Value Selection 0  CVR  15 bits When CVRR = 1: CVREF = (CVR/ 24)  (CVRSRC) When CVRR = 0: CVREF = 1/4  (CVRSRC) + (CVR/32)  (CVRSRC) DS39975A-page 318  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 25.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual”, Section 11. “Charge Time Measurement Unit (CTMU)” (DS39724). The information in this data sheet supersedes the information in the FRM. The Charge Time Measurement Unit (CTMU) is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. Its key features include: • • • • • • Four edge input trigger sources Polarity control for each edge source Control of edge sequence Control of response to edges Time measurement resolution of 1 nanosecond Accurate current source suitable for capacitive measurement Together with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses that are independent of the system clock. The CTMU module is ideal for interfacing with capacitive-based sensors. The CTMU is controlled through two registers: CTMUCON and CTMUICON. CTMUCON enables the module, and controls edge source selection, edge FIGURE 25-1: source polarity selection, and edge sequencing. The CTMUICON register controls the selection and trim of the current source. 25.1 Measuring Capacitance The CTMU module measures capacitance by generating an output pulse with a width equal to the time between edge events on two separate input channels. The pulse edge events to both input channels can be selected from four sources: two internal peripheral modules (OC1 and Timer1) and two external pins (CTEDG1 and CTEDG2). This pulse is used with the module’s precision current source to calculate capacitance according to the relationship: dV C = I  ------dT For capacitance measurements, the A/D Converter samples an external capacitor (CAPP) on one of its input channels after the CTMU output’s pulse. A precision resistor (RPR) provides current source calibration on a second A/D channel. After the pulse ends, the converter determines the voltage on the capacitor. The actual calculation of capacitance is performed in software by the application. Figure 25-1 shows the external connections used for capacitance measurements, and how the CTMU and A/D modules are related in this application. This example also shows the edge events coming from Timer1, but other configurations using external edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the “PIC24F Family Reference Manual”. TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 Current Source EDG2 Output Pulse A/D Converter ANx ANY CAPP  2010 Microchip Technology Inc. RPR DS39975A-page 319 PIC24FJ256GB210 FAMILY 25.2 Measuring Time When the module is configured for pulse generation delay by setting the TGEN (CTMUCON) bit, the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected. When CDELAY charges above the CVREF trip point, a pulse is output on CTPLS. The length of the pulse delay is determined by the value of CDELAY and the CVREF trip point. Time measurements on the pulse width can be similarly performed using the A/D module’s internal capacitor (CAD) and a precision resistor for current calibration. Figure 25-2 shows the external connections used for time measurements, and how the CTMU and A/D modules are related in this application. This example also shows both edge events coming from the external CTEDG pins, but other configurations using internal edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the “PIC24F Family Reference Manual”. 25.3 Figure 25-3 shows the external connections for pulse generation, as well as the relationship of the different analog modules required. While CTEDG1 is shown as the input pulse source, other options are available. A detailed discussion on pulse generation with the CTMU module is provided in the “PIC24F Family Reference Manual”. Pulse Generation and Delay The CTMU module can also generate an output pulse with edges that are not synchronous with the device’s system clock. More specifically, it can generate a pulse with a programmable delay from an edge event input to the module. FIGURE 25-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC24F Device CTMU CTEDG1 EDG1 CTEDG2 EDG2 Current Source Output Pulse A/D Converter ANx CAD RPR FIGURE 25-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTEDG1 EDG1 CTMU CTPLS Current Source Comparator C2INB CDELAY DS39975A-page 320 C2 CVREF  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN(1) EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HSC R/W-0, HSC EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation in Idle mode bit 12 TGEN: Time Generation Enable bit(1) 1 = Enables edge delay generation 0 = Disables edge delay generation bit 10 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 10 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 9 IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 8 CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative edge response bit 6-5 EDG2SEL: Edge 2 Source Select bits 11 = CTEDG1 pin 10 = CTEDG2 pin 01 = OC1 module 00 = Timer1 module bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 is programmed for a positive edge response 0 = Edge 1 is programmed for a negative edge response Note 1: x = Bit is unknown If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. DS39975A-page 321 PIC24FJ256GB210 FAMILY REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 3-2 EDG1SEL: Edge 1 Source Select bits 11 = CTEDG1 pin 10 = CTEDG2 pin 01 = OC1 module 00 = Timer1 module bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred Note 1: If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. REGISTER 25-2: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 ITRIM: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . . 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG 111111 = Minimum negative change from nominal current . . . 100010 100001 = Maximum negative change from nominal current bit 9-8 IRNG: Current Source Range Select bits 11 = 100  Base Current 10 = 10  Base Current 01 = Base current level (0.55 A nominal) 00 = Current source is disabled bit 7-0 Unimplemented: Read as ‘0’ DS39975A-page 322 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 26.0 Note: SPECIAL FEATURES 26.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the “PIC24F Family Reference Manual”. The information in this data sheet supersedes the information in the FRMs. In PIC24FJ256GB210 family devices, the configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the three words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific locations are shown in Table 26-1. These are packed representations of the actual device Configuration bits, whose actual locations are distributed among several locations in configuration space. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. • Section 9. “Watchdog Timer (WDT)” (DS39697) • Section 32. “High-Level Device Integration” (DS39719) • Section 33. “Programming and Diagnostics” (DS39716) Note: PIC24FJ256GB210 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • • • • • • The upper byte of all Flash Configuration Words in program memory should always be ‘0000 0000’. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing ‘0’s to these locations has no effect on device operation. Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location F80000h. A detailed explanation of the various bit functions is provided in Register 26-1 through Register 26-6. Note: Note that address F80000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh) which can only be accessed using table reads and table writes. TABLE 26-1: Configuration data is reloaded on all types of device Resets. When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. Flexible Configuration Watchdog Timer (WDT) Code Protection JTAG Boundary Scan Interface In-Circuit Serial Programming™ In-Circuit Emulation 26.1 CONSIDERATIONS FOR CONFIGURING PIC24FJ256GB210 FAMILY DEVICES Performing a page erase operation on the last page of program memory clears the Flash Configuration Words, enabling code protection as a result. Therefore, users should avoid performing page erase operations on the last page of program memory. FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ256GB210 FAMILY DEVICES Device Configuration Word Addresses 1 2 3 4 PIC24FJ128GB2XX 157FEh 157FCh 157FAh 157F8h PIC24FJ256GB2XX 2ABFEh 2ABFCh 2ABFAh 2ABF8h  2010 Microchip Technology Inc. DS39975A-page 323 PIC24FJ256GB210 FAMILY REGISTER 26-1: CW1: FLASH CONFIGURATION WORD 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1 reserved JTAGEN GCP GWRP DEBUG reserved ICS1 ICS0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 FWDTEN WINDIS ALTVREF(1) FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-16 Unimplemented: Read as ‘1’ bit 15 Reserved: The value is unknown; program as ‘0’ bit 14 JTAGEN: JTAG Port Enable bit 1 = JTAG port is enabled 0 = JTAG port is disabled bit 13 GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space bit 12 GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are not allowed bit 11 DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode bit 10 Reserved: Always maintain as ‘1’ bit 9-8 ICS: Emulator Pin Placement Select bits 11 = Emulator functions are shared with PGEC1/PGED1 10 = Emulator functions are shared with PGEC2/PGED2 01 = Emulator functions are shared with PGEC3/PGED3 00 = Reserved; do not use bit 7 FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled 0 = Watchdog Timer is disabled bit 6 WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer is enabled 0 = Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’ bit 5 ALTVREF: Alternate VREF Pin Selection bit(1) 1 = VREF is on a default pin (VREF+ on RA10 and VREF- on RA9) 0 = VREF is on an alternate pin (VREF+ on RB0 and VREF- on RB1) Note 1: x = Bit is unknown Unimplemented in 64-pin devices, maintain at ‘1’ (VREF+ on RB0 and VREF- on RB1). DS39975A-page 324  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 26-1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) bit 4 FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 bit 3-0 WDTPS: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 Note 1: Unimplemented in 64-pin devices, maintain at ‘1’ (VREF+ on RB0 and VREF- on RB1).  2010 Microchip Technology Inc. DS39975A-page 325 PIC24FJ256GB210 FAMILY REGISTER 26-2: CW2: FLASH CONFIGURATION WORD 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 IESO PLLDIV2 PLLDIV1 PLLDIV0 PLL96MHZ FNOSC2 FNOSC1 FNOSC0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 r-1 R/PO-1 R/PO-1 FCKSM1 FCKSM0 OSCIOFCN IOL1WAY reserved reserved POSCMD1 POSCMD0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) is enabled 0 = IESO mode (Two-Speed Start-up) is disabled bit 14-12 PLLDIV: 96 MHz PLL Prescaler Select bits 111 = Oscillator input is divided by 12 (48 MHz input) 110 = Oscillator input is divided by 8 (32 MHz input) 101 = Oscillator input is divided by 6 (24 MHz input) 100 = Oscillator input is divided by 5 (20 MHz input) 011 = Oscillator input is divided by 4 (16 MHz input) 010 = Oscillator input is divided by 3 (12 MHz input) 001 = Oscillator input is divided by 2 (8 MHz input) 000 = Oscillator input is used directly (4 MHz input) bit 11 PLL96MHZ: 96 MHz PLL Start-Up Enable bit 1 = 96 MHz PLL is enabled automatically on start-up 0 = 96 MHz PLL is software controlled (can be enabled by setting the PLLEN bit (CLKDIV)) bit 10-8 FNOSC: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 7-6 FCKSM: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 5 OSCIOFCN: OSCO Pin Configuration bit If POSCMD = 11 or 00: 1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RC15 functions as port I/O (RC15) If POSCMD = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RC15. DS39975A-page 326  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 26-2: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED) bit 4 IOL1WAY: IOLOCK One-Way Set Enable bit 1 = The IOLOCK bit (OSCCON) can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been completed bit 3-2 Reserved: Always maintain as ‘1’ bit 1-0 POSCMD: Primary Oscillator Configuration bits 11 = Primary Oscillator is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = EC Oscillator mode is selected REGISTER 26-3: CW3: FLASH CONFIGURATION WORD 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R/PO-1 R/PO-1 WPEND WPCFG R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 WPDIS ALTPMP(1) WUTSEL1 WUTSEL0 SOSCSEL1 SOSCSEL0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 WPFP7 WPFP6 WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0 bit 7 bit 0 Legend: PO = Program-Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 WPEND: Segment Write Protection End Page Select bit 1 = Protected code segment upper boundary is at the last page of program memory; the lower boundary is the code page specified by WPFP 0 = Protected code segment lower boundary is at the bottom of the program memory (000000h); upper boundary is the code page specified by WPFP bit 14 WPCFG: Configuration Word Code Page Write Protection Select bit 1 = Last page (at the top of program memory) and Flash Configuration Words are not write-protected(3) 0 = Last page and Flash Configuration Words are write-protected, provided WPDIS = ‘0’ bit 13 WPDIS: Segment Write Protection Disable bit 1 = Segmented code protection is disabled 0 = Segmented code protection is enabled; protected segment is defined by the WPEND, WPCFG and WPFPx Configuration bits bit 12 ALTPMP: Alternate EPMP Pin Mapping bit(1) 1 = EPMP pins are in default location mode 0 = EPMP pins are in alternate location mode Note 1: 2: 3: Unused in 64-pin devices, maintain at ‘1’. Ensure that the SCLKI pin is made a digital input while using this configuration, see Table 10-2. Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word’s page, the Configuration Word’s page is protected.  2010 Microchip Technology Inc. DS39975A-page 327 PIC24FJ256GB210 FAMILY REGISTER 26-3: CW3: FLASH CONFIGURATION WORD 3 (CONTINUED) bit 11-10 WUTSEL: Voltage Regulator Standby Mode Wake-up Time Select bits 11 = Default regulator start-up time is used 01 = Fast regulator start-up time is used x0 = Reserved; do not use bit 9-8 SOSCSEL: SOSC Selection Configuration bits 11 = Secondary oscillator is in Default (high drive strength) Oscillator mode 10 = Reserved; do not use 01 = Secondary oscillator is in Low-Power (low drive strength) Oscillator mode 00 = External clock (SCLKI) or Digital I/O mode(2) bit 7-0 WPFP: Write Protected Code Segment Boundary Page bits Designates the 512 instruction words page boundary of the protected code segment. If WPEND = 1: Specifies the lower page boundary of the code-protected segment; the last page being the last implemented page in the device. If WPEND = 0: Specifies the upper page boundary of the code-protected segment; Page 0 being the lower boundary. Note 1: 2: 3: Unused in 64-pin devices, maintain at ‘1’. Ensure that the SCLKI pin is made a digital input while using this configuration, see Table 10-2. Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word’s page, the Configuration Word’s page is protected. REGISTER 26-4: CW4: FLASH CONFIGURATION WORD 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 reserved reserved reserved reserved reserved reserved reserved reserved bit 15 bit 8 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 reserved reserved reserved reserved reserved reserved reserved reserved bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-16 Unimplemented: Read as ‘0’ bit 15-0 Reserved: Always maintain as ‘1’ DS39975A-page 328 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY REGISTER 26-5: DEVID: DEVICE ID REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R R R R R R R R FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit bit 23-16 Unimplemented: Read as ‘1’ bit 15-8 FAMID: Device Family Identifier bits 01000001 = PIC24FJ256GB210 family bit 7-0 DEV: Individual Device Identifier bits 00000000 = PIC24FJ128GB206 00000010 = PIC24FJ128GB210 00000100 = PIC24FJ256GB206 00000110 = PIC24FJ256GB210 REGISTER 26-6: DEVREV: DEVICE REVISION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R R R R — — — — REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit bit 23-4 Unimplemented: Read as ‘0’ bit 3-0 REV: Device Revision Identifier bits  2010 Microchip Technology Inc. U = Unimplemented bit DS39975A-page 329 PIC24FJ256GB210 FAMILY 26.2 On-Chip Voltage Regulator All PIC24FJ256GB210 family devices power their core digital logic at a nominal 1.8V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ256GB210 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR capacitor (such as ceramic) must be connected to the VCAP pin (Figure 26-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor (CEFC) is provided in Section 29.1 “DC Characteristics”. 26.2.1 VOLTAGE REGULATOR LOW-VOLTAGE DETECTION When the on-chip regulator is enabled, it provides a constant voltage of 1.8V nominal to the digital core logic. The regulator can provide this level from a VDD of about 2.1V, all the way up to the device’s VDDMAX. It does not have the capability to boost VDD levels. In order to prevent “brown-out” conditions when the voltage drops too low for the regulator, the Brown-out Reset occurs. Then the regulator output follows VDD with a typical voltage drop of 300 mV. To provide information about when the regulator voltage starts reducing, the on-chip regulator includes a simple Low-Voltage Detect circuit, which sets the Low-Voltage Detect Interrupt Flag, LVDIF (IFS4). This can be used to generate an interrupt to trigger an orderly shutdown. FIGURE 26-1: CONNECTIONS FOR THE ON-CHIP REGULATOR Regulator Enabled (ENVREG tied to VDD): 3.3V(1) PIC24FJXXXGB2XX VDD ENVREG VCAP CEFC (10 F typ) Note 1: VSS This is a typical operating voltage. Refer to Section 29.1 “DC Characteristics” for the full operating ranges of VDD. DS39975A-page 330 26.2.2 ON-CHIP REGULATOR AND POR When the voltage regulator is enabled, it takes approximately 10 s for it to generate output. During this time, designated as TVREG, code execution is disabled. TVREG is applied every time the device resumes operation after any power-down, including Sleep mode. TVREG is determined by the status of the VREGS bit (RCON) and the WUTSEL Configuration bits (CW3). Refer to Section 29.0 “Electrical Characteristics” for more information on TVREG. 26.2.3 ON-CHIP REGULATOR AND BOR When the on-chip regulator is enabled, PIC24FJ256GB210 family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain the output level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR (RCON) flag bit. The brown-out voltage specifications are provided in Section 7. “Reset” (DS39712) in the “PIC24F Family Reference Manual”. Note: 26.2.4 For more information, see Section 29.0 “Electrical Characteristics”. The information in this data sheet supersedes the information in the FRM. VOLTAGE REGULATOR STANDBY MODE When enabled, the on-chip regulator always consumes a small incremental amount of current over IDD/IPD, including when the device is in Sleep mode, even though the core digital logic does not require power. To provide additional savings in applications where power resources are critical, the regulator can be made to enter Standby mode on its own whenever the device goes into Sleep mode. This feature is controlled by the VREGS bit (RCON). Clearing the VREGS bit enables the Standby mode. When waking up from Standby mode, the regulator needs to wait for TVREG to expire before wake-up. The regulator wake-up time required for Standby mode is controlled by the WUTSEL (CW3) Configuration bits. The regulator wake-up time is lower when WUTSEL = 01, and higher when WUTSEL = 11. Refer to the TVREG specification in Table 29-10 for regulator wake-up time. When the regulator’s Standby mode is turned off (VREGS = 1), the device wakes up without waiting for TVREG. However, with the VREGS bit set, the power consumption while in Sleep mode will be approximately 40 A higher than what it would be if the regulator was allowed to enter Standby mode.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 26.3 Watchdog Timer (WDT) For PIC24FJ256GB210 family devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 31 kHz input, the prescaler yields a nominal WDT Time-out period (TWDT) of 1 ms in 5-bit mode or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPS Configuration bits (CW1), which allows the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler time-out periods, ranging from 1 ms to 131 seconds, can be achieved. The WDT Flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: 26.3.1 The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. WINDOWED OPERATION The Watchdog Timer has an optional Fixed-Window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction executed before that window causes a WDT Reset, similar to a WDT time-out. Windowed WDT mode is enabled by programming the WINDIS Configuration bit (CW1) to ‘0’. The WDT, prescaler and postscaler are reset: • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) • When the device exits Sleep or Idle mode to resume normal operation • By a CLRWDT instruction during normal execution 26.3.2 CONTROL REGISTER The WDT is enabled or disabled by the FWDTEN Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was FIGURE 26-2: executed. The corresponding SLEEP or IDLE (RCON) bit will need to be cleared in software after the device wakes up. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the SWDTEN Control bit (RCON). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. WDT BLOCK DIAGRAM SWDTEN FWDTEN LPRC Control FWPSA WDTPS Prescaler (5-bit/7-bit) LPRC Input 31 kHz Wake from Sleep 1 ms/4 ms WDT Counter Postscaler 1:1 to 1:32.768 WDT Overflow Reset All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode  2010 Microchip Technology Inc. DS39975A-page 331 PIC24FJ256GB210 FAMILY 26.4 Program Verification and Code Protection PIC24FJ256GB210 family devices provide two complimentary methods to protect application code from overwrites and erasures. These also help to protect the device from inadvertent configuration changes during run time. 26.4.1 GENERAL SEGMENT PROTECTION For all devices in the PIC24FJ256GB210 family, the on-chip program memory space is treated as a single block, known as the General Segment (GS). Code protection for this block is controlled by one Configuration bit, GCP. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. Write protection is controlled by the GWRP bit in the Configuration Word. When GWRP is programmed to ‘0’, internal write and erase operations to program memory are blocked. 26.4.2 CODE SEGMENT PROTECTION In addition to global General Segment protection, a separate subrange of the program memory space can be individually protected against writes and erases. This area can be used for many purposes where a separate block of write and erase-protected code is needed, such as bootloader applications. Unlike common boot block implementations, the specially protected segment in the PIC24FJ256GB210 family devices can be located by the user anywhere in the program space and configured in a wide range of sizes. The size and type of protection for the segmented code range are configured by the WPFPx, WPEND, WPCFG and WPDIS bits in Configuration Word 3. Code segment protection is enabled by programming the WPDIS bit (= 0). The WPFP bits specify the size of the segment to be protected by specifying the 512-word code page that is the start or end of the protected segment. The specified region is inclusive, therefore, this page will also be protected. The WPEND bit determines if the protected segment uses the top or bottom of the program space as a boundary. Programming WPEND (= 0) sets the bottom of program memory (000000h) as the lower boundary of the protected segment. Leaving WPEND unprogrammed (= 1) protects the specified page through the last page of implemented program memory, including the Configuration Word locations. A separate bit, WPCFG, is used to protect the last page of program space, including the Flash Configuration Words. Programming WPCFG (= 0) protects the last page in addition to the pages selected by the WPEND and WPFP bits setting. This is useful in circumstances where write protection is needed for both the code segment in the bottom of the memory and the Flash Configuration Words. The various options for segment code protection are shown in Table 26-2. Code segment protection provides an added level of protection to a designated area of program memory by disabling the NVM safety interlock whenever a write or erase address falls within a specified range. It does not override General Segment protection controlled by the GCP or GWRP bits. For example, if GCP and GWRP are enabled, enabling segmented code protection for the bottom half of program memory does not undo the General Segment protection for the top half. DS39975A-page 332  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 26.4.3 CONFIGURATION REGISTER PROTECTION The Configuration registers are protected against inadvertent or unwanted changes or reads in two ways. The primary protection method is the same as that of the RP registers – shadow registers contain a complimentary value which is constantly compared with the actual value. TABLE 26-2: To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity error and trigger a device Reset. The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the GCP bit is set, the source data for device configuration is also protected as a consequence. Even if General Segment protection is not enabled, the device configuration can be protected by using the appropriate code segment protection setting. CODE SEGMENT PROTECTION CONFIGURATION OPTIONS Segment Configuration Bits Write/Erase Protection of Code Segment WPDIS WPEND WPCFG 1 X x No additional protection is enabled; all program memory protection is configured by GCP and GWRP. 0 1 x Addresses from the first address of the code page are defined by WPFP through the end of implemented program memory (inclusive), write/erase protected, including Flash Configuration Words. 0 0 1 Address 000000h through the last address of the code page is defined by WPFP (inclusive), write/erase protected. 0 0 0 Address 000000h through the last address of code page is defined by WPFP (inclusive), write/erase protected and the last page, including Flash Configuration Words are write/erase protected. 26.5 JTAG Interface PIC24FJ256GB210 family devices implement a JTAG interface, which supports boundary scan device testing. 26.6 In-Circuit Serial Programming™ PIC24FJ256GB210 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGECx) and data (PGEDx), and three other lines for power (VDD), ground (VSS) and MCLR. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.  2010 Microchip Technology Inc. 26.7 In-Circuit Debugger When MPLAB® ICD 3 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pins. To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS and the PGECx/PGEDx pin pair designated by the ICS Configuration bits. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. DS39975A-page 333 PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 334  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 27.0 DEVELOPMENT SUPPORT The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers - MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 27.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2010 Microchip Technology Inc. DS39975A-page 335 PIC24FJ256GB210 FAMILY 27.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 27.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 27.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: 27.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 27.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS39975A-page 336  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 27.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 27.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ11) or with the new high-speed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.  2010 Microchip Technology Inc. 27.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easy-to-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 27.10 PICkit 3 In-Circuit Debugger/Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer’s PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. DS39975A-page 337 PIC24FJ256GB210 FAMILY 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured Windows® programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. 27.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39975A-page 338 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 28.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture and is not intended to be a comprehensive reference source. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: • • • • Word or byte-oriented operations Bit-oriented operations Literal operations Control operations • A literal value to be loaded into a W register or file register (specified by the value of ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand which is a register ‘Wb’ without any address modifier • The second source operand which is a literal value • The destination of the result (only if not the same as the first source operand), which is typically a register ‘Wd’ with or without an address modifier The control instructions may use some of the following operands: • A program memory address • The mode of the table read and table write instructions Table 28-1 shows the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 28-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand which is typically a register ‘Wb’ without any address modifier • The second source operand which is typically a register ‘Ws’ with or without an address modifier • The destination of the result which is typically a register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: • The file register specified by the value, ‘f’ • The destination, which could either be the file register, ‘f’, or the W0 register, which is denoted as ‘WREG’ Most bit-oriented instructions (including rotate/shift instructions) have two operands: The literal instructions that involve data movement may use some of the following operands: simple All instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register, ‘Wb’)  2010 Microchip Technology Inc. DS39975A-page 339 PIC24FJ256GB210 FAMILY TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0000h...1FFFh} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16383} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388607}; LSB must be ‘0’ None Field does not require an entry, may be blank PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing) Wn One of 16 working registers {W0..W15} Wnd One of 16 destination working registers {W0..W15} Wns One of 16 source working registers {W0..W15} WREG W0 (working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } DS39975A-page 340  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z AND f f = f .AND. WREG 1 1 N, Z AND f,WREG WREG = f .AND. WREG 1 1 N, Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None BRA LE,Expr Branch if Less than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None BRA LT,Expr Branch if Less than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW.C Ws,Wb Write C bit to Ws 1 1 None BSW.Z Ws,Wb Write Z bit to Ws 1 1 None BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3)  2010 Microchip Technology Inc. DS39975A-page 341 PIC24FJ256GB210 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax Description # of Words # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.Z Ws,Wb Bit Test Ws to Z 1 1 BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None Clear Watchdog Timer 1 1 WDTO, Sleep CLRWDT CLRWDT COM COM f f=f 1 1 N, Z COM f,WREG WREG = f 1 1 N, Z COM Ws,Wd Wd = Ws 1 1 N, Z CP f Compare f with WREG 1 1 C, DC, N, OV, Z CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, Z CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,Ws Compare Wb with Ws, with Borrow (Wb – Ws – C) 1 1 C, DC, N, OV, Z CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 None (2 or 3) CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 None (2 or 3) CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 None (2 or 3) CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if  1 1 None (2 or 3) DAW DAW.B Wn Wn = Decimal Adjust Wn 1 1 DEC DEC f f = f –1 1 1 C, DC, N, OV, Z DEC f,WREG WREG = f –1 1 1 C, DC, N, OV, Z CP C DEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, Z DEC2 f f=f–2 1 1 C, DC, N, OV, Z DEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, Z DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C DEC2 DS39975A-page 342  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic GOTO INC INC2 Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC2 Ws,Wd Wd = Ws + 2 1 1 IOR f f = f .IOR. WREG 1 1 N, Z IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z LNK LNK #lit14 Link Frame Pointer 1 1 None LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z MOV f,Wn Move f to Wn 1 1 None MOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 None MOV f Move f to f 1 1 N, Z MOV f,WREG Move f to WREG 1 1 N, Z MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1 MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N, Z MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None NEG f f=f+1 1 1 C, DC, N, OV, Z NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z NEG Ws,Wd IOR MOV MUL NEG NOP POP Wd = Ws + 1 1 1 C, DC, N, OV, Z NOP No Operation 1 1 None NOPR No Operation 1 1 None POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1 2 None Pop Shadow Registers 1 1 All POP.S PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None Push Shadow Registers 1 1 None PUSH.S  2010 Microchip Technology Inc. DS39975A-page 343 PIC24FJ256GB210 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 None RETFIE RETFIE Return from Interrupt 1 3 (2) None RETLW RETLW Return with Literal in Wn 1 3 (2) None RETURN RETURN Return from Subroutine 1 3 (2) None RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z C, N, Z RLNC RRC RRNC #lit10,Wn RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 RLNC f f = Rotate Left (No Carry) f 1 1 N, Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z N, Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 RRC f f = Rotate Right through Carry f 1 1 C, N, Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z RRNC f f = Rotate Right (No Carry) f 1 1 N, Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z SETM SETM f f = FFFFh 1 1 None SETM WREG WREG = FFFFh 1 1 None SETM Ws Ws = FFFFh 1 1 None SL f f = Left Shift f 1 1 C, N, OV, Z SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z SUB f f = f – WREG 1 1 C, DC, N, OV, Z SUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, Z SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, Z SL SUB SUBB SUBR SUBBR SWAP TBLRDH SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, Z SUBR f f = WREG – f 1 1 C, DC, N, OV, Z SUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, Z C, DC, N, OV, Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, Z C, DC, N, OV, Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None TBLRDH Ws,Wd Read Prog to Wd 1 2 None DS39975A-page 344  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDL TBLRDL Ws,Wd Read Prog to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws to Prog 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N ZE  2010 Microchip Technology Inc. DS39975A-page 345 PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 346  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ256GB210 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ256GB210 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +100°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS when VDD < 3.0V............................................ -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS when VDD > 3.0V..................................................... -0.3V to (+5.5V) Voltage on VBUS pin with respect to VSS, independent of VDD or VUSB ...................................................-0.3V to (+5.5V) Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (Note 1)................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 1)....................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 29-1). †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2010 Microchip Technology Inc. DS39975A-page 347 PIC24FJ256GB210 FAMILY 29.1 DC Characteristics FIGURE 29-1: PIC24FJ256GB210 FAMILY VOLTAGE FREQUENCY GRAPH (INDUSTRIAL) 3.6V 3.6V Voltage (VDD) PIC24FJXXXDA1 2.2V VBOR 2.2V VBOR 32 MHz Frequency Note: TABLE 29-1: VCAP (nominal On-Chip Regulator output voltage) = 1.8V. THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C PIC24FJ256GB210 family: Power Dissipation (with ENVREG = 1): Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W PDMAX (TJMAX – TA)/JA W I/O Pin Power Dissipation: PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation TABLE 29-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Note Package Thermal Resistance, 12x12x1 mm TQFP JA 69.4 — °C/W (Note 1) Package Thermal Resistance, 10x10x1 mm TQFP JA 76.6 — °C/W (Note 1) Package Thermal Resistance, 9x9x0.9 mm QFN JA 28.0 — °C/W (Note 1) Package Thermal Resistance, 10x10x1.1 mm BGA JA 40.2 — °C/W (Note 1) Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS39975A-page 348  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 29-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min Typ Max Units Conditions VBOR — 3.6 V Regulator enabled Regulator enabled Operating Voltage DC10 Supply Voltage VDD VCAP(2) — 1.8V — V DC12 VDR RAM Data Retention Voltage(1) 1.5 — — V DC16 VPOR VDD Start Voltage to Ensure Internal Power-on Reset Signal Vss — — V DC17 SVDD VDD Rise Rate to Ensure Internal Power-on Reset Signal 0.05 — — V/ms VBOR Brown-out Reset Voltage on VDD Transition, High-to-Low 2.0 2.10 2.2 V VLVD LVD Trip Voltage — VBOR + 0.10 — V Note 1: 2: 0-3.3V in 66 ms 0-2.5V in 50 ms Regulator enabled This is the limit to which the RAM data can be retained, while the on-chip regulator output voltage starts following the VDD. This is the on-chip regulator output voltage specification.  2010 Microchip Technology Inc. DS39975A-page 349 PIC24FJ256GB210 FAMILY TABLE 29-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) DC20D 0.8 1.3 mA -40°C DC20E 0.8 1.3 mA +25°C DC20F 0.8 1.3 mA +85°C DC23D 3.0 4.8 mA -40°C DC23E 3.0 4.8 mA +25°C DC23F 3.0 4.8 mA +85°C DC24D 12.0 18 mA -40°C DC24E 12.0 18 mA +25°C DC24F 12.0 18 mA +85°C DC31D 55 95 A -40°C DC31E 55 95 A +25°C DC31F 135 225 A +85°C Note 1: 2: 3: 3.3V(3) 1 MIPS 3.3V(3) 4 MIPS 3.3V(3) 16 MIPS 3.3V(3) LPRC (31 kHz) Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator enabled (ENVREG tied to VDD). Brown-out Reset (BOR) is enabled. DS39975A-page 350  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 29-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Idle Current (IIDLE)(2) DC40D 170 320 A -40°C DC40E 170 320 A +25°C DC40F 220 380 A +85°C DC43D 0.6 1.2 mA -40°C DC43E 0.6 1.2 mA +25°C DC43F 0.7 1.2 mA +85°C DC47D 2.3 4.8 mA -40°C DC47E 2.3 4.8 mA +25°C DC47F 2.4 4.8 mA +85°C DC50D 0.8 1.8 mA -40°C DC50E 0.8 1.8 mA +25°C DC50F 1.0 1.8 mA +85°C DC51D 40.0 85 A -40°C DC51E 40.0 85 A +25°C DC51F 120.0 210 A +85°C Note 1: 2: 3: 3.3V(3) 1 MIPS 3.3V(3) 4 MIPS 3.3V(3) 16 MIPS FRC (4 MIPS) 3.3V(3) LPRC (31 kHz) (3) 3.3V Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IIDLE current is measured with the core off; OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator enabled (ENVREG tied to VDD). Brown-out Reset (BOR) is enabled.  2010 Microchip Technology Inc. DS39975A-page 351 PIC24FJ256GB210 FAMILY TABLE 29-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD)(2) DC60D 20.0 45 A -40°C DC60E 20.0 45 A +25°C DC60H 55.0 105 A +60°C DC60F 95.0 185 A +85°C DC61D 1.0 3.5 A -40°C DC61E 1.0 3.5 A +25°C DC61H 1.0 3.5 A +60°C DC61F 2.5 6.5 A +85°C DC62D 1.5 6 A -40°C DC62E 1.5 6 A +25°C DC62H 1.5 6 A +60°C DC62F 8.0 18 A +85°C DC63D 4.0 18 A -40°C DC63E 4.0 18 A +25°C DC63H 6.5 18 A +60°C DC63F 12.0 25 A +85°C Note 1: 2: 3: 4: 3.3V(3) Base power-down current(4) 3.3V(3) 31 kHz LPRC oscillator with RTCC, WDT or Timer1: ILPRC(4) 3.3V(3) Low drive strength, 32 kHz crystal with RTCC or Timer1: ISOSC; SOSCSEL = 01(4) 3.3V(3) 32 kHz crystal with RTCC or Timer1: ISOSC; SOSCSEL = 11(4) Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with the device in Sleep mode (all peripherals and clocks are shut down). All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off, PMSLP bit is clear and the Peripheral Module Disable (PMD) bits for all unused peripherals are set. On-chip voltage regulator enabled (ENVREG tied to VDD). Brown-out Reset (BOR) is enabled. The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. DS39975A-page 352  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 29-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. VIL Characteristic Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min Typ(1) Max Units Input Low Voltage(3) DI10 I/O Pins with ST Buffer VSS — 0.2 VDD V DI11 I/O Pins with TTL Buffer VSS — 0.15 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.2 VDD V DI17 OSCI (HS mode) VSS — 0.2 VDD V DI18 I/O Pins with I2C™ Buffer: VSS — 0.3 VDD V I/O Pins with SMBus Buffer: VSS — 0.8 V I/O Pins with ST Buffer: with Analog Functions Digital Only 0.8 VDD 0.8 VDD — — VDD 5.5 V V I/O Pins with TTL Buffer: with Analog Functions Digital Only 0.25 VDD + 0.8 0.25 VDD + 0.8 — — VDD 5.5 V V DI19 VIH DI20 DI21 SMBus enabled Input High Voltage(3) DI25 MCLR 0.8 VDD — VDD V DI26 OSCI (XT mode) 0.7 VDD — VDD V DI27 OSCI (HS mode) 0.7 VDD — VDD V DI28 I/O Pins with I2C™ Buffer: with Analog Functions Digital Only 0.7 VDD 0.7 VDD — — VDD 5.5 V V VDD 5.5 V V DI29 Conditions 2.5V  VPIN  VDD I/O Pins with SMBus Buffer: with Analog Functions Digital Only 2.1 2.1 DI30 ICNPU CNxx Pull-up Current 15 70 150 A VDD = 3.3V, VPIN = VSS DI30A ICNPD CNxx Pull-down Current 150 350 550 A VDD = 3.3V, VPIN = VDD IIL Input Leakage Current(2) DI50 I/O Ports — — +1 A VSS  VPIN  VDD, pin at high-impedance DI51 Analog Input Pins — — +1 A VSS  VPIN  VDD, pin at high-impedance DI55 MCLR — — +1 A VSS VPIN VDD DI56 OSCI/CLKI — — +1 A VSS VPIN VDD, EC, XT and HS modes Note 1: 2: 3: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Negative current is defined as current sourced by the pin. Refer to Table 1-3 for I/O pins buffer types.  2010 Microchip Technology Inc. DS39975A-page 353 PIC24FJ256GB210 FAMILY TABLE 29-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. VOL DO10 OSCO/CLKO VOH DO20 Typ(1) Max Units Conditions — — 0.4 V IOL = 6.6mA, VDD = 3.6V — — 0.4 V IOL = 5.0 mA, VDD = 2.2V — — 0.4 V IOL = 6.6 mA, VDD = 3.6V — — 0.4 V IOL = 5.0 mA, VDD = 2.2V 3.0 — — V IOH = -3.0 mA, VDD = 3.6V Output High Voltage I/O Ports DO26 Min Output Low Voltage I/O Ports DO16 Note 1: Characteristic Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial OSCO/CLKO 2.4 — — V IOH = -6.0 mA, VDD = 3.6V 1.65 — — V IOH = -1.0 mA, VDD = 2.2V 1.4 — — V IOH = -3.0 mA, VDD = 2.2V 2.4 — — V IOH = -6.0 mA, VDD = 3.6V 1.4 — — V IOH = -1.0 mA, VDD = 2.2V Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 29-9: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min Typ(1) Max Units 10000 — — E/W — 3.6 V VMIN = Minimum operating voltage VMIN = Minimum operating voltage Conditions Program Flash Memory D130 EP Cell Endurance D131 VPR VDD for Read VMIN D132B VDD for Self-Timed Write VMIN — 3.6 V D133A TIW Self-Timed Word Write Cycle Time — 20 — s Self-Timed Row Write Cycle Time — 1.5 — ms D133B TIE Self-Timed Page Erase Time 20 — 40 ms D134 TRETD Characteristic Retention 20 — — Year D135 IDDP Supply Current during Programming — 16 — mA Note 1: -40C to +85C If no other specifications are violated Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS39975A-page 354  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 29-10: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Symbol No. Characteristics Typ Max Units Comments VRGOUT Regulator Output Voltage — 1.8 — V VBG Internal Band Gap Reference — 1.2 — V CEFC External Filter Capacitor Value 4.7 10 — F Series resistance < 3 Ohm recommended; < 5 Ohm required. — 10 — s VREGS = 1, VREGS = 0 with WUTSEL = 01 or any POR or BOR — 190 — s Sleep wake-up with VREGS = 0 and WUTSEL = 11 — 1 — ms TVREG Band Gap Reference Start-up Time TBG 29.2 Min AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ256GB210 family AC characteristics and timing parameters. TABLE 29-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Operating voltage VDD range as described in Section 29.1 “DC Characteristics”. AC CHARACTERISTICS FIGURE 29-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSCO Load Condition 2 – for OSCO VDD/2 RL CL Pin VSS CL Pin VSS  2010 Microchip Technology Inc. RL = 464 CL = 50 pF for all pins except OSCO 15 pF for OSCO output DS39975A-page 355 PIC24FJ256GB210 FAMILY TABLE 29-12: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions DO50 COSCO OSCO/CLKO Pin — — 15 pF In XT and HS modes when external clock is used to drive OSCI DO56 CIO All I/O Pins and OSCO — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 29-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS40 DS39975A-page 356 OS41  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY TABLE 29-13: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Characteristic Min Typ(1) Max Units External CLKI Frequency (External clocks allowed only in EC mode) DC 4 — — 32 48 MHz MHz EC ECPLL Oscillator Frequency 3.5 4 10 10 31 — — — — — 10 8 32 32 33 MHz MHz MHz MHz kHz XT XTPLL HS HSPLL SOSC OS20 TOSC TOSC = 1/FOSC — — — — OS25 TCY Instruction Cycle Time(2) 62.5 — DC ns OS30 TosL, TosH External Clock in (OSCI) High or Low Time 0.45 x TOSC — — ns EC OS31 TosR, TosF External Clock in (OSCI) Rise or Fall Time — — 20 ns EC OS40 TckR CLKO Rise Time(3) — 6 10 ns OS41 TckF CLKO Fall Time(3) — 6 10 ns OS10 FOSC Note 1: 2: 3: Conditions See parameter OS10 for FOSC value Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). TABLE 29-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.2V TO 3.6V) AC CHARACTERISTICS Param Symbol No. OS50 FPLLI Characteristic(1) PLL Input Frequency Range(2) OS51 FSYS PLL Output Frequency Range OS52 TLOCK PLL Start-up Time (Lock Time) OS53 DCLK CLKO Stability (Jitter) Note 1: 2: Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min Typ(2) Max Units 4 — 48 MHz ECPLL mode 4 — 32 MHz HSPLL mode XTPLL mode 4 — 8 MHz 95.76 — 96.24 MHz — — 200 s -0.25 — 0.25 % Conditions These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc. DS39975A-page 357 PIC24FJ256GB210 FAMILY TABLE 29-15: INTERNAL RC ACCURACY Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA +85°C for Industrial AC CHARACTERISTICS Param No. Characteristic Min Typ Max Units Conditions F20 FRC Accuracy @ 8 MHz(1,2) -1 ±0.15 1 % -40°C  TA +85°C 2.2V VDD 3.6V F21 LPRC @ 31 kHz -20 — 20 % -40°C  TA +85°C VCAP (on-chip regulator output voltage) = 1.8V Note 1: 2: Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift. To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB) must be kept to a minimum. TABLE 29-16: RC OSCILLATOR START-UP TIME Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial AC CHARACTERISTICS Param No. Characteristic Min Typ Max Units TFRC — 15 — s TLPRC — 50 — s Conditions TABLE 29-17: RESET AND BROWN-OUT RESET REQUIREMENTS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial AC CHARACTERISTICS Param Symbol No. Characteristic Min Typ Max Units — — s SY10 TMCL MCLR Pulse width (Low) 2 SY12 TPOR Power-on Reset Delay — 2 — s SY13 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset — — 100 ns SY25 TBOR Brown-out Reset Pulse Width 1 — — s TRST Internal State Reset Time — 50 — s DS39975A-page 358 Conditions VDD VBOR  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY FIGURE 29-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 29-2 for load conditions. TABLE 29-18: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units — 10 25 ns DO31 TIOR DO32 TIOF Port Output Fall Time — 10 25 ns DI35 TINP INTx Pin High or Low Time (input) 20 — — ns DI40 TRBP CNx High or Low Time (input) 2 — — TCY Note 1: Port Output Rise Time Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Conditions Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.  2010 Microchip Technology Inc. DS39975A-page 359 PIC24FJ256GB210 FAMILY TABLE 29-19: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 2.2 — Lesser of VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V AD05 VREFH Reference Voltage High AVSS + 1.7 AVDD V AD06 VREFL Reference Voltage Low AD07 VREF Absolute Reference Voltage Reference Inputs — AVSS — AVDD – 1.7 V AVSS – 0.3 — AVDD + 0.3 V Analog Input AD10 VINH-VINL Full-Scale Input Span AD11 VIN AD12 VINL AD13 AD17 RIN VREFL — VREFH V Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V Absolute VINL Input Voltage AVSS – 0.3 AVDD/2 V (Note 2) Leakage Current — ±1.0 ±610 nA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5 k Recommended Impedance of Analog Voltage Source — — 2.5K  10-bit ADC Accuracy AD20B Nr Resolution — 10 — bits AD21B INL Integral Nonlinearity — ±1 > > (  !"# $% &" ' ()"&'"!&) & #*&& & #  +'% !& !  &,!- '  ' !!#.#&"# '#%! &"!!#%! &"!!!& $ #/'' !#  ' !#&  .0/ 1+2 1!' !  & $& " !**&"&&  ! .32  %   ' !("!"*&"&&  (%%'& " ! !    * + 1  2010 Microchip Technology Inc. DS39975A-page 369 PIC24FJ256GB210 FAMILY           ##   !" #$  % & ' ( 3& '!&" & 4 #*!(  ! ! &  4 %&& #& && 255***' '5 4 DS39975A-page 370  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS39975A-page 371 PIC24FJ256GB210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39975A-page 372  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS39975A-page 373 PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 374  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY APPENDIX A: REVISION HISTORY Revision A (May 2010) Original data sheet for the PIC24FJ256GB210 family of devices.  2010 Microchip Technology Inc. DS39975A-page 375 PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 376  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY INDEX A Output Compare (Double-Buffered, 16-Bit PWM Mode) ........................................... 198 PIC24F CPU Core ...................................................... 38 PIC24FJ256GB210 Family (General)......................... 19 PSV Operation (Higher Word) .................................... 76 PSV Operation (Lower Word)..................................... 76 Reset System ............................................................. 85 RTCC........................................................................ 281 Shared I/O Port Structure ......................................... 151 SPI Master, Frame Master Connection .................... 214 SPI Master, Frame Slave Connection ...................... 214 SPI Master/Slave Connection (Enhanced Buffer Modes) ................................................... 213 SPI Master/Slave Connection (Standard Mode)....... 213 SPI Slave, Frame Master Connection ...................... 214 SPI Slave, Frame Slave Connection ........................ 214 SPIx Module (Enhanced Mode)................................ 207 SPIx Module (Standard Mode) ................................. 206 System Clock............................................................ 137 Triple Comparator Module........................................ 311 UART (Simplified)..................................................... 225 USB OTG Device Mode Power Modes .................... 235 USB OTG Dual Power Example............................... 236 USB OTG External Pull-up for Full-Speed Device Mode..................................................... 235 USB OTG Interface Example ................................... 237 USB OTG Interrupt Funnel ....................................... 243 USB OTG Module..................................................... 234 USB OTG Self-Power Only ...................................... 235 Watchdog Timer (WDT)............................................ 331 A/D Conversion 10-Bit High-Speed A/D Converter............................. 301 A/D Converter ................................................................... 301 Analog Input Model ................................................... 309 Transfer Function...................................................... 309 AC Characteristics A/D Specifications..................................................... 360 ADC Conversion Timing Requirements .................... 361 Capacitive Loading on Output Pin ............................ 356 CLKO and I/O Timing................................................ 359 External Clock Timing ............................................... 357 Internal RC Accuracy ................................................ 358 Load Conditions and Requirements for Specifications.................................................... 355 PLL Clock Timing Specifications............................... 357 RC Oscillator Start-up Time ...................................... 358 Reset and Brown-out Reset Requirements .............. 358 Timing Parameters.................................................... 355 Alternate Interrupt Vector Table (AIVT) .............................. 91 Assembler MPASM Assembler................................................... 336 B Block Diagram CRC .......................................................................... 293 Block Diagrams 10-Bit High-Speed A/D Converter............................. 302 16-Bit Asynchronous Timer3 and Timer5 ................. 187 16-Bit Synchronous Timer2 and Timer4 ................... 187 16-Bit Timer1 Module................................................ 183 32-Bit Timer2/3 and Timer4/5 ................................... 186 96 MHz PLL .............................................................. 145 Accessing Program Space Using Table Operations .......................................................... 74 Addressing for Table Registers................................... 79 BDT Mapping for Endpoint Buffering Modes ............ 239 CALL Stack Frame...................................................... 72 Comparator Voltage Reference ................................ 317 CPU Programmer’s Model .......................................... 39 CRC Shift Engine Detail............................................ 293 CTMU Connections and Internal Configuration for Capacitance Measurement.......................... 319 CTMU Typical Connections and Internal Configuration for Pulse Delay Generation ........ 320 CTMU Typical Connections and Internal Configuration for Time Measurement ............... 320 Data Access From Program Space Address Generation .......................................................... 73 EDS Address Generation for Read Operations .......... 69 EDS Address Generation for Write Operations .......... 70 Extended Data Space ................................................. 68 I2C Module ................................................................ 218 Individual Comparator Configurations, CREF = 0 .......................................................... 312 Individual Comparator Configurations, CREF = 1 and CVREFP = 0 ............................. 313 Individual Comparator Configurations, CREF = 1 and CVREFP = 1 ............................. 313 Input Capture ............................................................ 191 On-Chip Regulator Connections ............................... 330 Output Compare (16-Bit Mode)................................. 196  2010 Microchip Technology Inc. C C Compilers MPLAB C18.............................................................. 336 Charge Time Measurement Unit (CTMU)......................... 319 Key Features ............................................................ 319 Charge Time Measurement Unit. See CTMU. Code Examples Basic Sequence for Clock Switching in Assembly.... 144 Configuring UART1 I/O Input/Output Functions (PPS) ............................................... 162 EDS Read Code From Program Memory in Assembly ........................................................ 77 EDS Read Code in Assembly..................................... 69 EDS Write Code in Assembly..................................... 70 Erasing a Program Memory Block (Assembly) ........... 82 I/O Port Write/Read in ‘C’ ......................................... 157 I/O Port Write/Read in Assembly.............................. 157 Initiating a Programming Sequence ........................... 83 PWRSAV Instruction Syntax .................................... 149 Setting the RTCWREN Bit ........................................ 282 Single-Word Flash Programming ............................... 84 Single-Word Flash Programming (‘C’ Language)....... 84 Code Protection ................................................................ 332 Code Segment Protection ........................................ 332 Configuration Options....................................... 333 Configuration Register Protection............................. 333 Comparator Voltage Reference ........................................ 317 Configuring ............................................................... 317 Configuration Bits ............................................................. 323 Core Features..................................................................... 15 DS39975A-page 377 PIC24FJ256GB210 FAMILY CPU Arithmetic Logic Unit (ALU)......................................... 41 Control Registers ........................................................ 40 Core Registers ............................................................ 38 Programmer’s Model................................................... 37 CRC 32-Bit Programmable Cyclic Redundancy Check ..... 293 Polynomials............................................................... 294 Setup Examples for 16 and 32-Bit Polynomials ........ 294 User Interface ........................................................... 294 CTMU Measuring Capacitance ............................................ 319 Measuring Time ........................................................ 320 Pulse Generation and Delay ..................................... 320 Customer Change Notification Service ............................. 382 Customer Notification Service........................................... 382 Customer Support ............................................................. 382 D Data Memory Address Space............................................................ 45 Extended Data Space (EDS) ...................................... 68 Memory Map ............................................................... 46 Near Data Space ........................................................ 47 SFR Space.................................................................. 47 Software Stack ............................................................ 72 Space Organization, Alignment .................................. 47 DC Characteristics I/O Pin Input Specifications ....................................... 353 I/O Pin Output Specifications .................................... 354 Idle Current ............................................................... 351 Operating Current ..................................................... 350 Program Memory ...................................................... 354 Temperature and Voltage Specifications .................. 349 Thermal Conditions ................................................... 348 Voltage Regulator Specifications .............................. 355 Development Support ....................................................... 335 Device Features 100/121--Pin ............................................................... 18 64-Pin.......................................................................... 17 Doze Mode........................................................................ 150 E Electrical Characteristics Absolute Maximum Ratings ...................................... 347 V/F Graph ................................................................. 348 Enhanced Parallel Master Port. See EPMP...................... 269 ENVREG Pin..................................................................... 330 EPMP ................................................................................ 269 ALTPMP Setting ....................................................... 269 Key Features............................................................. 269 Master Port Pins ....................................................... 270 Equations 16-Bit, 32-Bit CRC Polynomials ................................ 294 A/D Conversion Clock Period ................................... 308 Baud Rate Reload Calculation .................................. 219 Calculating the PWM Period ..................................... 198 Calculation for Maximum PWM Resolution............... 199 Estimating USB Transceiver Current Consumption..................................................... 238 Relationship Between Device and SPI Clock Speed...................................................... 215 RTCC Calibration ...................................................... 290 UART Baud Rate with BRGH = 0 ............................. 226 UART Baud Rate with BRGH = 1 ............................. 226 DS39975A-page 378 Errata .................................................................................. 14 Extended Data Space (EDS) ............................................ 269 F Flash Configuration Words ......................................... 44, 323 Flash Program Memory ...................................................... 79 Enhanced ICSP Operation ......................................... 80 JTAG Operation.......................................................... 80 Programming Algorithm .............................................. 82 RTSP Operation ......................................................... 80 Single-Word Programming ......................................... 84 Table Instructions ....................................................... 79 I I/O Ports Analog Port Pins Configuration................................. 152 Analog/Digital Function of an I/O Pin........................ 152 Input Change Notification ......................................... 157 Open-Drain Configuration......................................... 152 Parallel (PIO) ............................................................ 151 Peripheral Pin Select ................................................ 158 Pull-ups and Pull-Downs........................................... 157 Selectable Input Sources.......................................... 159 Write/Read Timing .................................................... 152 I2C Clock Rates .............................................................. 219 Reserved Addresses ................................................ 219 Setting Baud Rate as Bus Master............................. 219 Slave Address Masking ............................................ 219 Idle Mode .......................................................................... 150 Input Capture 32-Bit Mode (Cascaded)........................................... 192 Operations ................................................................ 192 Synchronous and Trigger Modes.............................. 191 Input Capture with Dedicated Timers ............................... 191 Input Voltage Levels for Port or Pin Tolerated Description Input....................................... 152 Instruction Set Opcode Symbols ...................................................... 340 Overview................................................................... 341 Summary .................................................................. 339 Instruction-Based Power-Saving Modes................... 149, 150 Interfacing Program and Data Spaces................................ 72 Inter-Integrated Circuit. See I2C. ...................................... 217 Internet Address ............................................................... 382 Interrupt Vector Table (IVT) ................................................ 91 Interrupts Control and Status Registers...................................... 94 Implemented Vectors.................................................. 93 Reset Sequence ......................................................... 91 Setup and Service Procedures ................................. 135 Trap Vector Details ..................................................... 92 Vector Table ............................................................... 92 J JTAG Interface.................................................................. 333 K Key Features .................................................................... 323  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY M Memory Organization.......................................................... 43 Microchip Internet Web Site .............................................. 382 MPLAB ASM30 Assembler, Linker, Librarian ................... 336 MPLAB Integrated Development Environment Software.................................................................... 335 MPLAB PM3 Device Programmer .................................... 338 MPLAB REAL ICE In-Circuit Emulator System................. 337 MPLINK Object Linker/MPLIB Object Librarian ................ 336 N Near Data Space ................................................................ 47 O Oscillator Configuration 96 MHz PLL .............................................................. 144 Clock Selection ......................................................... 138 Clock Switching......................................................... 143 Sequence.......................................................... 143 CPU Clocking Scheme ............................................. 138 Initial Configuration on POR ..................................... 138 USB Operations ........................................................ 146 Output Compare 32-Bit Mode (Cascaded) ........................................... 195 Synchronous and Trigger Modes.............................. 195 Output Compare with Dedicated Timers ........................... 195 P Packaging ......................................................................... 363 Details ....................................................................... 364 Marking ..................................................................... 363 Peripheral Enable Bits ...................................................... 150 Peripheral Module Disable Bits ......................................... 150 Peripheral Pin Select (PPS) .............................................. 158 Available Peripherals and Pins ................................. 158 Configuration Control ................................................ 161 Considerations for Use ............................................. 162 Input Mapping ........................................................... 158 Mapping Exceptions.................................................. 161 Output Mapping ........................................................ 160 Peripheral Priority ..................................................... 158 Registers................................................................... 163 Pin Descriptions 100-Pin Devices............................................................ 8 121-Pin (BGA) Devices............................................... 11 64-Pin Devices.............................................................. 6 Pin Diagrams 100-Pin TQFP ............................................................... 7 121-Pin BGA ............................................................... 10 64-Pin TQFP/QFN ........................................................ 5 Pinout Descriptions ............................................................. 20 POR and On-Chip Voltage Regulator................................ 330 Power-Saving Features .................................................... 149 Clock Frequency and Clock Switching...................... 149 Instruction-Based Modes .......................................... 149 Power-up Requirements ................................................... 330 Product Identification System ........................................... 384 Program Memory Access Using Table Instructions................................. 74 Address Construction.................................................. 72 Address Space............................................................ 43 Flash Configuration Words ......................................... 44 Memory Maps ............................................................. 43 Organization................................................................ 44 Reading From Program Memory Using EDS.............. 75  2010 Microchip Technology Inc. Program Verification ......................................................... 332 Pulse-Width Modulation (PWM) Mode.............................. 197 Pulse-Width Modulation. See PWM. PWM Duty Cycle and Period.............................................. 198 R Reader Response............................................................. 383 Reference Clock Output ................................................... 147 Register Maps A/D Converter............................................................. 59 ANCFG ....................................................................... 62 ANSEL........................................................................ 62 Comparators............................................................... 64 CPU Core ................................................................... 48 CRC............................................................................ 64 CTMU ......................................................................... 60 I2C™........................................................................... 54 ICN ............................................................................. 49 Input Capture.............................................................. 52 Interrupt Controller...................................................... 50 NVM............................................................................ 67 Output Compare ......................................................... 53 Pad Configuration....................................................... 58 Peripheral Pin Select .................................................. 65 PMD............................................................................ 67 PORTA ....................................................................... 56 PORTB ....................................................................... 56 PORTC ....................................................................... 57 PORTD ....................................................................... 57 PORTE ....................................................................... 57 PORTF ....................................................................... 58 PORTG....................................................................... 58 RTCC.......................................................................... 63 SPI.............................................................................. 56 System........................................................................ 67 Timers......................................................................... 51 UART.......................................................................... 55 USB OTG ................................................................... 61 Registers AD1CHS (A/D Input Select)...................................... 306 AD1CON1 (A/D Control 1)........................................ 303 AD1CON2 (A/D Control 2)........................................ 304 AD1CON3 (A/D Control 3)........................................ 305 AD1CSSH (A/D Input Scan Select, High)................. 308 AD1CSSL (A/D Input Scan Select, Low) .................. 307 ALCFGRPT (Alarm Configuration) ........................... 285 ALMINSEC (Alarm Minutes and Seconds Value)..... 289 ALMTHDY (Alarm Month and Day Value) ................ 288 ALWDHR (Alarm Weekday and Hours Value) ......... 289 ANCFG (A/D Band Gap Reference Configuration) ................................................... 307 ANSA (PORTA Analog Function Selection) ............. 153 ANSB (PORTB Analog Function Selection) ............. 154 ANSC (PORTC Analog Function Selection) ............. 154 ANSD (PORTD Analog Function Selection) ............. 155 ANSE (PORTE Analog Function Selection) ............. 155 ANSF (PORTF Analog Function Selection).............. 156 ANSG (PORTG Analog Function Selection) ............ 156 BDnSTAT Prototype (Buffer Descriptor n Status, CPU Mode) ............................................................... 242 BDnSTAT Prototype (Buffer Descriptor n Status, USB Mode)........................................... 241 CLKDIV (Clock Divider) ............................................ 141 CMSTAT (Comparator Status) ................................. 315 DS39975A-page 379 PIC24FJ256GB210 FAMILY CMxCON (Comparator x Control, Comparators 1-3)............................................. 314 CORCON (CPU Core Control).............................. 41, 96 CRCCON1 (CRC Control 1) ..................................... 296 CRCCON2 (CRC Control 2) ..................................... 297 CRCDATH (CRC Data High) .................................... 298 CRCDATL (CRC Data Low)...................................... 298 CRCWDATH (CRC Shift High) ................................. 299 CRCWDATL (CRC Shift Low)................................... 299 CRCXORH (CRC XOR High) ................................... 298 CRCXORL (CRC XOR Polynomial, Low Byte) ......... 297 CTMUCON (CTMU Control) ..................................... 321 CTMUICON (CTMU Current Control) ....................... 322 CVRCON (Comparator Voltage Reference Control)............................................ 318 CW1 (Flash Configuration Word 1) ........................... 324 CW2 (Flash Configuration Word 2) ........................... 326 CW3 (Flash Configuration Word 3) ........................... 327 CW4 (Flash Configuration Word 4) ........................... 328 DEVID (Device ID) .................................................... 329 DEVREV (Device Revision) ...................................... 329 I2CxCON (I2Cx Control) ........................................... 220 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 224 I2CxSTAT (I2Cx Status) ........................................... 222 ICxCON1 (Input Capture x Control 1) ....................... 193 ICxCON2 (Input Capture x Control 2) ....................... 194 IEC0 (Interrupt Enable Control 0) ............................. 106 IEC1 (Interrupt Enable Control 1) ............................. 107 IEC2 (Interrupt Enable Control 2) ............................. 109 IEC3 (Interrupt Enable Control 3) ............................. 110 IEC4 (Interrupt Enable Control 4) ............................. 111 IEC5 (Interrupt Enable Control 5) ............................. 112 IFS0 (Interrupt Flag Status 0) ..................................... 99 IFS1 (Interrupt Flag Status 1) ................................... 100 IFS2 (Interrupt Flag Status 2) ................................... 101 IFS3 (Interrupt Flag Status 3) ................................... 103 IFS4 (Interrupt Flag Status 4) ................................... 104 IFS5 (Interrupt Flag Status 5) ................................... 105 INTCON1 (Interrupt Control 1) .................................... 97 INTCON2 (Interrupt Control 2) .................................... 98 INTTREG (Interrupt Controller Test) ......................... 134 IPC0 (Interrupt Priority Control 0) ............................. 113 IPC1 (Interrupt Priority Control 1) ............................. 114 IPC10 (Interrupt Priority Control 10) ......................... 123 IPC11 (Interrupt Priority Control 11) ......................... 124 IPC12 (Interrupt Priority Control 12) ......................... 125 IPC13 (Interrupt Priority Control 13) ......................... 126 IPC15 (Interrupt Priority Control 15) ......................... 127 IPC16 (Interrupt Priority Control 16) ......................... 128 IPC18 (Interrupt Priority Control 18) ......................... 129 IPC19 (Interrupt Priority Control 19) ......................... 129 IPC2 (Interrupt Priority Control 2) ............................. 115 IPC20 (Interrupt Priority Control 20) ......................... 130 IPC21 (Interrupt Priority Control 21) ......................... 131 IPC22 (Interrupt Priority Control 22) ......................... 132 IPC23 (Interrupt Priority Control 23) ......................... 133 IPC3 (Interrupt Priority Control 3) ............................. 116 IPC4 (Interrupt Priority Control 4) ............................. 117 IPC5 (Interrupt Priority Control 5) ............................. 118 IPC6 (Interrupt Priority Control 6) ............................. 119 IPC7 (Interrupt Priority Control 7) ............................. 120 IPC8 (Interrupt Priority Control 8) ............................. 121 IPC9 (Interrupt Priority Control 9) ............................. 122 MINSEC (RTCC Minutes and Seconds Value) ......... 287 MTHDY (RTCC Month and Day Value) .................... 286 DS39975A-page 380 NVMCON (Flash Memory Control) ............................. 81 OCxCON1 (Output Compare x Control 1) ................ 200 OCxCON2 (Output Compare x Control 2) ................ 202 OSCCON (Oscillator Control) ................................... 139 OSCTUN (FRC Oscillator Tune)............................... 142 PADCFG1 (Pad Configuration Control) ............ 279, 284 PMCON1 (EPMP Control 1) ..................................... 271 PMCON2 (EPMP Control 2) ..................................... 272 PMCON3 (EPMP Control 3) ..................................... 273 PMCON4 (EPMP Control 4) ..................................... 274 PMCSxBS (Chip Select x Base Address)................. 276 PMCSxCF (Chip Select x Configuration).................. 275 PMCSxMD (Chip Select x Mode) ............................. 277 PMSTAT (EPMP Status, Slave Mode) ..................... 278 RCFGCAL (RTCC Calibration and Configuration) ................................................... 283 RCON (Reset Control)................................................ 86 REFOCON (Reference Oscillator Control) ............... 148 RPINRn (PPS Input) ......................................... 163–173 RPORn (PPS Output) ....................................... 174–181 SPIxCON1 (SPIx Control 1)...................................... 210 SPIxCON2 (SPIx Control 2)...................................... 212 SPIxSTAT (SPIx Status and Control) ....................... 208 SR (ALU STATUS) ............................................... 40, 95 T1CON (Timer1 Control) .......................................... 184 TxCON (Timer2 and Timer4 Control) ....................... 188 TyCON (Timer3 and Timer5 Control) ....................... 189 U1ADDR (USB Address) .......................................... 256 U1CNFG1 (USB Configuration 1)............................. 257 U1CNFG2 (USB Configuration 2)............................. 258 U1CON (USB Control, Device Mode)....................... 254 U1CON (USB Control, Host Mode) .......................... 255 U1EIE (USB Error Interrupt Enable) ......................... 265 U1EIR (USB Error Interrupt Status).......................... 264 U1EPn (USB Endpoint n Control)............................. 266 U1IE (USB Interrupt Enable) .................................... 263 U1IR (USB Interrupt Status, Device Mode) .............. 261 U1IR (USB Interrupt Status, Host Mode).................. 262 U1OTGCON (USB OTG Control) ............................. 251 U1OTGIE (USB OTG Interrupt Enable, Host Mode) ....................................................... 260 U1OTGIR (USB OTG Interrupt Status, Host Mode) ....................................................... 259 U1OTGSTAT (USB OTG Status, Host Mode) .......... 250 U1PWMCON USB (VBUS PWM Generator Control)............................................ 267 U1PWRC (USB Power Control)................................ 252 U1SOF (USB OTG Start-of-Token Threshold, Host Mode) ....................................................... 257 U1STAT (USB Status) .............................................. 253 U1TOK (USB Token, Host Mode)............................. 256 UxMODE (UARTx Mode).......................................... 228 UxSTA (UARTx Status and Control)......................... 230 WKDYHR (RTCC Weekday and Hours Value)......... 287 YEAR (RTCC Year Value)........................................ 286 Resets BOR (Brown-out Reset).............................................. 85 Clock Source Selection............................................... 88 CM (Configuration Mismatch Reset)........................... 85 Delay Times................................................................ 89 Device Times .............................................................. 88 IOPUWR (Illegal Opcode Reset) ................................ 85 MCLR (Pin Reset)....................................................... 85 POR (Power-on Reset)............................................... 85 RCON Flags Operation............................................... 87  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY SFR States.................................................................. 88 SWR (RESET Instruction)........................................... 85 TRAPR (Trap Conflict Reset)...................................... 85 UWR (Uninitialized W Register Reset) ....................... 85 WDT (Watchdog Timer Reset).................................... 85 Revision History ................................................................ 375 RTCC Alarm Configuration .................................................. 290 Calibration................................................................. 290 Key Features............................................................. 281 Register Mapping...................................................... 282 S Selective Peripheral Power Control .................................. 150 Serial Peripheral Interface (SPI) ....................................... 205 Serial Peripheral Interface. See SPI. SFR Space.......................................................................... 47 Sleep Mode ....................................................................... 149 Software Simulator (MPLAB SIM)..................................... 337 Software Stack .................................................................... 72 Special Features ................................................................. 16 SPI .................................................................................... 205 T Timer1 ............................................................................... 183 Timer2/3 and Timer4/5...................................................... 185 Timing Diagrams CLKO and I/O Timing................................................ 359 External Clock........................................................... 356 Triple Comparator ............................................................. 311 Triple Comparator Module ................................................ 311 USB OTG ......................................................................... 233 Buffer Descriptors and BDT...................................... 239 Device Mode Operation............................................ 244 DMA Interface........................................................... 240 Hardware Calculating Transceiver Power Requirements ............ 237 Hardware Configuration............................................ 235 Device Mode..................................................... 235 External Interface ............................................. 237 Host and OTG Modes....................................... 236 VBUS Voltage Generation ................................. 237 Host Mode Operation ............................................... 245 Interrupts .................................................................. 243 Operation.................................................................. 247 Registers .................................................................. 249 VBUS Voltage Generation ......................................... 237 V Voltage Regulator (On-Chip) ............................................ 330 and BOR................................................................... 330 Low-Voltage Detection ............................................. 330 Standby Mode .......................................................... 330 W Watchdog Timer (WDT).................................................... 331 Control Register........................................................ 331 Windowed Operation ................................................ 331 WWW Address ................................................................. 382 WWW, On-Line Support ..................................................... 14 U UART ................................................................................ 225 Baud Rate Generator (BRG)..................................... 226 IrDA Support ............................................................. 227 Operation of UxCTS and UxRTS Pins ...................... 227 Receiving in 8-Bit or 9-Bit Data Mode....................... 227 Transmitting Break and Sync Sequence ............................... 227 in 8-Bit Data Mode ............................................ 227 Transmitting in 9-Bit Data Mode ............................... 227 Universal Asynchronous Receiver Transmitter. See UART. Universal Serial Bus Buffer Descriptors Assignment in Different Buffering Modes ......... 240 Interrupts and USB Transactions ...................................... 244 Universal Serial Bus. See USB OTG. USB On-The-Go (OTG) ...................................................... 16  2010 Microchip Technology Inc. DS39975A-page 381 PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 382  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.  2010 Microchip Technology Inc. DS39975A-page 383 PIC24FJ256GB210 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC24FJ256GB210 Family Literature Number: DS39975A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39975A-page 384  2010 Microchip Technology Inc. PIC24FJ256GB210 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 256 GB2 10 T - I / PT - XXX Examples: a) PIC24FJ128GB206-I/PT: PIC24F device with USB On-The-Go, 128-KB program memory, 96-KB data memory, 64-pin, Industrial temp., TQFP package. b) PIC24FJ256GB210-I/PT: PIC24F device with USB On-The-Go, 256-KB program memory, 96-KB data memory, 100-pin, Industrial temp., TQFP package. Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture 24 = 16-bit modified Harvard without DSP Flash Memory Family FJ = Flash program memory Product Group GB2 = General purpose microcontrollers with USB On-The-Go Pin Count 06 10 = 64-pin = 100-pin (TQFP)/121-pin (BGA) Temperature Range I = -40C to +85C (Industrial) Package PT PT MR BG = 100-lead (12x12x1 mm) TQFP (Thin Quad Flatpack) = 64-lead, TQFP (Thin Quad Flatpack) = 64-lead (9x9x0.9 mm) QFN (Quad Flatpack, No Lead) = 121-pin BGA package Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample  2010 Microchip Technology Inc. DS39975A-page 385 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 01/05/10 DS39975A-page 386  2010 Microchip Technology Inc.