PIC24FJ512GU410 Family
Data Sheet
16-Bit eXtreme Low-Power Microcontrollers with LCD
Controller and USB
High-Performance CPU
•
•
•
•
•
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Modified Harvard Architecture
512 Kbytes Flash Memory
32 Kbytes RAM
Up to 16 MIPS Operation @ 32 MHz
17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
32-Bit by 16-Bit Hardware Divider
16-Bit x 16-Bit Working Register Array
C Compiler Optimized Instruction Set Architecture
Two Address Generation Units for Separate Read and Write Addressing of Data Memory
LCD Display Controller
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64 Segments and 8 Commons Supporting up to 480 Pixels
LCD Charge Pump with 5 µA Low Power
Core-Independent LCD Animation
Operation in Sleep Mode
Analog Features
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Up to 24-Channel, Software Selectable 10/12-Bit Analog-to-Digital Converter:
– 12-bit, 350K samples/second conversion rate (single Sample-and-Hold)
– 10-bit, 400K samples/second conversion rate (single Sample-and-Hold)
– Sleep mode operation
– Low-voltage boost for input
– Band gap reference input feature
– Core-independent windowed threshold compare feature
– Auto-scan feature
Three Analog Comparators with Input Multiplexing:
– Programmable reference voltage for comparators
10-Bit, 1 Msps DAC with Buffered Output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1
PIC24FJ512GU410 Family Data Sheet
eXtreme Low-Power Features
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•
Sleep and Idle modes Selectively Shut Down:
– Peripherals and/or core for substantial power reduction and fast wake-up
Doze mode Allows CPU to Run at a Lower Clock Speed than Peripherals
Alternate Clock modes Allow On-the-Fly:
– Switching to a lower clock speed for selective power reduction
Retention Sleep with On-Chip Ultra Low-Power Retention Regulator
Functional Safety and Security Peripherals
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•
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•
•
•
•
•
•
•
•
Fail-Safe Clock Monitor Operation:
– Detects clock failure and switches to on-chip, low-power RC Oscillator
Power-on Reset (POR), Brown-out Reset (BOR)
Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
Programmable High or Low-Voltage Detect (HLVD)
Flexible Watchdog Timer (WDT) with RC Oscillator for Reliable Operation
Deadman Timer (DMT) for Safety-Critical Applications
Programmable 32-Bit Cyclic Redundancy Check (CRC) Generator
Flash Configurable as OTP by ICSP™ Write Inhibit
CodeGuard™ Security
ECC Flash Memory with Fault Injection:
– Single Error Correction (SEC)
– Double-Error Detection (DED)
Customer OTP Memory
Unique Device Identifier (UDID), 120-Bit Unique ID
Special Microcontroller Features
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Supply Voltage Range of 2.0V to 3.6V
Operating Ambient Temperature Range of -40°C to +125°C
On-Chip Voltage Regulators (1.8V) for Low-Power Operation
Large, Dual Partition Flash Program Array:
– The device’s Flash memory can be configured into two physical sections or a single physical section
– Capable of holding two independent software applications, including bootloader
– Permits simultaneous programming of one partition while executing application code from the other
– Allows run-time switching between Active Partitions
•
Flash Memory:
– 10,000 erase/write cycle endurance, typical
– Data retention: 20 years minimum
– Self-programmable under software control
– Flash OTP emulation
8 MHz Fast RC Internal Oscillator:
– Multiple clock divide options
– Fast start-up
96 MHz PLL Option
Programmable Reference Clock Output
In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via Two Pins
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© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 2
PIC24FJ512GU410 Family Data Sheet
•
JTAG Boundary Scan Support
Peripheral Features
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Independent, Low-Power 32 kHz Timer Oscillator
Six-Channel DMA Controller:
– Minimizes CPU overhead and increases data throughput
Timer1: 16-Bit Timer/Counter with External Crystal Oscillator; Timer1 can Provide an A/D Trigger
Timer2,3,4,5: 16-Bit Timer/Counter, can Create 32-Bit Timer; Timer3 and Timer5 can Provide an A/D Trigger
Eight MCCP modules, Each with a Dedicated
16/32-Bit Timer:
– Three 6-output MCCP modules
– Five 2-output MCCP modules
Four Variable Widths, Serial Peripheral Interface (SPI) Ports on All Devices; Three Operation modes:
– Three-wire SPI (supports all four SPI modes)
– Up to 32-byte deep FIFO buffer
– I2S mode
– Speed up to 24 MHz
Three I2C Master and Slave w/Address Masking, PMBus™ and IPMI Support
Six UART modules:
– LIN/J2602 bus support (auto-wake-up,
Auto-Baud Detect, Break character support)
– RS-232 and RS-485 support
®
– IrDA mode (hardware encoder/decoder functions)
Five External Interrupt Pins
Hardware Real-Time Clock and Calendar (RTCC)
Peripheral Pin Select (PPS) allows Independent
I/O Mapping of Many Peripherals
Configurable Interrupt-on-Change on All I/O Pins:
– Each pin is independently configurable for rising edge or falling edge change detection
Reference Clock Output with Programmable Divider
Four Configurable Logic Cell (CLC) Blocks:
– Two inputs and one output, all mappable to peripherals or I/O pins
– AND/OR/XOR logic and D/JK flip-flop functions
PIC24FJ512GU410 Product Families
The device names, pin counts, memory sizes and peripheral availability of each device are listed in Table 1. The
following pages show their pinout diagrams.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 3
© 2019-2020 Microchip Technology Inc.
Table 1. PIC24FJ512GU410 Family
DS30010203C-page 4
Data Memory (Bytes)
Total Pins
I/O
PPS
DMA
Comparators
DAC
CRC
MCCP
Timers
I2C
SPI
UART
LCD
CLC
RTCC
ADC
USB
PIC24FJ512GU410
512k
32k
100
85
37
6
3
Yes
Yes
8
5
3
4
6
(58x8)
4
Yes
24
Yes
PIC24FJ512GU408
512k
32k
80
69
36
6
3
Yes
Yes
8
5
3
4
6
(45x8)
4
Yes
17
Yes
PIC24FJ512GU406
512k
32k
64
53
33
6
3
Yes
Yes
8
5
3
4
6
(29x8)
4
Yes
16
Yes
PIC24FJ512GU405
512k
32k
48
38
24
6
3
No
Yes
7
5
3
4
4
(15x8)
4
Yes
12
Yes
PIC24FJ256GU410
256k
32k
100
85
37
6
3
Yes
Yes
8
5
3
4
6
(58x8)
4
Yes
24
Yes
PIC24FJ256GU408
256k
32k
80
69
36
6
3
Yes
Yes
8
5
3
4
6
(45x8)
4
Yes
17
Yes
PIC24FJ256GU406
256k
32k
64
53
33
6
3
Yes
Yes
8
5
3
4
6
(29x8)
4
Yes
16
Yes
PIC24FJ256GU405
256k
32k
48
38
24
6
3
No
Yes
7
5
3
4
4
(15x8)
4
Yes
12
Yes
PIC24FJ128GU410
128k
32k
100
85
37
6
3
Yes
Yes
8
5
3
4
6
(58x8)
4
Yes
24
Yes
PIC24FJ128GU408
128k
32k
80
69
36
6
3
Yes
Yes
8
5
3
4
6
(45x8)
4
Yes
17
Yes
PIC24FJ128GU406
128k
32k
64
53
33
6
3
Yes
Yes
8
5
3
4
6
(29x8)
4
Yes
16
Yes
PIC24FJ128GU405
128k
32k
48
38
24
6
3
No
Yes
7
5
3
4
4
(15x8)
4
Yes
12
Yes
PIC24FJ512GL410
512k
32k
100
86
37
6
3
Yes
Yes
8
5
3
4
6
(60x8)
4
Yes
24
No
PIC24FJ512GL408
512k
32k
80
70
36
6
3
Yes
Yes
8
5
3
4
6
(47x8)
4
Yes
17
No
PIC24FJ512GL406
512k
32k
64
54
34
6
3
Yes
Yes
8
5
3
4
6
(32x8)
4
Yes
16
No
PIC24FJ512GL405
512k
32k
48
39
26
6
3
No
Yes
7
5
3
4
4
(19x8)
4
Yes
12
No
PIC24FJ256GL410
256k
32k
100
86
37
6
3
Yes
Yes
8
5
3
4
6
(60x8)
4
Yes
24
No
PIC24FJ256GL408
256k
32k
80
70
36
6
3
Yes
Yes
8
5
3
4
6
(47x8)
4
Yes
17
No
PIC24FJ256GL406
256k
32k
64
54
34
6
3
Yes
Yes
8
5
3
4
6
(32x8)
4
Yes
16
No
PIC24FJ256GL405
256k
32k
48
39
26
6
3
No
Yes
7
5
3
4
4
(19x8)
4
Yes
12
No
PIC24FJ128GL410
128k
32k
100
86
37
6
3
Yes
Yes
8
5
3
4
6
(60x8)
4
Yes
24
No
PIC24FJ128GL408
128k
32k
80
70
36
6
3
Yes
Yes
8
5
3
4
6
(47x8)
4
Yes
17
No
PIC24FJ128GL406
128k
32k
64
54
34
6
3
Yes
Yes
8
5
3
4
6
(32x8)
4
Yes
16
No
PIC24FJ128GL405
128k
32k
48
39
26
6
3
No
Yes
7
5
3
4
4
(19x8)
4
Yes
12
No
rotatethispage90
PIC24FJ512GU410 Family Data Sheet
Datasheet
Program Memory (Bytes)
Device
PIC24FJ512GU410 Family Data Sheet
Pin Diagrams (PIC24FJXXXGL405 Devices)
48-Pin TQFP/UQFN
1
3
2,3
Notes:
1. Shaded pins are up to 5.5 VDC tolerant.
2. This pin may be toggled during programming.
3. This pin has an increased current drive strength.
Table 2. PIC24FJXXXGL405 Devices
Function(1)
Pin
Function(1)
Pin
1
LCDBIAS2/RP34/RE5
25
SEG12/RP16/RF3
2
LCDBIAS1/RP35/SCL3/RE6
26
SEG47/SDA1/OCM1F/INT0/RG3
3
LCDBIAS0/RP36/SDA3/RE7
27
SEG28/SCL1/RG2
4
VLCAP1/C1INC/AC2INC/AC3INC/RP26/RG7
28
VDD
5
VLCAP2/C2IND/RP19/OCM2A/RG8
29
OSC1/CLKI/RC12
6
MCLR
30
OSC2/CLKO/RC15(2,3)
7
VSS
31
VSS
8
VDD
32
SEG15/C3IND/RP3/RD10
9
PGEC3/SEG2/AN5/C1INA/RP18/ASCL1/RB5
33
SEG16/C3INC/RP12/RD11
10
PGED3/SEG3/AN4/C1INB/RP28/ASDA1/RB4
34
SEG17/RP11/RD0
11
PGEC1/SEG6/CVREF-/AN1/RP1/RB1
35
SOSCI/RC13
12
PGED1/SEG7/VREF+/CVREF+/DVREF+/AN0/RP0/RB0
36
SOSCO/SCLKI/RPI37/RC14
13
PGEC2/LCDBIAS3/AN6/RP6/RB6
37
SEG22/RP22/SCK3/RD3
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 5
PIC24FJ512GU410 Family Data Sheet
...........continued
Function(1)
Pin
Function(1)
Pin
14
PGED2/AN7/RP7/T1CK/RB7
38
SEG23/RP25/SDI3/RD4
15
AVDD
39
SEG24/RP20/SDO3/RD5
16
AVSS
40
SEG25/C3INB/RP32/SS3/FSYNC3/RD6
17
COM7/SEG31/AN8/RP8/RB8
41
SEG26/C3INA/RP33/RD7
18
COM6/SEG30/AN9/RP9/RB9
42
VCAP
19
TMS/COM5/SEG29/CVREF/AN10/RPI44/RB10
43
VSS
20
TDO/AN11/RB11
44
COM4/SEG48/RPI45/OCM1E/RF1
21
TCK/SEG8/AN14/RP14/OCM1C/RB14
45
COM3/RE0
22
TDI/SEG9/AN15/RP29/OCM1D/RB15(3)
46
COM2/RE1
23
SEG10/RP10/SDA2/RF4
47
COM1/RE2
24
SEG11/RP17/SCL2/RF5
48
COM0/LVDIN/RE3
Notes:
1. RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
2. This pin may be toggled during programming.
3. These pins have an increased current drive strength.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 6
PIC24FJ512GU410 Family Data Sheet
Pin Diagrams (PIC24FJXXXGU405 Devices) (Continued)
48-Pin TQFP/UQFN
1
2,3
4
3
4
Notes:
1. Shaded pins are up to 5.5 VDC tolerant.
2. This pin may be toggled during programming.
3. This pin has an increased current drive strength.
4. Open-drain configuration does not apply to this pin.
Table 3. PIC24FJXXXGU405 Devices
Function(1)
Pin
Function(1)
Pin
1
LCDBIAS2/RP34/RE5
25
VUSB3V3
2
LCDBIAS1/RP35/SCL3/RE6
26
D-/OCM1F/RG3(4)
3
LCDBIAS0/RP36/SDA3/RE7
27
D+/RG2(4)
4
VLCAP1/C1INC/AC2INC/AC3INC/RP26/RG7
28
VDD
5
VLCAP2/C2IND/RP19/OCM2A/RG8
29
OSC1/CLKI/RC12
6
MCLR
30
OSC2/CLKO/RC15(2,3)
7
VSS
31
VSS
8
VDD
32
SEG15/C3IND/RP3/RD10
9
PGEC3/SEG2/AN5/C1INA/RP18/ASCL1/RB5
33
SEG16/C3INC/RP12/RD11
10
PGED3/SEG3/AN4/C1INB/RP28/ASDA1/USBOEN/RB4
34
SEG17/RP11/RD0
11
PGEC1/SEG6/CVREF-/AN1/RP1/RB1
35
SOSCI/RC13
12
PGED1/SEG7/VREF+/CVREF+/DVREF+/AN0/RP0/RB0
36
SOSCO/SCLKI/RPI37/RC14
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 7
PIC24FJ512GU410 Family Data Sheet
...........continued
Function(1)
Pin
Function(1)
Pin
13
PGEC2/LCDBIAS3/AN6/RP6/RB6
37
SEG22/RP22/SCK3/RD3
14
PGED2/AN7/RP7/T1CK/RB7
38
SEG23/RP25/SDI3/RD4
15
AVDD
39
SEG24/RP20/SDO3/RD5
16
AVSS
40
SEG25/C3INB/RP32/SS3/FSYNC3/RD6
17
COM7/SEG31/AN8/RP8/RB8
41
SEG26/C3INA/RP33/RD7
18
COM6/SEG30/AN9/RP9/RB9
42
VCAP
19
TMS/COM5/SEG29/CVREF/AN10/RPI44/RB10
43
VSS
20
TDO/AN11/RB11
44
COM4/SEG48/RPI45/OCM1E/RF1
21
TCK/SEG8/AN14/RP14/OCM1C/RB14
45
COM3/RE0
22
TDI/SEG9/AN15/RP29/OCM1D/RB15(3)
46
COM2/RE1
23
SEG10/RP10/SDA2/USBID/RF4
47
COM1/RE2
24
VBUS/SCL2/RF7
48
COM0/LVDIN/RE3
Notes:
1. RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
2. This pin may be toggled during programming.
3. These pins have an increased current drive strength.
4. Open-drain configuration does not apply to this pin.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 8
PIC24FJ512GU410 Family Data Sheet
Pin Diagrams (PIC24FJXXXGL406 Devices) (Continued)
64-Pin TQFP/QFN
1
3
2,3
Notes:
1. Shaded pins are up to 5.5 VDC tolerant.
2. This pin may be toggled during programming.
3. This pin has an increased current drive strength.
Pinouts are subject to change.
Table 4. PIC24FJXXXGL406 Devices
Function(1)
Pin
Function(1)
Pin
1
LCDBIAS2/RP34/RE5
33
SEG12/RP16/RF3
2
LCDBIAS1/RP35/SCL3/RE6
34
SEG41/RP15/RF8
3
LCDBIAS0/RP36/SDA3/RE7
35
INT0/RF6
4
SEG0/C1IND/RP21/OCM1A/RG6
36
SEG47/SDA1/OCM1F/RG3
5
VLCAP1/C1INC/AC2INC/AC3INC/RP26/OCM1B/RG7
37
SEG28/SCL1/RG2
6
VLCAP2/C2IND/RP19/OCM2A/RG8
38
VDD
7
MCLR
39
OSC1/CLKI/RC12
8
SEG1/C2INC/RP27/DACOUT/OCM2B/RG9
40
OSC2/CLKO/RC15(2,3)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 9
PIC24FJ512GU410 Family Data Sheet
...........continued
Function(1)
Pin
Function(1)
Pin
9
VSS
41
VSS
10
VDD
42
SEG13/RP2/U6RTS/U6BCLK/RD8
11
PGEC3/SEG2/AN5/C1INA/RP18/ASCL1/OCM3A/RB5
43
SEG14/RP4/RD9
12
PGED3/SEG3/AN4/C1INB/RP28/ASDA1/OCM3B/RB4
44
SEG15/C3IND/RP3/RD10
13
SEG4/AN3/C2INA/RB3
45
SEG16/C3INC/RP12/RD11
14
SEG5/AN2/C2INB/RP13/RB2
46
SEG17/RP11/U6CTS/RD0
15
PGEC1/SEG6/CVREF-/AN1/RP1/RB1
47
SOSCI/RC13
16
PGED1/SEG7/VREF+/CVREF+/DVREF+/AN0/RP0/RB0
48
SOSCO/SCLKI/RPI37/RC14
17
PGEC2/LCDBIAS3/AN6/RP6/RB6
49
SEG20/RP24/U5TX/RD1
18
PGED2/AN7/RP7/T1CK/U6TX/RB7
50
SEG21/RP23/RD2
19
AVDD
51
SEG22/RP22/SCK3/RD3
20
AVSS
52
SEG23/RP25/SDI3/RD4
21
COM7/SEG31/AN8/RP8/RB8
53
SEG24/RP20/SDO3/RD5
22
COM6/SEG30/AN9/RP9/RB9
54
SEG25/C3INB/RP32/U5RX/SS3/FSYNC3/RD6
23
TMS/COM5/SEG29/CVREF/AN10/RPI44/RB10
55
SEG26/C3INA/RP33/U5RTS/U5BCLK/RD7
24
TDO/AN11/RB11
56
VCAP
25
VSS
57
RH0
26
VUSB3V3
58
SEG27/U5CTS/RF0
27
TCK/SEG18/AN12/U6RX/RB12
59
COM4/SEG48/RPI45/OCM1E/RF1
28
TDI/SEG19/AN13/RB13
60
COM3/RE0
29
SEG8/AN14/RP14/OCM1C/RB14
61
COM2/RE1
30
SEG9/AN15/RP29/OCM1D/RB15(3)
62
COM1/RE2
31
SEG10/RP10/SDA2/RF4
63
COM0/RE3
32
SEG11/RP17/SCL2/RF5
64
SEG63/LVDIN/RE4
Notes:
1. RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
2. This pin may be toggled during programming.
3. These pins have an increased current drive strength.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 10
PIC24FJ512GU410 Family Data Sheet
Pin Diagrams (PIC24FJXXXGU406 Devices) (Continued)
64-Pin TQFP/QFN
1
2,3
4
3
4
Notes:
1. Shaded pins are up to 5.5 VDC tolerant.
2. This pin may be toggled during programming.
3. This pin has an increased current drive strength.
4. Open-drain configuration does not apply to this pin.
Table 5. PIC24FJXXXGU406 Devices
Function(1)
Pin
Pin
Function(1)
1
LCDBIAS2/RP34/RE5
33 SEG12/RP16/USBID/RF3
2
LCDBIAS1/RP35/SCL3/RE6
34 VBUS/RF7
3
LCDBIAS0/RP36/SDA3/RE7
35 VUSB3V3
4
SEG0/C1IND/RP21/OCM1A/RG6
36 D-/OCM1F/RG3(4)
5
VLCAP1/C1INC/AC2INC/AC3INC/RP26/OCM1B/RG7
37 D+/RG2(4)
6
VLCAP2/C2IND/RP19/OCM2A/RG8
38 VDD
7
MCLR
39 OSC1/CLKI/RC12
8
SEG1/C2INC/RP27/DACOUT/OCM2B/RG9
40 OSC2/CLKO/RC15(2,3)
9
VSS
41 VSS
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 11
PIC24FJ512GU410 Family Data Sheet
...........continued
Pin
Function(1)
Pin
Function(1)
10 VDD
42 SEG13/RP2/U6RTS/U6BCLK/RD8
11 PGEC3/SEG2/AN5/C1INA/RP18/ASCL1/OCM3A/RB5
43 SEG14/RP4/SDA1/RD9
12 PGED3/SEG3/AN4/C1INB/RP28/ASDA1/USBOEN/
OCM3B/RB4
44 SEG15/C3IND/RP3/SCL1/RD10
13 SEG4/AN3/C2INA/RB3
45 SEG16/C3INC/RP12/RD11
14 SEG5/AN2/C2INB/RP13/RB2
46 SEG17/RP11/U6CTS/INT0/RD0
15 PGEC1/SEG6/CVREF-/AN1/RP1/RB1
47 SOSCI/RC13
16 PGED1/SEG7/VREF+/CVREF+/DVREF+/AN0/RP0/RB0
48 SOSCO/SCLKI/RPI37/RC14
17 PGEC2/LCDBIAS3/AN6/RP6/RB6
49 SEG20/RP24/U5TX/RD1
18 PGED2/AN7/RP7/T1CK/U6TX/RB7
50 SEG21/RP23/RD2
19 AVDD
51 SEG22/RP22/SCK3/RD3
20 AVSS
52 SEG23/RP25/SDI3/RD4
21 COM7/SEG31/AN8/RP8/RB8
53 SEG24/RP20/SDO3/RD5
22 COM6/SEG30/AN9/RP9/RB9
54 SEG25/C3INB/RP32/U5RX/SS3/
FSYNC3/RD6
23 TMS/COM5/SEG29/CVREF/AN10/RPI44/RB10
55 SEG26/C3INA/RP33/U5RTS/U5BCLK/RD7
24 TDO/AN11/RB11
56 VCAP
25 VSS
57 RH0
26 VDD
58 SEG27/U5CTS/RF0
27 TCK/SEG18/AN12/U6RX/RB12
59 COM4/SEG48/RPI45/OCM1E/RF1
28 TDI/SEG19/AN13/RB13
60 COM3/RE0
29 SEG8/AN14/RP14/OCM1C/RB14
61 COM2/RE1
30 SEG9/AN15/RP29/OCM1D/RB15(3)
62 COM1/RE2
31 SEG10/RP10/SDA2/RF4
63 COM0/RE3
32 SEG11/RP17/SCL2/RF5
64 SEG63/LVDIN/RE4
Notes:
1. RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
2. This pin may be toggled during programming.
3. These pins have an increased current drive strength.
4. Open-drain configuration does not apply to this pin.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 12
PIC24FJ512GU410 Family Data Sheet
Pin Diagrams (PIC24FJXXXGL408 Devices) (Continued)
80-Pin TQFP
1
3
2,3
Notes:
1. Shaded pins are up to 5.5 VDC tolerant.
2. This pin may be toggled during programming.
3. This pin has an increased current drive strength.
Table 6. PIC24FJXXXGL408 Devices
Function(1)
Pin
Pin
Function(1)
1
LCDBIAS2/RP34/RE5
41 SEG12/RP16/RF3
2
LCDBIAS1/RP35/SCL3/RE6
42 SEG40/RP30/RF2
3
LCDBIAS0/RP36/SDA3/RE7
43 SEG41/RP15/RF8
4
SEG32/RPI38/OCM1D/RC1
44 RF7
5
SEG33/RPI40/OCM2D/RC3
45 INT0/RF6
6
SEG0/C1IND/RP21/OCM1A/RG6
46 SEG47/SDA1/RG3
7
VLCAP1/C1INC/AC2INC/AC3INC/RP26/OCM1B/RG7
47 SEG28/SCL1/RG2
8
VLCAP2/C2IND/RP19/OCM2A/RG8
48 VDD
9
MCLR
49 OSC1/CLKI/RC12
10 SEG1/C2INC/RP27/DACOUT/OCM2B/RG9
© 2019-2020 Microchip Technology Inc.
50 OSC2/CLKO/RC15(2,3)
Datasheet
DS30010203C-page 13
PIC24FJ512GU410 Family Data Sheet
...........continued
Function(1)
Pin
11
Pin
VSS
Function(1)
51 VSS
12 VDD
52 SEG42/RPI50/RA14
13 SEG34/RPI47/RE8
53 SEG43/RPI49/RA15
14 SEG35/AN21/RPI48/RE9
54 SEG13/RP2/U6RTS/U6BCLK/RD8
15 PGEC3/SEG2/AN5/C1INA/RP18/ASCL1/OCM3A/RB5
55 SEG14/RP4/RD9
16 PGED3/SEG3/AN4/C1INB/RP28/ASDA1/OCM3B/RB4
56 SEG15/C3IND/RP3/RD10
17 SEG4/AN3/C2INA/RB3
57 SEG16/C3INC/RP12/RD11
18 SEG5/AN2/C2INB/RP13/RB2
58 SEG17/RP11/U6CTS/RD0
19 PGEC1/SEG6/CVREF-/AN1/RP1/RB1
59 SOSCI/RC13
20 PGED1/SEG7/VREF+/CVREF+/DVREF+/AN0/RP0/RB0
60 SOSCO/SCLKI/RPI37/RC14
21 PGEC2/LCDBIAS3/AN6/RP6/RB6
61 SEG20/RP24/U5TX/RD1
22 PGED2/AN7/RP7/T1CK/U6TX/RB7
62 SEG21/RP23/RD2
23 SEG36/RA9
63 SEG22/RP22/SCK3/RD3
24 SEG37/RA10
64 SEG44/RPI42/OCM3E/RD12
25 AVDD
65 SEG45/OCM3F/RD13
26 AVSS
66 SEG23/RP25/SDI3/RD4
27 COM7/SEG31/AN8/RP8/RB8
67 SEG24/RP20/SDO3/RD5
28 COM6/SEG30/AN9/RP9/RB9
68 SEG25/C3INB/RP32/U5RX/SS3/FSYNC3/RD6
29 TMS/COM5/SEG29/CVREF/AN10/RPI44/RB10
69 SEG26/C3INA/RP33/U5RTS/U5BCLK/RD7
30 TDO/AN11/RB11
70 VCAP
31 VSS
71 RH0
32 VUSB3V3
72 SEG27/U5CTS/RF0
33 TCK/SEG18/AN12/U6RX/RB12
73 COM4/SEG48/RPI45/RF1
34 TDI/SEG19/AN13/RB13
74 SEG46/RG1
35 SEG8/AN14/RP14/OCM1C/RB14
75 SEG50/RG0
36
SEG9/AN15/RP29/RB15(3)
76 COM3/RE0
37 SEG38/RPI43/RD14
77 COM2/RE1
38 SEG39/RP5/RD15
78 COM1/RE2
39 SEG10/RP10/SDA2/RF4
79 COM0/RE3
40 SEG11/RP17/SCL2/RF5
80 SEG63/LVDIN/RE4
Notes:
1. RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
2. This pin may be toggled during programming.
3. These pins have an increased current drive strength.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 14
PIC24FJ512GU410 Family Data Sheet
Pin Diagrams (PIC24FJXXXGU408 Devices) (Continued)
80-Pin TQFP
1
2,3
4
3
4
Notes:
1. Shaded pins are up to 5.5 VDC tolerant.
2. This pin may be toggled during programming.
3. This pin has an increased current drive strength.
4. Open-drain configuration does not apply to this pin.
Table 7. PIC24FJXXXGU408 Device
Function(1)
Pin
Pin
Function(1)
1
LCDBIAS2/RP34/RE5
41 SEG12/RP16/USBID/RF3
2
LCDBIAS1/RP35/SCL3/RE6
42 SEG40/RP30/RF2
3
LCDBIAS0/RP36/SDA3/RE7
43 SEG41/RP15/RF8
4
SEG32/RPI38/OCM1D/RC1
44 VBUS/RF7
5
SEG33/RPI40/OCM2D/RC3
45 VUSB3V3
6
SEG0/C1IND/RP21/OCM1A/RG6
46 D-/RG3(4)
7
VLCAP1/C1INC/AC2INC/AC3INC/RP26/OCM1B/RG7
47 D+/RG2(4)
8
VLCAP2/C2IND/RP19/OCM2A/RG8
48 VDD
9
MCLR
49 OSC1/CLKI/RC12
10 SEG1/C2INC/RP27/DACOUT/OCM2B/RG9
© 2019-2020 Microchip Technology Inc.
50 OSC2/CLKO/RC15(2,3)
Datasheet
DS30010203C-page 15
PIC24FJ512GU410 Family Data Sheet
...........continued
Pin
Function(1)
Pin
Function(1)
11 VSS
51 VSS
12 VDD
52 SEG42/RPI50/SCL1/RA14
13 SEG34/RPI47/RE8
53 SEG43/RPI49/SDA1/RA15
14 SEG35/AN21/RPI48/RE9
54 SEG13/RP2/U6RTS/U6BCLK/RD8
15 PGEC3/SEG2/AN5/C1INA/RP18/ASCL1/OCM3A/RB5
55 SEG14/RP4/RD9
16 PGED3/SEG3/AN4/C1INB/RP28/ASDA1/USBOEN/
OCM3B/RB4
56 SEG15/C3IND/RP3/RD10
17 SEG4/AN3/C2INA/RB3
57 SEG16/C3INC/RP12/RD11
18 SEG5/AN2/C2INB/RP13/RB2
58 SEG17/RP11/U6CTS/INT0/RD0
19 PGEC1/SEG6/CVREF-/AN1/RP1/RB1
59 SOSCI/RC13
20 PGED1/SEG7/VREF+/CVREF+/DVREF+/AN0/RP0/RB0
60 SOSCO/SCLKI/RPI37/RC14
21 PGEC2/LCDBIAS3/AN6/RP6/RB6
61 SEG20/RP24/U5TX/RD1
22 PGED2/AN7/RP7/T1CK/U6TX/RB7
62 SEG21/RP23/RD2
23 SEG36/RA9
63 SEG22/RP22/SCK3/RD3
24 SEG37/RA10
64 SEG44/RPI42/OCM3E/RD12
25 AVDD
65 SEG45/OCM3F/RD13
26 AVSS
66 SEG23/RP25/SDI3/RD4
27 COM7/SEG31/AN8/RP8/RB8
67 SEG24/RP20/SDO3/RD5
28 COM6/SEG30/AN9/RP9/RB9
68 SEG25/C3INB/RP32/U5RX/SS3/
FSYNC3/RD6
29 TMS/COM5/SEG29/CVREF/AN10/RPI44/RB10
69 SEG26/C3INA/RP33/U5RTS/U5BCLK/RD7
30 TDO/AN11/RB11
70 VCAP
31 VSS
71 RH0
32 VDD
72 SEG27/U5CTS/RF0
33 TCK/SEG18/AN12/U6RX/RB12
73 COM4/SEG48/RPI45/RF1
34 TDI/SEG19/AN13/RB13
74 SEG46/RG1
35 SEG8/AN14/RP14/OCM1C/RB14
75 SEG50/RG0
36 SEG9/AN15/RP29/RB15(3)
76 COM3/RE0
37 SEG38/RPI43/RD14
77 COM2/RE1
38 SEG39/RP5/RD15
78 COM1/RE2
39 SEG10/RP10/SDA2/RF4
79 COM0/RE3
40 SEG11/RP17/SCL2/RF5
80 SEG63/LVDIN/RE4
Notes:
1. RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
2. This pin may be toggled during programming.
3. These pins have an increased current drive strength.
4. Open-drain configuration does not apply to this pin.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 16
PIC24FJ512GU410 Family Data Sheet
Pin Diagrams (PIC24FJXXXGL410 Devices) (Continued)
100-Pin TQFP
2,3
3
1
Notes:
1. Shaded pins are up to 5.5 VDC tolerant.
2. This pin may be toggled during programming.
3. This pin has an increased current drive strength.
Table 8. PIC24FJXXXGL410 Devices
Function(1)
Pin
Function(1)
Pin
1
SEG51/OCM1C/RG15
51
SEG12/RP16/RF3
2
VDD
52
SEG40/RP30/RF2
3
LCDBIAS2/RP34/RE5
53
SEG41/RP15/RF8
4
LCDBIAS1/RP35/SCL3/RE6
54
RF7
5
LCDBIAS0/RP36/SDA3/RE7
55
INT0/RF6
6
SEG32/RPI38/OCM1D/RC1
56
SEG47/SDA1/RG3
7
SEG52/RPI39/OCM2C/RC2
57
SEG28/SCL1/RG2
8
SEG33/RPI40/OCM2D/RC3
58
SEG56/SCL2/RA2
9
SEG53/AN16/RPI41/OCM3C/RC4
59
SEG57/SDA2/RA3
10 SEG0/AN17/C1IND/RP21/OCM1A/RG6
60
TDI/RA4
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 17
PIC24FJ512GU410 Family Data Sheet
...........continued
Pin
Function(1)
Function(1)
Pin
11 VLCAP1/AN18/C1INC/AC2INC/AC3INC/RP26/
OCM1B/RG7
61
TDO/RA5
12 VLCAP2/AN19/C2IND/RP19/OCM2A/RG8
62
VDD
13 MCLR
63
OSC1/CLKI/RC12
14 SEG1/AN20/C2INC/RP27/DACOUT/OCM2B/RG9
64
OSC2/CLKO/RC15(2,3)
15 VSS
65
VSS
16 VDD
66
SEG42/RPI50/RA14
17 TMS/SEG49/OCM3D/RA0
67
SEG43/RPI49/RA15
18 SEG34/RPI47/RE8
68
SEG13/RP2/U6RTS/U6BCLK/RD8
19 SEG35/AN21/RPI48/RE9
69
SEG14/RP4/RD9
20 PGEC3/SEG2/AN5/C1INA/RP18/ASCL1/OCM3A/RB5
70
SEG15/C3IND/RP3/RD10
21 PGED3/SEG3/AN4/C1INB/RP28/ASDA1/OCM3B/RB4
71
SEG16/C3INC/RP12/RD11
22 SEG4/AN3/C2INA/RB3
72
SEG17/RP11/U6CTS/RD0
23 SEG5/AN2/C2INB/RP13/RB2
73
SOSCI/RC13
24 PGEC1/SEG6/CVREF-/AN1/RP1/RB1
74
SOSCO/SCLKI/RPI37/RC14
25 PGED1/SEG7/VREF+/CVREF+/DVREF+/AN0/RP0/RB0
75
VSS
26 PGEC2/LCDBIAS3/AN6/RP6/RB6
76
SEG20/RP24/U5TX/RD1
27 PGED2/AN7/RP7/T1CK/U6TX/RB7
77
SEG21/RP23/RD2
28 SEG36/RA9
78
SEG22/RP22/SCK3/RD3
29 SEG37/RA10
79
SEG44/RPI42/OCM3E/RD12
30 AVDD
80
SEG45/OCM3F/RD13
31 AVSS
81
SEG23/RP25/SDI3/RD4
32 COM7/SEG31/AN8/RP8/RB8
82
SEG24/RP20/SDO3/RD5
33 COM6/SEG30/AN9/RP9/RB9
83
SEG25/C3INB/RP32/U5RX/SS3/FSYNC3/RD6
34 COM5/SEG29/CVREF/AN10/RPI44/RB10
84
SEG26/C3INA/RP33/U5RTS/U5BCLK/RD7
35 AN11/RB11
85
VCAP
36 VSS
86
RH0
37 VUSB3V3
87
SEG27/U5CTS/RF0
38 TCK/RA1
88
COM4/SEG48/RPI45/RF1
39 SEG54/RP31/RF13
89
SEG46/RG1
40 SEG55/RPI46/RF12
90
SEG50/RG0
41 SEG18/AN12/U6RX/RB12
91
SEG58/AN23/OCM1E/RA6
42 SEG19/AN13/RB13
92
SEG59/AN22/OCM1F/RA7
43 SEG8/AN14/RP14/RB14
93
COM3/RE0
44 SEG9/AN15/RP29/RB15(3)
94
COM2/RE1
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 18
PIC24FJ512GU410 Family Data Sheet
...........continued
Pin
Function(1)
Function(1)
Pin
45 VSS
95
SEG60/RG14
46 VDD
96
SEG61/OCM2E/RG12
47 SEG38/RPI43/RD14
97
SEG62/OCM2F/RG13
48 SEG39/RP5/RD15
98
COM1/RE2
49 SEG10/RP10/RF4
99
COM0/RE3
50 SEG11/RP17/RF5
100 SEG63/LVDIN/RE4
Notes:
1. RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
2. This pin may be toggled during programming.
3. These pins have an increased current drive strength.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 19
PIC24FJ512GU410 Family Data Sheet
Pin Diagrams (PIC24FJXXXGU410 Devices) (Continued)
100-Pin TQFP
2,3
1
4
3
4
Notes:
1. Shaded pins are up to 5.5 VDC tolerant.
2. This pin may be toggled during programming.
3. This pin has an increased current drive strength.
4. Open-drain configuration does not apply to this pin.
Table 9. PIC24FJXXXGU410 Devices
Function(1)
Pin
Function(1)
Pin
1
SEG51/OCM1C/RG15
51
SEG12/RP16/USBID/RF3
2
VDD
52
SEG40/RP30/RF2
3
LCDBIAS2/RP34/RE5
53
SEG41/RP15/RF8
4
LCDBIAS1/RP35/SCL3/RE6
54
VBUS/RF7
5
LCDBIAS0/RP36/SDA3/RE7
55
VUSB3V3
6
SEG32/RPI38/OCM1D/RC1
56
D-/RG3(4)
7
SEG52/RPI39/OCM2C/RC2
57
D+/RG2(4)
8
SEG33/RPI40/OCM2D/RC3
58
SEG56/SCL2/RA2
9
SEG53/AN16/RPI41/OCM3C/RC4
59
SEG57/SDA2/RA3
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 20
PIC24FJ512GU410 Family Data Sheet
...........continued
Pin
Function(1)
Function(1)
Pin
10 SEG0/AN17/C1IND/RP21/OCM1A/RG6
60
TDI/RA4
11 VLCAP1/AN18/C1INC/AC2INC/AC3INC/RP26/
OCM1B/RG7
61
TDO/RA5
12 VLCAP2/AN19/C2IND/RP19/OCM2A/RG8
62
VDD
13 MCLR
63
OSC1/CLKI/RC12
14 SEG1/AN20/C2INC/RP27/DACOUT/OCM2B/RG9
64
OSC2/CLKO/RC15(2,3)
15 VSS
65
VSS
16 VDD
66
SEG42/RPI50/SCL1/RA14
17 TMS/SEG49/OCM3D/RA0
67
SEG43/RPI49/SDA1/RA15
18 SEG34/RPI47/RE8
68
SEG13/RP2/U6RTS/U6BCLK/RD8
19 SEG35/AN21/RPI48/RE9
69
SEG14/RP4/RD9
20 PGEC3/SEG2/AN5/C1INA/RP18/ASCL1/OCM3A/RB5
70
SEG15/C3IND/RP3/RD10
21 PGED3/SEG3/AN4/C1INB/RP28/ASDA1/USBOEN/
OCM3B/RB4
71
SEG16/C3INC/RP12/RD11
22 SEG4/AN3/C2INA/RB3
72
SEG17/RP11/U6CTS/INT0/RD0
23 SEG5/AN2/C2INB/RP13/RB2
73
SOSCI/RC13
24 PGEC1/SEG6/CVREF-/AN1/RP1/RB1
74
SOSCO/SCLKI/RPI37/RC14
25 PGED1/SEG7/VREF+/CVREF+/DVREF+/AN0/RP0/RB0
75
VSS
26 PGEC2/LCDBIAS3/AN6/RP6/RB6
76
SEG20/RP24/U5TX/RD1
27 PGED2/AN7/RP7/T1CK/U6TX/RB7
77
SEG21/RP23/RD2
28 SEG36/RA9
78
SEG22/RP22/SCK3/RD3
29 SEG37/RA10
79
SEG44/RPI42/OCM3E/RD12
30 AVDD
80
SEG45/OCM3F/RD13
31 AVSS
81
SEG23/RP25/SDI3/RD4
32 COM7/SEG31/AN8/RP8/RB8
82
SEG24/RP20/SDO3/RD5
33 COM6/SEG30/AN9/RP9/RB9
83
SEG25/C3INB/RP32/U5RX/SS3/FSYNC3/RD6
34 COM5/SEG29/CVREF/AN10/RPI44/RB10
84
SEG26/C3INA/RP33/U5RTS/U5BCLK/RD7
35 AN11/RB11
85
VCAP
36 VSS
86
RH0
37 VDD
87
SEG27/U5CTS/RF0
38 TCK/RA1
88
COM4/SEG48/RPI45/RF1
39 SEG54/RP31/RF13
89
SEG46/RG1
40 SEG55/RPI46/RF12
90
SEG50/RG0
41 SEG18/AN12/U6RX/RB12
91
SEG58/AN23/OCM1E/RA6
42 SEG19/AN13/RB13
92
SEG59/AN22/OCM1F/RA7
43 SEG8/AN14/RP14/RB14
93
COM3/RE0
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 21
PIC24FJ512GU410 Family Data Sheet
...........continued
Pin
Function(1)
Function(1)
Pin
44 SEG9/AN15/RP29/RB15(3)
94
COM2/RE1
45 VSS
95
SEG60/RG14
46 VDD
96
SEG61/OCM2E/RG12
47 SEG38/RPI43/RD14
97
SEG62/OCM2F/RG13
48 SEG39/RP5/RD15
98
COM1/RE2
49 SEG10/RP10/RF4
99
COM0/RE3
50 SEG11/RP17/RF5
100 SEG63/LVDIN/RE4
Notes:
1. RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
2. This pin may be toggled during programming.
3. These pins have an increased current drive strength.
4. Open-drain configuration does not apply to this pin.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 22
PIC24FJ512GU410 Family Data Sheet
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© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 23
PIC24FJ512GU410 Family Data Sheet
Table of Contents
High-Performance CPU..................................................................................................................................1
LCD Display Controller...................................................................................................................................1
Analog Features............................................................................................................................................. 1
eXtreme Low-Power Features........................................................................................................................2
Functional Safety and Security Peripherals................................................................................................... 2
Special Microcontroller Features....................................................................................................................2
Peripheral Features........................................................................................................................................3
PIC24FJ512GU410 Product Families............................................................................................................ 3
Pin Diagrams (PIC24FJXXXGL405 Devices).................................................................................................5
Pin Diagrams (PIC24FJXXXGU405 Devices) (Continued)............................................................................ 7
Pin Diagrams (PIC24FJXXXGL406 Devices) (Continued).............................................................................9
Pin Diagrams (PIC24FJXXXGU406 Devices) (Continued).......................................................................... 11
Pin Diagrams (PIC24FJXXXGL408 Devices) (Continued)...........................................................................13
Pin Diagrams (PIC24FJXXXGU408 Devices) (Continued).......................................................................... 15
Pin Diagrams (PIC24FJXXXGL410 Devices) (Continued)...........................................................................17
Pin Diagrams (PIC24FJXXXGU410 Devices) (Continued).......................................................................... 20
1.
Device Overview................................................................................................................................... 30
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
2.
Guidelines for Getting Started with 16-Bit MCUs.................................................................................. 39
2.1.
2.2.
2.3.
2.4.
2.5.
2.6.
2.7.
3.
Core Features............................................................................................................................ 30
DMA Controller...........................................................................................................................31
LCD Controller............................................................................................................................31
USB On-The-Go (OTG)..............................................................................................................31
Other Special Features.............................................................................................................. 32
Available Features......................................................................................................................32
Basic Connection Requirements................................................................................................ 39
Power Supply Pins..................................................................................................................... 40
Master Clear (MCLR) Pin........................................................................................................... 40
Voltage Regulator Pin (VCAP)..................................................................................................... 41
ICSP Pins................................................................................................................................... 42
External Oscillator Pins.............................................................................................................. 43
Unused I/Os............................................................................................................................... 43
CPU.......................................................................................................................................................44
3.1.
3.2.
Programmer’s Model.................................................................................................................. 44
Arithmetic Logic Unit (ALU)........................................................................................................ 47
© 2019-2020 Microchip Technology Inc.
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PIC24FJ512GU410 Family Data Sheet
3.3.
4.
Program Memory.................................................................................................................................. 77
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
4.10.
4.11.
5.
Special Function Register Reset States...................................................................................164
Device Reset Times................................................................................................................. 164
Brown-out Reset (BOR)........................................................................................................... 165
Low-Power BOR.......................................................................................................................166
Clock Source at Reset..............................................................................................................166
Reset Register..........................................................................................................................167
Interrupt Controller.............................................................................................................................. 170
8.1.
8.2.
8.3.
9.
Summary of DMA Operations...................................................................................................110
Typical Setup............................................................................................................................ 114
Peripheral Module Disable....................................................................................................... 114
DMA Registers......................................................................................................................... 115
Resets................................................................................................................................................. 163
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
8.
Data Space Width.................................................................................................................... 102
Data Memory Organization and Alignment.............................................................................. 103
Near Data Space......................................................................................................................103
Special Function Register (SFR) Space...................................................................................103
Interfacing Program and Data Memory Spaces....................................................................... 103
Direct Memory Access Controller (DMA)............................................................................................ 109
6.1.
6.2.
6.3.
6.4.
7.
Program Memory Organization.................................................................................................. 80
Hard Memory Vectors.................................................................................................................81
Configuration Bits Overview....................................................................................................... 81
Code-Protect Configuration Bits.................................................................................................81
Table Instructions and Flash Programming................................................................................ 81
RTSP Operation......................................................................................................................... 82
Error Correcting Code (ECC)..................................................................................................... 88
Flash OTP by ICSP™ Write Inhibit............................................................................................. 89
JTAG Operation..........................................................................................................................89
Enhanced In-Circuit Serial Programming................................................................................... 89
Program Memory Registers....................................................................................................... 90
Data Memory Space........................................................................................................................... 102
5.1.
5.2.
5.3.
5.4.
5.5.
6.
CPU Registers............................................................................................................................48
Interrupt Vector Table............................................................................................................... 170
Reset Sequence.......................................................................................................................170
Interrupt Controller Registers................................................................................................... 177
Oscillator Configuration.......................................................................................................................256
9.1.
9.2.
9.3.
9.4.
9.5.
9.6.
9.7.
Initial Configuration on POR.....................................................................................................257
Clock Switching Operation....................................................................................................... 257
Fail-Safe Clock Monitor (FSCM).............................................................................................. 258
Internal Fast RC (FRC) Oscillator with Active Clock Tuning.................................................... 259
Primary Oscillator (PRI or POSC)............................................................................................ 259
Low-Power RC (LPRC) Oscillator............................................................................................ 259
Secondary Oscillator (SOSC)...................................................................................................260
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PIC24FJ512GU410 Family Data Sheet
9.8. PLL Block and USB Operation................................................................................................. 260
9.9. Reference Clock Output........................................................................................................... 261
9.10. Oscillator Registers.................................................................................................................. 263
10. Power-Saving Features.......................................................................................................................275
10.1.
10.2.
10.3.
10.4.
10.5.
Clock Frequency and Clock Switching..................................................................................... 275
Instruction-Based Power-Saving Modes.................................................................................. 275
Doze Mode............................................................................................................................... 277
Selective Peripheral Module Control........................................................................................ 277
Peripheral Module Disable Registers....................................................................................... 279
11. I/O Ports.............................................................................................................................................. 288
11.1.
11.2.
11.3.
11.4.
11.5.
Parallel I/O (PIO) Ports.............................................................................................................288
Configuring Analog Port Pins................................................................................................... 289
Interrupt-on-Change (IOC)....................................................................................................... 290
Peripheral Pin Select (PPS)..................................................................................................... 291
I/O Port and Peripheral Pin Select Registers........................................................................... 298
12. Timer1................................................................................................................................................. 426
12.1. Timer1 Registers...................................................................................................................... 427
13. Timer2/3 and Timer4/5........................................................................................................................ 432
13.1. Timer2/3 and Timer4/5 Registers............................................................................................. 435
14. Capture/Compare/PWM/Timer Modules (MCCP)............................................................................... 454
14.1.
14.2.
14.3.
14.4.
14.5.
14.6.
Time Base Generator............................................................................................................... 455
General Purpose Timer............................................................................................................ 455
Output Compare Mode.............................................................................................................457
Input Capture Mode..................................................................................................................459
Auxiliary Output........................................................................................................................ 460
MCCP Registers.......................................................................................................................462
15. Serial Peripheral Interface (SPI)......................................................................................................... 612
15.1.
15.2.
15.3.
15.4.
15.5.
Master Mode Operation............................................................................................................614
Slave Mode Operation..............................................................................................................615
Audio Mode Operation............................................................................................................. 615
Relationship Between Device and SPI Clock Speed............................................................... 616
SPI Registers........................................................................................................................... 617
16. Inter-Integrated Circuit (I2C)................................................................................................................ 684
16.1.
16.2.
16.3.
16.4.
Communicating as a Master in a Single Master Environment..................................................686
Setting Baud Rate When Operating as a Bus Master.............................................................. 686
Slave Address Masking............................................................................................................686
I2C Registers............................................................................................................................688
17. Universal Asynchronous Receiver Transmitter (UART)...................................................................... 725
17.1.
17.2.
17.3.
17.4.
UART Baud Rate Generator (BRG)......................................................................................... 726
Transmitting in 8-Bit Data Mode............................................................................................... 727
Transmitting in 9-Bit Data Mode............................................................................................... 727
Break and Sync Transmit Sequence........................................................................................ 727
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
17.5.
17.6.
17.7.
17.8.
Receiving in 8-Bit or 9-Bit Data Mode...................................................................................... 727
Operation of UxCTS and UxRTS Control Pins.........................................................................727
Infrared Support....................................................................................................................... 728
UART Registers....................................................................................................................... 729
18. Liquid Crystal Display (LCD) Controller.............................................................................................. 779
18.1. LCD Registers.......................................................................................................................... 781
19. Real-Time Clock and Calendar (RTCC) with Timestamp....................................................................997
19.1.
19.2.
19.3.
19.4.
19.5.
19.6.
19.7.
RTCC Source Clock................................................................................................................. 998
RTCC Module Registers.......................................................................................................... 999
Calibration.............................................................................................................................. 1000
Alarm...................................................................................................................................... 1000
Power Control.........................................................................................................................1001
Event Timestamping...............................................................................................................1002
RTCC Registers..................................................................................................................... 1003
20. 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator.................................................1023
20.1. User Interface.........................................................................................................................1024
20.2. CRC Registers....................................................................................................................... 1026
21. Configurable Logic Cell (CLC).......................................................................................................... 1035
21.1. CLC Registers........................................................................................................................ 1038
22. 12-Bit A/D Converter with Threshold Detect..................................................................................... 1072
22.1.
22.2.
22.3.
22.4.
Basic Operation......................................................................................................................1074
Extended DMA Operations.....................................................................................................1074
Sampling Time Requirements................................................................................................ 1076
12-Bit A/D Converter Registers.............................................................................................. 1078
23. 10-Bit Digital-to-Analog Converter (DAC).......................................................................................... 1118
23.1. DAC Registers........................................................................................................................1120
24. Triple Comparator Module.................................................................................................................1124
24.1. Triple Comparator Module Registers......................................................................................1126
25. Comparator Voltage Reference......................................................................................................... 1134
25.1. Comparator Voltage Reference Register................................................................................1135
26. High/Low-Voltage Detect (HLVD)...................................................................................................... 1137
26.1. High/Low-Voltage Detect (HLVD) Register............................................................................. 1138
27. Deadman Timer (DMT)......................................................................................................................1141
27.1. Deadman Timer (DMT) Registers...........................................................................................1142
28. USB with On-The-Go (USB OTG) Support....................................................................................... 1154
28.1.
28.2.
28.3.
28.4.
Hardware Configuration..........................................................................................................1156
USB Buffer Descriptors and the BDT..................................................................................... 1159
USB On-The-Go Registers.....................................................................................................1162
USB Interrupts........................................................................................................................ 1165
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
28.5. Device Mode Operation..........................................................................................................1167
28.6. Host Mode Operation............................................................................................................. 1168
28.7. OTG Operation....................................................................................................................... 1170
28.8. USB OTG Module Registers.................................................................................................. 1171
28.9. USB Interrupt Registers..........................................................................................................1171
28.10. USB OTG Registers............................................................................................................... 1184
28.11. USB Endpoint Management Registers...................................................................................1201
29. Special Features............................................................................................................................... 1218
29.1. Configuration Bits................................................................................................................... 1218
29.2. Device Identification............................................................................................................... 1237
29.3. Unique Device Identifier (UDID)............................................................................................. 1239
29.4. On-Chip Voltage Regulator.................................................................................................... 1240
29.5. Watchdog Timer (WDT)..........................................................................................................1241
29.6. Program Verification and Code Protection............................................................................. 1242
29.7. JTAG Interface....................................................................................................................... 1242
29.8. In-Circuit Serial Programming™ (ICSP)™.............................................................................. 1242
29.9. Customer OTP Memory......................................................................................................... 1243
29.10. In-Circuit Debugger................................................................................................................ 1243
30. Development Support....................................................................................................................... 1244
31. Instruction Set Summary...................................................................................................................1245
32. Electrical Characteristics...................................................................................................................1255
32.1. Absolute Maximum Ratings(1)................................................................................................ 1255
32.2. DC Characteristics................................................................................................................. 1256
32.3. AC Characteristics and Timing Parameters........................................................................... 1268
33. Package Information......................................................................................................................... 1289
33.1. Package Marking Information.................................................................................................1289
33.2. Package Marking Information (Continued).............................................................................1290
33.3. Package Details..................................................................................................................... 1290
34. Revision History................................................................................................................................ 1307
34.1. Revision A (August 2019).......................................................................................................1307
34.2. Revision B (December 2019)................................................................................................. 1307
34.3. Revision C (May 2020)...........................................................................................................1307
The Microchip Website.............................................................................................................................1308
Product Change Notification Service........................................................................................................1308
Customer Support.................................................................................................................................... 1308
Product Identification System...................................................................................................................1309
Microchip Devices Code Protection Feature............................................................................................ 1309
Legal Notice............................................................................................................................................. 1310
Trademarks.............................................................................................................................................. 1310
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 28
PIC24FJ512GU410 Family Data Sheet
Quality Management System................................................................................................................... 1310
Worldwide Sales and Service................................................................................................................... 1311
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 29
PIC24FJ512GU410 Family Data Sheet
Device Overview
1.
Device Overview
This document contains device-specific information for the following devices:
•
PIC24FJ512GU410
•
PIC24FJ512GL410
•
PIC24FJ512GU408
•
PIC24FJ512GL408
•
PIC24FJ512GU406
•
PIC24FJ512GL406
•
PIC24FJ512GU405
•
PIC24FJ512GL405
•
PIC24FJ256GU410
•
PIC24FJ256GL410
•
PIC24FJ256GU408
•
PIC24FJ256GL408
•
PIC24FJ256GU406
•
PIC24FJ256GL406
•
PIC24FJ256GU405
•
PIC24FJ256GL405
•
PIC24FJ128GU410
•
PIC24FJ128GL410
•
PIC24FJ128GU408
•
PIC24FJ128GL408
•
PIC24FJ128GU406
•
PIC24FJ128GL406
•
PIC24FJ128GU405
•
PIC24FJ128GL405
The PIC24FJ512GU410 family introduces eXtreme Low-Power Microcontrollers with USB in smaller package sizes.
This is a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance.
This family also offers a new migration option for those high-performance applications which may be outgrowing their
8-bit platforms, but do not require the numerical processing power of a Digital Signal Processor (DSP).
Table 1-1 lists the functions of the various pins shown in the pinout diagrams.
1.1
Core Features
1.1.1
16-Bit Architecture
Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC®
Digital Signal Controllers (DSCs). The PIC24F CPU core offers a wide range of enhancements, such as:
•
•
•
•
•
•
•
1.1.2
16-bit data and 24-bit address paths with the ability to move information between program and data memory
spaces
Linear addressing of up to 12 Mbytes (program space) and 32 Kbytes (data)
A 16-element Working register array with built-in software stack support
A 17 x 17 hardware multiplier with support for integer math
Hardware support for 32 by 16-bit division
An instruction set that supports multiple addressing modes and is optimized for high-level languages,
such as ‘C’
Operational performance up to 16 MIPS
Power-Saving Technology
The PIC24FJ512GU410 family of devices includes low-voltage Sleep, a low-power mode with essential circuits being
powered from a separate low-voltage regulator. This low-power mode also supports the continuous operation of the
low-power, on-chip Real-Time Clock/Calendar (RTCC), making it possible for an application to keep time while the
device is otherwise asleep.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 30
PIC24FJ512GU410 Family Data Sheet
Device Overview
Aside from this feature, PIC24FJ512GU410 family devices also include all of the legacy power-saving features of
previous PIC24F microcontrollers, such as:
•
•
•
1.1.3
On-the-Fly Clock Switching, allowing the selection of a lower power clock during run time
Doze Mode Operation, for maintaining peripheral clock speed while slowing the CPU clock
Instruction-Based Power-Saving Modes, for quick invocation of the Idle and Sleep modes
Oscillator Options and Features
All of the devices in the PIC24FJ512GU410 family offer six different oscillator options, allowing users a range of
choices in developing application hardware. These include:
•
•
•
•
•
Two Crystal modes
External Clock (EC) mode
A Phase-Locked Loop (PLL) frequency multiplier, which allows processor speeds up to 32 MHz
An internal Fast RC Oscillator (FRC), a nominal 8 MHz output with multiple frequency divider options
A separate internal Low-Power RC (LPRC) Oscillator, 32 kHz nominal for low-power,
timing-insensitive applications
The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor (FSCM). This
option constantly monitors the main clock source against a reference signal provided by the internal oscillator and
enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe
application shutdown.
1.1.4
Easy Migration
Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration
path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in
migrating from one device to the next larger device.
1.2
DMA Controller
PIC24FJ512GU410 family devices have a Direct Memory Access (DMA) Controller. This module acts in concert with
the CPU, allowing data to move between data memory and peripherals without the intervention of the CPU,
increasing data throughput and decreasing execution time overhead. Six independently programmable channels
make it possible to service multiple peripherals at virtually the same time, with each channel peripheral performing a
different operation. Many types of data transfer operations are supported.
1.3
LCD Controller
The versatile on-chip LCD Controller includes many features that make the integration of displays in low-power
applications easier. These include an integrated voltage regulator with charge pump and an integrated internal
resistor ladder that allows contrast control in software, and display operation above the device VDD.
Core-Independent Automatic Display Features:
•
•
•
•
1.4
Dual display memory
Blink mode of individual pixels or all pixels
Blank of individual pixels or all pixels
Timing schedule can be changed without core intervention, based on user configurations
USB On-The-Go (OTG)
The PIC24FJ512GU410 family of devices has USB On-The-Go functionality. This module provides on-chip
functionality as a target device compatible with the USB 2.0 standard, as well as limited stand-alone functionality as a
USB embedded host. By implementing USB Host Negotiation Protocol (HNP), the module can also dynamically
switch between device and host operation, allowing for a much wider range of versatile USB-enabled applications on
a microcontroller platform. In addition to USB host functionality, the PIC24FJ512GU410 family devices provide a true
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 31
PIC24FJ512GU410 Family Data Sheet
Device Overview
single chip USB solution, including an on-chip transceiver and voltage regulator, and a voltage boost generator for
sourcing bus power during host operations.
1.5
Other Special Features
•
•
•
•
•
•
•
1.6
Peripheral Pin Select: The Peripheral Pin Select (PPS) feature allows most digital peripherals to be mapped
over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many
digital peripherals to any one of the I/O pins.
Configurable Logic Cell: The Configurable Logic Cell (CLC) module allows the user to specify combinations of
signals as inputs to a logic function and to use the logic output to control other peripherals or I/O pins.
Timing Modules: The PIC24FJ512GU410 family provides three independent, general purpose, 16-bit timers (two
of which can be combined into two 32-bit timer). The devices also include five multiple output advanced
Capture/Compare/PWM/Timer peripherals.
Communications: The PIC24FJ512GU410 family incorporates a range of serial communication peripherals to
handle a range of application requirements. There are two independent I2C modules that support both Master
and Slave modes of operation. Devices also have, through the PPS feature, two independent UARTs with built®
in IrDA encoders/decoders and two SPI modules.
Analog Features: All members of the PIC24FJ512GU410 family include a 12-bit A/D Converter (ADC) module
and a triple comparator module. The A/D module incorporates a range of new features that allow the converter
to assess and make decisions on incoming data, reducing CPU overhead for routine A/D conversions. The
comparator module includes three analog comparators that are configurable for a wide range of operations.
Real-Time Clock and Calendar (RTCC): This module implements a full-featured clock and calendar with alarm
functions in hardware, freeing up timer resources and program memory space for use of the core application.
Deadman Timer (DMT): This module is provided to interrupt the processor in the event of a software
malfunction.
Available Features
Devices in the PIC24FJ512GU410 family are available in 48-pin, 64-pin, 80-pin and 100-pin packages. The general
block diagram for all devices is shown in Figure 1-1.
A list of the pin features available on the PIC24FJ512GU410 family devices, sorted by function, is shown in Table 1-1.
Pin feature information is provided in the pinout diagrams in the beginning of this data sheet. Multiplexed features are
sorted by the priority given to a feature, with the highest priority peripheral being listed first.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 32
PIC24FJ512GU410 Family Data Sheet
Device Overview
Figure 1-1. PIC24FJ512GU410 Family General Block Diagram
MCCP
1-3 & 4-8
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 33
PIC24FJ512GU410 Family Data Sheet
Device Overview
Notes:
1. Not all I/O pins or features are implemented on all device pinout configurations. See pinout diagrams and
tables for specific implementations by pin count.
2. BOR functionality is provided when the on-board voltage regulator is enabled.
3. Some peripheral I/Os are only accessible through remappable pins.
4. USB is available on PIC24FJXXXGUXXX devices only.
Table 1-1. PIC24FJ512GU410 Family Pinout Description
Pin Name
Pin Type
Buffer Type
PPS
Description
AN0-AN23
I
Analog
No
A/D Analog Inputs
AVDD
P
—
No
Positive Supply for Analog Modules
AVSS
P
—
No
Ground Reference for Analog Modules
C1INA-C1IND
C1OUT
I
O
Analog
DIG
No Comparator 1 Input A through D
Yes Comparator 1 Output
C2INA-C2IND
C2OUT
I
O
Analog
DIG
No Comparator 2 Input A through D
Yes Comparator 2 Output
AC2INC
I
Analog
No
C3INA-C3IND
C3OUT
I
O
Analog
DIG
No Comparator 3 Input A through D
Yes Comparator 3 Output
AC3INC
I
Analog
No
Alternate Comparator 3 Input C
Alternate Comparator 2 Input C
CLKI
CLKO
—
O
—
DIG
No
No
Primary Oscillator Clock Input (EC)
System Clock Output
COM0-COM7
O
Analog
No
LCD Driver Common Outputs
LCDBIAS0-LCDBIAS3
O
Analog
No
Bias Inputs for LCD Driver Charge Pump
VLCAP1
O
Analog
No
LCD Drive Charge Pump Capacitor Input 1
VLCAP2
O
Analog
No
LCD Drive Charge Pump Capacitor Input 2
SEG0-SEG63
O
Analog
No
LCD Driver Segment Outputs
CVREF
O
Analog
No
Comparator Voltage Reference Output
CVREF+
I
Analog
No
Comparator Voltage Reference (high) Input
CVREF-
I
Analog
No
Comparator Voltage Reference (low) Input
INT0
INT1-INT4
I
I
ST
ST
No External Interrupt Input 0
Yes External Interrupt Inputs 1 through 4
LVDIN
I
Analog
No
Low-Voltage Detect Input
MCLR
I
ST
No
Master Clear (device Reset) Input, this line is brought
low to cause a Reset
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
Device Overview
...........continued
Pin Name
Pin Type
Buffer Type
PPS
Description
ICM1-ICM8
I
ST
Yes MCCP Capture Inputs 1 through 8
TCKIA-TCKIB
I
ST
Yes MCCP Timer Clock Inputs
OCFA-OCFB
I
ST
Yes MCCP Fault Inputs A through B
OCM1A-OCM1F
O
DIG
No
MCCP1 Outputs A through F
OCM2A-OCM2F
O
DIG
No
MCCP2 Outputs A through F
OCM3A-OCM3F
O
DIG
No
MCCP3 Outputs A through F
OCM4A-OCM4B
O
DIG
Yes MCCP4 Outputs A through B
OCM5A-OCM5B
O
DIG
Yes MCCP5 Outputs A through B
OCM6A-OCM6B
O
DIG
Yes MCCP6 Outputs A through B
OCM7A-OCM7B
O
DIG
Yes MCCP7 Outputs A through B
OCM8A-OCM7B
O
DIG
Yes MCCP8 Outputs A through B
CLCINA-CLCIND
CLC1OUT-CLC4OUT
I
O
ST
DIG
Yes CLC Inputs A through D
Yes CLC Outputs 1 through 4
DACOUT
O
Analog
No
DAC1 Output
OSC1
OSC2
I
O
Analog
Analog
No
No
Primary Oscillator Crystal Connection Input
Primary Oscillator Crystal Connection Output
SOSCI
SOSCO
I
O
Analog
Analog
No
No
Secondary Oscillator Crystal Connection Input
Secondary Oscillator Crystal Connection Output
CLKI
CLKO
I
O
ST
DIG
No
Primary Oscillator Input (EC)
CPU Clock Output
PGEC1
I
ST
No
ICSP™ Programming Clock 1
PGED1
I/O
DIG/ST
No
ICSP Programming Data 1
PGEC2
I
ST
No
ICSP Programming Clock 2
PGED2
I/O
DIG/ST
No
ICSP Programming Data 2
PGEC3
I
ST
No
ICSP Programming Clock 3
PGED3
I/O
DIG/ST
No
ICSP Programming Data 3
Real-Time Clock 50/60 Hz Clock Input
PWRLCLK
I
ST
No
TMPRN
I
ST
Yes Tamper Detect
PWRGT
O
DIG
Yes RTCC Power Control
RTCC
O
DIG
Yes RTCC Clock Output
REFO
O
DIG
Yes Reference Clock Output
REFI
I
ST
Yes Reference Clock Input
RA0-7, RA9-10, RA14-15
I/O
DIG/ST
No
PORTA Digital I/Os
RB0-15
I/O
DIG/ST
No
PORTB Digital I/Os
RC1-4, RC12-15
I/O
DIG/ST
No
PORTC Digital I/Os
RD0-15
I/O
DIG/ST
No
PORTD Digital I/Os
RE0-9
I/O
DIG/ST
No
PORTE Digital I/Os
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
Device Overview
...........continued
Pin Name
Pin Type
Buffer Type
PPS
Description
RF0-5, RF7-8, RF12-13
I/O
DIG/ST
No
PORTF Digital I/Os
RG0-3, RG6-9, RG12-15
RH0
I/O
I/O
DIG/ST
DIG/ST
No
No
PORTG Digital I/Os
PORTH Digital I/O
RP0-RP36
I/O
DIG/ST
Yes Remappable Peripherals (input or output)
I
ST
Yes Remappable Peripherals (input only)
SCK1
I/O
ST
Yes Synchronous Serial Clock Input/Output for SPI1
SDI1
I
ST
Yes SPI1 Data In
SDO1
O
DIG
Yes SPI1 Data Out
SS1
I/O
ST
Yes SPI1 Slave Synchronization or Frame Pulse I/O
SCK2
I/O
ST
Yes Synchronous Serial Clock Input/Output for SPI2
SDI2
I
ST
Yes SPI2 Data In
SDO2
O
DIG
Yes SPI2 Data Out
SS2
I/O
ST
Yes SPI2 Slave Synchronization or Frame Pulse I/O
SCK3
I/O
ST
No
Synchronous Serial Clock Input/Output for SPI3
SDI3
I
ST
No
SPI3 Data In
SDO3
O
DIG
No
SPI3 Data Out
SS3
I/O
ST
No
SPI3 Slave Synchronization or Frame Pulse I/O
SCK4
I/O
ST
Yes Synchronous Serial Clock Input/Output for SPI4
SDI4
I
ST
Yes SPI4 Data In
SDO4
O
DIG
Yes SPI4 Data Out
SS4
I/O
ST
Yes SPI4 Slave Synchronization or Frame Pulse I/O
SCL1
I/O
DIG/I2C/SMB
No
I2C1 Synchronous Serial Clock Input/Output
SDA1
I/O
DIG/I2C/SMB
No
I2C1 Data Input/Output
ASCL1
I/O
DIG/I2C/SMB
No
Alternate I2C1 Synchronous Serial Clock Input/Output
ASDA1
I/O
DIG/I2C/SMB
No
Alternate I2C1 Data Input/Output
SCL2
I/O
DIG/I2C/SMB
No
I2C2 Synchronous Serial Clock Input/Output
SDA2
I/O
DIG/I2C/SMB
No
I2C2 Data Input/Output
SCL3
SDA3
I/O
I/O
DIG/I2C/SMB
DIG/I2C/SMB
No
No
I2C3 Synchronous Serial Clock Input/Output
I2C3 Data Input/Output
RPI37-RPI50
U1CTS
I
ST
Yes UART1 Clear-to-Send
U1RTS
O
DIG
Yes UART1 Request-to-Send
U1RX
I
ST
Yes UART1 Receive
U1TX
O
DIG
Yes UART1 Transmit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 36
PIC24FJ512GU410 Family Data Sheet
Device Overview
...........continued
Pin Name
Pin Type
Buffer Type
PPS
Description
U2CTS
I
ST
Yes UART2 Clear-to-Send
U2RTS
O
DIG
Yes UART2 Request-to-Send
U2RX
I
ST
Yes UART2 Receive
U2TX
O
DIG
Yes UART2 Transmit
U3CTS
I
ST
Yes UART3 Clear-to-Send
U3RTS
O
DIG
Yes UART3 Request-to-Send
U3RX
I
ST
Yes UART3 Receive
U3TX
O
DIG
Yes UART3 Transmit
U4CTS
I
ST
Yes UART4 Clear-to-Send
U4RTS
O
DIG
Yes UART4 Request-to-Send
U4RX
I
ST
Yes UART4 Receive
U4TX
O
DIG
Yes UART4 Transmit
U5CTS
I
ST
No
UART5 Clear-to-Send
U5RTS
O
DIG
No
UART5 Request-to-Send
U5RX
I
ST
No
UART5 Receive
U5TX
O
DIG
No
UART5 Transmit
U6CTS
I
ST
No
UART6 Clear-to-Send
U6RTS
O
DIG
No
UART6 Request-to-Send
U6RX
I
ST
No
UART6 Receive
U6TX
O
DIG
No
UART6 Transmit
SCLKI
I
ST
No
Secondary Oscillator Clock Input
T1CK
I
ST
No
Timer1 Clock
T2CK-T5CK
I
ST
Yes Timer2 through Timer5 Clock
TxCK
I
ST
Yes Generic Timerx External Clock
TCK
I
ST
No
JTAG Test Clock/Programming Clock Input
TDI
I
ST
No
JTAG Test Data/Programming Data Input
TDO
O
DIG
No
JTAG Test Data Output
TMS
I
ST
No
JTAG Test Mode Select Input
VCAP
P
—
No
External Filter Capacitor Connection (regulator enabled)
VDD
P
—
No
Positive Supply for Peripheral Digital Logic and I/O Pins
VREF+
I
Analog
No
Comparator and A/D Reference Voltage (high) Input
VSS
P
—
No
Ground Reference for Peripheral Digital Logic and I/O
Pins
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 37
PIC24FJ512GU410 Family Data Sheet
Device Overview
...........continued
Pin Name
Pin Type
Buffer Type
PPS
Description
D+
I/O
—
USB Signaling High
D-
I/O
—
USB Signaling Low
USBOEN
I
DIG
USB Output Enable (active-low)
VBUS
I
Analog
VUSB Supply Detect
VUSB3V3
P
—
3.3V VUSB
USBID
I
ST
USB OTG ID Input
Legend: DIG = Digital levels output, ST = Schmitt Trigger input buffer, I2C = I2C/SMBus input buffer, Analog =
Analog level input/output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 38
PIC24FJ512GU410 Family Data Sheet
Guidelines for Getting Started with 16-Bit M...
Basic Connection Requirements
Getting started with the PIC24FJ512GU410 family of 16-bit microcontrollers requires attention to a minimal set of
device pin connections before proceeding with development.
The following pins must always be connected:
•
•
•
•
All VDD, VUSB3V3 and VSS pins (see 2.2 Power Supply Pins)
All AVDD and AVSS pins, regardless of whether or not the analog device features are used
(see 2.2 Power Supply Pins)
MCLR pin (see 2.3 Master Clear (MCLR) Pin)
VCAP pin
(see 2.4 Voltage Regulator Pin (VCAP))
These pins must also be connected if they are being used in the end application:
•
•
PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see 2.5 ICSP
Pins)
OSC1 and OSC2 pins when an external oscillator is used (see 2.6 External Oscillator Pins)
Additionally, the following pins may be required:
•
VREF+ pin used when external voltage reference for analog modules is implemented
Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are
being used.
The minimum mandatory connections are shown in Figure 2-1.
Figure 2-1. Recommended Minimum Connections
C1(2)
C2(2)
VSS
VSS
R1
R2
VDD
VDD
VCAP
MCLR
C8(1)
C7
PIC24FJXXX
VSS
V USB3V3
VDD
VSS
C3(2)
AVSS
C6(2)
AVDD
2.1
Guidelines for Getting Started with 16-Bit MCUs
VDD
2.
C5(2)
Key (all values are recommendations):
C1 through C7: 0.1 µF, 20V ceramic
C8: 10 µF, 6.3V or greater, tantalum or ceramic
R1: 10 k
R2: 100 to 470
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 39
PIC24FJ512GU410 Family Data Sheet
Guidelines for Getting Started with 16-Bit M...
Notes:
1. See 2.4 Voltage Regulator Pin (VCAP) for an explanation of voltage regulator pin connections.
2. The example shown is for a PIC24F device with five VDD/VSS, VUSB3V3/VSS and AVDD/AVSS pin pairs. Other
devices may have more or less pairs; adjust the number of decoupling capacitors appropriately.
3. These pins have an increased current drive strength.
2.2
Power Supply Pins
2.2.1
Decoupling Capacitors
The use of decoupling capacitors on every power supply pin, such as VDD, VUSB3V3 and AVDD, is required.
Consider the following criteria when using decoupling capacitors:
•
•
•
•
2.2.2
Value and type of capacitor: 0.1 μF (100 nF), 25V-50V capacitor is recommended. The capacitor should be a
low-ESR device with a self-resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are
recommended.
Placement on the Printed Circuit Board: The decoupling capacitors should be placed as close to the pins as
possible. It is recommended to place the capacitors on the same side of the board as the device. If space is
constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater than 0.25 inch (6 mm).
Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a
second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second
capacitor can be in the range of 0.01 μF to 0.001 μF. Place this second capacitor next to each primary
decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as
close to the power and ground pins as possible (e.g., 0.1 μF in parallel with 0.001 μF).
Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to
the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first
in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
Bulk Capacitors
On boards with power traces running longer than six inches in length, it is suggested to use a bulk capacitance of
10 µF or greater located near the MCU. The value of the capacitor should be determined based on the trace
resistance that connects the power supply source to the device and the maximum current drawn by the device in the
application. Typical values range from 10 µF to 47 µF.
2.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device functions: device Reset, and device programming and debugging. If
programming and debugging are not required in the end application, a direct connection to VDD may be all that is
required. The addition of other components to help increase the application’s resistance to spurious Resets from
voltage sags may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be
implemented depending on the application’s requirements.
During programming and debugging, the resistance and capacitance that can be added to the pin must be
considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and
VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be
adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be
isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The
jumper is replaced for normal run-time operations.
Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 40
PIC24FJ512GU410 Family Data Sheet
Guidelines for Getting Started with 16-Bit M...
Figure 2-2. Example of MCLR Pin Connections
Notes:
1. R1 ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL
specifications are met.
2. R2 ≤ 470Ω will limit any current flowing into MCLR from the external capacitor, C, in the event of a MCLR pin
breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
Voltage Regulator Pin (VCAP)
A low-ESR (< 5Ω) capacitor is required on the VCAP pin to stabilize the voltage regulator output voltage. The VCAP pin
must not be connected to VDD and must use a capacitor of 10 µF connected to ground. The type can be ceramic or
tantalum. Suitable examples of capacitors are shown in Table 2-1. Capacitors with equivalent specifications can be
used.
Designers may use Figure 2-3 to evaluate the ESR equivalence of candidate devices.
The placement of this capacitor should be close to VCAP. It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to 32. Electrical Characteristics for additional information.
Figure 2-3. Frequency vs. ESR Performance for Suggested VCAP
10
1
ESR ()
2.4
0.1
0.01
0.001
0.01
0.1
1
10
100
Frequency (MHz)
1000 10,000
Note: Typical data measurement at +25°C, 0V DC bias.
Table 2-1. Suitable Capacitor Equivalent (0805 Case Size)
Make
Part #
Nominal Capacitance
Base Tolerance
Rated Voltage
TDK Corporation
C2012X5R1E106K085AC
10 µF
±10%
25V
TDK Corporation
C2012X5R1C106K085AC
10 µF
±10%
16V
KEMET
C0805C106M4PACTU
10 µF
±10%
16V
GRM21BR61E106KA3L
10 µF
±10%
25V
GRM21BR61C106KE15
10 µF
±10%
16V
Murata Electronics
Murata Electronics
®
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 41
PIC24FJ512GU410 Family Data Sheet
Guidelines for Getting Started with 16-Bit M...
2.4.1
Considerations for Ceramic Capacitors
In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost-effective in sizes
up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very
attractive in many types of applications.
Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller. However, some care
is needed in selecting the capacitor to ensure that it maintains sufficient capacitance over the intended operating
range of the application.
Typical low-cost, 10 μF ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also
available, but are less common). The initial tolerance specifications for these types of capacitors are often specified
as ±10% to ±20% (X5R and X7R) or -20%/+80% (Y5V). However, the effective capacitance that these capacitors
provide in an application circuit will also vary based on additional factors, such as the applied DC bias voltage and
the temperature. The total in-circuit tolerance is, therefore, much wider than the initial tolerance specification.
The X5R and X7R capacitors typically exhibit satisfactory temperature stability (ex: ±15% over a wide temperature
range, but consult the manufacturer’s data sheets for exact specifications). However, Y5V capacitors typically have
extreme temperature tolerance specifications of +22%/-82%. Due to the extreme temperature tolerance, a 10 μF
nominal rated Y5V type capacitor may not deliver enough total capacitance to meet minimum internal voltage
regulator stability and transient response requirements. Therefore, Y5V capacitors are not recommended for use with
the internal regulator if the application must operate over a wide temperature range.
In addition to temperature tolerance, the effective capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage applied to the capacitor. This effect can be very significant, but is
often overlooked or is not always documented.
A typical DC bias voltage vs. capacitance graph for X7R type capacitors is shown in Figure 2-4.
Figure 2-4. DC Bias Voltage vs. Capacitance Characteristics
When selecting a ceramic capacitor to be used with the internal voltage regulator, it is suggested to select a highvoltage rating so that the operating voltage is a small percentage of the maximum rated capacitor voltage. For
example, choose a ceramic capacitor rated at a minimum of 16V for the 1.8V core voltage. Suggested capacitors are
shown in Table 2-1.
2.5
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is
recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as
possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the
value in the range of a few tens of ohms, not to exceed 100Ω.
Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will
interfere with the programmer/debugger communications to the device. If such discrete components are an
application requirement, they should be removed from the circuit during programming and debugging.
For device emulation, ensure that the “Communication Channel Select” pins (i.e., PGECx/PGEDx) programmed into
the device match the physical connections for the ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip development tool connection requirements, refer to 30. Development
Support.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 42
PIC24FJ512GU410 Family Data Sheet
Guidelines for Getting Started with 16-Bit M...
2.6
External Oscillator Pins
Many microcontrollers have options for at least two oscillators: a high-frequency Primary Oscillator and a lowfrequency Secondary Oscillator (refer to 9. Oscillator Configuration for details).
The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to
the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The
load capacitors should be placed next to the oscillator itself, on the same side of the board.
Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper
pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground
pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed.
Layout suggestions are shown in Figure 2-5. In-line packages may be handled with a single-sided layout that
completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely
surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer.
In all cases, the guard trace(s) must be returned to ground.
In planning the application’s routing and I/O assignments, ensure that adjacent port pins, and other signals in close
proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times and other similar noise).
For additional information and design guidance on oscillator circuits, please refer to these Microchip Application
Notes, available at the corporate website (www.microchip.com):
•
•
•
AN943, “Practical PICmicro® Oscillator Analysis and Design”
AN949, “Making Your Oscillator Work”
AN1798, “Crystal Selection for Low-Power
Secondary Oscillator”
Figure 2-5. Suggested Placement of the Oscillator Circuit
Fine-Pitch (Dual-Sided) Layouts:
Single-Sided and In-Line Layouts:
Copper Pour
(tied to ground)
Top Layer Copper Pour
(tied to ground)
Primary Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
C1
Bottom Layer
Copper Pour
(tied to ground)
`
OSCO
GND
C2
OSCO
OSCI
`
C2
Oscillator
Crystal
GND
C1
SOSCO
Secondary
Oscillator
Crystal
Sec Oscillator: C1
SOSC I
OSCI
`
Sec Oscillator: C2
DEVICE PINS
2.7
Unused I/Os
Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ to
10 kΩ resistor to VSS on unused pins.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 43
PIC24FJ512GU410 Family Data Sheet
CPU
3.
CPU
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information on the CPU, refer to “CPU with Extended Data Space
(EDS)” (www.microchip.com/DS39732) in the“dsPIC33/PIC24 Family Reference Manual”. The information in this
data sheet supersedes the information in the FRM.
The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit
instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to
4M instructions of user program memory space. A single-cycle instruction prefetch mechanism is used to help
maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception
of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions.
Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any
point.
PIC24F devices have sixteen, 16-bit Working registers in the programmer’s model. Each of the Working registers can
act as a Data, Address or Address Offset register. The 16th Working register (W15) operates as a Software Stack
Pointer (SSP) for interrupts and calls.
The lower 32 Kbytes of the Data Space (DS) can be accessed linearly. The upper 32 Kbytes of the Data Space are
referred to as Extended Data Space (EDS), to which the extended data RAM or program memory can be mapped.
The core supports Inherent (no operand), Relative, Literal and Memory Direct Addressing modes, along with three
groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group
offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon
their functional requirements.
For most instructions, the core is capable of executing a data (or program data) memory read, a Working register
(data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three
parameter instructions can be supported, allowing trinary operations (for example, A + B = C) to be executed in a
single cycle.
A high-speed, 17-bit x 17-bit multiplier has been included to significantly enhance the core arithmetic capability and
throughput. The multiplier supports Signed, Unsigned and Mixed mode, 16-bit x 16-bit or 8-bit x 8-bit, integer
multiplication. All multiply instructions execute in a single cycle.
The 16-bit ALU has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide
algorithm. It operates in conjunction with the REPEAT instruction looping mechanism and a selection of iterative divide
instructions to support 32-bit (or 16-bit), divided by 16-bit, integer signed and unsigned division. All divide operations
require 19 cycles to complete but are interruptible at any cycle boundary.
The PIC24F has a vectored exception scheme with up to eight sources of non-maskable traps and up to 118 interrupt
sources. Each interrupt source can be assigned to one of seven priority levels.
A block diagram of the CPU is shown in Figure 3-1.
3.1
Programmer’s Model
The programmer’s model for the PIC24F is shown in Figure 3-2. All registers in the programmer’s model are
memory-mapped and can be manipulated directly by instructions.
A description of each register is provided in Table 3-1. All registers associated with the programmer’s model are
memory-mapped.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 44
PIC24FJ512GU410 Family Data Sheet
CPU
Figure 3-1. PIC24F CPU Core Block Diagram
Table 3-1. CPU Core Registers
Register(s) Name
Description
W0 through W15
Working Register Array
PC
23-Bit Program Counter
SR
ALU STATUS Register
SPLIM
Stack Pointer Limit Value Register
TBLPAG
Table Memory Page Address Register
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 45
PIC24FJ512GU410 Family Data Sheet
CPU
...........continued
Register(s) Name
Description
RCOUNT
REPEAT Loop Counter Register
CORCON
CPU Control Register
DISICNT
Disable Interrupt Count Register
DSRPAG
Data Space Read Page Register
DSWPAG
Data Space Write Page Register
Figure 3-2. Programmer’s Model
15
Divider Working Registers
0
W0 (WREG)
W1
W2
Multiplier Registers
W3
W4
W5
W6
W7
Working/Address
Registers
W8
W9
W10
W11
W12
W13
W14
Frame Pointer
W15
Stack Pointer
0
SPLIM
0
22
0
0
PC
7
0
TBLPAG
9
Program Counter
Table Memory Page
Address Register
0
Data Space Read Page Register
DSRPAG
8
0
Data Space Write Page Register
DSWPAG
15
0
RCOUNT
15
Stack Pointer Limit
Value Register
SRH
SRL
0
— — — — — — — DC 2 IPL
1 0 RA N OV Z C
0
15
— — — — — — — — — — — — IPL3 — — —
13
REPEAT Loop Counter
Register
ALU STATUS Register (SR)
CPU Control Register (CORCON)
0
DISICNT
Disable Interrupt Count Register
Registers or bits are shadowed for PUSH.S and POP.S instructions.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 46
PIC24FJ512GU410 Family Data Sheet
CPU
3.2
Arithmetic Logic Unit (ALU)
The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are two’s complement in nature. Depending on the operation, the ALU
may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the
SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction
operations.
The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the
ALU operation can come from the W register array, or data memory, depending on the addressing mode of the
instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location.
The PIC24F CPU incorporates hardware support for both multiplication and division. This includes a dedicated
hardware multiplier and support hardware for 16-bit divisor division.
3.2.1
Multiplier
The ALU contains a high-speed, 17-bit x 17-bit multiplier. It supports unsigned, signed or mixed sign operation in
several multiplication modes:
•
•
•
•
•
•
•
3.2.2
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
Divider
The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the
following data sizes:
•
•
•
•
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0 and the remainder in W1. The 16-bit signed and unsigned DIV
instructions can specify any W register for both the 16-bit divisor (Wn), and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit
and 16-bit/16-bit instructions take the same number of cycles to execute.
3.2.3
Multibit Shift Support
The PIC24F ALU supports both single bit and single-cycle, multibit arithmetic and logic shifts. Multibit shifts are
implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift,
in a single cycle. All multibit shift instructions only support Register Direct Addressing for both the operand source
and result destination.
A full summary of instructions that use the shift operation is provided in Table 3-2.
Table 3-2. Instructions that Use the Single Bit and Multibit Shift Operation
Instruction
Description
ASR
Arithmetic Shift Right source register by one or more bits.
SL
Shift Left source register by one or more bits.
LSR
Logical Shift Right source register by one or more bits.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 47
PIC24FJ512GU410 Family Data Sheet
CPU
3.3
CPU Registers
Offset
Name
0x00
WREG0
0x02
WREG1
0x04
WREG2
0x06
WREG3
0x08
WREG4
0x0A
WREG5
0x0C
WREG6
0x0E
WREG7
0x10
WREG8
0x12
WREG9
0x14
WREG10
0x16
WREG11
0x18
WREG12
0x1A
WREG13
0x1C
WREG14
0x1E
WREG15
0x20
SPLIM
0x22
...
0x2D
Reserved
0x2E
PCL
0x30
PCH
0x32
DSRPAG
0x33
DSWPAG
0x35
Reserved
0x36
RCOUNT
0x38
...
0x41
Reserved
0x42
SR
0x44
CORCON
Bit Pos.
7
6
5
4
3
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
WREG0[7:0]
WREG0[15:8]
WREG1[7:0]
WREG1[15:8]
WREG2[7:0]
WREG2[15:8]
WREG3[7:0]
WREG3[15:8]
WREG4[7:0]
WREG4[15:8]
WREG5[7:0]
WREG5[15:8]
WREG6[7:0]
WREG6[15:8]
WREG7[7:0]
WREG7[15:8]
WREG8[7:0]
WREG8[15:8]
WREG9[7:0]
WREG9[15:8]
WREG10[7:0]
WREG10[15:8]
WREG11[7:0]
WREG11[15:8]
WREG12[7:0]
WREG12[15:8]
WREG13[7:0]
WREG13[15:8]
WREG14[7:0]
WREG14[15:8]
WREG15[7:0]
WREG15[15:8]
SPLIM[7:0]
SPLIM[15:8]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
PCL[7:0]
PCL[15:8]
PCH[7:0]
© 2019-2020 Microchip Technology Inc.
1
0
DSRPAG[7:0]
DSRPAG[9:8]
DSWPAG[7:0]
DSWPAG[8]
7:0
15:8
7:0
15:8
7:0
15:8
2
RCOUNT[7:0]
RCOUNT[15:8]
IPL[2:0]
RA
Datasheet
N
OV
IPL3
PSV
Z
C
DC
DS30010203C-page 48
PIC24FJ512GU410 Family Data Sheet
CPU
...........continued
Offset
Name
0x46
...
0x51
Reserved
0x52
DISICNT
0x52
TBLPAG
Bit Pos.
7
7:0
15:8
7:0
15:8
© 2019-2020 Microchip Technology Inc.
6
5
4
3
2
1
0
DISICNT[7:0]
DISICNT[13:8]
TBLPAG[7:0]
Datasheet
DS30010203C-page 49
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.1
Working Register 0
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
WREG0
0x00
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG0[15:8]
R/W
R/W
0
0
4
3
WREG0[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG0[15:0] Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 50
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.2
Working Register 1
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
WREG1
0x02
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG1[15:8]
R/W
R/W
0
0
4
3
WREG1[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG1[15:0] Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 51
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.3
Working Register 2
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
WREG2
0x04
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG2[15:8]
R/W
R/W
0
0
4
3
WREG2[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG2[15:0] Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 52
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.4
Working Register 3
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
WREG3
0x06
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG3[15:8]
R/W
R/W
0
0
4
3
WREG3[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG3[15:0] Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 53
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.5
Working Register 4
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
WREG4
0x08
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG4[15:8]
R/W
R/W
0
0
4
3
WREG4[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG4[15:0] Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 54
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.6
Working Register 5
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
WREG5
0x0A
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG5[15:8]
R/W
R/W
0
0
4
3
WREG5[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG5[15:0] Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 55
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.7
Working Register 6
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
WREG6
0x0C
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG6[15:8]
R/W
R/W
0
0
4
3
WREG6[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG6[15:0] Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 56
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.8
Working Register 7
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
WREG7
0x0E
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG7[15:8]
R/W
R/W
0
0
4
3
WREG7[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG7[15:0] Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 57
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.9
Working Register 8
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
WREG8
0x10
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG8[15:8]
R/W
R/W
0
0
4
3
WREG8[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG8[15:0] Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 58
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.10
Working Register 9
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
WREG9
0x12
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG9[15:8]
R/W
R/W
0
0
4
3
WREG9[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG9[15:0] Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 59
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.11
Working Register 10
Bit
Access
Reset
Bit
Access
Reset
Name:
Offset:
WREG10
0x14
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG10[15:8]
R/W
R/W
0
0
4
3
WREG10[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG10[15:0] Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 60
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.12
Working Register 11
Bit
Access
Reset
Bit
Access
Reset
Name:
Offset:
WREG11
0x16
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG11[15:8]
R/W
R/W
0
0
4
3
WREG11[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG11[15:0] Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 61
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.13
Working Register 12
Bit
Access
Reset
Bit
Access
Reset
Name:
Offset:
WREG12
0x18
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG12[15:8]
R/W
R/W
0
0
4
3
WREG12[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG12[15:0] Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 62
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.14
Working Register 13
Bit
Access
Reset
Bit
Access
Reset
Name:
Offset:
WREG13
0x1A
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG13[15:8]
R/W
R/W
0
0
4
3
WREG13[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG13[15:0] Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 63
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.15
Working Register 14
Bit
Access
Reset
Bit
Access
Reset
Name:
Offset:
WREG14
0x1C
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG14[15:8]
R/W
R/W
0
0
4
3
WREG14[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG14[15:0] Data or Frame Pointer bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 64
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.16
Working Register 15
Bit
Access
Reset
Bit
Access
Reset
Name:
Offset:
WREG15
0x1E
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
WREG15[15:8]
R/W
R/W
0
0
4
3
WREG15[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WREG15[15:0] Data or Stack Pointer bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 65
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.17
Stack Pointer Limit Value Register
Name:
Offset:
Bit
Access
Reset
Bit
SPLIM
0x20
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
SPLIM[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
SPLIM[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – SPLIM[15:0] Stack Limit Address bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 66
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.18
Program Counter Low Register
Name:
Offset:
Bit
15
PCL
0x2E
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PCL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PCL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PCL[15:0] Program Counter Low Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 67
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.19
Program Counter High Register
Name:
Offset:
Bit
PCH
0x30
15
14
13
12
7
6
5
4
11
10
9
8
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
PCH[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – PCH[7:0] Program Counter High Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 68
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.20
Data Space Read Page Register
Bit
Name:
Offset:
DSRPAG
0x32
15
14
13
12
7
6
5
4
R/W
0
R/W
0
R/W
0
11
10
Access
Reset
Bit
Access
Reset
3
DSRPAG[7:0]
R/W
R/W
0
0
9
8
DSRPAG[9:8]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – DSRPAG[9:0] Data Space Read Page Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 69
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.21
Data Space Write Page Register
Name:
Offset:
Bit
DSWPAG
0x33
15
14
13
12
7
6
5
4
R/W
0
R/W
0
R/W
0
11
10
9
8
DSWPAG[8]
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
3
DSWPAG[7:0]
R/W
R/W
0
0
Bits 8:0 – DSWPAG[8:0] Data Space Write Page Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 70
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.22
REPEAT Loop Counter Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
RCOUNT
0x36
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
RCOUNT[15:8]
R/W
R/W
0
0
4
3
RCOUNT[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – RCOUNT[15:0] Current Loop Counter Value for REPEAT Instruction bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 71
PIC24FJ512GU410 Family Data Sheet
CPU
3.3.23
ALU STATUS Register
Name:
Offset:
SR
0x42
Notes:
1. The IPLx Status bits are read-only when NSTDIS (INTCON1[15]) = 1.
2.
Bit
The IPLx Status bits are concatenated with the IPL3 Status bit (CORCON[3]) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
15
14
13
12
11
10
9
8
DC
R/W
0
7
6
IPL[2:0]
R/W
0
5
4
RA
R/W
0
3
N
R/W
0
2
OV
R/W
0
1
Z
R/W
0
0
C
R/W
0
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
Bit 8 – DC ALU Half Carry/Borrow bit
Value
Description
1
A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of
the result occurred
0
No carry-out from the 4th or 8th low-order bit of the result has occurred
Bits 7:5 – IPL[2:0] CPU Interrupt Priority Level Status bits(1,2)
Value
Description
111
CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110
SDOx pin is controlled by the module
101
CPU Interrupt Priority Level is 5 (13)
100
CPU Interrupt Priority Level is 4 (12)
011
CPU Interrupt Priority Level is 3 (11)
010
CPU Interrupt Priority Level is 2 (10)
001
CPU Interrupt Priority Level is 1 (9)
000
CPU Interrupt Priority Level is 0 (8)
Bit 4 – RA REPEAT Loop Active bit
Value
Description
1
REPEAT loop is in progress
0
REPEAT loop is not in progress
Bit 3 – N ALU Negative bit
Value
Description
1
Result was negative
0
Result was not negative (zero or positive)
Bit 2 – OV ALU Overflow bit
Value
Description
1
Overflow occurred for signed (two’s complement) arithmetic in this arithmetic operation
0
No overflow has occurred
Bit 1 – Z ALU Zero bit
Value
Description
1
An operation, which affects the Z bit, has set it at some time in the past
0
The most recent operation, which affects the Z bit, has cleared it (i.e., a non-zero result)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 72
PIC24FJ512GU410 Family Data Sheet
CPU
Bit 0 – C ALU Carry/Borrow bit
Value
Description
1
A carry-out from the Most Significant bit (MSb) of the result occurred
0
No carry-out from the Most Significant bit of the result occurred
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PIC24FJ512GU410 Family Data Sheet
CPU
3.3.24
CPU Core Control Register
Name:
Offset:
CORCON
0x44
Notes:
1. The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level; see
3.3.23 SR for bit description.
2. If PSV = 0, any reads from data memory at 0x8000 and above will cause an address trap error instead of
reading from the PSV section of program memory. This bit is not individually addressable.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
IPL3
R/W
0
2
PSV
R/W
0
1
0
Access
Reset
Bit
Access
Reset
Bit 3 – IPL3 CPU Interrupt Priority Level Status bit(1)
Value
Description
1
CPU Interrupt Priority Level is greater than 7
0
CPU Interrupt Priority Level is 7 or less
Bit 2 – PSV Program Space Visibility (PSV) in Data Space Enable(2)
Value
Description
1
Program space is visible in Data Space
0
Program space is not visible in Data Space
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PIC24FJ512GU410 Family Data Sheet
CPU
3.3.25
Disable Interrupt Count Register
Bit
Name:
Offset:
DISICNT
0x52
15
14
Access
Reset
Bit
Access
Reset
13
12
R/W
0
R/W
0
4
7
6
5
R/W
0
R/W
0
R/W
0
11
10
DISICNT[13:8]
R/W
R/W
0
0
3
DISICNT[7:0]
R/W
R/W
0
0
9
8
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 13:0 – DISICNT[13:0] Current Counter Value for DISI Instruction bits
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PIC24FJ512GU410 Family Data Sheet
CPU
3.3.26
Table Memory Page Address Register
Bit
Name:
Offset:
TBLPAG
0x52
15
14
13
12
7
6
5
4
R/W
0
R/W
0
R/W
0
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
3
TBLPAG[7:0]
R/W
R/W
0
0
Bits 7:0 – TBLPAG[7:0] Table Memory Page Value bits
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Program Memory
4.
Program Memory
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information, refer to “PIC24F Flash Program Memory”
(www.microchip.com/DS30009715) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data
sheet supersedes the information in the FRM.
As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory spaces and
buses. This architecture also allows direct access of program memory from the Data Space during code execution.
The program memory is readable, writable and erasable. The Flash memory can be programmed in four ways:
•
•
•
•
In-Circuit Serial Programming™ (ICSP™)
Run-Time Self-Programming (RTSP)
JTAG
Enhanced In-Circuit Serial Programming (Enhanced ICSP)
ICSP allows a PIC24FJ512GU410 family device to be serially programmed while in the end application circuit. This is
simply done with two lines for the programming clock and programming data (named PGECx and PGEDx,
respectively), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to
manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the
product. This also allows the most recent firmware or a custom firmware to be programmed.
RTSP is accomplished using TBLRD (Table Read) and TBLWT (Table Write) instructions. With RTSP, the user may
write program memory data in blocks of 128 instructions (384 bytes) at a time and erase program memory in blocks
of 1024 instructions (3072 bytes) at a time.
The device implements a 7-bit Error Correcting Code (ECC). The NVM block contains a logic to write and read ECC
bits to and from the Flash memory. The Flash is programmed at the same time as the corresponding ECC parity bits.
The ECC provides improved resistance to Flash errors. ECC single bit errors can be transparently corrected; ECC
double-bit errors generate an interrupt.
The program address memory space of the PIC24FJ512GU410 family devices is 4M instructions. The space is
addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during program execution, or from
table operation or Data Space remapping, as described in 5.5 Interfacing Program and Data Memory Spaces.
User access to the program memory space is restricted to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG[7] to permit access to the
Configuration bits and customer OTP sections of the configuration memory space.
The memory map for the PIC24FJ512GU410 family of devices is shown in Figure 4-1.
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PIC24FJ64GP205/GU205
PIC24FJ512GU410
Family DataFamily
Sheet
Program Memory
Memory
Program
Figure 4-1. Program
4-1. Program Memory
Memory Map
Map for
for PIC24FJ512GU410
PIC24FJ64GP205/GU205
Devices
Figure
FamilyFamily
Devices
See the Code Memory
details in Figure 4-2
and Figure 4-3
0x801024
0x80102C
Note: Memory areas are not shown to scale.
©2019-2020
2020 Microchip
Technology
Inc. Inc.
©
Microchip
Technology
Draft Advance
Information Datasheet
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66
DS30010203C-page
PIC24FJ512GU410 Family Data Sheet
Program Memory
Figure 4-2. Code Memory Map for Devices with 512 Kbytes Flash (PIC24FJ512GX4XX)
0x02AF00
0x02B000
0x055F00
0x056000
0x42AF00
0x42B000
0x800000
0x800000
Note: Memory areas are not shown to scale
Figure 4-3. Code Memory Map for Devices with 256 Kbytes Flash (PIC24FJ256GX4XX)
0x000000
0x000000
0x015700
0X015800
0x02AF00
0x02B000
0x415700
0x415800
0x800000
0x800000
Note: Memory areas are not shown to scale
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PIC24FJ512GU410 Family Data Sheet
Program Memory
Figure 4-4. Code Memory Map for Devices with 128 Kbytes Flash (PIC24FJ128GX4XX)
0x000000
0x000000
0x00AF00
0x00B000
0x015F00
0x016000
0x40AF00
0x40B000
0x800000
0x800000
4.1
Program Memory Organization
The program memory is organized as an array of 24-bit wide words. Although the program memory space is treated
as 24 bits wide (3 bytes per instruction), the upper byte is not addressable. Only the lower 2 bytes of the words
(instructions) have addresses. The entire 24-bits of the instruction words are read and decoded by the MCU. Also,
the upper byte can be accessed from the application code using special table instructions (TBLRD and TBLWT).
The program memory array is organized into write blocks (rows) of 128 words (instructions). Eight write blocks form
an erase block (page) of 1024 instructions. The program memory can be programmed one row (write block) at a time
and can be erased by one page (erase block) at a time. Also, the double-word programming (two instructions) and
entire code memory erase operations are supported.
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PIC24FJ512GU410 Family Data Sheet
Program Memory
4.2
Hard Memory Vectors
All PIC24F devices reserve the addresses between 000000h and 000200h for hard-coded program execution
vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on a device
Reset to the actual start of code. A GOTO instruction is programmed by the user at 000000h, with the actual address
for the start of code at 000002h.
The PIC24FJ512GU410 devices can have up to two Interrupt Vector Tables (IVT). The first is located from
addresses, 000004h to 0000FFh. The Alternate Interrupt Vector Table (AIVT) can be enabled by the AIVTDIS
Configuration bit if the Boot Segment (BS) is present. If the user has configured a Boot Segment, the AIVT will be
located at the address, (BSLIM[12:0] – 1) x 800h. These vector tables allow each of the many device interrupt
sources to be handled by separate ISRs. A more detailed discussion of the Interrupt Vector Tables is provided in 8.1
Interrupt Vector Table.
4.3
Configuration Bits Overview
The Configuration bits are stored in the last page location of implemented program memory. These bits can be set or
cleared to select various device configurations. There are two types of Configuration bits: system operation bits and
code-protect bits. The system operation bits determine the power-on settings for system-level components, such as
the oscillator and the Watchdog Timer. The code-protect bits prevent program memory from being read and written.
Refer to 29. Special Features for the full Configuration register description for each specific device.
4.4
Code-Protect Configuration Bits
The device implements intermediate security features defined by the FSEC register. The Boot Segment (BS) is the
higher privileged segment and the General Segment (GS) is the lower privileged segment. The total user code
memory can be split into BS or GS. The size of the segments is determined by the BSLIM[12:0] bits. The relative
location of the segments within user space does not change, such that BS (if present) occupies the memory area just
after the Interrupt Vector Table (IVT) and the GS occupies the space just after the BS (or if the Alternate IVT is
enabled, just after it).
The Configuration Segment (CS) is a small segment (less than a page, typically just one row) within user Flash
address space. It contains all user configuration data that are loaded by the NVM Controller during the Reset
sequence.
4.5
Table Instructions and Flash Programming
Regardless of the method used, all programming of Flash memory is done with the Table Read and Table Write
instructions. These allow direct read and write access to the program memory space from the data memory while the
device is in normal operating mode. The 24-bit target address in the program memory is formed using the
TBLPAG[7:0] bits and the Effective Address (EA) from a W register, specified in the table instruction, as shown in
Figure 4-5.
The TBLRDL and the TBLWTL instructions are used to read or write to bits[15:0] of program memory. TBLRDL and
TBLWTL can access program memory in both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read or write to bits[23:16] of program memory. TBLRDH and
TBLWTH can also access program memory in Word or Byte mode.
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PIC24FJ512GU410 Family Data Sheet
Program Memory
Figure 4-5. Addressing for Table Registers
4.6
RTSP Operation
The PIC24F Flash program memory array is organized into rows of 128 instructions or 384 bytes. RTSP allows the
user to erase blocks of eight rows (1024 instructions) at a time and to program one row at a time. It is also possible to
program two instruction word blocks.
The eight-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on
boundaries of 3072 bytes and 384 bytes, respectively.
When data are written to program memory using TBLWT instructions, the data are not written directly to memory.
Instead, data written using Table Writes are stored in holding latches until the programming sequence is executed.
Any number of TBLWT instructions can be executed and a write will be successfully performed. However, 128 TBLWT
instructions are required to write the full row of memory.
To ensure that no data are corrupted during a write, any unused address should be programmed with FFFFFFh. This
is because the holding latches reset to an unknown state, so if the addresses are left in the Reset state, they may
overwrite the locations on rows which were not rewritten.
The basic sequence for RTSP programming is to set the Table Pointer to point to the programming latches, do a
series of TBLWT instructions to load the buffers and set the NVMADRU/NVMADR registers to point to the destination.
Programming is performed by setting the control bits in the NVMCON register.
Data can be loaded in any order and the holding registers can be written to multiple times before performing a write
operation. Subsequent writes, however, will wipe out any previous writes.
Note: Writing to a location multiple times without erasing is not allowed.
All of the Table Write operations are single-word writes (two instruction cycles), because only the buffers are written.
A programming cycle is required for programming each row.
4.6.1
Programming Operations
A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode.
During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR
bit (NVMCON[15]) starts the operation and the WR bit is automatically cleared when the operation is finished.
4.6.2
Programming Algorithm for Flash Program Memory
The user can program one row of Flash program memory at a time. To do this, it is necessary to erase the eight-row
erase block containing the desired row. The general process is:
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PIC24FJ512GU410 Family Data Sheet
Program Memory
1.
2.
3.
4.
5.
6.
Read eight rows of program memory (1024 instructions) and store in data RAM.
Update the program data in RAM with the desired new data.
Erase the block (see Example 4-1):
3.1.
Set the NVMOP[3:0] bits (NVMCON[3:0]) to ‘0011’ to configure for block erase. Set the WREN
(NVMCON[14]) bit.
3.2.
Write the starting address of the block to be erased into the NVMADRU/NVMADR registers.
3.3.
Write 55h to NVMKEY.
3.4.
Write AAh to NVMKEY.
3.5.
Set the WR bit (NVMCON[15]). The erase cycle begins and the CPU stalls for the duration of the
erase cycle. When the erase is done, the WR bit is cleared automatically.
Update the TBLPAG register to point to the programming latches on the device. Update the NVMADRU/
NVMADR registers to point to the destination in the program memory.
Write the first 128 instructions from data RAM into the program memory buffers (see Example 4-2).
Write the program block to Flash memory:
6.1.
Set the NVMOPx bits to ‘0010’ to configure for row programming. Set the WREN bit.
6.2.
6.3.
6.4.
7.
Write 55h to NVMKEY.
Write AAh to NVMKEY.
Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle.
When the write to Flash memory is done, the WR bit is cleared automatically.
Repeat Steps 4 through 6, using the next available 128 instructions from the block in data RAM, by
incrementing the value in NVMADRU/NVMADR until all 1024 instructions are written back to Flash memory.
For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any
erase or program operation to proceed. After the programming command has been executed, the user must wait for
the programming time until programming is complete. The two instructions following the start of the programming
sequence should be NOPs.
Table 4-1. Page Erase
Step 1: Set the NVMCON register to erase a page.
MOV #0x4003, W0
MOV W0, NVMCON
Step 2: Load the address of the page to be erased into the NVMADR register pair.
MOV #PAGE_ADDR_LO, W0
MOV W0, NVMADR
MOV #PAGE_ADDR_HI, W0
MOV W0, NVMADRU
Step 3: Set the WR bit.
MOV #0x55, W0
MOV W0, NVMKEY
MOV #0xAA, W0
MOV W0, NVMKEY
BSET NVMCON, #WR
NOP
NOP
NOP
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PIC24FJ512GU410 Family Data Sheet
Program Memory
Example 4-1. Erasing a Program Memory Block (‘C’ Language Code)
// C example using MPLAB XC16
unsigned long progAddr = 0xXXXXXX; // Address of row to write
unsigned int offset;
//Set up pointer to the first memory location to be written
NVMADRU = progAddr>>16;
// Initialize PM Page Boundary SFR
NVMADR = progAddr & 0xFFFF;
// Initialize lower word of address
NVMCON = 0x4003;
// Initialize NVMCON
asm(“DISI #5”);
// Block all interrupts with priority 16;
// Initialize PM Page Boundary SFR
NVMADR = progAddr & 0xFFFF;
// Initialize lower word of address
//Perform TBLWT instructions to write latches
__builtin_tblwtl(0, progData1L);
// Write word 1 to address low word
__builtin_tblwth(0, progData2H);
// Write word 1 to upper byte
__builtin_tblwtl(1, progData2L);
// Write word 2 to address low word
__builtin_tblwth(1, progData2H);
// Write word 2 to upper byte
asm(“DISI #5”);
// Block interrupts with priority W0
; W0 has '1' for each bit set in IOCFx
; IOCFx & W0 ->IOCFx
Example 11-2. Port Read/Write in Assembly
MOV 0xFF00, W0
MOV W0, TRISB
NOP
BTSS PORTB, #13
;
;
;
;
Configure PORTB[15:8] as inputs
and PORTB[7:0] as outputs
Delay 1 cycle
Next Instruction
Example 11-3. Port Read/Write in ‘C’
TRISB = 0xFF00;
// Configure PORTB[15:8] as inputs and PORTB[7:0] as
outputs
Nop();
// Delay 1 cycle
If (PORTBbits.RB13){ }; // Next Instruction
11.4
Peripheral Pin Select (PPS)
A major challenge in general purpose devices is providing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. In an application that needs to use more than one peripheral
multiplexed on a single pin, inconvenient work arounds in application code, or a complete redesign may be the only
option.
The Peripheral Pin Select (PPS) feature provides an alternative to these choices by enabling the user’s peripheral set
selection and its placement on a wide range of I/O pins. By increasing the pinout options available on a particular
device, users can better tailor the microcontroller to their entire application, rather than trimming the application to fit
the device.
The Peripheral Pin Select feature operates over a fixed subset of digital I/O pins. Users may independently map the
input and/or output of any one of many digital peripherals to any one of these I/O pins. PPS is performed in software
and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent
accidental or spurious changes to the peripheral mapping once it has been established.
11.4.1
Available Pins
The number of available pins is dependent on the particular device and its pin count. Pins that support the Peripheral
Pin Select feature include the designation, “RPn” or “RPIn”, in their full pin designation, where “n” is the remappable
pin number. “RP” is used to designate pins that support both remappable input and output functions, while “RPI”
indicates pins that support remappable input functions only.
11.4.2
Available Peripherals and Peripheral Pin Select Function Priority
The peripherals managed by the PPS are all digital only peripherals. These include general serial communications
(UART and SPI), general purpose timer clock inputs, timer related peripherals (input capture and output compare)
and external interrupt inputs. Also included are the outputs of the comparator module, since these are discrete digital
signals.
PPS is not available for these peripherals:
•
•
•
I2C (input and output)
Input Change Notifications
Analog (inputs and outputs)
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PIC24FJ512GU410 Family Data Sheet
I/O Ports
•
INT0
A key difference between pin select and non-pin select peripherals is that pin select peripherals are not associated
with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast,
non-pin select peripherals are always available on a default pin, assuming that the peripheral is active and not
conflicting with another peripheral.
Pin-selectable peripheral outputs (e.g., output compare, UART transmit) will take priority over general purpose digital
functions on a pin, such as port I/Os. Specialized digital outputs will take priority over PPS outputs on the same pin.
The pin diagrams list peripheral outputs in the order of priority. Refer to them for priority concerns on a particular pin.
Unlike PIC24F devices with fixed peripherals, pin-selectable peripheral inputs will never take ownership of a pin. The
pin’s output buffer will be controlled by the TRISx setting or by a fixed peripheral on the pin. If the pin is configured in
Digital mode, then the PPS input will operate correctly. If an analog function is enabled on the pin, the PPS input will
be disabled.
11.4.3
Controlling Peripheral Pin Select
PPS features are controlled through two sets of Special Function Registers (SFRs): one to map peripheral inputs and
one to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the
peripheral has both) can be placed on any selectable function pin without constraint.
The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on if an
input or an output is being mapped.
11.4.3.1 Input Mapping
The inputs of the Peripheral Pin Select options are mapped on the basis of the peripheral; that is, a control register
associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure
peripheral input mapping (see 11.5 I/O Port and Peripheral Pin Select Registers).
Each register contains one or two sets of 6-bit fields, with each set associated with one of the pin-selectable
peripherals. Programming a given peripheral’s bit field with an appropriate 6-bit value maps the RPn/RPIn pin with
that value to that peripheral. For any given device, the valid range of values for any of the bit fields corresponds to the
maximum number of Peripheral Pin Selections supported by the device.
Table 11-2. Selectable Input Sources (Maps Input to Function)
Input Name
Function Name
Register
Function Mapping Bits
External Interrupt 1
INT1
RPINR0[13:8]
INT1R[5:0]
External Interrupt 2
INT2
RPINR1[5:0]
INT2R[5:0]
External Interrupt 3
INT3
RPINR1[13:8]
INT3R[5:0]
External Interrupt 4
INT4
RPINR2[5:0]
INT4R[5:0]
Timer2 External Clock
T2CK
RPINR3[5:0]
T2CKR[5:0]
Timer3 External Clock
T3CK
RPINR3[13:8]
T3CKR[5:0]
Timer4 External Clock
T4CK
RPINR4[5:0]
T4CKR[5:0]
Timer5 External Clock
T5CK
RPINR4[13:8]
T5CKR[5:0]
MCCP1 Input Capture
ICM1
RPINR5[5:0]
ICM1R[5:0]
MCCP2 Input Capture
ICM2
RPINR5[13:8]
ICM2R[5:0]
MCCP3 Input Capture
ICM3
RPINR6[5:0]
ICM3R[5:0]
MCCP4 Input Capture
ICM4
RPINR6[13:8]
ICM4R[5:0]
Output Compare Fault A
OCFA
RPINR11[5:0]
OCFAR[5:0]
Output Compare Fault B
OCFB
RPINR11[13:8]
OCFBR[5:0]
MCCP Clock Input A
TCKIA
RPINR12[5:0]
TCKIAR[5:0]
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PIC24FJ512GU410 Family Data Sheet
I/O Ports
...........continued
Input Name
Function Name
Register
Function Mapping Bits
MCCP Clock Input B
TCKIB
RPINR12[13:8]
TCKIBR[5:0]
Reference Clock Input
REFI
RPINR13[5:0]
REFIR[5:0]
Tamper Detect
TMPRN
RPINR13[13:8]
TMPRNR[5:0]
MCCP5 Input Capture
ICM5
RPINR14[5:0]
ICM5R[5:0]
MCCP6 Input Capture
ICM6
RPINR14[15:8]
ICM6R[5:0]
MCCP7 Input Capture
ICM7
RPINR15[7:0]
ICM7R[5:0]
MCCP8 Input Capture
ICM8
RPINR15[15:8]
ICM8R[5:0]
UART3 Receive
U3RX
RPINR17[13:8]
U3RXR[5:0]
UART1 Receive
U1RX
RPINR18[5:0]
U1RXR[5:0]
UART1 Clear-to-Send
U1CTS
RPINR18[13:8]
U1CTSR[5:0]
UART2 Receive
U2RX
RPINR19[5:0]
U2RXR[5:0]
UART2 Clear-to-Send
U2CTS
RPINR19[13:8]
U2CTSR[5:0]
SPI1 Data
SDI1
RPINR20[5:0]
SDI1R[5:0]
SPI1 Clock
SCK1
RPINR20[13:8]
SCK1R[5:0]
SPI1 Slave Select
SS1
RPINR21[5:0]
SS1R[5:0]
UART3 Clear-to-Send
U3CTS
RPINR21[13:8]
U3CTSR[5:0]
SPI2 Data
SDI2
RPINR22[5:0]
SDI2R[5:0]
SPI2 Clock
SCK2
RPINR22[13:8]
SCK2R[5:0]
SPI2 Slave Select
SS2
RPINR23[5:0]
SS2R[5:0]
Generic Timer External Clock
TxCK
RPINR23[13:8]
TXCKR[5:0]
CLC Input A
CLCINA
RPINR25[5:0]
CLCINAR[5:0]
CLC Input B
CLCINB
RPINR25[13:8]
CLCINBR[5:0]
CLC Input C
CLCINC
RPINR26[5:0]
CLCINCR[5:0]
CLC Input D
CLCIND
RPINR26[13:8]
CLCINDR[5:0]
UART4 Receive
U4RX
RPINR27[5:0]
U4RXR[5:0]
UART4 Clear-to-Send
U4CTS
RPINR27[13:8]
U4CTSR[5:0]
SPI4 Slave Select
SS4
RPINR30[7:0]
SS4INR[5:0]
SPI4 Data
SDI4
RPINR31[7:0]
SDI4R[5:0]
SPI4 Clock
SCK4
RPINR31[15:8]
SCK4R[5:0]
11.4.3.2 Output Mapping
In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case,
a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers
are used to control output mapping. Each register contains two 6-bit fields, with each field being associated with one
RPn pin (see 11.5 I/O Port and Peripheral Pin Select Registers). The value of the bit field corresponds to one of the
peripherals and that peripheral’s output is mapped to the pin (see Table 11-3).
Because of the mapping technique, the list of peripherals for output mapping also includes a null value of ‘000000’.
This permits any given pin to remain disconnected from the output of any of the pin-selectable peripherals.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 293
PIC24FJ512GU410 Family Data Sheet
I/O Ports
Table 11-3. Selectable Output Sources (Maps Function to Output)
Output Function Number
Function
Output Name
0
None (Pin Disabled)
—
1
C1OUT
Comparator 1
2
C2OUT
Comparator 2
3
U1TX
UART1 Transmit
4
U1RTS
UART1 Request-to-Send
5
U2TX
UART2 Transmit
6
U2RTS
UART2 Request-to-Send
7
SDO1
SPI1 Data
8
SCK1
SPI1 Clock
9
FSYNC1
SPI1 Synchronization
10
SDO2
SPI2 Data
11
SCK2
SPI2 Clock
12
FSYNC2
SPI2 Synchronization
13
SCK4
SPI4 Clock
14
FSYNC4
SPI4 Synchronization
15
SDO4
SPI4 Data
16
OCM4A
MCCP4 Output A
17
OCM4B
MCCP4 Output B
18
OCM5A
MCCP5 Output A
19
OCM5B
MCCP5 Output B
20
OCM6A
MCCP6 Output A
21
OCM6B
MCCP6 Output B
22
U3TX
UART3 Transmit
23
U3RTS
UART3 Request-to-Send
24
U4TX
UART4 Transmit
25
U4RTS
UART4 Request-to-Send
26
C3OUT
Comparator 3
27
PWRGT
RTCC Power Control
28
REFO
Reference Clock
29
CLC1OUT
CLC1 Output
30
CLC2OUT
CLC2 Output
31
CLC3OUT
CLC3 Output
32
CLC4OUT
CLC4 Output
33
RTCC
RTCC Clock
34
OCM7A
MCCP7 Output A
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 294
PIC24FJ512GU410 Family Data Sheet
I/O Ports
...........continued
Output Function Number
Function
Output Name
35
OCM7B
MCCP7 Output B
36
OCM8A
MCCP8 Output A
37
OCM8B
MCCP8 Output B
11.4.3.3 Mapping Limitations
The control schema of the Peripheral Pin Select is extremely flexible. Other than systematic blocks that prevent
signal contention caused by two physical pins being configured as the same functional input, or two functional
outputs configured as the same pin, there are no hardware enforced lockouts. The flexibility extends to the point of
allowing a single input to drive multiple peripherals or a single functional output to drive multiple output pins.
MAPPING EXCEPTIONS FOR FAMILY DEVICES
The differences in available remappable pins are summarized in Table 11-3.
When developing applications that use remappable pins, users should also keep these things in mind:
•
•
11.4.4
For the RPINRx registers, bit combinations corresponding to an unimplemented pin for a particular device are
treated as invalid; the corresponding module will not have an input mapped to it.
For RPORx registers, the bit fields corresponding to an unimplemented pin will also be
unimplemented; writing to these fields will have no effect.
Controlling Configuration Changes
Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are
needed to prevent accidental configuration changes. PIC24F devices include three features to prevent alterations to
the peripheral map:
•
•
•
Control register lock sequence
Continuous state monitoring
Configuration bit remapping lock
CONTROL REGISTER LOCK
Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to
execute normally, but the contents of the registers will remain unchanged. To change these registers, they must be
unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON[6]). Setting IOLOCK prevents
writes to the control registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence must be executed:
•
•
•
Write 46h to OSCCON[7:0].
Write 57h to OSCCON[7:0].
Clear (or set) IOLOCK as a single operation.
Unlike the similar sequence with the oscillator’s LOCK bit, IOLOCK remains in one state until changed. This allows all
of the Peripheral Pin Selects to be configured with a single unlock sequence, followed by an update to all control
registers, then locked with a second lock sequence.
CONTINUOUS STATE MONITORING
In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are constantly
monitored in hardware by shadow registers. If an unexpected change in any of the registers occurs (such as cell
disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered.
CONFIGURATION BIT REMAPPING LOCK
As an additional level of safety, the device can be configured to prevent more than one write session to the RPINRx
and RPORx registers. The IOL1WAY (FOSC[5]) Configuration bit blocks the IOLOCK bit from being cleared after it
has been set once. If IOLOCK remains set, the register unlock procedure will not execute and the Peripheral Pin
Select Control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to
perform a device Reset.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 295
PIC24FJ512GU410 Family Data Sheet
I/O Ports
In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY
allows users unlimited access (with the proper use of the unlock sequence) to the Peripheral Pin Select registers.
11.4.5
Considerations for Peripheral Pin Selection
The ability to control Peripheral Pin Selection introduces several considerations into application design that could be
overlooked. This is particularly true for several common peripherals that are available only as remappable
peripherals.
The main consideration is that the Peripheral Pin Selects are not available on default pins in the device’s default
(Reset) state. Since all RPINRx registers reset to ‘111111’ and all RPORx registers reset to ‘000000’, all Peripheral
Pin Select inputs are tied to VSS, and all Peripheral Pin Select outputs are disconnected.
This situation requires the user to initialize the device with the proper peripheral configuration before any other
application code is executed. Since the IOLOCK bit resets in the unlocked state, it is not necessary to execute the
unlock sequence after the device has come out of Reset. For application safety, however, it is best to set IOLOCK
and lock the configuration after writing to the control registers.
Because the unlock sequence is timing-critical, it must be executed as an assembly language routine in the same
manner as changes to the oscillator configuration. If the bulk of the application is written in ‘C’, or another high-level
language, the unlock sequence should be performed by writing in-line assembly.
Choosing the configuration requires the review of all Peripheral Pin Selects and their pin assignments, especially
those that will not be used in the application. In all cases, unused pin-selectable peripherals should be disabled
completely. Unused peripherals should have their inputs assigned to an unused RPn/RPIn pin function. I/O pins with
unused RPn functions should be configured with the null peripheral output.
The assignment of a peripheral to a particular pin does not automatically perform any other configuration of the pin’s
I/O circuitry. In theory, this means adding a pin-selectable output to a pin may mean inadvertently driving an existing
peripheral input when the output is driven. Users must be familiar with the behavior of other fixed peripherals that
share a remappable pin and know when to enable or disable them. To be safe, fixed digital peripherals that share the
same pin should be disabled when not in use.
Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that feature on.
The peripheral must be specifically configured for operation and enabled as if it were tied to a fixed pin. Where this
happens in the application code (immediately following a device Reset and peripheral configuration or inside the main
application routine) depends on the peripheral and its use in the application.
A final consideration is that Peripheral Pin Select functions neither override analog inputs nor reconfigure pins with
analog functions for digital I/Os. If a pin is configured as an analog input on a device Reset, it must be explicitly
reconfigured as a digital I/O when used with Peripheral Pin Select.
Example 11-4 shows a configuration for bidirectional communication with flow control using UART1. The following
input and output functions are used:
•
•
Input Functions: U1RX, U1CTS
Output Functions: U1TX, U1RTS
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 296
PIC24FJ512GU410 Family Data Sheet
I/O Ports
Example 11-4. Configuring UART1 Input and Output Functions
//
Unlock Registers
asm volatile
(“MOV #OSCCON, w1 \n”
“MOV #0x46, w2
\n”
“MOV #0x57, w3
\n”
“MOV.b w2, [w1] \n”
“MOV.b w3, [w1] \n”
“BCLR OSCCON, #6”) ;
// or use XC16 built-in macro:
// __builtin_write_OSCCONL(OSCCON & 0xbf);
// Configure Input Functions (Table 11-2)
// Assign U1RX To Pin RP0
RPINR18bits.U1RXR = 0;
// Assign U1CTS To Pin RP1
RPINR18bits.U1CTSR = 1;
// Configure Output Functions (Table 11-3)
// Assign U1TX To Pin RP2
RPOR1bits.RP2R = 3;
// Assign U1RTS To Pin RP3
RPOR1bits.RP3R = 4;
// Lock Registers
asm volatile
(“MOV #OSCCON, w1 \n”
“MOV #0x46, w2
\n”
“MOV #0x57, w3
\n”
“MOV.b w2, [w1] \n”
“MOV.b w3, [w1] \n"
”BSET OSCCON, #6") ;
// or use XC16 built-in macro:
// __builtin_write_OSCCONL(OSCCON | 0x40);
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 297
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5
I/O Port and Peripheral Pin Select Registers
Offset
Name
0x00
...
0x065B
Reserved
0x065C
PADCON
0x065E
IOCSTAT
0x0660
TRISA
0x0662
PORTA
0x0664
LATA
0x0666
ODCA
0x0668
ANSA
0x0668
ANSF
0x066A
IOCPA
0x066C
0x066E
IOCNA
IOCFA
0x0670
IOCPUA
0x0672
IOCPDA
0x0674
TRISB
0x0676
PORTB
0x0678
LATB
0x067A
ODCB
0x067C
ANSB
0x067E
IOCPB
0x0680
IOCNB
0x0682
IOCFB
0x0684
IOCPUB
0x0686
IOCPDB
0x0688
TRISC
0x068A
PORTC
0x068C
LATC
Bit Pos.
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7
6
5
4
3
2
1
0
IOCON
IOCPHF
IOCPGF
IOCPFF
IOCPEF
IOCPDF
IOCPCF
IOCPBF
IOCPAF
TRISA[7:0]
TRISA[15:14]
TRISA[10:9]
RA[7:0]
RA[15:14]
RA[10:9]
LATA[7:0]
LATA[15:14]
LATA[10:9]
ODCA[7:0]
ODCA[15:14]
ANSA[7:6]
ODCA[10:9]
ANSA[7:0]
ANSA[14:8]
IOCPA[7:0]
IOCPA[15:14]
IOCPA[10:9]
IOCNA[7:0]
IOCNA[15:14]
IOCNA[10:9]
IOCFA[7:0]
IOCFA[15:14]
IOCFA[10:9]
IOCPUA[7:0]
IOCPUA[15:14]
IOCPUA[10:9]
IOCPDA[7:0]
IOCPDA[15:14]
© 2019-2020 Microchip Technology Inc.
IOCPDA[10:9]
TRISB[7:0]
TRISB[15:8]
RB[7:0]
RB[15:8]
LATB[7:0]
LATB[15:8]
ODCB[7:0]
ODCB[15:8]
ANSB[7:0]
ANSB[15:8]
IOCPB[7:0]
IOCPB[15:8]
IOCNB[7:0]
IOCNB[15:8]
IOCFB[7:0]
IOCFB[15:8]
IOCPUB[7:0]
IOCPUB[15:8]
IOCPDB[7:0]
IOCPDB[15:8]
TRISC[4:1]
TRISC[15:12]
RC[4:1]
RC[15:12]
LATC[4:1]
LATC[15:12]
Datasheet
DS30010203C-page 298
PIC24FJ512GU410 Family Data Sheet
I/O Ports
...........continued
Offset
Name
Bit Pos.
0x068E
ODCC
7:0
15:8
0x0690
ANSC
0x0692
IOCPC
0x0694
IOCNC
0x0696
IOCFC
0x0698
IOCPUC
0x069A
IOCPDC
0x069C
TRISD
0x069E
PORTD
0x06A0
LATD
0x06A2
ODCD
0x06A4
ANSD
0x06A6
IOCPD
0x06A8
IOCND
0x06AA
IOCFD
0x06AC
IOCPUD
0x06AE
IOCPDD
0x06B0
TRISE
0x06B2
0x06B4
0x06B6
0x06B8
0x06BA
0x06BC
0x06BE
0x06C0
0x06C2
0x06C4
0x06C6
PORTE
LATE
ODCE
ANSE
IOCPE
IOCNE
IOCFE
IOCPUE
IOCPDE
TRISF
PORTF
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7
6
5
4
3
2
1
0
ODCC[4:1]
ODCC[15:12]
ANSC4
IOCPC[4:1]
IOCPC[15:12]
IOCNC[4:1]
IOCNC[15:12]
IOCFC[4:1]
IOCFC[15:12]
IOCPUC[4:1]
IOCPUC[15:12]
IOCPDC[4:1]
IOCPDC[15:12]
TRISD[7:0]
TRISD[14:8]
RD[7:0]
RD[14:8]
LATD[7:0]
LATD[14:8]
ODCD[7:0]
ODCD[14:8]
ANSD[7:6]
© 2019-2020 Microchip Technology Inc.
ANSD[11:10]
IOCPD[7:0]
IOCPD[14:8]
IOCND[7:0]
IOCND[14:8]
IOCFD[7:0]
IOCFD[14:8]
IOCPUD[7:0]
IOCPUD[14:8]
IOCPDD[7:0]
IOCPDD[14:8]
TRISE[9:0]
TRISE[9:0]
RE[9:0]
RE[9:0]
LATE[9:0]
LATE[9:0]
ODCE[9:0]
ODCE[9:0]
ANSE[4:3]
ANSE9
IOCPE[9:0]
IOCPE[9:0]
IOCNE[9:0]
IOCNE[9:0]
IOCFE[9:0]
IOCFE[9:0]
IOCPUE[9:0]
IOCPUE[9:0]
IOCPDE[9:0]
IOCPDE[9:0]
TRISF[8:0]
TRISF[13:12]
TRISF[8:0]
RF[8:0]
RF[13:12]
Datasheet
RF[8:0]
DS30010203C-page 299
PIC24FJ512GU410 Family Data Sheet
I/O Ports
...........continued
Offset
Name
Bit Pos.
0x06C8
LATF
7:0
15:8
0x06CA
...
0x06CD
Reserved
0x06CE
IOCPF
0x06CF
ODCF
0x06D0
IOCNF
0x06D2
IOCFF
0x06D4
0x06D6
IOCPUF
IOCPDF
0x06D8
TRISG
0x06DA
PORTG
0x06DC
0x06DE
LATG
ODCG
0x06E0
ANSG
0x06E2
IOCPG
0x06E4
0x06E6
IOCNG
IOCFG
0x06E8
IOCPUG
0x06EA
IOCPDG
0x06EC
TRISH
0x06EE
PORTH
0x06F0
LATH
0x06F2
ODCH
0x06F4
...
0x06F5
Reserved
0x06F6
IOCPH
0x06F8
IOCNH
0x06FA
IOCFH
0x06FC
IOCPUH
0x06FE
IOCPDH
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7
6
5
4
3
2
1
0
LATF[8:0]
LATF[13:12]
LATF[8:0]
IOCPF[8:0]
IOCPF[13:12]
IOCPF[8:0]
ODCF[8:0]
ODCF[13:12]
ODCF[8:0]
IOCNF[8:0]
IOCNF[13:12]
IOCNF[8:0]
IOCFF[8:0]
IOCFF[13:12]
IOCFF[8:0]
IOCPUF[8:0]
IOCPUF[13:12]
IOCPUF[8:0]
IOCPDF[8:0]
IOCPDF[13:12]
TRISG[9:6]
IOCPDF[8:0]
TRISG[3:0]
TRISG[15:12]
TRISG[9:6]
RG[9:6]
RG[3:0]
RG[15:12]
RG[9:6]
LATG[9:6]
LATG[3:0]
LATG[15:12]
LATG[9:6]
ODCG[9:6]
ODCG[3:0]
ODCG[15:12]
ODCG[9:6]
ANSG[9:6]
ANSG[9:6]
IOCPG[9:6]
IOCPG[3:0]
IOCPG[15:12]
IOCPG[9:6]
IOCNG[9:6]
IOCNG[3:0]
IOCNG[15:12]
IOCNG[9:6]
IOCFG[9:6]
IOCFG[3:0]
IOCFG[15:12]
IOCFG[9:6]
IOCPUG[9:6]
IOCPUG[3:0]
IOCPUG[15:12]
IOCPUG[9:6]
IOCPDG[9:6]
IOCPDG[3:0]
IOCPDG[15:12]
IOCPDG[9:6]
TRISH0
RH0
LATH0
ODCH0
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
© 2019-2020 Microchip Technology Inc.
IOCPH0
IOCNH0
IOCFH0
IOCPUH0
IOCPDH0
Datasheet
DS30010203C-page 300
PIC24FJ512GU410 Family Data Sheet
I/O Ports
...........continued
Offset
Name
0x0700
...
0x078F
Reserved
0x0790
RPINR0
0x0792
RPINR1
0x0794
RPINR2
0x0796
RPINR3
0x0798
RPINR4
0x079A
RPINR5
0x079C
RPINR6
0x079E
...
0x07A5
Reserved
0x07A6
RPINR11
0x07A8
RPINR12
0x07AA
RPINR13
0x07AC
RPINR14
0x07AE
...
0x07B1
Reserved
0x07B2
RPINR17
0x07B4
RPINR18
0x07B6
RPINR19
0x07B8
RPINR20
0x07BA
RPINR21
0x07BC
RPINR22
0x07BE
RPINR23
0x07C0
...
0x07C1
Reserved
0x07C2
RPINR25
0x07C4
RPINR26
0x07C6
RPINR27
0x07C8
...
0x07CB
Reserved
0x07CC
RPINR30
Bit Pos.
7
6
5
4
3
2
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
T2CKR[5:0]
T3CKR[5:0]
T4CKR[5:0]
T5CKR[5:0]
ICM1R[5:0]
ICM2R[5:0]
ICM3R[5:0]
ICM4R[5:0]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
OCFAR[5:0]
OCFBR[5:0]
TCKIAR[5:0]
TCKIBR[5:0]
REFIR[5:0]
TMPRNR[5:0]
ICM5R[5:0]
ICM6R[5:0]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
U3RXR[5:0]
U1RXR[5:0]
U1CTSR[5:0]
U2RXR[5:0]
U2CTSR[5:0]
SDI1R[5:0]
SCK1R[5:0]
SS1R[5:0]
U3CTSR[5:0]
SDI2R[5:0]
SCK2R[5:0]
SS2R[5:0]
TXCKR[5:0]
7:0
15:8
7:0
15:8
7:0
15:8
CLCINAR[5:0]
CLCINBR[5:0]
CLCINCR[5:0]
CLCINDR[5:0]
U4RXR[5:0]
U4CTSR[5:0]
7:0
15:8
SS4R[5:0]
© 2019-2020 Microchip Technology Inc.
1
0
INT1R[5:0]
INT2R[5:0]
INT3R[5:0]
INT4R[5:0]
Datasheet
DS30010203C-page 301
PIC24FJ512GU410 Family Data Sheet
I/O Ports
...........continued
Offset
Name
Bit Pos.
0x07CE
RPINR31
7:0
15:8
0x07D0
...
0x07D3
Reserved
0x07D4
RPOR0
0x07D6
RPOR1
0x07D8
RPOR2
0x07DA
RPOR3
0x07DC
RPOR4
0x07DE
RPOR5
0x07E0
RPOR6
0x07E2
RPOR7
0x07E4
RPOR8
0x07E6
RPOR9
0x07E8
RPOR10
0x07EA
RPOR11
0x07EC
RPOR12
0x07EE
RPOR13
0x07F0
RPOR14
0x07F2
RPOR15
0x07F4
RPOR16
0x07F6
RPOR17
0x07F8
RPOR18
7
6
5
4
2
1
0
SDI4R[5:0]
SCK4R[5:0]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
© 2019-2020 Microchip Technology Inc.
3
RP0R[6:0]
RP1R[6:0]
RP2R[6:0]
RP3R[6:0]
RP4R[6:0]
RP5R[6:0]
RP6R[6:0]
RP7R[6:0]
RP8R[6:0]
RP9R[6:0]
RP10R[6:0]
RP11R[6:0]
RP12R[6:0]
RP13R[6:0]
RP14R[6:0]
RP15R[6:0]
RP16R[6:0]
RP17R[6:0]
RP18R[6:0]
RP19R[6:0]
RP20R[6:0]
RP21R[6:0]
RP22R[6:0]
RP23R[6:0]
RP24R[6:0]
RP25R[6:0]
RP26R[6:0]
RP27R[6:0]
RP28R[6:0]
RP29R[6:0]
RP30R[6:0]
RP31R[6:0]
RP32R[6:0]
RP33R[6:0]
RP34R[6:0]
RP35R[6:0]
RP36R[6:0]
Datasheet
DS30010203C-page 302
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.1
Port Configuration Register
Name:
Offset:
Bit
Access
Reset
Bit
PADCON
0x65C
15
IOCON
R/W
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit 15 – IOCON Interrupt-on-Change Enable bit
Value
Description
1
Interrupt-on-change functionality is enabled
0
Interrupt-on-change functionality is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 303
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.2
Interrupt-on-Change Status Register
Name:
Offset:
IOCSTAT
0x65E
Legend: HS = Hardware Settable bit; HC = Hardware Clearable bit
Bit
15
14
13
12
11
10
9
8
7
IOCPHF
R/HS/HC
0
6
IOCPGF
R/HS/HC
0
5
IOCPFF
R/HS/HC
0
4
IOCPEF
R/HS/HC
0
3
IOCPDF
R/HS/HC
0
2
IOCPCF
R/HS/HC
0
1
IOCPBF
R/HS/HC
0
0
IOCPAF
R/HS/HC
0
Access
Reset
Bit
Access
Reset
Bit 7 – IOCPHF Interrupt-on-Change PORTH Flag bit
Value
Description
1
A change was detected on an IOC-enabled pin on PORTH
0
No change was detected or the user has cleared all detected changes
Bit 6 – IOCPGF Interrupt-on-Change PORTG Flag bit
Value
Description
1
A change was detected on an IOC-enabled pin on PORTG
0
No change was detected or the user has cleared all detected changes
Bit 5 – IOCPFF Interrupt-on-Change PORTF Flag bit
Value
Description
1
A change was detected on an IOC-enabled pin on PORTF
0
No change was detected or the user has cleared all detected changes
Bit 4 – IOCPEF Interrupt-on-Change PORTE Flag bit
Value
Description
1
A change was detected on an IOC-enabled pin on PORTE
0
No change was detected or the user has cleared all detected changes
Bit 3 – IOCPDF Interrupt-on-Change PORTD Flag bit
Value
Description
1
A change was detected on an IOC-enabled pin on PORTD
0
No change was detected or the user has cleared all detected changes
Bit 2 – IOCPCF Interrupt-on-Change PORTC Flag bit
Value
Description
1
A change was detected on an IOC-enabled pin on PORTC
0
No change was detected or the user has cleared all detected changes
Bit 1 – IOCPBF Interrupt-on-Change PORTB Flag bit
Value
Description
1
A change was detected on an IOC-enabled pin on PORTB
0
No change was detected or the user has cleared all detected changes
Bit 0 – IOCPAF Interrupt-on-Change PORTA Flag bit
Value
Description
1
A change was detected on an IOC-enabled pin on PORTA
0
No change was detected or the user has cleared all detected changes
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 304
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.3
Output Enable for PORTA Register
Name:
Offset:
Bit
Access
Reset
Bit
TRISA
0x0660
15
14
TRISA[15:14]
R/W
R/W
1
1
7
6
13
12
5
4
11
10
9
TRISA[10:9]
R/W
R/W
1
1
8
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
TRISA[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 15:14 – TRISA[15:14] Output Enable bits
Value
Description
1
Pin is configured as input
0
Pin is configured as output
Bits 10:9 – TRISA[10:9] Output Enable bits
Value
Description
1
Pin is configured as input
0
Pin is configured as output
Bits 7:0 – TRISA[7:0] Output Enable bits
Value
Description
1
Pin is configured as input
0
Pin is configured as output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 305
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.4
Input Data for PORTA Register
Name:
Offset:
Bit
PORTA
0x662
15
14
13
12
11
10
RA[15:14]
Access
Reset
Bit
9
8
RA[10:9]
R/W
0
R/W
0
7
6
5
4
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
RA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:14 – RA[15:14] Data Input Value bits
Bits 10:9 – RA[10:9] Data Input Value bits
Bits 7:0 – RA[7:0] Data Input Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 306
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.5
Output Data for PORTA Register
Name:
Offset:
Bit
Access
Reset
Bit
LATA
0x664
15
14
LATA[15:14]
R/W
R/W
0
0
7
13
12
11
10
9
8
LATA[10:9]
6
5
4
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
LATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:14 – LATA[15:14] Output Data bits
Bits 10:9 – LATA[10:9] Output Data bits
Bits 7:0 – LATA[7:0] Output Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 307
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.6
Open-Drain Enable for PORTA Register
Name:
Offset:
Bit
Access
Reset
Bit
ODCA
0x666
15
14
ODCA[15:14]
R/W
R/W
0
0
7
6
13
12
5
4
11
10
9
ODCA[10:9]
R/W
R/W
0
0
8
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ODCA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:14 – ODCA[15:14] Open-Drain Enable bits
Value
Description
1
Open-drain is enabled on the pin
0
Open-drain is disabled on the pin
Bits 10:9 – ODCA[10:9] Open-Drain Enable bits
Value
Description
1
Open-drain is enabled on the pin
0
Open-drain is disabled on the pin
Bits 7:0 – ODCA[7:0] Open-Drain Enable bits
Value
Description
1
Open-drain is enabled on the pin
0
Open-drain is disabled on the pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 308
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.7
Analog Select for PORTA Register
Name:
Offset:
Bit
ANSA
0x668
15
14
13
12
11
10
9
8
6
5
4
3
2
1
0
Access
Reset
Bit
7
ANSA[7:6]
Access
Reset
R/W
1
R/W
1
Bits 7:6 – ANSA[7:6] Analog Input Select bits
Value
Description
1
Analog input is enabled and digital input is disabled on the pin
0
Analog input is disabled and digital input is enabled on the pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 309
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.8
Interrupt-on-Change Positive Edge PORTA Register
Name:
Offset:
Bit
Access
Reset
Bit
IOCPA
0x66A
15
14
IOCPA[15:14]
R/W
R/W
0
0
7
6
13
12
5
4
11
10
9
IOCPA[10:9]
R/W
R/W
0
0
8
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCPA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:14 – IOCPA[15:14] Interrupt-on-Change Positive Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a positive going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a positive going edge
Bits 10:9 – IOCPA[10:9] Interrupt-on-Change Positive Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a positive going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a positive going edge
Bits 7:0 – IOCPA[7:0] Interrupt-on-Change Positive Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a positive going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a positive going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 310
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.9
Interrupt-on-Change Negative Edge PORTA Register
Name:
Offset:
Bit
Access
Reset
Bit
IOCNA
0x66C
15
14
IOCNA[15:14]
R/W
R/W
0
0
7
6
13
12
5
4
11
10
9
IOCNA[10:9]
R/W
R/W
0
0
8
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCNA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:14 – IOCNA[15:14] Interrupt-on-Change Negative Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a negative going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a negative going edge
Bits 10:9 – IOCNA[10:9] Interrupt-on-Change Negative Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a negative going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a negative going edge
Bits 7:0 – IOCNA[7:0] Interrupt-on-Change Negative Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a negative going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a negative going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 311
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.10 Interrupt-on-Change Flag PORTA Register
Name:
Offset:
Bit
Access
Reset
Bit
IOCFA
0x66E
15
14
IOCFA[15:14]
R/W
R/W
0
0
7
6
13
12
5
4
11
10
9
IOCFA[10:9]
R/W
R/W
0
0
8
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCFA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:14 – IOCFA[15:14] Interrupt-on-Change Flag bits
Value
Description
1
An enabled change was detected on the associated pin
0
No change was detected or the user cleared the detected change
Bits 10:9 – IOCFA[10:9] Interrupt-on-Change Flag bits
Value
Description
1
An enabled change was detected on the associated pin
0
No change was detected or the user cleared the detected change
Bits 7:0 – IOCFA[7:0] Interrupt-on-Change Flag bits
Value
Description
1
An enabled change was detected on the associated pin
0
No change was detected or the user cleared the detected change
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 312
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.11
Interrupt-on-Change Pull-up Enable PORTA Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
IOCPUA
0x670
15
14
IOCPUA[15:14]
R/W
R/W
0
0
13
12
4
7
6
5
R/W
0
R/W
0
R/W
0
11
3
IOCPUA[7:0]
R/W
R/W
0
0
10
9
IOCPUA[10:9]
R/W
R/W
0
0
8
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:14 – IOCPUA[15:14] Interrupt-on-Change Pull-up Enable bits
Value
Description
1
Pull-up is enabled
0
Pull-up is disabled
Bits 10:9 – IOCPUA[10:9] Interrupt-on-Change Pull-up Enable bits
Value
Description
1
Pull-up is enabled
0
Pull-up is disabled
Bits 7:0 – IOCPUA[7:0] Interrupt-on-Change Pull-up Enable bits
Value
Description
1
Pull-up is enabled
0
Pull-up is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 313
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.12 Interrupt-on-Change Pull-Down Enable PORTA Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
IOCPDA
0x672
15
14
IOCPDA[15:14]
R/W
R/W
0
0
13
12
4
7
6
5
R/W
0
R/W
0
R/W
0
11
3
IOCPDA[7:0]
R/W
R/W
0
0
10
9
IOCPDA[10:9]
R/W
R/W
0
0
8
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:14 – IOCPDA[15:14] Interrupt-on-Change Pull-Down Enable bits
Value
Description
1
Pull-down is enabled
0
Pull-down is disabled
Bits 10:9 – IOCPDA[10:9] Interrupt-on-Change Pull-Down Enable bits
Value
Description
1
Pull-down is enabled
0
Pull-down is disabled
Bits 7:0 – IOCPDA[7:0] Interrupt-on-Change Pull-Down Enable bits
Value
Description
1
Pull-down is enabled
0
Pull-down is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 314
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.13 Output Enable for PORTB Register
Name:
Offset:
Bit
Access
Reset
Bit
TRISB
0x674
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
12
11
TRISB[15:8]
R/W
R/W
1
1
4
10
9
8
R/W
1
R/W
1
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
TRISB[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 15:0 – TRISB[15:0] Output Enable bits
Value
Description
1
Pin is configured as input
0
Pin is configured as output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 315
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.14 Input Data for PORTB Register
Name:
Offset:
Bit
15
PORTB
0x676
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
RB[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
RB[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – RB[15:0] Data Input Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 316
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.15 Output Data for PORTB Register
Name:
Offset:
Bit
15
LATB
0x678
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
LATB[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
LATB[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – LATB[15:0] Output Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 317
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.16 Open-Drain Enable for PORTB Register
Name:
Offset:
Bit
Access
Reset
Bit
ODCB
0x67A
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
ODCB[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ODCB[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ODCB[15:0] Open-Drain Enable bits
Value
Description
1
Open-drain is enabled on the pin
0
Open-drain is disabled on the pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 318
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.17 Analog Select for PORTB Register
Name:
Offset:
Bit
15
ANSB
0x67C
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
ANSB[15:8]
Access
Reset
Bit
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
ANSB[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 15:0 – ANSB[15:0] Analog Input Select bits
Value
Description
1
Analog input is enabled and digital input is disabled on the pin
0
Analog input is disabled and digital input is enabled on the pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 319
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.18 Interrupt-on-Change Positive Edge PORTB Register
Name:
Offset:
Bit
Access
Reset
Bit
IOCPB
0x67E
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
IOCPB[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCPB[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – IOCPB[15:0] Interrupt-on-Change Positive Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a positive going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a positive going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 320
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.19 Interrupt-on-Change Negative Edge PORTB Register
Name:
Offset:
Bit
Access
Reset
Bit
IOCNB
0x680
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
IOCNB[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCNB[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – IOCNB[15:0] Interrupt-on-Change Negative Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a negative going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a negative going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 321
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.20 Interrupt-on-Change Flag PORTB Register
Name:
Offset:
Bit
Access
Reset
Bit
IOCFB
0x682
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
IOCFB[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCFB[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – IOCFB[15:0] Interrupt-on-Change Flag bits
Value
Description
1
An enabled change was detected on the associated pin
0
No change was detected or the user cleared the detected change
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 322
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.21 Interrupt-on-Change Pull-up Enable PORTB Register
Bit
Access
Reset
Bit
Access
Reset
Name:
Offset:
IOCPUB
0x684
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
IOCPUB[15:8]
R/W
R/W
0
0
4
3
IOCPUB[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – IOCPUB[15:0] Interrupt-on-Change Pull-up Enable bits
Value
Description
1
Pull-up is enabled
0
Pull-up is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 323
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.22 Interrupt-on-Change Pull-Down Enable PORTB Register
Bit
Access
Reset
Bit
Access
Reset
Name:
Offset:
IOCPDB
0x686
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
IOCPDB[15:8]
R/W
R/W
0
0
4
3
IOCPDB[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – IOCPDB[15:0] Interrupt-on-Change Pull-Down Enable bits
Value
Description
1
Pull-down is enabled
0
Pull-down is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 324
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.23 Output Enable for PORTC Register
Name:
Offset:
Bit
Access
Reset
Bit
15
R/W
1
7
TRISC
0x688
14
13
TRISC[15:12]
R/W
R/W
1
1
6
5
12
11
10
9
8
2
1
0
R/W
1
R/W
1
R/W
1
4
3
TRISC[4:1]
Access
Reset
R/W
1
R/W
1
Bits 15:12 – TRISC[15:12] Output Enable bits
Value
Description
1
Pin is configured as input
0
Pin is configured as output
Bits 4:1 – TRISC[4:1] Output Enable bits
Value
Description
1
Pin is configured as input
0
Pin is configured as output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 325
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.24 Input Data for PORTC Register
Name:
Offset:
Bit
15
PORTC
0x68A
14
13
12
11
10
9
8
2
1
0
R/W
0
R/W
0
RC[15:12]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
RC[4:1]
Access
Reset
R/W
0
R/W
0
Bits 15:12 – RC[15:12] Data Input Value bits
Bits 4:1 – RC[4:1] Data Input Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 326
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.25 Output Data for PORTC Register
Name:
Offset:
Bit
Access
Reset
Bit
15
R/W
0
7
LATC
0x68C
14
13
LATC[15:12]
R/W
R/W
0
0
6
5
12
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
4
3
LATC[4:1]
Access
Reset
R/W
0
R/W
0
Bits 15:12 – LATC[15:12] Output Data bits
Bits 4:1 – LATC[4:1] Output Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 327
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.26 Open-Drain Enable for PORTC Register
Name:
Offset:
Bit
Access
Reset
Bit
15
R/W
0
7
ODCC
0x68E
14
13
ODCC[15:12]
R/W
R/W
0
0
6
5
12
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
4
3
ODCC[4:1]
Access
Reset
R/W
0
R/W
0
Bits 15:12 – ODCC[15:12] Open-Drain Enable bits
Value
Description
1
Open-drain is enabled on the pin
0
Open-drain is disabled on the pin
Bits 4:1 – ODCC[4:1] Open-Drain Enable bits
Value
Description
1
Open-drain is enabled on the pin
0
Open-drain is disabled on the pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 328
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.27 Analog Select for PORTC Register
Name:
Offset:
Bit
ANSC
0x690
15
14
13
12
11
10
9
8
7
6
5
4
ANSC4
R/W
1
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit 4 – ANSC4 Analog Input Select bit
Value
Description
1
Analog input is enabled and digital input is disabled on the pin
0
Analog input is disabled and digital input is enabled on the pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 329
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.28 Interrupt-on-Change Positive Edge PORTC Register
Name:
Offset:
Bit
Access
Reset
Bit
15
R/W
0
7
IOCPC
0x692
14
13
IOCPC[15:12]
R/W
R/W
0
0
6
5
12
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
4
3
IOCPC[4:1]
Access
Reset
R/W
0
R/W
0
Bits 15:12 – IOCPC[15:12] Interrupt-on-Change Positive Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a positive going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a positive going edge
Bits 4:1 – IOCPC[4:1] Interrupt-on-Change Positive Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a positive going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a positive going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 330
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.29 Interrupt-on-Change Negative Edge PORTC Register
Name:
Offset:
Bit
Access
Reset
Bit
15
R/W
0
7
IOCNC
0x694
14
13
IOCNC[15:12]
R/W
R/W
0
0
6
5
12
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
4
3
IOCNC[4:1]
Access
Reset
R/W
0
R/W
0
Bits 15:12 – IOCNC[15:12] Interrupt-on-Change Negative Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a negative going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a negative going edge
Bits 4:1 – IOCNC[4:1] Interrupt-on-Change Negative Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a negative going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a negative going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 331
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.30 Interrupt-on-Change Flag PORTC Register
Name:
Offset:
Bit
Access
Reset
Bit
15
R/W
0
7
IOCFC
0x696
14
13
IOCFC[15:12]
R/W
R/W
0
0
6
5
12
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
4
3
IOCFC[4:1]
Access
Reset
R/W
0
R/W
0
Bits 15:12 – IOCFC[15:12] Interrupt-on-Change Flag bits
Value
Description
1
An enabled change was detected on the associated pin
0
No change was detected or the user cleared the detected change
Bits 4:1 – IOCFC[4:1] Interrupt-on-Change Flag bits
Value
Description
1
An enabled change was detected on the associated pin
0
No change was detected or the user cleared the detected change
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 332
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.31 Interrupt-on-Change Pull-up Enable PORTC Register
Name:
Offset:
Bit
Access
Reset
Bit
15
R/W
0
7
IOCPUC
0x698
14
13
IOCPUC[15:12]
R/W
R/W
0
0
6
Access
Reset
5
12
11
10
9
8
1
0
R/W
0
4
R/W
0
3
2
IOCPUC[4:1]
R/W
R/W
0
0
R/W
0
Bits 15:12 – IOCPUC[15:12] Interrupt-on-Change Pull-up Enable bits
Value
Description
1
Pull-up is enabled
0
Pull-up is disabled
Bits 4:1 – IOCPUC[4:1] Interrupt-on-Change Pull-up Enable bits
Value
Description
1
Pull-up is enabled
0
Pull-up is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 333
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.32 Interrupt-on-Change Pull-Down Enable PORTC Register
Name:
Offset:
Bit
Access
Reset
Bit
15
R/W
0
7
IOCPDC
0x69A
14
13
IOCPDC[15:12]
R/W
R/W
0
0
6
Access
Reset
5
12
11
10
9
8
1
0
R/W
0
4
R/W
0
3
2
IOCPDC[4:1]
R/W
R/W
0
0
R/W
0
Bits 15:12 – IOCPDC[15:12] Interrupt-on-Change Pull-Down Enable bits
Value
Description
1
Pull-down is enabled
0
Pull-down is disabled
Bits 4:1 – IOCPDC[4:1] Interrupt-on-Change Pull-Down Enable bits
Value
Description
1
Pull-down is enabled
0
Pull-down is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 334
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.33 Output Enable for PORTD Register
Name:
Offset:
Bit
15
Access
Reset
Bit
7
TRISD
0x69C
14
13
12
R/W
1
R/W
1
R/W
1
6
5
4
11
TRISD[14:8]
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
TRISD[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 14:0 – TRISD[14:0] Output Enable bits
Value
Description
1
Pin is configured as input
0
Pin is configured as output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 335
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.34 Input Data for PORTD Register
Name:
Offset:
Bit
15
Access
Reset
Bit
7
PORTD
0x69E
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
11
RD[14:8]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
RD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 14:0 – RD[14:0] Data Input Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 336
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.35 Output Data for PORTD Register
Name:
Offset:
Bit
15
Access
Reset
Bit
7
LATD
0x6A0
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
11
LATD[14:8]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
LATD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 14:0 – LATD[14:0] Output Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 337
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.36 Open-Drain Enable for PORTD Register
Name:
Offset:
Bit
15
Access
Reset
Bit
7
ODCD
0x6A2
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
11
ODCD[14:8]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ODCD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 14:0 – ODCD[14:0] Open-Drain Enable bits
Value
Description
1
Open-drain is enabled on the pin
0
Open-drain is disabled on the pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 338
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.37 Analog Select for PORTD Register
Name:
Offset:
Bit
ANSD
0x6A4
15
14
13
12
6
5
4
Access
Reset
Bit
7
11
10
ANSD[11:10]
R/W
R/W
1
1
3
2
9
8
1
0
ANSD[7:6]
Access
Reset
R/W
1
R/W
1
Bits 11:10 – ANSD[11:10] Analog Input Select bits
Value
Description
1
Analog input is enabled and digital input is disabled on the pin
0
Analog input is disabled and digital input is enabled on the pin
Bits 7:6 – ANSD[7:6] Analog Input Select bits
Value
Description
1
Analog input is enabled and digital input is disabled on the pin
0
Analog input is disabled and digital input is enabled on the pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 339
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.38 Interrupt-on-Change Positive Edge PORTD Register
Name:
Offset:
Bit
15
Access
Reset
Bit
7
IOCPD
0x6A6
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
11
IOCPD[14:8]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCPD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 14:0 – IOCPD[14:0] Interrupt-on-Change Positive Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a positive going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a positive going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 340
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.39 Interrupt-on-Change Negative Edge PORTD Register
Name:
Offset:
Bit
15
Access
Reset
Bit
7
IOCND
0x6A8
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
11
IOCND[14:8]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCND[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 14:0 – IOCND[14:0] Interrupt-on-Change Negative Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a negative going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a negative going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 341
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.40 Interrupt-on-Change Flag PORTD Register
Name:
Offset:
Bit
15
Access
Reset
Bit
7
IOCFD
0x6AA
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
11
IOCFD[14:8]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCFD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 14:0 – IOCFD[14:0] Interrupt-on-Change Flag bits
Value
Description
1
An enabled change was detected on the associated pin
0
No change was detected or the user cleared the detected change
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 342
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.41 Interrupt-on-Change Pull-up Enable PORTD Register
Bit
Name:
Offset:
IOCPUD
0x6AC
15
14
13
12
R/W
0
R/W
0
R/W
0
7
6
5
4
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
11
IOCPUD[14:8]
R/W
0
3
IOCPUD[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:0 – IOCPUD[14:0] Interrupt-on-Change Pull-up Enable bits
Value
Description
1
Pull-up is enabled
0
Pull-up is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 343
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.42 Interrupt-on-Change Pull-Down Enable PORTD Register
Bit
Name:
Offset:
IOCPDD
0x6AE
15
14
13
12
R/W
0
R/W
0
R/W
0
7
6
5
4
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
11
IOCPDD[14:8]
R/W
0
3
IOCPDD[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:0 – IOCPDD[14:0] Interrupt-on-Change Pull-Down Enable bits
Value
Description
1
Pull-down is enabled
0
Pull-down is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 344
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.43 Output Enable for PORTE Register
Name:
Offset:
Bit
15
TRISE
0x6B0
14
13
12
11
10
9
8
TRISE[9:0]
Access
Reset
Bit
7
6
5
4
R/W
1
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
TRISE[9:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 9:0 – TRISE[9:0] Output Enable bits
Value
Description
1
Pin is configured as input
0
Pin is configured as output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 345
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.44 Input Data for PORTE Register
Name:
Offset:
Bit
15
PORTE
0x6B2
14
13
12
11
10
9
8
RE[9:0]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
RE[9:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – RE[9:0] Data Input Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 346
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.45 Output Data for PORTE Register
Name:
Offset:
Bit
15
LATE
0x6B4
14
13
12
11
10
9
8
LATE[9:0]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
LATE[9:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – LATE[9:0] Output Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 347
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.46 Open-Drain Enable for PORTE Register
Name:
Offset:
Bit
15
ODCE
0x6B6
14
13
12
11
10
9
8
ODCE[9:0]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ODCE[9:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – ODCE[9:0] Open-Drain Enable bits
Value
Description
1
Open-drain is enabled on the pin
0
Open-drain is disabled on the pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 348
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.47 Analog Select for PORTE Register
Name:
Offset:
Bit
ANSE
0x6B8
15
14
13
12
7
6
5
4
11
10
9
ANSE9
R/W
1
8
3
2
1
0
Access
Reset
Bit
ANSE[4:3]
Access
Reset
R/W
1
R/W
1
Bit 9 – ANSE9 Analog Input Select bits
Value
Description
1
Analog input is enabled and digital input is disabled on the pin
0
Analog input is disabled and digital input is enabled on the pin
Bits 4:3 – ANSE[4:3] Analog Input Select bits
Value
Description
1
Analog input is enabled and digital input is disabled on the pin
0
Analog input is disabled and digital input is enabled on the pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 349
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.48 Interrupt-on-Change Positive Edge PORTE Register
Name:
Offset:
Bit
15
IOCPE
0x6BA
14
13
12
11
10
9
8
IOCPE[9:0]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCPE[9:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – IOCPE[9:0] Interrupt-on-Change Positive Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a positive going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a positive going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 350
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.49 Interrupt-on-Change Negative Edge PORTE Register
Name:
Offset:
Bit
15
IOCNE
0x6BC
14
13
12
11
10
9
8
IOCNE[9:0]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCNE[9:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – IOCNE[9:0] Interrupt-on-Change Negative Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a negative going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a negative going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 351
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.50 Interrupt-on-Change Flag PORTE Register
Name:
Offset:
Bit
15
IOCFE
0x6BE
14
13
12
11
10
9
8
IOCFE[9:0]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCFE[9:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – IOCFE[9:0] Interrupt-on-Change Flag bits
Value
Description
1
An enabled change was detected on the associated pin
0
No change was detected or the user cleared the detected change
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 352
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.51 Interrupt-on-Change Pull-up Enable PORTE Register
Bit
Name:
Offset:
IOCPUE
0x6C0
15
14
13
12
7
6
5
4
R/W
0
R/W
0
R/W
0
11
10
Access
Reset
Bit
Access
Reset
3
IOCPUE[9:0]
R/W
R/W
0
0
9
8
IOCPUE[9:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – IOCPUE[9:0] Interrupt-on-Change Pull-up Enable bits
Value
Description
1
Pull-up is enabled
0
Pull-up is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 353
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.52 Interrupt-on-Change Pull-Down Enable PORTE Register
Bit
Name:
Offset:
IOCPDE
0x6C2
15
14
13
12
7
6
5
4
R/W
0
R/W
0
R/W
0
11
10
Access
Reset
Bit
Access
Reset
3
IOCPDE[9:0]
R/W
R/W
0
0
9
8
IOCPDE[9:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – IOCPDE[9:0] Interrupt-on-Change Pull-Down Enable bits
Value
Description
1
Pull-down is enabled
0
Pull-down is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 354
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.53 Output Enable for PORTF Register
Name:
Offset:
Bit
TRISF
0x6C4
15
14
7
6
Access
Reset
Bit
13
12
TRISF[13:12]
R/W
R/W
1
1
5
4
11
10
9
8
TRISF[8:0]
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
TRISF[8:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 13:12 – TRISF[13:12] Output Enable bits
Value
Description
1
Pin is configured as input
0
Pin is configured as output
Bits 8:0 – TRISF[8:0] Output Enable bits
Value
Description
1
Pin is configured as input
0
Pin is configured as output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 355
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.54 Input Data for PORTF Register
Name:
Offset:
Bit
15
PORTF
0x6C6
14
13
12
11
10
9
8
RF[8:0]
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
RF[13:12]
Access
Reset
Bit
7
R/W
0
R/W
0
5
4
6
RF[8:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 13:12 – RF[13:12] Data Input Value bits
Bits 8:0 – RF[8:0] Data Input Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 356
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.55 Output Data for PORTF Register
Name:
Offset:
Bit
LATF
0x6C8
15
14
7
6
Access
Reset
Bit
13
12
LATF[13:12]
R/W
R/W
0
0
5
4
11
10
9
8
LATF[8:0]
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
LATF[8:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 13:12 – LATF[13:12] Output Data bits
Bits 8:0 – LATF[8:0] Output Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 357
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.56 Interrupt-on-Change Positive Edge PORTF Register
Name:
Offset:
Bit
IOCPF
0x6CE
15
14
7
6
Access
Reset
Bit
13
12
IOCPF[13:12]
R/W
R/W
0
0
5
4
11
10
9
8
IOCPF[8:0]
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCPF[8:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 13:12 – IOCPF[13:12] Interrupt-on-Change Positive Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a positive going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a positive going edge
Bits 8:0 – IOCPF[8:0] Interrupt-on-Change Positive Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a positive going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a positive going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 358
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.57 Open-Drain Enable for PORTF Register
Name:
Offset:
Bit
ODCF
0x6CF
15
14
7
6
Access
Reset
Bit
13
12
ODCF[13:12]
R/W
R/W
0
0
5
4
11
10
9
8
ODCF[8:0]
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ODCF[8:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 13:12 – ODCF[13:12] Open-Drain Enable bits
Value
Description
1
Open-drain is enabled on the pin
0
Open-drain is disabled on the pin
Bits 8:0 – ODCF[8:0] Open-Drain Enable bits
Value
Description
1
Open-drain is enabled on the pin
0
Open-drain is disabled on the pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 359
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.58 Analog Select for PORTF Register
Name:
Offset:
Bit
15
Access
Reset
Bit
7
ANSF
0x668
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
11
ANSA[14:8]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
1
ANSA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 14:0 – ANSA[14:0] Analog Select for PORTF bits
Value
Description
1
Analog input is enabled and digital input is disabled on the PORTx[n] pin
0
Analog input is disabled and digital input is enabled on the PORTx[n] pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 360
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.59 Interrupt-on-Change Negative Edge PORTF Register
Name:
Offset:
Bit
IOCNF
0x6D0
15
14
7
6
Access
Reset
Bit
13
12
IOCNF[13:12]
R/W
R/W
0
0
5
4
11
10
9
8
IOCNF[8:0]
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCNF[8:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 13:12 – IOCNF[13:12] Interrupt-on-Change Negative Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a negative going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a negative going edge
Bits 8:0 – IOCNF[8:0] Interrupt-on-Change Negative Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a negative going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a negative going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 361
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.60 Interrupt-on-Change Flag PORTF Register
Name:
Offset:
Bit
IOCFF
0x6D2
15
14
7
6
Access
Reset
Bit
13
12
IOCFF[13:12]
R/W
R/W
0
0
5
4
11
10
9
8
IOCFF[8:0]
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IOCFF[8:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 13:12 – IOCFF[13:12] Interrupt-on-Change Flag bits
Value
Description
1
An enabled change was detected on the associated pin
0
No change was detected or the user cleared the detected change
Bits 8:0 – IOCFF[8:0] Interrupt-on-Change Flag bits
Value
Description
1
An enabled change was detected on the associated pin
0
No change was detected or the user cleared the detected change
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 362
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.61 Interrupt-on-Change Pull-up Enable PORTF Register
Bit
Name:
Offset:
IOCPUF
0x6D4
15
14
7
6
5
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
13
12
IOCPUF[13:12]
R/W
R/W
0
0
11
4
3
IOCPUF[8:0]
R/W
R/W
0
0
10
9
8
IOCPUF[8:0]
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 13:12 – IOCPUF[13:12] Interrupt-on-Change Pull-up Enable bits
Value
Description
1
Pull-up is enabled
0
Pull-up is disabled
Bits 8:0 – IOCPUF[8:0] Interrupt-on-Change Pull-up Enable bits
Value
Description
1
Pull-up is enabled
0
Pull-up is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 363
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.62 Interrupt-on-Change Pull-Down Enable PORTF Register
Bit
Name:
Offset:
IOCPDF
0x6D6
15
14
7
6
5
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
13
12
IOCPDF[13:12]
R/W
R/W
0
0
11
4
3
IOCPDF[8:0]
R/W
R/W
0
0
10
9
8
IOCPDF[8:0]
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 13:12 – IOCPDF[13:12] Interrupt-on-Change Pull-Down Enable bits
Value
Description
1
Pull-down is enabled
0
Pull-down is disabled
Bits 8:0 – IOCPDF[8:0] Interrupt-on-Change Pull-Down Enable bits
Value
Description
1
Pull-down is enabled
0
Pull-down is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 364
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.63 Output Enable for PORTG Register
Name:
Offset:
Bit
Access
Reset
Bit
TRISG
0x6D8
15
14
13
TRISG[15:12]
R/W
R/W
1
1
R/W
1
7
6
5
12
11
10
R/W
1
8
TRISG[9:6]
R/W
1
4
3
2
TRISG[9:6]
Access
Reset
9
R/W
1
R/W
1
1
0
R/W
1
R/W
1
TRISG[3:0]
R/W
1
R/W
1
R/W
1
Bits 15:12 – TRISG[15:12] Output Enable bits
Value
Description
1
Pin is configured as input
0
Pin is configured as output
Bits 9:6 – TRISG[9:6] Output Enable bits
Value
Description
1
Pin is configured as input
0
Pin is configured as output
Bits 3:0 – TRISG[3:0] Output Enable bits
Value
Description
1
Pin is configured as input
0
Pin is configured as output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 365
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.64 Input Data for PORTG Register
Name:
Offset:
Bit
PORTG
0x6DA
15
14
13
12
11
10
9
RG[15:12]
Access
Reset
Bit
R/W
0
7
R/W
0
R/W
0
R/W
0
6
5
4
3
2
RG[9:6]
Access
Reset
R/W
0
8
RG[9:6]
R/W
0
R/W
0
1
0
R/W
0
R/W
0
RG[3:0]
R/W
0
R/W
0
R/W
0
Bits 15:12 – RG[15:12] Data Input Value bits
Bits 9:6 – RG[9:6] Data Input Value bits
Bits 3:0 – RG[3:0] Data Input Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 366
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.65 Output Data for PORTG Register
Name:
Offset:
Bit
Access
Reset
Bit
LATG
0x6DC
15
14
13
LATG[15:12]
R/W
R/W
0
0
R/W
0
7
6
5
12
11
10
R/W
0
8
LATG[9:6]
R/W
0
4
3
2
LATG[9:6]
Access
Reset
9
R/W
0
R/W
0
1
0
R/W
0
R/W
0
LATG[3:0]
R/W
0
R/W
0
R/W
0
Bits 15:12 – LATG[15:12] Output Data bits
Bits 9:6 – LATG[9:6] Output Data bits
Bits 3:0 – LATG[3:0] Output Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 367
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.66 Open-Drain Enable for PORTG Register
Name:
Offset:
Bit
Access
Reset
Bit
ODCG
0x6DE
15
14
13
ODCG[15:12]
R/W
R/W
0
0
R/W
0
7
6
5
12
11
10
R/W
0
8
ODCG[9:6]
R/W
0
4
3
2
ODCG[9:6]
Access
Reset
9
R/W
0
R/W
0
1
0
R/W
0
R/W
0
ODCG[3:0]
R/W
0
R/W
0
R/W
0
Bits 15:12 – ODCG[15:12] Open-Drain Enable bits
Value
Description
1
Open-drain is enabled on the pin
0
Open-drain is disabled on the pin
Bits 9:6 – ODCG[9:6] Open-Drain Enable bits
Value
Description
1
Open-drain is enabled on the pin
0
Open-drain is disabled on the pin
Bits 3:0 – ODCG[3:0] Open-Drain Enable bits
Value
Description
1
Open-drain is enabled on the pin
0
Open-drain is disabled on the pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 368
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.67 Analog Select for PORTG Register
Name:
Offset:
Bit
ANSG
0x6E0
15
14
13
12
11
10
9
8
ANSG[9:6]
Access
Reset
Bit
7
6
5
4
3
2
R/W
1
R/W
1
1
0
ANSG[9:6]
Access
Reset
R/W
1
R/W
1
Bits 9:6 – ANSG[9:6] Analog Input Select bits
Value
Description
1
Analog input is enabled and digital input is disabled on the pin
0
Analog input is disabled and digital input is enabled on the pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 369
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.68 Interrupt-on-Change Positive Edge PORTG Register
Name:
Offset:
Bit
Access
Reset
Bit
IOCPG
0x6E2
15
14
13
IOCPG[15:12]
R/W
R/W
0
0
R/W
0
7
6
5
12
11
10
R/W
0
8
IOCPG[9:6]
R/W
0
4
3
2
IOCPG[9:6]
Access
Reset
9
R/W
0
R/W
0
1
0
R/W
0
R/W
0
IOCPG[3:0]
R/W
0
R/W
0
R/W
0
Bits 15:12 – IOCPG[15:12] Interrupt-on-Change Positive Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a positive going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a positive going edge
Bits 9:6 – IOCPG[9:6] Interrupt-on-Change Positive Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a positive going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a positive going edge
Bits 3:0 – IOCPG[3:0] Interrupt-on-Change Positive Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a positive going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a positive going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 370
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.69 Interrupt-on-Change Negative Edge PORTG Register
Name:
Offset:
Bit
Access
Reset
Bit
IOCNG
0x6E4
15
14
13
IOCNG[15:12]
R/W
R/W
0
0
R/W
0
7
6
5
12
11
10
R/W
0
8
IOCNG[9:6]
R/W
0
4
3
2
IOCNG[9:6]
Access
Reset
9
R/W
0
R/W
0
1
0
R/W
0
R/W
0
IOCNG[3:0]
R/W
0
R/W
0
R/W
0
Bits 15:12 – IOCNG[15:12] Interrupt-on-Change Negative Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a negative going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a negative going edge
Bits 9:6 – IOCNG[9:6] Interrupt-on-Change Negative Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a negative going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a negative going edge
Bits 3:0 – IOCNG[3:0] Interrupt-on-Change Negative Edge Enable bits
Value
Description
1
Interrupt-on-change is enabled on the pin for a negative going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a negative going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 371
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.70 Interrupt-on-Change Flag PORTG Register
Name:
Offset:
Bit
Access
Reset
Bit
IOCFG
0x6E6
15
14
13
IOCFG[15:12]
R/W
R/W
0
0
R/W
0
7
6
5
12
11
10
R/W
0
8
IOCFG[9:6]
R/W
0
4
3
2
IOCFG[9:6]
Access
Reset
9
R/W
0
R/W
0
1
0
R/W
0
R/W
0
IOCFG[3:0]
R/W
0
R/W
0
R/W
0
Bits 15:12 – IOCFG[15:12] Interrupt-on-Change Flag bits
Value
Description
1
An enabled change was detected on the associated pin
0
No change was detected or the user cleared the detected change
Bits 9:6 – IOCFG[9:6] Interrupt-on-Change Flag bits
Value
Description
1
An enabled change was detected on the associated pin
0
No change was detected or the user cleared the detected change
Bits 3:0 – IOCFG[3:0] Interrupt-on-Change Flag bits
Value
Description
1
An enabled change was detected on the associated pin
0
No change was detected or the user cleared the detected change
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 372
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.71 Interrupt-on-Change Pull-up Enable PORTG Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
15
R/W
0
IOCPUG
0x6E8
14
13
IOCPUG[15:12]
R/W
R/W
0
0
7
6
IOCPUG[9:6]
R/W
R/W
0
0
5
12
11
10
3
2
R/W
0
4
R/W
0
9
8
IOCPUG[9:6]
R/W
R/W
0
0
1
IOCPUG[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 15:12 – IOCPUG[15:12] Interrupt-on-Change Pull-up Enable bits
Value
Description
1
Pull-up is enabled
0
Pull-up is disabled
Bits 9:6 – IOCPUG[9:6] Interrupt-on-Change Pull-up Enable bits
Value
Description
1
Pull-up is enabled
0
Pull-up is disabled
Bits 3:0 – IOCPUG[3:0] Interrupt-on-Change Pull-up Enable bits
Value
Description
1
Pull-up is enabled
0
Pull-up is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 373
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.72 Interrupt-on-Change Pull-Down Enable PORTG Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
15
R/W
0
IOCPDG
0x6EA
14
13
IOCPDG[15:12]
R/W
R/W
0
0
7
6
IOCPDG[9:6]
R/W
R/W
0
0
5
12
11
10
3
2
R/W
0
4
R/W
0
9
8
IOCPDG[9:6]
R/W
R/W
0
0
1
IOCPDG[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 15:12 – IOCPDG[15:12] Interrupt-on-Change Pull-Down Enable bits
Value
Description
1
Pull-down is enabled
0
Pull-down is disabled
Bits 9:6 – IOCPDG[9:6] Interrupt-on-Change Pull-Down Enable bits
Value
Description
1
Pull-down is enabled
0
Pull-down is disabled
Bits 3:0 – IOCPDG[3:0] Interrupt-on-Change Pull-Down Enable bits
Value
Description
1
Pull-down is enabled
0
Pull-down is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 374
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.73 Output Enable for PORTH Register
Name:
Offset:
Bit
TRISH
0x6EC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRISH0
R/W
1
Access
Reset
Bit
Access
Reset
Bit 0 – TRISH0 Output Enable bit
Value
Description
1
Pin is configured as input
0
Pin is configured as output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 375
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.74 Input Data for PORTH Register
Name:
Offset:
Bit
PORTH
0x6EE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RH0
R/W
1
Access
Reset
Bit
Access
Reset
Bit 0 – RH0 PORTH Data Input Value bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 376
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.75 Output Data for PORTH Register
Name:
Offset:
Bit
LATH
0x6F0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LATH0
R/W
0
Access
Reset
Bit
Access
Reset
Bit 0 – LATH0 Output Data bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 377
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.76 Open-Drain Enable for PORTH Register
Name:
Offset:
Bit
ODCH
0x6F2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ODCH0
R/W
0
Access
Reset
Bit
Access
Reset
Bit 0 – ODCH0 Open-Drain Enable bit
Value
Description
1
Open-drain is enabled on the pin
0
Open-drain is disabled on the pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 378
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.77 Interrupt-on-Change Positive Edge PORTH Register
Name:
Offset:
Bit
IOCPH
0x6F6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IOCPH0
R/W
0
Access
Reset
Bit
Access
Reset
Bit 0 – IOCPH0 Interrupt-on-Change Positive Edge Enable bit
Value
Description
1
Interrupt-on-change is enabled on the pin for a positive going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a positive going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 379
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.78 Interrupt-on-Change Negative Edge PORTH Register
Name:
Offset:
Bit
IOCNH
0x6F8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IOCNH0
R/W
0
Access
Reset
Bit
Access
Reset
Bit 0 – IOCNH0 Interrupt-on-Change Negative Edge Enable bit
Value
Description
1
Interrupt-on-change is enabled on the pin for a negative going edge; the associated status bit and
interrupt flag will be set upon detecting an edge
0
Interrupt-on-change is disabled on the pin for a negative going edge
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 380
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.79 Interrupt-on-Change Flag PORTH Register
Name:
Offset:
Bit
IOCFH
0x6FA
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IOCFH0
R/W
0
Access
Reset
Bit
Access
Reset
Bit 0 – IOCFH0 Interrupt-on-Change Flag bit
Value
Description
1
An enabled change was detected on the associated pin
0
No change was detected or the user cleared the detected change
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 381
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.80 Interrupt-on-Change Pull-up Enable PORTH Register
Bit
Name:
Offset:
IOCPUH
0x6FC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IOCPUH0
R/W
0
Access
Reset
Bit
Access
Reset
Bit 0 – IOCPUH0 Interrupt-on-Change Pull-up Enable bit
Value
Description
1
Pull-up is enabled
0
Pull-up is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 382
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.81 Interrupt-on-Change Pull-Down Enable PORTH Register
Bit
Name:
Offset:
IOCPDH
0x6FE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IOCPDH0
R/W
0
Access
Reset
Bit
Access
Reset
Bit 0 – IOCPDH0 Interrupt-on-Change Pull-Down Enable bit
Value
Description
1
Pull-down is enabled
0
Pull-down is disabled
11.5.82 Peripheral Pin Select Registers
Note: Input and Output register values can only be changed if IOLOCK (OSCCON[6]) = 0. See 11.4.4 Controlling
Configuration Changes for a specific command sequence.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 383
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.83 Peripheral Pin Select Input Register 0
Name:
Offset:
Bit
15
RPINR0
0x790
14
13
12
11
10
9
8
INT1R[5:0]
Access
Reset
Bit
7
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
5
4
3
2
1
0
6
Access
Reset
Bits 13:8 – INT1R[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 384
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.84 Peripheral Pin Select Input Register 1
Name:
Offset:
Bit
15
RPINR1
0x792
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
INT3R[5:0]
Access
Reset
Bit
7
R/W
0
R/W
0
R/W
0
5
4
3
6
INT2R[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – INT3R[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – INT2R[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 385
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.85 Peripheral Pin Select Input Register 2
Name:
Offset:
Bit
RPINR2
0x794
15
14
13
12
11
7
6
5
4
3
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
INT4R[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 5:0 – INT4R[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 386
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.86 Peripheral Pin Select Input Register 3
Name:
Offset:
Bit
15
RPINR3
0x796
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
T3CKR[5:0]
Access
Reset
Bit
7
R/W
0
R/W
0
R/W
0
5
4
3
6
T2CKR[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – T3CKR[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – T2CKR[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 387
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.87 Peripheral Pin Select Input Register 4
Name:
Offset:
Bit
15
RPINR4
0x798
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
T5CKR[5:0]
Access
Reset
Bit
7
R/W
0
R/W
0
R/W
0
5
4
3
6
T4CKR[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – T5CKR[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – T4CKR[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 388
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.88 Peripheral Pin Select Input Register 5
Name:
Offset:
Bit
15
RPINR5
0x79A
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
ICM2R[5:0]
Access
Reset
Bit
7
R/W
0
R/W
0
R/W
0
5
4
3
6
ICM1R[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – ICM2R[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – ICM1R[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 389
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.89 Peripheral Pin Select Input Register 6
Name:
Offset:
Bit
15
RPINR6
0x79C
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
ICM4R[5:0]
Access
Reset
Bit
7
R/W
0
R/W
0
R/W
0
5
4
3
6
ICM3R[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – ICM4R[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – ICM3R[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 390
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.90 Peripheral Pin Select Input Register 11
Bit
Name:
Offset:
RPINR11
0x7A6
15
14
Access
Reset
Bit
Access
Reset
7
13
12
R/W
0
R/W
0
5
4
R/W
0
R/W
0
6
11
10
OCFBR[5:0]
R/W
R/W
0
0
3
2
OCFAR[5:0]
R/W
R/W
0
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bits 13:8 – OCFBR[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – OCFAR[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 391
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.91 Peripheral Pin Select Input Register 12
Bit
Name:
Offset:
RPINR12
0x7A8
15
14
Access
Reset
Bit
Access
Reset
7
13
12
R/W
0
R/W
0
5
4
R/W
0
R/W
0
6
11
10
TCKIBR[5:0]
R/W
R/W
0
0
3
2
TCKIAR[5:0]
R/W
R/W
0
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bits 13:8 – TCKIBR[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – TCKIAR[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 392
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.92 Peripheral Pin Select Input Register 13
Bit
Name:
Offset:
RPINR13
0x7AA
15
14
Access
Reset
Bit
7
13
12
R/W
0
R/W
0
5
4
6
11
10
TMPRNR[5:0]
R/W
R/W
0
0
3
9
8
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
REFIR[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – TMPRNR[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – REFIR[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 393
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.93 Peripheral Pin Select Input Register 14
Bit
Name:
Offset:
RPINR14
0x7AC
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
ICM6R[5:0]
Access
Reset
Bit
7
R/W
0
R/W
0
R/W
0
5
4
3
6
ICM5R[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – ICM6R[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – ICM5R[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 394
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.94 Peripheral Pin Select Input Register 17
Bit
Name:
Offset:
RPINR17
0x7B2
15
14
13
12
11
10
9
8
U3RXR[5:0]
Access
Reset
Bit
7
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
5
4
3
2
1
0
6
Access
Reset
Bits 13:8 – U3RXR[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 395
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.95 Peripheral Pin Select Input Register 18
Bit
Name:
Offset:
RPINR18
0x7B4
15
14
Access
Reset
Bit
7
13
12
R/W
0
R/W
0
5
4
6
11
10
U1CTSR[5:0]
R/W
R/W
0
0
3
9
8
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
U1RXR[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – U1CTSR[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – U1RXR[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 396
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.96 Peripheral Pin Select Input Register 19
Bit
Name:
Offset:
RPINR19
0x7B6
15
14
Access
Reset
Bit
7
13
12
R/W
0
R/W
0
5
4
6
11
10
U2CTSR[5:0]
R/W
R/W
0
0
3
9
8
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
U2RXR[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – U2CTSR[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – U2RXR[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 397
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.97 Peripheral Pin Select Input Register 20
Bit
Name:
Offset:
RPINR20
0x7B8
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
SCK1R[5:0]
Access
Reset
Bit
7
R/W
0
R/W
0
R/W
0
5
4
3
6
SDI1R[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – SCK1R[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – SDI1R[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 398
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.98 Peripheral Pin Select Input Register 21
Bit
Name:
Offset:
RPINR21
0x7BA
15
14
Access
Reset
Bit
7
13
12
R/W
0
R/W
0
5
4
6
11
10
U3CTSR[5:0]
R/W
R/W
0
0
3
9
8
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
SS1R[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – U3CTSR[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – SS1R[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 399
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.99 Peripheral Pin Select Input Register 22
Bit
Name:
Offset:
RPINR22
0x7BC
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
SCK2R[5:0]
Access
Reset
Bit
7
R/W
0
R/W
0
R/W
0
5
4
3
6
SDI2R[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – SCK2R[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – SDI2R[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 400
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.100 Peripheral Pin Select Input Register 23
Bit
Name:
Offset:
RPINR23
0x7BE
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
TXCKR[5:0]
Access
Reset
Bit
7
R/W
0
R/W
0
R/W
0
5
4
3
6
SS2R[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – TXCKR[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – SS2R[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 401
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.101 Peripheral Pin Select Input Register 25
Bit
Name:
Offset:
RPINR25
0x7C2
15
14
Access
Reset
Bit
Access
Reset
7
13
12
R/W
0
R/W
0
5
4
R/W
0
R/W
0
6
11
10
CLCINBR[5:0]
R/W
R/W
0
0
3
2
CLCINAR[5:0]
R/W
R/W
0
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bits 13:8 – CLCINBR[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – CLCINAR[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 402
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.102 Peripheral Pin Select Input Register 26
Bit
Name:
Offset:
RPINR26
0x7C4
15
14
Access
Reset
Bit
Access
Reset
7
13
12
R/W
0
R/W
0
5
4
R/W
0
R/W
0
6
11
10
CLCINDR[5:0]
R/W
R/W
0
0
3
2
CLCINCR[5:0]
R/W
R/W
0
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bits 13:8 – CLCINDR[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – CLCINCR[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 403
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.103 Peripheral Pin Select Input Register 27
Bit
Name:
Offset:
RPINR27
0x7C6
15
14
Access
Reset
Bit
7
13
12
R/W
0
R/W
0
5
4
6
11
10
U4CTSR[5:0]
R/W
R/W
0
0
3
9
8
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
U4RXR[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – U4CTSR[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – U4RXR[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 404
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.104 Peripheral Pin Select Input Register 30
Bit
Name:
Offset:
RPINR30
0x7CC
15
14
13
12
11
7
6
5
4
3
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
SS4R[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 5:0 – SS4R[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 405
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.105 Peripheral Pin Select Input Register 31
Bit
Name:
Offset:
RPINR31
0x7CE
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
SCK4R[5:0]
Access
Reset
Bit
7
R/W
0
R/W
0
R/W
0
5
4
3
6
SDI4R[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 13:8 – SCK4R[5:0] Refer to Table 11-2 for bit field definitions
Bits 5:0 – SDI4R[5:0] Refer to Table 11-2 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 406
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.106 Peripheral Pin Select Output Register 0
Name:
Offset:
Bit
15
Access
Reset
Bit
Access
Reset
7
RPOR0
0x7D4
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
11
RP1R[6:0]
R/W
0
3
RP0R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP1R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP0R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 407
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.107 Peripheral Pin Select Output Register 1
Name:
Offset:
Bit
15
Access
Reset
Bit
Access
Reset
7
RPOR1
0x7D6
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
11
RP3R[6:0]
R/W
0
3
RP2R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP3R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP2R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 408
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.108 Peripheral Pin Select Output Register 2
Name:
Offset:
Bit
15
Access
Reset
Bit
Access
Reset
7
RPOR2
0x7D8
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
11
RP5R[6:0]
R/W
0
3
RP4R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP5R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP4R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 409
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.109 Peripheral Pin Select Output Register 3
Name:
Offset:
Bit
15
Access
Reset
Bit
Access
Reset
7
RPOR3
0x7DA
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
11
RP7R[6:0]
R/W
0
3
RP6R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP7R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP6R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 410
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.110 Peripheral Pin Select Output Register 4
Name:
Offset:
Bit
15
Access
Reset
Bit
Access
Reset
7
RPOR4
0x7DC
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
11
RP9R[6:0]
R/W
0
3
RP8R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP9R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP8R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 411
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.111 Peripheral Pin Select Output Register 5
Name:
Offset:
Bit
15
Access
Reset
Bit
Access
Reset
7
RPOR5
0x7DE
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
11
RP11R[6:0]
R/W
0
3
RP10R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP11R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP10R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 412
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.112 Peripheral Pin Select Output Register 6
Name:
Offset:
Bit
15
Access
Reset
Bit
Access
Reset
7
RPOR6
0x7E0
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
11
RP13R[6:0]
R/W
0
3
RP12R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP13R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP12R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 413
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.113 Peripheral Pin Select Output Register 7
Name:
Offset:
Bit
15
Access
Reset
Bit
Access
Reset
7
RPOR7
0x7E2
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
11
RP15R[6:0]
R/W
0
3
RP14R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP15R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP14R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 414
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.114 Peripheral Pin Select Output Register 8
Name:
Offset:
Bit
15
Access
Reset
Bit
Access
Reset
7
RPOR8
0x7E4
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
11
RP17R[6:0]
R/W
0
3
RP16R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP17R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP16R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 415
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.115 Peripheral Pin Select Output Register 9
Name:
Offset:
Bit
15
Access
Reset
Bit
Access
Reset
7
RPOR9
0x7E6
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
11
RP19R[6:0]
R/W
0
3
RP18R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP19R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP18R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 416
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.116 Peripheral Pin Select Output Register 10
Bit
Name:
Offset:
RPOR10
0x7E8
15
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
7
11
RP21R[6:0]
R/W
0
3
RP20R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP21R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP20R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 417
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.117 Peripheral Pin Select Output Register 11
Bit
Name:
Offset:
RPOR11
0x7EA
15
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
7
11
RP23R[6:0]
R/W
0
3
RP22R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP23R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP22R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 418
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.118 Peripheral Pin Select Output Register 12
Bit
Name:
Offset:
RPOR12
0x7EC
15
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
7
11
RP25R[6:0]
R/W
0
3
RP24R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP25R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP24R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 419
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.119 Peripheral Pin Select Output Register 13
Bit
Name:
Offset:
RPOR13
0x7EE
15
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
7
11
RP27R[6:0]
R/W
0
3
RP26R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP27R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP26R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 420
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.120 Peripheral Pin Select Output Register 14
Bit
Name:
Offset:
RPOR14
0x7F0
15
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
7
11
RP29R[6:0]
R/W
0
3
RP28R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP29R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP28R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 421
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.121 Peripheral Pin Select Output Register 15
Bit
Name:
Offset:
RPOR15
0x7F2
15
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
7
11
RP31R[6:0]
R/W
0
3
RP30R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP31R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP30R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 422
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.122 Peripheral Pin Select Output Register 16
Bit
Name:
Offset:
RPOR16
0x7F4
15
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
7
11
RP33R[6:0]
R/W
0
3
RP32R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP33R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP32R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 423
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.123 Peripheral Pin Select Output Register 17
Bit
Name:
Offset:
RPOR17
0x7F6
15
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
7
11
RP35R[6:0]
R/W
0
3
RP34R[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 14:8 – RP35R[6:0] Refer to Table 11-3 for bit field definitions
Bits 6:0 – RP34R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 424
PIC24FJ512GU410 Family Data Sheet
I/O Ports
11.5.124 Peripheral Pin Select Output Register 18
Bit
Name:
Offset:
RPOR18
0x7F8
15
14
13
12
11
10
9
8
7
6
5
4
2
1
0
R/W
0
R/W
0
R/W
0
3
RP36R[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 6:0 – RP36R[6:0] Refer to Table 11-3 for bit field definitions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 425
PIC24FJ512GU410 Family Data Sheet
Timer1
12.
Timer1
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information, refer to “Timers” (www.microchip.com/DS39704) in the
“dsPIC33/PIC24 Family Reference Manual”). The information in this data sheet supersedes the information in the
FRM.
Timer1 can operate in three modes:
•
•
•
16-Bit Timer
16-Bit Synchronous Counter
16-Bit Asynchronous Counter
Timer1 also supports these features:
•
•
•
•
Timer Gate Operation
Selectable Prescaler Settings
Timer Operation during CPU Idle and Sleep modes
Interrupt on 16-Bit Period Register Match or Falling Edge of External Gate Signal
Figure 12-1 shows a block diagram of the 16-bit timer module.
To configure Timer1 for operation:
1.
2.
3.
4.
5.
6.
Select the timer prescaler ratio using the TCKPS[1:0] bits.
Set the Clock and Gating modes using the TCS, TECS[1:0] and TGATE bits.
Set or clear the TSYNC bit to configure synchronous or asynchronous operation.
Load the timer period value into the PR1 register.
If interrupts are required, set the Timer1 Interrupt Enable bit, T1IE. Use the Timer1 Interrupt Priority bits,
T1IP[2:0], to set the interrupt priority.
Set the TON bit (= 1).
Figure 12-1. 16-Bit Timer1 Module Block Diagram
TECS[1:0]
SOSC
T1CK
LPRC
TSYNC
TGATE
TCKPS[1:0]
TxCK
Synchronization
(On/Off)
Gating
(On/Off)
Prescaler
(1,8,64,256)
Peripheral
Clock
T1CK
Peripheral
Clock
TCS
Reset
Interrupt
(Set T1IF)
TMR1
Comparator
PR1
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 426
PIC24FJ512GU410 Family Data Sheet
Timer1
12.1
Timer1 Registers
Offset
Name
0x00
...
0x018F
Reserved
0x0190
TMR1
0x0192
PR1
0x0194
T1CON
Bit Pos.
7:0
15:8
7:0
15:8
7:0
15:8
7
6
5
4
3
2
1
TSYNC
TCS
0
TMR1[7:0]
TMR1[15:8]
PR1[7:0]
PR1[15:8]
TGATE
TON
© 2019-2020 Microchip Technology Inc.
TCKPS[1:0]
TSIDL
Datasheet
TECS[1:0]
DS30010203C-page 427
PIC24FJ512GU410 Family Data Sheet
Timer1
12.1.1
Timer1 Counter Register
Name:
Offset:
Bit
15
TMR1
0x190
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMR1[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TMR1[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMR1[15:0] Timer1 Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 428
PIC24FJ512GU410 Family Data Sheet
Timer1
12.1.2
Timer1 Period Register
Name:
Offset:
Bit
15
PR1
0x192
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PR1[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PR1[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PR1[15:0] Timer1 Period Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 429
PIC24FJ512GU410 Family Data Sheet
Timer1
12.1.3
Timer1 Control Register
Name:
Offset:
T1CON
0x194
Note:
1. Changing the value of T1CON while the timer is running (TON = 1) causes the timer prescale counter to reset
and is not recommended.
Bit
Access
Reset
Bit
Access
Reset
15
TON
R/W
0
14
7
TGATE
R/W
0
6
13
TSIDL
R/W
0
12
5
4
11
9
8
TECS[1:0]
3
TCKPS[1:0]
R/W
0
10
R/W
0
2
TSYNC
R/W
0
R/W
0
R/W
0
1
TCS
R/W
0
0
Bit 15 – TON Timer1 On bit(1)
Value
Description
1
Starts 16-bit Timer1
0
Stops 16-bit Timer1
Bit 13 – TSIDL Timer1 Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bits 9:8 – TECS[1:0] Timer1 Extended Clock Select bits (selected when TCS = 1)
Value
Description
11
Generic timer (TxCK) external input
10
LPRC Oscillator
01
T1CK external clock input
00
SOSC
Bit 7 – TGATE Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
Value
Description
1
Gated time accumulation is enabled
0
Gated time accumulation is disabled
Bits 5:4 – TCKPS[1:0] Timer1 Input Clock Prescale Select bits
Value
Description
11
1:256
10
1:64
01
1:8
00
1:1
Bit 2 – TSYNC Timer1 External Clock Input Synchronization Select bit
When TCS = 0:
This bit is ignored.
When TCS = 1:
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 430
PIC24FJ512GU410 Family Data Sheet
Timer1
Value
1
0
Description
Synchronizes the external clock input
Does not synchronize the external clock input
Bit 1 – TCS Timer1 Clock Source Select bit
Value
Description
1
External clock source selected by TECS[1:0]
0
Internal peripheral clock (FOSC)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 431
PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.
Timer2/3 and Timer4/5
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information, refer to “Timers” (DS39704) in the “dsPIC33/PIC24 Family
Reference Manual”, which is available from the Microchip website (www.microchip.com). The information in this data
sheet supersedes the information in the FRM.
The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as independent, 16-bit timers
with selectable operating modes.
As a 32-bit timer, Timer2/3 or Timer4/5 can operate in four modes:
• Two Independent 16-Bit Synchronous Timers
• Two Independent 16-Bit Synchronous Counters
• Single 32-Bit Synchronous Timer
• Single 32-Bit Synchronous Counter
They also support these features:
•
•
•
•
•
Timer Gate Operation
Selectable Prescaler Settings
Timer Operation during Idle mode
Interrupt on a 32-Bit Period Register Match
A/D Event Trigger
Individually, all of the timers can function as synchronous timers or counters. These timers cannot operate in Sleep
mode. The operating modes and enabled features are determined by setting the appropriate bit(s) in the T2CON,
T3CON, T4CON, T5CON registers.
For 32-bit timer/counter operation, Timer2 and Timer4 are the least significant word; Timer3 and Timer5 are the most
significant word of the 32-bit timer.
Note: For 32-bit operation, T3CON and T5CON control bits are ignored. Only T2CON and T4CON control bits are
used for setup and control. Timer2 and Timer4 clocks and gate inputs are utilized for the 32-bit timer modules, but an
interrupt is generated with the Timer3 and Timer5 interrupt flags.
To configure Timer2/3 or Timer4/5 for 32-bit operation:
1.
Set the T32 bit (T2CON[3] = 1 or T4CON[3] = 1).
2.
3.
Select the prescaler ratio for Timer2 or Timer4 using the TCKPS[1:0] bits.
Set the Clock and Gating modes using the TCS and TGATE bits. If TCS is set to an external clock, RPINRx
(TyCK) must be configured to an available RPn/RPIn pin. For more information, see 11.4 Peripheral Pin
Select (PPS).
Load the timer period value. PR3 or PR5 will contain the most significant word (msw) of the value, while PR2
or PR4 contains the least significant word (lsw).
If interrupts are required, set the interrupt enable bit, T3IE or T5IE. Use the priority bits, T3IP[2:0] or T5IP[2:0],
to set the interrupt priority. Note that while Timer2 or Timer4 controls the timer, the interrupt appears as a
Timer3 or Timer5 interrupt.
Set the TON bit (= 1).
4.
5.
6.
The timer value, at any point, is stored in the register pair, TMR3/2 (or TMR5/4). TMR3 (or TMR5) always contains
the most significant word of the count, while TMR2 (or TMR4) contains the least significant word. The 32-bit timer is
shown in Figure 13-1.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 432
PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
Figure 13-1. 32-Bit Timer Block Diagram
TECS[1:0]
SOSC
T2CK (T4CK)
TGATE
TCKPS[1:0]
Synchronization
Gating
(On/Off)
Prescaler
(1,8,64,256)
Peripheral
Clock
T2CK (T4CK)
LPRC
TxCK
Peripheral
Clock
TCS
Reset
Interrupt
Set T3IF (T5IF)
TMR3
(TMR5)
TMR2
(TMR4)
Comparator
PR3
(PR5)
PR2
(PR4)
To configure any of the timers for individual 16-bit operation:
1.
2.
3.
4.
5.
6.
Clear the T32 bit (T2CON[3] for Timer2 and Timer3 or T4CON[3] for Timer4 and Timer5).
Select the timer prescaler ratio using the TCKPS[1:0] bits.
Set the Clock and Gating modes using the TCS and TGATE bits. See 11.4 Peripheral Pin Select (PPS) for
more information.
Load the timer period value into the PRx register.
If interrupts are required, set the Timerx Interrupt Enable bit, TxIE. Use the Timerx Interrupt Priority bits,
TxIP[2:0], to set the interrupt priority.
Set the TON bit (= 1).
The 16-bit timer is shown in Figure 13-2.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 433
PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
Figure 13-2. 16-Bit Timer Block Diagram
TECS[1:0]
SOSC
T2CK (T3CK,
T4CK or T5CK)
LPRC
TxCK
Synchronization
Peripheral
Clock
TCS
Peripheral
Clock
Reset
Interrupt
Set T2IF (T3IF,
T4IF or T5IF)
TGATE
TCKPS[1:0]
Gating
(On/Off)
Prescaler
(1,8,64,256)
T2CK
(T3CK, T4CK, T5CK)
TMR2
(TMR3, TMR4
or TMR5)
Comparator
PR2
(PR3, PR4
or PR5)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 434
PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1
Timer2/3 and Timer4/5 Registers
Offset
Name
0x00
...
0x0193
Reserved
0x0194
TMR4
0x0196
TMR2
0x0198
TMR3HLD
0x019A
TMR3
0x019C
PR2
0x019E
PR3
0x01A0
T2CON
0x01A2
T3CON
0x01A4
...
0x01A5
Reserved
0x01A6
TMR5HLD
0x01A8
TMR5
0x01AA
PR4
0x01AC
PR5
0x01AE
T4CON
0x01B0
T5CON
Bit Pos.
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7
6
5
4
3
TGATE
TON
TGATE
TON
TMR4[7:0]
TMR4[15:8]
TMR2[7:0]
TMR2[15:8]
TMR3HLD[7:0]
TMR3HLD[15:8]
TMR3[7:0]
TMR3[15:8]
PR2[7:0]
PR2[15:8]
PR3[7:0]
PR3[15:8]
TCKPS[1:0]
T32
TSIDL
TCKPS[1:0]
TSIDL
TGATE
TON
TGATE
TON
TMR5HLD[7:0]
TMR5HLD[15:8]
TMR5[7:0]
TMR5[15:8]
PR4[7:0]
PR4[15:8]
PR5[7:0]
PR5[15:8]
TCKPS[1:0]
T32
TSIDL
TCKPS[1:0]
TSIDL
© 2019-2020 Microchip Technology Inc.
Datasheet
2
1
TSYNC
TCS
TSYNC
TCS
0
TECS[1:0]
TECS[1:0]
TSYNC
TCS
TSYNC
TCS
TECS[1:0]
TECS[1:0]
DS30010203C-page 435
PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1.1
Timer2 Counter Register
Name:
Offset:
Bit
15
TMR2
0x196
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMR2[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TMR2[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMR2[15:0] Timer2 Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 436
PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1.2
Timer3 Holding Register (for 32-bit timer operations only)
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
TMR3HLD
0x198
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
TMR3HLD[15:8]
R/W
R/W
0
0
4
3
TMR3HLD[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMR3HLD[15:0] Timer3 Holding Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 437
PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1.3
Timer3 Counter Register
Name:
Offset:
Bit
15
TMR3
0x19A
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMR3[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TMR3[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMR3[15:0] Timer3 Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 438
PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1.4
Timer2 Period Register
Name:
Offset:
Bit
15
PR2
0x19C
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PR2[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PR2[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PR2[15:0] Timer2 Period Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 439
PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1.5
Timer3 Period Register
Name:
Offset:
Bit
15
PR3
0x19E
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PR3[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PR3[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PR3[15:0] Timer3 Period Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 440
PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1.6
Timer2 Control Register
Name:
Offset:
T2CON
0x1A0
Note:
1. Changing the value of T2CON while the timer is running (TON = 1) causes the timer prescale counter to reset
and is not recommended.
Bit
Access
Reset
Bit
Access
Reset
15
TON
R/W
0
14
7
TGATE
R/W
0
6
13
TSIDL
R/W
0
12
5
4
11
9
8
TECS[1:0]
3
T32
R/W
0
TCKPS[1:0]
R/W
0
10
R/W
0
2
TSYNC
R/W
0
R/W
0
R/W
0
1
TCS
R/W
0
0
Bit 15 – TON Timer2 On bit(1)
Value
Description
1
Starts 16-bit Timer
0
Stops 16-bit Timer
Bit 13 – TSIDL Timer2 Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bits 9:8 – TECS[1:0] Timer2 Extended Clock Select bits (selected when TCS = 1)
Value
Description
11
Generic timer (TxCK) external input
10
LPRC Oscillator
01
T1CK external clock input
00
SOSC
Bit 7 – TGATE Timer2 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
Value
Description
1
Gated time accumulation is enabled
0
Gated time accumulation is disabled
Bits 5:4 – TCKPS[1:0] Timer2 Input Clock Prescale Select bits
Value
Description
11
1:256
10
1:64
01
1:8
00
1:1
Bit 3 – T32 32-Bit Timer Mode Select bit
In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.
Value
Description
1
Timer2 and Timer3 form a single 32-bit timer
0
Timer2 and Timer3 act as two 16-bit timers
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 441
PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
Bit 2 – TSYNC Timer2 External Clock Input Synchronization Select bit(1)
When TCS = 0:
This bit is ignored.
When TCS = 1:
Value
Description
1
Synchronizes the external clock input
0
Does not synchronize the external clock input
Bit 1 – TCS Timer2 Clock Source Select bit
Value
Description
1
External clock source selected by TECS[1:0]
0
Internal peripheral clock (FOSC)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 442
PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1.7
Timer3 Control Register
Name:
Offset:
T3CON
0x1A2
Note:
1. Changing the value of T3CON while the timer is running (TON = 1) causes the timer prescale counter to reset
and is not recommended.
Bit
Access
Reset
Bit
Access
Reset
15
TON
R/W
0
14
7
TGATE
R/W
0
6
13
TSIDL
R/W
0
12
5
4
11
9
8
TECS[1:0]
3
TCKPS[1:0]
R/W
0
10
R/W
0
2
TSYNC
R/W
0
R/W
0
R/W
0
1
TCS
R/W
0
0
Bit 15 – TON Timer3 On bit(1)
Value
Description
1
Starts 16-bit Timer
0
Stops 16-bit Timer
Bit 13 – TSIDL Timer3 Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bits 9:8 – TECS[1:0] Timer3 Extended Clock Select bits (selected when TCS = 1)
Value
Description
11
Generic timer (TxCK) external input
10
LPRC Oscillator
01
T1CK external clock input
00
SOSC
Bit 7 – TGATE Timer3 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
Value
Description
1
Gated time accumulation is enabled
0
Gated time accumulation is disabled
Bits 5:4 – TCKPS[1:0] Timer3 Input Clock Prescale Select bits
Value
Description
11
1:256
10
1:64
01
1:8
00
1:1
Bit 2 – TSYNC Timer3 External Clock Input Synchronization Select bit(1)
When TCS = 0:
This bit is ignored.
When TCS = 1:
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PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
Value
1
0
Description
Synchronizes the external clock input
Does not synchronize the external clock input
Bit 1 – TCS Timer3 Clock Source Select bit
Value
Description
1
External clock source selected by TECS[1:0]
0
Internal peripheral clock (FOSC)
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PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1.8
Timer4 Counter Register
Name:
Offset:
Bit
15
TMR4
0x194
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMR4[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TMR4[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMR4[15:0] Timer4 Value bits
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PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1.9
Timer5 Holding Register (for 32-bit timer operations only)
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
TMR5HLD
0x1A6
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
TMR5HLD[15:8]
R/W
R/W
0
0
4
3
TMR5HLD[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMR5HLD[15:0] Timer5 Holding Value bits
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1.10 Timer5 Counter Register
Name:
Offset:
Bit
15
TMR5
0x1A8
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMR5[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TMR5[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMR5[15:0] Timer5 Value bits
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1.11 Timer4 Period Register
Name:
Offset:
Bit
15
PR4
0x1AA
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PR4[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PR4[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PR4[15:0] Timer4 Period Value bits
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1.12 Timer5 Period Register
Name:
Offset:
Bit
15
PR5
0x1AC
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PR5[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PR5[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PR5[15:0] Timer5 Period Value bits
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1.13 Timer4 Control Register
Name:
Offset:
T4CON
0x1AE
Note:
1. Changing the value of T4CON while the timer is running (TON = 1) causes the timer prescale counter to reset
and is not recommended.
Bit
Access
Reset
Bit
Access
Reset
15
TON
R/W
0
14
7
TGATE
R/W
0
6
13
TSIDL
R/W
0
12
5
4
11
9
8
TECS[1:0]
3
T32
R/W
0
TCKPS[1:0]
R/W
0
10
R/W
0
2
TSYNC
R/W
0
R/W
0
R/W
0
1
TCS
R/W
0
0
Bit 15 – TON Timer4 On bit(1)
Value
Description
1
Starts 16-bit Timer
0
Stops 16-bit Timer
Bit 13 – TSIDL Timer4 Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bits 9:8 – TECS[1:0] Timer4 Extended Clock Select bits (selected when TCS = 1)
Value
Description
11
Generic timer (TxCK) external input
10
LPRC Oscillator
01
T1CK external clock input
00
SOSC
Bit 7 – TGATE Timer4 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
Value
Description
1
Gated time accumulation is enabled
0
Gated time accumulation is disabled
Bits 5:4 – TCKPS[1:0] Timer4 Input Clock Prescale Select bits
Value
Description
11
1:256
10
1:64
01
1:8
00
1:1
Bit 3 – T32 32-Bit Timer Mode Select bit
In 32-bit mode, T5CON control bits do not affect 32-bit timer operation.
Value
Description
1
Timer4 and Timer5 form a single 32-bit timer
0
Timer4 and Timer5 act as two 16-bit timers
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
Bit 2 – TSYNC Timer4 External Clock Input Synchronization Select bit(1)
When TCS = 0:
This bit is ignored.
When TCS = 1:
Value
Description
1
Synchronizes the external clock input
0
Does not synchronize the external clock input
Bit 1 – TCS Timer4 Clock Source Select bit
Value
Description
1
External clock source selected by TECS[1:0]
0
Internal peripheral clock (FOSC)
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
13.1.14 Timer5 Control Register
Name:
Offset:
T5CON
0x1B0
Note:
1. Changing the value of T5CON while the timer is running (TON = 1) causes the timer prescale counter to reset
and is not recommended.
Bit
Access
Reset
Bit
Access
Reset
15
TON
R/W
0
14
7
TGATE
R/W
0
6
13
TSIDL
R/W
0
12
5
4
11
9
8
TECS[1:0]
3
TCKPS[1:0]
R/W
0
10
R/W
0
2
TSYNC
R/W
0
R/W
0
R/W
0
1
TCS
R/W
0
0
Bit 15 – TON Timer5 On bit(1)
Value
Description
1
Starts 16-bit Timer
0
Stops 16-bit Timer
Bit 13 – TSIDL Timer5 Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bits 9:8 – TECS[1:0] Timer5 Extended Clock Select bits (selected when TCS = 1)
Value
Description
11
Generic timer (TxCK) external input
10
LPRC Oscillator
01
T1CK external clock input
00
SOSC
Bit 7 – TGATE Timer5 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
Value
Description
1
Gated time accumulation is enabled
0
Gated time accumulation is disabled
Bits 5:4 – TCKPS[1:0] Timer5 Input Clock Prescale Select bits
Value
Description
11
1:256
10
1:64
01
1:8
00
1:1
Bit 2 – TSYNC Timer5 External Clock Input Synchronization Select bit(1)
When TCS = 0:
This bit is ignored.
When TCS = 1:
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PIC24FJ512GU410 Family Data Sheet
Timer2/3 and Timer4/5
Value
1
0
Description
Synchronizes the external clock input
Does not synchronize the external clock input
Bit 1 – TCS Timer5 Clock Source Select bit
Value
Description
1
External clock source selected by TECS[1:0]
0
Internal peripheral clock (FOSC)
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Datasheet
DS30010203C-page 453
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.
Capture/Compare/PWM/Timer Modules (MCCP)
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information, refer to “Capture/Compare/PWM/Timer (MCCP and
SCCP)” (DS30003035) in the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
website (www.microchip.com). The information in this data sheet supersedes the information in the FRM.
PIC24FJ512GU410 family devices include several Capture/Compare/PWM/Timer base modules, which provide the
functionality of three different peripherals of earlier PIC24F devices. The module can operate in one of three major
modes:
•
•
•
General Purpose Timer
Input Capture
Output Compare/PWM
This family of devices features eight instances of the MCCP module. MCCP1-3 provides up to six outputs and an
extended range of power control features, whereas MCCP4-MCCP8 support two outputs.
The MCCPx modules can be operated only in one of the three major modes at any time. The other modes are not
available unless the module is reconfigured for the new mode.
A conceptual block diagram for the module is shown in Figure 14-1. All three modules share a time base generator
and a common Timer register pair (CCPxTMRH/L); other shared hardware components are added as a particular
mode requires.
Each module has a total of eight control and status registers:
•
•
•
•
•
•
•
CCPxCON1L
CCPxCON1H
CCPxCON2L
CCPxCON2H
CCPxCON3L
CCPxCON3H
CCPxSTATL
Each module also includes eight buffer/counter registers that serve as Timer Value registers or data holding buffers:
•
•
•
•
•
CCPxTMRH/CCPxTMRL (Timer High/Low Counters)
CCPxPRH/CCPxPRL (Timer Period High/Low)
CCPxRAH/CCPxRAL (Primary Output Compare Data Buffer)
CCPxRBH/CCPxRBL (Secondary Output Compare Data Buffer)
CCPxBUFH/CCPxBUFL (Input Capture High/Low Buffers)
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Figure 14-1. MCCP Conceptual Block Diagram
CCPxIF
External
Capture Input
Input Capture
CCTxIF
Sync/Trigger Out
Special Trigger (to ADC)
Clock
Sources
Time Base
Generator
CCPxTMRH/L
Compare/PWM
Output(s)
T32
CCSEL
MOD
Sync and
Gating
Sources
14.1
16/32-Bit
Timer
Output Compare/
PWM
OCFA/OCFB
Time Base Generator
The Timer Clock Generator (TCG) generates a clock for the module’s internal time base using one of the clock
signals already available on the microcontroller. This is used as the time reference for the module in its three major
modes. The internal time base is shown in Figure 14-2.
There are eight inputs available to the clock generator, which are selected using the CLKSEL[2:0] bits
(CCPxCON1L[10:8]). Available sources include the FRC and LPRC, the Secondary Oscillator and the TCLKI external
clock inputs. The system clock is the default source (CLKSEL[2:0] = 000). On PIC24FJ512GU410 family devices,
clock sources to the MCCPx module can be synchronized with the system clock. As a result, when clock sources are
selected, clock input timing restrictions or module operating restrictions may exist.
Figure 14-2. Timer Clock Generator
Note:
1.
14.2
Gating available in Timer modes only.
General Purpose Timer
Timer mode is selected when CCSEL = 0 and MOD[3:0] = 0000. The timer can function as a 32-bit timer or a dual
16-bit timer, depending on the setting of the T32 bit (Table 14-1).
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Table 14-1. Timer Operation Mode
T32 (CCPxCON1L[5])
Operating Mode
0
Dual Timer Mode (16-bit)
1
Timer Mode (32-bit)
Dual 16-Bit Timer mode (Figure 14-3) provides a simple timer function with two independent 16-bit timer/counters.
The primary timer uses the CCPxTMRL and CCPxPRL registers. Only the primary timer can interact with other
modules on the device. It generates the MCCPx Sync out signals for use by other MCCPx modules. It can also use
the SYNC[4:0] bits’ signal generated by other modules.
The secondary timer uses the CCPxTMRH and CCPxPRH registers. It is intended to be used only as a periodic
interrupt source for scheduling CPU events. It does not generate an output Sync/Trigger mode signal like the primary
time base. In Dual Timer mode, the Timer Period High register, CCPxPRH, generates the MCCPx compare event
(CCPxIF) used by many other modules on the device.
The 32-Bit Timer mode (Figure 14-4) uses the CCPxTMRL and CCPxTMRH registers, together, as a single 32-bit
timer. When CCPxTMRL overflows, CCPxTMRH increments by one. This mode provides a simple timer function
when it is important to track long time periods. Note that the T32 bit (CCPxCON1L[5]) should be set before the
CCPxTMRL or CCPxPRH registers are written to initialize the 32-bit timer.
14.2.1
Sync and Trigger Operation
In both 16-bit and 32-bit modes, the timer can also function in either Synchronization (“Sync”) or Trigger mode
operation. Both use the SYNC[4:0] bits (CCPxCON1H[4:0]) to determine the input signal source. The difference is
how that signal affects the timer.
In Sync mode operation, the Timer Reset or clear occurs when the input selected by SYNC[4:0] is asserted. The
timer immediately begins to count again from zero unless it is held for some other reason. Sync operation is used
whenever the TRIGEN bit (CCPxCON1H[7]) is cleared. The SYNC[4:0] bits can have any value except ‘11111’.
In Trigger mode operation, the timer is held in Reset until the input selected by SYNC[4:0] is asserted; when it occurs,
the timer starts counting. Trigger operation is used whenever the TRIGEN bit is set. In Trigger mode, the timer will
continue running after a trigger event as long as the CCPTRIG bit (CCPxSTATL[7]) is set. To clear CCPTRIG, the
TRCLR bit (CCPxSTATL[5]) must be set to clear the trigger event, reset the timer and hold it at zero until another
trigger event occurs. On PIC24FJ512GU410 family devices, Trigger mode operation can only be used when the
peripheral clock is the time base source (CLKSEL[2:0] = 000).
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Figure 14-3. Dual 16-Bit Timer Mode
Figure 14-4. 32-Bit Timer Mode
14.3
Output Compare Mode
Output Compare mode compares the Timer register value with the value of one or two Compare registers, depending
on its mode of operation. The output compare module, on compare match events, has the ability to generate a single
®
output transition or a train of output pulses. Like most PIC MCU peripherals, the output compare module can also
generate interrupts on a compare match event.
Table 14-2 shows the various modes available in Output Compare modes. Figure 14-5 depicts a simplified block
diagram of the Output Compare mode.
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PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Table 14-2. Output Compare/PWM Modes
MOD[3:0] (CCPxCON1L[3:0])
T32 (CCPxCON1L[5])
Operating Mode
0001
0
Output High on Compare
(16-bit)
0001
1
Output High on Compare
(32-bit)
0010
0
Output Low on Compare
(16-bit)
0010
1
Output Low on Compare
(32-bit)
0011
0
Output Toggle on Compare
(16-bit)
0011
1
Output Toggle on Compare
(32-bit)
0100
0
Dual Edge Compare (16-bit)
Dual Edge Mode
0101
0
Dual Edge Compare
(16-bit buffered)
PWM Mode
0110
0
Center-Aligned Pulse
(16-bit buffered)(1)
Center PWM Mode
0111
0
Variable Frequency Pulse
(16-bit)(1)
1111
0
External Input Source Mode (16-bit)
Single Edge Mode
Note:
1.
Available only on MCCP1-MCCP3 modules.
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Figure 14-5. Output Compare Block Diagram
14.4
Input Capture Mode
Input Capture mode is used to capture a timer value from an independent timer base upon an event on an input pin
or other internal trigger source. The input capture features are useful in applications requiring frequency (time period)
and pulse measurement. Figure 14-6 depicts a simplified block diagram of the Input Capture mode.
Input Capture mode uses a dedicated 16/32-bit, synchronous, up counting timer for the capture function. The timer
value is written to the FIFO when a capture event occurs. The internal value may be read (with a synchronization
delay) using the CCPxTMRH/L registers.
To use Input Capture mode, the CCSEL bit (CCPxCON1L[4]) must be set. The T32 and MOD[3:0] bits are used to
select the proper Capture mode, as shown in Table 14-3.
Table 14-3. Input Capture Modes
MOD[3:0] (CCPxCON1L[3:0])
T32 (CCPxCON1L[5])
0000
0
Edge Detect (16-bit capture)
0000
1
Edge Detect (32-bit capture)
0001
0
Every Rising (16-bit capture)
0001
1
Every Rising (32-bit capture)
0010
0
Every Falling (16-bit capture)
0010
1
Every Falling (32-bit capture)
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Datasheet
Operating Mode
DS30010203C-page 459
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
...........continued
MOD[3:0] (CCPxCON1L[3:0])
T32 (CCPxCON1L[5])
Operating Mode
0011
0
Every Rise/Fall (16-bit capture)
0011
1
Every Rise/Fall (32-bit capture)
0100
0
Every 4th Rising (16-bit capture)
0100
1
Every 4th Rising (32-bit capture)
0101
0
Every 16th Rising (16-bit capture)
0101
1
Every 16th Rising (32-bit capture)
Figure 14-6. Input Capture Block Diagram
ICx Clock
Interrupt
Select
Set CCPxIF
Increment
4-Level FIFO Buffer
ICS[2:0]
14.5
Auxiliary Output
The MCCPx modules have an auxiliary (secondary) output that provides other peripherals access to internal module
signals. The auxiliary output is intended to connect to other MCCPx modules, or other digital peripherals, to provide
these types of functions:
•
•
•
Time Base Synchronization
Peripheral Trigger and Clock Inputs
Signal Gating
The type of output signal is selected using the AUXOUT[1:0] control bits (CCPxCON2H[4:3]). The type of output
signal is also dependent on the module operating mode, as shown in Table 14-4.
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PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Table 14-4. Auxiliary Output
AUXOUT[1:0]
CCSEL
MOD[3:0]
Comments
Signal Description
00
x
xxxx
Auxiliary Output Disabled
No Output
01
0
0000
Time Base Modes
Time Base Period Reset or Rollover
10
Special Event Trigger Output
11
No Output
01
0
10
Output Compare Modes
1
xxxx
Time Base Period Reset or Rollover
Output Compare Event Signal
1111
11
01
0001
through
Output Compare Signal
Input Capture Modes
Time Base Period Reset or Rollover
10
Reflects the Value of the ICDIS bit
11
Input Capture Event Signal
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PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6
MCCP Registers
Offset
Name
0x00
...
0x0247
Reserved
0x0248
CCP8CON1L
0x024A
CCP8CON1H
0x024C
CCP8CON2L
0x024E
CCP8CON2H
0x0250
CCP8CON3L
0x0252
CCP8CON3H
0x0254
CCP8STATL
0x0256
...
0x0257
Reserved
0x0258
CCP8TMRL
0x025A
CCP8TMRH
0x025C
CCP8PRL
0x025E
CCP8PRH
0x0260
CCP8RA
0x0262
...
0x0263
Reserved
0x0264
CCP8RB
0x0266
...
0x0267
Reserved
0x0268
CCP8BUFL
0x026A
CCP8BUFH
0x026C
CCP1CON1L
0x026E
CCP1CON1H
0x0270
CCP1CON2L
0x0272
CCP1CON2H
0x0274
CCP1CON3L
0x0276
CCP1CON3H
0x0278
CCP1STATL
Bit Pos.
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7
6
TMRPS[1:0]
CCPON
TRIGEN
ONESHOT
OPSSRC
RTRGEN
5
4
3
T32
CCPSIDL
ALTSYNC
CCSEL
CCPSLP
TMRSYNC
TRSET
ICS[2:0]
POLACE
OSCNT[2:0]
TRCLR
POLBDF
ASEVT
PSSACE[1:0]
SCEVT
TMRL[7:0]
TMRL[15:8]
TMRH[23:16]
TMRH[31:24]
PRL[7:0]
PRL[15:8]
PRH[23:16]
PRH[31:24]
CMP[7:0]
CMP[15:8]
7:0
15:8
CMP[7:0]
CMP[15:8]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
BUF[7:0]
BUF[15:8]
BUF[23:16]
BUF[31:24]
CCSEL
CCPSLP
TMRSYNC
T32
CCPSIDL
ALTSYNC
© 2019-2020 Microchip Technology Inc.
TRSET
ICDIS
ICGARM
PSSBDF[1:0]
OUTM[2:0]
ICOV
ICBNE
MOD[3:0]
CLKSEL[2:0]
SYNC[4:0]
OPS3[3:0]
ASDG[7:0]
SSDG
AUXOUT[1:0]
PWMRSEN
ASDGM
ICGSM[1:0]
OENSYNC
OETRIG
CCPTRIG
0
OC[F:A]EN
DT[4:0]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
TMRPS[1:0]
CCPON
TRIGEN
ONESHOT
OPSSRC
RTRGEN
1
MOD[3:0]
CLKSEL[2:0]
SYNC[4:0]
OPS3[3:0]
ASDG[7:0]
SSDG
AUXOUT[1:0]
PWMRSEN
ASDGM
ICGSM[1:0]
OENSYNC
OETRIG
CCPTRIG
2
ICS[2:0]
OC[F:A]EN
DT[4:0]
POLACE
OSCNT[2:0]
TRCLR
POLBDF
ASEVT
Datasheet
PSSACE[1:0]
SCEVT
ICDIS
ICGARM
PSSBDF[1:0]
OUTM[2:0]
ICOV
ICBNE
DS30010203C-page 462
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
...........continued
Offset
Name
0x027A
...
0x027B
Reserved
0x027C
CCP1TMRL
0x027E
CCP1TMRH
0x0280
CCP1PRL
0x0282
CCP1PRH
0x0284
CCP1RA
0x0286
...
0x0287
Reserved
0x0288
CCP1RB
0x028A
...
0x028B
Reserved
0x028C
CCP1BUFL
0x028E
CCP1BUFH
0x0290
CCP2CON1L
0x0292
CCP2CON1H
0x0294
CCP2CON2L
0x0296
CCP2CON2H
0x0298
CCP2CON3L
0x029A
CCP2CON3H
0x029C
CCP2STATL
0x029E
...
0x029F
Reserved
0x02A0
CCP2TMRL
0x02A2
CCP2TMRH
0x02A4
CCP2PRL
0x02A6
CCP2PRH
0x02A8
CCP2RA
0x02AA
...
0x02AB
Reserved
0x02AC
CCP2RB
Bit Pos.
7
6
5
4
3
2
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
TMRL[7:0]
TMRL[15:8]
TMRH[23:16]
TMRH[31:24]
PRL[7:0]
PRL[15:8]
PRH[23:16]
PRH[31:24]
CMP[7:0]
CMP[15:8]
7:0
15:8
CMP[7:0]
CMP[15:8]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
BUF[7:0]
BUF[15:8]
BUF[23:16]
BUF[31:24]
CCSEL
CCPSLP
TMRSYNC
TMRPS[1:0]
CCPON
TRIGEN
ONESHOT
OPSSRC
RTRGEN
T32
CCPSIDL
ALTSYNC
OETRIG
CCPTRIG
TRSET
ICS[2:0]
OC[F:A]EN
DT[4:0]
POLACE
OSCNT[2:0]
TRCLR
POLBDF
ASEVT
PSSACE[1:0]
SCEVT
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
TMRL[7:0]
TMRL[15:8]
TMRH[23:16]
TMRH[31:24]
PRL[7:0]
PRL[15:8]
PRH[23:16]
PRH[31:24]
CMP[7:0]
CMP[15:8]
7:0
15:8
CMP[7:0]
CMP[15:8]
© 2019-2020 Microchip Technology Inc.
0
MOD[3:0]
CLKSEL[2:0]
SYNC[4:0]
OPS3[3:0]
ASDG[7:0]
SSDG
AUXOUT[1:0]
PWMRSEN
ASDGM
ICGSM[1:0]
OENSYNC
1
Datasheet
ICDIS
ICGARM
PSSBDF[1:0]
OUTM[2:0]
ICOV
ICBNE
DS30010203C-page 463
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
...........continued
Offset
Name
0x02AE
...
0x02AF
Reserved
0x02B0
CCP2BUFL
0x02B2
CCP2BUFH
0x02B4
CCP3CON1L
0x02B6
CCP3CON1H
0x02B8
CCP3CON2L
0x02BA
CCP3CON2H
0x02BC
CCP3CON3L
0x02BE
CCP3CON3H
0x02C0
CCP3STATL
0x02C2
...
0x02C3
Reserved
0x02C4
CCP3TMRL
0x02C6
CCP3TMRH
0x02C8
CCP3PRL
0x02CA
CCP3PRH
0x02CC
CCP3RA
0x02CE
...
0x02CF
Reserved
0x02D0
CCP3RB
0x02D2
...
0x02D3
Reserved
0x02D4
CCP3BUFL
0x02D6
CCP3BUFH
0x02D8
...
0x02FF
Reserved
0x0300
CCP4CON1L
0x0302
CCP4CON1H
0x0304
CCP4CON2L
0x0306
CCP4CON2H
0x0308
CCP4CON3L
Bit Pos.
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7
6
TMRPS[1:0]
CCPON
TRIGEN
ONESHOT
OPSSRC
RTRGEN
5
4
T32
CCPSIDL
ALTSYNC
TRSET
BUF[7:0]
BUF[15:8]
BUF[23:16]
BUF[31:24]
CCSEL
CCPSLP
TMRSYNC
POLACE
OSCNT[2:0]
TRCLR
POLBDF
ASEVT
CMP[7:0]
CMP[15:8]
7:0
15:8
7:0
15:8
BUF[7:0]
BUF[15:8]
BUF[23:16]
BUF[31:24]
© 2019-2020 Microchip Technology Inc.
ICS[2:0]
SCEVT
7:0
15:8
PWMRSEN
ASDGM
ICGSM[1:0]
OENSYNC
0
MOD[3:0]
CLKSEL[2:0]
SYNC[4:0]
OPS3[3:0]
PSSACE[1:0]
TMRL[7:0]
TMRL[15:8]
TMRH[23:16]
TMRH[31:24]
PRL[7:0]
PRL[15:8]
PRH[23:16]
PRH[31:24]
CMP[7:0]
CMP[15:8]
TMRPS[1:0]
CCPON
TRIGEN
ONESHOT
OPSSRC
RTRGEN
1
OC[F:A]EN
DT[4:0]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
2
ASDG[7:0]
SSDG
AUXOUT[1:0]
PWMRSEN
ASDGM
ICGSM[1:0]
OENSYNC
OETRIG
CCPTRIG
3
T32
CCPSIDL
ALTSYNC
CCSEL
CCPSLP
TMRSYNC
ICDIS
ICGARM
PSSBDF[1:0]
OUTM[2:0]
ICOV
ICBNE
MOD[3:0]
CLKSEL[2:0]
SYNC[4:0]
OPS3[3:0]
ASDG[7:0]
SSDG
AUXOUT[1:0]
ICS[2:0]
OC[F:A]EN
DT[4:0]
Datasheet
DS30010203C-page 464
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
...........continued
Offset
Name
Bit Pos.
7
0x030A
CCP4CON3H
7:0
15:8
OETRIG
0x030C
CCP4STATL
7:0
15:8
0x030E
...
0x030F
Reserved
0x0310
CCP4TMRL
0x0312
CCP4TMRH
0x0314
CCP4PRL
0x0316
CCP4PRH
0x0318
CCP4RA
0x031A
...
0x031B
Reserved
0x031C
CCP4RB
0x031E
...
0x031F
Reserved
0x0320
CCP4BUFL
0x0322
CCP4BUFH
0x0324
CCP5CON1L
0x0326
CCP5CON1H
0x0328
CCP5CON2L
0x032A
CCP5CON2H
0x032C
CCP5CON3L
0x032E
CCP5CON3H
0x0330
CCP5STATL
0x0332
...
0x0333
Reserved
0x0334
CCP5TMRL
0x0336
CCP5TMRH
0x0338
CCP5PRL
0x033A
CCP5PRH
0x033C
CCP5RA
0x033E
...
0x033F
Reserved
CCPTRIG
6
TRSET
5
4
3
POLACE
OSCNT[2:0]
POLBDF
TRCLR
ASEVT
2
PSSACE[1:0]
SCEVT
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
TMRL[7:0]
TMRL[15:8]
TMRH[23:16]
TMRH[31:24]
PRL[7:0]
PRL[15:8]
PRH[23:16]
PRH[31:24]
CMP[7:0]
CMP[15:8]
7:0
15:8
CMP[7:0]
CMP[15:8]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
BUF[7:0]
BUF[15:8]
BUF[23:16]
BUF[31:24]
CCSEL
CCPSLP
TMRSYNC
TMRPS[1:0]
CCPON
TRIGEN
ONESHOT
OPSSRC
RTRGEN
T32
CCPSIDL
ALTSYNC
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
© 2019-2020 Microchip Technology Inc.
TRSET
0
PSSBDF[1:0]
OUTM[2:0]
ICOV
ICBNE
MOD[3:0]
CLKSEL[2:0]
SYNC[4:0]
OPS3[3:0]
ASDG[7:0]
SSDG
AUXOUT[1:0]
PWMRSEN
ASDGM
ICGSM[1:0]
OENSYNC
OETRIG
CCPTRIG
ICDIS
ICGARM
1
ICS[2:0]
OC[F:A]EN
DT[4:0]
POLACE
OSCNT[2:0]
TRCLR
POLBDF
ASEVT
PSSACE[1:0]
SCEVT
ICDIS
ICGARM
PSSBDF[1:0]
OUTM[2:0]
ICOV
ICBNE
TMRL[7:0]
TMRL[15:8]
TMRH[23:16]
TMRH[31:24]
PRL[7:0]
PRL[15:8]
PRH[23:16]
PRH[31:24]
CMP[7:0]
CMP[15:8]
Datasheet
DS30010203C-page 465
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
...........continued
Offset
Name
Bit Pos.
7
6
0x0340
CCP5RB
7:0
15:8
CMP[7:0]
CMP[15:8]
0x0342
...
0x0343
Reserved
0x0344
CCP5BUFL
0x0346
CCP5BUFH
0x0348
CCP6CON1L
BUF[7:0]
BUF[15:8]
BUF[23:16]
BUF[31:24]
CCSEL
CCPSLP
TMRSYNC
0x034A
CCP6CON1H
0x034C
CCP6CON2L
0x034E
CCP6CON2H
0x0350
CCP6CON3L
0x0352
CCP6CON3H
0x0354
CCP6STATL
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
0x0356
...
0x0357
Reserved
0x0358
CCP6TMRL
0x035A
CCP6TMRH
0x035C
CCP6PRL
0x035E
CCP6PRH
0x0360
CCP6RA
0x0362
...
0x0363
Reserved
0x0364
CCP6RB
0x0366
...
0x0367
Reserved
0x0368
CCP6BUFL
0x036A
CCP6BUFH
0x036C
CCP7CON1L
0x036E
CCP7CON1H
0x0370
CCP7CON2L
0x0372
CCP7CON2H
0x0374
CCP7CON3L
TMRPS[1:0]
CCPON
TRIGEN
ONESHOT
OPSSRC
RTRGEN
5
4
T32
CCPSIDL
ALTSYNC
TRSET
2
ICS[2:0]
POLACE
OSCNT[2:0]
TRCLR
POLBDF
ASEVT
PSSACE[1:0]
SCEVT
TMRL[7:0]
TMRL[15:8]
TMRH[23:16]
TMRH[31:24]
PRL[7:0]
PRL[15:8]
PRH[23:16]
PRH[31:24]
CMP[7:0]
CMP[15:8]
7:0
15:8
CMP[7:0]
CMP[15:8]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
BUF[7:0]
BUF[15:8]
BUF[23:16]
BUF[31:24]
CCSEL
CCPSLP
TMRSYNC
PWMRSEN
ASDGM
ICGSM[1:0]
OENSYNC
© 2019-2020 Microchip Technology Inc.
0
OC[F:A]EN
DT[4:0]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
TMRPS[1:0]
CCPON
TRIGEN
ONESHOT
OPSSRC
RTRGEN
1
MOD[3:0]
CLKSEL[2:0]
SYNC[4:0]
OPS3[3:0]
ASDG[7:0]
SSDG
AUXOUT[1:0]
PWMRSEN
ASDGM
ICGSM[1:0]
OENSYNC
OETRIG
CCPTRIG
3
T32
CCPSIDL
ALTSYNC
ICDIS
ICGARM
PSSBDF[1:0]
OUTM[2:0]
ICOV
ICBNE
MOD[3:0]
CLKSEL[2:0]
SYNC[4:0]
OPS3[3:0]
ASDG[7:0]
SSDG
AUXOUT[1:0]
ICS[2:0]
OC[F:A]EN
DT[4:0]
Datasheet
DS30010203C-page 466
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
...........continued
Offset
Name
Bit Pos.
7
0x0376
CCP7CON3H
7:0
15:8
OETRIG
0x0378
CCP7STATL
7:0
15:8
0x037A
...
0x037B
Reserved
0x037C
CCP7TMRL
0x037E
CCP7TMRH
0x0380
CCP7PRL
0x0382
CCP7PRH
0x0384
CCP7RA
0x0386
...
0x0387
Reserved
0x0388
CCP7RB
0x038A
...
0x038B
Reserved
0x038C
CCP7BUFL
0x038E
CCP7BUFH
CCPTRIG
6
TRSET
5
4
3
POLACE
OSCNT[2:0]
POLBDF
TRCLR
ASEVT
PSSACE[1:0]
SCEVT
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
TMRL[7:0]
TMRL[15:8]
TMRH[23:16]
TMRH[31:24]
PRL[7:0]
PRL[15:8]
PRH[23:16]
PRH[31:24]
CMP[7:0]
CMP[15:8]
7:0
15:8
CMP[7:0]
CMP[15:8]
7:0
15:8
7:0
15:8
BUF[7:0]
BUF[15:8]
BUF[23:16]
BUF[31:24]
© 2019-2020 Microchip Technology Inc.
Datasheet
2
ICDIS
ICGARM
1
0
PSSBDF[1:0]
OUTM[2:0]
ICOV
ICBNE
DS30010203C-page 467
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.1
CCP8 Control 1 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
15
CCPON
R/W
0
7
CCP8CON1L
0x248
14
6
TMRPS[1:0]
R/W
R/W
0
0
13
CCPSIDL
R/W
0
12
CCPSLP
R/W
0
11
TMRSYNC
R/W
0
10
R/W
0
5
T32
R/W
0
4
CCSEL
R/W
0
3
2
9
CLKSEL[2:0]
R/W
0
8
R/W
0
1
0
R/W
0
R/W
0
MOD[3:0]
R/W
0
R/W
0
Bit 15 – CCPON CCP Module Enable bit
Value
Description
1
Module is enabled with an operating mode specified by the MOD[3:0] control bits
0
Module is disabled
Bit 13 – CCPSIDL CCP Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bit 12 – CCPSLP CCP Sleep Mode Enable bit
Value
Description
1
Module continues to operate in Sleep modes
0
Module does not operate in Sleep modes
Bit 11 – TMRSYNC Time Base Clock Synchronization bit
Value
Description
1
Module time base clock is synchronized to the internal system clocks; timing restrictions apply
0
Module time base clock is not synchronized to the internal system clocks
Bits 10:8 – CLKSEL[2:0] CCP Time Base Clock Select bits
Value
Description
111
TCKIA pin
110
TCKIB pin
101
PLL clock
100
2x peripheral clock
011
CLC4
010
SOSC clock
001
Reference clock output
000
Peripheral clock
Bits 7:6 – TMRPS[1:0] Time Base Prescale Select bits
Value
Description
11
1:64 prescaler
10
1:16 prescaler
01
1:4 prescaler
00
1:1 prescaler
Bit 5 – T32 32-Bit Time Base Select bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 468
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
1
0
Description
Uses 32-bit time base for timer, single edge output compare or input capture function
Uses 16-bit time base for timer, single edge output compare or input capture function
Bit 4 – CCSEL Capture/Compare Mode Select bit
Value
Description
1
Input capture peripheral
0
Output Compare/PWM/Timer peripheral (exact function is selected by the MOD[3:0] bits)
Bits 3:0 – MOD[3:0] CCP Mode Select bits
For CCSEL = 1 (Input Capture modes):
Value
Description
1xxx
Reserved
011x
Reserved
0101
Capture every 16th rising edge
0100
Capture every 4th rising edge
0011
Capture every rising and falling edge
0010
Capture every falling edge
0001
Capture every rising edge
0000
Capture every rising and falling edge (Edge Detect mode)
For CCSEL = 0 (Output Compare/Timer modes):
Value
Description
1111
External Input mode: Pulse generator is disabled, source is selected by ICS[2:0]
1110
Reserved
110x
Reserved
10xx
Reserved
0111
Reserved
0110
Reserved
0101
Dual Edge Compare mode, buffered
0100
Dual Edge Compare mode
0011
16-Bit/32-Bit Single Edge mode, toggles output on compare match
0010
16-Bit/32-Bit Single Edge mode, drives output low on compare match
0001
16-Bit/32-Bit Single Edge mode, drives output high on compare match
0000
16-Bit/32-Bit Timer mode, output functions are disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 469
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.2
CCP8 Control 1 High Register
Name:
Offset:
CCP8CON1H
0x24A
Notes:
1. This control bit has no function in Input Capture modes.
2. This control bit has no function when TRIGEN = 0.
3.
Bit
Access
Reset
Bit
Access
Reset
Output postscale settings, from 1:5 to 1:16 (0100-1111), will result in a FIFO buffer overflow for
Input Capture modes.
15
OPSSRC
R/W
0
14
RTRGEN
R/W
0
13
7
TRIGEN
R/W
0
6
ONESHOT
R/W
0
5
ALTSYNC
R/W
0
12
11
10
9
8
OPS3[3:0]
R/W
0
R/W
0
R/W
0
R/W
0
4
3
1
0
R/W
0
R/W
0
2
SYNC[4:0]
R/W
0
R/W
0
R/W
0
Bit 15 – OPSSRC Output Postscaler Source Select bit(1)
Value
Description
1
Output postscaler scales module trigger output events
0
Output postscaler scales time base interrupt events
Bit 14 – RTRGEN Retrigger Enable bit(2)
Value
Description
1
Time base can be retriggered when TRIGEN bit = 1
0
Time base may not be retriggered when TRIGEN bit = 1
Bits 11:8 – OPS3[3:0] CCP Interrupt Output Postscale Select bits(3)
Value
Description
1111
Interrupt every 16th time base period match
1110
Interrupt every 15th time base period match
. . .
0100
Interrupt every 5th time base period match
0011
Interrupt every 4th time base period match or 4th input capture event
0010
Interrupt every 3rd time base period match or 3rd input capture event
0001
Interrupt every 2nd time base period match or 2nd input capture event
0000
Interrupt after each time base period match or input capture event
Bit 7 – TRIGEN CCP Trigger Enable bit
Value
Description
1
Trigger operation of time base is enabled
0
Trigger operation of time base is disabled
Bit 6 – ONESHOT One-Shot Trigger Mode Enable bit
Value
Description
1
One-Shot Trigger mode is enabled; trigger duration is set by OSCNT[2:0]
0
One-Shot Trigger mode is disabled
Bit 5 – ALTSYNC CCP Clock Select bit
Value
Description
1
An alternate signal is used as the module synchronization output signal
0
The module synchronization output signal is the Time Base Reset/rollover event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 470
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Bits 4:0 – SYNC[4:0] CCP Synchronization Source Select bits
SYNC[4:0]
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Synchronization Source
None; timer with rollover on CCPxPR match or FFFFh
Reserved
Reserved
Reserved
A/D start conversion
CMP3 trigger
CMP2 trigger
CMP1 trigger
Reserved
Reserved
Reserved
Reserved
CLC4 output
CLC3 output
CLC2 output
CLC1 output
Reserved
MCCP8 sync output
INT4 pin
INT3 pin
INT2 pin
INT1 pin
INT0 pin
MCCP7 sync output
MCCP6 sync output
MCCP5 sync output
MCCP4 sync output
MCCP3 sync output
MCCP2 sync output
MCCP1 sync output
MCCP8 sync output
MCCP8 timer sync output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 471
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.3
CCP8 Control 2 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP8CON2L
0x24C
15
PWMRSEN
R/W
0
14
ASDGM
R/W
0
13
12
SSDG
R/W
0
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ASDG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 15 – PWMRSEN CCP PWM Restart Enable bit
Value
Description
1
ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has
ended
0
ASEVT bit must be cleared in software to resume PWM activity on output pins
Bit 14 – ASDGM CCP Auto-Shutdown Gate Mode Enable bit
Value
Description
1
Waits until next Time Base Reset or rollover for shutdown to occur
0
Shutdown event occurs immediately
Bit 12 – SSDG CCP Software Shutdown/Gate Control bit
Value
Description
1
Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of ASDGM
bit still applies)
0
Normal module operation
Bits 7:0 – ASDG[7:0] CCP Auto-Shutdown/Gating Source Enable bits
Value
Description
10000000
OCFB
01000000
OCFA
00100000
CLC1
00010000
MCCP4
00001000
MCCP5
00000100
CMP3 out
00000010
CMP2 out
00000001
CMP1 out
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 472
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.4
CCP8 Control 2 High Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP8CON2H
0x24E
15
OENSYNC
R/W
0
14
7
6
13
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
ICS[2:0]
R/W
0
0
OC[F:A]EN
R/W
0
R/W
0
5
4
ICGSM[1:0]
Access
Reset
12
R/W
0
R/W
0
3
AUXOUT[1:0]
R/W
R/W
0
0
R/W
0
R/W
0
Bit 15 – OENSYNC Output Enable Synchronization bit
Value
Description
1
Update by output enable bits occurs on the next Time Base Reset or rollover
0
Update by output enable bits occurs immediately
Bits 13:8 – OC[F:A]EN Output Enable/Steering Control bits
Value
Description
1
OCx pin is controlled by the CCP module and produces an output compare or PWM signal
0
OCx pin is not controlled by the CCP module; the pin is available to the port logic or another peripheral
multiplexed on the pin
Bits 7:6 – ICGSM[1:0] Input Capture Gating Source Mode Control bits
Value
Description
11
Reserved
10
One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)
01
One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)
00
Level-Sensitive mode: A high level from gating source will enable future capture events; a low level will
disable future capture events
Bits 4:3 – AUXOUT[1:0] Auxiliary Output Signal on Event Selection bits
Value
Description
11
Input capture or output compare event; no signal in Timer mode
10
Signal output depends on module operating mode
01
Time base rollover event (all modes)
00
Disabled
Bits 2:0 – ICS[2:0] Input Capture Source Select bits
Value
Description
111
CLC4
110
CLC3
101
CLC2
100
CLC1
011
Comparator 3
010
Comparator 2
001
Comparator 1
000
Input capture pin (ICM8)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 473
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.5
CCP8 Control 3 Low Register
Name:
Offset:
Bit
CCP8CON3L
0x250
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
R/W
0
R/W
0
2
DT[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 4:0 – DT[4:0] PWM Dead-Time Select bits
Value
Description
111111
Inserts 63 dead-time delay periods between complementary output signals
111110
Inserts 62 dead-time delay periods between complementary output signals
...
000010
Inserts 2 dead-time delay periods between complementary output signals
000001
Inserts 1 dead-time delay period between complementary output signals
000000
Dead-time logic is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 474
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.6
CCP8 Control 3 High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP8CON3H
0x252
15
OETRIG
R/W
0
14
R/W
0
7
6
13
OSCNT[2:0]
R/W
0
12
R/W
0
5
POLACE
R/W
0
4
POLBDF
R/W
0
11
10
R/W
0
3
2
PSSACE[1:0]
R/W
R/W
0
0
9
OUTM[2:0]
R/W
0
8
R/W
0
1
0
PSSBDF[1:0]
R/W
R/W
0
0
Bit 15 – OETRIG CCP Dead-Time Select bit
Value
Description
1
For Triggered mode (TRIGEN = 1): Module does not drive enabled output pins until triggered
0
Normal output pin operation
Bits 14:12 – OSCNT[2:0] One-Shot Event Count bits
Value
Description
111
Extends one-shot event by 7 time base periods (8 time base periods total)
110
Extends one-shot event by 6 time base periods (7 time base periods total)
101
Extends one-shot event by 5 time base periods (6 time base periods total)
100
Extends one-shot event by 4 time base periods (5 time base periods total)
011
Extends one-shot event by 3 time base periods (4 time base periods total)
010
Extends one-shot event by 2 time base periods (3 time base periods total)
001
Extends one-shot event by 1 time base period (2 time base periods total)
000
Does not extend one-shot trigger event
Bits 10:8 – OUTM[2:0] PWM Output Mode Control bits
Value
Description
111
Reserved
110
Output Scan mode
101
Brush DC Output mode, forward
100
Brush DC Output mode, reverse
011
Reserved
010
Half-Bridge Output mode
001
Push-Pull Output mode
000
Steerable Single Output mode
Bit 5 – POLACE CCP Output Pins, OCMxA, OCMxC and OCMxE, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bit 4 – POLBDF CCP Output Pins, OCMxB, OCMxD and OCMxF, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bits 3:2 – PSSACE[1:0] PWM Output Pins, OCMxA, OCMxC and OCMxE, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 475
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
10
0x
Description
Pins are driven inactive when a shutdown event occurs
Pins are tri-stated when a shutdown event occurs
Bits 1:0 – PSSBDF[1:0] PWM Output Pins, OCMxB, OCMxD and OCMxF, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
10
Pins are driven inactive when a shutdown event occurs
0x
Pins are in a high-impedance state when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 476
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.7
CCP8 Status Register Low
Name:
Offset:
CCP8STATL
0x254
Legend: C = Clearable bit; W1 = Write ‘1’ Only bit
Bit
15
14
13
12
11
10
ICGARM
W
0
9
8
7
CCPTRIG
R
0
6
TRSET
W1
0
5
TRCLR
W1
0
4
ASEVT
R/C
0
3
SCEVT
R/C
0
2
ICDIS
R/C
0
1
ICOV
R/C
0
0
ICBNE
R/C
0
Access
Reset
Bit
Access
Reset
Bit 10 – ICGARM Input Capture Gate Arm bit
A write of ‘1’ to this location will arm the Input Capture x module for a one-shot gating event when ICGSM[1:0] = 01
or 10; read as ‘0’.
Bit 7 – CCPTRIG CCP Trigger Status bit
Value
Description
1
Timer has been triggered and is running
0
Timer has not been triggered and is held in Reset
Bit 6 – TRSET CCP Trigger Set Request bit
Writes ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads as ‘0’).
Bit 5 – TRCLR CCP Trigger Clear Request bit
Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads as ‘0’).
Bit 4 – ASEVT CCP Auto-Shutdown Event Status/Control bit
Value
Description
1
A shutdown event is in progress; CCP outputs are in the shutdown state
0
CCP outputs operate normally
Bit 3 – SCEVT Single Edge Compare Event Status bit
Value
Description
1
A single edge compare event has occurred
0
A single edge compare event has not occurred
Bit 2 – ICDIS Input Capture Disable bit
Value
Description
1
Event on input capture pin (ICM8) does not generate a capture event
0
Event on input capture pin will generate a capture event
Bit 1 – ICOV Input Capture Buffer Overflow Status bit
Value
Description
1
The input capture FIFO buffer has overflowed
0
The input capture FIFO buffer has not overflowed
Bit 0 – ICBNE Input Capture Buffer Status bit
Value
Description
1
Input capture buffer has data available
0
Input capture buffer is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 477
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.8
CCP8 Time Base Low Register
Name:
Offset:
Bit
15
CCP8TMRL
0x258
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
TMRL[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
TMRL[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – TMRL[15:0] CCP8 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 478
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.9
CCP8 Time Base High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP8TMRH
0x25A
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
TMRH[31:24]
R/W
R/W
0
0
4
3
TMRH[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – TMRH[31:24] CCP8 16-Bit Time Base Value bits
Bits 7:0 – TMRH[23:16] CCP8 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 479
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.10 CCP8 Period Low Register
Name:
Offset:
Bit
15
CCP8PRL
0x25C
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PRL[15:0] CCP8 Period Low Register bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 480
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.11 CCP8 Period High Register
Name:
Offset:
Bit
15
CCP8PRH
0x25E
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRH[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRH[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – PRH[31:24] CCP8 Period High Register bits
Bits 7:0 – PRH[23:16] CCP8 Period High Register bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 481
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.12 CCP8 Primary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP8RA
0x260
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP8 Primary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 482
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.13 CCP8 Secondary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP8RB
0x264
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP8 Secondary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 483
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.14 CCP8 Capture Buffer Low Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP8BUFL
0x268
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BUF[15:0] CCP8 Compare Buffer Value bits
Indicates the oldest captured time base value in the FIFO.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 484
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.15 CCP8 Capture Buffer High Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP8BUFH
0x26A
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – BUF[31:24] CCP8 Compare Buffer Value bits
Bits 7:0 – BUF[23:16] CCP8 Compare Buffer Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 485
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.16 CCP1 Control 1 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
15
CCPON
R/W
0
7
CCP1CON1L
0x26C
14
6
TMRPS[1:0]
R/W
R/W
0
0
13
CCPSIDL
R/W
0
12
CCPSLP
R/W
0
11
TMRSYNC
R/W
0
10
R/W
0
5
T32
R/W
0
4
CCSEL
R/W
0
3
2
9
CLKSEL[2:0]
R/W
0
8
R/W
0
1
0
R/W
0
R/W
0
MOD[3:0]
R/W
0
R/W
0
Bit 15 – CCPON CCP Module Enable bit
Value
Description
1
Module is enabled with an operating mode specified by the MOD[3:0] control bits
0
Module is disabled
Bit 13 – CCPSIDL CCP Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bit 12 – CCPSLP CCP Sleep Mode Enable bit
Value
Description
1
Module continues to operate in Sleep modes
0
Module does not operate in Sleep modes
Bit 11 – TMRSYNC Time Base Clock Synchronization bit
Value
Description
1
Module time base clock is synchronized to the internal system clocks; timing restrictions apply
0
Module time base clock is not synchronized to the internal system clocks
Bits 10:8 – CLKSEL[2:0] CCP Time Base Clock Select bits
Value
Description
111
TCKIA pin
110
TCKIB pin
101
PLL clock
100
2x peripheral clock
011
CLC1
010
SOSC clock
001
Reference clock output
000
Peripheral clock
Bits 7:6 – TMRPS[1:0] Time Base Prescale Select bits
Value
Description
11
1:64 prescaler
10
1:16 prescaler
01
1:4 prescaler
00
1:1 prescaler
Bit 5 – T32 32-Bit Time Base Select bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 486
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
1
0
Description
Uses 32-bit time base for timer, single edge output compare or input capture function
Uses 16-bit time base for timer, single edge output compare or input capture function
Bit 4 – CCSEL Capture/Compare Mode Select bit
Value
Description
1
Input capture peripheral
0
Output Compare/PWM/Timer peripheral (exact function is selected by the MOD[3:0] bits)
Bits 3:0 – MOD[3:0] CCP Mode Select bits
For CCSEL = 1 (Input Capture modes):
Value
Description
1xxx
Reserved
011x
Reserved
0101
Capture every 16th rising edge
0100
Capture every 4th rising edge
0011
Capture every rising and falling edge
0010
Capture every falling edge
0001
Capture every rising edge
0000
Capture every rising and falling edge (Edge Detect mode)
For CCSEL = 0 (Output Compare/Timer modes):
Value
Description
1111
External Input mode: Pulse generator is disabled, source is selected by ICS[2:0]
1110
Reserved
110x
Reserved
10xx
Reserved
0111
Variable Frequency Pulse mode
0110
Center-Aligned Pulse Compare mode, buffered
0101
Dual Edge Compare mode, buffered
0100
Dual Edge Compare mode
0011
16-Bit/32-Bit Single Edge mode, toggles output on compare match
0010
16-Bit/32-Bit Single Edge mode, drives output low on compare match
0001
16-Bit/32-Bit Single Edge mode, drives output high on compare match
0000
16-Bit/32-Bit Timer mode, output functions are disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 487
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.17 CCP1 Control 1 High Register
Name:
Offset:
CCP1CON1H
0x26E
Notes:
1. This control bit has no function in Input Capture modes.
2. This control bit has no function when TRIGEN = 0.
3.
Bit
Access
Reset
Bit
Access
Reset
Output postscale settings, from 1:5 to 1:16 (0100-1111), will result in a FIFO buffer overflow for
Input Capture modes.
15
OPSSRC
R/W
0
14
RTRGEN
R/W
0
13
7
TRIGEN
R/W
0
6
ONESHOT
R/W
0
5
ALTSYNC
R/W
0
12
11
10
9
8
OPS3[3:0]
R/W
0
R/W
0
R/W
0
R/W
0
4
3
1
0
R/W
0
R/W
0
2
SYNC[4:0]
R/W
0
R/W
0
R/W
0
Bit 15 – OPSSRC Output Postscaler Source Select bit(1)
Value
Description
1
Output postscaler scales module trigger output events
0
Output postscaler scales time base interrupt events
Bit 14 – RTRGEN Retrigger Enable bit(2)
Value
Description
1
Time base can be retriggered when TRIGEN bit = 1
0
Time base may not be retriggered when TRIGEN bit = 1
Bits 11:8 – OPS3[3:0] CCP Interrupt Output Postscale Select bits(3)
Value
Description
1111
Interrupt every 16th time base period match
1110
Interrupt every 15th time base period match
. . .
0100
Interrupt every 5th time base period match
0011
Interrupt every 4th time base period match or 4th input capture event
0010
Interrupt every 3rd time base period match or 3rd input capture event
0001
Interrupt every 2nd time base period match or 2nd input capture event
0000
Interrupt after each time base period match or input capture event
Bit 7 – TRIGEN CCP Trigger Enable bit
Value
Description
1
Trigger operation of time base is enabled
0
Trigger operation of time base is disabled
Bit 6 – ONESHOT One-Shot Trigger Mode Enable bit
Value
Description
1
One-Shot Trigger mode is enabled; trigger duration is set by OSCNT[2:0]
0
One-Shot Trigger mode is disabled
Bit 5 – ALTSYNC CCP Clock Select bit
Value
Description
1
An alternate signal is used as the module synchronization output signal
0
The module synchronization output signal is the Time Base Reset/rollover event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 488
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Bits 4:0 – SYNC[4:0] CCP Synchronization Source Select bits
SYNC[4:0]
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Synchronization Source
None; timer with rollover on CCP1PR match or FFFFh
Reserved
Reserved
Reserved
A/D start conversion
CMP3 trigger
CMP2 trigger
CMP1 trigger
Reserved
Reserved
Reserved
Reserved
CLC4 output
CLC3 output
CLC2 output
CLC1 output
Reserved
MCCP8 sync output
INT4 pin
INT3 pin
INT2 pin
INT1 pin
INT0 pin
MCCP7 sync output
MCCP6 sync output
MCCP5 sync output
MCCP4 sync output
MCCP3 sync output
MCCP2 sync output
MCCP1 sync output
MCCP1 sync output
MCCP1 timer sync output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 489
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.18 CCP1 Control 2 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP1CON2L
0x270
15
PWMRSEN
R/W
0
14
ASDGM
R/W
0
13
12
SSDG
R/W
0
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ASDG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 15 – PWMRSEN CCP PWM Restart Enable bit
Value
Description
1
ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has
ended
0
ASEVT bit must be cleared in software to resume PWM activity on output pins
Bit 14 – ASDGM CCP Auto-Shutdown Gate Mode Enable bit
Value
Description
1
Waits until next Time Base Reset or rollover for shutdown to occur
0
Shutdown event occurs immediately
Bit 12 – SSDG CCP Software Shutdown/Gate Control bit
Value
Description
1
Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of ASDGM
bit still applies)
0
Normal module operation
Bits 7:0 – ASDG[7:0] CCP Auto-Shutdown/Gating Source Enable bits
Value
Description
10000000
OCFB
01000000
OCFA
00100000
CLC1
00010000
MCCP2
00001000
MCCP3
00000100
CMP3 out
00000010
CMP2 out
00000001
CMP1 out
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 490
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.19 CCP1 Control 2 High Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP1CON2H
0x272
15
OENSYNC
R/W
0
14
7
6
13
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
ICS[2:0]
R/W
0
0
OC[F:A]EN
R/W
0
R/W
0
5
4
ICGSM[1:0]
Access
Reset
12
R/W
0
R/W
0
3
AUXOUT[1:0]
R/W
R/W
0
0
R/W
0
R/W
0
Bit 15 – OENSYNC Output Enable Synchronization bit
Value
Description
1
Update by output enable bits occurs on the next Time Base Reset or rollover
0
Update by output enable bits occurs immediately
Bits 13:8 – OC[F:A]EN Output Enable/Steering Control bits
Value
Description
1
OCx pin is controlled by the CCPx module and produces an output compare or PWM signal
0
OCx pin is not controlled by the CCPx module; the pin is available to the port logic or another
peripheral multiplexed on the pin
Bits 7:6 – ICGSM[1:0] Input Capture Gating Source Mode Control bits
Value
Description
11
Reserved
10
One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)
01
One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)
00
Level-Sensitive mode: A high level from gating source will enable future capture events; a low level will
disable future capture events
Bits 4:3 – AUXOUT[1:0] Auxiliary Output Signal on Event Selection bits
Value
Description
11
Input capture or output compare event; no signal in Timer mode
10
Signal output depends on module operating mode
01
Time base rollover event (all modes)
00
Disabled
Bits 2:0 – ICS[2:0] Input Capture Source Select bits
Value
Description
111
CLC4
110
CLC3
101
CLC2
100
CLC1
011
Comparator 3
010
Comparator 2
001
Comparator 1
000
Input capture pin (ICM1)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 491
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.20 CCP1 Control 3 Low Register
Name:
Offset:
Bit
CCP1CON3L
0x274
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
R/W
0
R/W
0
2
DT[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 4:0 – DT[4:0] PWM Dead-Time Select bits
Value
Description
111111
Inserts 63 dead-time delay periods between complementary output signals
111110
Inserts 62 dead-time delay periods between complementary output signals
...
000010
Inserts 2 dead-time delay periods between complementary output signals
000001
Inserts 1 dead-time delay period between complementary output signals
000000
Dead-time logic is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 492
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.21 CCP1 Control 3 High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP1CON3H
0x276
15
OETRIG
R/W
0
14
R/W
0
7
6
13
OSCNT[2:0]
R/W
0
12
R/W
0
5
POLACE
R/W
0
4
POLBDF
R/W
0
11
10
R/W
0
3
2
PSSACE[1:0]
R/W
R/W
0
0
9
OUTM[2:0]
R/W
0
8
R/W
0
1
0
PSSBDF[1:0]
R/W
R/W
0
0
Bit 15 – OETRIG CCP Dead-Time Select bit
Value
Description
1
For Triggered mode (TRIGEN = 1): Module does not drive enabled output pins until triggered
0
Normal output pin operation
Bits 14:12 – OSCNT[2:0] One-Shot Event Count bits
Value
Description
111
Extends one-shot event by 7 time base periods (8 time base periods total)
110
Extends one-shot event by 6 time base periods (7 time base periods total)
101
Extends one-shot event by 5 time base periods (6 time base periods total)
100
Extends one-shot event by 4 time base periods (5 time base periods total)
011
Extends one-shot event by 3 time base periods (4 time base periods total)
010
Extends one-shot event by 2 time base periods (3 time base periods total)
001
Extends one-shot event by 1 time base period (2 time base periods total)
000
Does not extend one-shot trigger event
Bits 10:8 – OUTM[2:0] PWM Output Mode Control bits
Value
Description
111
Reserved
110
Output Scan mode
101
Brush DC Output mode, forward
100
Brush DC Output mode, reverse
011
Reserved
010
Half-Bridge Output mode
001
Push-Pull Output mode
000
Steerable Single Output mode
Bit 5 – POLACE CCP Output Pins, OCMxA, OCMxC and OCMxE, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bit 4 – POLBDF CCP Output Pins, OCMxB, OCMxD and OCMxF, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bits 3:2 – PSSACE[1:0] PWM Output Pins, OCMxA, OCMxC and OCMxE, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 493
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
10
0x
Description
Pins are driven inactive when a shutdown event occurs
Pins are tri-stated when a shutdown event occurs
Bits 1:0 – PSSBDF[1:0] PWM Output Pins, OCMxB, OCMxD and OCMxF, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
10
Pins are driven inactive when a shutdown event occurs
0x
Pins are in a high-impedance state when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 494
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.22 CCP1 Status Register Low
Name:
Offset:
CCP1STATL
0x278
Legend: C = Clearable bit; W1 = Write ‘1’ Only bit
Bit
15
14
13
12
11
10
ICGARM
W
0
9
8
7
CCPTRIG
R
0
6
TRSET
W1
0
5
TRCLR
W1
0
4
ASEVT
R/C
0
3
SCEVT
R/C
0
2
ICDIS
R/C
0
1
ICOV
R/C
0
0
ICBNE
R/C
0
Access
Reset
Bit
Access
Reset
Bit 10 – ICGARM Input Capture Gate Arm bit
A write of ‘1’ to this location will arm the Input Capture x module for a one-shot gating event when ICGSM[1:0] = 01
or 10; read as ‘0’.
Bit 7 – CCPTRIG CCP Trigger Status bit
Value
Description
1
Timer has been triggered and is running
0
Timer has not been triggered and is held in Reset
Bit 6 – TRSET CCP Trigger Set Request bit
Writes ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads as ‘0’).
Bit 5 – TRCLR CCP Trigger Clear Request bit
Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads as ‘0’).
Bit 4 – ASEVT CCP Auto-Shutdown Event Status/Control bit
Value
Description
1
A shutdown event is in progress; CCP outputs are in the shutdown state
0
CCP outputs operate normally
Bit 3 – SCEVT Single Edge Compare Event Status bit
Value
Description
1
A single edge compare event has occurred
0
A single edge compare event has not occurred
Bit 2 – ICDIS Input Capture Disable bit
Value
Description
1
Event on input capture pin (ICM1) does not generate a capture event
0
Event on input capture pin will generate a capture event
Bit 1 – ICOV Input Capture Buffer Overflow Status bit
Value
Description
1
The input capture FIFO buffer has overflowed
0
The input capture FIFO buffer has not overflowed
Bit 0 – ICBNE Input Capture Buffer Status bit
Value
Description
1
Input capture buffer has data available
0
Input capture buffer is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 495
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.23 CCP1 Time Base Low Register
Name:
Offset:
Bit
15
CCP1TMRL
0x27C
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
TMRL[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
TMRL[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – TMRL[15:0] CCP1 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 496
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.24 CCP1 Time Base High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP1TMRH
0x27E
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
TMRH[31:24]
R/W
R/W
0
0
4
3
TMRH[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – TMRH[31:24] CCP1 16-Bit Time Base Value bits
Bits 7:0 – TMRH[23:16] CCP1 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 497
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.25 CCP1 Period Low Register
Name:
Offset:
Bit
15
CCP1PRL
0x280
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PRL[15:0] CCP1 Period Low Register bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 498
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.26 CCP1 Period High Register
Name:
Offset:
Bit
15
CCP1PRH
0x282
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRH[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRH[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – PRH[31:24] CCP1 Period High Register bits
Bits 7:0 – PRH[23:16] CCP1 Period High Register bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 499
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.27 CCP1 Primary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP1RA
0x284
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP1 Primary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 500
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.28 CCP1 Secondary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP1RB
0x288
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP1 Secondary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 501
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.29 CCP1 Capture Buffer Low Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP1BUFL
0x28C
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BUF[15:0] CCP1 Compare Buffer Value bits
Indicates the oldest captured time base value in the FIFO.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 502
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.30 CCP1 Capture Buffer High Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP1BUFH
0x28E
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – BUF[31:24] CCP1 Compare Buffer Value bits
Bits 7:0 – BUF[23:16] CCP1 Compare Buffer Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 503
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.31 CCP2 Control 1 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
15
CCPON
R/W
0
7
CCP2CON1L
0x290
14
6
TMRPS[1:0]
R/W
R/W
0
0
13
CCPSIDL
R/W
0
12
CCPSLP
R/W
0
11
TMRSYNC
R/W
0
10
R/W
0
5
T32
R/W
0
4
CCSEL
R/W
0
3
2
9
CLKSEL[2:0]
R/W
0
8
R/W
0
1
0
R/W
0
R/W
0
MOD[3:0]
R/W
0
R/W
0
Bit 15 – CCPON CCP Module Enable bit
Value
Description
1
Module is enabled with an operating mode specified by the MOD[3:0] control bits
0
Module is disabled
Bit 13 – CCPSIDL CCP Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bit 12 – CCPSLP CCP Sleep Mode Enable bit
Value
Description
1
Module continues to operate in Sleep modes
0
Module does not operate in Sleep modes
Bit 11 – TMRSYNC Time Base Clock Synchronization bit
Value
Description
1
Module time base clock is synchronized to the internal system clocks; timing restrictions apply
0
Module time base clock is not synchronized to the internal system clocks
Bits 10:8 – CLKSEL[2:0] CCP Time Base Clock Select bits
Value
Description
111
TCKIA pin
110
TCKIB pin
101
PLL clock
100
2x peripheral clock
011
CLC2
010
SOSC clock
001
Reference clock output
000
Peripheral clock
Bits 7:6 – TMRPS[1:0] Time Base Prescale Select bits
Value
Description
11
1:64 prescaler
10
1:16 prescaler
01
1:4 prescaler
00
1:1 prescaler
Bit 5 – T32 32-Bit Time Base Select bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 504
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
1
0
Description
Uses 32-bit time base for timer, single edge output compare or input capture function
Uses 16-bit time base for timer, single edge output compare or input capture function
Bit 4 – CCSEL Capture/Compare Mode Select bit
Value
Description
1
Input capture peripheral
0
Output Compare/PWM/Timer peripheral (exact function is selected by the MOD[3:0] bits)
Bits 3:0 – MOD[3:0] CCP Mode Select bits
For CCSEL = 1 (Input Capture modes):
Value
Description
1xxx
Reserved
011x
Reserved
0101
Capture every 16th rising edge
0100
Capture every 4th rising edge
0011
Capture every rising and falling edge
0010
Capture every falling edge
0001
Capture every rising edge
0000
Capture every rising and falling edge (Edge Detect mode)
For CCSEL = 0 (Output Compare/Timer modes):
Value
Description
1111
External Input mode: Pulse generator is disabled, source is selected by ICS[2:0]
1110
Reserved
110x
Reserved
10xx
Reserved
0111
Variable Frequency Pulse mode
0110
Center-Aligned Pulse Compare mode, buffered
0101
Dual Edge Compare mode, buffered
0100
Dual Edge Compare mode
0011
16-Bit/32-Bit Single Edge mode, toggles output on compare match
0010
16-Bit/32-Bit Single Edge mode, drives output low on compare match
0001
16-Bit/32-Bit Single Edge mode, drives output high on compare match
0000
16-Bit/32-Bit Timer mode, output functions are disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 505
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.32 CCP2 Control 1 High Register
Name:
Offset:
CCP2CON1H
0x292
Notes:
1. This control bit has no function in Input Capture modes.
2. This control bit has no function when TRIGEN = 0.
3.
Bit
Access
Reset
Bit
Access
Reset
Output postscale settings, from 1:5 to 1:16 (0100-1111), will result in a FIFO buffer overflow for
Input Capture modes.
15
OPSSRC
R/W
0
14
RTRGEN
R/W
0
13
7
TRIGEN
R/W
0
6
ONESHOT
R/W
0
5
ALTSYNC
R/W
0
12
11
10
9
8
OPS3[3:0]
R/W
0
R/W
0
R/W
0
R/W
0
4
3
1
0
R/W
0
R/W
0
2
SYNC[4:0]
R/W
0
R/W
0
R/W
0
Bit 15 – OPSSRC Output Postscaler Source Select bit(1)
Value
Description
1
Output postscaler scales module trigger output events
0
Output postscaler scales time base interrupt events
Bit 14 – RTRGEN Retrigger Enable bit(2)
Value
Description
1
Time base can be retriggered when TRIGEN bit = 1
0
Time base may not be retriggered when TRIGEN bit = 1
Bits 11:8 – OPS3[3:0] CCP Interrupt Output Postscale Select bits(3)
Value
Description
1111
Interrupt every 16th time base period match
1110
Interrupt every 15th time base period match
. . .
0100
Interrupt every 5th time base period match
0011
Interrupt every 4th time base period match or 4th input capture event
0010
Interrupt every 3rd time base period match or 3rd input capture event
0001
Interrupt every 2nd time base period match or 2nd input capture event
0000
Interrupt after each time base period match or input capture event
Bit 7 – TRIGEN CCP Trigger Enable bit
Value
Description
1
Trigger operation of time base is enabled
0
Trigger operation of time base is disabled
Bit 6 – ONESHOT One-Shot Trigger Mode Enable bit
Value
Description
1
One-Shot Trigger mode is enabled; trigger duration is set by OSCNT[2:0]
0
One-Shot Trigger mode is disabled
Bit 5 – ALTSYNC CCP Clock Select bit
Value
Description
1
An alternate signal is used as the module synchronization output signal
0
The module synchronization output signal is the Time Base Reset/rollover event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 506
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Bits 4:0 – SYNC[4:0] CCP Synchronization Source Select bits
SYNC[4:0]
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Synchronization Source
None; timer with rollover on CCP2PR match or FFFFh
Reserved
Reserved
Reserved
A/D start conversion
CMP3 trigger
CMP2 trigger
CMP1 trigger
Reserved
Reserved
Reserved
Reserved
CLC4 output
CLC3 output
CLC2 output
CLC1 output
Reserved
MCCP8 sync output
INT4 pin
INT3 pin
INT2 pin
INT1 pin
INT0 pin
MCCP7 sync output
MCCP6 sync output
MCCP5 sync output
MCCP4 sync output
MCCP3 sync output
MCCP2 sync output
MCCP1 sync output
MCCP2 sync output
MCCP2 timer sync output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 507
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.33 CCP2 Control 2 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP2CON2L
0x294
15
PWMRSEN
R/W
0
14
ASDGM
R/W
0
13
12
SSDG
R/W
0
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ASDG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 15 – PWMRSEN CCP PWM Restart Enable bit
Value
Description
1
ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has
ended
0
ASEVT bit must be cleared in software to resume PWM activity on output pins
Bit 14 – ASDGM CCP Auto-Shutdown Gate Mode Enable bit
Value
Description
1
Waits until next Time Base Reset or rollover for shutdown to occur
0
Shutdown event occurs immediately
Bit 12 – SSDG CCP Software Shutdown/Gate Control bit
Value
Description
1
Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of ASDGM
bit still applies)
0
Normal module operation
Bits 7:0 – ASDG[7:0] CCP Auto-Shutdown/Gating Source Enable bits
Value
Description
10000000
OCFB
01000000
OCFA
00100000
CLC2
00010000
MCCP1
00001000
MCCP2
00000100
CMP3 out
00000010
CMP2 out
00000001
CMP1 out
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 508
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.34 CCP2 Control 2 High Register
Name:
Offset:
CCP2CON2H
0x296
Note:
1. OCFEN through OCBEN (bits[13:9]) are implemented in MCCP modules only.
Bit
Access
Reset
Bit
15
OENSYNC
R/W
0
14
7
6
13
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
ICS[2:0]
R/W
0
0
OC[F:A]EN
R/W
0
R/W
0
5
4
ICGSM[1:0]
Access
Reset
12
R/W
0
R/W
0
3
AUXOUT[1:0]
R/W
R/W
0
0
R/W
0
R/W
0
Bit 15 – OENSYNC Output Enable Synchronization bit
Value
Description
1
Update by output enable bits occurs on the next Time Base Reset or rollover
0
Update by output enable bits occurs immediately
Bits 13:8 – OC[F:A]EN Output Enable/Steering Control bits(1)
Value
Description
1
OCx pin is controlled by the CCP module and produces an output compare or PWM signal
0
OCx pin is not controlled by the CCP module; the pin is available to the port logic or another peripheral
multiplexed on the pin
Bits 7:6 – ICGSM[1:0] Input Capture Gating Source Mode Control bits
Value
Description
11
Reserved
10
One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)
01
One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)
00
Level-Sensitive mode: A high level from gating source will enable future capture events; a low level will
disable future capture events
Bits 4:3 – AUXOUT[1:0] Auxiliary Output Signal on Event Selection bits
Value
Description
11
Input capture or output compare event; no signal in Timer mode
10
Signal output depends on module operating mode
01
Time base rollover event (all modes)
00
Disabled
Bits 2:0 – ICS[2:0] Input Capture Source Select bits
Value
Description
111
CLC4
110
CLC3
101
CLC2
100
CLC1
011
Comparator 3
010
Comparator 2
001
Comparator 1
000
Input capture pin (ICM2)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 509
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.35 CCP2 Control 3 Low Register
Name:
Offset:
Bit
CCP2CON3L
0x298
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
R/W
0
R/W
0
2
DT[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 4:0 – DT[4:0] PWM Dead-Time Select bits
Value
Description
111111
Inserts 63 dead-time delay periods between complementary output signals
111110
Inserts 62 dead-time delay periods between complementary output signals
...
000010
Inserts 2 dead-time delay periods between complementary output signals
000001
Inserts 1 dead-time delay period between complementary output signals
000000
Dead-time logic is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 510
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.36 CCP2 Control 3 High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP2CON3H
0x29A
15
OETRIG
R/W
0
14
R/W
0
7
6
13
OSCNT[2:0]
R/W
0
12
R/W
0
5
POLACE
R/W
0
4
POLBDF
R/W
0
11
10
R/W
0
3
2
PSSACE[1:0]
R/W
R/W
0
0
9
OUTM[2:0]
R/W
0
8
R/W
0
1
0
PSSBDF[1:0]
R/W
R/W
0
0
Bit 15 – OETRIG CCP Dead-Time Select bit
Value
Description
1
For Triggered mode (TRIGEN = 1): Module does not drive enabled output pins until triggered
0
Normal output pin operation
Bits 14:12 – OSCNT[2:0] One-Shot Event Count bits
Value
Description
111
Extends one-shot event by 7 time base periods (8 time base periods total)
110
Extends one-shot event by 6 time base periods (7 time base periods total)
101
Extends one-shot event by 5 time base periods (6 time base periods total)
100
Extends one-shot event by 4 time base periods (5 time base periods total)
011
Extends one-shot event by 3 time base periods (4 time base periods total)
010
Extends one-shot event by 2 time base periods (3 time base periods total)
001
Extends one-shot event by 1 time base period (2 time base periods total)
000
Does not extend one-shot trigger event
Bits 10:8 – OUTM[2:0] PWM Output Mode Control bits
Value
Description
111
Reserved
110
Output Scan mode
101
Brush DC Output mode, forward
100
Brush DC Output mode, reverse
011
Reserved
010
Half-Bridge Output mode
001
Push-Pull Output mode
000
Steerable Single Output mode
Bit 5 – POLACE CCP Output Pins, OCMxA, OCMxC and OCMxE, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bit 4 – POLBDF CCP Output Pins, OCMxB, OCMxD and OCMxF, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bits 3:2 – PSSACE[1:0] PWM Output Pins, OCMxA, OCMxC and OCMxE, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 511
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
10
0x
Description
Pins are driven inactive when a shutdown event occurs
Pins are tri-stated when a shutdown event occurs
Bits 1:0 – PSSBDF[1:0] PWM Output Pins, OCMxB, OCMxD and OCMxF, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
10
Pins are driven inactive when a shutdown event occurs
0x
Pins are in a high-impedance state when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 512
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.37 CCP2 Status Register Low
Name:
Offset:
CCP2STATL
0x29C
Legend: C = Clearable bit; W1 = Write ‘1’ Only bit
Bit
15
14
13
12
11
10
ICGARM
W
0
9
8
7
CCPTRIG
R
0
6
TRSET
W1
0
5
TRCLR
W1
0
4
ASEVT
R/C
0
3
SCEVT
R/C
0
2
ICDIS
R/C
0
1
ICOV
R/C
0
0
ICBNE
R/C
0
Access
Reset
Bit
Access
Reset
Bit 10 – ICGARM Input Capture Gate Arm bit
A write of ‘1’ to this location will arm the Input Capture x module for a one-shot gating event when ICGSM[1:0] = 01
or 10; read as ‘0’.
Bit 7 – CCPTRIG CCP Trigger Status bit
Value
Description
1
Timer has been triggered and is running
0
Timer has not been triggered and is held in Reset
Bit 6 – TRSET CCP Trigger Set Request bit
Writes ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads as ‘0’).
Bit 5 – TRCLR CCP Trigger Clear Request bit
Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads as ‘0’).
Bit 4 – ASEVT CCP Auto-Shutdown Event Status/Control bit
Value
Description
1
A shutdown event is in progress; CCP outputs are in the shutdown state
0
CCP outputs operate normally
Bit 3 – SCEVT Single Edge Compare Event Status bit
Value
Description
1
A single edge compare event has occurred
0
A single edge compare event has not occurred
Bit 2 – ICDIS Input Capture Disable bit
Value
Description
1
Event on input capture pin (ICM2) does not generate a capture event
0
Event on input capture pin will generate a capture event
Bit 1 – ICOV Input Capture Buffer Overflow Status bit
Value
Description
1
The input capture FIFO buffer has overflowed
0
The input capture FIFO buffer has not overflowed
Bit 0 – ICBNE Input Capture Buffer Status bit
Value
Description
1
Input capture buffer has data available
0
Input capture buffer is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 513
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.38 CCP2 Time Base Low Register
Name:
Offset:
Bit
15
CCP2TMRL
0x2A0
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMRL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TMRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMRL[15:0] CCP2 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 514
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.39 CCP2 Time Base High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP2TMRH
0x2A2
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
TMRH[31:24]
R/W
R/W
0
0
4
3
TMRH[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – TMRH[31:24] CCP2 16-Bit Time Base Value bits
Bits 7:0 – TMRH[23:16] CCP2 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 515
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.40 CCP2 Period Low Register
Name:
Offset:
Bit
15
CCP2PRL
0x2A4
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PRL[15:0] CCP2 Period Low Register bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 516
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.41 CCP2 Period High Register
Name:
Offset:
Bit
15
CCP2PRH
0x2A6
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRH[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRH[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – PRH[31:24] CCP2 Period High Register bits
Bits 7:0 – PRH[23:16] CCP2 Period High Register bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 517
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.42 CCP2 Primary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP2RA
0x2A8
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP2 Primary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 518
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.43 CCP2 Secondary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP2RB
0x2AC
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP2 Secondary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 519
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.44 CCP2 Capture Buffer Low Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP2BUFL
0x2B0
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BUF[15:0] CCP2 Compare Buffer Value bits
Indicates the oldest captured time base value in the FIFO.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 520
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.45 CCP2 Capture Buffer High Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP2BUFH
0x2B2
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – BUF[31:24] CCP2 Compare Buffer Value bits
Bits 7:0 – BUF[23:16] CCP2 Compare Buffer Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 521
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.46 CCP3 Control 1 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
15
CCPON
R/W
0
7
CCP3CON1L
0x2B4
14
6
TMRPS[1:0]
R/W
R/W
0
0
13
CCPSIDL
R/W
0
12
CCPSLP
R/W
0
11
TMRSYNC
R/W
0
10
R/W
0
5
T32
R/W
0
4
CCSEL
R/W
0
3
2
9
CLKSEL[2:0]
R/W
0
8
R/W
0
1
0
R/W
0
R/W
0
MOD[3:0]
R/W
0
R/W
0
Bit 15 – CCPON CCP Module Enable bit
Value
Description
1
Module is enabled with an operating mode specified by the MOD[3:0] control bits
0
Module is disabled
Bit 13 – CCPSIDL CCP Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bit 12 – CCPSLP CCP Sleep Mode Enable bit
Value
Description
1
Module continues to operate in Sleep modes
0
Module does not operate in Sleep modes
Bit 11 – TMRSYNC Time Base Clock Synchronization bit
Value
Description
1
Module time base clock is synchronized to the internal system clocks; timing restrictions apply
0
Module time base clock is not synchronized to the internal system clocks
Bits 10:8 – CLKSEL[2:0] CCP Time Base Clock Select bits
Value
Description
111
TCKIA pin
110
TCKIB pin
101
PLL clock
100
2x peripheral clock
011
CLC3
010
SOSC clock
001
Reference clock output
000
Peripheral clock
Bits 7:6 – TMRPS[1:0] Time Base Prescale Select bits
Value
Description
11
1:64 prescaler
10
1:16 prescaler
01
1:4 prescaler
00
1:1 prescaler
Bit 5 – T32 32-Bit Time Base Select bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 522
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
1
0
Description
Uses 32-bit time base for timer, single edge output compare or input capture function
Uses 16-bit time base for timer, single edge output compare or input capture function
Bit 4 – CCSEL Capture/Compare Mode Select bit
Value
Description
1
Input capture peripheral
0
Output Compare/PWM/Timer peripheral (exact function is selected by the MOD[3:0] bits)
Bits 3:0 – MOD[3:0] CCP Mode Select bits
For CCSEL = 1 (Input Capture modes):
Value
Description
1xxx
Reserved
011x
Reserved
0101
Capture every 16th rising edge
0100
Capture every 4th rising edge
0011
Capture every rising and falling edge
0010
Capture every falling edge
0001
Capture every rising edge
0000
Capture every rising and falling edge (Edge Detect mode)
For CCSEL = 0 (Output Compare/Timer modes):
Value
Description
1111
External Input mode: Pulse generator is disabled, source is selected by ICS[2:0]
1110
Reserved
110x
Reserved
10xx
Reserved
0111
Variable Frequency Pulse mode
0110
Center-Aligned Pulse Compare mode, buffered
0101
Dual Edge Compare mode, buffered
0100
Dual Edge Compare mode
0011
16-Bit/32-Bit Single Edge mode, toggles output on compare match
0010
16-Bit/32-Bit Single Edge mode, drives output low on compare match
0001
16-Bit/32-Bit Single Edge mode, drives output high on compare match
0000
16-Bit/32-Bit Timer mode, output functions are disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 523
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.47 CCP3 Control 1 High Register
Name:
Offset:
CCP3CON1H
0x2B6
Notes:
1. This control bit has no function in Input Capture modes.
2. This control bit has no function when TRIGEN = 0.
3.
Bit
Access
Reset
Bit
Access
Reset
Output postscale settings, from 1:5 to 1:16 (0100-1111), will result in a FIFO buffer overflow for
Input Capture modes.
15
OPSSRC
R/W
0
14
RTRGEN
R/W
0
13
7
TRIGEN
R/W
0
6
ONESHOT
R/W
0
5
ALTSYNC
R/W
0
12
11
10
9
8
OPS3[3:0]
R/W
0
R/W
0
R/W
0
R/W
0
4
3
1
0
R/W
0
R/W
0
2
SYNC[4:0]
R/W
0
R/W
0
R/W
0
Bit 15 – OPSSRC Output Postscaler Source Select bit(1)
Value
Description
1
Output postscaler scales module trigger output events
0
Output postscaler scales time base interrupt events
Bit 14 – RTRGEN Retrigger Enable bit(2)
Value
Description
1
Time base can be retriggered when TRIGEN bit = 1
0
Time base may not be retriggered when TRIGEN bit = 1
Bits 11:8 – OPS3[3:0] CCP Interrupt Output Postscale Select bits(3)
Value
Description
1111
Interrupt every 16th time base period match
1110
Interrupt every 15th time base period match
. . .
0100
Interrupt every 5th time base period match
0011
Interrupt every 4th time base period match or 4th input capture event
0010
Interrupt every 3rd time base period match or 3rd input capture event
0001
Interrupt every 2nd time base period match or 2nd input capture event
0000
Interrupt after each time base period match or input capture event
Bit 7 – TRIGEN CCP Trigger Enable bit
Value
Description
1
Trigger operation of time base is enabled
0
Trigger operation of time base is disabled
Bit 6 – ONESHOT One-Shot Trigger Mode Enable bit
Value
Description
1
One-Shot Trigger mode is enabled; trigger duration is set by OSCNT[2:0]
0
One-Shot Trigger mode is disabled
Bit 5 – ALTSYNC CCP Clock Select bit
Value
Description
1
An alternate signal is used as the module synchronization output signal
0
The module synchronization output signal is the Time Base Reset/rollover event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 524
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Bits 4:0 – SYNC[4:0] CCP Synchronization Source Select bits
SYNC[4:0]
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Synchronization Source
None; timer with rollover on CCP3PR match or FFFFh
Reserved
Reserved
Reserved
A/D start conversion
CMP3 trigger
CMP2 trigger
CMP1 trigger
Reserved
Reserved
Reserved
Reserved
CLC4 output
CLC3 output
CLC2 output
CLC1 output
Reserved
MCCP8 sync output
INT4 pin
INT3 pin
INT2 pin
INT1 pin
INT0 pin
MCCP7 sync output
MCCP6 sync output
MCCP5 sync output
MCCP4 sync output
MCCP3 sync output
MCCP2 sync output
MCCP1 sync output
MCCP3 sync output
MCCP3 timer sync output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 525
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.48 CCP3 Control 2 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP3CON2L
0x2B8
15
PWMRSEN
R/W
0
14
ASDGM
R/W
0
13
12
SSDG
R/W
0
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ASDG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 15 – PWMRSEN CCP PWM Restart Enable bit
Value
Description
1
ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has
ended
0
ASEVT bit must be cleared in software to resume PWM activity on output pins
Bit 14 – ASDGM CCP Auto-Shutdown Gate Mode Enable bit
Value
Description
1
Waits until next Time Base Reset or rollover for shutdown to occur
0
Shutdown event occurs immediately
Bit 12 – SSDG CCP Software Shutdown/Gate Control bit
Value
Description
1
Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of ASDGM
bit still applies)
0
Normal module operation
Bits 7:0 – ASDG[7:0] CCP Auto-Shutdown/Gating Source Enable bits
Value
Description
10000000
OCFB
01000000
OCFA
00100000
CLC3
00010000
MCCP1
00001000
MCCP2
00000100
CMP3 out
00000010
CMP2 out
00000001
CMP1 out
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 526
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.49 CCP3 Control 2 High Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP3CON2H
0x2BA
15
OENSYNC
R/W
0
14
7
6
13
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
ICS[2:0]
R/W
0
0
OC[F:A]EN
R/W
0
R/W
0
5
4
ICGSM[1:0]
Access
Reset
12
R/W
0
R/W
0
3
AUXOUT[1:0]
R/W
R/W
0
0
R/W
0
R/W
0
Bit 15 – OENSYNC Output Enable Synchronization bit
Value
Description
1
Update by output enable bits occurs on the next Time Base Reset or rollover
0
Update by output enable bits occurs immediately
Bits 13:8 – OC[F:A]EN Output Enable/Steering Control bits
Value
Description
1
OCx pin is controlled by the CCP module and produces an output compare or PWM signal
0
OCx pin is not controlled by the CCP module; the pin is available to the port logic or another peripheral
multiplexed on the pin
Bits 7:6 – ICGSM[1:0] Input Capture Gating Source Mode Control bits
Value
Description
11
Reserved
10
One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)
01
One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)
00
Level-Sensitive mode: A high level from gating source will enable future capture events; a low level will
disable future capture events
Bits 4:3 – AUXOUT[1:0] Auxiliary Output Signal on Event Selection bits
Value
Description
11
Input capture or output compare event; no signal in Timer mode
10
Signal output depends on module operating mode
01
Time base rollover event (all modes)
00
Disabled
Bits 2:0 – ICS[2:0] Input Capture Source Select bits
Value
Description
111
CLC4
110
CLC3
101
CLC2
100
CLC1
011
Comparator 3
010
Comparator 2
001
Comparator 1
000
Input capture pin (ICM3)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 527
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.50 CCP3 Control 3 Low Register
Name:
Offset:
Bit
CCP3CON3L
0x2BC
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
R/W
0
R/W
0
2
DT[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 4:0 – DT[4:0] PWM Dead-Time Select bits
Value
Description
111111
Inserts 63 dead-time delay periods between complementary output signals
111110
Inserts 62 dead-time delay periods between complementary output signals
...
000010
Inserts 2 dead-time delay periods between complementary output signals
000001
Inserts 1 dead-time delay period between complementary output signals
000000
Dead-time logic is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 528
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.51 CCP3 Control 3 High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP3CON3H
0x2BE
15
OETRIG
R/W
0
14
R/W
0
7
6
13
OSCNT[2:0]
R/W
0
12
R/W
0
5
POLACE
R/W
0
4
POLBDF
R/W
0
11
10
R/W
0
3
2
PSSACE[1:0]
R/W
R/W
0
0
9
OUTM[2:0]
R/W
0
8
R/W
0
1
0
PSSBDF[1:0]
R/W
R/W
0
0
Bit 15 – OETRIG CCP Dead-Time Select bit
Value
Description
1
For Triggered mode (TRIGEN = 1): Module does not drive enabled output pins until triggered
0
Normal output pin operation
Bits 14:12 – OSCNT[2:0] One-Shot Event Count bits
Value
Description
111
Extends one-shot event by 7 time base periods (8 time base periods total)
110
Extends one-shot event by 6 time base periods (7 time base periods total)
101
Extends one-shot event by 5 time base periods (6 time base periods total)
100
Extends one-shot event by 4 time base periods (5 time base periods total)
011
Extends one-shot event by 3 time base periods (4 time base periods total)
010
Extends one-shot event by 2 time base periods (3 time base periods total)
001
Extends one-shot event by 1 time base period (2 time base periods total)
000
Does not extend one-shot trigger event
Bits 10:8 – OUTM[2:0] PWM Output Mode Control bits
Value
Description
111
Reserved
110
Output Scan mode
101
Brush DC Output mode, forward
100
Brush DC Output mode, reverse
011
Reserved
010
Half-Bridge Output mode
001
Push-Pull Output mode
000
Steerable Single Output mode
Bit 5 – POLACE CCP Output Pins, OCMxA, OCMxC and OCMxE, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bit 4 – POLBDF CCP Output Pins, OCMxB, OCMxD and OCMxF, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bits 3:2 – PSSACE[1:0] PWM Output Pins, OCMxA, OCMxC and OCMxE, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 529
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
10
0x
Description
Pins are driven inactive when a shutdown event occurs
Pins are tri-stated when a shutdown event occurs
Bits 1:0 – PSSBDF[1:0] PWM Output Pins, OCMxB, OCMxD and OCMxF, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
10
Pins are driven inactive when a shutdown event occurs
0x
Pins are in a high-impedance state when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 530
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.52 CCP3 Status Register Low
Name:
Offset:
CCP3STATL
0x2C0
Legend: C = Clearable bit; W1 = Write ‘1’ Only bit
Bit
15
14
13
12
11
10
ICGARM
W
0
9
8
7
CCPTRIG
R
0
6
TRSET
W1
0
5
TRCLR
W1
0
4
ASEVT
R/C
0
3
SCEVT
R/C
0
2
ICDIS
R/C
0
1
ICOV
R/C
0
0
ICBNE
R/C
0
Access
Reset
Bit
Access
Reset
Bit 10 – ICGARM Input Capture Gate Arm bit
A write of ‘1’ to this location will arm the Input Capture x module for a one-shot gating event when ICGSM[1:0] = 01
or 10; read as ‘0’.
Bit 7 – CCPTRIG CCP Trigger Status bit
Value
Description
1
Timer has been triggered and is running
0
Timer has not been triggered and is held in Reset
Bit 6 – TRSET CCP Trigger Set Request bit
Writes ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads as ‘0’).
Bit 5 – TRCLR CCP Trigger Clear Request bit
Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads as ‘0’).
Bit 4 – ASEVT CCP Auto-Shutdown Event Status/Control bit
Value
Description
1
A shutdown event is in progress; CCP outputs are in the shutdown state
0
CCP outputs operate normally
Bit 3 – SCEVT Single Edge Compare Event Status bit
Value
Description
1
A single edge compare event has occurred
0
A single edge compare event has not occurred
Bit 2 – ICDIS Input Capture Disable bit
Value
Description
1
Event on input capture pin (ICM3) does not generate a capture event
0
Event on input capture pin will generate a capture event
Bit 1 – ICOV Input Capture Buffer Overflow Status bit
Value
Description
1
The input capture FIFO buffer has overflowed
0
The input capture FIFO buffer has not overflowed
Bit 0 – ICBNE Input Capture Buffer Status bit
Value
Description
1
Input capture buffer has data available
0
Input capture buffer is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 531
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.53 CCP3 Time Base Low Register
Name:
Offset:
Bit
15
CCP3TMRL
0x2C4
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMRL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TMRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMRL[15:0] CCP3 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 532
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.54 CCP3 Time Base High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP3TMRH
0x2C6
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
TMRH[31:24]
R/W
R/W
0
0
4
3
TMRH[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – TMRH[31:24] CCP3 16-Bit Time Base Value bits
Bits 7:0 – TMRH[23:16] CCP3 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 533
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.55 CCP3 Period Low Register
Name:
Offset:
Bit
15
CCP3PRL
0x2C8
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PRL[15:0] CCP3 Period Low Register bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 534
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.56 CCP3 Period High Register
Name:
Offset:
Bit
15
CCP3PRH
0x2CA
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRH[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRH[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – PRH[31:24] CCP3 Period High Register bits
Bits 7:0 – PRH[23:16] CCP3 Period High Register bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 535
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.57 CCP3 Primary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP3RA
0x2CC
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP3 Primary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 536
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.58 CCP3 Secondary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP3RB
0x2D0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP3 Secondary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 537
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.59 CCP3 Capture Buffer Low Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP3BUFL
0x2D4
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BUF[15:0] CCP3 Compare Buffer Value bits
Indicates the oldest captured time base value in the FIFO.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 538
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.60 CCP3 Capture Buffer High Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP3BUFH
0x2D6
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – BUF[31:24] CCP3 Compare Buffer Value bits
Bits 7:0 – BUF[23:16] CCP3 Compare Buffer Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 539
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.61 CCP4 Control 1 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
15
CCPON
R/W
0
7
CCP4CON1L
0x300
14
6
TMRPS[1:0]
R/W
R/W
0
0
13
CCPSIDL
R/W
0
12
CCPSLP
R/W
0
11
TMRSYNC
R/W
0
10
R/W
0
5
T32
R/W
0
4
CCSEL
R/W
0
3
2
9
CLKSEL[2:0]
R/W
0
8
R/W
0
1
0
R/W
0
R/W
0
MOD[3:0]
R/W
0
R/W
0
Bit 15 – CCPON CCP Module Enable bit
Value
Description
1
Module is enabled with an operating mode specified by the MOD[3:0] control bits
0
Module is disabled
Bit 13 – CCPSIDL CCP Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bit 12 – CCPSLP CCP Sleep Mode Enable bit
Value
Description
1
Module continues to operate in Sleep modes
0
Module does not operate in Sleep modes
Bit 11 – TMRSYNC Time Base Clock Synchronization bit
Value
Description
1
Module time base clock is synchronized to the internal system clocks; timing restrictions apply
0
Module time base clock is not synchronized to the internal system clocks
Bits 10:8 – CLKSEL[2:0] CCP Time Base Clock Select bits
Value
Description
111
TCKIA pin
110
TCKIB pin
101
PLL clock
100
2x peripheral clock
011
CLC4
010
SOSC clock
001
Reference clock output
000
Peripheral clock
Bits 7:6 – TMRPS[1:0] Time Base Prescale Select bits
Value
Description
11
1:64 prescaler
10
1:16 prescaler
01
1:4 prescaler
00
1:1 prescaler
Bit 5 – T32 32-Bit Time Base Select bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 540
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
1
0
Description
Uses 32-bit time base for timer, single edge output compare or input capture function
Uses 16-bit time base for timer, single edge output compare or input capture function
Bit 4 – CCSEL Capture/Compare Mode Select bit
Value
Description
1
Input capture peripheral
0
Output Compare/PWM/Timer peripheral (exact function is selected by the MOD[3:0] bits)
Bits 3:0 – MOD[3:0] CCP Mode Select bits
For CCSEL = 1 (Input Capture modes):
Value
Description
1xxx
Reserved
011x
Reserved
0101
Capture every 16th rising edge
0100
Capture every 4th rising edge
0011
Capture every rising and falling edge
0010
Capture every falling edge
0001
Capture every rising edge
0000
Capture every rising and falling edge (Edge Detect mode)
For CCSEL = 0 (Output Compare/Timer modes):
Value
Description
1111
External Input mode: Pulse generator is disabled, source is selected by ICS[2:0]
1110
Reserved
110x
Reserved
10xx
Reserved
0111
Reserved
0110
Reserved
0101
Dual Edge Compare mode, buffered
0100
Dual Edge Compare mode
0011
16-Bit/32-Bit Single Edge mode, toggles output on compare match
0010
16-Bit/32-Bit Single Edge mode, drives output low on compare match
0001
16-Bit/32-Bit Single Edge mode, drives output high on compare match
0000
16-Bit/32-Bit Timer mode, output functions are disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 541
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.62 CCP4 Control 1 High Register
Name:
Offset:
CCP4CON1H
0x302
Notes:
1. This control bit has no function in Input Capture modes.
2. This control bit has no function when TRIGEN = 0.
3.
Bit
Access
Reset
Bit
Access
Reset
Output postscale settings, from 1:5 to 1:16 (0100-1111), will result in a FIFO buffer overflow for
Input Capture modes.
15
OPSSRC
R/W
0
14
RTRGEN
R/W
0
13
7
TRIGEN
R/W
0
6
ONESHOT
R/W
0
5
ALTSYNC
R/W
0
12
11
10
9
8
OPS3[3:0]
R/W
0
R/W
0
R/W
0
R/W
0
4
3
1
0
R/W
0
R/W
0
2
SYNC[4:0]
R/W
0
R/W
0
R/W
0
Bit 15 – OPSSRC Output Postscaler Source Select bit(1)
Value
Description
1
Output postscaler scales module trigger output events
0
Output postscaler scales time base interrupt events
Bit 14 – RTRGEN Retrigger Enable bit(2)
Value
Description
1
Time base can be retriggered when TRIGEN bit = 1
0
Time base may not be retriggered when TRIGEN bit = 1
Bits 11:8 – OPS3[3:0] CCP Interrupt Output Postscale Select bits(3)
Value
Description
1111
Interrupt every 16th time base period match
1110
Interrupt every 15th time base period match
. . .
0100
Interrupt every 5th time base period match
0011
Interrupt every 4th time base period match or 4th input capture event
0010
Interrupt every 3rd time base period match or 3rd input capture event
0001
Interrupt every 2nd time base period match or 2nd input capture event
0000
Interrupt after each time base period match or input capture event
Bit 7 – TRIGEN CCP Trigger Enable bit
Value
Description
1
Trigger operation of time base is enabled
0
Trigger operation of time base is disabled
Bit 6 – ONESHOT One-Shot Trigger Mode Enable bit
Value
Description
1
One-Shot Trigger mode is enabled; trigger duration is set by OSCNT[2:0]
0
One-Shot Trigger mode is disabled
Bit 5 – ALTSYNC CCP Clock Select bit
Value
Description
1
An alternate signal is used as the module synchronization output signal
0
The module synchronization output signal is the Time Base Reset/rollover event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 542
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Bits 4:0 – SYNC[4:0] CCP Synchronization Source Select bits
SYNC[4:0]
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Synchronization Source
None; timer with rollover on CCP4PR match or FFFFh
Reserved
Reserved
Reserved
A/D start conversion
CMP3 trigger
CMP2 trigger
CMP1 trigger
Reserved
Reserved
Reserved
Reserved
CLC4 output
CLC3 output
CLC2 output
CLC1 output
Reserved
MCCP8 sync output
INT4 pin
INT3 pin
INT2 pin
INT1 pin
INT0 pin
MCCP7 sync output
MCCP6 sync output
MCCP5 sync output
MCCP4 sync output
MCCP3 sync output
MCCP2 sync output
MCCP1 sync output
MCCP4 sync output
MCCP4 timer sync output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 543
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.63 CCP4 Control 2 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP4CON2L
0x304
15
PWMRSEN
R/W
0
14
ASDGM
R/W
0
13
12
SSDG
R/W
0
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ASDG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 15 – PWMRSEN CCP PWM Restart Enable bit
Value
Description
1
ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has
ended
0
ASEVT bit must be cleared in software to resume PWM activity on output pins
Bit 14 – ASDGM CCP Auto-Shutdown Gate Mode Enable bit
Value
Description
1
Waits until the next Time Base Reset or rollover for shutdown to occur
0
Shutdown event occurs immediately
Bit 12 – SSDG CCP Software Shutdown/Gate Control bit
Value
Description
1
Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of ASDGM
bit still applies)
0
Normal module operation
Bits 7:0 – ASDG[7:0] CCP Auto-Shutdown/Gating Source Enable bits
Value
Description
10000000
OCFB
01000000
OCFA
00100000
CLC4
00010000
MCCP5
00001000
MCCP6
00000100
CMP3 out
00000010
CMP2 out
00000001
CMP1 out
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 544
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.64 CCP4 Control 2 High Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP4CON2H
0x306
15
OENSYNC
R/W
0
14
7
6
13
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
ICS[2:0]
R/W
0
0
OC[F:A]EN
R/W
0
R/W
0
5
4
ICGSM[1:0]
Access
Reset
12
R/W
0
R/W
0
3
AUXOUT[1:0]
R/W
R/W
0
0
R/W
0
R/W
0
Bit 15 – OENSYNC Output Enable Synchronization bit
Value
Description
1
Update by output enable bits occurs on the next Time Base Reset or rollover
0
Update by output enable bits occurs immediately
Bits 13:8 – OC[F:A]EN Output Enable/Steering Control bits
Value
Description
1
OCx pin is controlled by the CCPx module and produces an output compare or PWM signal
0
OCx pin is not controlled by the CCPx module; the pin is available to the port logic or another
peripheral multiplexed on the pin
Bits 7:6 – ICGSM[1:0] Input Capture Gating Source Mode Control bits
Value
Description
11
Reserved
10
One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)
01
One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)
00
Level-Sensitive mode: A high level from gating source will enable future capture events; a low level will
disable future capture events
Bits 4:3 – AUXOUT[1:0] Auxiliary Output Signal on Event Selection bits
Value
Description
11
Input capture or output compare event; no signal in Timer mode
10
Signal output depends on module operating mode
01
Time base rollover event (all modes)
00
Disabled
Bits 2:0 – ICS[2:0] Input Capture Source Select bits
Value
Description
111
CLC4
110
CLC3
101
CLC2
100
CLC1
011
Comparator 3
010
Comparator 2
001
Comparator 1
000
Input capture pin (ICM4)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 545
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.65 CCP4 Control 3 Low Register
Name:
Offset:
Bit
CCP4CON3L
0x308
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
R/W
0
R/W
0
2
DT[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 4:0 – DT[4:0] PWM Dead-Time Select bits
Value
Description
111111
Inserts 63 dead-time delay periods between complementary output signals
111110
Inserts 62 dead-time delay periods between complementary output signals
...
000010
Inserts 2 dead-time delay periods between complementary output signals
000001
Inserts 1 dead-time delay period between complementary output signals
000000
Dead-time logic is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 546
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.66 CCP4 Control 3 High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP4CON3H
0x30A
15
OETRIG
R/W
0
14
R/W
0
7
6
13
OSCNT[2:0]
R/W
0
12
R/W
0
5
POLACE
R/W
0
4
POLBDF
R/W
0
11
10
R/W
0
3
2
PSSACE[1:0]
R/W
R/W
0
0
9
OUTM[2:0]
R/W
0
8
R/W
0
1
0
PSSBDF[1:0]
R/W
R/W
0
0
Bit 15 – OETRIG CCP Dead-Time Select bit
Value
Description
1
For Triggered mode (TRIGEN = 1): Module does not drive enabled output pins until triggered
0
Normal output pin operation
Bits 14:12 – OSCNT[2:0] One-Shot Event Count bits
Value
Description
111
Extends one-shot event by 7 time base periods (8 time base periods total)
110
Extends one-shot event by 6 time base periods (7 time base periods total)
101
Extends one-shot event by 5 time base periods (6 time base periods total)
100
Extends one-shot event by 4 time base periods (5 time base periods total)
011
Extends one-shot event by 3 time base periods (4 time base periods total)
010
Extends one-shot event by 2 time base periods (3 time base periods total)
001
Extends one-shot event by 1 time base period (2 time base periods total)
000
Does not extend one-shot trigger event
Bits 10:8 – OUTM[2:0] PWM Output Mode Control bits
Value
Description
111
Reserved
110
Output Scan mode
101
Brush DC Output mode, forward
100
Brush DC Output mode, reverse
011
Reserved
010
Half-Bridge Output mode
001
Push-Pull Output mode
000
Steerable Single Output mode
Bit 5 – POLACE CCP Output Pins, OCMxA, OCMxC and OCMxE, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bit 4 – POLBDF CCP Output Pins, OCMxB, OCMxD and OCMxF, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bits 3:2 – PSSACE[1:0] PWM Output Pins, OCMxA, OCMxC and OCMxE, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 547
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
10
0x
Description
Pins are driven inactive when a shutdown event occurs
Pins are tri-stated when a shutdown event occurs
Bits 1:0 – PSSBDF[1:0] PWM Output Pins, OCMxB, OCMxD and OCMxF, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
10
Pins are driven inactive when a shutdown event occurs
0x
Pins are in a high-impedance state when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 548
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.67 CCP4 Status Register Low
Name:
Offset:
CCP4STATL
0x30C
Legend: C = Clearable bit; W1 = Write ‘1’ Only bit
Bit
15
14
13
12
11
10
ICGARM
W
0
9
8
7
CCPTRIG
R
0
6
TRSET
W1
0
5
TRCLR
W1
0
4
ASEVT
R/C
0
3
SCEVT
R/C
0
2
ICDIS
R/C
0
1
ICOV
R/C
0
0
ICBNE
R/C
0
Access
Reset
Bit
Access
Reset
Bit 10 – ICGARM Input Capture Gate Arm bit
A write of ‘1’ to this location will arm the input capture module for a one-shot gating event when ICGSM[1:0] = 01 or
10; read as ‘0’.
Bit 7 – CCPTRIG CCP Trigger Status bit
Value
Description
1
Timer has been triggered and is running
0
Timer has not been triggered and is held in Reset
Bit 6 – TRSET CCP Trigger Set Request bit
Writes ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads as ‘0’).
Bit 5 – TRCLR CCP Trigger Clear Request bit
Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads as ‘0’).
Bit 4 – ASEVT CCP Auto-Shutdown Event Status/Control bit
Value
Description
1
A shutdown event is in progress; CCP outputs are in the shutdown state
0
CCP outputs operate normally
Bit 3 – SCEVT Single Edge Compare Event Status bit
Value
Description
1
A single edge compare event has occurred
0
A single edge compare event has not occurred
Bit 2 – ICDIS Input Capture Disable bit
Value
Description
1
Event on input capture pin (ICM4) does not generate a capture event
0
Event on input capture pin will generate a capture event
Bit 1 – ICOV Input Capture Buffer Overflow Status bit
Value
Description
1
The input capture FIFO buffer has overflowed
0
The input capture FIFO buffer has not overflowed
Bit 0 – ICBNE Input Capture Buffer Status bit
Value
Description
1
Input capture buffer has data available
0
Input capture buffer is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 549
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.68 CCP4 Time Base Low Register
Name:
Offset:
Bit
15
CCP4TMRL
0x310
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMRL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TMRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMRL[15:0] CCP4 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 550
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.69 CCP4 Time Base High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP4TMRH
0x312
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
TMRH[31:24]
R/W
R/W
0
0
4
3
TMRH[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – TMRH[31:24] CCP4 16-Bit Time Base Value bits
Bits 7:0 – TMRH[23:16] CCP4 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 551
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.70 CCP4 Period Low Register
Name:
Offset:
Bit
15
CCP4PRL
0x314
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PRL[15:0] CCP4 Period Low Register bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 552
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.71 CCP4 Period High Register
Name:
Offset:
Bit
15
CCP4PRH
0x316
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRH[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRH[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – PRH[31:24] CCP4 Period High Register bits
Bits 7:0 – PRH[23:16] CCP4 Period High Register bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 553
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.72 CCP4 Primary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP4RA
0x318
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP4 Primary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 554
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.73 CCP4 Secondary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP4RB
0x31C
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP4 Secondary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 555
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.74 CCP4 Capture Buffer Low Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP4BUFL
0x320
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BUF[15:0] CCP4 Compare Buffer Value bits
Indicates the oldest captured time base value in the FIFO.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 556
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.75 CCP4 Capture Buffer High Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP4BUFH
0x322
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – BUF[31:24] CCP4 Compare Buffer Value bits
Bits 7:0 – BUF[23:16] CCP4 Compare Buffer Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 557
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.76 CCP5 Control 1 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
15
CCPON
R/W
0
7
CCP5CON1L
0x324
14
6
TMRPS[1:0]
R/W
R/W
0
0
13
CCPSIDL
R/W
0
12
CCPSLP
R/W
0
11
TMRSYNC
R/W
0
10
R/W
0
5
T32
R/W
0
4
CCSEL
R/W
0
3
2
9
CLKSEL[2:0]
R/W
0
8
R/W
0
1
0
R/W
0
R/W
0
MOD[3:0]
R/W
0
R/W
0
Bit 15 – CCPON CCP Module Enable bit
Value
Description
1
Module is enabled with an operating mode specified by the MOD[3:0] control bits
0
Module is disabled
Bit 13 – CCPSIDL CCP Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bit 12 – CCPSLP CCP Sleep Mode Enable bit
Value
Description
1
Module continues to operate in Sleep modes
0
Module does not operate in Sleep modes
Bit 11 – TMRSYNC Time Base Clock Synchronization bit
Value
Description
1
Module time base clock is synchronized to the internal system clocks; timing restrictions apply
0
Module time base clock is not synchronized to the internal system clocks
Bits 10:8 – CLKSEL[2:0] CCP Time Base Clock Select bits
Value
Description
111
TCKIA pin
110
TCKIB pin
101
PLL clock
100
2x peripheral clock
011
CLC1
010
SOSC clock
001
Reference clock output
000
Peripheral clock
Bits 7:6 – TMRPS[1:0] Time Base Prescale Select bits
Value
Description
11
1:64 prescaler
10
1:16 prescaler
01
1:4 prescaler
00
1:1 prescaler
Bit 5 – T32 32-Bit Time Base Select bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 558
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
1
0
Description
Uses 32-bit time base for timer, single edge output compare or input capture function
Uses 16-bit time base for timer, single edge output compare or input capture function
Bit 4 – CCSEL Capture/Compare Mode Select bit
Value
Description
1
Input capture peripheral
0
Output Compare/PWM/Timer peripheral (exact function is selected by the MOD[3:0] bits)
Bits 3:0 – MOD[3:0] CCP Mode Select bits
For CCSEL = 1 (Input Capture modes):
Value
Description
1xxx
Reserved
011x
Reserved
0101
Capture every 16th rising edge
0100
Capture every 4th rising edge
0011
Capture every rising and falling edge
0010
Capture every falling edge
0001
Capture every rising edge
0000
Capture every rising and falling edge (Edge Detect mode)
For CCSEL = 0 (Output Compare/Timer modes):
Value
Description
1111
External Input mode: Pulse generator is disabled, source is selected by ICS[2:0]
1110
Reserved
110x
Reserved
10xx
Reserved
0111
Reserved
0110
Reserved
0101
Dual Edge Compare mode, buffered
0100
Dual Edge Compare mode
0011
16-Bit/32-Bit Single Edge mode, toggles output on compare match
0010
16-Bit/32-Bit Single Edge mode, drives output low on compare match
0001
16-Bit/32-Bit Single Edge mode, drives output high on compare match
0000
16-Bit/32-Bit Timer mode, output functions are disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 559
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.77 CCP5 Control 1 High Register
Name:
Offset:
CCP5CON1H
0x326
Notes:
1. This control bit has no function in Input Capture modes.
2. This control bit has no function when TRIGEN = 0.
3.
Bit
Access
Reset
Bit
Access
Reset
Output postscale settings, from 1:5 to 1:16 (0100-1111), will result in a FIFO buffer overflow for
Input Capture modes.
15
OPSSRC
R/W
0
14
RTRGEN
R/W
0
13
7
TRIGEN
R/W
0
6
ONESHOT
R/W
0
5
ALTSYNC
R/W
0
12
11
10
9
8
OPS3[3:0]
R/W
0
R/W
0
R/W
0
R/W
0
4
3
1
0
R/W
0
R/W
0
2
SYNC[4:0]
R/W
0
R/W
0
R/W
0
Bit 15 – OPSSRC Output Postscaler Source Select bit(1)
Value
Description
1
Output postscaler scales module trigger output events
0
Output postscaler scales time base interrupt events
Bit 14 – RTRGEN Retrigger Enable bit(2)
Value
Description
1
Time base can be retriggered when TRIGEN bit = 1
0
Time base may not be retriggered when TRIGEN bit = 1
Bits 11:8 – OPS3[3:0] CCP Interrupt Output Postscale Select bits(3)
Value
Description
1111
Interrupt every 16th time base period match
1110
Interrupt every 15th time base period match
. . .
0100
Interrupt every 5th time base period match
0011
Interrupt every 4th time base period match or 4th input capture event
0010
Interrupt every 3rd time base period match or 3rd input capture event
0001
Interrupt every 2nd time base period match or 2nd input capture event
0000
Interrupt after each time base period match or input capture event
Bit 7 – TRIGEN CCP Trigger Enable bit
Value
Description
1
Trigger operation of time base is enabled
0
Trigger operation of time base is disabled
Bit 6 – ONESHOT One-Shot Trigger Mode Enable bit
Value
Description
1
One-Shot Trigger mode is enabled; trigger duration is set by OSCNT[2:0]
0
One-Shot Trigger mode is disabled
Bit 5 – ALTSYNC CCP Clock Select bit
Value
Description
1
An alternate signal is used as the module synchronization output signal
0
The module synchronization output signal is the Time Base Reset/rollover event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 560
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Bits 4:0 – SYNC[4:0] CCP Synchronization Source Select bits
SYNC[4:0]
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Synchronization Source
None; timer with rollover on CCP5PR match or FFFFh
Reserved
Reserved
Reserved
A/D start conversion
CMP3 trigger
CMP2 trigger
CMP1 trigger
Reserved
Reserved
Reserved
Reserved
CLC4 output
CLC3 output
CLC2 output
CLC1 output
Reserved
MCCP8 sync output
INT4 pin
INT3 pin
INT2 pin
INT1 pin
INT0 pin
MCCP7 sync output
MCCP6 sync output
MCCP5 sync output
MCCP4 sync output
MCCP3 sync output
MCCP2 sync output
MCCP1 sync output
MCCP5 sync output
MCCP5 timer sync output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 561
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.78 CCP5 Control 2 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP5CON2L
0x328
15
PWMRSEN
R/W
0
14
ASDGM
R/W
0
13
12
SSDG
R/W
0
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ASDG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 15 – PWMRSEN CCP PWM Restart Enable bit
Value
Description
1
ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has
ended
0
ASEVT bit must be cleared in software to resume PWM activity on output pins
Bit 14 – ASDGM CCP Auto-Shutdown Gate Mode Enable bit
Value
Description
1
Waits until the next Time Base Reset or rollover for shutdown to occur
0
Shutdown event occurs immediately
Bit 12 – SSDG CCP Software Shutdown/Gate Control bit
Value
Description
1
Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of ASDGM
bit still applies)
0
Normal module operation
Bits 7:0 – ASDG[7:0] CCP Auto-Shutdown/Gating Source Enable bits
Value
Description
10000000
OCFB
01000000
OCFA
00100000
CLC1
00010000
MCCP6
00001000
MCCP7
00000100
CMP3 out
00000010
CMP2 out
00000001
CMP1 out
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 562
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.79 CCP5 Control 2 High Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP5CON2H
0x32A
15
OENSYNC
R/W
0
14
7
6
13
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
ICS[2:0]
R/W
0
0
OC[F:A]EN
R/W
0
R/W
0
5
4
ICGSM[1:0]
Access
Reset
12
R/W
0
R/W
0
3
AUXOUT[1:0]
R/W
R/W
0
0
R/W
0
R/W
0
Bit 15 – OENSYNC Output Enable Synchronization bit
Value
Description
1
Update by output enable bits occurs on the next Time Base Reset or rollover
0
Update by output enable bits occurs immediately
Bits 13:8 – OC[F:A]EN Output Enable/Steering Control bits
Value
Description
1
OCx pin is controlled by the CCPx module and produces an output compare or PWM signal
0
OCx pin is not controlled by the CCPx module; the pin is available to the port logic or another
peripheral multiplexed on the pin
Bits 7:6 – ICGSM[1:0] Input Capture Gating Source Mode Control bits
Value
Description
11
Reserved
10
One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)
01
One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)
00
Level-Sensitive mode: A high level from gating source will enable future capture events; a low level will
disable future capture events
Bits 4:3 – AUXOUT[1:0] Auxiliary Output Signal on Event Selection bits
Value
Description
11
Input capture or output compare event; no signal in Timer mode
10
Signal output depends on module operating mode
01
Time base rollover event (all modes)
00
Disabled
Bits 2:0 – ICS[2:0] Input Capture Source Select bits
Value
Description
111
CLC4
110
CLC3
101
CLC2
100
CLC1
011
Comparator 3
010
Comparator 2
001
Comparator 1
000
Input capture pin (ICM5)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 563
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.80 CCP5 Control 3 Low Register
Name:
Offset:
Bit
CCP5CON3L
0x32C
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
R/W
0
R/W
0
2
DT[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 4:0 – DT[4:0] PWM Dead-Time Select bits
Value
Description
111111
Inserts 63 dead-time delay periods between complementary output signals
111110
Inserts 62 dead-time delay periods between complementary output signals
...
000010
Inserts 2 dead-time delay periods between complementary output signals
000001
Inserts 1 dead-time delay period between complementary output signals
000000
Dead-time logic is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 564
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.81 CCP5 Control 3 High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP5CON3H
0x32E
15
OETRIG
R/W
0
14
R/W
0
7
6
13
OSCNT[2:0]
R/W
0
12
R/W
0
5
POLACE
R/W
0
4
POLBDF
R/W
0
11
10
R/W
0
3
2
PSSACE[1:0]
R/W
R/W
0
0
9
OUTM[2:0]
R/W
0
8
R/W
0
1
0
PSSBDF[1:0]
R/W
R/W
0
0
Bit 15 – OETRIG CCP Dead-Time Select bit
Value
Description
1
For Triggered mode (TRIGEN = 1): Module does not drive enabled output pins until triggered
0
Normal output pin operation
Bits 14:12 – OSCNT[2:0] One-Shot Event Count bits
Value
Description
111
Extends one-shot event by 7 time base periods (8 time base periods total)
110
Extends one-shot event by 6 time base periods (7 time base periods total)
101
Extends one-shot event by 5 time base periods (6 time base periods total)
100
Extends one-shot event by 4 time base periods (5 time base periods total)
011
Extends one-shot event by 3 time base periods (4 time base periods total)
010
Extends one-shot event by 2 time base periods (3 time base periods total)
001
Extends one-shot event by 1 time base period (2 time base periods total)
000
Does not extend one-shot trigger event
Bits 10:8 – OUTM[2:0] PWM Output Mode Control bits
Value
Description
111
Reserved
110
Output Scan mode
101
Brush DC Output mode, forward
100
Brush DC Output mode, reverse
011
Reserved
010
Half-Bridge Output mode
001
Push-Pull Output mode
000
Steerable Single Output mode
Bit 5 – POLACE CCP Output Pins, OCMxA, OCMxC and OCMxE, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bit 4 – POLBDF CCP Output Pins, OCMxB, OCMxD and OCMxF, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bits 3:2 – PSSACE[1:0] PWM Output Pins, OCMxA, OCMxC and OCMxE, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 565
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
10
0x
Description
Pins are driven inactive when a shutdown event occurs
Pins are tri-stated when a shutdown event occurs
Bits 1:0 – PSSBDF[1:0] PWM Output Pins, OCMxB, OCMxD and OCMxF, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
10
Pins are driven inactive when a shutdown event occurs
0x
Pins are in a high-impedance state when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 566
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.82 CCP5 Status Register Low
Name:
Offset:
CCP5STATL
0x330
Legend: C = Clearable bit; W1 = Write ‘1’ Only bit
Bit
15
14
13
12
11
10
ICGARM
W
0
9
8
7
CCPTRIG
R
0
6
TRSET
W1
0
5
TRCLR
W1
0
4
ASEVT
R/C
0
3
SCEVT
R/C
0
2
ICDIS
R/C
0
1
ICOV
R/C
0
0
ICBNE
R/C
0
Access
Reset
Bit
Access
Reset
Bit 10 – ICGARM Input Capture Gate Arm bit
A write of ‘1’ to this location will arm the Input Capture x module for a one-shot gating event when ICGSM[1:0] = 01
or 10; read as ‘0’.
Bit 7 – CCPTRIG CCP Trigger Status bit
Value
Description
1
Timer has been triggered and is running
0
Timer has not been triggered and is held in Reset
Bit 6 – TRSET CCP Trigger Set Request bit
Writes ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads as ‘0’).
Bit 5 – TRCLR CCP Trigger Clear Request bit
Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads as ‘0’).
Bit 4 – ASEVT CCP Auto-Shutdown Event Status/Control bit
Value
Description
1
A shutdown event is in progress; CCP outputs are in the shutdown state
0
CCP outputs operate normally
Bit 3 – SCEVT Single Edge Compare Event Status bit
Value
Description
1
A single edge compare event has occurred
0
A single edge compare event has not occurred
Bit 2 – ICDIS Input Capture Disable bit
Value
Description
1
Event on input capture pin (ICM5) does not generate a capture event
0
Event on input capture pin will generate a capture event
Bit 1 – ICOV Input Capture Buffer Overflow Status bit
Value
Description
1
The input capture FIFO buffer has overflowed
0
The input capture FIFO buffer has not overflowed
Bit 0 – ICBNE Input Capture Buffer Status bit
Value
Description
1
Input capture buffer has data available
0
Input capture buffer is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 567
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.83 CCP5 Time Base Low Register
Name:
Offset:
Bit
15
CCP5TMRL
0x334
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMRL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TMRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMRL[15:0] CCP5 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 568
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.84 CCP5 Time Base High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP5TMRH
0x336
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
TMRH[31:24]
R/W
R/W
0
0
4
3
TMRH[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – TMRH[31:24] CCP5 16-Bit Time Base Value bits
Bits 7:0 – TMRH[23:16] CCP5 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 569
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.85 CCP5 Period Low Register
Name:
Offset:
Bit
15
CCP5PRL
0x338
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PRL[15:0] CCP5 Period Low Register bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 570
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.86 CCP5 Period High Register
Name:
Offset:
Bit
15
CCP5PRH
0x33A
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRH[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRH[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – PRH[31:24] CCP5 Period High Register bits
Bits 7:0 – PRH[23:16] CCP5 Period High Register bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 571
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.87 CCP5 Primary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP5RA
0x33C
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP5 Primary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 572
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.88 CCP5 Secondary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP5RB
0x340
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP5 Secondary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 573
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.89 CCP5 Capture Buffer Low Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP5BUFL
0x344
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BUF[15:0] CCP5 Compare Buffer Value bits
Indicates the oldest captured time base value in the FIFO.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 574
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.90 CCP5 Capture Buffer High Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP5BUFH
0x346
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – BUF[31:24] CCP5 Compare Buffer Value bits
Bits 7:0 – BUF[23:16] CCP5 Compare Buffer Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 575
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.91 CCP6 Control 1 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
15
CCPON
R/W
0
7
CCP6CON1L
0x348
14
6
TMRPS[1:0]
R/W
R/W
0
0
13
CCPSIDL
R/W
0
12
CCPSLP
R/W
0
11
TMRSYNC
R/W
0
10
R/W
0
5
T32
R/W
0
4
CCSEL
R/W
0
3
2
9
CLKSEL[2:0]
R/W
0
8
R/W
0
1
0
R/W
0
R/W
0
MOD[3:0]
R/W
0
R/W
0
Bit 15 – CCPON CCP Module Enable bit
Value
Description
1
Module is enabled with an operating mode specified by the MOD[3:0] control bits
0
Module is disabled
Bit 13 – CCPSIDL CCP Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bit 12 – CCPSLP CCP Sleep Mode Enable bit
Value
Description
1
Module continues to operate in Sleep modes
0
Module does not operate in Sleep modes
Bit 11 – TMRSYNC Time Base Clock Synchronization bit
Value
Description
1
Module time base clock is synchronized to the internal system clocks; timing restrictions apply
0
Module time base clock is not synchronized to the internal system clocks
Bits 10:8 – CLKSEL[2:0] CCP Time Base Clock Select bits(1)
Value
Description
111
TCKIA pin
110
TCKIB pin
101
PLL clock
100
2x peripheral clock
011
CLC2
010
SOSC clock
001
Reference clock output
000
Peripheral clock
Bits 7:6 – TMRPS[1:0] Time Base Prescale Select bits
Value
Description
11
1:64 prescaler
10
1:16 prescaler
01
1:4 prescaler
00
1:1 prescaler
Bit 5 – T32 32-Bit Time Base Select bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 576
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
1
0
Description
Uses 32-bit time base for timer, single edge output compare or input capture function
Uses 16-bit time base for timer, single edge output compare or input capture function
Bit 4 – CCSEL Capture/Compare Mode Select bit
Value
Description
1
Input capture peripheral
0
Output Compare/PWM/Timer peripheral (exact function is selected by the MOD[3:0] bits)
Bits 3:0 – MOD[3:0] CCP Mode Select bits
For CCSEL = 1 (Input Capture modes):
Value
Description
1xxx
Reserved
011x
Reserved
0101
Capture every 16th rising edge
0100
Capture every 4th rising edge
0011
Capture every rising and falling edge
0010
Capture every falling edge
0001
Capture every rising edge
0000
Capture every rising and falling edge (Edge Detect mode)
For CCSEL = 0 (Output Compare/Timer modes):
Value
Description
1111
External Input mode: Pulse generator is disabled, source is selected by ICS[2:0]
1110
Reserved
110x
Reserved
10xx
Reserved
0111
Reserved
0110
Reserved
0101
Dual Edge Compare mode, buffered
0100
Dual Edge Compare mode
0011
16-Bit/32-Bit Single Edge mode, toggles output on compare match
0010
16-Bit/32-Bit Single Edge mode, drives output low on compare match
0001
16-Bit/32-Bit Single Edge mode, drives output high on compare match
0000
16-Bit/32-Bit Timer mode, output functions are disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 577
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.92 CCP6 Control 1 High Register
Name:
Offset:
CCP6CON1H
0x34A
Notes:
1. This control bit has no function in Input Capture modes.
2. This control bit has no function when TRIGEN = 0.
3.
Bit
Access
Reset
Bit
Access
Reset
Output postscale settings, from 1:5 to 1:16 (0100-1111), will result in a FIFO buffer overflow for
Input Capture modes.
15
OPSSRC
R/W
0
14
RTRGEN
R/W
0
13
7
TRIGEN
R/W
0
6
ONESHOT
R/W
0
5
ALTSYNC
R/W
0
12
11
10
9
8
OPS3[3:0]
R/W
0
R/W
0
R/W
0
R/W
0
4
3
1
0
R/W
0
R/W
0
2
SYNC[4:0]
R/W
0
R/W
0
R/W
0
Bit 15 – OPSSRC Output Postscaler Source Select bit(1)
Value
Description
1
Output postscaler scales module trigger output events
0
Output postscaler scales time base interrupt events
Bit 14 – RTRGEN Retrigger Enable bit(2)
Value
Description
1
Time base can be retriggered when TRIGEN bit = 1
0
Time base may not be retriggered when TRIGEN bit = 1
Bits 11:8 – OPS3[3:0] CCP Interrupt Output Postscale Select bits(3)
Value
Description
1111
Interrupt every 16th time base period match
1110
Interrupt every 15th time base period match
. . .
0100
Interrupt every 5th time base period match
0011
Interrupt every 4th time base period match or 4th input capture event
0010
Interrupt every 3rd time base period match or 3rd input capture event
0001
Interrupt every 2nd time base period match or 2nd input capture event
0000
Interrupt after each time base period match or input capture event
Bit 7 – TRIGEN CCP Trigger Enable bit
Value
Description
1
Trigger operation of time base is enabled
0
Trigger operation of time base is disabled
Bit 6 – ONESHOT One-Shot Trigger Mode Enable bit
Value
Description
1
One-Shot Trigger mode is enabled; trigger duration is set by OSCNT[2:0]
0
One-Shot Trigger mode is disabled
Bit 5 – ALTSYNC CCP Clock Select bit
Value
Description
1
An alternate signal is used as the module synchronization output signal
0
The module synchronization output signal is the Time Base Reset/rollover event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 578
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Bits 4:0 – SYNC[4:0] CCP Synchronization Source Select bits
SYNC[4:0]
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Synchronization Source
None; timer with rollover on CCP6PR match or FFFFh
Reserved
Reserved
Reserved
A/D start conversion
CMP3 trigger
CMP2 trigger
CMP1 trigger
Reserved
Reserved
Reserved
Reserved
CLC4 output
CLC3 output
CLC2 output
CLC1 output
Reserved
MCCP8 sync output
INT4 pin
INT3 pin
INT2 pin
INT1 pin
INT0 pin
MCCP7 sync output
MCCP6 sync output
MCCP5 sync output
MCCP4 sync output
MCCP3 sync output
MCCP2 sync output
MCCP1 sync output
MCCP6 sync output
MCCP6 timer sync output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 579
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.93 CCP6 Control 2 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP6CON2L
0x34C
15
PWMRSEN
R/W
0
14
ASDGM
R/W
0
13
12
SSDG
R/W
0
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ASDG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 15 – PWMRSEN CCP PWM Restart Enable bit
Value
Description
1
ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has
ended
0
ASEVT bit must be cleared in software to resume PWM activity on output pins
Bit 14 – ASDGM CCP Auto-Shutdown Gate Mode Enable bit
Value
Description
1
Waits until the next Time Base Reset or rollover for shutdown to occur
0
Shutdown event occurs immediately
Bit 12 – SSDG CCP Software Shutdown/Gate Control bit
Value
Description
1
Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of ASDGM
bit still applies)
0
Normal module operation
Bits 7:0 – ASDG[7:0] CCP Auto-Shutdown/Gating Source Enable bits
Value
Description
10000000
OCFB
01000000
OCFA
00100000
CLC1
00010000
MCCP7
00001000
MCCP8
00000100
CMP3 out
00000010
CMP2 out
00000001
CMP1 out
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 580
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.94 CCP6 Control 2 High Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP6CON2H
0x34E
15
OENSYNC
R/W
0
14
7
6
13
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
ICS[2:0]
R/W
0
0
OC[F:A]EN
R/W
0
R/W
0
5
4
ICGSM[1:0]
Access
Reset
12
R/W
0
R/W
0
3
AUXOUT[1:0]
R/W
R/W
0
0
R/W
0
R/W
0
Bit 15 – OENSYNC Output Enable Synchronization bit
Value
Description
1
Update by output enable bits occurs on the next Time Base Reset or rollover
0
Update by output enable bits occurs immediately
Bits 13:8 – OC[F:A]EN Output Enable/Steering Control bits
Value
Description
1
OCx pin is controlled by the CCP module and produces an output compare or PWM signal
0
OCx pin is not controlled by the CCP module; the pin is available to the port logic or another peripheral
multiplexed on the pin
Bits 7:6 – ICGSM[1:0] Input Capture Gating Source Mode Control bits
Value
Description
11
Reserved
10
One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)
01
One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)
00
Level-Sensitive mode: A high level from gating source will enable future capture events; a low level will
disable future capture events
Bits 4:3 – AUXOUT[1:0] Auxiliary Output Signal on Event Selection bits
Value
Description
11
Input capture or output compare event; no signal in Timer mode
10
Signal output depends on module operating mode
01
Time base rollover event (all modes)
00
Disabled
Bits 2:0 – ICS[2:0] Input Capture Source Select bits
Value
Description
111
CLC4
110
CLC3
101
CLC2
100
CLC1
011
Comparator 3
010
Comparator 2
001
Comparator 1
000
Input capture pin (ICM6)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 581
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.95 CCP6 Control 3 Low Register
Name:
Offset:
Bit
CCP6CON3L
0x350
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
R/W
0
R/W
0
2
DT[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 4:0 – DT[4:0] PWM Dead-Time Select bits
Value
Description
111111
Inserts 63 dead-time delay periods between complementary output signals
111110
Inserts 62 dead-time delay periods between complementary output signals
...
000010
Inserts 2 dead-time delay periods between complementary output signals
000001
Inserts 1 dead-time delay period between complementary output signals
000000
Dead-time logic is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 582
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.96 CCP6 Control 3 High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP6CON3H
0x352
15
OETRIG
R/W
0
14
R/W
0
7
6
13
OSCNT[2:0]
R/W
0
12
R/W
0
5
POLACE
R/W
0
4
POLBDF
R/W
0
11
10
R/W
0
3
2
PSSACE[1:0]
R/W
R/W
0
0
9
OUTM[2:0]
R/W
0
8
R/W
0
1
0
PSSBDF[1:0]
R/W
R/W
0
0
Bit 15 – OETRIG CCP Dead-Time Select bit
Value
Description
1
For Triggered mode (TRIGEN = 1): Module does not drive enabled output pins until triggered
0
Normal output pin operation
Bits 14:12 – OSCNT[2:0] One-Shot Event Count bits
Value
Description
111
Extends one-shot event by 7 time base periods (8 time base periods total)
110
Extends one-shot event by 6 time base periods (7 time base periods total)
101
Extends one-shot event by 5 time base periods (6 time base periods total)
100
Extends one-shot event by 4 time base periods (5 time base periods total)
011
Extends one-shot event by 3 time base periods (4 time base periods total)
010
Extends one-shot event by 2 time base periods (3 time base periods total)
001
Extends one-shot event by 1 time base period (2 time base periods total)
000
Does not extend one-shot trigger event
Bits 10:8 – OUTM[2:0] PWM Output Mode Control bits
Value
Description
111
Reserved
110
Output Scan mode
101
Brush DC Output mode, forward
100
Brush DC Output mode, reverse
011
Reserved
010
Half-Bridge Output mode
001
Push-Pull Output mode
000
Steerable Single Output mode
Bit 5 – POLACE CCP Output Pins, OCMxA, OCMxC and OCMxE, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bit 4 – POLBDF CCP Output Pins, OCMxB, OCMxD and OCMxF, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bits 3:2 – PSSACE[1:0] PWM Output Pins, OCMxA, OCMxC and OCMxE, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 583
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
10
0x
Description
Pins are driven inactive when a shutdown event occurs
Pins are tri-stated when a shutdown event occurs
Bits 1:0 – PSSBDF[1:0] PWM Output Pins, OCMxB, OCMxD and OCMxF, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
10
Pins are driven inactive when a shutdown event occurs
0x
Pins are in a high-impedance state when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 584
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.97 CCP6 Status Register Low
Name:
Offset:
CCP6STATL
0x354
Legend: C = Clearable bit; W1 = Write ‘1’ Only bit
Bit
15
14
13
12
11
10
ICGARM
W
0
9
8
7
CCPTRIG
R
0
6
TRSET
W1
0
5
TRCLR
W1
0
4
ASEVT
R/C
0
3
SCEVT
R/C
0
2
ICDIS
R/C
0
1
ICOV
R/C
0
0
ICBNE
R/C
0
Access
Reset
Bit
Access
Reset
Bit 10 – ICGARM Input Capture Gate Arm bit
A write of ‘1’ to this location will arm the Input Capture x module for a one-shot gating event when ICGSM[1:0] = 01
or 10; read as ‘0’.
Bit 7 – CCPTRIG CCP Trigger Status bit
Value
Description
1
Timer has been triggered and is running
0
Timer has not been triggered and is held in Reset
Bit 6 – TRSET CCP Trigger Set Request bit
Writes ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads as ‘0’).
Bit 5 – TRCLR CCP Trigger Clear Request bit
Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads as ‘0’).
Bit 4 – ASEVT CCP Auto-Shutdown Event Status/Control bit
Value
Description
1
A shutdown event is in progress; CCP outputs are in the shutdown state
0
CCP outputs operate normally
Bit 3 – SCEVT Single Edge Compare Event Status bit
Value
Description
1
A single edge compare event has occurred
0
A single edge compare event has not occurred
Bit 2 – ICDIS Input Capture Disable bit
Value
Description
1
Event on input capture pin (ICM6) does not generate a capture event
0
Event on input capture pin will generate a capture event
Bit 1 – ICOV Input Capture Buffer Overflow Status bit
Value
Description
1
The input capture FIFO buffer has overflowed
0
The input capture FIFO buffer has not overflowed
Bit 0 – ICBNE Input Capture Buffer Status bit
Value
Description
1
Input capture buffer has data available
0
Input capture buffer is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 585
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.98 CCP6 Time Base Low Register
Name:
Offset:
Bit
15
CCP6TMRL
0x358
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMRL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TMRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMRL[15:0] CCP6 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 586
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.99 CCP6 Time Base High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP6TMRH
0x35A
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
TMRH[31:24]
R/W
R/W
0
0
4
3
TMRH[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – TMRH[31:24] CCP6 16-Bit Time Base Value bits
Bits 7:0 – TMRH[23:16] CCP6 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 587
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.100 CCP6 Period Low Register
Name:
Offset:
Bit
15
CCP6PRL
0x35C
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PRL[15:0] CCP6 Period Low Register bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 588
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.101 CCP6 Period High Register
Name:
Offset:
Bit
15
CCP6PRH
0x35E
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRH[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRH[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – PRH[31:24] CCP6 Period High Register bits
Bits 7:0 – PRH[23:16] CCP6 Period High Register bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 589
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.102 CCP6 Primary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP6RA
0x360
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP6 Primary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 590
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.103 CCP6 Secondary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP6RB
0x364
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP6 Secondary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 591
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.104 CCP6 Capture Buffer Low Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP6BUFL
0x368
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BUF[15:0] CCP6 Compare Buffer Value bits
Indicates the oldest captured time base value in the FIFO.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 592
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.105 CCP6 Capture Buffer High Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP6BUFH
0x36A
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – BUF[31:24] CCP6 Compare Buffer Value bits
Bits 7:0 – BUF[23:16] CCP6 Compare Buffer Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 593
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.106 CCP7 Control 1 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
15
CCPON
R/W
0
7
CCP7CON1L
0x36C
14
6
TMRPS[1:0]
R/W
R/W
0
0
13
CCPSIDL
R/W
0
12
CCPSLP
R/W
0
11
TMRSYNC
R/W
0
10
R/W
0
5
T32
R/W
0
4
CCSEL
R/W
0
3
2
9
CLKSEL[2:0]
R/W
0
8
R/W
0
1
0
R/W
0
R/W
0
MOD[3:0]
R/W
0
R/W
0
Bit 15 – CCPON CCP Module Enable bit
Value
Description
1
Module is enabled with an operating mode specified by the MOD[3:0] control bits
0
Module is disabled
Bit 13 – CCPSIDL CCP Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bit 12 – CCPSLP CCP Sleep Mode Enable bit
Value
Description
1
Module continues to operate in Sleep modes
0
Module does not operate in Sleep modes
Bit 11 – TMRSYNC Time Base Clock Synchronization bit
Value
Description
1
Module time base clock is synchronized to the internal system clocks; timing restrictions apply
0
Module time base clock is not synchronized to the internal system clocks
Bits 10:8 – CLKSEL[2:0] CCP Time Base Clock Select bits
Value
Description
111
TCKIA pin
110
TCKIB pin
101
PLL clock
100
2x peripheral clock
011
CLC3
010
SOSC clock
001
Reference clock output
000
Peripheral clock
Bits 7:6 – TMRPS[1:0] Time Base Prescale Select bits
Value
Description
11
1:64 prescaler
10
1:16 prescaler
01
1:4 prescaler
00
1:1 prescaler
Bit 5 – T32 32-Bit Time Base Select bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 594
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
1
0
Description
Uses 32-bit time base for timer, single edge output compare or input capture function
Uses 16-bit time base for timer, single edge output compare or input capture function
Bit 4 – CCSEL Capture/Compare Mode Select bit
Value
Description
1
Input capture peripheral
0
Output Compare/PWM/Timer peripheral (exact function is selected by the MOD[3:0] bits)
Bits 3:0 – MOD[3:0] CCP Mode Select bits
For CCSEL = 1 (Input Capture modes):
Value
Description
1xxx
Reserved
011x
Reserved
0101
Capture every 16th rising edge
0100
Capture every 4th rising edge
0011
Capture every rising and falling edge
0010
Capture every falling edge
0001
Capture every rising edge
0000
Capture every rising and falling edge (Edge Detect mode)
For CCSEL = 0 (Output Compare/Timer modes):
Value
Description
1111
External Input mode: Pulse generator is disabled, source is selected by ICS[2:0]
1110
Reserved
110x
Reserved
10xx
Reserved
0111
Reserved
0110
Reserved
0101
Dual Edge Compare mode, buffered
0100
Dual Edge Compare mode
0011
16-Bit/32-Bit Single Edge mode, toggles output on compare match
0010
16-Bit/32-Bit Single Edge mode, drives output low on compare match
0001
16-Bit/32-Bit Single Edge mode, drives output high on compare match
0000
16-Bit/32-Bit Timer mode, output functions are disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 595
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.107 CCP7 Control 1 High Register
Name:
Offset:
CCP7CON1H
0x36E
Notes:
1. This control bit has no function in Input Capture modes.
2. This control bit has no function when TRIGEN = 0.
3.
Bit
Access
Reset
Bit
Access
Reset
Output postscale settings, from 1:5 to 1:16 (0100-1111), will result in a FIFO buffer overflow for
Input Capture modes.
15
OPSSRC
R/W
0
14
RTRGEN
R/W
0
13
7
TRIGEN
R/W
0
6
ONESHOT
R/W
0
5
ALTSYNC
R/W
0
12
11
10
9
8
OPS3[3:0]
R/W
0
R/W
0
R/W
0
R/W
0
4
3
1
0
R/W
0
R/W
0
2
SYNC[4:0]
R/W
0
R/W
0
R/W
0
Bit 15 – OPSSRC Output Postscaler Source Select bit(1)
Value
Description
1
Output postscaler scales module trigger output events
0
Output postscaler scales time base interrupt events
Bit 14 – RTRGEN Retrigger Enable bit(2)
Value
Description
1
Time base can be retriggered when TRIGEN bit = 1
0
Time base may not be retriggered when TRIGEN bit = 1
Bits 11:8 – OPS3[3:0] CCP Interrupt Output Postscale Select bits(3)
Value
Description
1111
Interrupt every 16th time base period match
1110
Interrupt every 15th time base period match
. . .
0100
Interrupt every 5th time base period match
0011
Interrupt every 4th time base period match or 4th input capture event
0010
Interrupt every 3rd time base period match or 3rd input capture event
0001
Interrupt every 2nd time base period match or 2nd input capture event
0000
Interrupt after each time base period match or input capture event
Bit 7 – TRIGEN CCP Trigger Enable bit
Value
Description
1
Trigger operation of time base is enabled
0
Trigger operation of time base is disabled
Bit 6 – ONESHOT One-Shot Trigger Mode Enable bit
Value
Description
1
One-Shot Trigger mode is enabled; trigger duration is set by OSCNT[2:0]
0
One-Shot Trigger mode is disabled
Bit 5 – ALTSYNC CCP Clock Select bit
Value
Description
1
An alternate signal is used as the module synchronization output signal
0
The module synchronization output signal is the Time Base Reset/rollover event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 596
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Bits 4:0 – SYNC[4:0] CCP Synchronization Source Select bits
SYNC[4:0]
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Synchronization Source
None; timer with rollover on CCP7PR match or FFFFh
Reserved
Reserved
Reserved
A/D start conversion
CMP3 trigger
CMP2 trigger
CMP1 trigger
Reserved
Reserved
Reserved
Reserved
CLC4 output
CLC3 output
CLC2 output
CLC1 output
Reserved
MCCP8 sync output
INT4 pin
INT3 pin
INT2 pin
INT1 pin
INT0 pin
MCCP7 sync output
MCCP6 sync output
MCCP5 sync output
MCCP4 sync output
MCCP3 sync output
MCCP2 sync output
MCCP1 sync output
MCCP7 sync output
MCCP7 timer sync output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 597
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.108 CCP7 Control 2 Low Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP7CON2L
0x370
15
PWMRSEN
R/W
0
14
ASDGM
R/W
0
13
12
SSDG
R/W
0
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ASDG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 15 – PWMRSEN CCP PWM Restart Enable bit
Value
Description
1
ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has
ended
0
ASEVT bit must be cleared in software to resume PWM activity on output pins
Bit 14 – ASDGM CCP Auto-Shutdown Gate Mode Enable bit
Value
Description
1
Waits until the next Time Base Reset or rollover for shutdown to occur
0
Shutdown event occurs immediately
Bit 12 – SSDG CCP Software Shutdown/Gate Control bit
Value
Description
1
Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of ASDGM
bit still applies)
0
Normal module operation
Bits 7:0 – ASDG[7:0] CCP Auto-Shutdown/Gating Source Enable bits
Value
Description
10000000
OCFB
01000000
OCFA
00100000
CLC1
00010000
MCCP8
00001000
MCCP4
00000100
CMP3 out
00000010
CMP2 out
00000001
CMP1 out
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 598
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.109 CCP7 Control 2 High Register
Name:
Offset:
Bit
Access
Reset
Bit
CCP7CON2H
0x372
15
OENSYNC
R/W
0
14
7
6
13
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
2
1
ICS[2:0]
R/W
0
0
OC[F:A]EN
R/W
0
R/W
0
5
4
ICGSM[1:0]
Access
Reset
12
R/W
0
R/W
0
3
AUXOUT[1:0]
R/W
R/W
0
0
R/W
0
R/W
0
Bit 15 – OENSYNC Output Enable Synchronization bit
Value
Description
1
Update by output enable bits occurs on the next Time Base Reset or rollover
0
Update by output enable bits occurs immediately
Bits 13:8 – OC[F:A]EN Output Enable/Steering Control bits
Value
Description
1
OCx pin is controlled by the CCP module and produces an output compare or PWM signal
0
OCx pin is not controlled by the CCP module; the pin is available to the port logic or another peripheral
multiplexed on the pin
Bits 7:6 – ICGSM[1:0] Input Capture Gating Source Mode Control bits
Value
Description
11
Reserved
10
One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)
01
One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)
00
Level-Sensitive mode: A high level from gating source will enable future capture events; a low level will
disable future capture events
Bits 4:3 – AUXOUT[1:0] Auxiliary Output Signal on Event Selection bits
Value
Description
11
Input capture or output compare event; no signal in Timer mode
10
Signal output depends on module operating mode
01
Time base rollover event (all modes)
00
Disabled
Bits 2:0 – ICS[2:0] Input Capture Source Select bits
Value
Description
111
CLC4
110
CLC3
101
CLC2
100
CLC1
011
Comparator 3
010
Comparator 2
001
Comparator 1
000
Input capture pin (ICM7)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 599
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.110 CCP7 Control 3 Low Register
Name:
Offset:
Bit
CCP7CON3L
0x374
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
R/W
0
R/W
0
2
DT[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 4:0 – DT[4:0] PWM Dead-Time Select bits
Value
Description
111111
Inserts 63 dead-time delay periods between complementary output signals
111110
Inserts 62 dead-time delay periods between complementary output signals
...
000010
Inserts 2 dead-time delay periods between complementary output signals
000001
Inserts 1 dead-time delay period between complementary output signals
000000
Dead-time logic is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 600
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.111 CCP7 Control 3 High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP7CON3H
0x376
15
OETRIG
R/W
0
14
R/W
0
7
6
13
OSCNT[2:0]
R/W
0
12
R/W
0
5
POLACE
R/W
0
4
POLBDF
R/W
0
11
10
R/W
0
3
2
PSSACE[1:0]
R/W
R/W
0
0
9
OUTM[2:0]
R/W
0
8
R/W
0
1
0
PSSBDF[1:0]
R/W
R/W
0
0
Bit 15 – OETRIG CCP Dead-Time Select bit
Value
Description
1
For Triggered mode (TRIGEN = 1): Module does not drive enabled output pins until triggered
0
Normal output pin operation
Bits 14:12 – OSCNT[2:0] One-Shot Event Count bits
Value
Description
111
Extends one-shot event by 7 time base periods (8 time base periods total)
110
Extends one-shot event by 6 time base periods (7 time base periods total)
101
Extends one-shot event by 5 time base periods (6 time base periods total)
100
Extends one-shot event by 4 time base periods (5 time base periods total)
011
Extends one-shot event by 3 time base periods (4 time base periods total)
010
Extends one-shot event by 2 time base periods (3 time base periods total)
001
Extends one-shot event by 1 time base period (2 time base periods total)
000
Does not extend one-shot trigger event
Bits 10:8 – OUTM[2:0] PWM Output Mode Control bits
Value
Description
111
Reserved
110
Output Scan mode
101
Brush DC Output mode, forward
100
Brush DC Output mode, reverse
011
Reserved
010
Half-Bridge Output mode
001
Push-Pull Output mode
000
Steerable Single Output mode
Bit 5 – POLACE CCP Output Pins, OCMxA, OCMxC and OCMxE, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bit 4 – POLBDF CCP Output Pins, OCMxB, OCMxD and OCMxF, Polarity Control bit
Value
Description
1
Output pin polarity is active-low
0
Output pin polarity is active-high
Bits 3:2 – PSSACE[1:0] PWM Output Pins, OCMxA, OCMxC and OCMxE, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 601
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
Value
10
0x
Description
Pins are driven inactive when a shutdown event occurs
Pins are tri-stated when a shutdown event occurs
Bits 1:0 – PSSBDF[1:0] PWM Output Pins, OCMxB, OCMxD and OCMxF, Shutdown State Control bits
Value
Description
11
Pins are driven active when a shutdown event occurs
10
Pins are driven inactive when a shutdown event occurs
0x
Pins are in a high-impedance state when a shutdown event occurs
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 602
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.112 CCP7 Status Register Low
Name:
Offset:
CCP7STATL
0x378
Legend: C = Clearable bit; W1 = Write ‘1’ Only bit
Bit
15
14
13
12
11
10
ICGARM
W
0
9
8
7
CCPTRIG
R
0
6
TRSET
W1
0
5
TRCLR
W1
0
4
ASEVT
R/C
0
3
SCEVT
R/C
0
2
ICDIS
R/C
0
1
ICOV
R/C
0
0
ICBNE
R/C
0
Access
Reset
Bit
Access
Reset
Bit 10 – ICGARM Input Capture Gate Arm bit
A write of ‘1’ to this location will arm the Input Capture x module for a one-shot gating event when ICGSM[1:0] = 01
or 10; read as ‘0’.
Bit 7 – CCPTRIG CCP Trigger Status bit
Value
Description
1
Timer has been triggered and is running
0
Timer has not been triggered and is held in Reset
Bit 6 – TRSET CCP Trigger Set Request bit
Writes ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads as ‘0’).
Bit 5 – TRCLR CCP Trigger Clear Request bit
Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads as ‘0’).
Bit 4 – ASEVT CCP Auto-Shutdown Event Status/Control bit
Value
Description
1
A shutdown event is in progress; CCP outputs are in the shutdown state
0
CCP outputs operate normally
Bit 3 – SCEVT Single Edge Compare Event Status bit
Value
Description
1
A single edge compare event has occurred
0
A single edge compare event has not occurred
Bit 2 – ICDIS Input Capture Disable bit
Value
Description
1
Event on input capture pin (ICM7) does not generate a capture event
0
Event on input capture pin will generate a capture event
Bit 1 – ICOV Input Capture Buffer Overflow Status bit
Value
Description
1
The input capture FIFO buffer has overflowed
0
The input capture FIFO buffer has not overflowed
Bit 0 – ICBNE Input Capture Buffer Status bit
Value
Description
1
Input capture buffer has data available
0
Input capture buffer is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 603
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.113 CCP7 Time Base Low Register
Name:
Offset:
Bit
15
CCP7TMRL
0x37C
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMRL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TMRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMRL[15:0] CCP7 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 604
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.114 CCP7 Time Base High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CCP7TMRH
0x37E
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
TMRH[31:24]
R/W
R/W
0
0
4
3
TMRH[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – TMRH[31:24] CCP7 16-Bit Time Base Value bits
Bits 7:0 – TMRH[23:16] CCP7 16-Bit Time Base Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 605
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.115 CCP7 Period Low Register
Name:
Offset:
Bit
15
CCP7PRL
0x380
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRL[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PRL[15:0] CCP7 Period Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 606
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.116 CCP7 Period High Register
Name:
Offset:
Bit
15
CCP7PRH
0x382
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PRH[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PRH[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – PRH[31:24] CCP7 Period Value bits
Bits 7:0 – PRH[23:16] CCP7 Period Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 607
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.117 CCP7 Primary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP7RA
0x384
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP7 Primary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 608
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.118 CCP7 Secondary Compare Register (Timer/Compare Modes Only)
Bit
Name:
Offset:
CCP7RB
0x388
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CMP[15:0] CCP7 Secondary Compare Value bits
The 16-bit value to be compared against the CCP time base.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 609
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.119 CCP7 Capture Buffer Low Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP7BUFL
0x38C
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BUF[15:0] CCP7 Compare Buffer Value bits
Indicates the oldest captured time base value in the FIFO.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 610
PIC24FJ512GU410 Family Data Sheet
Capture/Compare/PWM/Timer Modules (MCCP)
14.6.120 CCP7 Capture Buffer High Register (Capture Modes Only)
Name:
Offset:
Bit
15
CCP7BUFH
0x38E
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BUF[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BUF[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – BUF[31:24] CCP7 Compare Buffer Value bits
Bits 7:0 – BUF[23:16] CCP7 Compare Buffer Value bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 611
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.
Serial Peripheral Interface (SPI)
Note: This data sheet summarizes the features of the PIC24FJ512GU410 family of devices. It is not intended to be
a comprehensive reference source. To complement the information in this data sheet, refer to “Serial Peripheral
Interface (SPI) with Audio Codec Support” (DS70005136) in the “dsPIC33/PIC24 Family Reference Manual”,
which is available from the Microchip website (www.microchip.com). The information in this data sheet supersedes
the information in the FRM.
The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display
®
drivers, A/D Converters, etc. The SPI module is compatible with the Motorola SPI and SIOP interfaces. All devices
in the PIC24FJ512GU410 family include four SPI modules.
The module supports operation in two buffer modes. In Standard Buffer mode, data are shifted through a single serial
buffer. In Enhanced Buffer mode, data are shifted through a FIFO buffer. The FIFO level depends on the configured
mode.
Note: FIFO depth for this device is 32 (in 8-Bit Data mode).
Variable length data can be transmitted and received from 2 to 32 bits.
Note: Do not perform Read-Modify-Write operations (such as bit-oriented instructions) on the SPIxBUF register in
either Standard or Enhanced Buffer mode.
The module also supports a basic framed SPI protocol while operating in either Master or Slave mode. A total of four
framed SPI configurations are supported.
The module also supports Audio modes. Four different Audio modes are available:
•
•
•
•
I2S mode
Left Justified mode
Right Justified mode
PCM/DSP mode
In each of these modes, the serial clock is free-running and audio data are always transferred.
If an audio protocol data transfer takes place between two devices, then usually one device is the Master and the
other is the Slave. However, audio data can be transferred between two Slaves. Because the audio protocols require
free-running clocks, the Master can be a third party controller. In either case, the Master generates two free-running
clocks: SCKx and LRC (Left, Right Channel Clock is available on the SSx/FSYNCx pin).
The SPI serial interface consists of four pins:
•
•
•
•
SDIx: Serial Data Input
SDOx: Serial Data Output
SCKx: Shift Clock Input or Output
SSx: Active-Low Slave Select or Frame Synchronization I/O Pulse
The SPI module can be configured to operate using two, three or four pins. In the 3-pin mode, SSx is not used. In the
2-pin mode, both SDOx and SSx are not used.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 612
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
The SPI module has the ability to generate three interrupts reflecting the events that occur during the data
communication. The following types of interrupts can be generated:
1.
Receive interrupts are signaled by SPIxRXIF. This event occurs when:
– RX watermark interrupt
– SPIROV = 1
– SPIRBF = 1
– SPIRBE = 1
2.
provided the respective mask bits are enabled in SPIxIMSKL/H.
Transmit interrupts are signaled by SPIxTXIF. This event occurs when:
– TX watermark interrupt
– SPITUR = 1
– SPITBF = 1
– SPITBE = 1
3.
provided the respective mask bits are enabled in SPIxIMSKL/H.
General interrupts are signaled by SPIxIF. This event occurs when:
– FRMERR = 1
– SPIBUSY = 1
– SRMT = 1
provided the respective mask bits are enabled in SPIxIMSKL/H.
A block diagram of the module in Enhanced Buffer mode is shown in Figure 15-1.
Note: In this section, the SPI modules are referred to together as SPIx, or separately as SPI1 or SPI2. Special
Function Registers will follow a similar notation. For example, SPIxCON1 and SPIxCON2 refer to the control registers
for either of the two SPI modules.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 613
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Figure 15-1. SPI Module Block Diagram (Enhanced Mode)
Internal
SPIxRXSR
SPIxTXSR
SDIx
Control
Peripheral Clock
Select
15.1
Enable Master Clock
Control
Master Mode Operation
Perform the following steps to set up the SPIx module for Master mode operation:
1.
2.
3.
4.
Disable the SPIx interrupts in the respective IECx register.
Stop and reset the SPIx module by clearing the SPIEN bit.
Clear the receive buffer.
Clear the ENHBUF bit (SPIxCON1L[0]) if using Standard Buffer mode or set the bit if using Enhanced Buffer
mode.
5. Clear the SPIx interrupt flags/events in the respective IFSx register.
6. Write the SPIx interrupt priority and sub-priority bits in the respective IPCx register.
7. Set the SPIx interrupt enable bits in the respective IECx register.
8. Write the Baud Rate register, SPIxBRGL.
9. Clear the SPIROV bit (SPIxSTATL[6]).
10. Write the desired settings to the SPIxCON1L register with MSTEN (SPIxCON1L[5]) = 1.
11. Enable SPI operation by setting the SPIEN bit (SPIxCON1L[15]).
12. Write the data to be transmitted to the SPIxBUFL and SPIxBUFH registers. Transmission (and reception) will
start as soon as data are written to the SPIxBUFL/H registers.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 614
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.2
Slave Mode Operation
The following steps are used to set up the SPIx module for the Slave mode of operation:
1.
2.
3.
4.
5.
6.
7.
8.
9.
If using interrupts, disable the SPIx interrupts in the respective IECx register.
Stop and reset the SPIx module by clearing the SPIEN bit.
Clear the receive buffer.
Clear the ENHBUF bit (SPIxCON1L[0]) if using Standard Buffer mode or set the bit if using Enhanced Buffer
mode.
Clear the SPIx interrupt flags/events in the respective IFSx register.
Write the SPIx interrupt priority and sub-priority bits in the respective IPCx register.
Set the SPIx interrupt enable bits in the respective IECx register.
Clear the SPIROV bit (SPIxSTATL[6]).
Write the desired settings to the SPIxCON1L register with MSTEN (SPIxCON1L[5]) = 0.
10. Enable SPI operation by setting the SPIEN bit (SPIxCON1L[15]).
Transmission (and reception) will start as soon as the Master provides the serial clock.
The following additional features are provided in Slave mode:
•
•
Slave Select Synchronization:
The SSx pin allows a Synchronous Slave mode. If the SSEN bit (SPIxCON1L[7]) is set, transmission and
reception are enabled in Slave mode only if the SSx pin is driven to a low state. The port output, or other
peripheral outputs, must not be driven in order to allow the SSx pin to function as an input. If the SSEN bit is set
and the SSx pin is driven high, the SDOx pin is no longer driven and will tri-state, even if the module is in the
middle of a transmission. An aborted transmission will be tried again the next time the SSx pin is driven low
using the data held in the SPIxTXB register. If the SSEN bit is not set, the SSx pin does not affect the module
operation in Slave mode.
SPITBE Status Flag Operation:
The SPITBE bit (SPIxSTATL[3]) has a different function in the Slave mode of operation. The following describes
the function of SPITBE for various settings of the Slave mode of operation:
– If SSEN (SPIxCON1L[7]) is cleared, the SPITBE bit is cleared when SPIxBUF is loaded by the user code. It
is set when the module transfers SPIxTXB to SPIxTXSR.
This is similar to the SPITBE bit function in Master mode.
– If SSEN is set, SPITBE is cleared when SPIxBUF is loaded by the user code. However, it is set only when
the SPIx module completes data transmission. A transmission will be aborted when the SSx pin goes high
and may be retried at a later time. So, each data word is held in SPIxTXB until all bits are transmitted to the
receiver.
15.3
Audio Mode Operation
To initialize the SPIx module for Audio mode, follow the steps to initialize it for Master/Slave mode, but also set the
AUDEN bit (SPIxCON1H[15]).
In Master+Audio mode:
•
This mode enables the device to generate SCKx and LRC pulses as long as the SPIEN bit
(SPIxCON1L[15]) = 1.
•
The SPIx module generates LRC and SCKx continuously in all cases, regardless of the
transmit data, while in Master mode.
The SPIx module drives the leading edge of LRC and SCKx within one SCKx period, and the serial data shift in
and out continuously, even when the TX FIFO is empty.
•
In Slave+Audio mode:
•
This mode enables the device to receive SCKx and LRC pulses as long as the SPIEN bit (SPIxCON1L[15]) = 1.
•
The SPIx module drives zeros out of SDOx, but does not shift data out or in (SDIx) until the module receives the
LRC (i.e., the edge that precedes the left channel).
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 615
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
•
15.4
Once the module receives the leading edge
of LRC, it starts receiving data if DISSDI (SPIxCON1L[4]) = 0 and the serial data shift out continuously, even
when the TX FIFO is empty.
Relationship Between Device and SPI Clock Speed
Equation 15-1. Relationship Between Device and SPI Clock Speed
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 616
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5
SPI Registers
Offset
Name
0x00
...
0x03F3
Reserved
0x03F4
SPI1CON1L
0x03F6
SPI1CON1H
0x03F8
SPI1CON2L
0x03FA
...
0x03FB
Reserved
0x03FC
SPI1STATL
0x03FE
SPI1STATH
0x0400
SPI1BUFL
0x0402
SPI1BUFH
0x0404
SPI1BRGL
0x0406
...
0x0407
Reserved
0x0408
SPI1IMSKL
0x040A
SPI1IMSKH
0x040C
SPI1URDTL
0x040E
SPI1URDTH
0x0410
SPI2CON1L
0x0412
SPI2CON1H
0x0414
SPI2CON2L
0x0416
...
0x0417
Reserved
0x0418
SPI2STATL
0x041A
SPI2STATH
0x041C
SPI2BUFL
0x041E
SPI2BUFH
0x0420
SPI2BRGL
0x0422
...
0x0423
Reserved
Bit Pos.
7
6
5
4
3
7:0
15:8
7:0
15:8
7:0
15:8
SSEN
SPIEN
FRMEN
AUDEN
CKP
FRMSYNC
SPISGNEXT
MSTEN
SPISIDL
FRMPOL
IGNROV
DISSDI
DISSDO
MSSEN
IGNTUR
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
SRMT
SPIROV
SPIRBE
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
SRMTEN
SSEN
SPIEN
FRMEN
AUDEN
FRMSYNC
SPISGNEXT
MSTEN
SPISIDL
FRMPOL
IGNROV
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
SRMT
SPIROV
SPIRBE
2
1
DISSCK
MCLKEN
SPIFE
ENHBUF
MODE[1:0]
SMP
CKE
FRMSYPW
FRMCNT[2:0]
AUDMONO
URDTEN
AUDMOD[1:0]
WLENGTH[4:0]
SPITBE
SPIBUSY
TXELM[5:0]
RXELM[5:0]
DATA[7:0]
DATA[15:8]
DATA[23:16]
DATA[31:24]
BRG[7:0]
BRG[12:8]
SPITBF
FRMERR
SPIROVEN
SPIRBEN
0
SPIRBF
SPITUR
SPITBEN
SPITBFEN
SPIRBFEN
BUSYEN
SPITUREN
TXMSK[5:0]
RXMSK[5:0]
URDATA[7:0]
URDATA[15:8]
URDATA[23:16]
URDATA[31:24]
DISSDI
DISSCK
MCLKEN
SPIFE
ENHBUF
DISSDO
MODE[1:0]
SMP
CKE
MSSEN
FRMSYPW
FRMCNT[2:0]
IGNTUR
AUDMONO
URDTEN
AUDMOD[1:0]
WLENGTH[4:0]
FRMERREN
TXWIEN
RXWIEN
© 2019-2020 Microchip Technology Inc.
CKP
SPITBE
SPIBUSY
TXELM[5:0]
RXELM[5:0]
DATA[7:0]
DATA[15:8]
DATA[23:16]
DATA[31:24]
BRG[7:0]
BRG[12:8]
FRMERR
Datasheet
SPITBF
SPIRBF
SPITUR
DS30010203C-page 617
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
...........continued
Offset
Name
Bit Pos.
7
6
5
0x0424
SPI2IMSKL
7:0
15:8
SRMTEN
SPIROVEN
SPIRBEN
0x0426
SPI2IMSKH
TXWIEN
RXWIEN
0x0428
SPI2URDTL
0x042A
SPI2URDTH
0x042C
SPI3CON1L
0x042E
SPI3CON1H
SSEN
SPIEN
FRMEN
AUDEN
FRMSYNC
SPISGNEXT
MSTEN
SPISIDL
FRMPOL
IGNROV
0x0430
SPI3CON2L
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
0x0432
...
0x0433
Reserved
0x0434
SPI3STATL
SRMT
SPIROV
SPIRBE
0x0436
SPI3STATH
0x0438
SPI3BUFL
0x043A
SPI3BUFH
0x043C
SPI3BRGL
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
0x043E
...
0x043F
Reserved
0x0440
SPI3IMSKL
SRMTEN
0x0442
SPI3IMSKH
0x0444
SPI3URDTL
0x0446
SPI3URDTH
0x0448
SPI4CON1L
CKP
MSTEN
0x044A
SPI4CON1H
SPIEN
FRMEN
AUDEN
FRMSYNC
SPISGNEXT
SPISIDL
FRMPOL
IGNROV
0x044C
SPI4CON2L
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
0x044E
...
0x044F
Reserved
0x0450
SPI4STATL
SRMT
SPIROV
SPIRBE
0x0452
SPI4STATH
0x0454
SPI4BUFL
0x0456
SPI4BUFH
0x0458
SPI4BRGL
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
4
3
2
FRMERREN
SPITBEN
BUSYEN
1
0
SPITBFEN
SPIRBFEN
SPITUREN
TXMSK[5:0]
RXMSK[5:0]
CKP
URDATA[7:0]
URDATA[15:8]
URDATA[23:16]
URDATA[31:24]
DISSDI
DISSCK
MCLKEN
SPIFE
ENHBUF
DISSDO
MODE[1:0]
SMP
CKE
MSSEN
FRMSYPW
FRMCNT[2:0]
IGNTUR
AUDMONO
URDTEN
AUDMOD[1:0]
WLENGTH[4:0]
SPITBE
SPIBUSY
TXELM[5:0]
RXELM[5:0]
DATA[7:0]
DATA[15:8]
DATA[23:16]
DATA[31:24]
BRG[7:0]
BRG[12:8]
SPITBF
FRMERR
SPIROVEN
SPIRBEN
SPIRBF
SPITUR
SPITBEN
SPITBFEN
SPIRBFEN
BUSYEN
SPITUREN
TXMSK[5:0]
RXMSK[5:0]
URDATA[7:0]
URDATA[15:8]
URDATA[23:16]
URDATA[31:24]
DISSDI
DISSCK
MCLKEN
SPIFE
ENHBUF
DISSDO
MODE[1:0]
SMP
CKE
MSSEN
FRMSYPW
FRMCNT[2:0]
IGNTUR
AUDMONO
URDTEN
AUDMOD[1:0]
WLENGTH[4:0]
FRMERREN
TXWIEN
RXWIEN
SSEN
© 2019-2020 Microchip Technology Inc.
SPITBE
SPIBUSY
TXELM[5:0]
RXELM[5:0]
DATA[7:0]
DATA[15:8]
DATA[23:16]
DATA[31:24]
BRG[7:0]
BRG[12:8]
FRMERR
Datasheet
SPITBF
SPIRBF
SPITUR
DS30010203C-page 618
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
...........continued
Offset
Name
0x045A
...
0x045B
Reserved
0x045C
SPI4IMSKL
0x045E
SPI4IMSKH
0x0460
SPI4URDTL
0x0462
SPI4URDTH
Bit Pos.
7
6
5
4
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
SRMTEN
SPIROVEN
SPIRBEN
SPITBEN
BUSYEN
TXMSK[5:0]
RXMSK[5:0]
URDATA[7:0]
URDATA[15:8]
URDATA[23:16]
URDATA[31:24]
FRMERREN
TXWIEN
RXWIEN
© 2019-2020 Microchip Technology Inc.
3
Datasheet
2
1
0
SPITBFEN
SPIRBFEN
SPITUREN
DS30010203C-page 619
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.1
SPI1 Control Register 1 Low
Name:
Offset:
SPI1CON1L
0x3F4
Note:
Bit
Access
Reset
Bit
Access
Reset
1.
When AUDEN = 1, this module functions as if CKE = 0, regardless of its actual value.
2.
When FRMEN = 1, SSEN is not used.
3.
MCLKEN can only be written when the SPIEN bit = 0.
4.
This channel is not meaningful for DSP/PCM mode as LRC follows the FRMSYPW bit.
15
SPIEN
R/W
0
14
7
SSEN
R/W
0
6
CKP
R/W
0
13
SPISIDL
R/W
0
12
DISSDO
R/W
0
11
10
R/W
0
5
MSTEN
R/W
0
4
DISSDI
R/W
0
3
DISSCK
R/W
0
R/W
0
9
SMP
R/W
0
8
CKE
R/W
0
2
MCLKEN
R/W
0
1
SPIFE
R/W
0
0
ENHBUF
R/W
0
MODE[1:0]
Bit 15 – SPIEN SPI On bit
Value
Description
1
Enables module
0
Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR
modifications
Bit 13 – SPISIDL SPI Stop in Idle Mode bit
Value
Description
1
Halts in CPU Idle mode
0
Continues to operate in CPU Idle mode
Bit 12 – DISSDO Disable SDO Output Port bit
Value
Description
1
SDO pin is not used by the module; pin is controlled by the port function
0
SDO pin is controlled by the module
Bits 11:10 – MODE[1:0] Serial Word Length bits(1,4)
AUDEN = 0:
MODE32
1
0
0
AUDEN = 1:
MODE32
1
1
0
0
MODE16
x
1
0
COMMUNICATION
32-Bit
16-Bit
8-Bit
FIFO DEPTH
8
16
32
MODE16
1
0
1
0
COMMUNICATION
24-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
32-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
16-Bit Data, 16-Bit FIFO, 32-Bit Channel/64-Bit Frame
16-Bit Data, 16-Bit FIFO, 16-Bit Channel/32-Bit Frame
Bit 9 – SMP SPI Data Input Sample Phase bit
Slave Mode:
Input data are always sampled at the middle of data output time, regardless of the SMP setting.
Master Mode:
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 620
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Value
1
0
Description
Input data are sampled at the end of data output time
Input data are sampled at the middle of data output time
Bit 8 – CKE SPI Clock Edge Select bit(1)
Value
Description
1
Transmit happens on transition from active clock state to Idle clock state
0
Transmit happens on transition from Idle clock state to active clock state
Bit 7 – SSEN Slave Select Enable bit (Slave mode)(2)
Value
Description
1
SS pin is used by the macro in Slave mode; SS pin is used as the Slave select input
0
SS pin is not used by the macro (SS pin will be controlled by the port I/O)
Bit 6 – CKP SPI Clock Polarity Select bit
Value
Description
1
Idle state for clock is a high level; active state is a low level
0
Idle state for clock is a low level; active state is a high level
Bit 5 – MSTEN Master Mode Enable bit
Value
Description
1
Master mode
0
Slave mode
Bit 4 – DISSDI Disable SDI Input Port bit
Value
Description
1
SDI pin is not used by the module; pin is controlled by the port function
0
SDI pin is controlled by the module
Bit 3 – DISSCK Disable SCK Output Port bit
Value
Description
1
SCK pin is not used by the module; pin is controlled by the port function
0
SCK pin is controlled by the module
Bit 2 – MCLKEN Master Clock Enable bit(3)
Value
Description
1
Reference Clock Output (REFO) is used by the BRG
0
Peripheral clock is used by the BRG
Bit 1 – SPIFE Frame Sync Pulse Edge Select bit
Value
Description
1
Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock
0
Frame Sync pulse (Idle-to-active edge) precedes the first bit clock
Bit 0 – ENHBUF Enhanced Buffer Mode Enable bit
Value
Description
1
Enhanced Buffer mode is enabled
0
Enhanced Buffer mode is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 621
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.2
SPI1 Control Register 1 High
Name:
Offset:
SPI1CON1H
0x3F6
Note:
Bit
Access
Reset
Bit
Access
Reset
1.
AUDEN can only be written when the SPIEN bit = 0.
2.
AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN = 1.
3.
URDTEN is only valid when IGNTUR = 1.
4.
AUDMOD[1:0] bits can only be written when the SPIEN bit = 0 and are only valid when AUDEN = 1. When
NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.
15
AUDEN
R/W
0
14
SPISGNEXT
R/W
0
13
IGNROV
R/W
0
12
IGNTUR
R/W
0
11
AUDMONO
R/W
0
10
URDTEN
R/W
0
7
FRMEN
R/W
0
6
FRMSYNC
R/W
0
5
FRMPOL
R/W
0
4
MSSEN
R/W
0
3
FRMSYPW
R/W
0
2
R/W
0
9
8
AUDMOD[1:0]
R/W
R/W
0
0
1
FRMCNT[2:0]
R/W
0
0
R/W
0
Bit 15 – AUDEN Audio Codec Support Enable bit(1)
Value
Description
1
Audio protocol is enabled; MSTEN controls the direction of both the SCK and frame (a.k.a. LRC), and
this module functions as if FRMEN = 1, FRMSYNC = MSTEN, FRMCNT[2:0] = 001 and SMP = 0,
regardless of their actual values
0
Audio protocol is disabled
Bit 14 – SPISGNEXT SPI Sign-Extend RX FIFO Read Data Enable bit
Value
Description
1
Data from RX FIFO are sign-extended
0
Data from RX FIFO are not sign-extended
Bit 13 – IGNROV Ignore Receive Overflow bit
Value
Description
1
A Receive Overflow (ROV) is NOT a critical error; during ROV, data in the FIFO are not overwritten by
the receive data
0
A ROV is a critical error that stops SPI operation
Bit 12 – IGNTUR Ignore Transmit Underrun bit
Value
Description
1
A Transmit Underrun (TUR) is NOT a critical error and data indicated by URDTEN are transmitted until
the SPI1TXB is not empty
0
A TUR is a critical error that stops SPI operation
Bit 11 – AUDMONO Audio Data Format Transmit bit(2)
Value
Description
1
Audio data are mono (i.e., each data word is transmitted on both left and right channels)
0
Audio data are stereo
Bit 10 – URDTEN Transmit Underrun Data Enable bit(3)
Value
Description
1
Transmits data out of SPI1URDTL/H register during Transmit Underrun conditions
0
Transmits the last received data during Transmit Underrun conditions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 622
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Bits 9:8 – AUDMOD[1:0] Audio Protocol Mode Selection bits(4)
Value
Description
11
PCM/DSP mode
10
Right Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
01
Left Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
01
I2S mode: This module functions as if SPIFE = 0, regardless of its actual value
Bit 7 – FRMEN Framed SPI Support bit
Value
Description
1
Framed SPI support is enabled (SS pin is used as the FSYNC input/output)
0
Framed SPI support is disabled
Bit 6 – FRMSYNC Frame Sync Pulse Direction Control bit
Value
Description
1
Frame Sync pulse input (Slave)
0
Frame Sync pulse output (Master)
Bit 5 – FRMPOL Frame Sync/Slave Select Polarity bit
Value
Description
1
Frame Sync pulse/Slave select is active-high
0
Frame Sync pulse/Slave select is active-low
Bit 4 – MSSEN Master Mode Slave Select Enable bit
Value
Description
1
SPI Slave select support is enabled with polarity determined by FRMPOL (SS pin is automatically
driven during transmission in Master mode)
0
SPI Slave select support is disabled (SS pin will be controlled by port I/O)
Bit 3 – FRMSYPW Frame Sync Pulse-Width bit
Value
Description
1
Frame Sync pulse is one serial word length wide (as defined by MODE[32,16]/WLENGTH[4:0] bits)
0
Frame Sync pulse is one clock (SCK) wide
Bits 2:0 – FRMCNT[2:0] Frame Sync Pulse Counter bits
Controls the number of serial words transmitted per Sync pulse.
Value
Description
111
Reserved
110
Reserved
101
Generates a Frame Sync pulse on every 32 serial words
100
Generates a Frame Sync pulse on every 16 serial words
011
Generates a Frame Sync pulse on every 8 serial words
010
Generates a Frame Sync pulse on every 4 serial words
001
Generates a Frame Sync pulse on every 2 serial words (value used by audio protocols)
000
Generates a Frame Sync pulse on each serial word
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 623
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.3
SPI1 Control Register 2 Low
Name:
Offset:
SPI1CON2L
0x3F8
Note:
Bit
1.
These bits are effective when AUDEN = 0 only.
2.
Varying the length by changing these bits does not affect the depth of the TX/RX FIFO.
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
R/W
0
R/W
0
2
WLENGTH[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 4:0 – WLENGTH[4:0] Variable Word Length bits(1,2)
Value
Description
11111
32-bit data
11110
31-bit data
11101
30-bit data
11100
29-bit data
11011
28-bit data
11010
27-bit data
11001
26-bit data
11000
25-bit data
10111
24-bit data
10110
23-bit data
10101
22-bit data
10100
21-bit data
10011
20-bit data
10010
19-bit data
10001
18-bit data
10000
17-bit data
01111
16-bit data
01110
15-bit data
01101
14-bit data
01100
13-bit data
01011
12-bit data
01010
11-bit data
01001
10-bit data
01000
9-bit data
00111
8-bit data
00110
7-bit data
00101
6-bit data
00100
5-bit data
00011
4-bit data
00010
3-bit data
00001
2-bit data
00000
See MODE[32,16] bits in SPI1CON1L[11:10]
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 624
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.4
SPI1 Status Register Low
Name:
Offset:
SPI1STATL
0x3FC
Note:
1.
SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the Transmit
Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software.
Legend: C = Clearable bit; HS = Hardware Settable bit; HSC = Hardware Settable/Clearable bit
Bit
15
14
13
12
FRMERR
HS/R/C
0
11
SPIBUSY
HSC
0
10
9
8
SPITUR
HS/R/C
0
7
SRMT
HSC
0
6
SPIROV
HSC
0
5
SPIRBE
HSC
0
4
3
SPITBE
HSC
0
2
1
SPITBF
HSC
0
0
SPIRBF
HSC
0
Access
Reset
Bit
Access
Reset
Bit 12 – FRMERR SPI Frame Error Status bit
Value
Description
1
Frame error is detected
0
No frame error is detected
Bit 11 – SPIBUSY SPI Activity Status bit
Value
Description
1
Module is currently busy with some transactions
0
No ongoing transactions (at time of read)
Bit 8 – SPITUR SPI Transmit Underrun Status bit(1)
Value
Description
1
Transmit buffer has encountered a Transmit Underrun condition
0
Transmit buffer does not have a Transmit Underrun condition
Bit 7 – SRMT Shift Register Empty Status bit
Value
Description
1
No current or pending transactions (i.e., neither SPI1TXB or SPI1TXSR contains data to transmit)
0
Current or pending transactions
Bit 6 – SPIROV SPI Receive Overflow Status bit
Value
Description
1
A new byte/half-word/word has been completely received when the SPI1RXB is full
0
No overflow
Bit 5 – SPIRBE SPI RX Buffer Empty Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI1BUF is read from, reading SPI1RXB. Automatically cleared in hardware
when SPI transfers data from SPI1RXSR to SPI1RXB.
Enhanced Buffer Mode:
Indicates RXELM[5:0] = 000000.
Value
Description
1
RX buffer is empty
0
RX buffer is not empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 625
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Bit 3 – SPITBE SPI Transmit Buffer Empty Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI1 transfers data from SPI1TXB to SPI1TXSR. Automatically cleared in
hardware when SPI1BUF is written, loading SPI1TXB.
Enhanced Buffer Mode:
Indicates TXELM[5:0] = 000000.
Value
Description
1
SPI1TXB is empty
0
SPI1TXB is not empty
Bit 1 – SPITBF SPI Transmit Buffer Full Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI1BUF is written, loading SPI1TXB. Automatically cleared in hardware when
SPI transfers data from SPI1TXB to SPI1TXSR.
Enhanced Buffer Mode:
Indicates TXELM[5:0] = 111111.
Value
Description
1
SPI1TXB is full
0
SPI1TXB not full
Bit 0 – SPIRBF SPI Receive Buffer Full Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI transfers data from SPI1RXSR to SPI1RXB. Automatically cleared in
hardware when SPI1BUF is read from, reading SPI1RXB.
Enhanced Buffer Mode:
Indicates RXELM[5:0] = 111111.
Value
Description
1
SDI pin is not used by the module; pin is controlled by the port function
0
SDI pin is controlled by the module
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 626
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.5
SPI1 Status Register High
Name:
Offset:
SPI1STATH
0x3FE
Legend: C = Clearable bit; HSC = Hardware Settable/Clearable bit
Bit
15
14
Access
Reset
Bit
Access
Reset
7
13
12
HSC/R/C
0
HSC/R/C
0
5
4
HSC/R/C
0
HSC/R/C
0
6
11
10
RXELM[5:0]
HSC/R/C
HSC/R/C
0
0
2
TXELM[5:0]
HSC/R/C
HSC/R/C
0
0
9
8
HSC/R/C
0
HSC/R/C
0
1
0
HSC/R/C
0
HSC/R/C
0
3
Bits 13:8 – RXELM[5:0] Receive Buffer Element Count bits (valid in Enhanced Buffer mode)
Bits 5:0 – TXELM[5:0] Transmit Buffer Element Count bits (valid in Enhanced Buffer mode)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 627
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.6
SPI1 Buffer Register Low
Name:
Offset:
Bit
15
SPI1BUFL
0x400
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – DATA[15:0] SPI FIFO Data bits
When the MODE[32,16] or WLENGTH[4:0] bits select 16 to 9-bit data, the SPI only uses DATA[15:0].
When the MODE[32,16] or WLENGTH[4:0] bits select 8 to 2-bit data, the SPI only uses DATA[7:0].
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 628
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.7
SPI1 Buffer Register High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI1BUFH
0x402
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
DATA[31:24]
R/W
R/W
0
0
4
3
DATA[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – DATA[31:24] SPI FIFO Data bits
Bits 7:0 – DATA[23:16] SPI FIFO Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 629
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.8
SPI1 Baud Rate Generator Register Low
Name:
Offset:
SPI1BRGL
0x404
Note:
1. Changing the BRG value when SPIEN = 1 causes undefined behavior.
Bit
15
14
13
Access
Reset
Bit
7
6
5
12
11
9
8
R/W
0
10
BRG[12:8]
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
4
BRG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 12:0 – BRG[12:0] SPI Baud Rate Generator Divisor bits(1)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 630
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.9
SPI1 Interrupt Mask Register Low
Name:
Offset:
SPI1IMSKL
0x408
Legend: C = Clearable bit
Bit
15
14
13
12
FRMERREN
R/W
0
11
BUSYEN
R/W
0
10
9
8
SPITUREN
R/C
0
7
SRMTEN
R/W
0
6
SPIROVEN
R/W
0
5
SPIRBEN
R/W
0
4
3
SPITBEN
R/W
0
2
1
SPITBFEN
R/W
0
0
SPIRBFEN
R/W
0
Access
Reset
Bit
Access
Reset
Bit 12 – FRMERREN Enable Interrupt Events via FRMERR bit
Value
Description
1
Frame error generates an interrupt event
0
Frame error does not generate an interrupt event
Bit 11 – BUSYEN Enable Interrupt Events via SPIBUSY bit
Value
Description
1
SPIBUSY generates an interrupt event
0
SPIBUSY does not generate an interrupt event
Bit 8 – SPITUREN Enable Interrupt Events via SPITUR bit
Value
Description
1
Transmit Underrun (TUR) generates an interrupt event
0
Transmit Underrun does not generate an interrupt event
Bit 7 – SRMTEN Enable Interrupt Events via SRMT bit
Value
Description
1
Shift Register Empty (SRMT) generates interrupt events
0
Shift Register Empty does not generate interrupt events
Bit 6 – SPIROVEN Enable Interrupt Events via SPIROV bit
Value
Description
1
SPI Receive Overflow generates an interrupt event
0
SPI Receive Overflow does not generate an interrupt event
Bit 5 – SPIRBEN Enable Interrupt Events via SPIRBE bit
Value
Description
1
SPI RX buffer empty generates an interrupt event
0
SPI RX buffer empty does not generate an interrupt event
Bit 3 – SPITBEN Enable Interrupt Events via SPITBE bit
Value
Description
1
SPI transmit buffer empty generates an interrupt event
0
SPI transmit buffer empty does not generate an interrupt event
Bit 1 – SPITBFEN Enable Interrupt Events via SPITBF bit
Value
Description
1
SPI transmit buffer full generates an interrupt event
0
SPI transmit buffer full does not generate an interrupt event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 631
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Bit 0 – SPIRBFEN Enable Interrupt Events via SPIRBF bit
Value
Description
1
SPI receive buffer full generates an interrupt event
0
SPI receive buffer full does not generate an interrupt event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 632
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.10 SPI1 Interrupt Mask Register High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI1IMSKH
0x40A
15
RXWIEN
R/W
0
14
7
TXWIEN
R/W
0
6
13
12
R/W
0
R/W
0
5
4
R/W
0
R/W
0
11
10
RXMSK[5:0]
R/W
R/W
0
0
3
2
TXMSK[5:0]
R/W
R/W
0
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bit 15 – RXWIEN Receive Watermark Interrupt Enable bit
Value
Description
1
Triggers receive buffer element watermark interrupt when RXMSK[5:0] ≤ RXELM[5:0]
0
Disables receive buffer element watermark interrupt
Bits 13:8 – RXMSK[5:0] RX Buffer Mask bits
RX mask bits; used in conjunction with the RXWIEN bit.
Bit 7 – TXWIEN Transmit Watermark Interrupt Enable bit
Value
Description
1
Triggers transmit buffer element watermark interrupt when TXMSK[5:0] = TXELM[5:0]
0
Disables transmit buffer element watermark interrupt
Bits 5:0 – TXMSK[5:0] TX Buffer Mask bits
TX mask bits; used in conjunction with the TXWIEN bit.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 633
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.11 SPI1 Underrun Data Register Low
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI1URDTL
0x40C
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
URDATA[15:8]
R/W
R/W
0
0
4
3
URDATA[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – URDATA[15:0] SPI Underrun Data bits
These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit Underrun
condition occurs.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 634
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.12 SPI1 Underrun Data Register High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI1URDTH
0x40E
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
URDATA[31:24]
R/W
R/W
0
0
4
3
URDATA[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – URDATA[31:24] SPI Underrun Data bits
These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit Underrun
condition occurs.
Bits 7:0 – URDATA[23:16] SPI Underrun Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 635
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.13 SPI2 Control Register 1 Low
Name:
Offset:
SPI2CON1L
0x410
Note:
Bit
Access
Reset
Bit
Access
Reset
1.
When AUDEN = 1, this module functions as if CKE = 0, regardless of its actual value.
2.
When FRMEN = 1, SSEN is not used.
3.
MCLKEN can only be written when the SPIEN bit = 0.
4.
This channel is not meaningful for DSP/PCM mode as LRC follows the FRMSYPW bit.
15
SPIEN
R/W
0
14
7
SSEN
R/W
0
6
CKP
R/W
0
13
SPISIDL
R/W
0
12
DISSDO
R/W
0
11
10
R/W
0
5
MSTEN
R/W
0
4
DISSDI
R/W
0
3
DISSCK
R/W
0
R/W
0
9
SMP
R/W
0
8
CKE
R/W
0
2
MCLKEN
R/W
0
1
SPIFE
R/W
0
0
ENHBUF
R/W
0
MODE[1:0]
Bit 15 – SPIEN SPI On bit
Value
Description
1
Enables module
0
Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR
modifications
Bit 13 – SPISIDL SPI Stop in Idle Mode bit
Value
Description
1
Halts in CPU Idle mode
0
Continues to operate in CPU Idle mode
Bit 12 – DISSDO Disable SDO Output Port bit
Value
Description
1
SDO pin is not used by the module; pin is controlled by the port function
0
SDO pin is controlled by the module
Bits 11:10 – MODE[1:0] Serial Word Length bits(1,4)
AUDEN = 0:
MODE32
1
0
0
AUDEN = 1:
MODE32
1
1
0
0
MODE16
x
1
0
COMMUNICATION
32-Bit
16-Bit
8-Bit
FIFO DEPTH
8
16
32
MODE16
1
0
1
0
COMMUNICATION
24-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
32-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
16-Bit Data, 16-Bit FIFO, 32-Bit Channel/64-Bit Frame
16-Bit Data, 16-Bit FIFO, 16-Bit Channel/32-Bit Frame
Bit 9 – SMP SPI Data Input Sample Phase bit
Slave Mode:
Input data are always sampled at the middle of data output time, regardless of the SMP setting.
Master Mode:
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 636
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Value
1
0
Description
Input data are sampled at the end of data output time
Input data are sampled at the middle of data output time
Bit 8 – CKE SPI Clock Edge Select bit(1)
Value
Description
1
Transmit happens on transition from active clock state to Idle clock state
0
Transmit happens on transition from Idle clock state to active clock state
Bit 7 – SSEN Slave Select Enable bit (Slave mode)(2)
Value
Description
1
SS pin is used by the macro in Slave mode; SS pin is used as the Slave select input
0
SS pin is not used by the macro (SS pin will be controlled by the port I/O)
Bit 6 – CKP SPI Clock Polarity Select bit
Value
Description
1
Idle state for clock is a high level; active state is a low level
0
Idle state for clock is a low level; active state is a high level
Bit 5 – MSTEN Master Mode Enable bit
Value
Description
1
Master mode
0
Slave mode
Bit 4 – DISSDI Disable SDI Input Port bit
Value
Description
1
SDI pin is not used by the module; pin is controlled by the port function
0
SDI pin is controlled by the module
Bit 3 – DISSCK Disable SCK Output Port bit
Value
Description
1
SCK pin is not used by the module; pin is controlled by the port function
0
SCK pin is controlled by the module
Bit 2 – MCLKEN Master Clock Enable bit(3)
Value
Description
1
Reference Clock Output (REFO) is used by the BRG
0
Peripheral clock is used by the BRG
Bit 1 – SPIFE Frame Sync Pulse Edge Select bit
Value
Description
1
Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock
0
Frame Sync pulse (Idle-to-active edge) precedes the first bit clock
Bit 0 – ENHBUF Enhanced Buffer Mode Enable bit
Value
Description
1
Enhanced Buffer mode is enabled
0
Enhanced Buffer mode is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 637
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.14 SPI2 Control Register 1 High
Name:
Offset:
SPI2CON1H
0x412
Note:
Bit
Access
Reset
Bit
Access
Reset
1.
AUDEN can only be written when the SPIEN bit = 0.
2.
AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN = 1.
3.
URDTEN is only valid when IGNTUR = 1.
4.
AUDMOD[1:0] bits can only be written when the SPIEN bit = 0 and are only valid when AUDEN = 1. When
NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.
15
AUDEN
R/W
0
14
SPISGNEXT
R/W
0
13
IGNROV
R/W
0
12
IGNTUR
R/W
0
11
AUDMONO
R/W
0
10
URDTEN
R/W
0
7
FRMEN
R/W
0
6
FRMSYNC
R/W
0
5
FRMPOL
R/W
0
4
MSSEN
R/W
0
3
FRMSYPW
R/W
0
2
R/W
0
9
8
AUDMOD[1:0]
R/W
R/W
0
0
1
FRMCNT[2:0]
R/W
0
0
R/W
0
Bit 15 – AUDEN Audio Codec Support Enable bit(1)
Value
Description
1
Audio protocol is enabled; MSTEN controls the direction of both the SCK and frame (a.k.a. LRC), and
this module functions as if FRMEN = 1, FRMSYNC = MSTEN, FRMCNT[2:0] = 001 and SMP = 0,
regardless of their actual values
0
Audio protocol is disabled
Bit 14 – SPISGNEXT SPI Sign-Extend RX FIFO Read Data Enable bit
Value
Description
1
Data from RX FIFO are sign-extended
0
Data from RX FIFO are not sign-extended
Bit 13 – IGNROV Ignore Receive Overflow bit
Value
Description
1
A Receive Overflow (ROV) is NOT a critical error; during ROV, data in the FIFO are not overwritten by
the receive data
0
A ROV is a critical error that stops SPI operation
Bit 12 – IGNTUR Ignore Transmit Underrun bit
Value
Description
1
A Transmit Underrun (TUR) is NOT a critical error and data indicated by URDTEN are transmitted until
the SPI2TXB is not empty
0
A TUR is a critical error that stops SPI operation
Bit 11 – AUDMONO Audio Data Format Transmit bit(2)
Value
Description
1
Audio data are mono (i.e., each data word is transmitted on both left and right channels)
0
Audio data are stereo
Bit 10 – URDTEN Transmit Underrun Data Enable bit(3)
Value
Description
1
Transmits data out of SPI2URDTL/H register during Transmit Underrun conditions
0
Transmits the last received data during Transmit Underrun conditions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 638
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Bits 9:8 – AUDMOD[1:0] Audio Protocol Mode Selection bits(4)
Value
Description
11
PCM/DSP mode
10
Right Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
01
Left Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
01
I2S mode: This module functions as if SPIFE = 0, regardless of its actual value
Bit 7 – FRMEN Framed SPI Support bit
Value
Description
1
Framed SPI support is enabled (SS pin is used as the FSYNC input/output)
0
Framed SPI support is disabled
Bit 6 – FRMSYNC Frame Sync Pulse Direction Control bit
Value
Description
1
Frame Sync pulse input (Slave)
0
Frame Sync pulse output (Master)
Bit 5 – FRMPOL Frame Sync/Slave Select Polarity bit
Value
Description
1
Frame Sync pulse/Slave select is active-high
0
Frame Sync pulse/Slave select is active-low
Bit 4 – MSSEN Master Mode Slave Select Enable bit
Value
Description
1
SPI Slave select support is enabled with polarity determined by FRMPOL (SS pin is automatically
driven during transmission in Master mode)
0
SPI Slave select support is disabled (SS pin will be controlled by port I/O)
Bit 3 – FRMSYPW Frame Sync Pulse-Width bit
Value
Description
1
Frame Sync pulse is one serial word length wide (as defined by MODE[32,16]/WLENGTH[4:0])
0
Frame Sync pulse is one clock (SCK) wide
Bits 2:0 – FRMCNT[2:0] Frame Sync Pulse Counter bits
Controls the number of serial words transmitted per Sync pulse.
Value
Description
111
Reserved
110
Reserved
101
Generates a Frame Sync pulse on every 32 serial words
100
Generates a Frame Sync pulse on every 16 serial words
011
Generates a Frame Sync pulse on every 8 serial words
010
Generates a Frame Sync pulse on every 4 serial words
001
Generates a Frame Sync pulse on every 2 serial words (value used by audio protocols)
000
Generates a Frame Sync pulse on each serial word
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 639
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.15 SPI2 Control Register 2 Low
Name:
Offset:
SPI2CON2L
0x414
Note:
Bit
1.
These bits are effective when AUDEN = 0 only.
2.
Varying the length by changing these bits does not affect the depth of the TX/RX FIFO.
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
R/W
0
R/W
0
2
WLENGTH[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 4:0 – WLENGTH[4:0] Variable Word Length bits(1,2)
Value
Description
11111
32-bit data
11110
31-bit data
11101
30-bit data
11100
29-bit data
11011
28-bit data
11010
27-bit data
11001
26-bit data
11000
25-bit data
10111
24-bit data
10110
23-bit data
10101
22-bit data
10100
21-bit data
10011
20-bit data
10010
19-bit data
10001
18-bit data
10000
17-bit data
01111
16-bit data
01110
15-bit data
01101
14-bit data
01100
13-bit data
01011
12-bit data
01010
11-bit data
01001
10-bit data
01000
9-bit data
00111
8-bit data
00110
7-bit data
00101
6-bit data
00100
5-bit data
00011
4-bit data
00010
3-bit data
00001
2-bit data
00000
See MODE[32,16] bits in SPI2CON1L[11:10]
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 640
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.16 SPI2 Status Register Low
Name:
Offset:
SPI2STATL
0x418
Note:
1.
SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the Transmit
Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software.
Legend: C = Clearable bit; HS = Hardware Settable bit; HSC = Hardware Settable/Clearable bit
Bit
15
14
13
12
FRMERR
HS/R/C
0
11
SPIBUSY
HSC
0
10
9
8
SPITUR
HS/R/C
0
7
SRMT
HSC
0
6
SPIROV
HSC
0
5
SPIRBE
HSC
0
4
3
SPITBE
HSC
0
2
1
SPITBF
HSC
0
0
SPIRBF
HSC
0
Access
Reset
Bit
Access
Reset
Bit 12 – FRMERR SPI Frame Error Status bit
Value
Description
1
Frame error is detected
0
No frame error is detected
Bit 11 – SPIBUSY SPI Activity Status bit
Value
Description
1
Module is currently busy with some transactions
0
No ongoing transactions (at time of read)
Bit 8 – SPITUR SPI Transmit Underrun Status bit(1)
Value
Description
1
Transmit buffer has encountered a Transmit Underrun condition
0
Transmit buffer does not have a Transmit Underrun condition
Bit 7 – SRMT Shift Register Empty Status bit
Value
Description
1
No current or pending transactions (i.e., neither SPI2TXB or SPI2TXSR contains data to transmit)
0
Current or pending transactions
Bit 6 – SPIROV SPI Receive Overflow Status bit
Value
Description
1
A new byte/half-word/word has been completely received when the SPI2RXB is full
0
No overflow
Bit 5 – SPIRBE SPI RX Buffer Empty Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI2BUF is read from, reading SPI2RXB. Automatically cleared in hardware
when SPI transfers data from SPI2RXSR to SPI2RXB.
Enhanced Buffer Mode:
Indicates RXELM[5:0] = 000000.
Value
Description
1
RX buffer is empty
0
RX buffer is not empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 641
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Bit 3 – SPITBE SPI Transmit Buffer Empty Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI transfers data from SPI2TXB to SPI2TXSR. Automatically cleared in
hardware when SPI2BUF is written, loading SPI2TXB.
Enhanced Buffer Mode:
Indicates TXELM[5:0] = 000000.
Value
Description
1
SPI2TXB is empty
0
SPI2TXB is not empty
Bit 1 – SPITBF SPI Transmit Buffer Full Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI2BUF is written, loading SPI2TXB. Automatically cleared in hardware when
SPI transfers data from SPI2TXB to SPI2TXSR.
Enhanced Buffer Mode:
Indicates TXELM[5:0] = 111111.
Value
Description
1
SPI2TXB is full
0
SPI2TXB not full
Bit 0 – SPIRBF SPI Receive Buffer Full Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI transfers data from SPI2RXSR to SPI2RXB. Automatically cleared in
hardware when SPI2BUF is read from, reading SPI2RXB.
Enhanced Buffer Mode:
Indicates RXELM[5:0] = 111111.
Value
Description
1
SDI pin is not used by the module; pin is controlled by the port function
0
SDI pin is controlled by the module
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 642
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.17 SPI2 Status Register High
Name:
Offset:
SPI2STATH
0x41A
Legend: C = Clearable bit, HSC = Hardware Settable/Clearable bit
Bit
15
14
Access
Reset
Bit
Access
Reset
7
13
12
HSC/R/C
0
HSC/R/C
0
5
4
HSC/R/C
0
HSC/R/C
0
6
11
10
RXELM[5:0]
HSC/R/C
HSC/R/C
0
0
2
TXELM[5:0]
HSC/R/C
HSC/R/C
0
0
9
8
HSC/R/C
0
HSC/R/C
0
1
0
HSC/R/C
0
HSC/R/C
0
3
Bits 13:8 – RXELM[5:0] Receive Buffer Element Count bits (valid in Enhanced Buffer mode)
Bits 5:0 – TXELM[5:0] Transmit Buffer Element Count bits (valid in Enhanced Buffer mode)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 643
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.18 SPI2 Buffer Register Low
Name:
Offset:
Bit
15
SPI2BUFL
0x41C
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – DATA[15:0] SPI FIFO Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 644
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.19 SPI2 Buffer Register High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI2BUFH
0x41E
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
DATA[31:24]
R/W
R/W
0
0
4
3
DATA[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – DATA[31:24] SPI FIFO Data bits
Bits 7:0 – DATA[23:16] SPI FIFO Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 645
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.20 SPI2 Baud Rate Generator Register Low
Name:
Offset:
SPI2BRGL
0x420
Note:
1. Changing the BRG value when SPIEN = 1 causes undefined behavior.
Bit
15
14
13
Access
Reset
Bit
7
6
5
12
11
9
8
R/W
0
10
BRG[12:8]
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
4
BRG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 12:0 – BRG[12:0] SPI Baud Rate Generator Divisor bits(1)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 646
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.21 SPI2 Interrupt Mask Register Low
Name:
Offset:
SPI2IMSKL
0x424
Legend: C = Clearable bit
Bit
15
14
13
12
FRMERREN
R/W
0
11
BUSYEN
R/W
0
10
9
8
SPITUREN
R/C
0
7
SRMTEN
R/W
0
6
SPIROVEN
R/W
0
5
SPIRBEN
R/W
0
4
3
SPITBEN
R/W
0
2
1
SPITBFEN
R/W
0
0
SPIRBFEN
R/W
0
Access
Reset
Bit
Access
Reset
Bit 12 – FRMERREN Enable Interrupt Events via FRMERR bit
Value
Description
1
Frame error generates an interrupt event
0
Frame error does not generate an interrupt event
Bit 11 – BUSYEN Enable Interrupt Events via SPIBUSY bit
Value
Description
1
SPIBUSY generates an interrupt event
0
SPIBUSY does not generate an interrupt event
Bit 8 – SPITUREN Enable Interrupt Events via SPITUR bit
Value
Description
1
Transmit Underrun (TUR) generates an interrupt event
0
Transmit Underrun does not generate an interrupt event
Bit 7 – SRMTEN Enable Interrupt Events via SRMT bit
Value
Description
1
Shift Register Empty (SRMT) generates interrupt events
0
Shift Register Empty does not generate interrupt events
Bit 6 – SPIROVEN Enable Interrupt Events via SPIROV bit
Value
Description
1
SPI receive overflow generates an interrupt event
0
SPI receive overflow does not generate an interrupt event
Bit 5 – SPIRBEN Enable Interrupt Events via SPIRBE bit
Value
Description
1
SPI RX buffer empty generates an interrupt event
0
SPI RX buffer empty does not generate an interrupt event
Bit 3 – SPITBEN Enable Interrupt Events via SPITBE bit
Value
Description
1
SPI transmit buffer empty generates an interrupt event
0
SPI transmit buffer empty does not generate an interrupt event
Bit 1 – SPITBFEN Enable Interrupt Events via SPITBF bit
Value
Description
1
SPI transmit buffer full generates an interrupt event
0
SPI transmit buffer full does not generate an interrupt event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 647
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Bit 0 – SPIRBFEN Enable Interrupt Events via SPIRBF bit
Value
Description
1
SPI receive buffer full generates an interrupt event
0
SPI receive buffer full does not generate an interrupt event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 648
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.22 SPI2 Interrupt Mask Register High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI2IMSKH
0x426
15
RXWIEN
R/W
0
14
7
TXWIEN
R/W
0
6
13
12
R/W
0
R/W
0
5
4
R/W
0
R/W
0
11
10
RXMSK[5:0]
R/W
R/W
0
0
3
2
TXMSK[5:0]
R/W
R/W
0
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bit 15 – RXWIEN Receive Watermark Interrupt Enable bit
Value
Description
1
Triggers receive buffer element watermark interrupt when RXMSK[5:0] ≤ RXELM[5:0]
0
Disables receive buffer element watermark interrupt
Bits 13:8 – RXMSK[5:0] RX Buffer Mask bits
RX mask bits; used in conjunction with the RXWIEN bit.
Bit 7 – TXWIEN Transmit Watermark Interrupt Enable bit
Value
Description
1
Triggers transmit buffer element watermark interrupt when TXMSK[5:0] = TXELM[5:0]
0
Disables transmit buffer element watermark interrupt
Bits 5:0 – TXMSK[5:0] TX Buffer Mask bits
TX mask bits; used in conjunction with the TXWIEN bit.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 649
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.23 SPI2 Underrun Data Register Low
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI2URDTL
0x428
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
URDATA[15:8]
R/W
R/W
0
0
4
3
URDATA[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – URDATA[15:0] SPI Underrun Data bits
These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit Underrun
condition occurs.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 650
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.24 SPI2 Underrun Data Register High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI2URDTH
0x42A
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
URDATA[31:24]
R/W
R/W
0
0
4
3
URDATA[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – URDATA[31:24] SPI Underrun Data bits
These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit Underrun
condition occurs.
Bits 7:0 – URDATA[23:16] SPI Underrun Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 651
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.25 SPI3 Control Register 1 Low
Name:
Offset:
SPI3CON1L
0x42C
Note:
Bit
Access
Reset
Bit
Access
Reset
1.
When AUDEN = 1, this module functions as if CKE = 0, regardless of its actual value.
2.
When FRMEN = 1, SSEN is not used.
3.
MCLKEN can only be written when the SPIEN bit = 0.
4.
This channel is not meaningful for DSP/PCM mode as LRC follows the FRMSYPW bit.
15
SPIEN
R/W
0
14
7
SSEN
R/W
0
6
CKP
R/W
0
13
SPISIDL
R/W
0
12
DISSDO
R/W
0
11
10
R/W
0
5
MSTEN
R/W
0
4
DISSDI
R/W
0
3
DISSCK
R/W
0
R/W
0
9
SMP
R/W
0
8
CKE
R/W
0
2
MCLKEN
R/W
0
1
SPIFE
R/W
0
0
ENHBUF
R/W
0
MODE[1:0]
Bit 15 – SPIEN SPI On bit
Value
Description
1
Enables module
0
Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR
modifications
Bit 13 – SPISIDL SPI Stop in Idle Mode bit
Value
Description
1
Halts in CPU Idle mode
0
Continues to operate in CPU Idle mode
Bit 12 – DISSDO Disable SDO Output Port bit
Value
Description
1
SDO pin is not used by the module; pin is controlled by the port function
0
SDO pin is controlled by the module
Bits 11:10 – MODE[1:0] Serial Word Length bits(1,4)
AUDEN = 0:
MODE32
1
0
0
AUDEN = 1:
MODE32
1
1
0
0
MODE16
x
1
0
COMMUNICATION
32-Bit
16-Bit
8-Bit
FIFO DEPTH
8
16
32
MODE16
1
0
1
0
COMMUNICATION
24-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
32-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
16-Bit Data, 16-Bit FIFO, 32-Bit Channel/64-Bit Frame
16-Bit Data, 16-Bit FIFO, 16-Bit Channel/32-Bit Frame
Bit 9 – SMP SPI Data Input Sample Phase bit
Slave Mode:
Input data are always sampled at the middle of data output time, regardless of the SMP setting.
Master Mode:
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 652
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Value
1
0
Description
Input data are sampled at the end of data output time
Input data are sampled at the middle of data output time
Bit 8 – CKE SPI Clock Edge Select bit(1)
Value
Description
1
Transmit happens on transition from active clock state to Idle clock state
0
Transmit happens on transition from Idle clock state to active clock state
Bit 7 – SSEN Slave Select Enable bit (Slave mode)(2)
Value
Description
1
SS pin is used by the macro in Slave mode; SS pin is used as the Slave select input
0
SS pin is not used by the macro (SS pin will be controlled by the port I/O)
Bit 6 – CKP SPI Clock Polarity Select bit
Value
Description
1
Idle state for clock is a high level; active state is a low level
0
Idle state for clock is a low level; active state is a high level
Bit 5 – MSTEN Master Mode Enable bit
Value
Description
1
Master mode
0
Slave mode
Bit 4 – DISSDI Disable SDI Input Port bit
Value
Description
1
SDI pin is not used by the module; pin is controlled by the port function
0
SDI pin is controlled by the module
Bit 3 – DISSCK Disable SCK Output Port bit
Value
Description
1
SCK pin is not used by the module; pin is controlled by the port function
0
SCK pin is controlled by the module
Bit 2 – MCLKEN Master Clock Enable bit(3)
Value
Description
1
Reference Clock Output (REFO) is used by the BRG
0
Peripheral clock is used by the BRG
Bit 1 – SPIFE Frame Sync Pulse Edge Select bit
Value
Description
1
Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock
0
Frame Sync pulse (Idle-to-active edge) precedes the first bit clock
Bit 0 – ENHBUF Enhanced Buffer Mode Enable bit
Value
Description
1
Enhanced Buffer mode is enabled
0
Enhanced Buffer mode is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 653
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.26 SPI3 Control Register 1 High
Name:
Offset:
SPI3CON1H
0x42E
Note:
Bit
Access
Reset
Bit
Access
Reset
1.
AUDEN can only be written when the SPIEN bit = 0.
2.
AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN = 1.
3.
URDTEN is only valid when IGNTUR = 1.
4.
AUDMOD[1:0] bits can only be written when the SPIEN bit = 0 and are only valid when AUDEN = 1. When
NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.
15
AUDEN
R/W
0
14
SPISGNEXT
R/W
0
13
IGNROV
R/W
0
12
IGNTUR
R/W
0
11
AUDMONO
R/W
0
10
URDTEN
R/W
0
7
FRMEN
R/W
0
6
FRMSYNC
R/W
0
5
FRMPOL
R/W
0
4
MSSEN
R/W
0
3
FRMSYPW
R/W
0
2
R/W
0
9
8
AUDMOD[1:0]
R/W
R/W
0
0
1
FRMCNT[2:0]
R/W
0
0
R/W
0
Bit 15 – AUDEN Audio Codec Support Enable bit(1)
Value
Description
1
Audio protocol is enabled; MSTEN controls the direction of both the SCK and frame (a.k.a. LRC), and
this module functions as if FRMEN = 1, FRMSYNC = MSTEN, FRMCNT[2:0] = 001 and SMP = 0,
regardless of their actual values
0
Audio protocol is disabled
Bit 14 – SPISGNEXT SPI Sign-Extend RX FIFO Read Data Enable bit
Value
Description
1
Data from RX FIFO are sign-extended
0
Data from RX FIFO are not sign-extended
Bit 13 – IGNROV Ignore Receive Overflow bit
Value
Description
1
A Receive Overflow (ROV) is NOT a critical error; during ROV, data in the FIFO are not overwritten by
the receive data
0
A ROV is a critical error that stops SPI operation
Bit 12 – IGNTUR Ignore Transmit Underrun bit
Value
Description
1
A Transmit Underrun (TUR) is NOT a critical error and data indicated by URDTEN are transmitted until
the SPI3TXB is not empty
0
A TUR is a critical error that stops SPI operation
Bit 11 – AUDMONO Audio Data Format Transmit bit(2)
Value
Description
1
Audio data are mono (i.e., each data word is transmitted on both left and right channels)
0
Audio data are stereo
Bit 10 – URDTEN Transmit Underrun Data Enable bit(3)
Value
Description
1
Transmits data out of SPI3URDTL/H register during Transmit Underrun conditions
0
Transmits the last received data during Transmit Underrun conditions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 654
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Bits 9:8 – AUDMOD[1:0] Audio Protocol Mode Selection bits(4)
Value
Description
11
PCM/DSP mode
10
Right Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
01
Left Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
01
I2S mode: This module functions as if SPIFE = 0, regardless of its actual value
Bit 7 – FRMEN Framed SPI Support bit
Value
Description
1
Framed SPI support is enabled (SS pin is used as the FSYNC input/output)
0
Framed SPI support is disabled
Bit 6 – FRMSYNC Frame Sync Pulse Direction Control bit
Value
Description
1
Frame Sync pulse input (Slave)
0
Frame Sync pulse output (Master)
Bit 5 – FRMPOL Frame Sync/Slave Select Polarity bit
Value
Description
1
Frame Sync pulse/Slave select is active-high
0
Frame Sync pulse/Slave select is active-low
Bit 4 – MSSEN Master Mode Slave Select Enable bit
Value
Description
1
SPI Slave select support is enabled with polarity determined by FRMPOL (SS pin is automatically
driven during transmission in Master mode)
0
SPI Slave select support is disabled (SS pin will be controlled by port I/O)
Bit 3 – FRMSYPW Frame Sync Pulse-Width bit
Value
Description
1
Frame Sync pulse is one serial word length wide (as defined by MODE[32,16]/WLENGTH[4:0])
0
Frame Sync pulse is one clock (SCK) wide
Bits 2:0 – FRMCNT[2:0] Frame Sync Pulse Counter bits
Controls the number of serial words transmitted per Sync pulse.
Value
Description
111
Reserved
110
Reserved
101
Generates a Frame Sync pulse on every 32 serial words
100
Generates a Frame Sync pulse on every 16 serial words
011
Generates a Frame Sync pulse on every 8 serial words
010
Generates a Frame Sync pulse on every 4 serial words
001
Generates a Frame Sync pulse on every 2 serial words (value used by audio protocols)
000
Generates a Frame Sync pulse on each serial word
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 655
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.27 SPI3 Control Register 2 Low
Name:
Offset:
SPI3CON2L
0x430
Note:
Bit
1.
These bits are effective when AUDEN = 0 only.
2.
Varying the length by changing these bits does not affect the depth of the TX/RX FIFO.
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
R/W
0
R/W
0
2
WLENGTH[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 4:0 – WLENGTH[4:0] Variable Word Length bits(1,2)
Value
Description
11111
32-bit data
11110
31-bit data
11101
30-bit data
11100
29-bit data
11011
28-bit data
11010
27-bit data
11001
26-bit data
11000
25-bit data
10111
24-bit data
10110
23-bit data
10101
22-bit data
10100
21-bit data
10011
20-bit data
10010
19-bit data
10001
18-bit data
10000
17-bit data
01111
16-bit data
01110
15-bit data
01101
14-bit data
01100
13-bit data
01011
12-bit data
01010
11-bit data
01001
10-bit data
01000
9-bit data
00111
8-bit data
00110
7-bit data
00101
6-bit data
00100
5-bit data
00011
4-bit data
00010
3-bit data
00001
2-bit data
00000
See MODE[32,16] bits in SPI3CON1L[11:10]
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 656
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.28 SPI3 Status Register Low
Name:
Offset:
SPI3STATL
0x434
Note:
1.
SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the Transmit
Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software.
Legend: C = Clearable bit; HS = Hardware Settable bit; HSC = Hardware Settable/Clearable bit
Bit
15
14
13
12
FRMERR
HS/R/C
0
11
SPIBUSY
HSC
0
10
9
8
SPITUR
HS/R/C
0
7
SRMT
HSC
0
6
SPIROV
HSC
0
5
SPIRBE
HSC
0
4
3
SPITBE
HSC
0
2
1
SPITBF
HSC
0
0
SPIRBF
HSC
0
Access
Reset
Bit
Access
Reset
Bit 12 – FRMERR SPI Frame Error Status bit
Value
Description
1
Frame error is detected
0
No frame error is detected
Bit 11 – SPIBUSY SPI Activity Status bit
Value
Description
1
Module is currently busy with some transactions
0
No ongoing transactions (at time of read)
Bit 8 – SPITUR SPI Transmit Underrun Status bit(1)
Value
Description
1
Transmit buffer has encountered a Transmit Underrun condition
0
Transmit buffer does not have a Transmit Underrun condition
Bit 7 – SRMT Shift Register Empty Status bit
Value
Description
1
No current or pending transactions (i.e., neither SPI3TXB or SPI3TXSR contains data to transmit)
0
Current or pending transactions
Bit 6 – SPIROV SPI Receive Overflow Status bit
Value
Description
1
A new byte/half-word/word has been completely received when SPI3RXB is full
0
No overflow
Bit 5 – SPIRBE SPI RX Buffer Empty Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI3BUF is read from, reading SPI3RXB. Automatically cleared in hardware
when SPI transfers data from SPI3RXSR to SPI3RXB.
Enhanced Buffer Mode:
Indicates RXELM[5:0] = 000000.
Value
Description
1
RX buffer is empty
0
RX buffer is not empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 657
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Bit 3 – SPITBE SPI Transmit Buffer Empty Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI3 transfers data from SPI3TXB to SPI3TXSR. Automatically cleared in
hardware when SPI3BUF is written, loading SPI3TXB.
Enhanced Buffer Mode:
Indicates TXELM[5:0] = 000000.
Value
Description
1
SPI3TXB is empty
0
SPI3TXB is not empty
Bit 1 – SPITBF SPI Transmit Buffer Full Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI3BUF is written, loading SPI3TXB. Automatically cleared in hardware when
SPI transfers data from SPI3TXB to SPI3TXSR.
Enhanced Buffer Mode:
Indicates TXELM[5:0] = 111111.
Value
Description
1
SPI3TXB is full
0
SPI3TXB not full
Bit 0 – SPIRBF SPI Receive Buffer Full Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI transfers data from SPI3RXSR to SPI3RXB. Automatically cleared in
hardware when SPI3BUF is read from, reading SPI3RXB.
Enhanced Buffer Mode:
Indicates RXELM[5:0] = 111111.
Value
Description
1
SDI pin is not used by the module; pin is controlled by the port function
0
SDI pin is controlled by the module
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 658
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.29 SPI3 Status Register High
Name:
Offset:
SPI3STATH
0x436
Legend: C = Clearable bit; HSC = Hardware Settable/Clearable bit
Bit
15
14
Access
Reset
Bit
Access
Reset
7
13
12
HSC/R/C
0
HSC/R/C
0
5
4
HSC/R/C
0
HSC/R/C
0
6
11
10
RXELM[5:0]
HSC/R/C
HSC/R/C
0
0
2
TXELM[5:0]
HSC/R/C
HSC/R/C
0
0
9
8
HSC/R/C
0
HSC/R/C
0
1
0
HSC/R/C
0
HSC/R/C
0
3
Bits 13:8 – RXELM[5:0] Receive Buffer Element Count bits (valid in Enhanced Buffer mode)
Bits 5:0 – TXELM[5:0] Transmit Buffer Element Count bits (valid in Enhanced Buffer mode)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 659
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.30 SPI3 Buffer Register Low
Name:
Offset:
Bit
15
SPI3BUFL
0x438
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – DATA[15:0] SPI FIFO Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 660
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.31 SPI3 Buffer Register High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI3BUFH
0x43A
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
DATA[31:24]
R/W
R/W
0
0
4
3
DATA[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – DATA[31:24] SPI FIFO Data bits
Bits 7:0 – DATA[23:16] SPI FIFO Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 661
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.32 SPI3 Baud Rate Generator Register Low
Name:
Offset:
SPI3BRGL
0x43C
Note:
1. Changing the BRG value when SPIEN = 1 causes undefined behavior.
Bit
15
14
13
Access
Reset
Bit
7
6
5
12
11
9
8
R/W
0
10
BRG[12:8]
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
4
BRG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 12:0 – BRG[12:0] SPI Baud Rate Generator Divisor bits(1)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 662
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.33 SPI3 Interrupt Mask Register Low
Name:
Offset:
SPI3IMSKL
0x440
Legend: C = Clearable bit
Bit
15
14
13
12
FRMERREN
R/W
0
11
BUSYEN
R/W
0
10
9
8
SPITUREN
R/C
0
7
SRMTEN
R/W
0
6
SPIROVEN
R/W
0
5
SPIRBEN
R/W
0
4
3
SPITBEN
R/W
0
2
1
SPITBFEN
R/W
0
0
SPIRBFEN
R/W
0
Access
Reset
Bit
Access
Reset
Bit 12 – FRMERREN Enable Interrupt Events via FRMERR bit
Value
Description
1
Frame error generates an interrupt event
0
Frame error does not generate an interrupt event
Bit 11 – BUSYEN Enable Interrupt Events via SPIBUSY bit
Value
Description
1
SPIBUSY generates an interrupt event
0
SPIBUSY does not generate an interrupt event
Bit 8 – SPITUREN Enable Interrupt Events via SPITUR bit
Value
Description
1
Transmit Underrun (TUR) generates an interrupt event
0
Transmit Underrun does not generate an interrupt event
Bit 7 – SRMTEN Enable Interrupt Events via SRMT bit
Value
Description
1
Shift Register Empty (SRMT) generates interrupt events
0
Shift Register Empty does not generate interrupt events
Bit 6 – SPIROVEN Enable Interrupt Events via SPIROV bit
Value
Description
1
SPI receive overflow generates an interrupt event
0
SPI receive overflow does not generate an interrupt event
Bit 5 – SPIRBEN Enable Interrupt Events via SPIRBE bit
Value
Description
1
SPI RX buffer empty generates an interrupt event
0
SPI RX buffer empty does not generate an interrupt event
Bit 3 – SPITBEN Enable Interrupt Events via SPITBE bit
Value
Description
1
SPI transmit buffer empty generates an interrupt event
0
SPI transmit buffer empty does not generate an interrupt event
Bit 1 – SPITBFEN Enable Interrupt Events via SPITBF bit
Value
Description
1
SPI transmit buffer full generates an interrupt event
0
SPI transmit buffer full does not generate an interrupt event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 663
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Bit 0 – SPIRBFEN Enable Interrupt Events via SPIRBF bit
Value
Description
1
SPI receive buffer full generates an interrupt event
0
SPI receive buffer full does not generate an interrupt event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 664
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.34 SPI3 Interrupt Mask Register High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI3IMSKH
0x442
15
RXWIEN
R/W
0
14
7
TXWIEN
R/W
0
6
13
12
R/W
0
R/W
0
5
4
R/W
0
R/W
0
11
10
RXMSK[5:0]
R/W
R/W
0
0
3
2
TXMSK[5:0]
R/W
R/W
0
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bit 15 – RXWIEN Receive Watermark Interrupt Enable bit
Value
Description
1
Triggers receive buffer element watermark interrupt when RXMSK[5:0] ≤ RXELM[5:0]
0
Disables receive buffer element watermark interrupt
Bits 13:8 – RXMSK[5:0] RX Buffer Mask bits
RX mask bits; used in conjunction with the RXWIEN bit.
Bit 7 – TXWIEN Transmit Watermark Interrupt Enable bit
Value
Description
1
Triggers transmit buffer element watermark interrupt when TXMSK[5:0] = TXELM[5:0]
0
Disables transmit buffer element watermark interrupt
Bits 5:0 – TXMSK[5:0] TX Buffer Mask bits
TX mask bits; used in conjunction with the TXWIEN bit.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 665
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.35 SPI3 Underrun Data Register Low
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI3URDTL
0x444
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
URDATA[15:8]
R/W
R/W
0
0
4
3
URDATA[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – URDATA[15:0] SPI Underrun Data bits
These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit Underrun
condition occurs.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 666
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.36 SPI3 Underrun Data Register High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI3URDTH
0x446
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
URDATA[31:24]
R/W
R/W
0
0
4
3
URDATA[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – URDATA[31:24] SPI Underrun Data bits
These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit Underrun
condition occurs.
Bits 7:0 – URDATA[23:16] SPI Underrun Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 667
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.37 SPI4 Control Register 1 Low
Name:
Offset:
SPI4CON1L
0x448
Note:
Bit
Access
Reset
Bit
Access
Reset
1.
When AUDEN = 1, this module functions as if CKE = 0, regardless of its actual value.
2.
When FRMEN = 1, SSEN is not used.
3.
MCLKEN can only be written when the SPIEN bit = 0.
4.
This channel is not meaningful for DSP/PCM mode as LRC follows the FRMSYPW bit.
15
SPIEN
R/W
0
14
7
SSEN
R/W
0
6
CKP
R/W
0
13
SPISIDL
R/W
0
12
DISSDO
R/W
0
11
10
R/W
0
5
MSTEN
R/W
0
4
DISSDI
R/W
0
3
DISSCK
R/W
0
R/W
0
9
SMP
R/W
0
8
CKE
R/W
0
2
MCLKEN
R/W
0
1
SPIFE
R/W
0
0
ENHBUF
R/W
0
MODE[1:0]
Bit 15 – SPIEN SPI On bit
Value
Description
1
Enables module
0
Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR
modifications
Bit 13 – SPISIDL SPI Stop in Idle Mode bit
Value
Description
1
Halts in CPU Idle mode
0
Continues to operate in CPU Idle mode
Bit 12 – DISSDO Disable SDO Output Port bit
Value
Description
1
SDO pin is not used by the module; pin is controlled by the port function
0
SDO pin is controlled by the module
Bits 11:10 – MODE[1:0] Serial Word Length bits(1,4)
AUDEN = 0:
MODE32
1
0
0
AUDEN = 1:
MODE32
1
1
0
0
MODE16
x
1
0
COMMUNICATION
32-Bit
16-Bit
8-Bit
FIFO DEPTH
8
16
32
MODE16
1
0
1
0
COMMUNICATION
24-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
32-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
16-Bit Data, 16-Bit FIFO, 32-Bit Channel/64-Bit Frame
16-Bit Data, 16-Bit FIFO, 16-Bit Channel/32-Bit Frame
Bit 9 – SMP SPI Data Input Sample Phase bit
Slave Mode:
Input data are always sampled at the middle of data output time, regardless of the SMP setting.
Master Mode:
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 668
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Value
1
0
Description
Input data are sampled at the end of data output time
Input data are sampled at the middle of data output time
Bit 8 – CKE SPI Clock Edge Select bit(1)
Value
Description
1
Transmit happens on transition from active clock state to Idle clock state
0
Transmit happens on transition from Idle clock state to active clock state
Bit 7 – SSEN Slave Select Enable bit (Slave mode)(2)
Value
Description
1
SS pin is used by the macro in Slave mode; SS pin is used as the Slave select input
0
SS pin is not used by the macro (SS pin will be controlled by the port I/O)
Bit 6 – CKP SPI Clock Polarity Select bit
Value
Description
1
Idle state for clock is a high level; active state is a low level
0
Idle state for clock is a low level; active state is a high level
Bit 5 – MSTEN Master Mode Enable bit
Value
Description
1
Master mode
0
Slave mode
Bit 4 – DISSDI Disable SDI Input Port bit
Value
Description
1
SDI pin is not used by the module; pin is controlled by the port function
0
SDI pin is controlled by the module
Bit 3 – DISSCK Disable SCK Output Port bit
Value
Description
1
SCK pin is not used by the module; pin is controlled by the port function
0
SCK pin is controlled by the module
Bit 2 – MCLKEN Master Clock Enable bit(3)
Value
Description
1
Reference Clock Output (REFO) is used by the BRG
0
Peripheral clock is used by the BRG
Bit 1 – SPIFE Frame Sync Pulse Edge Select bit
Value
Description
1
Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock
0
Frame Sync pulse (Idle-to-active edge) precedes the first bit clock
Bit 0 – ENHBUF Enhanced Buffer Mode Enable bit
Value
Description
1
Enhanced Buffer mode is enabled
0
Enhanced Buffer mode is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 669
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.38 SPI4 Control Register 1 High
Name:
Offset:
SPI4CON1H
0x44A
Note:
Bit
Access
Reset
Bit
Access
Reset
1.
AUDEN can only be written when the SPIEN bit = 0.
2.
AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN = 1.
3.
URDTEN is only valid when IGNTUR = 1.
4.
AUDMOD[1:0] bits can only be written when the SPIEN bit = 0 and are only valid when AUDEN = 1. When
NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.
15
AUDEN
R/W
0
14
SPISGNEXT
R/W
0
13
IGNROV
R/W
0
12
IGNTUR
R/W
0
11
AUDMONO
R/W
0
10
URDTEN
R/W
0
7
FRMEN
R/W
0
6
FRMSYNC
R/W
0
5
FRMPOL
R/W
0
4
MSSEN
R/W
0
3
FRMSYPW
R/W
0
2
R/W
0
9
8
AUDMOD[1:0]
R/W
R/W
0
0
1
FRMCNT[2:0]
R/W
0
0
R/W
0
Bit 15 – AUDEN Audio Codec Support Enable bit(1)
Value
Description
1
Audio protocol is enabled; MSTEN controls the direction of both the SCK and frame (a.k.a. LRC), and
this module functions as if FRMEN = 1, FRMSYNC = MSTEN, FRMCNT[2:0] = 001 and SMP = 0,
regardless of their actual values
0
Audio protocol is disabled
Bit 14 – SPISGNEXT SPI Sign-Extend RX FIFO Read Data Enable bit
Value
Description
1
Data from RX FIFO are sign-extended
0
Data from RX FIFO are not sign-extended
Bit 13 – IGNROV Ignore Receive Overflow bit
Value
Description
1
A Receive Overflow (ROV) is NOT a critical error; during ROV, data in the FIFO are not overwritten by
the receive data
0
A ROV is a critical error that stops SPI operation
Bit 12 – IGNTUR Ignore Transmit Underrun bit
Value
Description
1
A Transmit Underrun (TUR) is NOT a critical error and data indicated by URDTEN are transmitted until
the SPI4TXB is not empty
0
A TUR is a critical error that stops SPI operation
Bit 11 – AUDMONO Audio Data Format Transmit bit(2)
Value
Description
1
Audio data are mono (i.e., each data word is transmitted on both left and right channels)
0
Audio data are stereo
Bit 10 – URDTEN Transmit Underrun Data Enable bit(3)
Value
Description
1
Transmits data out of SPI4URDTL/H register during Transmit Underrun conditions
0
Transmits the last received data during Transmit Underrun conditions
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 670
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Bits 9:8 – AUDMOD[1:0] Audio Protocol Mode Selection bits(4)
Value
Description
11
PCM/DSP mode
10
Right Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
01
Left Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
01
I2S mode: This module functions as if SPIFE = 0, regardless of its actual value
Bit 7 – FRMEN Framed SPI Support bit
Value
Description
1
Framed SPI support is enabled (SS pin is used as the FSYNC input/output)
0
Framed SPI support is disabled
Bit 6 – FRMSYNC Frame Sync Pulse Direction Control bit
Value
Description
1
Frame Sync pulse input (Slave)
0
Frame Sync pulse output (Master)
Bit 5 – FRMPOL Frame Sync/Slave Select Polarity bit
Value
Description
1
Frame Sync pulse/Slave select is active-high
0
Frame Sync pulse/Slave select is active-low
Bit 4 – MSSEN Master Mode Slave Select Enable bit
Value
Description
1
SPI Slave select support is enabled with polarity determined by FRMPOL (SS pin is automatically
driven during transmission in Master mode)
0
SPI Slave select support is disabled (SS pin will be controlled by port I/O)
Bit 3 – FRMSYPW Frame Sync Pulse-Width bit
Value
Description
1
Frame Sync pulse is one serial word length wide (as defined by MODE[32,16]/WLENGTH[4:0])
0
Frame Sync pulse is one clock (SCK) wide
Bits 2:0 – FRMCNT[2:0] Frame Sync Pulse Counter bits
Controls the number of serial words transmitted per Sync pulse.
Value
Description
111
Reserved
110
Reserved
101
Generates a Frame Sync pulse on every 32 serial words
100
Generates a Frame Sync pulse on every 16 serial words
011
Generates a Frame Sync pulse on every 8 serial words
010
Generates a Frame Sync pulse on every 4 serial words
001
Generates a Frame Sync pulse on every 2 serial words (value used by audio protocols)
000
Generates a Frame Sync pulse on each serial word
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 671
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.39 SPI4 Control Register 2 Low
Name:
Offset:
SPI4CON2L
0x44C
Note:
Bit
1.
These bits are effective when AUDEN = 0 only.
2.
Varying the length by changing these bits does not affect the depth of the TX/RX FIFO.
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
R/W
0
R/W
0
2
WLENGTH[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 4:0 – WLENGTH[4:0] Variable Word Length bits(1,2)
Value
Description
11111
32-bit data
11110
31-bit data
11101
30-bit data
11100
29-bit data
11011
28-bit data
11010
27-bit data
11001
26-bit data
11000
25-bit data
10111
24-bit data
10110
23-bit data
10101
22-bit data
10100
21-bit data
10011
20-bit data
10010
19-bit data
10001
18-bit data
10000
17-bit data
01111
16-bit data
01110
15-bit data
01101
14-bit data
01100
13-bit data
01011
12-bit data
01010
11-bit data
01001
10-bit data
01000
9-bit data
00111
8-bit data
00110
7-bit data
00101
6-bit data
00100
5-bit data
00011
4-bit data
00010
3-bit data
00001
2-bit data
00000
See MODE[32,16] bits in SPI4CON1L[11:10]
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 672
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.40 SPI4 Status Register Low
Name:
Offset:
SPI4STATL
0x450
Note:
1.
SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the Transmit
Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software.
Legend: C = Clearable bit; HS = Hardware Settable bit; HSC = Hardware Settable/Clearable bit
Bit
15
14
13
12
FRMERR
HS/R/C
0
11
SPIBUSY
HSC
0
10
9
8
SPITUR
HS/R/C
0
7
SRMT
HSC
0
6
SPIROV
HSC
0
5
SPIRBE
HSC
0
4
3
SPITBE
HSC
0
2
1
SPITBF
HSC
0
0
SPIRBF
HSC
0
Access
Reset
Bit
Access
Reset
Bit 12 – FRMERR SPI Frame Error Status bit
Value
Description
1
Frame error is detected
0
No frame error is detected
Bit 11 – SPIBUSY SPI Activity Status bit
Value
Description
1
Module is currently busy with some transactions
0
No ongoing transactions (at time of read)
Bit 8 – SPITUR SPI Transmit Underrun Status bit(1)
Value
Description
1
Transmit buffer has encountered a Transmit Underrun condition
0
Transmit buffer does not have a Transmit Underrun condition
Bit 7 – SRMT Shift Register Empty Status bit
Value
Description
1
No current or pending transactions (i.e., neither SPI4TXB or SPI4TXSR contains data to transmit)
0
Current or pending transactions
Bit 6 – SPIROV SPI Receive Overflow Status bit
Value
Description
1
A new byte/half-word/word has been completely received when the SPI4RXB is full
0
No overflow
Bit 5 – SPIRBE SPI RX Buffer Empty Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI4BUF is read from, reading SPI4RXB. Automatically cleared in hardware
when SPI transfers data from SPI4RXSR to SPI4RXB.
Enhanced Buffer Mode:
Indicates RXELM[5:0] = 000000.
Value
Description
1
RX buffer is empty
0
RX buffer is not empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 673
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Bit 3 – SPITBE SPI Transmit Buffer Empty Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI transfers data from SPI4TXB to SPI4TXSR. Automatically cleared in
hardware when SPI4BUF is written, loading SPI4TXB.
Enhanced Buffer Mode:
Indicates TXELM[5:0] = 000000.
Value
Description
1
SPI4TXB is empty
0
SPI4TXB is not empty
Bit 1 – SPITBF SPI Transmit Buffer Full Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI4BUF is written, loading SPI4TXB. Automatically cleared in hardware when
SPI transfers data from SPI4TXB to SPI4TXSR.
Enhanced Buffer Mode:
Indicates TXELM[5:0] = 111111.
Value
Description
1
SPI4TXB is full
0
SPI4TXB not full
Bit 0 – SPIRBF SPI Receive Buffer Full Status bit
Standard Buffer Mode:
Automatically set in hardware when SPI transfers data from SPI4RXSR to SPI4RXB. Automatically cleared in
hardware when SPI4BUF is read from, reading SPI4RXB.
Enhanced Buffer Mode:
Indicates RXELM[5:0] = 111111.
Value
Description
1
SDI pin is not used by the module; pin is controlled by the port function
0
SDI pin is controlled by the module
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 674
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.41 SPI4 Status Register High
Name:
Offset:
SPI4STATH
0x452
Legend: C = Clearable bit; HSC = Hardware Settable/Clearable bit
Bit
15
14
Access
Reset
Bit
Access
Reset
7
13
12
HSC/R/C
0
HSC/R/C
0
5
4
HSC/R/C
0
HSC/R/C
0
6
11
10
RXELM[5:0]
HSC/R/C
HSC/R/C
0
0
2
TXELM[5:0]
HSC/R/C
HSC/R/C
0
0
9
8
HSC/R/C
0
HSC/R/C
0
1
0
HSC/R/C
0
HSC/R/C
0
3
Bits 13:8 – RXELM[5:0] Receive Buffer Element Count bits (valid in Enhanced Buffer mode)
Bits 5:0 – TXELM[5:0] Transmit Buffer Element Count bits (valid in Enhanced Buffer mode)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 675
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.42 SPI4 Buffer Register Low
Name:
Offset:
Bit
15
SPI4BUFL
0x454
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – DATA[15:0] SPI FIFO Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 676
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.43 SPI4 Buffer Register High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI4BUFH
0x456
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
DATA[31:24]
R/W
R/W
0
0
4
3
DATA[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – DATA[31:24] SPI FIFO Data bits
Bits 7:0 – DATA[23:16] SPI FIFO Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 677
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.44 SPI4 Baud Rate Generator Register Low
Name:
Offset:
SPI4BRGL
0x458
Note:
1. Changing the BRG value when SPIEN = 1 causes undefined behavior.
Bit
15
14
13
Access
Reset
Bit
7
6
5
12
11
9
8
R/W
0
10
BRG[12:8]
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
4
BRG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 12:0 – BRG[12:0] SPI Baud Rate Generator Divisor bits(1)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 678
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.45 SPI4 Interrupt Mask Register Low
Name:
Offset:
SPI4IMSKL
0x45C
Legend: C = Clearable bit
Bit
15
14
13
12
FRMERREN
R/W
0
11
BUSYEN
R/W
0
10
9
8
SPITUREN
R/C
0
7
SRMTEN
R/W
0
6
SPIROVEN
R/W
0
5
SPIRBEN
R/W
0
4
3
SPITBEN
R/W
0
2
1
SPITBFEN
R/W
0
0
SPIRBFEN
R/W
0
Access
Reset
Bit
Access
Reset
Bit 12 – FRMERREN Enable Interrupt Events via FRMERR bit
Value
Description
1
Frame error generates an interrupt event
0
Frame error does not generate an interrupt event
Bit 11 – BUSYEN Enable Interrupt Events via SPIBUSY bit
Value
Description
1
SPIBUSY generates an interrupt event
0
SPIBUSY does not generate an interrupt event
Bit 8 – SPITUREN Enable Interrupt Events via SPITUR bit
Value
Description
1
Transmit Underrun (TUR) generates an interrupt event
0
Transmit Underrun does not generate an interrupt event
Bit 7 – SRMTEN Enable Interrupt Events via SRMT bit
Value
Description
1
Shift Register Empty (SRMT) generates interrupt events
0
Shift Register Empty does not generate interrupt events
Bit 6 – SPIROVEN Enable Interrupt Events via SPIROV bit
Value
Description
1
SPI receive overflow generates an interrupt event
0
SPI receive overflow does not generate an interrupt event
Bit 5 – SPIRBEN Enable Interrupt Events via SPIRBE bit
Value
Description
1
SPI RX buffer empty generates an interrupt event
0
SPI RX buffer empty does not generate an interrupt event
Bit 3 – SPITBEN Enable Interrupt Events via SPITBE bit
Value
Description
1
SPI transmit buffer empty generates an interrupt event
0
SPI transmit buffer empty does not generate an interrupt event
Bit 1 – SPITBFEN Enable Interrupt Events via SPITBF bit
Value
Description
1
SPI transmit buffer full generates an interrupt event
0
SPI transmit buffer full does not generate an interrupt event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 679
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
Bit 0 – SPIRBFEN Enable Interrupt Events via SPIRBF bit
Value
Description
1
SPI receive buffer full generates an interrupt event
0
SPI receive buffer full does not generate an interrupt event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 680
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.46 SPI4 Interrupt Mask Register High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI4IMSKH
0x45E
15
RXWIEN
R/W
0
14
7
TXWIEN
R/W
0
6
13
12
R/W
0
R/W
0
5
4
R/W
0
R/W
0
11
10
RXMSK[5:0]
R/W
R/W
0
0
3
2
TXMSK[5:0]
R/W
R/W
0
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bit 15 – RXWIEN Receive Watermark Interrupt Enable bit
Value
Description
1
Triggers receive buffer element watermark interrupt when RXMSK[5:0] ≤ RXELM[5:0]
0
Disables receive buffer element watermark interrupt
Bits 13:8 – RXMSK[5:0] RX Buffer Mask bits
RX mask bits; used in conjunction with the RXWIEN bit.
Bit 7 – TXWIEN Transmit Watermark Interrupt Enable bit
Value
Description
1
Triggers transmit buffer element watermark interrupt when TXMSK[5:0] = TXELM[5:0]
0
Disables transmit buffer element watermark interrupt
Bits 5:0 – TXMSK[5:0] TX Buffer Mask bits
TX mask bits; used in conjunction with the TXWIEN bit.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 681
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.47 SPI4 Underrun Data Register Low
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI4URDTL
0x460
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
URDATA[15:8]
R/W
R/W
0
0
4
3
URDATA[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – URDATA[15:0] SPI Underrun Data bits
These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit Underrun
condition occurs.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 682
PIC24FJ512GU410 Family Data Sheet
Serial Peripheral Interface (SPI)
15.5.48 SPI4 Underrun Data Register High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
SPI4URDTH
0x462
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
URDATA[31:24]
R/W
R/W
0
0
4
3
URDATA[23:16]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – URDATA[31:24] SPI Underrun Data bits
These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit Underrun
condition occurs.
Bits 7:0 – URDATA[23:16] SPI Underrun Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 683
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.
Inter-Integrated Circuit (I2C)
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information, refer to “Inter-Integrated Circuit (I2C)”
(www.microchip.com/DS70000195) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data
sheet supersedes the information in the FRM.
The Inter-Integrated Circuit (I2C) module is a serial interface useful for communicating with other peripheral or
microcontroller devices. These peripheral devices may be serial EEPROMs, display drivers, A/D Converters, etc.
The I2C module supports these features:
•
•
•
•
•
•
•
•
•
Independent Master and Slave Logic
7-Bit and 10-Bit Device Addresses
General Call Address as Defined in the I2C Protocol
Clock Stretching to Provide Delays for the Processor to Respond to a Slave Data Request
Both 100 kHz, 400 kHz and 1 MHz Bus Specifications
Configurable Address Masking
Multi-Master modes to Prevent Loss of Messages in Arbitration
Bus Repeater mode, Allowing the Acceptance of All Messages as a Slave, regardless of the Address
Automatic SCL
•
PMBus™
A block diagram of the module is shown in Figure 16-1.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 684
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
Figure 16-1. I2C Block Diagram
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 685
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.1
Communicating as a Master in a Single Master Environment
The details of sending a message in Master mode depends on the communications protocol for the device being
communicated with. Typically, the sequence of events is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
16.2
Assert a Start condition on SDAx and SCLx.
Send the I2C device address byte to the Slave with a write indication.
Wait for and verify an Acknowledge from the Slave.
Send the first data byte (sometimes known as the command) to the Slave.
Wait for and verify an Acknowledge from the Slave.
Send the serial memory address low byte to the Slave.
Repeat Steps 4 and 5 until all data bytes are sent.
Assert a Repeated Start condition on SDAx and SCLx.
Send the device address byte to the Slave with a read indication.
Wait for and verify an Acknowledge from the Slave.
Enable Master reception to receive serial memory data.
Generate an ACK or NACK condition at the end of a received byte of data.
Generate a Stop condition on SDAx and SCLx.
Setting Baud Rate When Operating as a Bus Master
To compute the Baud Rate Generator reload value, use Equation 16-1.
Equation 16-1. Computing Baud Rate Reload Value(1,2,3)
FPB
FPB
Note:
1.
2.
3.
16.3
Based on FPB = FOSC/2 (Peripheral Clock).
These clock rate values are for guidance only. The actual clock rate can be affected by various system-level
parameters. The actual clock rate should be measured in its intended application.
BRG values of 0 to 3 are forbidden.
Slave Address Masking
The I2CxMSK register designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes.
Setting a particular bit location (= 1) in the I2CxMSK register causes the Slave module to respond, whether the
corresponding address bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK is set to ‘0010000000’, the Slave
module will detect both addresses, ‘0000000000’ and ‘0010000000’.
To enable address masking, the Intelligent Peripheral Management Interface (IPMI) must be disabled by clearing the
STRICT bit (I2CxCONL[11]).
Note: As a result of changes in the I2C protocol, the addresses in Table 16-1 are reserved and will not be
Acknowledged in Slave mode. This includes any address mask settings that include any of these addresses.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 686
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
Table 16-1. I2C Reserved Addresses(1)
Slave Address
R/W Bit
Description
0000 000
0
General Call Address(2)
0000 000
1
Start Byte
0000 001
x
C-Bus Address
0000 01x
x
Reserved
0000 1xx
x
HS Mode Master Code
1111 0xx
x
10-Bit Slave Upper Byte(3)
1111 1xx
x
Reserved
Note:
1.
2.
The address bits listed here will never cause an address match independent of address mask settings.
This address will be Acknowledged only if GCEN = 1.
3.
A match on this address can only occur on the upper byte in 10-Bit Addressing mode.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 687
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4
I2C Registers
Offset
Name
0x00
...
0x0493
Reserved
0x0494
I2C1RCV
0x0496
I2C1TRN
0x0498
I2C1BRG
0x049A
I2C1CONL
0x049C
I2C1CONH
0x049E
I2C1STAT
0x04A0
I2C1ADD
0x04A2
I2C1MSK
0x04A4
I2C2RCV
0x04A6
I2C2TRN
0x04A8
I2C2BRG
0x04AA
I2C2CONL
0x04AC
I2C2CONH
0x04AE
I2C2STAT
0x04B0
I2C2ADD
0x04B2
I2C2MSK
0x04B4
I2C3RCV
0x04B6
I2C3TRN
0x04B8
I2C3BRG
0x04BA
I2C3CONL
0x04BC
I2C3CONH
0x04BE
I2C3STAT
0x04C0
I2C3ADD
0x04C2
I2C3MSK
Bit Pos.
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7
6
5
4
3
2
1
0
PEN
A10M
SBCDE
RSEN
DISSLW
AHEN
SEN
SMEN
DHEN
R/W
BCL
RBF
GCSTAT
TBF
ADD10
I2CRXDATA[7:0]
I2CTXDATA[7:0]
GCEN
I2CEN
IWCOL
ACKSTAT
STREN
PCIE
ACKDT
I2CSIDL
SCIE
I2COV
TRSTAT
D/A
ACKTIM
I2CBRG[7:0]
I2CBRG[15:8]
ACKEN
RCEN
SCLREL
STRICT
BOEN
SDAHT
P
S
ADD[7:0]
ADD[9:8]
MSK[7:0]
MSK[9:8]
I2CRXDATA[7:0]
I2CTXDATA[7:0]
GCEN
I2CEN
IWCOL
ACKSTAT
STREN
PCIE
ACKDT
I2CSIDL
SCIE
I2COV
TRSTAT
D/A
ACKTIM
I2CBRG[7:0]
I2CBRG[15:8]
ACKEN
RCEN
SCLREL
STRICT
BOEN
SDAHT
P
S
PEN
A10M
SBCDE
RSEN
DISSLW
AHEN
SEN
SMEN
DHEN
R/W
BCL
RBF
GCSTAT
TBF
ADD10
ADD[7:0]
ADD[9:8]
MSK[7:0]
MSK[9:8]
I2CRXDATA[7:0]
I2CTXDATA[7:0]
GCEN
I2CEN
IWCOL
ACKSTAT
© 2019-2020 Microchip Technology Inc.
STREN
PCIE
ACKDT
I2CSIDL
SCIE
I2COV
TRSTAT
D/A
ACKTIM
I2CBRG[7:0]
I2CBRG[15:8]
ACKEN
RCEN
SCLREL
STRICT
BOEN
SDAHT
P
S
PEN
A10M
SBCDE
RSEN
DISSLW
AHEN
SEN
SMEN
DHEN
R/W
BCL
RBF
GCSTAT
TBF
ADD10
ADD[7:0]
ADD[9:8]
MSK[7:0]
MSK[9:8]
Datasheet
DS30010203C-page 688
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.1
I2C1 Receive Register
Bit
Name:
Offset:
I2C1RCV
0x494
15
14
13
7
6
5
R/W
0
R/W
0
R/W
0
12
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
4
3
I2CRXDATA[7:0]
R/W
R/W
0
0
Bits 7:0 – I2CRXDATA[7:0] I2C1 Receive Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 689
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.2
I2C1 Transmit Register
Bit
Name:
Offset:
I2C1TRN
0x496
15
14
13
7
6
5
R/W
0
R/W
0
R/W
0
12
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
4
3
I2CTXDATA[7:0]
R/W
R/W
0
0
Bits 7:0 – I2CTXDATA[7:0] I2C1 Transmit Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 690
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.3
I2C1 Baud Rate Generator Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
I2C1BRG
0x498
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
I2CBRG[15:8]
R/W
R/W
0
0
4
3
I2CBRG[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – I2CBRG[15:0] I2C1 Baud Rate Generator bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 691
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.4
I2C1 Control Register Low
Name:
Offset:
I2C1CONL
0x49A
Note:
1.
2.
Automatically cleared to ‘0’ at the beginning of Slave transmission; automatically cleared to ‘0’ at the end of
Slave reception. The user software must provide a delay between writing to the transmit buffer and setting the
SCLREL bit. This delay must be greater than the minimum setup time for Slave transmissions, as specified in
32. Electrical Characteristics.
Automatically cleared to ‘0’ at the beginning of Slave transmission.
3.
“SMBus 3.0 Specification” input level can be selected by the SMB3EN Configuration bit (FDEVOPT1[10]).
Legend: HC = Hardware Clearable bit
Bit
Access
Reset
Bit
Access
Reset
15
I2CEN
R/W
0
14
13
I2CSIDL
R/W
0
12
SCLREL
R/W
0
11
STRICT
R/W
0
10
A10M
R/W
0
9
DISSLW
R/W
0
8
SMEN
R/W
0
7
GCEN
R/W
0
6
STREN
R/W
0
5
ACKDT
R/W
0
4
ACKEN
HC/R/W
0
3
RCEN
HC/R/W
0
2
PEN
HC/R/W
0
1
RSEN
HC/R/W
0
0
SEN
HC/R/W
0
Bit 15 – I2CEN I2C1 Enable bit (writable from software only)
Value
Description
1
Enables the I2C module and configures the SDA and SCL pins as serial port pins
0
Disables the I2C module; all I2C pins are controlled by port functions
Bit 13 – I2CSIDL I2C1 Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bit 12 – SCLREL SCL Release Control bit (I2C Slave mode only)(1)
If STREN = 1:
Value
Description
1
0
Releases clock
Holds clock low (clock stretch); user may program this bit to ‘0’, clock stretch at next SCL low
If STREN = 0:(2)
Value
Description
1
0
Releases clock
Forces clock low (clock stretch)
Bit 11 – STRICT I2C1 Strict Reserved Address Rule Enable bit
Value
Description
1
Strict Reserved Addressing is enforced (for reserved addresses, refer to Table 16-1)
In Slave Mode: The device does not respond to reserved address space and addresses falling in that
category are NACKed.
In Master Mode: The device is allowed to generate addresses with reserved address space.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 692
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
Value
0
Description
Reserved Addressing would be Acknowledged
In Slave Mode: The device will respond to an address falling in the reserved address space. When
there is a match with any of the reserved addresses, the device will generate an ACK.
In Master Mode: Reserved.
Bit 10 – A10M 10-Bit Slave Address Flag bit
Value
Description
1
I2C1ADD is a 10-bit Slave address
0
I2C1ADD is a 7-bit Slave address
Bit 9 – DISSLW Slew Rate Control Disable bit
Value
Description
1
Slew rate control is disabled for Standard Speed mode (100 kHz, also disabled for 1 MHz mode)
0
Slew rate control is enabled for High-Speed mode (400 kHz)
Bit 8 – SMEN SMBus Input Levels Enable bit(3)
Value
Description
1
Enables input logic so thresholds are compliant with the SMBus specification
0
Disables SMBus-specific inputs
Bit 7 – GCEN General Call Enable bit (I2C Slave mode only)
Value
Description
1
Enables interrupt when a general call address is received in I2C1RSR; module is enabled for reception
0
General call address is disabled
Bit 6 – STREN SCL Clock Stretch Enable bit
In I2C Slave mode only; used in conjunction with the SCLREL bit.
Value
Description
1
Enables clock stretching
0
Disables clock stretching
Bit 5 – ACKDT Acknowledge Data bit
In I2C Master mode during Master Receive mode: The value that will be transmitted when the user initiates an
Acknowledge sequence at the end of a receive.
In I2C Slave mode when AHEN = 1 or DHEN = 1: The value that the Slave will transmit when it initiates an
Acknowledge sequence at the end of an address or data reception.
Value
Description
1
NACK is sent
0
ACK is sent
Bit 4 – ACKEN Acknowledge Sequence Enable bit
In I2C Master mode only; applicable during Master Receive mode.
Value
Description
1
Initiates Acknowledge sequence on SDA and SCL pins, and transmits the ACKDT data bit
0
Acknowledge sequence is Idle
Bit 3 – RCEN Receive Enable bit (I2C Master mode only)
Value
Description
1
Enables Receive mode for I2C; automatically cleared by hardware at the end of the 8-bit receive data
byte
0
Receive sequence is not in progress
Bit 2 – PEN Stop Condition Enable bit (I2C Master mode only)
Value
Description
1
Initiates Stop condition on the SDA and SCL pins
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 693
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
Value
0
Description
Stop condition is Idle
Bit 1 – RSEN Restart Condition Enable bit (I2C Master mode only)
Value
Description
1
Initiates Restart condition on the SDA and SCL pins
0
Restart condition is Idle
Bit 0 – SEN Start Condition Enable bit (I2C Master mode only)
Value
Description
1
Initiates Start condition on the SDA and SCL pins
0
Start condition is Idle
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 694
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.5
I2C1 Control Register High
Name:
Offset:
I2C1CONH
0x49C
Note:
1.
Bit
This bit must be set to ‘0’ for 1 MHz operation.
15
14
13
12
11
10
9
8
7
6
PCIE
R/W
0
5
SCIE
R/W
0
4
BOEN
R/W
0
3
SDAHT
R/W
0
2
SBCDE
R/W
0
1
AHEN
R/W
0
0
DHEN
R/W
0
Access
Reset
Bit
Access
Reset
Bit 6 – PCIE Stop Condition Interrupt Enable bit (I2C Slave mode only)
Value
Description
1
Enables interrupt on detection of Stop condition
0
Stop detection interrupts are disabled
Bit 5 – SCIE Start Condition Interrupt Enable bit (I2C Slave mode only)
Value
Description
1
Enables interrupt on detection of Start or Restart conditions
0
Start detection interrupts are disabled
Bit 4 – BOEN Buffer Overwrite Enable bit (I2C Slave mode only)
Value
Description
1
I2C1RCV is updated and an ACK is generated for a received address/data byte, ignoring the state of
the I2COV bit only if RBF bit = 0
0
I2C1RCV is only updated when I2COV is clear
Bit 3 – SDAHT SDA Hold Time Selection bit(1)
Value
Description
1
Minimum of 300 ns hold time on SDA after the falling edge of SCL
0
Minimum of 100 ns hold time on SDA after the falling edge of SCL
Bit 2 – SBCDE Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL bit is set and
the bus goes Idle. This Detection mode is only valid during data and ACK transmit sequences.
Value
Description
1
Enables Slave bus collision interrupts
0
Slave bus collision interrupts are disabled
Bit 1 – AHEN Address Hold Enable bit (I2C Slave mode only)
Value
Description
1
Following the 8th falling edge of SCL for a matching received address byte; SCLREL bit
(I2CxCONL[12]) will be cleared and SCL will be held low
0
Address holding is disabled
Bit 0 – DHEN Data Hold Enable bit (I2C Slave mode only)
Value
Description
1
Following the 8th falling edge of SCL for a received data byte; Slave hardware clears the SCLREL bit
(I2C1CONL[12]) and SCL is held low
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 695
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
Value
0
Description
Data holding is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 696
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.6
I2C1 Status Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
I2C1STAT
0x49E
15
ACKSTAT
R/W
0
14
TRSTAT
R/W
0
13
ACKTIM
R/W
0
12
11
10
BCL
R/W
0
9
GCSTAT
R/W
0
8
ADD10
R/W
0
7
IWCOL
R/W
0
6
I2COV
R/W
0
5
D/A
R/W
0
4
P
R/W
0
3
S
R/W
0
2
R/W
R/W
0
1
RBF
R/W
0
0
TBF
R/W
0
Bit 15 – ACKSTAT Acknowledge Status bit (updated in all Master and Slave modes)
Value
Description
1
Acknowledge was not received from Slave
0
Acknowledge was received from Slave
Bit 14 – TRSTAT Transmit Status bit (when operating as I2C Master; applicable to Master transmit operation)
Value
Description
1
Master transmit is in progress (8 bits + ACK)
0
Master transmit is not in progress
Bit 13 – ACKTIM Acknowledge Time Status bit (valid in I2C Slave mode only)
Value
Description
1
Indicates I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock
0
Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock
Bit 10 – BCL Bus Collision Detect bit (Master/Slave mode; cleared when I2C module is disabled, I2CEN = 0)
Value
Description
1
A bus collision has been detected during a Master or Slave transmit operation
0
No bus collision has been detected
Bit 9 – GCSTAT General Call Status bit (cleared after Stop detection)
Value
Description
1
General call address was received
0
General call address was not received
Bit 8 – ADD10 10-Bit Address Status bit (cleared after Stop detection)
Value
Description
1
10-bit address was matched
0
10-bit address was not matched
Bit 7 – IWCOL I2C1 Write Collision Detect bit
Value
Description
1
An attempt to write to the I2C1TRN register failed because the I2C module is busy; must be cleared in
software
0
No collision
Bit 6 – I2COV I2C1 Receive Overflow Flag bit
Value
Description
1
A byte was received while the I2C1RCV register was still holding the previous byte; I2COV is a “don’t
care” in Transmit mode, must be cleared in software
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 697
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
Value
0
Description
No overflow
Bit 5 – D/A Data/Address bit (when operating as I2C Slave)
Value
Description
1
Indicates that the last byte received was data
0
Indicates that the last byte received or transmitted was an address
Bit 4 – P I2C1 Stop bit
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
Value
Description
1
Indicates that a Stop bit has been detected last
0
Stop bit was not detected last
Bit 3 – S I2C1 Start bit
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
Value
Description
1
Indicates that a Start (or Repeated Start) bit has been detected last
0
Start (or Repeated Start) bit was not detected last
Bit 2 – R/W Read/Write Information bit (when operating as I2C Slave)
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
Value
Description
1
Read: Indicates the data transfer is output from the Slave
0
Write: Indicates the data transfer is input to the Slave
Bit 1 – RBF Receive Buffer Full Status bit
Value
Description
1
Receive is complete, I2C1RCV is full
0
Receive is not complete, I2C1RCV is empty
Bit 0 – TBF Transmit Buffer Full Status bit
Value
Description
1
Transmit is in progress, I2C1TRN is full (eight bits of data)
0
Transmit is complete, I2C1TRN is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 698
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.7
I2C1 Address Register
Bit
Name:
Offset:
I2C1ADD
0x4A0
15
14
13
12
11
10
9
8
ADD[9:8]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ADD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – ADD[9:0] I2C1 Address bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 699
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.8
I2C1 Slave Mode Address Mask Register
Name:
Offset:
Bit
15
I2C1MSK
0x4A2
14
13
12
11
10
9
8
MSK[9:8]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
MSK[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – MSK[9:0] I2C1 Mask for Address bits
Value
Description
1
Enables masking for bit of the incoming message address; bit match is not required in this position
0
Disables masking for bit; bit match is required in this position
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 700
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.9
I2C2 Receive Register
Bit
Name:
Offset:
I2C2RCV
0x4A4
15
14
13
7
6
5
R/W
0
R/W
0
R/W
0
12
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
4
3
I2CRXDATA[7:0]
R/W
R/W
0
0
Bits 7:0 – I2CRXDATA[7:0] I2C2 Receive Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 701
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.10 I2C2 Transmit Register
Bit
Name:
Offset:
I2C2TRN
0x4A6
15
14
13
7
6
5
R/W
0
R/W
0
R/W
0
12
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
4
3
I2CTXDATA[7:0]
R/W
R/W
0
0
Bits 7:0 – I2CTXDATA[7:0] I2C2 Transmit Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 702
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.11 I2C2 Baud Rate Generator Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
I2C2BRG
0x4A8
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
I2CBRG[15:8]
R/W
R/W
0
0
4
3
I2CBRG[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – I2CBRG[15:0] I2C2 Baud Rate Generator bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 703
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.12 I2C2 Control Register Low
Name:
Offset:
I2C2CONL
0x4AA
Note:
1.
2.
Automatically cleared to ‘0’ at the beginning of Slave transmission; automatically cleared to ‘0’ at the end of
Slave reception. The user software must provide a delay between writing to the transmit buffer and setting the
SCLREL bit. This delay must be greater than the minimum setup time for Slave transmissions, as specified in
32. Electrical Characteristics.
Automatically cleared to ‘0’ at the beginning of Slave transmission.
3.
“SMBus 3.0 Specification” input level can be selected by the SMB3EN Configuration bit (FDEVOPT1[10]).
Legend: HC = Hardware Clearable bit
Bit
Access
Reset
Bit
Access
Reset
15
I2CEN
R/W
0
14
13
I2CSIDL
R/W
0
12
SCLREL
R/W
0
11
STRICT
R/W
0
10
A10M
R/W
0
9
DISSLW
R/W
0
8
SMEN
R/W
0
7
GCEN
R/W
0
6
STREN
R/W
0
5
ACKDT
R/W
0
4
ACKEN
HC/R/W
0
3
RCEN
HC/R/W
0
2
PEN
HC/R/W
0
1
RSEN
HC/R/W
0
0
SEN
HC/R/W
0
Bit 15 – I2CEN I2C2 Enable bit (writable from software only)
Value
Description
1
Enables the I2C2 module and configures the SDA and SCL pins as serial port pins
0
Disables the I2C2 module; all I2C pins are controlled by port functions
Bit 13 – I2CSIDL I2C2 Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bit 12 – SCLREL SCL Release Control bit (I2C Slave mode only)(1)
If STREN = 1:
Value
Description
1
0
Releases clock
Holds clock low (clock stretch); user may program this bit to ‘0’, clock stretch at next SCL low
If STREN = 0:(2)
Value
Description
1
0
Releases clock
Forces clock low (clock stretch)
Bit 11 – STRICT I2C2 Strict Reserved Address Rule Enable bit
Value
Description
1
Strict Reserved Addressing is enforced (for reserved addresses, refer to Table 16-1)
In Slave mode: The device does not respond to reserved address space and addresses falling in that
category are NACKed.
In Master mode: The device is allowed to generate addresses with reserved address space.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 704
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
Value
0
Description
Reserved addressing would be Acknowledged
In Slave mode: The device will respond to an address falling in the reserved address space. When
there is a match with any of the reserved addresses, the device will generate an ACK.
In Master mode: Reserved.
Bit 10 – A10M 10-Bit Slave Address Flag bit
Value
Description
1
I2C2ADD is a 10-bit Slave address
0
I2C2ADD is a 7-bit Slave address
Bit 9 – DISSLW Slew Rate Control Disable bit
Value
Description
1
Slew rate control is disabled for Standard Speed mode (100 kHz, also disabled for 1 MHz mode)
0
Slew rate control is enabled for High-Speed mode (400 kHz)
Bit 8 – SMEN SMBus Input Levels Enable bit(3)
Value
Description
1
Enables input logic so thresholds are compliant with the SMBus specification
0
Disables SMBus-specific inputs
Bit 7 – GCEN General Call Enable bit (I2C Slave mode only)
Value
Description
1
Enables interrupt when a general call address is received in I2C2RSR; module is enabled for reception
0
General call address is disabled
Bit 6 – STREN SCL Clock Stretch Enable bit
In I2C Slave mode only; used in conjunction with the SCLREL bit.
Value
Description
1
Enables clock stretching
0
Disables clock stretching
Bit 5 – ACKDT Acknowledge Data bit
In I2C Master mode during Master Receive mode: The value that will be transmitted when the user initiates an
Acknowledge sequence at the end of a receive.
In I2C Slave mode when AHEN = 1 or DHEN = 1: The value that the Slave will transmit when it initiates an
Acknowledge sequence at the end of an address or data reception.
Value
Description
1
NACK is sent
0
ACK is sent
Bit 4 – ACKEN Acknowledge Sequence Enable bit
In I2C Master mode only; applicable during Master Receive mode.
Value
Description
1
Initiates Acknowledge sequence on SDA and SCL pins, and transmits the ACKDT data bit
0
Acknowledge sequence is Idle
Bit 3 – RCEN Receive Enable bit (I2C Master mode only)
Value
Description
1
Enables Receive mode for I2C; automatically cleared by hardware at the end of the 8-bit receive data
byte
0
Receive sequence is not in progress
Bit 2 – PEN Stop Condition Enable bit (I2C Master mode only)
Value
Description
1
Initiates Stop condition on the SDA and SCL pins
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 705
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
Value
0
Description
Stop condition is Idle
Bit 1 – RSEN Restart Condition Enable bit (I2C Master mode only)
Value
Description
1
Initiates Restart condition on the SDA and SCL pins
0
Restart condition is Idle
Bit 0 – SEN Start Condition Enable bit (I2C Master mode only)
Value
Description
1
Initiates Start condition on the SDA and SCL pins
0
Start condition is Idle
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 706
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.13 I2C2 Control Register High
Name:
Offset:
I2C2CONH
0x4AC
Note:
1.
Bit
This bit must be set to ‘0’ for 1 MHz operation.
15
14
13
12
11
10
9
8
7
6
PCIE
R/W
0
5
SCIE
R/W
0
4
BOEN
R/W
0
3
SDAHT
R/W
0
2
SBCDE
R/W
0
1
AHEN
R/W
0
0
DHEN
R/W
0
Access
Reset
Bit
Access
Reset
Bit 6 – PCIE Stop Condition Interrupt Enable bit (I2C Slave mode only)
Value
Description
1
Enables interrupt on detection of Stop condition
0
Stop detection interrupts are disabled
Bit 5 – SCIE Start Condition Interrupt Enable bit (I2C Slave mode only)
Value
Description
1
Enables interrupt on detection of Start or Restart conditions
0
Start detection interrupts are disabled
Bit 4 – BOEN Buffer Overwrite Enable bit (I2C Slave mode only)
Value
Description
1
I2C2RCV is updated and an ACK is generated for a received address/data byte, ignoring the state of
the I2COV bit only if RBF bit = 0
0
I2C2RCV is only updated when I2COV is clear
Bit 3 – SDAHT SDA Hold Time Selection bit(1)
Value
Description
1
Minimum of 300 ns hold time on SDA after the falling edge of SCL
0
Minimum of 100 ns hold time on SDA after the falling edge of SCL
Bit 2 – SBCDE Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL bit is set and
the bus goes Idle. This Detection mode is only valid during data and ACK transmit sequences.
Value
Description
1
Enables Slave bus collision interrupts
0
Slave bus collision interrupts are disabled
Bit 1 – AHEN Address Hold Enable bit (I2C Slave mode only)
Value
Description
1
Following the 8th falling edge of SCL for a matching received address byte; SCLREL bit
(I2C2CONL[12]) will be cleared and SCL will be held low
0
Address holding is disabled
Bit 0 – DHEN Data Hold Enable bit (I2C Slave mode only)
Value
Description
1
Following the 8th falling edge of SCL for a received data byte; Slave hardware clears the SCLREL bit
(I2C2CONL[12]) and SCL is held low
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 707
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
Value
0
Description
Data holding is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 708
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.14 I2C2 Status Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
I2C2STAT
0x4AE
15
ACKSTAT
R/W
0
14
TRSTAT
R/W
0
13
ACKTIM
R/W
0
12
11
10
BCL
R/W
0
9
GCSTAT
R/W
0
8
ADD10
R/W
0
7
IWCOL
R/W
0
6
I2COV
R/W
0
5
D/A
R/W
0
4
P
R/W
0
3
S
R/W
0
2
R/W
R/W
0
1
RBF
R/W
0
0
TBF
R/W
0
Bit 15 – ACKSTAT Acknowledge Status bit (updated in all Master and Slave modes)
Value
Description
1
Acknowledge was not received from Slave
0
Acknowledge was received from Slave
Bit 14 – TRSTAT Transmit Status bit (when operating as I2C Master; applicable to Master transmit operation)
Value
Description
1
Master transmit is in progress (8 bits + ACK)
0
Master transmit is not in progress
Bit 13 – ACKTIM Acknowledge Time Status bit (valid in I2C Slave mode only)
Value
Description
1
Indicates I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock
0
Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock
Bit 10 – BCL Bus Collision Detect bit (Master/Slave mode; cleared when I2C module is disabled, I2CEN = 0)
Value
Description
1
A bus collision has been detected during a Master or Slave transmit operation
0
No bus collision has been detected
Bit 9 – GCSTAT General Call Status bit (cleared after Stop detection)
Value
Description
1
General call address was received
0
General call address was not received
Bit 8 – ADD10 10-Bit Address Status bit (cleared after Stop detection)
Value
Description
1
10-bit address was matched
0
10-bit address was not matched
Bit 7 – IWCOL I2C2 Write Collision Detect bit
Value
Description
1
An attempt to write to the I2C2TRN register failed because the I2C module is busy; must be cleared in
software
0
No collision
Bit 6 – I2COV I2C2 Receive Overflow Flag bit
Value
Description
1
A byte was received while the I2C2RCV register was still holding the previous byte; I2COV is a “don’t
care” in Transmit mode, must be cleared in software
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 709
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
Value
0
Description
No overflow
Bit 5 – D/A Data/Address bit (when operating as I2C Slave)
Value
Description
1
Indicates that the last byte received was data
0
Indicates that the last byte received or transmitted was an address
Bit 4 – P I2C2 Stop bit
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
Value
Description
1
Indicates that a Stop bit has been detected last
0
Stop bit was not detected last
Bit 3 – S I2C2 Start bit
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
Value
Description
1
Indicates that a Start (or Repeated Start) bit has been detected last
0
Start (or Repeated Start) bit was not detected last
Bit 2 – R/W Read/Write Information bit (when operating as I2C Slave)
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
Value
Description
1
Read: Indicates the data transfer is output from the Slave
0
Write: Indicates the data transfer is input to the Slave
Bit 1 – RBF Receive Buffer Full Status bit
Value
Description
1
Receive is complete, I2C2RCV is full.
0
Receive is not complete, I2C2RCV is empty
Bit 0 – TBF Transmit Buffer Full Status bit
Value
Description
1
Transmit is in progress, I2C2TRN is full (eight bits of data)
0
Transmit is complete, I2C2TRN is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 710
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.15 I2C2 Address Register
Bit
Name:
Offset:
I2C2ADD
0x4B0
15
14
13
12
11
10
9
8
ADD[9:8]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ADD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – ADD[9:0] I2C2 Address bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 711
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.16 I2C2 Slave Mode Address Mask Register
Name:
Offset:
Bit
15
I2C2MSK
0x4B2
14
13
12
11
10
9
8
MSK[9:8]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
MSK[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – MSK[9:0] I2C2 Mask for Address bits
Value
Description
1
Enables masking for bit of the incoming message address; bit match is not required in this position
0
Disables masking for bit; bit match is required in this position
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 712
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.17 I2C3 Receive Register
Bit
Name:
Offset:
I2C3RCV
0x4B4
15
14
13
7
6
5
R/W
0
R/W
0
R/W
0
12
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
4
3
I2CRXDATA[7:0]
R/W
R/W
0
0
Bits 7:0 – I2CRXDATA[7:0] I2C3 Receive Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 713
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.18 I2C3 Transmit Register
Bit
Name:
Offset:
I2C3TRN
0x4B6
15
14
13
7
6
5
R/W
0
R/W
0
R/W
0
12
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
4
3
I2CTXDATA[7:0]
R/W
R/W
0
0
Bits 7:0 – I2CTXDATA[7:0] I2C3 Transmit Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 714
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.19 I2C3 Baud Rate Generator Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
I2C3BRG
0x4B8
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
I2CBRG[15:8]
R/W
R/W
0
0
4
3
I2CBRG[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – I2CBRG[15:0] I2C3 Baud Rate Generator bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 715
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.20 I2C3 Control Register Low
Name:
Offset:
I2C3CONL
0x4BA
Note:
1.
2.
Automatically cleared to ‘0’ at the beginning of Slave transmission; automatically cleared to ‘0’ at the end of
Slave reception. The user software must provide a delay between writing to the transmit buffer and setting the
SCLREL bit. This delay must be greater than the minimum setup time for Slave transmissions, as specified in
32. Electrical Characteristics.
Automatically cleared to ‘0’ at the beginning of Slave transmission.
3.
“SMBus 3.0 Specification” input level can be selected by the SMB3EN Configuration bit (FDEVOPT1[10]).
Legend: HC = Hardware Clearable bit
Bit
Access
Reset
Bit
Access
Reset
15
I2CEN
R/W
0
14
13
I2CSIDL
R/W
0
12
SCLREL
R/W
0
11
STRICT
R/W
0
10
A10M
R/W
0
9
DISSLW
R/W
0
8
SMEN
R/W
0
7
GCEN
R/W
0
6
STREN
R/W
0
5
ACKDT
R/W
0
4
ACKEN
HC/R/W
0
3
RCEN
HC/R/W
0
2
PEN
HC/R/W
0
1
RSEN
HC/R/W
0
0
SEN
HC/R/W
0
Bit 15 – I2CEN I2C3 Enable bit (writable from software only)
Value
Description
1
Enables the I2C3 module and configures the SDA and SCL pins as serial port pins
0
Disables the I2C3 module; all I2C pins are controlled by port functions
Bit 13 – I2CSIDL I2C3 Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bit 12 – SCLREL SCL Release Control bit (I2C Slave mode only)(1)
If STREN = 1:
Value
Description
1
0
Releases clock
Holds clock low (clock stretch); user may program this bit to ‘0’, clock stretch at next SCL low
If STREN = 0:(2)
Value
Description
1
0
Releases clock
Forces clock low (clock stretch)
Bit 11 – STRICT I2C3 Strict Reserved Address Rule Enable bit
Value
Description
1
Strict Reserved Addressing is enforced (for reserved addresses, refer to Table 16-1)
In Slave mode: The device does not respond to reserved address space and addresses falling in that
category are NACKed.
In Master mode: The device is allowed to generate addresses with reserved address space.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 716
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
Value
0
Description
Reserved Addressing would be Acknowledged
In Slave mode: The device will respond to an address falling in the reserved address space. When
there is a match with any of the reserved addresses, the device will generate an ACK.
In Master mode: Reserved.
Bit 10 – A10M 10-Bit Slave Address Flag bit
Value
Description
1
I2C3ADD is a 10-bit Slave address
0
I2C3ADD is a 7-bit Slave address
Bit 9 – DISSLW Slew Rate Control Disable bit
Value
Description
1
Slew rate control is disabled for Standard Speed mode (100 kHz, also disabled for 1 MHz mode)
0
Slew rate control is enabled for High-Speed mode (400 kHz)
Bit 8 – SMEN SMBus Input Levels Enable bit(3)
Value
Description
1
Enables input logic so thresholds are compliant with the SMBus specification
0
Disables SMBus-specific inputs
Bit 7 – GCEN General Call Enable bit (I2C Slave mode only)
Value
Description
1
Enables interrupt when a general call address is received in I2C2RSR; module is enabled for reception
0
General call address is disabled
Bit 6 – STREN SCL Clock Stretch Enable bit
In I2C Slave mode only; used in conjunction with the SCLREL bit.
Value
Description
1
Enables clock stretching
0
Disables clock stretching
Bit 5 – ACKDT Acknowledge Data bit
In I2C Master mode during Master Receive mode: The value that will be transmitted when the user initiates an
Acknowledge sequence at the end of a receive.
In I2C Slave mode when AHEN = 1 or DHEN = 1: The value that the Slave will transmit when it initiates an
Acknowledge sequence at the end of an address or data reception.
Value
Description
1
NACK is sent
0
ACK is sent
Bit 4 – ACKEN Acknowledge Sequence Enable bit
In I2C Master mode only; applicable during Master Receive mode.
Value
Description
1
Initiates Acknowledge sequence on SDA and SCL pins, and transmits the ACKDT data bit
0
Acknowledge sequence is Idle
Bit 3 – RCEN Receive Enable bit (I2C Master mode only)
Value
Description
1
Enables Receive mode for I2C; automatically cleared by hardware at the end of the 8-bit receive data
byte
0
Receive sequence is not in progress
Bit 2 – PEN Stop Condition Enable bit (I2C Master mode only)
Value
Description
1
Initiates Stop condition on the SDA and SCL pins
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 717
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
Value
0
Description
Stop condition is Idle
Bit 1 – RSEN Restart Condition Enable bit (I2C Master mode only)
Value
Description
1
Initiates Restart condition on the SDA and SCL pins
0
Restart condition is Idle
Bit 0 – SEN Start Condition Enable bit (I2C Master mode only)
Value
Description
1
Initiates Start condition on the SDA and SCL pins
0
Start condition is Idle
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 718
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.21 I2C3 Control Register High
Name:
Offset:
I2C3CONH
0x4BC
Note:
1.
Bit
This bit must be set to ‘0’ for 1 MHz operation.
15
14
13
12
11
10
9
8
7
6
PCIE
R/W
0
5
SCIE
R/W
0
4
BOEN
R/W
0
3
SDAHT
R/W
0
2
SBCDE
R/W
0
1
AHEN
R/W
0
0
DHEN
R/W
0
Access
Reset
Bit
Access
Reset
Bit 6 – PCIE Stop Condition Interrupt Enable bit (I2C Slave mode only)
Value
Description
1
Enables interrupt on detection of Stop condition
0
Stop detection interrupts are disabled
Bit 5 – SCIE Start Condition Interrupt Enable bit (I2C Slave mode only)
Value
Description
1
Enables interrupt on detection of Start or Restart conditions
0
Start detection interrupts are disabled
Bit 4 – BOEN Buffer Overwrite Enable bit (I2C Slave mode only)
Value
Description
1
I2C3RCV is updated and an ACK is generated for a received address/data byte, ignoring the state of
the I2COV bit only if RBF bit = 0
0
I2C3RCV is only updated when I2COV is clear
Bit 3 – SDAHT SDAx Hold Time Selection bit(1)
Value
Description
1
Minimum of 300 ns hold time on SDA after the falling edge of SCL
0
Minimum of 100 ns hold time on SDA after the falling edge of SCL
Bit 2 – SBCDE Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL bit is set and
the bus goes Idle. This Detection mode is only valid during data and ACK transmit sequences.
Value
Description
1
Enables Slave bus collision interrupts
0
Slave bus collision interrupts are disabled
Bit 1 – AHEN Address Hold Enable bit (I2C Slave mode only)
Value
Description
1
Following the 8th falling edge of SCL for a matching received address byte; SCLREL bit
(I2C3CONL[12]) will be cleared and SCL will be held low
0
Address holding is disabled
Bit 0 – DHEN Data Hold Enable bit (I2C Slave mode only)
Value
Description
1
Following the 8th falling edge of SCL for a received data byte; Slave hardware clears the SCLREL bit
(I2C3CONL[12]) and SCL is held low
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 719
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
Value
0
Description
Data holding is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 720
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.22 I2C3 Status Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
I2C3STAT
0x4BE
15
ACKSTAT
R/W
0
14
TRSTAT
R/W
0
13
ACKTIM
R/W
0
12
11
10
BCL
R/W
0
9
GCSTAT
R/W
0
8
ADD10
R/W
0
7
IWCOL
R/W
0
6
I2COV
R/W
0
5
D/A
R/W
0
4
P
R/W
0
3
S
R/W
0
2
R/W
R/W
0
1
RBF
R/W
0
0
TBF
R/W
0
Bit 15 – ACKSTAT Acknowledge Status bit (updated in all Master and Slave modes)
Value
Description
1
Acknowledge was not received from Slave
0
Acknowledge was received from Slave
Bit 14 – TRSTAT Transmit Status bit (when operating as I2C Master; applicable to Master transmit operation)
Value
Description
1
Master transmit is in progress (8 bits + ACK)
0
Master transmit is not in progress
Bit 13 – ACKTIM Acknowledge Time Status bit (valid in I2C Slave mode only)
Value
Description
1
Indicates I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCLx clock
0
Not an Acknowledge sequence, cleared on 9th rising edge of SCLx clock
Bit 10 – BCL Bus Collision Detect bit (Master/Slave mode; cleared when I2C module is disabled, I2CEN = 0)
Value
Description
1
A bus collision has been detected during a Master or Slave transmit operation
0
No bus collision has been detected
Bit 9 – GCSTAT General Call Status bit (cleared after Stop detection)
Value
Description
1
General call address was received
0
General call address was not received
Bit 8 – ADD10 10-Bit Address Status bit (cleared after Stop detection)
Value
Description
1
10-bit address was matched
0
10-bit address was not matched
Bit 7 – IWCOL I2C3 Write Collision Detect bit
Value
Description
1
An attempt to write to the I2C3TRN register failed because the I2C module is busy; must be cleared in
software
0
No collision
Bit 6 – I2COV I2C3 Receive Overflow Flag bit
Value
Description
1
A byte was received while the I2C3RCV register was still holding the previous byte; I2COV is a “don’t
care” in Transmit mode, must be cleared in software
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 721
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
Value
0
Description
No overflow
Bit 5 – D/A Data/Address bit (when operating as I2C Slave)
Value
Description
1
Indicates that the last byte received was data
0
Indicates that the last byte received or transmitted was an address
Bit 4 – P I2C3 Stop bit
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
Value
Description
1
Indicates that a Stop bit has been detected last
0
Stop bit was not detected last
Bit 3 – S I2C3 Start bit
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
Value
Description
1
Indicates that a Start (or Repeated Start) bit has been detected last
0
Start (or Repeated Start) bit was not detected last
Bit 2 – R/W Read/Write Information bit (when operating as I2C Slave)
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
Value
Description
1
Read: Indicates the data transfer is output from the Slave
0
Write: Indicates the data transfer is input to the Slave
Bit 1 – RBF Receive Buffer Full Status bit
Value
Description
1
Receive is complete, I2C3RCV is full
0
Receive is not complete, I2C3RCV is empty
Bit 0 – TBF Transmit Buffer Full Status bit
Value
Description
1
Transmit is in progress, I2C3TRN is full (eight bits of data)
0
Transmit is complete, I2C3TRN is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 722
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.23 I2C3 Address Register
Bit
Name:
Offset:
I2C3ADD
0x4C0
15
14
13
12
11
10
9
8
ADD[9:8]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ADD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – ADD[9:0] I2C3 Address bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 723
PIC24FJ512GU410 Family Data Sheet
Inter-Integrated Circuit (I2C)
16.4.24 I2C3 Slave Mode Address Mask Register
Name:
Offset:
Bit
15
I2C3MSK
0x4C2
14
13
12
11
10
9
8
MSK[9:8]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
MSK[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 9:0 – MSK[9:0] I2C3 Mask for Address bits
Value
Description
1
Enables masking for bit of the incoming message address; bit match is not required in this position
0
Disables masking for bit; bit match is required in this position
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 724
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.
Universal Asynchronous Receiver Transmitter (UART)
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information, refer to “Universal Asynchronous Receiver Transmitter
(UART)” (DS70000582) in the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
website (www.microchip.com). The information in this data sheet supersedes the information in the FRM.
The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the
PIC24F device family. The UART is a full-duplex, asynchronous system that can communicate with peripheral
devices, such as personal computers, LIN/J2602, RS-232 and RS-485 interfaces. The module also supports a
®
hardware flow control option with the UxCTS and UxRTS pins. The UART module includes an IrDA encoder/
decoder unit.
The PIC24FJ512GU410 family devices are equipped with six UART modules, referred to as UART1, UART2,
UART3, UART4, UART5 and UART6.
The primary features of the UARTx modules are:
•
•
•
•
•
•
•
•
•
•
•
Full-Duplex, 8 or 9-Bit Data Transmission through the UxTX and UxRX Pins
Even, Odd or No Parity Options (for 8-bit data)
One or Two Stop bits
Hardware Flow Control Option with the UxCTS and UxRTS Pins
Fully Integrated Baud Rate Generator with 16-Bit Prescaler
Baud Rates Range from Up to 1 Mbps and Down to 15 Hz at 16 MIPS in 16x mode
Baud Rates Range from Up to 4 Mbps and Down to 61 Hz at 16 MIPS in 4x mode
4-Deep, First-In First-Out (FIFO) Transmit Data Buffer
4-Deep FIFO Receive Data Buffer
Parity, Framing and Buffer Overrun Error Detection
Support for 9-Bit mode with Address Detect (9th bit = 1)
•
•
•
•
•
•
•
•
Separate Transmit and Receive Interrupts
Loopback mode for Diagnostic Support
Polarity Control for Transmit and Receive Lines
Support for Sync and Break Characters
Supports Automatic Baud Rate Detection
®
IrDA Encoder and Decoder Logic
Includes DMA Support
16x Baud Clock Output for IrDA Support
A simplified block diagram of the UARTx module is shown in Figure 17-1. The UARTx module consists of these key
important hardware elements:
•
•
•
Baud Rate Generator
Asynchronous Transmitter
Asynchronous Receiver
Note: Throughout this section, references to register and bit names that may be associated with a specific UART
module are referred to generically by the use of ‘x’ in place of the specific module number. Thus, “UxSTA” might refer
to the UART Status register for any UART module (from UART1 to UART6).
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 725
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Figure 17-1. UART Simplified Block Diagram
Baud Rate Generator
ISO 7816 Support
UxRX
UART Receiver
UxRTS
Hardware Flow Control
UxCTS
UxTX
UART Transmitter
IrDA®
BCLKx
Note: The UART inputs and outputs must all be assigned to available RPn/RPIn pins before use. See 11.4
Peripheral Pin Select (PPS) for more information.
17.1
UART Baud Rate Generator (BRG)
The UART module includes a dedicated, 16-bit Baud Rate Generator. The UxBRG register controls the period of a
free-running, 16-bit timer. Equation 17-1 shows the formula for computation of the baud rate when BRGH = 0.
Equation 17-1. UART Baud Rate with BRGH = 0(1)
FPB
16 • (UxBRG + 1)
Baud Rate =
UxBRG =
FPB
16 • Baud Rate
–1
Note:
1. FPB denotes the Peripheral Clock Frequency (FOSC/2).
Equation 17-2 shows the formula for computation of the baud rate when BRGH = 1.
Equation 17-2. UART Baud Rate with BRGH = 1(1)
Baud Rate =
UxBRG =
FPB
4 • (UxBRG + 1)
FPB
4 • Baud Rate
–1
Note:
1. FPB denotes the Peripheral Clock Frequency (FOSC/2).
Writing a new value to the UxBRG register causes the BRG timer to be reset (cleared). This ensures the BRG does
not wait for a timer overflow before generating the new baud rate.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 726
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.2
Transmitting in 8-Bit Data Mode
1.
2.
3.
4.
5.
6.
17.3
Transmitting in 9-Bit Data Mode
1.
2.
3.
4.
5.
17.4
Write appropriate baud rate value to the UxBRG register.
Enable the UART.
Set the UTXEN bit (causes a transmit interrupt, two cycles after being set).
Write a data byte to the lower byte of the UxTXREG word. The value will be immediately transferred to the
Transmit Shift Register (TSR) and the serial bit stream will start shifting out with the next rising edge of the
baud clock.
Alternatively, the data byte may be transferred while UTXEN = 0 and then the user may set UTXEN. This will
cause the serial bit stream to begin immediately because the baud clock will start from a cleared state.
A transmit interrupt will be generated as per interrupt control bits, UTXISEL[1:0].
Write appropriate baud rate value to the UxBRG register.
Enable the UART.
Set the UTXEN bit (causes a transmit interrupt).
Write UxTXREG as a 16-bit value only. A word write to UxTXREG triggers the transfer of the 9-bit data to the
TSR. The serial bit stream will start shifting out with the first rising edge of the baud clock.
A transmit interrupt will be generated as per the setting of control bits, UTXISELx.
Break and Sync Transmit Sequence
The following sequence will send a message frame header, made up of a Break, followed by an auto-baud Sync byte.
1.
2.
3.
4.
5.
17.5
Configure the UART for the desired mode.
Set UTXEN and UTXBRK to set up the Break character.
Load the UxTXREG with a dummy character to initiate transmission (value is ignored).
Write ‘55h’ to UxTXREG; this loads the Sync character into the transmit FIFO.
After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits.
Receiving in 8-Bit or 9-Bit Data Mode
1.
2.
3.
4.
5.
Write appropriate baud rate value to the UxBRG register.
Enable the UART by setting the URXEN bit (UxSTA[12]).
A receive interrupt will be generated when one or more data characters have been received as per interrupt
control bits, URXISEL[1:0].
Read the OERR bit to determine if an overrun error has occurred. The OERR bit must be reset in software.
Read UxRXREG.
The act of reading the UxRXREG character will move the next character to the top of the receive FIFO, including a
new set of PERR and FERR values.
17.6
Operation of UxCTS and UxRTS Control Pins
UARTx Clear-to-Send (UxCTS) and Request-to-Send (UxRTS) are the two hardware controlled pins that are
associated with the UARTx modules. These two pins allow the UARTx to operate in Simplex and Flow Control mode.
They are implemented to control the transmission and reception between the Data Terminal Equipment (DTE). The
UEN[1:0] bits in the UxMODE register configure these pins.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 727
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.7
Infrared Support
The UART module provides two types of infrared UART support: one is the IrDA clock output to support an external
IrDA encoder and decoder device (legacy module support), and the other is the full implementation of the IrDA
encoder and decoder. Note that because the IrDA modes require a 16x baud clock, they will only work when the
BRGH bit (UxMODE[3]) is ‘0’.
17.7.1
IrDA Clock Output for External IrDA Support
To support external IrDA encoder and decoder devices, the BCLKx pin (same as the UxRTS pin) can be configured
to generate the 16x baud clock. When UEN[1:0] = 11, the BCLKx pin will output the 16x baud clock if the UARTx
module is enabled; it can be used to support the IrDA codec chip.
17.7.2
Built-in IrDA Encoder and Decoder
The UARTx has full implementation of the IrDA encoder and decoder as part of the UARTx module. The built-in IrDA
encoder and decoder functionality is enabled using the IREN bit (UxMODE[12]). When enabled (IREN = 1), the
receive pin (UxRX) acts as the input from the infrared receiver. The transmit pin (UxTX) acts as the output to the
infrared transmitter.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 728
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8
UART Registers
Offset
Name
0x00
...
0x0397
Reserved
0x0398
U1MODE
0x039A
U1STA
0x039C
U1TXREG
0x039E
U1RXREG
0x03A0
U1BRG
0x03A2
...
0x03AD
Reserved
0x03AE
U2MODE
0x03B0
U2STA
0x03B2
U2TXREG
0x03B4
U2RXREG
0x03B6
U2BRG
0x03B8
...
0x03C3
Reserved
0x03C4
U3MODE
0x03C6
U3STA
0x03C8
U3TXREG
0x03CA
U3RXREG
0x03CC
U3BRG
0x03CE
...
0x03CF
Reserved
0x03D0
U4MODE
0x03D2
U4STA
0x03D4
U4TXREG
0x03D6
U4RXREG
0x03D8
U4BRG
0x03DA
...
0x03DB
Reserved
Bit Pos.
7
6
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
WAKE
LPBACK
UARTEN
URXISEL[1:0]
UTXISEL1
UTXINV
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
WAKE
LPBACK
UARTEN
URXISEL[1:0]
UTXISEL1
UTXINV
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
WAKE
LPBACK
UARTEN
URXISEL[1:0]
UTXISEL1
UTXINV
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
WAKE
LPBACK
UARTEN
URXISEL[1:0]
UTXISEL1
UTXINV
5
4
ABAUD
USIDL
ADDEN
UTXISEL0
3
URXINV
BRGH
IREN
RTSMD
RIDLE
PERR
URXEN
UTXBRK
U1TXREG[7:0]
2
1
0
PDSEL[1:0]
FERR
UTXEN
STSEL
UEN[1:0]
OERR
URXDA
UTXBF
TRMT
U1TXREG[8]
U1RXREG[7:0]
U1RXREG[8]
BRG[7:0]
BRG[15:8]
ABAUD
USIDL
ADDEN
UTXISEL0
URXINV
BRGH
IREN
RTSMD
RIDLE
PERR
URXEN
UTXBRK
U2TXREG[7:0]
PDSEL[1:0]
FERR
UTXEN
STSEL
UEN[1:0]
OERR
URXDA
UTXBF
TRMT
U2TXREG[8]
U2RXREG[7:0]
U2RXREG[8]
BRG[7:0]
BRG[15:8]
ABAUD
USIDL
ADDEN
UTXISEL0
URXINV
BRGH
IREN
RTSMD
RIDLE
PERR
URXEN
UTXBRK
U3TXREG[7:0]
PDSEL[1:0]
FERR
UTXEN
STSEL
UEN[1:0]
OERR
URXDA
UTXBF
TRMT
U3TXREG[8]
U3RXREG[7:0]
U3RXREG[8]
BRG[7:0]
BRG[15:8]
© 2019-2020 Microchip Technology Inc.
ABAUD
USIDL
ADDEN
UTXISEL0
URXINV
BRGH
IREN
RTSMD
RIDLE
PERR
URXEN
UTXBRK
U4TXREG[7:0]
PDSEL[1:0]
FERR
UTXEN
STSEL
UEN[1:0]
OERR
URXDA
UTXBF
TRMT
U4TXREG[8]
U4RXREG[7:0]
U4RXREG[8]
BRG[7:0]
BRG[15:8]
Datasheet
DS30010203C-page 729
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
...........continued
Offset
Name
Bit Pos.
7
6
5
4
3
0x03DC
U5MODE
7:0
15:8
WAKE
UARTEN
LPBACK
ABAUD
USIDL
URXINV
IREN
BRGH
RTSMD
0x03DE
U5STA
0x03E0
U5TXREG
0x03E2
U5RXREG
0x03E4
U5BRG
0x03E6
...
0x03E7
Reserved
0x03E8
U6MODE
0x03EA
U6STA
0x03EC
U6TXREG
0x03EE
U6RXREG
0x03F0
U6BRG
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
URXISEL[1:0]
UTXISEL1
UTXINV
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
WAKE
LPBACK
UARTEN
URXISEL[1:0]
UTXISEL1
UTXINV
ADDEN
UTXISEL0
RIDLE
PERR
URXEN
UTXBRK
U5TXREG[7:0]
2
1
PDSEL[1:0]
FERR
UTXEN
0
STSEL
UEN[1:0]
OERR
UTXBF
URXDA
TRMT
U5TXREG[8]
U5RXREG[7:0]
U5RXREG[8]
BRG[7:0]
BRG[15:8]
© 2019-2020 Microchip Technology Inc.
ABAUD
USIDL
ADDEN
UTXISEL0
URXINV
BRGH
IREN
RTSMD
RIDLE
PERR
URXEN
UTXBRK
U6TXREG[7:0]
PDSEL[1:0]
FERR
UTXEN
STSEL
UEN[1:0]
OERR
URXDA
UTXBF
TRMT
U6TXREG[8]
U6RXREG[7:0]
U6RXREG[8]
BRG[7:0]
BRG[15:8]
Datasheet
DS30010203C-page 730
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.1
UART1 Mode Register
Name:
Offset:
U1MODE
0x398
Note:
1.
2.
Bit
Access
Reset
Bit
Access
Reset
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more
information, see 11.4 Peripheral Pin Select (PPS).
This feature is only available for the 16x BRG mode (BRGH = 0).
15
UARTEN
R/W
0
14
7
WAKE
R/W
0
6
LPBACK
R/W
0
13
USIDL
R/W
0
12
IREN
R/W
0
11
RTSMD
R/W
0
10
5
ABAUD
R/W
0
4
URXINV
R/W
0
3
BRGH
R/W
0
2
9
8
UEN[1:0]
R/W
0
R/W
0
1
0
STSEL
R/W
0
PDSEL[1:0]
R/W
0
R/W
0
Bit 15 – UARTEN UART Enable bit(1)
Value
Description
1
UART is enabled; all UART pins are controlled by UART as defined by UEN[1:0]
0
UART is disabled; all UART pins are controlled by port latches, UART power consumption is minimal
Bit 13 – USIDL UART Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
®
Bit 12 – IREN IrDA Encoder and Decoder Enable bit(2)
Value
Description
1
IrDA encoder and decoder are enabled
0
IrDA encoder and decoder are disabled
Bit 11 – RTSMD Mode Selection for U1RTS Pin bit
Value
Description
1
U1RTS pin is in Simplex mode
0
U1RTS pin is in Flow Control mode
Bits 9:8 – UEN[1:0] UART Enable bits
Value
Description
11
U1TX, U1RX and BCLK1 pins are enabled and used; U1CTS pin is controlled by port latches
10
U1TX, U1RX, U1CTS and U1RTS pins are enabled and used
01
U1TX, U1RX and U1RTS pins are enabled and used; U1CTS pin is controlled by port latches
00
U1TX and U1RX pins are enabled and used; U1CTS and U1RTS/BCLK1 pins are controlled by port
latches
Bit 7 – WAKE Wake-up on Start Bit Detect During Sleep Mode Enable bit
Value
Description
1
UART continues to sample the U1RX pin; interrupt is generated on the falling edge, bit is cleared in
hardware on the following rising edge
0
No wake-up is enabled
Bit 6 – LPBACK UART Loopback Mode Select bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 731
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Value
1
0
Description
Enables Loopback mode
Loopback mode is disabled
Bit 5 – ABAUD Auto-Baud Enable bit
Value
Description
1
Enables baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0
Baud rate measurement is disabled or completed
Bit 4 – URXINV UART Receive Polarity Inversion bit
Value
Description
1
U1RX Idle state is ‘0’
0
U1RX Idle state is ‘1’
Bit 3 – BRGH High Baud Rate Enable bit
Value
Description
1
High-Speed mode (4 BRG clock cycles per bit)
0
Standard Speed mode (16 BRG clock cycles per bit)
Bits 2:1 – PDSEL[1:0] Parity and Data Selection bits
Value
Description
11
9-bit data, no parity
10
8-bit data, odd parity
01
8-bit data, even parity
00
8-bit data, no parity
Bit 0 – STSEL Stop Bit Selection bit
Value
Description
1
Two Stop bits
0
One Stop bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 732
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.2
UART1 Status and Control Register
Name:
Offset:
U1STA
0x39A
C = Clearable bit; HSC = Hardware Settable/Clearable bit
Note:
®
1.
The value of this bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
2.
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more
information, see 11.4 Peripheral Pin Select (PPS).
Legend: C = Clearable bit; HC = Hardware Clearable bit; HS = Hardware Settable bit; HSC = Hardware Settable/
Clearable bit
Bit
15
UTXISEL1
R/W
0
Access
Reset
Bit
14
UTXINV
R/W
0
13
UTXISEL0
R/W
0
12
URXEN
R/W
0
11
UTXBRK
HC/R/W
0
10
UTXEN
R/W
0
9
UTXBF
HSC/R
0
8
TRMT
HSC/R
1
5
ADDEN
R/W
0
4
RIDLE
HSC/R
1
3
PERR
HSC/R
0
2
FERR
HSC/R
0
1
OERR
HS/R/C
0
0
URXDA
HSC/R
0
7
6
URXISEL[1:0]
R/W
R/W
0
0
Access
Reset
Bit 15 – UTXISEL1 UART Transmission Interrupt Mode Selection bit
Value of
UTXISEL[1:0]
Description
11
10
Reserved; do not use
Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
01
00
®
Bit 14 – UTXINV UART IrDA Encoder Transmit Polarity Inversion bit(1)
IREN = 1:
Value
Description
1
0
U1TX Idle state is ‘1’
U1TX Idle state is ‘0’
IREN = 0:
Value
Description
1
0
U1TX Idle state is ‘0’
U1TX Idle state is ‘1’
Bit 13 – UTXISEL0 UART Transmission Interrupt Mode Selection bit
See description of bit 15 – UTXISEL1.
Bit 12 – URXEN UART Receive Enable bit
Value
Description
1
Receive is enabled, U1RX pin is controlled by UART
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 733
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Value
0
Description
Receive is disabled, U1RX pin is controlled by the port
Bit 11 – UTXBRK UART Transmit Break bit
Value
Description
1
Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0
Sync Break transmission is disabled or completed
Bit 10 – UTXEN UART Transmit Enable bit(2)
Value
Description
1
Transmit is enabled, U1TX pin is controlled by UART
0
Transmit is disabled, any pending transmission is aborted and the buffer is reset; U1TX pin is
controlled by the port
Bit 9 – UTXBF UART Transmit Buffer Full Status bit (read-only)
Value
Description
1
Transmit buffer is full
0
Transmit buffer is not full, at least one more character can be written
Bit 8 – TRMT Transmit Shift Register Empty bit (read-only)
Value
Description
1
Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0
Transmit Shift Register is not empty, a transmission is in progress or queued
Bits 7:6 – URXISEL[1:0] UART Receive Interrupt Mode Selection bits
Value
Description
11
Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has four data characters)
10
Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has three data characters)
0x
Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters
Bit 5 – ADDEN Address Character Detect bit (bit 8 of received data = 1)
Value
Description
1
Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect)
0
Address Detect mode is disabled
Bit 4 – RIDLE Receiver Idle bit (read-only)
Value
Description
1
Receiver is Idle
0
Receiver is active
Bit 3 – PERR Parity Error Status bit (read-only)
Value
Description
1
Parity error has been detected for the current character (the character at the top of the receive FIFO)
0
Parity error has not been detected
Bit 2 – FERR Framing Error Status bit (read-only)
Value
Description
1
Framing error has been detected for the current character (the character at the top of the receive FIFO)
0
Framing error has not been detected
Bit 1 – OERR Receive Buffer Overrun Error Status bit (clear/read-only)
Value
Description
1
Receive buffer has overflowed
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 734
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Value
0
Description
Receive buffer has not overflowed (clearing a previously set OERR bit (‘1’ to ‘0’ transition) will reset the
receive buffer and the RSR to the empty state)
Bit 0 – URXDA UART Receive Buffer Data Available bit (read-only)
Value
Description
1
Receive buffer has data, at least one more character can be read
0
Receive buffer is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 735
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.3
UART1 Transmit Register (Normally Write-Only)
Name:
Offset:
Bit
U1TXREG
0x39C
15
14
13
12
11
10
9
8
U1TXREG[8]
W
0
Bit
7
6
5
4
3
U1TXREG[7:0]
W
W
0
0
2
1
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
x
Access
Reset
Bits 8:0 – U1TXREG[8:0] UART1 Transmission Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 736
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.4
UART1 Receive Register (Normally Read-Only)
Name:
Offset:
Bit
U1RXREG
0x39E
15
14
13
12
11
10
9
8
U1RXREG[8]
R
0
Bit
7
6
5
2
1
0
Access
Reset
R
0
R
0
R
0
4
3
U1RXREG[7:0]
R
R
0
0
R
0
R
0
R
0
Access
Reset
Bits 8:0 – U1RXREG[8:0] UART1 Receive Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 737
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.5
UART1 Baud Rate Generator Register
Name:
Offset:
Bit
15
U1BRG
0x3A0
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BRG[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BRG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BRG[15:0] UART1 Baud Rate Divisor bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 738
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.6
UART2 Mode Register
Name:
Offset:
U2MODE
0x3AE
Note:
1.
2.
Bit
Access
Reset
Bit
Access
Reset
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more
information, see 11.4 Peripheral Pin Select (PPS).
This feature is only available for the 16x BRG mode (BRGH = 0).
15
UARTEN
R/W
0
14
7
WAKE
R/W
0
6
LPBACK
R/W
0
13
USIDL
R/W
0
12
IREN
R/W
0
11
RTSMD
R/W
0
10
5
ABAUD
R/W
0
4
URXINV
R/W
0
3
BRGH
R/W
0
2
9
8
UEN[1:0]
R/W
0
R/W
0
1
0
STSEL
R/W
0
PDSEL[1:0]
R/W
0
R/W
0
Bit 15 – UARTEN UART Enable bit(1)
Value
Description
1
UART is enabled; all UART pins are controlled by UART as defined by UEN[1:0]
0
UART is disabled; all UART pins are controlled by port latches, UART power consumption is minimal
Bit 13 – USIDL UART Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
®
Bit 12 – IREN IrDA Encoder and Decoder Enable bit(2)
Value
Description
1
IrDA encoder and decoder are enabled
0
IrDA encoder and decoder are disabled
Bit 11 – RTSMD Mode Selection for U2RTS Pin bit
Value
Description
1
U2RTS pin is in Simplex mode
0
U2RTS pin is in Flow Control mode
Bits 9:8 – UEN[1:0] UART Enable bits
Value
Description
11
U2TX, U2RX and BCLK2 pins are enabled and used; U2CTS pin is controlled by port latches
10
U2TX, U2RX, U2CTS and U2RTS pins are enabled and used
01
U2TX, U2RX and U2RTS pins are enabled and used; U2CTS pin is controlled by port latches
00
U2TX and U2RX pins are enabled and used; U2CTS and U2RTS/BCLK2 pins are controlled by port
latches
Bit 7 – WAKE Wake-up on Start Bit Detect During Sleep Mode Enable bit
Value
Description
1
UART continues to sample the U2RX pin; interrupt is generated on the falling edge, bit is cleared in
hardware on the following rising edge
0
No wake-up is enabled
Bit 6 – LPBACK UART Loopback Mode Select bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 739
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Value
1
0
Description
Enables Loopback mode
Loopback mode is disabled
Bit 5 – ABAUD Auto-Baud Enable bit
Value
Description
1
Enables baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0
Baud rate measurement is disabled or completed
Bit 4 – URXINV UART Receive Polarity Inversion bit
Value
Description
1
U2RX Idle state is ‘0’
0
U2RX Idle state is ‘1’
Bit 3 – BRGH High Baud Rate Enable bit
Value
Description
1
High-Speed mode (4 BRG clock cycles per bit)
0
Standard Speed mode (16 BRG clock cycles per bit)
Bits 2:1 – PDSEL[1:0] Parity and Data Selection bits
Value
Description
11
9-bit data, no parity
10
8-bit data, odd parity
01
8-bit data, even parity
00
8-bit data, no parity
Bit 0 – STSEL Stop Bit Selection bit
Value
Description
1
Two Stop bits
0
One Stop bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 740
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.7
UART2 Status and Control Register
Name:
Offset:
U2STA
0x3B0
Note:
®
1.
The value of this bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
2.
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more
information, see 11.4 Peripheral Pin Select (PPS).
Legend: C = Clearable bit; HC = Hardware Clearable bit; HS = Hardware Settable bit; HSC = Hardware Settable/
Clearable bit
Bit
15
UTXISEL1
R/W
0
Access
Reset
Bit
14
UTXINV
R/W
0
13
UTXISEL0
R/W
0
12
URXEN
R/W
0
11
UTXBRK
HC/R/W
0
10
UTXEN
R/W
0
9
UTXBF
HSC/R
0
8
TRMT
HSC/R
1
5
ADDEN
R/W
0
4
RIDLE
HSC/R
1
3
PERR
HSC/R
0
2
FERR
HSC/R
0
1
OERR
HS/R/C
0
0
URXDA
HSC/R
0
7
6
URXISEL[1:0]
R/W
R/W
0
0
Access
Reset
Bit 15 – UTXISEL1 UART Transmission Interrupt Mode Selection bit
Value of
UTXISEL[1:0]
Description
11
10
Reserved; do not use
Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
01
00
®
Bit 14 – UTXINV UART IrDA Encoder Transmit Polarity Inversion bit(1)
IREN = 1:
Value
Description
1
0
U2TX Idle state is ‘1’
U2TX Idle state is ‘0’
IREN = 0:
Value
Description
1
0
U2TX Idle state is ‘0’
U2TX Idle state is ‘1’
Bit 13 – UTXISEL0 UART Transmission Interrupt Mode Selection bit
See description of bit 15 – UTXISEL1.
Bit 12 – URXEN UART Receive Enable bit
Value
Description
1
Receive is enabled, U2RX pin is controlled by UART
0
Receive is disabled, U2RX pin is controlled by the port
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 741
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Bit 11 – UTXBRK UART Transmit Break bit
Value
Description
1
Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0
Sync Break transmission is disabled or completed
Bit 10 – UTXEN UART Transmit Enable bit(2)
Value
Description
1
Transmit is enabled, U2TX pin is controlled by UART
0
Transmit is disabled, any pending transmission is aborted and the buffer is reset; U2TX pin is
controlled by the port
Bit 9 – UTXBF UART Transmit Buffer Full Status bit (read-only)
Value
Description
1
Transmit buffer is full
0
Transmit buffer is not full, at least one more character can be written
Bit 8 – TRMT Transmit Shift Register Empty bit (read-only)
Value
Description
1
Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0
Transmit Shift Register is not empty, a transmission is in progress or queued
Bits 7:6 – URXISEL[1:0] UART Receive Interrupt Mode Selection bits
Value
Description
11
Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has four data characters)
10
Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has three data characters)
0x
Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters
Bit 5 – ADDEN Address Character Detect bit (bit 8 of received data = 1)
Value
Description
1
Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect)
0
Address Detect mode is disabled
Bit 4 – RIDLE Receiver Idle bit (read-only)
Value
Description
1
Receiver is Idle
0
Receiver is active
Bit 3 – PERR Parity Error Status bit (read-only)
Value
Description
1
Parity error has been detected for the current character (the character at the top of the receive FIFO)
0
Parity error has not been detected
Bit 2 – FERR Framing Error Status bit (read-only)
Value
Description
1
Framing error has been detected for the current character (the character at the top of the receive FIFO)
0
Framing error has not been detected
Bit 1 – OERR Receive Buffer Overrun Error Status bit (clear/read-only)
Value
Description
1
Receive buffer has overflowed
0
Receive buffer has not overflowed (clearing a previously set OERR bit (‘1’ to ‘0’ transition) will reset the
receive buffer and the RSR to the empty state)
Bit 0 – URXDA UART Receive Buffer Data Available bit (read-only)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 742
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Value
1
0
Description
Receive buffer has data, at least one more character can be read
Receive buffer is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 743
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.8
UART2 Transmit Register (Normally Write-Only)
Name:
Offset:
Bit
U2TXREG
0x3B2
15
14
13
12
11
10
9
8
U2TXREG[8]
W
0
Bit
7
6
5
4
3
U2TXREG[7:0]
W
W
0
0
2
1
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
x
Access
Reset
Bits 8:0 – U2TXREG[8:0] UART2 Transmission Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 744
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.9
UART2 Receive Register (Normally Read-Only)
Name:
Offset:
Bit
U2RXREG
0x3B4
15
14
13
12
11
10
9
8
U2RXREG[8]
R
0
Bit
7
6
5
2
1
0
Access
Reset
R
0
R
0
R
0
4
3
U2RXREG[7:0]
R
R
0
0
R
0
R
0
R
0
Access
Reset
Bits 8:0 – U2RXREG[8:0] UART2 Receive Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 745
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.10 UART2 Baud Rate Generator Register
Name:
Offset:
Bit
15
U2BRG
0x3B6
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BRG[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BRG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BRG[15:0] UART2 Baud Rate Divisor bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 746
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.11 UART3 Mode Register
Name:
Offset:
U3MODE
0x3C4
Note:
1.
2.
Bit
Access
Reset
Bit
Access
Reset
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more
information, see 11.4 Peripheral Pin Select (PPS).
This feature is only available for the 16x BRG mode (BRGH = 0).
15
UARTEN
R/W
0
14
7
WAKE
R/W
0
6
LPBACK
R/W
0
13
USIDL
R/W
0
12
IREN
R/W
0
11
RTSMD
R/W
0
10
5
ABAUD
R/W
0
4
URXINV
R/W
0
3
BRGH
R/W
0
2
9
8
UEN[1:0]
R/W
0
R/W
0
1
0
STSEL
R/W
0
PDSEL[1:0]
R/W
0
R/W
0
Bit 15 – UARTEN UART Enable bit(1)
Value
Description
1
UART is enabled; all UART pins are controlled by UART as defined by UEN[1:0]
0
UART is disabled; all UART pins are controlled by port latches, UART power consumption is minimal
Bit 13 – USIDL UART Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
®
Bit 12 – IREN IrDA Encoder and Decoder Enable bit(2)
Value
Description
1
IrDA encoder and decoder are enabled
0
IrDA encoder and decoder are disabled
Bit 11 – RTSMD Mode Selection for U3RTS Pin bit
Value
Description
1
U3RTS pin is in Simplex mode
0
U3RTS pin is in Flow Control mode
Bits 9:8 – UEN[1:0] UART Enable bits
Value
Description
11
U3TX, U3RX and BCLK3 pins are enabled and used; U3CTS pin is controlled by port latches
10
U3TX, U3RX, U3CTS and U3RTS pins are enabled and used
01
U3TX, U3RX and U3RTS pins are enabled and used; U3CTS pin is controlled by port latches
00
U3TX and U3RX pins are enabled and used; U3CTS and U3RTS/BCLK3 pins are controlled by port
latches
Bit 7 – WAKE Wake-up on Start Bit Detect During Sleep Mode Enable bit
Value
Description
1
UART continues to sample the U3RX pin; interrupt is generated on the falling edge, bit is cleared in
hardware on the following rising edge
0
No wake-up is enabled
Bit 6 – LPBACK UART Loopback Mode Select bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 747
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Value
1
0
Description
Enables Loopback mode
Loopback mode is disabled
Bit 5 – ABAUD Auto-Baud Enable bit
Value
Description
1
Enables baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0
Baud rate measurement is disabled or completed
Bit 4 – URXINV UART Receive Polarity Inversion bit
Value
Description
1
U3RX Idle state is ‘0’
0
U3RX Idle state is ‘1’
Bit 3 – BRGH High Baud Rate Enable bit
Value
Description
1
High-Speed mode (4 BRG clock cycles per bit)
0
Standard Speed mode (16 BRG clock cycles per bit)
Bits 2:1 – PDSEL[1:0] Parity and Data Selection bits
Value
Description
11
9-bit data, no parity
10
8-bit data, odd parity
01
8-bit data, even parity
00
8-bit data, no parity
Bit 0 – STSEL Stop Bit Selection bit
Value
Description
1
Two Stop bits
0
One Stop bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 748
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.12 UART3 Status and Control Register
Name:
Offset:
U3STA
0x3C6
Note:
®
1.
The value of this bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
2.
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more
information, see 11.4 Peripheral Pin Select (PPS).
Legend: C = Clearable bit; HC = Hardware Clearable bit; HS = Hardware Settable bit; HSC = Hardware Settable/
Clearable bit
Bit
15
UTXISEL1
R/W
0
Access
Reset
Bit
14
UTXINV
R/W
0
13
UTXISEL0
R/W
0
12
URXEN
R/W
0
11
UTXBRK
HC/R/W
0
10
UTXEN
R/W
0
9
UTXBF
HSC/R
0
8
TRMT
HSC/R
1
5
ADDEN
R/W
0
4
RIDLE
HSC/R
1
3
PERR
HSC/R
0
2
FERR
HSC/R
0
1
OERR
HS/R/C
0
0
URXDA
HSC/R
0
7
6
URXISEL[1:0]
R/W
R/W
0
0
Access
Reset
Bit 15 – UTXISEL1 UART Transmission Interrupt Mode Selection bit
Value of
UTXISEL[1:0]
Description
11
10
Reserved; do not use
Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
01
00
®
Bit 14 – UTXINV UART IrDA Encoder Transmit Polarity Inversion bit(1)
IREN = 1:
Value
Description
1
0
U3TX Idle state is ‘1’
U3TX Idle state is ‘0’
IREN = 0:
Value
Description
1
0
U3TX Idle state is ‘0’
U3TX Idle state is ‘1’
Bit 13 – UTXISEL0 UART Transmission Interrupt Mode Selection bit
See description of bit 15 – UTXISEL1.
Bit 12 – URXEN UART Receive Enable bit
Value
Description
1
Receive is enabled, U3RX pin is controlled by UART
0
Receive is disabled, U3RX pin is controlled by the port
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 749
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Bit 11 – UTXBRK UART Transmit Break bit
Value
Description
1
Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0
Sync Break transmission is disabled or completed
Bit 10 – UTXEN UART Transmit Enable bit(2)
Value
Description
1
Transmit is enabled, U3TX pin is controlled by UART
0
Transmit is disabled, any pending transmission is aborted and the buffer is reset; U3TX pin is
controlled by the port
Bit 9 – UTXBF UART Transmit Buffer Full Status bit (read-only)
Value
Description
1
Transmit buffer is full
0
Transmit buffer is not full, at least one more character can be written
Bit 8 – TRMT Transmit Shift Register Empty bit (read-only)
Value
Description
1
Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0
Transmit Shift Register is not empty, a transmission is in progress or queued
Bits 7:6 – URXISEL[1:0] UART Receive Interrupt Mode Selection bits
Value
Description
11
Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has four data characters)
10
Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has three data characters)
0x
Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters
Bit 5 – ADDEN Address Character Detect bit (bit 8 of received data = 1)
Value
Description
1
Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect)
0
Address Detect mode is disabled
Bit 4 – RIDLE Receiver Idle bit (read-only)
Value
Description
1
Receiver is Idle
0
Receiver is active
Bit 3 – PERR Parity Error Status bit (read-only)
Value
Description
1
Parity error has been detected for the current character (the character at the top of the receive FIFO)
0
Parity error has not been detected
Bit 2 – FERR Framing Error Status bit (read-only)
Value
Description
1
Framing error has been detected for the current character (the character at the top of the receive FIFO)
0
Framing error has not been detected
Bit 1 – OERR Receive Buffer Overrun Error Status bit (clear/read-only)
Value
Description
1
Receive buffer has overflowed
0
Receive buffer has not overflowed (clearing a previously set OERR bit (‘1’ to ‘0’ transition) will reset the
receive buffer and the RSR to the empty state)
Bit 0 – URXDA UART Receive Buffer Data Available bit (read-only)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 750
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Value
1
0
Description
Receive buffer has data, at least one more character can be read
Receive buffer is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 751
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.13 UART3 Transmit Register (Normally Write-Only)
Name:
Offset:
Bit
U3TXREG
0x3C8
15
14
13
12
11
10
9
8
U3TXREG[8]
W
0
Bit
7
6
5
4
3
U3TXREG[7:0]
W
W
0
0
2
1
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
x
Access
Reset
Bits 8:0 – U3TXREG[8:0] UART3 Transmission Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 752
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.14 UART3 Receive Register (Normally Read-Only)
Name:
Offset:
Bit
U3RXREG
0x3CA
15
14
13
12
11
10
9
8
U3RXREG[8]
R
0
Bit
7
6
5
2
1
0
Access
Reset
R
0
R
0
R
0
4
3
U3RXREG[7:0]
R
R
0
0
R
0
R
0
R
0
Access
Reset
Bits 8:0 – U3RXREG[8:0] UART3 Receive Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 753
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.15 UART3 Baud Rate Generator Register
Name:
Offset:
Bit
15
U3BRG
0x3CC
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BRG[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BRG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BRG[15:0] UART3 Baud Rate Divisor bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 754
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.16 UART4 Mode Register
Name:
Offset:
U4MODE
0x3D0
Note:
1.
2.
Bit
Access
Reset
Bit
Access
Reset
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more
information, see 11.4 Peripheral Pin Select (PPS).
This feature is only available for the 16x BRG mode (BRGH = 0).
15
UARTEN
R/W
0
14
7
WAKE
R/W
0
6
LPBACK
R/W
0
13
USIDL
R/W
0
12
IREN
R/W
0
11
RTSMD
R/W
0
10
5
ABAUD
R/W
0
4
URXINV
R/W
0
3
BRGH
R/W
0
2
9
8
UEN[1:0]
R/W
0
R/W
0
1
0
STSEL
R/W
0
PDSEL[1:0]
R/W
0
R/W
0
Bit 15 – UARTEN UART Enable bit(1)
Value
Description
1
UART is enabled; all UART pins are controlled by UART as defined by UEN[1:0]
0
UART is disabled; all UART pins are controlled by port latches, UART power consumption is minimal
Bit 13 – USIDL UART Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
®
Bit 12 – IREN IrDA Encoder and Decoder Enable bit(2)
Value
Description
1
IrDA encoder and decoder are enabled
0
IrDA encoder and decoder are disabled
Bit 11 – RTSMD Mode Selection for U4RTS Pin bit
Value
Description
1
U4RTS pin is in Simplex mode
0
U4RTS pin is in Flow Control mode
Bits 9:8 – UEN[1:0] UART Enable bits
Value
Description
11
U4TX, U4RX and BCLK4 pins are enabled and used; U4CTS pin is controlled by port latches
10
U4TX, U4RX, U4CTS and U4RTS pins are enabled and used
01
U4TX, U4RX and U4RTS pins are enabled and used; U4CTS pin is controlled by port latches
00
U4TX and U4RX pins are enabled and used; U4CTS and U4RTS/BCLK4 pins are controlled by port
latches
Bit 7 – WAKE Wake-up on Start Bit Detect During Sleep Mode Enable bit
Value
Description
1
UART continues to sample the U4RX pin; interrupt is generated on the falling edge, bit is cleared in
hardware on the following rising edge
0
No wake-up is enabled
Bit 6 – LPBACK UART Loopback Mode Select bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 755
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Value
1
0
Description
Enables Loopback mode
Loopback mode is disabled
Bit 5 – ABAUD Auto-Baud Enable bit
Value
Description
1
Enables baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0
Baud rate measurement is disabled or completed
Bit 4 – URXINV UART Receive Polarity Inversion bit
Value
Description
1
U4RX Idle state is ‘0’
0
U4RX Idle state is ‘1’
Bit 3 – BRGH High Baud Rate Enable bit
Value
Description
1
High-Speed mode (4 BRG clock cycles per bit)
0
Standard Speed mode (16 BRG clock cycles per bit)
Bits 2:1 – PDSEL[1:0] Parity and Data Selection bits
Value
Description
11
9-bit data, no parity
10
8-bit data, odd parity
01
8-bit data, even parity
00
8-bit data, no parity
Bit 0 – STSEL Stop Bit Selection bit
Value
Description
1
Two Stop bits
0
One Stop bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 756
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.17 UART4 Status and Control Register
Name:
Offset:
U4STA
0x3D2
Note:
®
1.
The value of this bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
2.
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more
information, see 11.4 Peripheral Pin Select (PPS).
Legend: C = Clearable bit; HC = Hardware Clearable bit; HS = Hardware Settable bit; HSC = Hardware Settable/
Clearable bit
Bit
15
UTXISEL1
R/W
0
Access
Reset
Bit
14
UTXINV
R/W
0
13
UTXISEL0
R/W
0
12
URXEN
R/W
0
11
UTXBRK
HC/R/W
0
10
UTXEN
R/W
0
9
UTXBF
HSC/R
0
8
TRMT
HSC/R
1
5
ADDEN
R/W
0
4
RIDLE
HSC/R
1
3
PERR
HSC/R
0
2
FERR
HSC/R
0
1
OERR
HS/R/C
0
0
URXDA
HSC/R
0
7
6
URXISEL[1:0]
R/W
R/W
0
0
Access
Reset
Bit 15 – UTXISEL1 UART Transmission Interrupt Mode Selection bit
Value of
UTXISEL[1:0]
Description
11
10
Reserved; do not use
Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
01
00
®
Bit 14 – UTXINV UART IrDA Encoder Transmit Polarity Inversion bit(1)
IREN = 1:
Value
Description
1
0
U4TX Idle state is ‘1’
U4TX Idle state is ‘0’
IREN = 0:
Value
Description
1
0
U4TX Idle state is ‘0’
U4TX Idle state is ‘1’
Bit 13 – UTXISEL0 UART Transmission Interrupt Mode Selection bit
See description of bit 15 – UTXISEL1.
Bit 12 – URXEN UART Receive Enable bit
Value
Description
1
Receive is enabled, U4RX pin is controlled by UART
0
Receive is disabled, U4RX pin is controlled by the port
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 757
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Bit 11 – UTXBRK UART Transmit Break bit
Value
Description
1
Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0
Sync Break transmission is disabled or completed
Bit 10 – UTXEN UART Transmit Enable bit(2)
Value
Description
1
Transmit is enabled, U4TX pin is controlled by UART
0
Transmit is disabled, any pending transmission is aborted and the buffer is reset; U4TX pin is
controlled by the port
Bit 9 – UTXBF UART Transmit Buffer Full Status bit (read-only)
Value
Description
1
Transmit buffer is full
0
Transmit buffer is not full, at least one more character can be written
Bit 8 – TRMT Transmit Shift Register Empty bit (read-only)
Value
Description
1
Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0
Transmit Shift Register is not empty, a transmission is in progress or queued
Bits 7:6 – URXISEL[1:0] UART Receive Interrupt Mode Selection bits
Value
Description
11
Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has four data characters)
10
Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has three data characters)
0x
Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters
Bit 5 – ADDEN Address Character Detect bit (bit 8 of received data = 1)
Value
Description
1
Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect)
0
Address Detect mode is disabled
Bit 4 – RIDLE Receiver Idle bit (read-only)
Value
Description
1
Receiver is Idle
0
Receiver is active
Bit 3 – PERR Parity Error Status bit (read-only)
Value
Description
1
Parity error has been detected for the current character (the character at the top of the receive FIFO)
0
Parity error has not been detected
Bit 2 – FERR Framing Error Status bit (read-only)
Value
Description
1
Framing error has been detected for the current character (the character at the top of the receive FIFO)
0
Framing error has not been detected
Bit 1 – OERR Receive Buffer Overrun Error Status bit (clear/read-only)
Value
Description
1
Receive buffer has overflowed
0
Receive buffer has not overflowed (clearing a previously set OERR bit (‘1’ to ‘0’ transition) will reset the
receive buffer and the RSR to the empty state)
Bit 0 – URXDA UART Receive Buffer Data Available bit (read-only)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 758
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Value
1
0
Description
Receive buffer has data, at least one more character can be read
Receive buffer is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 759
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.18 UART4 Transmit Register (Normally Write-Only)
Name:
Offset:
Bit
U4TXREG
0x3D4
15
14
13
12
11
10
9
8
U4TXREG[8]
W
0
Bit
7
6
5
4
3
U4TXREG[7:0]
W
W
0
0
2
1
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
x
Access
Reset
Bits 8:0 – U4TXREG[8:0] UART4 Transmission Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 760
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.19 UART4 Receive Register (Normally Read-Only)
Name:
Offset:
Bit
U4RXREG
0x3D6
15
14
13
12
11
10
9
8
U4RXREG[8]
R
0
Bit
7
6
5
2
1
0
Access
Reset
R
0
R
0
R
0
4
3
U4RXREG[7:0]
R
R
0
0
R
0
R
0
R
0
Access
Reset
Bits 8:0 – U4RXREG[8:0] UART4 Receive Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 761
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.20 UART4 Baud Rate Generator Register
Name:
Offset:
Bit
15
U4BRG
0x3D8
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BRG[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BRG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BRG[15:0] UART4 Baud Rate Divisor bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 762
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.21 UART5 Mode Register
Name:
Offset:
U5MODE
0x3DC
Note:
1.
2.
Bit
Access
Reset
Bit
Access
Reset
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more
information, see 11.4 Peripheral Pin Select (PPS).
This feature is only available for the 16x BRG mode (BRGH = 0).
15
UARTEN
R/W
0
14
7
WAKE
R/W
0
6
LPBACK
R/W
0
13
USIDL
R/W
0
12
IREN
R/W
0
11
RTSMD
R/W
0
10
5
ABAUD
R/W
0
4
URXINV
R/W
0
3
BRGH
R/W
0
2
9
8
UEN[1:0]
R/W
0
R/W
0
1
0
STSEL
R/W
0
PDSEL[1:0]
R/W
0
R/W
0
Bit 15 – UARTEN UART Enable bit(1)
Value
Description
1
UART is enabled; all UART pins are controlled by UART as defined by UEN[1:0]
0
UART is disabled; all UART pins are controlled by port latches, UART power consumption is minimal
Bit 13 – USIDL UART Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
®
Bit 12 – IREN IrDA Encoder and Decoder Enable bit(2)
Value
Description
1
IrDA encoder and decoder are enabled
0
IrDA encoder and decoder are disabled
Bit 11 – RTSMD Mode Selection for U5RTS Pin bit
Value
Description
1
U5RTS pin is in Simplex mode
0
U5RTS pin is in Flow Control mode
Bits 9:8 – UEN[1:0] UART Enable bits
Value
Description
11
U5TX, U5RX and BCLK5 pins are enabled and used; U5CTS pin is controlled by port latches
10
U5TX, U5RX, U5CTS and U5RTS pins are enabled and used
01
U5TX, U5RX and U5RTS pins are enabled and used; U5CTS pin is controlled by port latches
00
U5TX and U5RX pins are enabled and used; U5CTS and U5RTS/BCLK5 pins are controlled by port
latches
Bit 7 – WAKE Wake-up on Start Bit Detect During Sleep Mode Enable bit
Value
Description
1
UART5 continues to sample the U5RX pin; interrupt is generated on the falling edge, bit is cleared in
hardware on the following rising edge
0
No wake-up is enabled
Bit 6 – LPBACK UART Loopback Mode Select bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 763
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Value
1
0
Description
Enables Loopback mode
Loopback mode is disabled
Bit 5 – ABAUD Auto-Baud Enable bit
Value
Description
1
Enables baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0
Baud rate measurement is disabled or completed
Bit 4 – URXINV UART Receive Polarity Inversion bit
Value
Description
1
U5RX Idle state is ‘0’
0
U5RX Idle state is ‘1’
Bit 3 – BRGH High Baud Rate Enable bit
Value
Description
1
High-Speed mode (4 BRG clock cycles per bit)
0
Standard Speed mode (16 BRG clock cycles per bit)
Bits 2:1 – PDSEL[1:0] Parity and Data Selection bits
Value
Description
11
9-bit data, no parity
10
8-bit data, odd parity
01
8-bit data, even parity
00
8-bit data, no parity
Bit 0 – STSEL Stop Bit Selection bit
Value
Description
1
Two Stop bits
0
One Stop bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 764
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.22 UART5 Status and Control Register
Name:
Offset:
U5STA
0x3DE
Note:
®
1.
The value of this bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
2.
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more
information, see 11.4 Peripheral Pin Select (PPS).
Legend: C = Clearable bit; HC = Hardware Clearable bit; HS = Hardware Settable bit; HSC = Hardware Settable/
Clearable bit
Bit
15
UTXISEL1
R/W
0
Access
Reset
Bit
14
UTXINV
R/W
0
13
UTXISEL0
R/W
0
12
URXEN
R/W
0
11
UTXBRK
HC/R/W
0
10
UTXEN
R/W
0
9
UTXBF
HSC/R
0
8
TRMT
HSC/R
1
5
ADDEN
R/W
0
4
RIDLE
HSC/R
1
3
PERR
HSC/R
0
2
FERR
HSC/R
0
1
OERR
HS/R/C
0
0
URXDA
HSC/R
0
7
6
URXISEL[1:0]
R/W
R/W
0
0
Access
Reset
Bit 15 – UTXISEL1 UART Transmission Interrupt Mode Selection bit
Value of
UTXISEL[1:0]
Description
11
10
Reserved; do not use
Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
01
00
®
Bit 14 – UTXINV UART IrDA Encoder Transmit Polarity Inversion bit(1)
IREN = 1:
Value
Description
1
0
U5TX Idle state is ‘1’
U5TX Idle state is ‘0’
IREN = 0:
Value
Description
1
0
U5TX Idle state is ‘0’
U5TX Idle state is ‘1’
Bit 13 – UTXISEL0 UART Transmission Interrupt Mode Selection bit
See description of bit 15 – UTXISEL1.
Bit 12 – URXEN UART Receive Enable bit
Value
Description
1
Receive is enabled, U5RX pin is controlled by UART
0
Receive is disabled, U5RX pin is controlled by the port
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 765
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Bit 11 – UTXBRK UART Transmit Break bit
Value
Description
1
Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0
Sync Break transmission is disabled or completed
Bit 10 – UTXEN UART Transmit Enable bit(2)
Value
Description
1
Transmit is enabled, U5TX pin is controlled by UART
0
Transmit is disabled, any pending transmission is aborted and the buffer is reset; U5TX pin is
controlled by the port
Bit 9 – UTXBF UART Transmit Buffer Full Status bit (read-only)
Value
Description
1
Transmit buffer is full
0
Transmit buffer is not full, at least one more character can be written
Bit 8 – TRMT Transmit Shift Register Empty bit (read-only)
Value
Description
1
Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0
Transmit Shift Register is not empty, a transmission is in progress or queued
Bits 7:6 – URXISEL[1:0] UART Receive Interrupt Mode Selection bits
Value
Description
11
Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has four data characters)
10
Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has three data characters)
0x
Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters
Bit 5 – ADDEN Address Character Detect bit (bit 8 of received data = 1)
Value
Description
1
Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect)
0
Address Detect mode is disabled
Bit 4 – RIDLE Receiver Idle bit (read-only)
Value
Description
1
Receiver is Idle
0
Receiver is active
Bit 3 – PERR Parity Error Status bit (read-only)
Value
Description
1
Parity error has been detected for the current character (the character at the top of the receive FIFO)
0
Parity error has not been detected
Bit 2 – FERR Framing Error Status bit (read-only)
Value
Description
1
Framing error has been detected for the current character (the character at the top of the receive FIFO)
0
Framing error has not been detected
Bit 1 – OERR Receive Buffer Overrun Error Status bit (clear/read-only)
Value
Description
1
Receive buffer has overflowed
0
Receive buffer has not overflowed (clearing a previously set OERR bit (‘1’ to ‘0’ transition) will reset the
receive buffer and the RSR to the empty state)
Bit 0 – URXDA UART Receive Buffer Data Available bit (read-only)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 766
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Value
1
0
Description
Receive buffer has data, at least one more character can be read
Receive buffer is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 767
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.23 UART5 Transmit Register (Normally Write-Only)
Name:
Offset:
Bit
U5TXREG
0x3E0
15
14
13
12
11
10
9
8
U5TXREG[8]
W
0
Bit
7
6
5
4
3
U5TXREG[7:0]
W
W
0
0
2
1
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
x
Access
Reset
Bits 8:0 – U5TXREG[8:0] UART5 Transmission Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 768
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.24 UART5 Receive Register (Normally Read-Only)
Name:
Offset:
Bit
U5RXREG
0x3E2
15
14
13
12
11
10
9
8
U5RXREG[8]
R
0
Bit
7
6
5
2
1
0
Access
Reset
R
0
R
0
R
0
4
3
U5RXREG[7:0]
R
R
0
0
R
0
R
0
R
0
Access
Reset
Bits 8:0 – U5RXREG[8:0] UART5 Receive Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 769
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.25 UART5 Baud Rate Generator Register
Name:
Offset:
Bit
15
U5BRG
0x3E4
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BRG[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BRG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BRG[15:0] UART5 Baud Rate Divisor bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 770
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.26 UART6 Mode Register
Name:
Offset:
U6MODE
0x3E8
Note:
1.
2.
Bit
Access
Reset
Bit
Access
Reset
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more
information, see 11.4 Peripheral Pin Select (PPS).
This feature is only available for the 16x BRG mode (BRGH = 0).
15
UARTEN
R/W
0
14
7
WAKE
R/W
0
6
LPBACK
R/W
0
13
USIDL
R/W
0
12
IREN
R/W
0
11
RTSMD
R/W
0
10
5
ABAUD
R/W
0
4
URXINV
R/W
0
3
BRGH
R/W
0
2
9
8
UEN[1:0]
R/W
0
R/W
0
1
0
STSEL
R/W
0
PDSEL[1:0]
R/W
0
R/W
0
Bit 15 – UARTEN UART Enable bit(1)
Value
Description
1
UART is enabled; all UART pins are controlled by UART as defined by UEN[1:0]
0
UART is disabled; all UART pins are controlled by port latches, UART power consumption is minimal
Bit 13 – USIDL UART Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
®
Bit 12 – IREN IrDA Encoder and Decoder Enable bit(2)
Value
Description
1
IrDA encoder and decoder are enabled
0
IrDA encoder and decoder are disabled
Bit 11 – RTSMD Mode Selection for U6RTS Pin bit
Value
Description
1
U6RTS pin is in Simplex mode
0
U6RTS pin is in Flow Control mode
Bits 9:8 – UEN[1:0] UART Enable bits
Value
Description
11
U6TX, U6RX and BCLK6 pins are enabled and used; U6CTS pin is controlled by port latches
10
U6TX, U6RX, U6CTS and U6RTS pins are enabled and used
01
U6TX, U6RX and U6RTS pins are enabled and used; U6CTS pin is controlled by port latches
00
U6TX and U6RX pins are enabled and used; U6CTS and U6RTS/BCLK6 pins are controlled by port
latches
Bit 7 – WAKE Wake-up on Start Bit Detect During Sleep Mode Enable bit
Value
Description
1
UART6 continues to sample the U6RX pin; interrupt is generated on the falling edge, bit is cleared in
hardware on the following rising edge
0
No wake-up is enabled
Bit 6 – LPBACK UART Loopback Mode Select bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 771
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Value
1
0
Description
Enables Loopback mode
Loopback mode is disabled
Bit 5 – ABAUD Auto-Baud Enable bit
Value
Description
1
Enables baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0
Baud rate measurement is disabled or completed
Bit 4 – URXINV UART Receive Polarity Inversion bit
Value
Description
1
U6RX Idle state is ‘0’
0
U6RX Idle state is ‘1’
Bit 3 – BRGH High Baud Rate Enable bit
Value
Description
1
High-Speed mode (4 BRG clock cycles per bit)
0
Standard Speed mode (16 BRG clock cycles per bit)
Bits 2:1 – PDSEL[1:0] Parity and Data Selection bits
Value
Description
11
9-bit data, no parity
10
8-bit data, odd parity
01
8-bit data, even parity
00
8-bit data, no parity
Bit 0 – STSEL Stop Bit Selection bit
Value
Description
1
Two Stop bits
0
One Stop bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 772
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.27 UART6 Status and Control Register
Name:
Offset:
U6STA
0x3EA
Note:
®
1.
The value of this bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
2.
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more
information, see 11.4 Peripheral Pin Select (PPS).
Legend: C = Clearable bit; HC = Hardware Clearable bit; HS = Hardware Settable bit; HSC = Hardware Settable/
Clearable bit
Bit
15
UTXISEL1
R/W
0
Access
Reset
Bit
14
UTXINV
R/W
0
13
UTXISEL0
R/W
0
12
URXEN
R/W
0
11
UTXBRK
HC/R/W
0
10
UTXEN
R/W
0
9
UTXBF
HSC/R
0
8
TRMT
HSC/R
1
5
ADDEN
R/W
0
4
RIDLE
HSC/R
1
3
PERR
HSC/R
0
2
FERR
HSC/R
0
1
OERR
HS/R/C
0
0
URXDA
HSC/R
0
7
6
URXISEL[1:0]
R/W
R/W
0
0
Access
Reset
Bit 15 – UTXISEL1 UART Transmission Interrupt Mode Selection bit
Value of
UTXISEL[1:0]
Description
11
10
Reserved; do not use
Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
01
00
®
Bit 14 – UTXINV UART IrDA Encoder Transmit Polarity Inversion bit(1)
IREN = 1:
Value
Description
1
0
U6TX Idle state is ‘1’
U6TX Idle state is ‘0’
IREN = 0:
Value
Description
1
0
U6TX Idle state is ‘0’
U6TX Idle state is ‘1’
Bit 13 – UTXISEL0 UART Transmission Interrupt Mode Selection bit
See description of bit 15 – UTXISEL1.
Bit 12 – URXEN UART Receive Enable bit
Value
Description
1
Receive is enabled, U6RX pin is controlled by UART
0
Receive is disabled, U6RX pin is controlled by the port
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 773
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Bit 11 – UTXBRK UART Transmit Break bit
Value
Description
1
Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0
Sync Break transmission is disabled or completed
Bit 10 – UTXEN UART Transmit Enable bit(2)
Value
Description
1
Transmit is enabled, U6TX pin is controlled by UART
0
Transmit is disabled, any pending transmission is aborted and the buffer is reset; U6TX pin is
controlled by the port
Bit 9 – UTXBF UART Transmit Buffer Full Status bit (read-only)
Value
Description
1
Transmit buffer is full
0
Transmit buffer is not full, at least one more character can be written
Bit 8 – TRMT Transmit Shift Register Empty bit (read-only)
Value
Description
1
Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0
Transmit Shift Register is not empty, a transmission is in progress or queued
Bits 7:6 – URXISEL[1:0] UART Receive Interrupt Mode Selection bits
Value
Description
11
Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has four data characters)
10
Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has three data characters)
0x
Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters
Bit 5 – ADDEN Address Character Detect bit (bit 8 of received data = 1)
Value
Description
1
Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect)
0
Address Detect mode is disabled
Bit 4 – RIDLE Receiver Idle bit (read-only)
Value
Description
1
Receiver is Idle
0
Receiver is active
Bit 3 – PERR Parity Error Status bit (read-only)
Value
Description
1
Parity error has been detected for the current character (the character at the top of the receive FIFO)
0
Parity error has not been detected
Bit 2 – FERR Framing Error Status bit (read-only)
Value
Description
1
Framing error has been detected for the current character (the character at the top of the receive FIFO)
0
Framing error has not been detected
Bit 1 – OERR Receive Buffer Overrun Error Status bit (clear/read-only)
Value
Description
1
Receive buffer has overflowed
0
Receive buffer has not overflowed (clearing a previously set OERR bit (‘1’ to ‘0’ transition) will reset the
receive buffer and the RSR to the empty state)
Bit 0 – URXDA UART Receive Buffer Data Available bit (read-only)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 774
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
Value
1
0
Description
Receive buffer has data, at least one more character can be read
Receive buffer is empty
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 775
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.28 UART6 Transmit Register (Normally Write-Only)
Name:
Offset:
Bit
U6TXREG
0x3EC
15
14
13
12
11
10
9
8
U6TXREG[8]
W
0
Bit
7
6
5
4
3
U6TXREG[7:0]
W
W
0
0
2
1
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
x
Access
Reset
Bits 8:0 – U6TXREG[8:0] UART6 Transmission Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 776
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.29 UART6 Receive Register (Normally Read-Only)
Name:
Offset:
Bit
U6RXREG
0x3EE
15
14
13
12
11
10
9
8
U6RXREG[8]
R
0
Bit
7
6
5
2
1
0
Access
Reset
R
0
R
0
R
0
4
3
U6RXREG[7:0]
R
R
0
0
R
0
R
0
R
0
Access
Reset
Bits 8:0 – U6RXREG[8:0] UART6 Receive Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 777
PIC24FJ512GU410 Family Data Sheet
Universal Asynchronous Receiver Transmitter ...
17.8.30 UART6 Baud Rate Generator Register
Name:
Offset:
Bit
15
U6BRG
0x3F0
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BRG[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BRG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BRG[15:0] UART6 Baud Rate Divisor bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 778
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.
Liquid Crystal Display (LCD) Controller
Note: This data sheet summarizes the features of the PIC24FJ512GU410 family devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet, refer to “Liquid Crystal Display
(LCD)” (DS30009740) in the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
website (www.microchip.com).
The Liquid Crystal Display (LCD) controller generates the data and timing control required to directly drive a static or
multiplexed LCD panel. The module can drive up to eight Commons signals on all devices, and up to 64 Segments,
depending on the specific device.
Note: To be driven by the LCD controller, pins must be set as analog inputs. For the port corresponding to the
desired Common or Segment pin, set TRISx = 1 and ANSx = 1.
The LCD Controller has these features:
•
•
•
•
•
•
•
•
Direct Driving of LCD Panel
Three LCD Clock Sources with Selectable Prescaler
Up to Eight Commons:
– Static (one Common)
– 1/2 multiplex (two Commons)
– 1/3 multiplex (three Commons)
– 1/4 multiplex (four Commons)
– 1/5 multiplex (five Commons)
– 1/6 multiplex (six Commons)
– 1/7 multiplex (seven Commons)
– 1/8 multiplex (eight Commons)
Static, 1/2 or 1/3 LCD Bias
On-Chip Bias Generator with Dedicated Charge Pump to Support a Range of Fixed and Bias Options
Internal Resistors for Bias Voltage Generation
Software Contrast Control for LCD Using Internal Biasing
Core-Independent Automatic Display Features:
– Dual display memory used to display two different display contents
– Blink mode of individual pixels or the complete pixels
– Blanking of individual pixels or the complete pixels
– Timing schedule can be changed, without core intervention, based on user configurations
A simplified block diagram of the module is shown in Figure 18-1.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 779
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Figure 18-1. LCD Controller Module Block Diagram
SEG[63:0]
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 780
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1
LCD Registers
Offset
Name
0x00
...
0x053F
Reserved
0x0540
LCDCON
0x0542
LCDREF
0x0544
LCDPS
0x0546
LCDDATA0
0x0548
LCDDATA1
0x054A
LCDDATA2
0x054C
LCDDATA3
0x054E
LCDDATA4
0x0550
LCDDATA5
0x0552
LCDDATA6
0x0554
LCDDATA7
0x0556
LCDDATA8
0x0558
LCDDATA9
0x055A
LCDDATA10
0x055C
LCDDATA11
0x055E
LCDDATA12
0x0560
LCDDATA13
0x0562
LCDDATA14
0x0564
LCDDATA15
0x0566
LCDDATA16
0x0568
LCDDATA17
0x056A
LCDDATA18
0x056C
LCDDATA19
0x056E
LCDDATA20
0x0570
LCDDATA21
0x0572
LCDDATA22
Bit Pos.
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7
6
SLPEN
LCDEN
LRLAP[1:0]
LCDIRE
WFT
BIASMD
S07C0
S15C0
S23C0
S31C0
S39C0
S47C0
S55C0
S63C0
S07C1
S15C1
S23C1
S31C1
S39C1
S47C1
S55C1
S63C1
S07C2
S15C2
S23C2
S31C2
S39C2
S47C2
S55C2
S63C2
S07C3
S15C3
S23C3
S31C3
S39C3
S47C3
S55C3
S63C3
S07C4
S15C4
S23C4
S31C4
S39C4
S47C4
S55C4
S63C4
S07C5
S15C5
S23C5
S31C5
S39C5
S47C5
© 2019-2020 Microchip Technology Inc.
S06C0
S14C0
S22C0
S30C0
S38C0
S46C0
S54C0
S62C0
S06C1
S14C1
S22C1
S30C1
S38C1
S46C1
S54C1
S62C1
S06C2
S14C2
S22C2
S30C2
S38C2
S46C2
S54C2
S62C2
S06C3
S14C3
S22C3
S30C3
S38C3
S46C3
S54C3
S62C3
S06C4
S14C4
S22C4
S30C4
S38C4
S46C4
S54C4
S62C4
S06C5
S14C5
S22C5
S30C5
S38C5
S46C5
5
4
3
WERR
CS[1:0]
LCDSIDL
LRLBP[1:0]
LCDCST[2:0]
LCDA
WA
S05C0
S13C0
S21C0
S29C0
S37C0
S45C0
S53C0
S61C0
S05C1
S13C1
S21C1
S29C1
S37C1
S45C1
S53C1
S61C1
S05C2
S13C2
S21C2
S29C2
S37C2
S45C2
S53C2
S61C2
S05C3
S13C3
S21C3
S29C3
S37C3
S45C3
S53C3
S61C3
S05C4
S13C4
S21C4
S29C4
S37C4
S45C4
S53C4
S61C4
S05C5
S13C5
S21C5
S29C5
S37C5
S45C5
S04C0
S12C0
S20C0
S28C0
S36C0
S44C0
S52C0
S60C0
S04C1
S12C1
S20C1
S28C1
S36C1
S44C1
S52C1
S60C1
S04C2
S12C2
S20C2
S28C2
S36C2
S44C2
S52C2
S60C2
S04C3
S12C3
S20C3
S28C3
S36C3
S44C3
S52C3
S60C3
S04C4
S12C4
S20C4
S28C4
S36C4
S44C4
S52C4
S60C4
S04C5
S12C5
S20C5
S28C5
S36C5
S44C5
Datasheet
2
1
0
LMUX[2:0]
LRLAT[2:0]
VLCD3PE
VLCD2PE
LP[3:0]
S03C0
S11C0
S19C0
S27C0
S35C0
S43C0
S51C0
S59C0
S03C1
S11C1
S19C1
S27C1
S35C1
S43C1
S51C1
S59C1
S03C2
S11C2
S19C2
S27C2
S35C2
S43C2
S51C2
S59C2
S03C3
S11C3
S19C3
S27C3
S35C3
S43C3
S51C3
S59C3
S03C4
S11C4
S19C4
S27C4
S35C4
S43C4
S51C4
S59C4
S03C5
S11C5
S19C5
S27C5
S35C5
S43C5
S02C0
S10C0
S18C0
S26C0
S34C0
S42C0
S50C0
S58C0
S02C1
S10C1
S18C1
S26C1
S34C1
S42C1
S50C1
S58C1
S02C2
S10C2
S18C2
S26C2
S34C2
S42C2
S50C2
S58C2
S02C3
S10C3
S18C3
S26C3
S34C3
S42C3
S50C3
S58C3
S02C4
S10C4
S18C4
S26C4
S34C4
S42C4
S50C4
S58C4
S02C5
S10C5
S18C5
S26C5
S34C5
S42C5
S01C0
S09C0
S17C0
S25C0
S33C0
S41C0
S49C0
S57C0
S01C1
S09C1
S17C1
S25C1
S33C1
S41C1
S49C1
S57C1
S01C2
S09C2
S17C2
S25C2
S33C2
S41C2
S49C2
S57C2
S01C3
S09C3
S17C3
S25C3
S33C3
S41C3
S49C3
S57C3
S01C4
S09C4
S17C4
S25C4
S33C4
S41C4
S49C4
S57C4
S01C5
S09C5
S17C5
S25C5
S33C5
S41C5
VLCD1PE
S00C0
S08C0
S16C0
S24C0
S32C0
S40C0
S48C0
S56C0
S00C1
S08C1
S16C1
S24C1
S32C1
S40C1
S48C1
S56C1
S00C2
S08C2
S16C2
S24C2
S32C2
S40C2
S48C2
S56C2
S00C3
S08C3
S16C3
S24C3
S32C3
S40C3
S48C3
S56C3
S00C4
S08C4
S16C4
S24C4
S32C4
S40C4
S48C4
S56C4
S00C5
S08C5
S16C5
S24C5
S32C5
S40C5
DS30010203C-page 781
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
...........continued
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x0574
LCDDATA23
7:0
15:8
S55C5
S63C5
S54C5
S62C5
S53C5
S61C5
S52C5
S60C5
S51C5
S59C5
S50C5
S58C5
S49C5
S57C5
S48C5
S56C5
0x0576
LCDDATA24
0x0578
LCDDATA25
0x057A
LCDDATA26
0x057C
LCDDATA27
0x057E
LCDDATA28
0x0580
LCDDATA29
0x0582
LCDDATA30
0x0584
LCDDATA31
0x0586
LCDSE0
0x0588
LCDSE1
0x058A
LCDSE2
0x058C
LCDSE3
S07C6
S15C6
S23C6
S31C6
S39C6
S47C6
S55C6
S63C6
S07C7
S15C7
S23C7
S31C7
S39C7
S47C7
S55C7
S63C7
SE07
SE15
SE23
SE31
SE39
SE47
SE55
SE63
S06C6
S14C6
S22C6
S30C6
S38C6
S46C6
S54C6
S62C6
S06C7
S14C7
S22C7
S30C7
S38C7
S46C7
S54C7
S62C7
SE06
SE14
SE22
SE30
SE38
SE46
SE54
SE62
S05C6
S13C6
S21C6
S29C6
S37C6
S45C6
S53C6
S61C6
S05C7
S13C7
S21C7
S29C7
S37C7
S45C7
S53C7
S61C7
SE05
SE13
SE21
SE29
SE37
SE45
SE53
SE61
S04C6
S12C6
S20C6
S28C6
S36C6
S44C6
S52C6
S60C6
S04C7
S12C7
S20C7
S28C7
S36C7
S44C7
S52C7
S60C7
SE04
SE12
SE20
SE28
SE36
SE44
SE52
SE60
S03C6
S11C6
S19C6
S27C6
S35C6
S43C6
S51C6
S59C6
S03C7
S11C7
S19C7
S27C7
S35C7
S43C7
S51C7
S59C7
SE03
SE11
SE19
SE27
SE35
SE43
SE51
SE59
S02C6
S10C6
S18C6
S26C6
S34C6
S42C6
S50C6
S58C6
S02C7
S10C7
S18C7
S26C7
S34C7
S42C7
S50C7
S58C7
SE02
SE10
SE18
SE26
SE34
SE42
SE50
SE58
0x058E
LCDREG
S01C6
S00C6
S09C6
S08C6
S17C6
S16C6
S25C6
S24C6
S33C6
S32C6
S41C6
S40C6
S49C6
S48C6
S57C6
S56C6
S01C7
S00C7
S09C7
S08C7
S17C7
S16C7
S25C7
S24C7
S33C7
S32C7
S41C7
S40C7
S49C7
S48C7
S57C7
S56C7
SE01
SE00
SE09
SE08
SE17
SE16
SE25
SE24
SE33
SE32
SE41
SE40
SE49
SE48
SE57
SE56
CLKSEL[1:0]
0x0590
LCDACTRL
0x0592
LCDASTAT
0x0594
LCDFC0
0x0596
LCDFC1
0x0598
LCDFC2
0x059A
LCDEVNT
0x059C
LCDSDATA0
0x059E
LCDSDATA1
0x05A0
LCDSDATA2
0x05A2
LCDSDATA3
0x05A4
LCDSDATA4
0x05A6
LCDSDATA5
0x05A8
LCDSDATA6
0x05AA
LCDSDATA7
0x05AC
LCDSDATA8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
CPEN
BLANKFCS[2:0]
SMFCS[2:0]
SMLOCK
SMCLEAR
PMLOCK
SBLANK
SMEMACT
S07C
S15C
S23C
S31C
S39C
S47C
S55C
S63C
S07C
S15C
S23C
S31C
S39C
S47C
S55C
S63C
S07C
S15C
© 2019-2020 Microchip Technology Inc.
S06C
S14C
S22C
S30C
S38C
S46C
S54C
S62C
S06C
S14C
S22C
S30C
S38C
S46C
S54C
S62C
S06C
S14C
S05C
S13C
S21C
S29C
S37C
S45C
S53C
S61C
S05C
S13C
S21C
S29C
S37C
S45C
S53C
S61C
S05C
S13C
BLANKMODE[1:0]
FCCS[1:0]
ELCDEN
BLINKFCS[2:0]
BLINKMODE[1:0]
PMCLEAR
SMEMEN
PMEMDIS
DMSEL[1:0]
PMEMACT
TEVENTO
FC2O
FC1O
FC0O
FC0[7:0]
FC0[15:8]
FC1[7:0]
FC1[15:8]
FC2[7:0]
FC2[15:8]
TEVENT[7:0]
TEVENT[15:8]
S04C
S03C
S02C
S01C
S00C
S12C
S11C
S10C
S09C
S08C
S20C
S19C
S18C
S17C
S16C
S28C
S27C
S26C
S25C
S24C
S36C
S35C
S34C
S33C
S32C
S44C
S43C
S42C
S41C
S40C
S52C
S51C
S50C
S49C
S48C
S60C
S59C
S58C
S57C
S56C
S04C
S03C
S02C
S01C
S00C
S12C
S11C
S10C
S09C
S08C
S20C
S19C
S18C
S17C
S16C
S28C
S27C
S26C
S25C
S24C
S36C
S35C
S34C
S33C
S32C
S44C
S43C
S42C
S41C
S40C
S52C
S51C
S50C
S49C
S48C
S60C
S59C
S58C
S57C
S56C
S04C
S03C
S02C
S01C
S00C
S12C
S11C
S10C
S09C
S08C
Datasheet
DS30010203C-page 782
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
...........continued
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x05AE
LCDSDATA9
7:0
15:8
S23C
S31C
S22C
S30C
S21C
S29C
S20C
S28C
S19C
S27C
S18C
S26C
S17C
S25C
S16C
S24C
0x05B0
LCDSDATA10
0x05B2
LCDSDATA11
0x05B4
LCDSDATA12
0x05B6
LCDSDATA13
0x05B8
LCDSDATA14
0x05BA
LCDSDATA15
0x05BC
LCDSDATA16
0x05BE
LCDSDATA17
0x05C0
LCDSDATA18
0x05C2
LCDSDATA19
0x05C4
LCDSDATA20
0x05C6
LCDSDATA21
0x05C8
LCDSDATA22
0x05CA
LCDSDATA23
0x05CC
LCDSDATA24
0x05CE
LCDSDATA25
0x05D0
LCDDATA26
0x05D2
LCDSDATA27
0x05D4
LCDSDATA28
0x05D6
LCDSDATA29
0x05D8
LCDSDATA30
0x05DA
LCDSDATA31
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
S39C
S47C
S55C
S63C
S07C
S15C
S23C
S31C
S39C
S47C
S55C
S63C
S07C
S15C
S23C
S31C
S39C
S47C
S55C
S63C
S07C
S15C
S23C
S31C
S39C
S47C
S55C
S63C
S07C
S15C
S23C
S31C
S39C6
S47C6
S55C
S63C
S07C
S15C
S23C
S31C
S39C
S47C
S55C
S63C
S38C
S46C
S54C
S62C
S06C
S14C
S22C
S30C
S38C
S46C
S54C
S62C
S06C
S14C
S22C
S30C
S38C
S46C
S54C
S62C
S06C
S14C
S22C
S30C
S38C
S46C
S54C
S62C
S06C
S14C
S22C
S30C
S38C6
S46C6
S54C
S62C
S06C
S14C
S22C
S30C
S38C
S46C
S54C
S62C
S37C
S45C
S53C
S61C
S05C
S13C
S21C
S29C
S37C
S45C
S53C
S61C
S05C
S13C
S21C
S29C
S37C
S45C
S53C
S61C
S05C
S13C
S21C
S29C
S37C
S45C
S53C
S61C
S05C
S13C
S21C
S29C
S37C6
S45C6
S53C
S61C
S05C
S13C
S21C
S29C
S37C
S45C
S53C
S61C
S36C
S44C
S52C
S60C
S04C
S12C
S20C
S28C
S36C
S44C
S52C
S60C
S04C
S12C
S20C
S28C
S36C
S44C
S52C
S60C
S04C
S12C
S20C
S28C
S36C
S44C
S52C
S60C
S04C
S12C
S20C
S28C
S36C6
S44C6
S52C
S60C
S04C
S12C
S20C
S28C
S36C
S44C
S52C
S60C
S35C
S43C
S51C
S59C
S03C
S11C
S19C
S27C
S35C
S43C
S51C
S59C
S03C
S11C
S19C
S27C
S35C
S43C
S51C
S59C
S03C
S11C
S19C
S27C
S35C
S43C
S51C
S59C
S03C
S11C
S19C
S27C
S35C6
S43C6
S51C
S59C
S03C
S11C
S19C
S27C
S35C
S43C
S51C
S59C
S34C
S42C
S50C
S58C
S02C
S10C
S18C
S26C
S34C
S42C
S50C
S58C
S02C
S10C
S18C
S26C
S34C
S42C
S50C
S58C
S02C
S10C
S18C
S26C
S34C
S42C
S50C
S58C
S02C
S10C
S18C
S26C
S34C6
S42C6
S50C
S58C
S02C
S10C
S18C
S26C
S34C
S42C
S50C
S58C
S33C
S41C
S49C
S57C
S01C
S09C
S17C
S25C
S33C
S41C
S49C
S57C
S01C
S09C
S17C
S25C
S33C
S41C
S49C
S57C
S01C
S09C
S17C
S25C
S33C
S41C
S49C
S57C
S01C
S09C
S17C
S25C
S33C6
S41C6
S49C
S57C
S01C
S09C
S17C
S25C
S33C
S41C
S49C
S57C
S32C
S40C
S48C
S56C
S00C
S08C
S16C
S24C
S32C
S40C
S48C
S56C
S00C
S08C
S16C
S24C
S32C
S40C
S48C
S56C
S00C
S08C
S16C
S24C
S32C
S40C
S48C
S56C
S00C
S08C
S16C
S24C
S32C6
S40C6
S48C
S56C
S00C
S08C
S16C
S24C
S32C
S40C
S48C
S56C
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 783
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.1
LCD Control Register
Name:
Offset:
LCDCON
0x540
Legend: C = Clearable bit
Bit
Access
Reset
Bit
Access
Reset
15
LCDEN
R/W
0
14
13
LCDSIDL
R/W
0
12
7
6
SLPEN
R/W
0
5
WERR
R/C
0
4
11
10
9
8
3
2
0
R/W
0
R/W
0
1
LMUX[2:0]
R/W
0
CS[1:0]
R/W
0
R/W
0
Bit 15 – LCDEN LCD Driver Enable bit
Value
Description
1
LCD driver module is enabled
0
LCD driver module is not enabled
Bit 13 – LCDSIDL Stop LCD Drive in CPU Idle Mode Control bit
Value
Description
1
LCD driver halts in CPU Idle mode
0
LCD driver continues to operate in CPU Idle mode
Bit 6 – SLPEN LCD Driver Enable in Sleep Mode bit
Value
Description
1
LCD driver module is disabled in Sleep mode
0
LCD driver module is enabled in Sleep mode
Bit 5 – WERR LCD Write Failed Error bit
Value
Description
1
LCDDATA register is written while WA (LCDPS[4]) = 0 (must be cleared in software)
0
No LCD write error
Bits 4:3 – CS[1:0] Clock Source Select bits
Value
Description
1x
SOSC
01
LPRC
00
FRC
Bits 2:0 – LMUX[2:0] LCD Commons Select bits
LMUX[2:0]
111
110
101
100
011
010
001
000
© 2019-2020 Microchip Technology Inc.
Multiplex
1/8 MUX (COM[7:0])
1/7 MUX (COM[6:0])
1/6 MUX (COM[5:0])
1/5 MUX (COM[4:0])
1/4 MUX (COM[3:0])
1/3 MUX (COM[2:0])
1/2 MUX (COM[1:0])
Static (COM0)
Datasheet
Bias
1/3
1/3
1/3
1/3
1/3
1/2 or 1/3
1/2 or 1/3
Static
DS30010203C-page 784
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.2
LCD Reference Ladder Control Register
Name:
Offset:
Bit
Access
Reset
Bit
LCDREF
0x542
15
LCDIRE
R/W
0
14
7
6
13
R/W
0
R/W
0
4
5
LRLAP[1:0]
Access
Reset
12
LCDCST[2:0]
R/W
0
11
R/W
0
10
VLCD3PE
R/W
0
9
VLCD2PE
R/W
0
8
VLCD1PE
R/W
0
3
2
1
LRLAT[2:0]
R/W
0
0
LRLBP[1:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit 15 – LCDIRE LCD Internal Reference Enable bit
Value
Description
1
Internal LCD reference is enabled and connected to the internal contrast control circuit
0
Internal LCD reference is disabled
Bits 13:11 – LCDCST[2:0] LCD Contrast Control bits
Selects the resistance of the LCD contrast control resistor ladder.
Value
Description
111
Resistor ladder is at maximum resistance (minimum contrast)
110
Resistor ladder is at 6/7th of maximum resistance
101
Resistor ladder is at 5/7th of maximum resistance
100
Resistor ladder is at 4/7th of maximum resistance
011
Resistor ladder is at 3/7th of maximum resistance
010
Resistor ladder is at 2/7th of maximum resistance
001
Resistor ladder is at 1/7th of maximum resistance
000
Minimum resistance (maximum contrast); contrast resistor is shorted
Bit 10 – VLCD3PE LCD Bias 3 Pin Enable bit
Value
Description
1
Bias 3 level is connected to the external pin, LCDBIAS3
0
Bias 3 level is internal (internal resistor ladder)
Bit 9 – VLCD2PE LCD Bias 2 Pin Enable bit
Value
Description
1
Bias 2 level is connected to the external pin, LCDBIAS2
0
Bias 2 level is internal (internal resistor ladder)
Bit 8 – VLCD1PE LCD Bias 1 Pin Enable bit
Value
Description
1
Bias 1 level is connected to the external pin, LCDBIAS1
0
Bias 1 level is internal (internal resistor ladder)
Bits 7:6 – LRLAP[1:0] LCD Reference Ladder A Time Power Control bits
During A Time Interval:
Value
Description
11
Internal LCD reference ladder is powered in High-Power mode
10
Internal LCD reference ladder is powered in Medium Power mode
01
Internal LCD reference ladder is powered in Low-Power mode
00
Internal LCD reference ladder is powered down and unconnected
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 785
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bits 5:4 – LRLBP[1:0] LCD Reference Ladder B Time Power Control bits
During B Time Interval:
Value
Description
11
Internal LCD reference ladder is powered in High-Power mode
10
Internal LCD reference ladder is powered in Medium Power mode
01
Internal LCD reference ladder is powered in Low-Power mode
00
Internal LCD reference ladder is powered down and unconnected
Bits 2:0 – LRLAT[2:0] LCD Reference Ladder A Time Interval Control bits
Sets the number of 32 clock counts when the A Time Interval Power mode is active.
For Type-A Waveforms (WFT = 0):
Value
Description
111
Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 9
clocks
Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 10
clocks
Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 11
clocks
Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 12
clocks
Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 13
clocks
Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 14
clocks
Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 15
clocks
Internal LCD reference ladder is always in B Power mode
110
101
100
011
010
001
000
For Type-B Waveforms (WFT = 1):
Value
Description
111
Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 25
clocks
Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 26
clocks
Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 27
clocks
Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 28
clocks
Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 29
clocks
Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 30
clocks
Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 31
clocks
Internal LCD reference ladder is always in B Power mode
110
101
100
011
010
001
000
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 786
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.3
LCD Phase Register
Name:
Offset:
Bit
LCDPS
0x544
15
14
13
12
11
10
7
WFT
R/W
0
6
BIASMD
R/W
0
5
LCDA
R/W
0
4
WA
R/W
0
3
2
9
8
1
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
LP[3:0]
R/W
0
R/W
0
Bit 7 – WFT Waveform Type Select bit
Value
Description
1
Type-B waveform (phase changes on each frame boundary)
0
Type-A waveform (phase changes within each Common type)
Bit 6 – BIASMD Bias Mode Select bit
When LMUX[2:0] = 000 or 011 through 111:
0 = Static Bias mode (do not set this bit to ‘1’)
When LMUX[2:0] = 001 or 010:
Value
Description
1
1/2 Bias mode
0
1/3 Bias mode
Bit 5 – LCDA LCD Active Status bit
Value
Description
1
LCD driver module is active
0
LCD driver module is inactive
Bit 4 – WA LCD Write Allow Status bit
Value
Description
1
Write into the LCDDATAx registers is allowed
0
Write into the LCDDATAx registers is not allowed
Bits 3:0 – LP[3:0] LCD Prescaler Select bits
Value
Description
1111
1:16
1110
1:15
1101
1:14
1100
1:13
1011
1:12
1010
1:11
1001
1:10
1000
1:9
0111
1:8
0110
1:7
0101
1:6
0100
1:5
0011
1:4
0010
1:3
0001
1:2
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 787
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
0000
Description
1:1
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 788
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.4
LCD Data0 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA0
0x546
15
S15C0
R/W
0
14
S14C0
R/W
0
13
S13C0
R/W
0
12
S12C0
R/W
0
11
S11C0
R/W
0
10
S10C0
R/W
0
9
S09C0
R/W
0
8
S08C0
R/W
0
7
S07C0
R/W
0
6
S06C0
R/W
0
5
S05C0
R/W
0
4
S04C0
R/W
0
3
S03C0
R/W
0
2
S02C0
R/W
0
1
S01C0
R/W
0
0
S00C0
R/W
0
Bit 15 – S15C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S14C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S13C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S12C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S11C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S10C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S09C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S08C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 789
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S07C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S06C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S05C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S04C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S03C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S02C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S01C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S00C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 790
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.5
LCD Data1 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA1
0x548
15
S31C0
R/W
0
14
S30C0
R/W
0
13
S29C0
R/W
0
12
S28C0
R/W
0
11
S27C0
R/W
0
10
S26C0
R/W
0
9
S25C0
R/W
0
8
S24C0
R/W
0
7
S23C0
R/W
0
6
S22C0
R/W
0
5
S21C0
R/W
0
4
S20C0
R/W
0
3
S19C0
R/W
0
2
S18C0
R/W
0
1
S17C0
R/W
0
0
S16C0
R/W
0
Bit 15 – S31C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S30C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S29C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S28C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S27C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S26C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S25C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S24C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 791
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S23C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S22C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S21C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S20C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S19C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S18C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S17C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S16C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 792
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.6
LCD Data2 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA2
0x54A
15
S47C0
R/W
0
14
S46C0
R/W
0
13
S45C0
R/W
0
12
S44C0
R/W
0
11
S43C0
R/W
0
10
S42C0
R/W
0
9
S41C0
R/W
0
8
S40C0
R/W
0
7
S39C0
R/W
0
6
S38C0
R/W
0
5
S37C0
R/W
0
4
S36C0
R/W
0
3
S35C0
R/W
0
2
S34C0
R/W
0
1
S33C0
R/W
0
0
S32C0
R/W
0
Bit 15 – S47C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S46C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S45C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S44C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S43C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S42C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S41C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S40C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 793
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S39C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S38C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S37C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S36C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S35C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S34C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S33C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S32C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 794
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.7
LCD Data3 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA3
0x54C
15
S63C0
R/W
0
14
S62C0
R/W
0
13
S61C0
R/W
0
12
S60C0
R/W
0
11
S59C0
R/W
0
10
S58C0
R/W
0
9
S57C0
R/W
0
8
S56C0
R/W
0
7
S55C0
R/W
0
6
S54C0
R/W
0
5
S53C0
R/W
0
4
S52C0
R/W
0
3
S51C0
R/W
0
2
S50C0
R/W
0
1
S49C0
R/W
0
0
S48C0
R/W
0
Bit 15 – S63C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S62C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S61C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S60C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S59C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S58C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S57C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S56C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 795
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S55C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S54C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S53C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S52C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S51C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S50C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S49C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S48C0 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 796
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.8
LCD Data4 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA4
0x54E
15
S15C1
R/W
0
14
S14C1
R/W
0
13
S13C1
R/W
0
12
S12C1
R/W
0
11
S11C1
R/W
0
10
S10C1
R/W
0
9
S09C1
R/W
0
8
S08C1
R/W
0
7
S07C1
R/W
0
6
S06C1
R/W
0
5
S05C1
R/W
0
4
S04C1
R/W
0
3
S03C1
R/W
0
2
S02C1
R/W
0
1
S01C1
R/W
0
0
S00C1
R/W
0
Bit 15 – S15C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S14C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S13C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S12C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S11C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S10C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S09C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S08C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 797
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S07C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S06C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S05C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S04C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S03C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S02C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S01C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S00C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 798
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.9
LCD Data5 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA5
0x550
15
S31C1
R/W
0
14
S30C1
R/W
0
13
S29C1
R/W
0
12
S28C1
R/W
0
11
S27C1
R/W
0
10
S26C1
R/W
0
9
S25C1
R/W
0
8
S24C1
R/W
0
7
S23C1
R/W
0
6
S22C1
R/W
0
5
S21C1
R/W
0
4
S20C1
R/W
0
3
S19C1
R/W
0
2
S18C1
R/W
0
1
S17C1
R/W
0
0
S16C1
R/W
0
Bit 15 – S31C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S30C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S29C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S28C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S27C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S26C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S25C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S24C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 799
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S23C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S22C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S21C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S20C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S19C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S18C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S17C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S16C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 800
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.10 LCD Data6 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA6
0x552
15
S47C1
R/W
0
14
S46C1
R/W
0
13
S45C1
R/W
0
12
S44C1
R/W
0
11
S43C1
R/W
0
10
S42C1
R/W
0
9
S41C1
R/W
0
8
S40C1
R/W
0
7
S39C1
R/W
0
6
S38C1
R/W
0
5
S37C1
R/W
0
4
S36C1
R/W
0
3
S35C1
R/W
0
2
S34C1
R/W
0
1
S33C1
R/W
0
0
S32C1
R/W
0
Bit 15 – S47C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S46C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S45C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S44C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S43C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S42C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S41C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S40C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 801
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S39C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S38C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S37C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S36C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S35C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S34C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S33C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S32C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 802
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.11 LCD Data7 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA7
0x554
15
S63C1
R/W
0
14
S62C1
R/W
0
13
S61C1
R/W
0
12
S60C1
R/W
0
11
S59C1
R/W
0
10
S58C1
R/W
0
9
S57C1
R/W
0
8
S56C1
R/W
0
7
S55C1
R/W
0
6
S54C1
R/W
0
5
S53C1
R/W
0
4
S52C1
R/W
0
3
S51C1
R/W
0
2
S50C1
R/W
0
1
S49C1
R/W
0
0
S48C1
R/W
0
Bit 15 – S63C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S62C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S61C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S60C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S59C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S58C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S57C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S56C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 803
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S55C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S54C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S53C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S52C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S51C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S50C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S49C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S48C1 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 804
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.12 LCD Data8 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA8
0x556
15
S15C2
R/W
0
14
S14C2
R/W
0
13
S13C2
R/W
0
12
S12C2
R/W
0
11
S11C2
R/W
0
10
S10C2
R/W
0
9
S09C2
R/W
0
8
S08C2
R/W
0
7
S07C2
R/W
0
6
S06C2
R/W
0
5
S05C2
R/W
0
4
S04C2
R/W
0
3
S03C2
R/W
0
2
S02C2
R/W
0
1
S01C2
R/W
0
0
S00C2
R/W
0
Bit 15 – S15C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S14C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S13C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S12C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S11C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S10C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S09C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S08C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 805
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S07C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S06C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S05C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S04C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S03C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S02C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S01C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S00C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 806
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.13 LCD Data9 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA9
0x558
15
S31C2
R/W
0
14
S30C2
R/W
0
13
S29C2
R/W
0
12
S28C2
R/W
0
11
S27C2
R/W
0
10
S26C2
R/W
0
9
S25C2
R/W
0
8
S24C2
R/W
0
7
S23C2
R/W
0
6
S22C2
R/W
0
5
S21C2
R/W
0
4
S20C2
R/W
0
3
S19C2
R/W
0
2
S18C2
R/W
0
1
S17C2
R/W
0
0
S16C2
R/W
0
Bit 15 – S31C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S30C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S29C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S28C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S27C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S26C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S25C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S24C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 807
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S23C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S22C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S21C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S20C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S19C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S18C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S17C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S16C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 808
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.14 LCD Data10 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA10
0x55A
15
S47C2
R/W
0
14
S46C2
R/W
0
13
S45C2
R/W
0
12
S44C2
R/W
0
11
S43C2
R/W
0
10
S42C2
R/W
0
9
S41C2
R/W
0
8
S40C2
R/W
0
7
S39C2
R/W
0
6
S38C2
R/W
0
5
S37C2
R/W
0
4
S36C2
R/W
0
3
S35C2
R/W
0
2
S34C2
R/W
0
1
S33C2
R/W
0
0
S32C2
R/W
0
Bit 15 – S47C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S46C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S45C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S44C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S43C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S42C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S41C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S40C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 809
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S39C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S38C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S37C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S36C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S35C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S34C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S33C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S32C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 810
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.15 LCD Data11 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA11
0x55C
15
S63C2
R/W
0
14
S62C2
R/W
0
13
S61C2
R/W
0
12
S60C2
R/W
0
11
S59C2
R/W
0
10
S58C2
R/W
0
9
S57C2
R/W
0
8
S56C2
R/W
0
7
S55C2
R/W
0
6
S54C2
R/W
0
5
S53C2
R/W
0
4
S52C2
R/W
0
3
S51C2
R/W
0
2
S50C2
R/W
0
1
S49C2
R/W
0
0
S48C2
R/W
0
Bit 15 – S63C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S62C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S61C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S60C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S59C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S58C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S57C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S56C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 811
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S55C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S54C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S53C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S52C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S51C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S50C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S49C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S48C2 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 812
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.16 LCD Data12 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA12
0x55E
15
S15C3
R/W
0
14
S14C3
R/W
0
13
S13C3
R/W
0
12
S12C3
R/W
0
11
S11C3
R/W
0
10
S10C3
R/W
0
9
S09C3
R/W
0
8
S08C3
R/W
0
7
S07C3
R/W
0
6
S06C3
R/W
0
5
S05C3
R/W
0
4
S04C3
R/W
0
3
S03C3
R/W
0
2
S02C3
R/W
0
1
S01C3
R/W
0
0
S00C3
R/W
0
Bit 15 – S15C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S14C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S13C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S12C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S11C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S10C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S09C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S08C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 813
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S07C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S06C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S05C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S04C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S03C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S02C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S01C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S00C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 814
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.17 LCD Data13 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA13
0x560
15
S31C3
R/W
0
14
S30C3
R/W
0
13
S29C3
R/W
0
12
S28C3
R/W
0
11
S27C3
R/W
0
10
S26C3
R/W
0
9
S25C3
R/W
0
8
S24C3
R/W
0
7
S23C3
R/W
0
6
S22C3
R/W
0
5
S21C3
R/W
0
4
S20C3
R/W
0
3
S19C3
R/W
0
2
S18C3
R/W
0
1
S17C3
R/W
0
0
S16C3
R/W
0
Bit 15 – S31C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S30C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S29C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S28C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S27C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S26C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S25C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S24C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 815
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S23C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S22C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S21C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S20C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S19C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S18C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S17C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S16C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 816
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.18 LCD Data14 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA14
0x562
15
S47C3
R/W
0
14
S46C3
R/W
0
13
S45C3
R/W
0
12
S44C3
R/W
0
11
S43C3
R/W
0
10
S42C3
R/W
0
9
S41C3
R/W
0
8
S40C3
R/W
0
7
S39C3
R/W
0
6
S38C3
R/W
0
5
S37C3
R/W
0
4
S36C3
R/W
0
3
S35C3
R/W
0
2
S34C3
R/W
0
1
S33C3
R/W
0
0
S32C3
R/W
0
Bit 15 – S47C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S46C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S45C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S44C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S43C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S42C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S41C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S40C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 817
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S39C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S38C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S37C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S36C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S35C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S34C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S33C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S32C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 818
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.19 LCD Data15 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA15
0x564
15
S63C3
R/W
0
14
S62C3
R/W
0
13
S61C3
R/W
0
12
S60C3
R/W
0
11
S59C3
R/W
0
10
S58C3
R/W
0
9
S57C3
R/W
0
8
S56C3
R/W
0
7
S55C3
R/W
0
6
S54C3
R/W
0
5
S53C3
R/W
0
4
S52C3
R/W
0
3
S51C3
R/W
0
2
S50C3
R/W
0
1
S49C3
R/W
0
0
S48C3
R/W
0
Bit 15 – S63C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S62C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S61C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S60C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S59C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S58C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S57C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S56C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 819
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S55C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S54C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S53C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S52C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S51C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S50C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S49C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S48C3 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 820
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.20 LCD Data16 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA16
0x566
15
S15C4
R/W
0
14
S14C4
R/W
0
13
S13C4
R/W
0
12
S12C4
R/W
0
11
S11C4
R/W
0
10
S10C4
R/W
0
9
S09C4
R/W
0
8
S08C4
R/W
0
7
S07C4
R/W
0
6
S06C4
R/W
0
5
S05C4
R/W
0
4
S04C4
R/W
0
3
S03C4
R/W
0
2
S02C4
R/W
0
1
S01C4
R/W
0
0
S00C4
R/W
0
Bit 15 – S15C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S14C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S13C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S12C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S11C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S10C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S09C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S08C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 821
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S07C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S06C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S05C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S04C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S03C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S02C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S01C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S00C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 822
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.21 LCD Data17 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA17
0x568
15
S31C4
R/W
0
14
S30C4
R/W
0
13
S29C4
R/W
0
12
S28C4
R/W
0
11
S27C4
R/W
0
10
S26C4
R/W
0
9
S25C4
R/W
0
8
S24C4
R/W
0
7
S23C4
R/W
0
6
S22C4
R/W
0
5
S21C4
R/W
0
4
S20C4
R/W
0
3
S19C4
R/W
0
2
S18C4
R/W
0
1
S17C4
R/W
0
0
S16C4
R/W
0
Bit 15 – S31C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S30C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S29C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S28C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S27C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S26C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S25C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S24C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 823
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S23C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S22C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S21C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S20C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S19C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S18C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S17C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S16C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 824
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.22 LCD Data18 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA18
0x56A
15
S47C4
R/W
0
14
S46C4
R/W
0
13
S45C4
R/W
0
12
S44C4
R/W
0
11
S43C4
R/W
0
10
S42C4
R/W
0
9
S41C4
R/W
0
8
S40C4
R/W
0
7
S39C4
R/W
0
6
S38C4
R/W
0
5
S37C4
R/W
0
4
S36C4
R/W
0
3
S35C4
R/W
0
2
S34C4
R/W
0
1
S33C4
R/W
0
0
S32C4
R/W
0
Bit 15 – S47C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S46C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S45C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S44C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S43C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S42C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S41C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S40C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 825
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S39C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S38C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S37C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S36C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S35C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S34C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S33C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S32C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 826
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.23 LCD Data19 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA19
0x56C
15
S63C4
R/W
0
14
S62C4
R/W
0
13
S61C4
R/W
0
12
S60C4
R/W
0
11
S59C4
R/W
0
10
S58C4
R/W
0
9
S57C4
R/W
0
8
S56C4
R/W
0
7
S55C4
R/W
0
6
S54C4
R/W
0
5
S53C4
R/W
0
4
S52C4
R/W
0
3
S51C4
R/W
0
2
S50C4
R/W
0
1
S49C4
R/W
0
0
S48C4
R/W
0
Bit 15 – S63C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S62C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S61C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S60C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S59C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S58C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S57C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S56C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 827
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S55C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S54C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S53C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S52C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S51C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S50C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S49C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S48C4 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 828
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.24 LCD Data20 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA20
0x56E
15
S15C5
R/W
0
14
S14C5
R/W
0
13
S13C5
R/W
0
12
S12C5
R/W
0
11
S11C5
R/W
0
10
S10C5
R/W
0
9
S09C5
R/W
0
8
S08C5
R/W
0
7
S07C5
R/W
0
6
S06C5
R/W
0
5
S05C5
R/W
0
4
S04C5
R/W
0
3
S03C5
R/W
0
2
S02C5
R/W
0
1
S01C5
R/W
0
0
S00C5
R/W
0
Bit 15 – S15C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S14C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S13C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S12C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S11C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S10C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S09C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S08C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 829
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S07C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S06C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S05C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S04C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S03C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S02C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S01C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S00C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 830
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.25 LCD Data21 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA21
0x570
15
S31C5
R/W
0
14
S30C5
R/W
0
13
S29C5
R/W
0
12
S28C5
R/W
0
11
S27C5
R/W
0
10
S26C5
R/W
0
9
S25C5
R/W
0
8
S24C5
R/W
0
7
S23C5
R/W
0
6
S22C5
R/W
0
5
S21C5
R/W
0
4
S20C5
R/W
0
3
S19C5
R/W
0
2
S18C5
R/W
0
1
S17C5
R/W
0
0
S16C5
R/W
0
Bit 15 – S31C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S30C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S29C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S28C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S27C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S26C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S25C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S24C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 831
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S23C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S22C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S21C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S20C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S19C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S18C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S17C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S16C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 832
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.26 LCD Data22 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA22
0x572
15
S47C5
R/W
0
14
S46C5
R/W
0
13
S45C5
R/W
0
12
S44C5
R/W
0
11
S43C5
R/W
0
10
S42C5
R/W
0
9
S41C5
R/W
0
8
S40C5
R/W
0
7
S39C5
R/W
0
6
S38C5
R/W
0
5
S37C5
R/W
0
4
S36C5
R/W
0
3
S35C5
R/W
0
2
S34C5
R/W
0
1
S33C5
R/W
0
0
S32C5
R/W
0
Bit 15 – S47C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S46C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S45C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S44C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S43C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S42C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S41C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S40C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 833
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S39C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S38C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S37C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S36C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S35C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S34C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S33C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S32C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 834
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.27 LCD Data23 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA23
0x574
15
S63C5
R/W
0
14
S62C5
R/W
0
13
S61C5
R/W
0
12
S60C5
R/W
0
11
S59C5
R/W
0
10
S58C5
R/W
0
9
S57C5
R/W
0
8
S56C5
R/W
0
7
S55C5
R/W
0
6
S54C5
R/W
0
5
S53C5
R/W
0
4
S52C5
R/W
0
3
S51C5
R/W
0
2
S50C5
R/W
0
1
S49C5
R/W
0
0
S48C5
R/W
0
Bit 15 – S63C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S62C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S61C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S60C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S59C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S58C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S57C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S56C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 835
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S55C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S54C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S53C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S52C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S51C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S50C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S49C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S48C5 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 836
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.28 LCD Data24 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA24
0x576
15
S15C6
R/W
0
14
S14C6
R/W
0
13
S13C6
R/W
0
12
S12C6
R/W
0
11
S11C6
R/W
0
10
S10C6
R/W
0
9
S09C6
R/W
0
8
S08C6
R/W
0
7
S07C6
R/W
0
6
S06C6
R/W
0
5
S05C6
R/W
0
4
S04C6
R/W
0
3
S03C6
R/W
0
2
S02C6
R/W
0
1
S01C6
R/W
0
0
S00C6
R/W
0
Bit 15 – S15C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S14C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S13C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S12C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S11C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S10C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S09C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S08C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 837
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S07C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S06C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S05C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S04C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S03C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S02C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S01C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S00C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 838
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.29 LCD Data25 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA25
0x578
15
S31C6
R/W
0
14
S30C6
R/W
0
13
S29C6
R/W
0
12
S28C6
R/W
0
11
S27C6
R/W
0
10
S26C6
R/W
0
9
S25C6
R/W
0
8
S24C6
R/W
0
7
S23C6
R/W
0
6
S22C6
R/W
0
5
S21C6
R/W
0
4
S20C6
R/W
0
3
S19C6
R/W
0
2
S18C6
R/W
0
1
S17C6
R/W
0
0
S16C6
R/W
0
Bit 15 – S31C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S30C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S29C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S28C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S27C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S26C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S25C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S24C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 839
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S23C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S22C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S21C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S20C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S19C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S18C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S17C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S16C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 840
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.30 LCD Data26 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA26
0x57A
15
S47C6
R/W
0
14
S46C6
R/W
0
13
S45C6
R/W
0
12
S44C6
R/W
0
11
S43C6
R/W
0
10
S42C6
R/W
0
9
S41C6
R/W
0
8
S40C6
R/W
0
7
S39C6
R/W
0
6
S38C6
R/W
0
5
S37C6
R/W
0
4
S36C6
R/W
0
3
S35C6
R/W
0
2
S34C6
R/W
0
1
S33C6
R/W
0
0
S32C6
R/W
0
Bit 15 – S47C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S46C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S45C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S44C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S43C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S42C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S41C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S40C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 841
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S39C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S38C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S37C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S36C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S35C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S34C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S33C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S32C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 842
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.31 LCD Data27 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA27
0x57C
15
S63C6
R/W
0
14
S62C6
R/W
0
13
S61C6
R/W
0
12
S60C6
R/W
0
11
S59C6
R/W
0
10
S58C6
R/W
0
9
S57C6
R/W
0
8
S56C6
R/W
0
7
S55C6
R/W
0
6
S54C6
R/W
0
5
S53C6
R/W
0
4
S52C6
R/W
0
3
S51C6
R/W
0
2
S50C6
R/W
0
1
S49C6
R/W
0
0
S48C6
R/W
0
Bit 15 – S63C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S62C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S61C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S60C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S59C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S58C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S57C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S56C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 843
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S55C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S54C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S53C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S52C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S51C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S50C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S49C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S48C6 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 844
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.32 LCD Data28 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA28
0x57E
15
S15C7
R/W
0
14
S14C7
R/W
0
13
S13C7
R/W
0
12
S12C7
R/W
0
11
S11C7
R/W
0
10
S10C7
R/W
0
9
S09C7
R/W
0
8
S08C7
R/W
0
7
S07C7
R/W
0
6
S06C7
R/W
0
5
S05C7
R/W
0
4
S04C7
R/W
0
3
S03C7
R/W
0
2
S02C7
R/W
0
1
S01C7
R/W
0
0
S00C7
R/W
0
Bit 15 – S15C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S14C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S13C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S12C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S11C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S10C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S09C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S08C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 845
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S07C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S06C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S05C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S04C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S03C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S02C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S01C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S00C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 846
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.33 LCD Data29 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA29
0x580
15
S31C7
R/W
0
14
S30C7
R/W
0
13
S29C7
R/W
0
12
S28C7
R/W
0
11
S27C7
R/W
0
10
S26C7
R/W
0
9
S25C7
R/W
0
8
S24C7
R/W
0
7
S23C7
R/W
0
6
S22C7
R/W
0
5
S21C7
R/W
0
4
S20C7
R/W
0
3
S19C7
R/W
0
2
S18C7
R/W
0
1
S17C7
R/W
0
0
S16C7
R/W
0
Bit 15 – S31C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S30C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S29C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S28C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S27C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S26C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S25C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S24C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 847
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S23C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S22C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S21C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S20C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S19C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S18C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S17C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S16C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 848
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.34 LCD Data30 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA30
0x582
15
S47C7
R/W
0
14
S46C7
R/W
0
13
S45C7
R/W
0
12
S44C7
R/W
0
11
S43C7
R/W
0
10
S42C7
R/W
0
9
S41C7
R/W
0
8
S40C7
R/W
0
7
S39C7
R/W
0
6
S38C7
R/W
0
5
S37C7
R/W
0
4
S36C7
R/W
0
3
S35C7
R/W
0
2
S34C7
R/W
0
1
S33C7
R/W
0
0
S32C7
R/W
0
Bit 15 – S47C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S46C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S45C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S44C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S43C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S42C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S41C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S40C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 849
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S39C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S38C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S37C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S36C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S35C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S34C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S33C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S32C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 850
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.35 LCD Data31 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA31
0x584
15
S63C7
R/W
0
14
S62C7
R/W
0
13
S61C7
R/W
0
12
S60C7
R/W
0
11
S59C7
R/W
0
10
S58C7
R/W
0
9
S57C7
R/W
0
8
S56C7
R/W
0
7
S55C7
R/W
0
6
S54C7
R/W
0
5
S53C7
R/W
0
4
S52C7
R/W
0
3
S51C7
R/W
0
2
S50C7
R/W
0
1
S49C7
R/W
0
0
S48C7
R/W
0
Bit 15 – S63C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 14 – S62C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 13 – S61C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 12 – S60C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 11 – S59C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 10 – S58C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 9 – S57C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 8 – S56C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 851
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – S55C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 6 – S54C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 5 – S53C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 4 – S52C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 3 – S51C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 2 – S50C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 1 – S49C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
Bit 0 – S48C7 Segment Enable bit
Value
Description
1
Pixel is on
0
Pixel is off
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 852
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.36 LCD Segment Enable Register 0
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSE0
0x586
15
SE15
R/W
0
14
SE14
R/W
0
13
SE13
R/W
0
12
SE12
R/W
0
11
SE11
R/W
0
10
SE10
R/W
0
9
SE09
R/W
0
8
SE08
R/W
0
7
SE07
R/W
0
6
SE06
R/W
0
5
SE05
R/W
0
4
SE04
R/W
0
3
SE03
R/W
0
2
SE02
R/W
0
1
SE01
R/W
0
0
SE00
R/W
0
Bit 15 – SE15 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 14 – SE14 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 13 – SE13 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 12 – SE12 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 11 – SE11 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 10 – SE10 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 9 – SE09 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 8 – SE08 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 853
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – SE07 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 6 – SE06 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 5 – SE05 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 4 – SE04 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 3 – SE03 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 2 – SE02 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 1 – SE01 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 0 – SE00 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 854
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.37 LCD Segment Enable Register 1
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSE1
0x588
15
SE31
R/W
0
14
SE30
R/W
0
13
SE29
R/W
0
12
SE28
R/W
0
11
SE27
R/W
0
10
SE26
R/W
0
9
SE25
R/W
0
8
SE24
R/W
0
7
SE23
R/W
0
6
SE22
R/W
0
5
SE21
R/W
0
4
SE20
R/W
0
3
SE19
R/W
0
2
SE18
R/W
0
1
SE17
R/W
0
0
SE16
R/W
0
Bit 15 – SE31 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 14 – SE30 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 13 – SE29 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 12 – SE28 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 11 – SE27 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 10 – SE26 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 9 – SE25 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 8 – SE24 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 855
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – SE23 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 6 – SE22 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 5 – SE21 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 4 – SE20 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 3 – SE19 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 2 – SE18 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 1 – SE17 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 0 – SE16 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 856
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.38 LCD Segment Enable Register 2
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSE2
0x58A
15
SE47
R/W
0
14
SE46
R/W
0
13
SE45
R/W
0
12
SE44
R/W
0
11
SE43
R/W
0
10
SE42
R/W
0
9
SE41
R/W
0
8
SE40
R/W
0
7
SE39
R/W
0
6
SE38
R/W
0
5
SE37
R/W
0
4
SE36
R/W
0
3
SE35
R/W
0
2
SE34
R/W
0
1
SE33
R/W
0
0
SE32
R/W
0
Bit 15 – SE47 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 14 – SE46 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 13 – SE45 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 12 – SE44 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 11 – SE43 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 10 – SE42 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 9 – SE41 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 8 – SE40 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 857
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – SE39 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 6 – SE38 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 5 – SE37 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 4 – SE36 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 3 – SE35 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 2 – SE34 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 1 – SE33 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 0 – SE32 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 858
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.39 LCD Segment Enable Register 3
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSE3
0x58C
15
SE63
R/W
0
14
SE62
R/W
0
13
SE61
R/W
0
12
SE60
R/W
0
11
SE59
R/W
0
10
SE58
R/W
0
9
SE57
R/W
0
8
SE56
R/W
0
7
SE55
R/W
0
6
SE54
R/W
0
5
SE53
R/W
0
4
SE52
R/W
0
3
SE51
R/W
0
2
SE50
R/W
0
1
SE49
R/W
0
0
SE48
R/W
0
Bit 15 – SE63 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 14 – SE62 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 13 – SE61 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 12 – SE60 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 11 – SE59 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 10 – SE58 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 9 – SE57 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 8 – SE56 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 859
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 7 – SE55 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 6 – SE54 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 5 – SE53 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 4 – SE52 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 3 – SE51 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 2 – SE50 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 1 – SE49 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
Bit 0 – SE48 Segment Enable bit
Value
Description
1
Segment function of the pin is enabled, digital I/O is disabled
0
Segment function of the pin is disabled, digital I/O is enabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 860
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.40 LCD Charge Pump Control Register
Name:
Offset:
Bit
Access
Reset
Bit
LCDREG
0x58E
15
CPEN
R/W
0
14
13
12
11
10
9
7
6
5
4
3
2
1
Access
Reset
8
0
CLKSEL[1:0]
R/W
R/W
0
0
Bit 15 – CPEN 3.6V Charge Pump Enable bit
Value
Description
1
The regulator generates the highest (3.6V) voltage
0
Highest voltage in the system is supplied externally (AVDD)
Bits 1:0 – CLKSEL[1:0] Regulator Clock Select Control bits
Value
Description
11
SOSC
10
8 MHz FRC
01
32 kHz LPRC
00
Disables regulator and floats regulator voltage output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 861
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.41 LCD Automatic Control Register
Name:
Offset:
LCDACTRL
0x590
Note:
1.
Secondary memory is selected for pixel enable to Blink or Blank when BLINKMODE[1:0] = 01 |
BLANKMODE[1:0] = 01.
2.
3.
Secondary memory is used to store data to display or select the pixel to Blink or Blank.
The FC1 is used when Blink mode is not selected (i.e., BLINKMODE[1:0] = 00 | 11).
4.
The FC2 is used when Blank mode is not selected (i.e., BLANKMODE[1:0] = 00 | 11).
5.
6.
7.
Frame counter selection switchover based on time event.
Pixel will alternate between ON and OFF state at the frequency given by the selected frame counter.
The FC0 is used when secondary memory is not selected with switchover function (i.e., DMSEL[1:0] = 00 or
01).
8.
9.
Blink mode ON state is effective to the pixel when Blank mode is off.
Blink mode OFF state drives ‘0’ to the pixel.
10. One-time Blank continues to Blank until a user changes the Blank mode to enable or disable the enhanced
LCD feature (clears ELCDEN), or SBLANK is clear.
11. In One-Time Blank Configuration mode, the pixel continues to Blink (to alternate between on and off) until the
timer event happens.
Legend: C = Clearable bit
Bit
15
Access
Reset
R/W
0
Bit
7
Access
Reset
R/C
0
14
SMFCS[2:0]
R/W
0
13
12
R/W
0
R/W
0
6
BLANKFCS[2:0]
R/C
0
5
R/C
0
11
BLINKFCS[2:0]
R/W
0
4
3
BLANKMODE[1:0]
R/W
R/W
0
0
10
9
8
BLINKMODE[1:0]
R/W
R/W
0
0
R/W
0
2
1
FCCS[1:0]
R/W
0
R/W
0
0
ELCDEN
R/W
0
Bits 15:13 – SMFCS[2:0] Frame Counter Selection for Data Memory Selection bits(1,2,3,4,5)
When DMSEL[1:0] = 10 (one-time switchover from current display memory to another memory):
Value
Description
001
000
Selects Frame Counter 0 (FC0)
Reserved
When DMSEL[1:0] = 11 (continues to switch over from one memory to another memory):
Value
Description
011
010
Reserved
Selects Frame Counter 0 (FC0), then continues with Frame Counter 1 (FC1) at the frequency
given by the time event
Selects Frame Counter 0 (FC0)
Reserved
001
010
When DMSEL[1:0] = 11 (continues to switch over from one memory to another with a repeated pattern):
Value
Description
111
110
Reserved
Reserved
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 862
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
...........continued
Value
Description
101
100
Reserved
Alternates between FC0 and FC1 at the frequency given by the time event
Bits 12:10 – BLINKFCS[2:0] Frame Counter Selection for Blink Selection bits (BLINKMODE = 01 or 10)(4,5,6,7)
Value
Description
111
Reserved
110
Reserved
101
Reserved
100
Alternates between FC0 and FC1 at the frequency given by the time event (repeated pattern)
011
Reserved
010
Selects Frame Counter 0 (FC0), then continues with Frame Counter 1 (FC1) at the frequency given by
the time event
001
Selects Frame Counter 1 (FC1)
000
Reserved
Bits 9:8 – BLINKMODE[1:0] Blink Mode bits(8,9)
Value
Description
11
Reserved
10
Blink mode is enabled with all pixels
01
Blink mode is enabled with selected pixels (when DMSEL[1:0] = 00)
00
Blink mode is disabled
Bits 7:5 – BLANKFCS[2:0] Blank Operation Selection from Frame Counter Selection bits(3,5,6,7,10,11)
(when BLANKMODE[1:0] = 01 or 10)
Value
Description
111
Reserved
110
One-time Blank selects Frame Counter 2 (FC2) by the time event(10,11)
101
Reserved
100
Alternates between FC0 and FC1 at the frequency given by the time event (repeated pattern)
011
Reserved
010
Selects Frame Counter 0 (FC0), then continues with Frame Counter 1 (FC1) at the frequency given by
the time event
001
Selects Frame Counter 2 (FC2)
000
Reserved
Bits 4:3 – BLANKMODE[1:0] Blank Mode bits
Value
Description
11
Reserved
10
Blank mode is enabled with all pixels
01
Blank mode is enabled with selected pixels (when DMSEL[1:0] = 00)
00
Blank mode is disabled
Bits 2:1 – FCCS[1:0] Clock Source bits
Value
Description
11
CLC2
10
CLC1
01
RTCC
00
LCD clock
Bit 0 – ELCDEN Enhancement LCD Enable bit
Value
Description
1
Enhancement function is enabled
0
Enhancement function is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 863
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.42 LCD Automatic Status Register
Name:
Offset:
LCDASTAT
0x592
Note:
1.
Reflects BLANKFCS[2:0] = 110 status.
2.
3.
It is the user’s responsibility to clear the bit to make LCD active.
This bit is cleared by hardware when user changes Blank mode = 0 or clears the ELCDEN bit.
4.
5.
This flag bit is used to generate an enhanced feature interrupt.
This bit is effective when SMEMEN = 1; otherwise, the write follows the Write Allow bit, WA (LCDPS[4]).
6.
7.
When the PMLOCK bit is set, it does not allow the user to write to the primary memory.
When the SMLOCK bit is set, it does not allow user to write to the secondary memory.
Legend: C = Clearable bit
Bit
15
14
SBLANK
R/W
0
13
SMEMACT
R/W
0
12
PMEMACT
R/W
0
11
TEVENTO
R/C
0
10
FC2O
R/W
0
9
FC1O
R/W
0
7
SMLOCK
R/W
0
6
SMCLEAR
R/W
0
5
PMLOCK
R/W
0
4
PMCLEAR
R/W
0
3
SMEMEN
R/W
0
2
PMEMDIS
R/W
0
1
Access
Reset
Bit
Access
Reset
8
FC0O
R/W
0
0
DMSEL[1:0]
R/W
R/W
0
0
Bit 14 – SBLANK Blank Status bit(1,2,3,4)
Value
Description
1
Pixels are in continuous Blank
0
Pixels are not in continuous Blank
Bit 13 – SMEMACT Secondary Memory Active bit
Value
Description
1
Data display is from secondary memory
0
Data display is not from secondary memory
Bit 12 – PMEMACT Primary Memory Active bit
Value
Description
1
Data display is from primary memory
0
Data display is not from primary memory
Bit 11 – TEVENTO Time Event Overflow bit
Value
Description
1
This flag is set when the time event overflows
0
Time event does not overflow
Bit 10 – FC2O Frame Counter 2 Overflow bit
Value
Description
1
This flag is set when Frame Counter 2 overflows
0
Frame Counter 2 does not overflow
Bit 9 – FC1O Frame Counter 1 Overflow bit
Value
Description
1
This flag is set when Frame Counter 1 overflows
0
Frame Counter 1 does not overflow
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 864
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 8 – FC0O Frame Counter 0 Overflow bit
Value
Description
1
This flag is set when Frame Counter 0 overflows
0
Frame Counter 0 does not overflow
Bit 7 – SMLOCK Secondary Memory Lock Enable bit(7)
Value
Description
1
Secondary memory is locked
0
Secondary memory is unlocked
Bit 6 – SMCLEAR Secondary Memory Clear Enable bit
Value
Description
1
Writing a ‘1’ to this bit clears secondary memory immediately
0
Writing a ‘0’ to this bit has no effect
Bit 5 – PMLOCK Primary Memory Lock Enable bit(5,6)
Value
Description
1
Primary memory is locked
0
Primary memory is unlocked
Bit 4 – PMCLEAR Primary Memory Clear Enable bit
Value
Description
1
Writing a ‘1’ to this bit clears primary memory immediately
0
Writing a ‘0’ to this bit has no effect
Bit 3 – SMEMEN Secondary Memory Clear Enable bit
Value
Description
1
Secondary memory is enabled
0
Secondary memory is disabled
Bit 2 – PMEMDIS Primary Memory Disable bit
Value
Description
1
Primary memory is disabled
0
Primary memory is enabled
Bits 1:0 – DMSEL[1:0] Data Memory Selection bits
Value
Description
11
Continues alternating selection between primary and secondary memories based on SMFCS[2:0]
10
Alternates selection between primary and secondary memories on SMFCS[2:0]
01
Selects secondary memory as display memory
00
Selects primary memory as display memory
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 865
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.43 LCD Frame Counter 0 Register
Name:
Offset:
LCDFC0
0x594
Note:
1.
2.
Bit
It is recommended to make the FCx values to be multiples of the frame frequency.
FCx value must be greater than two.
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
FC0[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
FC0[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – FC0[15:0] Time Base Value bits(1,2)
These bits define the overflow value.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 866
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.44 LCD Frame Counter 1 Register
Name:
Offset:
LCDFC1
0x596
Note:
1.
2.
Bit
It is recommended to make the FCx values to be multiples of the frame frequency.
FCx value must be greater than two.
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
FC1[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
FC1[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – FC1[15:0] Time Base Value bits(1,2)
These bits define the overflow value.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 867
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.45 LCD Frame Counter 2 Register
Name:
Offset:
LCDFC2
0x598
Note:
1.
2.
Bit
It is recommended to make the FCx values to be multiples of the frame frequency.
FCx value must be greater than two.
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
FC2[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
FC2[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – FC2[15:0] Time Base Value bits(1,2)
These bits define the overflow value.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 868
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.46 LCD Time Event Selection Register
Name:
Offset:
LCDEVNT
0x59A
Note:
1.
2.
3.
Bit
Access
Reset
Bit
Access
Reset
The TEVENT value should be a multiple of the frame frequency.
The TEVENT value should be greater than the FCx value.
The overflow is (TEVENT * 16 ±1); the TEVENT overflow gets ±1 based on the TEVENT ratio with the FCx
overflow.
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
TEVENT[15:8]
R/W
R/W
0
0
4
3
TEVENT[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TEVENT[15:0] Time Base Event Value bits(1,2,3)
These bits define the time event value.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 869
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.47 LCD SData Register 0
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA0
0x59C
15
S15C
R/W
0
14
S14C
R/W
0
13
S13C
R/W
0
12
S12C
R/W
0
11
S11C
R/W
0
10
S10C
R/W
0
9
S09C
R/W
0
8
S08C
R/W
0
7
S07C
R/W
0
6
S06C
R/W
0
5
S05C
R/W
0
4
S04C
R/W
0
3
S03C
R/W
0
2
S02C
R/W
0
1
S01C
R/W
0
0
S00C
R/W
0
Bit 15 – S15C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S14C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S13C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S12C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 870
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S11C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S10C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S09C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S08C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 871
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S07C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S06C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S05C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S04C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 872
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S03C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S02C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S01C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S00C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 873
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.48 LCD SData Register 1
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA1
0x59E
15
S31C
R/W
0
14
S30C
R/W
0
13
S29C
R/W
0
12
S28C
R/W
0
11
S27C
R/W
0
10
S26C
R/W
0
9
S25C
R/W
0
8
S24C
R/W
0
7
S23C
R/W
0
6
S22C
R/W
0
5
S21C
R/W
0
4
S20C
R/W
0
3
S19C
R/W
0
2
S18C
R/W
0
1
S17C
R/W
0
0
S16C
R/W
0
Bit 15 – S31C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S30C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S29C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S28C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 874
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S27C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S26C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S25C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S24C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 875
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S23C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S22C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S21C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S20C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 876
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S19C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S18C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S17C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S16C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 877
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.49 LCD SData Register 2
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA2
0x5A0
15
S47C
R/W
0
14
S46C
R/W
0
13
S45C
R/W
0
12
S44C
R/W
0
11
S43C
R/W
0
10
S42C
R/W
0
9
S41C
R/W
0
8
S40C
R/W
0
7
S39C
R/W
0
6
S38C
R/W
0
5
S37C
R/W
0
4
S36C
R/W
0
3
S35C
R/W
0
2
S34C
R/W
0
1
S33C
R/W
0
0
S32C
R/W
0
Bit 15 – S47C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S46C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S45C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S44C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 878
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S43C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S42C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S41C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S40C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 879
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S39C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S38C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S37C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S36C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 880
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S35C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S34C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S33C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S32C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 881
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.50 LCD SData Register 3
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA3
0x5A2
15
S63C
R/W
0
14
S62C
R/W
0
13
S61C
R/W
0
12
S60C
R/W
0
11
S59C
R/W
0
10
S58C
R/W
0
9
S57C
R/W
0
8
S56C
R/W
0
7
S55C
R/W
0
6
S54C
R/W
0
5
S53C
R/W
0
4
S52C
R/W
0
3
S51C
R/W
0
2
S50C
R/W
0
1
S49C
R/W
0
0
S48C
R/W
0
Bit 15 – S63C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S62C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S61C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S60C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 882
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S59C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S58C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S57C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S56C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 883
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S55C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S54C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S53C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S52C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 884
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S51C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S50C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S49C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S48C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 885
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.51 LCD SData Register 4
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA4
0x5A4
15
S15C
R/W
0
14
S14C
R/W
0
13
S13C
R/W
0
12
S12C
R/W
0
11
S11C
R/W
0
10
S10C
R/W
0
9
S09C
R/W
0
8
S08C
R/W
0
7
S07C
R/W
0
6
S06C
R/W
0
5
S05C
R/W
0
4
S04C
R/W
0
3
S03C
R/W
0
2
S02C
R/W
0
1
S01C
R/W
0
0
S00C
R/W
0
Bit 15 – S15C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S14C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S13C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S12C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 886
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S11C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S10C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S09C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S08C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 887
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S07C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S06C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S05C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S04C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 888
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S03C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S02C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S01C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S00C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 889
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.52 LCD SData Register 5
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA5
0x5A6
15
S31C
R/W
0
14
S30C
R/W
0
13
S29C
R/W
0
12
S28C
R/W
0
11
S27C
R/W
0
10
S26C
R/W
0
9
S25C
R/W
0
8
S24C
R/W
0
7
S23C
R/W
0
6
S22C
R/W
0
5
S21C
R/W
0
4
S20C
R/W
0
3
S19C
R/W
0
2
S18C
R/W
0
1
S17C
R/W
0
0
S16C
R/W
0
Bit 15 – S31C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S30C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S29C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S28C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 890
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S27C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S26C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S25C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S24C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 891
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S23C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S22C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S21C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S20C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 892
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S19C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S18C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S17C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S16C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 893
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.53 LCD SData Register 6
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA6
0x5A8
15
S47C
R/W
0
14
S46C
R/W
0
13
S45C
R/W
0
12
S44C
R/W
0
11
S43C
R/W
0
10
S42C
R/W
0
9
S41C
R/W
0
8
S40C
R/W
0
7
S39C
R/W
0
6
S38C
R/W
0
5
S37C
R/W
0
4
S36C
R/W
0
3
S35C
R/W
0
2
S34C
R/W
0
1
S33C
R/W
0
0
S32C
R/W
0
Bit 15 – S47C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S46C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S45C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S44C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 894
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S43C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S42C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S41C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S40C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 895
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S39C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S38C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S37C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S36C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 896
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S35C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S34C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S33C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S32C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 897
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.54 LCD SData Register 7
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA7
0x5AA
15
S63C
R/W
0
14
S62C
R/W
0
13
S61C
R/W
0
12
S60C
R/W
0
11
S59C
R/W
0
10
S58C
R/W
0
9
S57C
R/W
0
8
S56C
R/W
0
7
S55C
R/W
0
6
S54C
R/W
0
5
S53C
R/W
0
4
S52C
R/W
0
3
S51C
R/W
0
2
S50C
R/W
0
1
S49C
R/W
0
0
S48C
R/W
0
Bit 15 – S63C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S62C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S61C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S60C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 898
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S59C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S58C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S57C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S56C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 899
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S55C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S54C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S53C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S52C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 900
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S51C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S50C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S49C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S48C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 901
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.55 LCD SData Register 8
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA8
0x5AC
15
S15C
R/W
0
14
S14C
R/W
0
13
S13C
R/W
0
12
S12C
R/W
0
11
S11C
R/W
0
10
S10C
R/W
0
9
S09C
R/W
0
8
S08C
R/W
0
7
S07C
R/W
0
6
S06C
R/W
0
5
S05C
R/W
0
4
S04C
R/W
0
3
S03C
R/W
0
2
S02C
R/W
0
1
S01C
R/W
0
0
S00C
R/W
0
Bit 15 – S15C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S14C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S13C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S12C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 902
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S11C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S10C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S09C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S08C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 903
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S07C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S06C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S05C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S04C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 904
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S03C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S02C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S01C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S00C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 905
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.56 LCD SData Register 9
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA9
0x5AE
15
S31C
R/W
0
14
S30C
R/W
0
13
S29C
R/W
0
12
S28C
R/W
0
11
S27C
R/W
0
10
S26C
R/W
0
9
S25C
R/W
0
8
S24C
R/W
0
7
S23C
R/W
0
6
S22C
R/W
0
5
S21C
R/W
0
4
S20C
R/W
0
3
S19C
R/W
0
2
S18C
R/W
0
1
S17C
R/W
0
0
S16C
R/W
0
Bit 15 – S31C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S30C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S29C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S28C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 906
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S27C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S26C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S25C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S24C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 907
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S23C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S22C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S21C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S20C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 908
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S19C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S18C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S17C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S16C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 909
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.57 LCD SData Register 10
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA10
0x5B0
15
S47C
R/W
0
14
S46C
R/W
0
13
S45C
R/W
0
12
S44C
R/W
0
11
S43C
R/W
0
10
S42C
R/W
0
9
S41C
R/W
0
8
S40C
R/W
0
7
S39C
R/W
0
6
S38C
R/W
0
5
S37C
R/W
0
4
S36C
R/W
0
3
S35C
R/W
0
2
S34C
R/W
0
1
S33C
R/W
0
0
S32C
R/W
0
Bit 15 – S47C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S46C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S45C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S44C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 910
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S43C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S42C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S41C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S40C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 911
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S39C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S38C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S37C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S36C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 912
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S35C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S34C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S33C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S32C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 913
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.58 LCD SData Register 11
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA11
0x5B2
15
S63C
R/W
0
14
S62C
R/W
0
13
S61C
R/W
0
12
S60C
R/W
0
11
S59C
R/W
0
10
S58C
R/W
0
9
S57C
R/W
0
8
S56C
R/W
0
7
S55C
R/W
0
6
S54C
R/W
0
5
S53C
R/W
0
4
S52C
R/W
0
3
S51C
R/W
0
2
S50C
R/W
0
1
S49C
R/W
0
0
S48C
R/W
0
Bit 15 – S63C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S62C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S61C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S60C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 914
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S59C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S58C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S57C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S56C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 915
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S55C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S54C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S53C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S52C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 916
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S51C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S50C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S49C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S48C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 917
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.59 LCD SData Register 12
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA12
0x5B4
15
S15C
R/W
0
14
S14C
R/W
0
13
S13C
R/W
0
12
S12C
R/W
0
11
S11C
R/W
0
10
S10C
R/W
0
9
S09C
R/W
0
8
S08C
R/W
0
7
S07C
R/W
0
6
S06C
R/W
0
5
S05C
R/W
0
4
S04C
R/W
0
3
S03C
R/W
0
2
S02C
R/W
0
1
S01C
R/W
0
0
S00C
R/W
0
Bit 15 – S15C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S14C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S13C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S12C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 918
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S11C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S10C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S09C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S08C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 919
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S07C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S06C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S05C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S04C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 920
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S03C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S02C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S01C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S00C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 921
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.60 LCD SData Register 13
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA13
0x5B6
15
S31C
R/W
0
14
S30C
R/W
0
13
S29C
R/W
0
12
S28C
R/W
0
11
S27C
R/W
0
10
S26C
R/W
0
9
S25C
R/W
0
8
S24C
R/W
0
7
S23C
R/W
0
6
S22C
R/W
0
5
S21C
R/W
0
4
S20C
R/W
0
3
S19C
R/W
0
2
S18C
R/W
0
1
S17C
R/W
0
0
S16C
R/W
0
Bit 15 – S31C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S30C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S29C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S28C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 922
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S27C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S26C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S25C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S24C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 923
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S23C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S22C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S21C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S20C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 924
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S19C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S18C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S17C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S16C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 925
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.61 LCD SData Register 14
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA14
0x5B8
15
S47C
R/W
0
14
S46C
R/W
0
13
S45C
R/W
0
12
S44C
R/W
0
11
S43C
R/W
0
10
S42C
R/W
0
9
S41C
R/W
0
8
S40C
R/W
0
7
S39C
R/W
0
6
S38C
R/W
0
5
S37C
R/W
0
4
S36C
R/W
0
3
S35C
R/W
0
2
S34C
R/W
0
1
S33C
R/W
0
0
S32C
R/W
0
Bit 15 – S47C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S46C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S45C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S44C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 926
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S43C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S42C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S41C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S40C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 927
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S39C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S38C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S37C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S36C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 928
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S35C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S34C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S33C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S32C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 929
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.62 LCD SData Register 15
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA15
0x5BA
15
S63C
R/W
0
14
S62C
R/W
0
13
S61C
R/W
0
12
S60C
R/W
0
11
S59C
R/W
0
10
S58C
R/W
0
9
S57C
R/W
0
8
S56C
R/W
0
7
S55C
R/W
0
6
S54C
R/W
0
5
S53C
R/W
0
4
S52C
R/W
0
3
S51C
R/W
0
2
S50C
R/W
0
1
S49C
R/W
0
0
S48C
R/W
0
Bit 15 – S63C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S62C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S61C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S60C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 930
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S59C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S58C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S57C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S56C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 931
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S55C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S54C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S53C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S52C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 932
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S51C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S50C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S49C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S48C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 933
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.63 LCD SData Register 16
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA16
0x5BC
15
S15C
R/W
0
14
S14C
R/W
0
13
S13C
R/W
0
12
S12C
R/W
0
11
S11C
R/W
0
10
S10C
R/W
0
9
S09C
R/W
0
8
S08C
R/W
0
7
S07C
R/W
0
6
S06C
R/W
0
5
S05C
R/W
0
4
S04C
R/W
0
3
S03C
R/W
0
2
S02C
R/W
0
1
S01C
R/W
0
0
S00C
R/W
0
Bit 15 – S15C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S14C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S13C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S12C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 934
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S11C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S10C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S09C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S08C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 935
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S07C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S06C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S05C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S04C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 936
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S03C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S02C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S01C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S00C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 937
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.64 LCD SData Register 17
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA17
0x5BE
15
S31C
R/W
0
14
S30C
R/W
0
13
S29C
R/W
0
12
S28C
R/W
0
11
S27C
R/W
0
10
S26C
R/W
0
9
S25C
R/W
0
8
S24C
R/W
0
7
S23C
R/W
0
6
S22C
R/W
0
5
S21C
R/W
0
4
S20C
R/W
0
3
S19C
R/W
0
2
S18C
R/W
0
1
S17C
R/W
0
0
S16C
R/W
0
Bit 15 – S31C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S30C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S29C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S28C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 938
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S27C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S26C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S25C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S24C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 939
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S23C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S22C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S21C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S20C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 940
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S19C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S18C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S17C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S16C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 941
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.65 LCD SData Register 18
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA18
0x5C0
15
S47C
R/W
0
14
S46C
R/W
0
13
S45C
R/W
0
12
S44C
R/W
0
11
S43C
R/W
0
10
S42C
R/W
0
9
S41C
R/W
0
8
S40C
R/W
0
7
S39C
R/W
0
6
S38C
R/W
0
5
S37C
R/W
0
4
S36C
R/W
0
3
S35C
R/W
0
2
S34C
R/W
0
1
S33C
R/W
0
0
S32C
R/W
0
Bit 15 – S47C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S46C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S45C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S44C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 942
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S43C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S42C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S41C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S40C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 943
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S39C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S38C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S37C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S36C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 944
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S35C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S34C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S33C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S32C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 945
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.66 LCD SData Register 19
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA19
0x5C2
15
S63C
R/W
0
14
S62C
R/W
0
13
S61C
R/W
0
12
S60C
R/W
0
11
S59C
R/W
0
10
S58C
R/W
0
9
S57C
R/W
0
8
S56C
R/W
0
7
S55C
R/W
0
6
S54C
R/W
0
5
S53C
R/W
0
4
S52C
R/W
0
3
S51C
R/W
0
2
S50C
R/W
0
1
S49C
R/W
0
0
S48C
R/W
0
Bit 15 – S63C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S62C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S61C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S60C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 946
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S59C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S58C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S57C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S56C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 947
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S55C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S54C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S53C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S52C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 948
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S51C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S50C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S49C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S48C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 949
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.67 LCD SData Register 20
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA20
0x5C4
15
S15C
R/W
0
14
S14C
R/W
0
13
S13C
R/W
0
12
S12C
R/W
0
11
S11C
R/W
0
10
S10C
R/W
0
9
S09C
R/W
0
8
S08C
R/W
0
7
S07C
R/W
0
6
S06C
R/W
0
5
S05C
R/W
0
4
S04C
R/W
0
3
S03C
R/W
0
2
S02C
R/W
0
1
S01C
R/W
0
0
S00C
R/W
0
Bit 15 – S15C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S14C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S13C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S12C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 950
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S11C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S10C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S09C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S08C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 951
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S07C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S06C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S05C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S04C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 952
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S03C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S02C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S01C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S00C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 953
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.68 LCD SData Register 21
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA21
0x5C6
15
S31C
R/W
0
14
S30C
R/W
0
13
S29C
R/W
0
12
S28C
R/W
0
11
S27C
R/W
0
10
S26C
R/W
0
9
S25C
R/W
0
8
S24C
R/W
0
7
S23C
R/W
0
6
S22C
R/W
0
5
S21C
R/W
0
4
S20C
R/W
0
3
S19C
R/W
0
2
S18C
R/W
0
1
S17C
R/W
0
0
S16C
R/W
0
Bit 15 – S31C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S30C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S29C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S28C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 954
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S27C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S26C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S25C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S24C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 955
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S23C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S22C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S21C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S20C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 956
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S19C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S18C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S17C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S16C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 957
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.69 LCD SData Register 22
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA22
0x5C8
15
S47C
R/W
0
14
S46C
R/W
0
13
S45C
R/W
0
12
S44C
R/W
0
11
S43C
R/W
0
10
S42C
R/W
0
9
S41C
R/W
0
8
S40C
R/W
0
7
S39C
R/W
0
6
S38C
R/W
0
5
S37C
R/W
0
4
S36C
R/W
0
3
S35C
R/W
0
2
S34C
R/W
0
1
S33C
R/W
0
0
S32C
R/W
0
Bit 15 – S47C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S46C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S45C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S44C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 958
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S43C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S42C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S41C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S40C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 959
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S39C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S38C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S37C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S36C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 960
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S35C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S34C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S33C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S32C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 961
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.70 LCD SData Register 23
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA23
0x5CA
15
S63C
R/W
0
14
S62C
R/W
0
13
S61C
R/W
0
12
S60C
R/W
0
11
S59C
R/W
0
10
S58C
R/W
0
9
S57C
R/W
0
8
S56C
R/W
0
7
S55C
R/W
0
6
S54C
R/W
0
5
S53C
R/W
0
4
S52C
R/W
0
3
S51C
R/W
0
2
S50C
R/W
0
1
S49C
R/W
0
0
S48C
R/W
0
Bit 15 – S63C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S62C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S61C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S60C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 962
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S59C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S58C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S57C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S56C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 963
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S55C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S54C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S53C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S52C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 964
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S51C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S50C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S49C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S48C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 965
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.71 LCD SData Register 24
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA24
0x5CC
15
S15C
R/W
0
14
S14C
R/W
0
13
S13C
R/W
0
12
S12C
R/W
0
11
S11C
R/W
0
10
S10C
R/W
0
9
S09C
R/W
0
8
S08C
R/W
0
7
S07C
R/W
0
6
S06C
R/W
0
5
S05C
R/W
0
4
S04C
R/W
0
3
S03C
R/W
0
2
S02C
R/W
0
1
S01C
R/W
0
0
S00C
R/W
0
Bit 15 – S15C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S14C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S13C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S12C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 966
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S11C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S10C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S09C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S08C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 967
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S07C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S06C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S05C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S04C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 968
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S03C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S02C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S01C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S00C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 969
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.72 LCD SData Register 25
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA25
0x5CE
15
S31C
R/W
0
14
S30C
R/W
0
13
S29C
R/W
0
12
S28C
R/W
0
11
S27C
R/W
0
10
S26C
R/W
0
9
S25C
R/W
0
8
S24C
R/W
0
7
S23C
R/W
0
6
S22C
R/W
0
5
S21C
R/W
0
4
S20C
R/W
0
3
S19C
R/W
0
2
S18C
R/W
0
1
S17C
R/W
0
0
S16C
R/W
0
Bit 15 – S31C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S30C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S29C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S28C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 970
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S27C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S26C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S25C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S24C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 971
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S23C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S22C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S21C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S20C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 972
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S19C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S18C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S17C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S16C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 973
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.73 LCD SData26 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDDATA26
0x5D0
15
S47C6
R/W
0
14
S46C6
R/W
0
13
S45C6
R/W
0
12
S44C6
R/W
0
11
S43C6
R/W
0
10
S42C6
R/W
0
9
S41C6
R/W
0
8
S40C6
R/W
0
7
S39C6
R/W
0
6
S38C6
R/W
0
5
S37C6
R/W
0
4
S36C6
R/W
0
3
S35C6
R/W
0
2
S34C6
R/W
0
1
S33C6
R/W
0
0
S32C6
R/W
0
Bit 15 – S47C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
Bit 14 – S46C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
Bit 13 – S45C6 Pixel Blink/Blank Enable bits
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
Bit 12 – S44C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
Bit 11 – S43C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
Bit 10 – S42C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 974
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
1
0
Description
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Bit 9 – S41C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
Bit 8 – S40C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
Bit 7 – S39C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
Bit 6 – S38C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
Bit 5 – S37C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
Bit 4 – S36C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
Bit 3 – S35C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 975
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 2 – S34C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
Bit 1 – S33C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
Bit 0 – S32C6 Pixel Blink/Blank Enable bit
If BLINKMODE = 01 or BLANKMODE = 01
Value
Description
1
Pixel is selected for Blink or Blank
0
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 976
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.74 LCD SData Register 27
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA27
0x5D2
15
S63C
R/W
0
14
S62C
R/W
0
13
S61C
R/W
0
12
S60C
R/W
0
11
S59C
R/W
0
10
S58C
R/W
0
9
S57C
R/W
0
8
S56C
R/W
0
7
S55C
R/W
0
6
S54C
R/W
0
5
S53C
R/W
0
4
S52C
R/W
0
3
S51C
R/W
0
2
S50C
R/W
0
1
S49C
R/W
0
0
S48C
R/W
0
Bit 15 – S63C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S62C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S61C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S60C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 977
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S59C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S58C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S57C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S56C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 978
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S55C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S54C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S53C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S52C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 979
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S51C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S50C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S49C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S48C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 980
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.75 LCD SData Register 28
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA28
0x5D4
15
S15C
R/W
0
14
S14C
R/W
0
13
S13C
R/W
0
12
S12C
R/W
0
11
S11C
R/W
0
10
S10C
R/W
0
9
S09C
R/W
0
8
S08C
R/W
0
7
S07C
R/W
0
6
S06C
R/W
0
5
S05C
R/W
0
4
S04C
R/W
0
3
S03C
R/W
0
2
S02C
R/W
0
1
S01C
R/W
0
0
S00C
R/W
0
Bit 15 – S15C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S14C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S13C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S12C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 981
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S11C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S10C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S09C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S08C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 982
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S07C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S06C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S05C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S04C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 983
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S03C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S02C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S01C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S00C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 984
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.76 LCD SData Register 29
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA29
0x5D6
15
S31C
R/W
0
14
S30C
R/W
0
13
S29C
R/W
0
12
S28C
R/W
0
11
S27C
R/W
0
10
S26C
R/W
0
9
S25C
R/W
0
8
S24C
R/W
0
7
S23C
R/W
0
6
S22C
R/W
0
5
S21C
R/W
0
4
S20C
R/W
0
3
S19C
R/W
0
2
S18C
R/W
0
1
S17C
R/W
0
0
S16C
R/W
0
Bit 15 – S31C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S30C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S29C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S28C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 985
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S27C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S26C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S25C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S24C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 986
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S23C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S22C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S21C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S20C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 987
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S19C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S18C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S17C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S16C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 988
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.77 LCD SData Register 30
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA30
0x5D8
15
S47C
R/W
0
14
S46C
R/W
0
13
S45C
R/W
0
12
S44C
R/W
0
11
S43C
R/W
0
10
S42C
R/W
0
9
S41C
R/W
0
8
S40C
R/W
0
7
S39C
R/W
0
6
S38C
R/W
0
5
S37C
R/W
0
4
S36C
R/W
0
3
S35C
R/W
0
2
S34C
R/W
0
1
S33C
R/W
0
0
S32C
R/W
0
Bit 15 – S47C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S46C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S45C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S44C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 989
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S43C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S42C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S41C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S40C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S39C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S38C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S37C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S36C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S35C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S34C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S33C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S32C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 992
PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
18.1.78 LCD SData Register 31
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
LCDSDATA31
0x5DA
15
S63C
R/W
0
14
S62C
R/W
0
13
S61C
R/W
0
12
S60C
R/W
0
11
S59C
R/W
0
10
S58C
R/W
0
9
S57C
R/W
0
8
S56C
R/W
0
7
S55C
R/W
0
6
S54C
R/W
0
5
S53C
R/W
0
4
S52C
R/W
0
3
S51C
R/W
0
2
S50C
R/W
0
1
S49C
R/W
0
0
S48C
R/W
0
Bit 15 – S63C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 14 – S62C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 13 – S61C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 12 – S60C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 11 – S59C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 10 – S58C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 9 – S57C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 8 – S56C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 7 – S55C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 6 – S54C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 5 – S53C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 4 – S52C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
Liquid Crystal Display (LCD) Controller
Bit 3 – S51C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 2 – S50C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 1 – S49C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
Bit 0 – S48C Pixel Blink/Blank Enable bit
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01
Value
Description
1
0
Pixel is selected for Blink or Blank
Pixel is not selected for Blink or Blank
Else
Value
Description
1
0
Pixel on (dark)
Pixel off (clear)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 996
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.
Real-Time Clock and Calendar (RTCC) with Timestamp
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information on the Real-Time Clock and Calendar, refer to “RTCC with
Timestamp” (www.microchip.com/DS70005193) in the “dsPIC33/PIC24 Family Reference Manual”. The information
in this data sheet supersedes the information in the FRM.
The RTCC provides the user with a Real-Time Clock and Calendar (RTCC) function that can be calibrated.
Key features of the RTCC module are:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Selectable Clock Source
Provides Hours, Minutes and Seconds Using 24-Hour Format
Visibility of One Half Second Period
Provides Calendar – Weekday, Date, Month and Year
Alarm-Configurable for Half a Second, 1 Second, 10 Seconds, 1 Minute, 10 Minutes, 1 Hour, 1 Day, 1 Week,
1 Month or 1 Year
Alarm Repeat with Decrementing Counter
Alarm with Indefinite Repeat Chime
Year 2000 to 2099 Leap Year Correction
BCD Format for Smaller Software Overhead
Optimized for Long-Term Battery Operation
User Calibration of the 32.768 kHz Clock Crystal/32 kHz LPRC Frequency with Periodic Auto-Adjust
Fractional Second Synchronization
Calibration to within ±2.64 Seconds Error per Month
Calibrates Up to 260 ppm of Crystal Error
Ability to Periodically Wake-up External Devices without CPU Intervention (external power control)
Power Control Output for External Circuit Control
Calibration takes Effect Every 15 Seconds
Timestamp Capture register for Time and Date
Programmable Prescaler and Clock Divider Circuit allows Operation with Any Clock Source
Up to 32 MHz, Including 32.768 kHz Crystal, 50/60 Hz Powerline Clock, External Real-Time Clock (RTC) or
32 kHz LPRC Clock
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
Figure 19-1. RTCC Block Diagram
PB
19.1
RTCC Source Clock
The RTCC clock divider block converts the incoming oscillator source into accurate 1/2 and 1 second clocks for the
RTCC. The clock divider is optimized to work with three different oscillator sources:
•
•
•
32.768 kHz Crystal Oscillator
32 kHz Low-Power RC Oscillator (LPRC)
External 50 Hz or 60 Hz Powerline Frequency
An asynchronous prescaler, PS[1:0] (RTCCON2L[5:4]), is provided that allows the RTCC to work with higher speed
clock sources, such as the peripheral clock. Divide ratios of 1:16, 1:64 or 1:256 may be selected, allowing sources of
up to 16 MHz to clock the RTCC.
19.1.1
Coarse Frequency Division
The clock divider block has a 16-bit counter used to divide the input clock frequency. The divide ratio is set by the
DIV[15:0] register bits (RTCCON2H[15:0]). The DIV[15:0] bits should be programmed with a value to produce a
nominal 1/2 second clock divider count period.
19.1.2
Fine Frequency Division
The fine frequency division is set using the FDIV[4:0] bits (RTCCON2L[15:11]). Increasing the FDIVx value will
lengthen the overall clock divider period.
If FDIV[4:0] = 00000, the fine frequency division circuit is effectively disabled. Otherwise, it will optionally remove a
clock pulse from the input of the clock divider every 1/2 second. This functionality will allow the user to remove up to
31 pulses over a fixed period of 16 seconds, depending on the value of FDIVx.
The value for DIV[15:0] is calculated as shown in Equation 19-1. The fractional remainder of the DIV[15:0] calculation
result can be used to calculate the value for FDIV[4:0].
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
Equation 19-1. RTCC Clock Divider Output Frequency
The FDIV[4:0] value is the fractional part of the DIV[15:0] calculation, multiplied by 32.
19.2
RTCC Module Registers
The RTCC module registers are organized into four categories:
•
•
•
•
19.2.1
RTCC Control Registers
RTCC Value Registers
Alarm Value Registers
Timestamp Registers
Register Mapping
Previous RTCC implementations used a Register Pointer to access the RTCC Time and Date registers, as well as
the Alarm Time and Date registers. These Registers are now mapped to memory and are individually addressable.
19.2.2
Write Lock
To prevent spurious changes to the Time Control or Time Value registers, the WRLOCK bit (RTCCON1L1[11]) must
be cleared (‘0’). The POR default state is when the WRLOCK bit is ‘0’ and is cleared on any device Reset (POR,
BOR, MCLR). It is recommended that the WRLOCK bit be set to ‘1’ after the Date and Time registers are properly
initialized, and after the RTCEN bit (RTCCON1L[15]) has been set.
Any attempt to write to the RTCEN bit, the RTCCON2L/H registers, or the Date or Time registers, will be ignored as
long as WRLOCK is ‘1’. The Alarm, Power Control and Timestamp registers can be changed when WRLOCK is ‘1’.
Clearing the WRLOCK bit requires an unlock sequence after it has been written to a ‘1’, writing two bytes
consecutively to the NVMKEY register. A sample assembly sequence is shown in Example 19-1. If WRLOCK is
already cleared, it can be set to ‘1’ without using the unlock sequence.
Note: To avoid accidental writes to the timer, it is recommended that the WRLOCK bit (RTCCON1L[11]) is kept clear
at any other time. For the WRLOCK bit to be set, there is only one instruction cycle time window allowed between the
55h/AA sequence and the setting of WRLOCK; therefore, it is recommended that code follow the procedure in
Example 19-1.
Example 19-1. Setting the WRLOCK Bit
DISI
MOV
MOV
MOV
MOV
MOV
BCLR
19.2.3
#6
#NVKEY, W1
#0x55, W2
W2, [W1]
#0xAA, W3
W3, [W1]
RTCCON1L, #WRLOCK
; disable interrupts for 6 instructions
;
;
;
;
;
first unlock code
write first unlock code
second unlock sequence
write second unlock sequence
clear the WRLOCK bit
Selecting RTCC Clock Source
The clock source for the RTCC module can be selected using the CLKSEL[1:0] bits in the RTCCON2L register. When
the bits are set to ‘00’, the Secondary Oscillator (SOSC) is used as the reference clock and when the bits are ‘01’,
LPRC is used as the reference clock. When CLKSEL[1:0] = 10, the external powerline (50 Hz and 60 Hz) is used as
the clock source. When CLKSEL[1:0] = 11, the system clock is used as the clock source.
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.3
Calibration
19.3.1
Clock Source Calibration
A crystal oscillator that is connected to the RTCC may be calibrated to provide an accurate one second clock in two
ways. First, coarse frequency adjustment is performed by adjusting the value written to the DIV[15:0] bits. Secondly,
a 5-bit value can be written to the FDIV[4:0] control bits to perform a fine clock division.
The DIVx and FDIVx values can be concatenated and considered as a 21-bit prescaler value. If the oscillator source
is slightly faster than ideal, the FDIV[4:0] value can be increased to make a small decrease in the RTC frequency.
The value of DIV[15:0] should be increased to make larger decreases in the RTC frequency. If the oscillator source is
slower than ideal, FDIV[4:0] may be decreased for small calibration changes and DIV[15:0] may need to be
decreased to make larger calibration changes.
Before calibration, the user must determine the error of the crystal. This should be done using another timer resource
on the device or an external timing reference. It is up to the user to include in the error value, the initial error of the
crystal, drift due to temperature and drift due to crystal aging.
19.4
Alarm
•
•
•
19.4.1
Configurable from half second to one year
Enabled using the ALRMEN bit (RTCCON1H[15])
One-time alarm and repeat alarm options are available
Configuring the Alarm
The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. Writes to the Alarm
Value registers should only take place when ALRMEN = 0.
As shown in Figure 19-2, the interval selection of the alarm is configured through the AMASK[3:0] bits
(RTCCON1H[11:8]). These bits determine which and how many digits of the alarm must match the clock value for the
alarm to occur.
Figure 19-2. Alarm Mask Settings
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PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
Note:
1. Annually, except when configured for February 29.
The alarm can also be configured to repeat based on a preconfigured interval. The amount of times this occurs, once
the alarm is enabled, is stored in the ALMRPT[7:0] bits (RTCCON1H[7:0]). When the value of the ALMRPTx bits
equals 00h and the CHIME bit (RTCCON1H[14]) is cleared, the repeat function is disabled and only a single alarm
will occur. The alarm can be repeated, up to 255 times, by loading ALMRPT[7:0] with FFh.
After each alarm is issued, the value of the ALMRPTx bits is decremented by one. Once the value has reached 00h,
the alarm will be issued one last time, after which, the ALRMEN bit will be cleared automatically and the alarm will
turn off.
Indefinite repetition of the alarm can occur if the CHIME bit = 1. Instead of the alarm being disabled when the value of
the ALMRPTx bits reaches 00h, it rolls over to FFh and continues counting indefinitely while CHIME is set.
19.4.2
Alarm Interrupt
At every alarm event, an interrupt is generated. This output is completely synchronous to the RTCC clock and can be
used as a trigger clock to the other peripherals.
Note: Changing any of the register bits, other than the RTCOE bit (RTCCON1L[7]), the ALMRPT[7:0] bits
(RTCCON1H[7:0] and the CHIME bit, while the alarm is enabled (ALRMEN = 1), can result in a false alarm event
leading to a false alarm interrupt. To avoid a false alarm event, the timer and alarm values should only be changed
while the alarm is disabled (ALRMEN = 0).
19.5
Power Control
The RTCC includes a power control feature that allows the device to periodically wake-up an external device, wait for
the device to be stable before sampling wake-up events from that device and then shut down the external device.
This can be done completely autonomously by the RTCC, without the need to wake-up from the current lower power
mode.
To use this feature:
1.
Enable the RTCC (RTCEN = 1).
2.
3.
Set the PWCEN bit (RTCCON1L[10]).
Configure the RTCC pin to drive the PWC control signal (RTCOE = 1 and OUTSEL[2:0] = 011).
The polarity of the PWC control signal may be chosen using the PWCPOL bit (RTCCON1L[9]). An active-low or
active-high signal may be used with the appropriate external switch to turn on or off the power to one or more
external devices. The active-low setting may also be used in conjunction with an open-drain setting on the RTCC pin,
in order to drive the ground pin(s) of the external device directly (with the appropriate external VDD pull-up device),
without the need for external switches. Finally, the CHIME bit should be set to enable the PWC periodicity.
Once the RTCC and PWC are enabled and running, the PWC logic will generate a control output and a sample gate
output. The control output is driven out on the RTCC pin (when RTCOE = 1 and OUTSEL[2:0] = 011) and is used to
power up or down the device, as described above.
Once the control output is asserted, the stability window begins, in which the external device is given enough time to
power up and provide a stable output.
Once the output is stable, the RTCC provides a sample gate during the sample window. The use of this sample gate
depends on the external device being used, but typically, it is used to mask out one or more wake-up signals from the
external device.
Finally, both the stability and the sample windows close after the expiration of the sample window and the external
device is powered down.
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PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.5.1
Power Control Clock Source
The stability and sample windows are controlled by the PWCSAMPx and PWCSTABx bit fields in the RTCCON3L
register (RTCCON3L[15:8] and [7:0], respectively). As both the stability and sample windows are defined in terms of
the RTCC clock, their absolute values vary by the value of the PWC clock base period (TPWCCLK). For example, using
a 32.768 kHz SOSC input clock would produce a TPWCCLK of 1/32768 = 30.518 µs. The 8-bit magnitude of
PWCSTABx and PWCSAMPx allows for a window size of 0 to 255 TPWCCLK. The period of the PWC clock can also
be adjusted with a 1:1, 1:16, 1:64 or 1:256 prescaler, determined by the PWCPS[1:0] bits (RTCCON2L[7:6]).
In addition, certain values for the PWCSTABx and PWCSAMPx fields have specific control meanings in determining
power control operations. If either bit field is 00h, the corresponding window is inactive. In addition, if the PWCSTABx
field is FFh, the stability window remains active continuously, even if power control is disabled.
19.6
Event Timestamping
The RTCC includes a set of Timestamp registers that may be used for the capture of Time and Date register values
when an external input signal is received. The RTCC will trigger a timestamp event when a low pulse occurs on the
TMPRN pin.
19.6.1
Timestamp Operation
The event input is enabled for timestamping using the TSAEN bit (RTCCON1L[0]). When the timestamp event
occurs, the present time and date values will be stored in the TSATIMEL/H and TSADATEL/H registers, the TSAEVT
status bit (RTCSTATL[3]) will be set and an RTCC interrupt will occur. A new timestamp capture event cannot occur
until the user clears the TSAEVT status bit.
The TSATIMEL/H and TSADATEL/H register pairs can be used for data storage when TSAEN = 0. The values of
TSATIMEL/H and TSADATEL/H will be maintained throughout all types of non-Power-on Resets (MCLR, WDT, etc).
19.6.2
Manual Timestamp Operation
The current time and date may be captured in the TSATIMEL/H and TSADATEL/H registers by writing a ‘1’ to the
TSAEVT bit location while the timestamp functionality is enabled (TSAEN = 1). This write will not set the TSAEVT bit,
but it will initiate a timestamp capture. The TSAEVT bit will be set when the capture operation is complete. The user
must poll the TSAEVT bit to determine when the capture operation is complete.
After the Timestamp registers have been read, the TSAEVT bit should be cleared to allow further hardware or
software timestamp capture events.
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7
RTCC Registers
Offset
Name
0x00
...
0x01CB
Reserved
0x01CC
RTCCON1L
0x01CE
RTCCON1H
0x01D0
RTCCON2L
0x01D2
RTCCON2H
0x01D4
RTCCON3L
0x01D6
...
0x01D7
Reserved
0x01D8
RTCSTATL
0x01DA
...
0x01DB
Reserved
0x01DC
TIMEL
0x01DE
TIMEH
0x01E0
DATEL
0x01E2
DATEH
0x01E4
ALMTIMEL
0x01E6
ALMTIMEH
0x01E8
ALMDATEL
0x01EA
ALMDATEH
0x01EC
TSATIMEL(1)
0x01EE
TSATIMEH(1)
0x01F0
TSADATEL(1)
0x01F2
TSADATEH(1)
Bit Pos.
7
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
RTCOE
RTCEN
6
5
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
© 2019-2020 Microchip Technology Inc.
3
2
1
0
PWCEN
PWCPOL
TSAEN
PWCPOE
OUTSEL[2:0]
WRLOCK
ALMRPT[7:0]
ALRMEN
CHIME
PWCPS[1:0]
7:0
15:8
4
AMASK[3:0]
PS[1:0]
FDIV[4:0]
CLKSEL[1:0]
DIV[7:0]
DIV[15:8]
PWCSTAB[7:0]
PWCSAMP[7:0]
ALMEVT
TSAEVT
SECTEN[2:0]
MINTEN[2:0]
HRTEN[1:0]
DAYTEN[1:0]
MTHTEN
YRTEN[3:0]
SECTEN[2:0]
MINTEN[2:0]
HRTEN[1:0]
DAYTEN[1:0]
MTHTEN
YRTEN[3:0]
SECTEN[2:0]
MINTEN[2:0]
HRTEN[1:0]
DAYTEN[1:0]
MTHTEN
YRTEN[3:0]
Datasheet
SYNC
ALMSYNC
HALFSEC
SECONE[3:0]
MINONE[3:0]
HRONE[3:0]
WDAY[2:0]
DAYONE[3:0]
MTHONE[3:0]
YRONE[3:0]
SECONE[3:0]
MINONE[3:0]
HRONE[3:0]
WDAY[2:0]
DAYONE[3:0]
MTHONE[3:0]
YRONE[3:0]
SECONE[3:0]
MINONE[3:0]
HRONE[3:0]
WDAY[2:0]
DAYONE[3:0]
MTHONE[3:0]
YRONE[3:0]
DS30010203C-page 1003
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.1
RTCC Control Register 1 Low
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
RTCCON1L
0x1CC
15
RTCEN
R/W
0
14
13
12
11
WRLOCK
R/W
0
10
PWCEN
R/W
0
9
PWCPOL
R/W
0
8
PWCPOE
R/W
0
7
RTCOE
R/W
0
6
5
OUTSEL[2:0]
R/W
0
4
3
2
1
0
TSAEN
R/W
0
R/W
0
R/W
0
Bit 15 – RTCEN RTCC Enable bit
Value
Description
1
RTCC is enabled and counts from selected clock source
0
RTCC is not enabled
Bit 11 – WRLOCK RTCC Register Write Lock bit
Value
Description
1
RTCC registers are locked
0
RTCC registers may be written to by user
Bit 10 – PWCEN Power Control Enable bit
Value
Description
1
Power control is enabled
0
Power control is disabled
Bit 9 – PWCPOL Power Control Polarity bit
Value
Description
1
Power control output is active-high
0
Power control output is active-low
Bit 8 – PWCPOE Power Control Output Enable bit
Value
Description
1
Power control output pin is enabled
0
Power control output pin is disabled
Bit 7 – RTCOE RTCC Output Enable bit
Value
Description
1
RTCC output is enabled
0
RTCC output is disabled
Bits 6:4 – OUTSEL[2:0] RTCC Output Signal Selection bits
Value
Description
111
Unused
110
Unused
101
Unused
100
Timestamp A event
011
Power control
010
RTCC input clock
001
Second clock
000
Alarm event
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1004
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
Bit 0 – TSAEN Timestamp A Enable bit
Value
Description
1
Timestamp event will occur when a low pulse is detected on the TMPRN pin
0
Timestamp is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1005
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.2
RTCC Control Register 1 High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
RTCCON1H
0x1CE
15
ALRMEN
R/W
0
14
CHIME
R/W
0
13
7
6
5
R/W
0
R/W
0
R/W
0
12
11
R/W
0
4
3
ALMRPT[7:0]
R/W
R/W
0
0
10
9
AMASK[3:0]
R/W
R/W
0
0
8
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bit 15 – ALRMEN Alarm Enable bit
Value
Description
1
Alarm is enabled (cleared automatically after an alarm event whenever ALMRPT[7:0] = 00h and
CHIME = 0)
0
Alarm is disabled
Bit 14 – CHIME Chime Enable bit
Value
Description
1
Chime is enabled; ALMRPT[7:0] bits roll over from 00h to FFh
0
Chime is disabled; ALMRPT[7:0] bits stop once they reach 00h
Bits 11:8 – AMASK[3:0] Alarm Mask Configuration bits
Value
Description
11xx
Reserved – do not use
101x
Reserved – do not use
1001
Once a year (except when configured for February 29th, once every four years)
1000
Once a month
0111
Once a week
0110
Once a day
0101
Every hour
0100
Every ten minutes
0011
Every minute
0010
Every ten seconds
0001
Every second
0000
Every half second
Bits 7:0 – ALMRPT[7:0] Alarm Repeat Counter Value bits
Value
Description
11111111 Alarm will repeat 255 more times
...
00000000 Alarm will repeat 0 more times
The counter decrements on any alarm event. The counter is prevented from rolling over from ‘00’ to
‘FF’ unless CHIME = 1.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1006
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.3
RTCC Control Register 2 Low
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
RTCCON2L
0x1D0
15
14
R/W
0
R/W
0
6
PWCPS[1:0]
R/W
R/W
0
0
13
FDIV[4:0]
R/W
0
12
11
R/W
0
R/W
0
5
4
3
7
PS[1:0]
R/W
0
R/W
0
10
9
2
1
8
0
CLKSEL[1:0]
R/W
R/W
0
0
Bits 15:11 – FDIV[4:0] Fractional Clock Divide bits
Value
Description
11111
Increase period by 31 RTCC input clock cycles every 16 seconds
11101
Increase period by 30 RTCC input clock cycles every 16 seconds
...
00010
Increase period by 2 RTCC input clock cycles every 16 seconds
00001
Increase period by 1 RTCC input clock cycle every 16 seconds
00000
No fractional clock division
Bits 7:6 – PWCPS[1:0] Power Control Prescale Select bits
Value
Description
11
1:256
10
1:64
01
1:16
00
1:1
Bits 5:4 – PS[1:0] Prescale Select bits
Value
Description
11
1:256
10
1:64
01
1:16
00
1:1
Bits 1:0 – CLKSEL[1:0] Clock Select bits
Value
Description
11
Peripheral clock
10
PWRLCLK pin
01
LPRC
00
SOSC
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1007
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.4
RTCC Control Register 2 High
Name:
Offset:
RTCCON2H
0x1D2
Note:
1.
Bit
A write to this register is only allowed when WRLOCK = 1.
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DIV[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DIV[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – DIV[15:0] Clock Divide bits(1)
Sets the period of the clock divider counter; value should cause a nominal 1/2 second underflow.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1008
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.5
RTCC Control Register 3 Low
Name:
Offset:
RTCCON3L
0x1D4
Note:
1. The sample window always starts when the stability window timer expires, except when its initial value is 00h.
Bit
Access
Reset
Bit
Access
Reset
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
PWCSAMP[7:0]
R/W
R/W
0
0
4
3
PWCSTAB[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – PWCSAMP[7:0] Power Control Sample Window Timer bits
Value
Description
11111111
Sample window is always enabled, even when PWCEN = 0
11111110
Sample window is 254 TPWCCLK clock periods
...
00000001
Sample window is 1 TPWCCLK clock period
00000000
No sample window
Bits 7:0 – PWCSTAB[7:0] Power Control Stability Window Timer bits(1)
Value
Description
11111111
Stability window is 255 TPWCCLK clock periods
11111110
Stability window is 254 TPWCCLK clock periods
...
00000001
Stability window is 1 TPWCCLK clock period
00000000
No stability window; sample window starts when the alarm event triggers
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1009
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.6
RTCC Status Register Low
Name:
Offset:
RTCSTATL
0x1D8
Notes:
1. User software may write a ‘1’ to this location to initiate a Timestamp A event; timestamp capture is not valid
until TSAEVT reads as ‘1’.
2.
Bit
This bit is read-only; it is cleared to ‘0’ on a write to the SECONE[3:0] bits.
15
14
13
12
11
10
9
8
7
6
5
ALMEVT
R/W
0
4
3
TSAEVT
R/W
0
2
SYNC
R/W
0
1
ALMSYNC
R/W
0
0
HALFSEC
R/W
0
Access
Reset
Bit
Access
Reset
Bit 5 – ALMEVT Alarm Event bit
Value
Description
1
An alarm event has occurred
0
An alarm event has not occurred
Bit 3 – TSAEVT Timestamp A Event bit(1)
Value
Description
1
A timestamp event has occurred
0
A timestamp event has not occurred
Bit 2 – SYNC Synchronization Status bit
Value
Description
1
TIME registers may change during software read
0
TIME registers may be read safely
Bit 1 – ALMSYNC Alarm Synchronization Status bit
Value
Description
1
Alarm registers (ALMTIME and ALMDATE) and Alarm bits (AMASK[3:0]) should not be modified, and
Alarm Control bits (ALRMEN, ALMRPT[7:0]) may change during software read
0
Alarm registers and Alarm Control bits may be written/modified safely
Bit 0 – HALFSEC Half Second Status bit(2)
Value
Description
1
Second half period of a second
0
First half period of a second
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1010
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.7
RTCC Time Register Low
Name:
Offset:
Bit
15
Access
Reset
Bit
7
TIMEL
0x1DC
14
12
11
R/W
0
13
SECTEN[2:0]
R/W
0
R/W
0
R/W
0
6
5
4
3
10
9
SECONE[3:0]
R/W
R/W
0
0
2
1
8
R/W
0
0
Access
Reset
Bits 14:12 – SECTEN[2:0] Binary Coded Decimal Value of Seconds ‘10’ Digit bits
Contains a value from 0 to 5.
Bits 11:8 – SECONE[3:0] Binary Coded Decimal Value of Seconds ‘1’ Digit bits
Contains a value from 0 to 9.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1011
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.8
RTCC Time Register High
Name:
Offset:
Bit
15
TIMEH
0x1DE
14
Access
Reset
Bit
Access
Reset
7
6
R/W
0
13
12
HRTEN[1:0]
R/W
R/W
0
0
5
MINTEN[2:0]
R/W
0
11
R/W
0
4
3
R/W
0
R/W
0
10
9
HRONE[3:0]
R/W
R/W
0
0
2
1
MINONE[3:0]
R/W
R/W
0
0
8
R/W
0
0
R/W
0
Bits 13:12 – HRTEN[1:0] Binary Coded Decimal Value of Hours ‘10’ Digit bits
Contains a value from 0 to 2.
Bits 11:8 – HRONE[3:0] Binary Coded Decimal Value of Hours ‘1’ Digit bits
Contains a value from 0 to 9.
Bits 6:4 – MINTEN[2:0] Binary Coded Decimal Value of Minutes ‘10’ Digit bits
Contains a value from 0 to 5.
Bits 3:0 – MINONE[3:0] Binary Coded Decimal Value of Minutes ‘1’ Digit bits
Contains a value from 0 to 9.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1012
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.9
RTCC Date Register Low
Name:
Offset:
Bit
15
DATEL
0x1E0
14
Access
Reset
Bit
7
12
DAYTEN[1:0]
R/W
R/W
0
0
6
13
5
4
11
R/W
0
10
9
DAYONE[3:0]
R/W
R/W
0
0
3
Access
Reset
2
R/W
0
1
WDAY[2:0]
R/W
0
8
R/W
0
0
R/W
0
Bits 13:12 – DAYTEN[1:0] Binary Coded Decimal Value of Days ‘10’ Digit bits
Contains a value from 0 to 3.
Bits 11:8 – DAYONE[3:0] Binary Coded Decimal Value of Days ‘1’ Digit bits
Contains a value from 0 to 9.
Bits 2:0 – WDAY[2:0] Binary Coded Decimal Value of Weekdays ‘1’ Digit bits
Contains a value from 0 to 6.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1013
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.10 RTCC Date Register High
Name:
Offset:
Bit
15
DATEH
0x1E2
14
13
12
11
YRTEN[3:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
MTHTEN
R/W
x
3
Access
Reset
R/W
0
10
9
YRONE[3:0]
R/W
R/W
0
0
2
1
MTHONE[3:0]
R/W
R/W
0
0
8
R/W
x
0
R/W
x
Bits 15:12 – YRTEN[3:0] Binary Coded Decimal Value of Years ‘10’ Digit bits
Bits 11:8 – YRONE[3:0] Binary Coded Decimal Value of Years ‘1’ Digit bits
Bit 4 – MTHTEN Binary Coded Decimal Value of Months ‘10’ Digit bits
Contains a value from 0 to 1.
Bits 3:0 – MTHONE[3:0] Binary Coded Decimal Value of Months ‘1’ Digit bits
Contains a value from 0 to 9.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1014
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.11 RTCC Alarm Time Register Low
Name:
Offset:
Bit
15
Access
Reset
Bit
7
ALMTIMEL
0x1E4
14
12
11
R/W
0
13
SECTEN[2:0]
R/W
0
R/W
0
R/W
0
6
5
4
3
10
9
SECONE[3:0]
R/W
R/W
0
0
2
1
8
R/W
0
0
Access
Reset
Bits 14:12 – SECTEN[2:0] Binary Coded Decimal Value of Seconds ‘10’ Digit bits
Contains a value from 0 to 5.
Bits 11:8 – SECONE[3:0] Binary Coded Decimal Value of Seconds ‘1’ Digit bits
Contains a value from 0 to 9.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1015
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.12 RTCC Alarm Time Register High
Name:
Offset:
Bit
15
ALMTIMEH
0x1E6
14
Access
Reset
Bit
Access
Reset
7
6
R/W
0
13
12
HRTEN[1:0]
R/W
R/W
0
0
5
MINTEN[2:0]
R/W
0
11
R/W
0
4
3
R/W
0
R/W
0
10
9
HRONE[3:0]
R/W
R/W
0
0
2
1
MINONE[3:0]
R/W
R/W
0
0
8
R/W
0
0
R/W
0
Bits 13:12 – HRTEN[1:0] Binary Coded Decimal Value of Hours ‘10’ Digit bits
Contains a value from 0 to 2.
Bits 11:8 – HRONE[3:0] Binary Coded Decimal Value of Hours ‘1’ Digit bits
Contains a value from 0 to 9.
Bits 6:4 – MINTEN[2:0] Binary Coded Decimal Value of Minutes ‘10’ Digit bits
Contains a value from 0 to 5.
Bits 3:0 – MINONE[3:0] Binary Coded Decimal Value of Minutes ‘1’ Digit bits
Contains a value from 0 to 9.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1016
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.13 RTCC Alarm Date Register Low
Name:
Offset:
Bit
15
ALMDATEL
0x1E8
14
Access
Reset
Bit
7
12
DAYTEN[1:0]
R/W
R/W
0
0
6
13
5
4
11
R/W
0
10
9
DAYONE[3:0]
R/W
R/W
0
0
3
Access
Reset
2
R/W
0
1
WDAY[2:0]
R/W
0
8
R/W
0
0
R/W
0
Bits 13:12 – DAYTEN[1:0] Binary Coded Decimal Value of Days ‘10’ Digit bits
Contains a value from 0 to 3.
Bits 11:8 – DAYONE[3:0] Binary Coded Decimal Value of Days ‘1’ Digit bits
Contains a value from 0 to 9.
Bits 2:0 – WDAY[2:0] Binary Coded Decimal Value of Weekdays ‘1’ Digit bits
Contains a value from 0 to 6.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1017
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.14 RTCC Alarm Date Register High
Name:
Offset:
Bit
15
ALMDATEH
0x1EA
14
13
12
11
YRTEN[3:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
MTHTEN
R/W
0
3
Access
Reset
R/W
0
10
9
YRONE[3:0]
R/W
R/W
0
0
2
1
MTHONE[3:0]
R/W
R/W
0
0
8
R/W
0
0
R/W
0
Bits 15:12 – YRTEN[3:0] Binary Coded Decimal Value of Years ‘10’ Digit bits
Bits 11:8 – YRONE[3:0] Binary Coded Decimal Value of Years ‘1’ Digit bits
Bit 4 – MTHTEN Binary Coded Decimal Value of Months ‘10’ Digit bits
Contains a value from 0 to 1.
Bits 3:0 – MTHONE[3:0] Binary Coded Decimal Value of Months ‘1’ Digit bits
Contains a value from 0 to 9.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1018
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.15 RTCC Timestamp A Time Register Low
Name:
Offset:
TSATIMEL(1)
0x1EC
Note:
1. If TSAEN = 0, bits[15:0] can be used for persistent storage throughout a non-Power-on Reset (MCLR, WDT,
etc.).
Bit
15
Access
Reset
Bit
7
14
12
11
R/W
0
13
SECTEN[2:0]
R/W
0
R/W
0
R/W
0
6
5
4
3
10
9
SECONE[3:0]
R/W
R/W
0
0
2
1
8
R/W
0
0
Access
Reset
Bits 14:12 – SECTEN[2:0] Binary Coded Decimal Value of Seconds ‘10’ Digit bits
Contains a value from 0 to 5.
Bits 11:8 – SECONE[3:0] Binary Coded Decimal Value of Seconds ‘1’ Digit bits
Contains a value from 0 to 9.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1019
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.16 RTCC Timestamp A Time Register High
Name:
Offset:
TSATIMEH(1)
0x1EE
Note:
1. If TSAEN = 0, bits[15:0] can be used for persistent storage throughout a non-Power-on Reset (MCLR, WDT,
etc.).
Bit
15
14
Access
Reset
Bit
Access
Reset
7
6
R/W
0
13
12
HRTEN[1:0]
R/W
R/W
0
0
5
MINTEN[2:0]
R/W
0
11
R/W
0
4
3
R/W
0
R/W
0
10
9
HRONE[3:0]
R/W
R/W
0
0
2
1
MINONE[3:0]
R/W
R/W
0
0
8
R/W
0
0
R/W
0
Bits 13:12 – HRTEN[1:0] Binary Coded Decimal Value of Hours ‘10’ Digit bits
Contains a value from 0 to 2.
Bits 11:8 – HRONE[3:0] Binary Coded Decimal Value of Hours ‘1’ Digit bits
Contains a value from 0 to 9.
Bits 6:4 – MINTEN[2:0] Binary Coded Decimal Value of Minutes ‘10’ Digit bits
Contains a value from 0 to 5.
Bits 3:0 – MINONE[3:0] Binary Coded Decimal Value of Minutes ‘1’ Digit bits
Contains a value from 0 to 9.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1020
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.17 RTCC Timestamp A Date Register Low
Name:
Offset:
TSADATEL(1)
0x1F0
Note:
1. If TSAEN = 0, bits[15:0] can be used for persistent storage throughout a non-Power-on Reset (MCLR, WDT,
etc.).
Bit
15
14
Access
Reset
Bit
7
12
DAYTEN[1:0]
R/W
R/W
0
0
6
13
5
4
11
R/W
0
10
9
DAYONE[3:0]
R/W
R/W
0
0
3
Access
Reset
2
R/W
0
1
WDAY[2:0]
R/W
0
8
R/W
0
0
R/W
0
Bits 13:12 – DAYTEN[1:0] Binary Coded Decimal Value of Days ‘10’ Digit bits
Contains a value from 0 to 3.
Bits 11:8 – DAYONE[3:0] Binary Coded Decimal Value of Days ‘1’ Digit bits
Contains a value from 0 to 9.
Bits 2:0 – WDAY[2:0] Binary Coded Decimal Value of Weekdays ‘1’ Digit bits
Contains a value from 0 to 6.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1021
PIC24FJ512GU410 Family Data Sheet
Real-Time Clock and Calendar (RTCC) with Tim...
19.7.18 RTCC Timestamp A Date Register High
Name:
Offset:
TSADATEH(1)
0x1F2
Note:
1. If TSAEN = 0, bits[15:0] can be used for persistent storage throughout a non-Power-on Reset (MCLR, WDT,
etc.).
Bit
15
14
13
12
11
YRTEN[3:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
MTHTEN
R/W
0
3
Access
Reset
R/W
0
10
9
YRONE[3:0]
R/W
R/W
0
0
2
1
MTHONE[3:0]
R/W
R/W
0
0
8
R/W
0
0
R/W
0
Bits 15:12 – YRTEN[3:0] Binary Coded Decimal Value of Years ‘10’ Digit bits
Bits 11:8 – YRONE[3:0] Binary Coded Decimal Value of Years ‘1’ Digit bits
Bit 4 – MTHTEN Binary Coded Decimal Value of Months ‘10’ Digit bits
Contains a value from 0 to 1.
Bits 3:0 – MTHONE[3:0] Binary Coded Decimal Value of Months ‘1’ Digit bits
Contains a value from 0 to 9.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1022
PIC24FJ512GU410 Family Data Sheet
32-Bit Programmable Cyclic Redundancy Check ...
20.
32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information, refer to “32-Bit Programmable Cyclic Redundancy Check
(CRC)” (www.microchip.com/DS30009729) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this
data sheet supersedes the information in the FRM.
The 32-bit programmable CRC generator provides a hardware implemented method of quickly generating checksums
for various networking and security applications. It offers the following features:
•
•
•
•
•
User-Programmable CRC Polynomial Equation, Up to 32 Bits
Programmable Shift Direction (little or big-endian)
Independent Data and Polynomial Lengths
Configurable Interrupt Output
Data FIFO
Figure 20-1 displays a simplified block diagram of the CRC generator. A simple version of the CRC shift engine is
displayed in Figure 20-2.
Figure 20-1. CRC Block Diagram
Figure 20-2. CRC Shift Engine Detail
Note:
1. n = PLEN[4:1] + 1.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1023
PIC24FJ512GU410 Family Data Sheet
32-Bit Programmable Cyclic Redundancy Check ...
20.1
User Interface
20.1.1
Polynomial Interface
The CRC module can be programmed for CRC polynomials of up to the 32nd order, using up to 32 bits.
Polynomial length, which reflects the highest exponent in the equation, is selected by the PLEN[4:0] bits
(CRCCON2[4:0]).
The CRCXORL and CRCXORH registers control which exponent terms are included in the equation. Setting a
particular bit includes that exponent term in the equation. Functionally, this includes an XOR operation on the
corresponding bit in the CRC engine. Clearing the bit disables the XOR.
For example, consider two CRC polynomials, one a 16-bit and the other a 32-bit equation.
X16 + X12 + X5 + 1
AND
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
To program these polynomials into the CRC generator, set the register bits, as shown in Table 20-1.
Table 20-1. CRC Setup Examples for 16 and 32-Bit Polynomials
Bit Values
CRC Control Bits
16-Bit Polynomial
32-Bit Polynomial
PLEN[4:0]
01111
11111
X[31:16]
0000 0000 0000 0001
0000 0100 1100 0001
X[15:1]
0001 0000 0010 000
0001 1101 1011 011
Note that the appropriate positions are set to ‘1’ to indicate that they are used in the equation (for example, X26 and
X23). The ‘0’ bit required by the equation is always XORed; thus, X0 is a don’t care. For a polynomial of length 32, it
is assumed that the 32nd bit will be used; therefore, the X[31:1] bits do not have the 32nd bit.
20.1.2
Data Interface
The module incorporates a FIFO that works with a variable data width. Input data width can be configured to any
value, between 1 and 32 bits, using the DWIDTH[4:0] bits (CRCCON2[12:8]). When the data width is greater than 15,
the FIFO is four words deep. When the DWIDTHx bits are between 15 and 8, the FIFO is eight words deep. When
the DWIDTHx bits are less than eight, the FIFO is 16 words deep.
The data for which the CRC is to be calculated must first be written into the FIFO. Even if the data width is less than
eight, the smallest data element that can be written into the FIFO is 1 byte. For example, if the DWIDTHx bits are
five, then the size of the data is DWIDTH[4:0] + 1 or 6. The data are written as a whole byte; the two unused upper
bits are ignored by the module.
Once data are written into the MSb of the CRCDAT registers (that is, the MSb as defined by the data width), the
value of the VWORD[4:0] bits (CRCCON1[12:8]) increments by one. For example, if the DWIDTHx bits are 24, the
VWORDx bits will increment when bit 7 of CRCDATH is written. Therefore, CRCDATL must always be written to
before CRCDATH.
The CRC engine starts shifting data when the CRCGO bit (CRCCON1[4]) is set and the value of the VWORDx bits is
greater than zero.
Each word is copied out of the FIFO into a buffer register, which decrements the VWORDx bits. The data are then
shifted out of the buffer. The CRC engine continues shifting at a rate of two bits per instruction cycle, until the
VWORDx bits reach zero. This means that for a given data width, it takes half that number of instructions for each
word to complete the calculation. For example, it takes 16 cycles to calculate the CRC for a single word of 32-bit
data.
When the VWORDx bits reach the maximum value for the configured value of the DWIDTHx bits (4, 8 or 16), the
CRCFUL bit (CRCCON1[7]) becomes set. When the VWORDx bits reach zero, the CRCMPT bit (CRCCON1[6])
becomes set. The FIFO is emptied and the VWORD[4:0] bits are set to ‘00000’ whenever CRCEN is ‘0’.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1024
PIC24FJ512GU410 Family Data Sheet
32-Bit Programmable Cyclic Redundancy Check ...
At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORDx bits is done.
20.1.3
Data Shift Direction
The LENDIAN bit (CRCCON1[3]) is used to control the shift direction. By default, the CRC will shift data through the
engine, MSb first. Setting LENDIAN (= 1) causes the CRC to shift data, LSb first. This setting allows better integration
with various communication schemes and removes the overhead of reversing the bit order in software. Note that this
only changes the direction the data are shifted into the engine. The result of the CRC calculation will still be a normal
CRC result, not a reverse CRC result.
20.1.4
Interrupt Operation
The module generates an interrupt that is configurable by the user for either of two conditions.
If CRCISEL is ‘0’, an interrupt is generated when the VWORD[4:0] bits make a transition from a value of ‘1’ to ‘0’. If
CRCISEL is ‘1’, an interrupt will be generated after the CRC operation finishes and the module sets the CRCGO bit
to ‘0’. Manually setting CRCGO to ‘0’ will not generate an interrupt. Note that when an interrupt occurs, the CRC
calculation would not yet be complete. The module will still need (PLENx + 1)/2 clock cycles after the interrupt is
generated until the CRC calculation is finished.
20.1.5
Typical Operation
To use the module for a typical CRC calculation:
1.
2.
3.
4.
5.
6.
7.
Set the CRCEN bit to enable the module.
Configure the module for the desired operation.
2.1.
Program the desired polynomial using the CRCXOR registers and PLEN[4:0] bits.
2.2.
Configure the data width and shift direction using the DWIDTH[4:0] and LENDIAN bits.
Set the CRCGO bit to start the calculations.
Set the desired CRC non-direct initial value by writing to the CRCWDAT registers.
Load all data into the FIFO by writing to the CRCDAT registers as space becomes available (the CRCFUL bit
must be zero before the next data loading).
Wait until the data FIFO is empty (CRCMPT bit is set).
Read the result:
If the data width (DWIDTH[4:0] bits) is more than the polynomial length (PLEN[4:0] bits):
7.1.
7.2.
7.3.
7.4.
Wait (DWIDTH[4:0] + 1)/2 instruction cycles to make sure that shifts from the shift buffer are finished.
Change the data width to the polynomial length (DWIDTH[4:0] = PLEN[4:0]).
Write one dummy data word to the CRCDAT registers.
Wait two instruction cycles to move the data from the FIFO to the shift buffer and (PLEN[4:0] + 1)/2
instruction cycles to shift out the result.
Or, if the data width (DWIDTH[4:0] bits) is less than the polynomial length (PLEN[4:0] bits):
1.
2.
3.
Clear the CRC Interrupt Selection bit (CRCISEL = 0) to get the interrupt when all shifts are done. Clear the
CRC interrupt flag. Write dummy data in the CRCDAT registers and wait until the CRC interrupt flag is set.
Read the final CRC result from the CRCWDAT registers.
Restore the data width (DWIDTH[4:0] bits) for further calculations (Optional). If the data width (DWIDTH[4:0]
bits) is equal to, or less than, the polynomial length (PLEN[4:0] bits):
3.1.
Clear the CRC Interrupt Selection bit (CRCISEL = 0) to get the interrupt when all shifts are done.
3.2.
Suspend the calculation by setting CRCGO = 0.
3.3.
3.4.
3.5.
Clear the CRC interrupt flag.
Write the dummy data with the total data length equal to the polynomial length in the CRCDAT
registers.
Resume the calculation by setting CRCGO = 1.
3.6.
3.7.
Wait until the CRC interrupt flag is set.
Read the final CRC result from the CRCWDAT registers.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1025
PIC24FJ512GU410 Family Data Sheet
32-Bit Programmable Cyclic Redundancy Check ...
20.2
CRC Registers
Offset
Name
0x00
...
0x0157
Reserved
0x0158
CRCCON1
0x015A
CRCCON2
0x015C
CRCXORL
0x015E
CRCXORH
0x0160
CRCDATL
0x0162
CRCDATH
0x0164
CRCWDATL
0x0166
CRCWDATH
Bit Pos.
7
6
5
4
3
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
CRCFUL
CRCEN
CRCMPT
CRCISEL
CSIDL
CRCGO
LENDIAN
© 2019-2020 Microchip Technology Inc.
2
1
0
VWORD[4:0]
PLEN[4:0]
DWIDTH[4:0]
X[6:0]
X[14:7]
X[23:16]
X[31:24]
CRCDATL[7:0]
CRCDATL[15:8]
CRCDATH[7:0]
CRCDATH[15:8]
CRCWDATL[7:0]
CRCWDATL[15:8]
CRCWDATH[7:0]
CRCWDATH[15:8]
Datasheet
DS30010203C-page 1026
PIC24FJ512GU410 Family Data Sheet
32-Bit Programmable Cyclic Redundancy Check ...
20.2.1
CRC Control 1 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CRCCON1
0x158
15
CRCEN
R/W
0
14
7
CRCFUL
R/W
0
6
CRCMPT
R/W
0
13
CSIDL
R/W
0
12
11
R/W
0
R/W
0
5
CRCISEL
R/W
0
4
CRCGO
R/W
0
3
LENDIAN
R/W
0
10
VWORD[4:0]
R/W
0
9
8
R/W
0
R/W
0
2
1
0
Bit 15 – CRCEN CRC Enable bit
Value
Description
1
Enables module
0
Disables module; all state machines, pointers and CRCWDAT/CRCDAT registers reset; other SFRs are
NOT reset
Bit 13 – CSIDL CRC Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bits 12:8 – VWORD[4:0] Pointer Value bits
Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN[4:0] ≥ 7 or 16 when
PLEN[4:0] ≤ 7.
Bit 7 – CRCFUL CRC FIFO Full bit
Value
Description
1
FIFO is full
0
FIFO is not full
Bit 6 – CRCMPT CRC FIFO Empty bit
Value
Description
1
FIFO is empty
0
FIFO is not empty
Bit 5 – CRCISEL CRC Interrupt Selection bit
Value
Description
1
Interrupt on FIFO is empty; the final word of data is still shifting through the CRC
0
Interrupt on shift is complete and results are ready
Bit 4 – CRCGO Start CRC bit
Value
Description
1
Starts CRC serial shifter
0
CRC serial shifter is turned off
Bit 3 – LENDIAN Data Shift Direction Select bit
Value
Description
1
Data word is shifted into the CRC, starting with the LSb (little-endian)
0
Data word is shifted into the CRC, starting with the MSb (big-endian)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1027
PIC24FJ512GU410 Family Data Sheet
32-Bit Programmable Cyclic Redundancy Check ...
20.2.2
CRC Control 2 Register
Name:
Offset:
Bit
15
CRCCON2
0x15A
14
13
Access
Reset
Bit
7
6
Access
Reset
5
12
11
R/W
0
R/W
0
4
3
R/W
0
R/W
0
10
DWIDTH[4:0]
R/W
0
2
PLEN[4:0]
R/W
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bits 12:8 – DWIDTH[4:0] CRC Data Word Width Configuration bits
Configures the width of the data word (Data Word Width – 1).
Bits 4:0 – PLEN[4:0] Polynomial Length Configuration bits
Configures the length of the polynomial (Polynomial Length – 1).
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1028
PIC24FJ512GU410 Family Data Sheet
32-Bit Programmable Cyclic Redundancy Check ...
20.2.3
CRC XOR Polynomial Register Low
Name:
Offset:
Bit
15
CRCXORL
0x15C
14
13
12
11
10
9
8
X[14:7]
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
3
2
1
0
R/W
0
R/W
0
R/W
0
4
X[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:1 – X[14:0] XOR of Polynomial Term Xn Enable bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1029
PIC24FJ512GU410 Family Data Sheet
32-Bit Programmable Cyclic Redundancy Check ...
20.2.4
CRC XOR Polynomial Register High
Name:
Offset:
Bit
15
CRCXORH
0x15E
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
X[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
X[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – X[31:24] XOR of Polynomial Term Xn Enable bits
Bits 7:0 – X[23:16] XOR of Polynomial Term Xn Enable bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1030
PIC24FJ512GU410 Family Data Sheet
32-Bit Programmable Cyclic Redundancy Check ...
20.2.5
CRC Data Register Low
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CRCDATL
0x160
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
CRCDATL[15:8]
R/W
R/W
0
0
4
3
CRCDATL[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CRCDATL[15:0] CRC Data Low bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1031
PIC24FJ512GU410 Family Data Sheet
32-Bit Programmable Cyclic Redundancy Check ...
20.2.6
CRC Data Register High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CRCDATH
0x162
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
CRCDATH[15:8]
R/W
R/W
0
0
4
3
CRCDATH[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CRCDATH[15:0] CRC Data High bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1032
PIC24FJ512GU410 Family Data Sheet
32-Bit Programmable Cyclic Redundancy Check ...
20.2.7
CRC Result Register Low
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CRCWDATL
0x164
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
CRCWDATL[15:8]
R/W
R/W
0
0
4
3
CRCWDATL[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CRCWDATL[15:0] CRC Result Low bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1033
PIC24FJ512GU410 Family Data Sheet
32-Bit Programmable Cyclic Redundancy Check ...
20.2.8
CRC Result Register High
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CRCWDATH
0x166
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
CRCWDATH[15:8]
R/W
R/W
0
0
4
3
CRCWDATH[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CRCWDATH[15:0] CRC Result High bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1034
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.
Configurable Logic Cell (CLC)
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information, refer to “Configurable Logic Cell (CLC)”
(www.microchip.com/DS70005298) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data
sheet supersedes the information in the FRM.
The Configurable Logic Cell (CLC) module allows the user to specify combinations of signals as inputs to a logic
function and to use the logic output to control other peripherals or I/O pins. This provides greater flexibility and
potential in embedded designs, since the CLC module can operate outside the limitations of software execution and
supports a vast amount of output designs.
There are four input gates to the selected logic function. These four input gates select from a pool of up to 32 signals
that are selected using four data source selection multiplexers. Figure 21-1 shows an overview of the module. Figure
21-3 shows the details of the data source multiplexers and logic input gate connections.
Figure 21-1. CLC Module
Note: All register bits shown in this figure can be found in the CLCxCONL register.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1035
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
Figure 21-2. CLC Logic Function Combinatorial Options
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1036
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
Figure 21-3. CLC Input Source Selection Diagram
Data Selection
CLCIN[0]
CLCIN[1]
CLCIN[2]
CLCIN[3]
CLCIN[4]
CLCIN[5]
CLCIN[6]
CLCIN[7]
000
Data Gate 1
Data 1 Noninverted
Data 1
Inverted
111
DS1x (CLCxSEL[2:0])
G1D1T
G1D1N
G1D2T
G1D2N
CLCIN[8]
CLCIN[9]
CLCIN[10]
CLCIN[11]
CLCIN[12]
CLCIN[13]
CLCIN[14]
CLCIN[15]
G1D3T
Data 2 Noninverted
Data 2
Inverted
G1D3N
G1D4T
G1D4N
000
Data Gate 2
Gate 2
Data 3 Noninverted
(Same as Data Gate 1)
Data 3
Inverted
Data Gate 3
111
Gate 3
DS3x (CLCxSEL[10:8])
CLCIN[24]
CLCIN[25]
CLCIN[26]
CLCIN[27]
CLCIN[28]
CLCIN[29]
CLCIN[30]
CLCIN[31]
G1POL
(CLCxCONH[0])
111
DS2x (CLCxSEL[6:4])
CLCIN[16]
CLCIN[17]
CLCIN[18]
CLCIN[19]
CLCIN[20]
CLCIN[21]
CLCIN[22]
CLCIN[23]
Gate 1
000
(Same as Data Gate 1)
Data Gate 4
000
Gate 4
(Same as Data Gate 1)
Data 4 Noninverted
Data 4
Inverted
111
DS4x (CLCxSEL[14:12])
Note: All controls are undefined at power-up.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1037
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1
CLC Registers
Offset
Name
0x00
...
0x0463
Reserved
0x0464
CLC1CONL
0x0466
CLC1CONH
0x0468
CLC1SEL
0x046A
...
0x046B
Reserved
0x046C
CLC1GLSL
0x046E
CLC1GLSH
0x0470
CLC2CONL
0x0472
CLC2CONH
0x0474
CLC2SEL
0x0476
...
0x0477
Reserved
0x0478
CLC2GLSL
0x047A
CLC2GLSH
0x047C
CLC3CONL
0x047E
CLC3CONH
0x0480
...
0x0483
Reserved
0x0484
CLC3SEL
0x0484
CLC3GLSL
0x0486
CLC3GLSH
0x0488
CLC4CONL
0x048A
CLC4CONH
0x048C
CLC4SEL
0x048E
...
0x048F
Reserved
0x0490
CLC4GLSL
0x0492
CLC4GLSH
Bit Pos.
7
6
5
7:0
15:8
7:0
15:8
7:0
15:8
LCOE
LCEN
LCOUT
LCPOL
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
G1D4T
G2D4T
G3D4T
G4D4T
LCOE
LCEN
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
G1D4T
G2D4T
G3D4T
G4D4T
LCOE
LCEN
3
2
INTP
G4POL
INTN
G3POL
G1D4N
G2D4N
G3D4N
G4D4N
LCOUT
G1D3T
G2D3T
G3D3T
G4D3T
LCPOL
G1D3T
G2D3T
G3D3T
G4D3T
LCPOL
7:0
DS2[2:0]
DS4[2:0]
G1D3T
G2D3T
G3D3T
G4D3T
LCPOL
G1D4T
G2D4T
G3D4T
G4D4T
LCOE
LCEN
G1D4N
G2D4N
G3D4N
G4D4N
LCOUT
G1D3N
G2D3N
G3D3N
G4D3N
G1D2T
G2D3N
G3D2T
G4D2N
G1D2N
G2D2N
G3D2N
G4D2N
INTP
G4POL
INTN
G3POL
© 2019-2020 Microchip Technology Inc.
G1D4N
G2D4N
G3D4N
G4D4N
G1D3T
G2D3T
G3D3T
G4D3T
G2POL
G1POL
G1D1T
G2D1T
G3D1T
G4D1T
MODE[2:0]
G1D1N
G2D1N
G3D1N
G4D1N
G2POL
G1POL
DS1[2:0]
DS3[2:0]
G1D3N
G2D3N
G3D3N
G4D3N
G1D3N
G2D3N
G3D3N
G4D3N
G1D2T
G2D3N
G3D2T
G4D2N
G1D2N
G2D2N
G3D2N
G4D2N
INTP
G4POL
INTN
G3POL
G1D2T
G2D3N
G3D2T
G4D2N
G1D2N
G2D2N
G3D2N
G4D2N
INTP
G4POL
INTN
G3POL
DS2[2:0]
DS4[2:0]
G1D4T
G2D4T
G3D4T
G4D4T
0
DS1[2:0]
DS3[2:0]
DS2[2:0]
DS4[2:0]
G1D4N
G2D4N
G3D4N
G4D4N
LCOUT
1
MODE[2:0]
DS2[2:0]
DS4[2:0]
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
4
G1D1T
G2D1T
G3D1T
G4D1T
MODE[2:0]
G1D1N
G2D1N
G3D1N
G4D1N
G2POL
G1POL
DS1[2:0]
DS3[2:0]
G1D1T
G2D1T
G3D1T
G4D1T
MODE[2:0]
G2POL
G1D1N
G2D1N
G3D1N
G4D1N
G1POL
DS1[2:0]
DS3[2:0]
G1D3N
G2D3N
G3D3N
G4D3N
Datasheet
G1D2T
G2D3N
G3D2T
G4D2N
G1D2N
G2D2N
G3D2N
G4D2N
G1D1T
G2D1T
G3D1T
G4D1T
G1D1N
G2D1N
G3D1N
G4D1N
DS30010203C-page 1038
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.1
Control Registers Overview
The CLCx module is controlled by the following registers:
•
•
•
•
•
CLCxCONL
CLCxCONH
CLCxSEL
CLCxGLSL
CLCxGLSH
The CLCx Control registers (CLCxCONL and CLCxCONH) are used to enable the module and interrupts, control the
output enable bit, select output polarity and select the logic function. The CLCx Control registers also allow the user
to control the logic polarity of not only the cell output, but also some intermediate variables.
The CLCx Input MUX Select register (CLCxSEL) allows the user to select up to four data input sources using the four
data input selection multiplexers. Each multiplexer has a list of eight data sources available.
The CLCx Gate Logic Input Select registers (CLCxGLSL and CLCxGLSH) allow the user to select which outputs from
each of the selection MUXes are used as inputs to the input gates of the logic cell. Each data source MUX outputs
both a true and a negated version of its output. All of these eight signals are enabled, ORed together by the logic cell
input gates.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1039
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.2
CLC1 Control Register Low
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CLC1CONL
0x464
15
LCEN
R/W
0
14
13
12
11
INTP
R/W
0
10
INTN
R/W
0
9
8
7
LCOE
R/W
0
6
LCOUT
R
0
5
LCPOL
R/W
0
4
3
2
1
MODE[2:0]
R/W
0
0
R/W
0
R/W
0
Bit 15 – LCEN CLC Enable bit
Value
Description
1
CLC is enabled and mixing input signals
0
CLC is disabled and has logic zero outputs
Bit 11 – INTP CLC Positive Edge Interrupt Enable bit
Value
Description
1
Interrupt will be generated when a rising edge occurs on LCOUT
0
Interrupt will not be generated
Bit 10 – INTN CLC Negative Edge Interrupt Enable bit
Value
Description
1
Interrupt will be generated when a falling edge occurs on LCOUT
0
Interrupt will not be generated
Bit 7 – LCOE CLC Port Enable bit
Value
Description
1
CLC port pin output is enabled
0
CLC port pin output is disabled
Bit 6 – LCOUT CLC Data Output Status bit
Value
Description
1
CLC output high
0
CLC output low
Bit 5 – LCPOL CLC Output Polarity Control bit
Value
Description
1
The output of the module is inverted
0
The output of the module is not inverted
Bits 2:0 – MODE[2:0] CLC Mode bits
Value
Description
111
Cell is a 1-input transparent latch with S and R
110
Cell is a JK flip-flop with R
101
Cell is a 2-input D flip-flop with R
100
Cell is a 1-input D flip-flop with S and R
011
Cell is an SR latch
010
Cell is a 4-input AND
001
Cell is an OR-XOR
000
Cell is an AND-OR
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1040
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.3
CLC1 Control Register High
Name:
Offset:
Bit
CLC1CONH
0x466
15
14
13
12
11
10
9
8
7
6
5
4
3
G4POL
R/W
0
2
G3POL
R/W
0
1
G2POL
R/W
0
0
G1POL
R/W
0
Access
Reset
Bit
Access
Reset
Bit 3 – G4POL Gate 4 Polarity Control bit
Value
Description
1
The output of Channel 4 logic is inverted when applied to the logic cell
0
The output of Channel 4 logic is not inverted
Bit 2 – G3POL Gate 3 Polarity Control bit
Value
Description
1
The output of Channel 3 logic is inverted when applied to the logic cell
0
The output of Channel 3 logic is not inverted
Bit 1 – G2POL Gate 2 Polarity Control bit
Value
Description
1
The output of Channel 2 logic is inverted when applied to the logic cell
0
The output of Channel 2 logic is not inverted
Bit 0 – G1POL Gate 1 Polarity Control bit
Value
Description
1
The output of Channel 1 logic is inverted when applied to the logic cell
0
The output of Channel 1 logic is not inverted
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1041
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.4
CLC1 Input MUX Select Register
Name:
Offset:
Bit
15
Access
Reset
Bit
Access
Reset
CLC1SEL
0x468
14
R/W
0
7
6
R/W
0
13
DS4[2:0]
R/W
0
5
DS2[2:0]
R/W
0
12
11
R/W
0
10
R/W
0
4
3
R/W
0
2
R/W
0
9
DS3[2:0]
R/W
0
1
DS1[2:0]
R/W
0
8
R/W
0
0
R/W
0
Bits 14:12 – DS4[2:0] Data Selection MUX 4 Signal Selection bits
Value
Description
111
MCCP3 output
110
MCCP1 output
101
Unimplemented
100
LCD automation timer
011
SPI1 Input (SDI1)
010
Comparator 3 output
001
CLC2 output
000
CLCIND pin
Bits 10:8 – DS3[2:0] Data Selection MUX 3 Signal Selection bits
Value
Description
111
MCCP3 output
110
MCCP2 output
101
DMA Channel 1
100
UART1 Input (U1RX)
011
SPI1 Output (SDO1)
010
Comparator 2 output
001
CLC1 output
000
CLCINC pin
Bits 6:4 – DS2[2:0] Data Selection MUX 2 Signal Selection bits
Value
Description
111
MCCP2 output
110
MCCP1 output
101
DMA Channel 0
100
A/D conversion done
011
UART1 Output (U1TX)
010
Comparator 1 output
001
CLC2 output
000
CLCINB pin
Bits 2:0 – DS1[2:0] Data Selection MUX 1 Signal Selection bits
Value
Description
111
Timer3 match event
110
Timer2 match event
101
Unimplemented
100
Reference Clock Output (REFO)
011
LPRC
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1042
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
Value
010
001
000
Description
SOSC
Peripheral clock (FPB)
CLCINA pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1043
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.5
CLC1 Gate Logic Input Select Low Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CLC1GLSL
0x46C
15
G2D4T
R/W
0
14
G2D4N
R/W
0
13
G2D3T
R/W
0
12
G2D3N
R/W
0
11
G2D3N
R/W
0
10
G2D2N
R/W
0
9
G2D1T
R/W
0
8
G2D1N
R/W
0
7
G1D4T
R/W
0
6
G1D4N
R/W
0
5
G1D3T
R/W
0
4
G1D3N
R/W
0
3
G1D2T
R/W
0
2
G1D2N
R/W
0
1
G1D1T
R/W
0
0
G1D1N
R/W
0
Bit 15 – G2D4T Gate 2 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 2
0
The Data Source 4 signal is disabled for Gate 2
Bit 14 – G2D4N Gate 2 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 2
0
The Data Source 4 inverted signal is disabled for Gate 2
Bit 13 – G2D3T Gate 2 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 2
0
The Data Source 3 signal is disabled for Gate 2
Bit 12 – G2D3N Gate 2 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 2
0
The Data Source 3 inverted signal is disabled for Gate 2
Bit 11 – G2D3N Gate 2 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 2
0
The Data Source 2 signal is disabled for Gate 2
Bit 10 – G2D2N Gate 2 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 2
0
The Data Source 2 inverted signal is disabled for Gate 2
Bit 9 – G2D1T Gate 2 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 2
0
The Data Source 1 signal is disabled for Gate 2
Bit 8 – G2D1N Gate 2 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 2
0
The Data Source 1 inverted signal is disabled for Gate 2
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1044
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
Bit 7 – G1D4T Gate 1 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 1
0
The Data Source 4 signal is disabled for Gate 1
Bit 6 – G1D4N Gate 1 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 1
0
The Data Source 4 inverted signal is disabled for Gate 1
Bit 5 – G1D3T Gate 1 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 1
0
The Data Source 3 signal is disabled for Gate 1
Bit 4 – G1D3N Gate 1 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 1
0
The Data Source 3 inverted signal is disabled for Gate 1
Bit 3 – G1D2T Gate 1 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 1
0
The Data Source 2 signal is disabled for Gate 1
Bit 2 – G1D2N Gate 1 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 1
0
The Data Source 2 inverted signal is disabled for Gate 1
Bit 1 – G1D1T Gate 1 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 1
0
The Data Source 1 signal is disabled for Gate 1
Bit 0 – G1D1N Gate 1 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 1
0
The Data Source 1 inverted signal is disabled for Gate 1
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1045
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.6
CLC1 Gate Logic Input Select High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CLC1GLSH
0x46E
15
G4D4T
R/W
0
14
G4D4N
R/W
0
13
G4D3T
R/W
0
12
G4D3N
R/W
0
11
G4D2N
R/W
0
10
G4D2N
R/W
0
9
G4D1T
R/W
0
8
G4D1N
R/W
0
7
G3D4T
R/W
0
6
G3D4N
R/W
0
5
G3D3T
R/W
0
4
G3D3N
R/W
0
3
G3D2T
R/W
0
2
G3D2N
R/W
0
1
G3D1T
R/W
0
0
G3D1N
R/W
0
Bit 15 – G4D4T Gate 4 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 4
0
The Data Source 4 signal is disabled for Gate 4
Bit 14 – G4D4N Gate 4 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 4
0
The Data Source 4 inverted signal is disabled for Gate 4
Bit 13 – G4D3T Gate 4 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 4
0
The Data Source 3 signal is disabled for Gate 4
Bit 12 – G4D3N Gate 4 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 4
0
The Data Source 3 inverted signal is disabled for Gate 4
Bit 11 – G4D2N Gate 4 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 4
0
The Data Source 2 signal is disabled for Gate 4
Bit 10 – G4D2N Gate 4 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 4
0
The Data Source 2 inverted signal is disabled for Gate 4
Bit 9 – G4D1T Gate 4 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 4
0
The Data Source 1 signal is disabled for Gate 4
Bit 8 – G4D1N Gate 4 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 4
0
The Data Source 1 inverted signal is disabled for Gate 4
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1046
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
Bit 7 – G3D4T Gate 3 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 3
0
The Data Source 4 signal is disabled for Gate 3
Bit 6 – G3D4N Gate 3 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 3
0
The Data Source 4 inverted signal is disabled for Gate 3
Bit 5 – G3D3T Gate 3 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 3
0
The Data Source 3 signal is disabled for Gate 3
Bit 4 – G3D3N Gate 3 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 3
0
The Data Source 3 inverted signal is disabled for Gate 3
Bit 3 – G3D2T Gate 3 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 3
0
The Data Source 2 signal is disabled for Gate 3
Bit 2 – G3D2N Gate 3 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 3
0
The Data Source 2 inverted signal is disabled for Gate 3
Bit 1 – G3D1T Gate 3 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 3
0
The Data Source 1 signal is disabled for Gate 3
Bit 0 – G3D1N Gate 3 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 3
0
The Data Source 1 inverted signal is disabled for Gate 3
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1047
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.7
CLC2 Control Register Low
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CLC2CONL
0x470
15
LCEN
R/W
0
14
13
12
11
INTP
R/W
0
10
INTN
R/W
0
9
8
7
LCOE
R/W
0
6
LCOUT
R
0
5
LCPOL
R/W
0
4
3
2
1
MODE[2:0]
R/W
0
0
R/W
0
R/W
0
Bit 15 – LCEN CLC Enable bit
Value
Description
1
CLC is enabled and mixing input signals
0
CLC is disabled and has logic zero outputs
Bit 11 – INTP CLC Positive Edge Interrupt Enable bit
Value
Description
1
Interrupt will be generated when a rising edge occurs on LCOUT
0
Interrupt will not be generated
Bit 10 – INTN CLC Negative Edge Interrupt Enable bit
Value
Description
1
Interrupt will be generated when a falling edge occurs on LCOUT
0
Interrupt will not be generated
Bit 7 – LCOE CLC Port Enable bit
Value
Description
1
CLC port pin output is enabled
0
CLC port pin output is disabled
Bit 6 – LCOUT CLC Data Output Status bit
Value
Description
1
CLC output high
0
CLC output low
Bit 5 – LCPOL CLC Output Polarity Control bit
Value
Description
1
The output of the module is inverted
0
The output of the module is not inverted
Bits 2:0 – MODE[2:0] CLC Mode bits
Value
Description
111
Cell is a 1-input transparent latch with S and R
110
Cell is a JK flip-flop with R
101
Cell is a 2-input D flip-flop with R
100
Cell is a 1-input D flip-flop with S and R
011
Cell is an SR latch
010
Cell is a 4-input AND
001
Cell is an OR-XOR
000
Cell is an AND-OR
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1048
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.8
CLC2 Control Register High
Name:
Offset:
Bit
CLC2CONH
0x472
15
14
13
12
11
10
9
8
7
6
5
4
3
G4POL
R/W
0
2
G3POL
R/W
0
1
G2POL
R/W
0
0
G1POL
R/W
0
Access
Reset
Bit
Access
Reset
Bit 3 – G4POL Gate 4 Polarity Control bit
Value
Description
1
The output of Channel 4 logic is inverted when applied to the logic cell
0
The output of Channel 4 logic is not inverted
Bit 2 – G3POL Gate 3 Polarity Control bit
Value
Description
1
The output of Channel 3 logic is inverted when applied to the logic cell
0
The output of Channel 3 logic is not inverted
Bit 1 – G2POL Gate 2 Polarity Control bit
Value
Description
1
The output of Channel 2 logic is inverted when applied to the logic cell
0
The output of Channel 2 logic is not inverted
Bit 0 – G1POL Gate 1 Polarity Control bit
Value
Description
1
The output of Channel 1 logic is inverted when applied to the logic cell
0
The output of Channel 1 logic is not inverted
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1049
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.9
CLC2 Input MUX Select Register
Name:
Offset:
Bit
15
Access
Reset
Bit
Access
Reset
CLC2SEL
0x474
14
R/W
0
7
6
R/W
0
13
DS4[2:0]
R/W
0
5
DS2[2:0]
R/W
0
12
11
R/W
0
10
R/W
0
4
3
R/W
0
2
R/W
0
9
DS3[2:0]
R/W
0
1
DS1[2:0]
R/W
0
8
R/W
0
0
R/W
0
Bits 14:12 – DS4[2:0] Data Selection MUX 4 Signal Selection bits
Value
Description
111
MCCP3 output
110
MCCP1 output
101
Unimplemented
100
LCD automation timer
011
SPI2 Input (SDI1)
010
Comparator 3 output
001
CLC1 output
000
CLCIND pin
Bits 10:8 – DS3[2:0] Data Selection MUX 3 Signal Selection bits
Value
Description
111
MCCP3 output
110
MCCP2 output
101
DMA Channel 1
100
UART2 Input (U2RX)
011
SPI2 Output (SDO2)
010
Comparator 2 output
001
CLC2 output
000
CLCINC pin
Bits 6:4 – DS2[2:0] Data Selection MUX 2 Signal Selection bits
Value
Description
111
MCCP2 output
110
MCCP1 output
101
DMA Channel 0
100
A/D conversion done
011
UART2 Output (U2TX)
010
Comparator 1 output
001
CLC1 output
000
CLCINB pin
Bits 2:0 – DS1[2:0] Data Selection MUX 1 Signal Selection bits
Value
Description
111
Timer3 match event
110
Timer2 match event
101
Unimplemented
100
Reference Clock Output (REFO)
011
LPRC
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1050
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
Value
010
001
000
Description
SOSC
Peripheral clock (FPB)
CLCINA pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1051
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.10 CLC2 Gate Logic Input Select Low Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CLC2GLSL
0x478
15
G2D4T
R/W
0
14
G2D4N
R/W
0
13
G2D3T
R/W
0
12
G2D3N
R/W
0
11
G2D3N
R/W
0
10
G2D2N
R/W
0
9
G2D1T
R/W
0
8
G2D1N
R/W
0
7
G1D4T
R/W
0
6
G1D4N
R/W
0
5
G1D3T
R/W
0
4
G1D3N
R/W
0
3
G1D2T
R/W
0
2
G1D2N
R/W
0
1
G1D1T
R/W
0
0
G1D1N
R/W
0
Bit 15 – G2D4T Gate 2 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 2
0
The Data Source 4 signal is disabled for Gate 2
Bit 14 – G2D4N Gate 2 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 2
0
The Data Source 4 inverted signal is disabled for Gate 2
Bit 13 – G2D3T Gate 2 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 2
0
The Data Source 3 signal is disabled for Gate 2
Bit 12 – G2D3N Gate 2 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 2
0
The Data Source 3 inverted signal is disabled for Gate 2
Bit 11 – G2D3N Gate 2 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 2
0
The Data Source 2 signal is disabled for Gate 2
Bit 10 – G2D2N Gate 2 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 2
0
The Data Source 2 inverted signal is disabled for Gate 2
Bit 9 – G2D1T Gate 2 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 2
0
The Data Source 1 signal is disabled for Gate 2
Bit 8 – G2D1N Gate 2 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 2
0
The Data Source 1 inverted signal is disabled for Gate 2
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1052
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
Bit 7 – G1D4T Gate 1 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 1
0
The Data Source 4 signal is disabled for Gate 1
Bit 6 – G1D4N Gate 1 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 1
0
The Data Source 4 inverted signal is disabled for Gate 1
Bit 5 – G1D3T Gate 1 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 1
0
The Data Source 3 signal is disabled for Gate 1
Bit 4 – G1D3N Gate 1 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 1
0
The Data Source 3 inverted signal is disabled for Gate 1
Bit 3 – G1D2T Gate 1 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 1
0
The Data Source 2 signal is disabled for Gate 1
Bit 2 – G1D2N Gate 1 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 1
0
The Data Source 2 inverted signal is disabled for Gate 1
Bit 1 – G1D1T Gate 1 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 1
0
The Data Source 1 signal is disabled for Gate 1
Bit 0 – G1D1N Gate 1 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 1
0
The Data Source 1 inverted signal is disabled for Gate 1
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1053
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.11 CLC2 Gate Logic Input Select High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CLC2GLSH
0x47A
15
G4D4T
R/W
0
14
G4D4N
R/W
0
13
G4D3T
R/W
0
12
G4D3N
R/W
0
11
G4D2N
R/W
0
10
G4D2N
R/W
0
9
G4D1T
R/W
0
8
G4D1N
R/W
0
7
G3D4T
R/W
0
6
G3D4N
R/W
0
5
G3D3T
R/W
0
4
G3D3N
R/W
0
3
G3D2T
R/W
0
2
G3D2N
R/W
0
1
G3D1T
R/W
0
0
G3D1N
R/W
0
Bit 15 – G4D4T Gate 4 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 4
0
The Data Source 4 signal is disabled for Gate 4
Bit 14 – G4D4N Gate 4 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 4
0
The Data Source 4 inverted signal is disabled for Gate 4
Bit 13 – G4D3T Gate 4 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 4
0
The Data Source 3 signal is disabled for Gate 4
Bit 12 – G4D3N Gate 4 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 4
0
The Data Source 3 inverted signal is disabled for Gate 4
Bit 11 – G4D2N Gate 4 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 4
0
The Data Source 2 signal is disabled for Gate 4
Bit 10 – G4D2N Gate 4 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 4
0
The Data Source 2 inverted signal is disabled for Gate 4
Bit 9 – G4D1T Gate 4 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 4
0
The Data Source 1 signal is disabled for Gate 4
Bit 8 – G4D1N Gate 4 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 4
0
The Data Source 1 inverted signal is disabled for Gate 4
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1054
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
Bit 7 – G3D4T Gate 3 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 3
0
The Data Source 4 signal is disabled for Gate 3
Bit 6 – G3D4N Gate 3 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 3
0
The Data Source 4 inverted signal is disabled for Gate 3
Bit 5 – G3D3T Gate 3 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 3
0
The Data Source 3 signal is disabled for Gate 3
Bit 4 – G3D3N Gate 3 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 3
0
The Data Source 3 inverted signal is disabled for Gate 3
Bit 3 – G3D2T Gate 3 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 3
0
The Data Source 2 signal is disabled for Gate 3
Bit 2 – G3D2N Gate 3 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 3
0
The Data Source 2 inverted signal is disabled for Gate 3
Bit 1 – G3D1T Gate 3 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 3
0
The Data Source 1 signal is disabled for Gate 3
Bit 0 – G3D1N Gate 3 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 3
0
The Data Source 1 inverted signal is disabled for Gate 3
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1055
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.12 CLC3 Control Register Low
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CLC3CONL
0x47C
15
LCEN
R/W
0
14
13
12
11
INTP
R/W
0
10
INTN
R/W
0
9
8
7
LCOE
R/W
0
6
LCOUT
R
0
5
LCPOL
R/W
0
4
3
2
1
MODE[2:0]
R/W
0
0
R/W
0
R/W
0
Bit 15 – LCEN CLC Enable bit
Value
Description
1
CLC is enabled and mixing input signals
0
CLC is disabled and has logic zero outputs
Bit 11 – INTP CLC Positive Edge Interrupt Enable bit
Value
Description
1
Interrupt will be generated when a rising edge occurs on LCOUT
0
Interrupt will not be generated
Bit 10 – INTN CLC Negative Edge Interrupt Enable bit
Value
Description
1
Interrupt will be generated when a falling edge occurs on LCOUT
0
Interrupt will not be generated
Bit 7 – LCOE CLC Port Enable bit
Value
Description
1
CLC port pin output is enabled
0
CLC port pin output is disabled
Bit 6 – LCOUT CLC Data Output Status bit
Value
Description
1
CLC output high
0
CLC output low
Bit 5 – LCPOL CLC Output Polarity Control bit
Value
Description
1
The output of the module is inverted
0
The output of the module is not inverted
Bits 2:0 – MODE[2:0] CLC Mode bits
Value
Description
111
Cell is a 1-input transparent latch with S and R
110
Cell is a JK flip-flop with R
101
Cell is a 2-input D flip-flop with R
100
Cell is a 1-input D flip-flop with S and R
011
Cell is an SR latch
010
Cell is a 4-input AND
001
Cell is an OR-XOR
000
Cell is an AND-OR
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1056
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.13 CLC3 Control Register High
Name:
Offset:
Bit
CLC3CONH
0x47E
15
14
13
12
11
10
9
8
7
6
5
4
3
G4POL
R/W
0
2
G3POL
R/W
0
1
G2POL
R/W
0
0
G1POL
R/W
0
Access
Reset
Bit
Access
Reset
Bit 3 – G4POL Gate 4 Polarity Control bit
Value
Description
1
The output of Channel 4 logic is inverted when applied to the logic cell
0
The output of Channel 4 logic is not inverted
Bit 2 – G3POL Gate 3 Polarity Control bit
Value
Description
1
The output of Channel 3 logic is inverted when applied to the logic cell
0
The output of Channel 3 logic is not inverted
Bit 1 – G2POL Gate 2 Polarity Control bit
Value
Description
1
The output of Channel 2 logic is inverted when applied to the logic cell
0
The output of Channel 2 logic is not inverted
Bit 0 – G1POL Gate 1 Polarity Control bit
Value
Description
1
The output of Channel 1 logic is inverted when applied to the logic cell
0
The output of Channel 1 logic is not inverted
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1057
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.14 CLC3 Input MUX Select Register
Name:
Offset:
Bit
15
Access
Reset
Bit
Access
Reset
CLC3SEL
0x484
14
R/W
0
7
6
R/W
0
13
DS4[2:0]
R/W
0
5
DS2[2:0]
R/W
0
12
11
R/W
0
10
R/W
0
4
3
R/W
0
2
R/W
0
9
DS3[2:0]
R/W
0
1
DS1[2:0]
R/W
0
8
R/W
0
0
R/W
0
Bits 14:12 – DS4[2:0] Data Selection MUX 4 Signal Selection bits
Value
Description
111
MCCP3 output
110
MCCP1 output
101
Unimplemented
100
LCD automation timer
011
SPI3 Input (SDI3)
010
Comparator 3 output
001
CLC4 output
000
CLCIND pin
Bits 10:8 – DS3[2:0] Data Selection MUX 3 Signal Selection bits
Value
Description
111
MCCP3 output
110
MCCP2 output
101
DMA Channel 1
100
UART3 Input (U3RX)
011
SPI3 Output (SDO3)
010
Comparator 2 output
001
CLC1 output
000
CLCINC pin
Bits 6:4 – DS2[2:0] Data Selection MUX 2 Signal Selection bits
Value
Description
111
MCCP2 output
110
MCCP1 output
101
DMA Channel 0
100
A/D conversion done
011
UART3 Output (U3TX)
010
Comparator 1 output
001
CLC2 output
000
CLCINB pin
Bits 2:0 – DS1[2:0] Data Selection MUX 1 Signal Selection bits
Value
Description
111
Timer3 match event
110
Timer2 match event
101
Unimplemented
100
Reference Clock Output (REFO)
011
LPRC
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1058
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
Value
010
001
000
Description
SOSC
Peripheral clock (FPB)
CLCINA pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1059
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.15 CLC3 Gate Logic Input Select Low Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CLC3GLSL
0x484
15
G2D4T
R/W
0
14
G2D4N
R/W
0
13
G2D3T
R/W
0
12
G2D3N
R/W
0
11
G2D3N
R/W
0
10
G2D2N
R/W
0
9
G2D1T
R/W
0
8
G2D1N
R/W
0
7
G1D4T
R/W
0
6
G1D4N
R/W
0
5
G1D3T
R/W
0
4
G1D3N
R/W
0
3
G1D2T
R/W
0
2
G1D2N
R/W
0
1
G1D1T
R/W
0
0
G1D1N
R/W
0
Bit 15 – G2D4T Gate 2 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 2
0
The Data Source 4 signal is disabled for Gate 2
Bit 14 – G2D4N Gate 2 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 2
0
The Data Source 4 inverted signal is disabled for Gate 2
Bit 13 – G2D3T Gate 2 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 2
0
The Data Source 3 signal is disabled for Gate 2
Bit 12 – G2D3N Gate 2 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 2
0
The Data Source 3 inverted signal is disabled for Gate 2
Bit 11 – G2D3N Gate 2 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 2
0
The Data Source 2 signal is disabled for Gate 2
Bit 10 – G2D2N Gate 2 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 2
0
The Data Source 2 inverted signal is disabled for Gate 2
Bit 9 – G2D1T Gate 2 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 2
0
The Data Source 1 signal is disabled for Gate 2
Bit 8 – G2D1N Gate 2 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 2
0
The Data Source 1 inverted signal is disabled for Gate 2
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1060
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
Bit 7 – G1D4T Gate 1 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 1
0
The Data Source 4 signal is disabled for Gate 1
Bit 6 – G1D4N Gate 1 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 1
0
The Data Source 4 inverted signal is disabled for Gate 1
Bit 5 – G1D3T Gate 1 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 1
0
The Data Source 3 signal is disabled for Gate 1
Bit 4 – G1D3N Gate 1 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 1
0
The Data Source 3 inverted signal is disabled for Gate 1
Bit 3 – G1D2T Gate 1 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 1
0
The Data Source 2 signal is disabled for Gate 1
Bit 2 – G1D2N Gate 1 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 1
0
The Data Source 2 inverted signal is disabled for Gate 1
Bit 1 – G1D1T Gate 1 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 1
0
The Data Source 1 signal is disabled for Gate 1
Bit 0 – G1D1N Gate 1 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 1
0
The Data Source 1 inverted signal is disabled for Gate 1
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1061
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.16 CLC3 Gate Logic Input Select High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CLC3GLSH
0x486
15
G4D4T
R/W
0
14
G4D4N
R/W
0
13
G4D3T
R/W
0
12
G4D3N
R/W
0
11
G4D2N
R/W
0
10
G4D2N
R/W
0
9
G4D1T
R/W
0
8
G4D1N
R/W
0
7
G3D4T
R/W
0
6
G3D4N
R/W
0
5
G3D3T
R/W
0
4
G3D3N
R/W
0
3
G3D2T
R/W
0
2
G3D2N
R/W
0
1
G3D1T
R/W
0
0
G3D1N
R/W
0
Bit 15 – G4D4T Gate 4 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 4
0
The Data Source 4 signal is disabled for Gate 4
Bit 14 – G4D4N Gate 4 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 4
0
The Data Source 4 inverted signal is disabled for Gate 4
Bit 13 – G4D3T Gate 4 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 4
0
The Data Source 3 signal is disabled for Gate 4
Bit 12 – G4D3N Gate 4 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 4
0
The Data Source 3 inverted signal is disabled for Gate 4
Bit 11 – G4D2N Gate 4 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 4
0
The Data Source 2 signal is disabled for Gate 4
Bit 10 – G4D2N Gate 4 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 4
0
The Data Source 2 inverted signal is disabled for Gate 4
Bit 9 – G4D1T Gate 4 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 4
0
The Data Source 1 signal is disabled for Gate 4
Bit 8 – G4D1N Gate 4 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 4
0
The Data Source 1 inverted signal is disabled for Gate 4
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1062
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
Bit 7 – G3D4T Gate 3 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 3
0
The Data Source 4 signal is disabled for Gate 3
Bit 6 – G3D4N Gate 3 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 3
0
The Data Source 4 inverted signal is disabled for Gate 3
Bit 5 – G3D3T Gate 3 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 3
0
The Data Source 3 signal is disabled for Gate 3
Bit 4 – G3D3N Gate 3 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 3
0
The Data Source 3 inverted signal is disabled for Gate 3
Bit 3 – G3D2T Gate 3 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 3
0
The Data Source 2 signal is disabled for Gate 3
Bit 2 – G3D2N Gate 3 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 3
0
The Data Source 2 inverted signal is disabled for Gate 3
Bit 1 – G3D1T Gate 3 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 3
0
The Data Source 1 signal is disabled for Gate 3
Bit 0 – G3D1N Gate 3 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 3
0
The Data Source 1 inverted signal is disabled for Gate 3
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1063
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.17 CLC4 Control Register Low
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CLC4CONL
0x488
15
LCEN
R/W
0
14
13
12
11
INTP
R/W
0
10
INTN
R/W
0
9
8
7
LCOE
R/W
0
6
LCOUT
R
0
5
LCPOL
R/W
0
4
3
2
1
MODE[2:0]
R/W
0
0
R/W
0
R/W
0
Bit 15 – LCEN CLC Enable bit
Value
Description
1
CLC is enabled and mixing input signals
0
CLC is disabled and has logic zero outputs
Bit 11 – INTP CLC Positive Edge Interrupt Enable bit
Value
Description
1
Interrupt will be generated when a rising edge occurs on LCOUT
0
Interrupt will not be generated
Bit 10 – INTN CLC Negative Edge Interrupt Enable bit
Value
Description
1
Interrupt will be generated when a falling edge occurs on LCOUT
0
Interrupt will not be generated
Bit 7 – LCOE CLC Port Enable bit
Value
Description
1
CLC port pin output is enabled
0
CLC port pin output is disabled
Bit 6 – LCOUT CLC Data Output Status bit
Value
Description
1
CLC output high
0
CLC output low
Bit 5 – LCPOL CLC Output Polarity Control bit
Value
Description
1
The output of the module is inverted
0
The output of the module is not inverted
Bits 2:0 – MODE[2:0] CLC Mode bits
Value
Description
111
Cell is a 1-input transparent latch with S and R
110
Cell is a JK flip-flop with R
101
Cell is a 2-input D flip-flop with R
100
Cell is a 1-input D flip-flop with S and R
011
Cell is an SR latch
010
Cell is a 4-input AND
001
Cell is an OR-XOR
000
Cell is an AND-OR
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1064
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.18 CLC4 Control Register High
Name:
Offset:
Bit
CLC4CONH
0x48A
15
14
13
12
11
10
9
8
7
6
5
4
3
G4POL
R/W
0
2
G3POL
R/W
0
1
G2POL
R/W
0
0
G1POL
R/W
0
Access
Reset
Bit
Access
Reset
Bit 3 – G4POL Gate 4 Polarity Control bit
Value
Description
1
The output of Channel 4 logic is inverted when applied to the logic cell
0
The output of Channel 4 logic is not inverted
Bit 2 – G3POL Gate 3 Polarity Control bit
Value
Description
1
The output of Channel 3 logic is inverted when applied to the logic cell
0
The output of Channel 3 logic is not inverted
Bit 1 – G2POL Gate 2 Polarity Control bit
Value
Description
1
The output of Channel 2 logic is inverted when applied to the logic cell
0
The output of Channel 2 logic is not inverted
Bit 0 – G1POL Gate 1 Polarity Control bit
Value
Description
1
The output of Channel 1 logic is inverted when applied to the logic cell
0
The output of Channel 1 logic is not inverted
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1065
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.19 CLC4 Input MUX Select Register
Name:
Offset:
Bit
15
Access
Reset
Bit
Access
Reset
CLC4SEL
0x48C
14
R/W
0
7
6
R/W
0
13
DS4[2:0]
R/W
0
5
DS2[2:0]
R/W
0
12
11
R/W
0
10
R/W
0
4
3
R/W
0
2
R/W
0
9
DS3[2:0]
R/W
0
1
DS1[2:0]
R/W
0
8
R/W
0
0
R/W
0
Bits 14:12 – DS4[2:0] Data Selection MUX 4 Signal Selection bits
Value
Description
111
MCCP3 output
110
MCCP1 output
101
Unimplemented
100
LCD automation timer
011
SPI4 Input (SDI4)
010
Comparator 3 output
001
CLC3 output
000
CLCIND pin
Bits 10:8 – DS3[2:0] Data Selection MUX 3 Signal Selection bits
Value
Description
111
MCCP3 output
110
MCCP2 output
101
DMA Channel 1
100
UART4 Input (U4RX)
011
SPI4 Output (SDO4)
010
Comparator 2 output
001
CLC2 output
000
CLCINC pin
Bits 6:4 – DS2[2:0] Data Selection MUX 2 Signal Selection bits
Value
Description
111
MCCP2 output
110
MCCP1 output
101
DMA Channel 0
100
A/D conversion done
011
UART4 Output (U4TX)
010
Comparator 1 output
001
CLC1 output
000
CLCINB pin
Bits 2:0 – DS1[2:0] Data Selection MUX 1 Signal Selection bits
Value
Description
111
Timer3 match event
110
Timer2 match event
101
Unimplemented
100
Reference Clock Output (REFO)
011
LPRC
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1066
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
Value
010
001
000
Description
SOSC
Peripheral clock (FPB)
CLCINA pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1067
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.20 CLC4 Gate Logic Input Select Low Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CLC4GLSL
0x490
15
G2D4T
R/W
0
14
G2D4N
R/W
0
13
G2D3T
R/W
0
12
G2D3N
R/W
0
11
G2D3N
R/W
0
10
G2D2N
R/W
0
9
G2D1T
R/W
0
8
G2D1N
R/W
0
7
G1D4T
R/W
0
6
G1D4N
R/W
0
5
G1D3T
R/W
0
4
G1D3N
R/W
0
3
G1D2T
R/W
0
2
G1D2N
R/W
0
1
G1D1T
R/W
0
0
G1D1N
R/W
0
Bit 15 – G2D4T Gate 2 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 2
0
The Data Source 4 signal is disabled for Gate 2
Bit 14 – G2D4N Gate 2 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 2
0
The Data Source 4 inverted signal is disabled for Gate 2
Bit 13 – G2D3T Gate 2 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 2
0
The Data Source 3 signal is disabled for Gate 2
Bit 12 – G2D3N Gate 2 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 2
0
The Data Source 3 inverted signal is disabled for Gate 2
Bit 11 – G2D3N Gate 2 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 2
0
The Data Source 2 signal is disabled for Gate 2
Bit 10 – G2D2N Gate 2 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 2
0
The Data Source 2 inverted signal is disabled for Gate 2
Bit 9 – G2D1T Gate 2 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 2
0
The Data Source 1 signal is disabled for Gate 2
Bit 8 – G2D1N Gate 2 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 2
0
The Data Source 1 inverted signal is disabled for Gate 2
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1068
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
Bit 7 – G1D4T Gate 1 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 1
0
The Data Source 4 signal is disabled for Gate 1
Bit 6 – G1D4N Gate 1 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 1
0
The Data Source 4 inverted signal is disabled for Gate 1
Bit 5 – G1D3T Gate 1 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 1
0
The Data Source 3 signal is disabled for Gate 1
Bit 4 – G1D3N Gate 1 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 1
0
The Data Source 3 inverted signal is disabled for Gate 1
Bit 3 – G1D2T Gate 1 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 1
0
The Data Source 2 signal is disabled for Gate 1
Bit 2 – G1D2N Gate 1 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 1
0
The Data Source 2 inverted signal is disabled for Gate 1
Bit 1 – G1D1T Gate 1 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 1
0
The Data Source 1 signal is disabled for Gate 1
Bit 0 – G1D1N Gate 1 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 1
0
The Data Source 1 inverted signal is disabled for Gate 1
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1069
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
21.1.21 CLC4 Gate Logic Input Select High Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
CLC4GLSH
0x492
15
G4D4T
R/W
0
14
G4D4N
R/W
0
13
G4D3T
R/W
0
12
G4D3N
R/W
0
11
G4D2N
R/W
0
10
G4D2N
R/W
0
9
G4D1T
R/W
0
8
G4D1N
R/W
0
7
G3D4T
R/W
0
6
G3D4N
R/W
0
5
G3D3T
R/W
0
4
G3D3N
R/W
0
3
G3D2T
R/W
0
2
G3D2N
R/W
0
1
G3D1T
R/W
0
0
G3D1N
R/W
0
Bit 15 – G4D4T Gate 4 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 4
0
The Data Source 4 signal is disabled for Gate 4
Bit 14 – G4D4N Gate 4 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 4
0
The Data Source 4 inverted signal is disabled for Gate 4
Bit 13 – G4D3T Gate 4 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 4
0
The Data Source 3 signal is disabled for Gate 4
Bit 12 – G4D3N Gate 4 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 4
0
The Data Source 3 inverted signal is disabled for Gate 4
Bit 11 – G4D2N Gate 4 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 4
0
The Data Source 2 signal is disabled for Gate 4
Bit 10 – G4D2N Gate 4 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 4
0
The Data Source 2 inverted signal is disabled for Gate 4
Bit 9 – G4D1T Gate 4 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 4
0
The Data Source 1 signal is disabled for Gate 4
Bit 8 – G4D1N Gate 4 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 4
0
The Data Source 1 inverted signal is disabled for Gate 4
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1070
PIC24FJ512GU410 Family Data Sheet
Configurable Logic Cell (CLC)
Bit 7 – G3D4T Gate 3 Data Source 4 True Enable bit
Value
Description
1
The Data Source 4 signal is enabled for Gate 3
0
The Data Source 4 signal is disabled for Gate 3
Bit 6 – G3D4N Gate 3 Data Source 4 Negated Enable bit
Value
Description
1
The Data Source 4 inverted signal is enabled for Gate 3
0
The Data Source 4 inverted signal is disabled for Gate 3
Bit 5 – G3D3T Gate 3 Data Source 3 True Enable bit
Value
Description
1
The Data Source 3 signal is enabled for Gate 3
0
The Data Source 3 signal is disabled for Gate 3
Bit 4 – G3D3N Gate 3 Data Source 3 Negated Enable bit
Value
Description
1
The Data Source 3 inverted signal is enabled for Gate 3
0
The Data Source 3 inverted signal is disabled for Gate 3
Bit 3 – G3D2T Gate 3 Data Source 2 True Enable bit
Value
Description
1
The Data Source 2 signal is enabled for Gate 3
0
The Data Source 2 signal is disabled for Gate 3
Bit 2 – G3D2N Gate 3 Data Source 2 Negated Enable bit
Value
Description
1
The Data Source 2 inverted signal is enabled for Gate 3
0
The Data Source 2 inverted signal is disabled for Gate 3
Bit 1 – G3D1T Gate 3 Data Source 1 True Enable bit
Value
Description
1
The Data Source 1 signal is enabled for Gate 3
0
The Data Source 1 signal is disabled for Gate 3
Bit 0 – G3D1N Gate 3 Data Source 1 Negated Enable bit
Value
Description
1
The Data Source 1 inverted signal is enabled for Gate 3
0
The Data Source 1 inverted signal is disabled for Gate 3
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1071
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.
12-Bit A/D Converter with Threshold Detect
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information on the 12-Bit A/D Converter, refer to “12-Bit A/D Converter
with Threshold Detect” (DS39739) in the “dsPIC33/PIC24 Family Reference Manual”, which is available from the
Microchip website (www.microchip.com). The information in this data sheet supersedes the information in the FRM.
The A/D Converter has the following key features:
•
•
•
•
•
•
•
•
•
•
•
•
•
Successive Approximation Register (SAR) Conversion
Selectable 10-Bit or 12-Bit (default) Conversion Resolution
Up to 28 Analog Input Channels (internal and external)
Multiple Internal Reference Input Channels
External Voltage Reference Input Pins
Unipolar Differential Sample-and-Hold (S/H) Amplifier
Automated Threshold Scan and Compare Operation to Pre-Evaluate Conversion Results
Selectable Conversion Trigger Source
Fixed Length (one word per channel), Configurable Conversion Result Buffer
Four Options for Results Alignment
Configurable Interrupt Generation
Enhanced DMA Operations with Indirect Address Generation
Operation During CPU Sleep and Idle modes
The 12-bit A/D Converter module is an enhanced version of the 10-bit module offered in earlier PIC24 devices. It is a
Successive Approximation Register (SAR) Converter, enhanced with 12-bit resolution, a wide range of automatic
sampling options, tighter integration with other analog modules and a configurable results buffer.
It also includes a unique Threshold Detect feature that allows the module itself to make simple decisions based on
the conversion results, and enhanced operation with the DMA Controller through Peripheral Indirect Addressing
(PIA).
A simplified block diagram for the module is shown in Figure 22-1.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1072
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
Figure 22-1. 12-Bit A/D Converter Block Diagram (PIC24FJ512GU410 Family)
ADC1BUF23
AN23
AD1CHITH
Note:
1. Available ANx pins are package-dependent.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1073
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.1
Basic Operation
To perform a standard A/D conversion:
1.
2.
3.
22.2
Configure the module:
1.1.
Configure port pins as analog inputs by setting the appropriate bits in the ANSx registers (see 11.2
Configuring Analog Port Pins for more information).
1.2.
Select the voltage reference source to match the expected range on analog inputs
(AD1CON2[15:13]).
1.3.
Select the positive and negative multiplexer inputs for each channel (AD1CHS[15:0]).
1.4.
Select the analog conversion clock to match the desired data rate with the processor clock
(AD1CON3[7:0]).
1.5.
Select the appropriate sample/conversion sequence (AD1CON1[7:4] and AD1CON3[12:8]).
1.6.
For Channel A scanning operations, select the positive channels to be included (AD1CSSH and
AD1CSSL registers).
1.7.
Select how conversion results are presented in the buffer (AD1CON1[9:8] and AD1CON5 register).
1.8.
Select the interrupt rate (AD1CON2[6:2]).
1.9.
Turn on A/D module (AD1CON1[15]).
Configure the A/D interrupt (if required):
2.1.
Clear the AD1IF bit (IFS0[13]).
2.2.
Enable the AD1IE interrupt (IEC0[13]).
2.3.
Select the A/D interrupt priority (IPC3[6:4]).
If the module is configured for manual sampling, set the SAMP bit (AD1CON1[1]) to begin sampling.
Extended DMA Operations
In addition to the standard features available on all 12-bit A/D Converters, PIC24FJ512GU410 family devices
implement a limited extension of DMA functionality. This extension adds features that work with the device’s DMA
Controller to expand the A/D module’s data storage abilities beyond the module’s built-in buffer.
The Extended DMA functionality is controlled by the DMAEN bit (AD1CON1[11]); setting this bit enables the
functionality. The DMABM bit (AD1CON1[12]) configures how the DMA feature operates.
22.2.1
Extended Buffer Mode
Extended Buffer mode (DMABM = 1) maps the A/D Data Buffer registers and data from all channels, above 13, into a
user-specified area of data RAM. This allows users to read the conversion results of channels above 13, which do not
have their own memory-mapped A/D buffer locations, from data memory.
To accomplish this, the DMA must be configured in Peripheral Indirect Addressing mode and the DMA destination
address must point to the beginning of the buffer. The DMA count must be set to generate an interrupt after the
desired number of conversions.
In Extended Buffer mode, the A/D control bits will function similarly to non-DMA modes. The BUFREGEN bit will still
select between FIFO mode and Channel-Aligned mode, but the number of words in the destination FIFO will be
determined by the SMPI[4:0] bits in DMA mode. In FIFO mode, the BUFM bit will still split the output FIFO into two
sets of 13 results (the SMPIx bits should be set accordingly) and the BUFS bit will still indicate which set of results is
being written to and which can be read.
22.2.2
PIA Mode
When DMABM = 0, the A/D module is configured to function with the DMA Controller for Peripheral Indirect
Addressing (PIA) mode operations. In this mode, the A/D module generates an 11-bit Indirect Address (IA). This is
ORed with the destination address in the DMA Controller to define where the A/D conversion data will be stored.
In PIA mode, the buffer space is created as a series of contiguous smaller buffers, one per analog channel. The size
of the channel buffer determines how many analog channels can be accommodated. The size of the buffer is
selected by the DMABL[2:0] bits (AD1CON4[2:0]). The size options range from a single word per buffer to 128 words.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1074
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
Each channel is allocated a buffer of this size, regardless of whether or not the channel will actually have conversion
data.
The IA is created by combining the base address within a channel buffer with three to five bits (depending on the
buffer size) to identify the channel. The base address ranges from zero to seven bits wide, depending on the buffer
size. The address is right-padded with a ‘0’ in order to maintain address alignment in the Data Space. The
concatenated channel and base address bits are then left-padded with zeros, as necessary, to complete the 11-bit IA.
The IA is configured to auto-increment which channel is written in each analog input’s sub-buffer, during write
operations, by using the SMPIx bits (AD1CON2[6:2]).
As with PIA operations for any DMA-enabled module, the base destination address in the DMADSTn register must be
masked properly to accommodate the IA. Table 22-1 shows how complete addresses are formed. Note that the
address masking varies for each buffer size option. Because of masking requirements, some address ranges may
not be available for certain buffer sizes. Users should verify that the DMA base address is compatible with the buffer
size selected.
Table 22-1. Indirect Address Generation in PIA Mode
DMABL[2:0]
Buffer Size per
Channel (words)
Generated Offset Address
(lower 11 bits)
Available Input
Channels
Allowable DMADSTn
Addresses
000
1
000 00cc ccc0
32
xxxx xxxx xx00 0000
001
2
000 0ccc ccn0
32
xxxx xxxx x000 0000
010
4
000 cccc cnn0
32
xxxx xxxx 0000 0000
011
8
00c cccc nnn0
32
xxxx xxx0 0000 0000
100
16
0cc cccn nnn0
32
xxxx xx00 0000 0000
101
32
ccc ccnn nnn0
32
xxxx x000 0000 0000
110
64
ccc cnnn nnn0
16
xxxx x000 0000 0000
111
128
ccc nnnn nnn0
8
xxxx x000 0000 0000
Legend: ccc = Channel number (three to five bits), n = Base buffer address (zero to seven bits),
x = User-definable range of DMADSTn for base address, 0 = Masked bits of DMADSTn for IA.
Figure 22-2 shows how the parts of the address define the buffer locations in data memory. In this case, the module
“allocates” 256 bytes of data RAM (1000h to 1100h) for 32 buffers of four words each. However, this is not a hard
allocation and nothing prevents these locations from being used for other purposes. For example, in the current case,
if Analog Channels 1, 3 and 8 are being sampled and converted, conversion data will only be written to the channel
buffers, starting at 1008h, 1018h and 1040h. The holes in the PIA buffer space can be used for any other purpose. It
is the user’s responsibility to keep track of buffer locations and prevent data overwrites.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1075
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
Figure 22-2. Example of Buffer Address Generation in PIA Mode
(4-Word Buffers per Channel)
22.3
Sampling Time Requirements
The analog input model of the 12-Bit High-Speed, Multiple SARs ADC is illustrated in Figure 22-3. The total
acquisition time for the Analog-to-Digital conversion is a function of the Holding Capacitor (CHOLD) charge time. For
the ADC module to meet its specified accuracy, the Holding Capacitor (CHOLD) must be allowed to fully charge to the
voltage level on the analog input pin. The analog output Source Impedance (RS), the Interconnect Impedance (RIC)
and the internal Sampling Switch Impedance (RSS) combine to directly affect the time required to charge the CHOLD.
The combined impedance of the analog sources must, therefore, be small enough to fully charge the Holding
Capacitor within the selected sample time.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1076
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
Figure 22-3. 12-Bit A/D Converter Analog Input Model
Note: The CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if
Rs ≤ 2.5 kΩ.
To charge this capacitor to the input signal level with precision 0.5 LSB, the following sampling time is required:
TSAMPLE = RTOTAL x CHOLD x ln(2Number Bits +1) or
TSAMPLE = RTOTAL x CHOLD x ln(2048) = 7.6 x 40 pF x RTOTAL for 10-bit mode and
TSAMPLE = RTOTAL x CHOLD x ln(8192) = 9 x 40 pF x RTOTAL for 12-bit mode,
where RTOTAL = RS + RIC + RSS
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1077
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4
12-Bit A/D Converter Registers
Offset
Name
0x00
...
0x06FF
Reserved
0x0700
ADC1BUF0
0x0702
ADC1BUF1
0x0704
ADC1BUF2
0x0706
ADC1BUF3
0x0708
ADC1BUF4
0x070A
ADC1BUF5
0x070C
ADC1BUF6
0x070E
ADC1BUF7
0x0710
ADC1BUF8
0x0712
ADC1BUF9
0x0714
ADC1BUF10
0x0716
ADC1BUF11
0x0718
ADC1BUF12
0x071A
ADC1BUF13
0x071C
ADC1BUF14
0x071E
ADC1BUF15
0x0720
ADC1BUF16
0x0722
ADC1BUF17
0x0724
ADC1BUF18
0x0726
ADC1BUF19
0x0728
ADC1BUF20
0x072A
ADC1BUF21
0x072C
ADC1BUF22
0x072E
ADC1BUF23
0x0730
...
0x0733
Reserved
0x0734
AD1CON1
Bit Pos.
7
6
5
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
4
3
2
1
0
ADC1BUF0[7:0]
ADC1BUF0[15:8]
ADC1BUF1[7:0]
ADC1BUF1[15:8]
ADC1BUF2[7:0]
ADC1BUF2[15:8]
ADC1BUF3[7:0]
ADC1BUF3[15:8]
ADC1BUF4[7:0]
ADC1BUF4[15:8]
ADC1BUF5[7:0]
ADC1BUF5[15:8]
ADC1BUF6[7:0]
ADC1BUF6[15:8]
ADC1BUF7[7:0]
ADC1BUF7[15:8]
ADC1BUF8[7:0]
ADC1BUF8[15:8]
ADC1BUF9[7:0]
ADC1BUF9[15:8]
ADC1BUF10[7:0]
ADC1BUF10[15:8]
ADC1BUF11[7:0]
ADC1BUF11[15:8]
ADC1BUF12[7:0]
ADC1BUF12[15:8]
ADC1BUF13[7:0]
ADC1BUF13[15:8]
ADC1BUF14[7:0]
ADC1BUF14[15:8]
ADC1BUF15[7:0]
ADC1BUF15[15:8]
ADC1BUF16[7:0]
ADC1BUF16[15:8]
ADC1BUF17[7:0]
ADC1BUF17[15:8]
ADC1BUF18[7:0]
ADC1BUF18[15:8]
ADC1BUF19[7:0]
ADC1BUF19[15:8]
ADC1BUF20[7:0]
ADC1BUF20[15:8]
ADC1BUF21[7:0]
ADC1BUF21[15:8]
ADC1BUF22[7:0]
ADC1BUF22[15:8]
ADC1BUF23[7:0]
ADC1BUF23[15:8]
ADON
© 2019-2020 Microchip Technology Inc.
SSRC[3:0]
ADSIDL
DMABM
Datasheet
DMAEN
ASAM
MODE12
SAMP
DONE
FORM[1:0]
DS30010203C-page 1078
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
...........continued
Offset
Name
Bit Pos.
0x0736
AD1CON2
7:0
15:8
0x0738
AD1CON3
0x073A
AD1CHS
0x073C
AD1CSSH
0x073E
AD1CSSL
0x0740
AD1CON4
0x0742
AD1CON5
0x0744
AD1CHITH
0x0746
AD1CHITL
0x0748
...
0x074B
Reserved
0x074C
AD1DMBUF
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7
6
5
4
3
2
BUFS
PVCFG[1:0]
NVCFG0
SMPI[4:0]
Reserved
BUFREGEN
CSCNA
ADRC
PUMPEN
1
0
BUFM
ALTS
ADCS[7:0]
EXTSAM
CH0NA[2:0]
CH0NB[2:0]
SAMC[4:0]
CH0SA[4:0]
CH0SB[2:0]
CSS[23:16]
CSS[30:28]
CSS[7:0]
CSS[15:8]
DMABL[2:0]
WM[1:0]
ASEN
7:0
15:8
© 2019-2020 Microchip Technology Inc.
LPEN
BGREQ
CHH[23:16]
CM[1:0]
ASINT[1:0]
CHH[7:0]
CHH[15:8]
AD1DMBUF[7:0]
AD1DMBUF[15:8]
Datasheet
DS30010203C-page 1079
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.1
ADC1 Buffer 0 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF0
0x700
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF0[15:8]
R/W
R/W
0
0
4
3
ADC1BUF0[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF0[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1080
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.2
ADC1 Buffer 1 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF1
0x702
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF1[15:8]
R/W
R/W
0
0
4
3
ADC1BUF1[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF1[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1081
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.3
ADC1 Buffer 2 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF2
0x704
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF2[15:8]
R/W
R/W
0
0
4
3
ADC1BUF2[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF2[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1082
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.4
ADC1 Buffer 3 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF3
0x706
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF3[15:8]
R/W
R/W
0
0
4
3
ADC1BUF3[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF3[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1083
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.5
ADC1 Buffer 4 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF4
0x708
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF4[15:8]
R/W
R/W
0
0
4
3
ADC1BUF4[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF4[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1084
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.6
ADC1 Buffer 5 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF5
0x70A
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF5[15:8]
R/W
R/W
0
0
4
3
ADC1BUF5[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF5[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1085
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.7
ADC1 Buffer 6 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF6
0x70C
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF6[15:8]
R/W
R/W
0
0
4
3
ADC1BUF6[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF6[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1086
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.8
ADC1 Buffer 7 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF7
0x70E
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF7[15:8]
R/W
R/W
0
0
4
3
ADC1BUF7[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF7[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1087
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.9
ADC1 Buffer 8 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF8
0x710
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF8[15:8]
R/W
R/W
0
0
4
3
ADC1BUF8[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF8[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1088
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.10 ADC1 Buffer 9 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF9
0x712
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF9[15:8]
R/W
R/W
0
0
4
3
ADC1BUF9[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF9[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1089
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.11 ADC1 Buffer 10 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF10
0x714
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF10[15:8]
R/W
R/W
0
0
4
3
ADC1BUF10[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF10[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1090
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.12 ADC1 Buffer 11 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF11
0x716
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF11[15:8]
R/W
R/W
0
0
4
3
ADC1BUF11[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF11[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1091
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.13 ADC1 Buffer 12 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF12
0x718
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF12[15:8]
R/W
R/W
0
0
4
3
ADC1BUF12[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF12[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1092
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.14 ADC1 Buffer 13 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF13
0x71A
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF13[15:8]
R/W
R/W
0
0
4
3
ADC1BUF13[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF13[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1093
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.15 ADC1 Buffer 14 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF14
0x71C
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF14[15:8]
R/W
R/W
0
0
4
3
ADC1BUF14[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF14[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1094
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.16 ADC1 Buffer 15 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF15
0x71E
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF15[15:8]
R/W
R/W
0
0
4
3
ADC1BUF15[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF15[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1095
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.17 ADC1 Buffer 16 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF16
0x720
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF16[15:8]
R/W
R/W
0
0
4
3
ADC1BUF16[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF16[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1096
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.18 ADC1 Buffer 17 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF17
0x722
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF17[15:8]
R/W
R/W
0
0
4
3
ADC1BUF17[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF17[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1097
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.19 ADC1 Buffer 18 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF18
0x724
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF18[15:8]
R/W
R/W
0
0
4
3
ADC1BUF18[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF18[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1098
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.20 ADC1 Buffer 19 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF19
0x726
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF19[15:8]
R/W
R/W
0
0
4
3
ADC1BUF19[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF19[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1099
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.21 ADC1 Buffer 20 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF20
0x728
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF20[15:8]
R/W
R/W
0
0
4
3
ADC1BUF20[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF20[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1100
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.22 ADC1 Buffer 21 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF21
0x72A
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF21[15:8]
R/W
R/W
0
0
4
3
ADC1BUF21[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF21[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1101
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.23 ADC1 Buffer 22 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF22
0x72C
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF22[15:8]
R/W
R/W
0
0
4
3
ADC1BUF22[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF22[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1102
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.24 ADC1 Buffer 23 Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
ADC1BUF23
0x72E
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
ADC1BUF23[15:8]
R/W
R/W
0
0
4
3
ADC1BUF23[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADC1BUF23[15:0] Buffer Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1103
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.25 A/D Control Register 1
Name:
Offset:
AD1CON1
0x734
Note:
1. This bit is only available when Extended DMA and buffer features are available (DMAEN = 1).
Bit
Access
Reset
Bit
15
ADON
R/W
0
14
7
6
13
ADSIDL
R/W
0
12
DMABM
R/W
0
11
DMAEN
R/W
0
10
MODE12
R/W
0
R/W
0
R/W
0
5
4
3
R/W
0
R/W
0
2
ASAM
R/W
0
1
SAMP
R/W
0
0
DONE
R/W
0
SSRC[3:0]
Access
Reset
R/W
0
R/W
0
9
8
FORM[1:0]
Bit 15 – ADON A/D Operating Mode bit
Value
Description
1
A/D Converter is operating
0
A/D Converter is off
Bit 13 – ADSIDL A/D Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bit 12 – DMABM Extended DMA Buffer Mode Select bit(1)
Value
Description
1
Extended Buffer mode: Buffer address is defined by the DMADSTn register
0
PIA mode: Buffer addresses are defined by the DMA Controller and AD1CON4[2:0]
Bit 11 – DMAEN Extended DMA/Buffer Enable bit
Value
Description
1
Extended DMA and buffer features are enabled
0
Extended features are disabled
Bit 10 – MODE12 A/D 12-Bit Operation Mode bit
Value
Description
1
12-bit A/D operation
0
10-bit A/D operation
Bits 9:8 – FORM[1:0] Data Output Format bits (see following formats)
Value
Description
11
Fractional result, signed, left-justified
10
Absolute fractional result, unsigned, left-justified
01
Decimal result, signed, right-justified
00
Absolute decimal result, unsigned, right-justified
Bits 7:4 – SSRC[3:0] Sample Clock Source Select bits
Value
Description
0111
Auto-Convert mode
0110
Timer1 (may trigger during Sleep mode)
0101
Timer1 (will not trigger during Sleep mode)
0011
Timer5
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1104
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
Value
0010
0001
0000
Description
Timer3
INT0
SAMP is cleared by software
Bit 2 – ASAM A/D Sample Auto-Start bit
Value
Description
1
Sampling begins immediately after last conversion; SAMP bit is auto-set
0
Sampling begins when SAMP bit is manually set
Bit 1 – SAMP A/D Sample Enable bit
Value
Description
1
A/D Sample-and-Hold amplifiers are sampling
0
A/D Sample-and-Hold amplifiers are holding
Bit 0 – DONE A/D Conversion Status bit
Value
Description
1
A/D conversion cycle has completed
0
A/D conversion cycle has not started or is in progress
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1105
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.26 A/D Control Register 2
Name:
Offset:
AD1CON2
0x736
Legend: r = Reserved bit
Bit
15
14
PVCFG[1:0]
R/W
R/W
0
0
Access
Reset
Bit
7
BUFS
R/W
0
Access
Reset
13
NVCFG0
R/W
0
12
Reserved
r
0
11
BUFREGEN
R/W
0
10
CSCNA
R/W
0
9
8
6
5
3
2
R/W
0
R/W
0
4
SMPI[4:0]
R/W
0
R/W
0
R/W
0
1
BUFM
R/W
0
0
ALTS
R/W
0
Bits 15:14 – PVCFG[1:0] A/D Converter Positive Voltage Reference Configuration bits
Value
Description
1x
Unimplemented, do not use
01
External VREF+
00
AVDD
Bit 13 – NVCFG0 A/D Converter Negative Voltage Reference Configuration bit
Value
Description
1
AVSS
0
AVSS
Bit 12 – Reserved Maintain as ‘0’
Bit 11 – BUFREGEN A/D Buffer Register Enable bit
Value
Description
1
Conversion result is loaded into the buffer location determined by the converted channel
0
A/D result buffer is treated as a FIFO
Bit 10 – CSCNA Scan Input Selections for CH0+ During Sample A bit
Value
Description
1
Scans inputs
0
Does not scan inputs
Bit 7 – BUFS Buffer Fill Status bit
When DMAEN = 1 and DMABM = 1:
Value Description
1
0
A/D is currently filling the destination buffer from [buffer start + (buffer size/2)] to [buffer start + (buffer size –
1)]. User should access data located from [buffer start] to [buffer start + (buffer size/2) – 1].
A/D is currently filling the destination buffer from [buffer start] to [buffer start + (buffer size/2) – 1]. User
should access data located from [buffer start + (buffer size/2)] to [buffer start + (buffer size – 1)].
When DMAEN = 0:
Value Description
1
0
A/D is currently filling ADC1BUF12-ADC1BUF23; user should access data in ADC1BUF0-ADC1BUF11
A/D is currently filling ADC1BUF0-ADC1BUF11; user should access data in ADC1BUF12-ADC1BUF23
Bits 6:2 – SMPI[4:0] Interrupt Sample/DMA Increment Rate Select bits
When DMAEN = 1 and DMABM = 0:
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1106
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
Value
Description
11111
11110
...
00001
00000
Increments the DMA address after completion of the 32nd sample/conversion operation
Increments the DMA address after completion of the 31st sample/conversion operation
Increments the DMA address after completion of the 2nd sample/conversion operation
Increments the DMA address after completion of each sample/conversion operation
When DMAEN = 1 and DMABM = 1:
Value
Description
11111
11110
...
00001
00000
Resets the DMA offset after completion of the 32nd sample/conversion operation
Resets the DMA offset after completion of the 31st sample/conversion operation
Resets the DMA offset after completion of the 2nd sample/conversion operation
Resets the DMA offset after completion of every sample/conversion operation
When DMAEN = 0:
Value
Description
11111
11110
...
00001
00000
Interrupts at the completion of the conversion for each 32nd sample
Interrupts at the completion of the conversion for each 31st sample
Interrupts at the completion of the conversion for every other sample
Interrupts at the completion of the conversion for each sample
Bit 1 – BUFM Buffer Fill Mode Select bit
Value
Description
1
Starts buffer filling at ADC1BUF0 on first interrupt and ADC1BUF12 on next interrupt
0
Always starts filling buffer at ADC1BUF0
Bit 0 – ALTS Alternate Input Sample Mode Select bit
Value
Description
1
Uses channel input selects for Sample A on first sample and Sample B on next sample
0
Always uses channel input selects for Sample A
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1107
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.27 A/D Control Register 3
Name:
Offset:
AD1CON3
0x738
Notes:
1. Selecting the internal ADC RC clock requires that the ADCSx bits be ‘1’ or greater. Setting ADCSx = 0 when
ADRC = 1 will violate the TAD (min) specification.
2.
Bit
Access
Reset
Bit
The user should enable the charge pump if AVDD is < 2.7V. Longer sample times are required due to the
increase of the internal resistance of the MUX if the charge pump is disabled.
15
ADRC
R/W
0
14
EXTSAM
R/W
0
13
PUMPEN
R/W
0
12
11
9
8
R/W
0
10
SAMC[4:0]
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ADCS[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 15 – ADRC A/D Conversion Clock Source bit(1)
Value
Description
1
Dedicated ADC RC clock generator (4 MHz nominal)
0
Clock derived from system clock
Bit 14 – EXTSAM Extended Sampling Time bit
Value
Description
1
A/D is still sampling after SAMP = 0
0
A/D is finished sampling
Bit 13 – PUMPEN Charge Pump Enable bit(2)
Value
Description
1
Charge pump for switches is enabled
0
Charge pump for switches is disabled
Bits 12:8 – SAMC[4:0] Auto-Sample Time Select bits
Value
Description
11111
31 TAD
...
00001
1 TAD
00000
0 TAD
Bits 7:0 – ADCS[7:0] A/D Conversion Clock Select bits
Value
Description
11111111
256 * TPB = TAD
...
00000001
2 * TPB = TAD
00000000
TPB = TAD
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1108
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.28 A/D Sample Select Register
Name:
Offset:
AD1CHS
0x73A
Note:
1. These input channels do not have corresponding memory-mapped result buffers.
Bit
Access
Reset
Bit
Access
Reset
15
R/W
0
7
R/W
0
14
CH0NB[2:0]
R/W
0
6
CH0NA[2:0]
R/W
0
13
12
11
R/W
0
R/W
0
R/W
0
5
4
3
R/W
0
R/W
0
R/W
0
10
CH0SB[2:0]
R/W
0
2
CH0SA[4:0]
R/W
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bits 15:13 – CH0NB[2:0] Sample B Channel 0 Negative Input Select bits
Value
Description
7-3
Unimplemented
2
AN1
1
Unimplemented
0
AVSS
Bits 12:8 – CH0SB[2:0] Sample B Channel 0 Positive Input Select bits
Value
Description
31
Reserved
30
AVDD(1)
29
AVSS(1)
28
Band Gap Reference (1.2V)
27-24
Reserved
23
AN23
22
AN22
21
AN21
20
AN20
19
AN19
18
AN18
17
AN17
16
AN16
15
AN15
14
AN14
13
AN13
12
AN12
11
AN11
10
AN10
9
AN9
8
AN8
7
AN7
6
AN6
5
AN5
4
AN4
3
AN3
2
AN2
1
AN1
0
AN0
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1109
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
Bits 7:5 – CH0NA[2:0] Sample A Channel 0 Negative Input Select bits
Same definitions as for CHONB[2:0].
Bits 4:0 – CH0SA[4:0] Sample A Channel 0 Negative Input Select bits
Same definitions as for CHOSB[2:0].
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1110
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.29 A/D Input Scan Select Register High
Name:
Offset:
Bit
15
Access
Reset
Bit
7
AD1CSSH
0x73C
14
R/W
0
13
CSS[30:28]
R/W
0
12
R/W
0
6
5
4
11
10
9
8
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CSS[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 14:12 – CSS[30:28] A/D Input Scan Selection bits
Value
Description
1
Includes corresponding channel for input scan
0
Skips channel for input scan
Bits 7:0 – CSS[23:16] A/D Input Scan Selection bits
Value
Description
1
Includes corresponding channel for input scan
0
Skips channel for input scan
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1111
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.30 A/D Input Scan Select Register Low
Name:
Offset:
Bit
15
AD1CSSL
0x73E
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CSS[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CSS[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CSS[15:0] A/D Input Scan Selection bits
Value
Description
1
Includes corresponding channel for input scan
0
Skips channel for input scan
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1112
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.31 A/D Control Register 4
Name:
Offset:
AD1CON4
0x740
Note:
1. The DMABL[2:0] bits are only used when AD1CON1[11] = 1 and AD1CON1[12] = 0; otherwise, their value is
ignored.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DMABL[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
Bits 2:0 – DMABL[2:0] DMA Buffer Size Select bits(1)
Value
Description
111
Allocates 128 words of buffer to each analog input
110
Allocates 64 words of buffer to each analog input
101
Allocates 32 words of buffer to each analog input
100
Allocates 16 words of buffer to each analog input
011
Allocates 8 words of buffer to each analog input
010
Allocates 4 words of buffer to each analog input
001
Allocates 2 words of buffer to each analog input
000
Allocates 1 word of buffer to each analog input
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1113
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.32 A/D Control Register 5
Name:
Offset:
Bit
Access
Reset
Bit
AD1CON5
0x742
15
ASEN
R/W
0
14
LPEN
R/W
0
13
7
6
5
12
BGREQ
R/W
0
11
4
3
10
9
R/W
0
2
R/W
0
R/W
0
1
WM[1:0]
Access
Reset
8
ASINT[1:0]
0
CM[1:0]
R/W
0
R/W
0
R/W
0
Bit 15 – ASEN Auto-Scan Enable bit
Value
Description
1
Auto-scan is enabled
0
Auto-scan is disabled
Bit 14 – LPEN Low-Power Enable bit
Value
Description
1
Low power is enabled after scan
0
Full power is enabled after scan
Bit 12 – BGREQ Band Gap Request bit
Value
Description
1
Band gap is enabled when the A/D is enabled and active
0
Band gap is not enabled by the A/D
Bits 9:8 – ASINT[1:0] Auto-Scan (Threshold Detect) Interrupt Mode bits
Value
Description
11
Interrupt after Threshold Detect sequence has completed and valid compare has occurred
10
Interrupt after valid compare has occurred
01
Interrupt after Threshold Detect sequence has completed
00
No interrupt
Bits 3:2 – WM[1:0] Write Mode bits
Value
Description
11
Reserved
10
Auto-compare only (conversion results are not saved, but interrupts are generated when a valid match
occurs, as defined by the CMx and ASINTx bits)
01
Convert and save (conversion results are saved to locations as determined by the register bits when a
match occurs, as defined by the CMx bits)
00
Legacy operation (conversion data are saved to a location determined by the Buffer register bits)
Bits 1:0 – CM[1:0] Compare Mode bits
Value
Description
11
Outside Window mode: Valid match occurs if the conversion result is outside of the window defined by
the corresponding buffer pair
10
Inside Window mode: Valid match occurs if the conversion result is inside the window defined by the
corresponding buffer pair
01
Greater Than mode: Valid match occurs if the result is greater than the value in the corresponding
Buffer register
00
Less Than mode: Valid match occurs if the result is less than the value in the corresponding Buffer
register
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1114
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.33 A/D Scan Compare Hit Register High
Name:
Offset:
Bit
AD1CHITH
0x744
15
14
13
12
7
6
5
4
11
10
9
8
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
CHH[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – CHH[23:16] Compare Hit bits
If CM[1:0] = 11:
Value
Description
1
0
A/D Result Buffer n has been written with data or a match has occurred
A/D Result Buffer n has not been written with data
For All Other Values of CM[1:0]:
Value
Description
1
0
A match has occurred on A/D Result Channel n
No match has occurred on A/D Result Channel n
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1115
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.34 A/D Scan Compare Hit Register Low
Name:
Offset:
Bit
15
AD1CHITL
0x746
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CHH[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
Bit
CHH[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CHH[15:0] Compare Hit bits
If CM[1:0] = 11:
Value
Description
1
0
A/D Result Buffer n has been written with data or a match has occurred
A/D Result Buffer n has not been written with data
For All Other Values of CM[1:0]:
Value
Description
1
0
A match has occurred on A/D Result Channel n
No match has occurred on A/D Result Channel n
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1116
PIC24FJ512GU410 Family Data Sheet
12-Bit A/D Converter with Threshold Detect
22.4.35 A/D Conversion Result Register (for DMA PIA mode)
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
AD1DMBUF
0x74C
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
AD1DMBUF[15:8]
R/W
R/W
0
0
4
3
AD1DMBUF[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – AD1DMBUF[15:0] ADC Conversion Result bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1117
PIC24FJ512GU410 Family Data Sheet
10-Bit Digital-to-Analog Converter (DAC)
23.
10-Bit Digital-to-Analog Converter (DAC)
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information, refer to “10-Bit Digital-to-Analog Converter (DAC)”
(DS39615) in the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip website
(www.microchip.com). The information in this data sheet supersedes the information in the FRM.
PIC24FJ512GU410 family devices include 10-bit Digital-to-Analog Converters (DACs) for generating analog outputs
from digital data. A simplified block diagram for the DAC is shown in Figure 23-1.
Figure 23-1. DAC Simplified Block Diagram
DACSIDL
Idle Mode
DACSLP
Sleep Mode
DACEN
DVREF+
AVDD
DACREF[1:0]
DACOE
DAC1CON
10
DAC1DAT
10-Bit
Resistor
Ladder
Unity Gain
Buffer
DAC1 Output
Pin
Trigger and
Trigger Sources
Interrupt Logic
DACTRIG
DACTSEL[4:0]
DAC1IF
AVSS
The DAC includes these features:
•
•
•
•
•
•
•
Precision 10-Bit Resistor Ladder for High Accuracy
Fast Settling Time, Supporting 1 Msps Effective Sampling Rates
Buffered Output Voltage
Three User-Selectable Voltage Reference Options
Multiple Conversion Trigger Options, Plus a
Manual Convert-on-Write Option
Left and Right Justified Input Data Options
User-Selectable Sleep and Idle mode Operation
When using the DAC, it is required to set the ANSx and TRISx bits for the DACx output pin to configure it as an
analog output. See 11.2 Configuring Analog Port Pins for more information.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1118
PIC24FJ512GU410 Family Data Sheet
10-Bit Digital-to-Analog Converter (DAC)
The DAC generates an analog output voltage based on the digital input code, according to the formula:
where VDAC is the analog output voltage and VDACREF is the reference voltage selected by the DACREF[1:0] bits.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1119
PIC24FJ512GU410 Family Data Sheet
10-Bit Digital-to-Analog Converter (DAC)
23.1
DAC Registers
Offset
Name
0x00
...
0x02F7
Reserved
0x02F8
DAC1CON
0x02FA
DAC1DAT
Bit Pos.
7
7:0
15:8
7:0
15:8
DACOE
DACEN
© 2019-2020 Microchip Technology Inc.
6
5
DACSIDL
4
3
DACTSEL[4:0]
DACSLP
DACFM
DACDAT[7:0]
DACDAT[15:8]
Datasheet
2
1
0
DACREF[1:0]
DACTRIG
DS30010203C-page 1120
PIC24FJ512GU410 Family Data Sheet
10-Bit Digital-to-Analog Converter (DAC)
23.1.1
DAC Control Register
Name:
Offset:
DAC1CON
0x2F8
Note:
1. The internal band gap reference is automatically enabled whenever the DAC is enabled.
Bit
Access
Reset
Bit
Access
Reset
15
DACEN
R/W
0
14
13
DACSIDL
R/W
0
12
DACSLP
R/W
0
11
DACFM
R/W
0
10
9
7
DACOE
R/W
0
6
5
3
2
1
R/W
0
R/W
0
4
DACTSEL[4:0]
R/W
0
R/W
0
R/W
0
8
DACTRIG
R/W
0
0
DACREF[1:0]
R/W
R/W
0
0
Bit 15 – DACEN DAC Enable bit(1)
Value
Description
1
Module is enabled
0
Module is disabled
Bit 13 – DACSIDL DAC Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bit 12 – DACSLP DAC Enable During Sleep bit
Value
Description
1
DAC continues to output the most recent value of DAC1DAT during Sleep mode
0
DAC is powered down in Sleep mode; DAC output pin is controlled by the TRIS and LAT bits
Bit 11 – DACFM DAC Data Format Select bit
Value
Description
1
Data are left justified (data stored in DAC1DAT[15:6])
0
Data are right justified (data stored in DAC1DAT[9:0])
Bit 8 – DACTRIG DAC Trigger Input Enable bit
Value
Description
1
Analog output value updates when the event selected by DACTSEL[4:0] occurs
0
Analog output value updates as soon as DAC1DAT is written (DAC trigger is ignored)
Bit 7 – DACOE DAC Output Enable bit
Value
Description
1
Analog output voltage is driven to the DACOUT pin
0
Analog output voltage is not available at the pin (voltage at pin floats)
Bits 6:2 – DACTSEL[4:0] DAC Trigger Source Selection bits
Value
Description
31-19
Reserved
...
18
External Interrupt 1 (INT1)
17
MCCP8
16
MCCP7
15
MCCP6
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1121
PIC24FJ512GU410 Family Data Sheet
10-Bit Digital-to-Analog Converter (DAC)
Value
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Description
MCCP5
MCCP4
MCCP3
MCCP2
MCCP1
Reserved
Timer5
Timer4
Timer3
Timer2
Timer1
ADC conversion done
Comparator 3
Comparator 2
Comparator 1
Bits 1:0 – DACREF[1:0] DAC Reference Source Select bits
Value
Description
11
Reserved
10
AVDD
01
DVREF+
00
Reference is not connected (lowest power but no DAC functionality)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1122
PIC24FJ512GU410 Family Data Sheet
10-Bit Digital-to-Analog Converter (DAC)
23.1.2
DAC Data Register
Name:
Offset:
Bit
Access
Reset
Bit
Access
Reset
DAC1DAT
0x2FA
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
DACDAT[15:8]
R/W
R/W
0
0
4
3
DACDAT[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – DACDAT[15:0] DAC Data bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1123
PIC24FJ512GU410 Family Data Sheet
Triple Comparator Module
24.
Triple Comparator Module
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information, refer to “Scalable Comparator Module”
(www.microchip.com/DS39734) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet
supersedes the information in the FRM.
The triple comparator module provides three dual input comparators. A simplified block diagram of the module in
shown in Figure 24-1.
The comparator has the following features:
•
•
•
•
•
•
Differential, Rail-to-Rail Inputs
Power-Down mode for Power Savings
Integrated Results Register
Software-Selectable Comparator Output Polarity
Software-Selectable Edge for Trigger/Interrupt Generation
Software-Selectable Comparator Power mode
Figure 24-1. Triple Comparator Module Block Diagram
Note:
1. Refer to the CVRCON register (25.1.1 CVRCON) for bit details.
The inputs to the comparator can be configured to use any one of five external analog inputs (CxINA, CxINB, CxINC,
CxIND and CVREF+) and a voltage reference input from one of the internal band gap references or the comparator
voltage reference generator (VBG and CVREF).
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1124
PIC24FJ512GU410 Family Data Sheet
Triple Comparator Module
The comparator outputs may be directly connected to the CxOUT pins. When the respective COE bit equals ‘1’, the
I/O pad logic makes the unsynchronized output of the comparator available on the pin.
Each comparator has its own control register, CMxCON, for enabling and configuring its operation. The output and
event status of all three comparators is provided in the CMSTAT register.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1125
PIC24FJ512GU410 Family Data Sheet
Triple Comparator Module
24.1
Triple Comparator Module Registers
Offset
Name
0x00
...
0x02E5
Reserved
0x02E6
CMSTAT
0x02E8
...
0x02E9
Reserved
0x02EA
CM1CON
0x02EC
CM2CON
0x02EE
CM3CON
Bit Pos.
7
7:0
15:8
CMIDL
7:0
15:8
7:0
15:8
7:0
15:8
6
EVPOL[1:0]
CON
COE
EVPOL[1:0]
CON
COE
EVPOL[1:0]
CON
COE
© 2019-2020 Microchip Technology Inc.
5
4
CREF
CPOL
CREF
CPOL
CREF
CPOL
Datasheet
3
2
1
0
C3OUT
C3EVT
C2OUT
C2EVT
C1OUT
C1EVT
CCH[1:0]
CEVT
COUT
CCH[1:0]
CEVT
COUT
CCH[1:0]
CEVT
COUT
DS30010203C-page 1126
PIC24FJ512GU410 Family Data Sheet
Triple Comparator Module
24.1.1
Comparator Module Status Register
Name:
Offset:
CMSTAT
0x2E6
Legend: HSC = Hardware Settable/Clearable bit
Bit
Access
Reset
Bit
15
CMIDL
R/W
0
14
13
12
11
10
C3EVT
R/W
0
9
C2EVT
R/W
0
8
C1EVT
R/W
0
7
6
5
4
3
2
C3OUT
HSC/R
0
1
C2OUT
R/W
0
0
C1OUT
R/W
0
Access
Reset
Bit 15 – CMIDL Comparator Stop in Idle Mode bit
Value
Description
1
Discontinues operation of all comparators when device enters Idle mode
0
Continues operation of all enabled comparators in Idle mode
Bit 10 – C3EVT Comparator 3 Event Status bit (read-only)
Shows the current event status of Comparator 3 (CM3CON[9]).
Bit 9 – C2EVT Comparator 2 Event Status bit (read-only)
Shows the current event status of Comparator 2 (CM2CON[9]).
Bit 8 – C1EVT Comparator 1 Event Status bit (read-only)
Shows the current event status of Comparator 1 (CM1CON[9]).
Bit 2 – C3OUT Comparator 3 Output Status bit (read-only)
Shows the current output of Comparator 3 (CM3CON[8]).
Bit 1 – C2OUT Comparator 2 Output Status bit (read-only)
Shows the current output of Comparator 2 (CM2CON[8]).
Bit 0 – C1OUT Comparator 1 Output Status bit (read-only)
Shows the current output of Comparator 1 (CM1CON[8]).
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1127
PIC24FJ512GU410 Family Data Sheet
Triple Comparator Module
24.1.2
Comparator 1 Control Register
Name:
Offset:
CM1CON
0x2EA
Legend: HSC = Hardware Settable/Clearable bit
Bit
Access
Reset
15
CON
R/W
0
14
COE
R/W
0
13
CPOL
R/W
0
12
11
10
9
CEVT
R/W
0
7
6
5
4
CREF
R/W
0
3
2
1
Bit
EVPOL[1:0]
Access
Reset
R/W
0
R/W
0
8
COUT
HSC/R
0
0
CCH[1:0]
R/W
0
R/W
0
Bit 15 – CON Comparator Enable bit
Value
Description
1
Comparator is enabled
0
Comparator is disabled
Bit 14 – COE Comparator Output Enable bit
Value
Description
1
Comparator output is present on the C1OUT pin
0
Comparator output is internal only
Bit 13 – CPOL Comparator Output Polarity Select bit
Value
Description
1
Comparator output is inverted
0
Comparator output is not inverted
Bit 9 – CEVT Comparator Event bit
Value
Description
1
Comparator event that is defined by EVPOL[1:0] has occurred; subsequent triggers and interrupts are
disabled until the bit is cleared
0
Comparator event has not occurred
Bit 8 – COUT Comparator Output bit
When CPOL = 1:
Value
Description
1
0
VIN+ < VINVIN+ > VIN-
When CPOL = 0:
Value
Description
1
0
VIN+ > VINVIN+ < VIN-
Bits 7:6 – EVPOL[1:0] Trigger/Event/Interrupt Polarity Select bits
Value
Description
11
Trigger/event/interrupt is generated on any change of the comparator output
(while CEVT = 0)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1128
PIC24FJ512GU410 Family Data Sheet
Triple Comparator Module
Value
10
Description
Trigger/event/interrupt is generated on transition of the comparator output:
If CPOL = 1 (inverted polarity):
Low-to-high transition only.
If CPOL = 0 (noninverted polarity):
01
High-to-low transition only.
Trigger/event/interrupt is generated on transition of comparator output:
If CPOL = 1 (inverted polarity):
High-to-low transition only.
If CPOL = 0 (noninverted polarity):
00
Low-to-high transition only.
Trigger/event/interrupt generation is disabled
Bit 4 – CREF DAC Reference Source Select bit
Value
Description
1
Noninverting input connects to the internal CVREF voltage
0
Noninverting input connects to the C1INA pin
Bits 1:0 – CCH[1:0] Comparator Channel Select bits
Value
Description
11
Inverting input of the comparator connects to the internal selectable reference voltage specified by the
CVREFM[1:0] bits in the CVRCON register
10
Inverting input of the comparator connects to the C1IND pin
01
Inverting input of the comparator connects to the C1INC pin
00
Inverting input of the comparator connects to the C1INB pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1129
PIC24FJ512GU410 Family Data Sheet
Triple Comparator Module
24.1.3
Comparator 2 Control Register
Name:
Offset:
CM2CON
0x2EC
Legend: HSC = Hardware Settable/Clearable bit
Bit
Access
Reset
15
CON
R/W
0
14
COE
R/W
0
13
CPOL
R/W
0
12
11
10
9
CEVT
R/W
0
7
6
5
4
CREF
R/W
0
3
2
1
Bit
EVPOL[1:0]
Access
Reset
R/W
0
R/W
0
8
COUT
HSC/R
0
0
CCH[1:0]
R/W
0
R/W
0
Bit 15 – CON Comparator Enable bit
Value
Description
1
Comparator is enabled
0
Comparator is disabled
Bit 14 – COE Comparator Output Enable bit
Value
Description
1
Comparator output is present on the C2OUT pin
0
Comparator output is internal only
Bit 13 – CPOL Comparator Output Polarity Select bit
Value
Description
1
Comparator output is inverted
0
Comparator output is not inverted
Bit 9 – CEVT Comparator Event bit
Value
Description
1
Comparator event that is defined by EVPOL[1:0] has occurred; subsequent triggers and interrupts are
disabled until the bit is cleared
0
Comparator event has not occurred
Bit 8 – COUT Comparator Output bit
When CPOL = 1:
Value
Description
1
0
VIN+ < VINVIN+ > VIN-
When CPOL = 0:
Value
Description
1
0
VIN+ > VINVIN+ < VIN-
Bits 7:6 – EVPOL[1:0] Trigger/Event/Interrupt Polarity Select bits
Value
Description
11
Trigger/event/interrupt is generated on any change of the comparator output
(while CEVT = 0)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1130
PIC24FJ512GU410 Family Data Sheet
Triple Comparator Module
Value
10
Description
Trigger/event/interrupt is generated on transition of the comparator output:
If CPOL = 1 (inverted polarity):
Low-to-high transition only.
If CPOL = 0 (noninverted polarity):
01
High-to-low transition only.
Trigger/event/interrupt is generated on transition of comparator output:
If CPOL = 1 (inverted polarity):
High-to-low transition only.
If CPOL = 0 (noninverted polarity):
00
Low-to-high transition only.
Trigger/event/interrupt generation is disabled
Bit 4 – CREF DAC Reference Source Select bit
Value
Description
1
Noninverting input connects to the internal CVREF voltage
0
Noninverting input connects to the C2INA pin
Bits 1:0 – CCH[1:0] Comparator Channel Select bits
Value
Description
11
Inverting input of the comparator connects to the internal selectable reference voltage specified by the
CVREFM[1:0] bits in the CVRCON register
10
Inverting input of the comparator connects to the C2IND pin
01
Inverting input of the comparator connects to the C2INC pin
00
Inverting input of the comparator connects to the C2INB pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1131
PIC24FJ512GU410 Family Data Sheet
Triple Comparator Module
24.1.4
Comparator 3 Control Register
Name:
Offset:
CM3CON
0x2EE
Legend: HSC = Hardware Settable/Clearable bit
Bit
Access
Reset
15
CON
R/W
0
14
COE
R/W
0
13
CPOL
R/W
0
12
11
10
9
CEVT
R/W
0
7
6
5
4
CREF
R/W
0
3
2
1
Bit
EVPOL[1:0]
Access
Reset
R/W
0
R/W
0
8
COUT
HSC/R
0
0
CCH[1:0]
R/W
0
R/W
0
Bit 15 – CON Comparator Enable bit
Value
Description
1
Comparator is enabled
0
Comparator is disabled
Bit 14 – COE Comparator Output Enable bit
Value
Description
1
Comparator output is present on the C3OUT pin
0
Comparator output is internal only
Bit 13 – CPOL Comparator Output Polarity Select bit
Value
Description
1
Comparator output is inverted
0
Comparator output is not inverted
Bit 9 – CEVT Comparator Event bit
Value
Description
1
Comparator event that is defined by EVPOL[1:0] has occurred; subsequent triggers and interrupts are
disabled until the bit is cleared
0
Comparator event has not occurred
Bit 8 – COUT Comparator Output bit
When CPOL = 1:
Value
Description
1
0
VIN+ < VINVIN+ > VIN-
When CPOL = 0:
Value
Description
1
0
VIN+ > VINVIN+ < VIN-
Bits 7:6 – EVPOL[1:0] Trigger/Event/Interrupt Polarity Select bits
Value
Description
11
Trigger/event/interrupt is generated on any change of the comparator output
(while CEVT = 0)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1132
PIC24FJ512GU410 Family Data Sheet
Triple Comparator Module
Value
10
Description
Trigger/event/interrupt is generated on transition of the comparator output:
If CPOL = 1 (inverted polarity):
Low-to-high transition only.
If CPOL = 0 (noninverted polarity):
01
High-to-low transition only.
Trigger/event/interrupt is generated on transition of comparator output:
If CPOL = 1 (inverted polarity):
High-to-low transition only.
If CPOL = 0 (noninverted polarity):
00
Low-to-high transition only.
Trigger/event/interrupt generation is disabled
Bit 4 – CREF DAC Reference Source Select bit
Value
Description
1
Noninverting input connects to the internal CVREF voltage
0
Noninverting input connects to the C3INA pin
Bits 1:0 – CCH[1:0] Comparator Channel Select bits
Value
Description
11
Inverting input of the comparator connects to the internal selectable reference voltage specified by the
CVREFM[1:0] bits in the CVRCON register
10
Inverting input of the comparator connects to the C3IND pin
01
Inverting input of the comparator connects to the C3INC pin
00
Inverting input of the comparator connects to the C3INB pin
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1133
PIC24FJ512GU410 Family Data Sheet
Comparator Voltage Reference
25.
Comparator Voltage Reference
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information, refer to “Dual Comparator Module” (www.microchip.com/
DS39710) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet supersedes the
information in the FRM.
The comparator voltage reference diagram is shown in Figure 25-1.
Figure 25-1. Comparator Voltage Reference Block Diagram
The voltage reference module is controlled through the CVRCON register. The comparator voltage reference
provides two ranges of output voltage, each with 16 distinct levels. The primary difference between the ranges is the
size of the steps selected by the CVREF Value Selection bits (CVR[4:0]), with one range offering finer resolution.
The comparator reference supply voltage can come from either AVDD and AVSS, or the external CVREF+ and CVREFpins. The voltage source is selected by the CVRSS bit (CVRCON[5]).
The settling time of the comparator voltage reference must be considered when changing the CVREF output.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1134
PIC24FJ512GU410 Family Data Sheet
Comparator Voltage Reference
25.1
Comparator Voltage Reference Register
Offset
Name
0x00
...
0x02E7
Reserved
0x02E8
CVRCON
Bit Pos.
7
6
5
7:0
15:8
CVREN
CVROE
CVRSS
© 2019-2020 Microchip Technology Inc.
4
3
2
CVR[4:0]
CVREFP
Datasheet
1
0
CVREFM[1:0]
DS30010203C-page 1135
PIC24FJ512GU410 Family Data Sheet
Comparator Voltage Reference
25.1.1
Comparator Voltage Reference Control Register
Name:
Offset:
Bit
CVRCON
0x2E8
15
14
13
12
11
10
CVREFP
R/W
0
7
CVREN
R/W
0
6
CVROE
R/W
0
5
CVRSS
R/W
0
4
3
R/W
0
R/W
0
2
CVR[4:0]
R/W
0
Access
Reset
Bit
Access
Reset
9
8
CVREFM[1:0]
R/W
R/W
0
0
1
0
R/W
0
R/W
0
Bit 10 – CVREFP Comparator Voltage Reference Select bit (valid only when CREF is ‘1’)
Value
Description
1
CVREF+ is used as a reference voltage to the comparators
0
The CVR[4:0] bits (5-bit DAC) within this module provide the reference voltage to the comparators
Bits 9:8 – CVREFM[1:0] Comparator Band Gap Reference Source Select bits(valid only when CCH[1:0] = 11)
Value
Description
11
CVREF+ is provided as an input to the comparators
10
Reserved
01
Reserved
00
Band gap voltage is provided as an input to the comparators
Bit 7 – CVREN Comparator Voltage Reference Enable bit
Value
Description
1
CVREF circuit is powered on
0
CVREF circuit is powered down
Bit 6 – CVROE Comparator VREF Output Enable bit
Value
Description
1
CVREF voltage level is output on the CVREF pin
0
CVREF voltage level is disconnected from the CVREF pin
Bit 5 – CVRSS Comparator VREF Source Selection bit
Value
Description
1
Comparator reference source, CVRSRC = CVREF+ – CVREF0
Comparator reference source, CVRSRC = AVDD – AVSS
Bits 4:0 – CVR[4:0] Comparator VREF Value Selection bits (0 ≤ CVR[4:0] ≤ 31)
When CVRSS = 1:
CVREF = (CVREF-) + (CVR[4:0]/32) × (CVREF+ – CVREF-)
When CVRSS = 0:
CVREF = (AVSS) + (CVR[4:0]/32) × (AVDD – AVSS)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1136
PIC24FJ512GU410 Family Data Sheet
High/Low-Voltage Detect (HLVD)
High/Low-Voltage Detect (HLVD)
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information on the High/Low-Voltage Detect, refer to “High-Level
Integration with Programmable High/Low-Voltage Detect (HLVD)” (www.microchip.com/DS39725) in the
“dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet supersedes the information in the
FRM.
The High/Low-Voltage Detect (HLVD) module is a programmable circuit that allows the user to specify both the
device voltage trip point and the direction of change. The module block diagram is shown in Figure 26-1.
An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the
interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then
respond to the interrupt. The HLVDIF flag may be set during a POR or BOR event. The firmware should clear the flag
before the application uses it for the first time, even if the interrupt was disabled.
The HLVDCON register completely controls the operation of the HLVD module. This allows the circuitry to be “turned
off” by the user under software control, which minimizes the current consumption for the device. To enable the High/
Low-Voltage Detect, the HLVDEN (HLVDCON[15]) and CMPEN (HLVDCON[7]) bits must be set.
Figure 26-1. High/Low-Voltage Detect (HLVD) Module Block Diagram
VDD
Externally Generated
Trip Point
VDD
LVDIN
HLVDL[3:0]
CMPEN
16-to-1 MUX
26.
VDIR
Set
HLVDIF
Band Gap
1.2V Typical
HLVDEN
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1137
PIC24FJ512GU410 Family Data Sheet
High/Low-Voltage Detect (HLVD)
26.1
High/Low-Voltage Detect (HLVD) Register
Offset
Name
0x00
...
0x0113
Reserved
0x0114
HLVDCON
Bit Pos.
7
7:0
15:8
CMPEN
HLVDEN
© 2019-2020 Microchip Technology Inc.
6
5
4
LSIDL
3
VDIR
Datasheet
2
1
HLVDL[3:0]
BGVST
IRVST
0
HLVDEVT
DS30010203C-page 1138
PIC24FJ512GU410 Family Data Sheet
High/Low-Voltage Detect (HLVD)
26.1.1
High/Low-Voltage Detect Control Register
Name:
Offset:
HLVDCON
0x114
Notes:
1. For the actual trip point, see 32. Electrical Characteristics.
2. The HLVDIF flag cannot be cleared by software unless HLVDEVT = 0. The voltage must be monitored so that
the HLVD condition (as set by VDIR and HLVDL[3:0]) is not asserted.
Bit
Access
Reset
Bit
Access
Reset
15
HLVDEN
R/W
0
14
13
LSIDL
R/W
0
12
11
VDIR
R/W
0
10
BGVST
R/W
0
9
IRVST
R/W
0
8
HLVDEVT
R/W
0
7
CMPEN
R/W
0
6
5
4
3
2
1
0
R/W
0
R/W
0
HLVDL[3:0]
R/W
0
R/W
0
Bit 15 – HLVDEN High/Low-Voltage Detect Power Enable bit
Value
Description
1
HLVD is enabled
0
HLVD is disabled
Bit 13 – LSIDL HLVD Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when device enters Idle mode
0
Continues module operation in Idle mode
Bit 11 – VDIR Voltage Change Direction Select bit
Value
Description
1
Event occurs when voltage equals or exceeds the trip point (HLVDL[3:0])
0
Event occurs when voltage equals or falls below the trip point (HLVDL[3:0])
Bit 10 – BGVST Band Gap Voltage Stable Flag bit
Value
Description
1
Indicates that the band gap voltage is stable
0
Indicates that the band gap voltage is unstable
Bit 9 – IRVST Internal Reference Voltage Stable Flag bit
Value
Description
1
Internal reference voltage is stable; the High-Voltage Detect logic generates the interrupt flag at the
specified voltage range
0
Internal reference voltage is unstable; the High-Voltage Detect logic will not generate the interrupt flag
at the specified voltage range and the HLVD interrupt should not be enabled
Bit 8 – HLVDEVT High or Low-Voltage Event Status bit(2)
Value
Description
1
HLVD event is true during current instruction cycle
0
HLVD event is not true during current instruction cycle
Bit 7 – CMPEN High/Low-Voltage Detect Comparator Enable bit
Value
Description
1
HLVD comparator is enabled
0
HLVD comparator is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1139
PIC24FJ512GU410 Family Data Sheet
High/Low-Voltage Detect (HLVD)
Bits 3:0 – HLVDL[3:0] High/Low-Voltage Detection Limit bits(1)
Value
Description
15
Voltage on external LVDIN pin is compared with band gap (1.2V)
14
2.1V
13
2.2V
12
2.3V
11
2.4V
10
2.5V
9
2.6V
8
2.8V
7
2.9V
6
3.1V
5
3.4V
4-0
Reserved
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1140
PIC24FJ512GU410 Family Data Sheet
Deadman Timer (DMT)
27.
Deadman Timer (DMT)
Note: This data sheet summarizes the features of the PIC24FJ512GU410 family of devices. It is not intended to be
a comprehensive reference source. To complement the information in this data sheet, refer to “Deadman Timer
(DMT)” (DS70005155) in the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
website (www.microchip.com). The information in this data sheet supersedes the information in the FRM.
The primary function of the Deadman Timer (DMT) is to interrupt the processor in the event of a software malfunction.
The DMT, which works on the system clock, is a free-running instruction fetch timer, which is clocked whenever an
instruction fetch occurs, until a count match occurs. Instructions are not fetched when the processor is in Sleep
mode.
DMT can be enabled in the Configuration fuse or by software in the DMTCON register by setting the ON bit. The
DMT consists of a 32-bit counter with a time-out count match value, as specified by the two 16-bit Configuration Fuse
registers: FDMTCNTL and FDMTCNTH.
A DMT is typically used in mission-critical and safety-critical applications, where any single failure of software
functionality and sequencing must be detected.
Figure 27-1 shows a block diagram of the Deadman Timer module.
Figure 27-1. Deadman Timer Block Diagram
Notes:
1. DMT Max Count is controlled by the initial value of the FDMTCNTL and FDMTCNTH Configuration registers.
2. DMT window interval is controlled by the value of the FDMTIVTL and FDMTIVTH Configuration registers.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1141
PIC24FJ512GU410 Family Data Sheet
Deadman Timer (DMT)
27.1
Deadman Timer (DMT) Registers
Offset
Name
0x00
...
0x5B
Reserved
0x5C
DMTCON
0x5E
...
0x5F
Reserved
0x60
DMTPRECLR
0x62
...
0x63
Reserved
0x64
DMTCLR
0x66
...
0x67
Reserved
0x68
DMTSTAT
0x6A
...
0x6B
Reserved
0x6C
DMTCNTL
0x6E
DMTCNTH
0x70
DMTHOLDREG(1)
0x72
...
0x73
Reserved
0x74
DMTPSCNTL
0x76
DMTPSCNTH
0x78
DMTPSINTVL
0x7A
DMTPSINTVH
Bit Pos.
7
7:0
15:8
ON
6
5
4
7:0
15:8
2
1
0
STEP1[7:0]
7:0
15:8
7:0
15:8
3
STEP2[7:0]
BAD1
BAD2
DMTEVENT
WINOPN
7:0
15:8
7:0
15:8
7:0
15:8
COUNTER[7:0]
COUNTER[15:8]
COUNTER[23:16]
COUNTER[31:24]
UPRCNT[7:0]
UPRCNT[15:8]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
PSCNT[7:0]
PSCNT[15:8]
PSCNT[23:16]
PSCNT[31:24]
PSINTV[7:0]
PSINTV[15:8]
PSINTV[23:16]
PSINTV[31:24]
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1142
PIC24FJ512GU410 Family Data Sheet
Deadman Timer (DMT)
27.1.1
Deadman Timer Control Register
Name:
Offset:
DMTCON
0x5C
Note:
1. This bit has control only when DMTDIS = 0 in the FDMT Configuration Word.
Bit
Access
Reset
Bit
15
ON
R/W
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit 15 – ON DMT Module Enable bit(1)
Value
Description
1
Deadman Timer module is enabled
0
Deadman Timer module is not enabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1143
PIC24FJ512GU410 Family Data Sheet
Deadman Timer (DMT)
27.1.2
Deadman Timer Preclear Register
Name:
Offset:
Bit
15
DMTPRECLR
0x60
14
13
12
11
10
9
8
STEP1[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
Access
Reset
Bits 15:8 – STEP1[7:0] DMT Preclear Enable bits
These bits must be set to 40h to enable the Deadman Timer prescaler. All other values (improper sequence)
generate the DMT event and set the BAD1 flag. These bits are cleared when a DMT Reset event occurs. STEP1[7:0]
bits are also cleared if the STEP2[7:0] bits are loaded with the correct value in the correct sequence.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1144
PIC24FJ512GU410 Family Data Sheet
Deadman Timer (DMT)
27.1.3
Deadman Timer Clear Register
Bit
Name:
Offset:
DMTCLR
0x64
15
14
13
12
7
6
5
4
11
10
9
8
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
STEP2[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – STEP2[7:0] DMT Clear Enable bits
If the correct (40h) value was loaded in the STEP1[7:0] bits, the 04h value written into the STEP2[7:0] bits resets the
Deadman Timer and clears the STEP1[7:0] bits. All other values (improper sequence) generate the DMT event and
set the BAD2 flag.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1145
PIC24FJ512GU410 Family Data Sheet
Deadman Timer (DMT)
27.1.4
Deadman Timer Status Register
Name:
Offset:
DMTSTAT
0x68
Legend: HC = Hardware Clearable bit
Bit
15
14
13
12
11
10
9
8
7
BAD1
HC/R
0
6
BAD2
HC/R
0
5
DMTEVENT
HC/R
0
4
3
2
1
0
WINOPN
R
0
Access
Reset
Bit
Access
Reset
Bit 7 – BAD1 Deadman Timer Bad STEP1[7:0] Value Detect bit
Value
Description
1
Incorrect STEP1[7:0] value was detected
0
Incorrect STEP1[7:0] value was not detected
Bit 6 – BAD2 Deadman Timer Bad STEP2[7:0] Value Detect bit
Value
Description
1
Incorrect STEP2[7:0] value was detected
0
Incorrect STEP2[7:0] value was not detected
Bit 5 – DMTEVENT Deadman Timer Event bit
Value
Description
1
Deadman Timer event was detected (counter expired or improper Reset sequence)
0
Deadman Timer event was not detected
Bit 0 – WINOPN Deadman Timer Clear Window bit
Value
Description
1
Deadman Timer clear window is open
0
Deadman Timer clear window is not open
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1146
PIC24FJ512GU410 Family Data Sheet
Deadman Timer (DMT)
27.1.5
Deadman Timer Count Register Low
Name:
Offset:
DMTCNTL
0x6C
Bit
15
14
13
Access
Reset
R
0
R
0
R
0
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
12
11
COUNTER[15:8]
R
R
0
0
10
9
8
R
0
R
0
R
0
4
3
COUNTER[7:0]
R
R
0
0
2
1
0
R
0
R
0
R
0
Bits 15:0 – COUNTER[15:0] Read Current Contents of Lower DMT Counter bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1147
PIC24FJ512GU410 Family Data Sheet
Deadman Timer (DMT)
27.1.6
Deadman Timer Count Register High
Name:
Offset:
DMTCNTH
0x6E
Bit
15
14
13
Access
Reset
R
0
R
0
R
0
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
12
11
COUNTER[31:24]
R
R
0
0
10
9
8
R
0
R
0
R
0
4
3
COUNTER[23:16]
R
R
0
0
2
1
0
R
0
R
0
R
0
Bits 15:8 – COUNTER[31:24] Read Current Contents of Higher DMT Counter bits
Bits 7:0 – COUNTER[23:16] Read Current Contents of Higher DMT Counter bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1148
PIC24FJ512GU410 Family Data Sheet
Deadman Timer (DMT)
27.1.7
DMT Post-Configure Count Status Register Low
Name:
Offset:
DMTPSCNTL
0x74
Legend: y = Value from Configuration bit on POR
Bit
15
14
13
Access
Reset
R-y
R-y
R-y
7
6
5
Bit
12
11
PSCNT[15:8]
R-y
R-y
4
10
9
8
R-y
R-y
R-y
3
2
1
0
R-y
R-y
R-y
R-y
PSCNT[7:0]
Access
Reset
R-y
R-y
R-y
R-y
Bits 15:0 – PSCNT[15:0] Lower DMT Instruction Count Value Configuration Status bits
This is always the value of the FDMTCNTL Configuration register.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1149
PIC24FJ512GU410 Family Data Sheet
Deadman Timer (DMT)
27.1.8
DMT Post-Configure Count Status Register High
Name:
Offset:
DMTPSCNTH
0x76
Legend: y = Value from Configuration bit on POR
Bit
15
14
13
Access
Reset
R-y
R-y
R-y
7
6
5
R-y
R-y
R-y
Bit
Access
Reset
12
11
PSCNT[31:24]
R-y
R-y
4
3
PSCNT[23:16]
R-y
R-y
10
9
8
R-y
R-y
R-y
2
1
0
R-y
R-y
R-y
Bits 15:8 – PSCNT[31:24] Higher DMT Instruction Count Value Configuration Status bits
This is always the value of the FDMTCNTH Configuration register.
Bits 7:0 – PSCNT[23:16] Higher DMT Instruction Count Value Configuration Status bits
This is always the value of the FDMTCNTH Configuration register.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1150
PIC24FJ512GU410 Family Data Sheet
Deadman Timer (DMT)
27.1.9
DMT Post-Configure Interval Status Register Low
Name:
Offset:
DMTPSINTVL
0x78
Legend: y = Value from Configuration bit on POR
Bit
15
14
13
Access
Reset
R-y
R-y
R-y
7
6
5
Bit
12
11
PSINTV[15:8]
R-y
R-y
4
10
9
8
R-y
R-y
R-y
3
2
1
0
R-y
R-y
R-y
R-y
PSINTV[7:0]
Access
Reset
R-y
R-y
R-y
R-y
Bits 15:0 – PSINTV[15:0] Lower DMT Window Interval Configuration Status bits
This is always the value of the FDMTIVTL Configuration register.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1151
PIC24FJ512GU410 Family Data Sheet
Deadman Timer (DMT)
27.1.10 DMT Post-Configure Interval Status Register High
Name:
Offset:
DMTPSINTVH
0x7A
Legend: y = Value from Configuration bit on POR
Bit
15
14
13
Access
Reset
R-y
0
R-y
0
R-y
0
7
6
5
R-y
0
R-y
0
R-y
0
Bit
Access
Reset
12
11
PSINTV[31:24]
R-y
R-y
0
0
4
3
PSINTV[23:16]
R-y
R-y
0
0
10
9
8
R-y
0
R-y
0
R-y
0
2
1
0
R-y
0
R-y
0
R-y
0
Bits 15:8 – PSINTV[31:24] Higher DMT Window Interval Configuration Status bits
This is always the value of the FDMTIVTH Configuration register.
Bits 7:0 – PSINTV[23:16] Higher DMT Window Interval Configuration Status bits
This is always the value of the FDMTIVTH Configuration register.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1152
PIC24FJ512GU410 Family Data Sheet
Deadman Timer (DMT)
27.1.11 DMT Hold Register
Name:
Offset:
DMTHOLDREG(1)
0x70
Note:
1. The DMTHOLDREG register is initialized to ‘0’ on Reset, and is only loaded when the DMTCNTL and
DMTCNTH registers are read.
Bit
15
14
13
10
9
8
R
0
12
11
UPRCNT[15:8]
R
R
0
0
Access
Reset
R
0
R
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
UPRCNT[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – UPRCNT[15:0] DMTCNTH Register Value When DMTCNTL or DMTCNTH were Last Read bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1153
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.
USB with On-The-Go (USB OTG) Support
Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information, refer to “USB On-The-Go (OTG)” (DS39721) in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip website (www.microchip.com). The
information in this data sheet supersedes the information in the FRM.
PIC24FJ512GU410 family devices contain a full-speed and low-speed compatible, On-The-Go (OTG) USB Serial
Interface Engine (SIE). The OTG capability allows the device to act as either a USB peripheral device or as a USB
embedded host with limited host capabilities. The OTG capability allows the device to dynamically switch from device
to host operation using OTG’s Host Negotiation Protocol (HNP).
For more details on OTG operation, refer to the “On-The-Go Supplement” to the “USB 2.0 Specification” published by
the USB-IF. For more details on USB operation, refer to the “Universal Serial Bus Specification, v2.0”.
The USB OTG module offers these features:
•
•
•
•
•
•
•
•
•
USB Functionality in Device and Host modes, and OTG Capabilities for Application-Controlled mode Switching
Software-Selectable module Speeds of Full Speed (12 Mbps) or Low Speed (1.5 Mbps available in Host mode
only)
Support for All Four USB Transfer Types: Control, Interrupt, Bulk and Isochronous
16 Bidirectional Endpoints for a Total of 32 Unique Endpoints
DMA Interface for Data RAM Access
Queues Up to 16 Unique Endpoint Transfers without Servicing
Integrated, On-Chip USB Transceiver with Support for Off-Chip Transceivers via a Digital Interface
Integrated VBUS Generation with On-Chip Comparators and Boost Generation, and Support of External VBUS
Comparators and Regulators through a Digital Interface
Configurations for On-Chip Bus Pull-up and Pull-Down Resistors
A simplified block diagram of the USB OTG module is shown in Figure 28-1.
The USB OTG module can function as a USB peripheral device or as a USB host, and may dynamically switch
between Device and Host modes under software control. In either mode, the same data paths and Buffer Descriptors
(BDs) are used for the transmission and reception of data.
In discussing USB operation, this section will use a controller-centric nomenclature for describing the direction of the
data transfer between the microcontroller and the USB. RX (Receive) will be used to describe transfers that move
data from the USB to the microcontroller and TX (Transmit) will be used to describe transfers that move data from the
microcontroller to the USB. Table 28-1 shows the relationship between data direction in this nomenclature and the
USB tokens exchanged.
Table 28-1. Controller-Centric Data Direction for USB Host or Target
Direction
USB Mode
RX
TX
Device
OUT or SETUP
IN
Host
IN
OUT or SETUP
This chapter presents the most basic operations needed to implement USB OTG functionality in an application. A
complete and detailed discussion of the USB protocol and its OTG supplement are beyond the scope of this data
sheet. It is assumed that the user already has a basic understanding of USB architecture and the latest version of the
protocol.
Not all steps for proper USB operation (such as device enumeration) are presented here. It is recommended that
application developers use an appropriate device driver to implement all of the necessary features. Microchip
provides a number of application-specific resources, such as USB firmware and driver support. Refer to
www.microchip.com/usb for the latest firmware and driver support.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1154
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
Figure 28-1. USB OTG Module Block Diagram
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1155
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
Notes:
1. Pins are multiplexed with digital I/Os and other device features.
2. Connecting VBUS3V3 to VDD is highly recommended, as floating this input can cause increased IPD currents.
The pin should be tied to VDD when the USB functions are not used.
28.1
Hardware Configuration
28.1.1
Device Mode
28.1.1.1 D+ Pull-up Resistor
PIC24FJ512GU410 family devices have a built-in 1.5 kΩ resistor on the D+ line that is available when the
microcontroller is operating in Device mode. This is used to signal an external host that the device is operating in
Full-Speed Device mode. It is engaged by setting the USBEN bit (U1CON[0]) and powering up the USB module
(USBPWR = 1). If the OTGEN bit (U1OTGCON[2]) is set, then the D+ pull-up is enabled through the DPPULUP bit
(U1OTGCON[7]).
28.1.1.2 The VBUS Pin
In order to meet the “USB 2.0 Specification” requirement, relating to the back drive voltage on the D+/D- pins, the
USB module incorporates VBUS-level sensing comparators. When the comparators detect the VBUS level below the
VA_SESS_VLD level, the hardware will automatically disable the D+ pull-up resistor described in 28.1.1.1 D+ Pull-up
Resistor. This allows the device to automatically meet the back drive requirement for D+ and D-, even if the
application firmware does not explicitly monitor the VBUS level. Therefore, the VBUS microcontroller pin should not be
left floating in USB Device mode application designs and should normally be connected to the VBUS pin on the USB
connector/cable (either directly or through a small resistance ≤ 100 ohms).
28.1.1.3 Power Modes
Many USB applications will likely have several different sets of power requirements and configuration. The most
common power modes encountered are:
•
•
•
•
Bus Power Only mode
Self-Power Only mode
Suspend mode
Dual Power with Self-Power Dominance mode
Bus Power Only mode (Figure 28-2) is effectively the simplest method. All power for the application is drawn from the
USB.
To meet the inrush current requirements of the “USB 2.0 Specification”, the total effective capacitance, appearing
across VBUS and ground, must be no more than 10 μF.
In the USB Suspend mode, devices must consume no more than 2.5 mA from the 5V VBUS line of the USB cable.
During the USB Suspend mode, the D+ or D- pull-up resistor must remain active, which will consume some of the
allowed suspend current.
In Self-Power Only mode (Figure 28-3), the USB application provides its own power, with very little power being
pulled from the USB. Note that an attach indication is added to indicate when the USB has been connected and the
host is actively powering VBUS.
To meet compliance specifications, the USB module (and the D+ or D- pull-up resistor) should not be enabled until
the host actively drives VBUS high. One of the 5.5V tolerant I/O pins may be used for this purpose.
The application should never source any current onto the 5V VBUS pin of the USB cable when the USB module is
operated in USB Device mode.
The Dual Power with Self-Power Dominance mode (Figure 28-4) allows the application to use internal power
primarily, but switch to power from the USB when no internal power is available. Dual power devices must also meet
all of the special requirements for inrush current and Suspend mode current previously described, and must not
enable the USB module until VBUS is driven high.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1156
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
Figure 28-2. Bus-Powered Interface Example
Figure 28-3. Self-Power Only
Figure 28-4. Dual Power Example
28.1.2
Host and OTG Modes
28.1.2.1 D+ and D- Pull-Down Resistors
PIC24FJ512GU410 family devices have built-in 15 kΩ pull-down resistors on the D+ and D- lines. These resistors are
used in tandem to signal to the bus that the microcontroller is operating in Host mode. They are engaged by setting
the HOSTEN bit (U1CON[3]). If the OTGEN bit (U1OTGCON[2]) is set, then these pull-downs are enabled by setting
the DPPULDWN and DMPULDWN bits (U1OTGCON[5:4]).
28.1.2.2 Power Configurations
In Host mode, as well as Host mode in On-The-Go operation, the “USB 2.0 Specification” requires that the host
application should supply power on VBUS. Since the microcontroller is running below VBUS, and is not able to source
sufficient current, a separate power supply must be provided.
When the application is always operating in Host mode, a simple circuit can be used to supply VBUS and regulate
current on the bus (Figure 28-5). For OTG operation, it is necessary to be able to turn VBUS on or off as needed, as
the microcontroller switches between Device and Host modes. A typical example using an external charge pump is
shown in Figure 28-6.
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
Figure 28-5. Host Interface Example
Figure 28-6. OTG Interface Example
28.1.3
Calculating Transceiver Power Requirements
The USB transceiver consumes a variable amount of current depending on the characteristic impedance of the USB
cable, the length of the cable, the VUSB supply voltage and the actual data patterns moving across the USB cable.
Longer cables have larger capacitances and consume more total energy when switching output states. The total
transceiver current consumption will be application-specific. Equation 28-1 can help estimate how much current
actually may be required in full-speed applications.
Refer to “USB On-The-Go (OTG)” (www.microchip.com/DS39721) in the “dsPIC33/PIC24 Family Reference
Manual” for a complete discussion on transceiver power consumption.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1158
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
Equation 28-1. Estimating USB Transceiver Current Consumption
28.2
USB Buffer Descriptors and the BDT
Endpoint buffer control is handled through a structure called the Buffer Descriptor Table (BDT). This provides a
flexible method for users to construct and control endpoint buffers of various lengths and configurations.
The BDT can be located in any available 512-byte, aligned block of data RAM. The BDT Pointer (U1BDTP1) contains
the upper address byte of the BDT and sets the location of the BDT in RAM. The user must set this pointer to indicate
the table’s location.
The BDT is composed of Buffer Descriptors (BDs), which are used to define and control the actual buffers in the USB
RAM space. Each BD consists of two 16-bit, “soft” (non-fixed address) registers, BDnSTAT and BDnADR, where n
represents one of the 64 possible BDs (range of 0 to 63). BDnSTAT is the status register for BDn, while BDnADR
specifies the starting address for the buffer associated with BDn.
Note: Since BDnADR is a 16-bit register, only the first 64 Kbytes of RAM can be accessed by the USB module.
Depending on the endpoint buffering configuration used, there are up to 64 sets of Buffer Descriptors, for a total of
256 bytes. At a minimum, the BDT must be at least eight bytes long. This is because the “USB 2.0 Specification”
mandates that every device must have Endpoint 0 with both input and output for initial setup.
Endpoint mapping in the BDT is dependent on three variables:
•
•
•
Endpoint number (0 to 15)
Endpoint direction (RX or TX)
Ping-pong settings (U1CNFG1[1:0])
Figure 28-7 illustrates how these variables are used to map endpoints in the BDT.
In Host mode, only Endpoint 0 Buffer Descriptors are used. All transfers utilize the Endpoint 0 Buffer Descriptor and
Endpoint Control register (U1EP0). For received packets, the attached device’s source endpoint is indicated by the
value of ENDPT[3:0] in the USB Status register (U1STAT[7:4]). For transmitted packets, the attached device’s
destination endpoint is indicated by the value written to the USB Token register (U1TOK).
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
Figure 28-7. BDT Mapping for Endpoint Buffering Modes
Note: Memory area is not shown to scale.
BDs have a fixed relationship to a particular endpoint, depending on the buffering configuration. Table 28-2 provides
the mapping of BDs to endpoints. This relationship also means that gaps may occur in the BDT if endpoints are not
enabled contiguously. This, theoretically, means that the BDs for disabled endpoints could be used as buffer space.
In practice, users should avoid using such spaces in the BDT unless a method of validating BD addresses is
implemented.
Table 28-2. Assignment of Buffer Descriptors for the Different Buffering Modes
BDs Assigned to Endpoint
Endpoint
Mode 1
(Ping-Pong on
EP0 RX)
Mode 0
(No Ping-Pong)
RX
TX
RX
TX
Mode 3
(Ping-Pong on All Other EPs,
Except EP0)
Mode 2
(Ping-Pong on All EPs)
RX
TX
RX
TX
0
0
1
0 (E), 1
(O)
2
0 (E), 1 (O)
2 (E), 3 (O)
0
1
1
2
3
3
4
4 (E), 5 (O)
6 (E), 7 (O)
2 (E), 3 (O)
4 (E), 5 (O)
2
4
5
5
6
8 (E), 9 (O)
10 (E), 11 (O) 6 (E), 7 (O)
8 (E), 9 (O)
3
6
7
7
8
12 (E), 13 (O) 14 (E), 15 (O) 10 (E), 11 (O)
12 (E), 13 (O)
4
8
9
9
10
16 (E), 17 (O) 18 (E), 19 (O) 14 (E), 15 (O)
16 (E), 17 (O)
5
10
11
11
12
20 (E), 21 (O) 22 (E), 23 (O) 18 (E), 19 (O)
20 (E), 21 (O)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1160
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
...........continued
BDs Assigned to Endpoint
Endpoint
Mode 0
(No Ping-Pong)
RX
Mode 1
(Ping-Pong on
EP0 RX)
TX
RX
TX
Mode 2
(Ping-Pong on All EPs)
RX
TX
Mode 3
(Ping-Pong on All Other EPs,
Except EP0)
RX
TX
6
12
13
13
14
24 (E), 25 (O) 26 (E), 27 (O) 22 (E), 23 (O)
24 (E), 25 (O)
7
14
15
15
16
28 (E), 29 (O) 30 (E), 31 (O) 26 (E), 27 (O)
28 (E), 29 (O)
8
16
17
17
18
32 (E), 33 (O) 34 (E), 35 (O) 30 (E), 31 (O)
32 (E), 33 (O)
9
18
19
19
20
36 (E), 37 (O) 38 (E), 39 (O) 34 (E), 35 (O)
36 (E), 37 (O)
10
20
21
21
22
40 (E), 41 (O) 42 (E), 43 (O) 38 (E), 39 (O)
40 (E), 41 (O)
11
22
23
23
24
44 (E), 45 (O) 46 (E), 47 (O) 42 (E), 43 (O)
44 (E), 45 (O)
12
24
25
25
26
48 (E), 49 (O) 50 (E), 51 (O) 46 (E), 47 (O)
48 (E), 49 (O)
13
26
27
27
28
52 (E), 53 (O) 54 (E), 55 (O) 50 (E), 51 (O)
52 (E), 53 (O)
14
28
29
29
30
56 (E), 57 (O) 58 (E), 59 (O) 54 (E), 55 (O)
56 (E), 57 (O)
15
30
31
31
32
60 (E), 61 (O) 62 (E), 63 (O) 58 (E), 59 (O)
60 (E), 61 (O)
Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer
28.2.1
Buffer Ownership
Because the buffers and their BDs are shared between the CPU and the USB module, a simple semaphore
mechanism is used to distinguish which is allowed to update the BD and associated buffers in memory. This is done
by using the UOWN bit as a semaphore to distinguish which is allowed to update the BD and associated buffers in
memory. UOWN is the only bit that is shared between the two configurations of BDnSTAT.
When UOWN is clear, the BD entry is “owned” by the microcontroller core. When the UOWN bit is set, the BD entry
and the buffer memory are “owned” by the USB peripheral. The core should not modify the BD or its corresponding
data buffer during this time. Note that the microcontroller core can still read BDnSTAT while the SIE owns the buffer
and vice versa.
The Buffer Descriptors have a different meaning based on the source of the register update. 28.3.1 BDnSTAT and
28.3.2 BDnSTAT show the differences in BDnSTAT depending on its current “ownership”.
When UOWN is set, the user can no longer depend on the values that were written to the BDs. From this point, the
USB module updates the BDs as necessary, overwriting the original BD values. The BDnSTAT register is updated by
the SIE with the token PID and the transfer count is updated.
28.2.2
DMA Interface
The USB OTG module uses a dedicated DMA to access both the BDT and the endpoint data buffers. Since part of
the address space of the DMA is dedicated to the Buffer Descriptors, a portion of the memory connected to the DMA
must comprise a contiguous address space, properly mapped for the access by the module.
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.3
USB On-The-Go Registers
Offset
Name
00
...
05FF
Reserved
0x0600
U1OTGIR(2)
0x0602
U1OTGIE
0x0604
U1OTGSTAT
0x0606
U1OTGCON
0x0608
U1PWRC
0x060A
U1IR(1)
0x060A
U1IR(1)
0x060C
U1IE
Bit Pos.
7
6
5
4
3
2
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
IDIF
T1MSECIF
LSTATEIF
ACTVIF
SESVDIF
SESENDIF
VBUSVDIF
IDIE
T1MSECIE
LSTATEIE
ACTVIE
SESVDIE
SESENDIE
VBUSVDIE
SESVD
SESEND
VBUSVD
Reserved
OTGEN
7:0
ID
DPPULUP
LSTATE
DMPULUP
DPPULDWN DMPULDWN
UACTPND
1
USLPGRD
STALLIF
0
Reserved
VBUSDIS
USUSPND
USBPWR
RESUMEIF
IDLEIF
TRNIF
SOFIF
UERRIF
URSTIF
STALLIF
ATTACHIF
RESUMEIF
IDLEIF
TRNIF
SOFIF
UERRIF
DETACHIF
STALLIE
ATTACHIE
RESUMEIE
IDLEIE
TRNIE
SOFIE
UERRIE
URSTIE or
DETACHIE
BTSEF
DMAEF
BTOEF
DFN8EF
CRC16EF
CRC5EF or
EOFEE
PIDEF
BTSEE
DMAEE
BTOEE
DFN8EE
CRC16EE
CRC5EE or
EOFEE
PIDEE
DIR
PPBI
HOSTEN
RESUME
PPBRST
USBEN
HOSTEN
RESUME
PPBRST
SOFEN
15:8
0x060E
U1EIR(1)
7:0
15:8
0x0610
U1EIE
0x0612
U1STAT
0x0614
U1CON
0x0614
U1CON
0x0616
U1ADDR
0x0618
U1BDTP1
0x061A
U1FRML
0x061C
U1FRMH
0x061E
U1TOK
0x0620
U1SOF
0x0622
U1BDTP2
0x0624
U1BDTP3
0x0626
U1CNFG1
0x0628
U1CNFG2
0x062A
U1EP0
0x062C
U1EP1
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
ENDPT[3:0]
JSTATE
SE0
PKTDIS
SE0
TOKBUSY
USBRST
LSPDEN
DEVADDR[6:0]
BDTPTRL[6:0]
FRM[7:0]
FRM[10:8]
PID[3:0]
EP[3:0]
CNT[7:0]
BDTPTRH[7:0]
BDTPTRU[7:0]
UTEYE
LSPD
© 2019-2020 Microchip Technology Inc.
UOEMON
RETRYDIS
USBSIDL
PPB[1:0]
PUVBUS
EXTI2CEN
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
Datasheet
DS30010203C-page 1162
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
...........continued
Offset
Name
Bit Pos.
0x062E
U1EP2
0x0630
U1EP3
0x0632
U1EP4
0x0634
U1EP5
0x0636
U1EP6
0x0638
U1EP7
0x063A
U1EP8
0x063C
U1EP9
0x063E
U1EP10
0x0640
U1EP11
0x0642
U1EP12
0x0644
U1EP13
0x0646
U1EP14
0x0648
U1EP15
7
4
3
2
1
0
7:0
15:8
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
© 2019-2020 Microchip Technology Inc.
6
5
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DS30010203C-page 1163
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.3.1
Buffer Descriptor n Status Register Prototype, USB Mode (BD0STAT through BD63STAT)
Name:
Offset:
BDnSTAT
User Defined
Legend: HSC = Hardware Settable/Clearable bit; x = Bit state is unknown
Bit
Access
Reset
Bit
Access
Reset
15
UOWN
HSC/R/W
x
14
DTS
HSC/R/W
x
13
HSC/R/W
x
7
6
5
HSC/R/W
x
HSC/R/W
x
HSC/R/W
x
12
11
PID[3:0]
HSC/R/W
HSC/R/W
x
x
4
3
BC[7:0]
HSC/R/W
HSC/R/W
x
x
10
HSC/R/W
x
9
8
BC[9:8]
HSC/R/W
HSC/R/W
x
x
2
1
0
HSC/R/W
x
HSC/R/W
x
HSC/R/W
x
Bit 15 – UOWN USB Own bit
Value
Description
1
The USB module owns the BD and its corresponding buffer; the CPU must not modify the BD or the
buffer
Bit 14 – DTS Data Toggle Packet bit
Value
Description
1
Data 1 packet
0
Data 0 packet
Bits 13:10 – PID[3:0] Packet Identifier bits (written by the USB module)
In Device mode:
Represents the PID of the received token during the last transfer.
In Host mode:
Represents the last returned PID or the transfer status indicator.
Bits 9:0 – BC[9:0] Byte Count bits
This represents the number of bytes to be transmitted or the maximum number of bytes to be received during a
transfer. Upon completion, the byte count is updated by the USB module with the actual number of bytes transmitted
or received.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1164
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.3.2
Buffer Descriptor n Status Register Prototype, CPU Mode (BD0STAT through BD63STAT)
Name:
Offset:
BDnSTAT
User Defined
Note:
1. This bit is ignored unless DTSEN = 1.
Legend: HSC = Hardware Settable/Clearable bit; x = Bit state is unknown
Bit
Access
Reset
Bit
Access
Reset
15
UOWN
HSC/R/W
x
14
DTS
HSC/R/W
x
13
12
7
6
5
4
HSC/R/W
x
HSC/R/W
x
HSC/R/W
x
11
DTSEN
HSC/R/W
x
3
BC[7:0]
HSC/R/W
HSC/R/W
x
x
10
BSTALL
HSC/R/W
x
9
8
BC[9:8]
HSC/R/W
HSC/R/W
x
x
2
1
0
HSC/R/W
x
HSC/R/W
x
HSC/R/W
x
Bit 15 – UOWN USB Own bit
Value
Description
1
The microcontroller core owns the BD and its corresponding buffer; the USB module ignores all other
fields in the BD
Bit 14 – DTS Data Toggle Packet bit(1)
Value
Description
1
Data 1 packet
0
Data 0 packet
Bit 11 – DTSEN Data Toggle Synchronization Enable bit
Value
Description
1
Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored
0
No data toggle synchronization is performed
Bit 10 – BSTALL Buffer Stall Enable bit
Value
Description
1
Buffer STALL is enabled; STALL handshake issued if a token is received that would use the BD in the
given location (UOWN bit remains set, BD value is unchanged), corresponding EPSTALL bit will get set
on any STALL handshake
0
Buffer STALL is disabled
Bits 9:0 – BC[9:0] Byte Count bits
This represents the number of bytes to be transmitted or the maximum number of bytes to be received during a
transfer. Upon completion, the byte count is updated by the USB module with the actual number of bytes transmitted
or received.
28.4
USB Interrupts
The USB OTG module has many conditions that can be configured to cause an interrupt. All interrupt sources use
the same interrupt vector.
Figure 28-8 shows the interrupt logic for the USB module. There are two layers of interrupt registers in the USB
module. The top level consists of overall USB status interrupts; these are enabled and flagged in the U1IE and U1IR
registers, respectively. The second level consists of USB error conditions, which are enabled and flagged in the
U1EIR and U1EIE registers. An interrupt condition in any of these triggers a USB Error Interrupt Flag (UERRIF) in the
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
top level. Unlike the device-level interrupt flags in the IFSx registers, USB interrupt flags in the U1IR registers can
only be cleared by writing a ‘1’ to the bit position.
Interrupts may be used to trap routine events in a USB transaction. Figure 28-8 provides some common events within
a USB frame and their corresponding interrupts.
Figure 28-8. USB OTG Interrupt Funnel
28.4.1
Clearing USB OTG Interrupts
Unlike device-level interrupts, the USB OTG interrupt status flags are not freely writable in software. All USB OTG
flag bits are implemented as hardware set only bits. Additionally, these bits can only be cleared in software by writing
a ‘1’ to their locations (i.e., performing a MOV type instruction). Writing a ‘0’ to a flag bit (i.e., a BCLR instruction) has
no effect.
Note: Throughout this data sheet, a bit that can only be cleared by writing a ‘1’ to its location is referred to as “Write
‘1’ to Clear”. In register descriptions; this function is indicated by the descriptor, “K”.
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
Figure 28-9. Example of a USB Transaction and Interrupt Events
Note:
1. The control transfer shown here is only an example showing events that can occur for every transaction.
Typical control transfers will spread across multiple frames.
28.5
Device Mode Operation
The following section describes how to perform a common Device mode task. In Device mode, USB transfers are
performed at the transfer level. The USB module automatically performs the status phase of the transfer.
28.5.1
Enabling Device Mode
1.
2.
3.
4.
5.
6.
7.
8.
9.
28.5.2
Reset the Ping-Pong Buffer Pointers by setting, then clearing, the Ping-Pong Buffer Reset bit, PPBRST
(U1CON[1]).
Disable all interrupts (U1IE and U1EIE = 00h).
Clear any existing interrupt flags by writing FFh to U1IR and U1EIR.
Verify that VBUS is present (non-OTG devices only).
Enable the USB module by setting the USBEN bit (U1CON[0]).
Set the OTGEN bit (U1OTGCON[2]) to enable OTG operation.
Enable the Endpoint 0 buffer to receive the first setup packet by setting the EPRXEN and EPHSHK bits for
Endpoint 0 (U1EP0[3,0] = 1).
Power up the USB module by setting the USBPWR bit (U1PWRC[0]).
Enable the D+ pull-up resistor to signal an attach by setting the DPPULUP bit (U1OTGCON[7]).
Receiving an IN Token in Device Mode
1.
2.
3.
Attach to a USB host and enumerate as described in Chapter 9 of the “USB 2.0 Specification”.
Create a data buffer and populate it with the data to send to the host.
In the appropriate (even or odd) TX BD for the desired endpoint:
3.1.
Set up the status register (BDnSTAT) with the correct data toggle (DATA0/1) value and the byte count
of the data buffer.
3.2.
Set up the address register (BDnADR) with the starting address of the data buffer.
3.3.
Set the UOWN bit of the status register to ‘1’.
4.
When the USB module receives an IN token, it automatically transmits the data in the buffer. Upon completion,
the module updates the status register (BDnSTAT) and sets the Token Processing Complete Interrupt Flag,
TRNIF (U1IR[3]).
© 2019-2020 Microchip Technology Inc.
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PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.5.3
28.6
Receiving an OUT Token in Device Mode
1.
2.
3.
Attach to a USB host and enumerate as described in Chapter 9 of the “USB 2.0 Specification”.
Create a data buffer with the amount of data you are expecting from the host.
In the appropriate (even or odd) TX BD for the desired endpoint:
3.1.
Set up the status register (BDnSTAT) with the correct data toggle (DATA0/1) value and the byte count
of the data buffer.
3.2.
Set up the address register (BDnADR) with the starting address of the data buffer.
3.3.
Set the UOWN bit of the status register to ‘1’.
4.
When the USB module receives an OUT token, it automatically receives the data sent by the host to the buffer.
Upon completion, the module updates the status register (BDnSTAT) and sets the Token Processing Complete
Interrupt Flag, TRNIF (U1IR[3]).
Host Mode Operation
The following sections describe how to perform common Host mode tasks. In Host mode, USB transfers are invoked
explicitly by the host software. The host software is responsible for the Acknowledge portion of the transfer. Also, all
transfers are performed using the Endpoint 0 Control register (U1EP0) and Buffer Descriptors.
28.6.1
Enable Host Mode and Discover a Connected Device
1.
2.
3.
4.
5.
Enable Host mode by setting the HOSTEN bit (U1CON[3]). This causes the Host mode control bits in other
USB OTG registers to become available.
Enable the D+ and D- pull-down resistors by setting the DPPULDWN and DMPULDWN bits
(U1OTGCON[5:4]). Disable the D+ and D- pull-up resistors by clearing the DPPULUP and DMPULUP bits
(U1OTGCON[7:6]).
At this point, SOF generation begins with the SOF counter loaded with 12,000. Eliminate noise on the USB by
clearing the SOFEN bit (U1CON[0]) to disable Start-of-Frame (SOF) packet generation.
Enable the device attached interrupt by setting the ATTACHIE bit (U1IE[6]).
Wait for the device attached interrupt (U1IR[6] = 1). This is signaled by the USB device changing the state of D
+ or D- from ‘0’ to ‘1’ (SE0 to J-state). After it occurs, wait 100 ms for the device power to stabilize.
6.
Check the state of the JSTATE and SE0 bits in U1CON. If the JSTATE bit (U1CON[7]) is ‘0’, the connecting
device is low speed. If the connecting device is low speed, set the LSPDEN and LSPD bits (U1ADDR[7] and
U1EP0[7]) to enable low-speed operation.
7. Reset the USB device by setting the USBRST bit (U1CON[4]) for at least 50 ms, sending Reset signaling on
the bus. After 50 ms, terminate the Reset by clearing USBRST.
8. In order to keep the connected device from going into suspend, enable the SOF packet generation by setting
the SOFEN bit.
9. Wait 10 ms for the device to recover from Reset.
10. Perform enumeration as described by Chapter 9 of the “USB 2.0 Specification”.
28.6.2
Complete a Control Transaction to a Connected Device
1.
2.
3.
4.
Follow the procedure described in 28.6.1 Enable Host Mode and Discover a Connected Device to discover a
device.
Set up the Endpoint Control register for bidirectional control transfers by writing 0Dh to U1EP0 (this sets the
EPCONDIS, EPTXEN and EPHSHK bits).
Place a copy of the device framework setup command in a memory buffer. See Chapter 9 of the “USB 2.0
Specification” for information on the device framework command set.
Initialize the Buffer Descriptor (BD) for the current (even or odd) TX EP0 to transfer the eight bytes of
command data for a device framework command (i.e., GET DEVICE DESCRIPTOR):
4.1.
4.2.
Set the BD Data Buffer Address (BD0ADR) to the starting address of the 8-byte memory buffer
containing the command.
Write 8008h to BD0STAT (this sets the UOWN bit and sets a byte count of eight).
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
5.
Set the USB device address of the target device in the USB Address register (U1ADDR[6:0]). After a USB bus
Reset, the device USB address will be zero. After enumeration, it will be set to another value between 1
and 127.
6. Write D0h to U1TOK; this is a SETUP token to Endpoint 0, the target device’s default control pipe. This
initiates a SETUP token on the bus, followed by a data packet. The device handshake is returned in the PID
field of BD0STAT after the packets are complete. When the USB module updates BD0STAT, a Token
Processing Complete Interrupt Flag is asserted (the TRNIF flag is set). This completes the setup phase of the
setup transaction, as referenced in Chapter 9 of the “USB 2.0 Specification”.
7. To initiate the data phase of the setup transaction (i.e., get the data for the GET DEVICE DESCRIPTOR
command), set up a buffer in memory to store the received data.
8. Initialize the current (even or odd) RX or TX (RX for IN, TX for OUT) EP0 BD to transfer the data:
8.1.
Write C040h to BD0STAT. This sets the UOWN bit, configures the Data Toggle Packet bit (DTS) to
DATA1 and sets the byte count to the length of the data buffer (64 or 40h in this case).
8.2.
Set BD0ADR to the starting address of the data buffer.
9. Write the Token register with the appropriate IN or OUT token to Endpoint 0, the target device’s default control
pipe (e.g., write 90h to U1TOK for an IN token for a GET DEVICE DESCRIPTOR command). This initiates an
IN token on the bus, followed by a data packet from the device to the host. When the data packet completes,
the BD0STAT is written and a Token Processing Complete Interrupt Flag is asserted (the TRNIF flag is set).
For control transfers with a single packet data phase, this completes the data phase of the setup transaction,
as referenced in Chapter 9 of the “USB 2.0 Specification”. If more data need to be transferred, return to
Step 8.
10. To initiate the status phase of the setup transaction, set up a buffer in memory to receive or send the zero
length status phase data packet.
11. Initialize the current (even or odd) TX EP0 BD to transfer the status data:
11.1.
Set the BDT buffer address field to the start address of the data buffer.
11.2.
Write 8000h to BD0STAT (set UOWN bit, configure DTS to DATA0 and set byte count to 0).
12. Write the Token register with the appropriate IN or OUT token to Endpoint 0, the target device’s default control
pipe (e.g., write 01h to U1TOK for an OUT token for a GET DEVICE DESCRIPTOR command). This initiates
an OUT token on the bus, followed by a zero length data packet from the host to the device. When the data
packet completes, the BD is updated with the handshake from the device and a Token Processing Complete
Interrupt Flag is asserted (the TRNIF flag is set). This completes the status phase of the setup transaction, as
described in Chapter 9 of the “USB 2.0 Specification”.
Note: Only one control transaction can be performed per frame.
28.6.3
Send a Full-Speed Bulk Data Transfer to a Target Device
1.
2.
3.
4.
5.
6.
7.
Follow the procedure described in 28.6.1 Enable Host Mode and Discover a Connected Device and 28.6.2
Complete a Control Transaction to a Connected Device to discover and configure a device.
To enable transmit and receive transfers with handshaking enabled, write 1Dh to U1EP0. If the target device is
a low-speed device, also set the LSPD (U1EP0[7]) bit. If you want the hardware to automatically retry
indefinitely if the target device asserts a NAK on the transfer, clear the Retry Disable bit, RETRYDIS
(U1EP0[6]).
Set up the BD for the current (even or odd) TX EP0 to transfer up to 64 bytes.
Set the USB device address of the target device in the address register (U1ADDR[6:0]).
Write an OUT token to the desired endpoint to U1TOK. This triggers the module’s transmit state machines to
begin transmitting the token and the data.
Wait for the Token Processing Complete Interrupt Flag, TRNIF. This indicates that the BD has been released
back to the microprocessor and the transfer has completed. If the Retry Disable bit (RETRYDIS) is set, the
handshake (ACK, NAK, STALL or ERROR (0Fh)) is returned in the BD PID field. If a STALL interrupt occurs,
the pending packet must be dequeued and the error condition in the target device cleared. If a detach interrupt
occurs (SE0 for more than 2.5 µs), then the target has detached (U1IR[0] is set).
Once the Token Processing Complete Interrupt Flag occurs (TRNIF is set), the BD can be examined and the
next data packet queued by returning to Step 2.
Note: USB speed, transceiver and pull-ups should only be configured during the module setup phase. It is not
recommended to change these settings while the module is enabled.
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.7
OTG Operation
28.7.1
Session Request Protocol (SRP)
An OTG A-device may decide to power down the VBUS supply when it is not using the USB link through the Session
Request Protocol (SRP). SRP can only be initiated at full speed. Software may do this by configuring a GPIO pin to
disable an external power transistor, or voltage regulator enable signal, which controls the VBUS supply. When the
VBUS supply is powered down, the A-device is said to have ended a USB session.
An OTG A-device or embedded host may repower the VBUS supply at any time (initiate a new session). An OTG Bdevice may also request that the OTG A-device repower the VBUS supply (initiate a new session). This is
accomplished via Session Request Protocol (SRP).
Prior to requesting a new session, the B-device must first check that the previous session has definitely ended. To do
this, the B-device must check for two conditions:
•
•
VBUS supply is below the session valid voltage.
Both D+ and D- have been low for at least 2 ms.
The B-device will be notified of Condition 1 by the SESENDIF (U1OTGIR[2]) interrupt. Software will have to manually
check for Condition 2.
Note: When the A-device powers down the VBUS supply, the B-device must disconnect its pull-up resistor from
power. If the device is self-powered, it can do this by clearing DPPULUP (U1OTGCON[7]) and DMPULUP
(U1OTGCON[6]).
The B-device may aid in achieving Condition 1 by discharging the VBUS supply through a resistor. Software may do
this by setting VBUSDIS (U1OTGCON[0]).
After these initial conditions are met, the B-device may begin requesting the new session. The B-device begins by
pulsing the D+ data line. Software should do this by setting DPPULUP (U1OTGCON[7]). The data line should be held
high for 5 to 10 ms.
The B-device then proceeds by pulsing the VBUS supply. Software should do this by setting PUVBUS (U1CNFG2[4]).
When an A-device detects SRP signaling (either via the ATTACHIF (U1IR[6]) interrupt or via the SESVDIF
(U1OTGIR[3]) interrupt), the A-device must restore the VBUS supply by properly configuring the general purpose I/O
port pin controlling the external power source.
The B-device should not monitor the state of the VBUS supply while performing VBUS supply pulsing. When the Bdevice does detect that the VBUS supply has been restored (via the SESVDIF (U1OTGIR[3]) interrupt), the B-device
must reconnect to the USB link by pulling up D+ or D- (via the DPPULUP or DMPULUP bit).
The A-device must complete the SRP by driving USB Reset signaling.
28.7.2
Host Negotiation Protocol (HNP)
In USB OTG applications, a Dual Role Device (DRD) is a device that is capable of being either a host or a peripheral.
Any OTG DRD must support Host Negotiation Protocol (HNP).
HNP allows an OTG B-device to temporarily become the USB host. The A-device must first enable the B-device to
follow HNP. Refer to the “On-The-Go Supplement” to the “USB 2.0 Specification” for more information regarding HNP.
HNP may only be initiated at full speed.
After being enabled for HNP by the A-device, the B-device requests being the host any time that the USB link is in
the suspend state, by simply indicating a disconnect. This can be done in software by clearing DPPULUP and
DMPULUP. When the A-device detects the disconnect condition (via the URSTIF (U1IR[0]) interrupt), the A-device
may allow the B-device to take over as host. The A-device does this by signaling connect as a full-speed function.
Software may accomplish this by setting DPPULUP.
If the A-device responds instead with resume signaling, the A-device remains as host. When the B-device detects the
connect condition (via ATTACHIF, U1IR[6]), the B-device becomes host. The B-device drives Reset signaling prior to
using the bus.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1170
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
When the B-device has finished in its role as host, it stops all bus activity and turns on its D+ pull-up resistor by
setting DPPULUP. When the A-device detects a suspend condition (Idle for 3 ms), the A-device turns off its D+ pullup. The A-device may also power down the VBUS supply to end the session. When the A-device detects the connect
condition (via ATTACHIF), the A-device resumes host operation and drives Reset signaling.
28.8
USB OTG Module Registers
The USB OTG module registers can be divided into four general categories:
•
•
•
•
USB OTG Module Control
USB Interrupt
USB Endpoint Management
USB VBUS Power Control
This total does not include the (up to) 128 BD registers in the BDT. Their prototypes, described in 28.3.1 BDnSTAT
and 28.3.2 BDnSTAT, are shown separately in 28.2 USB Buffer Descriptors and the BDT.
All USB OTG registers are implemented in the Least Significant Byte (LSB) of the register. Bits in the upper byte are
unimplemented and have no function. Note that some registers are instantiated only in Host mode, while other
registers have different bit instantiations and functions in Device and Host modes.
The registers described in the following sections are those that have bits with specific control and configuration
features. The following registers are used for data or address values only:
28.9
•
U1BDTP1, U1BDTP2 and U1BDTP3: Specify the 256-word page in data RAM used for the BDT; 8-bit value with
bit 0 fixed as ‘0’ for boundary alignment.
•
U1FRML and U1FRMH: Contain the 11-bit byte counter for the current data frame.
USB Interrupt Registers
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1171
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.9.1
USB OTG Interrupt Status Register (Host Mode Only)
Name:
Offset:
U1OTGIR(2)
0x600
Notes:
1. VBUS threshold crossings may either be rising or falling.
2. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set
bits, at the moment of the write, to become cleared.
Legend: HS = Hardware Settable bit; K = Write ‘1’ to Clear bit
Bit
15
14
13
12
11
10
9
8
7
IDIF
HS/R/K
0
6
T1MSECIF
HS/R/K
0
5
LSTATEIF
HS/R/K
0
4
ACTVIF
HS/R/K
0
3
SESVDIF
HS/R/K
0
2
SESENDIF
HS/R/K
0
1
0
VBUSVDIF
HS/R/K
0
Access
Reset
Bit
Access
Reset
Bit 7 – IDIF ID State Change Indicator bit
Value
Description
1
Change in ID state is detected
0
No ID state change is detected
Bit 6 – T1MSECIF 1 Millisecond Timer bit
Value
Description
1
The 1 millisecond timer has expired
0
The 1 millisecond timer has not expired
Bit 5 – LSTATEIF Line State Stable Indicator bit
Value
Description
1
USB line state (as defined by the SE0 and JSTATE bits) has been stable for 1 ms, but different from
the last time
0
USB line state has not been stable for 1 ms
Bit 4 – ACTVIF Bus Activity Indicator bit
Value
Description
1
Activity on the D+/D- lines or VBUS is detected
0
No activity on the D+/D- lines or VBUS is detected
Bit 3 – SESVDIF Session Valid Change Indicator bit
Value
Description
1
VBUS has crossed VA_SESS_END (as defined in the “USB 2.0 Specification”)(1)
0
VBUS has not crossed VA_SESS_END
Bit 2 – SESENDIF B-Device VBUS Change Indicator bit
Value
Description
1
VBUS change on B-device is detected; VBUS has crossed VB_SESS_END (as defined in the “USB 2.0
Specification”)(1)
0
VBUS has not crossed VB_SESS_END
Bit 0 – VBUSVDIF A-Device VBUS Change Indicator bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1172
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
Value
1
0
Description
VBUS change on A-device is detected; VBUS has crossed VA_VBUS_VLD (as defined in the “USB 2.0
Specification”)(1)
No VBUS change on A-device is detected
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1173
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.9.2
USB OTG Interrupt Enable Register (Host Mode Only)
Name:
Offset:
Bit
U1OTGIE
0x602
15
14
13
12
11
10
9
8
7
IDIE
R/W
0
6
T1MSECIE
R/W
0
5
LSTATEIE
R/W
0
4
ACTVIE
R/W
0
3
SESVDIE
R/W
0
2
SESENDIE
R/W
0
1
0
VBUSVDIE
R/W
0
Access
Reset
Bit
Access
Reset
Bit 7 – IDIE ID Interrupt Enable bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 6 – T1MSECIE 1 Millisecond Timer Interrupt Enable bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 5 – LSTATEIE Line State Stable Interrupt Enable bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 4 – ACTVIE Bus Activity Interrupt Enable bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 3 – SESVDIE Session Valid Interrupt Enable bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 2 – SESENDIE B-Device Session End Interrupt Enable bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 0 – VBUSVDIE A-Device VBUS Valid Interrupt Enable bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1174
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.9.3
USB Interrupt Status Register (Device Mode Only)
Name:
Offset:
U1IR(1)
0x60A
Note:
1. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set
bits, at the moment of the write, to become cleared.
Legend: HS = Hardware Settable bit; K = Write ‘1’ to Clear bit
Bit
15
14
13
12
11
10
9
8
7
STALLIF
HS/R/K
0
6
5
RESUMEIF
HS/R/K
0
4
IDLEIF
HS/R/K
0
3
TRNIF
HS/R/K
0
2
SOFIF
HS/R/K
0
1
UERRIF
HS/R/K
0
0
URSTIF
HS/R/K
0
Access
Reset
Bit
Access
Reset
Bit 7 – STALLIF STALL Handshake Interrupt bit
Value
Description
1
A STALL handshake was sent by the peripheral during the handshake phase of the transaction in
Device mode
0
A STALL handshake has not been sent
Bit 5 – RESUMEIF Resume Interrupt bit
Value
Description
1
A K-state is observed on the D+ or D- pin for 2.5 μs (differential ‘1’ for low speed, differential ‘0’ for full
speed)
0
No K-state is observed
Bit 4 – IDLEIF Idle Detect Interrupt bit
Value
Description
1
Idle condition is detected (constant Idle state of 3 ms or more)
0
No Idle condition is detected
Bit 3 – TRNIF Token Processing Complete Interrupt bit
Value
Description
1
Processing of the current token is complete; read the U1STAT register for endpoint information
0
Processing of the current token is not complete; clear the U1STAT register or load the next token from
STAT (clearing this bit causes the STAT FIFO to advance)
Bit 2 – SOFIF Start-of-Frame Token Interrupt bit
Value
Description
1
A Start-of-Frame token is received by the peripheral or the Start-of-Frame threshold is reached by the
host
0
No Start-of-Frame token is received or threshold reached
Bit 1 – UERRIF USB Error Condition Interrupt bit
Value
Description
1
An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this
bit
0
No unmasked error condition has occurred
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1175
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
Bit 0 – URSTIF USB Reset Interrupt bit
Value
Description
1
Valid USB Reset has occurred for at least 2.5 μs; Reset state must be cleared before this bit can be
reasserted
0
No USB Reset has occurred; individual bits can only be cleared by writing a ‘1’ to the bit position as
part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to
write to a single bit position will cause all set bits, at the moment of the write, to become cleared.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1176
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.9.4
USB Interrupt Status Register (Host Mode Only)
Name:
Offset:
U1IR(1)
0x60A
Note:
1. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set
bits, at the moment of the write, to become cleared.
Legend: HS = Hardware Settable bit; K = Write ‘1’ to Clear bit
Bit
15
14
13
12
11
10
9
8
7
STALLIF
HS/R/K
0
6
ATTACHIF
HS/R/K
0
5
RESUMEIF
HS/R/K
0
4
IDLEIF
HS/R/K
0
3
TRNIF
HS/R/K
0
2
SOFIF
HS/R/K
0
1
UERRIF
HS/R/K
0
0
DETACHIF
HS/R/K
0
Access
Reset
Bit
Access
Reset
Bit 7 – STALLIF STALL Handshake Interrupt bit
Value
Description
1
A STALL handshake was sent by the peripheral during the handshake phase of the transaction in
Device mode
0
A STALL handshake has not been sent
Bit 6 – ATTACHIF Peripheral Attach Interrupt bit
Value
Description
1
A peripheral attachment has been detected by the module; it is set if the bus state is not SE0 and there
has been no bus activity for 2.5 μs
0
No peripheral attachment has been detected
Bit 5 – RESUMEIF Resume Interrupt bit
Value
Description
1
A K-state is observed on the D+ or D- pin for 2.5 μs (differential ‘1’ for low speed, differential ‘0’ for full
speed)
0
No K-state is observed
Bit 4 – IDLEIF Idle Detect Interrupt bit
Value
Description
1
Idle condition is detected (constant Idle state of 3 ms or more)
0
No Idle condition is detected
Bit 3 – TRNIF Token Processing Complete Interrupt bit
Value
Description
1
Processing of the current token is complete; read the U1STAT register for endpoint information
0
Processing of the current token is not complete; clear the U1STAT register or load the next token from
STAT (clearing this bit causes the STAT FIFO to advance)
Bit 2 – SOFIF Start-of-Frame Token Interrupt bit
Value
Description
1
A Start-of-Frame token is received by the peripheral or the Start-of-Frame threshold is reached by the
host
0
No Start-of-Frame token is received or threshold reached
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1177
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
Bit 1 – UERRIF USB Error Condition Interrupt bit
Value
Description
1
An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this
bit
0
No unmasked error condition has occurred
Bit 0 – DETACHIF Detach Interrupt bit
Value
Description
1
A peripheral detachment has been detected by the module; Reset state must be cleared before this bit
can be reasserted
0
No peripheral detachment is detected. Individual bits can only be cleared by writing a ‘1’ to the bit
position as part of a word write operation on the entire register. Using Boolean instructions or bitwise
operations to write to a single bit position will cause all set bits, at the moment of the write, to become
cleared.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1178
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.9.5
USB Interrupt Enable Register (All USB Modes)
Name:
Offset:
U1IE
0x60C
Note:
1. This bit is unimplemented in Device mode, read as ‘0’.
Bit
15
14
13
12
11
10
9
8
7
STALLIE
6
ATTACHIE
5
RESUMEIE
4
IDLEIE
3
TRNIE
2
SOFIE
1
UERRIE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
URSTIE or
DETACHIE
R/W
0
Access
Reset
Bit
Access
Reset
Bit 7 – STALLIE STALL Handshake Interrupt Enable bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 6 – ATTACHIE Peripheral Attach Interrupt bit (Host mode only)(1)
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 5 – RESUMEIE Resume Interrupt bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 4 – IDLEIE Idle Detect Interrupt bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 3 – TRNIE Token Processing Complete Interrupt bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 2 – SOFIE Start-of-Frame Token Interrupt bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 1 – UERRIE USB Error Condition Interrupt bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 0 – URSTIE or DETACHIE USB Reset Interrupt (Device mode) or USB Detach Interrupt (Host mode) Enable bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1179
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
Value
1
0
Description
Interrupt is enabled
Interrupt is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1180
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.9.6
USB Error Interrupt Status Register
Name:
Offset:
U1EIR(1)
0x60E
Note:
1. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set
bits, at the moment of the write, to become cleared.
Legend: K = Write ‘1’ to Clear bit; HS = Hardware Settable bit
Bit
15
14
13
12
11
10
9
8
Bit
7
BTSEF
6
5
DMAEF
4
BTOEF
3
DFN8EF
2
CRC16EF
0
PIDEF
Access
Reset
HS/R/K
0
HS/R/K
0
HS/R/K
0
HS/R/K
0
HS/R/K
0
1
CRC5EF or
EOFEE
HS/R/K
0
Access
Reset
HS/R/K
0
Bit 7 – BTSEF Bit Stuff Error Flag bit
Value
Description
1
Bit stuff error has been detected
0
No bit stuff error has been detected
Bit 5 – DMAEF DMA Error Flag bit
Value
Description
1
A USB DMA error condition is detected; the data size indicated by the BD byte count field is less than
the number of received bytes, the received data are truncated
0
No DMA error
Bit 4 – BTOEF Bus Turnaround Time-out Error Flag bit
Value
Description
1
Bus turnaround time-out has occurred
0
No bus turnaround time-out has occurred
Bit 3 – DFN8EF Data Field Size Error Flag bit
Value
Description
1
Data field was not an integral number of bytes
0
Data field was an integral number of bytes
Bit 2 – CRC16EF CRC16 Failure Flag bit
Value
Description
1
CRC16 failed
0
CRC16 passed
Bit 1 – CRC5EF or EOFEE CRC5 Host Error Flag bit (For Device Mode Only)
Value
Description
1
Token packet is rejected due to CRC5 error
0
Token packet is accepted (no CRC5 error)
Bit 1 – EOFEF End-of-Frame (EOF) Error Flag bit (For Host Mode Only)
Value
Description
1
End-of-Frame error has occurred
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Datasheet
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PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
Value
0
Description
End-of-Frame interrupt is disabled
Bit 0 – PIDEF PID Check Failure Flag bit
Value
Description
1
PID check failed
0
PID check passed
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1182
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.9.7
USB Error Interrupt Enable Register
Name:
Offset:
Bit
U1EIE
0x610
15
14
13
12
11
10
9
8
7
BTSEE
6
5
DMAEE
4
BTOEE
3
DFN8EE
2
CRC16EE
0
PIDEE
R/W
0
R/W
0
R/W
0
R/W
0
1
CRC5EE or
EOFEE
R/W
0
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
Bit 7 – BTSEE Bit Stuff Error Interrupt Enable bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 5 – DMAEE DMA Error Interrupt Enable bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 4 – BTOEE Bus Turnaround Time-out Error Interrupt Enable bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 3 – DFN8EE Data Field Size Error Interrupt Enable bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 2 – CRC16EE CRC16 Failure Interrupt Enable bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 1 – CRC5EE or EOFEE CRC5 Host Error Interrupt Enable bit (For Device Mode Only)
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 1 – EOFEE End-of-Frame (EOF) Error interrupt Enable bit (For Host Mode Only)
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
Bit 0 – PIDEE PID Check Failure Interrupt Enable bit
Value
Description
1
Interrupt is enabled
0
Interrupt is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1183
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10
USB OTG Registers
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1184
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.1 USB OTG Status Register (Host Mode Only)
Name:
Offset:
U1OTGSTAT
0x604
Legend: HSC = Hardware Settable/Clearable bit
Bit
15
14
13
12
11
10
9
8
7
ID
HSC/R
0
6
5
LSTATE
HSC/R
0
4
3
SESVD
HSC/R
0
2
SESEND
HSC/R
0
1
0
VBUSVD
HSC/R
0
Access
Reset
Bit
Access
Reset
Bit 7 – ID ID Pin State Indicator bit
Value
Description
1
No plug is attached or a Type B cable has been plugged into the USB receptacle
0
A Type A plug has been plugged into the USB receptacle
Bit 5 – LSTATE Line State Stable Indicator bit
Value
Description
1
The USB line state (as defined by SE0 and JSTATE) has been stable for the previous 1 ms
0
The USB line state has not been stable for the previous 1 ms
Bit 3 – SESVD Session Valid Indicator bit
Value
Description
1
The VBUS voltage is above VA_SESS_VLD (as defined in the “USB 2.0 Specification”) on the A or Bdevice
0
The VBUS voltage is below VA_SESS_VLD on the A or B-device
Bit 2 – SESEND B Session End Indicator bit
Value
Description
1
The VBUS voltage is below VB_SESS_END (as defined in the “USB 2.0 Specification”) on the B-device
0
The VBUS voltage is above VB_SESS_END on the B-device
Bit 0 – VBUSVD A VBUS Valid Indicator bit
Value
Description
1
The VBUS voltage is above VA_VBUS_VLD (as defined in the “USB 2.0 Specification”) on the A-device
0
The VBUS voltage is below VA_VBUS_VLD on the A-device
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1185
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.2 USB On-The-Go Control Register
Name:
Offset:
U1OTGCON
0x606
Note:
1. These bits are only used in Host mode; do not use in Device mode.
Legend: r = Reserved bit
Bit
15
14
13
12
11
10
9
8
7
DPPULUP
R/W
0
6
DMPULUP
R/W
0
5
DPPULDWN
R/W
0
4
DMPULDWN
R/W
0
3
Reserved
r
0
2
OTGEN
R/W
0
1
Reserved
r
0
0
VBUSDIS
R/W
0
Access
Reset
Bit
Access
Reset
Bit 7 – DPPULUP D+ Pull-up Enable bit
Value
Description
1
D+ data line pull-up resistor is enabled
0
D+ data line pull-up resistor is disabled
Bit 6 – DMPULUP D- Pull-up Enable bit
Value
Description
1
D- data line pull-up resistor is enabled
0
D- data line pull-up resistor is disabled
Bit 5 – DPPULDWN D+ Pull-Down Enable bit(1)
Value
Description
1
D+ data line pull-down resistor is enabled
0
D+ data line pull-down resistor is disabled
Bit 4 – DMPULDWN D- Pull-Down Enable bit(1)
Value
Description
1
D- data line pull-down resistor is enabled
0
D- data line pull-down resistor is disabled
Bit 3 – Reserved Maintain as ‘0’
Bit 2 – OTGEN OTG Features Enable bit(1)
Value
Description
1
USB OTG is enabled; all D+/D- pull-up and pull-down bits are enabled
0
USB OTG is disabled; D+/D- pull-up and pull-down bits are controlled in hardware by the settings of
the HOSTEN and USBEN (U1CON[3:0]) bits
Bit 1 – Reserved Maintain as ‘0’
Bit 0 – VBUSDIS VBUS Discharge Enable bit(1)
Value
Description
1
VBUS line is discharged through a resistor
0
VBUS line is not discharged
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1186
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.3 USB Power Control Register
Name:
Offset:
U1PWRC
0x608
Note:
1. Do not clear this bit unless the HOSTEN, USBEN and OTGEN bits (U1CON[3,0] and U1OTGCON[2]) are all
cleared.
Legend: HC = Hardware Clearable bit; HSC = Hardware Settable/Clearable bit
Bit
15
14
13
12
11
10
9
8
7
UACTPND
HSC/R
x
6
5
4
USLPGRD
R/W
0
3
2
1
USUSPND
HC/R/W
0
0
USBPWR
R/W
0
Access
Reset
Bit
Access
Reset
Bit 7 – UACTPND USB Activity Pending bit
Value
Description
1
Module should not be suspended at the moment (requires the USLPGRD bit to be set)
0
Module may be suspended or powered down
Bit 4 – USLPGRD USB Sleep/Suspend Guard bit
Value
Description
1
Indicates to the USB module that it is about to be suspended or powered down
0
No suspend
Bit 1 – USUSPND USB Suspend Mode Enable bit
Value
Description
1
USB OTG module is in Suspend mode; USB clock is gated and the transceiver is placed in a lowpower state
0
Normal USB OTG operation
Bit 0 – USBPWR USB Operation Enable bit
Value
Description
1
USB OTG module is enabled
0
USB OTG module is disabled(1)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1187
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.4 USB Status Register
Name:
Offset:
U1STAT
0x612
Note:
1. This bit is only valid for endpoints with available even and odd BD registers.
Legend: HSC = Hardware Settable/Clearable bit
Bit
15
14
7
6
13
12
11
10
9
8
4
3
DIR
HSC/R
0
2
PPBI
HSC/R
0
1
0
Access
Reset
Bit
Access
Reset
HSC/R
0
5
ENDPT[3:0]
HSC/R
HSC/R
0
0
HSC/R
0
Bits 7:4 – ENDPT[3:0] USB Activity Pending bits
Number of the last endpoint activity bits.
(Represents the number of the BDT updated by the last USB transfer.)
Value
Description
1111
Endpoint 15
1110
Endpoint 14
...
0001
Endpoint 1
0000
Endpoint 0
Bit 3 – DIR Last BD Direction Indicator bit
Value
Description
1
The last transaction was a transmit transfer (TX)
0
The last transaction was a receive transfer (RX)
Bit 2 – PPBI Ping-Pong BD Pointer Indicator bit(1)
Value
Description
1
The last transaction was to the odd BD bank
0
The last transaction was to the even BD bank
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1188
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.5 USB Control Register (Device Mode)
Name:
Offset:
U1CON
0x614
Legend: HSC = Hardware Settable/Clearable bit
Bit
15
14
13
12
11
10
9
8
7
6
SE0
HSC/R
x
5
PKTDIS
R/W
0
4
3
HOSTEN
R/W
0
2
RESUME
R/W
0
1
PPBRST
R/W
0
0
USBEN
R/W
0
Access
Reset
Bit
Access
Reset
Bit 6 – SE0 Live Single-Ended Zero Flag bit
Value
Description
1
Single-ended zero is active on the USB bus
0
No single-ended zero is detected
Bit 5 – PKTDIS Packet Transfer Disable bit
Value
Description
1
SIE token and packet processing are disabled; automatically set when a SETUP token is received
0
SIE token and packet processing are enabled
Bit 3 – HOSTEN Host Mode Enable bit
Value
Description
1
USB host capability is enabled; pull-downs on D+ and D- are activated in hardware
0
USB host capability is disabled
Bit 2 – RESUME Resume Signaling Enable bit
Value
Description
1
Resume signaling is activated
0
Resume signaling is disabled
Bit 1 – PPBRST Ping-Pong Buffers Reset bit
Value
Description
1
Resets all Ping-Pong Buffer Pointers to the even BD banks
0
Ping-Pong Buffer Pointers are not reset
Bit 0 – USBEN USB Module Enable bit
Value
Description
1
USB module and supporting circuitry are enabled (device attached); D+ pull-up is activated in
hardware
0
USB module and supporting circuitry are disabled (device detached)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1189
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.6 USB Control Register (Host Mode Only)
Name:
Offset:
U1CON
0x614
Legend: HSC = Hardware Settable/Clearable bit
Bit
15
14
13
12
11
10
9
8
7
JSTATE
HSC/R
x
6
SE0
HSC/R
x
5
TOKBUSY
R/W
0
4
USBRST
R/W
0
3
HOSTEN
R/W
0
2
RESUME
R/W
0
1
PPBRST
R/W
0
0
SOFEN
R/W
0
Access
Reset
Bit
Access
Reset
Bit 7 – JSTATE Live Differential Receiver J-State Flag bit
Value
Description
1
J-state (differential ‘0’ in low speed, differential ‘1’ in full speed) is detected on the USB
0
No J-state is detected
Bit 6 – SE0 Live Single-Ended Zero Flag bit
Value
Description
1
Single-ended zero is active on the USB bus
0
No single-ended zero is detected
Bit 5 – TOKBUSY Token Busy Status bit
Value
Description
1
Token is being executed by the USB module in On-The-Go state
0
No token is being executed
Bit 4 – USBRST USB Module Reset bit
Value
Description
1
USB Reset has been generated for a software Reset; application must set this bit for 50 ms, then clear
it
0
USB Reset is terminated
Bit 3 – HOSTEN Host Mode Enable bit
Value
Description
1
USB host capability is enabled; pull-downs on D+ and D- are activated in hardware
0
USB host capability is disabled
Bit 2 – RESUME Resume Signaling Enable bit
Value
Description
1
Resume signaling is activated; software must set bit for 10 ms and then clear to enable remote wakeup
0
Resume signaling is disabled
Bit 1 – PPBRST Ping-Pong Buffers Reset bit
Value
Description
1
Resets all Ping-Pong Buffer Pointers to the even BD banks
0
Ping-Pong Buffer Pointers are not reset
Bit 0 – SOFEN Start-of-Frame Enable bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1190
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
Value
1
0
Description
Start-of-Frame token is sent every one 1 ms
Start-of-Frame token is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1191
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.7 USB Address Register
Name:
Offset:
U1ADDR
0x616
Note:
1. Host mode only. In Device mode, this bit is unimplemented and read as ‘0’.
Bit
15
14
13
12
11
10
9
8
7
LSPDEN
R/W
0
6
5
4
2
1
0
R/W
0
R/W
0
R/W
0
3
DEVADDR[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit 7 – LSPDEN Low-Speed Enable Indicator bit(1)
Value
Description
1
USB module operates at low speed
0
USB module operates at full speed
Bits 6:0 – DEVADDR[6:0] USB Device Address bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1192
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.8 BDT Address Low Bits Register
Name:
Offset:
Bit
U1BDTP1
0x618
15
14
13
12
11
10
9
8
7
6
5
3
2
1
0
R/W
0
R/W
0
R/W
0
4
BDTPTRL[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 7:1 – BDTPTRL[6:0] BDT Address Low bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1193
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.9 Current Data Frame Counter Register Low
Bit
Name:
Offset:
U1FRML
0x61A
15
14
13
12
7
6
5
4
11
10
9
8
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
FRM[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – FRM[7:0] Data Frame Counter bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1194
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.10 Current Data Frame Counter Register High
Bit
Name:
Offset:
U1FRMH
0x61C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
FRM[10:8]
R/W
0
0
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
Bits 2:0 – FRM[10:8] Data Frame Counter bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1195
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.11 USB Token Register (Host Mode Only)
Name:
Offset:
U1TOK
0x61E
Note:
1. All other combinations are reserved and are not to be used.
Bit
15
14
7
6
13
12
11
10
5
4
3
2
9
8
1
0
R/W
0
R/W
0
Access
Reset
Bit
PID[3:0]
Access
Reset
R/W
0
R/W
0
EP[3:0]
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:4 – PID[3:0] Token Type Identifier bits
Value
Description
1101
SETUP (TX) token type transaction(1)
1001
IN (RX) token type transaction(1)
0001
OUT (TX) token type transaction(1)
Bits 3:0 – EP[3:0] Token Command Endpoint Address bits
This value must specify a valid endpoint on the attached device.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1196
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.12 USB OTG Start of Token Threshold Register (Host Mode Only)
Name:
Offset:
Bit
U1SOF
0x620
15
14
13
12
7
6
5
4
11
10
9
8
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
CNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – CNT[7:0] Start-of-Frame Size bits
Value represents 10 + (packet size of n bytes). For example:
Value
Description
01001010
64-byte packet
00101010
32-byte packet
00010010
8-byte packet
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1197
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.13 BDT Address High Bits Register
Name:
Offset:
Bit
U1BDTP2
0x622
15
14
13
12
7
6
5
4
R/W
0
R/W
0
R/W
0
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
3
BDTPTRH[7:0]
R/W
R/W
0
0
Bits 7:0 – BDTPTRH[7:0] BDT Address High bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1198
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.14 BDT Address Upper Bits Register
Name:
Offset:
Bit
U1BDTP3
0x624
15
14
13
12
7
6
5
4
R/W
0
R/W
0
R/W
0
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
3
BDTPTRU[7:0]
R/W
R/W
0
0
Bits 7:0 – BDTPTRU[7:0] BDT Address Upper bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1199
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.15 USB Configuration Register 1
Name:
Offset:
U1CNFG1
0x626
Note:
1. This bit is only active when the UTRDIS bit (U1CNFG2[0]) is set.
Bit
15
14
13
12
11
10
9
7
UTEYE
R/W
0
6
UOEMON
R/W
0
5
4
USBSIDL
R/W
0
3
2
1
8
Access
Reset
Bit
Access
Reset
0
PPB[1:0]
R/W
0
R/W
0
Bit 7 – UTEYE USB Eye Pattern Test Enable bit
Value
Description
1
Eye pattern test is enabled
0
Eye pattern test is disabled
Bit 6 – UOEMON USB OE Monitor Enable bit(1)
Value
Description
1
OE signal is active; it indicates intervals during which the D+/D- lines are driving
0
OE signal is inactive
Bit 4 – USBSIDL USB OTG Stop in Idle Mode bit
Value
Description
1
Discontinues module operation when the device enters Idle mode
0
Continues module operation in Idle mode
Bits 1:0 – PPB[1:0] Ping-Pong Buffers Configuration bits
Value
Description
11
Even/Odd Ping-Pong Buffers are enabled for Endpoints 1 to 15
10
Even/Odd Ping-Pong Buffers are enabled for all endpoints
01
Even/Odd Ping-Pong Buffers are enabled for RX Endpoint 0
00
Even/Odd Ping-Pong Buffers are disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1200
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.10.16 USB Configuration Register 2
Name:
Offset:
Bit
U1CNFG2
0x628
15
14
13
12
11
10
9
8
7
6
5
4
PUVBUS
R/W
0
3
EXTI2CEN
R/W
0
2
1
0
Access
Reset
Bit
Access
Reset
Bit 4 – PUVBUS VBUS Pull-up Enable bit
Value
Description
1
Pull-up on VBUS pin is enabled
0
Pull-up on VBUS pin is disabled
Bit 3 – EXTI2CEN I2C Interface for External Module Control Enable bit
Value
Description
1
External module(s) is controlled via the I2C interface
0
External module(s) is controlled via the dedicated pins
28.11
USB Endpoint Management Registers
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1201
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.1 USB Endpoint 0 Control Register
Name:
Offset:
U1EP0
0x62A
Note:
1. These bits are available only for U1EP0 and only in Host mode. For all other U1EPn registers, these bits are
always unimplemented and read as ‘0’.
Bit
15
14
13
12
11
10
9
8
7
LSPD
R/W
0
6
RETRYDIS
R/W
0
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 7 – LSPD Low-Speed Direct Connection Enable bit (U1EP0 only)(1)
Value
Description
1
Direct connection to a low-speed device is enabled
0
Direct connection to a low-speed device is disabled
Bit 6 – RETRYDIS Retry Disable bit (U1EP0 only)(1)
Value
Description
1
Retry NAK transactions are disabled
0
Retry NAK transactions are enabled; retry is done in hardware
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1202
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.2 USB Endpoint 1 Control Register
Name:
Offset:
Bit
U1EP1
0x62C
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1203
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.3 USB Endpoint 2 Control Register
Name:
Offset:
Bit
U1EP2
0x62E
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1204
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.4 USB Endpoint 3 Control Register
Name:
Offset:
Bit
U1EP3
0x630
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1205
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.5 USB Endpoint 4 Control Register
Name:
Offset:
Bit
U1EP4
0x632
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1206
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.6 USB Endpoint 5 Control Register
Name:
Offset:
Bit
U1EP5
0x634
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1207
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.7 USB Endpoint 6 Control Register
Name:
Offset:
Bit
U1EP6
0x636
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1208
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.8 USB Endpoint 7 Control Register
Name:
Offset:
Bit
U1EP7
0x638
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1209
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.9 USB Endpoint 8 Control Register
Name:
Offset:
Bit
U1EP8
0x63A
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1210
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.10 USB Endpoint 9 Control Register
Name:
Offset:
Bit
U1EP9
0x63C
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1211
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.11 USB Endpoint 10 Control Register
Name:
Offset:
Bit
U1EP10
0x63E
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1212
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.12 USB Endpoint 11 Control Register
Name:
Offset:
Bit
U1EP11
0x640
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1213
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.13 USB Endpoint 12 Control Register
Name:
Offset:
Bit
U1EP12
0x642
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1214
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.14 USB Endpoint 13 Control Register
Name:
Offset:
Bit
U1EP13
0x644
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1215
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.15 USB Endpoint 14 Control Register
Name:
Offset:
Bit
U1EP14
0x646
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1216
PIC24FJ512GU410 Family Data Sheet
USB with On-The-Go (USB OTG) Support
28.11.16 USB Endpoint 15 Control Register
Name:
Offset:
Bit
U1EP15
0x648
15
14
13
12
11
10
9
8
7
6
5
4
EPCONDIS
R/W
0
3
EPRXEN
R/W
0
2
EPTXEN
R/W
0
1
EPSTALL
R/W
0
0
EPHSHK
R/W
0
Access
Reset
Bit
Access
Reset
Bit 4 – EPCONDIS Bidirectional Endpoint Control bit
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
If EPTXEN and EPRXEN = 1:
Value
Description
1
Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0
Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
Bit 3 – EPRXEN Endpoint Receive Enable bit
Value
Description
1
Endpoint n receive is enabled
0
Endpoint n receive is disabled
Bit 2 – EPTXEN Endpoint Transmit Enable bit
Value
Description
1
Endpoint n transmit is enabled
0
Endpoint n transmit is disabled
Bit 1 – EPSTALL Endpoint STALL Status bit
Value
Description
1
Endpoint n was stalled
0
Endpoint n was not stalled
Bit 0 – EPHSHK Endpoint Handshake Enable bit
Value
Description
1
Endpoint handshake is enabled
0
Endpoint handshake is disabled (typically used for isochronous endpoints)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1217
PIC24FJ512GU410 Family Data Sheet
Special Features
29.
Special Features
Notes: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a
comprehensive reference source. For more information, refer to the following sections of the “dsPIC33/PIC24 Family
Reference Manual”, which are available from the Microchip website (www.microchip.com ). The information in this
data sheet supersedes the information in the FRM.
• “Watchdog Timer (WDT)” (DS39697)
• “High-Level Device Integration” (DS39719)
• “Programming and Diagnostics” (DS39716)
PIC24FJ512GU410 family devices include several features intended to maximize application flexibility and reliability,
and minimize cost through elimination of external components. These are:
•
•
•
•
•
•
29.1
Flexible Configuration
Watchdog Timer (WDT)
Code Protection
JTAG Boundary Scan Interface
In-Circuit Serial Programming™
In-Circuit Emulation
Configuration Bits
The Configuration bits are stored in the last page location of implemented program memory. These bits can be set or
cleared to select various device configurations. There are two types of Configuration bits: system operation bits and
code-protect bits. The system operation bits determine the power-on settings for system-level components, such as
the oscillator and the Watchdog Timer. The code-protect bits prevent program memory from being read and written.
29.1.1
Considerations for Configuring PIC24FJ512GU410 Family Devices
In PIC24FJ512GU410 family devices, the Configuration bytes are implemented as volatile memory. This means that
configuration data must be programmed each time the device is powered up. Configuration data are stored in the
three words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific
locations are shown in Table 29-1. The configuration data are automatically loaded from the Flash Configuration
Words to the proper Configuration registers during device Resets.
Note: Configuration data are reloaded on all types of device Resets.
When creating applications for these devices, users should always specifically allocate the location of the Flash
Configuration Word for configuration data. This is to make certain that program code is not stored in this address
when the code is compiled.
The upper byte of all Flash Configuration Words in program memory should always be ‘0000 0000’. This makes
them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since
Configuration bits are not implemented in the corresponding locations, writing ‘0’s to these locations has no effect on
device operation.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1218
PIC24FJ512GU410 Family Data Sheet
Special Features
Table 29-1. Configuration Words Addresses
Register
Name
Single Partition
Dual Partition, Active
Dual Partition, Inactive
512k
256k
128k
512k
256k
128k
512k
256k
128k
FSEC(2)
0x055F00
0x02BF00
0x015F00
0x02AF00
0x015F00
0x00AF00
0x42AF00
0x415F00
0x40AF00
FBSLIM(2)
0x055F10
0x02BF10
0x015F10
0x02AF10
0x015F10
0x00AF10
0x42AF10
0x415F10
0x40AF10
FSIGN(2)
0x055F14
0x02BF14
0x015F14
0x02AF14
0x015F14
0x00AF14
0x42AF14
0x415F14
0x40AF14
FOSCSEL
0x055F18
0x02BF18
0x015F18
0x02AF18
0x015F18
0x00AF18
0x42AF18
0x415F18
0x40AF18
FOSC
0x055F1C
0x02BF1C
0x015F1C
0x02AF1C
0x015F1C
0x00AF1C
0x42AF1C
0x415F1C
0x40AF1C
FWDT
0x055F20
0x02BF20
0x015F20
0x02AF20
0x015F20
0x00AF20
0x42AF20
0x415F20
0x40AF20
FPOR
0x055F24
0x02BF24
0x015F24
0x02AF24
0x015F24
0x00AF24
0x42AF24
0x415F24
0x40AF24
FICD
0x055F28
0x02BF28
0x015F28
0x02AF28
0x015F28
0x00AF28
0x42AF28
0x415F28
0x40AF28
FDMTIVTL
0x055F2C
0x02BF2C
0x015F2C
0x02AF2C
0x015F2C
0x00AF2C
0x42AF2C
0x415F2C
0x40AF2C
FDMTIVTH
0x055F30
0x02BF30
0x015F30
0x02AF30
0x015F30
0x00AF30
0x42AF30
0x415F30
0x40AF30
FDMTCNTL
0x055F34
0x02BF34
0x015F34
0x02AF34
0x015F34
0x00AF34
0x42AF34
0x415F34
0x40AF34
FDMTCNTH
0x055F38
0x02BF38
0x015F38
0x02AF38
0x015F38
0x00AF38
0x42AF38
0x415F38
0x40AF38
FDMT
0x055F3C
0x02BF3C
0x015F3C
0x02AF3C
0x015F3C
0x00AF3C
0x42AF3C
0x415F3C
0x40AF3C
FDEVOPT1
0x055F40
0x02BF40
0x015F40
0x02AF40
0x015F40
0x00AF40
0x42AF40
0x415F40
0x40AF40
FALTREG
0x055F44
0x02BF44
0x015F44
0x02AF44
0x015F44
0x00AF44
0x42AF44
0x415F44
0x40AF44
FBTSEQ
0x055FFC
0x02BFFC
0x015FFC
0x02AFFC
0x015FFC
0x00AFFC
0x42AFFC
0x415FFC
0x40AFFC
FBOOT(1)
0x801800
Notes:
1. FBOOT resides in calibration memory space.
2. Changes to the Inactive Partition Configuration Words affect how the Active Partition accesses the Inactive
Partition.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1219
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.2
FSEC Configuration Register
Name:
FSEC
Legend: PO = Program Once bit
Bit
Access
Reset
Bit
15
AIVTDIS
R/PO
1
14
7
6
R/PO
1
12
11
R/PO
1
GSS[1:0]
Access
Reset
13
R/PO
1
5
GWRP
R/PO
1
4
10
CSS[2:0]
R/PO
1
R/PO
1
2
1
3
BSEN
R/PO
1
9
BSS[1:0]
R/PO
1
R/PO
1
8
CWRP
R/PO
1
0
BWRP
R/PO
1
Bit 15 – AIVTDIS Alternate Interrupt Vector Table Disable bit
Value
Description
1
Disables AIVT; INTCON2[8] (AIVTEN) bit is not available
0
Enables AIVT; INTCON2[8] (AIVTEN) bit is available
Bits 11:9 – CSS[2:0] Configuration Segment (CS) Code Protection Level bits
Value
Description
111
No protection (other than CWRP)
110
Standard security
10x
Enhanced security
0xx
High security
Bit 8 – CWRP Configuration Segment Program Write Protection bit
Value
Description
1
Configuration Segment is not write-protected
0
Configuration Segment is write-protected
Bits 7:6 – GSS[1:0] General Segment (GS) Code Protection Level bits
Value
Description
11
No protection (other than GWRP)
10
Standard security
0x
High security
Bit 5 – GWRP General Segment Program Write Protection bit
Value
Description
1
General Segment is not write-protected
0
General Segment is write-protected
Bit 3 – BSEN Boot Segment (BS) Control bit
Value
Description
1
No Boot Segment is enabled
0
Boot Segment size is determined by BSLIM[12:0]
Bits 2:1 – BSS[1:0] Boot Segment Code Protection Level bits
Value
Description
11
No protection (other than BWRP)
10
Standard security
0x
High security
Bit 0 – BWRP Boot Segment Program Write Protection bit
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1220
PIC24FJ512GU410 Family Data Sheet
Special Features
Value
1
0
Description
Boot Segment can be written
Boot Segment is write-protected
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1221
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.3
FBSLIM Configuration Register
Name:
FBSLIM
Note:
1. The BSLIMx bits are a ‘write-once’ element. If, after the Reset sequence, they are not erased (all ‘1’s), then
programming of the FBSLIM bits is prohibited. An attempt to do so will fail to set the WR bit (NVMCON[15]),
and consequently, have no effect.
Legend: PO = Program Once bit
PO = Program Once bit
Bit
15
14
13
Access
Reset
Bit
Access
Reset
7
6
5
R/PO
1
R/PO
1
R/PO
1
12
11
R/PO
1
R/PO
1
4
3
BSLIM[7:0]
R/PO
R/PO
1
1
10
BSLIM[12:8]
R/PO
1
9
8
R/PO
1
R/PO
1
2
1
0
R/PO
1
R/PO
1
R/PO
1
Bits 12:0 – BSLIM[12:0] Active Boot Segment Code Flash Page Address Limit (Inverted) bits(1)
This bit field contains the last active Boot Segment Page + 1 (i.e., first page address of GS). The value is stored as
an inverted page address, such that programming additional ‘0’s can only increase the size of BS. If BSLIM[12:0] is
set to all ‘1’s (unprogrammed default), the active Boot Segment size is zero.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1222
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.4
FSIGN Configuration Register
Name:
FSIGN
Legend: PO = Program Once bit
Bit
Access
Reset
Bit
15
SIGN
R/PO
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit 15 – SIGN Valid Configuration bit
This bit must be maintained as ‘0’.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1223
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.5
FOSCSEL Configuration Register
Name:
FOSCSEL
Legend: PO = Program Once bit; r = Reserved bit
Bit
15
14
13
12
11
10
9
8
Reserved[1:0]
Access
Reset
Bit
Access
Reset
7
IESO
R/PO
1
6
R/PO
1
5
4
PLLMODE[3:0]
R/PO
R/PO
1
1
3
2
R/PO
1
R/PO
1
r
0
r
0
1
FNOSC[2:0]
R/PO
1
0
R/PO
1
Bits 9:8 – Reserved[1:0] Maintain as ‘0’
Bit 7 – IESO Two-Speed Oscillator Start-up Enable bit
Value
Description
1
Starts up the device with FRC, then automatically switches to the user-selected oscillator when ready
0
Starts up the device with the user-selected oscillator source
Bits 6:3 – PLLMODE[3:0] Frequency Multiplier Select bits
Value
Description
1111
No PLL is used (PLLEN bit is unavailable)
1110
8x PLL is selected
1101
6x PLL is selected
1100
4x PLL is selected
0111
96 MHz PLL is selected (Input Frequency = 48 MHz)
0110
96 MHz PLL is selected (Input Frequency = 32 MHz)
0101
96 MHz PLL is selected (Input Frequency = 24 MHz)
0100
96 MHz PLL is selected (Input Frequency = 20 MHz)
0011
96 MHz PLL is selected (Input Frequency = 16 MHz)
0010
96 MHz PLL is selected (Input Frequency = 12 MHz)
0001
96 MHz PLL is selected (Input Frequency = 8 MHz)
0000
96 MHz PLL is selected (Input Frequency = 4 MHz)
Bits 2:0 – FNOSC[2:0] Oscillator Selection bits
Value
Description
111
Oscillator with Frequency Divider (OSCFDIV)
110
Reserved
101
Low-Power RC Oscillator (LPRC)
100
Secondary Oscillator (SOSC)
011
Primary Oscillator with PLL (XTPLL, HSPLL, ECPLL)
010
Primary Oscillator (XT, HS, EC)
001
Fast RC Oscillator with PLL (FRCPLL)
000
Fast RC Oscillator (FRC)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1224
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.6
FOSC Configuration Register
Name:
FOSC
Legend: PO = Program Once bit
Bit
15
14
13
12
11
10
9
5
IOL1WAY
R/PO
1
4
PLLSS
R/PO
1
3
SOSCSEL
R/PO
1
2
OSCIOFCN
R/PO
1
1
8
Access
Reset
Bit
Access
Reset
7
6
FCKSM[1:0]
R/PO
R/PO
1
1
0
POSCMD[1:0]
R/PO
R/PO
1
1
Bits 7:6 – FCKSM[1:0] Clock Switching and Monitor Selection bits
Value
Description
1x
Clock switching and the Fail-Safe Clock Monitor are disabled
01
Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00
Clock switching and the Fail-Safe Clock Monitor are enabled
Bit 5 – IOL1WAY Peripheral Pin Select Configuration bit
Value
Description
1
The IOLOCK bit can be set only once (with unlock sequence)
0
The IOLOCK bit can be set and cleared as needed (with unlock sequence)
Bit 4 – PLLSS PLL Secondary Selection Configuration bit
This Configuration bit only takes effect when the PLL is NOT being used by the system (i.e., not selected as part of
the system clock source). Used to generate an independent clock out of REFO.
Value
Description
1
PLL is fed by the Primary Oscillator
0
PLL is fed by the on-chip Fast RC (FRC) Oscillator
Bit 3 – SOSCSEL SOSC Selection Configuration bit
Value
Description
1
Crystal (SOSCI/SOSCO) mode
0
Digital (SCLKI) Externally Supplied Clock mode
Bit 2 – OSCIOFCN CLKO Enable Configuration bit
Value
Description
1
CLKO output signal is active on the OSCO pin (when the Primary Oscillator is disabled or configured
for EC mode)
0
CLKO output is disabled
Bits 1:0 – POSCMD[1:0] Primary Oscillator Configuration bits
Value
Description
11
Primary Oscillator mode is disabled
10
HS Oscillator mode is selected (10 MHz-32 MHz)
01
XT Oscillator mode is selected (1.5 MHz-10 MHz)
00
External Clock mode is selected
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1225
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.7
FWDT Configuration Register
Name:
FWDT
Legend: PO = Program Once bit
Bit
15
Access
Reset
Bit
Access
Reset
7
WINDIS
R/PO
1
14
13
WDTCLK[1:0]
R/PO
R/PO
1
1
12
11
WDTCMX
R/PO
1
10
6
4
FWPSA
R/PO
1
3
2
5
FWDTEN[1:0]
R/PO
R/PO
1
1
R/PO
1
9
8
WDTWIN[1:0]
R/PO
R/PO
1
1
1
WDTPS[3:0]
R/PO
R/PO
1
1
0
R/PO
1
Bits 14:13 – WDTCLK[1:0] Watchdog Timer Clock Select bits (when WDTCMX = 1)
Value
Description
11
Always uses LPRC
10
Uses FRC when WINDIS = 0, system clock is not LPRC and device is not in Sleep; otherwise, uses
LPRC
01
Always uses SOSC
00
Uses peripheral clock when system clock is not LPRC and device is not in Sleep; otherwise, uses
LPRC
Bit 11 – WDTCMX WDT Clock MUX Control bit
Value
Description
1
Enables WDT clock MUX, WDT clock is selected by WDTCLK[1:0]
0
WDT clock is LPRC
Bits 9:8 – WDTWIN[1:0] Watchdog Timer Window Width bits
Value
Description
11
WDT window is 25% of the WDT period
10
WDT window is 37.5% of the WDT period
01
WDT window is 50% of the WDT period
00
WDT window is 75% of the WDT period
Bit 7 – WINDIS Windowed Watchdog Timer Disable bit
Value
Description
1
Windowed WDT is disabled
0
Windowed WDT is enabled
Bits 6:5 – FWDTEN[1:0] Watchdog Timer Enable bits
Value
Description
11
WDT is enabled
10
WDT is disabled (control is placed on the SWDTEN bit)
01
WDT is enabled only while device is active and disabled in Sleep; SWDTEN bit is disabled
00
WDT and SWDTEN are disabled
Bit 4 – FWPSA Watchdog Timer Prescaler bit
Value
Description
1
WDT prescaler ratio of 1:128
0
WDT prescaler ratio of 1:32
Bits 3:0 – WDTPS[3:0] Watchdog Timer Postscale Select bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1226
PIC24FJ512GU410 Family Data Sheet
Special Features
Value
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Description
1:32,768
1:16,384
1:8,192
1:4,096
1:2,048
1:1,024
1:512
1:256
1:128
1:64
1:32
1:16
1:8
1:4
1:2
1:1
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1227
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.8
FPOR Configuration Register
Name:
FPOR
Legend: PO = Program Once bit
Bit
15
14
13
12
11
10
9
7
6
5
4
3
LPBOREN
R/PO
1
2
LPREGEN
R/PO
1
1
8
Access
Reset
Bit
Access
Reset
0
BOREN[1:0]
R/PO
R/PO
1
1
Bit 3 – LPBOREN Low-Power Brown-out Reset Enable bit
Value
Description
1
Low-power BOR is enabled and active when main BOR is inactive
0
Low-power BOR is disabled
Bit 2 – LPREGEN Low-Voltage Regulator Control bit
Value
Description
1
Low-voltage and low-power regulator are not available
0
Low-voltage and low-power regulator are available and controlled by the RETEN bit during Sleep mode
Bits 1:0 – BOREN[1:0] Brown-out Reset Enable bits
Value
Description
11
Brown-out Reset is enabled in hardware; SBOREN bit is disabled
10
Brown-out Reset is enabled only while device is active and is disabled in Sleep; SBOREN bit is
disabled
01
Brown-out Reset is controlled with the SBOREN bit setting
00
Brown-out Reset is disabled in hardware; SBOREN bit is disabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1228
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.9
FICD Configuration Register
Name:
FICD
Legend: PO = Program Once bit; r = Reserved bit
Bit
Access
Reset
Bit
Access
Reset
15
BTSWP
R/PO
1
14
13
12
11
10
9
7
Reserved
r
1
6
5
JTAGEN
R/PO
1
4
3
2
1
8
0
ICS[1:0]
R/PO
1
R/PO
1
Bit 15 – BTSWP BOOTSWP Instruction Enable bit
Value
Description
1
BOOTSWP instruction is disabled
0
BOOTSWP instruction is enabled
Bit 7 – Reserved Maintain as ‘1’
Bit 5 – JTAGEN JTAG Port Enable bit
Value
Description
1
JTAG port is enabled
0
JTAG port is disabled
Bits 1:0 – ICS[1:0] ICD Communication Channel Select bits
Value
Description
11
Communicates on PGC1/PGD1
10
Communicates on PGC2/PGD2
01
Communicates on PGC3/PGD3
00
Reserved; do not use
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1229
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.10 FDMTIVTL Configuration Register
Name:
FDMTIVTL
Legend: PO = Program Once bit
Bit
Access
Reset
Bit
Access
Reset
15
14
13
R/PO
1
R/PO
1
R/PO
1
7
6
5
R/PO
1
R/PO
1
R/PO
1
12
11
DMTIVTL[15:8]
R/PO
R/PO
1
1
4
3
DMTIVTL[7:0]
R/PO
R/PO
1
1
10
9
8
R/PO
1
R/PO
1
R/PO
1
2
1
0
R/PO
1
R/PO
1
R/PO
1
Bits 15:0 – DMTIVTL[15:0] DMT Window Interval Lower 16 bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1230
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.11 FDMTIVTH Configuration Register
Name:
FDMTIVTH
Legend: PO = Program Once bit
Bit
23
22
21
15
14
13
R/PO
1
R/PO
1
R/PO
1
7
6
5
R/PO
1
R/PO
1
R/PO
1
20
19
18
17
16
10
9
8
R/PO
1
R/PO
1
R/PO
1
2
1
0
R/PO
1
R/PO
1
R/PO
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
12
11
DMTIVTH[31:24]
R/PO
R/PO
1
1
4
3
DMTIVTH[23:16]
R/PO
R/PO
1
1
Bits 15:8 – DMTIVTH[31:24] DMT Window Interval Higher 16 bits
Bits 7:0 – DMTIVTH[23:16] DMT Window Interval Higher 16 bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1231
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.12 FDMTCNTL Configuration Register
Name:
FDMTCNTL
Legend: PO = Program Once bit
Bit
23
22
21
15
14
13
R/PO
1
R/PO
1
R/PO
1
7
6
5
R/PO
1
R/PO
1
R/PO
1
20
19
18
17
16
10
9
8
R/PO
1
R/PO
1
R/PO
1
2
1
0
R/PO
1
R/PO
1
R/PO
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
12
11
DMTCNTL[15:8]
R/PO
R/PO
1
1
4
3
DMTCNTL[7:0]
R/PO
R/PO
1
1
Bits 15:0 – DMTCNTL[15:0] DMT Instruction Count Time-out Value Lower 16 bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1232
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.13 FDMTCNTH Configuration Register
Name:
FDMTCNTH
Legend: PO = Program Once bit
Bit
23
22
21
15
14
13
R/PO
1
R/PO
1
R/PO
1
7
6
5
R/PO
1
R/PO
1
R/PO
1
20
19
18
17
16
10
9
8
R/PO
1
R/PO
1
R/PO
1
2
1
0
R/PO
1
R/PO
1
R/PO
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
12
11
DMTCNTH[31:24]
R/PO
R/PO
1
1
4
3
DMTCNTH[23:16]
R/PO
R/PO
1
1
Bits 15:8 – DMTCNTH[31:24] DMT Instruction Count Time-out Value Higher 16 bits
Bits 7:0 – DMTCNTH[23:16] DMT Instruction Count Time-out Value Higher 16 bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1233
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.14 FDMT Configuration Register
Name:
FDMT
Legend: PO = Program Once bit
Bit
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMTDIS
R/PO
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – DMTDIS DMT Disable bit
Value
Description
1
DMT is disabled
0
DMT is enabled
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1234
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.15 FDEVOPT1 Configuration Register
Name:
FDEVOPT1
Note:
1. SMBus mode is enabled by the SMEN bit (I2CxCONL[8]).
Legend: PO = Program Once bit
Bit
23
22
21
20
19
18
17
16
15
14
13
12
11
10
SMB3EN
R/PO
1
9
8
7
6
5
4
ALTI2C1
R/PO
1
3
SOSCHP
R/PO
1
2
TMPRPIN
R/PO
1
1
ALTCMPI
R/PO
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 10 – SMB3EN SMBus 3.0 Levels Enable bit(1)
Value
Description
1
SMBus 3.0 input levels
0
Normal SMBus input levels
Bit 4 – ALTI2C1 Alternate I2C1 bit
Value
Description
1
SDA1 and SCL1 are on RG2 and RG3
0
ASDA1 and ASCL1 are on RB5 and RB4
Bit 3 – SOSCHP SOSC High-Power Enable bit (valid only when SOSCSEL = 1)
Value
Description
1
SOSC High-Power mode is enabled
0
SOSC Low-Power mode is enabled (see 9.7.3 Low-Power Operation for more information)
Bit 2 – TMPRPIN Tamper Pin Enable bit
Value
Description
1
TMPRN pin function is disabled
0
TMPRN pin function is enabled
Bit 1 – ALTCMPI Alternate Comparator Input Enable bit
Value
Description
1
C2INC and C3INC are on RG9 and RD11
0
AC2INC and AC3INC are on RG7
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1235
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.16 FBTSEQ Configuration Register
Name:
FBTSEQ
Legend: PO = Program Once bit
Bit
Access
Reset
Bit
Access
Reset
Bit
23
22
21
R/PO
0
R/PO
0
R/PO
0
15
14
R/PO
0
7
13
IBSEQ[3:0]
R/PO
R/PO
0
0
6
5
20
19
IBSEQ[11:4]
R/PO
R/PO
0
0
12
11
R/PO
0
R/PO
0
4
18
17
16
R/PO
0
R/PO
0
R/PO
0
10
9
BSEQ[11:8]
R/PO
R/PO
0
0
8
R/PO
0
3
2
1
0
R/PO
0
R/PO
0
R/PO
0
R/PO
0
BSEQ[7:0]
Access
Reset
R/PO
0
R/PO
0
R/PO
0
R/PO
0
Bits 23:16 – IBSEQ[11:4] Inverse Boot Sequence Number bits (Dual Partition modes only)
The one’s complement of BSEQ[11:0]; must be calculated by the user and written into device programming.
Bits 15:12 – IBSEQ[3:0] Inverse Boot Sequence Number bits (Dual Partition modes only)
The one’s complement of BSEQ[11:0]; must be calculated by the user and written into device programming.
Bits 11:8 – BSEQ[11:8] Boot Sequence Number bits
Relative value defining which partition will be active after a device Reset; the partition containing a lower boot number
will be active.
Bits 7:0 – BSEQ[7:0] Boot Sequence Number bits
Relative value defining which partition will be active after a device Reset; the partition containing a lower boot number
will be active.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1236
PIC24FJ512GU410 Family Data Sheet
Special Features
29.1.17 FBOOT Configuration Register
Name:
FBOOT
Legend: PO = Program Once bit
Bit
15
14
13
12
11
10
9
7
6
5
4
3
2
1
8
Access
Reset
Bit
Access
Reset
0
BTMODE[1:0]
R/PO
R/PO
0
0
Bits 1:0 – BTMODE[1:0] Device Partition Mode Configuration Status bits
Value
Description
11
Single Partition mode
10
Dual Partition mode
01
Protected Dual Partition mode (Partition 1 is write-protected when inactive)
00
Reserved; do not use
29.2
Device Identification
The PIC24FJ512GU410 devices have two Identification registers near the end of configuration memory space that
store the Device ID (DEVID) and Device Revision (DEVREV). These registers are used to determine the variant and
manufacturing information about the device. These registers are read-only and are shown in 29.2.2 DEVID and
29.2.1 DEVREV.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1237
PIC24FJ512GU410 Family Data Sheet
Special Features
29.2.1
Device Revision Register
Bit
Name:
DEVREV
15
14
13
12
11
10
7
6
5
4
3
2
9
8
Access
Reset
Bit
Access
Reset
R/W
0
1
DEVREV[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 3:0 – DEVREV[3:0] Device Revision bits
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1238
PIC24FJ512GU410 Family Data Sheet
Special Features
29.2.2
DEVID Device ID Register
Name:
DEVID
Note:
1. See Table 29-2 for the list of Device Identifier bits.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
FAMID[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DEV[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – FAMID[7:0] Device Family Identifier bits
(23h = PIC24FJ512GU410 family)
Bits 7:0 – DEV[7:0] Individual Device Identifier bits(1)
29.2.3
Device IDs
Table 29-2. Device IDs
Device
29.3
DEVID
Device
DEVID
PIC24FJ512GL405
2320
PIC24FJ512GU405
2321
PIC24FJ256GL405
2310
PIC24FJ256GU405
2311
PIC24FJ128GL405
2300
PIC24FJ128GU405
2301
PIC24FJ512GL406
2324
PIC24FJ512GU406
2325
PIC24FJ256GL406
2314
PIC24FJ256GU406
2315
PIC24FJ128GL406
2304
PIC24FJ128GU406
2305
PIC24FJ512GL408
2328
PIC24FJ512GU408
2329
PIC24FJ256GL408
2318
PIC24FJ256GU408
2319
PIC24FJ128GL408
2308
PIC24FJ128GU408
2309
PIC24FJ512GL410
232C
PIC24FJ512GU410
232D
PIC24FJ256GL410
231C
PIC24FJ256GU410
231D
PIC24FJ128GL410
230C
PIC24FJ128GU410
230D
Unique Device Identifier (UDID)
All PIC24FJ512GU410 family devices are individually encoded during final manufacturing with a Unique Device
Identifier or UDID. The UDID cannot be erased by a bulk erase command or any other user-accessible means. This
feature allows for manufacturing traceability of Microchip Technology devices in applications where this is a
requirement. It may also be used by the application manufacturer for any number of things that may require unique
identification, such as:
•
•
Tracking the device
Unique serial number
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1239
PIC24FJ512GU410 Family Data Sheet
Special Features
•
Unique security key
The UDID comprises five 24-bit program words. When taken together, these fields form a unique 120-bit identifier.
The UDID is stored in five read-only locations, located between 0x801600 and 0x801608 in the device Configuration
space. Table 29-3 lists the addresses of the Identifier Words and shows their contents.
Table 29-3. UDID Addresses
UDID
29.4
Address
Description
UDID1
0x80 1600
UDID Word 1
UDID2
0x80 1602
UDID Word 2
UDID3
0x80 1604
UDID Word 3
UDID4
0x80 1606
UDID Word 4
UDID5
0x80 1608
UDID Word 5
On-Chip Voltage Regulator
All PIC24FJ512GU410 family devices power their core digital logic at a nominal 1.8V. This may create an issue for
designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in
the PIC24FJ512GU410 family incorporate an on-chip regulator that allows the device to run its core logic from VDD.
This regulator is always enabled. It provides a constant voltage (1.8V nominal) to the digital core logic, from a VDD of
2.0V, all the way up to the device’s VDDMAX. It does not have the capability to boost VDD levels. In order to prevent
“brown-out” conditions when the voltage drops too low for the regulator, the Brown-out Reset occurs. Then, the
regulator output follows VDD with a typical voltage drop of 200 mV.
A low-ESR capacitor (such as ceramic) must be connected to the VCAP pin (Figure 29-1). This helps to maintain the
stability of the regulator. The recommended value for the Filter Capacitor (CEFC) is provided in 32. Electrical
Characteristics.
Figure 29-1. Connections for the On-Chip Regulator
Note:
1. This is a typical operating voltage. Refer to 32. Electrical Characteristics for the full operating ranges of VDD.
29.4.1
On-Chip Regulator and POR
The voltage regulator takes approximately 10 μs for it to generate output. During this time, designated as TVREG,
code execution is disabled. TVREG is applied every time the device resumes operation after any power-down,
including Sleep mode. TVREG is determined by the status of the VREGS bit (RCON[8]) and the WDTWIN[1:0]
Configuration bits (FWDT[9:8]).
29.4.2
Voltage Regulator Standby Mode
The on-chip regulator always consumes a small incremental amount of current over IDD/IPD, including when the
device is in Sleep mode, even though the core digital logic does not require power. To provide additional savings in
applications where power resources are critical, the regulator can be made to enter Standby mode, on its own,
whenever the device goes into Sleep mode. This feature is controlled by the VREGS bit (RCON[8]). Clearing the
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1240
PIC24FJ512GU410 Family Data Sheet
Special Features
VREGS bit enables the Standby mode. When waking up from Standby mode, the regulator needs to wait for TVREG to
expire before wake-up.
29.4.3
Low-Voltage Regulator
When in Sleep mode, PIC24FJ512GU410 family devices may use a separate low-power, low-voltage regulator to
power critical circuits. This regulator, which operates from 0.9V to 1.2V, maintains power to data RAM and the RTCC
while all other core digital logic is powered down. The low-voltage regulator is described in more detail in 10.2.4 LowVoltage Regulator Mode and Band Gap Power.
29.5
Watchdog Timer (WDT)
For PIC24FJ512GU410 family devices, the WDT is driven by the LPRC Oscillator, the Secondary Oscillator (SOSC)
or the system timer. When the device is in Sleep mode, the LPRC Oscillator will be used. When the WDT is enabled,
the clock source is also enabled.
The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler that can be configured for either 5-bit
(divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 32 kHz
input, the prescaler yields a nominal WDT Time-out (TWDT) period of 1 ms in 5-bit mode or 4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The
postscaler is controlled by the WDTPS[3:0] Configuration bits (FWDT[3:0]), which allows the selection of a total of 16
settings, from 1:1 to 1:32,768. Using the prescaler and postscaler time-out periods, ranges from 1 ms to 131 seconds
can be achieved.
The WDT, prescaler and postscaler are reset:
•
•
•
On any device Reset
On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the
NOSCx bits) or by hardware (i.e., Fail-Safe Clock Monitor)
When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered)
•
•
When the device exits Sleep or Idle mode to resume normal operation
By a CLRWDT instruction during normal execution
If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device
will wake-up and code execution will continue from where the PWRSAV instruction was executed. The corresponding
SLEEP or IDLE (RCON[3:2]) bits will need to be cleared in software after the device wakes up.
The WDT Flag bit, WDTO (RCON[4]), is not automatically cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed.
29.5.1
Windowed Operation
The Watchdog Timer has an optional Fixed Window mode of operation. In this Windowed mode, CLRWDT instructions
can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction executed before
that window causes a WDT Reset, similar to a WDT time-out.
Windowed WDT mode is enabled by programming the WINDIS Configuration bit (FWDT[7]) to ‘0’.
29.5.2
Control Register
The WDT is enabled or disabled by the FWDTEN[1:0] Configuration bits (FWDT[6:5]). When the Configuration bits,
FWDTEN[1:0] = 11, the WDT is always enabled.
The WDT can be optionally controlled in software when the Configuration bits, FWDTEN[1:0] = 10. When
FWDTEN[1:0] = 00, the Watchdog Timer is always disabled. The WDT is enabled in software by setting the
SWDTEN control bit (RCON[5]). The SWDTEN control bit is cleared on any device Reset. The software WDT option
allows the user to enable the WDT for critical code segments and disable the WDT during non-critical code segments
for maximum power savings.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1241
PIC24FJ512GU410 Family Data Sheet
Special Features
Figure 29-2. WDT Block Diagram
SWDTEN
FWDTEN[1:0]
Wake from
Sleep
LPRC Control
WDTPS[3:0]
FWPSA
WDTCLK[1:0]
32 kHz
SOSC
Prescaler
(5-bit/7-bit)
WDT
Counter
Postscaler
1:1 to 1:32.768
WDT Overflow
Reset
1 ms/4 ms
FRC
Peripheral Clock
All Device Resets
Transition to New
Clock Source
LPRC
Exit Sleep or
Idle Mode
WINDIS
System Clock (LRPC)
CLRWDT Instr.
PWRSAV Instr.
Sleep or Idle Mode
29.6
Program Verification and Code Protection
PIC24FJ512GU410 family devices offer basic implementation of CodeGuard™ Security that supports General
Segment (GS) security and Boot Segment (BS) security. This feature helps protect individual intellectual property.
Note: For more information on usage, configuration and operation, refer to “CodeGuard™ Intermediate Security”
(DS70005182) in the “dsPIC33/PIC24 Family Reference Manual”.
29.7
JTAG Interface
PIC24FJ512GU410 family devices implement a JTAG interface, which supports boundary scan device testing.
29.8
In-Circuit Serial Programming™ (ICSP)™
PIC24FJ512GU410 family microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock (PGECx) and data (PGEDx), and three other lines for power (VDD), ground (VSS)
and MCLR. This allows customers to manufacture boards with unprogrammed devices and then program the
microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be
programmed.
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
Special Features
29.9
Customer OTP Memory
PIC24FJ512GU410 family devices provide 256 bytes of One-Time-Programmable (OTP) memory, located at
addresses, 801700h through 8017FEh. This memory can be used for persistent storage of application-specific
information that will not be erased by reprogramming the device. This includes many types of information, such as
(but not limited to):
•
•
•
•
•
•
Application checksums
Code revision information
Product information
Serial numbers
System manufacturing dates
Manufacturing lot numbers
Customer OTP memory may be programmed in any mode, including user RTSP mode, but it cannot be erased. Data
are not cleared by a chip erase.
Note: Do not write the OTP memory more than once. Writing to the OTP memory more than once may result in an
ECC Double-Bit Error (ECCDBE).
29.10
In-Circuit Debugger
®
This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pins.
To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD,
VSS and the PGECx/PGEDx pin pair, designated by the ICS[1:0] Configuration bits. In addition, when the feature is
enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data
RAM and two I/O pins.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1243
PIC24FJ512GU410 Family Data Sheet
Development Support
30.
Development Support
Move a design from concept to production in record time with Microchip’s award-winning development tools.
Microchip tools work together to provide state of the art debugging for any project with easy-to-use Graphical User
®
Interfaces (GUIs) in our free MPLAB X and Atmel Studio Integrated Development Environments (IDEs), and our
code generation tools. Providing the ultimate ease-of-use experience, Microchip’s line of programmers, debuggers
and emulators work seamlessly with our software tools. Microchip development boards help evaluate the best silicon
device for an application, while our line of third party tools round out our comprehensive development tool solutions.
Microchip’s MPLAB X and Atmel Studio ecosystems provide a variety of embedded design tools to consider, which
®
®
®
support multiple devices, such as PIC MCUs, AVR MCUs, SAM MCUs and dsPIC DSCs. MPLAB X tools are
®
®
®
compatible with Windows , Linux and Mac operating systems while Atmel Studio tools are compatible with
Windows.
Go to the following website for more information and details:
https://www.microchip.com/development-tools/
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
Instruction Set Summary
31.
Instruction Set Summary
Note: This chapter is a brief summary of the PIC24F Instruction Set Architecture (ISA) and is not intended to be a
comprehensive reference source.
®
The PIC24F instruction set adds many enhancements to the previous PIC MCU instruction sets, while maintaining
an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word.
Only three instructions require two program memory locations.
Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one
or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is
grouped into four basic categories:
•
•
•
•
Word or byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
Table 31-1 shows the general symbols used in describing the instructions. The PIC24F instruction set summary in
Table 31-2 lists all the instructions, along with the status flags affected by each instruction.
Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands:
•
•
•
The first source operand, which is typically a register, ‘Wb’, without any address modifier
The second source operand, which is typically a register, ‘Ws’, with or without an address modifier
The destination of the result, which is typically a register, ‘Wd’, with or without an address modifier
However, word or byte-oriented file register instructions have two operands:
•
•
The file register specified by the value, ‘f’
The destination, which could either be the file register, ‘f’, or the W0 register, which is denoted as ‘WREG’
Most bit-oriented instructions (including simple rotate/shift instructions) have two operands:
•
•
The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’)
The bit in the W register or file register (specified by a literal value or indirectly by the contents of register, ‘Wb’)
The literal instructions that involve data movement may use some of the following operands:
•
•
A literal value to be loaded into a W register or file register (specified by the value of ‘k’)
The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or logical operations use some of the following operands:
•
•
•
The first source operand, which is a register, ‘Wb’, without any address modifier
The second source operand, which is a literal value
The destination of the result (only if not the same as the first source operand), which is typically a register, ‘Wd’,
with or without an address modifier
The control instructions may use some of the following operands:
•
•
A program memory address
The mode of the Table Read and Table Write instructions
All instructions are a single word, except for certain double-word instructions, which were made double-word
instructions so that all the required information is available in these 48 bits. In the second word, the eight MSbs are
‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP.
Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the
Program Counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles,
with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed
branch), indirect CALL/GOTO, all Table Reads and Table Writes, and RETURN/RETFIE instructions, which are singleword instructions but take two or three cycles.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1245
PIC24FJ512GU410 Family Data Sheet
Instruction Set Summary
Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip
is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover,
double-word moves require two cycles. The double-word instructions execute in two instruction cycles.
Table 31-1. Symbols Used In Opcode Descriptions
Field
Description
#text
Means literal defined by “text”
(text)
Means “content of text”
[text]
Means “the location addressed by text”
{}
Optional field or operation
[n:m]
Register bit field
.b
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
bit4
4-bit Bit Selection field (used in word-addressed instructions) ∈ {0...15}
C, DC, N, OV, Z
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
Absolute address, label or expression (resolved by the linker)
f
File register address ∈ {0000h...1FFFh}
lit1
1-bit unsigned literal ∈ {0,1}
lit4
4-bit unsigned literal ∈ {0...15}
lit5
5-bit unsigned literal ∈ {0...31}
lit8
8-bit unsigned literal ∈ {0...255}
lit10
10-bit unsigned literal ∈ {0...255} for Byte mode, {0...1023} for Word mode
lit14
14-bit unsigned literal ∈ {0...16383}
lit16
16-bit unsigned literal ∈ {0...65535}
lit23
23-bit unsigned literal ∈ {0...8388607}; LSb must be ‘0’
None
Field does not require an entry, may be blank
PC
Program Counter
Slit10
10-bit signed literal ∈ {-512...511}
Slit16
16-bit signed literal ∈ {-32768...32767}
Slit6
6-bit signed literal ∈ {-16...16}
Wb
Base W register ∈ {W0..W15}
Wd
Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register ∈
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor Working register pair (direct addressing)
Wn
One of 16 Working registers ∈ {W0..W15}
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
Instruction Set Summary
...........continued
Field
Description
Wnd
One of 16 destination Working registers ∈ {W0..W15}
Wns
One of 16 source Working registers ∈ {W0..W15}
WREG
W0 (Working register used in file register instructions)
Ws
Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register ∈ { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Table 31-2. Instruction Set Overview
Assembly
Mnemonic
ADD
ADDC
AND
ASR
BCLR
Assembly Syntax
Description
# of
Words
# of Cycles
Status Flags
Affected
ADD
f
f = f + WREG
1
1
C, DC, N, OV, Z
ADD
f,WREG
WREG = f + WREG
1
1
C, DC, N, OV, Z
ADD
#lit10,Wn
Wd = lit10 + Wd
1
1
C, DC, N, OV, Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
1
C, DC, N, OV, Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
1
C, DC, N, OV, Z
ADDC
f
f = f + WREG + (C)
1
1
C, DC, N, OV, Z
ADDC
f,WREG
WREG = f + WREG + (C)
1
1
C, DC, N, OV, Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
1
1
C, DC, N, OV, Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
1
C, DC, N, OV, Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
1
C, DC, N, OV, Z
AND
f
f = f .AND. WREG
1
1
N, Z
AND
f,WREG
WREG = f .AND. WREG
1
1
N, Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
1
1
N, Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
1
1
N, Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
1
1
N, Z
ASR
f
f = Arithmetic Right Shift f
1
1
C, N, OV, Z
ASR
f,WREG
WREG = Arithmetic Right
Shift f
1
1
C, N, OV, Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift
Ws
1
1
C, N, OV, Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift
Wb by Wns
1
1
N, Z
ASR
Wb,#lit5,Wnd Wnd = Arithmetic Right Shift
Wb by lit5
1
1
N, Z
BCLR
f,#bit4
Bit Clear f
1
1
None
BCLR
Ws,#bit4
Bit Clear Ws
1
1
None
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
Instruction Set Summary
...........continued
Assembly
Mnemonic
BRA
BSET
BSW
BTG
BTSC
BTSS
Assembly Syntax
Description
# of
Words
# of Cycles
Status Flags
Affected
BRA
C,Expr
Branch if Carry
1
1 (2)
None
BRA
GE,Expr
Branch if Greater Than or
Equal
1
1 (2)
None
BRA
GEU,Expr
Branch if Unsigned Greater
Than or Equal
1
1 (2)
None
BRA
GT,Expr
Branch if Greater Than
1
1 (2)
None
BRA
GTU,Expr
Branch if Unsigned Greater
Than
1
1 (2)
None
BRA
LE,Expr
Branch if Less Than or Equal
1
1 (2)
None
BRA
LEU,Expr
Branch if Unsigned Less
Than or Equal
1
1 (2)
None
BRA
LT,Expr
Branch if Less Than
1
1 (2)
None
BRA
LTU,Expr
Branch if Unsigned Less
Than
1
1 (2)
None
BRA
N,Expr
Branch if Negative
1
1 (2)
None
BRA
NC,Expr
Branch if Not Carry
1
1 (2)
None
BRA
NN,Expr
Branch if Not Negative
1
1 (2)
None
BRA
NOV,Expr
Branch if Not Overflow
1
1 (2)
None
BRA
NZ,Expr
Branch if Not Zero
1
1 (2)
None
BRA
OV,Expr
Branch if Overflow
1
1 (2)
None
BRA
Expr
Branch Unconditionally
1
2
None
BRA
Z,Expr
Branch if Zero
1
1 (2)
None
BRA
Wn
Computed Branch
1
2
None
BSET
f,#bit4
Bit Set f
1
1
None
BSET
Ws,#bit4
Bit Set Ws
1
1
None
BSW.C
Ws,Wb
Write C bit to Ws[Wb]
1
1
None
BSW.Z
Ws,Wb
Write Z bit to Ws[Wb]
1
1
None
BTG
f,#bit4
Bit Toggle f
1
1
None
BTG
Ws,#bit4
Bit Toggle Ws
1
1
None
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
1
(2 or 3)
None
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
(2 or 3)
None
BTSS
f,#bit4
Bit Test f, Skip if Set
1
1
(2 or 3)
None
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
(2 or 3)
None
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
Instruction Set Summary
...........continued
Assembly
Mnemonic
BTST
BTSTS
CALL
CLR
Assembly Syntax
Description
# of
Words
# of Cycles
Status Flags
Affected
BTST
f,#bit4
Bit Test f
1
1
Z
BTST.C
Ws,#bit4
Bit Test Ws to C
1
1
C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
1
1
Z
BTST.C
Ws,Wb
Bit Test Ws[Wb] to C
1
1
C
BTST.Z
Ws,Wb
Bit Test Ws[Wb] to Z
1
1
Z
BTSTS
f,#bit4
Bit Test, then Set f
1
1
Z
BTSTS.C Ws,#bit4
Bit Test Ws to C, then Set
1
1
C
BTSTS.Z Ws,#bit4
Bit Test Ws to Z, then Set
1
1
Z
CALL
lit23
Call Subroutine
2
2
None
CALL
Wn
Call Indirect Subroutine
1
2
None
CLR
f
f = 0x0000
1
1
None
CLR
WREG
WREG = 0x0000
1
1
None
CLR
Ws
Ws = 0x0000
1
1
None
Clear Watchdog Timer
1
1
WDTO, Sleep
CLRWDT
CLRWDT
COM
COM
f
f=f
1
1
N, Z
COM
f,WREG
WREG = f
1
1
N, Z
COM
Ws,Wd
Wd = Ws
1
1
N, Z
CP
f
Compare f with WREG
1
1
C, DC, N, OV, Z
CP
Wb,#lit5
Compare Wb with lit5
1
1
C, DC, N, OV, Z
CP
Wb,Ws
Compare Wb with Ws (Wb –
Ws)
1
1
C, DC, N, OV, Z
CP0
f
Compare f with 0x0000
1
1
C, DC, N, OV, Z
CP0
Ws
Compare Ws with 0x0000
1
1
C, DC, N, OV, Z
CPB
f
Compare f with WREG, with
Borrow
1
1
C, DC, N, OV, Z
CPB
Wb,#lit5
Compare Wb with lit5, with
Borrow
1
1
C, DC, N, OV, Z
CPB
Wb,Ws
Compare Wb with Ws, with
Borrow
(Wb – Ws – C)
1
1
C, DC, N, OV, Z
CPSEQ
CPSEQ
Wb,Wn
Compare Wb with Wn, Skip
if =
1
1
(2 or 3)
None
CPSGT
CPSGT
Wb,Wn
Compare Wb with Wn, Skip
if >
1
1
(2 or 3)
None
CPSLT
CPSLT
Wb,Wn
Compare Wb with Wn, Skip
if <
1
1
(2 or 3)
None
CP
CP0
CPB
© 2019-2020 Microchip Technology Inc.
Datasheet
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PIC24FJ512GU410 Family Data Sheet
Instruction Set Summary
...........continued
Assembly
Mnemonic
Assembly Syntax
Description
# of
Words
# of Cycles
Status Flags
Affected
CPSNE
CPSNE
Wb,Wn
Compare Wb with Wn, Skip
if ≠
1
1
(2 or 3)
None
DAW
DAW.B
Wn
Wn = Decimal Adjust Wn
1
1
C
DEC
DEC
f
f=f–1
1
1
C, DC, N, OV, Z
DEC
f,WREG
WREG = f – 1
1
1
C, DC, N, OV, Z
DEC
Ws,Wd
Wd = Ws – 1
1
1
C, DC, N, OV, Z
DEC2
f
f=f–2
1
1
C, DC, N, OV, Z
DEC2
f,WREG
WREG = f – 2
1
1
C, DC, N, OV, Z
DEC2
Ws,Wd
Wd = Ws – 2
1
1
C, DC, N, OV, Z
DISI
DISI
#lit14
Disable Interrupts for k
Instruction Cycles
1
1
None
DIV
DIV.SW
Wm,Wn
Signed 16/16-bit Integer
Divide
1
18
N, Z, C, OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer
Divide
1
18
N, Z, C, OV
DIV.UW
Wm,Wn
Unsigned 16/16-bit Integer
Divide
1
18
N, Z, C, OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer
Divide
1
18
N, Z, C, OV
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
None
FF1L
FF1L
Ws,Wnd
Find First One from Left
(MSb) Side
1
1
C
FF1R
FF1R
Ws,Wnd
Find First One from Right
(LSb) Side
1
1
C
GOTO
GOTO
Expr
Go to Address
2
2
None
GOTO
Wn
Go to Indirect
1
2
None
INC
f
f=f+1
1
1
C, DC, N, OV, Z
INC
f,WREG
WREG = f + 1
1
1
C, DC, N, OV, Z
INC
Ws,Wd
Wd = Ws + 1
1
1
C, DC, N, OV, Z
INC2
f
f=f+2
1
1
C, DC, N, OV, Z
INC2
f,WREG
WREG = f + 2
1
1
C, DC, N, OV, Z
INC2
Ws,Wd
Wd = Ws + 2
1
1
C, DC, N, OV, Z
IOR
f
f = f .IOR. WREG
1
1
N, Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N, Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N, Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N, Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N, Z
DEC2
INC
INC2
IOR
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1250
PIC24FJ512GU410 Family Data Sheet
Instruction Set Summary
...........continued
Assembly
Mnemonic
Assembly Syntax
Description
# of
Words
# of Cycles
Status Flags
Affected
LNK
LNK
#lit14
Link Frame Pointer
1
1
None
LSR
LSR
f
f = Logical Right Shift f
1
1
C, N, OV, Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C, N, OV, Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C, N, OV, Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift
Wb by Wns
1
1
N, Z
LSR
Wb,#lit5,Wnd Wnd = Logical Right Shift
Wb by lit5
1
1
N, Z
MOV
f,Wn
1
1
None
MOV
[Wns
Move [Wns + Slit10] to Wnd
+Slit10],Wnd
1
1
None
MOV
f
Move f to f
1
1
N, Z
MOV
f,WREG
Move f to WREG
1
1
N, Z
MOV
#lit16,Wn
Move 16-Bit Literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-Bit Literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wns,[Wns
+Slit10]
Move Wns to [Wns + Slit10]
1
1
None
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
N, Z
MOV.D
Wns,Wd
Move Double from
W(ns):W(ns + 1) to Wd
1
2
None
MOV.D
Ws,Wnd
Move Double from Ws to
W(nd + 1):W(nd)
1
2
None
MUL.SS
Wb,Ws,Wnd
{Wnd + 1, Wnd} =
Signed(Wb) * Signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd + 1, Wnd} =
Signed(Wb) * Unsigned(Ws)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd + 1, Wnd} =
Unsigned(Wb) * Signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd + 1, Wnd} =
Unsigned(Wb) *
Unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd {Wnd + 1, Wnd} =
Signed(Wb) * Unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd {Wnd + 1, Wnd} =
Unsigned(Wb) *
Unsigned(lit5)
1
1
None
MUL
f
1
1
None
MOV
MUL
© 2019-2020 Microchip Technology Inc.
Move f to Wn
W3:W2 = f * WREG
Datasheet
DS30010203C-page 1251
PIC24FJ512GU410 Family Data Sheet
Instruction Set Summary
...........continued
Assembly
Mnemonic
NEG
NOP
POP
Assembly Syntax
# of
Words
# of Cycles
Status Flags
Affected
NEG
f
f=f+1
1
1
C, DC, N, OV, Z
NEG
f,WREG
WREG = f + 1
1
1
C, DC, N, OV, Z
NEG
Ws,Wd
Wd = Ws + 1
1
1
C, DC, N, OV, Z
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
POP
f
Pop f from Top-of-Stack
(TOS)
1
1
None
POP
Wdo
Pop from Top-of-Stack (TOS)
to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS)
to W(nd):W(nd + 1)
1
2
None
Pop Shadow Registers
1
1
All
POP.S
PUSH
Description
PUSH
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack
(TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns + 1) to
Top-of-Stack (TOS)
1
2
None
Push Shadow Registers
1
1
None
PUSH.S
PWRSAV
PWRSAV
#lit1
Go into Sleep or Idle mode
1
1
WDTO, Sleep
RCALL
RCALL
Expr
Relative Call
1
2
None
RCALL
Wn
Computed Call
1
2
None
REPEAT
#lit14
Repeat Next Instruction lit14
+ 1 times
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn)
+ 1 times
1
1
None
REPEAT
RESET
RESET
Software Device Reset
1
1
None
RETFIE
RETFIE
Return from Interrupt
1
3 (2)
None
RETLW
RETLW
Return with Literal in Wn
1
3 (2)
None
RETURN
RETURN
Return from Subroutine
1
3 (2)
None
RLC
RLC
f
f = Rotate Left through Carry
f
1
1
C, N, Z
RLC
f,WREG
WREG = Rotate Left through
Carry f
1
1
C, N, Z
RLC
Ws,Wd
Wd = Rotate Left through
Carry Ws
1
1
C, N, Z
#lit10,Wn
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1252
PIC24FJ512GU410 Family Data Sheet
Instruction Set Summary
...........continued
Assembly
Mnemonic
RLNC
Assembly Syntax
Description
# of
Words
# of Cycles
Status Flags
Affected
RLNC
f
f = Rotate Left (No Carry) f
1
1
N, Z
RLNC
f,WREG
WREG = Rotate Left (No
Carry) f
1
1
N, Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry)
Ws
1
1
N, Z
RRC
f
f = Rotate Right through
Carry f
1
1
C, N, Z
RRC
f,WREG
WREG = Rotate Right
through Carry f
1
1
C, N, Z
RRC
Ws,Wd
Wd = Rotate Right through
Carry Ws
1
1
C, N, Z
RRNC
f
f = Rotate Right (No Carry) f
1
1
N, Z
RRNC
f,WREG
WREG = Rotate Right (No
Carry) f
1
1
N, Z
RRNC
Ws,Wd
Wd = Rotate Right (No
Carry) Ws
1
1
N, Z
SE
SE
Ws,Wnd
Wnd = Sign-Extended Ws
1
1
C, N, Z
SETM
SETM
f
f = FFFFh
1
1
None
SETM
WREG
WREG = FFFFh
1
1
None
SETM
Ws
Ws = FFFFh
1
1
None
SL
f
f = Left Shift f
1
1
C, N, OV, Z
SL
f,WREG
WREG = Left Shift f
1
1
C, N, OV, Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C, N, OV, Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N, Z
SL
Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5
1
1
N, Z
SUB
f
f = f – WREG
1
1
C, DC, N, OV, Z
SUB
f,WREG
WREG = f – WREG
1
1
C, DC, N, OV, Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C, DC, N, OV, Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C, DC, N, OV, Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C, DC, N, OV, Z
SUBB
f
f = f – WREG – (C)
1
1
C, DC, N, OV, Z
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C, DC, N, OV, Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C, DC, N, OV, Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C, DC, N, OV, Z
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
C, DC, N, OV, Z
RRC
RRNC
SL
SUB
SUBB
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1253
PIC24FJ512GU410 Family Data Sheet
Instruction Set Summary
...........continued
Assembly
Mnemonic
SUBR
Assembly Syntax
Description
# of
Words
# of Cycles
Status Flags
Affected
SUBR
f
f = WREG – f
1
1
C, DC, N, OV, Z
SUBR
f,WREG
WREG = WREG – f
1
1
C, DC, N, OV, Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C, DC, N, OV, Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
C, DC, N, OV, Z
SUBBR
f
f = WREG – f – (C)
1
1
C, DC, N, OV, Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C, DC, N, OV, Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C, DC, N, OV, Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
C, DC, N, OV, Z
SWAP.b
Wn
Wn = Nibble Swap Wn
1
1
None
SWAP
Wn
Wn = Byte Swap Wn
1
1
None
TBLRDH
TBLRDH
Ws,Wd
Read Prog[23:16] to Wd[7:0]
1
2
None
TBLRDL
TBLRDL
Ws,Wd
Read Prog[15:0] to Wd
1
2
None
TBLWTH
TBLWTH
Ws,Wd
Write Ws[7:0] to Prog[23:16]
1
2
None
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog[15:0]
1
2
None
ULNK
ULNK
Unlink Frame Pointer
1
1
None
XOR
XOR
f
f = f .XOR. WREG
1
1
N, Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N, Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N, Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N, Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N, Z
ZE
Ws,Wnd
Wnd = Zero-Extend Ws
1
1
C, Z, N
SUBBR
SWAP
ZE
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1254
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
32.
Electrical Characteristics
This section provides an overview of the PIC24FJ512GU410 family electrical characteristics. Additional information
will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24FJ512GU410 family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
32.1
Absolute Maximum Ratings(1)
Parameter
Rating
Ambient temperature under bias
-40°C to +125°C
Storage temperature
-65°C to +150°C
Voltage on VDD with respect to VSS
-0.3V to +4.0V
Voltage on any general purpose digital/analog pin (not 5.5V tolerant) with respect to VSS -0.3V to (VDD + 0.3V)
Voltage on any general purpose digital/ analog pin (5.5V tolerant, including MCLR) with respect to VSS:
When VDD = 0V:
-0.3V to +4.0V
When VDD ≥ 2.0V:
-0.3V to +6.0V
Voltage on AVDD with respect to VSS
(VDD – 0.3V) to (lesser of:
4.0V or (VDD + 0.3V))
Voltage on AVSS with respect to VSS
-0.3V to +0.3V
Maximum current out of VSS pin
300 mA
Maximum current into VDD pin(2)
250 mA
Maximum output current sunk by any I/O pin
25 mA
Maximum output current sourced by any I/O pin
25 mA
Maximum current sunk by all ports
200 mA
Maximum current sourced by all ports(2)
200 mA
Notes:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those, or any other conditions above those
indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
2. Maximum allowable current is a function of device maximum power dissipation (see Table 32-1).
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1255
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
32.2
DC Characteristics
Figure 32-1. PIC24FJ512GU410 Family Voltage-Frequency Graph (Industrial)
Note:
1. Lower operating boundary is 2.0V or VBOR (when BOR is enabled), whichever is lower. For best analog
performance, operate above 2.2V.
Table 32-1. Thermal Operating Conditions
Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
TJ
-40
—
+135
°C
Operating Ambient Temperature Range
TA
-40
—
+125
°C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – Σ IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/ΘJA
W
PIC24FJ128GU410:
I/O Pin Power Dissipation:
PI/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL)
Maximum Allowed Power Dissipation
Table 32-2. Package Thermal Resistance
Characteristic(1)
Symbol
Typ
Unit
48-Pin UQFN
ΘJA
28.3
°C/W
48-Pin TQFP
ΘJA
71.0
°C/W
64-Pin QFN
ΘJA
23.0
°C/W
64-Pin TQFP
ΘJA
68.9
°C/W
80-Pin TQFP
ΘJA
52.0
°C/W
100-Pin TQFP
ΘJA
44.7
°C/W
Note:
1. Junction to ambient thermal resistance; Theta-JA (θJA) numbers are achieved by package simulations.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1256
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-3. Temperature and Voltage Specifications
Operating Conditions (unless otherwise stated):
2.0V ≤ VDD ≤ 3.6V
-40° ≤ TA ≤ +85°C
Param No.
Symbol
Characteristic
Min
Typ
Max
Units
DC10
VDD
Supply Voltage
2.0
—
3.6
V
DC16
VPOR(1)
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
VSS
—
—
V
DC17A
SVDD(1,3)
Recommended
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
1V/20 ms
—
1V/10 µS
sec
DC17B
VBOR(2)
Brown-out Reset
Voltage on VDD
Transition, High-to-Low
2.0
2.1
2.2
V
Notes:
1. If the VPOR or SVDD parameters are not met, or the application experiences slow power-down VDD ramp rates,
it is recommended to enable and use BOR.
2. On a rising VDD power-up sequence, application firmware execution begins at the higher of the VPORREL or
VBOR level (when BOREN = 1).
3.
VDD rise times outside this window may not internally reset the processor and are not parametrically tested.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1257
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-4. Operating Current (IDD)
Operating Conditions (unless otherwise stated):
-40° ≤ TA ≤ +125°C
Param No.
DC19
DC20
DC23
DC24
DC31
DC32
Typ
Max
Units
VDD
225
400
μA
2.0V
230
400
μA
3.3V
410
625
μA
2.0V
415
625
μA
3.3V
1.5
2.5
mA
2.0V
1.6
2.5
mA
3.3V
6.4
9
mA
2.0V
6.5
9
mA
3.3V
70
350
μA
2.0V
80
350
μA
3.3V
1.55
2.5
mA
2.0V
1.6
2.5
mA
3.3V
Conditions(2)
0.5 MIPS,
FOSC = 1 MHz
1 MIPS,
FOSC = 2 MHz
4 MIPS,
FOSC = 8 MHz
16 MIPS,
FOSC = 32 MHz
LPRC (16 KIPS),
FOSC = 32 kHz
FRC (4 MIPS),
FOSC = 8 MHz
Notes:
1. Data in the “Typ” column are at +25°C. Typical parameters are for design guidance only and are not tested.
2. Base IDD current is measured with:
• Oscillator is configured in EC mode without PLL (FNOSC[2:0] (FOSCSEL[2:0]) = 010, PLLMODE[3:0]
(FOSCSEL[6:3]) = 1111 and POSCMOD[1:0] (FOSC[1:0]) = 00)
•
•
OSC1 pin is driven with external square wave with levels from 0.3V to VDD – 0.3V
OSC2 is configured as an I/O in the Configuration Words (OSCIOFCN (FOSC[2]) = 0)
•
FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 11)
•
Secondary Oscillator circuit is disabled (SOSCSEL (FOSC[3]) = 0)
•
Main and low-power BOR circuits are disabled (BOREN[1:0] (FPOR[1:0]) = 00 and LPBOREN
(FPOR[3]) = 0)
•
Watchdog Timer is disabled (FWDTEN[1:0] (FWDT[6:5]) = 00)
•
•
•
All I/O pins (except OSC1) are configured as outputs and driving low
No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
JTAG is disabled (JTAGEN (FICD[5]) = 0)
•
NOP instructions are executed
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1258
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-5. Idle Current (IIDLE)
Operating Conditions (unless otherwise stated):
-40° ≤ TA ≤ +125°C
Param No.
DC40
DC43
DC47
DC50
DC51
Typ
Max
Units
VDD
150
350
µA
2.0V
160
350
µA
3.3V
500
850
µA
2.0V
520
850
µA
3.3V
2.1
3.5
mA
2.0V
2.2
3.5
mA
3.3V
530
800
µA
2.0V
530
800
µA
3.0V
60
300
µA
2.0V
70
300
µA
3.3V
Conditions(2)
1 MIPS, FOSC = 2 MHz
4 MIPS, FOSC = 8 MHz
16 MIPS, FOSC = 32 MHz
FRC (4 MIPS), FOSC = 8 MHz
LPRC (16 KIPS), FOSC = 32 kHz
Notes:
1. Data in the “Typ” column are at +25°C. Parameters are for design guidance only and are not tested.
2. Base IIDLE current is measured with:
•
Oscillator is configured in EC mode without PLL (FNOSC[2:0] (FOSCSEL[2:0]) = 010, PLLMODE[3:0]
(FOSCSEL[6:3]) = 1111 and POSCMOD[1:0] (FOSC[1:0]) = 00)
•
•
OSC1 pin is driven with external square wave with levels from 0.3V to VDD – 0.3V
OSC2 is configured as an I/O in Configuration Words (OSCIOFCN (FOSC[2]) = 0)
•
FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 11)
•
Secondary Oscillator circuit is disabled (SOSCSEL (FOSC[3]) = 0)
•
Main and low-power BOR circuits are disabled (BOREN[1:0] (FPOR[1:0]) = 00 and LPBOREN
(FPOR[3]) = 0)
•
Watchdog Timer is disabled (FWDTEN[1:0] (FWDT[6:5]) = 00)
•
•
•
All I/O pins (except OSC1) are configured as outputs and driving low
No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
JTAG is disabled (JTAGEN (FICD[5]) = 0)
•
pwrsav #1 (IDLE) instruction is executed
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1259
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-6. Power-Down Current (IPD)
Param
No.
DC60
DC61
Typ Max Units
Operating
Temperature
5
15
μA
-40°C
5
15
μA
+25°C
12
25
μA
+85°C
60
150
μA
+125°C
6
15
μA
-40°C
6
15
μA
+25°C
15
25
μA
+85°C
70
150
μA
+125°C
425
—
nA
-40°C
625
—
nA
+25°C
10
—
μA
+85°C
40
—
μA
+125°C
450
—
nA
-40°C
650
—
nA
+25°C
12
—
μA
+85°C
45
—
μA
+125°C
Conditions(2)
VDD
2.0V Sleep with main voltage regulator in Standby mode
(VREGS (RCON[8]) = 0, RETEN (RCON[12]) = 0,
LPREGEN (FPOR[2]) = 1)
3.3V
2.0V Sleep with enabled low-voltage retention regulator
(VREGS (RCON[8]) = 0, RETEN (RCON[12]) = 1,
LPREGEN (FPOR[2]) = 0)
3.3V
Notes:
1. Data in the “Typ” column are at +25°C. Parameters are for design guidance only and are not tested.
2. Base IPD current is measured with:
– Oscillator is configured in FRC mode without PLL (FNOSC[2:0] (FOSCSEL[2:0]) = 000, PLLMODE[3:0]
(FOSCSEL[6:3]) = 1111 and POSCMOD[1:0] (FOSC[1:0]) = 11)
– OSC2 is configured as an I/O in Configuration Words (OSCIOFCN (FOSC[2]) = 0)
– FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 11)
– Secondary Oscillator circuit is disabled (SOSCSEL (FOSC[3]) = 0)
– Main and low-power BOR circuits are disabled (BOREN[1:0] (FPOR[1:0]) = 00 and LPBOREN
(FPOR[3]) = 0)
– Watchdog Timer is disabled (FWDTEN[1:0] (FWDT[6:5]) = 00)
– All I/O pins are configured as outputs and driving low
– No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
– JTAG is disabled (JTAGEN (FICD[5]) = 0)
– The currents are measured on the device containing the most memory in this family
– pwrsav #0 (SLEEP) instruction is executed.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1260
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-7. Incremental Peripheral Δ Current
Operating Conditions (unless otherwise stated):
-40°C ≤ TA ≤ +125°C
Param No. Typ Max Units Operating Temperature VDD
Conditions
Incremental Current Brown-out Reset (ΔBOR)(2)
DC25
2.4
7
µA
-40°C to +85°C
2.0V ΔBOR
2.8
7
µA
-40°C to +85°C
3.3V
6
15
µA
-40°C to +125°C
2.0V
7
15
µA
-40°C to +125°C
3.3V
Incremental Current Watchdog Timer (ΔWDT)(2)
DC71
0.8
1.5
μA
-40°C to +85°C
2.0V ΔWDT
0.8
1.5
μA
-40°C to +85°C
3.3V
1.3
7
μA
-40°C to +125°C
2.0V
2.2
7
μA
-40°C to +125°C
3.3V
Incremental Current High/Low-Voltage Detect (ΔHLVD)(2)
DC75
2
7
µA
-40°C to +85°C
2.0V ΔHLVD
3
7
µA
-40°C to +85°C
3.3V
5
15
µA
-40°C to +125°C
2.0V
6
15
µA
-40°C to +125°C
3.3V
Incremental Current Analog-to-Digital Converter (ΔADC)(2)
0.5
1.5
mA
-40°C to +85°C
2.0V ΔADC
0.6
1.5
mA
-40°C to +85°C
3.3V
0.6
2
mA
-40°C to +125°C
2.0V
0.8
2
mA
-40°C to +125°C
3.3V
Incremental Current Liquid Crystal Display (ΔLCD)(2)
DC82
DC90
3
6
µA
-40°C to +85°C
4
6
µA
-40°C to +85°C
10
15
µA
-40°C to +125°C
2.0V Internal LCD charge pump, 1/8 MUX,
1/3 Bias, LCD is enabled and running, no glass is
3.3V connected, the low-power resistor ladder current is
2.0V included
12
20
µA
-40°C to +125°C
3.3V
5
10
µA
-40°C to +85°C
6
10
µA
-40°C to +85°C
15
25
µA
-40°C to +125°C
2.0V External LCD charge pump, 1/8 MUX, 1/3 Bias,
LCD is enabled and running, no glass is
3.3V connected, the resistor ladder current is not
2.0V included
20
30
µA
-40°C to +125°C
3.3V
Incremental Current Deadman Timer (ΔDMT)(2)
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1261
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
...........continued
Operating Conditions (unless otherwise stated):
-40°C ≤ TA ≤ +125°C
Param No. Typ Max Units Operating Temperature VDD
1
3
µA
-40°C to +85°C
2.0V ΔDMT(2)
1
3
µA
-40°C to +85°C
3.3V
3
8
µA
-40°C to +125°C
2.0V
4
8
µA
-40°C to +125°C
3.3V
Conditions
Incremental Current Real-Time Clock and Calendar (ΔRTCC)(2)
DC77
DC77A
2.5
4
µA
-40°C to +85°C
2.0V With SOSC enabled in Low-Power mode
2.6
4
µA
-40°C to +85°C
3.3V
2.8
6
µA
-40°C to +125°C
2.0V
3.5
6
µA
-40°C to +125°C
3.3V
0.7
2
µA
-40°C to +85°C
2.0V With LPRC enabled
0.8
2
µA
-40°C to +85°C
3.3V
1.2
4
µA
-40°C to +125°C
2.0V
1.3
4
µA
-40°C to +125°C
3.3V
Notes:
1. Data in the “Typ” column are at +25°C. Parameters are for design guidance only and are not tested.
2. Incremental current while the module is enabled and running. This current should be added to the base IPD
current.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1262
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-8. I/O Pin Input Specifications
Operating Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param
No.
Symbol
VIL
Characteristic
Min
Max
Units
Input Low Voltage(2)
DI10
I/O Pins with ST Buffer
VSS
0.2 VDD
V
DI11
I/O Pins with TTL Buffer
VSS
0.15 VDD
V
DI15
MCLR
VSS
0.2 VDD
V
DI16
OSCI (XT mode)
VSS
0.2 VDD
V
DI17
OSCI (HS mode)
VSS
0.2 VDD
V
DI18
I/O Pins with
I2C
VSS
0.3 VDD
V
DI19
I/O Pins with SMBus Buffer
—
0.8
V
I/O Pins with ST Buffer:
with Analog Functions,
0.8 VDD
VDD
V
Digital Only
0.8 VDD
5.5
V
I/O Pins with TTL Buffer:
with Analog Functions,
0.25 VDD + 0.8
VDD
V
Digital Only
0.25 VDD + 0.8
5.5
V
VIH
DI20
DI21
Conditions
Input High
Buffer
SMBus is enabled
Voltage(3)
DI25
MCLR
0.8 VDD
VDD
V
DI26
OSCI (XT mode)
0.7 VDD
VDD
V
DI27
OSCI (HS mode)
0.7 VDD
VDD
V
DI28
I2C
I/O Pins with
Buffer:
with Analog Functions,
0.7 VDD
VDD
V
Digital Only
0.7 VDD
5.5
V
1.35
—
V
2.5V ≤ VPIN ≤ VDD
DI29
I/O Pins with SMBus Buffer:
with Analog Functions,
Digital Only
DI30
ICNPU
CNx Pull-up Current
100
450
μA
VDD = 3.3V, VPIN = VSS
DI30A
ICNPD
CNx Pull-Down Current
150
550
μA
VDD = 3.3V, VPIN = VDD
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1263
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
...........continued
Operating Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param
No.
Symbol
IIL
Characteristic
Min
Max
Units
Conditions
Input Leakage Current(1)
DI50
I/O Ports
—
±1
μA
VSS ≤ VPIN ≤ VDD,
pin at high-impedance
DI51
Analog Input Pins
—
±1
μA
VSS ≤ VPIN ≤ VDD,
pin at high-impedance
DI55
MCLR
—
±1
μA
VSS ≤ VPIN ≤ VDD
DI56
OSCI/CLKI
—
±1
μA
VSS ≤ VPIN ≤ VDD,
EC, XT and HS modes
Notes:
1. Negative current is defined as current sourced by the pin.
2. Refer to Table 1-1 for I/O pin buffer types.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1264
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-9. I/O Pin Output Specifications
Operating Conditions (unless otherwise stated):
-40°C < TA < +85°C
Param
No.
Symbol
VOL
DO10
OSCO/CLKO
VOH
DO26
Min
Max
Units
Conditions
—
0.4
V
IOL = 3 mA, VDD = 3.6V
—
0.8
V
IOL = 6 mA, VDD = 3.6V
—
0.18
V
IOL = 3 mA, VDD = 3.6V
—
0.2
V
IOL = 6 mA, VDD = 3.6V
3.4
—
V
IOL = -3.0 mA, VDD = 3.6V
3.25
—
V
IOL = -6.0 mA, VDD = 3.6V
3.3
—
V
IOL = -3 mA, VDD = 3.6V
1.85
—
V
IOL = -6 mA, VDD = 3.6V
Output Low Voltage
I/O Ports
DO16
DO20
Characteristic
Output High Voltage
I/O Ports
OSCO/CLKO
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1265
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-10. Program Memory
Operating Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param
No.
Symbol
Characteristic
Min
Max
Units
10000
—
E/W
Program Flash Memory
D130
EP
Cell Endurance
D133A
TIW
Self-Timed Double-Word Write Cycle Time
—
30
μs
Self-Timed Row Write Cycle Time
—
2
ms
D133B
TIE
Self-Timed Page Erase Time
—
40
ms
D134
TRETD
Characteristic Retention
20
—
Year
Table 32-11. Internal Voltage Regulator Specifications
Operating Conditions (unless otherwise stated):
-40°C< TA < +85°C
Param
Symbol
No.
DVR
TVREG
Characteristics
Voltage Regulator Start-up Time
Min Typ Max Units
—
10
—
VREGS = 0 with any POR or BOR
DVR10 VBG
Internal Band Gap Reference
DVR11 TBG
Band Gap Reference
Start-up Time
—
1
—
ms
DVR20 VRGOUT
Regulator Output Voltage
—
1.8
—
V
VDD > 1.9V
DVR21 CEFC
External Filter Capacitor Value
10
—
—
μF
Series resistance < 3Ω
recommended; < 5Ω required
DVR30 VLVR
Low-Voltage Regulator
Output Voltage
0.9
—
1.2
V
RETEN = 1, LPREGEN = 0
© 2019-2020 Microchip Technology Inc.
1.14 1.2 1.26
μs
Comments
Datasheet
V
DS30010203C-page 1266
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-12. High/Low-Voltage Detect Characteristics
Operating Conditions (unless otherwise stated):
-40°C < TA < +85°C
Param No.
DC18
Symbol
VHLVD
Characteristic
HLVD Voltage on VDD Transition
DC101
VTHL
HLVD Voltage on
LVDIN Pin Transition
DC105
TONLVD
HLVD Module Enable Time
© 2019-2020 Microchip Technology Inc.
Min
Typ
Max
Units
HLVDL[3:0] = 0110
2.93
—
3.39
V
HLVDL[3:0] = 0111
2.73
—
3.17
V
HLVDL[3:0] = 1000
2.62
—
3.06
V
HLVDL[3:0] = 1001
2.39
—
2.8
V
HLVDL[3:0] = 1010
2.29
—
2.68
V
HLVDL[3:0] = 1011
2.18
—
2.56
V
HLVDL[3:0] = 1100
2.08
—
2.45
V
HLVDL[3:0] = 1101
1.98
—
2.34
V
HLVDL[3:0] = 1110
1.88
—
2.23
V
HLVDL[3:0] = 1111
—
1.20
—
V
—
5
—
μs
Datasheet
DS30010203C-page 1267
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-13. Comparator DC Specifications
Operating Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param
No.
Characteristic(1)
Symbol
Min
Typ
Max
Units
D300
VIOFF
Input Offset Voltage
—
12
50
mV
D301
VICM
Input Common-Mode Voltage
0
—
VDD
V
D302
CMRR
Common-Mode Rejection Ratio
55
—
—
dB
D306
IQCMP
AVDD Quiescent Current per Comparator
—
27
—
µA
D307
TRESP
Response Time(2)
—
300
—
ns
D308
TMC2OV
Comparator Mode Change to Valid Output
—
—
10
µs
D309
IDD
Operating Supply Current
—
30
—
µA
Notes:
1. Parameters are characterized but not tested.
2. Measured with one input at VDD/2 and the other transitioning from VSS to VDD, 40 mV step, 15 mV overdrive.
Table 32-14. Comparator Voltage Reference DC Specifications
Operating Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param
No.
32.3
Symbol
Characteristic
VR310
TSET
Settling Time
VRD311
CVRAA
Absolute Accuracy
Min
Max
Units
—
10
µs
-100
+100
mV
AC Characteristics and Timing Parameters
Figure 32-2. Load Conditions for I/O Specifications
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1268
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Figure 32-3. CLKO and I/O Timing Characteristics
Table 32-15. I/O Timing Requirements
Operating Conditions 2.0V to 3.6V (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param
No.
Symbol
Characteristic
Min
Max
Units
DO31
TIOR
Port Output Rise Time
—
25
ns
DO32
TIOF
Port Output Fall Time
—
25
ns
DI35
TINP
INTx Pin High or Low Time (input)
1
—
TCY
DI40
TRBP
CNx High or Low Time (input)
1
—
TCY
Figure 32-4. External Clock Timing
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1269
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-16. External Clock Timing Requirements
Operating Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param
No.
OS10
Symbol
FOSC
Min
Typ(1)
Max
Units
External CLKI Frequency
(External clocks allowed
only in EC mode)(2)
—
4
—
—
32
48
MHz
MHz
EC
Oscillator Frequency
3.5
—
10
MHz
XT
4
—
8
MHz
XTPLL
10
—
32
MHz
HS
12
—
24
MHz
HSPLL
31
—
33
kHz
SOSC
Characteristic
Conditions
OS25
TCY
Instruction Cycle Time(3)
62.5
—
DC
ns
OS30
TOSL,
TOSH
External Clock in (OSCI)
High or Low Time
0.45 x TOSC
—
—
ns
EC
OS31
TOSR,
TOSF
External Clock in (OSCI)
Rise or Fall Time
—
—
20
ns
EC
OS40
TCKR
CLKO Rise Time(4)
—
15
30
ns
OS41
TCKF
CLKO Fall Time(4)
—
15
30
ns
Notes:
1. Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2. Represents input to the system clock prescaler. PLL dividers and postscalers must still be configured so that
the system clock frequency does not exceed the maximum frequency shown in Figure 32-1.
3. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type, under standard operating conditions, with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “Min.” values with an external
clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC”
(no clock) for all devices.
4. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the
Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1270
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-17. PLL Clock Timing Specifications
Operating Conditions 2.0V to 3.6V (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Sym
Characteristic
Min Max Units
Conditions
FIN
Input Frequency Range
2
24
MHz
FMIN
Minimum Output Frequency from the
Frequency Multiplier
—
16
MHz 4 MHz FIN with 4x feedback ratio,
2 MHz FIN with 8x feedback ratio
FMAX
Maximum Output Frequency from the
Frequency Multiplier
96
—
MHz 4 MHz FIN with 24x net
multiplication ratio,
24 MHz FIN with 4x net
multiplication ratio
FSLEW Maximum Step Function of FIN at which the PLL will
be Ensured to Maintain Lock
-4
+4
%
Full input range of FIN
TLOCK Lock Time for VCO
—
24
μs
With the specified minimum, TREF,
and a lock timer count of one
cycle, this is the maximum VCO
lock time supported
JFM8
—
±0.12
%
4 MHz FIN with 4x feedback ratio
Cumulative Jitter of Frequency Multiplier Over
Voltage and Temperature during Any Eight
Consecutive Cycles of the PLL Output
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1271
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-18. FRC Oscillator Specifications
Operating Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param No.
F20
Symbol
AFRC
Characteristic
FRC Accuracy @ 8
MHz(1)
Min
Typ(3) Max Units
-1.5
+0.15
1.5
%
-20°C ≤ TA ≤ +85°C
-2.5
—
2.5
%
-40°C ≤ TA ≤ -20°C
-2.5
—
2.5
%
85°C ≤ TA ≤ +125°C
%
0°C ≤ TA ≤ +85°C
F20A
AFRCTUNE FRC Accuracy @ 8 MHz with Enabled
Self-Tune Feature
FR0
TFRC
FRC Oscillator Start-up Time
—
2
—
µS
F22
STUNE
OSCTUN Step-Size
—
0.05
—
%/bit
—
5
8
ms
F23
TLOCK
FRC Self-Tune Lock
-0.20 +0.05 -0.20
Time(2)
Conditions
Notes:
1. To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB) must
be kept to a minimum.
2. Time from reference clock stable, and in range, to FRC tuned with range specified by F20 (with self-tune).
3. Data in the “Typ” column are 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1272
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-19. LPRC Oscillator Specifications
Operating Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
FR21
ALPRC
LPRC Accuracy @ 32 kHz
-20
—
20
%
FR1
TLPRC
Low-Power RC Oscillator Start-up Time
—
50
—
μs
Note:
1. Data in the “Typ” column are 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1273
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-20. Reset and Brown-out Reset Requirements
Operating Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param No. Symbol
Characteristic
Min
Typ
Max
Units
Conditions
SY10
TMCL
MCLR Pulse Width (Low)
2
—
—
μs
SY12
TPOR
Power-on Reset Delay
—
2
—
μs
SY13
TIOZ
I/O High-Impedance from MCLR Low or
Watchdog Timer Reset
Lesser of:
(3 TCY + 2)
or 700
—
(3 TCY
+ 2)
μs
SY25
TBOR
Brown-out Reset Pulse Width
1
—
—
μs
SY45
TRST
Internal State Reset Time
—
50
—
μs
SY71
TPM
Program Memory
Wake-up Time
—
20
—
μs
Sleep wake-up with
VREGS = 0
—
1
—
μs
Sleep wake-up with
VREGS = 1
—
90
—
μs
Sleep wake-up with
VREGS = 0
—
70
—
μs
Sleep wake-up with
VREGS = 1
SY72
TLVR
Low-Voltage Regulator Wake-up Time
VDD ≤ VBOR
Figure 32-5. Timer1 External Clock Timing Characteristics
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1274
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-21. Timer1 External Clock Timing Characteristics
Operating Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param No.
TA10
TA11
TA15
TA20
Characteristics(1)
Symbol
TCKH
TCKL
TCKP
T1CK High Time
T1CK Low Time
T1CK Input Period
Min Max Units
Synchronous
1
—
TCY
Asynchronous
10
—
ns
Synchronous
1
—
TCY
Asynchronous
10
—
ns
Synchronous
2
—
TCY
Asynchronous
20
—
ns
—
3
TCY
TCKEXTMRL Delay from External T1CK Clock Edge to Timer
Increment
Conditions
Must also meet
Parameter TA15
Must also meet
Parameter TA15
Synchronous mode
Note:
1. These parameters are characterized but not tested in manufacturing.
Figure 32-6. MCCP Timer Mode External Clock Timing Characteristics
Table 32-22. MCCP Timer Mode Timing Requirements
Operation Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param No.
TMR10
TMR11
Characteristics(1)
Symbol
TCKH
TCKL
TCKIx High Time
TCKIx Low Time
© 2019-2020 Microchip Technology Inc.
Min Max Units
Synchronous
1
—
TCY
Asynchronous
10
—
ns
Synchronous
1
—
TCY
Asynchronous
10
—
ns
Datasheet
Conditions
Must also meet
Parameter TMR15
Must also meet
Parameter TMR15
DS30010203C-page 1275
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
...........continued
Operation Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
TMR15
TMR20
TCKP
TCKIx Input Period
Synchronous
2
—
TCY
Asynchronous
20
—
ns
—
1
TCY
TCKEXTMRL Delay from External TCKIx Clock Edge to Timer Increment
Note:
1. These parameters are characterized but not tested in manufacturing.
Figure 32-7. MCCP Input Capture Mode Timing Characteristics
Table 32-23. MCCP Input Capture Mode Timing Requirements
Operation Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param No.
Symbol
Characteristics(1)
Min
Max
Units
Conditions
IC10
TICL
ICMx Input Low Time
25
—
ns
Must also meet Parameter IC15
IC11
TICH
ICMx Input High Time
25
—
ns
Must also meet Parameter IC15
IC15
TICP
ICMx Input Period
50
—
ns
Note:
1. These parameters are characterized but not tested in manufacturing.
Figure 32-8. MCCP PWM Mode Timing Characteristics
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1276
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-24. MCCP PWM Mode Timing Requirements
Operation Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param
No.
Characteristics(1)
Symbol
Min
Max
Units
OC15
TFD
Fault Input to PWM I/O Change
—
30
ns
OC20
TFLT
Fault Input Pulse Width
10
—
ns
Note:
1. These parameters are characterized but not tested in manufacturing.
Figure 32-9. SPI Module Master Mode (CKE = 0) Timing Characteristics
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1277
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Figure 32-10. SPI Module Master Mode (CKE = 1) Timing Characteristics
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1278
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-25. SPI Module Master Mode Timing Requirements
Operation Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param No.
Symbol
Characteristics(1)
Min
Max
Units
SP10
TSCL, TscH
SCKx Output Low or High Time
20
—
ns
SP35
TSCH2DOV, TSCL2DOV
SDOx Data Output Valid after SCKx Edge
—
7
ns
SP36
TDOV2SC, TDOV2SCL
SDOx Data Output Setup to First SCKx Edge
7
—
ns
SP40
TDIV2SCH, TDIV2SCL
Setup Time of SDIx Data Input to SCKx Edge
7
—
ns
SP41
TSCH2DIL, TSCL2DIL
Hold Time of SDIx Data Input to SCKx Edge
7
—
ns
Note:
1. These parameters are characterized but not tested in manufacturing.
Figure 32-11. SPI Module Slave Mode (CKE = 0) Timing Characteristics
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1279
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Figure 32-12. SPI Module Slave Mode (CKE = 1) Timing Characteristics
Table 32-26. SPI Module Slave Mode Timing Requirements
Operation Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param No.
Symbol
Characteristics(1)
Min
Max
Units
SP70
TSCL, TSCH
SCKx Input Low Time or High Time
20
—
ns
SP35
TSCH2DOV,
TSCL2DOV
SDOx Data Output Valid after SCKx Edge
—
10
ns
SP40
TDIV2SCH, TDIV2SCL
Setup Time of SDIx Data Input to SCKx Edge
0
—
ns
SP41
TSCH2DIL, TSCL2DIL
Hold Time of SDIx Data Input to SCKx Edge
7
—
ns
SP50
TSSL2SCH, TSSL2SCL
SSx ↓ to SCKx ↓ or SCKx ↑ Input
40
—
ns
SP51
TSSH2SDOZ
SSx ↑ to SDOx Output High-Impedance
2.5
12
ns
SP52
TSCH2SSH, TSCL2SSH
SSx ↑ after SCKx Edge
10
—
ns
SP60
TSSL2DOV
SDOx Data Output Valid after SSx Edge
—
12.5
ns
Note:
1. These parameters are characterized but not tested in manufacturing.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1280
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Figure 32-13. I2C Bus Start/Stop Bits Timing Characteristics (Master Mode)
Figure 32-14. I2C Bus Data Timing Characteristics (Master Mode)
Table 32-27. I2C Bus Data Timing Requirements (Master Mode)
Operation Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param No. Symbol
IM10
IM11
IM20
IM21
TLO:SCL
THI:SCL
TF:SCL
TR:SCL
Characteristics(1)
Clock Low Time
Clock High Time
SDAx and SCLx
Fall Time
SDAx and SCLx
Rise Time
Min.
100 kHz mode TCY * (BRG + 2)
—
μs
400 kHz mode TCY * (BRG + 2)
—
μs
1 MHz mode
TCY * (BRG + 2)
—
μs
100 kHz mode TCY * (BRG + 2)
—
μs
400 kHz mode TCY * (BRG + 2)
—
μs
1 MHz mode
TCY * (BRG + 2)
—
μs
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode
100
—
ns
1 MHz mode
IM25
TSU:DAT
Data Input
Setup Time
© 2019-2020 Microchip Technology Inc.
Max. Units
Datasheet
Conditions
DS30010203C-page 1281
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
...........continued
Operation Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param No. Symbol
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
IM51
Characteristics(1)
THD:DAT Data Input
Hold Time
TSU:STA
THD:STA
Start Condition
Setup Time
Start Condition Hold
Time
TSU:STO Stop Condition Setup
Time
THD:STO Stop Condition
Hold Time
TAA:SCL
TBF:SDA
CB
TPGD
Output Valid from
Clock
Bus Free Time
Bus Capacitive
Loading
Min.
Max. Units
100 kHz mode
0
—
μs
400 kHz mode
0
0.9
μs
1 MHz mode
0
0.3
μs
100 kHz mode TCY * (BRG + 2)
—
μs
400 kHz mode TCY * (BRG + 2)
—
μs
1 MHz mode
TCY * (BRG + 2)
—
μs
100 kHz mode TCY * (BRG + 2)
—
μs
400 kHz mode TCY * (BRG + 2)
—
μs
1 MHz mode
TCY * (BRG + 2)
—
μs
100 kHz mode TCY * (BRG + 2)
—
μs
400 kHz mode TCY * (BRG + 2)
—
μs
1 MHz mode
TCY * (BRG + 2)
—
μs
100 kHz mode TCY * (BRG + 2)
—
ns
400 kHz mode TCY * (BRG + 2)
—
ns
1 MHz mode
TCY * (BRG + 2)
—
ns
100 kHz mode
—
3500
ns
400 kHz mode
—
1000
ns
1 MHz mode
—
350
ns
100 kHz mode
4.7
—
μs
400 kHz mode
1.3
—
μs
1 MHz mode
0.5
—
μs
100 kHz mode
—
400
pF
400 kHz mode
—
400
pF
1 MHz mode
—
10
pF
52
312
ns
Pulse Gobbler Delay
Conditions
Only relevant for
Repeated Start
condition
After this period, the
first clock pulse is
generated
The amount of time
the bus must be free
before a new
transmission can
start
Note:
1. These parameters are characterized but not tested in manufacturing.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1282
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Figure 32-15. I2C Bus Start/Stop Bits Timing Characteristics (Slave Mode)
Figure 32-16. I2C Bus Data Timing Characteristics (Slave Mode)
Table 32-28. I2C Bus Data Timing Requirements (Slave Mode)
Operation Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param
Symbol
No.
IS10
IS11
IS20
TLO:SCL
THI:SCL
TF:SCL
Characteristics
Clock Low Time
Clock High Time
SDAx and SCLx Fall
Time
© 2019-2020 Microchip Technology Inc.
Min.
Max. Units
Conditions
100 kHz mode
4.7
—
μs
CPU clock must be a
minimum of 800 kHz
400 kHz mode
1.3
—
μs
CPU clock must be a
minimum of 3.2 MHz
1 MHz mode
0.5
—
μs
100 kHz mode
4.0
—
μs
CPU clock must be a
minimum of 800 kHz
400 kHz mode
0.6
—
μs
CPU clock must be a
minimum of 3.2 MHz
1 MHz mode
0.5
—
μs
100 kHz mode
—
300
ns
400 kHz mode 20 + 0.1 CB 300
ns
1 MHz mode
ns
—
Datasheet
100
DS30010203C-page 1283
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
...........continued
Operation Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param
Symbol
No.
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
TR:SCL
TSU:DAT
Characteristics
SDAx and SCLx Rise
Time
THD:STA
CB
1000
ns
400 kHz mode 20 + 0.1 CB 300
ns
1 MHz mode
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode
100
—
ns
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
μs
1 MHz mode
0
0.3
μs
100 kHz mode
4700
—
ns
400 kHz mode
600
—
ns
1 MHz mode
250
—
ns
Start Condition Hold Time 100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode
250
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode
600
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode
250
—
ns
100 kHz mode
0
3500
ns
400 kHz mode
0
1000
ns
1 MHz mode
0
350
ns
100 kHz mode
4.7
—
μs
400 kHz mode
1.3
—
μs
1 MHz mode
0.5
—
μs
100 kHz mode
—
400
pF
400 kHz mode
—
400
pF
1 MHz mode
—
10
pF
Data Input
Setup Time
Start Condition
Setup Time
THD:STO Stop Condition
Hold Time
TBF:SDA
—
300
TSU:STO Stop Condition Setup
Time
TAA:SCL
100 kHz mode
Max. Units
—
THD:DAT Data Input
Hold Time
TSU:STA
Min.
Output Valid from Clock
Bus Free Time
Bus Capacitive Loading
© 2019-2020 Microchip Technology Inc.
Datasheet
Conditions
Only relevant for
Repeated Start
condition
After this period, the first
clock pulse is generated
The amount of time the
bus must be free before a
new transmission can
start
DS30010203C-page 1284
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-29. A/D Module Specifications
Operation Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param No. Symbol
Characteristic
Min.
Typ
Max.
Units
Greater of:
—
Lesser of:
V
Conditions
Device Supply
AD01
AD02
AVDD
AVSS
Module VDD Supply
Module VSS Supply
VDD – 0.3
VDD + 0.3
or 2.2
or 3.6
VSS – 0.3
—
VSS + 0.3
V
Reference Inputs
AD05
VREFH
Reference Voltage High
AVSS + 1.7
—
AVDD
V
AD06
VREFL
Reference Voltage Low
AVSS
—
AVDD – 1.7
V
AD07
VREF
Absolute Reference
Voltage
AVSS – 0.3
—
AVDD + 0.3
V
VREFL
—
VREFH
V
Analog Inputs
AD10
VINH-VINL Full-Scale Input Span
AD11
VIN
Absolute Input Voltage
AVSS – 0.3
—
AVDD + 0.3
V
AD12
VINL
Absolute VINL Input
Voltage
AVSS – 0.3
—
AVDD/3
V
Leakage Current
—
±1.0
±610
nA
VINL = AVSS = VREFL= 0V,
AVDD = VREFH = 3V,
Source Impedance =
2.5 kΩ
Recommended
Impedance of Analog
Voltage Source
—
—
2.5k
Ω
10-bit
AD13
AD17
RIN
(Note 2)
A/D Accuracy
AD20B
NR
Resolution
—
12
—
bits
AD21B
INL
Integral Nonlinearity
—
±1
< ±2
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD22B
DNL
Differential Nonlinearity
—
—
< ±1(3)
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD23B
GERR
Gain Error
-2
±1
+4
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD24B
EOFF
Offset Error
-2
±1
+5
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
Monotonicity(1)
—
—
—
—
AD25B
© 2019-2020 Microchip Technology Inc.
Datasheet
Guaranteed
DS30010203C-page 1285
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Notes:
1. The A/D conversion result never decreases with an increase in the input voltage.
2. Measurements are taken with the external VREF+ and VREF- used as the A/D voltage reference.
3. Code 2047 can have a DNL error of ≥ ±1 LSb to < ±1.5 LSb and code 3071 can have a DNL error of ≥ ±1 LSb
to < ±2.5 LSb.
Table 32-30. A/D Conversion Timing Requirements(1)
Operation Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param No.
Symbol
Characteristic
Min.
Typ
Max.
Units
278
—
—
ns
Conditions
Clock Parameters
AD50
TAD
A/D Clock Period
AD51
tRC
A/D Internal RC Oscillator
Period
—
250
—
ns
SAR Conversion Time,
12-Bit Mode
—
14
—
TAD
SAR Conversion Time,
10-Bit Mode is Typical
12 TAD
—
12
—
TAD
Conversion Rate
AD55
tCONV
AD55A
AD56
FCNV
Throughput Rate
—
—
400
ksps
AD57
tSAMP
Sample Time
—
1
—
TAD
Sample Start Delay from
Setting Sample bit (SAMP)
1.5
—
2.5
TAD
AVDD > 2.7V(2)
Clock Synchronization
AD61
tPSS
Notes:
1. Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
2. Throughput rate is based on AD55 + AD57 + AD61 and the period of TAD.
Table 32-31. 10-Bit DAC Specifications(1)
Operation Conditions (unless otherwise stated):
VDD = AVDD = DVREF+ = 3.3V,
3 kΩ Load to VSS,
-40°C < TA < +85°C
Param No. Symbol
Characteristic(3)
Min.
Typ.
Max.
Units
DAC01
Resolution
10
—
—
bits
DAC02
DVREF+ Input Voltage
Range
—
—
AVDD
V
-1
—
+1
LSb
-3.0
—
+3.0
LSb
DAC03
DNL
Differential Linearity
Error
DAC04
INL
Integral Linearity Error
© 2019-2020 Microchip Technology Inc.
Datasheet
Comments
DS30010203C-page 1286
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
...........continued
Operation Conditions (unless otherwise stated):
VDD = AVDD = DVREF+ = 3.3V,
3 kΩ Load to VSS,
-40°C < TA < +85°C
Param No. Symbol
Characteristic(3)
Min.
Typ.
Max.
Units
DAC05
Offset Error
-20
—
+20
mV
DAC06
Gain Error
-3.0
—
+3.0
LSb
DAC07
Monotonicity
DAC08
Maximum Output
Voltage Swing
DAC09
Note 2
Comments
—
AVSS + 20
—
AVDD –
20
mV
No output load
Slew Rate
—
3.8
—
V/μs
DAC10
Settling Time
—
0.9
—
μs
Within ½ LSb of final value,
transition from ¼ to ¾ fullscale range
DAC11
Maximum Continuous
Output Current Rating
(DC or AC RMS)
—
—
6
mA
This value is not tested in
production
DAC12
AVDD Quiescent
Current
—
700
—
μA
Module enabled, DAC
Reference = AVDD, no output
load
DAC13
DVREF+ Quiescent
Current
—
330
—
μA
Module enabled, DAC
Reference = DVREF+
Notes:
1. Unless otherwise stated, test conditions are with VDD = AVDD = DVREF+ = 3.3V, 3 kΩ load to VSS.
2. DAC output voltage never decreases with an increase in the data code.
3. These parameters are characterized but not tested in manufacturing.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1287
PIC24FJ512GU410 Family Data Sheet
Electrical Characteristics
Table 32-32. USB OTG Electrical Specifications
Operation Conditions (unless otherwise stated):
2.0V < VDD < 3.6V
-40°C < TA < +85°C
Param No. Symbol
Characteristics(1)
Min. Max. Units
Conditions
USB313
VUSB3V3 USB Voltage
3.0
3.6
V
Voltage on VUSB3V3 must be in this
range for proper USB operation
USB315
VILUSB
Input Low Voltage for USB Buffer
—
0.8
V
USB316
VIHUSB
Input High Voltage for USB Buffer
2.0
—
V
USB318
VDIFS
Differential Input Sensitivity
—
0.2
V
USB319
VCM
Differential Common-Mode Range
0.8
2.5
V
USB320
ZOUT
Driver Output Impedance
28.0 44.0
Ω
USB321
VOL
Voltage Output Low
0.0
0.3
V
14.25 kΩ load connected to 3.6V
USB322
VOH
Voltage Output High
2.8
3.6
V
14.25 kΩ load connected to ground
The difference between D+ and Dmust exceed this value while VCM is
met
Note:
1. These parameters are characterized but not tested in manufacturing.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1288
PIC24FJ512GU410 Family Data Sheet
Package Information
33.
Package Information
33.1
Package Marking Information
48-Lead UQFN (6x6 mm)
PIN 1
Example
PIN 1
XXXXXXXX
XXXXXXXX
YYWWNNN
PIC24FJ
128GU405
1910017
48-Lead TQFP (7x7 mm)
Example
XXXXXXX
XXXYYWW
NNN
FJ128GU
4051910
017
64-Lead QFN (9x9 mm)
PIN 1
Example
PIN 1
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
Note:
PIC24FJ128
GU406
1920017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1289
PIC24FJ512GU410 Family Data Sheet
Package Information
33.2
Package Marking Information (Continued)
64-Lead TQFP (10x10x1 mm)
Example
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
PIC24FJ128
GU406
1920017
80-Lead TQFP (12x12 mm)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC24FJ128
GU408
1920017
100-Lead TQFP (12x12 mm)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
33.3
PIC24FJ128
GU410
1920017
Package Details
The following sections give the technical details of the packages.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1290
PIC24FJ512GU410 Family Data Sheet
Package Information
48-Lead Ultra Thin Plastic Quad Flat, No Lead Package (PTX) - 6x6 mm Body [UQFN]
With Corner Anchors and 4.6x4.6 mm Exposed Pad
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
A1
52X
0.08 C
D
NOTE 1
A
0.10 C
B
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
0.10 C
(A3)
TOP VIEW
A
8X (b1)
0.10
C A B
D2
C
SEATING
PLANE
SIDE VIEW
0.10
C A B
8X (b2)
E2
e
2
2
1
NOTE 1
(K)
N
L
e
48X b
0.07
0.05
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-442A-PTX Sheet 1 of 2
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1291
PIC24FJ512GU410 Family Data Sheet
Package Information
48-Lead Ultra Thin Plastic Quad Flat, No Lead Package (PTX) - 6x6 mm Body [UQFN]
With Corner Anchors and 4.6x4.6 mm Exposed Pad
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Notes:
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Standoff
A1
Terminal Thickness
A3
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
Exposed Pad Width
E2
b
Terminal Width
b1
Corner Anchor Pad
Corner Anchor Pad, Metal-free Zone
b2
Terminal Length
L
Terminal-to-Exposed-Pad
K
MIN
0.50
0.00
4.50
4.50
0.15
0.35
MILLIMETERS
NOM
48
0.40 BSC
0.55
0.02
0.15 REF
6.00 BSC
4.60
6.00 BSC
4.60
0.20
0.45 REF
0.23 REF
0.40
0.30 REF
MAX
0.60
0.05
4.70
4.70
0.25
0.45
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-442A-PTX Sheet 2 of 2
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1292
PIC24FJ512GU410 Family Data Sheet
Package Information
48-Lead Ultra Thin Plastic Quad Flat, No Lead Package (PTX) - 6x6 mm Body [UQFN]
With Corner Anchors and 4.6x4.6 mm Exposed Pad
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
R
48
Y3
1
2
Y2
C2
ØV
EV
G2
G1
Y1
SILK SCREEN
X1
X3
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
X2
Center Pad Width
Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X48)
X1
Contact Pad Length (X48)
Y1
X3
Corner Anchor Pad Width (X4)
Corner Anchor Pad Length (X4)
Y3
Pad Corner Radius (X 20)
R
Contact Pad to Center Pad (X48)
G1
Contact Pad to Contact Pad
G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.40 BSC
MAX
4.70
4.70
6.00
6.00
0.20
0.80
0.90
0.90
0.10
0.25
0.20
0.33
1.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2442A-PTX
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1293
PIC24FJ512GU410 Family Data Sheet
Package Information
48-Lead Plastic Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1
2
D
2
D
E1
2
A
B
E
E1
A
NOTE 1
A
E
2
N
N/4 TIPS
0.20 C A-B D
1
2
3
0.20 C A-B D 4X
e
2
e
TOP VIEW
C
SEATING
PLANE
A A2
48X
A1
48X b
0.08
0.08 C
C A-B D
SIDE VIEW
Microchip Technology Drawing C04-300-Y8 Rev D Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1294
PIC24FJ512GU410 Family Data Sheet
Package Information
48-Lead Plastic Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ϴ2
ϴ1
R2
H
R1
ϴ2
c
ϴ
L
(L1)
SECTION A-A
Notes:
Number of Terminals
Pitch
Overall Height
Standoff
Molded Package Thickness
Overall Length
Molded Package Length
Overall Width
Molded Package Width
Terminal Width
Terminal Thickness
Terminal Length
Footprint
Lead Bend Radius
Lead Bend Radius
Foot Angle
Lead Angle
Mold Draft Angle
Units
Dimension Limits
N
e
A
A1
A2
D
D1
E
E1
b
c
L
L1
R1
R2
ϴ
ϴ1
ϴ2
MIN
0.05
0.95
0.17
0.09
0.45
0.08
0.08
0°
0°
11°
MILLIMETERS
NOM
48
0.50 BSC
1.00
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
0.22
0.60
1.00 REF
3.5°
12°
MAX
1.20
0.15
1.05
0.27
0.16
0.75
0.20
7°
13°
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-300-Y8 Rev D Sheet 2 of 2
© 2018 Microchip Technology Inc.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1295
PIC24FJ512GU410 Family Data Sheet
Package Information
48-Lead Plastic Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
G
C2
SILK SCREEN
48
Y1
1 2
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X48)
X1
Contact Pad Length (X48)
Y1
Distance Between Pads
G
MIN
MILLIMETERS
NOM
0.50 BSC
8.40
8.40
MAX
0.30
1.50
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2300-Y8 Rev D
© 2018 Microchip Technology Inc.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1296
PIC24FJ512GU410 Family Data Sheet
Package Information
64-Lead Very Thin Plastic Quad Flat, No Lead Package (R4X) – 9x9x0.9 mm Body [VQFN]
With 7.15 x 7.15 Exposed Pad [Also called QFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
NOTE 1
A
B
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.25 C
2X
TOP VIEW
0.25 C
SEATING
PLANE
A1
0.10 C
C
A
64X
(A3)
0.08 C
SIDE VIEW
0.10
C A B
D2
0.10
C A B
E2
NOTE 1
K
2
1
N
64X b
L
e
2
e
0.10
0.05
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-149 [R4X] Rev E Sheet 1 of 2
© 2019 Microchip Technology Incorporated
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1297
PIC24FJ512GU410 Family Data Sheet
Package Information
64-Lead Very Thin Plastic Quad Flat, No Lead Package (R4X) – 9x9x0.9 mm Body [VQFN]
With 7.15 x 7.15 Exposed Pad [Also called QFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
N
Number of Pins
e
Pitch
A
Overall Height
A1
Standoff
A3
Contact Thickness
E
Overall Width
E2
Exposed Pad Width
D
Overall Length
D2
Exposed Pad Length
b
Contact Width
Contact Length
L
Contact-to-Exposed Pad
K
MIN
0.80
0.00
7.05
7.05
0.18
0.30
0.20
MILLIMETERS
NOM
64
0.50 BSC
0.90
0.02
0.20 REF
9.00 BSC
7.15
9.00 BSC
7.15
0.25
0.40
-
MAX
1.00
0.05
7.25
7.25
0.30
0.50
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-149 [R4X] Rev E Sheet 2 of 2
© 2019 Microchip Technology Incorporated
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1298
PIC24FJ512GU410 Family Data Sheet
Package Information
64-Lead Very Thin Plastic Quad Flat, No Lead Package (R4X) – 9x9x0.9 mm Body [VQFN]
With 7.15 x 7.15 Exposed Pad [Also called QFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
Y1
EV
20
G1
1
2
ØV
Y2
G2
C2
EV
Y1
X1
E
2
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X64)
X1
Contact Pad Length (X64)
Y1
Contact Pad to Center Pad (X64)
G1
Spacing Between Contact Pads (X60)
G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
7.25
7.25
9.00
9.00
0.30
0.95
0.40
0.20
0.33
1.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-149 [R4X] Rev E
© 2019 Microchip Technology Incorporated
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1299
PIC24FJ512GU410 Family Data Sheet
Package Information
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1/2
D
NOTE 2
A
B
E1/2
E1
A
E
A
SEE DETAIL 1
N
4X N/4 TIPS
0.20 C A-B D
1 3
2
4X
NOTE 1
0.20 H A-B D
TOP VIEW
A2
A
0.05
C
SEATING
PLANE
0.08 C
64 X b
0.08
e
A1
C A-B D
SIDE VIEW
Microchip Technology Drawing C04-085C Sheet 1 of 2
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1300
PIC24FJ512GU410 Family Data Sheet
Package Information
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
H
c
L
(L1)
X=A—B OR D
X
SECTION A-A
e/2
DETAIL 1
Notes:
Units
Dimension Limits
Number of Leads
N
e
Lead Pitch
Overall Height
A
Molded Package Thickness
A2
Standoff
A1
Foot Length
L
Footprint
L1
Foot Angle
Overall Width
E
Overall Length
D
Molded Package Width
E1
Molded Package Length
D1
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
0.95
0.05
0.45
0°
0.09
0.17
11°
11°
MILLIMETERS
NOM
64
0.50 BSC
1.00
0.60
1.00 REF
3.5°
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
0.22
12°
12°
MAX
1.20
1.05
0.15
0.75
7°
0.20
0.27
13°
13°
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085C Sheet 2 of 2
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1301
PIC24FJ512GU410 Family Data Sheet
Package Information
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
E
C2
G
Y1
X1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X28)
X1
Contact Pad Length (X28)
Y1
Distance Between Pads
G
MIN
MILLIMETERS
NOM
0.50 BSC
11.40
11.40
MAX
0.30
1.50
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2085B Sheet 1 of 1
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1302
M
PIC24FJ512GU410 Family Data Sheet
Packaging Diagrams and Parameters
Package Information
80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
NOTE 1
12 3
NOTE 2
c
β
φ
L
α
A
A2
A1
L1
Units
Dimension Limits
Number of Leads
MILLIMETERS
MIN
N
NOM
MAX
80
Lead Pitch
e
Overall Height
A
–
0.50 BSC
–
Molded Package Thickness
A2
0.95
1.00
1.05
Standoff
A1
0.05
–
0.15
Foot Length
L
0.45
0.60
0.75
Footprint
L1
1.20
1.00 REF
Foot Angle
φ
Overall Width
E
14.00 BSC
Overall Length
D
14.00 BSC
Molded Package Width
E1
12.00 BSC
Molded Package Length
D1
12.00 BSC
0°
3.5°
7°
Lead Thickness
c
0.09
–
0.20
Lead Width
b
0.17
0.22
0.27
Mold Draft Angle Top
α
11°
12°
13°
Mold Draft Angle Bottom
β
11°
12°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-092B
© 2007 Microchip Technology Inc.
DS00049AR-page 138
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1303
M
PIC24FJ512GU410 Family Data Sheet
Packaging Diagrams and Parameters
Package Information
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009 Microchip Technology Inc.
© 2019-2020 Microchip Technology Inc.
DS00049BC-page 97
Datasheet
DS30010203C-page 1304
M
PIC24FJ512GU410 Family Data Sheet
Packaging Diagrams and Parameters
Package Information
100-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
e
E
E1
N
b
NOTE 1
1 23
NOTE 2
c
α
A
φ
L
β
A1
Units
Dimension Limits
Number of Leads
A2
L1
MILLIMETERS
MIN
N
NOM
MAX
100
Lead Pitch
e
Overall Height
A
–
0.40 BSC
–
Molded Package Thickness
A2
0.95
1.00
1.05
Standoff
A1
0.05
–
0.15
Foot Length
L
0.45
0.60
0.75
Footprint
L1
1.20
1.00 REF
Foot Angle
φ
Overall Width
E
14.00 BSC
Overall Length
D
14.00 BSC
Molded Package Width
E1
12.00 BSC
Molded Package Length
D1
12.00 BSC
0°
3.5°
7°
Lead Thickness
c
0.09
–
0.20
Lead Width
b
0.13
0.18
0.23
Mold Draft Angle Top
α
11°
12°
13°
Mold Draft Angle Bottom
β
11°
12°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-100B
© 2007 Microchip Technology Inc.
DS00049AR-page 142
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1305
M
PIC24FJ512GU410 Family Data Sheet
Packaging Diagrams and Parameters
Package Information
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009 Microchip Technology Inc.
DS00049BC-page 102
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1306
PIC24FJ512GU410 Family Data Sheet
Revision History
34.
34.1
Revision History
Revision A (August 2019)
This is the initial version of the document.
34.2
Revision B (December 2019)
Updates Analog Features, eXtreme Low-Power Features, Functional Safety and Security Peripherals, Special
Microcontroller Features, PIC24FJ512GU410 Family, Figure 1-1, 4.8 Flash OTP by ICSP™ Write Inhibit, 14.
Capture/Compare/PWM/Timer Modules (MCCP), 15. Serial Peripheral Interface (SPI), Equation 16-1, Table 32-4,
Table 32-5, Table 32-6, Table 32-7, Table 32-8, Table 32-12, Table 32-16, Table 32-17, Table 32-18, Table 32-29 and
Table 32-30.
34.3
Revision C (May 2020)
Updates Peripheral Features, Table 1, 6.4.1 DMACON, 7.6.1 RCON(1,6), all Interrupt Request Flag and Interrupt
Enable registers, 18.1.1 LCDCON, Table 32-6, Table 32-18 and Table 32-31.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1307
PIC24FJ512GU410 Family Data Sheet
The Microchip Website
Microchip provides online support via our website at www.microchip.com/. This website is used to make files and
information easily available to customers. Some of the content available includes:
•
•
•
Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online
discussion groups, Microchip design partner program member listing
Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of
seminars and events, listings of Microchip sales offices, distributors and factory representatives
Product Change Notification Service
Microchip’s product change notification service helps keep customers current on Microchip products. Subscribers will
receive email notification whenever there are changes, updates, revisions or errata related to a specified product
family or development tool of interest.
To register, go to www.microchip.com/pcn and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Embedded Solutions Engineer (ESE)
Technical Support
Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to
help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the website at: www.microchip.com/support
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1308
PIC24FJ512GU410 Family Data Sheet
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](1)
PART NO.
Device
-
X
Tape and Reel Temperature
Option
Range
/XX
XXX
Package
Pattern
Device:
PIC16F18313, PIC16LF18313, PIC16F18323, PIC16LF18323
Tape and Reel Option:
Blank
= Standard packaging (tube or tray)
T
= Tape and Reel(1)
I
= -40°C to +85°C (Industrial)
E
= -40°C to +125°C (Extended)
JQ
= UQFN
P
= PDIP
ST
= TSSOP
SL
= SOIC-14
SN
= SOIC-8
RF
= UDFN
Temperature Range:
Package:(2)
Pattern:
QTP, SQTP, Code or Special Requirements (blank otherwise)
Examples:
•
•
PIC16LF18313- I/P Industrial temperature, PDIP package
PIC16F18313- E/SS Extended temperature, SSOP package
Notes:
1. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering
purposes and is not printed on the device package. Check with your Microchip Sales Office for package
availability with the Tape and Reel option.
2. Small form-factor packaging options may be available. Please check www.microchip.com/packaging for smallform factor package availability, or contact your local Sales Office.
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
•
•
•
•
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these
methods, to our knowledge, require using the Microchip products in a manner outside the operating
specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of
intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code
protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection
features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital
Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you
may have a right to sue for relief under that Act.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1309
PIC24FJ512GU410 Family Data Sheet
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for your
convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with
your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER
EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,
indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such
use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless
otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,
BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,
KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST,
MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer,
QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control,
HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus,
ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider,
Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom,
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP,
INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM,
PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad
I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
©
2019-2020, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-6160-9
AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart,
DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb,
TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered
trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Quality Management System
For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
© 2019-2020 Microchip Technology Inc.
Datasheet
DS30010203C-page 1310
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© 2019-2020 Microchip Technology Inc.
Datasheet
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