PIC24FJ64GA004 FAMILY
28/44-Pin General Purpose, 16-Bit Flash Microcontrollers
High-Performance CPU
Analog Features
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator with 4x PLL Option and
Multiple Divide Options
• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16-Bit x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture:
- 76 base instructions
- Flexible addressing modes
• Two Address Generation Units (AGUs) for Separate
Read and Write Addressing of Data Memory
• 10-Bit, up to 13-Channel Analog-to-Digital Converter:
- 500 ksps conversion rate
- Conversion available during Sleep and Idle
• Dual Analog Comparators with Programmable
Input/Output Configuration
Peripheral Features
• Peripheral Pin Select (PPS):
- Allows independent I/O mapping of many peripherals
- Up to 26 available pins (44-pin devices)
- Continuous hardware integrity checking and safety
interlocks prevent unintentional configuration changes
• 8-Bit Parallel Master/Slave Port (PMP/PSP):
- Up to 16-bit multiplexed addressing, with up to
11 dedicated address pins on 44-pin devices
- Programmable polarity on control lines
• Hardware Real-Time Clock/Calendar (RTCC):
- Provides clock, calendar and alarm functions
• Programmable Cyclic Redundancy Check (CRC)
• Two 3-Wire/4-Wire SPI modules (support 4 Frame
modes) with 8-Level FIFO Buffer
• Two I2C™ modules Support Multi-Master/Slave
mode and 7-Bit/10-Bit Addressing
• Two UART modules:
- Supports RS-485, RS-232, and LIN/J2602
- On-chip hardware encoder/decoder for IrDA®
- Auto-wake-up on Start bit
- Auto-Baud Detect
- 4-level deep FIFO buffer
• Five 16-Bit Timers/Counters with Programmable Prescaler
• Five 16-Bit Capture Inputs
• Five 16-Bit Compare/PWM Outputs
• Configurable Open-Drain Outputs on Digital I/O Pins
• Up to 3 External Interrupt Sources
Special Microcontroller Features
•
•
•
•
•
•
•
•
•
•
•
Operating Voltage Range of 2.0V to 3.6V
5.5V Tolerant Input (digital pins only)
High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
Flash Program Memory:
- 10,000 erase/write
- 20-year data retention minimum
Power Management modes:
- Sleep, Idle, Doze and Alternate Clock modes
- Operating current: 650 A/MIPS, typical at 2.0V
- Sleep current: 150 nA, typical at 2.0V
Fail-Safe Clock Monitor (FSCM) Operation:
- Detects clock failure and switches to on-chip,
low-power RC oscillator
On-Chip, 2.5V Regulator with Tracking mode
Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
Flexible Watchdog Timer (WDT) with On-Chip,
Low-Power RC Oscillator for Reliable Operation
In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Debug (ICD) via 2 Pins
JTAG Boundary Scan Support
Device
Pins
Program
Memory
(bytes)
SRAM
(bytes)
Remappable
Pins
Timers
16-Bit
Capture
Input
Compare/
PWM
Output
UART w/
IrDA®
SPI
I2C™
10-Bit A/D
(ch)
Comparators
PMP/PSP
JTAG
Remappable Peripherals
PIC24FJ16GA002
28
16K
4K
16
5
5
5
2
2
2
10
2
Y
Y
PIC24FJ32GA002
28
32K
8K
16
5
5
5
2
2
2
10
2
Y
Y
PIC24FJ48GA002
28
48K
8K
16
5
5
5
2
2
2
10
2
Y
Y
PIC24FJ64GA002
28
64K
8K
16
5
5
5
2
2
2
10
2
Y
Y
PIC24FJ16GA004
44
16K
4K
26
5
5
5
2
2
2
13
2
Y
Y
PIC24FJ32GA004
44
32K
8K
26
5
5
5
2
2
2
13
2
Y
Y
PIC24FJ48GA004
44
48K
8K
26
5
5
5
2
2
2
13
2
Y
Y
PIC24FJ64GA004
44
64K
8K
26
5
5
5
2
2
2
13
2
Y
Y
2010-2013 Microchip Technology Inc.
DS39881E-page 1
PIC24FJ64GA004 FAMILY
Pin Diagrams
28-Pin QFN(1)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VSS
AN9/RP15/CN11/PMCS1/RB15
AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14
AN11/RP13/CN13/PMRD/RB13
AN12/RP12/CN14/PMD0/RB12
PGEC2/TMS/RP11/CN15/PMD1/RB11
PGED2/TDI/RP10/CN16/PMD2/RB10
VCAP/VDDCORE
DISVREG
TDO/SDA1/RP9/CN21/PMD3/RB9
TCK/SCL1/RP8/CN22/PMD4/RB8
RP7/INT0/CN23/PMD5/RB7
PGEC3/ASCL1/RP6/CN24/PMD6/RB6
28 27 26 25 24 23 22
1
21
2
20
3
19
4 PIC24FJXXGA002 18
5
17
6
16
7
15
8 9 10 11 12 13 14
AN11/RP13/CN13/PMRD/RB13
AN12/RP12/CN14/PMD0/RB12
PGEC2/TMS/RP11/CN15/PMD1/RB11
PGED2/TDI/RP10/CN16/PMD2/RB10
VCAP/VDDCORE
DISVREG
TDO/SDA1/RP9/CN21/PMD3/RB9
SOSCI/RP4/PMBE/CN1/RB4
SOSCO/T1CK/CN0/PMA1/RA4
VDD
PGED3/ASDA1/RP5/CN27/PMD7/RB5
PGEC3/ASCL1/RP6/CN24/PMD6/RB6
RP7/INT0/CN23/PMD5/RB7
TCK/SCL1/RP8/CN22/PMD4/RB8
PGED1/AN2/C2IN-/RP0/CN4/RB0
PGEC1/AN3/C2IN+/RP1/CN5/RB1
AN4/C1IN-/SDA2/RP2/CN6/RB2
AN5/C1IN+/SCL2/RP3/CN7/RB3
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/PMA0/RA3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AN1/VREF-/CN3/RA1
AN0/VREF+/CN2/RA0
MCLR
VDD
VSS
AN9/RP15/CN11/PMCS1/RB15
AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14
MCLR
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
PGED1/AN2/C2IN-/RP0/CN4/RB0
PGEC1/AN3/C2IN+/RP1/CN5/RB1
AN4/C1IN-/SDA2/RP2/CN6/RB2
AN5/C1IN+/SCL2/RP3/CN7/RB3
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/PMA0/RA3
SOSCI/RP4/PMBE/CN1/RB4
SOSCO/T1CK/CN0/PMA1/RA4
VDD
PGED3/ASDA1/RP5/CN27/PMD7/RB5
PIC24FJXXGA002
28-Pin SPDIP, SSOP, SOIC
Legend:
Note 1:
DS39881E-page 2
RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins.
Back pad on QFN devices should be connected to Vss.
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Pin Diagrams (Continued)
44
43
42
41
40
39
38
37
36
35
34
SCL1/RP8/CN22/PMD4/RB8
RP7/INT0/CN23/PMD5/RB7
PGEC3/ASCL1/RP6/CN24/PMD6/RB6
PGED3/ASDA1/RP5/CN27/PMD7/RB5
VDD
VSS
RP21/CN26/PMA3/RC5
RP20/CN25/PMA4/RC4
RP19/CN28/PMBE/RC3
TDI/PMA9/RA9
SOSCO/T1CK/CN0/RA4
44-Pin QFN(1)
PIC24FJXXGA004
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
SOSCI/RP4/CN1/RB4
TDO/PMA8/RA8
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
VSS
VDD
AN8/RP18/CN10/PMA2/RC2
AN7/RP17/CN9/RC1
AN6/RP16/CN8/RC0
AN5/C1IN+/SCL2/RP3/CN7/RB3
AN4/C1IN-/SDA2/RP2/CN6/RB2
TMS/PMA10/RA10
TCK/PMA7/RA7
AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14
AN9/RP15/CN11/PMCS1/RB15
AVSS
AVDD
MCLR
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
PGED1/AN2/C2IN-/RP0/CN4/RB0
PGEC1/AN3/C2IN+/RP1/CN5/RB1
SDA1/RP9/CN21/PMD3/RB9
RP22/CN18/PMA1/RC6
RP23/CN17/PMA0/RC7
RP24/CN20/PMA5/RC8
RP25/CN19/PMA6/RC9
DISVREG
VCAP/VDDCORE
PGED2/RP10/CN16/PMD2/RB10
PGEC2/RP11/CN15/PMD1/RB11
AN12/RP12/CN14/PMD0/RB12
AN11/RP13/CN13/PMRD/RB13
Legend:
Note 1:
RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins.
Back pad on QFN devices should be connected to Vss.
2010-2013 Microchip Technology Inc.
DS39881E-page 3
PIC24FJ64GA004 FAMILY
Pin Diagrams (Continued)
44
43
42
41
40
39
38
37
36
35
34
SCL1/RP8/CN22/PMD4/RB8
RP7/INT0/CN23/PMD5/RB7
PGEC3/RP6/ASCL1/CN24/PMD6/RB6
PGED3/RP5/ASDA1/CN27/PMD7/RB5
VDD
VSS
RP21/CN26/PMA3/RC5
RP20/CN25/PMA4/RC4
RP19/CN28/PMBE/RC3
TDI/PMA9/RA9
SOSCO/T1CK/CN0/RA4
44-Pin TQFP
PIC24FJXXGA004
33
32
31
30
29
28
27
26
25
24
23
SOSCI/RP4/CN1/RB4
TDO/PMA8/RA8
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
VSS
VDD
AN8/RP18/CN10/PMA2/RC2
AN7/RP17/CN9/RC1
AN6/RP16/CN8/RC0
AN5/C1IN+/SCL2/RP3/CN7/RB3
AN4/C1IN-/SDA2/RP2/CN6/RB2
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
TMS/PMA10/RA10
TCK/PMA7/RA7
AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14
AN9/RP15/CN11/PMCS1/RB15
AVSS
AVDD
MCLR
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
PGED1/AN2/C2IN-/RP0/CN4/RB0
PGEC1/AN3/C2IN+/RP1/CN5/RB1
SDA1/RP9/CN21/PMD3/RB9
RP22/CN18/PMA1/RC6
RP23/CN17/PMA0/RC7
RP24/CN20/PMA5/RC8
RP25/CN19/PMA6/RC9
DISVREG
VCAP/VDDCORE
PGED2/RP10/CN16/PMD2/RB10
PGEC2/RP11/CN15/PMD1/RB11
AN12/RP12/CN14/PMD0/RB12
AN11/RP13/CN13/PMRD/RB13
Legend:
DS39881E-page 4
RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins.
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 17
3.0 CPU ........................................................................................................................................................................................... 23
4.0 Memory Organization ................................................................................................................................................................. 29
5.0 Flash Program Memory.............................................................................................................................................................. 47
6.0 Resets ........................................................................................................................................................................................ 53
7.0 Interrupt Controller ..................................................................................................................................................................... 59
8.0 Oscillator Configuration .............................................................................................................................................................. 95
9.0 Power-Saving Features............................................................................................................................................................ 103
10.0 I/O Ports ................................................................................................................................................................................... 105
11.0 Timer1 ..................................................................................................................................................................................... 125
12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 127
13.0 Input Capture............................................................................................................................................................................ 133
14.0 Output Compare....................................................................................................................................................................... 135
15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 141
16.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 151
17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 159
18.0 Parallel Master Port (PMP)....................................................................................................................................................... 167
19.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 177
20.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 189
21.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 193
22.0 Comparator Module.................................................................................................................................................................. 203
23.0 Comparator Voltage Reference................................................................................................................................................ 207
24.0 Special Features ...................................................................................................................................................................... 209
25.0 Development Support............................................................................................................................................................... 219
26.0 Instruction Set Summary .......................................................................................................................................................... 223
27.0 Electrical Characteristics .......................................................................................................................................................... 231
28.0 Packaging Information.............................................................................................................................................................. 251
Appendix A: Revision History............................................................................................................................................................. 267
Appendix B: Additional Guidance for PIC24FJ64GA004 Family Applications ................................................................................... 268
Index ................................................................................................................................................................................................. 269
The Microchip Web Site ..................................................................................................................................................................... 273
Customer Change Notification Service .............................................................................................................................................. 273
Customer Support .............................................................................................................................................................................. 273
Reader Response .............................................................................................................................................................................. 274
Product Identification System ............................................................................................................................................................ 275
2010-2013 Microchip Technology Inc.
DS39881E-page 5
PIC24FJ64GA004 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS39881E-page 6
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
•
•
•
•
•
•
•
•
PIC24FJ16GA002
PIC24FJ32GA002
PIC24FJ48GA002
PIC24FJ64GA002
PIC24FJ16GA004
PIC24FJ32GA004
PIC24FJ48GA004
PIC24FJ64GA004
This family introduces a new line of Microchip devices:
a 16-bit microcontroller family with a broad peripheral
feature set and enhanced computational performance.
The PIC24FJ64GA004 family offers a new migration
option for those high-performance applications which
may be outgrowing their 8-bit platforms, but don’t
require the numerical processing power of a digital
signal processor.
1.1
1.1.1
Core Features
16-BIT ARCHITECTURE
1.1.2
POWER-SAVING TECHNOLOGY
All of the devices in the PIC24FJ64GA004 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:
• On-the-Fly Clock Switching: The device clock
can be changed under software control to the
Timer1 source or the internal, low-power RC
oscillator during operation, allowing the user to
incorporate power-saving ideas into their software
designs.
• Doze Mode Operation: When timing-sensitive
applications, such as serial communications,
require the uninterrupted operation of peripherals,
the CPU clock speed can be selectively reduced,
allowing incremental power savings without
missing a beat.
• Instruction-Based Power-Saving Modes: The
microcontroller can suspend all operations, or
selectively shut down its core while leaving its
peripherals active, with a single instruction in
software.
1.1.3
OSCILLATOR OPTIONS AND
FEATURES
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® Digital Signal Controllers (DSCs). The PIC24F
CPU core offers a wide range of enhancements, such as:
All of the devices in the PIC24FJ64GA004 family offer
five different oscillator options, allowing users a range
of choices in developing application hardware. These
include:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• Linear addressing of up to 12 Mbytes (program
space) and 64 Kbytes (data)
• A 16-element working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages such as ‘C’
• Operational performance up to 16 MIPS
• Two Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes offering the option of a
divide-by-2 clock output.
• A Fast Internal Oscillator (FRC) with a nominal
8 MHz output, which can also be divided under
software control to provide clock speeds as low as
31 kHz.
• A Phase Lock Loop (PLL) frequency multiplier,
available to the External Oscillator modes and the
FRC oscillator, which allows clock speeds of up to
32 MHz.
• A separate internal RC oscillator (LPRC) with a
fixed 31 kHz output, which provides a low-power
option for timing-insensitive applications.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor. This
option constantly monitors the main clock source
against a reference signal provided by the internal
oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
2010-2013 Microchip Technology Inc.
DS39881E-page 7
PIC24FJ64GA004 FAMILY
1.1.4
EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between devices with
the same pin count, or even jumping from 28-pin to
44-pin devices.
The PIC24F family is pin-compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.
1.2
Other Special Features
• Communications: The PIC24FJ64GA004 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There are two independent I2C
modules that support both Master and Slave
modes of operation. Devices also have, through
the Peripheral Pin Select (PPS) feature, two
independent UARTs with built-in IrDA
encoder/decoders and two SPI modules.
• Peripheral Pin Select (PPS): The Peripheral Pin
Select feature allows most digital peripherals to
be mapped over a fixed set of digital I/O pins.
Users may independently map the input and/or
output of any one of the many digital peripherals
to any one of the I/O pins.
• Parallel Master/Enhanced Parallel Slave Port:
One of the general purpose I/O ports can be
reconfigured for enhanced parallel data communications. In this mode, the port can be configured
for both master and slave operations, and
supports 8-bit and 16-bit data transfers with up to
16 external address lines in Master modes.
• Real-Time Clock/Calendar (RTCC): This module
implements a full-featured clock and calendar with
alarm functions in hardware, freeing up timer
resources and program memory space for use of
the core application.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, as
well as faster sampling speeds.
DS39881E-page 8
1.3
Details on Individual Family
Members
Devices in the PIC24FJ64GA004 family are available
in 28-pin and 44-pin packages. The general block
diagram for all devices is shown in Figure 1-1.
The devices are differentiated from each other in two
ways:
1.
2.
3.
Flash program memory (64 Kbytes for
PIC24FJ64GA devices, 48 Kbytes for
PIC24FJ48GA devices, 32 Kbytes for
PIC24FJ32GA devices and 16 Kbytes for
PIC24FJ16GA devices).
Internal SRAM memory (4k for PIC24FJ16GA
devices, 8k for all other devices in the family).
Available I/O pins and ports (21 pins on 2 ports
for 28-pin devices and 35 pins on 3 ports for
44-pin devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1.
A list of the pin features that are available on the
PIC24FJ64GA004 family devices, sorted by function, is
shown in Table 1-2. Note that this table shows the pin
location of individual peripheral features and not how
they are multiplexed on the same pin. This information
is provided in the pinout diagrams in the beginning of
the data sheet. Multiplexed features are sorted by the
priority given to a feature, with the highest priority
peripheral being listed first.
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Operating Frequency
Program Memory (bytes)
64GA004
48GA004
32GA004
16GA004
64GA002
48GA002
Features
32GA002
DEVICE FEATURES FOR THE PIC24FJ64GA004 FAMILY
16GA002
TABLE 1-1:
DC – 32 MHz
16K
32K
48K
64K
16K
32K
48K
64K
Program Memory (instructions)
5,504
11,008
16,512
22,016
5,504
11,008
16,512
22,016
Data Memory (bytes)
4096
8192
Interrupt Sources
(soft vectors/NMI traps)
I/O Ports
Total I/O Pins
4096
8192
43
(39/4)
Ports A, B
Ports A, B, C
21
35
Timers:
5(1)
Total Number (16-bit)
32-Bit (from paired 16-bit timers)
2
Input Capture Channels
5(1)
Output Compare/PWM Channels
5(1)
Input Change Notification Interrupt
21
30
Serial Communications:
UART
2(1)
SPI (3-wire/4-wire)
2(1)
I2C™
2
Parallel Communications (PMP/PSP)
Yes
JTAG Boundary Scan
Yes
10-Bit Analog-to-Digital Module
(input channels)
10
Analog Comparators
Remappable Pins
Resets (and delays)
Instruction Set
Packages
Note 1:
13
2
16
26
POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode,
REPEAT Instruction, Hardware Traps, Configuration Word Mismatch
(PWRT, OST, PLL Lock)
76 Base Instructions, Multiple Addressing Mode Variations
28-Pin SPDIP/SSOP/SOIC/QFN
44-Pin QFN/TQFP
Peripherals are accessible through remappable pins.
2010-2013 Microchip Technology Inc.
DS39881E-page 9
PIC24FJ64GA004 FAMILY
FIGURE 1-1:
PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAM
Data Bus
Interrupt
Controller
16
16
8
16
Data Latch
PSV & Table
Data Access
Control Block
Data RAM
PCL
PCH
Program Counter
Repeat
Stack
Control
Control
Logic
Logic
23
Address
Latch
PORTA(1)
RA
16
23
16
Read AGU
Write AGU
Address Latch
PORTB
Program Memory
RB
Data Latch
16
EA MUX
24
Inst Latch
Literal Data
Address Bus
PORTC(1)
16
16
RC
Inst Register
RP(1)
Instruction
Decode &
Control
Control Signals
OSCO/CLKO
OSCI/CLKI
Timing
Generation
FRC/LPRC
Oscillators
DISVREG
RP
16 x 16
W Reg Array
Oscillator
Start-up Timer
16-Bit ALU
Power-on
Reset
Watchdog
Timer
Voltage
Regulator
BOR and
LVD(2)
Timer1
17x17
Multiplier
Power-up
Timer
Precision
Band Gap
Reference
VDDCORE/VCAP
Divide
Support
VDD, VSS
16
MCLR
Timer2/3(3)
Timer4/5(3)
RTCC
10-Bit
A/D
Comparators(3)
PMP/PSP
IC1-5(3)
Note 1:
2:
3:
PWM/
OC1-5(3)
CN1-22(1)
SPI1/2(3)
I2C1/2
UART1/2(3)
Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions.
BOR and LVD functionality is provided when the on-board voltage regulator is enabled.
Peripheral I/Os are accessible through remappable pins.
DS39881E-page 10
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 1-2:
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS
Pin Number
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
44-Pin
QFN/TQFP
I/O
Input
Buffer
2
27
19
I
ANA
AN1
3
28
20
I
ANA
AN2
4
1
21
I
ANA
AN3
5
2
22
I
ANA
AN4
6
3
23
I
ANA
Function
AN0
Description
A/D Analog Inputs.
AN5
7
4
24
I
ANA
AN6
—
—
25
I
ANA
AN7
—
—
26
I
ANA
AN8
—
—
27
I
ANA
AN9
26
23
15
I
ANA
AN10
25
22
14
I
ANA
AN11
24
21
11
I
ANA
AN12
23
20
10
I
ANA
ASCL1
15
12
42
I/O
I2C
Alternate I2C1 Synchronous Serial Clock Input/Output.(1)
2
ASDA1
14
11
41
I/O
I C
Alternate I2C2 Synchronous Serial Clock Input/Output. (1)
AVDD
—
—
17
P
—
Positive Supply for Analog Modules.
AVSS
—
—
16
P
—
Ground Reference for Analog Modules.
C1IN-
6
3
23
I
ANA
Comparator 1 Negative Input.
C1IN+
7
4
24
I
ANA
Comparator 1 Positive Input.
C2IN-
4
1
21
I
ANA
Comparator 2 Negative Input.
C2IN+
5
2
22
I
ANA
Comparator 2 Positive Input.
CLKI
9
6
30
I
ANA
CLKO
10
7
31
O
—
Legend:
Note 1:
Main Clock Input Connection.
System Clock Output.
TTL = TTL input buffer
ST = Schmitt Trigger input buffer
ANA = Analog level input/output
I2C™ = I2C/SMBus input buffer
Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
2010-2013 Microchip Technology Inc.
DS39881E-page 11
PIC24FJ64GA004 FAMILY
TABLE 1-2:
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
44-Pin
QFN/TQFP
I/O
Input
Buffer
CN0
12
9
34
I
ST
CN1
11
8
33
I
ST
CN2
2
27
19
I
ST
CN3
3
28
20
I
ST
CN4
4
1
21
I
ST
CN5
5
2
22
I
ST
CN6
6
3
23
I
ST
CN7
7
4
24
I
ST
CN8
—
—
25
I
ST
CN9
—
—
26
I
ST
Function
CN10
—
—
27
I
ST
CN11
26
23
15
I
ST
CN12
25
22
14
I
ST
CN13
24
21
11
I
ST
CN14
23
20
10
I
ST
CN15
22
19
9
I
ST
CN16
21
18
8
I
ST
CN17
—
—
3
I
ST
CN18
—
—
2
I
ST
CN19
—
—
5
I
ST
CN20
—
—
4
I
ST
CN21
18
15
1
I
ST
CN22
17
14
44
I
ST
CN23
16
13
43
I
ST
CN24
15
12
42
I
ST
CN25
—
—
37
I
ST
CN26
—
—
38
I
ST
CN27
14
11
41
I
ST
CN28
—
—
36
I
ST
CN29
10
7
31
I
ST
Description
Interrupt-on-Change Inputs.
CN30
9
6
30
I
ST
CVREF
25
22
14
O
ANA
DISVREG
19
16
6
I
ST
Voltage Regulator Disable.
INT0
16
13
43
I
ST
External Interrupt Input.
MCLR
1
26
18
I
ST
Master Clear (device Reset) Input. This line is brought low
to cause a Reset.
Legend:
Note 1:
Comparator Voltage Reference Output.
TTL = TTL input buffer
ST = Schmitt Trigger input buffer
ANA = Analog level input/output
I2C™ = I2C/SMBus input buffer
Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
DS39881E-page 12
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 1-2:
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
44-Pin
QFN/TQFP
I/O
Input
Buffer
Description
OSCI
9
6
30
I
ANA
Main Oscillator Input Connection.
OSCO
10
7
31
O
ANA
Main Oscillator Output Connection.
PGEC1
5
2
22
I/O
ST
PGEC2
22
19
9
I/O
ST
PGEC3
14
12
42
I/O
ST
PGED1
4
1
21
I/O
ST
PGED2
21
18
8
I/O
ST
PGED3
15
11
41
I/O
ST
PMA0
10
7
3
I/O
ST/TTL
Parallel Master Port Address Bit 0 Input (Buffered Slave
modes) and Output (Master modes).
PMA1
12
9
2
I/O
ST/TTL
Parallel Master Port Address Bit 1 Input (Buffered Slave
modes) and Output (Master modes).
PMA2
—
—
27
O
—
PMA3
—
—
38
O
—
PMA4
—
—
37
O
—
PMA5
—
—
4
O
—
PMA6
—
—
5
O
—
PMA7
—
—
13
O
—
PMA8
—
—
32
O
—
PMA9
—
—
35
O
—
PMA10
—
—
12
O
—
PMA11
—
—
—
O
—
PMA12
—
—
—
O
—
PMA13
—
—
—
O
—
In-Circuit Debugger/Emulator and ICSP™ Programming
Clock.
In-Circuit Debugger/Emulator and ICSP Programming
Data.
Parallel Master Port Address (Demultiplexed Master
modes).
PMBE
11
8
36
O
—
Parallel Master Port Byte Enable Strobe.
PMCS1
26
23
15
O
—
Parallel Master Port Chip Select 1 Strobe/Address Bit 14.
Parallel Master Port Data (Demultiplexed Master mode) or
Address/Data (Multiplexed Master modes).
PMD0
23
20
10
I/O
ST/TTL
PMD1
22
19
9
I/O
ST/TTL
PMD2
21
18
8
I/O
ST/TTL
PMD3
18
15
1
I/O
ST/TTL
PMD4
17
14
44
I/O
ST/TTL
PMD5
16
13
43
I/O
ST/TTL
PMD6
15
12
42
I/O
ST/TTL
PMD7
14
11
41
I/O
ST/TTL
PMRD
24
21
11
O
—
Parallel Master Port Read Strobe.
PMWR
25
22
14
O
—
Parallel Master Port Write Strobe.
Legend:
Note 1:
TTL = TTL input buffer
ST = Schmitt Trigger input buffer
ANA = Analog level input/output
I2C™ = I2C/SMBus input buffer
Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
2010-2013 Microchip Technology Inc.
DS39881E-page 13
PIC24FJ64GA004 FAMILY
TABLE 1-2:
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Input
Buffer
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
RA0
2
27
19
I/O
ST
RA1
3
28
20
I/O
ST
Function
44-Pin
QFN/TQFP
I/O
RA2
9
6
30
I/O
ST
RA3
10
7
31
I/O
ST
RA4
12
9
34
I/O
ST
RA7
—
—
13
I/O
ST
RA8
—
—
32
I/O
ST
RA9
—
—
35
I/O
ST
RA10
—
—
12
I/O
ST
RB0
4
1
21
I/O
ST
RB1
5
2
22
I/O
ST
RB2
6
3
23
I/O
ST
RB3
7
4
24
I/O
ST
RB4
11
8
33
I/O
ST
RB5
14
11
41
I/O
ST
RB6
15
12
42
I/O
ST
RB7
16
13
43
I/O
ST
RB8
17
14
44
I/O
ST
RB9
18
15
1
I/O
ST
RB10
21
18
8
I/O
ST
RB11
22
19
9
I/O
ST
RB12
23
20
10
I/O
ST
RB13
24
21
11
I/O
ST
RB14
25
22
14
I/O
ST
RB15
26
23
15
I/O
ST
RC0
—
—
25
I/O
ST
RC1
—
—
26
I/O
ST
RC2
—
—
27
I/O
ST
RC3
—
—
36
I/O
ST
RC4
—
—
37
I/O
ST
RC5
—
—
38
I/O
ST
RC6
—
—
2
I/O
ST
RC7
—
—
3
I/O
ST
RC8
—
—
4
I/O
ST
—
—
5
I/O
ST
RC9
Legend:
Note 1:
Description
PORTA Digital I/O.
PORTB Digital I/O.
PORTC Digital I/O.
TTL = TTL input buffer
ST = Schmitt Trigger input buffer
ANA = Analog level input/output
I2C™ = I2C/SMBus input buffer
Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
DS39881E-page 14
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 1-2:
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Input
Buffer
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
44-Pin
QFN/TQFP
I/O
RP0
4
1
21
I/O
ST
RP1
5
2
22
I/O
ST
RP2
6
3
23
I/O
ST
RP3
7
4
24
I/O
ST
RP4
11
8
33
I/O
ST
RP5
14
11
41
I/O
ST
RP6
15
12
42
I/O
ST
RP7
16
13
43
I/O
ST
RP8
17
14
44
I/O
ST
RP9
18
15
1
I/O
ST
RP10
21
18
8
I/O
ST
RP11
22
19
9
I/O
ST
RP12
23
20
10
I/O
ST
RP13
24
21
11
I/O
ST
RP14
25
22
14
I/O
ST
RP15
26
23
15
I/O
ST
RP16
—
—
25
I/O
ST
RP17
—
—
26
I/O
ST
RP18
—
—
27
I/O
ST
RP19
—
—
36
I/O
ST
RP20
—
—
37
I/O
ST
RP21
—
—
38
I/O
ST
RP22
—
—
2
I/O
ST
RP23
—
—
3
I/O
ST
RP24
—
—
4
I/O
ST
RP25
—
—
5
I/O
ST
RTCC
25
22
14
O
—
Real-Time Clock Alarm Output.
SCL1
17
14
44
I/O
I2C
I2C1 Synchronous Serial Clock Input/Output.
SCL2
7
4
24
I/O
I2C
I2C2 Synchronous Serial Clock Input/Output.
SDA1
18
15
1
I/O
I2C
I2C1 Data Input/Output.
Function
Description
Remappable Peripheral.
SDA2
6
3
23
I/O
I2C
SOSCI
11
8
33
I
ANA
Secondary Oscillator/Timer1 Clock Input.
12
9
34
O
ANA
Secondary Oscillator/Timer1 Clock Output.
SOSCO
Legend:
Note 1:
I2C2 Data Input/Output.
TTL = TTL input buffer
ST = Schmitt Trigger input buffer
ANA = Analog level input/output
I2C™ = I2C/SMBus input buffer
Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
2010-2013 Microchip Technology Inc.
DS39881E-page 15
PIC24FJ64GA004 FAMILY
TABLE 1-2:
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Function
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
44-Pin
QFN/TQFP
I/O
Input
Buffer
Description
T1CK
12
9
34
I
ST
Timer1 Clock.
TCK
17
14
13
I
ST
JTAG Test Clock Input.
TDI
21
18
35
I
ST
JTAG Test Data Input.
TDO
18
15
32
O
—
JTAG Test Data Output.
TMS
22
19
12
I
ST
JTAG Test Mode Select Input.
VDD
13, 28
10, 25
28, 40
P
—
Positive Supply for Peripheral Digital Logic and I/O Pins.
VDDCAP
20
17
7
P
—
External Filter Capacitor Connection (regulator enabled).
VDDCORE
20
17
7
P
—
Positive Supply for Microcontroller Core Logic (regulator
disabled).
VREF-
3
28
20
I
ANA
VREF+
2
27
19
I
ANA
8, 27
5, 24
29, 39
P
—
VSS
Legend:
Note 1:
A/D and Comparator Reference Voltage (low) Input.
A/D and Comparator Reference Voltage (high) Input.
Ground Reference for Logic and I/O Pins.
TTL = TTL input buffer
ST = Schmitt Trigger input buffer
ANA = Analog level input/output
I2C™ = I2C/SMBus input buffer
Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
DS39881E-page 16
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
MICROCONTROLLERS
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTIONS
C2(2)
• All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”)
• All AVDD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
• ENVREG/DISVREG and VCAP/VDDCORE pins
(PIC24F J devices only)
(see Section 2.4 “Voltage Regulator Pins
(ENVREG/DISVREG and VCAP/VDDCORE)”)
These pins must also be connected if they are being
used in the end application:
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for analog modules is implemented
Note:
VSS
VDD
R2
(1) (1)
(EN/DIS)VREG
MCLR
VCAP/VDDCORE
C1
C7
PIC24FJXXXX
VSS
VDD
VDD
VSS
C3(2)
C6(2)
C5(2)
VSS
The following pins must always be connected:
R1
VDD
Getting started with the PIC24FJ64GA004 family of
16-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.
VDD
AVSS
Basic Connection Requirements
AVDD
2.1
C4(2)
Key (all values are recommendations):
C1 through C6: 0.1 F, 20V ceramic
C7: 10 F, 6.3V or greater, tantalum or ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
Note 1:
2:
See Section 2.4 “Voltage Regulator Pins
(ENVREG/DISVREG and VCAP/VDDCORE)”
for an explanation of the ENVREG/DISVREG
pin connections.
The example shown is for a PIC24F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
The minimum mandatory connections are shown in
Figure 2-1.
2010-2013 Microchip Technology Inc.
DS39881E-page 17
PIC24FJ64GA004 FAMILY
2.2
2.2.1
Power Supply Pins
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including microcontrollers to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
DS39881E-page 18
2.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device functions:
device Reset, and device programming and debugging. If programming and debugging are not required
in the end application, a direct connection to VDD may
be all that is required. The addition of other components, to help increase the application’s resistance
to spurious Resets from voltage sags, may be
beneficial. A typical configuration is shown in
Figure 2-1. Other circuit designs may be implemented,
depending on the application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The
jumper is replaced for normal run-time operations.
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R1
R2
MCLR
JP
PIC24FXXXX
C1
Note 1:
2:
R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
R2 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
2.4
Designers may use Figure 2-3 to evaluate ESR
equivalence of candidate devices.
Voltage Regulator Pins
(ENVREG/DISVREG and
VCAP/VDDCORE)
Note:
This section applies only to PIC24F J
devices with an on-chip voltage regulator.
The on-chip voltage regulator enable/disable pin
(ENVREG or DISVREG, depending on the device
family) must always be connected directly to either a
supply voltage or to ground. The particular connection
is determined by whether or not the regulator is to be
used:
The placement of this capacitor should be close to
VCAP/VDDCORE. It is recommended that the trace
length not exceed 0.25 inch (6 mm). Refer to
Section 27.0 “Electrical Characteristics” for
additional information.
When the regulator is disabled, the VCAP/VDDCORE pin
must be tied to a voltage supply at the VDDCORE level.
Refer to Section 27.0 “Electrical Characteristics” for
information on VDD and VDDCORE.
FIGURE 2-3:
• For ENVREG, tie to VDD to enable the regulator,
or to ground to disable the regulator
• For DISVREG, tie to ground to enable the
regulator or to VDD to disable the regulator
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
10
Refer to Section 24.2 “On-Chip Voltage Regulator”
for details on connecting and using the on-chip
regulator.
ESR ()
1
When the regulator is enabled, a low-ESR (< 5Ω)
capacitor is required on the VCAP/VDDCORE pin to
stabilize the voltage regulator output voltage. The
VCAP/VDDCORE pin must not be connected to VDD and
must use a capacitor of 10 µF connected to ground. The
type can be ceramic or tantalum. Suitable examples of
capacitors are shown in Table 2-1. Capacitors with
equivalent specification can be used.
0.1
0.01
0.001
0.01
Note:
0.1
1
10
100
Frequency (MHz)
1000 10,000
Typical data measurement at 25°C, 0V DC bias.
.
TABLE 2-1:
SUITABLE CAPACITOR EQUIVALENTS
Make
Part #
Nominal
Capacitance
Base Tolerance
Rated Voltage
Temp. Range
TDK
C3216X7R1C106K
10 µF
±10%
16V
-55 to +125ºC
TDK
C3216X5R1C106K
10 µF
±10%
16V
-55 to +85ºC
Panasonic
ECJ-3YX1C106K
10 µF
±10%
16V
-55 to +125ºC
Panasonic
ECJ-4YB1C106K
10 µF
±10%
16V
-55 to +85ºC
Murata
GRM32DR71C106KA01L
10 µF
±10%
16V
-55 to +125ºC
Murata
GRM31CR61C106KC31L
10 µF
±10%
16V
-55 to +85ºC
2010-2013 Microchip Technology Inc.
DS39881E-page 19
PIC24FJ64GA004 FAMILY
CONSIDERATIONS FOR CERAMIC
CAPACITORS
In recent years, large value, low-voltage, surface-mount
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
physical size and other properties make ceramic
capacitors very attractive in many types of applications.
Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller. However,
some care is needed in selecting the capacitor to
ensure that it maintains sufficient capacitance over the
intended operating range of the application.
Typical low-cost, 10 F ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial tolerance specifications for these types of capacitors are
often specified as ±10% to ±20% (X5R and X7R), or
-20%/+80% (Y5V). However, the effective capacitance
that these capacitors provide in an application circuit will
also vary based on additional factors, such as the
applied DC bias voltage and the temperature. The total
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification.
The X5R and X7R capacitors typically exhibit satisfactory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer’s data
sheets for exact specifications). However, Y5V capacitors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme temperature tolerance, a 10 F nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum internal voltage regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
internal regulator if the application must operate over a
wide temperature range.
In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very significant, but is often overlooked or is not always
documented.
Typical DC bias voltage vs. capacitance graph for X7R
type capacitors is shown in Figure 2-4.
FIGURE 2-4:
Capacitance Change (%)
2.4.1
DC BIAS VOLTAGE vs.
CAPACITANCE
CHARACTERISTICS
10
0
-10
16V Capacitor
-20
-30
-40
10V Capacitor
-50
-60
-70
6.3V Capacitor
-80
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DC Bias Voltage (VDC)
When selecting a ceramic capacitor to be used with the
internal voltage regulator, it is suggested to select a
high-voltage rating, so that the operating voltage is a
small percentage of the maximum rated capacitor voltage. For example, choose a ceramic capacitor rated at
16V for the 2.5V or 1.8V core voltage. Suggested
capacitors are shown in Table 2-1.
2.5
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming (ICSP) and debugging purposes.
It is recommended to keep the trace length between
the ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGECx/PGEDx pins),
programmed into the device, matches the physical
connections for the ICSP to the Microchip
debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 25.0 “Development Support”.
DS39881E-page 20
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
2.6
External Oscillator Pins
FIGURE 2-5:
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency
secondary
oscillator
(refer to
Section 8.0 “Oscillator Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
Use a grounded copper pour around the oscillator
circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Layout suggestions are shown in Figure 2-5. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
In planning the application’s routing and I/O assignments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times
and other similar noise).
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design”
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
SUGGESTED
PLACEMENT OF THE
OSCILLATOR CIRCUIT
Single-Sided and In-line Layouts:
Copper Pour
(tied to ground)
Primary Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
OSCI
C1
`
OSCO
GND
C2
`
SOSCO
SOSC I
Secondary
Oscillator
Crystal
`
Sec Oscillator: C1
Sec Oscillator: C2
Fine-Pitch (Dual-Sided) Layouts:
Top Layer Copper Pour
(tied to ground)
Bottom Layer
Copper Pour
(tied to ground)
OSCO
C2
Oscillator
Crystal
GND
C1
OSCI
DEVICE PINS
2010-2013 Microchip Technology Inc.
DS39881E-page 21
PIC24FJ64GA004 FAMILY
2.7
Configuration of Analog and
Digital Pins During ICSP
Operations
If an ICSP compliant emulator is selected as a debugger, it automatically initializes all of the A/D input pins
(ANx) as “digital” pins. Depending on the particular
device, this is done by setting all bits in the ADnPCFG
register(s), or clearing all bit in the ANSx registers.
All PIC24F devices will have either one or more
ADnPCFG registers or several ANSx registers (one for
each port); no device will have both. Refer to
Section 21.0 “10-Bit High-Speed A/D Converter” for
more specific information.
The bits in these registers that correspond to the A/D
pins that initialized the emulator must not be changed
by the user application firmware; otherwise,
communication errors will result between the debugger
and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must modify the appropriate bits during
initialization of the A/D module, as follows:
• For devices with an ADnPCFG register, clear the
bits corresponding to the pin(s) to be configured
as analog. Do not change any other bits, particularly those corresponding to the PGECx/PGEDx
pair, at any time.
• For devices with ANSx registers, set the bits
corresponding to the pin(s) to be configured as
analog. Do not change any other bits, particularly
those corresponding to the PGECx/PGEDx pair,
at any time.
When a Microchip debugger/emulator is used as a
programmer, the user application firmware must
correctly configure the ADnPCFG or ANSx registers.
Automatic initialization of this register is only done
during debugger operation. Failure to correctly
configure the register(s) will result in all A/D pins being
recognized as analog input pins, resulting in the port
value being read as a logic ‘0’, which may affect user
application functionality.
2.8
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
DS39881E-page 22
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
3.0
Note:
CPU
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
“CPU” (DS39703).
The PIC24F CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M instructions of user program
memory space. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a
single cycle, with the exception of instructions that
change the program flow, the double-word move
(MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using
the REPEAT instructions, which are interruptible at any
point.
PIC24F devices have sixteen, 16-bit working registers
in the programmer’s model. Each of the working
registers can act as a data, address or address offset
register. The 16th working register (W15) operates as
a Software Stack Pointer for interrupts and calls.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K word boundary defined by the 8-bit Program Space
Visibility Page Address (PSVPAG) register. The program
to data space mapping feature lets any instruction
access program space as if it were data space.
The Instruction Set Architecture (ISA) has been
significantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are
supported, either directly, or through simple macros.
Many of the ISA enhancements have been driven by
compiler efficiency needs.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working register (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, three parameter instructions can be supported,
allowing trinary operations (that is, A + B = C) to be
executed in a single cycle.
A high-speed, 17-bit by 17-bit multiplier has been
included to significantly enhance the core arithmetic
capability and throughput. The multiplier supports
Signed, Unsigned and Mixed mode, 16-bit by 16-bit or
8-bit by 8-bit, integer multiplication. All multiply
instructions execute in a single cycle.
The 16-bit ALU has been enhanced with integer divide
assist hardware that supports an iterative non-restoring
divide algorithm. It operates in conjunction with the
REPEAT instruction looping mechanism and a selection
of iterative divide instructions to support 32-bit (or
16-bit), divided by 16-bit, integer signed and unsigned
division. All divide operations require 19 cycles to
complete, but are interruptible at any cycle boundary.
The PIC24F has a vectored exception scheme with up
to 8 sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to
one of seven priority levels.
A “block diagram of the CPU is shown in Figure 3-1.
3.1
Programmer’s Model
The programmer’s model for the PIC24F is shown in
Figure 3-2. All registers in the programmer’s model are
memory mapped and can be manipulated directly by
instructions. A description of each register is provided
in Table 3-1. All registers associated with the
programmer’s model are memory mapped.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct and three groups of addressing
modes. All modes support Register Direct and various
Register Indirect modes. Each group offers up to seven
addressing modes. Instructions are associated with
predefined addressing modes depending upon their
functional requirements.
2010-2013 Microchip Technology Inc.
DS39881E-page 23
PIC24FJ64GA004 FAMILY
FIGURE 3-1:
PIC24F CPU CORE BLOCK DIAGRAM
PSV & Table
Data Access
Control Block
Data Bus
Interrupt
Controller
16
8
16
16
Data Latch
23
23
PCH
PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
16
Data RAM
Address
Latch
23
16
RAGU
WAGU
Address Latch
Program Memory
EA MUX
Address Bus
ROM Latch
24
Instruction
Decode &
Control
Control Signals
to Various Blocks
16
Instruction Reg
Hardware
Multiplier
Divide
Support
16
Literal Data
Data Latch
16 x 16
W Register Array
16
16-Bit ALU
16
To Peripheral Modules
DS39881E-page 24
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 3-1:
CPU CORE REGISTERS
Register(s) Name
Description
W0 through W15
Working Register Array
PC
23-Bit Program Counter
SR
ALU STATUS Register
SPLIM
Stack Pointer Limit Value Register
TBLPAG
Table Memory Page Address Register
PSVPAG
Program Space Visibility Page Address Register
RCOUNT
Repeat Loop Counter Register
CORCON
CPU Control Register
FIGURE 3-2:
PROGRAMMER’S MODEL
15
Divider Working Registers
0
W0 (WREG)
W1
W2
Multiplier Registers
W3
W4
W5
W6
W7
Working/Address
Registers
W8
W9
W10
W11
W12
W13
W14
Frame Pointer
W15
Stack Pointer
0
SPLIM
0
22
0
0
PC
7
0
TBLPAG
7
0
PSVPAG
15
0
RCOUNT
SRH
SRL
— — — — — — — DC
IPL
RA N OV Z C
2 1 0
15
15
Stack Pointer Limit
Value Register
Program Counter
Table Memory Page
Address Register
Program Space Visibility
Page Address Register
Repeat Loop Counter
Register
0
ALU STATUS Register (SR)
0
— — — — — — — — — — — — IPL3 PSV — —
CPU Control Register (CORCON)
Registers or bits shadowed for PUSH.S and POP.S instructions.
2010-2013 Microchip Technology Inc.
DS39881E-page 25
PIC24FJ64GA004 FAMILY
3.2
CPU Control Registers
REGISTER 3-1:
SR: ALU STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
DC
bit 15
bit 8
R/W-0(1)
IPL2
R/W-0(1)
(2)
IPL1
(2)
R/W-0(1)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
IPL0(2)
RA
N
OV
Z
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8
DC: ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th or 8th low-order bit of the result has occurred
bit 7-5
IPL: CPU Interrupt Priority Level Status bits(1,2)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3
N: ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2
OV: ALU Overflow bit
1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0 = No overflow has occurred
bit 1
Z: ALU Zero bit
1 = An operation which effects the Z bit has set it at some time in the past
0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)
bit 0
C: ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
The IPL Status bits are read-only when NSTDIS (INTCON1) = 1.
The IPL Status bits are concatenated with the IPL3 bit (CORCON) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
DS39881E-page 26
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 3-2:
CORCON: CPU CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R/C-0
R/W-0
U-0
U-0
—
—
—
—
IPL3(1)
PSV
—
—
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-4
Unimplemented: Read as ‘0’
bit 3
IPL3: CPU Interrupt Priority Level Status bit(1)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
bit 2
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space is visible in data space
0 = Program space is not visible in data space
bit 1-0
Unimplemented: Read as ‘0’
Note 1:
3.3
x = Bit is unknown
User interrupts are disabled when IPL3 = 1.
Arithmetic Logic Unit (ALU)
The PIC24F ALU is 16 bits wide, and is capable of addition, subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are 2’s
complement in nature. Depending on the operation, the
ALU may affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
2010-2013 Microchip Technology Inc.
The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a
dedicated hardware multiplier and support hardware
for 16-bit divisor division.
3.3.1
MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit
multiplier. It supports unsigned, signed or mixed sign
operation in several multiplication modes:
1.
2.
3.
4.
5.
6.
7.
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
DS39881E-page 27
PIC24FJ64GA004 FAMILY
3.3.2
DIVIDER
3.3.3
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1.
2.
3.
4.
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn), and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
TABLE 3-2:
Instruction
MULTI-BIT SHIFT SUPPORT
The PIC24F ALU supports both single bit and
single-cycle, multi-bit arithmetic and logic shifts.
Multi-bit shifts are implemented using a shifter block,
capable of performing up to a 15-bit arithmetic right
shift, or up to a 15-bit left shift, in a single cycle. All
multi-bit shift instructions only support Register Direct
Addressing for both the operand source and result
destination.
A full summary of instructions that use the shift
operation is provided below in Table 3-2.
INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION
Description
ASR
Arithmetic shift right source register by one or more bits.
SL
Shift left source register by one or more bits.
LSR
Logical shift right source register by one or more bits.
DS39881E-page 28
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
4.0
MEMORY ORGANIZATION
As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory
spaces and buses. This architecture also allows the
direct access of program memory from the data space
during code execution.
4.1
Program Address Space
The program address memory space of the
PIC24FJ64GA004 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
FIGURE 4-1:
from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space
remapping, as described in Section 4.3 “Interfacing
Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations which use TBLPAG to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24FJ64GA004 family of
devices are shown in Figure 4-1.
PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES
PIC24FJ16GA
PIC24FJ32GA
PIC24FJ48GA
PIC24FJ64GA
GOTO Instruction
Reset Address
Interrupt Vector Table
GOTO Instruction
Reset Address
Interrupt Vector Table
GOTO Instruction
Reset Address
Interrupt Vector Table
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Reserved
Reserved
Reserved
Alternate Vector Table
Alternate Vector Table
Alternate Vector Table
Alternate Vector Table
User Flash
Program Memory
(5.5K instructions)
Flash Config Words
User Memory Space
User Flash
Program Memory
(11K instructions)
User Flash
Program Memory
(16K instructions)
User Flash
Program Memory
(22K instructions)
0057FEh
005800h
0083FEh
008400h
Flash Config Words
Unimplemented
Read ‘0’
0000FEh
000100h
000104h
0001FEh
000200h
002BFEh
002C00h
Flash Config Words
Unimplemented
Read ‘0’
000000h
000002h
000004h
Flash Config Words
Unimplemented
Read ‘0’
00ABFEh
00AC00h
Unimplemented
Read ‘0’
Configuration Memory Space
7FFFFFh
800000h
Reserved
Reserved
Reserved
Reserved
Device Config Registers
Device Config Registers
Device Config Registers
Device Config Registers
Reserved
Reserved
Reserved
Reserved
DEVID (2)
DEVID (2)
DEVID (2)
DEVID (2)
F7FFFEh
F80000h
F8000Eh
F80010h
FEFFFEh
FF0000h
FFFFFFh
Note:
Memory areas are not shown to scale.
2010-2013 Microchip Technology Inc.
DS39881E-page 29
PIC24FJ64GA004 FAMILY
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.3
In PIC24FJ64GA004 family devices, the top two words
of on-chip program memory are reserved for configuration information. On device Reset, the configuration
information is copied into the appropriate Configuration
registers. The addresses of the Flash Configuration
Word for devices in the PIC24FJ64GA004 family are
shown in Table 4-1. Their location in the memory map
is shown with the other memory vectors in Figure 4-1.
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 4-2).
The Configuration Words in program memory are a
compact format. The actual Configuration bits are
mapped in several different registers in the configuration
memory space. Their order in the Flash Configuration
Words does not reflect a corresponding arrangement in
the configuration space. Additional details on the device
Configuration Words are provided in Section 24.1
“Configuration Bits”.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
4.1.2
HARD MEMORY VECTORS
TABLE 4-1:
All PIC24F devices reserve the addresses between
00000h and 000200h for hard-coded program execution vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h with
the actual address for the start of code at 000002h.
msw
Address
PIC24FJ16GA
5.5
002BFCh:
002BFEh
PIC24FJ32GA
11
0057FCh:
0057FEh
PIC24FJ48GA
16
0083FCh:
0083FEh
PIC24FJ64GA
22
00ABFCh:
00ABFEh
least significant word
most significant word
16
8
PC Address
(lsw Address)
0
000000h
000002h
000004h
000006h
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
DS39881E-page 30
Configuration
Word
Addresses
PROGRAM MEMORY ORGANIZATION
23
000001h
000003h
000005h
000007h
FLASH CONFIGURATION
WORDS FOR PIC24FJ64GA004
FAMILY DEVICES
Program
Memory
(K words)
Device
PIC24F devices also have two Interrupt Vector Tables
(IVT), located from 000004h to 0000FFh and 000100h
to 0001FFh. These vector tables allow each of the
many device interrupt sources to be handled by separate ISRs. A more detailed discussion of the Interrupt
Vector Tables is provided in Section 7.1 “Interrupt
Vector Table”.
FIGURE 4-2:
FLASH CONFIGURATION WORDS
Instruction Width
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
4.2
Data Address Space
The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The
data space is accessed using two Address Generation
Units (AGUs), one each for read and write operations.
The data space memory map is shown in Figure 4-3.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This gives a data space address range of 64 Kbytes or
32K words. The lower half of the data memory space
(that is, when EA = 0) is used for implemented
memory addresses, while the upper half (EA = 1) is
reserved for the Program Space Visibility (PSV) area
(see Section 4.3.3 “Reading Data From Program
Memory Using Program Space Visibility”).
PIC24FJ64GA004 family devices implement a total of
8 Kbytes of data memory. Should an EA point to a
location outside of this area, an all zero word or byte will
be returned.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in
byte-addressable, 16-bit wide blocks. Data is aligned
in data memory and registers as 16-bit words, but all
data space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
DATA SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES(1)
FIGURE 4-3:
MSB
Address
0001h
07FFh
0801h
Implemented
Data RAM
MSB
LSB
SFR Space
LSB
Address
0000h
07FEh
0800h
Near
Data Space
Data RAM
1FFFh
2001h
27FFh(2)
2801h
SFR
Space
1FFEh
2000h
27FEh(2)
2800h
Unimplemented
Read as ‘0’
7FFFh
8001h
7FFFh
8000h
Program Space
Visibility Area
FFFFh
Note 1:
2:
FFFEh
Data memory areas are not shown to scale.
Upper memory limit for PIC24FJ16GAXXX devices is 17FFh.
2010-2013 Microchip Technology Inc.
DS39881E-page 31
PIC24FJ64GA004 FAMILY
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
A Sign-Extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
Zero-Extend (ZE) instruction on the appropriate
address.
To maintain backward compatibility with PIC® devices
and improve data space memory usage efficiency, the
PIC24F instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
Effective Address (EA) calculations are internally scaled
to step through word-aligned memory. For example, the
core recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] will result in a value of Ws + 1
for byte operations and Ws + 2 for word operations.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions operate only on words.
4.2.3
The 8-Kbyte area between 0000h and 1FFFh is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions. The
remainder of the data space is addressable indirectly.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing with a 16-bit address field.
Data byte reads will read the complete word which contains the byte, using the LSb of any EA to determine
which byte to select. The selected byte is placed onto
the LSB of the data path. That is, data memory and registers are organized as two parallel, byte-wide entities
with shared (word) address decode but separate write
lines. Data byte writes only write to the corresponding
side of the array or register which matches the byte
address.
4.2.4
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed; if it occurred on
a write, the instruction will be executed but the write will
not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine
state prior to execution of the address Fault.
SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0000h
to 07FFh, are primarily occupied with Special Function
Registers (SFRs). These are used by the PIC24F core
and peripheral modules for controlling the operation of
the device.
SFRs are distributed among the modules that they
control and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A diagram of the SFR space,
showing where SFRs are actually implemented, is
shown in Table 4-2. Each implemented area indicates
a 32-byte region where at least one address is implemented as an SFR. A complete listing of implemented
SFRs, including their addresses, is shown in Tables 4-3
through 4-24.
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
TABLE 4-2:
NEAR DATA SPACE
IMPLEMENTED REGIONS OF SFR DATA SPACE
SFR Space Address
xx00
xx20
xx60
Core
000h
Timers
100h
200h
xx40
I2C™
ICN
—
Capture
UART
A/D
300h
xx80
SPI
xxA0
xxC0
xxE0
Interrupts
Compare
—
—
—
—
—
—
I/O
—
—
—
—
—
—
400h
—
—
—
—
—
—
—
—
500h
—
—
—
—
—
—
—
—
600h
PMP
RTC/Comp
CRC
—
700h
—
—
System
NVM/PMD
—
—
—
—
PPS
Legend: — = No implemented SFRs in this block
DS39881E-page 32
2010-2013 Microchip Technology Inc.
2010-2013 Microchip Technology Inc.
TABLE 4-3:
File
Name
CPU CORE REGISTERS MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
WREG0
0000
Working Register 0
0000
WREG1
0002
Working Register 1
0000
WREG2
0004
Working Register 2
0000
WREG3
0006
Working Register 3
0000
WREG4
0008
Working Register 4
0000
WREG5
000A
Working Register 5
0000
WREG6
000C
Working Register 6
0000
WREG7
000E
Working Register 7
0000
WREG8
0010
Working Register 8
0000
WREG9
0012
Working Register 9
0000
WREG10
0014
Working Register 10
0000
WREG11
0016
Working Register 11
0000
0018
Working Register 12
0000
001A
Working Register 13
0000
WREG14
001C
Working Register 14
0000
WREG15
001E
Working Register 15
0800
SPLIM
0020
Stack Pointer Limit Value Register
xxxx
PCL
002E
Program Counter Low Byte Register
0000
PCH
0030
—
—
—
—
—
—
—
—
Program Counter Register High Byte
0000
TBLPAG
0032
—
—
—
—
—
—
—
—
Table Memory Page Address Register
0000
PSVPAG
0034
—
—
—
—
—
—
—
—
Program Space Visibility Page Address Register
RCOUNT
0036
SR
0042
—
—
—
—
—
—
—
DC
IPL2
IPL1
IPL0
RA
N
OV
Z
C
0000
CORCON
0044
—
—
—
—
—
—
—
—
—
—
—
—
IPL3
PSV
—
—
0000
DISICNT
0052
—
—
Legend:
xxxx
Disable Interrupts Counter Register
xxxx
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-4:
ICN REGISTER MAP
DS39881E-page 33
File
Addr
Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
CNEN1 0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE(1)
CN9IE(1)
CN27IE
(1)
CNEN2 0062
—
CNPU2 006A
—
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
CN8IE(1)
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
CN24IE
CN23IE
CN22IE
CN21IE
CN20IE(1)
CN19IE(1)
CN18IE(1)
CN17IE(1)
CN16IE
0000
CN11PUE CN10PUE(1) CN9PUE(1) CN8PUE(1) CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
0000
CN30PUE CN29PUE CN28PUE(1) CN27PUE CN26PUE(1) CN25PUE(1) CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE(1) CN19PUE(1) CN18PUE(1) CN17PUE(1) CN16PUE
0000
CN30IE
CN29IE
CNPU1 0068 CN15PUE CN14PUE CN13PUE
Legend:
Note 1:
0000
Repeat Loop Counter Register
(1)
CN28IE
CN12PUE
CN26IE
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These bits are not available on 28-pin devices; read as ‘0’.
(1)
CN25IE
PIC24FJ64GA004 FAMILY
WREG12
WREG13
File
Name
INTERRUPT CONTROLLER REGISTER MAP
2010-2013 Microchip Technology Inc.
Bit 0
All
Resets
OSCFAIL
—
0000
INT1EP
INT0EP
0000
OC1IF
IC1IF
INT0IF
0000
CNIF
CMIF
MI2C1IF
SI2C1IF
0000
—
—
—
SPI2IF
SPF2IF
0000
—
—
—
MI2C2IF
SI2C2IF
—
0000
—
—
—
CRCIF
U2ERIF
U1ERIF
—
0000
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000
—
—
—
—
INT1IE
CNIE
CMIE
MI2C1IE
SI2C1IE
0000
OC5IE
—
IC5IE
IC4IE
IC3IE
—
—
—
SPI2IE
SPF2IE
0000
—
—
—
—
—
—
—
—
MI2C2IE
SI2C2IE
—
0000
—
—
—
LVDIE
—
—
—
—
CRCIE
U2ERIE
U1ERIE
—
0000
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
—
—
—
4444
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPF1IP2
SPF1IP1
SPF1IP0
—
T3IP2
T3IP1
T3IP0
4444
—
—
—
—
—
—
—
—
—
AD1IP2
AD1IP1
AD1IP0
—
U1TXIP2
U1TXIP1
U1TXIP0
4444
00AC
—
CNIP2
CNIP1
CNIP0
—
CMIP2
CMIP1
CMIP0
—
MI2C1P2
MI2C1P1
MI2C1P0
—
SI2C1P2
SI2C1P1
SI2C1P0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
4444
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
—
—
—
4444
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
00B4
—
—
—
—
—
—
—
—
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPF2IP2
SPF2IP1
SPF2IP0
4444
IPC9
00B6
—
IC5IP2
IC5IP1
IC5IP0
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
—
—
—
4444
IPC10
00B8
—
—
—
—
—
—
—
—
—
OC5IP2
OC5IP1
OC5IP0
—
—
—
—
4444
IPC11
00BA
—
—
—
—
—
—
—
—
—
PMPIP2
PMPIP1
PMPIP0
—
—
—
—
4444
IPC12
00BC
—
—
—
—
—
MI2C2P2
MI2C2P1
MI2C2P0
—
SI2C2P2
SI2C2P1
SI2C2P0
—
—
—
—
4444
IPC15
00C2
—
—
—
—
—
RTCIP2
RTCIP1
RTCIP0
—
—
—
—
—
—
—
—
4444
IPC16
00C4
—
CRCIP2
CRCIP1
CRCIP0
—
U2ERIP2
U2ERIP1
U2ERIP0
—
U1ERIP2
U1ERIP1
U1ERIP0
—
—
—
—
4444
IPC18
00C8
—
—
—
—
—
—
—
—
—
—
—
—
—
LVDIP2
LVDIP1
LVDIP0
4444
CPUIRQ
—
VHOLD
—
ILR3
ILR2
ILR1
ILR0
—
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
INTCON1
0080
INTCON2
0082
IFS0
Bit 2
Bit 1
NSTDIS
—
—
—
—
—
—
—
—
—
—
ALTIVT
DISI
—
—
—
—
—
—
—
—
—
—
—
STKERR
INT2EP
0084
—
—
AD1IF
U1TXIF
U1RXIF
SPI1IF
SPF1IF
T3IF
T2IF
OC2IF
IC2IF
—
T1IF
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
—
—
—
—
INT1IF
IFS2
0088
—
—
PMPIF
—
—
—
OC5IF
—
IC5IF
IC4IF
IC3IF
IFS3
008A
—
RTCIF
—
—
—
—
—
—
—
—
IFS4
008C
—
—
—
—
—
—
—
LVDIF
—
IEC0
0094
—
—
AD1IE
U1TXIE
U1RXIE
SPI1IE
SPF1IE
T3IE
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
IEC2
0098
—
—
PMPIE
—
—
—
IEC3
009A
—
RTCIE
—
—
—
IEC4
009C
—
—
—
—
IPC0
00A4
—
T1IP2
T1IP1
IPC1
00A6
—
T2IP2
IPC2
00A8
—
IPC3
00AA
IPC4
INTTREG 00E0
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 4
Bit 3
MATHERR ADDRERR
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
PIC24FJ64GA004 FAMILY
DS39881E-page 34
TABLE 4-5:
2010-2013 Microchip Technology Inc.
TABLE 4-6:
File Name
Addr
TIMER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
TMR1
0100
Timer1 Register
PR1
0102
Timer1 Period Register
T1CON
0104
TON
—
TSIDL
—
—
—
—
—
—
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
FFFF
TGATE
TCKPS1
TCKPS0
—
TSYNC
TCS
—
0000
TMR2
0106
Timer2 Register
0000
TMR3HLD
0108
Timer3 Holding Register (for 32-bit timer operations only)
0000
TMR3
010A
Timer3 Register
0000
PR2
010C
Timer2 Period Register
FFFF
PR3
010E
Timer3 Period Register
T2CON
0110
TON
—
TSIDL
—
—
—
—
T3CON
0112
TON
—
TSIDL
—
—
—
—
TMR4
0114
Timer4 Register
0000
TMR5HLD
0116
Timer5 Holding Register (for 32-bit operations only)
0000
FFFF
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
0000
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
0000
0118
Timer5 Register
0000
PR4
011A
Timer4 Period Register
FFFF
PR5
011C
Timer5 Period Register
T4CON
011E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
0000
0120
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
0000
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
T5CON
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-7:
File
Name
Addr
IC1BUF
0140
IC1CON
0142
IC2BUF
0144
IC2CON
0146
IC3BUF
0148
DS39881E-page 35
IC3CON
014A
IC4BUF
014C
IC4CON
014E
IC5BUF
0150
IC5CON
Legend:
FFFF
0152
INPUT CAPTURE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
—
ICSIDL
—
—
—
—
Input Capture 1 Register
—
ICTMR
FFFF
Input Capture 2 Register
—
—
ICSIDL
—
—
—
—
—
ICTMR
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
Input Capture 3 Register
—
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
—
—
ICSIDL
—
—
—
—
—
ICTMR
0000
FFFF
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
Input Capture 5 Register
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
FFFF
Input Capture 4 Register
—
0000
FFFF
0000
FFFF
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
PIC24FJ64GA004 FAMILY
TMR5
OUTPUT COMPARE REGISTER MAP
File
Name
Addr
OC1RS
0180
Output Compare 1 Secondary Register
OC1R
0182
Output Compare 1 Register
OC1CON
0184
OC2RS
0186
Output Compare 2 Secondary Register
OC2R
0188
Output Compare 2 Register
OC2CON
018A
OC3RS
018C
Output Compare 3 Secondary Register
OC3R
018E
Output Compare 3 Register
OC3CON
0190
OC4RS
0192
Output Compare 4 Secondary Register
OC4R
0194
Output Compare 4 Register
OC4CON
0196
OC5RS
0198
Output Compare 5 Secondary Register
OC5R
019A
Output Compare 5 Register
OC5CON
019C
Legend:
Bit 15
—
—
—
—
—
Bit 14
—
—
—
—
—
Bit 13
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
Bit 12
—
—
—
—
—
Bit 11
—
—
—
—
—
Bit 10
—
—
—
—
—
Bit 9
Bit 8
—
—
—
—
—
—
—
—
Bit 7
—
—
—
—
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FFFF
FFFF
—
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
0000
FFFF
FFFF
—
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
0000
FFFF
FFFF
—
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
0000
FFFF
FFFF
—
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
0000
FFFF
FFFF
—
—
—
—
—
Bit 7
Bit 6
Bit 5
OCFLT
OCTSEL
OCM2
OCM1
OCM0
Bit 2
Bit 1
Bit 0
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-9:
I2C™ REGISTER MAP
2010-2013 Microchip Technology Inc.
File
Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C1RCV
0200
—
—
—
—
—
—
—
—
I2C1 Receive Register
0000
I2C1TRN
0202
—
—
—
—
—
—
—
—
I2C1 Transmit Register
00FF
I2C1BRG
0204
—
—
—
—
—
—
—
I2C1CON
0206
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C1STAT
0208
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
AMSK7
AMSK6
AMSK3
AMSK2
AMSK1
AMSK0
Bit 4
Bit 3
Baud Rate Generator Register 1
All
Resets
0000
I2C1ADD
020A
—
—
—
—
—
—
I2C1MSK
020C
—
—
—
—
—
—
AMSK9
AMSK8
I2C2RCV
0210
—
—
—
—
—
—
—
—
I2C2 Receive Register
0000
I2C2TRN
0212
—
—
—
—
—
—
—
—
I2C2 Transmit Register
00FF
I2C2BRG
0214
—
—
—
—
—
—
—
I2C2CON
0216
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C2STAT
0218
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
I2C2ADD
021A
—
—
—
—
—
—
I2C2MSK
021C
—
—
—
—
—
—
AMSK9
AMSK8
AMSK7
AMSK6
AMSK3
AMSK2
AMSK1
AMSK0
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
I2C1 Address Register
AMSK5
AMSK4
0000
Baud Rate Generator Register 2
0000
I2C2 Address Register
AMSK5
AMSK4
0000
0000
0000
PIC24FJ64GA004 FAMILY
DS39881E-page 36
TABLE 4-8:
2010-2013 Microchip Technology Inc.
TABLE 4-10:
File
Name
Addr
UART REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
—
UTXBRK
UTXEN
UTXBF
TRMT
—
UTX8
UTX7
—
URX8
URX7
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1 UTXINV UTXISEL0
U1TXREG
0224
—
—
—
—
—
—
U1RXREG
0226
—
—
—
—
—
—
U1BRG
0228
U2MODE
0230
UARTEN
U2STA
0232
UTXISEL1 UTXINV UTXISEL0
U2TXREG
0234
—
—
—
U2RXREG
0236
—
—
—
U2BRG
0238
Legend:
Bit 8
Bit 7
Bit 6
WAKE
LPBACK
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
ABAUD
RXINV
BRGH
PDSEL1
PDSEL0
STSEL
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
UTX6
UTX5
UTX4
UTX3
UTX2
UTX1
UTX0
0000
URX6
URX5
URX4
URX3
URX2
URX1
URX0
0000
ABAUD
RXINV
BRGH
PDSEL1
PDSEL0
STSEL
0000
URXISEL1 URXISEL0
Baud Rate Generator Prescaler Register
—
USIDL
WAKE
LPBACK
0000
IREN
RTSMD
—
UEN1
UEN0
—
UTXBRK
UTXEN
UTXBF
TRMT
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
UTX8
UTX7
UTX6
UTX5
UTX4
UTX3
UTX2
UTX1
UTX0
0000
—
—
—
—
URX8
URX7
URX6
URX5
URX4
URX3
URX2
URX1
URX0
0000
URXISEL1 URXISEL0
Baud Rate Generator Prescaler
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-11:
SPI REGISTER MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
SPI1STAT
0240
SPIEN
—
SPISIDL
—
—
SPI1CON1
0242
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE
SPI1CON2
0244
FRMEN
SPIFSD
SPIFPOL
—
—
—
—
—
SPI1BUF
0248
SPI2STAT
0260
SPIEN
—
SPISIDL
—
—
SPIBEC2 SPIBEC1 SPIBEC0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
SPITBF
SPIRBF
0000
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
0000
—
—
—
—
—
—
SPIFE
SPIBEN
0000
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
SPITBF
SPIRBF
0000
SPI1 Transmit/Receive Buffer
SPIBEC2 SPIBEC1 SPIBEC0
0000
SPI2CON1
0262
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
0000
SPI2CON2
0264
FRMEN
SPIFSD
SPIFPOL
—
—
—
—
—
—
—
—
—
—
—
SPIFE
SPIBEN
0000
SPI2BUF
Legend:
0268
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SPI2 Transmit/Receive Buffer
0000
DS39881E-page 37
PIC24FJ64GA004 FAMILY
File
Name
Bit 9
File
Name
TRISA
PORTA REGISTER MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
02C0
—
—
—
—
—
Bit 10
Bit 9
Bit 8
Bit 7
TRISA10(1) TRISA9(1) TRISA8(1) TRISA7(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TRISA3(2) TRISA2(3)
Bit 1
Bit 0
All
Resets
079F
—
—
TRISA4
TRISA1
TRISA0
RA9(1)
RA8(1)
RA7(1)
—
—
RA4
RA3(2)
RA2(3)
RA1
RA0
0000
PORTA
02C2
—
—
—
—
—
RA10(1)
LATA
02C4
—
—
—
—
—
LATA10(1)
LATA9(1)
LATA8(1)
LATA7(1)
—
—
LATA4
LATA3(2)
LATA2(3)
LATA1
LATA0
0000
ODCA
02C6
—
—
—
—
—
ODA10(1)
ODA9(1)
ODA8(1)
ODA7(1)
—
—
ODA4
ODA3(2)
ODA2(3)
ODA1
ODA0
0000
Legend:
Note 1:
2:
3:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These bits are not available on 28-pin devices; read as ‘0’.
These bits are only available when the primary oscillator is disabled (POSCMD = 00); otherwise, read as ‘0’.
These bits are only available when the primary oscillator is disabled or EC mode is selected (POSCMD = 00 or 11) and CLKO is disabled (OSCIOFNC = 0); otherwise, read as ‘0’.
TABLE 4-13:
File
Name
Addr
PORTB REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISB
02C8
TRISB10
TRISB9
TRISB8
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
FFFF
PORTB
02CA
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
0000
LATB
02CC
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
0000
ODCB
02CE
ODB15
ODB14
ODB13
ODB12
ODB11
ODB10
ODB9
ODB8
ODB7
ODB6
ODB5
ODB4
ODB3
ODB2
ODB1
ODB0
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-14:
File
Name
TRISB15 TRISB14 TRISB13 TRISB12 TRISB11
Bit 10
PORTC REGISTER MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
2010-2013 Microchip Technology Inc.
TRISC(1)
02D0
—
—
—
—
—
—
TRISC9
TRISC8
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
03FF
PORTC(1)
02D2
—
—
—
—
—
—
RC9
RC8
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
0000
LATC(1)
02D4
—
—
—
—
—
—
LATC9
LATC8
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
0000
ODCC(1)
02D6
—
—
—
—
—
—
ODC9
OSC8
ODC7
ODC6
ODC5
ODC4
ODC3
ODC2
ODC1
ODC0
0000
Bit 0
All
Resets
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.Bits are not available on 28-pin devices; read as ‘0’.
TABLE 4-15:
File
Name
PADCFG1
Legend:
PAD CONFIGURATION REGISTER MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
02FC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 1
RTSECSEL PMPTTL
0000
PIC24FJ64GA004 FAMILY
DS39881E-page 38
TABLE 4-12:
2010-2013 Microchip Technology Inc.
TABLE 4-16:
A/D REGISTER MAP
File
Name
Addr
ADC1BUF0
0300
A/D Data Buffer 0
xxxx
ADC1BUF1
0302
A/D Data Buffer 1
xxxx
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ADC1BUF2
0304
A/D Data Buffer 2
xxxx
ADC1BUF3
0306
A/D Data Buffer 3
xxxx
ADC1BUF4
0308
A/D Data Buffer 4
xxxx
ADC1BUF5
030A
A/D Data Buffer 5
xxxx
ADC1BUF6
030C
A/D Data Buffer 6
xxxx
ADC1BUF7
030E
A/D Data Buffer 7
xxxx
0310
A/D Data Buffer 8
xxxx
0312
A/D Data Buffer 9
xxxx
ADC1BUFA
0314
A/D Data Buffer 10
xxxx
ADC1BUFB
0316
A/D Data Buffer 11
xxxx
ADC1BUFC
0318
A/D Data Buffer 12
xxxx
ADC1BUFD
031A
A/D Data Buffer 13
xxxx
ADC1BUFE
031C
A/D Data Buffer 14
xxxx
ADC1BUFF
031E
A/D Data Buffer 15
AD1CON1
0320
ADON
—
ADSIDL
—
—
—
FORM1
FORM0
SSRC2
SSRC1
SSRC0
—
—
ASAM
SAMP
DONE
0000
AD1CON2
0322
VCFG2
VCFG1
VCFG0
—
—
CSCNA
—
—
BUFS
—
SMPI3
SMPI2
SMPI1
SMPI0
BUFM
ALTS
0000
0000
xxxx
AD1CON3
0324
ADRC
—
—
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
ADCS7
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
AD1CHS
0328
CH0NB
—
—
—
CH0SB3
CH0SB2
CH0SB1
CH0SB0
CH0NA
—
—
—
CH0SA3
CH0SA2
CH0SA1
CH0SA0
0000
AD1PCFG
032C
PCFG15
—
—
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8(1) PCFG7(1) PCFG6(1)
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
AD1CSSL
0330
CSSL15
—
—
CSSL12
CSSL11
CSSL10
CSSL9
CSSL8(1) CSSL7(1) CSSL6(1)
CSSL5
CSSL4
CSSL3
CSSL2
CSSL1
CSSL0
0000
Legend:
Note 1:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These bits are not available on 28-pin devices; read as ‘0’.
DS39881E-page 39
PIC24FJ64GA004 FAMILY
ADC1BUF8
ADC1BUF9
PARALLEL MASTER/SLAVE PORT REGISTER MAP
File
Name
Addr
Bit 15
PMCON
0600
PMPEN
—
PSIDL
CSF1
CSF0
ALP
—
CS1P
BEP
PMMODE
0602
BUSY
IRQM1
IRQM0
INCM1
INCM0
MODE16
MODE1
MODE0
WAITB1
WAITB0
WAITM3
WAITM2
WAITM1
WAITM0
PMADDR
0604
—
CS1
—
—
—
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 0
All
Resets
WRSP
RDSP
0000
WAITE1
WAITE0
0000
ADDR0
0000
Bit 1
PMDOUT1
Parallel Port Data Out Register 1 (Buffers 0 and 1)
0000
PMDOUT2 0606
Parallel Port Data Out Register 2 (Buffers 2 and 3)
0000
0000
PMDIN1
0608
Parallel Port Data In Register 1 (Buffers 0 and 1)
PMDIN2
060A
Parallel Port Data In Register 2 (Buffers 2 and 3)
PMAEN
060C
—
PTEN14
—
—
—
PTEN10
PTEN9
PTEN8
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
0000
PMSTAT
060E
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
0000
All
Resets
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-18:
File
Name
Addr
ALRMVAL
0620
ALCFGRPT
0622
RTCVAL
0624
RCFGCAL
0626
Legend:
REAL-TIME CLOCK AND CALENDAR REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
ALRMEN
CHIME
AMASK3
AMASK2
AMASK1
Bit 10
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0
0000
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
0000
Alarm Value Register Window Based on ALRMPTR
ARPT6
xxxx
RTCC Value Register Window Based on RTCPTR
RTCEN
—
RTCWREN RTCSYNC HALFSEC
RTCOE
RTCPTR1
RTCPTR0
CAL7
CAL6
xxxx
DUAL COMPARATOR REGISTER MAP
2010-2013 Microchip Technology Inc.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
CMCON
0630
CMIDL
—
C2EVT
C1EVT
C2EN
C1EN
CVRCON
0632
—
—
—
—
—
—
Bit 9
Bit 8
C2OUTEN C1OUTEN
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
C2OUT
C1OUT
C2INV
C1INV
C2NEG
C2POS
C1NEG
C1POS
0000
—
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
0000
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
CRCGO
PLEN3
PLEN2
PLEN1
PLEN0
0040
X5
X4
X3
X2
X1
—
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-20:
File
Name
Bit 8
AMASK0 ALRMPTR1 ALRMPTR0 ARPT7
Addr
Legend:
Bit 9
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-19:
File
Name
0000
Addr
CRC REGISTER MAP
Bit 15
Bit 14
Bit 13
CRCCON
0640
—
—
CSIDL
CRCXOR
0642
X15
X14
X13
Bit 12
Bit 11
Bit 10
Bit 9
VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT
X12
X11
X10
X9
X8
X7
X6
CRCDAT
0644
CRC Data Input Register
0000
CRCWDAT
0646
CRC Result Register
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24FJ64GA004 FAMILY
DS39881E-page 40
TABLE 4-17:
2010-2013 Microchip Technology Inc.
TABLE 4-21:
File
Name
PERIPHERAL PIN SELECT REGISTER MAP (PPS)
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0680
—
—
—
INT1R4
INT1R3
INT1R2
INT1R1
INT1R0
—
—
—
—
—
—
—
—
1F00
0682
—
—
—
—
—
—
—
—
—
—
—
INT2R4
INT2R3
INT2R2
INT2R1
INT2R0
001F
RPINR3
0686
—
—
—
T3CKR4
T3CKR3
T3CKR2
T3CKR1
T3CKR0
—
—
—
T2CKR4
T2CKR3
T2CKR2
T2CKR1
T2CKR0
1F1F
RPINR4
0688
—
—
—
T5CKR4
T5CKR3
T5CKR2
T5CKR1
T5CKR0
—
—
—
T4CKR4
T4CKR3
T4CKR2
T4CKR1
T4CKR0
1F1F
RPINR7
068E
—
—
—
IC2R4
IC2R3
IC2R2
IC2R1
IC2R0
—
—
—
IC1R4
IC1R3
IC1R2
IC1R1
IC1R0
1F1F
RPINR8
0690
—
—
—
IC4R4
IC4R3
IC4R2
IC4R1
IC4R0
—
—
—
IC3R4
IC3R3
IC3R2
IC3R1
IC3R0
1F1F
RPINR9
0692
—
—
—
—
—
—
—
—
—
—
—
IC5R4
IC5R3
IC5R2
IC5R1
IC5R0
001F
RPINR11
0696
—
—
—
OCFBR4
OCFBR3
OCFBR2
OCFBR1
OCFBR0
—
—
—
OCFAR4
OCFAR3
OCFAR2
OCFAR1
OCFAR0
1F1F
RPINR18
06A4
—
—
—
U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0
—
—
—
U1RXR4
U1RXR3
U1RXR2
U1RXR1
U1RXR0
1F1F
RPINR19
06A6
—
—
—
U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0
—
—
—
U2RXR4
U2RXR3
U2RXR2
U2RXR1
U2RXR0
1F1F
RPINR20
06A8
—
—
—
SCK1R4
SCK1R3
SCK1R2
SCK1R1
SCK1R0
—
—
—
SDI1R4
SDI1R3
SDI1R2
SDI1R1
SDI1R0
1F1F
RPINR21
06AA
—
—
—
—
—
—
—
—
—
—
—
SS1R4
SS1R3
SS1R2
SS1R1
SS1R0
001F
RPINR22
06AC
—
—
—
SCK2R4
SCK2R3
SCK2R2
SCK2R1
SCK2R0
—
—
—
SDI2R4
SDI2R3
SDI2R2
SDI2R1
SDI2R0
1F1F
RPINR23
06AE
—
—
—
—
—
—
—
—
—
—
—
SS2R4
SS2R3
SS2R2
SS2R1
SS2R0
001F
RPOR0
06C0
—
—
—
RP1R4
RP1R3
RP1R2
RP1R1
RP1R0
—
—
—
RP0R4
RP0R3
RP0R2
RP0R1
RP0R0
0000
RPOR1
06C2
—
—
—
RP3R4
RP3R3
RP3R2
RP3R1
RP3R0
—
—
—
RP2R4
RP2R3
RP2R2
RP2R1
RP2R0
0000
RPOR2
06C4
—
—
—
RP5R4
RP5R3
RP5R2
RP5R1
RP5R0
—
—
—
RP4R4
RP4R3
RP4R2
RP4R1
RP4R0
0000
RPOR3
06C6
—
—
—
RP7R4
RP7R3
RP7R2
RP7R1
RP7R0
—
—
—
RP6R4
RP6R3
RP6R2
RP6R1
RP6R0
0000
RPOR4
06C8
—
—
—
RP9R4
RP9R3
RP9R2
RP9R1
RP9R0
—
—
—
RP8R4
RP8R3
RP8R2
RP8R1
RP8R0
0000
RPOR5
06CA
—
—
—
RP11R4
RP11R3
RP11R2
RP11R1
RP11R0
—
—
—
RP10R4
RP10R3
RP10R2
RP10R1
RP10R0
0000
RPOR6
06CC
—
—
—
RP13R4
RP13R3
RP13R2
RP13R1
RP13R0
—
—
—
RP12R4
RP12R3
RP12R2
RP12R1
RP12R0
0000
RPOR7
06CE
—
—
—
RP15R4
RP15R3
RP15R2
RP15R1
RP15R0
—
—
—
RP14R4
RP14R3
RP14R2
RP14R1
RP14R0
0000
RPOR8
06D0
—
—
—
RP17R4(1) RP17R3(1) RP17R2(1) RP17R1(1) RP17R0(1)
—
—
—
RP16R4(1) RP16R3(1) RP16R2(1) RP16R1(1) RP16R0(1)
0000
RPOR9
06D2
—
—
—
RP19R4(1) RP19R3(1) RP19R2(1) RP19R1(1) RP19R0(1)
—
—
—
RP18R4(1) RP18R3(1) RP18R2(1) RP18R1(1) RP18R0(1)
0000
RPOR10
06D4
—
—
—
RP21R4(1) RP21R3(1) RP21R2(1) RP21R1(1) RP21R0(1)
—
—
—
RP20R4(1) RP20R3(1) RP20R2(1) RP20R1(1) RP20R0(1)
0000
RPOR11
06D6
—
—
—
RP23R4(1) RP23R3(1) RP23R2(1) RP23R1(1) RP23R0(1)
—
—
—
RP22R4(1) RP22R3(1) RP22R2(1) RP22R1(1) RP22R0(1)
0000
RPOR12
06D8
—
—
—
RP25R4(1) RP25R3(1) RP25R2(1) RP25R1(1) RP25R0(1)
—
—
—
RP24R4(1) RP24R3(1) RP24R2(1) RP24R1(1) RP24R0(1)
0000
Legend:
Note 1:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These bits are only available on 44-pin devices; otherwise, they read as ‘0’.
DS39881E-page 41
PIC24FJ64GA004 FAMILY
RPINR0
RPINR1
File
Name
CLOCK CONTROL REGISTER MAP
Addr
Bit 15
Bit 14
RCON
0740
TRAPR
IOPUWR
OSCCON
0742
—
COSC2
CLKDIV
0744
ROI
DOZE2
OSCTUN
0748
—
—
Legend:
Note 1:
2:
Bit 13
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
BOR
CLKLOCK
IOLOCK
LOCK
—
CF
—
SOSCEN
POR
(Note 1)
—
—
—
—
CM
PMSLP
COSC1
COSC0
—
NOSC2
NOSC1
NOSC0
DOZE1
DOZE0
DOZEN
RCDIV2
RCDIV1
RCDIV0
—
—
—
—
—
—
—
—
3140
—
—
—
—
—
—
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
0000
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
OSWEN (Note 2)
NVM REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
NVMCON
0760
WR
WREN
WRERR
—
—
—
—
—
—
ERASE
—
NVMKEY
0766
—
—
—
—
—
—
—
—
—
NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1)
NVMKEY
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for a POR only. The value on other Reset states is dependent on the state of the memory write or erase operations at the time of Reset.
TABLE 4-24:
File Name
All
Resets
Bit 11
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values are dependent on the type of Reset.
OSCCON register Reset values are dependent on configuration fuses and by the type of Reset.
TABLE 4-23:
Legend:
Note 1:
Bit 1
Bit 0
Bit 12
PMD REGISTER MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PMD1
0770
T5MD
T4MD
T3MD
T2MD
T1MD
—
—
—
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
—
—
ADC1MD
0000
PMD2
0772
—
—
—
IC5MD
IC4MD
IC3MD
IC2MD
IC1MD
—
—
—
OC5MD
OC4MD
OC3MD
OC2MD
OC1MD
0000
PMD3
0774
—
—
—
—
—
CMPMD
RTCCMD
PMPMD
CRCPMD
—
—
—
—
—
I2C2MD
—
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24FJ64GA004 FAMILY
DS39881E-page 42
TABLE 4-22:
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
4.2.5
SOFTWARE STACK
4.3
In addition to its use as a working register, the W15
register in PIC24F devices is also used as a Software
Stack Pointer. The pointer always points to the first
available free word and grows from lower to higher
addresses. It pre-decrements for stack pops and
post-increments for stack pushes, as shown in
Figure 4-4. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
Note:
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
The Stack Pointer Limit Value register (SPLIM), associated with the Stack Pointer, sets an upper address
boundary for the stack. SPLIM is uninitialized at Reset.
As is the case for the Stack Pointer, SPLIM is
forced to ‘0’ because all stack operations must be
word-aligned. Whenever an EA is generated using
W15 as a source or destination pointer, the resulting
address is compared with the value in SPLIM. If the
contents of the Stack Pointer (W15) and the SPLIM
register are equal, and a push operation is performed,
a stack error trap will not occur. The stack error trap will
occur on a subsequent push operation. Thus, for
example, if it is desirable to cause a stack error trap
when the stack grows beyond address 2000h in RAM,
initialize the SPLIM with the value, 1FFEh.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0800h. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-4:
Stack Grows Towards
Higher Address
0000h
CALL STACK FRAME
15
0
PC
000000000 PC
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
2010-2013 Microchip Technology Inc.
Interfacing Program and Data
Memory Spaces
The PIC24F architecture uses a 24-bit wide program
space and 16-bit wide data space. The architecture is
also a modified Harvard scheme, meaning that data
can also be present in the program space. To use this
data successfully, it must be accessed in a way that
preserves the alignment of information in both spaces.
Aside from normal execution, the PIC24F architecture
provides two methods by which program space can be
accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
• Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This makes the
method ideal for accessing data tables that need to be
updated from time to time. It also allows access to all
bytes of the program word. The remapping method
allows an application to access a large block of data on
a read-only basis, which is ideal for look-ups from a
large table of static data. It can only access the least
significant word of the program word.
4.3.1
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Memory Page
Address register (TBLPAG) is used to define a 32K word
region within the program space. This is concatenated
with a 16-bit EA to arrive at a full 24-bit program space
address. In this format, the Most Significant bit of
TBLPAG is used to determine if the operation occurs in
the user memory (TBLPAG = 0) or the configuration
memory (TBLPAG = 1).
For remapping operations, the 8-bit Program Space
Visibility Page Address register (PSVPAG) is used to
define a 16K word page in the program space. When
the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a
23-bit program space address. Unlike table operations,
this limits remapping operations strictly to the user
memory area.
Table 4-25 and Figure 4-5 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P refers to a program
space word, whereas D refers to a data space
word.
DS39881E-page 43
PIC24FJ64GA004 FAMILY
TABLE 4-25:
PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
Instruction Access
(Code Execution)
User
TBLRD/TBLWT
(Byte/Word Read/Write)
User
TBLPAG
Data EA
0xxx xxxx
xxxx xxxx xxxx xxxx
Configuration
TBLPAG
Data EA
1xxx xxxx
xxxx xxxx xxxx xxxx
0
0xx xxxx xxxx xxxx xxxx xxx0
Program Space Visibility
(Block Remap/Read)
Note 1:
PC
0
User
0
PSVPAG
Data EA(1)
0
xxxx xxxx
xxx xxxx xxxx xxxx
Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG.
FIGURE 4-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
0
0
23 Bits
EA
Table Operations(2)
1/0
1/0
TBLPAG
8 Bits
16 Bits
24 Bits
Select
Program Space
(Remapping)
Visibility(1)
0
EA
1
0
PSVPAG
8 Bits
15 Bits
23 Bits
User/Configuration
Space Select
Note 1:
2:
DS39881E-page 44
Byte Select
The LSb of program space addresses is always fixed as ‘0’ in order to maintain word
alignment of data in the program and data spaces.
Table operations are not required to be word-aligned. Table read operations are permitted
in the configuration memory space.
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
4.3.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going through
data space. The TBLRDH and TBLWTH instructions are
the only method to read or write the upper 8 bits of a
program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH access the space
which contains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1.
TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P) to a data address (D).
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when byte select is ‘1’; the lower byte
is selected when it is ‘0’.
FIGURE 4-6:
2.
TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P) to a data address. Note that
D, the ‘phantom’ byte, will always be ‘0’.
In Byte mode, it maps the upper or lower byte of
the program word to D of the data
address, as above. Note that the data will
always be ‘0’ when the upper ‘phantom’ byte is
selected (Byte Select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table
Memory Page Address register (TBLPAG). TBLPAG
covers the entire program memory space of the
device, including user and configuration spaces. When
TBLPAG = 0, the table page is located in the user
memory space. When TBLPAG = 1, the page is
located in configuration space.
Note:
Only table read operations will execute in
the configuration memory space, and only
then, in implemented areas, such as the
Device ID. Table write operations are not
allowed.
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
Data EA
23
15
0
000000h
23
16
8
0
00000000
020000h
030000h
00000000
00000000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn = 0)
TBLRDL.B (Wn = 1)
TBLRDL.B (Wn = 0)
TBLRDL.W
800000h
2010-2013 Microchip Technology Inc.
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
DS39881E-page 45
PIC24FJ64GA004 FAMILY
4.3.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This provides transparent access of stored constant
data from the data space without the need to use
special instructions (i.e., TBLRDL/H).
Program space access through the data space occurs if
the Most Significant bit of the data space EA is ‘1’ and
Program Space Visibility is enabled by setting the PSV
bit in the CPU Control register (CORCON). The
location of the program memory space to be mapped
into the data space is determined by the Program Space
Visibility Page Address register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. Note that by incrementing the PC by 2 for
each program memory word, the lower 15 bits of data
space addresses directly map to the lower 15 bits in the
corresponding program space addresses.
Data reads to this area add an additional cycle to the
instruction being executed, since two program memory
fetches are required.
Although each data space address, 8000h and higher,
maps directly into a corresponding program memory
address (see Figure 4-7), only the lower 16 bits of the
FIGURE 4-7:
24-bit program word are used to contain the data. The
upper 8 bits of any program space locations used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
PSV access is temporarily disabled during
table reads/writes.
Note:
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions will
require one instruction cycle in addition to the specified
execution time. All other instructions will require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
PROGRAM SPACE VISIBILITY OPERATION
When CORCON = 1 and EA = 1:
Program Space
PSVPAG
02
23
15
Data Space
0
000000h
0000h
Data EA
010000h
018000h
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space....
8000h
PSV Area
FFFFh
800000h
DS39881E-page 46
...while the lower
15 bits of the EA
specify an exact
address within the
PSV area. This corresponds exactly to the
same lower 15 bits of
the actual program
space address.
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
5.0
Note:
RTSP is accomplished using TBLRD (Table Read) and
TBLWT (Table Write) instructions. With RTSP, the user
may write program memory data in blocks of 64 instructions (192 bytes) at a time and erase program memory
in blocks of 512 instructions (1536 bytes) at a time.
FLASH PROGRAM MEMORY
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
“Program Memory” (DS39715).
5.1
The PIC24FJ64GA004 family of devices contains internal Flash program memory for storing and executing
application code. The memory is readable, writable and
erasable when operating with VDD over 2.25V.
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using the TBLPAG bits and the Effective
Address (EA) from a W register, specified in the table
instruction, as shown in Figure 5-1.
Flash memory can be programmed in three ways:
• In-Circuit Serial Programming™ (ICSP™)
• Run-Time Self-Programming (RTSP)
• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
The TBLRDL and the TBLWTL instructions are used to
read or write to bits of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
ICSP allows a PIC24FJ64GA004 family device to be
serially programmed while in the end application circuit.
This is simply done with two lines for the programming
clock and programming data (which are named PGCx
and PGDx, respectively), and three other lines for
power (VDD), ground (VSS) and Master Clear (MCLR).
This allows customers to manufacture boards with
unprogrammed devices and then program the microcontroller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
FIGURE 5-1:
Table Instructions and Flash
Programming
The TBLRDH and TBLWTH instructions are used to read
or write to bits of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
ADDRESSING FOR TABLE REGISTERS
24 Bits
Using
Program
Counter
Program Counter
0
0
Working Reg EA
Using
Table
Instruction
User/Configuration
Space Select
2010-2013 Microchip Technology Inc.
1/0
TBLPAG Reg
8 Bits
16 Bits
24-Bit EA
Byte
Select
DS39881E-page 47
PIC24FJ64GA004 FAMILY
5.2
RTSP Operation
The PIC24F Flash program memory array is organized
into rows of 64 instructions or 192 bytes. RTSP allows
the user to erase blocks of eight rows (512 instructions)
at a time and to program one row at a time. It is also
possible to program single words.
The 8-row erase blocks and single row write blocks are
edge-aligned, from the beginning of program memory, on
boundaries of 1536 bytes and 192 bytes, respectively.
When data is written to program memory using TBLWT
instructions, the data is not written directly to memory.
Instead, data written using table writes is stored in
holding latches until the programming sequence is
executed.
Any number of TBLWT instructions can be executed
and a write will be successfully performed. However,
64 TBLWT instructions are required to write the full row
of memory.
To ensure that no data is corrupted during a write, any
unused addresses should be programmed with
FFFFFFh. This is because the holding latches reset to
an unknown state, so if the addresses are left in the
Reset state, they may overwrite the locations on rows
which were not rewritten.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register.
Data can be loaded in any order and the holding registers can be written to multiple times before performing
a write operation. Subsequent writes, however, will
wipe out any previous writes.
Note:
Writing to a location multiple times without
erasing it is not recommended.
All of the table write operations are single-word writes
(2 instruction cycles), because only the buffers are written. A programming cycle is required for programming
each row.
DS39881E-page 48
5.3
Enhanced In-Circuit Serial
Programming
Enhanced In-Circuit Serial Programming uses an
on-board bootloader, known as the Program Executive
(PE), to manage the programming process. Using an
SPI data frame format, the Program Executive can
erase, program and verify program memory. For more
information on Enhanced ICSP, see the device
programming specification.
5.4
Control Registers
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and when the programming cycle starts.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 55h and AAh to the
NVMKEY register. Refer to Section 5.5 “Programming
Operations” for further details.
5.5
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. During a programming or erase operation, the
processor stalls (waits) until the operation is finished.
Setting the WR bit (NVMCON) starts the operation and the WR bit is automatically cleared when the
operation is finished.
Configuration Word values are stored in the last two
locations of program memory. Performing a page erase
operation on the last page of program memory clears
these values and enables code protection. As a result,
avoid performing page erase operations on the last
page of program memory.
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 5-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
WR
WREN
WRERR
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
—
U-0
ERASE
—
U-0
—
R/W-0
NVMOP3
R/W-0
(1)
R/W-0
(1)
NVMOP2
NVMOP1
R/W-0
(1)
NVMOP0(1)
bit 7
bit 0
Legend:
SO = Settable Only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once operation is complete
0 = Program or erase operation is complete and inactive
bit 14
WREN: Write Enable bit
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
bit 13
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12-7
Unimplemented: Read as ‘0’
bit 6
ERASE: Erase/Program Enable bit
1 = Performs the erase operation specified by the NVMOP bits on the next WR command
0 = Performs the program operation specified by the NVMOP bits on the next WR command
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
NVMOP: NVM Operation Select bits(1)
1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(2)
0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)
0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)
0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
Note 1:
2:
All other combinations of NVMOP are unimplemented.
Available in ICSP™ mode only. Refer to the device programming specifications.
2010-2013 Microchip Technology Inc.
DS39881E-page 49
PIC24FJ64GA004 FAMILY
5.5.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
4.
5.
The user can program one row of Flash program memory
at a time. To do this, it is necessary to erase the 8-row
erase block containing the desired row. The general
process is:
1.
2.
3.
Read eight rows of program memory
(512 instructions) and store in data RAM.
Update the program data in RAM with the
desired new data.
Erase the block (see Example 5-1):
a) Set the NVMOPx bits (NVMCON) to
‘0010’ to configure for block erase. Set the
ERASE (NVMCON) and WREN
(NVMCON) bits.
b) Write the starting address of the block to be
erased into the TBLPAG and W registers.
c) Write 55h to NVMKEY.
d) Write AAh to NVMKEY.
e) Set the WR bit (NVMCON). The erase
cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 5-1:
DS39881E-page 50
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 5-3.
ERASING A PROGRAM MEMORY BLOCK
; Set up NVMCON for block erase operation
MOV
#0x4042, W0
MOV
W0, NVMCON
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR), W0
MOV
W0, TBLPAG
MOV
#tbloffset(PROG_ADDR), W0
TBLWTL W0, [W0]
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
6.
Write the first 64 instructions from data RAM into
the program memory buffers (see Example 5-1).
Write the program block to Flash memory:
a) Set the NVMOPx bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 55h to NVMKEY.
c) Write AAh to NVMKEY.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration
of the write cycle. When the write to Flash
memory is done, the WR bit is cleared
automatically.
Repeat Steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash
memory.
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
;
; Initialize NVMCON
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PM Page Boundary SFR
Initialize in-page EA[15:0] pointer
Set base address of erase block
Block all interrupts with priority C2 VIN1 = C2 VIN+ < C2 VIN-
Note 1:
2:
If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPn pin. See
Section 10.4 “Peripheral Pin Select (PPS)” for more information.
If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPn pin. See
Section 10.4 “Peripheral Pin Select (PPS)” for more information.
DS39881E-page 204
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 22-1:
CMCON: COMPARATOR CONTROL REGISTER (CONTINUED)
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1:
0 = C1 VIN+ > C1 VIN1 = C1 VIN+ < C1 VIN-
bit 5
C2INV: Comparator 2 Output Inversion bit
1 = C2 output is inverted
0 = C2 output is not inverted
bit 4
C1INV: Comparator 1 Output Inversion bit
1 = C1 output is inverted
0 = C1 output is not inverted
bit 3
C2NEG: Comparator 2 Negative Input Configure bit
1 = Input is connected to VIN+
0 = Input is connected to VINSee Figure 22-1 for the Comparator modes.
bit 2
C2POS: Comparator 2 Positive Input Configure bit
1 = Input is connected to VIN+
0 = Input is connected to CVREF
See Figure 22-1 for the Comparator modes.
bit 1
C1NEG: Comparator 1 Negative Input Configure bit
1 = Input is connected to VIN+
0 = Input is connected to VINSee Figure 22-1 for the Comparator modes.
bit 0
C1POS: Comparator 1 Positive Input Configure bit
1 = Input is connected to VIN+
0 = Input is connected to CVREF
See Figure 22-1 for the Comparator modes.
Note 1:
2:
If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPn pin. See
Section 10.4 “Peripheral Pin Select (PPS)” for more information.
If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPn pin. See
Section 10.4 “Peripheral Pin Select (PPS)” for more information.
2010-2013 Microchip Technology Inc.
DS39881E-page 205
PIC24FJ64GA004 FAMILY
NOTES:
DS39881E-page 206
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
23.0
Note:
23.1
output voltage, each with 16 distinct levels. The range
to be used is selected by the CVRR bit (CVRCON).
The primary difference between the ranges is the size
of the steps selected by the CVREF Selection bits
(CVR), with one range offering finer resolution.
COMPARATOR VOLTAGE
REFERENCE
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
the “PIC24F Family Reference Manual”,
“Comparator
Voltage
Reference
Module” (DS39709).
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF-. The voltage source is selected by the CVRSS
bit (CVRCON).
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output.
Configuring the Comparator
Voltage Reference
The comparator voltage reference module is controlled
through the CVRCON register (Register 23-1). The
comparator voltage reference provides two ranges of
FIGURE 23-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+
AVDD
CVRSS = 1
8R
CVRSS = 0
CVR
R
CVREN
R
R
16-to-1 MUX
R
16 Steps
R
CVREF
R
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
AVSS
2010-2013 Microchip Technology Inc.
DS39881E-page 207
PIC24FJ64GA004 FAMILY
REGISTER 23-1:
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit is powered on
0 = CVREF circuit is powered down
bit 6
CVROE: Comparator VREF Output Enable bit
1 = CVREF voltage level is output on the CVREF pin
0 = CVREF voltage level is disconnected from the CVREF pin
bit 5
CVRR: Comparator VREF Range Selection bit
1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step-size
0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step-size
bit 4
CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = VREF+ – VREF0 = Comparator reference source, CVRSRC = AVDD – AVSS
bit 3-0
CVR: Comparator VREF Value Selection 0 CVR 15 bits
When CVRR = 1:
CVREF = (CVR/24) • (CVRSRC)
When CVRR = 0:
CVREF = 1/4 • (CVRSRC) + (CVR/32) • (CVRSRC)
DS39881E-page 208
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
24.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference source. For more information, refer
to the following sections of the “PIC24F
Family Reference Manual”:
• “Watchdog Timer (WDT)”
(DS39697)
• “High-Level Device Integration”
(DS39719)
• “Programming and Diagnostics”
(DS39716)
PIC24FJ64GA004 family devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
•
•
•
•
•
•
Flexible Configuration
Watchdog Timer (WDT)
Code Protection
JTAG Boundary Scan Interface
In-Circuit Serial Programming
In-Circuit Emulation
24.1.1
CONSIDERATIONS FOR
CONFIGURING PIC24FJ64GA004
FAMILY DEVICES
In PIC24FJ64GA004 family devices, the configuration
bytes are implemented as volatile memory. This means
that configuration data must be programmed each time
the device is powered up. Configuration data is stored
in the two words at the top of the on-chip program
memory space, known as the Flash Configuration
Words. Their specific locations are shown in
Table 24-1. These are packed representations of the
actual device Configuration bits, whose actual
locations are distributed among five locations in configuration space. The configuration data is automatically
loaded from the Flash Configuration Words to the
proper Configuration registers during device Resets.
Note:
Configuration data is reloaded on all types
of device Resets.
TABLE 24-1:
Device
24.1
Configuration Bits
The Configuration bits can be programmed (read as ‘0’),
or left unprogrammed (read as ‘1’), to select various
device configurations. These bits are mapped starting at
program memory location, F80000h. A complete list of
locations is shown in Table 24-1. A detailed explanation
of the various bit functions is provided in Register 24-1
through Register 24-4.
Note that address, F80000h, is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (800000h-FFFFFFh), which can only be
accessed using table reads and table writes.
PIC24FJ16GA
FLASH CONFIGURATION
WORD LOCATIONS FOR
PIC24FJ64GA004 FAMILY
DEVICES
Configuration Word
Addresses
1
2
002BFEh
002BFCh
PIC24FJ32GA
0057FEh
0057FCh
PIC24FJ48GA
0083FEh
0083FCh
PIC24FJ64GA
00ABFEh
00ABFCh
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
The Configuration bits are reloaded from the Flash
Configuration Word on any device Reset.
The upper byte of both Flash Configuration Words in
program memory should always be ‘1111 1111’. This
makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
2010-2013 Microchip Technology Inc.
DS39881E-page 209
PIC24FJ64GA004 FAMILY
REGISTER 24-1:
CW1: FLASH CONFIGURATION WORD 1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
r-x
R/PO-1
R/PO-1
R/PO-1
R/PO-1
r-1
R/PO-1
R/PO-1
r
JTAGEN
GCP
GWRP
DEBUG
r
ICS1
ICS0
bit 15
bit 8
R/PO-1
R/PO-1
r
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
FWDTEN
WINDIS
r
FWPSA
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
bit 0
Legend:
r = Reserved bit
R = Readable bit
PO = Program Once bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-16
Unimplemented: Read as ‘1’
bit 15
Reserved: The value is unknown; program as ‘0’
bit 14
JTAGEN: JTAG Port Enable bit
1 = JTAG port is enabled
0 = JTAG port is disabled
bit 13
GCP: General Segment Program Memory Code Protection bit
1 = Code protection is disabled
0 = Code protection is enabled for the entire program memory space
bit 12
GWRP: General Segment Code Flash Write Protection bit
1 = Writes to program memory are allowed
0 = Writes to program memory are disabled
bit 11
DEBUG: Background Debugger Enable bit
1 = Device resets into Operational mode
0 = Device resets into Debug mode
bit 10
Reserved: Always maintain as ‘1’
bit 9-8
ICS: Emulator Pin Placement Select bits
11 = Emulator EMUC1/EMUD1 pins are shared with PGC1/PGD1
10 = Emulator EMUC2/EMUD2 pins are shared with PGC2/PGD2
01 = Emulator EMUC3/EMUD3 pins are shared with PGC3/PGD3
00 = Reserved; do not use
bit 7
FWDTEN: Watchdog Timer Enable bit
1 = Watchdog Timer is enabled
0 = Watchdog Timer is disabled
bit 6
WINDIS: Windowed Watchdog Timer Disable bit
1 = Standard Watchdog Timer is enabled
0 = Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’
bit 5
Reserved
bit 4
FWPSA: WDT Prescaler Ratio Select bit
1 = Prescaler ratio of 1:128
0 = Prescaler ratio of 1:32
DS39881E-page 210
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 24-1:
bit 3-0
CW1: FLASH CONFIGURATION WORD 1 (CONTINUED)
WDTPS: Watchdog Timer Postscaler Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
2010-2013 Microchip Technology Inc.
DS39881E-page 211
PIC24FJ64GA004 FAMILY
REGISTER 24-2:
CW2: FLASH CONFIGURATION WORD 2
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
R/PO-1
IESO
bit 16
R/PO-1
R/PO-1
(1)
WUTSEL1
WUTSEL0
R/PO-1
(1)
SOSCSEL1
R/PO-1
(1)
SOSCSEL0
(1)
R/PO-1
R/PO-1
R/PO-1
FNOSC2
FNOSC1
FNOSC0
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
r
R/PO-1
R/PO-1
R/PO-1
FCKSM1
FCKSM0
OSCIOFCN
IOL1WAY
r
I2C1SEL
POSCMD1
POSCMD0
bit 7
bit 0
Legend:
r = Reserved bit
R = Readable bit
PO = Program Once bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-16
Unimplemented: Read as ‘1’
bit 15
IESO: Internal External Switchover bit
1 = IESO mode (Two-Speed Start-up) is enabled
0 = IESO mode (Two-Speed Start-up) is disabled
bit 14-13
WUTSEL: Voltage Regulator Standby Mode Wake-up Time Select bits(1)
11 = Default regulator start-up time is used
01 = Fast regulator start-up time is used
x0 = Reserved; do not use
bit 12-11
SOSCSEL: Secondary Oscillator Power Mode Select bits(1)
11 = Default (High Drive Strength) mode
01 = Low-Power (Low Drive Strength) mode
x0 = Reserved; do not use
bit 10-8
FNOSC: Initial Oscillator Select bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 7-6
FCKSM: Clock Switching and Fail-Safe Clock Monitor Configuration bits
1x = Clock switching and Fail-Safe Clock Monitor are disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 5
OSCIOFCN: OSCO Pin Configuration bit
If POSCMD = 11 or 00:
1 = OSCO/CLKO/RA3 functions as CLKO (FOSC/2)
0 = OSCO/CLKO/RA3 functions as port I/O (RA3)
If POSCMD = 10 or 01:
OSCIOFCN has no effect on OSCO/CLKO/RA3.
Note 1:
These bits are implemented only in devices with a major silicon revision level of B or later (DEVREV register value is 3042h or greater). Refer to Section 28.0 “Packaging Information” in the device data sheet
for the location and interpretation of product date codes.
DS39881E-page 212
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 24-2:
CW2: FLASH CONFIGURATION WORD 2 (CONTINUED)
bit 4
IOL1WAY: IOLOCK One-Way Set Enable bit
1 = The IOLOCK (OSCCON) bit can be set once, provided the unlock sequence has been
completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.
0 = The IOLOCK (OSCCON) bit can be set and cleared as needed, provided the unlock sequence
has been completed
bit 3
Reserved
bit 2
I2C1SEL: I2C1 Pin Select bit
1 = Use default SCL1/SDA1 pins
0 = Use alternate SCL1/SDA1 pins
bit 1-0
POSCMD Primary Oscillator Configuration bits
11 = Primary oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = EC Oscillator mode is selected
Note 1:
These bits are implemented only in devices with a major silicon revision level of B or later (DEVREV register value is 3042h or greater). Refer to Section 28.0 “Packaging Information” in the device data sheet
for the location and interpretation of product date codes.
REGISTER 24-3:
DEVID: DEVICE ID REGISTER
U
U
U
U
U
U
U
U
—
—
—
—
—
—
—
—
bit 23
bit 16
U
U
R
R
R
R
R
R
—
—
FAMID7
FAMID6
FAMID5
FAMID4
FAMID3
FAMID2
bit 15
bit 8
R
R
R
R
R
R
R
R
FAMID1
FAMID0
DEV5
DEV4
DEV3
DEV2
DEV1
DEV0
bit 7
bit 0
Legend: R = Read-only bit
bit 23-14
Unimplemented: Read as ‘1’
bit 13-6
FAMID: Device Family Identifier bits
00010001 = PIC24FJ64GA004 family
bit 5-0
DEV: Individual Device Identifier bits
000100 = PIC24FJ16GA002
000101 = PIC24FJ32GA002
000110 = PIC24FJ48GA002
000111 = PIC24FJ64GA002
001100 = PIC24FJ16GA004
001101 = PIC24FJ32GA004
001110 = PIC24FJ48GA004
001111 = PIC24FJ64GA004
2010-2013 Microchip Technology Inc.
U = Unimplemented bit
DS39881E-page 213
PIC24FJ64GA004 FAMILY
REGISTER 24-4:
DEVREV: DEVICE REVISION REGISTER
U
U
U
U
U
U
U
U
—
—
—
—
—
—
—
—
bit 23
bit 16
U
U
U
U
U
U
U
R
—
—
—
—
—
—
—
MAJRV2
bit 15
bit 8
R
R
U
U
U
R
R
R
MAJRV1
MAJRV0
—
—
—
DOT2
DOT1
DOT0
bit 7
bit 0
Legend: R = Read-only bit
bit 23-9
Unimplemented: Read as ‘0’
bit 8-6
MAJRV: Major Revision Identifier bits
bit 5-3
Unimplemented: Read as ‘0’
bit 2-0
DOT: Minor Revision Identifier bits
DS39881E-page 214
U = Unimplemented bit
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
24.2
On-Chip Voltage Regulator
FIGURE 24-1:
All of the PIC24FJ64GA004 family devices power their
core digital logic at a nominal 2.5V. This may create an
issue for designs that are required to operate at a
higher typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC24FJ64GA004 family
incorporate an on-chip regulator that allows the device
to run its core logic from VDD.
Regulator Enabled (DISVREG tied to VSS):
3.3V
PIC24FJ64GA
VDD
DISVREG
The regulator is controlled by the DISVREG pin. Tying
VSS to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When
the regulator is enabled, a low-ESR capacitor (such as
ceramic) must be connected to the VDDCORE/VCAP pin
(Figure 24-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capacitor
is provided in Section 27.1 “DC Characteristics”.
VDDCORE/VCAP
CEFC
(10 F typ)
2.5V(1)
DISVREG
VDDCORE/VCAP
VSS
Regulator Disabled (VDD tied to VDDCORE):
2.5V(1)
When it is enabled, the on-chip regulator provides a
constant voltage of 2.5V nominal to the digital core
logic.
When the device enters Tracking mode, it is no longer
possible to operate at full speed. To provide information
about when the device enters Tracking mode, the
on-chip regulator includes a simple, Low-Voltage
Detect (LVD) circuit. When VDD drops below full-speed
operating voltage, the circuit sets the Low-Voltage
Detect Interrupt Flag, LVDIF (IFS4). This can be
used to generate an interrupt and put the application
into a low-power operational mode or trigger an orderly
shutdown.
Low-Voltage Detection is only available when the
regulator is enabled.
2010-2013 Microchip Technology Inc.
3.3V(1)
PIC24FJ64GA
VDD
VOLTAGE REGULATOR TRACKING
MODE AND LOW-VOLTAGE
DETECTION
The regulator can provide this level from a VDD of about
2.5V, all the way up to the device’s VDDMAX. It does not
have the capability to boost VDD levels below 2.5V. In
order to prevent “brown out” conditions, when the voltage drops too low for the regulator, the regulator enters
Tracking mode. In Tracking mode, the regulator output
follows VDD, with a typical voltage drop of 100 mV.
VSS
Regulator Disabled (DISVREG tied to VDD):
If DISVREG is tied to VDD, the regulator is disabled. In
this case, separate power for the core logic at a nominal 2.5V must be supplied to the device on the
VDDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the VDDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 24-1 for possible
configurations.
24.2.1
CONNECTIONS FOR THE
ON-CHIP REGULATOR
PIC24FJ64GA
VDD
DISVREG
VDDCORE/VCAP
VSS
Note 1: These are typical operating voltages. Refer
to Section 27.1 “DC Characteristics” for
the full operating ranges of VDD and
VDDCORE.
24.2.2
ON-CHIP REGULATOR AND BOR
When
the
on-chip
regulator
is
enabled,
PIC24FJ64GA004 family devices also have a simple
brown-out capability. If the voltage supplied to the regulator is inadequate to maintain the tracking level, the
regulator Reset circuitry will generate a Brown-out
Reset. This event is captured by the BOR flag bit
(RCON). The brown-out voltage levels are
specified in Section 27.1 “DC Characteristics”.
DS39881E-page 215
PIC24FJ64GA004 FAMILY
24.2.3
ON-CHIP REGULATOR AND POR
When the voltage regulator is enabled, it takes approximately 10 µs for it to generate output. During this time,
designated as TVREG, code execution is disabled.
TVREG is applied every time the device resumes operation after any power-down, including Sleep mode.
TVREG is determined by the setting of the PMSLP bit
(RCON) and the WUTSELx Configuration bits
(CW2). For more information on TVREG, see
Section 27.0 “Electrical Characteristics”.
If the regulator is disabled, a separate Power-up Timer
(PWRT) is automatically enabled. The PWRT adds a
fixed delay of 64 ms nominal delay at device start-up
(POR or BOR only). When waking up from Sleep with
the regulator disabled, TVREG is used to determine the
wake-up time. To decrease the device wake-up time
when operating with the regulator disabled, the PMSLP
bit can be set.
24.2.4
POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE must
never exceed VDD by 0.3 volts.
Note:
24.2.5
For more information, see Section 27.0
“Electrical Characteristics”.
VOLTAGE REGULATOR STANDBY
MODE
When enabled, the on-chip regulator always consumes
a small incremental amount of current over IDD/IPD,
including when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator automatically
places itself into Standby mode whenever the device
goes into Sleep mode. This feature is controlled by the
PMSLP bit (RCON). By default, this bit is cleared,
which enables Standby mode.
For select PIC24FJ64GA004 family devices, the time
required for regulator wake-up from Standby mode is
controlled by the WUTSEL Configuration bits
(CW2). The default wake-up time for all
devices is 190 s. Where the WUTSELx Configuration
bits are implemented, a fast wake-up option is also
available. When WUTSEL = 01, the regulator
wake-up time is 25 s.
Note:
This feature is implemented only on
PIC24FJ64GA004 family devices with a
major silicon revision level of B or later
(DEVREV register value is 3042h or
greater).
DS39881E-page 216
When the regulator’s Standby mode is turned off
(PMSLP = 1), Flash program memory stays powered
in Sleep mode and the device can wake-up in less than
10 s. When PMSLP is set, the power consumption
while in Sleep mode will be approximately 40 A higher
than power consumption when the regulator is allowed
to enter Standby mode.
24.3
Watchdog Timer (WDT)
For PIC24FJ64GA004 family devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT Time-out period (TWDT) of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPS Configuration bits (CW1), which allow the selection of
a total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler, time-out periods, ranges from
1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDT instruction during normal execution
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE bits
(RCON) will need to be cleared in software after
the device wakes up.
The WDT Flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
24.3.1
WINDOWED OPERATION
24.3.2
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
WINDIS Configuration bit (CW1) to ‘0’.
FIGURE 24-2:
CONTROL REGISTER
The WDT is enabled or disabled by the FWDTEN
Configuration bit. When the FWDTEN Configuration bit
is set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for
critical code segments and disable the WDT during
non-critical segments for maximum power savings.
WDT BLOCK DIAGRAM
SWDTEN
FWDTEN
LPRC Control
FWPSA
WDTPS
Prescaler
(5-bit/7-bit)
LPRC Input
31 kHz
Wake from Sleep
WDT
Counter
Postscaler
1:1 to 1:32.768
WDT Overflow
Reset
1 ms/4 ms
All Device Resets
Transition to
New Clock Source
Exit Sleep or
Idle Mode
CLRWDT Instr.
PWRSAV Instr.
Sleep or Idle Mode
2010-2013 Microchip Technology Inc.
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24.4
JTAG Interface
PIC24FJ64GA004 family devices implement a JTAG
interface, which supports boundary scan device
testing.
24.5
Program Verification and
Code Protection
For all devices in the PIC24FJ64GA004 family, the
on-chip program memory space is treated as a single
block. Code protection for this block is controlled by
one Configuration bit, GCP. This bit inhibits external
reads and writes to the program memory space. It has
no direct effect in normal execution mode.
Write protection is controlled by the GWRP bit in Configuration Word 1. When GWRP is programmed to ‘0’,
internal write and erase operations to program memory
are blocked.
24.5.1
CONFIGURATION REGISTER
PROTECTION
The Configuration registers are protected against
inadvertent or unwanted changes, or reads in two
ways. The primary protection method is the same as
that of the RP registers – shadow registers contain a
complimentary value which is constantly compared
with the actual value.
24.6
In-Circuit Serial Programming
PIC24FJ64GA004 family microcontrollers can be serially programmed while in the end application circuit.
This is simply done with two lines for clock (PGCx) and
data (PGDx), and three other lines for power, ground
and the programming voltage. This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or a custom firmware to be programmed.
24.7
In-Circuit Debugger
When MPLAB® ICD 2 is selected as a debugger, the
in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the EMUCx (Emulation/Debug Clock) and
EMUDx (Emulation/Debug Data) pins.
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS, PGCx, PGDx and the
EMUDx/EMUCx pin pair. In addition, when the feature
is enabled, some of the resources are not available for
general use. These resources include the first 80 bytes
of data RAM and two I/O pins.
To safeguard against unpredictable events, Configuration bit changes, resulting from individual cell level
disruptions (such as ESD events), will cause a parity
error and trigger a device Reset.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the GCP bit is set, the source data for device
configuration is also protected as a consequence.
DS39881E-page 218
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
25.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
25.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2010-2013 Microchip Technology Inc.
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25.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
25.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
25.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
25.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS39881E-page 220
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25.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
25.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2010-2013 Microchip Technology Inc.
25.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
25.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
25.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
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25.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
25.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
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26.0
Note:
INSTRUCTION SET SUMMARY
This chapter is a brief summary of the
PIC24F Instruction Set Architecture (ISA)
and is not intended to be a comprehensive
reference source.
The PIC24F instruction set adds many enhancements
to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU
instruction sets. Most instructions are a single program
memory word. Only three instructions require two
program memory locations.
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction. The instruction set is
highly orthogonal and is grouped into four basic
categories:
•
•
•
•
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand which is a register ‘Wb’
without any address modifier
• The second source operand which is a literal
value
• The destination of the result (only if not the same
as the first source operand) which is typically a
register ‘Wd’ with or without an address modifier
The control instructions may use some of the following
operands:
• A program memory address
• The mode of the table read and table write
instructions
Word or byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
Table 26-1 shows the general symbols used in
describing the instructions. The PIC24F instruction set
summary in Table 26-2 lists all the instructions, along
with the status flags affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand which is typically a
register ‘Wb’ without any address modifier
• The second source operand which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value, ‘f’
• The destination, which could either be the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
Most bit-oriented instructions (including
rotate/shift instructions) have two operands:
The literal instructions that involve data movement may
use some of the following operands:
simple
All instructions are a single word, except for certain
double-word instructions, which were made
double-word instructions so that all the required information is available in these 48 bits. In the second word,
the 8 MSbs are ‘0’s. If this second word is executed as
an instruction (by itself), it will execute as a NOP.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter (PC) is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles, with the additional instruction
cycle(s) executed as a NOP. Notable exceptions are the
BRA (unconditional/computed branch), indirect
CALL/GOTO, all table reads and writes, and
RETURN/RETFIE instructions, which are single-word
instructions but take two or three cycles.
Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if
the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles. The double-word instructions execute in two
instruction cycles.
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register, ‘Wb’)
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TABLE 26-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
Means literal defined by “text”
(text)
Means “content of text”
[text]
Means “the location addressed by text”
{ }
Optional field or operation
Register bit field
.b
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
bit4
4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
Absolute address, label or expression (resolved by the linker)
f
File register address {0000h...1FFFh}
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14
14-bit unsigned literal {0...16384}
lit16
16-bit unsigned literal {0...65535}
lit23
23-bit unsigned literal {0...8388608}; LSB must be ‘0’
None
Field does not require an entry, may be blank
PC
Program Counter
Slit10
10-bit signed literal {-512...511}
Slit16
16-bit signed literal {-32768...32767}
Slit6
6-bit signed literal {-16...16}
Wb
Base W register {W0..W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor working register pair (direct addressing)
Wn
One of 16 working registers {W0..W15}
Wnd
One of 16 destination working registers {W0..W15}
Wns
One of 16 source working registers {W0..W15}
WREG
W0 (working register used in file register instructions)
Ws
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
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TABLE 26-2:
INSTRUCTION SET OVERVIEW
Assembly
Mnemonic
ADD
ADDC
AND
ASR
BCLR
BRA
BSET
BSW
BTG
BTSC
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
ADD
f
f = f + WREG
1
1
C, DC, N, OV, Z
ADD
f,WREG
WREG = f + WREG
1
1
C, DC, N, OV, Z
ADD
#lit10,Wn
Wd = lit10 + Wd
1
1
C, DC, N, OV, Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
1
C, DC, N, OV, Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
1
C, DC, N, OV, Z
ADDC
f
f = f + WREG + (C)
1
1
C, DC, N, OV, Z
ADDC
f,WREG
WREG = f + WREG + (C)
1
1
C, DC, N, OV, Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
1
1
C, DC, N, OV, Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
1
C, DC, N, OV, Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
1
C, DC, N, OV, Z
AND
f
f = f .AND. WREG
1
1
N, Z
AND
f,WREG
WREG = f .AND. WREG
1
1
N, Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
1
1
N, Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
1
1
N, Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
1
1
N, Z
ASR
f
f = Arithmetic Right Shift f
1
1
C, N, OV, Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
1
1
C, N, OV, Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
1
1
C, N, OV, Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
1
1
N, Z
ASR
Wb,#lit4,Wnd
Wnd = Arithmetic Right Shift Wb by lit4
1
1
N, Z
BCLR
f,#bit4
Bit Clear f
1
1
None
BCLR
Ws,#bit4
Bit Clear Ws
1
1
None
BRA
C,Expr
Branch if Carry
1
1 (2)
None
BRA
GE,Expr
Branch if Greater than or Equal
1
1 (2)
None
BRA
GEU,Expr
Branch if Unsigned Greater than or Equal
1
1 (2)
None
BRA
GT,Expr
Branch if Greater than
1
1 (2)
None
BRA
GTU,Expr
Branch if Unsigned Greater than
1
1 (2)
None
BRA
LE,Expr
Branch if Less than or Equal
1
1 (2)
None
BRA
LEU,Expr
Branch if Unsigned Less than or Equal
1
1 (2)
None
BRA
LT,Expr
Branch if Less than
1
1 (2)
None
BRA
LTU,Expr
Branch if Unsigned Less than
1
1 (2)
None
BRA
N,Expr
Branch if Negative
1
1 (2)
None
BRA
NC,Expr
Branch if Not Carry
1
1 (2)
None
BRA
NN,Expr
Branch if Not Negative
1
1 (2)
None
BRA
NOV,Expr
Branch if Not Overflow
1
1 (2)
None
BRA
NZ,Expr
Branch if Not Zero
1
1 (2)
None
BRA
OV,Expr
Branch if Overflow
1
1 (2)
None
BRA
Expr
Branch Unconditionally
1
2
None
BRA
Z,Expr
Branch if Zero
1
1 (2)
None
BRA
Wn
Computed Branch
1
2
None
BSET
f,#bit4
Bit Set f
1
1
None
BSET
Ws,#bit4
Bit Set Ws
1
1
None
BSW.C
Ws,Wb
Write C bit to Ws
1
1
None
BSW.Z
Ws,Wb
Write Z bit to Ws
1
1
None
BTG
f,#bit4
Bit Toggle f
1
1
None
BTG
Ws,#bit4
Bit Toggle Ws
1
1
None
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
1
None
(2 or 3)
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
None
(2 or 3)
2010-2013 Microchip Technology Inc.
DS39881E-page 225
PIC24FJ64GA004 FAMILY
TABLE 26-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
BTSS
BTST
BTSTS
Assembly Syntax
# of
Words
Description
# of
Cycles
Status Flags
Affected
BTSS
f,#bit4
Bit Test f, Skip if Set
1
1
None
(2 or 3)
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
None
(2 or 3)
BTST
f,#bit4
Bit Test f
1
1
Z
BTST.C
Ws,#bit4
Bit Test Ws to C
1
1
C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
1
1
Z
BTST.C
Ws,Wb
Bit Test Ws to C
1
1
C
Z
BTST.Z
Ws,Wb
Bit Test Ws to Z
1
1
BTSTS
f,#bit4
Bit Test then Set f
1
1
Z
BTSTS.C
Ws,#bit4
Bit Test Ws to C, then Set
1
1
C
BTSTS.Z
Ws,#bit4
Bit Test Ws to Z, then Set
1
1
Z
CALL
CALL
lit23
Call Subroutine
2
2
None
CALL
Wn
Call Indirect Subroutine
1
2
None
CLR
CLR
f
f = 0x0000
1
1
None
CLR
WREG
WREG = 0x0000
1
1
None
CLR
Ws
Ws = 0x0000
1
1
None
Clear Watchdog Timer
1
1
WDTO, Sleep
CLRWDT
CLRWDT
COM
COM
f
f=f
1
1
N, Z
COM
f,WREG
WREG = f
1
1
N, Z
COM
Ws,Wd
Wd = Ws
1
1
N, Z
CP
f
Compare f with WREG
1
1
C, DC, N, OV, Z
CP
Wb,#lit5
Compare Wb with lit5
1
1
C, DC, N, OV, Z
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
1
1
C, DC, N, OV, Z
CP0
CP0
f
Compare f with 0x0000
1
1
C, DC, N, OV, Z
CP0
Ws
Compare Ws with 0x0000
1
1
C, DC, N, OV, Z
CPB
CPB
f
Compare f with WREG, with Borrow
1
1
C, DC, N, OV, Z
CPB
Wb,#lit5
Compare Wb with lit5, with Borrow
1
1
C, DC, N, OV, Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1
1
C, DC, N, OV, Z
CPSEQ
CPSEQ
Wb,Wn
Compare Wb with Wn, Skip if =
1
1
None
(2 or 3)
CPSGT
CPSGT
Wb,Wn
Compare Wb with Wn, Skip if >
1
1
None
(2 or 3)
CPSLT
CPSLT
Wb,Wn
Compare Wb with Wn, Skip if <
1
1
None
(2 or 3)
CPSNE
CPSNE
Wb,Wn
Compare Wb with Wn, Skip if
1
1
None
(2 or 3)
DAW
DAW.B
Wn
Wn = Decimal Adjust Wn
1
1
DEC
DEC
f
f = f –1
1
1
C, DC, N, OV, Z
DEC
f,WREG
WREG = f –1
1
1
C, DC, N, OV, Z
CP
C
DEC
Ws,Wd
Wd = Ws – 1
1
1
C, DC, N, OV, Z
DEC2
f
f=f–2
1
1
C, DC, N, OV, Z
DEC2
f,WREG
WREG = f – 2
1
1
C, DC, N, OV, Z
DEC2
Ws,Wd
Wd = Ws – 2
1
1
C, DC, N, OV, Z
DISI
DISI
#lit14
Disable Interrupts for k Instruction Cycles
1
1
None
DIV
DIV.SW
Wm,Wn
Signed 16/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.UW
Wm,Wn
Unsigned 16/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer Divide
1
18
N, Z, C, OV
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
None
FBCL
FFBCL
Ws, Wnd
Find Bit Change from left (MSb) Side
1
1
None
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
DEC2
DS39881E-page 226
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 26-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
GOTO
INC
INC2
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
GOTO
Expr
Go to Address
2
2
None
GOTO
Wn
Go to Indirect
1
2
None
INC
f
f=f+1
1
1
C, DC, N, OV, Z
INC
f,WREG
WREG = f + 1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
INC
Ws,Wd
Wd = Ws + 1
1
1
INC2
f
f=f+2
1
1
C, DC, N, OV, Z
INC2
f,WREG
WREG = f + 2
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
INC2
Ws,Wd
Wd = Ws + 2
1
1
IOR
f
f = f .IOR. WREG
1
1
N, Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N, Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N, Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N, Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N, Z
LNK
LNK
#lit14
Link Frame Pointer
1
1
None
LSR
LSR
f
f = Logical Right Shift f
1
1
C, N, OV, Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C, N, OV, Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C, N, OV, Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N, Z
LSR
Wb,#lit4,Wnd
Wnd = Logical Right Shift Wb by lit4
1
1
N, Z
MOV
f,Wn
Move f to Wn
1
1
None
MOV
[Wns+Slit10],Wnd
Move [Wns+Slit10] to Wnd
1
1
None
MOV
f
Move f to f
1
1
N, Z
MOV
f,WREG
Move f to WREG
1
1
None
MOV
#lit16,Wn
Move 16-bit Literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-bit Literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wns,[Wns+Slit10]
Move Wns to [Wns+Slit10]
1
1
None
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
None
MOV.D
Wns,Wd
Move Double from W(ns):W(ns+1) to Wd
1
2
None
MOV.D
Ws,Wnd
Move Double from Ws to W(nd+1):W(nd)
1
2
None
MUL.SS
Wb,Ws,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5)
1
1
None
MUL
f
W3:W2 = f * WREG
1
1
None
NEG
f
f=f+1
1
1
C, DC, N, OV, Z
NEG
f,WREG
WREG = f + 1
1
1
C, DC, N, OV, Z
NEG
Ws,Wd
IOR
MOV
MUL
NEG
NOP
POP
Wd = Ws + 1
1
1
C, DC, N, OV, Z
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
POP
f
Pop f from Top-of-Stack (TOS)
1
1
None
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to W(nd):W(nd+1)
1
2
None
Pop Shadow Registers
1
1
All
POP.S
PUSH
PUSH
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns+1) to Top-of-Stack (TOS)
1
2
None
Push Shadow Registers
1
1
None
PUSH.S
2010-2013 Microchip Technology Inc.
DS39881E-page 227
PIC24FJ64GA004 FAMILY
TABLE 26-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
PWRSAV
PWRSAV
#lit1
Go into Sleep or Idle mode
1
1
WDTO, Sleep
RCALL
RCALL
Expr
Relative Call
1
2
None
RCALL
Wn
Computed Call
1
2
None
REPEAT
REPEAT
#lit14
Repeat Next Instruction lit14 + 1 times
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 times
1
1
None
RESET
RESET
Software Device Reset
1
1
None
RETFIE
RETFIE
Return from Interrupt
1
3 (2)
None
RETLW
RETLW
Return with Literal in Wn
1
3 (2)
None
RETURN
RETURN
Return from Subroutine
1
3 (2)
None
RLC
RLC
f
f = Rotate Left through Carry f
1
1
C, N, Z
RLC
f,WREG
WREG = Rotate Left through Carry f
1
1
C, N, Z
C, N, Z
RLNC
RRC
RRNC
#lit10,Wn
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
RLNC
f
f = Rotate Left (No Carry) f
1
1
N, Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N, Z
N, Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
RRC
f
f = Rotate Right through Carry f
1
1
C, N, Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C, N, Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C, N, Z
RRNC
f
f = Rotate Right (No Carry) f
1
1
N, Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N, Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
1
1
N, Z
SE
SE
Ws,Wnd
Wnd = Sign-Extended Ws
1
1
C, N, Z
SETM
SETM
f
f = FFFFh
1
1
None
SETM
WREG
WREG = FFFFh
1
1
None
SETM
Ws
Ws = FFFFh
1
1
None
SL
f
f = Left Shift f
1
1
C, N, OV, Z
SL
f,WREG
WREG = Left Shift f
1
1
C, N, OV, Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C, N, OV, Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N, Z
SL
Wb,#lit4,Wnd
Wnd = Left Shift Wb by lit4
1
1
N, Z
SUB
f
f = f – WREG
1
1
C, DC, N, OV, Z
SUB
f,WREG
WREG = f – WREG
1
1
C, DC, N, OV, Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C, DC, N, OV, Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C, DC, N, OV, Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C, DC, N, OV, Z
SUBB
f
f = f – WREG – (C)
1
1
C, DC, N, OV, Z
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C, DC, N, OV, Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C, DC, N, OV, Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C, DC, N, OV, Z
SL
SUB
SUBB
SUBR
SUBBR
SWAP
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
C, DC, N, OV, Z
SUBR
f
f = WREG – f
1
1
C, DC, N, OV, Z
SUBR
f,WREG
WREG = WREG – f
1
1
C, DC, N, OV, Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
SUBBR
f
f = WREG – f – (C)
1
1
C, DC, N, OV, Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C, DC, N, OV, Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
SWAP.b
Wn
Wn = Nibble Swap Wn
1
1
None
SWAP
Wn
Wn = Byte Swap Wn
1
1
None
DS39881E-page 228
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 26-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
TBLRDH
TBLRDH
Ws,Wd
Read Prog to Wd
1
2
TBLRDL
TBLRDL
Ws,Wd
Read Prog to Wd
1
2
None
TBLWTH
TBLWTH
Ws,Wd
Write Ws to Prog
1
2
None
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog
1
2
None
ULNK
ULNK
Unlink Frame Pointer
1
1
None
XOR
XOR
f
f = f .XOR. WREG
1
1
N, Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N, Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N, Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N, Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N, Z
ZE
Ws,Wnd
Wnd = Zero-Extend Ws
1
1
C, Z, N
ZE
2010-2013 Microchip Technology Inc.
None
DS39881E-page 229
PIC24FJ64GA004 FAMILY
NOTES:
DS39881E-page 230
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
27.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24FJ64GA004 family electrical characteristics. Additional information will
be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24FJ64GA004 family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +135°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)
Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V
Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +3.0V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin (Note 1)................................................................................................................250 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 1)....................................................................................................200 mA
Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 27-1).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
2010-2013 Microchip Technology Inc.
DS39881E-page 231
PIC24FJ64GA004 FAMILY
27.1
DC Characteristics
FIGURE 27-1:
PIC24FJ64GA004 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
3.00V
2.75V
Voltage (VDDCORE)(1)
2.75V
2.50V
PIC24FJ64GA004/32GA004/64GA002/32GA002
2.35V
2.25V
2.00V
32 MHz
16 MHz
Frequency
For frequencies between 16 MHz and 32 MHz, FMAX = (45.7 MHz/V) * (VDDCORE – 2V) + 16 MHz.
Note 1:
FIGURE 27-2:
WHEN the voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCOREVDD3.6V.
PIC24FJ64GA004 FAMILY VOLTAGE-FREQUENCY GRAPH
(EXTENDED TEMPERATURE)
3.00V
2.75V
Voltage (VDDCORE)(1)
2.75V
2.50V
PIC24FJ64GA004/32GA004/64GA002/32GA002
2.35V
2.25V
2.00V
16 MHz
24 MHz
Frequency
For frequencies between 16 MHz and 24 MHz, FMAX = (22.9 MHz/V) * (VDDCORE – 2V) + 16 MHz.
Note 1:
DS39881E-page 232
WHEN the voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCOREVDD3.6V.
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 27-1:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
TJ
-40
—
+140
°C
Operating Ambient Temperature Range
TA
-40
—
+125
°C
PIC24FJ64GA004 Family:
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
PI/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 27-2:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 300 mil SOIC
JA
49
—
°C/W
(Note 1)
Package Thermal Resistance, 6x6x0.9 mm QFN
JA
33.7
—
°C/W
(Note 1)
Package Thermal Resistance, 8x8x1 mm QFN
JA
28
—
°C/W
(Note 1)
Package Thermal Resistance, 10x10x1 mm TQFP
JA
39.3
—
°C/W
(Note 1)
Note 1:
Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations.
2010-2013 Microchip Technology Inc.
DS39881E-page 233
PIC24FJ64GA004 FAMILY
TABLE 27-3:
DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICS
Param
Symbol
No.
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min
Typ(1)
Max
Units
VDD
VBORMIN
—
3.6
V
Regulator enabled
VDD
VDDCORE
—
3.6
V
Regulator disabled
2.0
—
2.75
V
Regulator disabled
Characteristic
Conditions
Operating Voltage
DC10 Supply Voltage
VDDCORE
DC12 VDR
RAM Data Retention
Voltage(2)
1.5
—
—
V
DC16 VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
—
—
VSS
V
DC17 SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05
—
—
V/ms
DC18 VBOR
Brown-out Reset
Voltage
1.8
2.1
2.2
V
Note 1:
2:
0-3.3V in 0.1s
0-2.5V in 60 ms
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered without losing RAM data.
DS39881E-page 234
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 27-4:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter No.
Typical(1)
Max
Operating Current (IDD): PMD Bits are
Units
Conditions
Set(2)
DC20
0.650
0.850
mA
-40°C
DC20a
0.650
0.850
mA
+25°C
DC20b
0.650
0.850
mA
+85°C
DC20c
0.650
0.850
mA
+125°C
DC20d
1.2
1.6
mA
-40°C
DC20e
1.2
1.6
mA
+25°C
DC20f
1.2
1.6
mA
+85°C
DC20g
1.2
1.6
mA
+125°C
DC23
2.6
3.4
mA
-40°C
DC23a
2.6
3.4
mA
+25°C
DC23b
2.6
3.4
mA
+85°C
DC23c
2.6
3.4
mA
+125°C
DC23d
4.1
5.4
mA
-40°C
DC23e
4.1
5.4
mA
+25°C
DC23f
4.1
5.4
mA
+85°C
DC23g
4.1
5.4
mA
+125°C
DC24
13.5
17.6
mA
-40°C
DC24a
13.5
17.6
mA
+25°C
DC24b
13.5
17.6
mA
+85°C
DC24c
13.5
17.6
mA
+125°C
DC24d
15
20
mA
-40°C
DC24e
15
20
mA
+25°C
DC24f
15
20
mA
+85°C
DC24g
15
20
mA
+125°C
DC31
13
17
A
-40°C
DC31a
13
17
A
+25°C
DC31b
20
26
A
+85°C
DC31c
40
50
A
+125°C
DC31d
54
70
A
-40°C
DC31e
54
70
A
+25°C
DC31f
95
124
A
+85°C
120
260
A
+125°C
DC31g
Note 1:
2:
3:
4:
2.0V(3)
1 MIPS
3.3V(4)
2.0V(3)
4 MIPS
3.3V(4)
2.5V(3)
16 MIPS
3.3V(4)
2.0V(3)
LPRC (31 kHz)
3.3V(4)
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the
current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square
wave from rail-to-rail. All I/O pins are configured as inputs and pulled to VDD.
MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No
peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set.
On-chip voltage regulator is disabled (DISVREG tied to VDD).
On-chip voltage regulator is enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect
(BOD) are enabled.
2010-2013 Microchip Technology Inc.
DS39881E-page 235
PIC24FJ64GA004 FAMILY
TABLE 27-5:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Idle Current (IIDLE): Core Off, Clock On Base Current, PMD Bits are Set(2)
DC40
150
200
A
-40°C
DC40a
150
200
A
+25°C
DC40b
150
200
A
+85°C
DC40c
165
220
A
+125°C
DC40d
250
325
A
-40°C
DC40e
250
325
A
+25°C
DC40f
250
325
A
+85°C
+125°C
DC40g
275
360
A
DC43
0.55
0.72
mA
-40°C
DC43a
0.55
0.72
mA
+25°C
DC43b
0.55
0.72
mA
+85°C
DC43c
0.60
0.8
mA
+125°C
DC43d
0.82
1.1
mA
-40°C
DC43e
0.82
1.1
mA
+25°C
DC43f
0.82
1.1
mA
+85°C
DC43g
0.91
1.2
mA
+125°C
DC47
3
4
mA
-40°C
DC47a
3
4
mA
+25°C
DC47b
3
4
mA
+85°C
DC47c
3.3
4.4
mA
+125°C
DC47d
3.5
4.6
mA
-40°C
DC47e
3.5
4.6
mA
+25°C
DC47f
3.5
4.6
mA
+85°C
DC47g
3.9
5.1
mA
+125°C
DC50
0.85
1.1
mA
-40°C
DC50a
0.85
1.1
mA
+25°C
DC50b
0.85
1.1
mA
+85°C
DC50c
0.94
1.2
mA
+125°C
DC50d
1.2
1.6
mA
-40°C
DC50e
1.2
1.6
mA
+25°C
DC50f
1.2
1.6
mA
+85°C
1.3
1.8
mA
+125°C
DC50g
Note 1:
2:
3:
4:
2.0V(3)
1 MIPS
3.3V(4)
2.0V(3)
4 MIPS
3.3V(4)
2.5V(3)
16 MIPS
3.3V(4)
2.0V(3)
FRC (4 MIPS)
3.3V(4)
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
The test conditions for all IIDLE measurements are as follows: OSCI driven with external square wave from
rail-to-rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled.
CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all
of the Peripheral Module Disable (PMD) bits are set.
On-chip voltage regulator is disabled (DISVREG tied to VDD).
On-chip voltage regulator is enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect
(BOD) are enabled.
DS39881E-page 236
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 27-5:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Idle Current (IIDLE): Core Off, Clock On Base Current, PMD Bits are Set(2)
DC51
4
6
A
-40°C
DC51a
4
6
A
+25°C
DC51b
8
16
A
+85°C
DC51c
20
50
A
+125°C
DC51d
42
55
A
-40°C
DC51e
42
55
A
+25°C
DC51f
70
91
A
+85°C
DC51g
100
180
A
+125°C
Note 1:
2:
3:
4:
2.0V(3)
LPRC (31 kHz)
3.3V(4)
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
The test conditions for all IIDLE measurements are as follows: OSCI driven with external square wave from
rail-to-rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled.
CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all
of the Peripheral Module Disable (PMD) bits are set.
On-chip voltage regulator is disabled (DISVREG tied to VDD).
On-chip voltage regulator is enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect
(BOD) are enabled.
2010-2013 Microchip Technology Inc.
DS39881E-page 237
PIC24FJ64GA004 FAMILY
TABLE 27-6:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2)
DC60
0.1
1
A
-40°C
DC60a
0.15
1
A
+25°C
DC60m
2.2
7.4
A
+60°C
DC60b
3.7
12
A
+85°C
DC60j
15
50
A
+125°C
DC60c
0.2
1
A
-40°C
DC60d
0.25
1
A
+25°C
DC60n
2.6
15
A
+60°C
DC60e
4.2
25
A
+85°C
DC60k
16
100
A
+125°C
DC60f
3.3
9
A
-40°C
DC60g
3.5
10
A
+25°C
DC60o
6.7
22
A
+60°C
DC60h
9
30
A
+85°C
DC60l
36
120
A
+125°C
DC61
1.75
3
A
-40°C
DC61a
1.75
3
A
+25°C
DC61m
1.75
3
A
+60°C
DC61b
1.75
3
A
+85°C
DC61j
3.5
6
A
+125°C
DC61c
2.4
4
A
-40°C
DC61d
2.4
4
A
+25°C
DC61n
2.4
4
A
+60°C
DC61e
2.4
4
A
+85°C
DC61k
4.8
8
A
+125°C
DC61f
2.8
5
A
-40°C
DC61g
2.8
5
A
+25°C
DC61o
2.8
5
A
+60°C
DC61h
2.8
5
A
+85°C
5.6
10
A
+125°C
DC61l
Note 1:
2:
3:
4:
5:
2.0V(3)
2.5V(3)
Base Power-Down Current(5)
3.3V(4)
2.0V(3)
2.5V(3)
Watchdog Timer Current: IWDT(5)
3.3V(4)
Data in the Typical column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled high. WDT, etc., are all switched off.
On-chip voltage regulator is disabled (DISVREG tied to VDD).
On-chip voltage regulator is enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out
Detect (BOD) are enabled.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
DS39881E-page 238
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 27-6:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2)
DC62
8
16
A
-40°C
DC62a
12
16
A
+25°C
DC62m
12
16
A
+60°C
DC62b
12
16
A
+85°C
DC62j
18
23
A
+125°C
DC62c
9
16
A
-40°C
DC62d
12
16
A
+25°C
DC62n
12
16
A
+60°C
DC62e
12.5
16
A
+85°C
DC62k
20
25
A
+125°C
DC62f
10.3
18
A
-40°C
DC62g
13.4
18
A
+25°C
DC62o
14.0
18
A
+60°C
DC62h
14.2
18
A
+85°C
+125°C
DC62l
23
28
A
DC63
2
—
A
-40°C
DC63a
2
—
A
+25°C
DC63b
6
—
A
+85°C
DC63c
2
—
A
-40°C
DC63d
2
—
A
+25°C
+85°C
DC63e
7
—
A
DC63f
2
—
A
-40°C
DC63g
3
—
A
+25°C
DC63h
7
—
A
+85°C
Note 1:
2:
3:
4:
5:
2.0V(3)
2.5V(3)
RTCC + Timer1 w/32 kHz Crystal:
RTCC, ITI32(5)
3.3V(4)
2.0V(3)
2.5V
(3)
RTCC + Timer1 w/Low-Power
32 kHz Crystal
(SOCSEL = 01): RTCC,
ITI32(5)
3.3V(4)
Data in the Typical column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled high. WDT, etc., are all switched off.
On-chip voltage regulator is disabled (DISVREG tied to VDD).
On-chip voltage regulator is enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out
Detect (BOD) are enabled.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
2010-2013 Microchip Technology Inc.
DS39881E-page 239
PIC24FJ64GA004 FAMILY
TABLE 27-7:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Param
Sym
No.
VIL
Characteristic
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min
Typ(1)
Max
Units
Conditions
Input Low Voltage(4)
DI10
I/O Pins
VSS
—
0.2 VDD
V
DI11
PMP Pins
VSS
—
0.15 VDD
V
DI15
MCLR
VSS
—
0.2 VDD
V
DI16
OSCI (XT mode)
VSS
—
0.2 VDD
V
DI17
OSCI (HS mode)
VSS
—
0.2 VDD
V
DI18
I/O Pins with I2C™ Buffer
VSS
—
0.3 VDD
V
SMBus disabled
I/O Pins with SMBus Buffer
VSS
—
0.8
V
SMBus enabled
I/O Pins:
with Analog Functions
Digital Only
0.8 VDD
0.8 VDD
—
—
VDD
5.5
V
V
PMP Pins:
with Analog Functions
Digital Only
0.25 VDD + 0.8
0.25 VDD + 0.8
—
—
VDD
5.5
V
V
DI19
VIH
DI20
DI21
PMPTTL = 1
Input High Voltage(4)
PMPTTL = 1
DI25
MCLR
0.8 VDD
—
VDD
V
DI26
OSCI (XT mode)
0.7 VDD
—
VDD
V
DI27
OSCI (HS mode)
0.7 VDD
—
VDD
V
DI28
I/O Pins with I2C Buffer:
with Analog Functions
Digital Only
0.7 VDD
0.7 VDD
—
—
VDD
5.5
V
V
2.1
2.1
—
—
VDD
5.5
V
v
2.5V VPIN VDD
50
250
400
A
VDD = 3.3V, VPIN = VSS
DI29
I/O Pins with SMBus Buffer:
with Analog Functions
Digital Only
DI30
ICNPU CNxx Pull-up Current
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Refer to Table 1-2 for I/O pin buffer types.
Parameter is characterized but not tested.
Non-5V tolerant pins, VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources greater
than 5.5V.
Injection currents > | 0 | can affect the performance of all analog peripherals (e.g., A/D, comparators,
internal band gap reference, etc.)
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
DS39881E-page 240
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 27-7:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Param
Sym
No.
DI31
IPU
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min
Typ(1)
Max
Units
Maximum Load Current
for Digital High Detection
with Internal Pull-up
—
—
30
µA
VDD = 2.0V
—
—
100
µA
VDD = 3.3V
Conditions
Input Leakage Current(2,3)
IIL
DI50
I/O Ports
—
—
+1
A
VSS VPIN VDD,
Pin at high-impedance
DI51
Analog Input Pins
—
—
+1
A
VSS VPIN VDD,
Pin at high-impedance
DI55
MCLR
—
—
+1
A
VSS VPIN VDD
DI56
OSCI
—
—
+1
A
VSS VPIN VDD,
XT and HS modes
0
—
-5(5,8)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
RB11, SOSCI, SOSCO,
D+, D-, VUSB, and VBUS
0
—
+5(6,7,8)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
RB11, SOSCI, SOSCO,
D+, D-, VUSB, and VBUS,
and all 5V tolerant pins(7)
-20(9)
—
+20(9)
mA
Absolute instantaneous
sum of all ± input injection
currents from all I/O pins
(| IICL + | IICH |) IICT)
IICL
Input Low Injection
Current
DI60a
IICH
Input High Injection
Current
DI60b
IICT Total Input Injection
Current
DI60c
(sum of all I/O and control
pins)
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Refer to Table 1-2 for I/O pin buffer types.
Parameter is characterized but not tested.
Non-5V tolerant pins, VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources greater
than 5.5V.
Injection currents > | 0 | can affect the performance of all analog peripherals (e.g., A/D, comparators,
internal band gap reference, etc.)
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
2010-2013 Microchip Technology Inc.
DS39881E-page 241
PIC24FJ64GA004 FAMILY
TABLE 27-8:
DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Param
No.
Sym
VOL
Characteristic
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min
Typ(1)
Max
Units
—
0.4
V
Conditions
Output Low Voltage
IOL = 8.5 mA, VDD = 3.6V
DO10
All I/O Pins
—
—
—
0.4
V
IOL = 5.0 mA, VDD = 2.0V
DO16
All I/O Pins
—
—
0.4
V
IOL = 8.0 mA, VDD = 3.6V, +125°C
—
—
0.4
V
IOL = 4.5 mA, VDD = 2.0V, +125°C
3
—
—
V
IOH = -3.0 mA, VDD = 3.6V
VOH
Output High Voltage
DO20
All I/O Pins
DO26
All I/O Pins
Note 1:
—
—
V
IOH = -1.0 mA, VDD = 2.0V
3
—
—
V
IOH = -2.5 mA, VDD = 3.6V, +125°C
1.65
—
—
V
IOH = -0.5 mA, VDD = 2.0V, +125°C
Data in “Typ” column is at +25°C unless otherwise stated. Parameters are for design guidance only and are not
tested.
TABLE 27-9:
DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Param
No.
1.65
Sym
Characteristic
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min
Typ(1)
Max
Units
Conditions
Program Flash Memory
D130
EP
Cell Endurance
10000
—
—
E/W
D131
VPR
VDD for Read
VMIN
—
3.6
V
D132B
VPEW
VDDCORE for Self-Timed
Write
2.25
—
2.75
V
D133A
TIW
Self-Timed Write Cycle
Time
—
3
—
ms
D134
TRETD Characteristic Retention
20
—
—
Year
D135
IDDP
—
7
—
mA
Note 1:
Supply Current during
Programming
-40C to +125C
VMIN = Minimum operating voltage
Provided no other specifications are
violated
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
DS39881E-page 242
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 27-10: COMPARATOR SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Symbol
D300
VIOFF
Characteristic
Input Offset Voltage*
Min
Typ
Max
Units
—
10
30
mV
D301
VICM
Input Common-Mode Voltage*
0
—
VDD
V
D302
CMRR
Common-Mode Rejection
Ratio*
55
—
—
dB
300
TRESP
Response Time*(1)
—
150
400
ns
301
TMC2OV
Comparator Mode Change to
Output Valid*
—
—
10
s
*
Note 1:
Comments
Parameters are characterized but not tested.
Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 27-11: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
VDD/24
—
VDD/32
LSb
—
—
1
LSb
VRD310 CVRES
Resolution
VRD311 CVRAA
Absolute Accuracy
VRD312 CVRUR
Unit Resistor Value (R)
—
2k
—
VR310
Settling Time(1)
—
—
10
s
Note 1:
TSET
Comments
Settling time is measured while CVRR = 1 and the CVR bits transition from ‘0000’ to ‘1111’.
TABLE 27-12: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +125°C (unless otherwise stated)
Param
No.
Symbol
Characteristics
2:
Typ
Max
Units
Comments
VRGOUT
Regulator Output Voltage
—
2.5
—
V
VBG
Band Gap Reference Voltage
—
1.2
—
V
CEFC
External Filter Capacitor
Value
4.7
10
—
F
Series resistance < 3 Ohm
recommended;
< 5 Ohm required
TVREG
Voltage Regulator Start-up
Time
—
10
—
s
POR, BOR or when
PMSLP = 1
—
25
—
s
PMSLP = 0,
WUTSEL = 01(1)
—
190
—
s
PMSLP = 0,
WUTSEL = 11(2)
—
64
—
ms
DISVREG = VDD
TPWRT
Note 1:
Min
Available only in devices with a major silicon revision level of B or later (DEVREV register value is 3042h
or greater).
WUTSELx Configuration bits setting is applicable only in devices with a major silicon revision level of B or
later. This specification also applies to all devices prior to Revision Level B whenever PMSLP = 0.
2010-2013 Microchip Technology Inc.
DS39881E-page 243
PIC24FJ64GA004 FAMILY
27.2
AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24FJ64GA004 family AC characteristics and timing
parameters.
TABLE 27-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Section 27.1 “DC Characteristics”.
AC CHARACTERISTICS
FIGURE 27-3:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for All Pins Except OSCO
Load Condition 2 – for OSCO
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSCO
15 pF for OSCO output
VSS
TABLE 27-14: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
DO50
COSC2
OSCO/CLKO Pin
—
—
15
pF
In XT and HS modes when
external clock is used to drive
OSCI
DO56
CIO
All I/O Pins and OSCO
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C™ mode
Note 1:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS39881E-page 244
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
FIGURE 27-4:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
OSCI
OS20
OS30
OS30
OS31
OS31
OS25
CLKO
OS40
OS41
TABLE 27-15: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Sym
No.
OS10
Characteristic
FOSC External CLKI Frequency
(External clocks allowed
only in EC mode)
Oscillator Frequency
Standard Operating Conditions: 2.0 to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min
Typ(1)
Max
Units
DC
4
DC
4
—
—
—
—
32
8
24
6
MHz
MHz
MHz
MHz
EC, -40°C TA +85°C
ECPLL, -40°C TA +85°C
EC, -40°C TA +125°C
ECPLL, -40°C TA +125°C
3
3
10
31
3
10
—
—
—
—
—
—
10
8
32
33
6
24
MHz
MHz
MHz
kHz
MHz
MHz
XT
XTPLL, -40°C TA +85°C
HS, -40°C TA +85°C
SOSC
XTPLL, -40°C TA +125°C
HS, -40°C TA +125°C
—
—
—
—
Conditions
OS20
TOSC TOSC = 1/FOSC
OS25
TCY
62.5
—
DC
ns
OS30
TosL, External Clock In (OSCI)
TosH High or Low Time
0.45 x TOSC
—
—
ns
EC
OS31
TosR, External Clock In (OSCI)
TosF Rise or Fall Time
—
—
20
ns
EC
OS40
TckR
CLKO Rise Time(3)
—
6
10
ns
OS41
TckF
CLKO Fall Time(3)
—
6
10
ns
Note 1:
2:
3:
Instruction Cycle Time(2)
See Parameter OS10 for
FOSC value
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type, under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an
external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time
limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the
Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
2010-2013 Microchip Technology Inc.
DS39881E-page 245
PIC24FJ64GA004 FAMILY
TABLE 27-16: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
OS50
Characteristic(1)
Sym
FPLLI
PLL Input Frequency
Range
OS51
FSYS
OS52
TLOCK PLL Start-up Time
(Lock Time)
OS53
DCLK
Note 1:
2:
PLL Output Frequency
Range
CLKO Stability (Jitter)
Min
Typ(2)
Max
Units
Conditions
3
—
8
MHz
3
—
6
MHz
ECPLL, HSPLL, XTPLL modes,
-40°C TA +85°C
ECPLL, HSPLL, XTPLL modes,
-40°C TA +125°C
8
8
—
—
32
24
MHz
MHz
—
—
2
ms
-2
1
2
%
-40°C TA +85°C
-40°C TA +125°C
Measured over 100 ms period
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 27-17: INTERNAL RC OSCILLATOR SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Sym
TFRC
Characteristic
FRC Start-up Time
TLPRC LPRC Start-up Time
Min
Typ
Max
Units
—
15
—
s
—
40
—
s
Conditions
TABLE 27-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY
AC CHARACTERISTICS
Param
No.
F20
F21
Note 1:
2:
Characteristic
Internal FRC @ 8 MHz(1)
LPRC @ 31 kHz(2)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min
Typ
Max
Units
Conditions
-2
—
2
%
+25°C
-5
—
5
%
-40°C TA +85°C
-7
—
7
%
+125°C
-15
—
15
%
+25°C
-15
—
15
%
-40°C TA +85°C
-30
—
30
%
+125°C
3.0V VDD 3.6V
3.0V VDD 3.6V
Frequency calibrated at +25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.
Change of LPRC frequency as VDD changes.
DS39881E-page 246
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
FIGURE 27-5:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
Old Value
New Value
DO31
DO32
Note: Refer to Figure 27-3 for load conditions.
TABLE 27-19: CLKO AND I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Sym
Characteristic
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min
Typ(1)
Max
Units
DO31
TIOR
Port Output Rise Time
—
10
25
ns
DO32
TIOF
Port Output Fall Time
—
10
25
ns
DI35
TINP
INTx Pin High or Low
Time (output)
20
—
—
ns
DI40
TRBP
CNx High or Low Time
(input)
2
—
—
TCY
Note 1:
Conditions
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2010-2013 Microchip Technology Inc.
DS39881E-page 247
PIC24FJ64GA004 FAMILY
TABLE 27-20: A/D MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01 AVDD
Module VDD Supply
Greater of:
VDD – 0.3
or 2.0
—
Lesser of:
VDD + 0.3
or 3.6
V
AD02 AVSS
Module VSS Supply
VSS – 0.3
—
VSS + 0.3
V
Reference Inputs
AD05 VREFH
Reference Voltage High
AVSS + 1.7
—
AVDD
V
AD06 VREFL
Reference Voltage Low
AVSS
—
AVDD – 1.7
V
AD07 VREF
Absolute Reference
Voltage
AVSS – 0.3
—
AVDD + 0.3
V
AD08 IVREF
Reference Voltage Input
Current
—
—
1.25
mA
AD09 ZREF
Reference Input Impedance
—
10k
—
Measured during sampling,
3.3V, +25°C
(Note 1)
Measured during conversion,
3.3V, +25°C (Note 1)
Analog Input
AD10 VINH-VINL Full-Scale Input Span
AD11
VIN
Absolute Input Voltage
VREFL
—
VREFH
V
AVSS – 0.3
—
AVDD + 0.3
V
AVDD/2
V
AD12 VINL
Absolute VINL Input Voltage AVSS – 0.3
AD13
Leakage Current
—
±1
±610
nA
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V,
Source Impedance = 2.5 k
AD17 RIN
Recommended
Impedance of Analog
Voltage Source
—
—
2.5K
10-bit
AD20b Nr
Resolution
—
10
—
bits
AD21b INL
Integral Nonlinearity
—
±1
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DS39881E-page 260
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
2010-2013 Microchip Technology Inc.
DS39881E-page 261
PIC24FJ64GA004 FAMILY
DS39881E-page 262
2010-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
2010-2013 Microchip Technology Inc.
DS39881E-page 263
PIC24FJ64GA004 FAMILY
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