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PIC24FJ32GA104T-I/PT

PIC24FJ32GA104T-I/PT

  • 厂商:

    ACTEL(微芯科技)

  • 封装:

    TQFP44

  • 描述:

    IC MCU 16BIT 32KB FLASH 44TQFP

  • 数据手册
  • 价格&库存
PIC24FJ32GA104T-I/PT 数据手册
PIC24FJ64GA104 Family Data Sheet 28/44-Pin, 16-Bit General Purpose Flash Microcontrollers with nanoWatt XLP Technology  2010 Microchip Technology Inc. DS39951C Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN:978-1-60932-440-7 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39951C-page 2  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 28/44-Pin, 16-Bit General Purpose Flash Microcontrollers with nanoWatt XLP Technology Power Management Modes: Special Microcontroller Features (continued): • Selectable Power Management modes with nanoWatt XLP Technology for Extremely Low Power: - Deep Sleep mode allows near total power-down (20 nA typical and 500 nA with RTCC or WDT), along with the ability to wake-up on external triggers, or self-wake on programmable WDT or RTCC alarm - Extreme low-power DSBOR for Deep Sleep, LPBOR for all other modes - Sleep mode shuts down peripherals and core for substantial power reduction, fast wake-up - Idle mode shuts down the CPU and peripherals for significant power reduction, down to 4.5 A typical - Doze mode enables CPU clock to run slower than peripherals - Alternate Clock modes allow on-the-fly switching to a lower clock speed for selective power reduction during Run mode, down to 15 A typical • Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary • Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip FRC Oscillator • On-Chip 2.5V Regulator • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Two Flexible Watchdog Timers (WDT) for Reliable Operation: - Standard programmable WDT for normal operation - Extreme low-power WDT with programmable period of 2 ms to 26 days for Deep Sleep mode • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via 2 Pins • JTAG Boundary Scan Support High-Performance CPU: • Modified Harvard Architecture • Up to 16 MIPS Operation @ 32 MHz • 8 MHz Internal Oscillator with: - 4x PLL option - Multiple divide options • 17-Bit x 17-Bit Single-Cycle Hardware Fractional/integer Multiplier • 32-Bit by 16-Bit Hardware Divider • 16 x 16-Bit Working Register Array • C Compiler Optimized Instruction Set Architecture: - 76 base instructions - Flexible addressing modes • Linear Program Memory Addressing, up to 12 Mbytes • Linear Data Memory Addressing, up to 64 Kbytes • Two Address Generation Units for Separate Read and Write Addressing of Data Memory Analog Features: • 10-Bit, up to 13-Channel Analog-to-Digital (A/D) Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Three Analog Comparators with Programmable Input/Output Configuration • Charge Time Measurement Unit (CTMU): - Supports capacitive touch sensing for touch screens and capacitive switches - Provides high-resolution time measurement and simple temperature sensing Special Microcontroller Features: Operating Voltage Range of 2.0V to 3.6V Self-Reprogrammable under Software Control 5.5V Tolerant Input (digital pins only) High-Current Sink/Source (18 mA/18 mA) on All I/O pins PIC24FJ Device Program Memory (Bytes) SRAM (Bytes) Remappable Pins Timers 16-Bit Capture Input Compare/PWM Output UART w/ IrDA® SPI I2C™ 10-Bit A/D (ch) Comparators PMP/PSP RTCC CTMU Remappable Peripherals Pins • • • • 32GA102 28 32K 8K 16 5 5 5 2 2 2 10 3 Y Y Y 64GA102 28 64K 8K 16 5 5 5 2 2 2 10 3 Y Y Y 32GA104 44 32K 8K 26 5 5 5 2 2 2 13 3 Y Y Y 64GA104 44 64K 8K 26 5 5 5 2 2 2 13 3 Y Y Y  2010 Microchip Technology Inc. DS39951C-page 3 PIC24FJ64GA104 FAMILY Peripheral Features: • Two UART modules: - Supports RS-485, RS-232 and LIN/J2602 - On-chip hardware encoder/decoder for IrDA® - Auto-wake-up on Start bit - Auto-Baud Detect (ABD) - 4-level deep FIFO buffer • Five 16-Bit Timers/Counters with Programmable Prescaler • Five 16-Bit Capture Inputs, each with a Dedicated Time Base • Five 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base • Programmable, 32-Bit Cyclic Redundancy Check (CRC) Generator • Configurable Open-Drain Outputs on Digital I/O Pins • Up to 3 External Interrupt Sources • Peripheral Pin Select: - Allows independent I/O mapping of many peripherals - Up to 26 available pins (44-pin devices) - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes • 8-Bit Parallel Master Port (PMP/PSP): - Up to 16-bit multiplexed addressing, with up to 11 dedicated address pins on 44-pin devices - Programmable polarity on control lines - Supports legacy Parallel Slave Port • Hardware Real-Time Clock/Calendar (RTCC): - Provides clock, calendar and alarm functions - Functions even in Deep Sleep mode • Two 3-Wire/4-Wire SPI modules (support 4 Frame modes) with 8-Level FIFO Buffer • Two I2C™ modules support Multi-Master/Slave mode and 7-Bit/10-Bit Addressing Pin Diagrams 28-Pin SPDIP, SOIC, SSOP(1) Legend: Note 1: 2: DS39951C-page 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC24FJXXGA102 MCLR AN0/C3INC/VREF+/CN2/CTED1/RA0 AN1/C3IND/VREF-/CN3/CTED2/RA1 PGED1/AN2/C2INB/RP0/CN4/RB0 PGEC1/AN3/C2INA/RP1/CN5/RB1 AN4/C1INB/RP2/SDA2/CN6/RB2 AN5/C1INA/RP3/SCL2/CN7/RB3 VSS OSCI/CLKI/C1IND/CN30/RA2 OSCO/CLKO/PMA0/CN29/RA3 SOSCI/C2IND/RP4/PMBE/CN1/RB4 SOSCO/SCLKI/T1CK/C2INC/CN0/PMA1/RA4 VDD PGED3/RP5/ASDA1(2)/CN27/PMD7/RB5 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VSS AN9/C3INA/RP15/CN11/PMCS1/RB15 AN10/C3INB/CVREF/RTCC/RP14/CN12/PMWR/RB14 AN11/C1INC/RP13/CN13/PMRD/REFO/RB13 AN12/RP12/CN14/PMD0/RB12 PGEC2/TMS/RP11/CN15/PMD1/RB11 PGED2/TDI/RP10/CN16/PMD2/RB10 VCAP/VDDCORE DISVREG TDO/RP9/SDA1/CN21/PMD3/RB9 TCK/RP8/SCL1/CN22/PMD4/RB8 RP7/INT0/CN23/PMD5/RB7 PGC3/EMUC3/RP6/ASCL1(2)/CN24/PMD6/RB6 RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins. Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set.  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY AN1/C3IND/VREF-/CN3/CTED2/RA1 AN0/C3INC/VREF+/CN2/CTED1/RA0 MCLR 28-Pin QFN(1,3) VDD VSS AN9/C3INA/RP15/CN11/PMCS1/RB15 AN10/C3INB/CVREF/RTCC/RP14/CN12/PMWR/RB14 Pin Diagrams 28 27 26 25 24 23 22 AN5/C1INA/SCL2/RP3/CN7/RB3 VSS OSCI/CLKI/C1IND/CN30/RA2 OSCO/CLKO/CN29/PMA0/RA3 PIC24FJXXGA102 SOSCI/C2IND/RP4/PMBE/CN1/RB4 8 Legend: Note 1: 2: 3: 9 10 11 12 13 14 21 20 19 18 17 16 15 AN11/C1INC/RP13/CN13/PMRD/REFO/RB13 AN12/RP12/CN14/PMD0/RB12 PGEC2/TMS/RP11/CN15/PMD1/RB11 PGED2/TDI/RP10/CN16/PMD2/RB10 VCAP/VDDCORE DISVREG TDO/RP9/SDA1/CN21/PMD3/RB9 RP7/INT0/CN23/PMD5/RB7 TCK/RP8/SCL1/CN22/PMD4/RB8 AN4/C1INB/SDA2/RP2/CN6/RB2 1 2 3 4 5 6 7 SOSCO/SCLKI/T1CK/C2INC/CN0/PMA1/RA4 VDD PGED3/RP5/ASDA1(2)/CN27/PMD7/RB5 PGEC3/RP6/ASCL1(2)/CN24/PMD6/RB6 PGED1/AN2/C2INB/RP0/CN4/RB0 PGEC1/AN3/C2INA/RP1/CN5/RB1 RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins. Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set. The back pad on QFN devices should be connected to VSS.  2010 Microchip Technology Inc. DS39951C-page 5 PIC24FJ64GA104 FAMILY RP8/SCL1/CN22/PMD4/RB8 RP7/INT0/CN23/PMD5/RB7 PGEC3/RP6/ASCL1(2)/CN24/PMD6/RB6 PGED3/RP5/ASDA1(2)/CN27/PMD7/RB5 VDD VSS RP21/CN26/PMA3/RC5 RP20/CN25/PMA4/RC4 RP19/CN28/PMBE/RC3 TDI/PMA9/RA9 SOSCO/SCLKI/T1CK/C2INC/CN0/RA4 Pin Diagrams 44-PIN TQFP, 44 43 42 41 40 39 38 37 36 35 34 44-Pin QFN(1,3) PIC24FJXXGA104 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 SOSCI/C1IND/RP4/CN1/RB4 TDO/PMA8/RA8 OSCO/CLKO/CN29/RA3 OSCI/CLKI/C1IND/CN30/RA2 VSS VDD AN8/RP18/PMA2/CN10/RC2 AN7/RP17/CN9/RC1 AN6/RP16/CN8/RC0 AN5/C1INA/RP3/SCL2/CN7/RB3 AN4/C1INB/RP2/SDA2/CN6/RB2 TMS/PMA10/RA10 TCK/PMA7/RA7 AN10/C3INB/CVREF/RTCC/RP14/CN12/PMWR/RB14 AN9/C3INA/RP15/CN11/RB15 AVSS AVDD MCLR AN0/C3INC/VREF+/CN2/CTED1/RA0 AN1/C3IND/VREF-/CN3/CTED2/RA1 PGED1/AN2/C2INB/RP0/CN4/RB0 PGEC1/AN3/C2INA/RP1/CN5/RB1 RP9/SDA1/CN21/PMD3/RB9 RP22/CN18/PMA1/RC6 RP23/CN17/PMA0/RC7 RP24/CN20/PMA5/RC8 RP25/CN19/PMA6/RC9 DISVREG VCAP/VDDCORE PGED2/RP10/CN16/PMD2/RB10 PGEC2/RP11/CN15/PMD1/RB11 AN12/RP12/CN14/PMD0/RB12 AN11/C1INC/RP13/PMRD/REFO/CN13/RB13 Legend: Note 1: 2: 3: DS39951C-page 6 RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins. Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set. The back pad on QFN devices should be connected to VSS.  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 19 3.0 CPU ........................................................................................................................................................................................... 25 4.0 Memory Organization ................................................................................................................................................................. 31 5.0 Flash Program Memory.............................................................................................................................................................. 51 6.0 Resets ........................................................................................................................................................................................ 59 7.0 Interrupt Controller ..................................................................................................................................................................... 65 8.0 Oscillator Configuration ............................................................................................................................................................ 101 9.0 Power-Saving Features............................................................................................................................................................ 111 10.0 I/O Ports ................................................................................................................................................................................... 121 11.0 Timer1 ...................................................................................................................................................................................... 143 12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 145 13.0 Input Capture with Dedicated Timers ....................................................................................................................................... 151 14.0 Output Compare with Dedicated Timers .................................................................................................................................. 155 15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 165 16.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 175 17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 183 18.0 Parallel Master Port (PMP)....................................................................................................................................................... 191 19.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 201 20.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 213 21.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 219 22.0 Triple Comparator Module........................................................................................................................................................ 229 23.0 Comparator Voltage Reference................................................................................................................................................ 233 24.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 235 25.0 Special Features ...................................................................................................................................................................... 239 26.0 Development Support............................................................................................................................................................... 251 27.0 Instruction Set Summary .......................................................................................................................................................... 255 28.0 Electrical Characteristics .......................................................................................................................................................... 263 29.0 Packaging Information.............................................................................................................................................................. 283 Appendix A: Revision History............................................................................................................................................................. 297 Index ................................................................................................................................................................................................. 299 The Microchip Web Site ..................................................................................................................................................................... 305 Customer Change Notification Service .............................................................................................................................................. 305 Customer Support .............................................................................................................................................................................. 305 Reader Response .............................................................................................................................................................................. 306 Product Identification System ............................................................................................................................................................ 307  2010 Microchip Technology Inc. DS39951C-page 7 PIC24FJ64GA104 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39951C-page 8  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ32GA102 • PIC24FJ32GA104 • PIC24FJ64GA102 • PIC24FJ64GA104 The PIC24FJ64GA104 family provides an expanded peripheral feature set and a new option for high-performance applications which may need more than an 8-bit platform, but do not require the power of a digital signal processor. 1.1 1.1.1 Core Features 16-BIT ARCHITECTURE Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC® digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: • 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces • Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data) • A 16-element working register array with built-in software stack support • A 17 x 17 hardware multiplier with support for integer math • Hardware support for 32 by 16-bit division • An instruction set that supports multiple addressing modes and is optimized for high-level languages, such as ‘C’ • Operational performance up to 16 MIPS 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ64GA104 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, Low-Power Internal RC Oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. • Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat.  2010 Microchip Technology Inc. • Instruction-Based Power-Saving Modes: There are three instruction-based power-saving modes: - Idle Mode – The core is shut down while leaving the peripherals active. - Sleep Mode – The core and peripherals that require the system clock are shut down, leaving the peripherals active that use their own clock or the clock from other devices. - Deep Sleep Mode – The core, peripherals (except RTCC and DSWDT), Flash and SRAM are shut down for optimal current savings to extend battery life for portable applications. 1.1.3 OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ64GA104 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. • Two External Clock modes offering the option of a divide-by-2 clock output. • A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. • A Phase Lock Loop (PLL) frequency multiplier available to the external oscillator modes and the FRC Oscillator, which allows clock speeds of up to 32 MHz. • A separate Low-Power Internal RC Oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.1.4 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger device. The PIC24F family is pin-compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30 devices. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device. DS39951C-page 9 PIC24FJ64GA104 FAMILY 1.2 Other Special Features • Peripheral Pin Select: The Peripheral Pin Select feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins. • Communications: The PIC24FJ64GA104 family incorporates a range of serial communication peripherals to handle a range of application requirements. There are two independent I2C™ modules that support both Master and Slave modes of operation. Devices also have, through the Peripheral Pin Select (PPS) feature, two independent UARTs with built-in IrDA® encoder/decoders and two SPI modules. • Analog Features: All members of the PIC24FJ64GA104 family include a 10-bit A/D Converter module and a triple comparator module. The A/D module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds. The comparator module includes three analog comparators that are configurable for a wide range of operations. • CTMU Interface: This module provides a convenient method for precision time measurement and pulse generation, and can serve as an interface for capacitive sensors. • Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communications. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 12 external address lines in Master modes. • Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for the use of the core application. DS39951C-page 10 1.3 Details on Individual Family Members Devices in the PIC24FJ64GA104 family are available in 28-pin and 44-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in several ways: • Flash Program Memory: - PIC24FJ32GA1 devices – 32 Kbytes - PIC24FJ64GA1 devices – 64 Kbytes • Available I/O Pins and Ports: - 28-pin devices – 21 pins on two ports - 44-pin devices – 35 pins on three ports • Available Interrupt-on-Change Notification (ICN) Inputs: - 28-pin devices – 21 - 44-pin devices – 31 • Available Remappable Pins: - 28-pin devices – 16 pins - 44-pin devices – 26 pins • Available PMP Address Pins: - 28-pin devices – 3 pins - 44-pin devices – 12 pins • Available A/D Input Channels: - 28-pin devices – 10 pins - 44-pin devices – 13 pins All other features for devices in this family are identical. These are summarized in Table 1-1. A list of the pin features available on the PIC24FJ64GA104 family devices, sorted by function, is shown in Table 1-2. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of this data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first.  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GA104 FAMILY Features PIC24FJ32GA102 PIC24FJ64GA102 PIC24FJ32GA104 PIC24FJ64GA104 Operating Frequency Program Memory (bytes) Program Memory (instructions) DC – 32 MHz 32K 64K 11,008 22,016 Data Memory (bytes) 64K 11,008 22,016 8,192 Interrupt Sources (soft vectors/ NMI traps) I/O Ports 32K 45 (41/4) Ports A and B Ports A, B, C Total I/O Pins 21 35 Remappable Pins 16 26 Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 5(1) Output Compare/PWM Channels 5(1) Input Change Notification Interrupt 21 31 Serial Communications: UART 2(1) SPI (3-wire/4-wire) 2(1) I2C™ 2 Parallel Communications (PMP/PSP) Yes JTAG Boundary Scan 10-Bit Analog-to-Digital Module (input channels) Yes 10 Analog Comparators 3 CTMU Interface Resets (and delays) Instruction Set Packages Note 1: 13 Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 28-Pin QFN, SOIC, SSOP and SPDIP 44-Pin QFN and TQFP Peripherals are accessible through remappable pins.  2010 Microchip Technology Inc. DS39951C-page 11 PIC24FJ64GA104 FAMILY FIGURE 1-1: PIC24FJ64GA104 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller PORTA(1) 16 (9 I/O) 16 16 8 Data Latch PSV & Table Data Access Control Block Data RAM PCH PCL Program Counter Repeat Stack Control Control Logic Logic 23 Address Latch PORTB (16 I/O) 16 23 16 Read AGU Write AGU Address Latch PORTC(1) Program Memory (10 I/O) Data Latch 16 EA MUX Literal Data Address Bus 24 Inst Latch 16 16 RP(1) Inst Register RP0:RP25 Instruction Decode & Control Divide Support Control Signals OSCO/CLKO OSCI/CLKI Timing Generation FRC/LPRC Oscillators REFO DISVREG Power-up Timer Oscillator Start-up Timer Watchdog Timer Voltage Regulator BOR and LVD(2) Timer1 Timer2/3(3) 16-Bit ALU Power-on Reset Precision Band Gap Reference VDDCORE/VCAP 16 x 16 W Reg Array 17 x 17 Multiplier VDD, VSS Timer4/5(3) 16 MCLR RTCC 10-Bit ADC Comparators(3) PMP/PSP IC 1-5(3) Note 1: 2: 3: PWM/OC 1-5(3) ICNs(1) SPI 1/2(3) I2C 1/2 UART 1/2(3) CTMU Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-2 for specific implementations by pin count. BOR functionality is provided when the on-board voltage regulator is enabled. These peripheral I/Os are only accessible through remappable pins. DS39951C-page 12  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS Pin Number Function 28-Pin SPDIP/ SOIC/SSOP 28-Pin QFN 44-Pin QFN/ TQFP I/O Input Buffer AN0 2 27 19 I ANA AN1 3 28 20 I ANA AN2 4 1 21 I ANA AN3 5 2 22 I ANA AN4 6 3 23 I ANA AN5 7 4 24 I ANA AN6 — — 25 I ANA AN7 — — 26 I ANA AN8 — — 27 I ANA AN9 26 23 15 I ANA AN10 25 22 14 I ANA AN11 24 21 11 I ANA AN12 23 20 10 I ANA ASCL1 15 12 42 I/O I2C 2 Description A/D Analog Inputs. Alternate I2C1 Synchronous Serial Clock Input/Output. ASDA1 14 11 41 I/O I C Alternate I2C1 Synchronous Serial Data Input/Output. AVDD — — 17 P — Positive Supply for Analog modules. AVSS — — 16 P — Ground Reference for Analog modules. C1INA 7 4 24 I ANA Comparator 1 Input A. C1INB 6 3 23 I ANA Comparator 1 Input B. C1INC 24 21 11 I ANA Comparator 1 Input C. C1IND 9 6 30 I ANA Comparator 1 Input D. C2INA 5 2 22 I ANA Comparator 2 Input A. C2INB 4 1 21 I ANA Comparator 2 Input B. C2INC 12 9 34 I ANA Comparator 2 Input C. C2IND 11 8 33 I ANA Comparator 2 Input D. C3INA 26 23 15 I ANA Comparator 3 Input A. C3INB 25 22 14 I ANA Comparator 3 Input B. C3INC 2 27 19 I ANA Comparator 3 Input C. C3IND 3 28 20 I ANA Comparator 3 Input D. CLKI 9 6 30 I ANA Main Clock Input Connection. 10 7 31 O — CLKO Legend: TTL = TTL input buffer ANA = Analog level input/output  2010 Microchip Technology Inc. System Clock Output. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39951C-page 13 PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 28-Pin SPDIP/ SOIC/SSOP 28-Pin QFN 44-Pin QFN/ TQFP I/O Input Buffer CN0 12 9 34 I ST CN1 11 8 33 I ST CN2 2 27 19 I ST CN3 3 28 20 I ST CN4 4 1 21 I ST CN5 5 2 22 I ST CN6 6 3 23 I ST Description Interrupt-on-Change Inputs. CN7 7 4 24 I ST CN8 — — 25 I ST CN9 — — 26 I ST CN10 — — 27 I ST CN11 26 23 15 I ST CN12 25 22 14 I ST CN13 24 21 11 I ST CN14 23 20 10 I ST CN15 22 19 9 I ST CN16 21 18 8 I ST CN17 — — 3 I ST CN18 — — 2 I ST CN19 — — 5 I ST CN20 — — 4 I ST CN21 18 15 1 I ST CN22 17 14 44 I ST CN23 16 13 43 I ST CN24 15 12 42 I ST CN25 — — 37 I ST CN26 — — 38 I ST CN27 14 11 41 I ST CN28 — — 36 I ST CN29 10 7 31 I ST CN30 9 6 30 I ST CTED1 2 27 19 I ANA CTMU External Edge Input 1. CTED2 3 28 20 I ANA CTMU External Edge Input 2. CVREF 25 22 14 O — Comparator Voltage Reference Output. DISVREG 19 16 6 I ST Voltage Regulator Disable. Legend: TTL = TTL input buffer ANA = Analog level input/output DS39951C-page 14 ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin SPDIP/ SOIC/SSOP 28-Pin QFN 44-Pin QFN/ TQFP I/O Input Buffer INT0 16 13 43 I ST External Interrupt Input. MCLR 1 26 18 I ST Master Clear (device Reset) Input. This line is brought low to cause a Reset. Function Description OSCI 9 6 30 I ANA Main Oscillator Input Connection. OSCO 10 7 31 O ANA Main Oscillator Output Connection. PGEC1 5 2 22 I/O ST PGED1 4 1 21 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data. PGEC2 22 19 9 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock. PGED2 21 18 8 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data. PGEC3 15 12 42 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock. PGED3 14 11 41 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data. PMA0 10 7 3 I/O ST Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). PMA1 12 9 2 I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). PMA2 — — 27 O — Parallel Master Port Address (Demultiplexed Master modes). PMA3 — — 38 O — PMA4 — — 37 O — PMA5 — — 4 O — PMA6 — — 5 O — PMA7 — — 13 O — PMA8 — — 32 O — PMA9 — — 35 O — PMA10 — — 12 O PMCS1 26 23 15 I/O In-Circuit Debugger/Emulator/ICSP™ Programming Clock. — ST/TTL Parallel Master Port Chip Select 1 Strobe/Address Bit 15. PMBE 11 8 36 O PMD0 23 20 10 I/O PMD1 22 19 9 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or ST/TTL Address/Data (Multiplexed Master modes). PMD2 21 18 8 I/O ST/TTL PMD3 18 15 1 I/O ST/TTL PMD4 17 14 44 I/O ST/TTL PMD5 16 13 43 I/O ST/TTL PMD6 15 12 42 I/O ST/TTL PMD7 14 11 41 I/O ST/TTL PMRD 24 21 11 O — Parallel Master Port Read Strobe. 25 22 14 O — Parallel Master Port Write Strobe. PMWR Legend: TTL = TTL input buffer ANA = Analog level input/output  2010 Microchip Technology Inc. — Parallel Master Port Byte Enable Strobe. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39951C-page 15 PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Buffer 28-Pin SPDIP/ SOIC/SSOP 28-Pin QFN RA0 2 27 19 I/O ST RA1 3 28 20 I/O ST RA2 9 6 30 I/O ST RA3 10 7 31 I/O ST RA4 12 9 34 I/O ST RA7 — — 13 I/O ST RA8 — — 32 I/O ST Function 44-Pin QFN/ TQFP I/O RA9 — — 35 I/O ST RA10 — — 12 I/O ST RB0 4 1 21 I/O ST RB1 5 2 22 I/O ST RB2 6 3 23 I/O ST RB3 7 4 24 I/O ST RB4 11 8 33 I/O ST RB5 14 11 41 I/O ST RB6 15 12 42 I/O ST RB7 16 13 43 I/O ST RB8 17 14 44 I/O ST RB9 18 15 1 I/O ST RB10 21 18 8 I/O ST RB11 22 19 9 I/O ST RB12 23 20 10 I/O ST RB13 24 21 11 I/O ST RB14 25 22 14 I/O ST RB15 26 23 15 I/O ST RC0 — — 25 I/O ST RC1 — — 26 I/O ST RC2 — — 27 I/O ST RC3 — — 36 I/O ST RC4 — — 37 I/O ST RC5 — — 38 I/O ST RC6 — — 2 I/O ST RC7 — — 3 I/O ST RC8 — — 4 I/O ST RC9 — — 5 I/O ST 24 21 11 O — REFO Legend: TTL = TTL input buffer ANA = Analog level input/output DS39951C-page 16 Description PORTA Digital I/O. PORTB Digital I/O. PORTC Digital I/O. Reference Clock Output. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin SPDIP/ SOIC/SSOP 28-Pin QFN 44-Pin QFN/ TQFP I/O Input Buffer RP0 4 1 21 I/O ST RP1 5 2 22 I/O ST RP2 6 3 23 I/O ST Function Description Remappable Peripheral (input or output). RP3 7 4 24 I/O ST RP4 11 8 33 I/O ST RP5 14 11 41 I/O ST RP6 15 12 42 I/O ST RP7 16 13 43 I/O ST RP8 17 14 44 I/O ST RP9 18 15 1 I/O ST RP10 21 18 8 I/O ST RP11 22 19 9 I/O ST RP12 23 20 10 I/O ST RP13 24 21 11 I/O ST RP14 25 22 14 I/O ST RP15 26 23 15 I/O ST RP16 — — 25 I/O ST RP17 — — 26 I/O ST RP18 — — 27 I/O ST RP19 — — 36 I/O ST RP20 — — 37 I/O ST RP21 — — 38 I/O ST RP22 — — 2 I/O ST RP23 — — 3 I/O ST RP24 — — 4 I/O ST RP25 — — 5 I/O ST RTCC 25 22 14 O — Real-Time Clock Alarm/Seconds Pulse Output. I2C1 Synchronous Serial Clock Input/Output. SCL1 17 14 44 I/O I2C SCL2 7 4 24 I/O I2C I2C2 Synchronous Serial Clock Input/Output. SDA1 18 15 1 I/O I2C I2C1 Data Input/Output. SDA2 6 3 23 I/O I2C I2C2 Data Input/Output. SOSCI 11 8 33 I ANA Secondary Oscillator/Timer1 Clock Input. SOSCO 12 9 34 O ANA Secondary Oscillator/Timer1 Clock Output. T1CK 12 9 34 I ST Timer1 Clock Input. TCK 17 14 13 I ST JTAG Test Clock Input. TDI 21 18 35 I ST JTAG Test Data Input. TDO 18 15 32 O — JTAG Test Data Output. 22 19 12 I ST JTAG Test Mode Select Input. TMS Legend: TTL = TTL input buffer ANA = Analog level input/output  2010 Microchip Technology Inc. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39951C-page 17 PIC24FJ64GA104 FAMILY TABLE 1-2: PIC24FJ64GA104 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 28-Pin SPDIP/ SOIC/SSOP 28-Pin QFN 44-Pin QFN/ TQFP I/O Input Buffer Description VCAP 20 17 7 P — External Filter Capacitor Connection (regulator enabled). VDD 13, 28 10, 25 28, 40 P — Positive Supply for Peripheral Digital Logic and I/O Pins. VDDCORE 20 17 7 P — Positive Supply for Microcontroller Core Logic (regulator disabled). VREF- 3 28 20 I ANA A/D and Comparator Reference Voltage (low) Input. VREF+ 2 27 19 I ANA A/D and Comparator Reference Voltage (high) Input. 8, 27 5, 24 29, 39 P — VSS Legend: TTL = TTL input buffer ANA = Analog level input/output DS39951C-page 18 Ground Reference for Logic and I/O Pins. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG/DISVREG and VCAP/VDDCORE pins (PIC24FJ devices only) (see Section 2.4 “Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)”) These pins must also be connected if they are being used in the end application: • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for analog modules is implemented Note: VDD R2 VSS R1 (1) (1) (EN/DIS)VREG MCLR VCAP/VDDCORE C1 C7 PIC24FXXXX C6(2) VSS VDD VDD VSS C3(2) C5(2) VSS The following pins must always be connected: C2(2) VDD Getting started with the PIC24FJ64GA104 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. RECOMMENDED MINIMUM CONNECTIONS VDD Basic Connection Requirements FIGURE 2-1: AVSS 2.1 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS AVDD 2.0 C4(2) Key (all values are recommendations): C1 through C6: 0.1 F, 20V ceramic C7: 10 F, 6.3V or greater, tantalum or ceramic R1: 10 kΩ R2: 100Ω to 470Ω Note 1: 2: See Section 2.4 “Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)” for explanation of ENVREG/DISVREG pin connections. The example shown is for a PIC24F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1.  2010 Microchip Technology Inc. DS39951C-page 19 PIC24FJ64GA104 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). • Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. 2.2.2 TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including microcontrollers to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. DS39951C-page 20 2.3 Master Clear (MCLR) Pin The MCLR pin provides two specific device functions: device Reset, and device programming and debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application’s requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD R1 R2 JP MCLR PIC24FXXXX C1 Note 1: R1  10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R2  470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met.  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Note: Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE) FIGURE 2-3: The on-chip voltage regulator enable/disable pin (ENVREG or DISVREG, depending on the device family) must always be connected directly to either a supply voltage or to ground. The particular connection is determined by whether or not the regulator is to be used: • For ENVREG, tie to VDD to enable the regulator, or to ground to disable the regulator • For DISVREG, tie to ground to enable the regulator or to VDD to disable the regulator Refer to Section 25.2 “On-Chip Voltage Regulator” for details on connecting and using the on-chip regulator. When the regulator is enabled, a low-ESR (16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4042; // Initialize NVMCON asm("DISI #5"); // // // // __builtin_write_NVM(); EXAMPLE 5-3: Block all interrupts with priority >16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write necessary number of latches for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++) { __builtin_tblwtl(offset, progData[i++]); // Write to address low word __builtin_tblwth(offset, progData[i]); // Write to upper byte offset = offset + 2; // Increment address } EXAMPLE 5-5: INITIATING A PROGRAMMING SEQUENCE (ASSEMBLY LANGUAGE CODE) DISI #5 MOV MOV MOV MOV BSET NOP NOP BTSC BRA #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR EXAMPLE 5-6: ; Block all interrupts with priority >16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write latches __builtin_tblwtl(offset, progDataL); __builtin_tblwth(offset, progDataH); asm(“DISI #5”); __builtin_write_NVM();  2010 Microchip Technology Inc. // // // // // // Write to address low word Write to upper byte Block interrupts with priority < 7 for next 5 instructions C30 function to perform unlock sequence and set WR DS39951C-page 57 PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 58  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 6.0 Note: RESETS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 7. “Reset” (DS39712). The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: • • • • • • • • • POR: Power-on Reset MCLR: Pin Reset SWR: RESET Instruction WDT: Watchdog Timer Reset BOR: Brown-out Reset CM: Configuration Mismatch Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode Reset UWR: Uninitialized W Register Reset Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets. Note: All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 6-1). A Power-on Reset will clear all bits, except for the BOR and POR bits (RCON), which are set. The user may set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this data sheet. A simplified block diagram of the Reset module is shown in Figure 6-1. FIGURE 6-1: Refer to the specific peripheral or CPU section of this manual for register Reset states. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle VDD Rise Detect POR Brown-out Reset BOR SYSRST VDD Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register  2010 Microchip Technology Inc. DS39951C-page 59 PIC24FJ64GA104 FAMILY RCON: RESET CONTROL REGISTER(1) REGISTER 6-1: R/W-0 TRAPR bit 15 R/W-0 IOPUWR U-0 — U-0 — U-0 — R/CO-0, HS DPSLP R/W-0 CM R/W-0 PMSLP bit 8 R/W-0 EXTR bit 7 R/W-0 SWR R/W-0 SWDTEN(2) R/W-0 WDTO R/W-0, SLEEP R/W-0 IDLE R/W-1 BOR R/W-1 POR bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Note 1: 2: CO = Clearable Only bit W = Writable bit ‘1’ = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred Unimplemented: Read as ‘0’ DPSLP: Deep Sleep Mode Flag bit 1 = Deep Sleep has occurred 0 = Deep Sleep has not occurred CM: Configuration Word Mismatch Reset Flag bit 1 = A Configuration Word Mismatch Reset has occurred 0 = A Configuration Word Mismatch Reset has not occurred PMSLP: Program Memory Power During Sleep bit 1 = Program memory bias voltage remains powered during Sleep 0 = Program memory bias voltage is powered down during Sleep and voltage regulator enters Standby mode EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred SLEEP: Wake From Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode IDLE: Wake-up From Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS39951C-page 60  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY RCON: RESET CONTROL REGISTER(1) (CONTINUED) REGISTER 6-1: bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred. Note that BOR is also set after a Power-on Reset. 0 = A Brown-out Reset has not occurred POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred bit 0 Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. 2: TABLE 6-1: RESET FLAG BIT OPERATION Flag Bit Setting Event Clearing Event TRAPR (RCON) Trap Conflict Event POR IOPUWR (RCON) Illegal Opcode or Uninitialized W Register Access POR CM (RCON) Configuration Mismatch Reset POR EXTR (RCON) MCLR Reset POR SWR (RCON) RESET Instruction WDTO (RCON) WDT Time-out SLEEP (RCON) PWRSAV #SLEEP Instruction POR IDLE (RCON) PWRSAV #IDLE Instruction POR POR PWRSAV Instruction, POR BOR (RCON) POR, BOR — POR (RCON) POR — DPSLP (RCON) PWRSAV #SLEEP instruction with DSCON set Note: 6.1 POR All Reset flag bits may be set or cleared by the user software. Clock Source Selection at Reset If clock switching is enabled, the system clock source at device Reset is chosen as shown in Table 6-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 8.0 “Oscillator Configuration” for further details. TABLE 6-2: Reset Type POR BOR MCLR WDTO OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED) Clock Source Determinant FNOSC Configuration bits (CW2) 6.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 6-3. Note that the System Reset signal, SYSRST, is released after the POR and PWRT delay times expire. The time at which the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released. COSC Control bits (OSCCON) SWR  2010 Microchip Technology Inc. DS39951C-page 61 PIC24FJ64GA104 FAMILY TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type POR(6) EC BOR All Others Note 1: 2: 3: 4: 5: 6: Clock Source SYSRST Delay System Clock Delay TPOR + TRST + TPWRT — Notes 1, 2, 3, 8 FRC, FRCDIV TPOR + TRST + TPWRT TFRC 1, 2, 3, 4, 7, 8 LPRC TPOR + TRST + TPWRT TLPRC 1, 2, 3, 4, 8 1, 2, 3, 5, 8 ECPLL TPOR + TRST + TPWRT TLOCK FRCPLL TPOR + TRST + TPWRT TFRC + TLOCK XT, HS, SOSC TPOR+ TRST + TPWRT TOST XTPLL, HSPLL TPOR + TRST + TPWRT TOST + TLOCK 1, 2, 3, 4, 5, 7, 8 1, 2, 3, 6, 8 1, 2, 3, 5, 6, 8 EC TRST + TPWRT — FRC, FRCDIV TRST + TPWRT TFRC 2, 3, 4, 7, 8 LPRC TRST + TPWRT TLPRC 2, 3, 4, 8 ECPLL TRST + TPWRT TLOCK 2, 3, 5, 8 FRCPLL TRST + TPWRT TFRC + TLOCK XT, HS, SOSC TRST + TPWRT TOST XTPLL, HSPLL TRST + TPWRT TFRC + TLOCK TRST — Any Clock 2, 3, 8 2, 3, 4, 5, 7, 8 2, 3, 6, 8 2, 3, 4, 5, 8 2, 8 8: TPOR = Power-on Reset delay. TRST = Internal State Reset time. TPWRT = 64 ms nominal if regulator is disabled (DISVREG tied to VDD). TFRC and TLPRC = RC Oscillator start-up times. TLOCK = PLL lock time. TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the oscillator clock to the system. If Two-Speed Start-up is enabled, regardless of the Primary Oscillator selected, the device starts with FRC, and in such cases, FRC start-up time is valid. TRST = Configuration setup time. Note: For detailed operating frequency and timing specifications, see Section 28.0 “Electrical Characteristics”. 7: DS39951C-page 62  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 6.2.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate. • The Oscillator Start-up Timer has not expired (if a crystal oscillator is used). • The PLL has not achieved a lock (if PLL is used). The device will not begin to execute code until a valid clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known. 6.2.2 FAIL-SAFE CLOCK MONITOR (FSCM) AND DEVICE RESETS If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released. If a valid clock source is not available at this time, the device will automatically switch to the FRC Oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine (TSR).  2010 Microchip Technology Inc. 6.3 Special Function Register Reset States Most of the Special Function Registers (SFRs) associated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual. The Reset value for each SFR does not depend on the type of Reset with the exception of four registers. The Reset value for the Reset Control register, RCON, will depend on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the type of Reset and the programmed values of the FNOSC bits in Flash Configuration Word 2 (CW2); see Table 6-2. The RCFGCAL and NVMCON registers are only affected by a POR. 6.4 Deep Sleep BOR (DSBOR) Deep Sleep BOR is a very low-power BOR circuitry, used when the device is in Deep Sleep mode. Due to low-current consumption, accuracy may vary. The DSBOR trip point is around 2.0V. DSBOR is enabled by configuring CW4 (DSBOREN) = 1. DSBOR will re-arm the POR to ensure the device will reset if VDD drops below the POR threshold. DS39951C-page 63 PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 64  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 7.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 8. “Interrupts” (DS39707). The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24F CPU. It has the following features: • • • • Up to 8 processor exceptions and software traps 7 user-selectable priority levels Interrupt Vector Table (IVT) with up to 118 vectors A unique vector for each interrupt or exception source • Fixed priority within a specified user priority level • Alternate Interrupt Vector Table (AIVT) for debug support • Fixed interrupt entry and return latencies 7.1 Interrupt Vector Table The Interrupt Vector Table (IVT) is shown in Figure 7-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors, consisting of 8 non-maskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2). If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT. 7.2 Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24F devices clear their registers in response to a Reset which forces the PC to zero. The microcontroller then begins program execution at location 000000h. The user programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction. Interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. PIC24FJ64GA104 family devices implement non-maskable traps and unique interrupts. These are summarized in Table 7-1 and Table 7-2.  2010 Microchip Technology Inc. DS39951C-page 65 PIC24FJ64GA104 FAMILY FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE Decreasing Natural Order Priority Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Start of Code Note 1: TABLE 7-1: 000000h 000002h 000004h 000014h 00007Ch 00007Eh 000080h 0000FCh 0000FEh 000100h 000102h 000114h Alternate Interrupt Vector Table (AIVT)(1) 00017Ch 00017Eh 000180h 0001FEh 000200h See Table 7-2 for the interrupt vector list. TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address 0 1 2 3 4 5 6 7 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000104h 000106h 000108h 00010Ah 00010Ch 00010Eh 000110h 000112h DS39951C-page 66 Interrupt Vector Table (IVT)(1) Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Bit Locations Vector Number IVT Address AIVT Address Flag Enable ADC1 Conversion Done 13 00002Eh 00012Eh IFS0 IEC0 IPC3 Comparator Event 18 000038h 000138h IFS1 IEC1 IPC4 CRC Generator 67 00009Ah 00019Ah IFS4 IEC4 IPC16 CTMU Event 77 0000AEh 0001AEh IFS4 IEC4 IPC19 Interrupt Source Priority External Interrupt 0 0 000014h 000114h IFS0 IEC0 IPC0 External Interrupt 1 20 00003Ch 00013Ch IFS1 IEC1 IPC5 External Interrupt 2 29 00004Eh 00014Eh IFS1 IEC1 IPC7 I2C1 Master Event 17 000036h 000136h IFS1 IEC1 IPC4 I2C1 Slave Event 16 000034h 000134h IFS1 IEC1 IPC4 I2C2 Master Event 50 000078h 000178h IFS3 IEC3 IPC12 I2C2 Slave Event 49 000076h 000176h IFS3 IEC3 IPC12 Input Capture 1 1 000016h 000116h IFS0 IEC0 IPC0 Input Capture 2 5 00001Eh 00011Eh IFS0 IEC0 IPC1 Input Capture 3 37 00005Eh 00015Eh IFS2 IEC2 IPC9 Input Capture 4 38 000060h 000160h IFS2 IEC2 IPC9 Input Capture 5 39 000062h 000162h IFS2 IEC2 IPC9 Input Change Notification 19 00003Ah 00013Ah IFS1 IEC1 IPC4 LVD Low-Voltage Detect 72 0000A4h 0001A4h IFS4 IEC4 IPC18 Output Compare 1 2 000018h 000118h IFS0 IEC0 IPC0 Output Compare 2 6 000020h 000120h IFS0 IEC0 IPC1 Output Compare 3 25 000046h 000146h IFS1 IEC1 IPC6 Output Compare 4 26 000048h 000148h IFS1 IEC1 IPC6 Output Compare 5 41 000066h 000166h IFS2 IEC2 IPC10 Parallel Master Port 45 00006Eh 00016Eh IFS2 IEC2 IPC11 Real-Time Clock/Calendar 62 000090h 000190h IFS3 IEC3 IPC15 SPI1 Error 9 000026h 000126h IFS0 IEC0 IPC2 SPI1 Event 10 000028h 000128h IFS0 IEC0 IPC2 SPI2 Error 32 000054h 000154h IFS2 IEC2 IPC8 SPI2 Event 33 000056h 000156h IFS2 IEC2 IPC8 Timer1 3 00001Ah 00011Ah IFS0 IEC0 IPC0 Timer2 7 000022h 000122h IFS0 IEC0 IPC1 Timer3 8 000024h 000124h IFS0 IEC0 IPC2 Timer4 27 00004Ah 00014Ah IFS1 IEC1 IPC6 Timer5 28 00004Ch 00014Ch IFS1 IEC1 IPC7 UART1 Error 65 000096h 000196h IFS4 IEC4 IPC16 IPC2 UART1 Receiver 11 00002Ah 00012Ah IFS0 IEC0 UART1 Transmitter 12 00002Ch 00012Ch IFS0 IEC0 IPC3 UART2 Error 66 000098h 000198h IFS4 IEC4 IPC16 UART2 Receiver 30 000050h 000150h IFS1 IEC1 IPC7 UART2 Transmitter 31 000052h 000152h IFS1 IEC1 IPC7  2010 Microchip Technology Inc. DS39951C-page 67 PIC24FJ64GA104 FAMILY 7.3 Interrupt Control and Status Registers The PIC24FJ64GA104 family of devices implements the following registers for the interrupt controller: • • • • • INTCON1 INTCON2 IFS0 through IFS4 IEC0 through IEC4 IPC0 through IPC20 (except IPC13, IPC14 and IPC17) • INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table. The IFSx registers maintain all of the interrupt request flags. Each source of interrupt has a status bit which is set by the respective peripherals, or an external signal, and is cleared via software. The IECx registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. The IPCx registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. DS39951C-page 68 The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the order of their vector numbers, as shown in Table 7-2. For example, the INT0 (External Interrupt 0) is shown as having a vector number and a natural order priority of 0. Thus, the INT0IF status bit is found in IFS0, the INT0IE enable bit in IEC0 and the INT0IP priority bits in the first position of IPC0 (IPC0). Although they are not specifically part of the interrupt control hardware, two of the CPU control registers contain bits that control interrupt functionality. The ALU STATUS Register (SR) contains the IPL bits (SR); these indicate the current CPU interrupt priority level. The user may change the current CPU priority level by writing to the IPL bits. The CORCON register contains the IPL3 bit, which, together with IPL, indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. The interrupt controller has the Interrupt Controller Test Register (INTTREG) that displays the status of the interrupt controller. When an interrupt request occurs, its associated vector number and the new interrupt priority level are latched into INTTREG. This information can be used to determine a specific interrupt source if a generic ISR is used for multiple vectors – such as when ISR remapping is used in bootloader applications. It also could be used to check if another interrupt is pending while in an ISR. All interrupt registers are described in Register 7-1 through Register 7-32, on the following pages.  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-1: SR: ALU STATUS REGISTER (IN CPU) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0 — — — — — — — DC(1) bit 15 bit 8 R/W-0 IPL2 (2,3) R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU interrupt priority level is 7 (15). User interrupts are disabled. 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) bit 7-5 Note 1: 2: 3: See Register 3-1 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. The IPL bits are concatenated with the IPL3 bit (CORCON) to form the CPU interrupt priority level. The value in parentheses indicates the interrupt priority level if IPL3 = 1. The IPL Status bits are read-only when NSTDIS (INTCON1) = 1. REGISTER 7-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0 — — — — IPL3(2) PSV(1) — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL3: CPU Interrupt Priority Level Status bit(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 3 Note 1: 2: See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level.  2010 Microchip Technology Inc. DS39951C-page 69 PIC24FJ64GA104 FAMILY REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14-5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Arithmetic Error Trap Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS39951C-page 70 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use Alternate Interrupt Vector Table 0 = Use standard (default) vector table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-3 Unimplemented: Read as ‘0’ bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge  2010 Microchip Technology Inc. x = Bit is unknown DS39951C-page 71 PIC24FJ64GA104 FAMILY REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 — bit 15 U-0 — R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPF1IF R/W-0 T3IF bit 8 R/W-0 T2IF bit 7 R/W-0 OC2IF R/W-0 IC2IF U-0 — R/W-0 T1IF R/W-0 OC1IF R/W-0 IC1IF R/W-0 INT0IF bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ AD1IF: A/D Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF1IF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS39951C-page 72  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2010 Microchip Technology Inc. x = Bit is unknown DS39951C-page 73 PIC24FJ64GA104 FAMILY REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 — — PMPIF — — — OC5IF — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-10 Unimplemented: Read as ‘0’ bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 Unimplemented: Read as ‘0’ bit 7 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-2 Unimplemented: Read as ‘0’ bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS39951C-page 74 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIF — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0, R/W-0 U-0 — — — — — MI2C2IF SI2C2IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IF: Master I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. x = Bit is unknown DS39951C-page 75 PIC24FJ64GA104 FAMILY REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIF — — — — LVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-9 Unimplemented: Read as ‘0’ bit 8 LVDIF: Low-Voltage Detect Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7-4 Unimplemented: Read as ‘0’ bit 3 CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ DS39951C-page 76 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 — bit 15 U-0 — R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 T2IE bit 7 R/W-0 OC2IE R/W-0 IC2IE U-0 — R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE R/W-0 INT0IE bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ AD1IE: A/D Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI1IE: SPI1 Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPF1IE: SPI1 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as ‘0’ T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2010 Microchip Technology Inc. DS39951C-page 77 PIC24FJ64GA104 FAMILY REGISTER 7-11: R/W-0 U2TXIE bit 15 IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 U2RXIE R/W-0 INT2IE(1) R/W-0 T5IE R/W-0 T4IE U-0 — U-0 — R/W-0 INT1IE(1) R/W-0 CNIE bit 7 Legend: R = Readable bit -n = Value at POR bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8-5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: R/W-0 OC3IE U-0 — bit 8 U-0 — bit 15 R/W-0 OC4IE W = Writable bit ‘1’ = Bit is set R/W-0 CMIE R/W-0 MI2C1IE R/W-0 SI2C1IE bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT2IE: External Interrupt 2 Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as ‘0’ INT1IE: External Interrupt 1 Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled CMIE: Comparator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or PRIx pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. DS39951C-page 78  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 — — PMPIE — — — OC5IE — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 PMPIE: Parallel Master Port Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12-10 Unimplemented: Read as ‘0’ bit 9 OC5IE: Output Compare Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 Unimplemented: Read as ‘0’ bit 7 IC5IE: Input Capture Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4-2 Unimplemented: Read as ‘0’ bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2010 Microchip Technology Inc. x = Bit is unknown DS39951C-page 79 PIC24FJ64GA104 FAMILY REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIE — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IE: Master I2C2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ DS39951C-page 80 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIE — — — — LVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12-9 Unimplemented: Read as ‘0’ bit 8 LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7-4 Unimplemented: Read as ‘0’ bit 3 CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. x = Bit is unknown DS39951C-page 81 PIC24FJ64GA104 FAMILY REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39951C-page 82 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC2IP2 IC2IP1 IC2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC2IP: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC2IP: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. x = Bit is unknown DS39951C-page 83 PIC24FJ64GA104 FAMILY REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPF1IP: SPI1 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39951C-page 84 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP: A/D Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. x = Bit is unknown DS39951C-page 85 PIC24FJ64GA104 FAMILY REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP: Input Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 CMIP: Comparator Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1IP: Master I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39951C-page 86 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. x = Bit is unknown DS39951C-page 87 PIC24FJ64GA104 FAMILY REGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — OC3IP2 OC3IP1 OC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP: Timer4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC4IP: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC3IP: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39951C-page 88 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2RXIP: UART2 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T5IP: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. x = Bit is unknown DS39951C-page 89 PIC24FJ64GA104 FAMILY REGISTER 7-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP: SPI2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SPF2IP: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39951C-page 90 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC3IP2 IC3IP1 IC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC5IP: Input Capture Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC4IP: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC3IP: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. x = Bit is unknown DS39951C-page 91 PIC24FJ64GA104 FAMILY REGISTER 7-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — OC5IP2 OC5IP1 OC5IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 OC5IP: Output Compare Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39951C-page 92 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-26: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — PMPIP2 PMPIP1 PMPIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PMPIP: Parallel Master Port Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. x = Bit is unknown DS39951C-page 93 PIC24FJ64GA104 FAMILY REGISTER 7-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP: Master I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SI2C2IP: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39951C-page 94 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-28: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. x = Bit is unknown DS39951C-page 95 PIC24FJ64GA104 FAMILY REGISTER 7-29: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP: CRC Generator Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2ERIP: UART2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U1ERIP: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39951C-page 96 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 7-30: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — LVDIP2 LVDIP1 LVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 LVDIP: Low-Voltage Detect Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled REGISTER 7-31: x = Bit is unknown IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CTMUIP2 CTMUIP1 CTMUIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CTMUIP: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. x = Bit is unknown DS39951C-page 97 PIC24FJ64GA104 FAMILY REGISTER 7-32: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit 1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens when the CPU priority is higher than the interrupt priority 0 = No interrupt request is unacknowledged bit 14 Unimplemented: Read as ‘0’ bit 13 VHOLD: Vector Number Capture Configuration bit 1 = The VECNUM bits contain the value of the highest priority pending interrupt 0 = The VECNUM bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that has occurred with higher priority than the CPU, even if other interrupts are pending) bit 12 Unimplemented: Read as ‘0’ bit 11-8 ILR: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM: Pending Interrupt Vector ID bits (pending vector number is VECNUM + 8) 0111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS39951C-page 98  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 7.4 Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS control bit (INTCON1) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources may be programmed to the same non-zero value. Note: 3. 4. At a device Reset, the IPCx registers are initialized, such that all user interrupt sources are assigned to priority level 4. Clear the interrupt flag status bit associated with the peripheral in the associated IFSx register. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx register. 7.4.2 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR. 7.4.4 INTERRUPT DISABLE All user interrupts can be disabled using the following procedure: 1. 2. Push the current SR value onto the software stack using the PUSH instruction. Force the CPU to priority level 7 by inclusive ORing the value OEh with SRL. To enable user interrupts, the POP instruction may be used to restore the previous SR value. Note that only user interrupts with a priority level of 7 or less can be disabled. Trap sources (level 8-15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. INTERRUPT SERVICE ROUTINE The method that is used to declare an ISR and initialize the IVT with the correct vector address will depend on the programming language (i.e., ‘C’ or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of the interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.  2010 Microchip Technology Inc. DS39951C-page 99 PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 100  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 8.0 OSCILLATOR CONFIGURATION Note: • Software-controllable switching between various clock sources • Software-controllable postscaler for selective clocking of CPU for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown • A separate and independently configurable system clock output for synchronizing external hardware This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, “Section 6. Oscillator” (DS39700). The oscillator system for PIC24FJ64GA104 family devices has the following features: A simplified diagram of the oscillator system is shown in Figure 8-1. • A total of four external and internal oscillator options as clock sources, providing 11 different clock modes • On-chip 4x PLL to boost internal operating frequency on select internal and external oscillator sources FIGURE 8-1: PIC24FJ64GA104 FAMILY CLOCK DIAGRAM Primary Oscillator REFOCON XT, HS, EC OSCO OSCI 4 x PLL 8 MHz (nominal) 8 MHz 4 MHz Postscaler FRC Oscillator Reference Clock Generator XTPLL, HSPLL ECPLL,FRCPLL REFO FRCDIV Peripherals CLKDIV FRC CLKO LPRC Postscaler LPRC Oscillator 31 kHz (nominal) Secondary Oscillator SOSC SOSCO SOSCI CPU CLKDIV SOSCEN Enable Oscillator Clock Control Logic Fail-Safe Clock Monitor WDT, PWRT Clock Source Option for Other Modules  2010 Microchip Technology Inc. DS39951C-page 101 PIC24FJ64GA104 FAMILY 8.1 CPU Clocking Scheme 8.2 The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator The Primary Oscillator and FRC sources have the option of using the internal 4x PLL. The frequency of the FRC clock source can optionally be reduced by the programmable clock divider. The selected clock source generates the processor and peripheral clock sources. The processor clock source is divided by two to produce the internal instruction cycle clock, FCY. In this document, the instruction cycle clock is also denoted by FOSC/2. The internal instruction cycle clock, FOSC/2, can be provided on the OSCO I/O pin for some operating modes of the Primary Oscillator. Initial Configuration on POR The oscillator source (and operating mode) that is used at a device Power-on Reset event is selected using Configuration bit settings. The oscillator Configuration bit settings are located in the Configuration registers in the program memory (refer to Section 25.1 “Configuration Bits” for further details). The Primary Oscillator Configuration bits, POSCMD (Configuration Word 2), and the Initial Oscillator Select Configuration bits, FNOSC (Configuration Word 2), select the oscillator source that is used at a Power-on Reset. The FRC Primary Oscillator with postscaler (FRCDIV) is the default (unprogrammed) selection. The Secondary Oscillator, or one of the internal oscillators, may be chosen by programming these bit locations. The Configuration bits allow users to choose between the various clock modes, shown in Table 8-1. 8.2.1 CLOCK SWITCHING MODE CONFIGURATION BITS The FCKSM Configuration bits (Configuration Word 2) are used to jointly configure device clock switching and the Fail-Safe Clock Monitor (FSCM). Clock switching is enabled only when FCKSM1 is programmed (‘0’). The FSCM is enabled only when the FCKSM bits are both programmed (‘00’). TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD FNOSC Note Fast RC Oscillator with Postscaler (FRCDIV) Internal 11 111 1, 2 (Reserved) Internal xx 110 1 Low-Power RC Oscillator (LPRC) Internal 11 101 1 Secondary 11 100 1 Primary Oscillator (XT) with PLL Module (XTPLL) Primary 01 011 Primary Oscillator (EC) with PLL Module (ECPLL) Primary 00 011 Primary Oscillator (HS) Primary 10 010 Primary Oscillator (XT) Primary 01 010 Primary Oscillator (EC) Primary 00 010 Fast RC Oscillator with PLL Module (FRCPLL) Internal 11 001 1 Fast RC Oscillator (FRC) Internal 11 000 1 Secondary (Timer1) Oscillator (SOSC) Note 1: 2: OSCO pin function is determined by the OSCIOFCN Configuration bit. This is the default oscillator mode for an unprogrammed (erased) device. DS39951C-page 102  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 8.3 Control Registers The operation of the oscillator is controlled by three Special Function Registers: • OSCCON • CLKDIV • OSCTUN The OSCCON register (Register 8-1) is the main control register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. REGISTER 8-1: The CLKDIV register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC Oscillator. The OSCTUN register (Register 8-3) allows the user to fine tune the FRC Oscillator over a range of approximately ±12%. Each bit increment or decrement changes the factory calibrated frequency of the FRC Oscillator by a fixed amount. OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 R-0 U-0 R/W-x(1) R/W-x(1) R/W-x(1) — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 bit 15 bit 8 R/SO-0 R/W-0 R-0(3) U-0 R/CO-0 R/W-0 R/W-0 R/W-0 CLKLOCK IOLOCK(2) LOCK — CF POSCEN SOSCEN OSWEN bit 7 bit 0 Legend: CO = Clearable Only bit SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC: Current Oscillator Selection bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC: New Oscillator Selection bits(1) 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) Note 1: 2: 3: x = Bit is unknown Reset values for these bits are determined by the FNOSC Configuration bits. The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected.  2010 Microchip Technology Inc. DS39951C-page 103 PIC24FJ64GA104 FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. bit 6 IOLOCK: I/O Lock Enable bit(2) 1 = I/O lock is active 0 = I/O lock is not active bit 5 LOCK: PLL Lock Status bit(3) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 POSCEN: Primary Oscillator Sleep Enable bit 1 = Primary Oscillator continues to operate during Sleep mode 0 = Primary Oscillator disabled during Sleep mode bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to clock source specified by NOSC bits 0 = Oscillator switch is complete Note 1: 2: 3: Reset values for these bits are determined by the FNOSC Configuration bits. The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected. DS39951C-page 104  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 8-2: R/W-0 CLKDIV: CLOCK DIVIDER REGISTER R/W-0 ROI R/W-0 DOZE2 DOZE1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE: CPU Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 11 DOZEN: DOZE Enable bit(1) 1 = DOZE bits specify the CPU peripheral clock ratio 0 = CPU peripheral clock ratio set to 1:1 bit 10-8 RCDIV: FRC Postscaler Select bits 111 = 31.25 kHz (divide-by-256) 110 = 125 kHz (divide-by-64) 101 = 250 kHz (divide-by-32) 100 = 500 kHz (divide-by-16) 011 = 1 MHz (divide-by-8) 010 = 2 MHz (divide-by-4) 001 = 4 MHz (divide-by-2) 000 = 8 MHz (divide-by-1) bit 7-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.  2010 Microchip Technology Inc. DS39951C-page 105 PIC24FJ64GA104 FAMILY REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN: FRC Oscillator Tuning bits(1) 011111 = Maximum frequency deviation 011110 =    000001 = 000000 = Center frequency, oscillator is running at factory calibrated frequency 111111 =    100001 = 100000 = Minimum frequency deviation Note 1: 8.4 Increments or decrements of TUN may not change the FRC frequency in equal steps over the FRC tuning range and may not be monotonic. Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: The Primary Oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMDx Configuration bits. While an application can switch to and from Primary Oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. DS39951C-page 106 8.4.1 ENABLING CLOCK SWITCHING To enable clock switching, the FCKSM Configuration bits in CW2 must be programmed to ‘00’. (Refer to Section 25.1 “Configuration Bits” for further details.) If the FCKSM Configuration bits are unprogrammed (‘1x’), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting. The NOSCx control bits (OSCCON) do not control the clock selection when clock switching is disabled. However, the COSCx bits (OSCCON) will reflect the clock source selected by the FNOSCx Configuration bits. The OSWEN control bit (OSCCON) has no effect when clock switching is disabled. It is held at ‘0’ at all times.  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 8.4.2 OSCILLATOR SWITCHING SEQUENCE A recommended code sequence for a clock switch includes the following: At a minimum, performing a clock switch requires this basic sequence: 1. 1. 2. 2. 3. 4. 5. If desired, read the COSCx bits (OSCCON), to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSCx bits (OSCCON) for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit to initiate the oscillator switch. 3. 4. 5. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 6. 1. 7. 2. 3. 4. 5. 6. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. If a valid clock switch has been initiated, the LOCK (OSCCON) and CF (OSCCON) bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the OST expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSCx bit values are transferred to the COSCx bits. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM are enabled) or SOSC (if SOSCEN remains set). Note 1: The processor will continue to execute code throughout the clock switching sequence. Timing sensitive code should not be executed during this time. 8. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON in two back-to-back instructions. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence. Execute the unlock sequence for the OSCCON low byte by writing 46h and 57h to OSCCON in two back-to-back instructions. Set the OSWEN bit in the instruction immediately following the unlock sequence. Continue to execute code that is not clock sensitive (optional). Invoke an appropriate amount of software delay (cycle counting) to allow the selected oscillator and/or PLL to start and stabilize. Check to see if OSWEN is ‘0’. If it is, the switch was successful. If OSWEN is still set, then check the LOCK bit to determine the cause of failure. The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example 8-1. EXAMPLE 8-1: BASIC CODE SEQUENCE FOR CLOCK SWITCHING ;Place the new oscillator selection in W0 ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Set new oscillator selection MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON,#0 2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.  2010 Microchip Technology Inc. DS39951C-page 107 PIC24FJ64GA104 FAMILY 8.5 8.5.1 Secondary Oscillator (SOSC) BASIC SOSC OPERATION PIC24FJ64GA104 family devices do not have to set the SOSCEN bit to use the Secondary Oscillator. Any module requiring the SOSC (such as RTCC, Timer1 or DSWDT) will automatically turn on the SOSC when the clock signal is needed. The SOSC, however, has a long start-up time. To avoid delays for peripheral start-up, the SOSC can be manually started using the SOSCEN bit. To use the Secondary Oscillator, the SOSCSEL bits (CW3) must be configured in an oscillator mode – either ‘11’ or ‘01’. Setting SOSCSEL to ‘00’ configures the SOSC pins for Digital mode, enabling digital I/O functionality on the pins. Digital functionality will not be available if the SOSC is configured in either of the oscillator modes. 8.5.2 LOW-POWER SOSC OPERATION The Secondary Oscillator can operate in two distinct levels of power consumption based on device configuration. In Low-Power mode, the oscillator operates in a low drive strength, low-power state. By default, the oscillator uses a higher drive strength, and therefore, requires more power. The Secondary Oscillator Mode Configuration bits, SOSCSEL (CW3), determine the oscillator’s power mode. Programming the SOSCSEL bits to ‘01’ selects low-power operation. The lower drive strength of this mode makes the SOSC more sensitive to noise and requires a longer start-up time. When Low-Power mode is used, care must be taken in the design and layout of the SOSC circuit to ensure that the oscillator starts up and oscillates properly. 8.5.3 EXTERNAL (DIGITAL) CLOCK MODE (SCLKI) The SOSC can also be configured to run from an external 32 kHz clock source, rather than the internal oscillator. In this mode, also referred to as Digital mode, the clock source provided on the SCLKI pin is used to clock any modules that are configured to use the Secondary Oscillator. In this mode, the crystal driving circuit is disabled and the SOSCEN bit (OSCCON) has no effect. 8.5.4 In general, the crystal circuit connections should be as short as possible. It is also good practice to surround the crystal circuit with a ground loop or ground plane. For more information on crystal circuit design, please refer to Section 6 “Oscillator” (DS39700) of the “PIC24F Family Reference Manual”. Additional information is also available in these Microchip Application Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PICmicro® Devices” (DS00826) • AN849, “Basic PICmicro® Oscillator Design” (DS00849). 8.6 Reference Clock Output In addition to the CLKO output (FOSC/2) available in certain oscillator modes, the device clock in the PIC24FJ64GA104 family devices can also be configured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. This reference clock output is controlled by the REFOCON register (Register 8-4). Setting the ROEN bit (REFOCON) makes the clock signal available on the REFO pin. The RODIV bits (REFOCON) enable the selection of 16 different clock divider options. The ROSSLP and ROSEL bits (REFOCON) control the availability of the reference output during Sleep mode. The ROSEL bit determines if the oscillator on OSC1 and OSC2, or the current system clock source, is used for the reference clock output. The ROSSLP bit determines if the reference source is available on REFO when the device is in Sleep mode. To use the reference clock output in Sleep mode, both the ROSSLP and ROSEL bits must be set. The device clock must also be configured for one of the primary modes (EC, HS or XT); otherwise, if the POSCEN bit is not also set, the oscillator on OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches. SOSC LAYOUT CONSIDERATIONS The pinout limitations on low pin count devices, such as those in the PIC24FJ64GA104 family, may make the SOSC more susceptible to noise than other PIC24F devices. Unless proper care is taken in the design and layout of the SOSC circuit, this external noise may introduce inaccuracies into the oscillator’s period. DS39951C-page 108  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 8-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Reference oscillator is enabled on REFO pin 0 = Reference oscillator is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep bit 12 ROSEL: Reference Oscillator Source Select bit 1 = Primary Oscillator is used as the base clock. Note that the crystal oscillator must be enabled using the FOSC bits; the crystal maintains the operation in Sleep mode. 0 = System clock is used as the base clock; base clock reflects any clock switching of the device bit 11-8 RODIV: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. DS39951C-page 109 PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 110  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 9.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 39. “Power-Saving Features with Deep Sleep” (DS39727). The PIC24FJ64GA104 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. All PIC24F devices manage power consumption in four different ways: • Clock Frequency • Instruction-Based Sleep, Idle and Deep Sleep modes • Software Controlled Doze mode • Selective Peripheral Control in Software Combinations of these methods can be used to selectively tailor an application’s power consumption, while still maintaining critical application features, such as timing-sensitive communications. 9.1 Clock Frequency and Clock Switching PIC24F devices allow for a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits. The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 8.0 “Oscillator Configuration”. 9.2 Instruction-Based Power-Saving Modes PIC24F devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution; Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. Deep Sleep mode stops clock operation, code execution and all peripherals except RTCC and DSWDT. It also freezes I/O states and removes power to SRAM and Flash memory. EXAMPLE 9-1: PWRSAV PWRSAV BSET PWRSAV The assembly syntax of the PWRSAV instruction is shown in Example 9-1. Note: SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to “wake-up”. 9.2.1 SLEEP MODE Sleep mode has these features: • The system clock source is shut down. If an on-chip oscillator is used, it is turned off. • The device current consumption will be reduced to a minimum provided that no I/O pin is sourcing current. • The I/O pin directions and states are frozen. • The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source is disabled. • The LPRC clock will continue to run in Sleep mode if the WDT or RTCC with LPRC as clock source is enabled. • The WDT, if enabled, is automatically cleared prior to entering Sleep mode. • Some device features or peripherals may continue to operate in Sleep mode. This includes items, such as the input change notification on the I/O ports, or peripherals that use an external clock input. Any peripheral that requires the system clock source for its operation will be disabled in Sleep mode. The device will wake-up from Sleep mode on any of these events: • On any interrupt source that is individually enabled • On any form of device Reset • On a WDT time-out On wake-up from Sleep, the processor will restart with the same clock source that was active when Sleep mode was entered. PWRSAV INSTRUCTION SYNTAX #SLEEP_MODE #IDLE_MODE DSCON, #DSEN #SLEEP_MODE  2010 Microchip Technology Inc. ; ; ; ; Put the device into SLEEP mode Put the device into IDLE mode Enable Deep Sleep Put the device into Deep SLEEP mode DS39951C-page 111 PIC24FJ64GA104 FAMILY 9.2.2 IDLE MODE Note: Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Selective Peripheral Module Control”). • If the WDT or FSCM is enabled, the LPRC will also remain active. The device will wake from Idle mode on any of these events: • Any interrupt that is individually enabled • Any device Reset • A WDT time-out 9.2.4.1 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS Any interrupt that coincides with the execution of a PWRSAV instruction (except for Deep Sleep) will be held off until entry into Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode. 9.2.4 DEEP SLEEP MODE In PIC24FJ64GA104 family devices, Deep Sleep mode is intended to provide the lowest levels of power consumption available, without requiring the use of external switches to completely remove all power from the device. Entry into Deep Sleep mode is completely under software control. Exit from Deep Sleep mode can be triggered from any of the following events: • • • • • POR event MCLR event RTCC alarm (If the RTCC is present) External Interrupt 0 Deep Sleep Watchdog Timer (DSWDT) time-out In Deep Sleep mode, it is possible to keep the device Real-Time Clock and Calendar (RTCC) running without the loss of clock cycles. Entering Deep Sleep Mode Deep Sleep mode is entered by setting the DSEN bit in the DSCON register, and then executing a SLEEP instruction (PWRSAV #SLEEP_MODE) within one to three instruction cycles to minimize the chance that Deep Sleep will be spuriously entered. If the PWRSAV command is not given within three instruction cycles, the DSEN bit will be cleared by the hardware and must be set again by the software before entering Deep Sleep mode. The DSEN bit is also automatically cleared when exiting the Deep Sleep mode. On wake-up from Idle, the clock is reapplied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction or the first instruction in the ISR. 9.2.3 Since Deep Sleep mode powers down the microcontroller by turning off the on-chip VDDCORE voltage regulator, Deep Sleep capability is available only when operating with the internal regulator enabled. Note: To re-enter Deep Sleep after a Deep Sleep wake-up, allow a delay of at least 3 TCY after clearing the RELEASE bit. The sequence to enter Deep Sleep mode is: 1. 2. 3. 4. 5. 6. If the application requires the Deep Sleep WDT, enable it and configure its clock source (see Section 9.2.4.7 “Deep Sleep WDT” for details). If the application requires Deep Sleep BOR, enable it by programming the DSBOREN Configuration bit (CW4). If the application requires wake-up from Deep Sleep on RTCC alarm, enable and configure the RTCC module (see Section 19.0 “Real-Time Clock and Calendar (RTCC)” for more information). If needed, save any critical application context data by writing it to the DSGPR0 and DSGPR1 registers (optional). Enable Deep Sleep mode by setting the DSEN bit (DSCON). Enter Deep Sleep mode by immediately issuing a PWRSAV #0 instruction. Any time the DSEN bit is set, all bits in the DSWAKE register will be automatically cleared. The device has a dedicated Deep Sleep Brown-out Reset (DSBOR) and a Deep Sleep Watchdog Timer Reset (DSWDT) for monitoring voltage and time-out events. The DSBOR and DSWDT are independent of the standard BOR and WDT used with other power-managed modes (Sleep, Idle and Doze). DS39951C-page 112  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 9.2.4.2 Special Cases when Entering Deep Sleep Mode When entering Deep Sleep mode, there are certain circumstances that require a delay between setting the DSEN bit and executing the PWRSAV instruction. These can be generally reduced to three scenarios: 1. 2. 3. Scenario (1): use an external wake-up source (INT0) or the RTCC is used Scenario (2): with application-level interrupts that can be temporarily disabled Scenario (3): with interrupts that must be monitored In the first scenario, the application requires a wake-up from Deep Sleep on the assertion of the INT0 pin or the RTCC interrupt. In this case, three NOP instructions must be inserted to properly synchronize the detection of an asynchronous INT0 interrupt after the device enters Deep Sleep mode. If the application does not use wake-up on INT0 or RTCC, the NOP instructions are optional. In the second scenario, the application also uses interrupts which can be briefly ignored. With these applications, an interrupt event during the execution of the NOP instructions may cause an ISR to be executed. This means that more than three instruction cycles will elapse before returning to the code and that the DSEN bit will be cleared. To prevent the missed entry into Deep Sleep, temporarily disable interrupts prior to entering Deep Sleep mode. Invoking the DISI instruction for four cycles is sufficient to prevent interrupts from disrupting Deep Sleep entry. In the third scenario, interrupts cannot be ignored even briefly; constant interrupt detection is required, even during the interval between setting DSEN and executing the PWRSAV instruction. For these cases, it is possible to disable interrupts and test for an interrupt condition, skipping the PWRSAV instruction if necessary. Testing for interrupts can be accomplished by checking the status of the CPUIRQ bit (INTTREG). If an unserviced interrupt is pending, this bit will be set. If CPUIRQ is set prior to executing the PWRSAV instruction, the instruction is skipped. At this point, the DISI instruction has expired (being more than 4 instructions from when it was executed) and the application vectors to the appropriate ISR. When the application returns, it can either attempt to re-enter Deep Sleep mode or perform some other system function. In either case, the application must have some functional code located, following the PWRSAV instruction, in the event that the PWRSAV instruction is skipped and the device does not enter Deep Sleep mode.  2010 Microchip Technology Inc. Examples for implementing these cases are shown in Example 9-2. It is recommended that an assembler, or in-line C routine be used in these cases, to ensure that the code executes in the number of cycles required. EXAMPLE 9-2: IMPLEMENTING THE SPECIAL CASES FOR ENTERING DEEP SLEEP // Case 1: simplest delay scenario // asm("bset DSCON, #15"); asm("nop"); asm("nop"); asm("nop"); asm("pwrsav #0"); // // Case 2: interrupts disabled // asm("disi #4"); asm("bset DSCON, #15"); asm("nop"); asm("nop"); asm("nop"); asm("pwrsav #0"); // // Case 3: interrupts disabled with // interrupt testing // asm("disi #4"); asm("bset DSCON, #15"); asm("nop"); asm("nop"); asm("btss INTTREG, #15"); asm("pwrsav #0"); // continue with application code here // DS39951C-page 113 PIC24FJ64GA104 FAMILY 9.2.4.3 Exiting Deep Sleep Mode Deep Sleep mode exits on any one of the following events: • POR event on VDD supply. If there is no DSBOR circuit to re-arm the VDD supply POR circuit, the external VDD supply must be lowered to the natural arming voltage of the POR circuit. • DSWDT time-out. When the DSWDT timer times out, the device exits Deep Sleep. • RTCC alarm (if RTCEN = 1). • Assertion (‘0’) of the MCLR pin. • Assertion of the INT0 pin (if the interrupt was enabled before Deep Sleep mode was entered). The polarity configuration is used to determine the assertion level (‘0’ or ‘1’) of the pin that will cause an exit from Deep Sleep mode. Exiting from Deep Sleep mode requires a change on the INT0 pin while in Deep Sleep mode. Note: Any interrupt pending when entering Deep Sleep mode is cleared. Exiting Deep Sleep mode generally does not retain the state of the device and is equivalent to a Power-on Reset (POR) of the device. Exceptions to this include the RTCC (if present), which remains operational through the wake-up, the DSGPRx registers and the DSWDT bit. 9.2.4.4 Deep Sleep Wake-up Time Since wake-up from Deep Sleep results in a POR, the wake-up time from Deep Sleep is the same as the device POR time. Also, because the internal regulator is turned off, the voltage on VCAP may drop depending on how long the device is asleep. If VCAP has dropped below 2V, then there will be additional wake-up time while the regulator charges VCAP. Deep Sleep wake-up time is specified in Section 28.0 “Electrical Characteristics” as TDSWU. This specification indicates the worst-case wake-up time, including the full POR Reset time (including TPOR and TRST), as well as the time to fully charge a 10 F capacitor on VCAP which has discharged to 0V. Wake-up may be significantly faster if VCAP has not discharged. 9.2.4.5 Saving Context Data with the DSGPR0/DSGPR1 Registers As exiting Deep Sleep mode causes a POR, most Special Function Registers reset to their default POR values. In addition, because VDDCORE power is not supplied in Deep Sleep mode, information in data RAM may be lost when exiting this mode. The sequence for exiting Deep Sleep mode is: Applications which require critical data to be saved prior to Deep Sleep may use the Deep Sleep General Purpose registers, DSGPR0 and DSGPR1, or data EEPROM (if available). Unlike other SFRs, the contents of these registers are preserved while the device is in Deep Sleep mode. After exiting Deep Sleep, software can restore the data by reading the registers and clearing the RELEASE bit (DSCON). 1. 9.2.4.6 Wake-up events that occur from the time Deep Sleep exits, until the time that the POR sequence completes, are ignored, and are not captured in the DSWAKE register. 2. 3. 4. 5. 6. After a wake-up event, the device exits Deep Sleep and performs a POR. The DSEN bit is cleared automatically. Code execution resumes at the Reset vector. To determine if the device exited Deep Sleep, read the Deep Sleep bit, DPSLP (RCON). This bit will be set if there was an exit from Deep Sleep mode. If the bit is set, clear it. Determine the wake-up source by reading the DSWAKE register. Determine if a DSBOR event occurred during Deep Sleep mode by reading the DSBOR bit (DSCON). If application context data has been saved, read it back from the DSGPR0 and DSGPR1 registers. Clear the RELEASE bit (DSCON). DS39951C-page 114 I/O Pins During Deep Sleep During Deep Sleep, the general purpose I/O pins retain their previous states and the Secondary Oscillator (SOSC) will remain running, if enabled. Pins that are configured as inputs (TRIS bit is set) prior to entry into Deep Sleep remain high-impedance during Deep Sleep. Pins that are configured as outputs (TRIS bit is clear) prior to entry into Deep Sleep remain as output pins during Deep Sleep. While in this mode, they continue to drive the output level determined by their corresponding LAT bit at the time of entry into Deep Sleep.  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY Once the device wakes back up, all I/O pins continue to maintain their previous states, even after the device has finished the POR sequence and is executing application code again. Pins configured as inputs during Deep Sleep remain high-impedance and pins configured as outputs continue to drive their previous value. After waking up, the TRIS and LAT registers, and the SOSCEN bit (OSCCON) are reset. If firmware modifies any of these bits or registers, the I/O will not immediately go to the newly configured states. Once the firmware clears the RELEASE bit (DSCON) the I/O pins are “released”. This causes the I/O pins to take the states configured by their respective TRIS and LAT bit values. This means that keeping the SOSC running after waking up requires the SOSCEN bit to be set before clearing RELEASE. If the Deep Sleep BOR (DSBOR) is enabled, and a DSBOR or a true POR event occurs during Deep Sleep, the I/O pins will be immediately released similar to clearing the RELEASE bit. All previous state information will be lost, including the general purpose DSGPR0 and DSGPR1 contents. If a MCLR Reset event occurs during Deep Sleep, the DSGPRx, DSCON and DSWAKE registers will remain valid and the RELEASE bit will remain set. The state of the SOSC will also be retained. The I/O pins, however, will be reset to their MCLR Reset state. Since RELEASE is still set, changes to the SOSCEN bit (OSCCON) cannot take effect until the RELEASE bit is cleared. In all other Deep Sleep wake-up cases, application firmware must clear the RELEASE bit in order to reconfigure the I/O pins. 9.2.4.7 Deep Sleep WDT To enable the DSWDT in Deep Sleep mode, program the Configuration bit, DSWDTEN (CW4). The device Watchdog Timer (WDT) need not be enabled for the DSWDT to function. Entry into Deep Sleep mode automatically resets the DSWDT. 9.2.4.8 Switching Clocks in Deep Sleep Mode Both the RTCC and the DSWDT may run from either SOSC or the LPRC clock source. This allows both the RTCC and DSWDT to run without requiring both the LPRC and SOSC to be enabled together, reducing power consumption. Running the RTCC from LPRC will result in a loss of accuracy in the RTCC of approximately 5 to 10%. If an accurate RTCC is required, it must be run from the SOSC clock source. The RTCC clock source is selected with the RTCOSC Configuration bit (CW4). Under certain circumstances, it is possible for the DSWDT clock source to be off when entering Deep Sleep mode. In this case, the clock source is turned on automatically (if DSWDT is enabled), without the need for software intervention. However, this can cause a delay in the start of the DSWDT counters. In order to avoid this delay when using SOSC as a clock source, the application can activate SOSC prior to entering Deep Sleep mode. 9.2.4.9 Checking and Clearing the Status of Deep Sleep Upon entry into Deep Sleep mode, the status bit, DPSLP (RCON), becomes set and must be cleared by software. On power-up, the software should read this status bit to determine if the Reset was due to an exit from Deep Sleep mode and clear the bit if it is set. Of the four possible combinations of DPSLP and POR bit states, three cases can be considered: • Both the DPSLP and POR bits are cleared. In this case, the Reset was due to some event other than a Deep Sleep mode exit. • The DPSLP bit is clear, but the POR bit is set. This is a normal Power-on Reset. • Both the DPSLP and POR bits are set. This means that Deep Sleep mode was entered, the device was powered down and Deep Sleep mode was exited. The DSWDT clock source is selected by the DSWDTOSC Configuration bit (CW4). The postscaler options are programmed by the DSWDTPS Configuration bits (CW4). The minimum time-out period that can be achieved is 2.1 ms and the maximum is 25.7 days. For more details on the CW4 Configuration register and DSWDT configuration options, refer to Section 25.0 “Special Features”.  2010 Microchip Technology Inc. DS39951C-page 115 PIC24FJ64GA104 FAMILY 9.2.4.10 Power-on Resets (PORs) 9.2.4.11 Summary of Deep Sleep Sequence VDD voltage is monitored to produce PORs. Since exiting from Deep Sleep functionally looks like a POR, the technique described in Section 9.2.4.9 “Checking and Clearing the Status of Deep Sleep” should be used to distinguish between Deep Sleep and a true POR event. To review, these are the necessary steps involved in invoking and exiting Deep Sleep mode: When a true POR occurs, the entire device, including all Deep Sleep logic (Deep Sleep registers, RTCC, DSWDT, etc.) is reset. 3. 1. 2. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. DS39951C-page 116 Device exits Reset and begins to execute its application code. If DSWDT functionality is required, program the appropriate Configuration bit. Select the appropriate clock(s) for the DSWDT and RTCC (optional). Enable and configure the RTCC (optional). Write context data to the DSGPRx registers (optional). Enable the INT0 interrupt (optional). Set the DSEN bit in the DSCON register. Enter Deep Sleep by issuing a PWRSV #SLEEP_MODE command. Device exits Deep Sleep when a wake-up event occurs. The DSEN bit is automatically cleared. Read and clear the DPSLP status bit in RCON, and the DSWAKE status bits. Read the DSGPRx registers (optional). Once all state related configurations are complete, clear the RELEASE bit. Application resumes normal operation.  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 9-1: DSCON: DEEP SLEEP CONTROL REGISTER R/W-0, HC U-0 U-0 U-0 U-0 U-0 U-0 U-0 DSEN(1) — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — U-0 — U-0 — U-0 — R/W-0, HCS R/C-0, HS (1,2,3) RELEASE(1,2) DSBOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit C = Clearable bit U = Unimplemented, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HC = Hardware Clearable bit HS = Hardware Settable bit HCS = Hardware Clearable/Settable bit bit 15 DSEN: Deep Sleep Enable bit(1) 1 = Device enters Deep Sleep when PWRSAV #0 is executed in the next instruction 0 = Device enters normal Sleep when PWRSAV #0 is executed bit 14-2 Unimplemented: Read as ‘0’ bit 1 DSBOR: Deep Sleep BOR Event Status bit(1,2,3) 1 = The DSBOR was active and a BOR event was detected during Deep Sleep 0 = The DSBOR was disabled or was active and did not detect a BOR event during Deep Sleep bit 0 RELEASE: I/O Pin State Deep Sleep Release bit(1,2) 1 = I/O pins and SOSC maintain their states following exit from Deep Sleep, regardless of their LAT and TRIS configuration 0 = I/O pins and SOSC are released from their Deep Sleep states. The pin state is controlled by the LAT and TRIS configurations, and the SOSCEN bit. Note 1: 2: 3: These bits are reset only in the case of a POR event outside of Deep Sleep mode. Reset value is ‘0’ for initial power-on POR only and ‘1’ for Deep Sleep POR. This is a status bit only; a DSBOR event will NOT cause a wake-up from Deep Sleep.  2010 Microchip Technology Inc. DS39951C-page 117 PIC24FJ64GA104 FAMILY REGISTER 9-2: DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — DSINT0(1) bit 15 bit 8 R/W-0, HS DSFLT U-0 (1) — U-0 — R/W-0, HS R/W-0, HS R/W-0, HS (1) (1) (1) DSWDT DSRTC U-0 R/W-0, HS — DSPOR(2) DSMCLR bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 DSINT0: Interrupt-on-Change bit(1) 1 = External Interrupt 0 was asserted during Deep Sleep 0 = External Interrupt 0 was not asserted during Deep Sleep bit 7 DSFLT: Deep Sleep Fault Detected bit(1) 1 = A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been corrupted 0 = No Fault was detected during Deep Sleep bit 6-5 Unimplemented: Read as ‘0’ bit 4 DSWDT: Deep Sleep Watchdog Timer Time-out bit(1) 1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep 0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep bit 3 DSRTC: Real-Time Clock and Calendar Alarm bit(1) 1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep 0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep bit 2 DSMCLR: Deep Sleep MCLR Event bit(1) 1 = The MCLR pin was asserted during Deep Sleep 0 = The MCLR pin was not asserted during Deep Sleep bit 1 Unimplemented: Read as ‘0’ bit 0 DSPOR: Power-on Reset Event bit(2) 1 = The VDD supply POR circuit was active and a POR event was detected 0 = The VDD supply POR circuit was not active, or was active, but did not detect a POR event Note 1: 2: This bit can only be set while the device is in Deep Sleep mode. This bit can be set outside of Deep Sleep. DS39951C-page 118  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 9.3 Doze Mode Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely. Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. Doze mode is enabled by setting the DOZEN bit (CLKDIV). The ratio between peripheral and core clock speed is determined by the DOZE bits (CLKDIV). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default. It is also possible to use Doze mode to selectively reduce power consumption in event driven applications. This allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the CPU Idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV). By default, interrupt events have no effect on Doze mode operation. 9.4 Selective Peripheral Module Control Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock. Even so, peripheral modules still remain clocked, and thus, consume power. There may be cases where the application needs what these modes do not provide: the allocation of power resources to CPU processing with minimal power consumption from the peripherals. PIC24F devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with two control bits: • The Peripheral Enable bit, generically named “XXXEN”, located in the module’s main control SFR. • The Peripheral Module Disable (PMD) bit, generically named “XXXMD”, located in one of the PMD Control registers. Both bits have similar functions in enabling or disabling its associated module. Setting the PMD bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. In this state, the control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect and read values will be invalid. Many peripheral modules have a corresponding PMD bit. In contrast, disabling a module by clearing its XXXEN bit disables its functionality, but leaves its registers available to be read and written to. This reduces power consumption, but not by as much as setting the PMD bit does. Most peripheral modules have an enable bit; exceptions include input capture, output compare and RTCC. To achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters Idle mode. This is done through the control bit of the generic name format, “XXXIDL”. By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications.  2010 Microchip Technology Inc. DS39951C-page 119 PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 120  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 10.0 Note: I/O PORTS When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 12. “I/O Ports with Peripheral Pin Select (PPS)” (DS39711). All of the device pins (except VDD, VSS, MCLR and OSCI/CLKI) are shared between the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity. 10.1 Parallel I/O (PIO) Ports A parallel I/O port that shares a pin with a peripheral is, in general, subservient to the peripheral. The peripheral’s output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. Figure 10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. FIGURE 10-1: All port pins have three registers directly associated with their operation as digital I/Os. The Data Direction register (TRIS) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the Output Latch register (LAT), read the latch. Writes to the Output Latch register, write the latch. Reads from the port (PORT), read the port pins, while writes to the port pins, write the latch. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LAT and TRIS registers, and the port pin will read as zeros. When a pin is shared with another peripheral or function that is defined as an input only, it is regarded as a dedicated port because there is no other competing source of outputs. BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Peripheral Output Data 0 PIO Module Read TRIS Data Bus WR TRIS 1 Output Enable Output Data 0 D Q I/O Pin CK TRIS Latch D WR LAT + WR PORT Q CK Data Latch Read LAT Input Data Read PORT  2010 Microchip Technology Inc. DS39951C-page 121 PIC24FJ64GA104 FAMILY 10.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired digital only pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. 10.2 Configuring Analog Port Pins The AD1PCFGL and TRIS registers control the operation of the A/D port pins. Setting a port pin as an analog input also requires that the corresponding TRIS bit be set. If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. 10.2.2 ANALOG INPUT PINS AND VOLTAGE CONSIDERATIONS The voltage tolerance of pins used as device inputs is dependent on the pin’s input function. Pins that are used as digital only inputs are able to handle DC voltages up to 5.5V, a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind can only tolerate voltages up to VDD. Voltage excursions beyond VDD on these pins should be avoided. Table 10-1 summarizes the input voltage capabilities. Refer to Section 28.0 “Electrical Characteristics” for more details. TABLE 10-1: Port or Pin PORTA PORTB Pins configured as digital inputs will not convert an analog input. Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. PORTA(1) I/O PORT WRITE/READ TIMING Tolerated Input Description VDD Only VDD input levels tolerated. 5.5V Tolerates input levels above VDD, useful for most standard logic. PORTB When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). 10.2.1 INPUT VOLTAGE TOLERANCE PORTC(1) PORTB PORTB PORTC(1) Note 1: Not available on 28-pin devices. One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP (Example 10-1). EXAMPLE 10-1: MOV MOV NOP BTSS 0xFF00, W0 W0, TRISB PORTB, #13 DS39951C-page 122 PORT WRITE/READ EXAMPLE ; ; ; ; Configure PORTB as inputs and PORTB as outputs Delay 1 cycle Next Instruction  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 10.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ64GA104 family of devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature is capable of detecting input Change-of-States even in Sleep mode, when the clocks are disabled. Depending on the device pin count, there are up to 31 external inputs that may be selected (enabled) for generating an interrupt request on a Change-of-State. Registers, CNEN1 and CNEN2, contain the interrupt enable control bits for each of the CN input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. Each CN pin has a weak pull-up connected to it. The pull-up acts as a current source that is connected to the pin. This eliminates the need for external resistors when push button or keypad devices are connected. The pull-ups are separately enabled using the CNPU1 and CNPU2 registers (for pull-ups). Each CN pin has individual control bits for its pull-up. Setting a control bit enables the weak pull-up for the corresponding pin. When the internal pull-up is selected, the pin pulls up to VDD – 0.7V (typical). Make sure that there is no external pull-up source when the internal pull-ups are enabled, as the voltage difference can cause a current path. Note: 10.4 Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. Peripheral Pin Select (PPS) A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. In an application that needs to use more than one peripheral multiplexed on a single pin, inconvenient work arounds in application code or a complete redesign may be the only option. The Peripheral Pin Select feature provides an alternative to these choices by enabling the user’s peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The Peripheral Pin Select feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of any one of many digital peripherals to any one of these I/O pins. Peripheral Pin Select is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established.  2010 Microchip Technology Inc. 10.4.1 AVAILABLE PINS The Peripheral Pin Select feature is used with a range of up to 25 pins, depending on the particular device and its pin count. Pins that support the Peripheral Pin Select feature include the designation “RPn” in their full pin designation, where “n” is the remappable pin number. See Table 1-2 for a summary of pinout options in each package offering. 10.4.2 AVAILABLE PERIPHERALS The peripherals managed by the Peripheral Pin Select are all digital only peripherals. These include general serial communications (UART and SPI), general purpose timer clock inputs, timer related peripherals (input capture and output compare) and external interrupt inputs. Also included are the outputs of the comparator module, since these are discrete digital signals. Peripheral Pin Select is not available for I2C™ change notification inputs, RTCC alarm outputs or peripherals with analog inputs. A key difference between pin select and non pin select peripherals is that pin select peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non pin select peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. 10.4.2.1 Peripheral Pin Select Function Priority Pin-selectable peripheral outputs (for example, OC and UART transmit) take priority over any general purpose digital functions permanently tied to that pin, such as PMP and port I/O. Specialized digital outputs, such as USB functionality, take priority over PPS outputs on the same pin. The pin diagrams at the beginning of this data sheet list peripheral outputs in order of priority. Refer to them for priority concerns on a particular pin. Unlike devices with fixed peripherals, pin-selectable peripheral inputs never take ownership of a pin. The pin’s output buffer is controlled by the pin’s TRIS bit setting, or by a fixed peripheral on the pin. If the pin is configured in Digital mode, then the PPS input will operate correctly, reading the input. If an analog function is enabled on the same pin, the pin-selectable input will be disabled. DS39951C-page 123 PIC24FJ64GA104 FAMILY 10.4.3 CONTROLLING PERIPHERAL PIN SELECT Peripheral Pin Select features are controlled through two sets of Special Function Registers: one to map peripheral inputs and one to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on if an input or an output is being mapped. TABLE 10-2: 10.4.3.1 Input Mapping The inputs of the Peripheral Pin Select options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 10-1 through Register 10-14). Each register contains up to two sets of 5-bit fields, with each set associated with one of the pin-selectable peripherals. Programming a given peripheral’s bit field with an appropriate 6-bit value maps the RPn pin with that value to that peripheral. For any given device, the valid range of values for any of the bit fields corresponds to the maximum number of Peripheral Pin Select options supported by the device. SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Function Name Register Function Mapping Bits External Interrupt 1 INT1 RPINR0 INT1R External Interrupt 2 Input Capture 1 INT2 IC1 RPINR1 RPINR7 INT2R IC1R Input Capture 2 Input Capture 3 IC2 IC3 RPINR7 RPINR8 IC2R IC3R Input Capture 4 Input Capture 5 IC4 IC5 RPINR8 RPINR9 IC4R IC5R OCFA OCFB RPINR11 RPINR11 OCFAR OCFBR SPI1 Clock Input SPI1 Data Input SCK1IN SDI1 RPINR20 RPINR20 SCK1R SDI1R SPI1 Slave Select Input SPI2 Clock Input SS1IN SCK2IN RPINR21 RPINR22 SS1R SCK2R SPI2 Data Input SPI2 Slave Select Input SDI2 SS2IN RPINR22 RPINR23 SDI2R SS2R Timer2 External Clock Timer3 External Clock T2CK T3CK RPINR3 RPINR3 T2CKR T3CKR Timer4 External Clock Timer5 External Clock T4CK T5CK RPINR4 RPINR4 T4CKR T5CKR UART1 Clear To Send U1CTS RPINR18 U1CTSR U1RX RPINR18 U1RXR U2CTS U2RX RPINR19 RPINR19 U2CTSR U2RXR Input Name Output Compare Fault A Output Compare Fault B UART1 Receive UART2 Clear To Send UART2 Receive Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. DS39951C-page 124  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 10.4.3.2 Output Mapping the bit field corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 10-3). In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Each register contains up to two 5-bit fields, with each field being associated with one RPn pin (see Register 10-15 through Register 10-27). The value of TABLE 10-3: Because of the mapping technique, the list of peripherals for output mapping also includes a null value of ‘000000’. This permits any given pin to remain disconnected from the output of any of the pin-selectable peripherals. SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT) Output Function Number(1) Function 0 NULL(2) Null 1 C1OUT Comparator 1 Output 2 C2OUT Comparator 2 Output 3 U1TX UART1 Transmit 4 U1RTS 5 U2TX 6 Note 1: 2: 3: (3) U2RTS (3) Output Name UART1 Request To Send UART2 Transmit UART2 Request To Send 7 SDO1 SPI1 Data Output 8 SCK1OUT SPI1 Clock Output 9 SS1OUT SPI1 Slave Select Output 10 SDO2 SPI2 Data Output 11 SCK2OUT SPI2 Clock Output 12 SS2OUT SPI2 Slave Select Output 18 OC1 Output Compare 1 19 OC2 Output Compare 2 20 OC3 Output Compare 3 21 OC4 Output Compare 4 22 OC5 Output Compare 5 23-28 (unused) NC 29 CTPLS CTMU Output Pulse 30 C3OUT Comparator 3 Output 31 (unused) NC Setting the RPORx register with the listed value assigns that output function to the associated RPn pin. The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. IrDA® BCLK functionality uses this output.  2010 Microchip Technology Inc. DS39951C-page 125 PIC24FJ64GA104 FAMILY 10.4.3.3 Mapping Limitations The control schema of the Peripheral Pin Select is extremely flexible. Other than systematic blocks that prevent signal contention caused by two physical pins being configured as the same functional input, or two functional outputs configured as the same pin, there are no hardware enforced lock outs. The flexibility extends to the point of allowing a single input to drive multiple peripherals or a single functional output to drive multiple output pins. 10.4.3.4 PPS Mapping Exceptions for PIC24FJ64GA1 Family Devices Although the PPS registers allow for up to 32 remappable pins, a maximum of 26 pins are implemented in 44-pin devices (RP0 through RP25). In 28-pin devices, none of the remappable pins above RP15 are implemented. 10.4.4 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC24F devices include three features to prevent alterations to the peripheral map: • Control register lock sequence • Continuous state monitoring • Configuration bit remapping lock 10.4.4.1 Control Register Lock Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. Unlike the similar sequence with the oscillator’s LOCK bit, IOLOCK remains in one state until changed. This allows all of the Peripheral Pin Selects to be configured with a single unlock sequence, followed by an update to all control registers, then locked with a second lock sequence. 10.4.4.2 Continuous State Monitoring In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are constantly monitored in hardware by shadow registers. If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered. 10.4.4.3 Configuration Bit Pin Select Lock As an additional level of safety, the device can be configured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (CW2) Configuration bit blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure will not execute and the Peripheral Pin Select Control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows users unlimited access (with the proper use of the unlock sequence) to the Peripheral Pin Select registers. To set or clear IOLOCK, a specific command sequence must be executed: 1. 2. 3. Write 46h to OSCCON. Write 57h to OSCCON. Clear (or set) IOLOCK as a single operation. DS39951C-page 126  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 10.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION The ability to control Peripheral Pin Selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the Peripheral Pin Selects are not available on default pins in the device’s default (Reset) state. Since all RPINRx registers reset to ‘11111’ and all RPORx registers reset to ‘00000’, all Peripheral Pin Select inputs are tied to VSS and all Peripheral Pin Select outputs are disconnected. Note: RP31 does not have to exist on a device for the registers to be reset to it, or for peripheral pin outputs to be tied to it. This situation requires the user to initialize the device with the proper peripheral configuration before any other application code is executed. Since the IOLOCK bit resets in the unlocked state, it is not necessary to execute the unlock sequence after the device has come out of Reset. For application safety, however, it is best to set IOLOCK and lock the configuration after writing to the control registers. Because the unlock sequence is timing-critical, it must be executed as an assembly language routine in the same manner as changes to the oscillator configuration. If the bulk of the application is written in C or another high-level language, the unlock sequence should be performed by writing in-line assembly. The assignment of a peripheral to a particular pin does not automatically perform any other configuration of the pin’s I/O circuitry. In theory, this means adding a pin-selectable output to a pin may mean inadvertently driving an existing peripheral input when the output is driven. Users must be familiar with the behavior of other fixed peripherals that share a remappable pin and know when to enable or disable them. To be safe, fixed digital peripherals that share the same pin should be disabled when not in use. Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that feature on. The peripheral must be specifically configured for operation and enabled, as if it were tied to a fixed pin. Where this happens in the application code (immediately following device Reset and peripheral configuration or inside the main application routine) depends on the peripheral and its use in the application. A final consideration is that Peripheral Pin Select functions neither override analog inputs, nor reconfigure pins with analog functions for digital I/O. If a pin is configured as an analog input on device Reset, it must be explicitly reconfigured as digital I/O when used with a Peripheral Pin Select. Example 10-2 shows a configuration for bidirectional communication with flow control using UART1. The following input and output functions are used: • Input Functions: U1RX, U1CTS • Output Functions: U1TX, U1RTS Choosing the configuration requires the review of all Peripheral Pin Selects and their pin assignments, especially those that will not be used in the application. In all cases, unused pin-selectable peripherals should be disabled completely. Unused peripherals should have their inputs assigned to an unused RPn pin function. I/O pins with unused RPn functions should be configured with the null peripheral output.  2010 Microchip Technology Inc. DS39951C-page 127 PIC24FJ64GA104 FAMILY EXAMPLE 10-2: ;unlock push push push mov mov mov mov.b mov.b bclr CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS IN ASSEMBLY CODE registers w1; w2; w3; #OSCCON, w1; #0x46, w2; #0x57, w3; w2, [w1]; w3, [w1]; OSCCON, #6; ; Configure Input Functions (Table10-2) ; Assign U1CTS To Pin RP1, U1RX To Pin RP0 mov #0x0100, w1; mov w1,RPINR18; ; Configure Output Functions (Table 10-3) ; Assign U1RTS To Pin RP3, U1TX To Pin RP2 mov #0x0403, w1; mov w1, RPOR1; ;lock mov mov mov mov.b mov.b bset pop pop pop registers #OSCCON, w1; #0x46, w2; #0x57, w3; w2, [w1]; w3, [w1]; OSCCON, #6; w3; w2; w1; EXAMPLE 10-3: CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS IN C //unlock registers __builtin_write_OSCCONL(OSCCON & 0xBF); // Configure Input Functions (Table 9-1) // Assign U1RX To Pin RP0 RPINR18bits.U1RXR = 0; // Assign U1CTS To Pin RP1 RPINR18bits.U1CTSR = 1; // Configure Output Functions (Table 9-2) // Assign U1TX To Pin RP2 RPOR1bits.RP2R = 3; // Assign U1RTS To Pin RP3 RPOR1bits.RP3R = 4; //lock registers __builtin_write_OSCCONL(OSCCON | 0x40); DS39951C-page 128  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 10.4.6 PERIPHERAL PIN SELECT REGISTERS Note: The PIC24FJ64GA104 family of devices implements a total of 27 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (14) • Output Remappable Peripheral Registers (13) REGISTER 10-1: Input and output register values can only be changed if IOLOCK (OSCCON) = 0. See Section 10.4.4.1 “Control Register Lock” for a specific command sequence. RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 INT1R: Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’ REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 INT2R: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn pin bits  2010 Microchip Technology Inc. DS39951C-page 129 PIC24FJ64GA104 FAMILY REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T3CKR: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T2CKR: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits REGISTER 10-4: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T4CKR4 T4CKR3 T4CKR2 T4CKR1 T4CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T5CKR: Assign Timer5 External Clock (T5CK) to Corresponding RPn or RPIn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T4CKR: Assign Timer4 External Clock (T4CK) to Corresponding RPn or RPIn Pin bits DS39951C-page 130  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 10-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC2R: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC1R: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits REGISTER 10-6: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC4R: Assign Input Capture 4 (IC4) to Corresponding RPn or RPIn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC3R: Assign Input Capture 3 (IC3) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. DS39951C-page 131 PIC24FJ64GA104 FAMILY REGISTER 10-7: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC5R4 IC5R3 IC5R2 IC5R1 IC5R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 IC5R: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits REGISTER 10-8: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 OCFBR: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits DS39951C-page 132  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 10-9: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 U1CTSR: Assign UART1 Clear to Send (U1CTS) to Corresponding RPn or RPIn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 U1RXR: Assign UART1 Receive (U1RX) to Corresponding RPn or RPIn Pin bits REGISTER 10-10: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 U2CTSR: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 U2RXR: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. DS39951C-page 133 PIC24FJ64GA104 FAMILY REGISTER 10-11: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 SCK1R: Assign SPI1 Clock Input (SCK1IN) to Corresponding RPn or RPIn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SDI1R: Assign SPI1 Data Input (SDI1) to Corresponding RPn or RPIn Pin bits REGISTER 10-12: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS1R: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits DS39951C-page 134  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 10-13: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 SCK2R: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SDI2R: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits REGISTER 10-14: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SS2R4 SS2R3 SS2R2 SS2R1 SS2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS2R: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. DS39951C-page 135 PIC24FJ64GA104 FAMILY REGISTER 10-15: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP1R CxINA Compare CEN = 1, CREF = 0, CCH = 01 COE VIN- CXINC Cx CxOUT Pin CXINA COE VINVIN+ CVREF- Cx CxOUT Pin Comparator CxINB > CVREF+ Compare CEN = 1, CREF = 1, CCH = 00 CXINB CVREF+ CXINC Cx CxOUT Pin CVREF+ DS39951C-page 230 VIN+ CVREF+ Cx CxOUT Pin COE VINVIN+ Cx CxOUT Pin COE VINVIN+ Cx CxOUT Pin Comparator CVREF- > CVREF+ Compare CEN = 1, CREF = 1, CCH = 11 COE VIN- VIN+ Comparator CxINC > CVREF+ Compare CEN = 1, CREF = 1, CCH = 01 Comparator CxIND > CVREF+ Compare CEN = 1, CREF = 1, CCH = 10 CXIND CXINA COE VINVIN+ CXINA COE VIN- Comparator CVREF- > CxINA Compare CEN = 1, CREF = 0, CCH = 11 Comparator CxIND > CxINA Compare CEN = 1, CREF = 0, CCH = 10 CXIND CxOUT Pin CVREF- Cx CxOUT Pin CVREF+ COE VINVIN+ Cx CxOUT Pin  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 22-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R-0 CEN COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CEN: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 14 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin. 0 = Comparator output is internal only bit 13 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 12-10 Unimplemented: Read as ‘0’ bit 9 CEVT: Comparator Event bit 1 = Comparator event defined by EVPOL has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred bit 8 COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VIN- bit 7-6 EVPOL: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt generated on transition of comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled bit 5 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. DS39951C-page 231 PIC24FJ64GA104 FAMILY REGISTER 22-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) bit 4 CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to internal CVREF+ input reference voltage 0 = Non-inverting input connects to CxINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH: Comparator Channel Select bits 11 = Inverting input of comparator connects to CVREF- input reference voltage 10 = Inverting input of comparator connects to CxIND pin 01 = Inverting input of comparator connects to CxINC pin 00 = Inverting input of comparator connects to CxINB pin REGISTER 22-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 CMIDL — — — — C3EVT C2EVT C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — C3OUT C2OUT C1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMIDL: Comparator Stop in Idle Mode bit 1 = Discontinue operation of all comparators when device enters Idle mode 0 = Continue operation of all enabled comparators in Idle mode bit 14-11 Unimplemented: Read as ‘0’ bit 10 C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON). bit 9 C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON). bit 8 C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON). bit 7-3 Unimplemented: Read as ‘0’ bit 2 C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON). bit 1 C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON). bit 0 C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON). DS39951C-page 232  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 23.0 COMPARATOR VOLTAGE REFERENCE Note: 23.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 20. “Comparator Voltage Reference Module” (DS39709). Configuring the Comparator Voltage Reference voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR), with one range offering finer resolution. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON). The settling time of the comparator voltage reference must be considered when changing the CVREF output. The voltage reference module is controlled through the CVRCON register (Register 23-1). The comparator voltage reference provides two ranges of output FIGURE 23-1: VREF+ AVDD COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 8R CVRSS = 0 CVR CVREFP R CVREN R VREF+ 1 CVREF+ R 16-to-1 MUX R 0 16 Steps R CVREF R CVROE R CVRR VREF- CVREFM 8R CVRSS = 1 CVRSS = 0 AVSS  2010 Microchip Technology Inc. VREF+ 11 VBG/6 10 VBG 01 VBG/2 00 CVREF- DS39951C-page 233 PIC24FJ64GA104 FAMILY REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CVREFP CVREFM1 CVREFM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CVREFP: CVREF+ Reference Output Select bit 1 = Use VREF+ input pin as CVREF+ reference output to comparators 0 = Use comparator voltage reference module’s generated output as CVREF+ reference output to comparators bit 9-8 CVREFM: CVREF- Reference Output Select bits 11 = Use VREF+ input pin as CVREF- reference output to comparators 10 = Use VBG/6 as CVREF- reference output to comparators 01 = Use VBG as CVREF- reference output to comparators 00 = Use VBG/2 as CVREF- reference output to comparators bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit is powered on 0 = CVREF circuit is powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = VREF+ – VREF0 = Comparator reference source, CVRSRC = AVDD – AVSS bit 3-0 CVR: Comparator VREF Value Selection (0  CVR  15) bits When CVRR = 1: CVREF = (CVR/24)  (CVRSRC) When CVRR = 0: CVREF = 1/4  (CVRSRC) + (CVR/32)  (CVRSRC) DS39951C-page 234  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 24.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual”, Section 11. “Charge Time Measurement Unit (CTMU)” (DS39724). The Charge Time Measurement Unit is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. Its key features include: • • • • • • Four edge input trigger sources Polarity control for each edge source Control of edge sequence Control of response to edges Time measurement resolution of 1 nanosecond Accurate current source suitable for capacitive measurement Together with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses that are independent of the system clock. The CTMU module is ideal for interfacing with capacitive-based sensors. The CTMU is controlled through two registers: CTMUCON and CTMUICON. CTMUCON enables the module and controls edge source selection, edge source polarity selection and edge sequencing. The CTMUICON register controls the selection and trim of the current source. FIGURE 24-1: 24.1 Measuring Capacitance The CTMU module measures capacitance by generating an output pulse, with a width equal to the time between edge events, on two separate input channels. The pulse edge events to both input channels can be selected from four sources: two internal peripheral modules (OC1 and Timer1) and two external pins (CTEDG1 and CTEDG2). This pulse is used with the module’s precision current source to calculate capacitance according to the relationship: i=C• dV dT For capacitance measurements, the A/D Converter samples an external capacitor (CAPP) on one of its input channels after the CTMU output’s pulse. A Precision Resistor (RPR) provides current source calibration on a second A/D channel. After the pulse ends, the converter determines the voltage on the capacitor. The actual calculation of capacitance is performed in software by the application. Figure 24-1 shows the external connections used for capacitance measurements, and how the CTMU and A/D modules are related in this application. This example also shows the edge events coming from Timer1, but other configurations using external edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the “PIC24F Family Reference Manual”. TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 Current Source EDG2 Output Pulse ANx A/D Converter ANY CAPP  2010 Microchip Technology Inc. RPR DS39951C-page 235 PIC24FJ64GA104 FAMILY 24.2 Measuring Time When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON), the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected. When CDELAY charges above the CVREF trip point, a pulse is output on CTPLS. The length of the pulse delay is determined by the value of CDELAY and the CVREF trip point. Time measurements on the pulse width can be similarly performed using the A/D module’s internal capacitor (CAD) and a precision resistor for current calibration. Figure 24-2 shows the external connections used for time measurements, and how the CTMU and A/D modules are related in this application. This example also shows both edge events coming from the external CTEDG pins, but other configurations using internal edge sources are possible. For the smallest time measurements, select the internal A/D Channel 31, CH0Sx = 11111. This minimizes any stray capacitance that may otherwise be associated with using an input pin, thus keeping the total capacitance to that of the A/D Converter itself (4-5 pF). A detailed discussion on measuring capacitance and time with the CTMU module is provided in the “PIC24F Family Reference Manual”. 24.3 Figure 24-3 shows the external connections for pulse generation, as well as the relationship of the different analog modules required. While CTEDG1 is shown as the input pulse source, other options are available. A detailed discussion on pulse generation with the CTMU module is provided in the “PIC24F Family Reference Manual”. Pulse Generation and Delay The CTMU module can also generate an output pulse with edges that are not synchronous with the device’s system clock. More specifically, it can generate a pulse with a programmable delay from an edge event input to the module. FIGURE 24-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC24F Device CTMU CTEDG1 EDG1 CTEDG2 EDG2 Current Source Output Pulse A/D Converter ANx CAD RPR FIGURE 24-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTEDG1 EDG1 CTMU CTPLS Current Source Comparator C2INB C2 CDELAY CVREF DS39951C-page 236  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 24-1: R/W-0 CTMUCON: CTMU CONTROL REGISTER U-0 CTMUEN R/W-0 — CTMUSIDL R/W-0 (1) TGEN R/W-0 R/W-0 R/W-0 R/W-0 EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 TGEN: Time Generation Enable bit(1) 1 = Enables edge delay generation 0 = Disables edge delay generation bit 11 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 10 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 9 IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 8 CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative edge response bit 6-5 EDG2SEL: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 is programmed for a positive edge response 0 = Edge 1 is programmed for a negative edge response Note 1: x = Bit is unknown If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. For more information, see Section 10.4 “Peripheral Pin Select (PPS)”.  2010 Microchip Technology Inc. DS39951C-page 237 PIC24FJ64GA104 FAMILY REGISTER 24-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 3-2 EDG1SEL: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred Note 1: If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. For more information, see Section 10.4 “Peripheral Pin Select (PPS)”. REGISTER 24-2: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 ITRIM: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 ..... 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG 111111 = Minimum negative change from nominal current ..... 100010 100001 = Maximum negative change from nominal current bit 9-8 IRNG: Current Source Range Select bits 11 = 100  Base Current 10 = 10  Base Current 01 = Base current level (0.55 A nominal) 00 = Current source is disabled bit 7-0 Unimplemented: Read as ‘0’ DS39951C-page 238 x = Bit is unknown  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 25.0 Note: SPECIAL FEATURES 25.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the “PIC24F Family Reference Manual”: In PIC24FJ64GA104 family devices, the configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the three words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific locations are shown in Table 25-1. These are packed representations of the actual device Configuration bits, whose actual locations are distributed among several locations in configuration space. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. • Section 9. “Watchdog Timer (WDT)” (DS39697) • Section 32. “High-Level Device Integration” (DS39719) • Section 33. “Programming and Diagnostics” (DS39716) PIC24FJ64GA104 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • • • • • • Note: Flexible Configuration Watchdog Timer (WDT) Code Protection JTAG Boundary Scan Interface In-Circuit Serial Programming In-Circuit Emulation 25.1 Configuration data is reloaded on all types of device Resets. When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. The upper byte of all Flash Configuration Words in program memory should always be ‘1111 1111’. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing ‘1’s to these locations has no effect on device operation. Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location F80000h. A detailed explanation of the various bit functions is provided in Register 25-1 through Register 25-6. Note: Note that address F80000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh) which can only be accessed using table reads and table writes. TABLE 25-1: CONSIDERATIONS FOR CONFIGURING PIC24FJ64GA104 FAMILY DEVICES Performing a page erase operation on the last page of program memory clears the Flash Configuration Words, enabling code protection as a result. Therefore, users should avoid performing page erase operations on the last page of program memory. FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ64GA104 FAMILY DEVICES Device Configuration Word Addresses 1 2 3 4 PIC24FJ32GA10x 57FEh 57FCh 57FAh 57F8h PIC24FJ64GA10x ABFEh ABFCh ABFAh ABF8h  2010 Microchip Technology Inc. DS39951C-page 239 PIC24FJ64GA104 FAMILY REGISTER 25-1: CW1: FLASH CONFIGURATION WORD 1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 r JTAGEN(1) GCP GWRP DEBUG — ICS1 ICS0 bit 15 bit 8 R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 FWDTEN WINDIS — FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set bit 23-16 Unimplemented: Read as ‘1’ bit 15 Reserved: The value is unknown; program as ‘0’ bit 14 JTAGEN: JTAG Port Enable bit(1) 1 = JTAG port is enabled 0 = JTAG port is disabled bit 13 GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space bit 12 GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are disabled bit 11 DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode bit 10 Unimplemented: Read as ‘1’ bit 9-8 ICS: Emulator Pin Placement Select bits 11 = Emulator functions are shared with PGEC1/PGED1 10 = Emulator functions are shared with PGEC2/PGED2 01 = Emulator functions are shared with PGEC3/PGED3 00 = Reserved; do not use bit 7 FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled 0 = Watchdog Timer is disabled bit 6 WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer is enabled 0 = Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’ bit 5 Unimplemented: Read as ‘1’ bit 4 FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 Note 1: ‘0’ = Bit is cleared The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be modified while connected through the JTAG interface. DS39951C-page 240  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 25-1: bit 3-0 Note 1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) WDTPS: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be modified while connected through the JTAG interface.  2010 Microchip Technology Inc. DS39951C-page 241 PIC24FJ64GA104 FAMILY REGISTER 25-2: CW2: FLASH CONFIGURATION WORD 2 U-1 — bit 23 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — R/PO-1 IESO bit 15 U-1 — U-1 — U-1 — U-1 — R/PO-1 FNOSC2 R/PO-1 FNOSC1 R/PO-1 FNOSC0 bit 8 R/PO-1 FCKSM1 bit 7 R/PO-1 FCKSM0 R/PO-1 OSCIOFCN R/PO-1 IOL1WAY U-1 — R/PO-1 I2C1SEL R/PO-1 POSCMD1 R/PO-1 POSCMD0 bit 0 Legend: R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed bit 23-16 bit 15 bit 14-11 bit 10-8 bit 7-6 bit 5 bit 4 bit 3 bit 2 bit 1-0 U-1 — bit 16 U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Unimplemented: Read as ‘1’ IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) is enabled 0 = IESO mode (Two-Speed Start-up) is disabled Unimplemented: Read as ‘1’ FNOSC: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) FCKSM: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSCIOFCN: OSCO Pin Configuration bit If POSCMD = 11 or 00: 1 = OSCO/CLKO/RA3 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RA3 functions as port I/O (RC15) If POSCMD = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RA3. IOL1WAY: IOLOCK One-Way Set Enable bit 1 = The IOLOCK bit (OSCCON) can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been completed Unimplemented: Read as ‘1’ I2C1SEL: I2C1 Pin Select bit 1 = Use default SCL1/SDA1 pins 0 = Use alternate SCL1/SDA1 pins POSCMD: Primary Oscillator Configuration bits 11 = Primary Oscillator is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = EC Oscillator mode is selected DS39951C-page 242  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 25-3: U-1 — bit 23 R/PO-1 WPEND bit 15 U-1 — CW3: FLASH CONFIGURATION WORD 3 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — bit 16 R/PO-1 WPCFG R/PO-1 WPDIS U-1 — R/PO-1 WUTSEL1 R/PO-1 WUTSEL0 R/PO-1 SOSCSEL1(1) U-1 — R/PO-1 WPFP5 R/PO-1 WPFP4 R/PO-1 WPFP3 R/PO-1 WPFP2 R/PO-1 WPFP1 R/PO-1 SOSCSEL0(1) bit 8 R/PO-1 WPFP0 bit 0 bit 7 Legend: R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed bit 23-16 bit 15 bit 14 bit 13 bit 12 bit 11-10 bit 9-8 bit 7-6 bit 5-0 Note 1: U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Unimplemented: Read as ‘1’ WPEND: Segment Write Protection End Page Select bit 1 = Protected code segment lower boundary is at the bottom of program memory (000000h); upper boundary is the code page specified by WPFP 0 = Protected code segment upper boundary is at the last page of program memory; lower boundary is the code page specified by WPFP WPCFG: Configuration Word Code Page Protection Select bit 1 = Last page (at the top of program memory) and Flash Configuration Words are not protected 0 = Last page and Flash Configuration Words are code-protected WPDIS: Segment Write Protection Disable bit 1 = Segmented code protection is disabled 0 = Segmented code protection is enabled; protected segment defined by WPEND, WPCFG and WPFPx Configuration bits Unimplemented: Read as ‘1’ WUTSEL: Voltage Regulator Standby Mode Wake-up Time Select bits 11 = Default regulator start-up time used 01 = Fast regulator start-up time used x0 = Reserved; do not use SOSCSEL: Secondary Oscillator Power Mode Select bits(1) 11 = SOSC pins are in default (high drive strength) oscillator mode 01 = SOSC pins are in Low-Power (low drive strength) Oscillator mode 00 = SOSC pins have digital I/O functions (RA4, RB4); SCLKI can be used 10 = Reserved Unimplemented: Read as ‘1’ WPFP5:WPFP0: Protected Code Segment Boundary Page bits Designates the 512 instruction page that is the boundary of the protected code segment, starting with Page 9 at the bottom of program memory. If WPEND = 1: Last address of designated code page is the upper boundary of the segment. If WPEND = 0: First address of designated code page is the lower boundary of the segment. Digital functions on the SOSCI and SOSCO pins are only available when configured in Digital I/O mode (‘00’).  2010 Microchip Technology Inc. DS39951C-page 243 PIC24FJ64GA104 FAMILY REGISTER 25-4: CW4: FLASH CONFIGURATION WORD 4 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 DSWDTEN DSBOREN RTCOSC R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 DSWDTOSC DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 bit 7 bit 0 Legend: R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-8 Unimplemented: Read as ‘1’ bit 7 DSWDTEN: Deep Sleep Watchdog Timer Enable bit 1 = DSWDT is enabled 0 = DSWDT is disabled bit 6 DSBOREN: Deep Sleep BOR Enable bit 1 = BOR is enabled in Deep Sleep 0 = BOR is disabled in Deep Sleep (does not affect Sleep mode) bit 5 RTCOSC: RTCC Reference Clock Select bit 1 = RTCC uses SOSC as reference clock 0 = RTCC uses LPRC as reference clock bit 4 DSWDTOSC: DSWDT Reference Clock Select bit 1 = DSWDT uses LPRC as reference clock 0 = DSWDT uses SOSC as reference clock bit 3-0 DSWDTPS: DSWDT Postscale select bits The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms. 1111 = 1:2,147,483,648 (25.7 days) 1110 = 1:536,870,912 (6.4 days) 1101 = 1:134,217,728 (38.5 hours) 1100 = 1:33,554,432 (9.6 hours) 1011 = 1:8,388,608 (2.4 hours) 1010 = 1:2,097,152 (36 minutes) 1001 = 1:524,288 (9 minutes) 1000 = 1:131,072 (135 seconds) 0111 = 1:32,768 (34 seconds) 0110 = 1:8,192 (8.5 seconds) 0101 = 1:2,048 (2.1 seconds) 0100 = 1:512 (528 ms) 0011 = 1:128 (132 ms) 0010 = 1:32 (33 ms) 0001 = 1:8 (8.3 ms) 0000 = 1:2 (2.1 ms) DS39951C-page 244  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY REGISTER 25-5: U — bit 23 DEVID: DEVICE ID REGISTER U — U — U — U — U — U — R FAMID7 bit 15 R FAMID6 R FAMID5 R FAMID4 R FAMID3 R FAMID2 R FAMID1 R FAMID0 bit 8 R DEV7 bit 7 R DEV6 R DEV5 R DEV4 R DEV3 R DEV2 R DEV1 R DEV0 bit 0 Legend: R = Read-Only bit bit 23-16 bit 15-8 bit 7-0 U — bit 16 U = Unimplemented bit Unimplemented: Read as ‘1’ FAMID: Device Family Identifier bits 01000010 = PIC24FJ64GA104 family DEV: Individual Device Identifier bits 00000010 = PIC24FJ32GA102 00000110 = PIC24FJ64GA102 00001010 = PIC24FJ32GA104 00001110 = PIC24FJ64GA104 REGISTER 25-6: DEVREV: DEVICE REVISION REGISTER U — U — U — U — U — U — U — U — bit 16 U — U — U — U — U — U — U — U — bit 23 bit 15 bit 8 U — U — U — U — R REV3 R REV2 R REV1 bit 7 Legend: R = Read-only bit bit 23-4 bit 3-0 R REV0 bit 0 U = Unimplemented bit Unimplemented: Read as ‘0’ REV: Minor Revision Identifier bits Encodes revision number of the device (sequential number only; no major/minor fields).  2010 Microchip Technology Inc. DS39951C-page 245 PIC24FJ64GA104 FAMILY 25.2 On-Chip Voltage Regulator All PIC24FJ64GA104 family devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ64GA104 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the DISVREG pin. Tying VSS to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR capacitor (such as ceramic) must be connected to the VDDCORE/VCAP pin (Figure 25-1). This helps to maintain the stability of the regulator. The recommended value for the Filter Capacitor (CEFC) is provided in Section 28.1 “DC Characteristics”. FIGURE 25-1: Regulator Enabled (DISVREG tied to VSS): 3.3V PIC24FJ64GA104 VDD DISVREG VDDCORE/VCAP CEFC (10 F typ) VOLTAGE REGULATOR TRACKING MODE AND LOW-VOLTAGE DETECTION 2.5V(1) When the device enters Tracking mode, it is no longer possible to operate at full speed. To provide information about when the device enters Tracking mode, the on-chip regulator includes a simple, Low-Voltage Detect circuit. When VDD drops below full-speed operating voltage, the circuit sets the Low-Voltage Detect Interrupt Flag, LVDIF (IFS4). This can be used to generate an interrupt and put the application into a Low-Power Operational mode or trigger an orderly shutdown. Low-Voltage Detection is only available when the regulator is enabled. 3.3V(1) PIC24FJ64GA104 VDD DISVREG VDDCORE/VCAP VSS Regulator Disabled (VDD tied to VDDCORE): 2.5V(1) PIC24FJ64GA104 VDD When it is enabled, the on-chip regulator provides a constant voltage of 2.5V nominal to the digital core logic. The regulator can provide this level from a VDD of about 2.5V, all the way up to the device’s VDDMAX. It does not have the capability to boost VDD levels below 2.5V. In order to prevent “brown-out” conditions when the voltage drops too low for the regulator, the regulator enters Tracking mode. In Tracking mode, the regulator output follows VDD with a typical voltage drop of 100 mV. VSS Regulator Disabled (DISVREG tied to VDD): If DISVREG is tied to VDD, the regulator is disabled. In this case, separate power for the core logic, at a nominal 2.5V, must be supplied to the device on the VDDCORE/VCAP pin to run the I/O pins at higher voltage levels, typically 3.3V. Alternatively, the VDDCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 25-1 for possible configurations. 25.2.1 CONNECTIONS FOR THE ON-CHIP REGULATOR DISVREG VDDCORE/VCAP VSS Note 1: 25.2.2 These are typical operating voltages. Refer to Section 28.1 “DC Characteristics” for the full operating ranges of VDD and VDDCORE. ON-CHIP REGULATOR AND POR When the voltage regulator is enabled, it takes approximately 10 s for it to generate output. During this time, designated as TPM, code execution is disabled. TPM is applied every time the device resumes operation after any power-down, including Sleep mode. TPM is determined by the setting of the PMSLP bit (RCON) and the WUTSEL Configuration bits (CW3). Note: For more information on TPM, see Section 28.0 “Electrical Characteristics”. If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of 64 ms nominal delay at device start-up (POR or BOR only). DS39951C-page 246  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY When waking up from Sleep with the regulator disabled, TPM is used to determine the wake-up time. To decrease the device wake-up time when operating with the regulator disabled, the PMSLP bit can be set. 25.3 25.2.3 The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 31 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. ON-CHIP REGULATOR AND BOR When the on-chip regulator is enabled, PIC24FJ64GA104 family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain the tracking level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON). The brown-out voltage specifications are provided in Section 28.0 “Electrical Characteristics”. 25.2.4 POWER-UP REQUIREMENTS The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts. Note: 25.2.5 For more information, see Section 28.0 “Electrical Characteristics”. VOLTAGE REGULATOR STANDBY MODE When enabled, the on-chip regulator always consumes a small incremental amount of current over IDD/IPD, including when the device is in Sleep mode, even though the core digital logic does not require power. To provide additional savings in applications where power resources are critical, the regulator automatically places itself into Standby mode whenever the device goes into Sleep mode by removing power from the Flash program memory. This feature is controlled by the PMSLP bit (RCON). By default, this bit is cleared, which enables Standby mode. For PIC24FJ64GA104 family devices, the time required for regulator wake-up from Standby mode is controlled by the WUTSEL Configuration bits (CW3). The default wake-up time for all devices is 190 s, which is a Legacy mode provided to match older PIC24F device wake-up times. Implementing the WUTSEL Configuration bits provides a fast wake-up option. When WUTSEL = 01, the regulator wake-up time is TPM, 10 s. Watchdog Timer (WDT) For PIC24FJ64GA104 family devices, the WDT is driven by the LPRC Oscillator. When the WDT is enabled, the clock source is also enabled. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPS Configuration bits (CW1), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler time-out periods, ranges from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) • When the device exits Sleep or Idle mode to resume normal operation • By a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON) will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. When the regulator’s Standby mode is turned off (PMSLP = 1), Flash program memory stays powered in Sleep mode. That enables device wake-up without waiting for TPM. With PMSLP set, however, the power consumption, while in Sleep mode, will be approximately 40 A higher than what it would be if the regulator was allowed to enter Standby mode.  2010 Microchip Technology Inc. DS39951C-page 247 PIC24FJ64GA104 FAMILY 25.3.1 WINDOWED OPERATION 25.3.2 The Watchdog Timer has an optional Fixed Window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction is executed before that window causes a WDT Reset; this is similar to a WDT time-out. Windowed WDT mode is enabled by programming the WINDIS Configuration bit (CW1) to ‘0’. FIGURE 25-2: CONTROL REGISTER The WDT is enabled or disabled by the FWDTEN Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the SWDTEN control bit (RCON). The SWDTEN control bit is cleared on any device Reset. The WDT software option allows the user to enable the WDT for critical code segments, and disable the WDT during non-critical segments, for maximum power savings. WDT BLOCK DIAGRAM SWDTEN FWDTEN LPRC Control FWPSA WDTPS Prescaler (5-bit/7-bit) LPRC Input 31 kHz Wake From Sleep WDT Counter Postscaler 1:1 to 1:32.768 1 ms/4 ms WDT Overflow Reset All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode 25.4 Deep Sleep Watchdog Timer (DSWDT) PIC24FJ64GA104 family devices have both a WDT module and a DSWDT module. The latter runs, if enabled, when a device is in Deep Sleep and is driven by either the SOSC or LPRC Oscillator. The clock source is selected by the DSWDTOSC (CW4) Configuration bit. The DSWDT can be configured to generate a time-out at 2.1 ms to 25.7 days by selecting the respective postscaler.The postscaler can be selected by the Configuration bits, DSWDTPS (CW4). When the DSWDT is enabled, the clock source is also enabled. DSWDT is one of the sources that can wake the device from Deep Sleep mode. 25.5 Program Verification and Code Protection PIC24FJ64GA104 family devices provide two complimentary methods to protect application code from overwrites and erasures. These also help to protect the device from inadvertent configuration changes during run time. 25.5.1 GENERAL SEGMENT PROTECTION For all devices in the PIC24FJ64GA104 family, the on-chip program memory space is treated as a single block, known as the General Segment (GS). Code protection for this block is controlled by one Configuration bit, GCP. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. Write protection is controlled by the GWRP bit in the Configuration Word. When GWRP is programmed to ‘0’, internal write and erase operations to program memory are blocked. DS39951C-page 248  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 25.5.2 CODE SEGMENT PROTECTION In addition to global General Segment protection, a separate subrange of the program memory space can be individually protected against writes and erases. This area can be used for many purposes where a separate block of erase and write-protected code is needed, such as bootloader applications. Unlike common boot block implementations, the specially protected segment in the PIC24FJ64GA104 family devices can be located by the user anywhere in the program space and configured in a wide range of sizes. Code segment protection provides an added level of protection to a designated area of program memory, by disabling the NVM safety interlock, whenever a write or erase address falls within a specified range. It does not override General Segment protection controlled by the GCP or GWRP bits. For example, if GCP and GWRP are enabled, enabling segmented code protection for the bottom half of program memory does not undo General Segment protection for the top half. The size and type of protection for the segmented code range are configured by the WPFPx, WPEND, WPCFG and WPDIS bits in Configuration Word 3. Code segment protection is enabled by programming the WPDIS bit (= 0). The WPFP bits specify the size of the segment to be protected by specifying the 512-word code page that is the start or end of the protected segment. The specified region is inclusive, therefore, this page will also be protected. A separate bit, WPCFG, is used to independently protect the last page of program space, including the Flash Configuration Words. Programming WPCFG (= 0) protects the last page, regardless of the other bit settings. This may be useful in circumstances where write protection is needed for both a code segment in the bottom of memory, as well as the Flash Configuration Words. The various options for segment code protection are shown in Table 25-2. 25.5.3 CONFIGURATION REGISTER PROTECTION The Configuration registers are protected against inadvertent or unwanted changes, or reads in two ways. The primary protection method is the same as that of the RP registers – shadow registers contain a complimentary value which is constantly compared with the actual value. To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity error and trigger a device Reset. The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the GCP bit is set, the source data for device configuration is also protected as a consequence. Even if General Segment protection is not enabled, the device configuration can be protected by using the appropriate code cement protection setting. The WPEND bit determines if the protected segment uses the top or bottom of the program space as a boundary. Programming WPEND (= 0) sets the bottom of program memory (000000h) as the lower boundary of the protected segment. Leaving WPEND unprogrammed (= 1) protects the specified page through the last page of implemented program memory, including the Configuration Word locations. TABLE 25-2: SEGMENT CODE PROTECTION CONFIGURATION OPTIONS Segment Configuration Bits Write/Erase Protection of Code Segment WPDIS WPEND WPCFG 1 x 1 No additional protection enabled; all program memory protection is configured by GCP and GWRP 1 x 0 Last code page protected, including Flash Configuration Words 0 1 0 Addresses from the first address of code page are defined by WPFP through the end of implemented program memory (inclusive) are protected, including Flash Configuration Words 0 0 0 Address, 000000h, through the last address of code page, defined by WPFP (inclusive) is protected 0 1 1 Addresses from first address of code page, defined by WPFP through the end of implemented program memory (inclusive), are protected, including Flash Configuration Words 0 0 1 Addresses from first address of code page, defined by WPFP through the end of implemented program memory (inclusive), are protected  2010 Microchip Technology Inc. DS39951C-page 249 PIC24FJ64GA104 FAMILY 25.6 JTAG Interface PIC24FJ64GA104 family devices implement a JTAG interface, which supports boundary scan device testing. 25.7 In-Circuit Serial Programming PIC24FJ64GA104 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGECx) and data (PGEDx), and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. DS39951C-page 250 25.8 In-Circuit Debugger When MPLAB® ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pins. To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS and the PGECx/PGEDx pin pair designated by the ICS Configuration bits. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins.  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 26.0 DEVELOPMENT SUPPORT The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers - MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 26.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2010 Microchip Technology Inc. DS39951C-page 251 PIC24FJ64GA104 FAMILY 26.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 26.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 26.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: 26.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 26.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS39951C-page 252  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 26.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 26.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.  2010 Microchip Technology Inc. 26.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 26.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. DS39951C-page 253 PIC24FJ64GA104 FAMILY 26.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 26.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured Windows® programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. 26.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39951C-page 254 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 27.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture, and is not intended to be a comprehensive reference source. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: • • • • Word or byte-oriented operations Bit-oriented operations Literal operations Control operations • A literal value to be loaded into a W register or file register (specified by the value of ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand, which is a register ‘Wb’ without any address modifier • The second source operand, which is a literal value • The destination of the result (only if not the same as the first source operand), which is typically a register ‘Wd’ with or without an address modifier The control instructions may use some of the following operands: • A program memory address • The mode of the table read and table write instructions Table 27-1 shows the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 27-2 lists all of the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand, which is typically a register ‘Wb’ without any address modifier • The second source operand, which is typically a register ‘Ws’ with or without an address modifier • The destination of the result, which is typically a register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: • The file register specified by the value, ‘f’ • The destination, which could either be the file register, ‘f’, or the W0 register, which is denoted as ‘WREG’ Most bit-oriented instructions (including rotate/shift instructions) have two operands: The literal instructions that involve data movement may use some of the following operands: simple All instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register, ‘Wb’)  2010 Microchip Technology Inc. DS39951C-page 255 PIC24FJ64GA104 FAMILY TABLE 27-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0000h...1FFFh} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16383} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388607}; LSB must be ‘0’ None Field does not require an entry, may be blank PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing) Wn One of 16 working registers {W0..W15} Wnd One of 16 destination working registers {W0..W15} Wns One of 16 source working registers {W0..W15} WREG W0 (working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } DS39951C-page 256  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z AND f f = f .AND. WREG 1 1 N, Z AND f,WREG WREG = f .AND. WREG 1 1 N, Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None BRA LE,Expr Branch if Less than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None BRA LT,Expr Branch if Less than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW.C Ws,Wb Write C bit to Ws 1 1 None BSW.Z Ws,Wb Write Z bit to Ws 1 1 None BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3)  2010 Microchip Technology Inc. DS39951C-page 257 PIC24FJ64GA104 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax Description # of Words # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.Z Ws,Wb Bit Test Ws to Z 1 1 BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None Clear Watchdog Timer 1 1 WDTO, Sleep CLRWDT CLRWDT COM COM f f=f 1 1 N, Z COM f,WREG WREG = f 1 1 N, Z COM Ws,Wd Wd = Ws 1 1 N, Z CP f Compare f with WREG 1 1 C, DC, N, OV, Z CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, Z CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,Ws Compare Wb with Ws, with Borrow (Wb – Ws – C) 1 1 C, DC, N, OV, Z CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 None (2 or 3) CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 None (2 or 3) CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 None (2 or 3) CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if  1 1 None (2 or 3) DAW DAW.B Wn Wn = Decimal Adjust Wn 1 1 DEC DEC f f=f–1 1 1 C, DC, N, OV, Z DEC f,WREG WREG = f – 1 1 1 C, DC, N, OV, Z CP C DEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, Z DEC2 f f=f–2 1 1 C, DC, N, OV, Z DEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, Z DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C DEC2 DS39951C-page 258  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic GOTO INC INC2 Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC2 Ws,Wd Wd = Ws + 2 1 1 IOR f f = f .IOR. WREG 1 1 N, Z IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z LNK LNK #lit14 Link Frame Pointer 1 1 None LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z MOV f,Wn Move f to Wn 1 1 None MOV [Wns+Slit10],Wnd Move [Wns + Slit10] to Wnd 1 1 None MOV f Move f to f 1 1 N, Z MOV f,WREG Move f to WREG 1 1 N, Z MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wns,[Wns+Slit10] Move Wns to [Wns + Slit10] 1 1 MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N, Z MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None NEG f f=f+1 1 1 C, DC, N, OV, Z NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z NEG Ws,Wd IOR MOV MUL NEG NOP POP Wd = Ws + 1 1 1 C, DC, N, OV, Z NOP No Operation 1 1 None NOPR No Operation 1 1 None POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd + 1) 1 2 None Pop Shadow Registers 1 1 All POP.S PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack (TOS) 1 2 None Push Shadow Registers 1 1 None PUSH.S  2010 Microchip Technology Inc. DS39951C-page 259 PIC24FJ64GA104 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 None RETFIE RETFIE Return from Interrupt 1 3 (2) None RETLW RETLW Return with Literal in Wn 1 3 (2) None RETURN RETURN Return from Subroutine 1 3 (2) None RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z C, N, Z RLNC RRC RRNC #lit10,Wn RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 RLNC f f = Rotate Left (No Carry) f 1 1 N, Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z N, Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 RRC f f = Rotate Right through Carry f 1 1 C, N, Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z RRNC f f = Rotate Right (No Carry) f 1 1 N, Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z SETM SETM f f = FFFFh 1 1 None SETM WREG WREG = FFFFh 1 1 None SETM Ws Ws = FFFFh 1 1 None SL f f = Left Shift f 1 1 C, N, OV, Z SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z SUB f f = f – WREG 1 1 C, DC, N, OV, Z SUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, Z SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, Z SL SUB SUBB SUBR SUBBR SWAP SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, Z SUBR f f = WREG – f 1 1 C, DC, N, OV, Z SUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, Z C, DC, N, OV, Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C, DC, N, OV, Z SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None DS39951C-page 260  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDH TBLRDH Ws,Wd Read Prog to Wd 1 2 TBLRDL TBLRDL Ws,Wd Read Prog to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws to Prog 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N ZE  2010 Microchip Technology Inc. None DS39951C-page 261 PIC24FJ64GA104 FAMILY NOTES: DS39951C-page 262  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 28.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ64GA104 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ64GA104 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +135°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin, and MCLR, with respect to VSS ........................ -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +3.0V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (Note 1)................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 1)....................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 28-1). NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2010 Microchip Technology Inc. DS39951C-page 263 PIC24FJ64GA104 FAMILY 28.1 DC Characteristics FIGURE 28-1: PIC24FJ64GA104 FAMILY VOLTAGE/FREQUENCY GRAPH (INDUSTRIAL) 3.00V Voltage (VDDCORE)(1) 2.75V 2.75V 2.50V PIC24FJ64GA104 Family 2.35V 2.35V 2.00V 16 MHz Frequency 32 MHz For frequencies between 16 MHz and 32 MHz, FMAX = (45.7 MHz/V) * (VDDCORE – 2V) + 16 MHz. When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCOREVDD3.6V. Note 1: FIGURE 28-2: PIC24FJ64GA104 FAMILY VOLTAGE/FREQUENCY GRAPH (EXTENDED TEMPERATURE) 3.00V Voltage (VDDCORE)(1) 2.75V 2.50V 2.75V PIC24FJ64GA104 Family 2.35V 2.25V 2.00V 16 MHz 24 MHz Frequency For frequencies between 16 MHz and 24 MHz, FMAX = (22.9 MHz/V) * (VDDCORE – 2V) + 16 MHz. Note 1: DS39951C-page 264 When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCOREVDD3.6V.  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 28-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C PIC24FJ64GA104 Family: Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W PDMAX (TJ – TA)/JA W I/O Pin Power Dissipation: PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation TABLE 28-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Package Thermal Resistance, 300 mil SOIC Symbol Typ Max Unit Notes JA 49 — °C/W (Note 1) Package Thermal Resistance, 6x6x0.9 mm QFN JA 33.7 — °C/W (Note 1) Package Thermal Resistance, 8x8x1 mm QFN JA 28 — °C/W (Note 1) Package Thermal Resistance, 10x10x1 mm TQFP JA 39.3 — °C/W (Note 1) Note 1: Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations.  2010 Microchip Technology Inc. DS39951C-page 265 PIC24FJ64GA104 FAMILY TABLE 28-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min Typ(1) Max Units VDD 2.2 — 3.6 V Regulator enabled VDD VDDCORE — 3.6 V Regulator disabled 2.0 — 2.75 V Regulator disabled Characteristic Conditions Operating Voltage DC10 Supply Voltage VDDCORE DC12 VDR RAM Data Retention Voltage(2) 1.5 — — V DC16 VPOR VDD Start Voltage to Ensure Internal Power-on Reset Signal VSS — — V DC17 SVDD VDD Rise Rate to Ensure Internal Power-on Reset Signal 0.05 — — V/ms DC18 VBOR Brown-out Reset Voltage — 2.05 — V Note 1: 2: 0-3.3V in 0.1s 0-2.5V in 60 ms Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. DS39951C-page 266  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 28-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) DC21 0.24 0.395 mA -40°C DC21a 0.25 0.395 mA +25°C DC21b 0.25 0.395 mA +85°C DC21f 0.3 0.395 mA +125°C DC21c 0.44 0.78 mA -40°C DC21d 0.41 0.78 mA +25°C DC21e 0.41 0.78 mA +85°C DC21g 0.6 0.78 mA +125°C DC20 0.5 0.75 mA -40°C DC20a 0.5 0.75 mA +25°C DC20b 0.5 0.75 mA +85°C DC20c 0.6 0.75 mA +125°C DC20d 0.75 1.4 mA -40°C DC20e 0.75 1.4 mA +25°C DC20f 0.75 1.4 mA +85°C DC20g 1.0 1.4 mA +125°C DC23 2.0 3.0 mA -40°C DC23a 2.0 3.0 mA +25°C DC23b 2.0 3.0 mA +85°C DC23c 2.4 3.0 mA +125°C DC23d 2.9 4.2 mA -40°C DC23e 2.9 4.2 mA +25°C DC23f 2.9 4.2 mA +85°C 3.5 4.2 mA +125°C DC23g Note 1: 2: 3: 4: 2.0V(3) 0.5 MIPS 3.3V(4) 2.0V(3) 1 MIPS 3.3V(4) 2.0V(3) 4 MIPS 3.3V(4) Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator is disabled (DISVREG is tied to VDD). On-chip voltage regulator is enabled (DISVREG is tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled.  2010 Microchip Technology Inc. DS39951C-page 267 PIC24FJ64GA104 FAMILY TABLE 28-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) DC24 10.5 15.5 mA -40°C DC24a 10.5 15.5 mA +25°C DC24b 10.5 15.5 mA +85°C DC24c 11.3 15.5 mA +125°C DC24d 11.3 15.5 mA -40°C DC24e 11.3 15.5 mA +25°C DC24f 11.3 15.5 mA +85°C DC24g 11.3 15.5 mA +125°C DC31 15.0 18.0 A -40°C DC31a 15.0 19.0 A +25°C DC31b 20.0 36.0 A +85°C DC31c 42.0 55.0 A +125°C DC31d 57.0 120.0 A -40°C DC31e 57.0 125.0 A +25°C DC31f 95.0 160.0 A +85°C 114.0 180.0 A +125°C DC31g Note 1: 2: 3: 4: 2.5V(3) 16 MIPS 3.3V(4) 2.0V(3) LPRC (31 kHz) 3.3V(4) Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator is disabled (DISVREG is tied to VDD). On-chip voltage regulator is enabled (DISVREG is tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. DS39951C-page 268  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 28-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) -40°C  TA  +125°C for Extended Max Units Conditions Idle Current (IIDLE)(2) DC41 67 100 A -40°C DC41a 68 100 A +25°C DC41b 74 100 A +85°C DC41f 102 120 A +125°C DC41c 166 265 A -40°C DC41d 167 265 A +25°C DC41e 177 265 A +85°C DC41g 225 285 A +125°C DC40 125 180 A -40°C DC40a 125 180 A +25°C DC40b 125 180 A +85°C DC40c 167 200 A +125°C DC40d 210 350 A -40°C DC40e 210 350 A +25°C DC40f 210 350 A +85°C DC40g 305 370 A +125°C DC43 0.5 0.6 mA -40°C DC43a 0.5 0.6 mA +25°C DC43b 0.5 0.6 mA +85°C DC43c 0.54 0.62 mA +125°C DC43d 0.75 0.95 mA -40°C DC43e 0.75 0.95 mA +25°C DC43f 0.75 0.95 mA +85°C DC43g 0.8 0.97 mA +125°C DC47 2.6 3.3 mA -40°C DC47a 2.6 3.3 mA +25°C DC47b 2.6 3.3 mA +85°C DC47f 2.7 3.4 mA +125°C DC47c 2.9 3.5 mA -40°C DC47d 2.9 3.5 mA +25°C DC47e 2.9 3.5 mA +85°C 3.0 3.6 mA +125°C DC47g Note 1: 2: 3: 4: 2.0V(3) 0.5 MIPS 3.3V(4) 2.0V(3) 1 MIPS 3.3V(4) 2.0V(3) 4 MIPS 3.3V(4) 2.5V(3) 16 MIPS 3.3V(4) Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IIDLE current is measured with the core off, OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator is disabled (DISVREG is tied to VDD). On-chip voltage regulator is enabled (DISVREG is tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled.  2010 Microchip Technology Inc. DS39951C-page 269 PIC24FJ64GA104 FAMILY TABLE 28-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) -40°C  TA  +125°C for Extended Max Units Conditions Idle Current (IIDLE)(2) DC50 0.8 1.0 mA -40°C DC50a 0.8 1.0 mA +25°C DC50b 0.8 1.0 mA +85°C DC50c 0.9 1.1 mA +125°C DC50d 1.1 1.3 mA -40°C DC50e 1.1 1.3 mA +25°C DC50f 1.1 1.3 mA +85°C DC50g 1.2 1.4 mA +125°C DC51 2.4 8.0 A -40°C DC51a 2.2 8.0 A +25°C DC51b 7.2 21 A +85°C DC51c 35 50 A +125°C DC51d 38 55 A -40°C DC51e 44 60 A +25°C DC51f 70 100 A +85°C DC51g 96 150 A +125°C Note 1: 2: 3: 4: 2.0V(3) FRC (4 MIPS) 3.3V(4) 2.0V(3) LPRC (31 kHz) 3.3V(4) Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IIDLE current is measured with the core off, OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator is disabled (DISVREG is tied to VDD). On-chip voltage regulator is enabled (DISVREG is tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. DS39951C-page 270  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 28-6: DC CHARACTERISTICS: POWER-DOWN BASE CURRENT (IPD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units 1.0 A Conditions Power-Down Current (IPD)(2) DC60 0.05 -40°C DC60a 0.2 1.0 A +25°C DC60i 2.0 6.5 A +60°C DC60b 3.5 12 A +85°C DC60m 29.9 50 A +125°C DC60c 0.1 1.0 A -40°C DC60d 0.4 1.0 A +25°C DC60j 2.5 15 A +60°C DC60e 4.2 25 A +85°C DC60n 36.2 75 A +125°C DC60f 3.3 9.0 A -40°C DC60g 3.3 10 A +25°C DC60k 5.0 20 A +60°C DC60h 7.0 30 A +85°C DC60p 39.2 80 A +125°C DC70c 0.003 0.2 A -40°C DC70d 0.02 0.2 A +25°C DC70j 0.2 0.35 A +60°C DC70e 0.51 1.5 A +85°C DC70a 6.1 12 A +125°C DC70f 0.01 0.3 A -40°C DC70g 0.04 0.3 A +25°C DC70k 0.2 0.5 A +60°C DC70h 0.71 2.0 A +85°C DC70b 7.2 16 A +125°C Note 1: 2: 3: 4: 5: 2.0V(3) 2.5V(3) Base Power-Down Current(5) 3.3V(4) 2.5V(4) Base Deep Sleep Current 3.3V(4) Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with the device in Sleep mode (all peripherals and clocks shut down). All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off, PMSLP bit is clear and the Peripheral Module Disable (PMD) bits for all unused peripherals are set. On-chip voltage regulator is disabled (DISVREG is tied to VDD). On-chip voltage regulator is enabled (DISVREG is tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.  2010 Microchip Technology Inc. DS39951C-page 271 PIC24FJ64GA104 FAMILY TABLE 28-7: DC CHARACTERISTICS: POWER-DOWN PERIPHERAL MODULE CURRENT (IPD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions  Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC61 0.2 0.7 A -40°C DC61a 0.2 0.7 A +25°C DC61i 0.2 0.7 A +60°C DC61b 0.23 0.7 A +85°C +125°C DC61m 0.3 1.0 A DC61c 0.25 0.9 A -40°C DC61d 0.25 0.9 A +25°C DC61j 0.25 0.9 A +60°C DC61e 0.28 0.9 A +85°C DC61p 0.5 1.2 A +125°C DC61f 0.6 1.5 A -40°C DC61g 0.6 1.5 A +25°C DC61k 0.6 1.5 A +60°C DC61h 0.8 1.5 A +85°C DC61n 1.0 1.7 A +125°C DC62 0.5 1.0 A -40°C DC62a 0.5 1.0 A +25°C DC62i 0.5 1.0 A +60°C DC62b 0.5 1.3 A +85°C DC62m 0.6 1.6 A +125°C DC62c 0.7 1.5 A -40°C DC62d 0.7 1.5 A +25°C DC62j 0.7 1.5 A +60°C DC62e 0.7 1.8 A +85°C DC62n 0.8 2.1 A +125°C DC62f 1.5 2.0 A -40°C DC62g 1.5 2.0 A +25°C DC62k 1.5 2.0 A +60°C DC62h 1.5 2.5 A +85°C 1.9 3.0 A +125°C DC62p Note 1: 2: 3: 4: 5: 2.0V(3) 2.5V(3) 31 kHz LPRC Oscillator with RTCC, WDT, DSWDT or Timer 1: ILPRC(5) 3.3V(4) 2.0V(3) 2.5V(3) Low drive strength, 32 kHz Crystal with RTCC, DSWDT or Timer1: ISOSC; SOSCSEL = 01 3.3V(4) Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Peripheral IPD deltas are measured with the device in Sleep mode (all peripherals and clocks shut down). All I/Os are configured as inputs and pulled high. Only the peripheral or clock being measured is enabled. PMSLP bit is clear and the Peripheral Module Disable bits (PMD) for all unused peripherals are set. On-chip voltage regulator is disabled (DISVREG is tied to VDD). On-chip voltage regulator is enabled (DISVREG is tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. DS39951C-page 272  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 28-7: DC CHARACTERISTICS: POWER-DOWN PERIPHERAL MODULE CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions  Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC63 1.8 2.3 A -40°C DC63a 1.8 2.7 A +25°C DC63i 1.8 3.0 A +60°C DC63b 1.8 3.0 A +85°C +125°C DC63m 2.2 3.3 A DC63c 2 2.7 A -40°C DC63d 2 2.9 A +25°C DC63j 2 3.2 A +60°C DC63e 2 3.5 A +85°C DC63n 2.5 3.8 A +125°C DC63f 2.25 3.0 A -40°C DC63g 2.25 3.0 A +25°C DC63k 2.25 3.3 A +60°C DC63h 2.25 3.5 A +85°C DC63p 2.8 4.0 A +125°C DC71c 0.001 0.25 A -40°C DC71d 0.03 0.25 A +25°C DC71j 0.05 0.60 A +60°C DC71e 0.08 2.0 A +85°C DC71a 3.9 10 A +125°C DC71f 0.001 0.50 A -40°C DC71g 0.03 0.50 A +25°C DC71k 0.05 0.75 A +60°C DC71h 0.08 2.5 A +85°C 3.9 12.5 A +125°C DC71b Note 1: 2: 3: 4: 5: 2.0V(3) 2.5V(3) 32 kHz Crystal with RTCC, DSWDT or Timer1: ISOSC; SOSCSEL = 11(5) 3.3V(4) 2.5V(4) Deep Sleep BOR: IDSBOR 3.3V(4) Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Peripheral IPD deltas are measured with the device in Sleep mode (all peripherals and clocks shut down). All I/Os are configured as inputs and pulled high. Only the peripheral or clock being measured is enabled. PMSLP bit is clear and the Peripheral Module Disable bits (PMD) for all unused peripherals are set. On-chip voltage regulator is disabled (DISVREG is tied to VDD). On-chip voltage regulator is enabled (DISVREG is tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.  2010 Microchip Technology Inc. DS39951C-page 273 PIC24FJ64GA104 FAMILY TABLE 28-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ(1) Max Units Input Low Voltage(4) DI10 I/O Pins with ST Buffer VSS — 0.2 VDD V DI11 I/O Pins with TTL Buffer VSS — 0.15 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSC1 (XT mode) VSS — 0.2 VDD V DI17 OSC1 (HS mode) VSS — 0.2 VDD V DI18 2 I/O Pins with I C™ Buffer: VSS — 0.3 VDD V DI19 I/O Pins with SMBus Buffer: VSS — 0.8 V I/O Pins with ST Buffer: with Analog Functions, Digital Only 0.8 VDD 0.8 VDD — — VDD 5.5 V V I/O Pins with TTL Buffer: with Analog Functions, Digital Only 0.25 VDD + 0.8 0.25 VDD + 0.8 — — VDD 5.5 V V VIH DI20 DI21 Conditions Input High SMBus enabled Voltage(4) DI25 MCLR 0.8 VDD — VDD V DI26 OSC1 (XT mode) 0.7 VDD — VDD V DI27 OSC1 (HS mode) 0.7 VDD — VDD V 0.7 VDD 0.7 VDD — — VDD 5.5 V V VDD 5.5 V V I2C DI28 I/O Pins with Buffer: with Analog Functions, Digital Only DI29 I/O Pins with SMBus Buffer: with Analog Functions, Digital Only DI30 ICNPU CNx Pull-up Current IIL 2.5V  VPIN  VDD 2.1 2.1 50 250 400 A VDD = 3.3V, VPIN = VSS Input Leakage Current(2,3) DI50 I/O Ports — — +50 nA VSS  VPIN  VDD, Pin at high-impedance DI51 Analog Input Pins — — +50 nA VSS  VPIN  VDD, Pin at high-impedance DI55 MCLR — — +50 nA VSS VPIN VDD DI56 OSC1 — — +50 nA VSS VPIN VDD, XT and HS modes Note 1: 2: 3: 4: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Refer to Table 1-2 for I/O pins buffer types. DS39951C-page 274  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 28-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param No. Sym VOL Characteristic I/O Ports DO16 I/O Ports VOH Note 1: Max Units — — 0.4 V IOL = 8.5 mA, VDD = 3.6V — — 0.4 V IOL = 5.0 mA, VDD = 2.0V — — 0.4 V IOL = 8.0 mA, VDD = 3.6V, 125°C — — 0.4 V IOL = 4.5 mA, VDD = 2.0V, 125°C 3.0 — — V IOH = -3.0 mA, VDD = 3.6V Conditions Output High Voltage I/O Ports I/O Ports DO26 Typ(1) Output Low Voltage DO10 DO20 Min 2.4 — — V IOH = -6.0 mA, VDD = 3.6V 1.65 — — V IOH = -1.0 mA, VDD = 2.0V 1.4 — — V IOH = -3.0 mA, VDD = 2.0V 3.0 — — V IOH = -2.5 mA, VDD = 3.6V, 125°C 1.65 — — V IOH = -0.5 mA, VDD = 2.0V, 125°C Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 28-10: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param No. Sym Characteristic D130 EP Cell Endurance D131 VPR VDD for Read Min Typ(1) Max Units 10,000 — — E/W VMIN — 3.6 V Conditions -40C to +85C VMIN = Minimum operating voltage VPEW Supply Voltage for Self-Timed Writes D132A VDDCORE 2.25 — 3.6 V D132B VDD 2.35 — 3.6 V D133A TIW Self-Timed Write Cycle Time — 3 — ms D133B TIE Self-Timed Page Erase Time 40 — — ms D134 TRETD Characteristic Retention 20 — — Year D135 IDDP — 7 — mA Note 1: Supply Current during Programming Provided no other specifications are violated Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.  2010 Microchip Technology Inc. DS39951C-page 275 PIC24FJ64GA104 FAMILY TABLE 28-11: COMPARATOR SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No. Symbol Characteristic Min Typ Max Units D300 VIOFF Input Offset Voltage* — 20 40 mV D301 VICM Input Common Mode Voltage* 0 — VDD V D302 CMRR Common Mode Rejection Ratio* 55 — — dB 300 TRESP Response Time*(1) — 150 400 ns 301 TMC2OV Comparator Mode Change to Output Valid* — — 10 s * Note 1: Comments Parameters are characterized but not tested. Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 28-12: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No. Symbol Characteristic Min Typ Max Units VDD/24 — VDD/32 LSb VRD310 CVRES Resolution VRD311 CVRAA Absolute Accuracy — — AVDD – 1.5 LSb VRD312 CVRUR Unit Resistor Value (R) — 2k —  Time(1) — — 10 s VR310 Note 1: TSET Settling Comments Settling time measured while CVRR = 1 and CVR bits transition from ‘0000’ to ‘1111’. TABLE 28-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Symbol No. Characteristics Min Typ Max Units VBG Band Gap Reference Voltage 1.14 1.2 1.26 V TBG Band Gap Reference Start-up Time — 1 — ms VRGOUT Regulator Output Voltage 2.35 2.5 2.75 V CEFC External Filter Capacitor Value 4.7 10 — F DS39951C-page 276 Comments Series resistance < 3 Ohm recommended; < 5 Ohm required.  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY 28.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ64GA104 family AC characteristics and timing parameters. TABLE 28-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial and -40°C  TA  +125°C for Extended Operating voltage VDD range as described in Section 28.1 “DC Characteristics”. AC CHARACTERISTICS FIGURE 28-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSCO Load Condition 2 – for OSCO VDD/2 CL Pin RL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSCO 15 pF for OSCO output VSS TABLE 28-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions 15 pF In XT and HS modes when external clock is used to drive OSCI. COSC2 OSCO/CLKO Pin — — DO56 CIO All I/O Pins and OSCO — — 50 pF EC mode. DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode. DO50 Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc. DS39951C-page 277 PIC24FJ64GA104 FAMILY FIGURE 28-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS40 OS41 TABLE 28-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.50 to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param Sym No. OS10 Characteristic FOSC External CLKI Frequency (External clocks allowed only in EC mode) Oscillator Frequency Min Typ(1) Max Units Conditions DC 4 DC 4 — — — — 32 8 24 6 MHz MHz MHz MHz EC, -40°C  TA  +85°C ECPLL, -40°C  TA  +85°C EC, -40°C  TA  +125°C ECPLL, -40°C  TA  +125°C 3 3 10 31 3 10 — — — — — — 10 8 32 33 6 24 MHz MHz MHz kHz MHz MHz XT XTPLL, -40°C  TA  +85°C HS, -40°C  TA  +85°C SOSC XTPLL, -40°C  TA  +125°C HS, -40°C  TA  +125°C — — — — 62.5 — DC ns OS20 TOSC TOSC = 1/FOSC OS25 TCY OS30 TosL, External Clock in (OSCI) TosH High or Low Time 0.45 x TOSC — — ns EC OS31 TosR, External Clock in (OSCI) TosF Rise or Fall Time — — 20 ns EC OS40 TckR — 6 10 ns — 6 10 ns OS41 TckF Note 1: 2: 3: Instruction Cycle Time(2) CLKO Rise Time(3) CLKO Fall Time(3) See parameter OS10 for FOSC value Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). DS39951C-page 278  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 28-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. OS50 Sym FPLLI Characteristic(1) PLL Input Frequency Range Typ(2) Max Units 3 — 8 MHz 3 — 6 MHz 8 8 — — 32 24 MHz MHz OS51 FSYS OS52 TLOCK PLL Start-up Time (Lock Time) — — 2 ms OS53 DCLK -2 1 2 % Note 1: 2: PLL Output Frequency Range Min CLKO Stability (Jitter) Conditions ECPLL, HSPLL, XTPLL modes, -40°C  TA  +85°C ECPLL, HSPLL, XTPLL modes, -40°C  TA  +125°C -40°C  TA  +85°C -40°C  TA  +125°C Measured over 100 ms period These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 28-18: INTERNAL RC OSCILLATOR SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. Sym TFRC Characteristic(1) FRC Start-up Time TLPRC LPRC Start-up Time Min Typ Max Units — 15 — s — 500 — s Conditions TABLE 28-19: INTERNAL RC OSCILLATOR ACCURACY Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. Characteristic F20 FRC Accuracy @ 8 MHz(1,3) F21 kHz(2) Note 1: 2: 3: LPRC Accuracy @ 31 Min Typ Max Units Conditions -1.25 +0.25 1.0 % -40°C  TA +85°C, 3.0V  VDD 3.6V -15 — 15 % -40°C  TA +85°C, 3.0V  VDD 3.6V Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift. Change of LPRC frequency as VDD changes. To achieve this accuracy, physical stress applied to the microcontroller package (ex: by flexing the PCB) must be kept to a minimum.  2010 Microchip Technology Inc. DS39951C-page 279 PIC24FJ64GA104 FAMILY FIGURE 28-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 28-3 for load conditions. TABLE 28-20: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. Sym Characteristic Typ(1) Min Max Units DO31 TIOR Port Output Rise Time — 10 25 ns DO32 TIOF Port Output Fall Time — 10 25 ns DI35 TINP INTx pin High or Low Time (output) 20 — — ns DI40 TRBP CNx High or Low Time (input) 2 — — TCY Note 1: Conditions Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. TABLE 28-21: RESET, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ(1) Max. Units SY10 TmcL MCLR Pulse Width (low) 2 — — s SY11 TPWRT Power-up Timer Period — 64 — ms Conditions SY12 TPOR Power-on Reset Delay — 2 — s SY13 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset — — 100 ns SY25 TBOR Brown-out Reset Pulse Width 1 — — s TRST Internal State Reset Time — 50 — s TDSWU Wake-up from Deep Sleep Time — 200 — s Based on full discharge of 10 F capacitor on VCAP. Includes TPOR and TRST. Sleep wake-up with PMSLP = 0 and WUTSEL = 11 TPM Note 1: — 10 — s — 190 — s VDD VBOR Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS39951C-page 280  2010 Microchip Technology Inc. PIC24FJ64GA104 FAMILY TABLE 28-22: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 2.0 — Lesser of VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V Reference Inputs AD05 VREFH Reference Voltage High AVSS + 1.7 — AVDD V AD06 VREFL Reference Voltage Low AVSS — AVDD – 1.7 V AD07 VREF Absolute Reference Voltage AVSS – 0.3 — AVDD + 0.3 V AD08 IVREF Reference Voltage Input Current — — 1.25 mA (Note 3) AD09 ZVREF Reference Input Impedance — 10K —  (Note 4) (Note 2) Analog Input AD10 VINH-VINL Full-Scale Input Span VREFL — VREFH V AD11 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V AD12 VINL Absolute VINL Input Voltage AVSS – 0.3 — AVDD/2 V Leakage Current — ±0.001 ±0.610 A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5 k Recommended Impedance of Analog Voltage Source — — 2.5K  10-bit AD13 — AD17 RIN ADC Accuracy AD20b NR Resolution — 10 — bits AD21b INL Integral Nonlinearity — ±1      ) 0 ./  2010 Microchip Technology Inc. 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